hal_gdc_regs.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file hal_gdc_regs.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of Graphics library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
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12
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35 ****************************************************************************************
36 */
37
38 /** @addtogroup GRAPHICS_SDK Graphics
39 * @{
40 */
41
42 /** @addtogroup HAL_DC HAL DC
43 * @{
44 */
45
46 /** @defgroup HAL_GDC_REG GDC REG
47 * @brief DC's registers definition
48 * @{
49 */
50
51 #ifndef HAL_GDC_REGS_H__
52 #define HAL_GDC_REGS_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /**
59 * @defgroup HAL_GDC_REG_MACRO_DEFINITION Defines
60 * @{
61 */
62 #define HAL_GDC_REG_MODE (0x00U) /**< This register specifies the general control. */
63 #define HAL_GDC_REG_CLKCTRL (0x04U) /**< This register specifies the clock division. */
64 #define HAL_GDC_REG_PLAY (0x10U) /**< This register sequence the trigger the DC. */
65 #define HAL_GDC_REG_CLKCTRL_CG (0x1a8U) /**< This register specifies the clock control of DC.. */
66 #define HAL_GDC_REG_BGCOLOR (0x08U) /**< This register specifies the main background color */
67 #define HAL_GDC_REG_RESXY (0x0cU) /**< This register specifies the main X and Y resolutions. */
68 #define HAL_GDC_REG_FRONTPORCHXY (0x14U) /**< This register specifies the X and Y front porch. */
69 #define HAL_GDC_REG_BLANKINGXY (0x18U) /**< This register specifies the X and Y blanking period. */
70 #define HAL_GDC_REG_BACKPORCHXY (0x1cU) /**< This register specifies the X and Y back porch. */
71 #define HAL_GDC_REG_CURSORXY (0x20U) /**< This register specifies the cursor's start X and Y coordinates */
72 #define HAL_GDC_REG_STARTXY (0x24U) /**< This register specifies the start position of the first frame. */
73 #define HAL_GDC_REG_DBIB_CFG (0x28U) /**< This register specifies the configuration of the interface. */
74 #define HAL_GDC_REG_GPIO (0x2cU) /**< This register specifies the general Purpose */
75
76 #define HAL_GDC_REG_LAYER0_MODE (0x30U) /**< This register specifies the mode of layer0. */
77 #define HAL_GDC_REG_LAYER0_STARTXY (0x34U) /**< This register specifies the start position of the layer0. */
78 #define HAL_GDC_REG_LAYER0_SIZEXY (0x38U) /**< This register specifies the size of the layer0. */
79 #define HAL_GDC_REG_LAYER0_BASEADDR (0x3cU) /**< This register specifies the start address of the framebuffer. */
80 #define HAL_GDC_REG_LAYER0_STRIDE (0x40U) /**< This register specifies the stride of the layer0. */
81 #define HAL_GDC_REG_LAYER0_RESXY (0x44U) /**< This register specifies the resolution of the layer0. */
82 #define HAL_GDC_REG_LAYER0_SCALEX (0x48U) /**< This register specifies the scale-x of the layer0. */
83 #define HAL_GDC_REG_LAYER0_SCALEY (0x4cU) /**< This register specifies the scale-y of the layer0. */
84
85 #define HAL_GDC_REG_LAYER1_MODE (0x50U) /**< This register specifies the mode of layer1. */
86 #define HAL_GDC_REG_LAYER1_STARTXY (0x54U) /**< This register specifies the start position of the layer1. */
87 #define HAL_GDC_REG_LAYER1_SIZEXY (0x58U) /**< This register specifies the size of the layer1. */
88 #define HAL_GDC_REG_LAYER1_BASEADDR (0x5cU) /**< This register specifies the start address of the framebuffer. */
89 #define HAL_GDC_REG_LAYER1_STRIDE (0x60U) /**< This register specifies the stride of the layer1. */
90 #define HAL_GDC_REG_LAYER1_RESXY (0x64U) /**< This register specifies the resolution of the layer1. */
91 #define HAL_GDC_REG_LAYER1_SCALEX (0x68U) /**< This register specifies the scale-x of the layer1. */
92 #define HAL_GDC_REG_LAYER1_SCALEY (0x6cU) /**< This register specifies the scale-y of the layer1. */
93
94 #define HAL_GDC_REG_LAYER2_MODE (0x70U) /**< This register specifies the mode of layer2. */
95 #define HAL_GDC_REG_LAYER2_STARTXY (0x74U) /**< This register specifies the start position of the layer2. */
96 #define HAL_GDC_REG_LAYER2_SIZEXY (0x78U) /**< This register specifies the size of the layer2. */
97 #define HAL_GDC_REG_LAYER2_BASEADDR (0x7cU) /**< This register specifies the start address of the framebuffer. */
98 #define HAL_GDC_REG_LAYER2_STRIDE (0x80U) /**< This register specifies the stride of the layer2. */
99 #define HAL_GDC_REG_LAYER2_RESXY (0x84U) /**< This register specifies the resolution of the layer2. */
100 #define HAL_GDC_REG_LAYER2_SCALEX (0x88U) /**< This register specifies the scale-x of the layer2. */
101 #define HAL_GDC_REG_LAYER2_SCALEY (0x8cU) /**< This register specifies the scale-y of the layer2. */
102
103 #define HAL_GDC_REG_LAYER3_MODE (0x90U) /**< This register specifies the mode of layer3. */
104 #define HAL_GDC_REG_LAYER3_STARTXY (0x94U) /**< This register specifies the start position of the layer3. */
105 #define HAL_GDC_REG_LAYER3_SIZEXY (0x98U) /**< This register specifies the size of the layer3. */
106 #define HAL_GDC_REG_LAYER3_BASEADDR (0x9cU) /**< This register specifies the start address of the framebuffer. */
107 #define HAL_GDC_REG_LAYER3_STRIDE (0xa0U) /**< This register specifies the stride of the layer3. */
108 #define HAL_GDC_REG_LAYER3_RESXY (0xa4U) /**< This register specifies the resolution of the layer3. */
109 #define HAL_GDC_REG_LAYER3_SCALEX (0xa8U) /**< This register specifies the scale-x of the layer3. */
110 #define HAL_GDC_REG_LAYER3_SCALEY (0xacU) /**< This register specifies the scale-y of the layer3. */
111
112 #define HAL_GDC_REG_LAYER0_UBASE (0xd0U) /**< This register specifies the start address of the U chroma for layer 0 YUV planar format */
113 #define HAL_GDC_REG_LAYER0_VBASE (0xd4U) /**< This register specifies the start address of the V chroma for layer 0 YUV planar format */
114 #define HAL_GDC_REG_LAYER0_UVSTRIDE (0xd8U) /**< This register specifies the start address of the V chroma for layer 0 YUV planar format */
115 #define HAL_GDC_REG_LAYER1_UBASE (0xdcU) /**< This register specifies the start address of the U chroma for layer 1 YUV planar format */
116 #define HAL_GDC_REG_LAYER1_VBASE (0xe0U) /**< This register specifies the start address of the V chroma for layer 1 YUV planar format */
117 #define HAL_GDC_REG_LAYER1_UVSTRIDE (0xe4U) /**< This register specifies the start address of the V chroma for layer 1 YUV planar format */
118 #define HAL_GDC_REG_LAYER2_UBASE (0x188U) /**< This register specifies the start address of the U chroma for layer 2 YUV planar format */
119 #define HAL_GDC_REG_LAYER2_VBASE (0x18cU) /**< This register specifies the start address of the V chroma for layer 2 YUV planar format */
120 #define HAL_GDC_REG_LAYER2_UVSTRIDE (0x190U) /**< This register specifies the start address of the V chroma for layer 2 YUV planar format */
121 #define HAL_GDC_REG_LAYER3_UBASE (0x194U) /**< This register specifies the start address of the U chroma for layer 3 YUV planar format */
122 #define HAL_GDC_REG_LAYER3_VBASE (0x198U) /**< This register specifies the start address of the V chroma for layer 3 YUV planar format */
123 #define HAL_GDC_REG_LAYER3_UVSTRIDE (0x19cU) /**< This register specifies the start address of the V chroma for layer 3 YUV planar format */
124
125 #define HAL_GDC_REG_DBIB_CMD (0xe8U) /**< This register specifies the CMD to SPI interface. */
126 #define HAL_GDC_REG_DBIB_RDAT (0xecU) /**< This register specifies the read data by SPI interface. */
127 #define HAL_GDC_REG_CONFIG (0xf0U) /**< This register specifies the configuration of DC. */
128 #define HAL_GDC_REG_IDREG (0xf4U) /**< This register specifies the ID of DC. */
129 #define HAL_GDC_REG_INTERRUPT (0xf8U) /**< This register specifies the interrupt of DC. */
130 #define HAL_GDC_REG_STATUS (0xfcU) /**< This register specifies the status of DC. */
131 #define HAL_GDC_REG_COLMOD (0x100U) /**< This register specifies the color mode of DC. */
132 #define HAL_GDC_REG_CRC (0x184U) /**< This register specifies the CRC check of DC. */
133
134 #define HAL_GDC_REG_FORMAT_CTRL (0x1a0U) /**< This register specifies the format control of DC. */
135 #define HAL_GDC_REG_FORMAT_CTRL2 (0x1a4U) /**< This register specifies the format control of DC. */
136 #define HAL_GDC_REG_FORMAT_CTRL3 (0x1acU) /**< This register specifies the format control of DC. */
137 #define HAL_GDC_REG_PALETTE (0x400U) /**< This register global palette/gamma correction memory region */
138 #define HAL_GDC_REG_CURSOR_IMAGE (0x800U) /**< This register specifies the cursor image. */
139 #define HAL_GDC_REG_CURSOR_LUT (0xA00U) /**< This register specifies the lut of cursor */
140 #define HAL_GDC_REG_GAMMALUT_0 (0x1000U) /**< This register specifies the gammalut of layer0. */
141 #define HAL_GDC_REG_GAMMALUT_1 (0x1400U) /**< This register specifies the gammalut of layer1. */
142 #define HAL_GDC_REG_GAMMALUT_2 (0x1800U) /**< This register specifies the gammalut of layer2. */
143 #define HAL_GDC_REG_GAMMALUT_3 (0x1c00U) /**< This register specifies the gammalut of layer3. */
144
145 #define HAL_GDC_REG_LAYER_MODE(i) (0x030 + 0x20*(i)) /**< This register specifies the mode of layeri. */
146 #define HAL_GDC_REG_LAYER_STARTXY(i) (0x034 + 0x20*(i)) /**< This register specifies the start position of the layeri. */
147 #define HAL_GDC_REG_LAYER_SIZEXY(i) (0x038 + 0x20*(i)) /**< This register specifies the size of the layeri. */
148 #define HAL_GDC_REG_LAYER_BASEADDR(i) (0x03c + 0x20*(i)) /**< This register specifies the start address of the framebuffer. */
149 #define HAL_GDC_REG_LAYER_STRIDE(i) (0x040 + 0x20*(i)) /**< This register specifies the stride of the layeri. */
150 #define HAL_GDC_REG_LAYER_RESXY(i) (0x044 + 0x20*(i)) /**< This register specifies the resolution of the layeri. */
151 #define HAL_GDC_REG_LAYER_SCALEX(i) (0x048 + 0x20*(i)) /**< This register specifies the scale-x of the layeri. */
152 #define HAL_GDC_REG_LAYER_SCALEY(i) (0x04c + 0x20*(i)) /**< This register specifies the scale-y of the layeri. */
153 #define HAL_GDC_REG_GAMMALUT(i) (0x1000+ 0x400*(i)) /**< This register specifies the gammaluti. */
154 /** @} */
155
156 #ifdef __cplusplus
157 }
158 #endif
159
160 #endif
161 /** @} */
162 /** @} */
163 /** @} */