gr55xx_hal_qspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_QSPI QSPI
47 * @brief QSPI HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_QSPI_H__
53 #define __GR55xx_HAL_QSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60
61 #include "gr55xx_ll_qspi.h"
62 #include "gr55xx_hal_def.h"
63
64 /* Exported types ------------------------------------------------------------*/
65 /** @addtogroup HAL_QSPI_ENUMERATIONS Enumerations
66 * @{
67 */
68
69 /** @defgroup HAL_QSPI_state HAL QSPI state
70 * @{
71 */
72
73 /**
74 * @brief HAL QSPI State Enumerations definition
75 */
76 typedef enum
77 {
78 HAL_QSPI_STATE_RESET = 0x00, /**< Peripheral not initialized */
79 HAL_QSPI_STATE_READY = 0x01, /**< Peripheral initialized and ready for use */
80 HAL_QSPI_STATE_BUSY = 0x02, /**< Peripheral in indirect mode and busy */
81 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /**< Peripheral in indirect mode with transmission ongoing */
82 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /**< Peripheral in indirect mode with reception ongoing */
83 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
84 HAL_QSPI_STATE_ABORT = 0x08, /**< Peripheral with abort request ongoing */
85 HAL_QSPI_STATE_ERROR = 0x04 /**< Peripheral in error */
86
87 } hal_qspi_state_t;
88
89 /**
90 *@brief HAL Status structures Of memorymapped definition
91 */
92 typedef enum
93 {
94 HAL_MMAPPED_STATE_DEACTIVED = 0x00U, /**< Deactived. */
95 HAL_MMAPPED_STATE_ACTIVED = 0x01U, /**< Actived. */
96 HAL_MMAPPED_STATE_ERROR = 0xFFU, /**< Actived. */
97 } hal_memorymapped_status_t;
98
99 /**
100 *@brief KEY index enum for memorymapped mode, use to modify any parameter quickly
101 */
102 typedef enum _qspi_memorymapped_idx_e {
103 QSPI_MMAPED_IDX_DFS_HARDCCODE_EN = 0x00, /**< paired value: QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE/QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE */
104 QSPI_MMAPED_IDX_DFS = 0x01, /**< paired value: @ref QSPI_CONCURRENT_XIP_DFS*/
105 QSPI_MMAPED_IDX_INST_EN = 0x02, /**< paired value: QSPI_CONCURRENT_XIP_INST_ENABLE/QSPI_CONCURRENT_XIP_INST_DISABLE */
106 QSPI_MMAPED_IDX_INST_SIZE = 0x03, /**< paired value: @ref QSPI_CONCURRENT_XIP_INSTSIZE */
107 QSPI_MMAPED_IDX_INST_VAL = 0x04, /**< paired value: instruction data */
108 QSPI_MMAPED_IDX_ADDR_SIZE = 0x05, /**< paired value: @ref QSPI_CONCURRENT_XIP_ADDRSIZE */
109 QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT = 0x06, /**< paired value: @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT */
110 QSPI_MMAPED_IDX_MODE_BITS_EN = 0x07, /**< paired value: QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE / QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE */
111 QSPI_MMAPED_IDX_MODE_BITS_SIZE = 0x08, /**< paired value: @ref QSPI_CONCURRENT_XIP_MBL */
112 QSPI_MMAPED_IDX_MODE_BITS_VAL = 0x09, /**< paired value: mode bits data */
113 QSPI_MMAPED_IDX_WAIT_CYCLES = 0x0A, /**< paired value: wait cycles, 0 ~ 31 */
114 QSPI_MMAPED_IDX_DATA_FRF = 0x0B, /**< paired value: @ref QSPI_CONCURRENT_XIP_FRF */
115 QSPI_MMAPED_IDX_PREFETCH_EN = 0x0C, /**< paired value: QSPI_CONCURRENT_XIP_PREFETCH_ENABLE / QSPI_CONCURRENT_XIP_PREFETCH_DISABLE */
116 QSPI_MMAPED_IDX_CONT_XFER_EN = 0x0D, /**< paired value: QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE / QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE*/
117 QSPI_MMAPED_IDX_CONT_XFER_TOC = 0x0E, /**< paired value: timeout count for the continuous transfer, 0 ~ 255 */
118 QSPI_MMAPED_IDX_EDIAN_MODE = 0x0F, /**< paired value: @ref QSPI_CONCURRENT_XIP_ENDIAN_MODE */
119 } qspi_memorymapped_idx_e;
120
121 /** @} */
122
123 /** @} */
124
125 /** @addtogroup HAL_QSPI_STRUCTURES Structures
126 * @{
127 */
128
129 /** @defgroup QSPI_Configuration QSPI Configuration
130 * @{
131 */
132
133 /**
134 * @brief QSPI init Structure definition.
135 */
136 typedef struct _qspi_init_t
137 {
138 uint32_t clock_prescaler; /**< Specifies the prescaler factor for generating clock based on the AHB clock.
139 This parameter can be a number between 0 and 0xFFFF. */
140
141 uint32_t clock_mode; /**< Specifies the Clock Mode. It indicates the level that clock takes between commands.
142 This parameter can be a value of @ref QSPI_Clock_Mode. */
143
144 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
145 This parameter can be a number between 0 and 0x7. */
146 } qspi_init_t;
147 /** @} */
148
149 /** @defgroup QSPI_handle QSPI handle
150 * @{
151 */
152
153 /**
154 * @brief QSPI handle Structure definition
155 */
156 typedef struct _qspi_handle
157 {
158 qspi_regs_t *p_instance; /**< QSPI registers base address. */
159
160 qspi_init_t init; /**< QSPI communication parameters. */
161
162 uint8_t *p_tx_buffer; /**< Pointer to QSPI Tx transfer Buffer. */
163
164 __IO uint32_t tx_xfer_size; /**< QSPI Tx Transfer size. */
165
166 __IO uint32_t tx_xfer_count; /**< QSPI Tx Transfer Counter */
167
168 uint8_t *p_rx_buffer; /**< Pointer to QSPI Rx transfer Buffer */
169
170 __IO uint32_t rx_xfer_size; /**< QSPI Rx Transfer size */
171
172 __IO uint32_t rx_xfer_count; /**< QSPI Rx Transfer Counter */
173
174 void (*write_fifo)(struct _qspi_handle *p_qspi); /**< Pointer to QSPI Tx transfer FIFO write function */
175
176 void (*read_fifo)(struct _qspi_handle *p_qspi); /**< Pointer to QSPI Rx transfer FIFO read function */
177
178 dma_handle_t *p_dma; /**< QSPI Rx/Tx DMA Handle parameters */
179
180 __IO hal_lock_t lock; /**< Locking object */
181
182 __IO hal_qspi_state_t state; /**< QSPI communication state */
183
184 __IO uint32_t error_code; /**< QSPI Error code */
185
186 uint32_t timeout; /**< Timeout for the QSPI memory access */
187
188 uint32_t retention[22]; /**< Save important register information. */
189 } qspi_handle_t;
190 /** @} */
191
192 /** @defgroup QSPI_Command QSPI command
193 * @{
194 */
195
196 /**
197 * @brief QSPI command Structure definition
198 */
199 typedef struct _qspi_command_t
200 {
201 uint32_t instruction; /**< Specifies the Instruction to be sent.
202 This parameter can be a value (8-bit) between 0x00 and 0xFF. */
203
204 uint32_t address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
205 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
206
207 uint32_t instruction_size; /**< Specifies the Instruction Size.
208 This parameter can be a value of @ref QSPI_Instruction_Size. */
209
210 uint32_t address_size; /**< Specifies the Address Size.
211 This parameter can be a value of @ref QSPI_Address_Size. */
212
213 uint32_t dummy_cycles; /**< Specifies the Number of Dummy Cycles.
214 This parameter can be a number between 0 and 31. */
215
216 uint32_t data_size; /**< Specifies the QSPI address width.
217 This parameter can be a value of @ref QSPI_Data_Size. */
218
219 uint32_t instruction_address_mode; /**< Specifies the Instruction and Address Mode.
220 This parameter can be a value of @ref QSPI_Inst_Addr_Mode. */
221
222 uint32_t data_mode; /**< Specifies the Data Mode (used for dummy cycles and data phases).
223 This parameter can be a value of @ref QSPI_Data_Mode. */
224
225 uint32_t length; /**< Specifies the number of data to transfer. (This is the number of bytes).
226 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
227 until end of memory).
228 when using in DMA LLP xfer, length means total length of all linkedlist block in bytes */
229
230 uint32_t clock_stretch_en; /**< Specifies whether to enable the clock stretch feature
231 This parameter can be LL_QSPI_CLK_STRETCH_ENABLE or LL_QSPI_CLK_STRETCH_DISABLE */
232 } qspi_command_t;
233 /** @} */
234
235 /** @defgroup QSPI_Memory_Map QSPI memory map
236 * @{
237 */
238 /**
239 * @brief QSPI memory map Structure definition
240 */
241 typedef struct _qspi_memorymapped_t
242 {
243
244 uint32_t x_sioo_mode; /**< Specifies instruction sent mode in memorymapped(xip) mode.
245 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_SENT_MODE. */
246
247 uint32_t x_instruction_en; /**< Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
248 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_PHASE. */
249
250 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
251 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INSTSIZE.*/
252
253 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
254
255
256 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
257 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ADDRSIZE. */
258
259 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
260 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT. */
261
262 uint32_t x_mode_bits_en; /**< Specifies whether to enable mode bits phase in memorymapped(xip) mode.
263 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_MODE_BITS_PHASE. */
264
265 uint32_t x_mode_bits_length; /**< Specifies mode bits length.
266 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_MBL. */
267
268 uint32_t x_mode_bits_data; /**< Specifies value of mode bits phase */
269
270
271 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
272 value range [0 ~ 31]. */
273
274 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
275 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_FRF. */
276
277 uint32_t x_prefetch_en; /**< Specifies whether to enable the prefetch feature.
278 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_PREFETCH. */
279
280 uint32_t x_continous_xfer_en; /**< Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
281 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_CONT_XFER. */
282
283 uint32_t x_continous_xfer_toc; /**< Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
284 unit in terms of hclk, range [0, 255]. */
285
286 uint32_t x_endian_mode; /**< Specifies endian mode in memorymapped(xip) mode.
287 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ENDIAN_MODE. */
288
289 } qspi_memorymapped_t;
290 /** @} */
291
292 /** @defgroup QSPI_Memory_Map_Write QSPI memory map write
293 * @{
294 */
295 /**
296 * @brief QSPI memory map write Structure definition
297 */
298 typedef struct _qspi_memorymapped_write_t
299 {
300
301 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
302 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INSTSIZE. */
303
304 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
305
306
307 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
308 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ADDRSIZE. */
309
310 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
311 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT. */
312
313 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
314 value range [0 ~ 31]. */
315
316 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
317 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_FRF. */
318 } qspi_memorymapped_write_t;
319 /** @} */
320
321 /** @defgroup QSPI_Memorymapped Parameter QSPI memorymapped parameter
322 * @{
323 */
324 /**
325 *@brief KEY:Value pair to set memorymapped parameter.
326 */
327 typedef struct _qspi_memorymapped_set_t {
328 qspi_memorymapped_idx_e mmap_key; /**< Memorymapped key. */
329 uint32_t mmap_val; /**< Memorymapped value. */
330 } qspi_memorymapped_set_t;
331 /** @} */
332
333 /** @defgroup QSPI_Psram_Write_Command QSPI psram-write command
334 * @{
335 */
336 /**
337 * @brief QSPI command for psram-write Structure definition.
338 */
339 typedef struct {
340
341 uint32_t data_size; /**< Specifies the QSPI data width.
342 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 : data_size support 8/16/32 bits;
343 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 : data_size support 8/16 bits.
344 This parameter can be a value of @ref QSPI_Data_Size. */
345
346 uint32_t data_block_length; /**< Specifies the number of data in each block, This is the number of bytes.
347 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 : the length equals each block's length(including the inst & addr length);
348 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 : the length equals the result of one inst&addr block plus one data block.
349 This parameter can be any value between 0 and 4095. */
350
351 uint32_t llp_data_mode; /**< Specifies Linked list data mode. @ref QSPI_PSRAM_DATA_IN_LLP_MODE. */
352
353 uint32_t llp_data_shape; /**< Specifies Linked list data shape.
354 Just support @ref QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_RECTANGLE now. */
355
356 } qspi_psram_command_t;
357 /** @} */
358
359 /** @} */
360
361
362 /** @addtogroup HAL_QSPI_CALLBACK_STRUCTURES Callback Structures
363 * @{
364 */
365
366 /** @defgroup HAL_QSPI_Callback Callback
367 * @{
368 */
369
370 /**
371 * @brief HAL_QSPI Callback function definition
372 */
373
374 typedef struct _hal_qspi_callback
375 {
376 void (*qspi_msp_init)(qspi_handle_t *p_qspi); /**< QSPI init MSP callback */
377 void (*qspi_msp_deinit)(qspi_handle_t *p_qspi); /**< QSPI de-init MSP callback */
378 void (*qspi_error_callback)(qspi_handle_t *p_qspi); /**< QSPI error callback */
379 void (*qspi_abort_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI abort complete callback */
380 void (*qspi_rx_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI rx transfer completed callback */
381 void (*qspi_tx_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI tx transfer completed callback */
382 } hal_qspi_callback_t;
383
384 /** @} */
385
386 /** @} */
387
388 /**
389 * @defgroup HAL_QSPI_MACRO Defines
390 * @{
391 */
392
393 /* Exported constants --------------------------------------------------------*/
394 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
395 * @{
396 */
397
398 /** @defgroup QSPI_DMA_CTRL_REGISTER_CFG Set DMA Control Register
399 * @{
400 */
401 /**@brief Set DMA Control Register.
402 *@param src_direction : DMA_SRC_INCREMENT, DMA_SRC_DECREMENT, DMA_SRC_NO_CHANGE
403 *@param src_tr_width : DMA_SDATAALIGN_BYTE, DMA_SDATAALIGN_HALFWORD, DMA_SDATAALIGN_WORD
404 *@param dst_tr_width : DMA_DDATAALIGN_BYTE, DMA_DDATAALIGN_HALFWORD, DMA_DDATAALIGN_WORD
405 *@param src_msize : DMA_CTLL_SRC_MSIZE_1/DMA_CTLL_SRC_MSIZE_4/DMA_CTLL_SRC_MSIZE_8/DMA_CTLL_SRC_MSIZE_16
406 *@param dst_msize : DMA_CTLL_DST_MSIZE_1/DMA_CTLL_DST_MSIZE_4/DMA_CTLL_DST_MSIZE_8/DMA_CTLL_DST_MSIZE_16
407 *@param en_gather : DMA_SRC_GATHER_ENABLE / DMA_SRC_GATHER_DISABLE
408 */
409 #define QSPI_DMA_CRTL_LOW_REGISTER_CFG(src_direction, src_tr_width, dst_tr_width, src_msize, dst_msize, en_gather) \
410 ( \
411 DMA_CTLL_INI_EN | DMA_MEMORY_TO_PERIPH | DMA_LLP_SRC_ENABLE | DMA_LLP_DST_DISABLE | \
412 en_gather | DMA_DST_SCATTER_DISABLE | DMA_DST_NO_CHANGE | \
413 src_direction | src_tr_width | dst_tr_width | src_msize | dst_msize \
414 )
415 /** @} */
416
417
418 /** @defgroup HAL_QSPI_FIFO_DEPTH Fifo Depth
419 * @{
420 */
421 #define QSPI_MAX_FIFO_DEPTH LL_QSPI_MAX_FIFO_DEPTH /**< Max FIFO Depth for QSPI Master. */
422 /** @} */
423
424 /** @defgroup QSPI_Error_Code QSPI Error Code
425 * @{
426 */
427 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /**< No error. */
428 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /**< Timeout error */
429 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /**< Transfer error */
430 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /**< DMA transfer error */
431 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /**< Invalid parameter error */
432 /** @} */
433
434 /** @defgroup QSPI_Clock_Mode QSPI Clock Mode
435 * @{
436 */
437
438 #define QSPI_CLOCK_MODE_0 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_1EDGE) /**< Inactive state of CLK is low; CLK toggles at the start of the first data bit */
439 #define QSPI_CLOCK_MODE_1 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_2EDGE) /**< Inactive state of CLK is low; CLK toggles in the middle of the first data bit */
440 #define QSPI_CLOCK_MODE_2 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_1EDGE) /**< Inactive state of CLK is high; CLK toggles at the start of the first data bit */
441 #define QSPI_CLOCK_MODE_3 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_2EDGE) /**< Inactive state of CLK is high; CLK toggles in the middle of the first data bit */
442
443 /** @} */
444
445 /** @defgroup QSPI_Data_Mode QSPI Data Mode
446 * @{
447 */
448
449 #define QSPI_DATA_MODE_SPI LL_QSPI_FRF_SPI /**< Standard SPI Frame Format */
450 #define QSPI_DATA_MODE_DUALSPI LL_QSPI_FRF_DUALSPI /**< Dual SPI Frame Format */
451 #define QSPI_DATA_MODE_QUADSPI LL_QSPI_FRF_QUADSPI /**< Quad SPI Frame Format */
452
453 /** @} */
454
455 /** @defgroup QSPI_Instruction_Size QSPI Instruction Size
456 * @{
457 */
458
459 #define QSPI_INSTSIZE_00_BITS LL_QSPI_INSTSIZE_0BIT /**< 0-bit (No Instruction) */
460 #define QSPI_INSTSIZE_04_BITS LL_QSPI_INSTSIZE_4BIT /**< 4-bit Instruction */
461 #define QSPI_INSTSIZE_08_BITS LL_QSPI_INSTSIZE_8BIT /**< 8-bit Instruction */
462 #define QSPI_INSTSIZE_16_BITS LL_QSPI_INSTSIZE_16BIT /**< 16-bit Instruction */
463
464 /** @} */
465
466 /** @defgroup QSPI_Address_Size QSPI Address Size
467 * @{
468 */
469
470 #define QSPI_ADDRSIZE_00_BITS LL_QSPI_ADDRSIZE_0BIT /**< 0-bit address */
471 #define QSPI_ADDRSIZE_04_BITS LL_QSPI_ADDRSIZE_4BIT /**< 4-bit address */
472 #define QSPI_ADDRSIZE_08_BITS LL_QSPI_ADDRSIZE_8BIT /**< 8-bit address */
473 #define QSPI_ADDRSIZE_12_BITS LL_QSPI_ADDRSIZE_12BIT /**< 12-bit address */
474 #define QSPI_ADDRSIZE_16_BITS LL_QSPI_ADDRSIZE_16BIT /**< 16-bit address */
475 #define QSPI_ADDRSIZE_20_BITS LL_QSPI_ADDRSIZE_20BIT /**< 20-bit address */
476 #define QSPI_ADDRSIZE_24_BITS LL_QSPI_ADDRSIZE_24BIT /**< 24-bit address */
477 #define QSPI_ADDRSIZE_28_BITS LL_QSPI_ADDRSIZE_28BIT /**< 28-bit address */
478 #define QSPI_ADDRSIZE_32_BITS LL_QSPI_ADDRSIZE_32BIT /**< 32-bit address */
479
480 /** @} */
481
482 /** @defgroup QSPI_Data_Size Data Width
483 * @{
484 */
485
486 #define QSPI_DATASIZE_04_BITS LL_QSPI_DATASIZE_4BIT /**< Data length for SPI transfer: 4 bits */
487 #define QSPI_DATASIZE_05_BITS LL_QSPI_DATASIZE_5BIT /**< Data length for SPI transfer: 5 bits */
488 #define QSPI_DATASIZE_06_BITS LL_QSPI_DATASIZE_6BIT /**< Data length for SPI transfer: 6 bits */
489 #define QSPI_DATASIZE_07_BITS LL_QSPI_DATASIZE_7BIT /**< Data length for SPI transfer: 7 bits */
490 #define QSPI_DATASIZE_08_BITS LL_QSPI_DATASIZE_8BIT /**< Data length for SPI transfer: 8 bits */
491 #define QSPI_DATASIZE_09_BITS LL_QSPI_DATASIZE_9BIT /**< Data length for SPI transfer: 9 bits */
492 #define QSPI_DATASIZE_10_BITS LL_QSPI_DATASIZE_10BIT /**< Data length for SPI transfer: 10 bits */
493 #define QSPI_DATASIZE_11_BITS LL_QSPI_DATASIZE_11BIT /**< Data length for SPI transfer: 11 bits */
494 #define QSPI_DATASIZE_12_BITS LL_QSPI_DATASIZE_12BIT /**< Data length for SPI transfer: 12 bits */
495 #define QSPI_DATASIZE_13_BITS LL_QSPI_DATASIZE_13BIT /**< Data length for SPI transfer: 13 bits */
496 #define QSPI_DATASIZE_14_BITS LL_QSPI_DATASIZE_14BIT /**< Data length for SPI transfer: 14 bits */
497 #define QSPI_DATASIZE_15_BITS LL_QSPI_DATASIZE_15BIT /**< Data length for SPI transfer: 15 bits */
498 #define QSPI_DATASIZE_16_BITS LL_QSPI_DATASIZE_16BIT /**< Data length for SPI transfer: 16 bits */
499 #define QSPI_DATASIZE_17_BITS LL_QSPI_DATASIZE_17BIT /**< Data length for SPI transfer: 17 bits */
500 #define QSPI_DATASIZE_18_BITS LL_QSPI_DATASIZE_18BIT /**< Data length for SPI transfer: 18 bits */
501 #define QSPI_DATASIZE_19_BITS LL_QSPI_DATASIZE_19BIT /**< Data length for SPI transfer: 19 bits */
502 #define QSPI_DATASIZE_20_BITS LL_QSPI_DATASIZE_20BIT /**< Data length for SPI transfer: 20 bits */
503 #define QSPI_DATASIZE_21_BITS LL_QSPI_DATASIZE_21BIT /**< Data length for SPI transfer: 21 bits */
504 #define QSPI_DATASIZE_22_BITS LL_QSPI_DATASIZE_22BIT /**< Data length for SPI transfer: 22 bits */
505 #define QSPI_DATASIZE_23_BITS LL_QSPI_DATASIZE_23BIT /**< Data length for SPI transfer: 23 bits */
506 #define QSPI_DATASIZE_24_BITS LL_QSPI_DATASIZE_24BIT /**< Data length for SPI transfer: 24 bits */
507 #define QSPI_DATASIZE_25_BITS LL_QSPI_DATASIZE_25BIT /**< Data length for SPI transfer: 25 bits */
508 #define QSPI_DATASIZE_26_BITS LL_QSPI_DATASIZE_26BIT /**< Data length for SPI transfer: 26 bits */
509 #define QSPI_DATASIZE_27_BITS LL_QSPI_DATASIZE_27BIT /**< Data length for SPI transfer: 27 bits */
510 #define QSPI_DATASIZE_28_BITS LL_QSPI_DATASIZE_28BIT /**< Data length for SPI transfer: 28 bits */
511 #define QSPI_DATASIZE_29_BITS LL_QSPI_DATASIZE_29BIT /**< Data length for SPI transfer: 29 bits */
512 #define QSPI_DATASIZE_30_BITS LL_QSPI_DATASIZE_30BIT /**< Data length for SPI transfer: 30 bits */
513 #define QSPI_DATASIZE_31_BITS LL_QSPI_DATASIZE_31BIT /**< Data length for SPI transfer: 31 bits */
514 #define QSPI_DATASIZE_32_BITS LL_QSPI_DATASIZE_32BIT /**< Data length for SPI transfer: 32 bits */
515
516
517 /** @} */
518
519
520 /** @defgroup QSPI_Inst_Addr_Mode QSPI Instruction and Address Mode
521 * @{
522 */
523
524 #define QSPI_INST_ADDR_ALL_IN_SPI LL_QSPI_INST_ADDR_ALL_IN_SPI /**< Instruction and address are sent in SPI mode */
525 #define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF /**< Instruction is sent in SPI mode, and address is sent in Daul/Quad SPI mode */
526 #define QSPI_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_INST_ADDR_ALL_IN_SPIFRF /**< Instruction and address are sent in Daul/Quad SPI mode */
527
528 /** @} */
529
530 /** @defgroup QSPI_Flags QSPI Flags
531 * @{
532 */
533
534 #define QSPI_FLAG_DCOL LL_QSPI_SR_DCOL /**< Data collision error flag */
535 #define QSPI_FLAG_TXE LL_QSPI_SR_TXE /**< Transmission error flag */
536 #define QSPI_FLAG_RFF LL_QSPI_SR_RFF /**< Rx FIFO full flag */
537 #define QSPI_FLAG_RFNE LL_QSPI_SR_RFNE /**< Rx FIFO not empty flag */
538 #define QSPI_FLAG_TFE LL_QSPI_SR_TFE /**< Tx FIFO empty flag */
539 #define QSPI_FLAG_TFNF LL_QSPI_SR_TFNF /**< Tx FIFO not full flag */
540 #define QSPI_FLAG_BUSY LL_QSPI_SR_BUSY /**< Busy flag */
541
542 /** @} */
543
544 /** @defgroup QSPI_Interrupts QSPI Interrupts
545 * @{
546 */
547
548 #define QSPI_IT_TXU LL_QSPI_IS_TXU /**< Transmit FIFO Underflow Interrupt flag */
549 #define QSPI_IT_XRXO LL_QSPI_IS_XRXO /**< XIP Receive FIFO Overflow Interrupt flag. */
550 #define QSPI_IT_MST LL_QSPI_IS_MST /**< Multi-Master Contention Interrupt flag. */
551 #define QSPI_IT_RXF LL_QSPI_IS_RXF /**< Receive FIFO Full Interrupt flag. */
552 #define QSPI_IT_RXO LL_QSPI_IS_RXO /**< Receive FIFO Overflow Interrupt flag. */
553 #define QSPI_IT_RXU LL_QSPI_IS_RXU /**< Receive FIFO Underflow Interrupt flag. */
554 #define QSPI_IT_TXO LL_QSPI_IS_TXO /**< Transmit FIFO Overflow Interrupt flag. */
555 #define QSPI_IT_TXE LL_QSPI_IS_TXE /**< Transmit FIFO Empty Interrupt flag. */
556 #define QSPI_IT_ALL LL_QSPI_IS_ALL /**< ALL QSPI Interrupts flag. */
557
558 /** @} */
559
560 /** @defgroup QSPI_Timeout_definition QSPI Timeout_definition
561 * @{
562 */
563 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000) /**< 5s. */
564 /** @} */
565
566 /** @defgroup QSPI_CONCURRENT_XIP_ENDIAN_MODE endian mode for qspi xip
567 * @{
568 */
569 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 /**< Default endian order from AHB. */
570 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 /**< Re-order the read data as [23:16], [31:24], [7:0], [15:8]. */
571 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 /**< Re-order the read data as [7:0], [15:8], [23:16], [31:24]. */
572 /** @} */
573
574 /** @defgroup QSPI_CONCURRENT_XIP_SLAVE Which Slave to Enable in XIP
575 * @{
576 */
577 #define QSPI_CONCURRENT_XIP_SLAVE0 LL_QSPI_CONCURRENT_XIP_SLAVE0 /**< Enable Slave0 in XIP. */
578 /** @} */
579
580 /** @defgroup QSPI_CONCURRENT_XIP_DFS data frame size in xip, take effect when enable DFS_HC
581 * @{
582 */
583 #define QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_CONCURRENT_XIP_DFS_BYTE /**< Set data frame size as byte. */
584 #define QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD /**< Set data frame size as halfword. */
585 #define QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_CONCURRENT_XIP_DFS_WORD /**< Set data frame size as word. */
586 /** @} */
587
588 /** @defgroup QSPI_CONCURRENT_XIP_MBL mode bits length for xip mode
589 * @{
590 */
591 #define QSPI_CONCURRENT_XIP_MBL_2 LL_QSPI_CONCURRENT_XIP_MBL_2 /**< mode bits length equals to 2 bit. */
592 #define QSPI_CONCURRENT_XIP_MBL_4 LL_QSPI_CONCURRENT_XIP_MBL_4 /**< mode bits length equals to 4 bit. */
593 #define QSPI_CONCURRENT_XIP_MBL_8 LL_QSPI_CONCURRENT_XIP_MBL_8 /**< mode bits length equals to 8 bit. */
594 #define QSPI_CONCURRENT_XIP_MBL_16 LL_QSPI_CONCURRENT_XIP_MBL_16 /**< mode bits length equals to 16 bit. */
595 /** @} */
596
597 /** @defgroup QSPI_CONCURRENT_XIP_INSTSIZE instruction size for concurrent xip mode
598 * @{
599 */
600 #define QSPI_CONCURRENT_XIP_INSTSIZE_0BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT /**< no instruction */
601 #define QSPI_CONCURRENT_XIP_INSTSIZE_4BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT /**< instruction size equals 4bits */
602 #define QSPI_CONCURRENT_XIP_INSTSIZE_8BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT /**< instruction size equals 8bits */
603 #define QSPI_CONCURRENT_XIP_INSTSIZE_16BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT /**< instruction size equals 16bits */
604 /** @} */
605
606 /** @defgroup QSPI_CONCURRENT_XIP_ADDRSIZE address size for concurrent xip mode
607 * @{
608 */
609 #define QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT /**< Address length for QSPI XIP transfer: 0 bits */
610 #define QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT /**< Address length for QSPI XIP transfer: 4 bits */
611 #define QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT /**< Address length for QSPI XIP transfer: 8 bits */
612 #define QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT /**< Address length for QSPI XIP transfer: 12 bits */
613 #define QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT /**< Address length for QSPI XIP transfer: 16 bits */
614 #define QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT /**< Address length for QSPI XIP transfer: 20 bits */
615 #define QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT /**< Address length for QSPI XIP transfer: 24 bits */
616 #define QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT /**< Address length for QSPI XIP transfer: 28 bits */
617 #define QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT /**< Address length for QSPI XIP transfer: 32 bits */
618 #define QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT /**< Address length for QSPI XIP transfer: 36 bits */
619 #define QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT /**< Address length for QSPI XIP transfer: 40 bits */
620 #define QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT /**< Address length for QSPI XIP transfer: 44 bits */
621 #define QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT /**< Address length for QSPI XIP transfer: 48 bits */
622 #define QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT /**< Address length for QSPI XIP transfer: 52 bits */
623 #define QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT /**< Address length for QSPI XIP transfer: 56 bits */
624 #define QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT /**< Address length for QSPI XIP transfer: 60 bits */
625 /** @} */
626
627 /** @defgroup QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT transfer of inst & address for concurrent xip mode
628 * @{
629 */
630 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI /**< Instruction and address are sent in SPI mode */
631 #define QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
632 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF /**< Instruction and address are sent in Daul/Quad SPI mode */
633 /** @} */
634
635 /** @defgroup QSPI_CONCURRENT_XIP_FRF frame format for concurrent xip mode
636 * @{
637 */
638 #define QSPI_CONCURRENT_XIP_FRF_RSVD LL_QSPI_CONCURRENT_XIP_FRF_RSVD /**< SPI Frame format : Reserved. */
639 #define QSPI_CONCURRENT_XIP_FRF_DUAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI /**< SPI Frame format : DUAL. */
640 #define QSPI_CONCURRENT_XIP_FRF_QUAD_SPI LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI /**< SPI Frame format : QUAD. */
641 #define QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI /**< SPI Frame format : OCTAL. */
642 /** @} */
643
644 /** @defgroup QSPI_XIP_CLK_STRETCH Mode Clock stretch mode
645 * @{
646 */
647 #define QSPI_CLK_STRETCH_ENABLE LL_QSPI_CLK_STRETCH_ENABLE /**< Enable Clock stretch. */
648 #define QSPI_CLK_STRETCH_DISABLE LL_QSPI_CLK_STRETCH_DISABLE /**< Disable Clock stretch. */
649 /** @} */
650
651 /** @defgroup QSPI_CONCURRENT_XIP_PREFETCH Prefetch for concurrent xip mode
652 * @{
653 */
654 #define QSPI_CONCURRENT_XIP_PREFETCH_ENABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE /**< Enable Prefetch. */
655 #define QSPI_CONCURRENT_XIP_PREFETCH_DISABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE /**< Disable Prefetch. */
656 /** @} */
657
658 /** @defgroup QSPI_CONCURRENT_XIP_CONT_XFER Cont transfer for concurrent xip mode
659 * @{
660 */
661 #define QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE /**< Enable Cont trasfer. */
662 #define QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE /**< Disable Cont trasfer. */
663 /** @} */
664
665 /** @defgroup QSPI_CONCURRENT_XIP_INST_PHASE Instruction phase for concurrent xip mode
666 * @{
667 */
668 #define QSPI_CONCURRENT_XIP_INST_ENABLE LL_QSPI_CONCURRENT_XIP_INST_ENABLE /**< Enable Instruction phase. */
669 #define QSPI_CONCURRENT_XIP_INST_DISABLE LL_QSPI_CONCURRENT_XIP_INST_DISABLE /**< Disable Instruction phase. */
670 /** @} */
671
672 /** @defgroup QSPI_CONCURRENT_XIP_MODE_BITS_PHASE Bits phase for concurrent xip mode
673 * @{
674 */
675 #define QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE /**< Enable Bits phase. */
676 #define QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE /**< Disable Bits phase. */
677 /** @} */
678
679 /** @defgroup QSPI_CONCURRENT_XIP_DFS_HARDCODE DFS hardcore for concurrent xip mode
680 * @{
681 */
682 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE /**< Enable DFS Hardcode. */
683 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE /**< Disable DFS Hardcode. */
684 /** @} */
685
686 /** @defgroup QSPI_CONCURRENT_XIP_INST_SENT_MODE Instruction sent mode for concurrent xip mode
687 * @{
688 */
689 #define QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS /*!< Send instruction for every transaction */
690 #define QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS /*!< Send instruction only for first transaction */
691 /** @} */
692
693
694 /** @defgroup QSPI_PSRAM_DATA_IN_LLP_MODE BLOCK Mode for LLP
695 * @{
696 */
697 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 0u /**< This is Loop Block Mode, inst & addr in the head of each block,
698 data are following insta & addr in the same block. */
699 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 1u /**< This is Crossed Block Mode, inst & addr in the first block,
700 data in the second block, then inst & addr block, then data block again,
701 and repeat till the end. */
702 /** @} */
703
704
705 /** @defgroup QSPI_PSRAM_DATA_BLOCK_SHAPE BLOCK SHAPE for DMA LLP
706 * @{
707 */
708 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_RECTANGLE 0u /**< Data length in every Block are the same */
709
710 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_NON_RECTANGLE 1u /**< Data length in every Block are the different */
711 /** @} */
712
713 /** @} */
714
715 /* Exported macro ------------------------------------------------------------*/
716 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
717 * @{
718 */
719
720 /** @brief Reset QSPI handle states.
721 * @param __HANDLE__ QSPI handle.
722 * @retval None
723 */
724 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_QSPI_STATE_RESET)
725
726 /** @brief Enable the specified QSPI peripheral.
727 * @param __HANDLE__ Specifies the QSPI Handle.
728 * @retval None
729 */
730
731 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
732
733 /** @brief Disable the specified QSPI peripheral.
734 * @param __HANDLE__ Specifies the QSPI Handle.
735 * @retval None
736 */
737
738 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
739
740 /** @brief Enable the QSPI DMA TX Request.
741 * @param __HANDLE__ Specifies the QSPI Handle.
742 * @retval None
743 */
744
745 #define __HAL_QSPI_ENABLE_DMATX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
746
747 /** @brief Enable the QSPI DMA RX Request.
748 * @param __HANDLE__ Specifies the QSPI Handle.
749 * @retval None
750 */
751 #define __HAL_QSPI_ENABLE_DMARX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
752
753
754 /** @brief Disable the QSPI DMA TX Request.
755 * @param __HANDLE__ Specifies the QSPI Handle.
756 * @retval None
757 */
758 #define __HAL_QSPI_DISABLE_DMATX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
759
760
761 /** @brief Disable the QSPI DMA RX Request.
762 * @param __HANDLE__ Specifies the QSPI Handle.
763 * @retval None
764 */
765 #define __HAL_QSPI_DISABLE_DMARX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
766
767
768 /** @brief Enable the specified QSPI interrupts.
769 * @param __HANDLE__ Specifies the QSPI Handle.
770 * @param __INTERRUPT__ Specifies the interrupt source to enable.
771 * This parameter can be one of the following values:
772 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
773 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
774 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
775 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
776 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
777 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
778 * @retval None
779 */
780 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
781
782
783 /** @brief Disable the specified QSPI interrupts.
784 * @param __HANDLE__ Specifies the QSPI handle.
785 * @param __INTERRUPT__ Specifies the interrupt source to disable.
786 * This parameter can be one of the following values:
787 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
788 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
789 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
790 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
791 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
792 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
793 * @retval None
794 */
795 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
796
797
798 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
799 * @param __HANDLE__ Specifies the QSPI Handle.
800 * @param __INTERRUPT__ Specifies the interrupt source to check.
801 * This parameter can be one of the following values:
802 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
803 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
804 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
805 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
806 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
807 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
808 * @retval The new state of __IT__ (TRUE or FALSE).
809 */
810 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BITS((__HANDLE__)->p_instance->INTSTAT, (__INTERRUPT__)) == (__INTERRUPT__))
811
812
813 /** @brief Check whether the specified QSPI flag is set or not.
814 * @param __HANDLE__ Specifies the QSPI Handle.
815 * @param __FLAG__ Specifies the flag to check.
816 * This parameter can be one of the following values:
817 * @arg @ref QSPI_FLAG_DCOL Data collision error flag
818 * @arg @ref QSPI_FLAG_TXE Transmission error flag
819 * @arg @ref QSPI_FLAG_RFF Rx FIFO full flag
820 * @arg @ref QSPI_FLAG_RFNE Rx FIFO not empty flag
821 * @arg @ref QSPI_FLAG_TFE Tx FIFO empty flag
822 * @arg @ref QSPI_FLAG_TFNF Tx FIFO not full flag
823 * @arg @ref QSPI_FLAG_BUSY Busy flag
824 * @retval The new state of __FLAG__ (TRUE or FALSE).
825 */
826 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__)) != 0) ? SET : RESET)
827
828
829 /** @brief Clear the specified QSPI flag.
830 * @param __HANDLE__ Specifies the QSPI Handle.
831 * @param __FLAG__ Specifies the flag to clear.
832 * This parameter can be one of the following values:
833 * @arg @ref QSPI_FLAG_DCOL Data collision error flag
834 * @arg @ref QSPI_FLAG_TXE Transmission error flag
835 * @arg @ref QSPI_FLAG_RFF Rx FIFO full flag
836 * @arg @ref QSPI_FLAG_RFNE Rx FIFO not empty flag
837 * @arg @ref QSPI_FLAG_TFE Tx FIFO empty flag
838 * @arg @ref QSPI_FLAG_TFNF Tx FIFO not full flag
839 * @arg @ref QSPI_FLAG_BUSY Busy flag
840 * @retval None
841 */
842 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__))
843
844 /** @} */
845
846 /* Private macros ------------------------------------------------------------*/
847 /** @defgroup QSPI_Private_Macro QSPI Private Macros
848 * @{
849 */
850
851 /** @brief Check if QSPI Clock Prescaler is valid.
852 * @param __PRESCALER__ QSPI Clock Prescaler.
853 * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
854 */
855 #define IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
856
857
858 /** @brief Check if QSPI FIFO Threshold is valid.
859 * @param __THR__ QSPI FIFO Threshold.
860 * @retval SET (__THR__ is valid) or RESET (__THR__ is invalid)
861 */
862 #define IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= (QSPI_MAX_FIFO_DEPTH - 1)))
863
864 /** @brief Check if QSPI Clock Mode is valid.
865 * @param __CLKMODE__ QSPI Clock Mode.
866 * @retval SET (__CLKMODE__ is valid) or RESET (__CLKMODE__ is invalid)
867 */
868 #define IS_QSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
869 ((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
870 ((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
871 ((__CLKMODE__) == QSPI_CLOCK_MODE_3))
872
873 /** @brief Check if QSPI RX Sample Delay Value is valid.
874 * @param __DLY__ QSPI RX Sample Delay value
875 * @retval SET (__DLY__ is valid) or RESET (__DLY__ is invalid)
876 */
877 #define IS_QSPI_RX_SAMPLE_DLY(__DLY__) (((__DLY__) >= 0) && ((__DLY__) <= 7))
878
879
880 /** @brief Check if QSPI Instruction Size is valid.
881 * @param __INST_SIZE__ QSPI Instruction Size.
882 * @retval SET (__INST_SIZE__ is valid) or RESET (__INST_SIZE__ is invalid)
883 */
884 #define IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
885 ((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
886 ((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
887 ((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))
888
889 /** @brief Check if QSPI Address Size is valid.
890 * @param __ADDR_SIZE__ QSPI Address Size .
891 * @retval SET (__ADDR_SIZE__ is valid) or RESET (__ADDR_SIZE__ is invalid)
892 */
893 #define IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
894 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
895 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
896 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
897 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
898 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
899 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
900 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
901 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))
902
903 /** @brief Check if QSPI Dummy Cycle is valid.
904 * @param __DCY__ QSPI Dummy Cycle.
905 * @retval SET (__DCY__ is valid) or RESET (__DCY__ is invalid)
906 */
907 #define IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
908
909 /** @brief Check if QSPI Instruction and Address Mode is valid.
910 * @param __MODE__ QSPI Instruction and Address Mode.
911 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
912 */
913 #define IS_QSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
914 ((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
915 ((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))
916
917 /** @brief Check if QSPI Data Mode is valid.
918 * @param __MODE__ QSPI Data Mode.
919 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
920 */
921 #define IS_QSPI_DATA_MODE(__MODE__) (((__MODE__) == QSPI_DATA_MODE_SPI) || \
922 ((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
923 ((__MODE__) == QSPI_DATA_MODE_QUADSPI))
924
925
926 /** @brief Check if QSPI Data Size is supported currently.
927 * @param __SIZE__ QSPI Data Size.
928 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
929 */
930 #define IS_QSPI_SUPPORTED_DATA_SIZE(__SIZE__) (((__SIZE__) == QSPI_DATASIZE_08_BITS) || \
931 ((__SIZE__) == QSPI_DATASIZE_16_BITS) || \
932 ((__SIZE__) == QSPI_DATASIZE_32_BITS))
933
934 /** @} */
935
936
937
938 /** @defgroup QSPI_XIP_Private_Macro QSPI-XIP Private Macros
939 * @{
940 */
941
942 /** @brief Check if QSPI.XIP SIOO Mode is valid.
943 * @param _SIOO_ QSPI.XIP Data Mode.
944 * @retval SET (_SIOO_ is valid) or RESET (_SIOO_ is invalid)
945 */
946 #define IS_QSPI_CONC_XIP_SIOO_MODE(_SIOO_) ( (QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS == (_SIOO_)) || \
947 (QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS == (_SIOO_)) )
948
949 /** @brief Check if QSPI.XIP DFS Value is valid.
950 * @param _DFS_ QSPI.XIP DFS Value
951 * @retval SET (_DFS_ is valid) or RESET (_DFS_ is invalid)
952 */
953 #define IS_QSPI_CONC_XIP_DFS(_DFS_) ( (QSPI_CONCURRENT_XIP_DFS_BYTE == (_DFS_)) || \
954 (QSPI_CONCURRENT_XIP_DFS_HALFWORD == (_DFS_)) || \
955 (QSPI_CONCURRENT_XIP_DFS_WORD == (_DFS_)) )
956
957 /** @brief Check if QSPI.XIP DFS_HC Switch Value is valid.
958 * @param _HC_EN_ QSPI.XIP DFS Hardcode Switch.
959 * @retval SET (_HC_EN_ is valid) or RESET (_HC_EN_ is invalid)
960 */
961 #define IS_QSPI_CONC_XIP_DFS_HC_EN(_HC_EN_) ( (QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE == (_HC_EN_)) || \
962 (QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE == (_HC_EN_)) )
963
964 /** @brief Check if QSPI.XIP inst Switch is valid.
965 * @param _INST_EN_ QSPI.XIP inst en/dis.
966 * @retval SET (_INST_EN_ is valid) or RESET (_INST_EN_ is invalid)
967 */
968 #define IS_QSPI_CONC_XIP_INST_EN(_INST_EN_) ( (QSPI_CONCURRENT_XIP_INST_ENABLE == (_INST_EN_)) || \
969 (QSPI_CONCURRENT_XIP_INST_DISABLE == (_INST_EN_)) )
970
971 /** @brief Check if QSPI.XIP inst size is valid.
972 * @param _INST_SIZE_ QSPI.XIP inst size.
973 * @retval SET (_INST_SIZE_ is valid) or RESET (_INST_SIZE_ is invalid)
974 */
975 #define IS_QSPI_CONC_XIP_INST_SIZE(_INST_SIZE_) ( (QSPI_CONCURRENT_XIP_INSTSIZE_0BIT == (_INST_SIZE_) ) || \
976 (QSPI_CONCURRENT_XIP_INSTSIZE_4BIT == (_INST_SIZE_) ) || \
977 (QSPI_CONCURRENT_XIP_INSTSIZE_8BIT == (_INST_SIZE_) ) || \
978 (QSPI_CONCURRENT_XIP_INSTSIZE_16BIT == (_INST_SIZE_) ) )
979
980 /** @brief Check if QSPI.XIP inst is valid.
981 * @param _INST_ QSPI.XIP inst.
982 * @retval SET (_INST_ is valid) or RESET (_INST_ is invalid)
983 */
984 #define IS_QSPI_CONC_XIP_INST(_INST_) ((_INST_) <= 0xFFFF )
985
986 /** @brief Check if QSPI.XIP Address Size is valid.
987 * @param _ADDR_SIZE_ QSPI.XIP Address Size.
988 * @retval SET (_ADDR_SIZE_ is valid) or RESET (_ADDR_SIZE_ is invalid)
989 */
990 #define IS_QSPI_CONC_XIP_ADDR_SIZE(_ADDR_SIZE_) ( (QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT == (_ADDR_SIZE_) ) || \
991 (QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT == (_ADDR_SIZE_) ) || \
992 (QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT == (_ADDR_SIZE_) ) || \
993 (QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT == (_ADDR_SIZE_) ) || \
994 (QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT == (_ADDR_SIZE_) ) || \
995 (QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT == (_ADDR_SIZE_) ) || \
996 (QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT == (_ADDR_SIZE_) ) || \
997 (QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT == (_ADDR_SIZE_) ) || \
998 (QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT == (_ADDR_SIZE_) ) || \
999 (QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT == (_ADDR_SIZE_) ) || \
1000 (QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT == (_ADDR_SIZE_) ) || \
1001 (QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT == (_ADDR_SIZE_) ) || \
1002 (QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT == (_ADDR_SIZE_) ) || \
1003 (QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT == (_ADDR_SIZE_) ) || \
1004 (QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT == (_ADDR_SIZE_) ) || \
1005 (QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT == (_ADDR_SIZE_) ) )
1006
1007 /** @brief Check if QSPI.XIP Addr Xfer format is valid.
1008 * @param _FORMAT_ QSPI.XIP Addr Xfer format.
1009 * @retval SET (_FORMAT_ is valid) or RESET (_FORMAT_ is invalid)
1010 */
1011 #define IS_QSPI_CONC_INST_ADDR_XFER_FORMAT(_FORMAT_) ( (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI == (_FORMAT_)) || \
1012 (QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF == (_FORMAT_)) || \
1013 (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF == (_FORMAT_)) )
1014
1015 /** @brief Check if QSPI.XIP Mode bits Switch is valid.
1016 * @param _MD_EN_ QSPI.XIP Mode bits Switch.
1017 * @retval SET (_MD_EN_ is valid) or RESET (_MD_EN_ is invalid)
1018 */
1019 #define IS_QSPI_CONC_XIP_MODE_BITS_EN(_MD_EN_) ( (QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE == (_MD_EN_) ) || \
1020 (QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE == (_MD_EN_) ))
1021
1022 /** @brief Check if QSPI.XIP Mode Bits size is valid.
1023 * @param _MD_SIZE_ QSPI.XIP Mode Bits size.
1024 * @retval SET (_MD_SIZE_ is valid) or RESET (_MD_SIZE_ is invalid)
1025 */
1026 #define IS_QSPI_CONC_XIP_MODE_BITS_SIZE(_MD_SIZE_) ( (QSPI_CONCURRENT_XIP_MBL_2 == (_MD_SIZE_)) || \
1027 (QSPI_CONCURRENT_XIP_MBL_4 == (_MD_SIZE_)) || \
1028 (QSPI_CONCURRENT_XIP_MBL_8 == (_MD_SIZE_)) || \
1029 (QSPI_CONCURRENT_XIP_MBL_16 == (_MD_SIZE_)) )
1030
1031 /** @brief Check if QSPI.XIP Mode Bits is valid.
1032 * @param _MD_BITS_ QSPI.XIP Mode Bits.
1033 * @retval SET (_MD_BITS_ is valid) or RESET (_MD_BITS_ is invalid)
1034 */
1035 #define IS_QSPI_CONC_XIP_MODE_BITS(_MD_BITS_) ( (_MD_BITS_) <= 0xFFFF)
1036
1037 /** @brief Check if QSPI.XIP dummy cycles is valid.
1038 * @param __DCY__ QSPI.XIPdummy cycles.
1039 * @retval SET (__DCY__ is valid) or RESET (__DCY__ is invalid)
1040 */
1041 #define IS_QSPI_CONC_XIP_DUMMY_CYCLES(__DCY__) ( (__DCY__) <= 31)
1042
1043 /** @brief Check if QSPI.XIP frame format is valid.
1044 * @param _XIP_FRF_ QSPI.XIP frame format.
1045 * @retval SET (_XIP_FRF_ is valid) or RESET (_XIP_FRF_ is invalid)
1046 */
1047 #define IS_QSPI_CONC_XIP_DATA_FRF(_XIP_FRF_) ( (QSPI_CONCURRENT_XIP_FRF_DUAL_SPI == (_XIP_FRF_)) || \
1048 (QSPI_CONCURRENT_XIP_FRF_QUAD_SPI == (_XIP_FRF_)) )
1049
1050 /** @brief Check if QSPI.XIP prefetch switch is valid.
1051 * @param _PREFETCH_EN_ QSPI.XIP prefetch switch.
1052 * @retval SET (_PREFETCH_EN_ is valid) or RESET (_PREFETCH_EN_ is invalid)
1053 */
1054 #define IS_QSPI_CONC_XIP_PREFETCH_EN(_PREFETCH_EN_) ( (QSPI_CONCURRENT_XIP_PREFETCH_ENABLE == (_PREFETCH_EN_)) || \
1055 (QSPI_CONCURRENT_XIP_PREFETCH_DISABLE == (_PREFETCH_EN_)) )
1056
1057 /** @brief Check if QSPI.XIP cont xfer switch is valid.
1058 * @param _CONT_XFER_EN_ QSPI.XIP cont xfer switch.
1059 * @retval SET (_CONT_XFER_EN_ is valid) or RESET (_CONT_XFER_EN_ is invalid)
1060 */
1061 #define IS_QSPI_CONC_XIP_CONT_XFER_EN(_CONT_XFER_EN_) ( (QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE == (_CONT_XFER_EN_)) || \
1062 (QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE == (_CONT_XFER_EN_)) )
1063
1064 /** @brief Check if QSPI.XIP timeout count of cont xfer is valid.
1065 * @param _TOC_ QSPI.XIP timeout count of cont xfer.
1066 * @retval SET (_TOC_ is valid) or RESET (_TOC_ is invalid)
1067 */
1068 #define IS_QSPI_CONC_XIP_CONT_XFER_TOC(_TOC_) ( (_TOC_) <= 0xFF)
1069
1070 /** @brief Check if QSPI.XIP Data endian Mode is valid.
1071 * @param _MODE_ QSPI.XIP Data endian Mode.
1072 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
1073 */
1074 #define IS_QSPI_CONC_XIP_ENDIAN_MODE(_MODE_) ( (QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 == (_MODE_)) || \
1075 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 == (_MODE_)) || \
1076 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 == (_MODE_)) )
1077 /** @} */
1078
1079 /** @} */
1080
1081 /* Exported functions --------------------------------------------------------*/
1082 /** @addtogroup HAL_QSPI_DRIVER_FUNCTIONS Functions
1083 * @{
1084 */
1085
1086 /** @defgroup QSPI_Exported_Functions_Group1 Initialization and de-initialization functions
1087 * @brief Initialization and de-initialization functions
1088 *
1089 @verbatim
1090 ===============================================================================
1091 ##### Initialization and de-initialization functions #####
1092 ===============================================================================
1093 [..] This subsection provides a set of functions allowing to initialize and
1094 de-initialize the QSPIx peripheral:
1095
1096 (+) User must implement hal_qspi_msp_init() function in which he configures
1097 all related peripherals resources (GPIO, DMA, IT and NVIC ).
1098
1099 (+) Call the function hal_qspi_init() to configure the selected device with
1100 the selected configuration:
1101 (++) Clock Prescaler
1102 (++) Clock Mode
1103
1104 (+) Call the function hal_qspi_deinit() to restore the default configuration
1105 of the selected QSPIx peripheral.
1106
1107 @endverbatim
1108 * @{
1109 */
1110
1111 /**
1112 ****************************************************************************************
1113 * @brief Initialize the QSPI according to the specified parameters
1114 * in the qspi_init_t and initialize the associated handle.
1115 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1116 * @retval ::HAL_OK: Operation is OK.
1117 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1118 * @retval ::HAL_BUSY: Driver is busy.
1119 * @retval ::HAL_TIMEOUT: Timeout occurred.
1120 ****************************************************************************************
1121 */
1122 hal_status_t hal_qspi_init(qspi_handle_t *p_qspi);
1123
1124 /**
1125 ****************************************************************************************
1126 * @brief De-initialize the QSPI peripheral.
1127 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1128 * @retval ::HAL_OK: Operation is OK.
1129 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1130 * @retval ::HAL_BUSY: Driver is busy.
1131 * @retval ::HAL_TIMEOUT: Timeout occurred.
1132 ****************************************************************************************
1133 */
1134 hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi);
1135
1136 /**
1137 ****************************************************************************************
1138 * @brief Initialize the QSPI MSP.
1139 * @note This function should not be modified. When the callback is needed,
1140 * the hal_qspi_msp_init can be implemented in the user file.
1141 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1142 ****************************************************************************************
1143 */
1144 void hal_qspi_msp_init(qspi_handle_t *p_qspi);
1145
1146 /**
1147 ****************************************************************************************
1148 * @brief De-initialize the QSPI MSP.
1149 * @note This function should not be modified. When the callback is needed,
1150 * the hal_qspi_msp_deinit can be implemented in the user file.
1151 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1152 ****************************************************************************************
1153 */
1154 void hal_qspi_msp_deinit(qspi_handle_t *p_qspi);
1155
1156 /** @} */
1157
1158 /** @defgroup QSPI_Exported_Functions_Group2 QSPI operation functions
1159 * @brief Data transfers functions
1160 *
1161 @verbatim
1162 ==============================================================================
1163 ##### QSPI operation functions #####
1164 ===============================================================================
1165 [..]
1166 This subsection provides a set of functions allowing to manage the QSPI
1167 data transfers.
1168
1169 [..] The QSPI supports master and slave mode:
1170
1171 (#) There are two modes of transfer:
1172 (++) Blocking mode: The communication is performed in polling mode.
1173 The HAL status of all data processing is returned by the same function
1174 after finishing transfer.
1175 (++) No-Blocking mode: The communication is performed using Interrupts.
1176 or DMA, These APIs return the HAL status.
1177 The end of the data processing will be indicated through the
1178 dedicated QSPI IRQ when using Interrupt mode or the DMA IRQ when
1179 using DMA mode.
1180 The hal_qspi_tx_cplt_callback(), hal_qspi_rx_cplt_callback() and hal_qspi_txrx_cplt_callback() user callbacks
1181 will be executed respectively at the end of the transmit or Receive process.
1182 The hal_qspi_error_callback() user callback will be executed when a communication error is detected
1183
1184 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
1185 exist for 1 Line (simplex) and 2 Lines (full duplex) modes.
1186
1187 @endverbatim
1188 * @{
1189 */
1190 /**
1191 ****************************************************************************************
1192 * @brief Configure the Memory Mapped mode. Called after hal_qspi_init(...)
1193 * @note This function is used only in Memory mapped Mode
1194 * @param[in] p_qspi: Pointer to a QSPI handle
1195 * @param[in] mmap_cmd: Structure that contains the memorymapped read command configuration information.
1196 * @param[in] mmap_wr_cmd: Structure that contains the memorymapped write command configuration information.
1197 * @retval hal status
1198 ****************************************************************************************
1199 */
1200 hal_status_t hal_qspi_memorymapped(qspi_handle_t *p_qspi, qspi_memorymapped_t * mmap_cmd, qspi_memorymapped_write_t * mmap_wr_cmd);
1201
1202 /**
1203 * @brief Active the memory mapped mode from Ready state. users must make sure parameters of mmaped mode hava been set correctly
1204 * @param p_qspi: QSPI handle
1205 * @param is_sioo_mode (TRUE/FALSE)- specifies SIOO Mode, must match to Slave device's inst
1206 * @note 1) This function is used only in Memory mapped Mode
1207 * 2) User must config the registers correcly firstly
1208 * 3) It requires that slave device's inst supports the SIOO Mode
1209 * @retval hal status
1210 */
1211 hal_status_t hal_qspi_memorymapped_active(qspi_handle_t *p_qspi, uint32_t is_sioo_mode);
1212
1213 /**
1214 * @brief Deactive the memory mapped mode to Ready state
1215 * it's recommended to use with hal_qspi_memorymapped_active to switch mode quickly
1216 * @param p_qspi: QSPI handle
1217 * @note This function is used only in Memory mapped Mode
1218 * @retval hal status
1219 */
1220 hal_status_t hal_qspi_memorymapped_deactive(qspi_handle_t *p_qspi);
1221
1222 /**
1223 * @brief Check whether the memory mapped mode is Actived
1224 * @param p_qspi: QSPI handle
1225 * @note This function is used only in Memory mapped Mode
1226 * @retval 1 - actived; 0 - not actived
1227 */
1228 hal_memorymapped_status_t hal_qspi_memorymapped_is_actived(qspi_handle_t *p_qspi);
1229
1230
1231 /**
1232 * @brief Used to update memorymapped any parameter quickly
1233 * @param p_qspi: QSPI handle
1234 * @param mmap_set: Pointer to k:v pair of qspi_memorymapped_set_t
1235 * @param count: Amount of mmap_set's element
1236 * @note This function is used only in Memory mapped Mode
1237 * @retval hal status
1238 */
1239 hal_status_t hal_qspi_memorymapped_update(qspi_handle_t *p_qspi, qspi_memorymapped_set_t * mmap_set, uint32_t count);
1240 /**
1241 ****************************************************************************************
1242 * @brief Transmit an amount of data with the specified instruction and address in blocking mode.
1243 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1244 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1245 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1246 * @param[in] p_data: Pointer to data buffer
1247 * @param[in] timeout: Timeout duration
1248 * @retval ::HAL_OK: Operation is OK.
1249 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1250 * @retval ::HAL_BUSY: Driver is busy.
1251 * @retval ::HAL_TIMEOUT: Timeout occurred.
1252 ****************************************************************************************
1253 */
1254 hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
1255
1256 /**
1257 ****************************************************************************************
1258 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
1259 * @note This function is used only in Indirect Read Mode.
1260 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1261 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1262 * @param[out] p_data: Pointer to data buffer
1263 * @param[in] timeout: Timeout duration
1264 * @retval ::HAL_OK: Operation is OK.
1265 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1266 * @retval ::HAL_BUSY: Driver is busy.
1267 * @retval ::HAL_TIMEOUT: Timeout occurred.
1268 ****************************************************************************************
1269 */
1270 hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
1271
1272 /**
1273 ****************************************************************************************
1274 * @brief Transmit only instruction in blocking mode.
1275 * @note This function is used only in Indirect Write Mode.
1276 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1277 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1278 * @param[in] timeout: Timeout duration
1279 * @retval ::HAL_OK: Operation is OK.
1280 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1281 * @retval ::HAL_BUSY: Driver is busy.
1282 * @retval ::HAL_TIMEOUT: Timeout occurred.
1283 ****************************************************************************************
1284 */
1285 hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout);
1286
1287 /**
1288 ****************************************************************************************
1289 * @brief Transmit an amount of data in blocking mode with standard SPI.
1290 * @note This function is used only in Indirect Write Mode.
1291 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1292 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1293 * QSPI_DATA_MODE_DUALSPI
1294 * QSPI_DATA_MODE_QUADSPI
1295 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1296 * QSPI_DATASIZE_16_BITS
1297 * QSPI_DATASIZE_32_BITS
1298 * @param[in] p_data: Pointer to data buffer
1299 * @param[in] data_length: Amount of data to be sent in bytes
1300 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1301 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1302 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1303 * @param[in] timeout: Timeout duration
1304 * @retval ::HAL_OK: Operation is OK.
1305 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1306 * @retval ::HAL_BUSY: Driver is busy.
1307 * @retval ::HAL_TIMEOUT: Timeout occurred.
1308 ****************************************************************************************
1309 */
1310 hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length, uint32_t timeout);
1311
1312 /**
1313 ****************************************************************************************
1314 * @brief Receive an amount of data in blocking mode with standard SPI.
1315 * @note This function is used only in Indirect Read Mode.
1316 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1317 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1318 * QSPI_DATA_MODE_DUALSPI
1319 * QSPI_DATA_MODE_QUADSPI
1320 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1321 * QSPI_DATASIZE_16_BITS
1322 * QSPI_DATASIZE_32_BITS
1323 * @param[in] p_data: Pointer to data buffer
1324 * @param[in] length: Amount of data to be sent in bytes
1325 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1326 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1327 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1328 * @param[in] timeout: Timeout duration
1329 * @retval ::HAL_OK: Operation is OK.
1330 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1331 * @retval ::HAL_BUSY: Driver is busy.
1332 * @retval ::HAL_TIMEOUT: Timeout occurred.
1333 ****************************************************************************************
1334 */
1335 hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length, uint32_t timeout);
1336
1337 /**
1338 ****************************************************************************************
1339 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with Interrupt.
1340 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1341 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1342 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1343 * @param[in] p_data: Pointer to data buffer
1344 * @retval ::HAL_OK: Operation is OK.
1345 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1346 * @retval ::HAL_BUSY: Driver is busy.
1347 * @retval ::HAL_TIMEOUT: Timeout occurred.
1348 ****************************************************************************************
1349 */
1350 hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1351
1352 /**
1353 ****************************************************************************************
1354 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
1355 * @note This function is used only in Indirect Read Mode.
1356 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1357 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1358 * @param[out] p_data: Pointer to data buffer
1359 * @retval ::HAL_OK: Operation is OK.
1360 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1361 * @retval ::HAL_BUSY: Driver is busy.
1362 * @retval ::HAL_TIMEOUT: Timeout occurred.
1363 ****************************************************************************************
1364 */
1365 hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1366
1367 /**
1368 ****************************************************************************************
1369 * @brief Transmit instruction in non-blocking mode with Interrupt.
1370 * @note This function is used only in Indirect Write Mode.
1371 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1372 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1373 * @retval ::HAL_OK: Operation is OK.
1374 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1375 * @retval ::HAL_BUSY: Driver is busy.
1376 * @retval ::HAL_TIMEOUT: Timeout occurred.
1377 ****************************************************************************************
1378 */
1379 hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
1380
1381 /**
1382 ****************************************************************************************
1383 * @brief Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
1384 * @note This function is used only in Indirect Write Mode.
1385 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1386 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1387 * QSPI_DATA_MODE_DUALSPI
1388 * QSPI_DATA_MODE_QUADSPI
1389 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1390 * QSPI_DATASIZE_16_BITS
1391 * QSPI_DATASIZE_32_BITS
1392 * @param[in] p_data: Pointer to data buffer
1393 * @param[in] data_length: Amount of data to be sent in bytes
1394 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1395 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1396 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1397 * @retval ::HAL_OK: Operation is OK.
1398 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1399 * @retval ::HAL_BUSY: Driver is busy.
1400 * @retval ::HAL_TIMEOUT: Timeout occurred.
1401 ****************************************************************************************
1402 */
1403 hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length);
1404
1405 /**
1406 ****************************************************************************************
1407 * @brief Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
1408 * @note This function is used only in Indirect Read Mode.
1409 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1410 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1411 * QSPI_DATA_MODE_DUALSPI
1412 * QSPI_DATA_MODE_QUADSPI
1413 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1414 * QSPI_DATASIZE_16_BITS
1415 * QSPI_DATASIZE_32_BITS
1416 * @param[in] p_data: Pointer to data buffer
1417 * @param[in] length: Amount of data to be sent in bytes
1418 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1419 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1420 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1421 * @retval ::HAL_OK: Operation is OK.
1422 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1423 * @retval ::HAL_BUSY: Driver is busy.
1424 * @retval ::HAL_TIMEOUT: Timeout occurred.
1425 ****************************************************************************************
1426 */
1427 hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1428
1429 /**
1430 ****************************************************************************************
1431 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
1432 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1433 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1434 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1435 * @param[in] p_data: Pointer to data buffer
1436 * @retval ::HAL_OK: Operation is OK.
1437 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1438 * @retval ::HAL_BUSY: Driver is busy.
1439 * @retval ::HAL_TIMEOUT: Timeout occurred.
1440 ****************************************************************************************
1441 */
1442 hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1443
1444 /**
1445 ****************************************************************************************
1446 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with DMA .
1447 * @note This function is used only in Indirect Read Mode.
1448 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1449 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1450 * @param[out] p_data: Pointer to data buffer
1451 * @retval ::HAL_OK: Operation is OK.
1452 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1453 * @retval ::HAL_BUSY: Driver is busy.
1454 * @retval ::HAL_TIMEOUT: Timeout occurred.
1455 ****************************************************************************************
1456 */
1457 hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1458
1459 /**
1460 ****************************************************************************************
1461 * @brief Transmit instruction in non-blocking mode with DMA.
1462 * @note This function is used only in Indirect Write Mode.
1463 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1464 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1465 * @retval ::HAL_OK: Operation is OK.
1466 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1467 * @retval ::HAL_BUSY: Driver is busy.
1468 * @retval ::HAL_TIMEOUT: Timeout occurred.
1469 ****************************************************************************************
1470 */
1471 hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
1472
1473 /**
1474 ****************************************************************************************
1475 * @brief Transmit an amount of data in non-blocking mode at standard SPI with DMA.
1476 * @note This function is used only in Indirect Write Mode.
1477 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1478 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1479 * QSPI_DATA_MODE_DUALSPI
1480 * QSPI_DATA_MODE_QUADSPI
1481 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1482 * QSPI_DATASIZE_16_BITS
1483 * QSPI_DATASIZE_32_BITS
1484 * @param[in] p_data: Pointer to data buffer
1485 * @param[in] length: Amount of data to be sent in bytes
1486 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1487 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1488 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1489 * @retval ::HAL_OK: Operation is OK.
1490 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1491 * @retval ::HAL_BUSY: Driver is busy.
1492 * @retval ::HAL_TIMEOUT: Timeout occurred.
1493 ****************************************************************************************
1494 */
1495 hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1496
1497 /**
1498 ****************************************************************************************
1499 * @brief Receive an amount of data in non-blocking mode at standard SPI with DMA.
1500 * @note This function is used only in Indirect Read Mode.
1501 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1502 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1503 * QSPI_DATA_MODE_DUALSPI
1504 * QSPI_DATA_MODE_QUADSPI
1505 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1506 * QSPI_DATASIZE_16_BITS
1507 * QSPI_DATASIZE_32_BITS
1508 * @param[in] p_data: Pointer to data buffer
1509 * @param[in] length: Amount of data to be sent in bytes
1510 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1511 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1512 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1513 * @retval ::HAL_OK: Operation is OK.
1514 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1515 * @retval ::HAL_BUSY: Driver is busy.
1516 * @retval ::HAL_TIMEOUT: Timeout occurred.
1517 ****************************************************************************************
1518 */
1519 hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1520
1521
1522 /**
1523 ****************************************************************************************
1524 * @brief Transmit Multi-Block of data with the specified instruction and address in non-blocking mode with DMA Linked List Block.
1525 * @note This function is used only in Indirect Write Mode.
1526 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1527 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1528 * @param[in] p_llp_config: Pointer to Linked List Block
1529 * @retval ::HAL_OK: Operation is OK.
1530 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1531 * @retval ::HAL_BUSY: Driver is busy.
1532 * @retval ::HAL_TIMEOUT: Timeout occurred.
1533 ****************************************************************************************
1534 */
1535 hal_status_t hal_qspi_command_transmit_dma_llp(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_llp_config_t * p_llp_config);
1536
1537 /**
1538 ****************************************************************************************
1539 * @brief Transmit Multi-Block of data without instruction and address in non-blocking mode with DMA Linked List Block.
1540 * @note This function is used only in Indirect Write Mode.
1541 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1542 * @param[in] p_llp_config: Pointer to Linked List Block
1543 * @param[in] data_mode : @ref QSPI_Data_Mode
1544 * @param[in] data_length: Total data length of all blocks, in terms of bytes.
1545 * 1. if data_mode equals QSPI_DATA_MODE_SPI : data_length must >= 2 bytes
1546 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : data_length must >= 4 bytes and be multiple of HALFWORD
1547 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : data_length must >= 8 bytes and be multiple of WORD
1548 * @param[in] clock_stretch_enable: Whether enable the clock stretch feature
1549 * @retval ::HAL_OK: Operation is OK.
1550 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1551 * @retval ::HAL_BUSY: Driver is busy.
1552 * @retval ::HAL_TIMEOUT: Timeout occurred.
1553 ****************************************************************************************
1554 */
1555 hal_status_t hal_qspi_transmit_dma_llp(qspi_handle_t *p_qspi, dma_llp_config_t * p_llp_config, uint32_t data_mode, uint32_t data_length, uint32_t clock_stretch_enable);
1556
1557 /**
1558 ****************************************************************************************
1559 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA Gather.
1560 * @note This function is used only in Indirect Write Mode.
1561 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1562 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1563 * @param[in] p_gather_config: Pointer to DMA Gather Configure
1564 * @param[in] p_data: Pointer to data buffer to be sent
1565 * @retval ::HAL_OK: Operation is OK.
1566 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1567 * @retval ::HAL_BUSY: Driver is busy.
1568 * @retval ::HAL_TIMEOUT: Timeout occurred.
1569 ****************************************************************************************
1570 */
1571 hal_status_t hal_qspi_command_transmit_dma_gather(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_gather_config_t * p_gather_config, uint8_t *p_data);
1572
1573
1574 /**
1575 ****************************************************************************************
1576 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA LLP.
1577 * And In Each Block, xfered specified by gather, every data block has the same gather configuration
1578 * @note This function is used only in Indirect Write Mode.
1579 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1580 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1581 * @param[in] p_llp_config: Pointer to DMA LLP Configure
1582 * @param[in] p_gather_config: Pointer to DMA Gather Configure
1583 *
1584 * @retval ::HAL_OK: Operation is OK.
1585 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1586 * @retval ::HAL_BUSY: Driver is busy.
1587 * @retval ::HAL_TIMEOUT: Timeout occurred.
1588 ****************************************************************************************
1589 */
1590 hal_status_t hal_qspi_command_transmit_dma_llp_gather(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_llp_config_t * p_llp_config, dma_gather_config_t * p_gather_config);
1591
1592
1593 /**
1594 ****************************************************************************************
1595 * @brief Receive an amount of data with the specified instruction and address in non-blocking mode with DMA Scatter.
1596 * @note This function is used only in Indirect Write Mode.
1597 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1598 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1599 * @param[in] p_data: Pointer to data buffer to be sent
1600 * @param[in] sct_interval: Specifies the destination address increment/decrement in multiples of data_size in qspi_command_t on a scatter boundary
1601 * @param[in] sct_count: Specifies the number of contiguous destination transfers of data_size in qspi_command_t between successive scatter intervals
1602 * @retval ::HAL_OK: Operation is OK.
1603 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1604 * @retval ::HAL_BUSY: Driver is busy.
1605 * @retval ::HAL_TIMEOUT: Timeout occurred.
1606 ****************************************************************************************
1607 */
1608 hal_status_t hal_qspi_command_receive_dma_scatter(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t sct_interval, uint32_t sct_count);
1609
1610
1611 /**
1612 ****************************************************************************************
1613 * @brief : Used to write PSRAM in high speed mode with dma LLP
1614 *
1615 * @note : THIS IS A RESTRICTED OR LIMITED USED FUNCTION !
1616 *
1617 * It requires the following usage Conditions :
1618 *
1619 * 1. Just USED to WRITE PSRAM, And The Length Of Block MUST be under the control of tCEM of PSRAM
1620 * 2. This Function can be USED Just When QSPI Clock Frequency is half Of System Frequency. And MUST config the prescaler firstly before calling this
1621 * 3. This Function Just Supports QUAD WRITE Command Of PSRAM in Quad Mode, such as the 0x02/0x38 QPI WRITE CMD in IPUS or AP-MEMORY
1622 * 4. Following the third point, The instruction size must be 8-bits, The address size must be 24-bits
1623 * 5. This Function Just Supports Rectangular data block, Data length in each data block are the same
1624 * 6. This Function Supports TWO DATA Block Mode : QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 (Loop Mode); QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 (Crossed Mode)
1625 * 7. When in QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 Mode, it supports the DATA_SIZE as 8/16/32bits;
1626 * When in QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 Mode, it just supports the DATA_SIZE as 8/16bits, not Support 32bits
1627 * 8. It Just support Single BURST for SRC&DST when configuring the DMA xfer
1628 * 9. Attention The Data Order.
1629 * When Data_Size is 8 Bits : INST -> ADDR-High -> ADDR-Middle -> ADDR-Low -> Byte 0 -> Byte 1 -> Byte 2 -> ...
1630 * When Data_Size is 16 Bits : ADDR-High -> INST -> ADDR-Low -> ADDR-Middle -> Short0.1 -> Short0.0 -> Short1.1 -> Short1.0 -> ...
1631 * When Data_Size is 32 Bits : ADDR-Low -> ADDR-Middle -> ADDR-High -> INST -> Word 0.3 -> Word 0.2 -> Word 0.1 -> Word 0.0 -> ...
1632 *
1633 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1634 * @param[in] p_cmd : Pointer to a psram command configuration.
1635 * @param[in] p_llp_config: Pointer to Linked List Block
1636 * @retval ::HAL_OK: Operation is OK.
1637 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1638 * @retval ::HAL_BUSY: Driver is busy.
1639 * @retval ::HAL_TIMEOUT: Timeout occurred.
1640 ****************************************************************************************
1641 */
1642 hal_status_t hal_qspi_psram_transmit_dma_llp_limited(qspi_handle_t *p_qspi, qspi_psram_command_t * p_cmd, dma_llp_config_t * p_llp_config);
1643
1644
1645 /**
1646 ****************************************************************************************
1647 * @brief Abort the current transmission.
1648 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1649 * @retval ::HAL_OK: Operation is OK.
1650 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1651 * @retval ::HAL_BUSY: Driver is busy.
1652 * @retval ::HAL_TIMEOUT: Timeout occurred.
1653 ****************************************************************************************
1654 */
1655 hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi);
1656
1657 /**
1658 ****************************************************************************************
1659 * @brief Abort the current transmission (non-blocking function)
1660 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1661 * @retval ::HAL_OK: Operation is OK.
1662 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1663 * @retval ::HAL_BUSY: Driver is busy.
1664 * @retval ::HAL_TIMEOUT: Timeout occurred.
1665 ****************************************************************************************
1666 */
1667 hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi);
1668
1669 /** @} */
1670
1671 /** @addtogroup QSPI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
1672 * @brief IRQ Handler and Callbacks functions
1673 * @{
1674 */
1675
1676 /**
1677 ****************************************************************************************
1678 * @brief Handle QSPI interrupt request.
1679 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1680 ****************************************************************************************
1681 */
1682 void hal_qspi_irq_handler(qspi_handle_t *p_qspi);
1683
1684 /**
1685 ****************************************************************************************
1686 * @brief Tx Transfer completed callback.
1687 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1688 ****************************************************************************************
1689 */
1690 void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi);
1691
1692 /**
1693 ****************************************************************************************
1694 * @brief Rx Transfer completed callback.
1695 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1696 ****************************************************************************************
1697 */
1698 void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi);
1699
1700 /**
1701 ****************************************************************************************
1702 * @brief QSPI error callback.
1703 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1704 ****************************************************************************************
1705 */
1706 void hal_qspi_error_callback(qspi_handle_t *p_qspi);
1707
1708 /**
1709 ****************************************************************************************
1710 * @brief QSPI Abort Complete callback.
1711 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1712 ****************************************************************************************
1713 */
1714 void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi);
1715
1716 /** @} */
1717
1718 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral State and Errors functions
1719 * @brief QSPI control functions
1720 *
1721 @verbatim
1722 ===============================================================================
1723 ##### Peripheral State and Errors functions #####
1724 ===============================================================================
1725 [..]
1726 This subsection provides a set of functions allowing to control the QSPI.
1727 (+) hal_qspi_get_state() API can be helpful to check in run-time the state of the QSPI peripheral.
1728 (+) hal_qspi_get_error() check in run-time Errors occurring during communication.
1729 (+) hal_qspi_set_timeout() set the timeout during internal process.
1730 @endverbatim
1731 * @{
1732 */
1733
1734 /**
1735 ****************************************************************************************
1736 * @brief Return the QSPI handle state.
1737 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1738 * @retval ::HAL_QSPI_STATE_RESET: Peripheral not initialized.
1739 * @retval ::HAL_QSPI_STATE_READY: Peripheral initialized and ready for use.
1740 * @retval ::HAL_QSPI_STATE_BUSY: Peripheral in indirect mode and busy.
1741 * @retval ::HAL_QSPI_STATE_BUSY_INDIRECT_TX: Peripheral in indirect mode with transmission ongoing.
1742 * @retval ::HAL_QSPI_STATE_BUSY_INDIRECT_RX: Peripheral in indirect mode with reception ongoing.
1743 * @retval ::HAL_QSPI_STATE_ABORT: Peripheral with abort request ongoing.
1744 * @retval ::HAL_QSPI_STATE_ERROR: Peripheral in error.
1745 ****************************************************************************************
1746 */
1747 hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi);
1748
1749 /**
1750 ****************************************************************************************
1751 * @brief Return the QSPI error code.
1752 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1753 * @return QSPI error code in bitmap format
1754 ****************************************************************************************
1755 */
1756 uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi);
1757
1758 /**
1759 ****************************************************************************************
1760 * @brief Set the QSPI cs setup & release time value.
1761 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1762 * @param[in] delay: delay clocks for cs setup & release, [0, 0x7]
1763 * @retval :: None.
1764 ****************************************************************************************
1765 */
1766 void hal_qspi_set_tcsu(qspi_handle_t *p_qspi, uint32_t delay);
1767
1768 /**
1769 ****************************************************************************************
1770 * @brief Set the QSPI internal process timeout value.
1771 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1772 * @param[in] timeout: Internal process timeout value.
1773 * @retval :: None.
1774 ****************************************************************************************
1775 */
1776 void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout);
1777
1778 /**
1779 ****************************************************************************************
1780 * @brief Suspend some registers related to QSPI configuration before sleep.
1781 * @param[in] p_qspi: Pointer to a QSPIhandle which contains the configuration
1782 * information for the specified QSPI module.
1783 * @retval ::HAL_OK: Operation is OK.
1784 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1785 * @retval ::HAL_BUSY: Driver is busy.
1786 * @retval ::HAL_TIMEOUT: Timeout occurred.
1787 ****************************************************************************************
1788 */
1789 hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi);
1790
1791 /**
1792 ****************************************************************************************
1793 * @brief Restore some registers related to QSPI configuration after sleep.
1794 * This function must be used in conjunction with the hal_qspi_suspend_reg().
1795 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration
1796 * information for the specified QSPI module.
1797 * @retval ::HAL_OK: Operation is OK.
1798 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1799 * @retval ::HAL_BUSY: Driver is busy.
1800 * @retval ::HAL_TIMEOUT: Timeout occurred.
1801 ****************************************************************************************
1802 */
1803 hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi);
1804
1805 /** @} */
1806
1807 /** @} */
1808
1809 #ifdef __cplusplus
1810 }
1811 #endif
1812
1813 #endif /* __GR55xx_HAL_QSPI_H__ */
1814
1815 /** @} */
1816
1817 /** @} */
1818
1819 /** @} */
_qspi_memorymapped_t::x_endian_mode
uint32_t x_endian_mode
Specifies endian mode in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:286
_hal_qspi_callback::qspi_msp_deinit
void(* qspi_msp_deinit)(qspi_handle_t *p_qspi)
QSPI de-init MSP callback
Definition: gr55xx_hal_qspi.h:377
_qspi_handle::tx_xfer_size
__IO uint32_t tx_xfer_size
QSPI Tx Transfer size.
Definition: gr55xx_hal_qspi.h:164
_qspi_command_t::instruction_size
uint32_t instruction_size
Specifies the Instruction Size.
Definition: gr55xx_hal_qspi.h:207
_qspi_handle::timeout
uint32_t timeout
Timeout for the QSPI memory access.
Definition: gr55xx_hal_qspi.h:186
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
qspi_memorymapped_idx_e
enum _qspi_memorymapped_idx_e qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
_qspi_memorymapped_t::x_instruction
uint32_t x_instruction
Specifies instruction in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:253
_hal_qspi_callback::qspi_rx_cplt_callback
void(* qspi_rx_cplt_callback)(qspi_handle_t *p_qspi)
QSPI rx transfer completed callback
Definition: gr55xx_hal_qspi.h:380
_qspi_memorymapped_t::x_dummy_cycles
uint32_t x_dummy_cycles
Specifies wait(dummy) cycles in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:271
_qspi_memorymapped_t::x_instruction_size
uint32_t x_instruction_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:250
HAL_MMAPPED_STATE_ACTIVED
@ HAL_MMAPPED_STATE_ACTIVED
Actived.
Definition: gr55xx_hal_qspi.h:95
hal_qspi_memorymapped_update
hal_status_t hal_qspi_memorymapped_update(qspi_handle_t *p_qspi, qspi_memorymapped_set_t *mmap_set, uint32_t count)
Used to update memorymapped any parameter quickly.
_qspi_command_t::data_size
uint32_t data_size
Specifies the QSPI address width.
Definition: gr55xx_hal_qspi.h:216
_qspi_handle::p_instance
qspi_regs_t * p_instance
QSPI registers base address.
Definition: gr55xx_hal_qspi.h:158
qspi_memorymapped_write_t
struct _qspi_memorymapped_write_t qspi_memorymapped_write_t
QSPI memory map write Structure definition.
_qspi_memorymapped_t::x_sioo_mode
uint32_t x_sioo_mode
Specifies instruction sent mode in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:244
QSPI_MMAPED_IDX_CONT_XFER_TOC
@ QSPI_MMAPED_IDX_CONT_XFER_TOC
paired value: timeout count for the continuous transfer, 0 ~ 255
Definition: gr55xx_hal_qspi.h:117
HAL_QSPI_STATE_BUSY_MEM_MAPPED
@ HAL_QSPI_STATE_BUSY_MEM_MAPPED
Definition: gr55xx_hal_qspi.h:83
_qspi_memorymapped_set_t::mmap_key
qspi_memorymapped_idx_e mmap_key
Memorymapped key.
Definition: gr55xx_hal_qspi.h:328
hal_qspi_receive
hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
_qspi_memorymapped_write_t::x_address_size
uint32_t x_address_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:307
hal_qspi_command_receive
hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
_qspi_command_t::instruction_address_mode
uint32_t instruction_address_mode
Specifies the Instruction and Address Mode.
Definition: gr55xx_hal_qspi.h:219
_qspi_memorymapped_write_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Specifies xfer format of inst & addr in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:310
HAL_QSPI_STATE_ABORT
@ HAL_QSPI_STATE_ABORT
Peripheral with abort request ongoing
Definition: gr55xx_hal_qspi.h:84
_qspi_command_t::length
uint32_t length
Specifies the number of data to transfer.
Definition: gr55xx_hal_qspi.h:225
QSPI_MMAPED_IDX_EDIAN_MODE
@ QSPI_MMAPED_IDX_EDIAN_MODE
paired value: endian mode for qspi xip
Definition: gr55xx_hal_qspi.h:118
_qspi_handle::rx_xfer_size
__IO uint32_t rx_xfer_size
QSPI Rx Transfer size
Definition: gr55xx_hal_qspi.h:170
_qspi_memorymapped_t::x_continous_xfer_en
uint32_t x_continous_xfer_en
Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:280
gr55xx_ll_qspi.h
Header file containing functions prototypes of QSPI LL library.
_qspi_handle::state
__IO hal_qspi_state_t state
QSPI communication state
Definition: gr55xx_hal_qspi.h:182
_hal_qspi_callback::qspi_error_callback
void(* qspi_error_callback)(qspi_handle_t *p_qspi)
QSPI error callback
Definition: gr55xx_hal_qspi.h:378
_qspi_handle::rx_xfer_count
__IO uint32_t rx_xfer_count
QSPI Rx Transfer Counter
Definition: gr55xx_hal_qspi.h:172
QSPI_MMAPED_IDX_ADDR_SIZE
@ QSPI_MMAPED_IDX_ADDR_SIZE
paired value: address size for concurrent xip mode
Definition: gr55xx_hal_qspi.h:108
hal_qspi_deinit
hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI peripheral.
hal_qspi_command_transmit_dma_llp_gather
hal_status_t hal_qspi_command_transmit_dma_llp_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config, dma_gather_config_t *p_gather_config)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA L...
_qspi_handle::p_tx_buffer
uint8_t * p_tx_buffer
Pointer to QSPI Tx transfer Buffer.
Definition: gr55xx_hal_qspi.h:162
_qspi_init_t
QSPI init Structure definition.
Definition: gr55xx_hal_qspi.h:137
hal_qspi_msp_init
void hal_qspi_msp_init(qspi_handle_t *p_qspi)
Initialize the QSPI MSP.
_qspi_memorymapped_t::x_instruction_en
uint32_t x_instruction_en
Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:247
HAL_QSPI_STATE_RESET
@ HAL_QSPI_STATE_RESET
Peripheral not initialized
Definition: gr55xx_hal_qspi.h:78
QSPI_MMAPED_IDX_MODE_BITS_SIZE
@ QSPI_MMAPED_IDX_MODE_BITS_SIZE
paired value: mode bits length for xip mode
Definition: gr55xx_hal_qspi.h:111
qspi_psram_command_t::data_block_length
uint32_t data_block_length
Specifies the number of data in each block, This is the number of bytes.
Definition: gr55xx_hal_qspi.h:346
hal_qspi_set_tcsu
void hal_qspi_set_tcsu(qspi_handle_t *p_qspi, uint32_t delay)
Set the QSPI cs setup & release time value.
_qspi_command_t
QSPI command Structure definition.
Definition: gr55xx_hal_qspi.h:200
_qspi_memorymapped_t::x_prefetch_en
uint32_t x_prefetch_en
Specifies whether to enable the prefetch feature.
Definition: gr55xx_hal_qspi.h:277
HAL_QSPI_STATE_READY
@ HAL_QSPI_STATE_READY
Peripheral initialized and ready for use
Definition: gr55xx_hal_qspi.h:79
hal_qspi_receive_dma
hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with DMA.
_qspi_memorymapped_write_t::x_dummy_cycles
uint32_t x_dummy_cycles
Specifies wait(dummy) cycles in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:313
_qspi_handle::write_fifo
void(* write_fifo)(struct _qspi_handle *p_qspi)
Pointer to QSPI Tx transfer FIFO write function.
Definition: gr55xx_hal_qspi.h:174
hal_qspi_init
hal_status_t hal_qspi_init(qspi_handle_t *p_qspi)
Initialize the QSPI according to the specified parameters in the qspi_init_t and initialize the assoc...
QSPI_MMAPED_IDX_MODE_BITS_EN
@ QSPI_MMAPED_IDX_MODE_BITS_EN
paired value: QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE / QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
Definition: gr55xx_hal_qspi.h:110
_qspi_command_t::address_size
uint32_t address_size
Specifies the Address Size.
Definition: gr55xx_hal_qspi.h:210
_qspi_memorymapped_t::x_address_size
uint32_t x_address_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:256
hal_qspi_msp_deinit
void hal_qspi_msp_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI MSP.
QSPI_MMAPED_IDX_DFS
@ QSPI_MMAPED_IDX_DFS
paired value: data frame size in xip, take effect when enable DFS_HC
Definition: gr55xx_hal_qspi.h:104
hal_qspi_command_transmit_it
hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with Inter...
hal_qspi_transmit_dma
hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with DMA.
_qspi_handle::retention
uint32_t retention[22]
Save important register information.
Definition: gr55xx_hal_qspi.h:188
_qspi_memorymapped_write_t::x_data_frame_format
uint32_t x_data_frame_format
Specifies enhanced spi's frame format in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:316
hal_qspi_suspend_reg
hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi)
Suspend some registers related to QSPI configuration before sleep.
hal_qspi_transmit_it
hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
hal_qspi_tx_cplt_callback
void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi)
Tx Transfer completed callback.
hal_qspi_transmit
hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
hal_qspi_command_receive_dma
hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
QSPI_MMAPED_IDX_PREFETCH_EN
@ QSPI_MMAPED_IDX_PREFETCH_EN
paired value: QSPI_CONCURRENT_XIP_PREFETCH_ENABLE / QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
Definition: gr55xx_hal_qspi.h:115
hal_qspi_abort_cplt_callback
void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi)
QSPI Abort Complete callback.
hal_qspi_command_transmit
hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Transmit an amount of data with the specified instruction and address in blocking mode.
hal_qspi_memorymapped_active
hal_status_t hal_qspi_memorymapped_active(qspi_handle_t *p_qspi, uint32_t is_sioo_mode)
Active the memory mapped mode from Ready state.
_qspi_memorymapped_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Specifies xfer format of inst & addr in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:259
_hal_qspi_callback::qspi_tx_cplt_callback
void(* qspi_tx_cplt_callback)(qspi_handle_t *p_qspi)
QSPI tx transfer completed callback
Definition: gr55xx_hal_qspi.h:381
_qspi_handle::p_dma
dma_handle_t * p_dma
QSPI Rx/Tx DMA Handle parameters
Definition: gr55xx_hal_qspi.h:178
HAL_QSPI_STATE_ERROR
@ HAL_QSPI_STATE_ERROR
Peripheral in error
Definition: gr55xx_hal_qspi.h:85
hal_qspi_memorymapped_deactive
hal_status_t hal_qspi_memorymapped_deactive(qspi_handle_t *p_qspi)
Deactive the memory mapped mode to Ready state it's recommended to use with hal_qspi_memorymapped_act...
_qspi_command_t::dummy_cycles
uint32_t dummy_cycles
Specifies the Number of Dummy Cycles.
Definition: gr55xx_hal_qspi.h:213
hal_qspi_irq_handler
void hal_qspi_irq_handler(qspi_handle_t *p_qspi)
Handle QSPI interrupt request.
hal_qspi_abort
hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi)
Abort the current transmission.
hal_memorymapped_status_t
hal_memorymapped_status_t
HAL Status structures Of memorymapped definition.
Definition: gr55xx_hal_qspi.h:93
_qspi_memorymapped_write_t::x_instruction_size
uint32_t x_instruction_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:301
_qspi_memorymapped_set_t
KEY:Value pair to set memorymapped parameter.
Definition: gr55xx_hal_qspi.h:327
qspi_psram_command_t::llp_data_mode
uint32_t llp_data_mode
Specifies Linked list data mode.
Definition: gr55xx_hal_qspi.h:351
qspi_memorymapped_set_t
struct _qspi_memorymapped_set_t qspi_memorymapped_set_t
KEY:Value pair to set memorymapped parameter.
_hal_qspi_callback
HAL_QSPI Callback function definition.
Definition: gr55xx_hal_qspi.h:375
hal_qspi_rx_cplt_callback
void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi)
Rx Transfer completed callback.
QSPI_MMAPED_IDX_INST_SIZE
@ QSPI_MMAPED_IDX_INST_SIZE
paired value: instruction size for concurrent xip mode
Definition: gr55xx_hal_qspi.h:106
hal_qspi_transmit_dma_llp
hal_status_t hal_qspi_transmit_dma_llp(qspi_handle_t *p_qspi, dma_llp_config_t *p_llp_config, uint32_t data_mode, uint32_t data_length, uint32_t clock_stretch_enable)
Transmit Multi-Block of data without instruction and address in non-blocking mode with DMA Linked Lis...
QSPI_MMAPED_IDX_DATA_FRF
@ QSPI_MMAPED_IDX_DATA_FRF
paired value: frame format for concurrent xip mode
Definition: gr55xx_hal_qspi.h:114
QSPI_MMAPED_IDX_INST_VAL
@ QSPI_MMAPED_IDX_INST_VAL
paired value: instruction data
Definition: gr55xx_hal_qspi.h:107
_qspi_memorymapped_t
QSPI memory map Structure definition.
Definition: gr55xx_hal_qspi.h:242
_qspi_memorymapped_write_t
QSPI memory map write Structure definition.
Definition: gr55xx_hal_qspi.h:299
hal_qspi_abort_it
hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi)
Abort the current transmission (non-blocking function)
QSPI_MMAPED_IDX_WAIT_CYCLES
@ QSPI_MMAPED_IDX_WAIT_CYCLES
paired value: wait cycles, 0 ~ 31
Definition: gr55xx_hal_qspi.h:113
qspi_command_t
struct _qspi_command_t qspi_command_t
QSPI command Structure definition.
HAL_QSPI_STATE_BUSY_INDIRECT_RX
@ HAL_QSPI_STATE_BUSY_INDIRECT_RX
Peripheral in indirect mode with reception ongoing
Definition: gr55xx_hal_qspi.h:82
_qspi_memorymapped_write_t::x_instruction
uint32_t x_instruction
Specifies instruction in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:304
_hal_qspi_callback::qspi_abort_cplt_callback
void(* qspi_abort_cplt_callback)(qspi_handle_t *p_qspi)
QSPI abort complete callback
Definition: gr55xx_hal_qspi.h:379
QSPI_MMAPED_IDX_CONT_XFER_EN
@ QSPI_MMAPED_IDX_CONT_XFER_EN
paired value: QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE / QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
Definition: gr55xx_hal_qspi.h:116
hal_qspi_psram_transmit_dma_llp_limited
hal_status_t hal_qspi_psram_transmit_dma_llp_limited(qspi_handle_t *p_qspi, qspi_psram_command_t *p_cmd, dma_llp_config_t *p_llp_config)
: Used to write PSRAM in high speed mode with dma LLP
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
hal_qspi_command
hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
_qspi_memorymapped_t::x_continous_xfer_toc
uint32_t x_continous_xfer_toc
Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:283
_qspi_init_t::clock_prescaler
uint32_t clock_prescaler
Specifies the prescaler factor for generating clock based on the AHB clock.
Definition: gr55xx_hal_qspi.h:138
_qspi_handle::read_fifo
void(* read_fifo)(struct _qspi_handle *p_qspi)
Pointer to QSPI Rx transfer FIFO read function
Definition: gr55xx_hal_qspi.h:176
hal_qspi_command_transmit_dma_llp
hal_status_t hal_qspi_command_transmit_dma_llp(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config)
Transmit Multi-Block of data with the specified instruction and address in non-blocking mode with DMA...
qspi_psram_command_t::data_size
uint32_t data_size
Specifies the QSPI data width.
Definition: gr55xx_hal_qspi.h:341
HAL_MMAPPED_STATE_DEACTIVED
@ HAL_MMAPPED_STATE_DEACTIVED
Deactived.
Definition: gr55xx_hal_qspi.h:94
_qspi_memorymapped_t::x_data_frame_format
uint32_t x_data_frame_format
Specifies enhanced spi's frame format in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:274
QSPI_MMAPED_IDX_DFS_HARDCCODE_EN
@ QSPI_MMAPED_IDX_DFS_HARDCCODE_EN
paired value: QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE/QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
Definition: gr55xx_hal_qspi.h:103
_qspi_handle::error_code
__IO uint32_t error_code
QSPI Error code
Definition: gr55xx_hal_qspi.h:184
hal_qspi_resume_reg
hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi)
Restore some registers related to QSPI configuration after sleep.
dma_llp_config
LL DMA llp config definition.
Definition: gr55xx_hal_dma.h:197
hal_qspi_command_receive_it
hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
_qspi_handle::init
qspi_init_t init
QSPI communication parameters.
Definition: gr55xx_hal_qspi.h:160
qspi_psram_command_t::llp_data_shape
uint32_t llp_data_shape
Specifies Linked list data shape.
Definition: gr55xx_hal_qspi.h:353
_qspi_memorymapped_idx_e
_qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
Definition: gr55xx_hal_qspi.h:102
_qspi_handle::lock
__IO hal_lock_t lock
Locking object
Definition: gr55xx_hal_qspi.h:180
_qspi_command_t::instruction
uint32_t instruction
Specifies the Instruction to be sent.
Definition: gr55xx_hal_qspi.h:201
_qspi_memorymapped_t::x_mode_bits_en
uint32_t x_mode_bits_en
Specifies whether to enable mode bits phase in memorymapped(xip) mode.
Definition: gr55xx_hal_qspi.h:262
_qspi_handle::tx_xfer_count
__IO uint32_t tx_xfer_count
QSPI Tx Transfer Counter
Definition: gr55xx_hal_qspi.h:166
HAL_QSPI_STATE_BUSY_INDIRECT_TX
@ HAL_QSPI_STATE_BUSY_INDIRECT_TX
Peripheral in indirect mode with transmission ongoing.
Definition: gr55xx_hal_qspi.h:81
hal_qspi_command_transmit_dma
hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
hal_qspi_set_timeout
void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout)
Set the QSPI internal process timeout value.
hal_qspi_memorymapped
hal_status_t hal_qspi_memorymapped(qspi_handle_t *p_qspi, qspi_memorymapped_t *mmap_cmd, qspi_memorymapped_write_t *mmap_wr_cmd)
Configure the Memory Mapped mode.
dma_gather_config
LL DMA gather config definition.
Definition: gr55xx_hal_dma.h:181
qspi_handle_t
struct _qspi_handle qspi_handle_t
QSPI handle Structure definition.
hal_qspi_receive_it
hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
_qspi_memorymapped_set_t::mmap_val
uint32_t mmap_val
Memorymapped value.
Definition: gr55xx_hal_qspi.h:329
hal_qspi_command_it
hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
_qspi_command_t::data_mode
uint32_t data_mode
Specifies the Data Mode (used for dummy cycles and data phases).
Definition: gr55xx_hal_qspi.h:222
HAL_QSPI_STATE_BUSY
@ HAL_QSPI_STATE_BUSY
Peripheral in indirect mode and busy
Definition: gr55xx_hal_qspi.h:80
qspi_init_t
struct _qspi_init_t qspi_init_t
QSPI init Structure definition.
hal_qspi_callback_t
struct _hal_qspi_callback hal_qspi_callback_t
HAL_QSPI Callback function definition.
hal_qspi_command_receive_dma_scatter
hal_status_t hal_qspi_command_receive_dma_scatter(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t sct_interval, uint32_t sct_count)
Receive an amount of data with the specified instruction and address in non-blocking mode with DMA Sc...
hal_qspi_state_t
hal_qspi_state_t
HAL QSPI State Enumerations definition.
Definition: gr55xx_hal_qspi.h:77
qspi_psram_command_t
QSPI command for psram-write Structure definition.
Definition: gr55xx_hal_qspi.h:339
hal_qspi_get_state
hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi)
Return the QSPI handle state.
_hal_qspi_callback::qspi_msp_init
void(* qspi_msp_init)(qspi_handle_t *p_qspi)
QSPI init MSP callback
Definition: gr55xx_hal_qspi.h:376
hal_qspi_command_dma
hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with DMA.
_qspi_handle::p_rx_buffer
uint8_t * p_rx_buffer
Pointer to QSPI Rx transfer Buffer.
Definition: gr55xx_hal_qspi.h:168
_qspi_handle
QSPI handle Structure definition.
Definition: gr55xx_hal_qspi.h:157
_qspi_command_t::address
uint32_t address
Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
Definition: gr55xx_hal_qspi.h:204
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:277
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
QSPI_MMAPED_IDX_MODE_BITS_VAL
@ QSPI_MMAPED_IDX_MODE_BITS_VAL
paired value: mode bits data
Definition: gr55xx_hal_qspi.h:112
hal_qspi_get_error
uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi)
Return the QSPI error code.
_qspi_command_t::clock_stretch_en
uint32_t clock_stretch_en
Specifies whether to enable the clock stretch feature This parameter can be LL_QSPI_CLK_STRETCH_ENABL...
Definition: gr55xx_hal_qspi.h:230
HAL_MMAPPED_STATE_ERROR
@ HAL_MMAPPED_STATE_ERROR
Actived.
Definition: gr55xx_hal_qspi.h:96
qspi_memorymapped_t
struct _qspi_memorymapped_t qspi_memorymapped_t
QSPI memory map Structure definition.
_qspi_init_t::clock_mode
uint32_t clock_mode
Specifies the Clock Mode.
Definition: gr55xx_hal_qspi.h:141
hal_qspi_error_callback
void hal_qspi_error_callback(qspi_handle_t *p_qspi)
QSPI error callback.
QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT
@ QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT
paired value: transfer of inst & address for concurrent xip mode
Definition: gr55xx_hal_qspi.h:109
_qspi_memorymapped_t::x_mode_bits_data
uint32_t x_mode_bits_data
Specifies value of mode bits phase.
Definition: gr55xx_hal_qspi.h:268
_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_hal_qspi.h:144
hal_qspi_memorymapped_is_actived
hal_memorymapped_status_t hal_qspi_memorymapped_is_actived(qspi_handle_t *p_qspi)
Check whether the memory mapped mode is Actived.
_qspi_memorymapped_t::x_mode_bits_length
uint32_t x_mode_bits_length
Specifies mode bits length.
Definition: gr55xx_hal_qspi.h:265
QSPI_MMAPED_IDX_INST_EN
@ QSPI_MMAPED_IDX_INST_EN
paired value: QSPI_CONCURRENT_XIP_INST_ENABLE/QSPI_CONCURRENT_XIP_INST_DISABLE
Definition: gr55xx_hal_qspi.h:105
hal_qspi_command_transmit_dma_gather
hal_status_t hal_qspi_command_transmit_dma_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_gather_config_t *p_gather_config, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA G...