gr55xx_ll_pwr.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (AON_CTL) && defined (AON_IO)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
70 * @{
71 */
72
73 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
74 * @{
75 */
76 #define LL_PWR_WKUP_COND_EXT AON_CTL_MCU_WAKEUP_CTRL_EXT /**< External wakeup: AON_GPIO */
77 #define LL_PWR_WKUP_COND_TIMER AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER /**< AON Timer wakeup */
78 #define LL_PWR_WKUP_COND_BLE AON_CTL_MCU_WAKEUP_CTRL_SMS_OSC /**< BLE wakeup */
79 #define LL_PWR_WKUP_COND_CLDR AON_CTL_MCU_WAKEUP_CTRL_RTC0 /**< RTC0 wakeup */
80 #define LL_PWR_WKUP_COND_CLDR_TICK AON_CTL_MCU_WAKEUP_CTRL_RTC1 /**< RTC0 wakeup */
81 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_CTL_MCU_WAKEUP_CTRL_PMU_BOD /**< PMU Bod falling edge wakeup */
82 #define LL_PWR_WKUP_COND_AUSB AON_CTL_MCU_WAKEUP_CTRL_USB_ATTACH /**< USB ATTACH wakeup */
83 #define LL_PWR_WKUP_COND_DUSB AON_CTL_MCU_WAKEUP_CTRL_USB_DETACH /**< USB DETACH wakeup */
84 #define LL_PWR_WKUP_COND_BLE_IRQ AON_CTL_MCU_WAKEUP_CTRL_BLE_IRQ /**< BLE IRQ wakeup */
85 #define LL_PWR_WKUP_COND_AON_WDT AON_CTL_MCU_WAKEUP_CTRL_AON_WDT /**< AON WDT reahch 0 wakeup */
86 #define LL_PWR_WKUP_COND_COMP AON_CTL_MCU_WAKEUP_CTRL_PMU_COMP /**< COMP wakeup */
87 #define LL_PWR_WKUP_COND_ALL (0xFFFU << AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER_Pos) /**< All wakeup sources mask */
88
89 /** @} */
90
91 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
92 * @note Only available on GR551xx_B2 and later version
93 * @{
94 */
95 #define LL_PWR_WKUP_EVENT_BLE AON_CTL_SLP_EVENT_SMS_OSC /**< BLE Timer wakeup event */
96 #define LL_PWR_WKUP_EVENT_TIMER AON_CTL_SLP_EVENT_SLP_TIMER /**< AON Timer wakeup event */
97 #define LL_PWR_WKUP_EVENT_EXT AON_CTL_SLP_EVENT_EXT /**< External wakeup event: AON_GPIO */
98 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_CTL_SLP_EVENT_PMU_BOD /**< PMU Bod wakeup event */
99 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_CTL_SLP_EVENT_PMU_MSIO /**< Msio comparator wakeup event */
100 #define LL_PWR_WKUP_EVENT_WDT AON_CTL_SLP_EVENT_AON_WDT /**< AON WDT Alarm wakeup event */
101 #define LL_PWR_WKUP_EVENT_CLDR AON_CTL_SLP_EVENT_RTC0 /**< RTC0 wakeup event */
102 #define LL_PWR_WKUP_EVENT_AUSB AON_CTL_SLP_EVENT_USB_ATTACH /**< USB attach wakeup event */
103 #define LL_PWR_WKUP_EVENT_DUSB AON_CTL_SLP_EVENT_USB_DETACH /**< USB detach wakeup event */
104 #define LL_PWR_WKUP_EVENT_CLDR_TICK AON_CTL_SLP_EVENT_RTC1 /**< RTC1 wakeup event */
105 #define LL_PWR_WKUP_EVENT_BLE_IRQ AON_CTL_SLP_EVENT_BLE_IRQ /**< BLE IRQ wakeup event */
106 #define LL_PWR_WKUP_EVENT_ALL (0xFFFU << AON_CTL_SLP_EVENT_SLP_TIMER_Pos) /**< All event mask */
107 /** @} */
108
109 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
110 * @{
111 */
112 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
113 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
114 /** @} */
115
116 /** @} */
117
118 /** @} */
119
120 /* Exported functions --------------------------------------------------------*/
121 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
122 * @{
123 */
124
125 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
126 * @{
127 */
128
129 /**
130 * @brief Set the DeepSleep WakeUp Condition
131 *
132 * Register|BitsName
133 * --------|--------
134 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
135 *
136 * @param condition This parameter can be one of the following values:
137 * @arg @ref LL_PWR_WKUP_COND_EXT
138 * @arg @ref LL_PWR_WKUP_COND_TIMER
139 * @arg @ref LL_PWR_WKUP_COND_BLE
140 * @arg @ref LL_PWR_WKUP_COND_CLDR
141 * @arg @ref LL_PWR_WKUP_COND_CLDR_TICK
142 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
143 * @arg @ref LL_PWR_WKUP_COND_AUSB
144 * @arg @ref LL_PWR_WKUP_COND_DUSB
145 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
146 * @arg @ref LL_PWR_WKUP_COND_COMP
147 * @arg @ref LL_PWR_WKUP_COND_ALL
148 * @retval None
149 */
150 __STATIC_FORCEINLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
151 {
152 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
153 }
154
155 /**
156 * @brief Clear the DeepSleep WakeUp Condition
157 *
158 * Register|BitsName
159 * --------|--------
160 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
161 *
162 * @param condition This parameter can be one of the following values:
163 * @arg @ref LL_PWR_WKUP_COND_EXT
164 * @arg @ref LL_PWR_WKUP_COND_TIMER
165 * @arg @ref LL_PWR_WKUP_COND_BLE
166 * @arg @ref LL_PWR_WKUP_COND_CLDR
167 * @arg @ref LL_PWR_WKUP_COND_CLDR_TICK
168 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
169 * @arg @ref LL_PWR_WKUP_COND_AUSB
170 * @arg @ref LL_PWR_WKUP_COND_DUSB
171 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
172 * @arg @ref LL_PWR_WKUP_COND_COMP
173 * @arg @ref LL_PWR_WKUP_COND_ALL
174 * @retval None
175 */
176 __STATIC_FORCEINLINE void ll_pwr_clear_wakeup_condition(uint32_t condition)
177 {
178 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
179 }
180
181 /**
182 * @brief Get the Selected DeepSleep WakeUp Condition
183 *
184 * Register|BitsName
185 * --------|--------
186 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
187 *
188 * @retval Returned value can be one of the following values:
189 * @arg @ref LL_PWR_WKUP_COND_EXT
190 * @arg @ref LL_PWR_WKUP_COND_EXT
191 * @arg @ref LL_PWR_WKUP_COND_TIMER
192 * @arg @ref LL_PWR_WKUP_COND_BLE
193 * @arg @ref LL_PWR_WKUP_COND_CLDR
194 * @arg @ref LL_PWR_WKUP_COND_CLDR_TICK
195 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
196 * @arg @ref LL_PWR_WKUP_COND_AUSB
197 * @arg @ref LL_PWR_WKUP_COND_DUSB
198 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
199 * @arg @ref LL_PWR_WKUP_COND_COMP
200 * @arg @ref LL_PWR_WKUP_COND_ALL
201 */
202 __STATIC_FORCEINLINE uint32_t ll_pwr_get_wakeup_condition(void)
203 {
204 return ((uint32_t)READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, LL_PWR_WKUP_COND_ALL));
205 }
206
207 /**
208 * @brief Get the Event that triggered the DeepSleep WakeUp.
209 * @note Only available on GR551xx_B2 and later version
210 *
211 * Register|BitsName
212 * --------|--------
213 * AON_SLP_EVENT | AON_SLP_EVENT
214 *
215 * @retval Returned value can be combination of the following values:
216 * @arg @ref LL_PWR_WKUP_EVENT_BLE
217 * @arg @ref LL_PWR_WKUP_EVENT_BLE
218 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
219 * @arg @ref LL_PWR_WKUP_EVENT_EXT
220 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
221 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
222 * @arg @ref LL_PWR_WKUP_EVENT_WDT
223 * @arg @ref LL_PWR_WKUP_EVENT_CLDR
224 * @arg @ref LL_PWR_WKUP_EVENT_AUSB
225 * @arg @ref LL_PWR_WKUP_EVENT_DUSB
226 * @arg @ref LL_PWR_WKUP_EVENT_CLDR_TICK
227 * @arg @ref LL_PWR_WKUP_EVENT_BLE_IRQ
228 */
229 __STATIC_FORCEINLINE uint32_t ll_pwr_get_wakeup_event(void)
230 {
231 return ((uint32_t)READ_BITS(AON_CTL->AON_SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
232 }
233
234 /**
235 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
236 * @note After the value was set, use LL_PWR_CMD_32_TIMER_LD command to
237 * load the configuration into Power State Controller.
238 *
239 * Register|BitsName
240 * --------|--------
241 * SLEEP_TIMER_W | SLEEP_TIMER_W
242 *
243 * @param value 32 bits count value loaded into the t32bit_timer
244 * @retval None
245 */
246 __STATIC_FORCEINLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
247 {
248 WRITE_REG(SLP_TIMER->TIMER_W, value);
249 }
250
251 /**
252 * @brief Read the AON Sleep Timer counter current value.
253 *
254 * Register|BitsName
255 * --------|--------
256 * SLEEP_TIMER_R | PWR_CTL_TIMER_32B
257 *
258 * @retval 32 bit AON Timer Count Value
259 */
260 __STATIC_FORCEINLINE uint32_t ll_pwr_get_sleep_timer_read_value(void)
261 {
262 return READ_REG(SLP_TIMER->TIMER_R);
263 }
264
265
266 /**
267 * @brief Enable the SMC WakeUp Request.
268 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
269 *
270 * Register|BitsName
271 * --------|--------
272 * BLE_MISC | SMC_WAKEUP_REQ
273 *
274 * @retval None
275 */
276 __STATIC_FORCEINLINE void ll_pwr_enable_smc_wakeup_req(void)
277 {
278 SET_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
279 }
280
281 /**
282 * @brief Disable the SMC WakeUp Request.
283 * @note This function is used to clear SMC WakeUp Request.
284 *
285 * Register|BitsName
286 * --------|--------
287 * BLE_MISC | SMC_WAKEUP_REQ
288 *
289 * @retval None
290 */
291 __STATIC_FORCEINLINE void ll_pwr_disable_smc_wakeup_req(void)
292 {
293 CLEAR_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
294 }
295
296 /**
297 * @brief Check if the SMC WakeUp Request was enabled or disabled.
298 *
299 * Register|BitsName
300 * --------|--------
301 * BLE_MISC | SMC_WAKEUP_REQ
302 *
303 * @retval State of bit (1 or 0).
304 */
305 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
306 {
307 return (READ_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ) == AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
308 }
309
310 /**
311 * @brief Set the DPAD LE value during sleep and after wake up.
312 *
313 * Register|BitsName
314 * --------|--------
315 * DPAD_LE_CTRL | DPAD_LE_SLP_VAL
316 * DPAD_LE_CTRL | DPAD_LE_WKUP_VAL
317 *
318 * @param sleep This parameter can be one of the following values:
319 * @arg @ref LL_PWR_DPAD_LE_OFF
320 * @arg @ref LL_PWR_DPAD_LE_ON
321 * @param wakeup This parameter can be one of the following values:
322 * @arg @ref LL_PWR_DPAD_LE_OFF
323 * @arg @ref LL_PWR_DPAD_LE_ON
324 * @retval None
325 */
326 __STATIC_FORCEINLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
327 {
328 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_SLEEP, (sleep << AON_PWR_DPAD_LE_CTRL_SLEEP_Pos));
329 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_WAKEUP, (wakeup << AON_PWR_DPAD_LE_CTRL_WAKEUP_Pos));
330 }
331
332 /** @} */
333
334 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
335 * @{
336 */
337
338 /**
339 * @brief Enable the Communication Timer Reset.
340 * @note Comm timer can be reset when all ble connection were disconnected and
341 * MCU was ready to enter into deepsleep mode.
342 *
343 * Register|BitsName
344 * --------|--------
345 * COMM_CTRL | COMM_TIMER_RST_N
346 *
347 * @retval None
348 */
349 __STATIC_FORCEINLINE void ll_pwr_enable_comm_timer_reset(void)
350 {
351 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
352 }
353
354 /**
355 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
356 * @note After powered up, Comm Timer need to enter into running mode.
357 *
358 * Register|BitsName
359 * --------|--------
360 * COMM_CTRL | COMM_TIMER_RST_N
361 *
362 * @retval None
363 */
364 __STATIC_FORCEINLINE void ll_pwr_disable_comm_timer_reset(void)
365 {
366 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
367 }
368
369 /**
370 * @brief Check if the Communication Timer Reset was enabled or disabled.
371 *
372 * Register|BitsName
373 * --------|--------
374 * COMM_CTRL | COMM_TIMER_RST_N
375 *
376 * @retval State of bit (1 or 0).
377 */
378 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
379 {
380 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N) == 0x0U));
381 }
382
383 /**
384 * @brief Enable the Communication Core Reset.
385 * @note Comm Core can be reset when all ble connection were disconnected and
386 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
387 * is 0, the ble is held in reset.
388 *
389 * Register|BitsName
390 * --------|--------
391 * COMM_CTRL | COMM_CORE_RST_N
392 *
393 * @retval None
394 */
395 __STATIC_FORCEINLINE void ll_pwr_enable_comm_core_reset(void)
396 {
397 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
398 }
399
400 /**
401 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
402 * @note After powered up, Comm Core need to enter into running mode.
403 *
404 * Register|BitsName
405 * --------|--------
406 * COMM_CTRL | COMM_CORE_RST_N
407 *
408 * @retval None
409 */
410 __STATIC_FORCEINLINE void ll_pwr_disable_comm_core_reset(void)
411 {
412 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
413 }
414
415 /**
416 * @brief Check if the Communication Core Reset was enabled or disabled.
417 *
418 * Register|BitsName
419 * --------|--------
420 * COMM_CTRL | COMM_CORE_RST_N
421 *
422 * @retval State of bit (1 or 0).
423 */
424 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
425 {
426 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_RST_N_RD) == 0x0U));
427 }
428
429 /**
430 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
431 *
432 * Register|BitsName
433 * --------|--------
434 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
435 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
436 *
437 * @retval None
438 */
439 __STATIC_FORCEINLINE void ll_pwr_enable_comm_timer_power(void)
440 {
441 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
442 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
443 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
444 }
445
446 /**
447 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
448 *
449 * Register|BitsName
450 * --------|--------
451 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
452 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
453 *
454 * @retval None
455 */
456 __STATIC_FORCEINLINE void ll_pwr_disable_comm_timer_power(void)
457 {
458 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
459 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
460 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
461 }
462
463 /**
464 * @brief Check if the Communication Timer Power was enabled or disabled.
465 *
466 * Register|BitsName
467 * --------|--------
468 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
469 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
470 *
471 * @retval State of bit (1 or 0).
472 */
473 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
474 {
475 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN) == AON_PWR_COMM_TIMER_PWR_CTRL_EN));
476 }
477
478 /**
479 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
480 *
481 * Register|BitsName
482 * --------|--------
483 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
484 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
485 *
486 * @retval None
487 */
488 __STATIC_FORCEINLINE void ll_pwr_enable_comm_core_power(void)
489 {
490 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
491 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
492 }
493
494 /**
495 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
496 *
497 * Register|BitsName
498 * --------|--------
499 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
500 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
501 *
502 * @retval None
503 */
504 __STATIC_FORCEINLINE void ll_pwr_disable_comm_core_power(void)
505 {
506 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
507 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
508 }
509
510 /**
511 * @brief Check if the Communication Core Power was enabled or disabled.
512 *
513 * Register|BitsName
514 * --------|--------
515 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
516 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
517 *
518 * @retval None
519 */
520 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
521 {
522 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD) == AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD));
523 }
524
525 /**
526 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
527 *
528 * Register|BitsName
529 * --------|--------
530 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
531 *
532 * @retval None
533 */
534 __STATIC_FORCEINLINE void ll_pwr_enable_osc_sleep(void)
535 {
536 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
537 }
538
539 /**
540 * @brief Disable high frequency crystal oscillator sleep mode.
541 * @note Switch OSC from sleep mode into normal active mode.
542 *
543 * Register|BitsName
544 * --------|--------
545 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
546 *
547 * @retval None
548 */
549 __STATIC_FORCEINLINE void ll_pwr_disable_osc_sleep(void)
550 {
551 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
552 }
553
554 /**
555 * @brief Check if the OSC sleep mode was enabled or disabled.
556 *
557 * Register|BitsName
558 * --------|--------
559 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
560 *
561 * @retval State of bit (1 or 0).
562 */
563 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
564 {
565 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN));
566 }
567
568 /**
569 * @brief Enable Radio sleep mode, and disable Radio module.
570 *
571 * Register|BitsName
572 * --------|--------
573 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
574 *
575 * @retval None
576 */
577 __STATIC_FORCEINLINE void ll_pwr_enable_radio_sleep(void)
578 {
579 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
580 }
581
582 /**
583 * @brief Disable Radio sleep mode.
584 * @note Switch Radio from sleep mode into normal active mode.
585 *
586 * Register|BitsName
587 * --------|--------
588 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
589 *
590 * @retval None
591 */
592 __STATIC_FORCEINLINE void ll_pwr_disable_radio_sleep(void)
593 {
594 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
595 }
596
597 /**
598 * @brief Check if the Radio sleep mode was enabled or disabled.
599 *
600 * Register|BitsName
601 * --------|--------
602 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
603 *
604 * @retval State of bit (1 or 0).
605 */
606 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
607 {
608 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN));
609 }
610
611 /**
612 * @brief Enable Communication Core Deep Sleep Mode.
613 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
614 *
615 * Register|BitsName
616 * --------|--------
617 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
618 *
619 * @retval None
620 */
621 __STATIC_FORCEINLINE void ll_pwr_enable_comm_core_deep_sleep(void)
622 {
623 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
624 }
625
626 /**
627 * @brief Disable Communication Core Deep Sleep Mode.
628 * @note Switch Communication Core from sleep mode into normal active mode.
629 *
630 * Register|BitsName
631 * --------|--------
632 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
633 *
634 * @retval None
635 */
636 __STATIC_FORCEINLINE void ll_pwr_disable_comm_core_deep_sleep(void)
637 {
638 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
639 }
640
641 /**
642 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
643 *
644 * Register|BitsName
645 * --------|--------
646 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
647 *
648 * @retval State of bit (1 or 0).
649 */
650 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
651 {
652 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON));
653 }
654
655 /**
656 * @brief Enable Wake Up Request from Software.
657 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
658 * when written with a 1. No action happens if it is written with 0.
659 *
660 * Register|BitsName
661 * --------|--------
662 * BLE_PWR_CTL | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
663 *
664 * @retval None
665 */
666 __STATIC_FORCEINLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
667 {
668 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ);
669 }
670
671 /**
672 * @brief Check if the Wake Up Request was enabled or disabled.
673 * @note Resets at 0 means request action is performed.
674 *
675 * Register|BitsName
676 * --------|--------
677 * BLE_PWR_CTL | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
678 *
679 * @retval State of bit (1 or 0).
680 */
681 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
682 {
683 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ));
684 }
685
686 /**
687 * @brief Enable Communication Core external wakeup.
688 * @note After this configuration, Communication Core can be woken up by external wake-up
689 *
690 * Register|BitsName
691 * --------|--------
692 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
693 *
694 * @retval None
695 */
696 __STATIC_FORCEINLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
697 {
698 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
699 }
700
701 /**
702 * @brief Disable Communication Core external wakeup.
703 * @note After this configuration, Communication Core cannot be woken up by external wake-up
704 *
705 * Register|BitsName
706 * --------|--------
707 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
708 *
709 * @retval None
710 */
711 __STATIC_FORCEINLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
712 {
713 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
714 }
715
716 /**
717 * @brief Check if the Communication Core external wakeup was enabled or disabled.
718 *
719 * Register|BitsName
720 * --------|--------
721 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
722 *
723 * @retval State of bit (1 or 0).
724 */
725 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
726 {
727 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
728 }
729
730 /**
731 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
732 *
733 * Register|BitsName
734 * --------|--------
735 * COMM_TIMER_CFG_0 | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
736 *
737 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
738 * @retval None
739 */
740 __STATIC_FORCEINLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
741 {
742 WRITE_REG(AON_CTL->COMM_TIMER_CFG0, time);
743 }
744
745 /**
746 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
747 *
748 * Register|BitsName
749 * --------|--------
750 * COMM_TIMER_CFG_0 | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
751 *
752 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
753 */
754 __STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
755 {
756 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG0));
757 }
758
759 /**
760 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
761 *
762 * Register|BitsName
763 * --------|--------
764 * COMM_TMR_REG | DEEPSLDUR
765 *
766 * @retval Sleep duration
767 */
768 __STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
769 {
770 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_STAT));
771 }
772
773 /**
774 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
775 *
776 * Register|BitsName
777 * --------|--------
778 * COMM_TIMER_CFG_1 | TWEXT
779 * COMM_TIMER_CFG_1 | TWOSC
780 * COMM_TIMER_CFG_1 | TWRM
781 *
782 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
783 * oscillator following an external wake–up request (signal wakeup_req).
784 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
785 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
786 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
787 * @retval None
788 */
789 __STATIC_FORCEINLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
790 {
791 WRITE_REG(AON_CTL->COMM_TIMER_CFG1, (twext << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWEXT_Pos) |
792 (twosc << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos) |
793 (twrm << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWRM_Pos));
794 }
795
796 /**
797 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
798 *
799 * Register|BitsName
800 * --------|--------
801 * COMM_TIMER_CFG_1 | TWEXT
802 * COMM_TIMER_CFG_1 | TWOSC
803 * COMM_TIMER_CFG_1 | TWRM
804 *
805 * @retval COMM_TMR_ENBPRESET Register value
806 */
807 __STATIC_FORCEINLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
808 {
809 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1));
810 }
811
812 /**
813 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
814 *
815 * @retval TWOSC value
816 */
817 __STATIC_FORCEINLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
818 {
819 return ((((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1) & AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Msk)) >> AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos);
820 }
821
822 /** @} */
823
824 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
825 * @{
826 */
827
828 /**
829 * @brief Get the External Wake Up Status.
830 * @note 0 means not waked up and 1 means waked up.
831 *
832 * Register|BitsName
833 * --------|--------
834 * EXT_WAKEUP_STAT | EXT_WKUP_STATUS
835 *
836 * @retval Returned value can be a combination of the following values:
837 * LL_PWR_EXTWKUP_PIN0
838 * LL_PWR_EXTWKUP_PIN1
839 * LL_PWR_EXTWKUP_PIN2
840 * LL_PWR_EXTWKUP_PIN3
841 * LL_PWR_EXTWKUP_PIN4
842 * LL_PWR_EXTWKUP_PIN5
843 * LL_PWR_EXTWKUP_PIN6
844 * LL_PWR_EXTWKUP_PIN7
845 * LL_PWR_EXTWKUP_PIN_ALL
846 */
847 __STATIC_FORCEINLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
848 {
849 return ((uint32_t)(READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) >> AON_IO_EXT_WAKEUP_STAT_STAT_POS));
850 }
851
852 /**
853 * @brief Clear the External Wake Up Status.
854 *
855 * Register|BitsName
856 * --------|--------
857 * EXT_WAKEUP_STAT | EXT_WKUP_STATUS
858 *
859 * @param wakeup_pin This parameter can be a combination of the following values:
860 * LL_PWR_EXTWKUP_PIN0
861 * LL_PWR_EXTWKUP_PIN1
862 * LL_PWR_EXTWKUP_PIN2
863 * LL_PWR_EXTWKUP_PIN3
864 * LL_PWR_EXTWKUP_PIN4
865 * LL_PWR_EXTWKUP_PIN5
866 * LL_PWR_EXTWKUP_PIN6
867 * LL_PWR_EXTWKUP_PIN7
868 * LL_PWR_EXTWKUP_PIN_ALL
869 * @retval None
870 */
871 __STATIC_FORCEINLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
872 {
873 WRITE_REG(AON_IO->EXT_WAKEUP_STAT, ~(wakeup_pin << AON_IO_EXT_WAKEUP_STAT_STAT_POS));
874 }
875
876 /**
877 * @brief Clear the Event that triggered the DeepSleep WakeUp.
878 *
879 * Register|BitsName
880 * --------|--------
881 * AON_SLEEP_EVENT | AON_SLEEP_EVENT
882 *
883 * @param event This parameter can be a combination of the following values:
884 * @arg @ref LL_PWR_WKUP_EVENT_BLE
885 * @arg @ref LL_PWR_WKUP_EVENT_BLE
886 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
887 * @arg @ref LL_PWR_WKUP_EVENT_EXT
888 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
889 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
890 * @arg @ref LL_PWR_WKUP_EVENT_WDT
891 * @arg @ref LL_PWR_WKUP_EVENT_CLDR
892 * @arg @ref LL_PWR_WKUP_EVENT_AUSB
893 * @arg @ref LL_PWR_WKUP_EVENT_DUSB
894 * @arg @ref LL_PWR_WKUP_EVENT_CLDR_TICK
895 * @arg @ref LL_PWR_WKUP_EVENT_BLE_IRQ
896 * @retval None
897 */
898 __STATIC_FORCEINLINE void ll_pwr_clear_wakeup_event(uint32_t event)
899 {
900 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
901 }
902
903 /**
904 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
905 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
906 *
907 * Register|BitsName
908 * --------|--------
909 * COMM_CTRL | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT
910 *
911 * @retval State of bit (1 or 0).
912 */
913 __STATIC_FORCEINLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
914 {
915 return (READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT);
916 }
917
918 /**
919 * @brief Disable cache function
920 * @note The cache should be closed before chip go to deepsleep.
921 *
922 * Register|BitsName
923 * --------|--------
924 * CACHE.CTRL0 |EN
925 *
926 * @retval None
927 */
928 __STATIC_FORCEINLINE void ll_pwr_disable_cache_module(void)
929 {
930 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
931 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
932 }
933
934 /**
935 * @brief Set DCDC prepare timing.
936 *
937 * Register|BitsName
938 * --------|--------
939 * AON_PWR | DCDC
940 *
941 * @param value Timing setting value.
942 * @retval None
943 */
944 __STATIC_INLINE void ll_pwr_set_dcdc_prepare_timing(uint32_t value)
945 {
946 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DCDC, (value << AON_PWR_A_TIMING_CTRL0_DCDC_Pos));
947 }
948
949 /**
950 * @brief Set digtal LDO prepare timing.
951 *
952 * Register|BitsName
953 * --------|--------
954 * A_TIMING_CTRL0 | DIG_LDO
955 *
956 * @param value Timing setting value.
957 * @retval None
958 */
959 __STATIC_INLINE void ll_pwr_set_dig_ldo_prepare_timing(uint32_t value)
960 {
961 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DIG_LDO, (value << AON_PWR_A_TIMING_CTRL0_DIG_LDO_Pos));
962 }
963
964
965 /**
966 * @brief Set fast LDO prepare timing.
967 *
968 * Register|BitsName
969 * --------|--------
970 * A_TIMING_CTRL1 | FAST_LDO
971 *
972 * @param value Timing setting value.
973 * @retval None
974 */
975 __STATIC_INLINE void ll_pwr_set_fast_ldo_prepare_timing(uint32_t value)
976 {
977 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_FAST_LDO, (value << AON_PWR_A_TIMING_CTRL1_FAST_LDO_Pos));
978 }
979
980 /**
981 * @brief Set HF OSC prepare timing.
982 *
983 * Register|BitsName
984 * --------|--------
985 * A_TIMING_CTRL1 | HF_OSC
986 *
987 * @param value Timing setting value.
988 * @retval None
989 */
990 __STATIC_INLINE void ll_pwr_set_hf_osc_prepare_timing(uint32_t value)
991 {
992 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_HF_OSC, (value << AON_PWR_A_TIMING_CTRL1_HF_OSC_Pos));
993 }
994
995 /**
996 * @brief Set PLL lock prepare timing.
997 *
998 * Register|BitsName
999 * --------|--------
1000 * A_TIMING_CTRL2 | PLL_LOCK
1001 *
1002 * @param value Timing setting value.
1003 * @retval None
1004 */
1005 __STATIC_INLINE void ll_pwr_set_pll_lock_timing(uint32_t value)
1006 {
1007 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL_LOCK, (value << AON_PWR_A_TIMING_CTRL2_PLL_LOCK_Pos));
1008 }
1009
1010 /**
1011 * @brief Set PLL prepare timing.
1012 *
1013 * Register|BitsName
1014 * --------|--------
1015 * A_TIMING_CTRL2 | PLL
1016 *
1017 * @param value Timing setting value.
1018 * @retval None
1019 */
1020 __STATIC_INLINE void ll_pwr_set_pll_prepare_timing(uint32_t value)
1021 {
1022 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL, (value << AON_PWR_A_TIMING_CTRL2_PLL_Pos));
1023 }
1024
1025 /**
1026 * @brief Set power switch prepare timing.
1027 *
1028 * Register|BitsName
1029 * --------|--------
1030 * A_TIMING_CTRL3 | PWR_SWITCH
1031 *
1032 * @param value Timing setting value.
1033 * @retval None
1034 */
1035 __STATIC_INLINE void ll_pwr_set_pwr_switch_prepare_timing(uint32_t value)
1036 {
1037 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_PWR_SWITCH, (value << AON_PWR_A_TIMING_CTRL3_PWR_SWITCH_Pos));
1038 }
1039
1040 /**
1041 * @brief Set Set XO prepare timing.
1042 *
1043 * Register|BitsName
1044 * --------|--------
1045 * A_TIMING_CTRL3 | CTRL3_XO
1046 *
1047 * @param value Timing setting value.
1048 * @retval None
1049 */
1050 __STATIC_INLINE void ll_pwr_set_xo_prepare_timing(uint32_t value)
1051 {
1052 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_XO, (value << AON_PWR_A_TIMING_CTRL3_XO_Pos));
1053 }
1054
1055 /**
1056 * @brief Set Set XO Bias switch timing.
1057 *
1058 * Register|BitsName
1059 * --------|--------
1060 * A_TIMING_CTRL4 | REG_TIMING_XO_BIAS_SW_PREP
1061 *
1062 * @param value Timing setting value.
1063 * @retval None
1064 */
1065 __STATIC_INLINE void ll_pwr_set_xo_bias_switch_timing(uint32_t value)
1066 {
1067 MODIFY_REG(AON_PWR->A_TIMING_CTRL4, AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH, (value << AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH_Pos));
1068 }
1069
1070 /**
1071 * @brief Enable Fast LDO power mode.
1072 *
1073 * Register|BitsName
1074 * --------|--------
1075 * AON_START_CFG | MCU_PWR_TYPE
1076 *
1077 * @retval None
1078 */
1079 __STATIC_INLINE void ll_pwr_enable_fast_ldo_pwr_mode(void)
1080 {
1081 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_MCU_PWR_TYPE);
1082 }
1083
1084 /**
1085 * @brief Turn on DCDC after wakeup.
1086 *
1087 * Register|BitsName
1088 * --------|--------
1089 * AON_START_CFG | FAST_DCDC_OFF
1090 *
1091 * @retval None
1092 */
1093 __STATIC_INLINE void ll_pwr_turn_on_dcdc_after_wakeup(void)
1094 {
1095 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_DCDC_OFF);
1096 }
1097
1098 /**
1099 * @brief Keep turn off Fast LDO in regular boot.
1100 *
1101 * Register|BitsName
1102 * --------|--------
1103 * AON_START_CFG | FAST_LDO_OFF
1104 *
1105 * @retval None
1106 */
1107 __STATIC_INLINE void ll_pwr_turn_off_fast_ldo_in_regular_boot(void)
1108 {
1109 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_LDO_OFF);
1110 }
1111
1112 /**
1113 * @brief Turn off enable xo/pll in warm boot.
1114 *
1115 * Register|BitsName
1116 * --------|--------
1117 * AON_START_CFG | AON_PWR_AON_START_CFG_XO_EN_PWR | AON_PWR_AON_START_CFG_PLL_EN_PWR
1118 *
1119 * @retval None
1120 */
1121 __STATIC_INLINE void ll_pwr_turn_off_enable_xo_pll_after_dcdc_ready(void)
1122 {
1123 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1124 }
1125 /**
1126 * @brief Turn on enable xo/pll in srpg.
1127 *
1128 * Register|BitsName
1129 * --------|--------
1130 * AON_START_CFG | AON_PWR_AON_START_CFG_XO_EN_PWR | AON_PWR_AON_START_CFG_PLL_EN_PWR
1131 *
1132 * @retval None
1133 */
1134 __STATIC_INLINE void ll_pwr_turn_on_enable_xo_pll_after_dcdc_ready(void)
1135 {
1136 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1137 }
1138 /** @} */
1139
1140 /** @} */
1141
1142 #endif /* defined(AON) */
1143
1144 #ifdef __cplusplus
1145 }
1146 #endif
1147
1148 #endif /* __GR55xx_LL_PWR_H__ */
1149
1150 /** @} */
1151
1152 /** @} */
1153
1154 /** @} */