gr55xx_ll_msio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_MSIO) || defined(MCU_RET)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief MSIO pad Enumerations definition
75 */
76 typedef enum
77 {
78 MSIOA = 0x00, /**< MSIO_A_PAD */
79 } msio_pad_t;
80
81
82 /**
83 * @brief LL MSIO init Structure definition
84 */
85 typedef struct _ll_msio_init
86 {
87 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
88 This parameter can be any value of @ref MSIO_LL_EC_PIN */
89
90 uint32_t direction; /**< Specifies the direction for the selected pins.
91 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
92
93 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_direction(). */
94
95 uint32_t mode; /**< Specifies the operating mode for the selected pins.
96 This parameter can be a value of @ref MSIO_LL_EC_MODE.
97
98 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_mode(). */
99
100 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
101 This parameter can be a value of @ref MSIO_LL_EC_PULL.
102
103 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_pull().*/
104
105 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
106 This parameter can be a value of @ref MSIO_LL_EC_MUX.
107
108 GPIO HW MSIO_InitStructuration can be modified afterwards using unitary function
109 @ref ll_msio_set_pin_mux(). */
110
111 } ll_msio_init_t;
112
113 /** @} */
114
115 /** @} */
116
117 /**
118 * @defgroup MSIO_LL_MACRO Defines
119 * @{
120 */
121
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
124 * @{
125 */
126
127 /** @defgroup MSIO_LL_EC_PIN PIN
128 * @{
129 */
130 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
131 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
132 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
133 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
134 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
135 #define LL_MSIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
136 #define LL_MSIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
137 #define LL_MSIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
138 #define LL_MSIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
139
140 /** @} */
141
142 /** @defgroup MSIO_LL_EC_DIRECTION Direction
143 * @{
144 */
145 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
146 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
147 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
148 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
149 /** @} */
150
151 /** @defgroup MSIO_LL_EC_MODE Mode
152 * @{
153 */
154 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U) /**< Select analog mode */
155 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U) /**< Enable digital mode */
156 /** @} */
157
158 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
159 * @{
160 */
161 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
162 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
163 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
164 /** @} */
165
166 /** @defgroup MSIO_LL_EC_MUX Alternate Function
167 * @{
168 */
169 #define LL_MSIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
170 #define LL_MSIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
171 #define LL_MSIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
172 #define LL_MSIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
173 #define LL_MSIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
174 #define LL_MSIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
175 #define LL_MSIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
176 #define LL_MSIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
177 /** @} */
178
179 /** @} */
180
181 /* Exported macro ------------------------------------------------------------*/
182 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
183 * @{
184 */
185
186 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
187 * @{
188 */
189
190 /**
191 * @brief Write a value in MSIO register
192 * @param __instance__ MSIO instance
193 * @param __REG__ Register to be written
194 * @param __VALUE__ Value to be written in the register
195 * @retval None
196 */
197 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
198
199 /**
200 * @brief Read a value in MSIO register
201 * @param __instance__ MSIO instance
202 * @param __REG__ Register to be read
203 * @retval Register value
204 */
205 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
206
207 /** @} */
208
209 /** @} */
210
211 /* Private types -------------------------------------------------------------*/
212 /* Private variables ---------------------------------------------------------*/
213 /* Private constants ---------------------------------------------------------*/
214 /* Private macros ------------------------------------------------------------*/
215 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
216 * @{
217 */
218
219 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuration
220 * @{
221 */
222
223 /**
224 * @brief LL MSIO InitStrcut default configuration
225 */
226 #define LL_MSIO_DEFAULT_CONFIG \
227 { \
228 .pin = LL_MSIO_PIN_ALL, \
229 .direction = LL_MSIO_DIRECTION_INPUT, \
230 .mode = LL_MSIO_MODE_DIGITAL, \
231 .pull = LL_MSIO_PULL_DOWN, \
232 .mux = LL_MSIO_MUX_7, \
233 }
234 /** @} */
235
236 /** @} */
237
238 /** @} */
239
240 /* Exported functions --------------------------------------------------------*/
241 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
242 * @{
243 */
244
245 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
246 * @{
247 */
248
249 /**
250 * @brief Set several MSIO pins to input/output direction.
251 *
252 * Register|BitsName
253 * --------|--------
254 * MSIO_PAD_CFG_0 | OE_N
255 * MSIO_PAD_CFG_0 | IE_N
256 *
257 * @param MSIOx MSIO instance.
258 * @param pin_mask This parameter can be a combination of the following values:
259 * @arg @ref LL_MSIO_PIN_0
260 * @arg @ref LL_MSIO_PIN_1
261 * @arg @ref LL_MSIO_PIN_2
262 * @arg @ref LL_MSIO_PIN_3
263 * @arg @ref LL_MSIO_PIN_4
264 * @arg @ref LL_MSIO_PIN_5
265 * @arg @ref LL_MSIO_PIN_6
266 * @arg @ref LL_MSIO_PIN_7
267 * @arg @ref LL_MSIO_PIN_ALL
268 * @param direction This parameter can be one of the following values:
269 * @arg @ref LL_MSIO_DIRECTION_NONE
270 * @arg @ref LL_MSIO_DIRECTION_INPUT
271 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
272 * @arg @ref LL_MSIO_DIRECTION_INOUT
273 * @retval None
274 */
275 __STATIC_INLINE void ll_msio_set_pin_direction(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t direction)
276 {
277 uint32_t oe_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_OUT_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT_EN;
278 uint32_t ie_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG1_IN_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_IN_EN;
279
280 if (direction != LL_MSIO_DIRECTION_NONE)
281 {
282 if (direction != LL_MSIO_DIRECTION_INOUT)
283 {
284 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask, (direction == LL_MSIO_DIRECTION_OUTPUT) ? 0x00 : oe_mask);
285 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask, (direction == LL_MSIO_DIRECTION_INPUT) ? 0x00 : ie_mask);
286 }
287 else
288 {
289 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask);
290 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask);
291 }
292 }
293 else
294 {
295 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask);
296 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask);
297 }
298 }
299
300 /**
301 * @brief Return gpio direction for a MSIO pin.
302 * @note I/O direction can be Input direction, General purpose output.
303 * @note Warning: only one pin can be passed as parameter.
304 *
305 * Register|BitsName
306 * --------|--------
307 * MSIO_PAD_CFG_0 | OE_N
308 * MSIO_PAD_CFG_0 | IE_N
309 *
310 * @param MSIOx MSIO instance.
311 * @param pin This parameter can be one of the following values:
312 * @arg @ref LL_MSIO_PIN_0
313 * @arg @ref LL_MSIO_PIN_1
314 * @arg @ref LL_MSIO_PIN_2
315 * @arg @ref LL_MSIO_PIN_3
316 * @arg @ref LL_MSIO_PIN_4
317 * @arg @ref LL_MSIO_PIN_5
318 * @arg @ref LL_MSIO_PIN_6
319 * @arg @ref LL_MSIO_PIN_7
320 * @retval Returned value can be one of the following values:
321 * @arg @ref LL_MSIO_DIRECTION_NONE
322 * @arg @ref LL_MSIO_DIRECTION_INPUT
323 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
324 * @arg @ref LL_MSIO_DIRECTION_INOUT
325 */
326 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(msio_pad_t MSIOx, uint32_t pin)
327 {
328 uint32_t oe_mask = (pin << AON_MSIO_MSIO_A_PAD_CFG0_OUT_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT_EN;
329 uint32_t ie_mask = (pin << AON_MSIO_MSIO_A_PAD_CFG1_IN_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_IN_EN;
330 uint32_t mask = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask);
331 mask |= READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask);
332 if (mask == (ie_mask | oe_mask))
333 return LL_MSIO_DIRECTION_NONE;
334 else
335 {
336 if (mask == 0)
337 return LL_MSIO_DIRECTION_INOUT;
338 else
339 return ((mask == ie_mask) ? LL_MSIO_DIRECTION_OUTPUT : LL_MSIO_DIRECTION_INPUT);
340 }
341 }
342
343 /**
344 * @brief Set several MSIO pins to analog/digital mode.
345 *
346 * Register|BitsName
347 * --------|--------
348 * MSIO_PAD_CFG_1 | AE_N
349 *
350 * @param MSIOx MSIO instance.
351 * @param pin_mask This parameter can be a combination of the following values:
352 * @arg @ref LL_MSIO_PIN_0
353 * @arg @ref LL_MSIO_PIN_1
354 * @arg @ref LL_MSIO_PIN_2
355 * @arg @ref LL_MSIO_PIN_3
356 * @arg @ref LL_MSIO_PIN_4
357 * @arg @ref LL_MSIO_PIN_5
358 * @arg @ref LL_MSIO_PIN_6
359 * @arg @ref LL_MSIO_PIN_7
360 * @arg @ref LL_MSIO_PIN_ALL
361 * @param mode This parameter can be one of the following values:
362 * @arg @ref LL_MSIO_MODE_ANALOG
363 * @arg @ref LL_MSIO_MODE_DIGITAL
364 * @retval None
365 */
366 __STATIC_INLINE void ll_msio_set_pin_mode(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t mode)
367 {
368 uint32_t ae_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG1_A_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_A_EN;
369 uint32_t ae_n = (mode == LL_MSIO_MODE_ANALOG) ? 0U : ae_mask;
370 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, ae_mask, ae_n);
371 }
372
373 /**
374 * @brief Return gpio mode for a MSIO pin.
375 * @note I/O mode can be analog or digital.
376 * @note Warning: only one pin can be passed as parameter.
377 *
378 * Register|BitsName
379 * --------|--------
380 * MSIO_PAD_CFG_1 | AE_N
381 *
382 * @param MSIOx MSIO instance.
383 * @param pin This parameter can be one of the following values:
384 * @arg @ref LL_MSIO_PIN_0
385 * @arg @ref LL_MSIO_PIN_1
386 * @arg @ref LL_MSIO_PIN_2
387 * @arg @ref LL_MSIO_PIN_3
388 * @arg @ref LL_MSIO_PIN_4
389 * @arg @ref LL_MSIO_PIN_5
390 * @arg @ref LL_MSIO_PIN_6
391 * @arg @ref LL_MSIO_PIN_7
392 * @retval Returned value can be one of the following values:
393 * @arg @ref LL_MSIO_MODE_ANALOG
394 * @arg @ref LL_MSIO_MODE_DIGITAL
395 */
396 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(msio_pad_t MSIOx, uint32_t pin)
397 {
398 uint32_t ae_mask = (pin << AON_MSIO_MSIO_A_PAD_CFG1_A_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_A_EN;
399 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ae_mask) == ae_mask) ? LL_MSIO_MODE_DIGITAL : LL_MSIO_MODE_ANALOG);
400 }
401
402 /**
403 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
404 *
405 * Register|BitsName
406 * --------|--------
407 * MSIO_PAD_CFG_0 | RE_N
408 * MSIO_PAD_CFG_1 | RTYPE
409 *
410 * @param MSIOx MSIO instance.
411 * @param pin_mask This parameter can be a combination of the following values:
412 * @arg @ref LL_MSIO_PIN_0
413 * @arg @ref LL_MSIO_PIN_1
414 * @arg @ref LL_MSIO_PIN_2
415 * @arg @ref LL_MSIO_PIN_3
416 * @arg @ref LL_MSIO_PIN_4
417 * @arg @ref LL_MSIO_PIN_5
418 * @arg @ref LL_MSIO_PIN_6
419 * @arg @ref LL_MSIO_PIN_7
420 * @arg @ref LL_MSIO_PIN_ALL
421 * @param pull This parameter can be one of the following values:
422 * @arg @ref LL_MSIO_PULL_NO
423 * @arg @ref LL_MSIO_PULL_UP
424 * @arg @ref LL_MSIO_PULL_DOWN
425 * @retval None
426 */
427 __STATIC_INLINE void ll_msio_set_pin_pull(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t pull)
428 {
429 if (pull != LL_MSIO_PULL_NO)
430 {
431 uint32_t rtype_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG1_R_TYPE_POS) & AON_MSIO_MSIO_A_PAD_CFG1_R_TYPE;
432 uint32_t rtype = (pull != LL_MSIO_PULL_UP) ? 0U : rtype_mask;
433 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, rtype_mask, rtype);
434 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG1,
435 (pin_mask << AON_MSIO_MSIO_A_PAD_CFG1_R_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_R_EN);
436 }
437 else
438 {
439 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG1,
440 (pin_mask << AON_MSIO_MSIO_A_PAD_CFG1_R_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_R_EN);
441 }
442 }
443
444 /**
445 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
446 * @note Warning: only one pin can be passed as parameter.
447 *
448 * Register|BitsName
449 * --------|--------
450 * MSIO_PAD_CFG_0 | RE_N
451 * MSIO_PAD_CFG_1 | RTYPE
452 *
453 * @param MSIOx MSIO instance.
454 * @param pin This parameter can be one of the following values:
455 * @arg @ref LL_MSIO_PIN_0
456 * @arg @ref LL_MSIO_PIN_1
457 * @arg @ref LL_MSIO_PIN_2
458 * @arg @ref LL_MSIO_PIN_3
459 * @arg @ref LL_MSIO_PIN_4
460 * @arg @ref LL_MSIO_PIN_5
461 * @arg @ref LL_MSIO_PIN_6
462 * @arg @ref LL_MSIO_PIN_7
463 * @retval Returned value can be one of the following values:
464 * @arg @ref LL_MSIO_PULL_NO
465 * @arg @ref LL_MSIO_PULL_UP
466 * @arg @ref LL_MSIO_PULL_DOWN
467 */
468 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(msio_pad_t MSIOx, uint32_t pin)
469 {
470 if (READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1,
471 (pin << AON_MSIO_MSIO_A_PAD_CFG1_R_EN_POS) & AON_MSIO_MSIO_A_PAD_CFG1_R_EN))
472 {
473 return LL_MSIO_PULL_NO;
474 }
475 else
476 {
477 uint32_t rtype_mask = (pin << AON_MSIO_MSIO_A_PAD_CFG1_R_TYPE_POS) & AON_MSIO_MSIO_A_PAD_CFG1_R_TYPE;
478 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, rtype_mask) != RESET) ? LL_MSIO_PULL_UP : LL_MSIO_PULL_DOWN);
479 }
480 }
481
482 /**
483 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
484 * @note Possible values are from AF0 to AF7 depending on target.
485 * @note Warning: only one pin can be passed as parameter.
486 *
487 * Register|BitsName
488 * --------|--------
489 * MSIO_PAD_MUX_CTL | CTL_00_04
490 * MSIO_PAD_CFG_1 | MCU_OVR
491 *
492 * @param MSIOx MSIO instance.
493 * @param pin This parameter can be one of the following values:
494 * @arg @ref LL_MSIO_PIN_0
495 * @arg @ref LL_MSIO_PIN_1
496 * @arg @ref LL_MSIO_PIN_2
497 * @arg @ref LL_MSIO_PIN_3
498 * @arg @ref LL_MSIO_PIN_4
499 * @arg @ref LL_MSIO_PIN_5
500 * @arg @ref LL_MSIO_PIN_6
501 * @arg @ref LL_MSIO_PIN_7
502 * @param mux This parameter can be one of the following values:
503 * @arg @ref LL_MSIO_MUX_0
504 * @arg @ref LL_MSIO_MUX_1
505 * @arg @ref LL_MSIO_MUX_2
506 * @arg @ref LL_MSIO_MUX_3
507 * @arg @ref LL_MSIO_MUX_4
508 * @arg @ref LL_MSIO_MUX_5
509 * @arg @ref LL_MSIO_MUX_6
510 * @arg @ref LL_MSIO_MUX_7
511 * @retval None
512 */
513 __STATIC_INLINE void ll_msio_set_pin_mux(msio_pad_t MSIOx, uint32_t pin, uint32_t mux)
514 {
515 uint32_t pos = POSITION_VAL(pin) << 2;
516 if (LL_MSIO_MUX_7 == mux)
517 {
518 CLEAR_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MSIO_MCU_OVR_MSIO_OVR_POS);
519 }
520 else
521 {
522 MODIFY_REG(MCU_RET->MSIO_A_PAD_MUX_CTL, 0xF << pos, mux << pos);
523 SET_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MSIO_MCU_OVR_MSIO_OVR_POS);
524 }
525 }
526
527 /**
528 * @brief Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
529 *
530 * Register|BitsName
531 * --------|--------
532 * MSIO_PAD_MUX_CTL | CTL_00_04
533 * MSIO_PAD_CFG_1 | MCU_OVR
534 *
535 * @param MSIOx MSIO instance.
536 * @param pin This parameter can be one of the following values:
537 * @arg @ref LL_MSIO_PIN_0
538 * @arg @ref LL_MSIO_PIN_1
539 * @arg @ref LL_MSIO_PIN_2
540 * @arg @ref LL_MSIO_PIN_3
541 * @arg @ref LL_MSIO_PIN_4
542 * @arg @ref LL_MSIO_PIN_5
543 * @arg @ref LL_MSIO_PIN_6
544 * @arg @ref LL_MSIO_PIN_7
545 * @retval Returned value can be one of the following values:
546 * @arg @ref LL_MSIO_MUX_0
547 * @arg @ref LL_MSIO_MUX_1
548 * @arg @ref LL_MSIO_MUX_2
549 * @arg @ref LL_MSIO_MUX_3
550 * @arg @ref LL_MSIO_MUX_4
551 * @arg @ref LL_MSIO_MUX_5
552 * @arg @ref LL_MSIO_MUX_6
553 * @arg @ref LL_MSIO_MUX_7
554 */
555 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(msio_pad_t MSIOx, uint32_t pin)
556 {
557 if (READ_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MSIO_MCU_OVR_MSIO_OVR_POS))
558 {
559 uint32_t pos = POSITION_VAL(pin) << 2;
560 return (READ_BITS(MCU_RET->MSIO_A_PAD_MUX_CTL, 0xF << pos) >> pos);
561 }
562 else
563 {
564 return LL_MSIO_MUX_7;
565 }
566 }
567
568 /** @} */
569
570 /** @defgroup MSIO_LL_EF_Data_Access Data Access
571 * @{
572 */
573
574 /**
575 * @brief Return full input data register value of MSIO.
576 *
577 * Register|BitsName
578 * --------|--------
579 * MSIO_REG0 | MSIO_C
580 *
581 * @param MSIOx MSIO instance.
582 * @retval Input data register value of port
583 */
584 __STATIC_INLINE uint32_t ll_msio_read_input_port(msio_pad_t MSIOx)
585 {
586 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_MSIO_A_PAD_CFG0_IN) >> AON_MSIO_MSIO_A_PAD_CFG0_IN_POS);
587 }
588
589 /**
590 * @brief Return if input data level of several MSIO pins is high or low.
591 *
592 * Register|BitsName
593 * --------|--------
594 * MSIO_PAD_CFG_0 | IN
595 *
596 * @param MSIOx MSIO instance.
597 * @param pin_mask This parameter can be a combination of the following values:
598 * @arg @ref LL_MSIO_PIN_0
599 * @arg @ref LL_MSIO_PIN_1
600 * @arg @ref LL_MSIO_PIN_2
601 * @arg @ref LL_MSIO_PIN_3
602 * @arg @ref LL_MSIO_PIN_4
603 * @arg @ref LL_MSIO_PIN_5
604 * @arg @ref LL_MSIO_PIN_6
605 * @arg @ref LL_MSIO_PIN_7
606 * @arg @ref LL_MSIO_PIN_ALL
607 * @retval State of bit (1 or 0).
608 */
609 __STATIC_INLINE uint32_t ll_msio_read_input_pin(msio_pad_t MSIOx, uint32_t pin_mask)
610 {
611 pin_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_IN_POS) & AON_MSIO_MSIO_A_PAD_CFG0_IN;
612 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
613 }
614
615 /**
616 * @brief Return if input data level of several MSIO pins is high or low.
617 *
618 * Register|BitsName
619 * --------|--------
620 * MSIO_PAD_CFG_0 | OUT
621 *
622 * @param MSIOx MSIO instance.
623 * @param pin_mask This parameter can be a combination of the following values:
624 * @arg @ref LL_MSIO_PIN_0
625 * @arg @ref LL_MSIO_PIN_1
626 * @arg @ref LL_MSIO_PIN_2
627 * @arg @ref LL_MSIO_PIN_3
628 * @arg @ref LL_MSIO_PIN_4
629 * @arg @ref LL_MSIO_PIN_5
630 * @arg @ref LL_MSIO_PIN_6
631 * @arg @ref LL_MSIO_PIN_7
632 * @arg @ref LL_MSIO_PIN_ALL
633 * @retval State of bit (1 or 0).
634 */
635 __STATIC_INLINE uint32_t ll_msio_read_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
636 {
637 pin_mask = (pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT;
638 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
639 }
640
641 /**
642 * @brief Write output data register of MSIO.
643 *
644 * Register|BitsName
645 * --------|--------
646 * MSIO_PAD_CFG_0 | IN
647 *
648 * @param MSIOx MSIO instance.
649 * @param port_value Level value for each pin of the port
650 * @retval None
651 */
652 __STATIC_INLINE void ll_msio_write_output_port(msio_pad_t MSIOx, uint32_t port_value)
653 {
654 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_MSIO_A_PAD_CFG0_OUT, (port_value << AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT);
655 }
656 /**
657 * @brief Return full output data register value of MSIO.
658 *
659 * Register|BitsName
660 * --------|--------
661 * MSIO_PAD_CFG_0 | IN
662 *
663 * @param MSIOx MSIO instance.
664 * @retval Output data register value of port
665 */
666 __STATIC_INLINE uint32_t ll_msio_read_output_port(msio_pad_t MSIOx)
667 {
668 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_MSIO_A_PAD_CFG0_OUT) >> AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS);
669 }
670
671 /**
672 * @brief Set specified MSIO pins to high level
673 *
674 * Register|BitsName
675 * --------|--------
676 * MSIO_PAD_CFG_0 | IN
677 *
678 * @param MSIOx MSIO instance.
679 * @param pin_mask This parameter can be a combination of the following values:
680 * @arg @ref LL_MSIO_PIN_0
681 * @arg @ref LL_MSIO_PIN_1
682 * @arg @ref LL_MSIO_PIN_2
683 * @arg @ref LL_MSIO_PIN_3
684 * @arg @ref LL_MSIO_PIN_4
685 * @arg @ref LL_MSIO_PIN_5
686 * @arg @ref LL_MSIO_PIN_6
687 * @arg @ref LL_MSIO_PIN_7
688 * @arg @ref LL_MSIO_PIN_ALL
689 * @retval None
690 */
691 __STATIC_INLINE void ll_msio_set_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
692 {
693 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT);
694 }
695
696 /**
697 * @brief Set specified MSIO pins to low level.
698 *
699 * Register|BitsName
700 * --------|--------
701 * MSIO_PAD_CFG_0 | IN
702 *
703 * @param MSIOx MSIO instance.
704 * @param pin_mask This parameter can be a combination of the following values:
705 * @arg @ref LL_MSIO_PIN_0
706 * @arg @ref LL_MSIO_PIN_1
707 * @arg @ref LL_MSIO_PIN_2
708 * @arg @ref LL_MSIO_PIN_3
709 * @arg @ref LL_MSIO_PIN_4
710 * @arg @ref LL_MSIO_PIN_5
711 * @arg @ref LL_MSIO_PIN_6
712 * @arg @ref LL_MSIO_PIN_7
713 * @arg @ref LL_MSIO_PIN_ALL
714 * @retval None
715 */
716 __STATIC_INLINE void ll_msio_reset_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
717 {
718 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT);
719 }
720
721 /**
722 * @brief Toggle data value of specified MSIO pins.
723 *
724 * Register|BitsName
725 * --------|--------
726 * MSIO_PAD_CFG_0 | IN
727 *
728 * @param MSIOx MSIO instance.
729 * @param pin_mask This parameter can be a combination of the following values:
730 * @arg @ref LL_MSIO_PIN_0
731 * @arg @ref LL_MSIO_PIN_1
732 * @arg @ref LL_MSIO_PIN_2
733 * @arg @ref LL_MSIO_PIN_3
734 * @arg @ref LL_MSIO_PIN_4
735 * @arg @ref LL_MSIO_PIN_5
736 * @arg @ref LL_MSIO_PIN_6
737 * @arg @ref LL_MSIO_PIN_7
738 * @arg @ref LL_MSIO_PIN_ALL
739 * @retval None
740 */
741 __STATIC_INLINE void ll_msio_toggle_pin(msio_pad_t MSIOx, uint32_t pin_mask)
742 {
743 WRITE_REG(AON_MSIO->MSIO_A_PAD_CFG0, (READ_REG(AON_MSIO->MSIO_A_PAD_CFG0) ^ ((pin_mask << AON_MSIO_MSIO_A_PAD_CFG0_OUT_POS) & AON_MSIO_MSIO_A_PAD_CFG0_OUT)));
744 }
745
746 /** @} */
747
748 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
749 * @{
750 */
751 /**
752 * @brief Initialize MSIO registers according to the specified.
753 * parameters in p_msio_init.
754 *
755 * @param MSIOx MSIO instance.
756 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
757 * information for the specified MSIO peripheral.
758 * @retval An error_status_t enumeration value:
759 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
760 * - ERROR: Problem occurred during MSIO Registers initialization
761 */
762 error_status_t ll_msio_init(msio_pad_t MSIOx,ll_msio_init_t *p_msio_init);
763
764 /** @} */
765
766 /** @} */
767
768 #endif /* defined(AON_MSIO) || defined(MCU_RET) */
769
770 #ifdef __cplusplus
771 }
772 #endif
773
774 #endif /* __GR55XX_LL_MSIO_H__ */
775
776 /** @} */
777
778 /** @} */
779
780 /** @} */