gr55xx_ll_cgc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_cgc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CGC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_CGC CGC
47 * @brief CGC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(MCU_SUB) || defined(MCU_RET)
63 /**
64 * @defgroup LL_CGC_MACRO Defines
65 * @{
66 */
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup LL_CGC_Exported_Constants CGC Exported Constants
69 * @{
70 */
71 /** @defgroup LL_CGC_EC_WFI_CLK0 Block0 Clock During WFI
72 * @{
73 */
74 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK /**< Hclk for all security blocks */
75 #define LL_CGC_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK /**< Hclk for sim card interface */
76 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK /**< Hclk for hopping table */
77 #define LL_CGC_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK /**< Hclk for PWM */
78 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK /**< Hclk for ROM */
79 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK /**< Hclk for sense ADC */
80 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK /**< Hclk for GPIOs */
81 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
82 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK /**< Hclk for APB subsystem */
83 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK /**< Hclk for serial blocks */
84 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x000007FFU) /**< All clock group 0 */
85
86 /** @} */
87
88 /** @defgroup LL_CGC_EC_WFI_CLK1 Block1 Clock During WFI
89 * @{
90 */
91 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
92 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK /**< Hclk for cache top */
93 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK /**< Hclk for SRAMs */
94
95 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U) /**< All clock group 1 */
96 /** @} */
97
98 /** @defgroup LL_CGC_EC_WFI_CLK2 Block2 Clock During WFI
99 * @{
100 */
101 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK /**< Div4 clk for security blocks */
102 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
103
104 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U) /**< All clock group 2 */
105 /** @} */
106
107
108 /** @defgroup LL_CGC_EC_FRC_CLK0 Block0 Clock During FRC
109 * @{
110 */
111 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK /**< Hclk for all security blocks */
112 #define LL_CGC_FRC_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK /**< Hclk for sim card interface */
113 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK /**< Hclk for hopping table */
114 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK /**< Hclk for ROM */
115 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK /**< Hclk for sense ADC */
116 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK /**< Hclk for GPIOs */
117 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
118 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK /**< Hclk for APB subsystem */
119 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK /**< Hclk for serial blocks */
120 #define LL_CGC_FRC_USB_HCLK MCU_SUB_FORCE_USB_HCLK /**< Hclk for USB */
121 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x0000177FU) /**< All clock group 0 */
122 /** @} */
123
124 /** @defgroup LL_CGC_EC_FRC_CLK1 Block1 Clock During FRC
125 * @{
126 */
127 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
128 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK /**< Hclk for cache top */
129 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK /**< Hclk for SRAMs */
130
131 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U) /**< All clock group 1 */
132 /** @} */
133
134 /** @defgroup LL_CGC_EC_FRC_CLK2 Block2 Clock During FRC
135 * @{
136 */
137 #define LL_CGC_FRC_UART0_PCLK MCU_SUB_FORCE_UART0_PCLK /**< Pclk for uart0 */
138 #define LL_CGC_FRC_UART1_PCLK MCU_SUB_FORCE_UART1_PCLK /**< Pclk for uart1 */
139 #define LL_CGC_FRC_UART2_PCLK MCU_SUB_FORCE_UART2_PCLK /**< Pclk for uart2 */
140 #define LL_CGC_FRC_UART3_PCLK MCU_SUB_FORCE_UART3_PCLK /**< Pclk for uart3 */
141 #define LL_CGC_FRC_UART4_PCLK MCU_SUB_FORCE_UART4_PCLK /**< Pclk for uart4 */
142 #define LL_CGC_FRC_UART5_PCLK MCU_SUB_FORCE_UART5_PCLK /**< Pclk for uart5 */
143 #define LL_CGC_FRC_I2C0_PCLK MCU_SUB_FORCE_I2C0_PCLK /**< Hclk for i2c0 */
144 #define LL_CGC_FRC_I2C1_PCLK MCU_SUB_FORCE_I2C1_PCLK /**< Hclk for i2c1 */
145 #define LL_CGC_FRC_I2C2_PCLK MCU_SUB_FORCE_I2C2_PCLK /**< Hclk for i2c2 */
146 #define LL_CGC_FRC_I2C3_PCLK MCU_SUB_FORCE_I2C3_PCLK /**< Hclk for i2c3 */
147 #define LL_CGC_FRC_I2C4_PCLK MCU_SUB_FORCE_I2C4_PCLK /**< Hclk for i2c4 */
148 #define LL_CGC_FRC_I2C5_PCLK MCU_SUB_FORCE_I2C5_PCLK /**< Hclk for i2c5 */
149 #define LL_CGC_FRC_QSPI0_PCLK MCU_SUB_FORCE_QSPI0_PCLK /**< Hclk for qspi0 */
150 #define LL_CGC_FRC_QSPI1_PCLK MCU_SUB_FORCE_QSPI1_PCLK /**< Hclk for qspi1 */
151 #define LL_CGC_FRC_QSPI2_PCLK MCU_SUB_FORCE_QSPI2_PCLK /**< Hclk for qspi2 */
152 #define LL_CGC_FRC_SPI_M_PCLK MCU_SUB_FORCE_SPI_M_PCLK /**< Hclk for spim */
153 #define LL_CGC_FRC_SPI_S_PCLK MCU_SUB_FORCE_SPI_S_PCLK /**< Hclk for spis */
154 #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_PCLK /**< Hclk for i2s */
155 #define LL_CGC_FRC_I2S_S_PCLK MCU_SUB_FORCE_I2S_S_PCLK /**< Hclk for i2ss */
156 #define LL_CGC_FRC_DSPI_PCLK MCU_SUB_FORCE_DSPI_PCLK /**< Hclk for dspi */
157 #define LL_CGC_FRC_PDM_PCLK MCU_SUB_FORCE_PDM_PCLK /**< Hclk for pdm */
158 #define LL_CGC_FRC_PWM_0_PCLK MCU_SUB_FORCE_PWM_0_PCLK /**< Pclk for PWM0 */
159 #define LL_CGC_FRC_PWM_1_PCLK MCU_SUB_FORCE_PWM_1_PCLK /**< Pclk for PWM1 */
160 #define LL_CGC_FRC_VTTBL_PCLK MCU_SUB_FORCE_VTTBL_PCLK /**< Pclk for VTTBL */
161 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK /**< Div4 clk for security blocksi */
162 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
163
164 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x705E0FFFUL) /**< Hclk for serial blocks */
165 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0xFF7FCFFFUL) /**< All clock group 2 */
166 /** @} */
167
168 /** @defgroup LL_CGC_PERIPH_CG_LP_EN Low Power Feature
169 * @{
170 */
171 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN /**< Enable AHB2APB ASYNC low-power feature */
172 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN /**< Enable AHB2APB SYNC low-power feature */
173 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_EN MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN /**< Enable qspim low-power feature */
174 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN /**< Enable AHB bus low-power feature */
175 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN /**< Enable i2c sclk low-power feature */
176 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN /**< Enable spis sclk low-power feature */
177 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN /**< Enable spim sclk low-power feature */
178 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN /**< Enable i2s master low-power feature */
179 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN /**< Enable uart pclk low-power feature */
180 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN /**< Enable uart sclk low-power feature */
181
182 #define LL_CGC_MCU_PERIPH_CG_LP ((uint32_t)0x00000F3FUL) /**< All Low Power Feature */
183 /** @} */
184
185 /** @defgroup LL_CGC_SUBSYS_PERI_CLK_SLP_OFF Peripherals Off During WFI/WFE
186 * @brief Turn the peripherals off during WFI/WFE
187 * @{
188 */
189 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 /**< Turn the uart0 off during WFI/WFE */
190 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 /**< Turn the uart1 off during WFI/WFE */
191 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 /**< Turn the uart2 off during WFI/WFE */
192 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 /**< Turn the uart3 off during WFI/WFE */
193 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_4_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART4 /**< Turn the uart4 off during WFI/WFE */
194 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_5_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART5 /**< Turn the uart5 off during WFI/WFE */
195 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM /**< Turn the i2s_m off during WFI/WFE */
196 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS /**< Turn the i2s_s off during WFI/WFE */
197 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM /**< Turn the spi_m off during WFI/WFE */
198 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS /**< Turn the spi_s off during WFI/WFE */
199 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 /**< Turn the pwm0 off during WFI/WFE */
200 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 /**< Turn the pwm1 off during WFI/WFE */
201 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 /**< Turn the qspim0 off during WFI/WFE */
202 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 /**< Turn the qspim1 off during WFI/WFE */
203 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 /**< Turn the qspim2 off during WFI/WFE */
204 #define LL_CGC_MCU_PERIPH_CG_LP_EN_DSPI_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI /**< Turn the dspi off during WFI/WFE */
205 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PDM_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PDM /**< Turn the pdm off during WFI/WFE */
206 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 /**< Turn the i2c0 off during WFI/WFE */
207 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 /**< Turn the i2c1 off during WFI/WFE */
208 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 /**< Turn the i2c0 off during WFI/WFE */
209 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 /**< Turn the i2c1 off during WFI/WFE */
210 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_4_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4 /**< Turn the i2c0 off during WFI/WFE */
211 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5 /**< Turn the i2c1 off during WFI/WFE */
212
213 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_OFF ((uint32_t)0x01FC3FFFUL) /**< Serial blocks */
214 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL ((uint32_t)0x03FFFF3FUL) /**< Serial blocks */
215
216 /** @} */
217
218 /** @defgroup LL_CGC_SUBSYS_SECU_CLK_CTRL Individual Block's Clock Control
219 * @brief Individual block's clock control inside security system
220 * @{
221 */
222 #define LL_CGC_MCU_FRC_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF /**< Force individual aes's clock control */
223 #define LL_CGC_MCU_SLP_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF /**< Individual aes's clock control */
224 #define LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF /**< Force individual hmac's clock control */
225 #define LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF /**< Individual hmac's clock control */
226 #define LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF /**< Force individual pkc's clock control */
227 #define LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF /**< Individual pkc's clock control */
228 #define LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF /**< Force individual present's clock control */
229 #define LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF /**< Individual present's clock control */
230 #define LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF /**< Force individual ramkey's clock control */
231 #define LL_CGC_MCU_SLP_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF /**< Individual ramkey's clock control */
232 #define LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF /**< Force individual rng's clock control */
233 #define LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF /**< Individual rng's clock control */
234 #define LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF /**< Force individual efuse's clock control */
235 #define LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF /**< Individual efuse's clock control */
236
237 #define LL_CGC_MCU_SECU_FRC_OFF_HCLK ((uint32_t)0x00001555U) /**< Hclk for security clock */
238 #define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK ((uint32_t)0x00002AAAU) /**< Hclk for security clock WFI/WFE */
239
240 #define LL_CGC_MCU_SECU_FRC_OFF_ALL (LL_CGC_MCU_SECU_FRC_OFF_HCLK |\
241 LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK) /**< Hclk for security clock */
242
243 #define LL_CGC_MCU_MISC_CLK_DEFAULT ((uint32_t)0x0000003BU) /**< Hclk for msic default clock */
244
245 #define LL_CGC_MCU_MISC_CLK ((uint32_t)0x0000003FU) /**< Hclk for msic all clock */
246
247 #define LL_CGC_MCU_MISC_DMA_CLK ((uint32_t)0x00000038U) /**< Hclk for msic dma clock */
248
249 /** @} */
250
251 /** @defgroup LL_CGC_SUBSYS_DEFAULT_CLK Default System Clock Specify
252 * @brief Specify the default system clock when the system is initialized
253 * @{
254 */
255 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0 (LL_CGC_WFI_SECU_HCLK |\
256 LL_CGC_WFI_SIM_HCLK |\
257 LL_CGC_WFI_PWM_HCLK |\
258 LL_CGC_WFI_SNSADC_HCLK |\
259 LL_CGC_WFI_GPIO_HCLK |\
260 LL_CGC_WFI_BLE_BRG_HCLK |\
261 LL_CGC_WFI_SERIAL_HCLK) /**< Hclk0 for the system default clock WFI/WFE */
262
263 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1 (LL_CGC_WFI_AON_MCUSUB_HCLK |\
264 LL_CGC_WFI_XF_XQSPI_HCLK |\
265 LL_CGC_WFI_SRAM_HCLK) /**< Hclk1 for the system default clock WFI/WFE */
266
267
268 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK (LL_CGC_FRC_SECU_HCLK |\
269 LL_CGC_FRC_SIM_HCLK |\
270 LL_CGC_FRC_SNSADC_HCLK |\
271 LL_CGC_FRC_SERIAL_HCLK) /**< Hclk for the system default clock */
272
273 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK1 (MCU_SUB_FORCE_SECU_DIV4_PCLK) /**< Hclk for the system default clock */
274
275
276 #define LL_CGC_MCU_PERIPH_CG_DEFAULT (LL_CGC_FRC_UART0_PCLK |\
277 LL_CGC_FRC_UART1_PCLK |\
278 LL_CGC_FRC_UART2_PCLK |\
279 LL_CGC_FRC_UART3_PCLK |\
280 LL_CGC_FRC_UART4_PCLK |\
281 LL_CGC_FRC_UART5_PCLK |\
282 LL_CGC_FRC_I2C0_PCLK |\
283 LL_CGC_FRC_I2C1_PCLK |\
284 LL_CGC_FRC_I2C2_PCLK |\
285 LL_CGC_FRC_I2C3_PCLK |\
286 LL_CGC_FRC_I2C4_PCLK |\
287 LL_CGC_FRC_I2C5_PCLK |\
288 LL_CGC_FRC_QSPI0_PCLK |\
289 LL_CGC_FRC_QSPI1_PCLK |\
290 LL_CGC_FRC_QSPI2_PCLK |\
291 LL_CGC_FRC_SPI_M_PCLK |\
292 LL_CGC_FRC_SPI_S_PCLK |\
293 LL_CGC_FRC_I2S_HCLK |\
294 LL_CGC_FRC_I2S_S_PCLK |\
295 LL_CGC_FRC_DSPI_PCLK |\
296 LL_CGC_FRC_PDM_PCLK |\
297 LL_CGC_FRC_PWM_0_PCLK |\
298 LL_CGC_FRC_PWM_1_PCLK) /**< pclk for the system default periph clock */
299
300 #define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT (MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
301 MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
302 MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 |\
303 MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 |\
304 MCU_SUB_PERIPH_CLK_SLP_OFF_UART4 |\
305 MCU_SUB_PERIPH_CLK_SLP_OFF_UART5 |\
306 MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM |\
307 MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS |\
308 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
309 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
310 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
311 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
312 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 |\
313 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 |\
314 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 |\
315 MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI |\
316 MCU_SUB_PERIPH_CLK_SLP_OFF_PDM |\
317 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
318 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 |\
319 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 |\
320 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 |\
321 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4 |\
322 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5) /**< pclk for the system default periph wfi clock */
323
324 #define CGC_CLOCK_ENABLE (1) /**< Bit segment address enable */
325 #define CGC_CLOCK_DISABLE (0) /**< Bit segment address disable */
326
327 #if defined(BIT_BAND_SUPPORT)
328
329 #define BIT_SEGMENT_VALUE BIT_ADDR /**< Bit segment address value manipulation */
330
331 #else
332
333 #define BIT_BAND(addr, bitnum) (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2)) /**< Bit segment address calculation */
334 #define MEMORY_ADDR(addr) (*((volatile uint32_t *)(addr))) /**< Bit segment address type conversion */
335 #define BIT_SEGMENT_VALUE(addr, bitnum) MEMORY_ADDR(BIT_BAND(addr, bitnum)) /**< Bit segment address value manipulation */
336
337 #endif
338
339 /** @} */
340
341 /** @} */
342
343 /** @} */
344
345 /* Private types -------------------------------------------------------------*/
346 /* Private variables ---------------------------------------------------------*/
347 /* Private constants ---------------------------------------------------------*/
348 /* Private macros ------------------------------------------------------------*/
349 /* Exported functions --------------------------------------------------------*/
350 /** @defgroup LL_CGC_DRIVER_FUNCTIONS Functions
351 * @{
352 */
353
354 /**
355 * @brief Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/
356 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
357 *
358 * Register | BitsName
359 * ----------|--------
360 * CG_CTRL_0 | SECU_HCLK
361 * CG_CTRL_0 | SIM_HCLK
362 * CG_CTRL_0 | HTB_HCLK
363 * CG_CTRL_0 | PWM_HCLK
364 * CG_CTRL_0 | ROM_HCLK
365 * CG_CTRL_0 | SNSADC_HCLK
366 * CG_CTRL_0 | GPIO_HCLK
367 * CG_CTRL_0 | BLE_BRG_HCLK
368 * CG_CTRL_0 | APB_SUB_HCLK
369 * CG_CTRL_0 | SERIAL_HCLK
370 *
371 * @param clk_mask This parameter can be a combination of the following values:
372 * @arg @ref LL_CGC_WFI_SECU_HCLK
373 * @arg @ref LL_CGC_WFI_SIM_HCLK
374 * @arg @ref LL_CGC_WFI_HTB_HCLK
375 * @arg @ref LL_CGC_WFI_PWM_HCLK
376 * @arg @ref LL_CGC_WFI_ROM_HCLK
377 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
378 * @arg @ref LL_CGC_WFI_GPIO_HCLK
379 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
380 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
381 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
382 * @retval None
383 */
384 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
385 {
386 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0], LL_CGC_WFI_ALL_HCLK0, clk_mask);
387 }
388
389 /**
390 * @brief Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/
391 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
392 *
393 * Register | BitsName
394 * ----------|--------
395 * CG_CTRL_0 | SECU_HCLK
396 * CG_CTRL_0 | SIM_HCLK
397 * CG_CTRL_0 | HTB_HCLK
398 * CG_CTRL_0 | PWM_HCLK
399 * CG_CTRL_0 | ROM_HCLK
400 * CG_CTRL_0 | SNSADC_HCLK
401 * CG_CTRL_0 | GPIO_HCLK
402 * CG_CTRL_0 | BLE_BRG_HCLK
403 * CG_CTRL_0 | APB_SUB_HCLK
404 * CG_CTRL_0 | SERIAL_HCLK
405 *
406 * @retval Returned value can be a combination of the following values:
407 * @arg @ref LL_CGC_WFI_SECU_HCLK
408 * @arg @ref LL_CGC_WFI_SIM_HCLK
409 * @arg @ref LL_CGC_WFI_HTB_HCLK
410 * @arg @ref LL_CGC_WFI_PWM_HCLK
411 * @arg @ref LL_CGC_WFI_ROM_HCLK
412 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
413 * @arg @ref LL_CGC_WFI_GPIO_HCLK
414 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
415 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
416 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
417 */
418 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
419 {
420 return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0]);
421 }
422
423 /**
424 * @brief Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
425 *
426 * Register | BitsName
427 * ----------|--------
428 * CG_CTRL_2 | AON_MCUSUB_HCLK
429 * CG_CTRL_2 | XF_XQSPI_HCLK
430 * CG_CTRL_2 | SRAM_HCLK
431 *
432 * @param clk_mask This parameter can be a combination of the following values:
433 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
434 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
435 * @arg @ref LL_CGC_WFI_SRAM_HCLK
436 * @retval None
437 */
438 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
439 {
440 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1, clk_mask);
441 }
442
443 /**
444 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
445 *
446 * Register | BitsName
447 * ----------|--------
448 * CG_CTRL_2 | AON_MCUSUB_HCLK
449 * CG_CTRL_2 | XF_XQSPI_HCLK
450 * CG_CTRL_2 | SRAM_HCLK
451 *
452 * @retval Returned value can be a combination of the following values:
453 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
454 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
455 * @arg @ref LL_CGC_WFI_SRAM_HCLK
456 */
457 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
458 {
459 return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1);
460 }
461
462 /**
463 * @brief Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
464 *
465 * Register | BitsName
466 * ----------|--------
467 * PERIPH_GC | SECU_DIV4_PCLK
468 * PERIPH_GC | XQSPI_DIV4_PCLK
469 *
470 * @param clk_mask This parameter can be a combination of the following values:
471 * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
472 * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
473 * @retval None
474 */
475 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
476 {
477 MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2, clk_mask);
478 }
479
480 /**
481 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
482 *
483 * Register | BitsName
484 * ----------|--------
485 * PERIPH_GC | SECU_DIV4_PCLK
486 * PERIPH_GC | XQSPI_DIV4_PCLK
487 *
488 * @retval Returned value can be a combination of the following values:
489 * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
490 * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
491 */
492 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
493 {
494 return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2);
495 }
496
497 /**
498 * @brief Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI.etc)
499 *
500 * Register | BitsName
501 * ----------|--------
502 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
503 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
504 *
505 * @param clk_mask This parameter can be a combination of the following values:
506 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
507 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
508 * .....
509 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF
510 * @retval None
511 */
512 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
513 {
514 MODIFY_REG(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL, clk_mask);
515 }
516
517 /**
518 * @brief Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI.etc)
519 *
520 * Register | BitsName
521 * ----------|--------
522 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
523 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
524 *
525 * @retval Returned value can be a combination of the following values:
526 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
527 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
528 * .....
529 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF
530 */
531 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
532 {
533 return READ_BITS(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL);
534 }
535
536 /**
537 * @brief Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
538 *
539 * Register | BitsName
540 * ----------|--------
541 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
542 *
543 * @param clk_mask This parameter can be a combination of the following values:
544 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
545 * .....
546 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
547 * @retval None
548 */
549 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
550 {
551 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
552 }
553
554 /**
555 * @brief Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
556 *
557 * Register | BitsName
558 * ----------|--------
559 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
560 *
561 * @retval Returned value can be a combination of the following values:
562 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
563 * .....
564 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
565 */
566 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
567 {
568 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
569 }
570
571 /**
572 * @brief Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/
573 * DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
574 *
575 * Register | BitsName
576 * ----------|--------
577 * CG_CTRL_1 | SECU_HCLK
578 * CG_CTRL_1 | SIM_HCLK
579 * CG_CTRL_1 | HTB_HCLK
580 * CG_CTRL_1 | ROM_HCLK
581 * CG_CTRL_1 | SNSADC_HCLK
582 * CG_CTRL_1 | GPIO_HCLK
583 * CG_CTRL_1 | BLE_BRG_HCLK
584 * CG_CTRL_1 | APB_SUB_HCLK
585 * CG_CTRL_1 | SERIAL_HCLK
586 *
587 * @param clk_mask This parameter can be a combination of the following values:
588 * @arg @ref LL_CGC_FRC_SECU_HCLK
589 * @arg @ref LL_CGC_FRC_SIM_HCLK
590 * @arg @ref LL_CGC_FRC_HTB_HCLK
591 * @arg @ref LL_CGC_FRC_ROM_HCLK
592 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
593 * @arg @ref LL_CGC_FRC_GPIO_HCLK
594 * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
595 * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
596 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
597 * @retval None
598 */
599 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
600 {
601 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1], LL_CGC_FRC_ALL_HCLK0, clk_mask);
602 }
603
604 /**
605 * @brief Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/
606 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
607 *
608 * Register | BitsName
609 * ----------|--------
610 * CG_CTRL_1 | SECU_HCLK
611 * CG_CTRL_1 | SIM_HCLK
612 * CG_CTRL_1 | HTB_HCLK
613 * CG_CTRL_1 | ROM_HCLK
614 * CG_CTRL_1 | SNSADC_HCLK
615 * CG_CTRL_1 | GPIO_HCLK
616 * CG_CTRL_1 | BLE_BRG_HCLK
617 * CG_CTRL_1 | APB_SUB_HCLK
618 * CG_CTRL_1 | SERIAL_HCLK
619 *
620 * @retval Returned value can be a combination of the following values:
621 * @arg @ref LL_CGC_FRC_SECU_HCLK
622 * @arg @ref LL_CGC_FRC_SIM_HCLK
623 * @arg @ref LL_CGC_FRC_HTB_HCLK
624 * @arg @ref LL_CGC_FRC_ROM_HCLK
625 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
626 * @arg @ref LL_CGC_FRC_GPIO_HCLK
627 * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
628 * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
629 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
630 */
631 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
632 {
633 return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1]);
634 }
635
636 /**
637 * @brief Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
638 *
639 * Register | BitsName
640 * ----------|--------
641 * CG_CTRL_2 | AON_MCUSUB_HCLK
642 * CG_CTRL_2 | XF_XQSPI_HCLK
643 * CG_CTRL_2 | SRAM_HCLK
644 *
645 * @param clk_mask This parameter can be a combination of the following values:
646 * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
647 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
648 * @arg @ref LL_CGC_FRC_SRAM_HCLK
649 * @retval None
650 */
651 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
652 {
653 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1, clk_mask);
654 }
655
656 /**
657 * @brief Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
658 *
659 * Register | BitsName
660 * ----------|--------
661 * CG_CTRL_2 | AON_MCUSUB_HCLK
662 * CG_CTRL_2 | XF_XQSPI_HCLK
663 * CG_CTRL_2 | SRAM_HCLK
664 *
665 * @retval Returned value can be a combination of the following values:
666 * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
667 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
668 * @arg @ref LL_CGC_FRC_SRAM_HCLK
669 */
670 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
671 {
672 return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1);
673 }
674
675 /**
676 * @brief Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
677 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
678 *
679 * Register | BitsName
680 * ----------|--------
681 * PERIPH_GC | UART0_PCLK
682 * PERIPH_GC | UART1_PCLK
683 * PERIPH_GC | UART2_PCLK
684 * PERIPH_GC | UART3_PCLK
685 * PERIPH_GC | UART4_PCLK
686 * PERIPH_GC | UART5_PCLK
687 * PERIPH_GC | I2C0_PCLK
688 * PERIPH_GC | I2C1_PCLK
689 * PERIPH_GC | I2C2_PCLK
690 * PERIPH_GC | I2C3_PCLK
691 * PERIPH_GC | I2C4_PCLK
692 * PERIPH_GC | I2C5_PCLK
693 * PERIPH_GC | QSPI0_PCLK
694 * PERIPH_GC | QSPI1_PCLK
695 * PERIPH_GC | QSPI2_PCLK
696 * PERIPH_GC | SPIM_PCLK
697 * PERIPH_GC | SPIS_PCLK
698 * PERIPH_GC | I2S_HCLK
699 * PERIPH_GC | I2S_S_PCLK
700 * PERIPH_GC | DSPI_PCLK
701 * PERIPH_GC | PDM_PCLK
702 * PERIPH_GC | PWM_0_PCLK
703 * PERIPH_GC | PWM_1_PCLK
704 * PERIPH_GC | VTTBL_PCLK
705 * PERIPH_GC | SECU_DIV4_PCLK
706 * PERIPH_GC | XQSPI_DIV4_PCLK
707 * PERIPH_GC | SERIALS_HCLK2
708 *
709 * @param clk_mask This parameter can be a combination of the following values:
710 * @arg @ref LL_CGC_FRC_UART0_PCLK
711 * @arg @ref LL_CGC_FRC_UART1_PCLK
712 * @arg @ref LL_CGC_FRC_UART2_PCLK
713 * @arg @ref LL_CGC_FRC_UART3_PCLK
714 * @arg @ref LL_CGC_FRC_UART4_PCLK
715 * @arg @ref LL_CGC_FRC_UART5_PCLK
716 * @arg @ref LL_CGC_FRC_I2C0_PCLK
717 * @arg @ref LL_CGC_FRC_I2C1_PCLK
718 * @arg @ref LL_CGC_FRC_I2C2_PCLK
719 * @arg @ref LL_CGC_FRC_I2C3_PCLK
720 * @arg @ref LL_CGC_FRC_I2C4_PCLK
721 * @arg @ref LL_CGC_FRC_I2C5_PCLK
722 * @arg @ref LL_CGC_FRC_QSPI0_PCLK
723 * @arg @ref LL_CGC_FRC_QSPI1_PCLK
724 * @arg @ref LL_CGC_FRC_QSPI2_PCLK
725 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
726 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
727 * @arg @ref LL_CGC_FRC_I2S_HCLK
728 * @arg @ref LL_CGC_FRC_I2S_S_PCLK
729 * @arg @ref LL_CGC_FRC_DSPI_PCLK
730 * @arg @ref LL_CGC_FRC_PDM_PCLK
731 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
732 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
733 * @arg @ref LL_CGC_FRC_VTTBL_PCLK
734 * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
735 * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
736 * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
737 * @retval None
738 */
739 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
740 {
741 MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2, clk_mask);
742 }
743
744
745 /**
746 * @brief Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
747 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
748 *
749 * Register | BitsName
750 * ----------|--------
751 * PERIPH_GC | UART0_PCLK
752 * PERIPH_GC | UART1_PCLK
753 * PERIPH_GC | UART2_PCLK
754 * PERIPH_GC | UART3_PCLK
755 * PERIPH_GC | UART4_PCLK
756 * PERIPH_GC | UART5_PCLK
757 * PERIPH_GC | I2C0_PCLK
758 * PERIPH_GC | I2C1_PCLK
759 * PERIPH_GC | I2C2_PCLK
760 * PERIPH_GC | I2C3_PCLK
761 * PERIPH_GC | I2C4_PCLK
762 * PERIPH_GC | I2C5_PCLK
763 * PERIPH_GC | QSPI0_PCLK
764 * PERIPH_GC | QSPI1_PCLK
765 * PERIPH_GC | QSPI2_PCLK
766 * PERIPH_GC | SPIM_PCLK
767 * PERIPH_GC | SPIS_PCLK
768 * PERIPH_GC | I2S_HCLK
769 * PERIPH_GC | I2S_S_PCLK
770 * PERIPH_GC | DSPI_PCLK
771 * PERIPH_GC | PDM_PCLK
772 * PERIPH_GC | PWM_0_PCLK
773 * PERIPH_GC | PWM_1_PCLK
774 * PERIPH_GC | VTTBL_PCLK
775 * PERIPH_GC | SECU_DIV4_PCLK
776 * PERIPH_GC | XQSPI_DIV4_PCLK
777 * PERIPH_GC | SERIALS_HCLK2
778 *
779 * @retval Returned value can be a combination of the following values:
780 * @arg @ref LL_CGC_FRC_UART0_PCLK
781 * @arg @ref LL_CGC_FRC_UART1_PCLK
782 * @arg @ref LL_CGC_FRC_UART2_PCLK
783 * @arg @ref LL_CGC_FRC_UART3_PCLK
784 * @arg @ref LL_CGC_FRC_UART4_PCLK
785 * @arg @ref LL_CGC_FRC_UART5_PCLK
786 * @arg @ref LL_CGC_FRC_I2C0_PCLK
787 * @arg @ref LL_CGC_FRC_I2C1_PCLK
788 * @arg @ref LL_CGC_FRC_I2C2_PCLK
789 * @arg @ref LL_CGC_FRC_I2C3_PCLK
790 * @arg @ref LL_CGC_FRC_I2C4_PCLK
791 * @arg @ref LL_CGC_FRC_I2C5_PCLK
792 * @arg @ref LL_CGC_FRC_QSPI0_PCLK
793 * @arg @ref LL_CGC_FRC_QSPI1_PCLK
794 * @arg @ref LL_CGC_FRC_QSPI2_PCLK
795 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
796 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
797 * @arg @ref LL_CGC_FRC_I2S_HCLK
798 * @arg @ref LL_CGC_FRC_I2S_S_PCLK
799 * @arg @ref LL_CGC_FRC_DSPI_PCLK
800 * @arg @ref LL_CGC_FRC_PDM_PCLK
801 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
802 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
803 * @arg @ref LL_CGC_FRC_VTTBL_PCLK
804 * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
805 * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
806 * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
807 */
808 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
809 {
810 return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2);
811 }
812
813 /**
814 * @brief Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
815 *
816 * Register | BitsName
817 * ----------|--------
818 * PERIPH_GC | AES/HMAC/PKC/PRESENT/RAMKEY/RNG/EFUSE
819 *
820 * @param clk_mask This parameter can be a combination of the following values:
821 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
822 * .....
823 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
824 * @retval None
825 */
826 __STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
827 {
828 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
829 }
830
831 /**
832 * @brief Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
833 *
834 * Register | BitsName
835 * ----------|--------
836 * PERIPH_GC | AES/HMAC/PKC/PRESENT/RAMKEY/RNG/EFUSE
837 *
838 * @retval Returned value can be a combination of the following values:
839 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
840 * .....
841 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
842 */
843 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
844 {
845 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
846 }
847
848
849 /**
850 * @brief Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
851 *
852 * Register | BitsName
853 * ----------|--------
854 * CG_CTRL_0 | SECU_HCLK
855 *
856 * @retval None
857 */
858 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
859 {
860 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
861 }
862
863 /**
864 * @brief Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
865 *
866 * Register | BitsName
867 * ----------|--------
868 * CG_CTRL_0 | SECU_HCLK
869 *
870 * @retval None
871 */
872 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
873 {
874 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
875 }
876
877 /**
878 * @brief Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is enabled.
879 *
880 * Register | BitsName
881 * ----------|--------
882 * CG_CTRL_0 | SECU_HCLK
883 *
884 * @retval State of bit (1 or 0).
885 */
886 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
887 {
888 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
889 }
890
891 /**
892 * @brief Enable SIM automatic turn off clock during WFI
893 *
894 * Register | BitsName
895 * ----------|--------
896 * CG_CTRL_0 | SIM_HCLK
897 *
898 * @retval None
899 */
900 __STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
901 {
902 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) = CGC_CLOCK_ENABLE;
903 }
904
905 /**
906 * @brief Disable SIM automatic turn off clock during WFI
907 *
908 * Register | BitsName
909 * ----------|--------
910 * CG_CTRL_0 | SIM_HCLK
911 *
912 * @retval None
913 */
914 __STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
915 {
916 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) = CGC_CLOCK_DISABLE;
917 }
918
919 /**
920 * @brief Indicate whether the SIM automatic turn off clock is enabled.
921 *
922 * Register | BitsName
923 * ----------|--------
924 * CG_CTRL_0 | SIM_HCLK
925 *
926 * @retval State of bit (1 or 0).
927 */
928 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
929 {
930 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
931 }
932
933 /**
934 * @brief Enable Hopping Table automatic turn off clock during WFI
935 *
936 * Register | BitsName
937 * ----------|--------
938 * CG_CTRL_0 | HTB_HCLK
939 *
940 * @retval None
941 */
942 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
943 {
944 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
945 }
946
947 /**
948 * @brief Disable Hopping Table automatic turn off clock during WFI
949 *
950 * Register | BitsName
951 * ----------|--------
952 * CG_CTRL_0 | HTB_HCLK
953 *
954 * @retval None
955 */
956 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
957 {
958 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
959 }
960
961 /**
962 * @brief Indicate whether the Hopping Table automatic turn off clock is enabled.
963 *
964 * Register | BitsName
965 * ----------|--------
966 * CG_CTRL_0 | HTB_HCLK
967 *
968 * @retval State of bit (1 or 0).
969 */
970 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
971 {
972 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
973 }
974
975 /**
976 * @brief Enable PWM automatic turn off clock during WFI
977 *
978 * Register | BitsName
979 * ----------|--------
980 * CG_CTRL_0 | PWM_HCLK
981 *
982 * @retval None
983 */
984 __STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
985 {
986 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) = CGC_CLOCK_ENABLE;
987 }
988
989 /**
990 * @brief Disable PWM automatic turn off clock during WFI
991 *
992 * Register | BitsName
993 * ----------|--------
994 * CG_CTRL_0 | PWM_HCLK
995 *
996 * @retval None
997 */
998 __STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
999 {
1000 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1001 }
1002
1003 /**
1004 * @brief Indicate whether the PWM automatic turn off clock is enabled.
1005 *
1006 * Register | BitsName
1007 * ----------|--------
1008 * CG_CTRL_0 | PWM_HCLK
1009 *
1010 * @retval State of bit (1 or 0).
1011 */
1012 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
1013 {
1014 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1015 }
1016
1017 /**
1018 * @brief Enable ROM automatic turn off clock during WFI
1019 *
1020 * Register | BitsName
1021 * ----------|--------
1022 * CG_CTRL_0 | ROM_HCLK
1023 *
1024 * @retval None
1025 */
1026 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
1027 {
1028 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1029 }
1030
1031 /**
1032 * @brief Disable ROM automatic turn off clock during WFI
1033 *
1034 * Register | BitsName
1035 * ----------|--------
1036 * CG_CTRL_0 | ROM_HCLK
1037 *
1038 * @retval None
1039 */
1040 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
1041 {
1042 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1043 }
1044
1045 /**
1046 * @brief Indicate whether the ROM automatic turn off clock is enabled.
1047 *
1048 * Register | BitsName
1049 * ----------|--------
1050 * CG_CTRL_0 | ROM_HCLK
1051 *
1052 * @retval State of bit (1 or 0).
1053 */
1054 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
1055 {
1056 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1057 }
1058
1059 /**
1060 * @brief Enable SNSADC automatic turn off clock during WFI
1061 *
1062 * Register | BitsName
1063 * ----------|--------
1064 * CG_CTRL_0 | SNSADC_HCLK
1065 *
1066 * @retval None
1067 */
1068 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
1069 {
1070 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1071 }
1072
1073 /**
1074 * @brief Disable SNSADC automatic turn off clock during WFI
1075 *
1076 * Register | BitsName
1077 * ----------|--------
1078 * CG_CTRL_0 | SNSADC_HCLK
1079 *
1080 * @retval None
1081 */
1082 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
1083 {
1084 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1085 }
1086
1087 /**
1088 * @brief Indicate whether the SNSADC automatic turn off clock is enabled.
1089 *
1090 * Register | BitsName
1091 * ----------|--------
1092 * CG_CTRL_0 | SNSADC_HCLK
1093 *
1094 * @retval State of bit (1 or 0).
1095 */
1096 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
1097 {
1098 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1099 }
1100
1101 /**
1102 * @brief Enable GPIO automatic turn off clock during WFI
1103 *
1104 * Register | BitsName
1105 * ----------|--------
1106 * CG_CTRL_0 | GPIO_HCLK
1107 *
1108 * @retval None
1109 */
1110 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
1111 {
1112 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1113 }
1114
1115 /**
1116 * @brief Disable GPIO automatic turn off clock during WFI
1117 *
1118 * Register | BitsName
1119 * ----------|--------
1120 * CG_CTRL_0 | GPIO_HCLK
1121 *
1122 * @retval None
1123 */
1124 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
1125 {
1126 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1127 }
1128
1129 /**
1130 * @brief Indicate whether the GPIO automatic turn off clock is enabled.
1131 *
1132 * Register | BitsName
1133 * ----------|--------
1134 * CG_CTRL_0 | GPIO_HCLK
1135 *
1136 * @retval State of bit (1 or 0).
1137 */
1138 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
1139 {
1140 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1141 }
1142
1143 /**
1144 * @brief Enable DMA automatic turn off clock during WFI
1145 *
1146 * Register | BitsName
1147 * ----------|--------
1148 * CG_CTRL_0 | DMA_HCLK
1149 *
1150 * @retval None
1151 */
1152 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
1153 {
1154 // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_ENABLE;
1155 }
1156
1157 /**
1158 * @brief Disable DMA automatic turn off clock during WFI
1159 *
1160 * Register | BitsName
1161 * ----------|--------
1162 * CG_CTRL_0 | DMA_HCLK
1163 *
1164 * @retval None
1165 */
1166 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
1167 {
1168 // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_DISABLE;
1169 }
1170
1171 /**
1172 * @brief Indicate whether the DMA automatic turn off clock is enabled.
1173 *
1174 * Register | BitsName
1175 * ----------|--------
1176 * CG_CTRL_0 | DMA_HCLK
1177 *
1178 * @retval State of bit (1 or 0).
1179 */
1180 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
1181 {
1182 // return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1183 return 0;
1184 }
1185
1186 /**
1187 * @brief Enable BLE Bridge automatic turn off clock during WFI
1188 *
1189 * Register | BitsName
1190 * ----------|--------
1191 * CG_CTRL_0 | BLE_BRG_HCLK
1192 *
1193 * @retval None
1194 */
1195 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
1196 {
1197 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1198 }
1199
1200 /**
1201 * @brief Disable BLE Bridge automatic turn off clock during WFI
1202 *
1203 * Register | BitsName
1204 * ----------|--------
1205 * CG_CTRL_0 | BLE_BRG_HCLK
1206 *
1207 * @retval None
1208 */
1209 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1210 {
1211 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1212 }
1213
1214 /**
1215 * @brief Indicate whether the BLE Bridge automatic turn off clock is enabled.
1216 *
1217 * Register | BitsName
1218 * ----------|--------
1219 * CG_CTRL_0 | BLE_BRG_HCLK
1220 *
1221 * @retval State of bit (1 or 0).
1222 */
1223 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1224 {
1225 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1226 }
1227
1228 /**
1229 * @brief Enable APB Subsystem automatic turn off clock during WFI
1230 *
1231 * Register | BitsName
1232 * ----------|--------
1233 * CG_CTRL_0 | APB_SUB_HCLK
1234 *
1235 * @retval None
1236 */
1237 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1238 {
1239 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1240 }
1241
1242 /**
1243 * @brief Disable APB Subsystem automatic turn off clock during WFI
1244 *
1245 * Register | BitsName
1246 * ----------|--------
1247 * CG_CTRL_0 | APB_SUB_HCLK
1248 *
1249 * @retval None
1250 */
1251 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1252 {
1253 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1254 }
1255
1256 /**
1257 * @brief Indicate whether the APB Subsystem automatic turn off clock is enabled.
1258 *
1259 * Register | BitsName
1260 * ----------|--------
1261 * CG_CTRL_0 | APB_SUB_HCLK
1262 *
1263 * @retval State of bit (1 or 0).
1264 */
1265 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1266 {
1267 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1268 }
1269
1270 /**
1271 * @brief Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1272 *
1273 * Register | BitsName
1274 * ----------|--------
1275 * CG_CTRL_0 | SERIAL_HCLK
1276 *
1277 * @retval None
1278 */
1279 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1280 {
1281 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1282 }
1283
1284 /**
1285 * @brief Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1286 *
1287 * Register | BitsName
1288 * ----------|--------
1289 * CG_CTRL_0 | SERIAL_HCLK
1290 *
1291 * @retval None
1292 */
1293 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1294 {
1295 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1296 }
1297
1298 /**
1299 * @brief Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off
1300 * clock is enabled.
1301 *
1302 * Register | BitsName
1303 * ----------|--------
1304 * CG_CTRL_0 | SERIAL_HCLK
1305 *
1306 * @retval State of bit (1 or 0).
1307 */
1308 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1309 {
1310 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1311 }
1312
1313 /**
1314 * @brief Enable USB automatic turn off clock during WFI
1315 *
1316 * Register | BitsName
1317 * ----------|--------
1318 * CG_CTRL_0 | USB_HCLK
1319 *
1320 * @retval None
1321 */
1322 __STATIC_INLINE void ll_cgc_enable_wfi_off_usb_hclk(void)
1323 {
1324 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1325 }
1326
1327 /**
1328 * @brief Disable USB automatic turn off clock during WFI
1329 *
1330 * Register | BitsName
1331 * ----------|--------
1332 * CG_CTRL_0 | USB_HCLK
1333 *
1334 * @retval None
1335 */
1336 __STATIC_INLINE void ll_cgc_disable_wfi_off_usb_hclk(void)
1337 {
1338 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1339 }
1340
1341 /**
1342 * @brief Indicate whether the USB automatic turn off
1343 * clock is enabled.
1344 *
1345 * Register | BitsName
1346 * ----------|--------
1347 * CG_CTRL_0 | USB_HCLK
1348 *
1349 * @retval State of bit (1 or 0).
1350 */
1351 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_usb_hclk(void)
1352 {
1353 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1354 }
1355
1356 /**
1357 * @brief Enable AON_MUCSUB automatic turn off clock during WFI
1358 *
1359 * Register | BitsName
1360 * ----------|--------
1361 * CG_CTRL_2 | AON_MCUSUB_HCLK
1362 *
1363 * @retval None
1364 */
1365 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1366 {
1367 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1368 }
1369
1370 /**
1371 * @brief Disable AON_MUCSUB automatic turn off clock during WFI
1372 *
1373 * Register | BitsName
1374 * ----------|--------
1375 * CG_CTRL_2 | AON_MCUSUB_HCLK
1376 *
1377 * @retval None
1378 */
1379 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1380 {
1381 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1382 }
1383
1384 /**
1385 * @brief Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
1386 *
1387 * Register | BitsName
1388 * ----------|--------
1389 * CG_CTRL_2 | AON_MCUSUB_HCLK
1390 *
1391 * @retval State of bit (1 or 0).
1392 */
1393 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1394 {
1395 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1396 }
1397
1398 /**
1399 * @brief Enable XQSPI automatic turn off clock during WFI
1400 *
1401 * Register | BitsName
1402 * ----------|--------
1403 * CG_CTRL_2 | XF_XQSPI_HCLK
1404 *
1405 * @retval None
1406 */
1407 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1408 {
1409 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1410 }
1411
1412 /**
1413 * @brief Disable XQSPI automatic turn off clock during WFI
1414 *
1415 * Register | BitsName
1416 * ----------|--------
1417 * CG_CTRL_2 | XF_XQSPI_HCLK
1418 *
1419 * @retval None
1420 */
1421 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1422 {
1423 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1424 }
1425
1426 /**
1427 * @brief Indicate whether the XQSPI automatic turn off clock is enabled.
1428 *
1429 * Register | BitsName
1430 * ----------|--------
1431 * CG_CTRL_2 | XF_XQSPI_HCLK
1432 *
1433 * @retval State of bit (1 or 0).
1434 */
1435 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1436 {
1437 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1438 }
1439
1440 /**
1441 * @brief Enable SRAM automatic turn off clock during WFI
1442 *
1443 * Register | BitsName
1444 * ----------|--------
1445 * CG_CTRL_2 | SRAM_HCLK
1446 *
1447 * @retval None
1448 */
1449 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1450 {
1451 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1452 }
1453
1454 /**
1455 * @brief Disable SRAM automatic turn off clock during WFI
1456 *
1457 * Register | BitsName
1458 * ----------|--------
1459 * CG_CTRL_2 | SRAM_HCLK
1460 *
1461 * @retval None
1462 */
1463 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1464 {
1465 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1466 }
1467
1468 /**
1469 * @brief Indicate whether the SRAM automatic turn off clock is enabled.
1470 *
1471 * Register | BitsName
1472 * ----------|--------
1473 * CG_CTRL_2 | SRAM_HCLK
1474 *
1475 * @retval State of bit (1 or 0).
1476 */
1477 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1478 {
1479 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1480 }
1481
1482 /**
1483 * @brief Enable security blocks automatic turn off div4 clock during WFI
1484 *
1485 * Register | BitsName
1486 * ----------|--------
1487 * PERIPH_GC | SECU_DIV4_PCLK
1488 *
1489 * @retval None
1490 */
1491 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1492 {
1493 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1494 }
1495
1496 /**
1497 * @brief Disable security blocks automatic turn off div4 clock during WFI
1498 *
1499 * Register | BitsName
1500 * ----------|--------
1501 * PERIPH_GC | SECU_DIV4_PCLK
1502 *
1503 * @retval None
1504 */
1505 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1506 {
1507 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1508 }
1509
1510 /**
1511 * @brief Indicate whether the security blocks automatic turn off div4
1512 * clock is enabled.
1513 *
1514 * Register | BitsName
1515 * ----------|--------
1516 * PERIPH_GC | SECU_DIV4_PCLK
1517 *
1518 * @retval State of bit (1 or 0).
1519 */
1520 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1521 {
1522 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1523 }
1524
1525 /**
1526 * @brief Enable XQSPI automatic turn off div4 clock during WFI
1527 *
1528 * Register | BitsName
1529 * ----------|--------
1530 * PERIPH_GC | XQSPI_DIV4_PCLK
1531 *
1532 * @retval None
1533 */
1534 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1535 {
1536 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1537 }
1538
1539 /**
1540 * @brief Disable XQSPI automatic turn off div4 clock during WFI
1541 *
1542 * Register | BitsName
1543 * ----------|--------
1544 * PERIPH_GC | XQSPI_DIV4_PCLK
1545 *
1546 * @retval None
1547 */
1548 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1549 {
1550 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1551 }
1552
1553 /**
1554 * @brief Indicate whether the XQSPI automatic turn off div4 clock is enabled.
1555 *
1556 * Register | BitsName
1557 * ----------|--------
1558 * PERIPH_GC | XQSPI_DIV4_PCLK
1559 *
1560 * @retval State of bit (1 or 0).
1561 */
1562 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1563 {
1564 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1565 }
1566
1567 /**
1568 * @brief Enabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1569 *
1570 * Register | BitsName
1571 * ----------|--------
1572 * CG_CTRL_1 | SECU_HCLK
1573 *
1574 * @retval None
1575 */
1576 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1577 {
1578 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
1579 }
1580
1581 /**
1582 * @brief Disabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1583 *
1584 * Register | BitsName
1585 * ----------|--------
1586 * CG_CTRL_1 | SECU_HCLK
1587 *
1588 * @retval None
1589 */
1590 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1591 {
1592 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
1593 }
1594
1595 /**
1596 * @brief Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
1597 *
1598 * Register | BitsName
1599 * ----------|--------
1600 * CG_CTRL_1 | SECU_HCLK
1601 *
1602 * @retval State of bit (1 or 0).
1603 */
1604 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1605 {
1606 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1607 }
1608
1609 /**
1610 * @brief Enabling force to turn off the clock for SIM.
1611 *
1612 * Register | BitsName
1613 * ----------|--------
1614 * CG_CTRL_1 | SIM_HCLK
1615 *
1616 * @retval None
1617 */
1618 __STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
1619 {
1620 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1621 }
1622
1623 /**
1624 * @brief Disabling force to turn off the clock for SIM.
1625 *
1626 * Register | BitsName
1627 * ----------|--------
1628 * CG_CTRL_1 | SIM_HCLK
1629 *
1630 * @retval None
1631 */
1632 __STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
1633 {
1634 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1635 }
1636
1637 /**
1638 * @brief Indicate whether the clock for SIM is forced to close.
1639 *
1640 * Register | BitsName
1641 * ----------|--------
1642 * CG_CTRL_1 | SIM_HCLK
1643 *
1644 * @retval State of bit (1 or 0).
1645 */
1646 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
1647 {
1648 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1649 }
1650
1651 /**
1652 * @brief Enabling force to turn off the clock for Hopping Table.
1653 *
1654 * Register | BitsName
1655 * ----------|--------
1656 * CG_CTRL_1 | HTB_HCLK
1657 *
1658 * @retval None
1659 */
1660 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1661 {
1662 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1663 }
1664
1665 /**
1666 * @brief Disabling force to turn off the clock for Hopping Table.
1667 *
1668 * Register | BitsName
1669 * ----------|--------
1670 * CG_CTRL_1 | HTB_HCLK
1671 *
1672 * @retval None
1673 */
1674 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1675 {
1676 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1677 }
1678
1679 /**
1680 * @brief Indicate whether the clock for Hopping Table is forced to close.
1681 *
1682 * Register | BitsName
1683 * ----------|--------
1684 * CG_CTRL_1 | HTB_HCLK
1685 *
1686 * @retval State of bit (1 or 0).
1687 */
1688 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1689 {
1690 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1691 }
1692
1693 /**
1694 * @brief Enabling force to turn off the clock for ROM.
1695 *
1696 * Register | BitsName
1697 * ----------|--------
1698 * CG_CTRL_1 | ROM_HCLK
1699 *
1700 * @retval None
1701 */
1702 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1703 {
1704 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1705 }
1706
1707 /**
1708 * @brief Disabling force to turn off the clock for ROM.
1709 *
1710 * Register | BitsName
1711 * ----------|--------
1712 * CG_CTRL_1 | ROM_HCLK
1713 *
1714 * @retval None
1715 */
1716 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1717 {
1718 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1719 }
1720
1721 /**
1722 * @brief Indicate whether the clock for ROM is forced to close.
1723 *
1724 * Register | BitsName
1725 * ----------|--------
1726 * CG_CTRL_1 | ROM_HCLK
1727 *
1728 * @retval State of bit (1 or 0).
1729 */
1730 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1731 {
1732 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1733 }
1734
1735 /**
1736 * @brief Enabling force to turn off the clock for SNSADC.
1737 *
1738 * Register | BitsName
1739 * ----------|--------
1740 * CG_CTRL_1 | SNSADC_HCLK
1741 *
1742 * @retval None
1743 */
1744 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1745 {
1746 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1747 }
1748
1749 /**
1750 * @brief Disabling force to turn off the clock for SNSADC.
1751 *
1752 * Register | BitsName
1753 * ----------|--------
1754 * CG_CTRL_1 | SNSADC_HCLK
1755 *
1756 * @retval None
1757 */
1758 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1759 {
1760 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1761 }
1762
1763 /**
1764 * @brief Indicate whether the clock for SNSADC is forced to close.
1765 *
1766 * Register | BitsName
1767 * ----------|--------
1768 * CG_CTRL_1 | SNSADC_HCLK
1769 *
1770 * @retval State of bit (1 or 0).
1771 */
1772 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1773 {
1774 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1775 }
1776
1777 /**
1778 * @brief Enabling force to turn off the clock for GPIO.
1779 *
1780 * Register | BitsName
1781 * ----------|--------
1782 * CG_CTRL_1 | GPIO_HCLK
1783 *
1784 * @retval None
1785 */
1786 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1787 {
1788 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1789 }
1790
1791 /**
1792 * @brief Disabling force to turn off the clock for GPIO.
1793 *
1794 * Register | BitsName
1795 * ----------|--------
1796 * CG_CTRL_1 | GPIO_HCLK
1797 *
1798 * @retval None
1799 */
1800 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1801 {
1802 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1803 }
1804
1805 /**
1806 * @brief Indicate whether the clock for GPIO is forced to close.
1807 *
1808 * Register | BitsName
1809 * ----------|--------
1810 * CG_CTRL_1 | GPIO_HCLK
1811 *
1812 * @retval State of bit (1 or 0).
1813 */
1814 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1815 {
1816 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1817 }
1818
1819 /**
1820 * @brief Enabling force to turn off the clock for BLE Bridge.
1821 *
1822 * Register | BitsName
1823 * ----------|--------
1824 * CG_CTRL_1 | BLE_BRG_HCLK
1825 *
1826 * @retval None
1827 */
1828 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1829 {
1830 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1831 }
1832
1833 /**
1834 * @brief Disabling force to turn off the clock for BLE Bridge.
1835 *
1836 * Register | BitsName
1837 * ----------|--------
1838 * CG_CTRL_1 | BLE_BRG_HCLK
1839 *
1840 * @retval None
1841 */
1842 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1843 {
1844 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1845 }
1846
1847 /**
1848 * @brief Indicate whether the clock for BLE Bridge is forced to close.
1849 *
1850 * Register | BitsName
1851 * ----------|--------
1852 * CG_CTRL_1 | BLE_BRG_HCLK
1853 *
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1857 {
1858 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1859 }
1860
1861 /**
1862 * @brief Enabling force to turn off the clock for APB Subsystem.
1863 *
1864 * Register | BitsName
1865 * ----------|--------
1866 * CG_CTRL_1 | APB_SUB_HCLK
1867 *
1868 * @retval None
1869 */
1870 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1871 {
1872 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1873 }
1874
1875 /**
1876 * @brief Disabling force to turn off the clock for APB Subsystem.
1877 *
1878 * Register | BitsName
1879 * ----------|--------
1880 * CG_CTRL_1 | APB_SUB_HCLK
1881 *
1882 * @retval None
1883 */
1884 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1885 {
1886 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1887 }
1888
1889 /**
1890 * @brief Indicate whether the clock for APB Subsystem is forced to close.
1891 *
1892 * Register | BitsName
1893 * ----------|--------
1894 * CG_CTRL_1 | APB_SUB_HCLK
1895 *
1896 * @retval State of bit (1 or 0).
1897 */
1898 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1899 {
1900 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1901 }
1902
1903 /**
1904 * @brief Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1905 *
1906 * Register | BitsName
1907 * ----------|--------
1908 * CG_CTRL_1 | SERIAL_HCLK
1909 *
1910 * @retval None
1911 */
1912 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1913 {
1914 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1915 }
1916
1917 /**
1918 * @brief Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1919 *
1920 * Register | BitsName
1921 * ----------|--------
1922 * CG_CTRL_1 | SERIAL_HCLK
1923 *
1924 * @retval None
1925 */
1926 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1927 {
1928 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1929 }
1930
1931 /**
1932 * @brief Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
1933 *
1934 * Register | BitsName
1935 * ----------|--------
1936 * CG_CTRL_1 | SERIAL_HCLK
1937 *
1938 * @retval State of bit (1 or 0).
1939 */
1940 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1941 {
1942 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1943 }
1944
1945 /**
1946 * @brief Enabling force to turn off the clock for USB.
1947 *
1948 * Register | BitsName
1949 * ----------|--------
1950 * CG_CTRL_1 | USB_HCLK
1951 *
1952 * @retval None
1953 */
1954 __STATIC_INLINE void ll_cgc_enable_force_off_usb_hclk(void)
1955 {
1956 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1957 }
1958
1959 /**
1960 * @brief Disabling force to turn off the clock for USB.
1961 *
1962 * Register | BitsName
1963 * ----------|--------
1964 * CG_CTRL_1 | USB_HCLK
1965 *
1966 * @retval None
1967 */
1968 __STATIC_INLINE void ll_cgc_disable_force_off_usb_hclk(void)
1969 {
1970 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1971 }
1972
1973 /**
1974 * @brief Indicate whether the clock for USB is forced to close.
1975 *
1976 * Register | BitsName
1977 * ----------|--------
1978 * CG_CTRL_1 | USB_HCLK
1979 *
1980 * @retval State of bit (1 or 0).
1981 */
1982 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_usb_hclk(void)
1983 {
1984 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1985 }
1986
1987 /**
1988 * @brief Enabling force to turn off the clock for AON_MUCSUB.
1989 *
1990 * Register | BitsName
1991 * ----------|--------
1992 * CG_CTRL_2 | AON_MCUSUB_HCLK
1993 *
1994 * @retval None
1995 */
1996 __STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
1997 {
1998 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1999 }
2000
2001 /**
2002 * @brief Disabling force to turn off the clock for AON_MUCSUB.
2003 *
2004 * Register | BitsName
2005 * ----------|--------
2006 * CG_CTRL_2 | AON_MCUSUB_HCLK
2007 *
2008 * @retval None
2009 */
2010 __STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
2011 {
2012 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
2013 }
2014
2015 /**
2016 * @brief Indicate whether the clock for AON_MUCSUB is forced to close.
2017 *
2018 * Register | BitsName
2019 * ----------|--------
2020 * CG_CTRL_2 | AON_MCUSUB_HCLK
2021 *
2022 * @retval State of bit (1 or 0).
2023 */
2024 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
2025 {
2026 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2027 }
2028
2029 /**
2030 * @brief Enabling force to turn off the clock for XQSPI.
2031 *
2032 * Register | BitsName
2033 * ----------|--------
2034 * CG_CTRL_2 | XF_XQSPI_HCLK
2035 *
2036 * @retval None
2037 */
2038 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
2039 {
2040 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
2041 }
2042
2043 /**
2044 * @brief Disabling force to turn off the clock for XQSPI.
2045 *
2046 * Register | BitsName
2047 * ----------|--------
2048 * CG_CTRL_2 | XF_XQSPI_HCLK
2049 *
2050 * @retval None
2051 */
2052 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
2053 {
2054 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
2055 }
2056
2057 /**
2058 * @brief Indicate whether the clock for XQSPI is forced to close.
2059 *
2060 * Register | BitsName
2061 * ----------|--------
2062 * CG_CTRL_2 | XF_XQSPI_HCLK
2063 *
2064 * @retval State of bit (1 or 0).
2065 */
2066 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
2067 {
2068 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2069 }
2070
2071 /**
2072 * @brief Enabling force to turn off the clock for SRAM.
2073 *
2074 * Register | BitsName
2075 * ----------|--------
2076 * CG_CTRL_2 | SRAM_HCLK
2077 *
2078 * @retval None
2079 */
2080 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
2081 {
2082 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
2083 }
2084
2085 /**
2086 * @brief Disabling force to turn off the clock for SRAM.
2087 *
2088 * Register | BitsName
2089 * ----------|--------
2090 * CG_CTRL_2 | SRAM_HCLK
2091 *
2092 * @retval None
2093 */
2094 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
2095 {
2096 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
2097 }
2098
2099 /**
2100 * @brief Indicate whether the clock for SRAM is forced to close.
2101 *
2102 * Register | BitsName
2103 * ----------|--------
2104 * CG_CTRL_2 | SRAM_HCLK
2105 *
2106 * @retval State of bit (1 or 0).
2107 */
2108 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
2109 {
2110 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2111 }
2112
2113 /**
2114 * @brief Enabling force to turn off the clock for UART0.
2115 *
2116 * Register | BitsName
2117 * ----------|--------
2118 * PERIPH_GC | UART0_HCLK
2119 *
2120 * @retval None
2121 */
2122 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
2123 {
2124 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2125 }
2126
2127 /**
2128 * @brief Disabling force to turn off the clock for UART0.
2129 *
2130 * Register | BitsName
2131 * ----------|--------
2132 * PERIPH_GC | UART0_HCLK
2133 *
2134 * @retval None
2135 */
2136 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
2137 {
2138 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2139 }
2140
2141 /**
2142 * @brief Indicate whether the clock for UART0 is forced to close.
2143 *
2144 * Register | BitsName
2145 * ----------|--------
2146 * PERIPH_GC | UART0_HCLK
2147 *
2148 * @retval State of bit (1 or 0).
2149 */
2150 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
2151 {
2152 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2153 }
2154
2155 /**
2156 * @brief Enabling force to turn off the clock for UART1.
2157 *
2158 * Register | BitsName
2159 * ----------|--------
2160 * PERIPH_GC | UART1_HCLK
2161 *
2162 * @retval None
2163 */
2164 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
2165 {
2166 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2167 }
2168
2169 /**
2170 * @brief Disabling force to turn off the clock for UART1.
2171 *
2172 * Register | BitsName
2173 * ----------|--------
2174 * PERIPH_GC | UART1_HCLK
2175 *
2176 * @retval None
2177 */
2178 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
2179 {
2180 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2181 }
2182
2183 /**
2184 * @brief Indicate whether the clock for UART1 is forced to close.
2185 *
2186 * Register | BitsName
2187 * ----------|--------
2188 * PERIPH_GC | UART1_HCLK
2189 *
2190 * @retval State of bit (1 or 0).
2191 */
2192 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
2193 {
2194 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2195 }
2196
2197 /**
2198 * @brief Enabling force to turn off the clock for UART2.
2199 *
2200 * Register | BitsName
2201 * ----------|--------
2202 * PERIPH_GC | UART2_HCLK
2203 *
2204 * @retval None
2205 */
2206 __STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
2207 {
2208 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2209 }
2210
2211 /**
2212 * @brief Disabling force to turn off the clock for UART2.
2213 *
2214 * Register | BitsName
2215 * ----------|--------
2216 * PERIPH_GC | UART2_HCLK
2217 *
2218 * @retval None
2219 */
2220 __STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
2221 {
2222 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2223 }
2224
2225 /**
2226 * @brief Indicate whether the clock for UART2 is forced to close.
2227 *
2228 * Register | BitsName
2229 * ----------|--------
2230 * PERIPH_GC | UART2_HCLK
2231 *
2232 * @retval State of bit (1 or 0).
2233 */
2234 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
2235 {
2236 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2237 }
2238
2239 /**
2240 * @brief Enabling force to turn off the clock for UART3.
2241 *
2242 * Register | BitsName
2243 * ----------|--------
2244 * PERIPH_GC | UART3_HCLK
2245 *
2246 * @retval None
2247 */
2248 __STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
2249 {
2250 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_ENABLE;
2251 }
2252
2253 /**
2254 * @brief Disabling force to turn off the clock for UART3.
2255 *
2256 * Register | BitsName
2257 * ----------|--------
2258 * PERIPH_GC | UART3_HCLK
2259 *
2260 * @retval None
2261 */
2262 __STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
2263 {
2264 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_DISABLE;
2265 }
2266
2267 /**
2268 * @brief Indicate whether the clock for UART3 is forced to close.
2269 *
2270 * Register | BitsName
2271 * ----------|--------
2272 * PERIPH_GC | UART3_HCLK
2273 *
2274 * @retval State of bit (1 or 0).
2275 */
2276 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
2277 {
2278 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2279 }
2280
2281 /**
2282 * @brief Enabling force to turn off the clock for UART4.
2283 *
2284 * Register | BitsName
2285 * ----------|--------
2286 * PERIPH_GC | UART4_HCLK
2287 *
2288 * @retval None
2289 */
2290 __STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
2291 {
2292 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2293 }
2294
2295 /**
2296 * @brief Disabling force to turn off the clock for UART4.
2297 *
2298 * Register | BitsName
2299 * ----------|--------
2300 * PERIPH_GC | UART4_HCLK
2301 *
2302 * @retval None
2303 */
2304 __STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
2305 {
2306 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2307 }
2308
2309 /**
2310 * @brief Indicate whether the clock for UART4 is forced to close.
2311 *
2312 * Register | BitsName
2313 * ----------|--------
2314 * PERIPH_GC | UART4_HCLK
2315 *
2316 * @retval State of bit (1 or 0).
2317 */
2318 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
2319 {
2320 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2321 }
2322
2323 /**
2324 * @brief Enabling force to turn off the clock for UART5.
2325 *
2326 * Register | BitsName
2327 * ----------|--------
2328 * PERIPH_GC | UART5_HCLK
2329 *
2330 * @retval None
2331 */
2332 __STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
2333 {
2334 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) = CGC_CLOCK_ENABLE;
2335 }
2336
2337 /**
2338 * @brief Disabling force to turn off the clock for UART5.
2339 *
2340 * Register | BitsName
2341 * ----------|--------
2342 * PERIPH_GC | UART5_HCLK
2343 *
2344 * @retval None
2345 */
2346 __STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
2347 {
2348 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) = CGC_CLOCK_DISABLE;
2349 }
2350
2351 /**
2352 * @brief Indicate whether the clock for UART5 is forced to close.
2353 *
2354 * Register | BitsName
2355 * ----------|--------
2356 * PERIPH_GC | UART5_HCLK
2357 *
2358 * @retval State of bit (1 or 0).
2359 */
2360 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
2361 {
2362 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2363 }
2364
2365 /**
2366 * @brief Enabling force to turn off the clock for I2C0.
2367 *
2368 * Register | BitsName
2369 * ----------|--------
2370 * PERIPH_GC | I2C0_HCLK
2371 *
2372 * @retval None
2373 */
2374 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2375 {
2376 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2377 }
2378
2379 /**
2380 * @brief Disabling force to turn off the clock for I2C0.
2381 *
2382 * Register | BitsName
2383 * ----------|--------
2384 * PERIPH_GC | I2C0_HCLK
2385 *
2386 * @retval None
2387 */
2388 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2389 {
2390 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2391 }
2392
2393 /**
2394 * @brief Indicate whether the clock for I2C0 is forced to close.
2395 *
2396 * Register | BitsName
2397 * ----------|--------
2398 * PERIPH_GC | I2C0_HCLK
2399 *
2400 * @retval State of bit (1 or 0).
2401 */
2402 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2403 {
2404 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2405 }
2406
2407 /**
2408 * @brief Enabling force to turn off the clock for I2C1.
2409 *
2410 * Register | BitsName
2411 * ----------|--------
2412 * PERIPH_GC | I2C1_HCLK
2413 *
2414 * @retval None
2415 */
2416 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2417 {
2418 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2419 }
2420
2421 /**
2422 * @brief Disabling force to turn off the clock for I2C1.
2423 *
2424 * Register | BitsName
2425 * ----------|--------
2426 * PERIPH_GC | I2C1_HCLK
2427 *
2428 * @retval None
2429 */
2430 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2431 {
2432 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2433 }
2434
2435 /**
2436 * @brief Indicate whether the clock for I2C1 is forced to close.
2437 *
2438 * Register | BitsName
2439 * ----------|--------
2440 * PERIPH_GC | I2C1_HCLK
2441 *
2442 * @retval State of bit (1 or 0).
2443 */
2444 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2445 {
2446 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2447 }
2448
2449 /**
2450 * @brief Enabling force to turn off the clock for I2C2.
2451 *
2452 * Register | BitsName
2453 * ----------|--------
2454 * PERIPH_GC | I2C2_HCLK
2455 *
2456 * @retval None
2457 */
2458 __STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
2459 {
2460 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2461 }
2462
2463 /**
2464 * @brief Disabling force to turn off the clock for I2C2.
2465 *
2466 * Register | BitsName
2467 * ----------|--------
2468 * PERIPH_GC | I2C2_HCLK
2469 *
2470 * @retval None
2471 */
2472 __STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
2473 {
2474 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2475 }
2476
2477 /**
2478 * @brief Indicate whether the clock for I2C2 is forced to close.
2479 *
2480 * Register | BitsName
2481 * ----------|--------
2482 * PERIPH_GC | I2C2_HCLK
2483 *
2484 * @retval State of bit (1 or 0).
2485 */
2486 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
2487 {
2488 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2489 }
2490
2491 /**
2492 * @brief Enabling force to turn off the clock for I2C3.
2493 *
2494 * Register | BitsName
2495 * ----------|--------
2496 * PERIPH_GC | I2C3_HCLK
2497 *
2498 * @retval None
2499 */
2500 __STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
2501 {
2502 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_ENABLE;
2503 }
2504
2505 /**
2506 * @brief Disabling force to turn off the clock for I2C3.
2507 *
2508 * Register | BitsName
2509 * ----------|--------
2510 * PERIPH_GC | I2C3_HCLK
2511 *
2512 * @retval None
2513 */
2514 __STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
2515 {
2516 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_DISABLE;
2517 }
2518
2519 /**
2520 * @brief Indicate whether the clock for I2C3 is forced to close.
2521 *
2522 * Register | BitsName
2523 * ----------|--------
2524 * PERIPH_GC | I2C3_HCLK
2525 *
2526 * @retval State of bit (1 or 0).
2527 */
2528 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
2529 {
2530 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2531 }
2532
2533 /**
2534 * @brief Enabling force to turn off the clock for I2C4.
2535 *
2536 * Register | BitsName
2537 * ----------|--------
2538 * PERIPH_GC | I2C4_HCLK
2539 *
2540 * @retval None
2541 */
2542 __STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
2543 {
2544 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2545 }
2546
2547 /**
2548 * @brief Disabling force to turn off the clock for I2C4.
2549 *
2550 * Register | BitsName
2551 * ----------|--------
2552 * PERIPH_GC | I2C4_HCLK
2553 *
2554 * @retval None
2555 */
2556 __STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
2557 {
2558 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2559 }
2560
2561 /**
2562 * @brief Indicate whether the clock for I2C4 is forced to close.
2563 *
2564 * Register | BitsName
2565 * ----------|--------
2566 * PERIPH_GC | I2C4_HCLK
2567 *
2568 * @retval State of bit (1 or 0).
2569 */
2570 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
2571 {
2572 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2573 }
2574
2575 /**
2576 * @brief Enabling force to turn off the clock for I2C5.
2577 *
2578 * Register | BitsName
2579 * ----------|--------
2580 * PERIPH_GC | I2C5_HCLK
2581 *
2582 * @retval None
2583 */
2584 __STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
2585 {
2586 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) = CGC_CLOCK_ENABLE;
2587 }
2588
2589 /**
2590 * @brief Disabling force to turn off the clock for I2C5.
2591 *
2592 * Register | BitsName
2593 * ----------|--------
2594 * PERIPH_GC | I2C5_HCLK
2595 *
2596 * @retval None
2597 */
2598 __STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
2599 {
2600 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) = CGC_CLOCK_DISABLE;
2601 }
2602
2603 /**
2604 * @brief Indicate whether the clock for I2C5 is forced to close.
2605 *
2606 * Register | BitsName
2607 * ----------|--------
2608 * PERIPH_GC | I2C5_HCLK
2609 *
2610 * @retval State of bit (1 or 0).
2611 */
2612 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
2613 {
2614 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2615 }
2616
2617 /**
2618 * @brief Enabling force to turn off the clock for SPIM.
2619 *
2620 * Register | BitsName
2621 * ----------|--------
2622 * PERIPH_GC | SPIM_HCLK
2623 *
2624 * @retval None
2625 */
2626 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2627 {
2628 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_ENABLE;
2629 }
2630
2631 /**
2632 * @brief Disabling force to turn off the clock for SPIM.
2633 *
2634 * Register | BitsName
2635 * ----------|--------
2636 * PERIPH_GC | SPIM_HCLK
2637 *
2638 * @retval None
2639 */
2640 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2641 {
2642 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_DISABLE;
2643 }
2644
2645 /**
2646 * @brief Indicate whether the clock for SPIM is forced to close.
2647 *
2648 * Register | BitsName
2649 * ----------|--------
2650 * PERIPH_GC | SPIM_HCLK
2651 *
2652 * @retval State of bit (1 or 0).
2653 */
2654 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2655 {
2656 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2657 }
2658
2659 /**
2660 * @brief Enabling force to turn off the clock for SPIS.
2661 *
2662 * Register | BitsName
2663 * ----------|--------
2664 * PERIPH_GC | SPIS_HCLK
2665 *
2666 * @retval None
2667 */
2668 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2669 {
2670 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2671 }
2672
2673 /**
2674 * @brief Disabling force to turn off the clock for SPIS.
2675 *
2676 * Register | BitsName
2677 * ----------|--------
2678 * PERIPH_GC | SPIS_HCLK
2679 *
2680 * @retval None
2681 */
2682 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2683 {
2684 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2685 }
2686
2687 /**
2688 * @brief Indicate whether the clock for SPIS is forced to close.
2689 *
2690 * Register | BitsName
2691 * ----------|--------
2692 * PERIPH_GC | SPIS_HCLK
2693 *
2694 * @retval State of bit (1 or 0).
2695 */
2696 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2697 {
2698 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2699 }
2700
2701 /**
2702 * @brief Enabling force to turn off the clock for QSPI0.
2703 *
2704 * Register | BitsName
2705 * ----------|--------
2706 * PERIPH_GC | QSPI0_HCLK
2707 *
2708 * @retval None
2709 */
2710 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2711 {
2712 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2713 }
2714
2715 /**
2716 * @brief Disabling force to turn off the clock for QSPI0.
2717 *
2718 * Register | BitsName
2719 * ----------|--------
2720 * PERIPH_GC | QSPI0_HCLK
2721 *
2722 * @retval None
2723 */
2724 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2725 {
2726 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2727 }
2728
2729 /**
2730 * @brief Indicate whether the clock for QSPI0 is forced to close.
2731 *
2732 * Register | BitsName
2733 * ----------|--------
2734 * PERIPH_GC | QSPI0_HCLK
2735 *
2736 * @retval State of bit (1 or 0).
2737 */
2738 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2739 {
2740 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2741 }
2742
2743 /**
2744 * @brief Enabling force to turn off the clock for QSPI1.
2745 *
2746 * Register | BitsName
2747 * ----------|--------
2748 * PERIPH_GC | QSPI1_HCLK
2749 *
2750 * @retval None
2751 */
2752 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2753 {
2754 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2755 }
2756
2757 /**
2758 * @brief Disabling force to turn off the clock for QSPI1.
2759 *
2760 * Register | BitsName
2761 * ----------|--------
2762 * PERIPH_GC | QSPI1_HCLK
2763 *
2764 * @retval None
2765 */
2766 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2767 {
2768 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2769 }
2770
2771 /**
2772 * @brief Indicate whether the clock for QSPI1 is forced to close.
2773 *
2774 * Register | BitsName
2775 * ----------|--------
2776 * PERIPH_GC | QSPI1_HCLK
2777 *
2778 * @retval State of bit (1 or 0).
2779 */
2780 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2781 {
2782 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2783 }
2784
2785 /**
2786 * @brief Enabling force to turn off the clock for QSPI2.
2787 *
2788 * Register | BitsName
2789 * ----------|--------
2790 * PERIPH_GC | QSPI2_HCLK
2791 *
2792 * @retval None
2793 */
2794 __STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
2795 {
2796 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2797 }
2798
2799 /**
2800 * @brief Disabling force to turn off the clock for QSPI2.
2801 *
2802 * Register | BitsName
2803 * ----------|--------
2804 * PERIPH_GC | QSPI2_HCLK
2805 *
2806 * @retval None
2807 */
2808 __STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
2809 {
2810 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2811 }
2812
2813 /**
2814 * @brief Indicate whether the clock for QSPI2 is forced to close.
2815 *
2816 * Register | BitsName
2817 * ----------|--------
2818 * PERIPH_GC | QSPI2_HCLK
2819 *
2820 * @retval State of bit (1 or 0).
2821 */
2822 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
2823 {
2824 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2825 }
2826
2827
2828 /**
2829 * @brief Enabling force to turn off the clock for I2S master.
2830 *
2831 * Register | BitsName
2832 * ----------|--------
2833 * PERIPH_GC | I2S_HCLK
2834 *
2835 * @retval None
2836 */
2837 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2838 {
2839 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2840 }
2841
2842 /**
2843 * @brief Disabling force to turn off the clock for I2S master.
2844 *
2845 * Register | BitsName
2846 * ----------|--------
2847 * PERIPH_GC | I2S_HCLK
2848 *
2849 * @retval None
2850 */
2851 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2852 {
2853 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2854 }
2855
2856 /**
2857 * @brief Indicate whether the clock for I2S master is forced to close.
2858 *
2859 * Register | BitsName
2860 * ----------|--------
2861 * PERIPH_GC | I2S_HCLK
2862 *
2863 * @retval State of bit (1 or 0).
2864 */
2865 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2866 {
2867 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2868 }
2869
2870 /**
2871 * @brief Enabling force to turn off the clock for I2S slave.
2872 *
2873 * Register | BitsName
2874 * ----------|--------
2875 * PERIPH_GC | I2S_S_PCLK
2876 *
2877 * @retval None
2878 */
2879 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
2880 {
2881 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2882 }
2883
2884 /**
2885 * @brief Disabling force to turn off the clock for I2S slave.
2886 *
2887 * Register | BitsName
2888 * ----------|--------
2889 * PERIPH_GC | I2S_S_PCLK
2890 *
2891 * @retval None
2892 */
2893 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
2894 {
2895 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2896 }
2897
2898 /**
2899 * @brief Indicate whether the clock for I2S slave is forced to close.
2900 *
2901 * Register | BitsName
2902 * ----------|--------
2903 * PERIPH_GC | I2S_S_PCLK
2904 *
2905 * @retval State of bit (1 or 0).
2906 */
2907 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
2908 {
2909 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2910 }
2911
2912 /**
2913 * @brief Enabling force to turn off the clock for DSPI slave.
2914 *
2915 * Register | BitsName
2916 * ----------|--------
2917 * PERIPH_GC | DSPI_PCLK
2918 *
2919 * @retval None
2920 */
2921 __STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
2922 {
2923 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_ENABLE;
2924 }
2925
2926 /**
2927 * @brief Disabling force to turn off the clock for DSPI slave.
2928 *
2929 * Register | BitsName
2930 * ----------|--------
2931 * PERIPH_GC | DSPI_PCLK
2932 *
2933 * @retval None
2934 */
2935 __STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
2936 {
2937 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_DISABLE;
2938 }
2939
2940 /**
2941 * @brief Indicate whether the clock for DSPI is forced to close.
2942 *
2943 * Register | BitsName
2944 * ----------|--------
2945 * PERIPH_GC | DSPI_PCLK
2946 *
2947 * @retval State of bit (1 or 0).
2948 */
2949 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
2950 {
2951 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2952 }
2953
2954 /**
2955 * @brief Enabling force to turn off the clock for PDM slave.
2956 *
2957 * Register | BitsName
2958 * ----------|--------
2959 * PERIPH_GC | PDM_PCLK
2960 *
2961 * @retval None
2962 */
2963 __STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
2964 {
2965 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_ENABLE;
2966 }
2967
2968 /**
2969 * @brief Disabling force to turn off the clock for PDM slave.
2970 *
2971 * Register | BitsName
2972 * ----------|--------
2973 * PERIPH_GC | PDM_PCLK
2974 *
2975 * @retval None
2976 */
2977 __STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
2978 {
2979 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_DISABLE;
2980 }
2981
2982 /**
2983 * @brief Indicate whether the clock for PDM is forced to close.
2984 *
2985 * Register | BitsName
2986 * ----------|--------
2987 * PERIPH_GC | PDM_PCLK
2988 *
2989 * @retval State of bit (1 or 0).
2990 */
2991 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
2992 {
2993 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2994 }
2995
2996 /**
2997 * @brief Enabling force to turn off the div4 clock for security blocks.
2998 *
2999 * Register | BitsName
3000 * ----------|--------
3001 * PERIPH_GC | I2S_HCLK
3002 *
3003 * @retval None
3004 */
3005 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
3006 {
3007 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
3008 }
3009
3010 /**
3011 * @brief Disabling force to turn off the div4 clock for security blocks.
3012 *
3013 * Register | BitsName
3014 * ----------|--------
3015 * PERIPH_GC | I2S_HCLK
3016 *
3017 * @retval None
3018 */
3019 __STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
3020 {
3021 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
3022 }
3023
3024 /**
3025 * @brief Indicate whether the div4 clock for security blocks is forced to close.
3026 *
3027 * Register | BitsName
3028 * ----------|--------
3029 * PERIPH_GC | I2S_HCLK
3030 *
3031 * @retval State of bit (1 or 0).
3032 */
3033 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
3034 {
3035 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3036 }
3037 /**
3038 * @brief Enabling force to turn off the div4 clock for xf qspi blocks.
3039 *
3040 * Register | BitsName
3041 * ----------|--------
3042 * PERIPH_GC | XQSPI_HCLK
3043 *
3044 * @retval None
3045 */
3046 __STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
3047 {
3048 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
3049 }
3050
3051 /**
3052 * @brief Disabling force to turn off the div4 clock for xf qspi blocks.
3053 *
3054 * Register | BitsName
3055 * ----------|--------
3056 * PERIPH_GC | XQSPI_HCLK
3057 *
3058 * @retval None
3059 */
3060 __STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
3061 {
3062 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
3063 }
3064
3065 /**
3066 * @brief Indicate whether the div4 clock for xf qspi blocks is forced to close.
3067 *
3068 * Register | BitsName
3069 * ----------|--------
3070 * PERIPH_GC | XQSPI_HCLK
3071 *
3072 * @retval State of bit (1 or 0).
3073 */
3074 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
3075 {
3076 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3077 }
3078
3079 /**
3080 * @brief Enabling force to turn off the clock for PWM0.
3081 *
3082 * Register | BitsName
3083 * ----------|--------
3084 * PERIPH_GC | PWM0_PCLK
3085 *
3086 * @retval None
3087 */
3088 __STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
3089 {
3090 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_ENABLE;
3091 }
3092
3093 /**
3094 * @brief Disabling force to turn off the clock for PWM0.
3095 *
3096 * Register | BitsName
3097 * ----------|--------
3098 * PERIPH_GC | PWM0_PCLK
3099 *
3100 * @retval None
3101 */
3102 __STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
3103 {
3104 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_DISABLE;
3105 }
3106
3107 /**
3108 * @brief Indicate whether the clock for PWM0 is forced to close.
3109 *
3110 * Register | BitsName
3111 * ----------|--------
3112 * PERIPH_GC | PWM0_PCLK
3113 *
3114 * @retval State of bit (1 or 0).
3115 */
3116 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
3117 {
3118 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3119 }
3120
3121 /**
3122 * @brief Enabling force to turn off the clock for PWM1.
3123 *
3124 * Register | BitsName
3125 * ----------|--------
3126 * PERIPH_GC | PWM1_PCLK
3127 *
3128 * @retval None
3129 */
3130 __STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
3131 {
3132 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_ENABLE;
3133 }
3134
3135 /**
3136 * @brief Disabling force to turn off the clock for PWM1.
3137 *
3138 * Register | BitsName
3139 * ----------|--------
3140 * PERIPH_GC | PWM1_PCLK
3141 *
3142 * @retval None
3143 */
3144 __STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
3145 {
3146 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_DISABLE;
3147 }
3148
3149 /**
3150 * @brief Indicate whether the clock for PWM1 is forced to close.
3151 *
3152 * Register | BitsName
3153 * ----------|--------
3154 * PERIPH_GC | PWM1_PCLK
3155 *
3156 * @retval State of bit (1 or 0).
3157 */
3158 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
3159 {
3160 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3161 }
3162
3163 /**
3164 * @brief Enabling force to turn off the clock for VTTBL.
3165 *
3166 * Register | BitsName
3167 * ----------|--------
3168 * PERIPH_GC | VTTBL_PCLK
3169 *
3170 * @retval None
3171 */
3172 __STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
3173 {
3174 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_ENABLE;
3175 }
3176
3177 /**
3178 * @brief Disabling force to turn off the clock for VTTBL.
3179 *
3180 * Register | BitsName
3181 * ----------|--------
3182 * PERIPH_GC | VTTBL_PCLK
3183 *
3184 * @retval None
3185 */
3186 __STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
3187 {
3188 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_DISABLE;
3189 }
3190
3191 /**
3192 * @brief Indicate whether the clock for VTTBL is forced to close.
3193 *
3194 * Register | BitsName
3195 * ----------|--------
3196 * PERIPH_GC | VTTBL_PCLK
3197 *
3198 * @retval State of bit (1 or 0).
3199 */
3200 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
3201 {
3202 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3203 }
3204
3205 /**
3206 * @brief Enabling force to turn off the clock for PSRAM ctrl.
3207 *
3208 * Register | BitsName
3209 * ----------|--------
3210 * PERIPH_GC | PSRAM_PCLK
3211 *
3212 * @retval None
3213 */
3214 __STATIC_INLINE void ll_cgc_enable_force_off_psram_pclk(void)
3215 {
3216 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PSRAM_PCLK_Pos) = CGC_CLOCK_ENABLE;
3217 }
3218
3219 /**
3220 * @brief Disabling force to turn off the clock for PSRAM ctrl.
3221 *
3222 * Register | BitsName
3223 * ----------|--------
3224 * PERIPH_GC | PSRAM_PCLK
3225 *
3226 * @retval None
3227 */
3228 __STATIC_INLINE void ll_cgc_disable_force_off_psram_pclk(void)
3229 {
3230 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PSRAM_PCLK_Pos) = CGC_CLOCK_DISABLE;
3231 }
3232
3233 /**
3234 * @brief Indicate whether the clock for PSRAM ctrl is forced to close.
3235 *
3236 * Register | BitsName
3237 * ----------|--------
3238 * PERIPH_GC | PSRAM_PCLK
3239 *
3240 * @retval State of bit (1 or 0).
3241 */
3242 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_psram_pclk(void)
3243 {
3244 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PSRAM_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3245 }
3246 /**
3247 * @brief Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
3248 *
3249 * Register | BitsName
3250 * ---------|--------
3251 * CG_LP_EN | UART_LP_SCLK
3252 * CG_LP_EN | UART_LP_PCLK
3253 * CG_LP_EN | I2S_LP
3254 * CG_LP_EN | SPIM_LP_SCLK
3255 * CG_LP_EN | SPIS_LP_SCLK
3256 * CG_LP_EN | I2C_LP_SCLK
3257 * CG_LP_EN | AHB_BUS_LP
3258 *
3259 * @param clk_mask This parameter can be a combination of the following values:
3260 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
3261 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
3262 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
3263 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
3264 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
3265 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
3266 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
3267 * @retval None
3268 */
3269 __STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
3270 {
3271 WRITE_REG(MCU_RET->MCU_PERIPH_CG_LP_EN, clk_mask);
3272 }
3273
3274 /**
3275 * @brief Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
3276 *
3277 * Register | BitsName
3278 * ---------|--------
3279 * CG_LP_EN | UART_LP_SCLK
3280 * CG_LP_EN | UART_LP_PCLK
3281 * CG_LP_EN | I2S_LP
3282 * CG_LP_EN | SPIM_LP_SCLK
3283 * CG_LP_EN | SPIS_LP_SCLK
3284 * CG_LP_EN | I2C_LP_SCLK
3285 * CG_LP_EN | AHB_BUS_LP
3286 *
3287 * @retval Returned value can be a combination of the following values:
3288 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
3289 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
3290 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
3291 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
3292 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
3293 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
3294 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
3295 */
3296 __STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
3297 {
3298 return READ_REG(MCU_RET->MCU_PERIPH_CG_LP_EN);
3299 }
3300
3301 /**
3302 * @brief Enable uart sclk low-power feature
3303 *
3304 * Register | BitsName
3305 * ---------|--------
3306 * CG_LP_EN | UART_LP_SCLK
3307 *
3308 * @retval None
3309 */
3310 __STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
3311 {
3312 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3313 }
3314
3315 /**
3316 * @brief Disable uart sclk low-power feature
3317 *
3318 * Register | BitsName
3319 * ---------|--------
3320 * CG_LP_EN | UART_LP_SCLK
3321 *
3322 * @retval None
3323 */
3324 __STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
3325 {
3326 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3327 }
3328
3329 /**
3330 * @brief Indicate whether the uart sclk low-power is enabled.
3331 *
3332 * Register | BitsName
3333 * ---------|--------
3334 * CG_LP_EN | UART_LP_SCLK
3335 *
3336 * @retval State of bit (1 or 0).
3337 */
3338 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
3339 {
3340 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3341 }
3342
3343 /**
3344 * @brief Enable uart pclk low-power feature
3345 *
3346 * Register | BitsName
3347 * ---------|--------
3348 * CG_LP_EN | UART_LP_PCLK
3349 *
3350 * @retval None
3351 */
3352 __STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
3353 {
3354 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3355 }
3356
3357 /**
3358 * @brief Disable uart pclk low-power feature
3359 *
3360 * Register | BitsName
3361 * ---------|--------
3362 * CG_LP_EN | UART_LP_PCLK
3363 *
3364 * @retval None
3365 */
3366 __STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
3367 {
3368 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3369 }
3370
3371 /**
3372 * @brief Indicate whether the uart pclk low-power is enabled.
3373 *
3374 * Register | BitsName
3375 * ---------|--------
3376 * CG_LP_EN | UART_LP_PCLK
3377 *
3378 * @retval State of bit (1 or 0).
3379 */
3380 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
3381 {
3382 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3383 }
3384
3385 /**
3386 * @brief Enable i2s low-power feature
3387 *
3388 * Register | BitsName
3389 * ---------|--------
3390 * CG_LP_EN | I2S_LP
3391 *
3392 * @retval None
3393 */
3394 __STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
3395 {
3396 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3397 }
3398
3399 /**
3400 * @brief Disable i2s low-power feature
3401 *
3402 * Register | BitsName
3403 * ---------|--------
3404 * CG_LP_EN | I2S_LP
3405 *
3406 * @retval None
3407 */
3408 __STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
3409 {
3410 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3411 }
3412
3413 /**
3414 * @brief Indicate whether the i2s low-power is enabled.
3415 *
3416 * Register | BitsName
3417 * ---------|--------
3418 * CG_LP_EN | I2S_LP
3419 *
3420 * @retval State of bit (1 or 0).
3421 */
3422 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
3423 {
3424 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3425 }
3426
3427 /**
3428 * @brief Enable spim sclk low-power feature
3429 *
3430 * Register | BitsName
3431 * ---------|--------
3432 * CG_LP_EN | SPIM_LP_SCLK
3433 *
3434 * @retval None
3435 */
3436 __STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
3437 {
3438 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3439 }
3440
3441 /**
3442 * @brief Disable spim sclk low-power feature
3443 *
3444 * Register | BitsName
3445 * ---------|--------
3446 * CG_LP_EN | SPIM_LP_SCLK
3447 *
3448 * @retval None
3449 */
3450 __STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
3451 {
3452 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3453 }
3454
3455 /**
3456 * @brief Indicate whether the spim sclk low-power is enabled.
3457 *
3458 * Register | BitsName
3459 * ---------|--------
3460 * CG_LP_EN | SPIM_LP_SCLK
3461 *
3462 * @retval State of bit (1 or 0).
3463 */
3464 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
3465 {
3466 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3467 }
3468
3469 /**
3470 * @brief Enable spis sclk low-power feature
3471 *
3472 * Register | BitsName
3473 * ---------|--------
3474 * CG_LP_EN | SPIS_LP_SCLK
3475 *
3476 * @retval None
3477 */
3478 __STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
3479 {
3480 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3481 }
3482
3483 /**
3484 * @brief Disable spis sclk low-power feature
3485 *
3486 * Register | BitsName
3487 * ---------|--------
3488 * CG_LP_EN | SPIS_LP_SCLK
3489 *
3490 * @retval None
3491 */
3492 __STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
3493 {
3494 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3495 }
3496
3497 /**
3498 * @brief Indicate whether the spis sclk low-power is enabled.
3499 *
3500 * Register | BitsName
3501 * ---------|--------
3502 * CG_LP_EN | SPIS_LP_SCLK
3503 *
3504 * @retval State of bit (1 or 0).
3505 */
3506 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
3507 {
3508 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3509 }
3510
3511 /**
3512 * @brief Enable i2c sclk low-power feature
3513 *
3514 * Register | BitsName
3515 * ---------|--------
3516 * CG_LP_EN | I2C_LP_SCLK
3517 *
3518 * @retval None
3519 */
3520 __STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
3521 {
3522 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3523 }
3524
3525 /**
3526 * @brief Disable i2c sclk low-power feature
3527 *
3528 * Register | BitsName
3529 * ---------|--------
3530 * CG_LP_EN | I2C_LP_SCLK
3531 *
3532 * @retval None
3533 */
3534 __STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
3535 {
3536 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3537 }
3538
3539 /**
3540 * @brief Indicate whether the i2c sclk low-power is enabled.
3541 *
3542 * Register | BitsName
3543 * ---------|--------
3544 * CG_LP_EN | I2C_LP_SCLK
3545 *
3546 * @retval State of bit (1 or 0).
3547 */
3548 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
3549 {
3550 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3551 }
3552
3553 /**
3554 * @brief Enable ahb bus low-power feature
3555 *
3556 * Register | BitsName
3557 * ---------|--------
3558 * CG_LP_EN | AHB_BUS_LP
3559 *
3560 * @retval None
3561 */
3562 __STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
3563 {
3564 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3565 }
3566
3567 /**
3568 * @brief Disable ahb bus low-power feature
3569 *
3570 * Register | BitsName
3571 * ---------|--------
3572 * CG_LP_EN | AHB_BUS_LP
3573 *
3574 * @retval None
3575 */
3576 __STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
3577 {
3578 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3579 }
3580
3581 /**
3582 * @brief Indicate whether the ahb bus low-power is enabled.
3583 *
3584 * Register | BitsName
3585 * ---------|--------
3586 * CG_LP_EN | AHB_BUS_LP
3587 *
3588 * @retval State of bit (1 or 0).
3589 */
3590 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
3591 {
3592 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3593 }
3594
3595 /**
3596 * @brief Enable QSPIM low-power feature
3597 *
3598 * Register | BitsName
3599 * ---------|--------
3600 * CG_LP_EN | QSPIM_LP
3601 *
3602 * @retval None
3603 */
3604 __STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
3605 {
3606 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_ENABLE;
3607 }
3608
3609 /**
3610 * @brief Disable QSPIM low-power feature
3611 *
3612 * Register | BitsName
3613 * ---------|--------
3614 * CG_LP_EN | QSPIM_LP
3615 *
3616 * @retval None
3617 */
3618 __STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
3619 {
3620 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_DISABLE;
3621 }
3622
3623 /**
3624 * @brief Indicate whether the QSPIM low-power is enabled.
3625 *
3626 * Register | BitsName
3627 * ---------|--------
3628 * CG_LP_EN | QSPIM_LP
3629 *
3630 * @retval State of bit (1 or 0).
3631 */
3632 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
3633 {
3634 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) == (CGC_CLOCK_ENABLE));
3635 }
3636
3637 /**
3638 * @brief Enable AHB2APB bus low-power feature
3639 *
3640 * Register | BitsName
3641 * ---------|--------
3642 * CG_LP_EN | AHB2APB_BUS_LP
3643 *
3644 * @retval None
3645 */
3646 __STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
3647 {
3648 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3649 }
3650
3651 /**
3652 * @brief Disable AHB2APB bus low-power feature
3653 *
3654 * Register | BitsName
3655 * ---------|--------
3656 * CG_LP_EN | AHB2APB_BUS_LP
3657 *
3658 * @retval None
3659 */
3660 __STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
3661 {
3662 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3663 }
3664
3665 /**
3666 * @brief Indicate whether the AHB2APB bus low-power is enabled.
3667 *
3668 * Register | BitsName
3669 * ---------|--------
3670 * CG_LP_EN | AHB2APB_BUS_LP
3671 *
3672 * @retval State of bit (1 or 0).
3673 */
3674 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
3675 {
3676 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3677 }
3678
3679 /**
3680 * @brief Enable ahb bus low-power feature
3681 *
3682 * Register | BitsName
3683 * ---------|--------
3684 * CG_LP_EN | AHB_BUS_LP
3685 *
3686 * @retval None
3687 */
3688 __STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
3689 {
3690 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3691 }
3692
3693 /**
3694 * @brief Disable ahb bus low-power feature
3695 *
3696 * Register | BitsName
3697 * ---------|--------
3698 * CG_LP_EN | AHB_BUS_LP
3699 *
3700 * @retval None
3701 */
3702 __STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
3703 {
3704 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3705 }
3706
3707 /**
3708 * @brief Indicate whether the ahb bus low-power is enabled.
3709 *
3710 * Register | BitsName
3711 * ---------|--------
3712 * CG_LP_EN | AHB_BUS_LP
3713 *
3714 * @retval State of bit (1 or 0).
3715 */
3716 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
3717 {
3718 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3719 }
3720
3721 /**
3722 * @brief Enable turn UART0 off during WFI/WFE
3723 *
3724 * Register | BitsName
3725 * ---------|--------
3726 * CLK_SLP_OFF | UART0_SLP
3727 *
3728 * @retval None
3729 */
3730 __STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
3731 {
3732 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_ENABLE;
3733 }
3734
3735 /**
3736 * @brief Disable turn UART0 off during WFI/WFE
3737 *
3738 * Register | BitsName
3739 * ---------|--------
3740 * CLK_SLP_OFF | UART0_SLP
3741 *
3742 * @retval None
3743 */
3744 __STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
3745 {
3746 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_DISABLE;
3747 }
3748
3749 /**
3750 * @brief Indicate whether turn UART0 off during WFI/WFE is enabled.
3751 *
3752 * Register | BitsName
3753 * ---------|--------
3754 * CLK_SLP_OFF | UART0_SLP
3755 *
3756 * @retval State of bit (1 or 0).
3757 */
3758 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
3759 {
3760 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) == (CGC_CLOCK_ENABLE));
3761 }
3762
3763 /**
3764 * @brief Enable turn UART1 off during WFI/WFE
3765 *
3766 * Register | BitsName
3767 * ---------|--------
3768 * CLK_SLP_OFF | UART1_SLP
3769 *
3770 * @retval None
3771 */
3772 __STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
3773 {
3774 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_ENABLE;
3775 }
3776
3777 /**
3778 * @brief Disable turn UART1 off during WFI/WFE
3779 *
3780 * Register | BitsName
3781 * ---------|--------
3782 * CLK_SLP_OFF | UART1_SLP
3783 *
3784 * @retval None
3785 */
3786 __STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
3787 {
3788 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_DISABLE;
3789 }
3790
3791 /**
3792 * @brief Indicate whether turn UART1 off during WFI/WFE is enabled.
3793 *
3794 * Register | BitsName
3795 * ---------|--------
3796 * CLK_SLP_OFF | UART1_SLP
3797 *
3798 * @retval State of bit (1 or 0).
3799 */
3800 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
3801 {
3802 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) == (CGC_CLOCK_ENABLE));
3803 }
3804
3805 /**
3806 * @brief Enable turn UART2 off during WFI/WFE
3807 *
3808 * Register | BitsName
3809 * ---------|--------
3810 * CLK_SLP_OFF | UART2_SLP
3811 *
3812 * @retval None
3813 */
3814 __STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
3815 {
3816 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_ENABLE;
3817 }
3818
3819 /**
3820 * @brief Disable turn UART2 off during WFI/WFE
3821 *
3822 * Register | BitsName
3823 * ---------|--------
3824 * CLK_SLP_OFF | UART2_SLP
3825 *
3826 * @retval None
3827 */
3828 __STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
3829 {
3830 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_DISABLE;
3831 }
3832
3833 /**
3834 * @brief Indicate whether turn UART2 off during WFI/WFE is enabled.
3835 *
3836 * Register | BitsName
3837 * ---------|--------
3838 * CLK_SLP_OFF | UART2_SLP
3839 *
3840 * @retval State of bit (1 or 0).
3841 */
3842 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
3843 {
3844 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) == (CGC_CLOCK_ENABLE));
3845 }
3846
3847 /**
3848 * @brief Enable turn UART3 off during WFI/WFE
3849 *
3850 * Register | BitsName
3851 * ---------|--------
3852 * CLK_SLP_OFF | UART3_SLP
3853 *
3854 * @retval None
3855 */
3856 __STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
3857 {
3858 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_ENABLE;
3859 }
3860
3861 /**
3862 * @brief Disable turn UART3 off during WFI/WFE
3863 *
3864 * Register | BitsName
3865 * ---------|--------
3866 * CLK_SLP_OFF | UART3_SLP
3867 *
3868 * @retval None
3869 */
3870 __STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
3871 {
3872 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_DISABLE;
3873 }
3874
3875 /**
3876 * @brief Indicate whether turn UART3 off during WFI/WFE is enabled.
3877 *
3878 * Register | BitsName
3879 * ---------|--------
3880 * CLK_SLP_OFF | UART3_SLP
3881 *
3882 * @retval State of bit (1 or 0).
3883 */
3884 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
3885 {
3886 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) == (CGC_CLOCK_ENABLE));
3887 }
3888
3889 /**
3890 * @brief Enable turn UART4 off during WFI/WFE
3891 *
3892 * Register | BitsName
3893 * ---------|--------
3894 * CLK_SLP_OFF | UART4_SLP
3895 *
3896 * @retval None
3897 */
3898 __STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
3899 {
3900 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) = CGC_CLOCK_ENABLE;
3901 }
3902
3903 /**
3904 * @brief Disable turn UART4 off during WFI/WFE
3905 *
3906 * Register | BitsName
3907 * ---------|--------
3908 * CLK_SLP_OFF | UART4_SLP
3909 *
3910 * @retval None
3911 */
3912 __STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
3913 {
3914 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) = CGC_CLOCK_DISABLE;
3915 }
3916
3917 /**
3918 * @brief Indicate whether turn UART4 off during WFI/WFE is enabled.
3919 *
3920 * Register | BitsName
3921 * ---------|--------
3922 * CLK_SLP_OFF | UART4_SLP
3923 *
3924 * @retval State of bit (1 or 0).
3925 */
3926 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
3927 {
3928 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) == (CGC_CLOCK_ENABLE));
3929 }
3930
3931 /**
3932 * @brief Enable turn UART5 off during WFI/WFE
3933 *
3934 * Register | BitsName
3935 * ---------|--------
3936 * CLK_SLP_OFF | UART5_SLP
3937 *
3938 * @retval None
3939 */
3940 __STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
3941 {
3942 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) = CGC_CLOCK_ENABLE;
3943 }
3944
3945 /**
3946 * @brief Disable turn UART5 off during WFI/WFE
3947 *
3948 * Register | BitsName
3949 * ---------|--------
3950 * CLK_SLP_OFF | UART5_SLP
3951 *
3952 * @retval None
3953 */
3954 __STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
3955 {
3956 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) = CGC_CLOCK_DISABLE;
3957 }
3958
3959 /**
3960 * @brief Indicate whether turn UART5 off during WFI/WFE is enabled.
3961 *
3962 * Register | BitsName
3963 * ---------|--------
3964 * CLK_SLP_OFF | UART5_SLP
3965 *
3966 * @retval State of bit (1 or 0).
3967 */
3968 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
3969 {
3970 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) == (CGC_CLOCK_ENABLE));
3971 }
3972
3973 /**
3974 * @brief Enable turn I2C0 off during WFI/WFE
3975 *
3976 * Register | BitsName
3977 * ---------|--------
3978 * CLK_SLP_OFF | I2C0_SLP
3979 *
3980 * @retval None
3981 */
3982 __STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
3983 {
3984 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_ENABLE;
3985 }
3986
3987 /**
3988 * @brief Disable turn I2C0 off during WFI/WFE
3989 *
3990 * Register | BitsName
3991 * ---------|--------
3992 * CLK_SLP_OFF | I2C0_SLP
3993 *
3994 * @retval None
3995 */
3996 __STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
3997 {
3998 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_DISABLE;
3999 }
4000
4001 /**
4002 * @brief Indicate whether turn I2C0 off during WFI/WFE is enabled.
4003 *
4004 * Register | BitsName
4005 * ---------|--------
4006 * CLK_SLP_OFF | I2C0_SLP
4007 *
4008 * @retval State of bit (1 or 0).
4009 */
4010 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
4011 {
4012 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) == (CGC_CLOCK_ENABLE));
4013 }
4014
4015 /**
4016 * @brief Enable turn I2C1 off during WFI/WFE
4017 *
4018 * Register | BitsName
4019 * ---------|--------
4020 * CLK_SLP_OFF | I2C1_SLP
4021 *
4022 * @retval None
4023 */
4024 __STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
4025 {
4026 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_ENABLE;
4027 }
4028
4029 /**
4030 * @brief Disable turn I2C1 off during WFI/WFE
4031 *
4032 * Register | BitsName
4033 * ---------|--------
4034 * CLK_SLP_OFF | I2C1_SLP
4035 *
4036 * @retval None
4037 */
4038 __STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
4039 {
4040 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_DISABLE;
4041 }
4042
4043 /**
4044 * @brief Indicate whether turn I2C1 off during WFI/WFE is enabled.
4045 *
4046 * Register | BitsName
4047 * ---------|--------
4048 * CLK_SLP_OFF | I2C1_SLP
4049 *
4050 * @retval State of bit (1 or 0).
4051 */
4052 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
4053 {
4054 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) == (CGC_CLOCK_ENABLE));
4055 }
4056
4057 /**
4058 * @brief Enable turn I2C2 off during WFI/WFE
4059 *
4060 * Register | BitsName
4061 * ---------|--------
4062 * CLK_SLP_OFF | I2C2_SLP
4063 *
4064 * @retval None
4065 */
4066 __STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
4067 {
4068 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_ENABLE;
4069 }
4070
4071 /**
4072 * @brief Disable turn I2C2 off during WFI/WFE
4073 *
4074 * Register | BitsName
4075 * ---------|--------
4076 * CLK_SLP_OFF | I2C2_SLP
4077 *
4078 * @retval None
4079 */
4080 __STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
4081 {
4082 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_DISABLE;
4083 }
4084
4085 /**
4086 * @brief Indicate whether turn I2C2 off during WFI/WFE is enabled.
4087 *
4088 * Register | BitsName
4089 * ---------|--------
4090 * CLK_SLP_OFF | I2C2_SLP
4091 *
4092 * @retval State of bit (1 or 0).
4093 */
4094 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
4095 {
4096 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) == (CGC_CLOCK_ENABLE));
4097 }
4098
4099 /**
4100 * @brief Enable turn I2C3 off during WFI/WFE
4101 *
4102 * Register | BitsName
4103 * ---------|--------
4104 * CLK_SLP_OFF | I2C3_SLP
4105 *
4106 * @retval None
4107 */
4108 __STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
4109 {
4110 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_ENABLE;
4111 }
4112
4113 /**
4114 * @brief Disable turn I2C3 off during WFI/WFE
4115 *
4116 * Register | BitsName
4117 * ---------|--------
4118 * CLK_SLP_OFF | I2C3_SLP
4119 *
4120 * @retval None
4121 */
4122 __STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
4123 {
4124 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_DISABLE;
4125 }
4126
4127 /**
4128 * @brief Indicate whether turn I2C3 off during WFI/WFE is enabled.
4129 *
4130 * Register | BitsName
4131 * ---------|--------
4132 * CLK_SLP_OFF | I2C3_SLP
4133 *
4134 * @retval State of bit (1 or 0).
4135 */
4136 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
4137 {
4138 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) == (CGC_CLOCK_ENABLE));
4139 }
4140
4141 /**
4142 * @brief Enable turn I2C4 off during WFI/WFE
4143 *
4144 * Register | BitsName
4145 * ---------|--------
4146 * CLK_SLP_OFF | I2C4_SLP
4147 *
4148 * @retval None
4149 */
4150 __STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
4151 {
4152 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) = CGC_CLOCK_ENABLE;
4153 }
4154
4155 /**
4156 * @brief Disable turn I2C4 off during WFI/WFE
4157 *
4158 * Register | BitsName
4159 * ---------|--------
4160 * CLK_SLP_OFF | I2C4_SLP
4161 *
4162 * @retval None
4163 */
4164 __STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
4165 {
4166 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) = CGC_CLOCK_DISABLE;
4167 }
4168
4169 /**
4170 * @brief Indicate whether turn I2C4 off during WFI/WFE is enabled.
4171 *
4172 * Register | BitsName
4173 * ---------|--------
4174 * CLK_SLP_OFF | I2C4_SLP
4175 *
4176 * @retval State of bit (1 or 0).
4177 */
4178 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
4179 {
4180 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) == (CGC_CLOCK_ENABLE));
4181 }
4182
4183 /**
4184 * @brief Enable turn I2C5 off during WFI/WFE
4185 *
4186 * Register | BitsName
4187 * ---------|--------
4188 * CLK_SLP_OFF | I2C5_SLP
4189 *
4190 * @retval None
4191 */
4192 __STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
4193 {
4194 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) = CGC_CLOCK_ENABLE;
4195 }
4196
4197 /**
4198 * @brief Disable turn I2C5 off during WFI/WFE
4199 *
4200 * Register | BitsName
4201 * ---------|--------
4202 * CLK_SLP_OFF | I2C5_SLP
4203 *
4204 * @retval None
4205 */
4206 __STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
4207 {
4208 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) = CGC_CLOCK_DISABLE;
4209 }
4210
4211 /**
4212 * @brief Indicate whether turn I2C5 off during WFI/WFE is enabled.
4213 *
4214 * Register | BitsName
4215 * ---------|--------
4216 * CLK_SLP_OFF | I2C5_SLP
4217 *
4218 * @retval State of bit (1 or 0).
4219 */
4220 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
4221 {
4222 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) == (CGC_CLOCK_ENABLE));
4223 }
4224
4225 /**
4226 * @brief Enable turn I2S_M off during WFI/WFE
4227 *
4228 * Register | BitsName
4229 * ---------|--------
4230 * CLK_SLP_OFF | I2SM_SLP
4231 *
4232 * @retval None
4233 */
4234 __STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
4235 {
4236 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_ENABLE;
4237 }
4238
4239 /**
4240 * @brief Disable turn I2S_M off during WFI/WFE
4241 *
4242 * Register | BitsName
4243 * ---------|--------
4244 * CLK_SLP_OFF | I2SM_SLP
4245 *
4246 * @retval None
4247 */
4248 __STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
4249 {
4250 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_DISABLE;
4251 }
4252
4253 /**
4254 * @brief Indicate whether turn I2S_M off during WFI/WFE is enabled.
4255 *
4256 * Register | BitsName
4257 * ---------|--------
4258 * CLK_SLP_OFF | I2SM_SLP
4259 *
4260 * @retval State of bit (1 or 0).
4261 */
4262 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
4263 {
4264 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) == (CGC_CLOCK_ENABLE));
4265 }
4266
4267 /**
4268 * @brief Enable turn I2S_S off during WFI/WFE
4269 *
4270 * Register | BitsName
4271 * ---------|--------
4272 * CLK_SLP_OFF | I2SS_SLP
4273 *
4274 * @retval None
4275 */
4276 __STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
4277 {
4278 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_ENABLE;
4279 }
4280
4281 /**
4282 * @brief Disable turn I2S_S off during WFI/WFE
4283 *
4284 * Register | BitsName
4285 * ---------|--------
4286 * CLK_SLP_OFF | I2SS_SLP
4287 *
4288 * @retval None
4289 */
4290 __STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
4291 {
4292 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_DISABLE;
4293 }
4294
4295 /**
4296 * @brief Indicate whether turn I2S_S off during WFI/WFE is enabled.
4297 *
4298 * Register | BitsName
4299 * ---------|--------
4300 * CLK_SLP_OFF | I2SS_SLP
4301 *
4302 * @retval State of bit (1 or 0).
4303 */
4304 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
4305 {
4306 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) == (CGC_CLOCK_ENABLE));
4307 }
4308
4309 /**
4310 * @brief Enable turn SPI_M off during WFI/WFE
4311 *
4312 * Register | BitsName
4313 * ---------|--------
4314 * CLK_SLP_OFF | SPIM_SLP
4315 *
4316 * @retval None
4317 */
4318 __STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
4319 {
4320 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_ENABLE;
4321 }
4322
4323 /**
4324 * @brief Disable turn SPI_M off during WFI/WFE
4325 *
4326 * Register | BitsName
4327 * ---------|--------
4328 * CLK_SLP_OFF | SPIM_SLP
4329 *
4330 * @retval None
4331 */
4332 __STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
4333 {
4334 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_DISABLE;
4335 }
4336
4337 /**
4338 * @brief Indicate whether turn SPI_M off during WFI/WFE is enabled.
4339 *
4340 * Register | BitsName
4341 * ---------|--------
4342 * CLK_SLP_OFF | SPIM_SLP
4343 *
4344 * @retval State of bit (1 or 0).
4345 */
4346 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
4347 {
4348 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) == (CGC_CLOCK_ENABLE));
4349 }
4350
4351 /**
4352 * @brief Enable turn SPI_S off during WFI/WFE
4353 *
4354 * Register | BitsName
4355 * ---------|--------
4356 * CLK_SLP_OFF | SPIS_SLP
4357 *
4358 * @retval None
4359 */
4360 __STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
4361 {
4362 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_ENABLE;
4363 }
4364
4365 /**
4366 * @brief Disable turn SPI_S off during WFI/WFE
4367 *
4368 * Register | BitsName
4369 * ---------|--------
4370 * CLK_SLP_OFF | SPIS_SLP
4371 *
4372 * @retval None
4373 */
4374 __STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
4375 {
4376 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_DISABLE;
4377 }
4378
4379 /**
4380 * @brief Indicate whether turn SPI_S off during WFI/WFE is enabled.
4381 *
4382 * Register | BitsName
4383 * ---------|--------
4384 * CLK_SLP_OFF | SPIS_SLP
4385 *
4386 * @retval State of bit (1 or 0).
4387 */
4388 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
4389 {
4390 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) == (CGC_CLOCK_ENABLE));
4391 }
4392
4393 /**
4394 * @brief Enable turn pwm0 off during WFI/WFE
4395 *
4396 * Register | BitsName
4397 * ---------|--------
4398 * CLK_SLP_OFF | PWM0_SLP
4399 *
4400 * @retval None
4401 */
4402 __STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
4403 {
4404 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_ENABLE;
4405 }
4406
4407 /**
4408 * @brief Disable turn pwm0 off during WFI/WFE
4409 *
4410 * Register | BitsName
4411 * ---------|--------
4412 * CLK_SLP_OFF | PWM0_SLP
4413 *
4414 * @retval None
4415 */
4416 __STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
4417 {
4418 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_DISABLE;
4419 }
4420
4421 /**
4422 * @brief Indicate whether turn pwm0 off during WFI/WFE is enabled.
4423 *
4424 * Register | BitsName
4425 * ---------|--------
4426 * CLK_SLP_OFF | PWM0_SLP
4427 *
4428 * @retval State of bit (1 or 0).
4429 */
4430 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
4431 {
4432 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) == (CGC_CLOCK_ENABLE));
4433 }
4434
4435 /**
4436 * @brief Enable turn pwm1 off during WFI/WFE
4437 *
4438 * Register | BitsName
4439 * ---------|--------
4440 * CLK_SLP_OFF | PWM1_SLP
4441 *
4442 * @retval None
4443 */
4444 __STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
4445 {
4446 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_ENABLE;
4447 }
4448
4449 /**
4450 * @brief Disable turn pwm1 off during WFI/WFE
4451 *
4452 * Register | BitsName
4453 * ---------|--------
4454 * CLK_SLP_OFF | PWM1_SLP
4455 *
4456 * @retval None
4457 */
4458 __STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
4459 {
4460 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_DISABLE;
4461 }
4462
4463 /**
4464 * @brief Indicate whether turn pwm1 off during WFI/WFE is enabled.
4465 *
4466 * Register | BitsName
4467 * ---------|--------
4468 * CLK_SLP_OFF | PWM1_SLP
4469 *
4470 * @retval State of bit (1 or 0).
4471 */
4472 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
4473 {
4474 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) == (CGC_CLOCK_ENABLE));
4475 }
4476
4477 /**
4478 * @brief Enable turn QSPIM0 off during WFI/WFE
4479 *
4480 * Register | BitsName
4481 * ---------|--------
4482 * CLK_SLP_OFF | QSPIM0_SLP
4483 *
4484 * @retval None
4485 */
4486 __STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
4487 {
4488 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_ENABLE;
4489 }
4490
4491 /**
4492 * @brief Disable turn QSPIM0 off during WFI/WFE
4493 *
4494 * Register | BitsName
4495 * ---------|--------
4496 * CLK_SLP_OFF | QSPIM0_SLP
4497 *
4498 * @retval None
4499 */
4500 __STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
4501 {
4502 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_DISABLE;
4503 }
4504
4505 /**
4506 * @brief Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
4507 *
4508 * Register | BitsName
4509 * ---------|--------
4510 * CLK_SLP_OFF | QSPIM0_SLP
4511 *
4512 * @retval State of bit (1 or 0).
4513 */
4514 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
4515 {
4516 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) == (CGC_CLOCK_ENABLE));
4517 }
4518
4519 /**
4520 * @brief Enable turn QSPIM1 off during WFI/WFE
4521 *
4522 * Register | BitsName
4523 * ---------|--------
4524 * CLK_SLP_OFF | QSPIM1_SLP
4525 *
4526 * @retval None
4527 */
4528 __STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
4529 {
4530 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_ENABLE;
4531 }
4532
4533 /**
4534 * @brief Disable turn QSPIM1 off during WFI/WFE
4535 *
4536 * Register | BitsName
4537 * ---------|--------
4538 * CLK_SLP_OFF | QSPIM1_SLP
4539 *
4540 * @retval None
4541 */
4542 __STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
4543 {
4544 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_DISABLE;
4545 }
4546
4547 /**
4548 * @brief Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
4549 *
4550 * Register | BitsName
4551 * ---------|--------
4552 * CLK_SLP_OFF | QSPIM1_SLP
4553 *
4554 * @retval State of bit (1 or 0).
4555 */
4556 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
4557 {
4558 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) == (CGC_CLOCK_ENABLE));
4559 }
4560
4561 /**
4562 * @brief Enable turn QSPIM2 off during WFI/WFE
4563 *
4564 * Register | BitsName
4565 * ---------|--------
4566 * CLK_SLP_OFF | QSPIM2_SLP
4567 *
4568 * @retval None
4569 */
4570 __STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
4571 {
4572 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_ENABLE;
4573 }
4574
4575 /**
4576 * @brief Disable turn QSPIM2 off during WFI/WFE
4577 *
4578 * Register | BitsName
4579 * ---------|--------
4580 * CLK_SLP_OFF | QSPIM2_SLP
4581 *
4582 * @retval None
4583 */
4584 __STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
4585 {
4586 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_DISABLE;
4587 }
4588
4589 /**
4590 * @brief Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
4591 *
4592 * Register | BitsName
4593 * ---------|--------
4594 * CLK_SLP_OFF | QSPIM2_SLP
4595 *
4596 * @retval State of bit (1 or 0).
4597 */
4598 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
4599 {
4600 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) == (CGC_CLOCK_ENABLE));
4601 }
4602
4603 /**
4604 * @brief Enable turn DSPI off during WFI/WFE
4605 *
4606 * Register | BitsName
4607 * ---------|--------
4608 * CLK_SLP_OFF | DSPI_SLP
4609 *
4610 * @retval None
4611 */
4612 __STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
4613 {
4614 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_ENABLE;
4615 }
4616
4617 /**
4618 * @brief Disable turn DSPI off during WFI/WFE
4619 *
4620 * Register | BitsName
4621 * ---------|--------
4622 * CLK_SLP_OFF | DSPI_SLP
4623 *
4624 * @retval None
4625 */
4626 __STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
4627 {
4628 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_DISABLE;
4629 }
4630
4631 /**
4632 * @brief Indicate whether turn DSPI off during WFI/WFE is enabled.
4633 *
4634 * Register | BitsName
4635 * ---------|--------
4636 * CLK_SLP_OFF | DSPI_SLP
4637 *
4638 * @retval State of bit (1 or 0).
4639 */
4640 __STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
4641 {
4642 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) == (CGC_CLOCK_ENABLE));
4643 }
4644
4645 /**
4646 * @brief Enable turn PDM off during WFI/WFE
4647 *
4648 * Register | BitsName
4649 * ---------|--------
4650 * CLK_SLP_OFF | PDM_SLP
4651 *
4652 * @retval None
4653 */
4654 __STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
4655 {
4656 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_ENABLE;
4657 }
4658
4659 /**
4660 * @brief Disable turn PDM off during WFI/WFE
4661 *
4662 * Register | BitsName
4663 * ---------|--------
4664 * CLK_SLP_OFF | PDM_SLP
4665 *
4666 * @retval None
4667 */
4668 __STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
4669 {
4670 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_DISABLE;
4671 }
4672
4673 /**
4674 * @brief Indicate whether turn PDM off during WFI/WFE is enabled.
4675 *
4676 * Register | BitsName
4677 * ---------|--------
4678 * CLK_SLP_OFF | PDM_SLP
4679 *
4680 * @retval State of bit (1 or 0).
4681 */
4682 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
4683 {
4684 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) == (CGC_CLOCK_ENABLE));
4685 }
4686
4687 /**
4688 * @brief Individual block's clock control inside security system which was forced to turn off (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4689 *
4690 * Register | BitsName
4691 * ----------|--------
4692 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4693 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4694 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4695 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4696 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4697 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4698 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4699 *
4700 * @param clk_mask This parameter can be a combination of the following values:
4701 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4702 * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4703 * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4704 * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4705 * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4706 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4707 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4708 * @retval None
4709 */
4710 __STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
4711 {
4712 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
4713 }
4714
4715 /**
4716 * @brief Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4717 *
4718 * Register | BitsName
4719 * ----------|--------
4720 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4721 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4722 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4723 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4724 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4725 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4726 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4727 *
4728 * @retval Returned value can be a combination of the following values:
4729 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4730 * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4731 * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4732 * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4733 * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4734 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4735 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4736 */
4737 __STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
4738 {
4739 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
4740 }
4741
4742 /**
4743 * @brief Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4744 *
4745 * Register | BitsName
4746 * ----------|--------
4747 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4748 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4749 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4750 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4751 *
4752 * @param clk_mask This parameter can be a combination of the following values:
4753 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4754 * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4755 * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4756 * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4757 * @retval None
4758 */
4759 __STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
4760 {
4761 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
4762 }
4763
4764 /**
4765 * @brief Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4766 *
4767 * Register | BitsName
4768 * ----------|--------
4769 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4770 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4771 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4772 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4773 *
4774 * @retval Returned value can be a combination of the following values:
4775 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4776 * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4777 * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4778 * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4779 */
4780 __STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
4781 {
4782 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
4783 }
4784
4785 /**
4786 * @brief Enabling force to turn off the clock for AES.
4787 *
4788 * Register | BitsName
4789 * ----------|--------
4790 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4791 *
4792 * @retval None
4793 */
4794 __STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
4795 {
4796 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4797 }
4798
4799 /**
4800 * @brief Disabling force to turn off the clock for AES.
4801 *
4802 * Register | BitsName
4803 * ----------|--------
4804 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4805 *
4806 * @retval None
4807 */
4808 __STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
4809 {
4810 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4811 }
4812
4813 /**
4814 * @brief Indicate whether the clock for AES is forced to close.
4815 *
4816 * Register | BitsName
4817 * ----------|--------
4818 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4819 *
4820 * @retval State of bit (1 or 0).
4821 */
4822 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
4823 {
4824 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4825 }
4826
4827 /**
4828 * @brief Enabling force to turn off the clock for HMAC.
4829 *
4830 * Register | BitsName
4831 * ----------|--------
4832 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4833 *
4834 * @retval None
4835 */
4836 __STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
4837 {
4838 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4839 }
4840
4841 /**
4842 * @brief Disabling force to turn off the clock for HMAC.
4843 *
4844 * Register | BitsName
4845 * ----------|--------
4846 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4847 *
4848 * @retval None
4849 */
4850 __STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
4851 {
4852 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4853 }
4854
4855 /**
4856 * @brief Indicate whether the clock for HMAC is forced to close.
4857 *
4858 * Register | BitsName
4859 * ----------|--------
4860 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4861 *
4862 * @retval State of bit (1 or 0).
4863 */
4864 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
4865 {
4866 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4867 }
4868
4869 /**
4870 * @brief Enabling force to turn off the clock for PKC.
4871 *
4872 * Register | BitsName
4873 * ----------|--------
4874 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4875 *
4876 * @retval None
4877 */
4878 __STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
4879 {
4880 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4881 }
4882
4883 /**
4884 * @brief Disabling force to turn off the clock for PKC.
4885 *
4886 * Register | BitsName
4887 * ----------|--------
4888 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4889 *
4890 * @retval None
4891 */
4892 __STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
4893 {
4894 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4895 }
4896
4897 /**
4898 * @brief Indicate whether the clock for PKC is forced to close.
4899 *
4900 * Register | BitsName
4901 * ----------|--------
4902 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4903 *
4904 * @retval State of bit (1 or 0).
4905 */
4906 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
4907 {
4908 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4909 }
4910
4911 /**
4912 * @brief Enabling force to turn off the clock for PRESENT.
4913 *
4914 * Register | BitsName
4915 * ----------|--------
4916 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4917 *
4918 * @retval None
4919 */
4920 __STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
4921 {
4922 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4923 }
4924
4925 /**
4926 * @brief Disabling force to turn off the clock for PRESENT.
4927 *
4928 * Register | BitsName
4929 * ----------|--------
4930 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4931 *
4932 * @retval None
4933 */
4934 __STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
4935 {
4936 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4937 }
4938
4939 /**
4940 * @brief Indicate whether the clock for PRESENT is forced to close.
4941 *
4942 * Register | BitsName
4943 * ----------|--------
4944 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4945 *
4946 * @retval State of bit (1 or 0).
4947 */
4948 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
4949 {
4950 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4951 }
4952
4953 /**
4954 * @brief Enabling force to turn off the clock for RAMKEY.
4955 *
4956 * Register | BitsName
4957 * ----------|--------
4958 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4959 *
4960 * @retval None
4961 */
4962 __STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
4963 {
4964 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4965 }
4966
4967 /**
4968 * @brief Disabling force to turn off the clock for RAMKEY.
4969 *
4970 * Register | BitsName
4971 * ----------|--------
4972 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4973 *
4974 * @retval None
4975 */
4976 __STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
4977 {
4978 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4979 }
4980
4981 /**
4982 * @brief Indicate whether the clock for RAMKEY is forced to close.
4983 *
4984 * Register | BitsName
4985 * ----------|--------
4986 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4987 *
4988 * @retval State of bit (1 or 0).
4989 */
4990 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
4991 {
4992 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4993 }
4994
4995
4996 /**
4997 * @brief Enabling force to turn off the clock for RNG.
4998 *
4999 * Register | BitsName
5000 * ----------|--------
5001 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
5002 *
5003 * @retval None
5004 */
5005 __STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
5006 {
5007 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
5008 }
5009
5010 /**
5011 * @brief Disabling force to turn off the clock for RNG.
5012 *
5013 * Register | BitsName
5014 * ----------|--------
5015 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
5016 *
5017 * @retval None
5018 */
5019 __STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
5020 {
5021 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
5022 }
5023
5024 /**
5025 * @brief Indicate whether the clock for RNG is forced to close.
5026 *
5027 * Register | BitsName
5028 * ----------|--------
5029 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
5030 *
5031 * @retval State of bit (1 or 0).
5032 */
5033 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
5034 {
5035 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
5036 }
5037
5038 /**
5039 * @brief Enabling force to turn off the clock for EFUSE.
5040 *
5041 * Register | BitsName
5042 * ----------|--------
5043 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5044 *
5045 * @retval None
5046 */
5047 __STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
5048 {
5049 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
5050 }
5051
5052 /**
5053 * @brief Disabling force to turn off the clock for EFUSE.
5054 *
5055 * Register | BitsName
5056 * ----------|--------
5057 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5058 *
5059 * @retval None
5060 */
5061 __STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
5062 {
5063 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
5064 }
5065
5066 /**
5067 * @brief Indicate whether the clock for EFUSE is forced to close.
5068 *
5069 * Register | BitsName
5070 * ----------|--------
5071 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5072 *
5073 * @retval State of bit (1 or 0).
5074 */
5075 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
5076 {
5077 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
5078 }
5079
5080 /**
5081 * @brief Enable AES automatic turn off clock during WFI/WFE
5082 *
5083 * Register | BitsName
5084 * ----------|--------
5085 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5086 *
5087 * @retval None
5088 */
5089 __STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
5090 {
5091 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5092 }
5093
5094 /**
5095 * @brief Disable AES automatic turn off clock during WFI/WFE
5096 *
5097 * Register | BitsName
5098 * ----------|--------
5099 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5100 *
5101 * @retval None
5102 */
5103 __STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
5104 {
5105 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5106 }
5107
5108 /**
5109 * @brief Indicate whether the AES automatic turn off clock is enabled.
5110 *
5111 * Register | BitsName
5112 * ----------|--------
5113 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5114 *
5115 * @retval State of bit (1 or 0).
5116 */
5117 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
5118 {
5119 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5120 }
5121
5122 /**
5123 * @brief Enable HMAC automatic turn off clock during WFI/WFE
5124 *
5125 * Register | BitsName
5126 * ----------|--------
5127 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5128 *
5129 * @retval None
5130 */
5131 __STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
5132 {
5133 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5134 }
5135
5136 /**
5137 * @brief Disable HMAC automatic turn off clock during WFI/WFE
5138 *
5139 * Register | BitsName
5140 * ----------|--------
5141 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5142 *
5143 * @retval None
5144 */
5145 __STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
5146 {
5147 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5148 }
5149
5150 /**
5151 * @brief Indicate whether the HMAC automatic turn off clock is enabled.
5152 *
5153 * Register | BitsName
5154 * ----------|--------
5155 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5156 *
5157 * @retval State of bit (1 or 0).
5158 */
5159 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
5160 {
5161 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5162 }
5163
5164 /**
5165 * @brief Enable PKC automatic turn off clock during WFI/WFE
5166 *
5167 * Register | BitsName
5168 * ----------|--------
5169 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5170 *
5171 * @retval None
5172 */
5173 __STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
5174 {
5175 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5176 }
5177
5178 /**
5179 * @brief Disable PKC automatic turn off clock during WFI/WFE
5180 *
5181 * Register | BitsName
5182 * ----------|--------
5183 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5184 *
5185 * @retval None
5186 */
5187 __STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
5188 {
5189 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5190 }
5191
5192 /**
5193 * @brief Indicate whether the PKC automatic turn off clock is enabled.
5194 *
5195 * Register | BitsName
5196 * ----------|--------
5197 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5198 *
5199 * @retval State of bit (1 or 0).
5200 */
5201 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
5202 {
5203 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5204 }
5205
5206 /**
5207 * @brief Enable PRESENT automatic turn off clock during WFI/WFE
5208 *
5209 * Register | BitsName
5210 * ----------|--------
5211 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5212 *
5213 * @retval None
5214 */
5215 __STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
5216 {
5217 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5218 }
5219
5220 /**
5221 * @brief Disable PRESENT automatic turn off clock during WFI/WFE
5222 *
5223 * Register | BitsName
5224 * ----------|--------
5225 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5226 *
5227 * @retval None
5228 */
5229 __STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
5230 {
5231 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5232 }
5233
5234 /**
5235 * @brief Indicate whether the PRESENT automatic turn off clock is enabled.
5236 *
5237 * Register | BitsName
5238 * ----------|--------
5239 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5240 *
5241 * @retval State of bit (1 or 0).
5242 */
5243 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
5244 {
5245 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5246 }
5247
5248 /**
5249 * @brief Enable RAMKEY automatic turn off clock during WFI/WFE
5250 *
5251 * Register | BitsName
5252 * ----------|--------
5253 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5254 *
5255 * @retval None
5256 */
5257 __STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
5258 {
5259 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5260 }
5261
5262 /**
5263 * @brief Disable RAMKEY automatic turn off clock during WFI/WFE
5264 *
5265 * Register | BitsName
5266 * ----------|--------
5267 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5268 *
5269 * @retval None
5270 */
5271 __STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
5272 {
5273 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5274 }
5275
5276 /**
5277 * @brief Indicate whether the RAMKEY automatic turn off clock is enabled.
5278 *
5279 * Register | BitsName
5280 * ----------|--------
5281 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5282 *
5283 * @retval State of bit (1 or 0).
5284 */
5285 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
5286 {
5287 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5288 }
5289
5290 /**
5291 * @brief Enable RNG automatic turn off clock during WFI/WFE
5292 *
5293 * Register | BitsName
5294 * ----------|--------
5295 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5296 *
5297 * @retval None
5298 */
5299 __STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
5300 {
5301 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5302 }
5303
5304 /**
5305 * @brief Disable RNG automatic turn off clock during WFI/WFE
5306 *
5307 * Register | BitsName
5308 * ----------|--------
5309 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5310 *
5311 * @retval None
5312 */
5313 __STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
5314 {
5315 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5316 }
5317
5318 /**
5319 * @brief Indicate whether the RNG automatic turn off clock is enabled.
5320 *
5321 * Register | BitsName
5322 * ----------|--------
5323 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5324 *
5325 * @retval State of bit (1 or 0).
5326 */
5327 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
5328 {
5329 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5330 }
5331
5332 /**
5333 * @brief Enable EFUSE automatic turn off clock during WFI/WFE
5334 *
5335 * Register | BitsName
5336 * ----------|--------
5337 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5338 *
5339 * @retval None
5340 */
5341 __STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
5342 {
5343 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5344 }
5345
5346 /**
5347 * @brief Disable EFUSE automatic turn off clock during WFI/WFE
5348 *
5349 * Register | BitsName
5350 * ----------|--------
5351 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5352 *
5353 * @retval None
5354 */
5355 __STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
5356 {
5357 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5358 }
5359
5360 /**
5361 * @brief Indicate whether the EFUSE automatic turn off clock is enabled.
5362 *
5363 * Register | BitsName
5364 * ----------|--------
5365 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5366 *
5367 * @retval State of bit (1 or 0).
5368 */
5369 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
5370 {
5371 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5372 }
5373
5374 /**
5375 * @brief Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
5376 *
5377 * Register | BitsName
5378 * ----------|--------
5379 * MCU_MISC_CLK | GPADC/XQSPI/DMA0/DMA1/DMA2
5380 *
5381 * @retval None
5382 */
5383 __STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
5384 {
5385 MODIFY_REG(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK, clk_mask);
5386 }
5387
5388 /**
5389 * @brief Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
5390 *
5391 * Register | BitsName
5392 * ----------|--------
5393 * MCU_MISC_CLK | GPADC/XQSPI/DMA0/DMA1/DMA2
5394 */
5395 __STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
5396 {
5397 return READ_BITS(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK);
5398 }
5399
5400 /**
5401 * @brief Enable XQSPI SCK CLK turn off
5402 *
5403 * Register | BitsName
5404 * ----------|--------
5405 * MCU_MISC_CLK |XQSPI SCK CLK_OFF
5406 *
5407 * @retval None
5408 */
5409 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
5410 {
5411 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_ENABLE;
5412 }
5413
5414 /**
5415 * @brief Disable XQSPI SCK CLK turn off
5416 *
5417 * Register | BitsName
5418 * ----------|--------
5419 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5420 *
5421 * @retval None
5422 */
5423 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
5424 {
5425 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_DISABLE;
5426 }
5427
5428 /**
5429 * @brief Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
5430 *
5431 * Register | BitsName
5432 * ----------|--------
5433 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5434 *
5435 * @retval State of bit (1 or 0).
5436 */
5437 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
5438 {
5439 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5440 }
5441
5442 /**
5443 * @brief Enable DMA0 turn off
5444 *
5445 * Register | BitsName
5446 * ----------|--------
5447 * MCU_MISC_CLK |DMA0_OFF
5448 *
5449 * @retval None
5450 */
5451 __STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
5452 {
5453 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5454 }
5455
5456 /**
5457 * @brief Disable DMA0 turn off
5458 *
5459 * Register | BitsName
5460 * ----------|--------
5461 * MCU_MISC_CLK | DMA0_OFF
5462 *
5463 * @retval None
5464 */
5465 __STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
5466 {
5467 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5468 }
5469
5470 /**
5471 * @brief Indicate whether the DMA0 automatic turn off clock is enabled.
5472 *
5473 * Register | BitsName
5474 * ----------|--------
5475 * MCU_MISC_CLK | DMA0_OFF
5476 *
5477 * @retval State of bit (1 or 0).
5478 */
5479 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
5480 {
5481 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5482 }
5483
5484 /**
5485 * @brief Enable DMA1 turn off
5486 *
5487 * Register | BitsName
5488 * ----------|--------
5489 * MCU_MISC_CLK |DMA1_OFF
5490 *
5491 * @retval None
5492 */
5493 __STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
5494 {
5495 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5496 }
5497
5498 /**
5499 * @brief Disable DMA1 turn off
5500 *
5501 * Register | BitsName
5502 * ----------|--------
5503 * MCU_MISC_CLK | DMA1_OFF
5504 *
5505 * @retval None
5506 */
5507 __STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
5508 {
5509 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5510 }
5511
5512 /**
5513 * @brief Indicate whether the DMA1 automatic turn off clock is enabled.
5514 *
5515 * Register | BitsName
5516 * ----------|--------
5517 * MCU_MISC_CLK | DMA1_OFF
5518 *
5519 * @retval State of bit (1 or 0).
5520 */
5521 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
5522 {
5523 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5524 }
5525
5526 /**
5527 * @brief Enable DMA2 turn off
5528 *
5529 * Register | BitsName
5530 * ----------|--------
5531 * MCU_MISC_CLK |DMA2_OFF
5532 *
5533 * @retval None
5534 */
5535 __STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
5536 {
5537 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5538 }
5539
5540 /**
5541 * @brief Disable DMA2 turn off
5542 *
5543 * Register | BitsName
5544 * ----------|--------
5545 * MCU_MISC_CLK | DMA2_OFF
5546 *
5547 * @retval None
5548 */
5549 __STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
5550 {
5551 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5552 }
5553
5554 /**
5555 * @brief Indicate whether the DMA2 automatic turn off clock is enabled.
5556 *
5557 * Register | BitsName
5558 * ----------|--------
5559 * MCU_MISC_CLK | DMA2_OFF
5560 *
5561 * @retval State of bit (1 or 0).
5562 */
5563 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
5564 {
5565 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5566 }
5567
5568 /** @} */
5569
5570 #endif /* CGC */
5571
5572 #ifdef __cplusplus
5573 }
5574 #endif
5575
5576 #endif /* __GR55XX_LL_CGC_H__ */
5577
5578 /** @} */
5579
5580 /** @} */
5581
5582 /** @} */
ll_cgc_enable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
Enable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4234
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock.
Definition: gr55xx_ll_cgc.h:651
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1688
ll_cgc_enable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
Enabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4794
ll_cgc_is_enabled_force_off_uart4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
Indicate whether the clock for UART4 is forced to close.
Definition: gr55xx_ll_cgc.h:2318
ll_cgc_is_enabled_force_off_i2c4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
Indicate whether the clock for I2C4 is forced to close.
Definition: gr55xx_ll_cgc.h:2570
ll_cgc_is_enabled_force_off_uart5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
Indicate whether the clock for UART5 is forced to close.
Definition: gr55xx_ll_cgc.h:2360
ll_cgc_enable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
Enabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:5047
ll_cgc_disable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
Disabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2935
ll_cgc_is_enabled_force_off_i2c5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
Indicate whether the clock for I2C5 is forced to close.
Definition: gr55xx_ll_cgc.h:2612
ll_cgc_enable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
Enabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:5005
ll_cgc_is_enabled_force_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
Indicate whether the clock for RAMKEY is forced to close.
Definition: gr55xx_ll_cgc.h:4990
ll_cgc_is_enabled_wfi_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
Indicate whether the PKC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5201
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1800
ll_cgc_disable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
Disabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4892
ll_cgc_disable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
Disable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3744
ll_cgc_enable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
Enabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2500
ll_cgc_disable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:998
ll_cgc_is_enabled_i2c_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
Indicate whether the i2c sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3548
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2444
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2402
ll_cgc_is_enabled_spi_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
Indicate whether turn SPI_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4346
ll_cgc_disable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
Disabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:5061
ll_cgc_disable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
Disable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4080
ll_cgc_is_enabled_uart1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
Indicate whether turn UART1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3800
ll_cgc_enable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
Enable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:5493
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1279
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1209
ll_cgc_disable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
Disable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5187
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1068
LL_CGC_WFI_ALL_HCLK2
#define LL_CGC_WFI_ALL_HCLK2
All clock group 2
Definition: gr55xx_ll_cgc.h:104
ll_cgc_enable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
Enable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3856
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock.
Definition: gr55xx_ll_cgc.h:739
ll_cgc_disable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
Disabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4808
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1744
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1491
ll_cgc_enable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
Enable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5173
ll_cgc_disable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
Disable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4122
ll_cgc_enable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
Enabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:3046
ll_cgc_is_enabled_wfi_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1012
ll_cgc_enable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3562
ll_cgc_is_enabled_force_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
Indicate whether the clock for EFUSE is forced to close.
Definition: gr55xx_ll_cgc.h:5075
ll_cgc_is_enabled_i2c2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
Indicate whether turn I2C2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4094
ll_cgc_enable_force_off_psram_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_psram_pclk(void)
Enabling force to turn off the clock for PSRAM ctrl.
Definition: gr55xx_ll_cgc.h:3214
ll_cgc_is_enabled_force_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
Indicate whether the clock for HMAC is forced to close.
Definition: gr55xx_ll_cgc.h:4864
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1477
ll_cgc_disable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
Disable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:5507
ll_cgc_is_enabled_force_off_i2c2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
Indicate whether the clock for I2C2 is forced to close.
Definition: gr55xx_ll_cgc.h:2486
ll_cgc_enable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
Enable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3982
ll_cgc_enable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
Enable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3520
ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
Indicate whether the div4 clock for xf qspi blocks is forced to close.
Definition: gr55xx_ll_cgc.h:3074
ll_cgc_enable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:900
ll_cgc_disable_wfi_off_usb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_usb_hclk(void)
Disable USB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1336
ll_cgc_enable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
Enabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1618
ll_cgc_enable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
Enable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4402
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:872
ll_cgc_disable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
Disabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2514
ll_cgc_disable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
Disabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:2220
ll_cgc_disable_qspim_low_power
__STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
Disable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3618
ll_cgc_disable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
Disable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4668
ll_cgc_enable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
Enable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4360
ll_cgc_is_enabled_wfi_off_usb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_usb_hclk(void)
Indicate whether the USB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1351
ll_cgc_is_enabled_force_off_pwm0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
Indicate whether the clock for PWM0 is forced to close.
Definition: gr55xx_ll_cgc.h:3116
ll_cgc_get_mcu_periph_low_power
__STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
Return to clock blocks that has low power feature.
Definition: gr55xx_ll_cgc.h:3296
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1758
ll_cgc_enable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
Enable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3814
ll_cgc_is_enabled_force_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
Indicate whether the clock for AES is forced to close.
Definition: gr55xx_ll_cgc.h:4822
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1449
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1856
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1096
ll_cgc_set_mcu_periph_low_power
__STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
Some peripherals has low power feature.
Definition: gr55xx_ll_cgc.h:3269
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2780
ll_cgc_is_enabled_wfi_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
Indicate whether the HMAC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5159
ll_cgc_is_enabled_force_off_uart3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
Indicate whether the clock for UART3 is forced to close.
Definition: gr55xx_ll_cgc.h:2276
ll_cgc_enable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
Enable turn UART5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3940
ll_cgc_is_enabled_ahb2apb_async_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3716
ll_cgc_enable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
Enable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3646
ll_cgc_disable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3702
ll_cgc_get_wfi_off_hclk_4
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
Return to clock blocks that is turned off during WFI.
Definition: gr55xx_ll_cgc.h:566
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2766
ll_cgc_is_enabled_uart_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
Indicate whether the uart sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3338
ll_cgc_is_enabled_i2s_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
Indicate whether the i2s low-power is enabled.
Definition: gr55xx_ll_cgc.h:3422
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.
Definition: gr55xx_ll_cgc.h:808
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1435
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1898
ll_cgc_disable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
Disabling force to turn off the clock for UART5.
Definition: gr55xx_ll_cgc.h:2346
ll_cgc_enable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
Enable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:5409
ll_cgc_is_enabled_force_off_vttbl_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
Indicate whether the clock for VTTBL is forced to close.
Definition: gr55xx_ll_cgc.h:3200
ll_cgc_enable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
Enabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2794
LL_CGC_FRC_ALL_HCLK0
#define LL_CGC_FRC_ALL_HCLK0
All clock group 0
Definition: gr55xx_ll_cgc.h:121
ll_cgc_disable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
Disable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4248
ll_cgc_disable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
Disable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5103
ll_cgc_is_enabled_qspim1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4556
ll_cgc_enable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
Enabling force to turn off the clock for I2C5.
Definition: gr55xx_ll_cgc.h:2584
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2136
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:438
ll_cgc_enable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
Enable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3310
ll_cgc_enable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
Enable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4108
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2374
ll_cgc_set_wfi_off_hclk_3
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:512
ll_cgc_enable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
Enable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:3352
CGC_CLOCK_ENABLE
#define CGC_CLOCK_ENABLE
Bit segment address enable
Definition: gr55xx_ll_cgc.h:324
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.
Definition: gr55xx_ll_cgc.h:457
ll_cgc_enable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
Enabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2963
ll_cgc_is_enabled_i2c0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
Indicate whether turn I2C0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4010
ll_cgc_disable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
Disable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3534
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1702
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock.
Definition: gr55xx_ll_cgc.h:599
ll_cgc_is_enabled_qspim_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
Indicate whether the QSPIM low-power is enabled.
Definition: gr55xx_ll_cgc.h:3632
ll_cgc_disable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
Disable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4332
ll_cgc_disable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
Disable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3450
ll_cgc_is_enabled_force_off_dma0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
Indicate whether the DMA0 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5479
ll_cgc_disable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
Disable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:5465
ll_cgc_enable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
Enable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4486
ll_cgc_disable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
Disabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2808
ll_cgc_is_enabled_force_off_qspi2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
Indicate whether the clock for QSPI2 is forced to close.
Definition: gr55xx_ll_cgc.h:2822
ll_cgc_disable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
Disable turn I2C4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4164
ll_cgc_is_enabled_uart_pclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
Indicate whether the uart pclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3380
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2066
ll_cgc_is_enabled_force_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
Indicate whether the clock for PKC is forced to close.
Definition: gr55xx_ll_cgc.h:4906
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1926
ll_cgc_enable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
Enable turn I2C4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4150
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1138
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1814
ll_cgc_disable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
Disable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4038
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1180
ll_cgc_enable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
Enable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5215
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1842
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1716
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1124
ll_cgc_disable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
Disable turn UART4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3912
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1223
ll_cgc_enable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
Enabling force to turn off the clock for I2C4.
Definition: gr55xx_ll_cgc.h:2542
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2851
ll_cgc_is_enabled_force_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
Indicate whether the clock for RNG is forced to close.
Definition: gr55xx_ll_cgc.h:5033
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:956
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.
Definition: gr55xx_ll_cgc.h:492
ll_cgc_enable_wfi_off_usb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_usb_hclk(void)
Enable USB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1322
ll_cgc_disable_i2s_low_power
__STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
Disable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:3408
ll_cgc_disable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:914
ll_cgc_disable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
Disable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5313
ll_cgc_disable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
Disable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4458
ll_cgc_is_enabled_force_off_pdm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
Indicate whether the clock for PDM is forced to close.
Definition: gr55xx_ll_cgc.h:2991
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1884
ll_cgc_enable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
Enable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5341
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1730
ll_cgc_is_enabled_force_off_uart2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
Indicate whether the clock for UART2 is forced to close.
Definition: gr55xx_ll_cgc.h:2234
ll_cgc_is_enabled_force_off_i2s_s_p_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2907
ll_cgc_is_enabled_ahb2apb_sync_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
Indicate whether the AHB2APB bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3674
ll_cgc_enable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:984
ll_cgc_enable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
Enabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2458
ll_cgc_disable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
Disabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:3102
LL_CGC_MCU_SECU_FRC_OFF_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_HCLK
Hclk for security clock
Definition: gr55xx_ll_cgc.h:237
ll_cgc_disable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
Disabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:3060
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:2108
ll_cgc_disable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
Disabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:5019
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1548
ll_cgc_enable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
Enable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4276
ll_cgc_disable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
Disabling force to turn off the clock for I2C4.
Definition: gr55xx_ll_cgc.h:2556
ll_cgc_is_enabled_force_off_pwm1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
Indicate whether the clock for PWM1 is forced to close.
Definition: gr55xx_ll_cgc.h:3158
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:2024
ll_cgc_is_enabled_uart3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
Indicate whether turn UART3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3884
ll_cgc_is_enabled_spis_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
Indicate whether the spis sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3506
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1604
ll_cgc_is_enabled_force_off_dspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
Indicate whether the clock for DSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2949
ll_cgc_get_slp_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
Return to security clock blocks that is turned off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4780
ll_cgc_is_enabled_force_off_xqspi_sck
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5437
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1379
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1040
ll_cgc_set_misc_clk
__STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
Some MISC_CLK blocks turn off clock.
Definition: gr55xx_ll_cgc.h:5383
ll_cgc_disable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2893
ll_cgc_is_enabled_force_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
Indicate whether the clock for SIM is forced to close.
Definition: gr55xx_ll_cgc.h:1646
LL_CGC_FRC_ALL_HCLK2
#define LL_CGC_FRC_ALL_HCLK2
All clock group 2
Definition: gr55xx_ll_cgc.h:165
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1265
LL_CGC_MCU_MISC_CLK
#define LL_CGC_MCU_MISC_CLK
Hclk for msic all clock
Definition: gr55xx_ll_cgc.h:245
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1576
ll_cgc_disable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3576
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1421
LL_CGC_WFI_ALL_HCLK0
#define LL_CGC_WFI_ALL_HCLK0
All clock group 0
Definition: gr55xx_ll_cgc.h:84
ll_cgc_disable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
Disable turn I2C5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4206
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2178
BIT_SEGMENT_VALUE
#define BIT_SEGMENT_VALUE(addr, bitnum)
Bit segment address value manipulation
Definition: gr55xx_ll_cgc.h:335
LL_CGC_WFI_ALL_HCLK1
#define LL_CGC_WFI_ALL_HCLK1
All clock group 1
Definition: gr55xx_ll_cgc.h:95
ll_cgc_enable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
Enabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4836
ll_cgc_enable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
Enable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4654
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1293
ll_cgc_disable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
Disabling force to turn off the clock for UART4.
Definition: gr55xx_ll_cgc.h:2304
ll_cgc_is_enabled_wfi_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
Indicate whether the AES automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5117
ll_cgc_disable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
Disable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5145
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2682
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1534
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:3019
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1674
ll_cgc_enable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
Enable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:5451
ll_cgc_disable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
Disable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4500
ll_cgc_enable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
Enable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3730
ll_cgc_is_enabled_uart2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
Indicate whether turn UART2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3842
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2080
ll_cgc_enable_force_off_usb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_usb_hclk(void)
Enabling force to turn off the clock for USB.
Definition: gr55xx_ll_cgc.h:1954
ll_cgc_get_force_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
Return to clock blocks that is turned off.
Definition: gr55xx_ll_cgc.h:843
ll_cgc_disable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
Disable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4542
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2654
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:970
ll_cgc_enable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2879
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1562
ll_cgc_is_enabled_spi_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
Indicate whether turn SPI_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4388
ll_cgc_disable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
Disabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2977
ll_cgc_disable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
Disable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3786
ll_cgc_disable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
Disabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:2262
ll_cgc_enable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
Enable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3436
ll_cgc_is_enabled_qspim0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4514
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:3005
ll_cgc_is_enabled_wfi_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
Indicate whether the RAMKEY automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5285
ll_cgc_disable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
Disabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:3186
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1505
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2122
ll_cgc_disable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
Disabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:3144
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1772
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1251
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1026
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2696
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1308
ll_cgc_is_enabled_pwm1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
Indicate whether turn pwm1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4472
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2752
ll_cgc_enable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3688
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1082
ll_cgc_disable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
Disable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5271
ll_cgc_enable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
Enable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4612
ll_cgc_get_force_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
Return to clock blocks that was forcibly closed inside security system.
Definition: gr55xx_ll_cgc.h:4737
ll_cgc_is_enabled_wfi_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
Indicate whether the EFUSE automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5369
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2626
ll_cgc_enable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
Enabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:3088
ll_cgc_disable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
Disabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2472
ll_cgc_disable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
Disable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5229
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.
Definition: gr55xx_ll_cgc.h:670
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1365
ll_cgc_enable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
Enable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5257
ll_cgc_set_wfi_off_hclk_4
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:549
ll_cgc_enable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
Enabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4920
ll_cgc_enable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
Enable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4318
ll_cgc_disable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
Disable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3324
CGC_CLOCK_DISABLE
#define CGC_CLOCK_DISABLE
Bit segment address disable
Definition: gr55xx_ll_cgc.h:325
ll_cgc_enable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
Enabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:2206
ll_cgc_disable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
Disable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3828
ll_cgc_enable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
Enable turn I2C5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4192
ll_cgc_enable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
Enable turn UART4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3898
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2738
ll_cgc_enable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
Enabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4962
ll_cgc_is_enabled_dspi_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
Indicate whether turn DSPI off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4640
ll_cgc_enable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
Enabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:3130
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2052
ll_cgc_is_enabled_uart0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
Indicate whether turn UART0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3758
ll_cgc_enable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
Enable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4528
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2668
ll_cgc_is_enabled_i2c4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
Indicate whether turn I2C4 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4178
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2416
ll_cgc_enable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
Enabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:2248
ll_cgc_disable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
Disable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:3366
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2388
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1940
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2038
ll_cgc_enable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
Enable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3772
ll_cgc_is_enabled_force_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
Indicate whether the clock for PRESENT is forced to close.
Definition: gr55xx_ll_cgc.h:4948
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.
Definition: gr55xx_ll_cgc.h:631
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2010
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:3033
ll_cgc_is_enabled_force_off_dma2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
Indicate whether the DMA2 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5563
ll_cgc_is_enabled_uart5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
Indicate whether turn UART5 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3968
ll_cgc_disable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
Disabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4976
ll_cgc_disable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
Disabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1632
ll_cgc_is_enabled_qspim2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4598
ll_cgc_enable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
Enable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5131
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1237
ll_cgc_disable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
Disable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3870
ll_cgc_is_enabled_i2c3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
Indicate whether turn I2C3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4136
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2640
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2164
ll_cgc_is_enabled_force_off_usb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_usb_hclk(void)
Indicate whether the clock for USB is forced to close.
Definition: gr55xx_ll_cgc.h:1982
ll_cgc_enable_i2s_low_power
__STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
Enable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:3394
ll_cgc_enable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
Enable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:5535
ll_cgc_enable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
Enable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5089
ll_cgc_disable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
Disable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4584
ll_cgc_enable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
Enable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4066
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1786
ll_cgc_is_enabled_spim_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
Indicate whether the spim sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3464
ll_cgc_disable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
Disabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4934
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2430
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1152
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1463
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1166
ll_cgc_is_enabled_force_off_dma1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
Indicate whether the DMA1 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5521
ll_cgc_set_slp_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
Some security blocks automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4759
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:384
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2837
ll_cgc_is_enabled_uart4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
Indicate whether turn UART4 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3926
ll_cgc_is_enabled_ahb_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3590
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2094
ll_cgc_disable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
Disabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4850
ll_cgc_enable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
Enabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2921
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:2150
ll_cgc_is_enabled_wfi_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
Indicate whether the PRESENT automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5243
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1912
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:1996
ll_cgc_is_enabled_i2s_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
Indicate whether turn I2S_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4304
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1110
ll_cgc_is_enabled_i2s_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
Indicate whether turn I2S_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4262
ll_cgc_disable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
Disable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5355
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1195
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1393
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1660
ll_cgc_get_wfi_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
Return to clock blocks that is turned off during WFI.
Definition: gr55xx_ll_cgc.h:531
ll_cgc_is_enabled_pdm_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
Indicate whether turn PDM off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4682
ll_cgc_enable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
Enable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4024
ll_cgc_enable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
Enabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4878
ll_cgc_is_enabled_force_off_i2c3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
Indicate whether the clock for I2C3 is forced to close.
Definition: gr55xx_ll_cgc.h:2528
ll_cgc_is_enabled_force_off_psram_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_psram_pclk(void)
Indicate whether the clock for PSRAM ctrl is forced to close.
Definition: gr55xx_ll_cgc.h:3242
ll_cgc_disable_force_off_usb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_usb_hclk(void)
Disabling force to turn off the clock for USB.
Definition: gr55xx_ll_cgc.h:1968
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1828
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:886
ll_cgc_enable_qspim_low_power
__STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
Enable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3604
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1870
ll_cgc_is_enabled_wfi_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:928
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:858
ll_cgc_enable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
Enable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4444
LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
Hclk for security clock WFI/WFE
Definition: gr55xx_ll_cgc.h:238
ll_cgc_enable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
Enabling force to turn off the clock for UART4.
Definition: gr55xx_ll_cgc.h:2290
ll_cgc_is_enabled_i2c5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
Indicate whether turn I2C5 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4220
ll_cgc_disable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
Disable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4374
ll_cgc_disable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
Disable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4290
ll_cgc_disable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
Disable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3660
ll_cgc_enable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
Enable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3478
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2724
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1054
ll_cgc_enable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
Enabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:3172
ll_cgc_enable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
Enable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4570
ll_cgc_enable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
Enable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5299
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1590
ll_cgc_disable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
Disable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3996
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2865
LL_CGC_FRC_ALL_HCLK1
#define LL_CGC_FRC_ALL_HCLK1
All clock group 1
Definition: gr55xx_ll_cgc.h:131
ll_cgc_disable_force_off_psram_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_psram_pclk(void)
Disabling force to turn off the clock for PSRAM ctrl.
Definition: gr55xx_ll_cgc.h:3228
ll_cgc_set_force_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
Individual block's clock control inside security system which was forced to turn off (Include: AES/HM...
Definition: gr55xx_ll_cgc.h:4710
ll_cgc_is_enabled_pwm0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
Indicate whether turn pwm0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4430
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1520
ll_cgc_disable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
Disable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3492
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1407
ll_cgc_set_force_off_hclk_3
__STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock.
Definition: gr55xx_ll_cgc.h:826
ll_cgc_is_enabled_i2c1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
Indicate whether turn I2C1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4052
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:475
ll_cgc_disable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
Disable turn UART5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3954
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2710
ll_cgc_disable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
Disable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:5423
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:942
ll_cgc_enable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
Enabling force to turn off the clock for UART5.
Definition: gr55xx_ll_cgc.h:2332
ll_cgc_disable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
Disabling force to turn off the clock for I2C5.
Definition: gr55xx_ll_cgc.h:2598
ll_cgc_disable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
Disable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4626
ll_cgc_is_enabled_wfi_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
Indicate whether the RNG automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5327
ll_cgc_get_misc_clk
__STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
Return to MISC_CLK clock blocks that is turned off.
Definition: gr55xx_ll_cgc.h:5395
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:2192
ll_cgc_disable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
Disable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4416
ll_cgc_disable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
Disable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:5549
LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
#define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
Serial blocks
Definition: gr55xx_ll_cgc.h:214
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.
Definition: gr55xx_ll_cgc.h:418