gr55xx_ll_i2c.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2c.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2C LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2C I2C
47 * @brief I2C LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2C0) || defined (I2C1)
63
64 /** @defgroup I2C_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2C_LL_ES_INIT I2C Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2C init Structure definition
75 */
76 typedef struct _ll_i2c_init
77 {
78 uint32_t speed; /**< Specifies the transfer speed. See @ref I2C_LL_EC_SPEED. */
79
80 uint32_t own_address; /**< Specifies the device own address.
81 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
82
83 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
84
85 uint32_t own_addr_size; /**< Specifies the device own address 1 size (7-bit or 10-bit).
86 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS
87
88 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
89 } ll_i2c_init_t;
90
91 /** @} */
92
93 /** @} */
94
95 /**
96 * @defgroup I2C_LL_MACRO Defines
97 * @{
98 */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
102 * @{
103 */
104
105 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
106 * @brief Flags definitions which can be used with LL_I2C_ReadReg function
107 * @{
108 */
109 #define LL_I2C_INTR_STAT_SCL_STUCK_AT_LOW I2C_RAW_INT_STAT_SCL_STUCKLOW /**< SCL_STUCK_AT_LOW interrupt flag */
110 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_RAW_INT_STAT_M_HOLD /**< MST_ON_HOLD interrupt flag */
111 #define LL_I2C_INTR_STAT_RESTART_DET I2C_RAW_INT_STAT_RESTART_DET /**< RESTART_DET interrupt flag */
112 #define LL_I2C_INTR_STAT_GEN_CALL I2C_RAW_INT_STAT_GEN_CALL /**< GEN_CALL interrupt flag */
113 #define LL_I2C_INTR_STAT_START_DET I2C_RAW_INT_STAT_START_DET /**< START_DET interrupt flag */
114 #define LL_I2C_INTR_STAT_STOP_DET I2C_RAW_INT_STAT_STOP_DET /**< STOP_DET interrupt flag */
115 #define LL_I2C_INTR_STAT_ACTIVITY I2C_RAW_INT_STAT_ACTIVITY /**< ACTIVITY interrupt flag */
116 #define LL_I2C_INTR_STAT_RX_DONE I2C_RAW_INT_STAT_RX_DONE /**< RX_DONE interrupt flag */
117 #define LL_I2C_INTR_STAT_TX_ABRT I2C_RAW_INT_STAT_TX_ABORT /**< TX_ABRT interrupt flag */
118 #define LL_I2C_INTR_STAT_RD_REQ I2C_RAW_INT_STAT_RD_REQ /**< RD_REQ interrupt flag */
119 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_RAW_INT_STAT_TX_EMPTY /**< TX_EMPTY interrupt flag */
120 #define LL_I2C_INTR_STAT_TX_OVER I2C_RAW_INT_STAT_TX_OVER /**< TX_OVER interrupt flag */
121 #define LL_I2C_INTR_STAT_RX_FULL I2C_RAW_INT_STAT_RX_FULL /**< RX_FULL interrupt flag */
122 #define LL_I2C_INTR_STAT_RX_OVER I2C_RAW_INT_STAT_RX_OVER /**< RX_OVER interrupt flag */
123 #define LL_I2C_INTR_STAT_RX_UNDER I2C_RAW_INT_STAT_RX_UNDER /**< RX_UNDER interrupt flag */
124
125 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABORT_SRC_TX_FLUSH_CNT /**< Indcates the number of TX FOFO data command */
126 #define LL_I2C_ABRT_SDA_STUCK_AT_LOW I2C_TX_ABORT_SRC_ABORT_SDA_STUCK /**< The SDA stuck at low detected by master */
127 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABORT_SRC_ABORT_USER_ABORT /**< Transfer abort detected by master */
128 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABORT_SRC_ABORT_SLVRD_INTX /**< Slave trying to transmit to remote master in read mode */
129 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABORT_SRC_ABORT_S_ARBLOST /**< Slave lost arbitration to remote master */
130 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABORT_SRC_ABORT_SLVFLUSH_TXFIFO /**< Slave flushes existing data in TX-FIFO upon getting read command */
131 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABORT_SRC_ABORT_LOST /**< Master or Slave Transmitter lost arbitration */
132 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABORT_SRC_ABORT_MASTER_DIS /**< User intitating master operation when MASTER disabled */
133 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABORT_SRC_ABORT_10B_RD_NORSTR /**< Master trying to read in 10-Bit addressing mode when RESTART disabled */
134 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABORT_SRC_ABORT_SBYTE_NORSTRT /**< User trying to send START byte when RESTART disabled */
135 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABORT_SRC_ABORT_HS_NORSTRT /**< User trying to swidth Master to HS mode when RESTART disabled */
136 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABORT_SRC_ABORT_SBYTE_ACKDET /**< ACK detected for START byte */
137 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABORT_SRC_ABORT_HS_ACKDET /**< HS Master code is ACKed in HS Mode */
138 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABORT_SRC_ABORT_GCALL_RD /**< GCALL is followed by read from bus */
139 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABORT_SRC_ABORT_GCALL_NOACK /**< GCALL is not ACKed by any slave */
140 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABORT_SRC_ABORT_TX_NOACK /**< Transmitted data is not ACKed by addressed slave */
141 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABORT_SRC_ABORT_10B2_NOACK /**< Byte 2 of 10-Bit Address is not ACKed by any slave */
142 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABORT_SRC_ABORT_10B1_NOACK /**< Byte 1 of 10-Bit Address is not ACKed by any slave */
143 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABORT_SRC_ABORT_7B_NOACK /**< 7Bit Address is not ACKed by any slave */
144 /** @} */
145
146 /** @defgroup I2C_LL_EC_IT IT Defines
147 * @brief Interrupt definitions which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
148 * @{
149 */
150 #define LL_I2C_INTR_MASK_SCL_STUCK_AT_LOW I2C_INT_MASK_MASK_SCL_STUCKLOW /**< SCL_STUCK_AT_LOW interrupt flag */
151 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INT_MASK_MASK_M_HOLD /**< MST_ON_HOLD interrupt */
152 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INT_MASK_MASK_RESTART_DET /**< RESTART_DET interrupt */
153 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INT_MASK_MASK_GEN_CALL /**< GEN_CALL interrupt */
154 #define LL_I2C_INTR_MASK_START_DET I2C_INT_MASK_MASK_START_DET /**< START_DET interrupt */
155 #define LL_I2C_INTR_MASK_STOP_DET I2C_INT_MASK_MASK_STOP_DET /**< STOP_DET interrupt */
156 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INT_MASK_MASK_ACTIVITY /**< ACTIVITY interrupt */
157 #define LL_I2C_INTR_MASK_RX_DONE I2C_INT_MASK_MASK_RX_DONE /**< RX_DONE interrupt */
158 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INT_MASK_MASK_TX_ABORT /**< TX_ABRT interrupt */
159 #define LL_I2C_INTR_MASK_RD_REQ I2C_INT_MASK_MASK_RD_REQ /**< RD_REQ interrupt */
160 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INT_MASK_MASK_TX_EMPTY /**< TX_EMPTY interrupt */
161 #define LL_I2C_INTR_MASK_TX_OVER I2C_INT_MASK_MASK_TX_OVER /**< TX_OVER interrupt */
162 #define LL_I2C_INTR_MASK_RX_FULL I2C_INT_MASK_MASK_RX_FULL /**< RX_FULL interrupt */
163 #define LL_I2C_INTR_MASK_RX_OVER I2C_INT_MASK_MASK_RX_OVER /**< RX_OVER interrupt */
164 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INT_MASK_MASK_RX_UNDER /**< RX_UNDER interrupt */
165
166 #define LL_I2C_INTR_MASK_ALL 0x00007FFFU /**< All interrupt */
167 /** @} */
168
169 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
170 * @{
171 */
172 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /**< Master operates in 7-bit addressing mode. */
173 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CTRL_ADDR_BIT_M /**< Master operates in 10-bit addressing mode.*/
174 /** @} */
175
176 /** @defgroup I2C_LL_EC_OWNADDRESS Own Address Length
177 * @{
178 */
179 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U /**< Own address 1 is a 7-bit address. */
180 #define LL_I2C_OWNADDRESS_10BIT I2C_CTRL_ADDR_BIT_S /**< Own address 1 is a 10-bit address.*/
181 /** @} */
182
183
184 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
185 * @{
186 */
187 #define LL_I2C_CMD_SLV_NONE 0x00000000U /**< Slave No command. */
188 #define LL_I2C_CMD_MST_WRITE 0x00000000U /**< Master write command. */
189 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD /**< Master read command. */
190 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP /**< Master issue STOP after this command. */
191 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART /**< Master issue RESTART before this command. */
192 /** @} */
193
194 /** @defgroup I2C_LL_EC_SPEED_MODE Transfer Speed Mode
195 * @{
196 */
197 #define LL_I2C_SPEED_MODE_STANDARD (0x1U << I2C_CTRL_SPEED_POS) /**< Standard Speed mode(0 to 100 Kb/s) of operation. */
198 #define LL_I2C_SPEED_MODE_FAST (0x2U << I2C_CTRL_SPEED_POS) /**< Fast (400 Kb/s) or Fast Plus mode (1000 Kb/s) of operation. */
199 #define LL_I2C_SPEED_MODE_HIGH (0x3U << I2C_CTRL_SPEED_POS) /**< High Speed mode (3.4 Mb/s) of operation. */
200 /** @} */
201
202 /** @defgroup I2C_LL_EC_SPEED Transfer Speed
203 * @{
204 */
205 #define LL_I2C_SPEED_100K (100000ul) /**< Standard Speed. */
206 #define LL_I2C_SPEED_400K (400000ul) /**< Fast Speed. */
207 #define LL_I2C_SPEED_1000K (1000000ul) /**< Fast Plus Speed. */
208 #define LL_I2C_SPEED_2000K (2000000ul) /**< High Speed. */
209 /** @} */
210
211 /** @defgroup I2C_LL_EC_TX_FIFO_TH TX FIFO Threshold
212 * @{
213 */
214 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
215 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U /**< 1 character in TX FIFO */
216 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U /**< 2 characters in TX FIFO */
217 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U /**< 3 characters in TX FIFO */
218 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U /**< 4 characters in TX FIFO */
219 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U /**< 5 characters in TX FIFO */
220 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U /**< 6 characters in TX FIFO */
221 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U /**< 7 characters in TX FIFO */
222 #define LL_I2C_TX_FIFO_TH_CHAR_8 0x00000008U /**< 9 character in TX FIFO */
223 #define LL_I2C_TX_FIFO_TH_CHAR_9 0x00000009U /**< 9 characters in TX FIFO */
224 #define LL_I2C_TX_FIFO_TH_CHAR_10 0x0000000AU /**< 10 characters in TX FIFO */
225 #define LL_I2C_TX_FIFO_TH_CHAR_11 0x0000000BU /**< 11 characters in TX FIFO */
226 #define LL_I2C_TX_FIFO_TH_CHAR_12 0x0000000CU /**< 12 characters in TX FIFO */
227 #define LL_I2C_TX_FIFO_TH_CHAR_13 0x0000000DU /**< 13 characters in TX FIFO */
228 #define LL_I2C_TX_FIFO_TH_CHAR_14 0x0000000EU /**< 14 characters in TX FIFO */
229 #define LL_I2C_TX_FIFO_TH_CHAR_15 0x0000000FU /**< 15 character in TX FIFO */
230 #define LL_I2C_TX_FIFO_TH_CHAR_16 0x00000010U /**< 16 characters in TX FIFO */
231 #define LL_I2C_TX_FIFO_TH_CHAR_17 0x00000011U /**< 17 characters in TX FIFO */
232 #define LL_I2C_TX_FIFO_TH_CHAR_18 0x00000012U /**< 18 characters in TX FIFO */
233 #define LL_I2C_TX_FIFO_TH_CHAR_19 0x00000013U /**< 19 characters in TX FIFO */
234 #define LL_I2C_TX_FIFO_TH_CHAR_20 0x00000014U /**< 20 characters in TX FIFO */
235 #define LL_I2C_TX_FIFO_TH_CHAR_21 0x00000015U /**< 21 characters in TX FIFO */
236 #define LL_I2C_TX_FIFO_TH_CHAR_22 0x00000016U /**< 22 character in TX FIFO */
237 #define LL_I2C_TX_FIFO_TH_CHAR_23 0x00000017U /**< 23 characters in TX FIFO */
238 #define LL_I2C_TX_FIFO_TH_CHAR_24 0x00000018U /**< 24 characters in TX FIFO */
239 #define LL_I2C_TX_FIFO_TH_CHAR_25 0x00000019U /**< 25 characters in TX FIFO */
240 #define LL_I2C_TX_FIFO_TH_CHAR_26 0x0000001AU /**< 26 characters in TX FIFO */
241 #define LL_I2C_TX_FIFO_TH_CHAR_27 0x0000001BU /**< 27 characters in TX FIFO */
242 #define LL_I2C_TX_FIFO_TH_CHAR_28 0x0000001CU /**< 28 characters in TX FIFO */
243 #define LL_I2C_TX_FIFO_TH_CHAR_29 0x0000001DU /**< 29 characters in TX FIFO */
244 #define LL_I2C_TX_FIFO_TH_CHAR_30 0x0000001EU /**< 30 characters in TX FIFO */
245 #define LL_I2C_TX_FIFO_TH_CHAR_31 0x0000001FU /**< 31 characters in TX FIFO */
246 #define LL_I2C_TX_FIFO_TH_CHAR_32 0x00000020U /**< 32 characters in TX FIFO */
247
248 /** @} */
249
250 /** @defgroup I2C_LL_EC_RX_FIFO_TH RX FIFO Threshold
251 * @{
252 */
253 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
254 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in RX FIFO */
255 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U /**< 3 characters in RX FIFO */
256 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U /**< 4 characters in RX FIFO */
257 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U /**< 5 characters in RX FIFO */
258 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U /**< 6 characters in RX FIFO */
259 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U /**< 7 characters in RX FIFO */
260 #define LL_I2C_RX_FIFO_TH_CHAR_8 0x00000007U /**< 8 character in RX FIFO */
261 #define LL_I2C_RX_FIFO_TH_CHAR_9 0x00000008U /**< 9 characters in RX FIFO */
262 #define LL_I2C_RX_FIFO_TH_CHAR_10 0x00000009U /**< 10 characters in RX FIFO */
263 #define LL_I2C_RX_FIFO_TH_CHAR_11 0x0000000AU /**< 11 characters in RX FIFO */
264 #define LL_I2C_RX_FIFO_TH_CHAR_12 0x0000000BU /**< 12 characters in RX FIFO */
265 #define LL_I2C_RX_FIFO_TH_CHAR_13 0x0000000CU /**< 13 characters in RX FIFO */
266 #define LL_I2C_RX_FIFO_TH_CHAR_14 0x0000000DU /**< 14 characters in RX FIFO */
267 #define LL_I2C_RX_FIFO_TH_CHAR_15 0x0000000EU /**< 15 character in RX FIFO */
268 #define LL_I2C_RX_FIFO_TH_CHAR_16 0x0000000FU /**< 16 characters in RX FIFO */
269 #define LL_I2C_RX_FIFO_TH_CHAR_17 0x00000010U /**< 17 characters in RX FIFO */
270 #define LL_I2C_RX_FIFO_TH_CHAR_18 0x00000011U /**< 18 characters in RX FIFO */
271 #define LL_I2C_RX_FIFO_TH_CHAR_19 0x00000012U /**< 19 characters in RX FIFO */
272 #define LL_I2C_RX_FIFO_TH_CHAR_20 0x00000013U /**< 20 characters in RX FIFO */
273 #define LL_I2C_RX_FIFO_TH_CHAR_21 0x00000014U /**< 21 characters in RX FIFO */
274 #define LL_I2C_RX_FIFO_TH_CHAR_22 0x00000015U /**< 22 character in RX FIFO */
275 #define LL_I2C_RX_FIFO_TH_CHAR_23 0x00000016U /**< 23 characters in RX FIFO */
276 #define LL_I2C_RX_FIFO_TH_CHAR_24 0x00000017U /**< 24 characters in RX FIFO */
277 #define LL_I2C_RX_FIFO_TH_CHAR_25 0x00000018U /**< 25 characters in RX FIFO */
278 #define LL_I2C_RX_FIFO_TH_CHAR_26 0x00000019U /**< 26 characters in RX FIFO */
279 #define LL_I2C_RX_FIFO_TH_CHAR_27 0x0000001AU /**< 27 characters in RX FIFO */
280 #define LL_I2C_RX_FIFO_TH_CHAR_28 0x0000001BU /**< 28 characters in RX FIFO */
281 #define LL_I2C_RX_FIFO_TH_CHAR_29 0x0000001CU /**< 29 character in RX FIFO */
282 #define LL_I2C_RX_FIFO_TH_CHAR_30 0x0000001DU /**< 30 characters in RX FIFO */
283 #define LL_I2C_RX_FIFO_TH_CHAR_31 0x0000001EU /**< 31 characters in RX FIFO */
284 #define LL_I2C_RX_FIFO_TH_CHAR_32 0x0000001FU /**< 32 characters in RX FIFO */
285 #define LL_I2C_RX_FIFO_TH_FULL 0x00000020U /**< RX FIFO full */
286 /** @} */
287
288 /** @defgroup I2C_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
289 * @{
290 */
291
292 /**
293 * @brief LL I2C InitStrcut default configuartion
294 */
295 #define LL_I2C_DEFAULT_CONFIG \
296 { \
297 .speed = LL_I2C_SPEED_400K, \
298 .own_address = 0x55U, \
299 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
300 }
301 /** @} */
302
303 /** @} */
304
305 /* Exported macro ------------------------------------------------------------*/
306 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
307 * @{
308 */
309
310 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
311 * @{
312 */
313
314 /**
315 * @brief Write a value in I2C register
316 * @param __instance__ I2C instance
317 * @param __REG__ Register to be written
318 * @param __VALUE__ Value to be written in the register
319 * @retval None.
320 */
321 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
322
323 /**
324 * @brief Read a value in I2C register
325 * @param __instance__ I2C instance
326 * @param __REG__ Register to be read
327 * @retval Register value
328 */
329 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
330 /** @} */
331
332 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
333 * @{
334 */
335
336 /**
337 * @brief Compute CLK_SSL_CNT value according to Peripheral Clock and expected Speed.
338 * @param __PERIPHCLK__ Peripheral Clock frequency used for I2C instance
339 * @param __SPEED__ Speed value to achieve
340 * @retval CLK_SSL_CNT value to be used for XS_SCL_HCNT, XS_SCL_LCNT registers where X can be (S, F, H)
341 */
342 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
343
344 /**
345 * @brief Get Speed Mode according to expected Speed.
346 * @param __SPEED__ Speed value to achieve
347 * @retval Returned value can be one of the following values:
348 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
349 * @arg @ref LL_I2C_SPEED_MODE_FAST
350 * @arg @ref LL_I2C_SPEED_MODE_HIGH
351 */
352 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
353 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
354 /** @} */
355
356 /** @} */
357
358 /** @} */
359
360 /* Private types -------------------------------------------------------------*/
361 /* Private variables ---------------------------------------------------------*/
362 /* Private constants ---------------------------------------------------------*/
363 /* Private macros ------------------------------------------------------------*/
364
365 /* Exported functions --------------------------------------------------------*/
366 /** @defgroup I2C_LL_DRIVER_FUNCTIONS Functions
367 * @{
368 */
369
370 /** @defgroup I2C_LL_EF_Configuration Configuration
371 * @{
372 */
373
374 /**
375 * @brief Enable I2C peripheral (ENABLE = 1).
376 *
377 * Register|BitsName
378 * ---------------|---------------
379 * EN | ACTIVITY
380 *
381 * @param I2Cx I2C instance.
382 * @retval None.
383 */
384 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
385 {
386 SET_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
387 }
388
389 /**
390 * @brief Disable I2C peripheral (ENABLE = 0).
391 * @note When ENABLE = 0, the TX FIFO and RX FIFO get flushed.
392 * Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state.
393 * If the module is transmitting, it stops as well as deletes the contents of the transmit buffer
394 * after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops
395 * the current transfer at the end of the current byte and does not acknowledge the transfer..
396 *
397 * Register|BitsName
398 * ---------------|---------------
399 * EN | ACTIVITY
400 *
401 * @param I2Cx I2C instance.
402 * @retval None.
403 */
404 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
405 {
406 CLEAR_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
407 }
408
409 /**
410 * @brief Check if the I2C peripheral is enabled or disabled.
411 *
412 * Register|BitsName
413 * ---------------|---------------
414 * STAT | STAT_EN
415 *
416 * @param I2Cx I2C instance.
417 * @retval State of bit (1 or 0).
418 */
419 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
420 {
421 return (READ_BITS(I2Cx->STAT, I2C_EN_STAT_EN) == (I2C_EN_STAT_EN));
422 }
423
424 /**
425 * @brief Enable I2C master mode.
426 *
427 * Register|BitsName
428 * ---------------|---------------
429 * CTRL | MASTER_ENABLE
430 * CTRL | SLAVE_DISABLE
431 * @param I2Cx I2C instance.
432 * @retval None.
433 */
434 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
435 {
436 SET_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
437 }
438
439 /**
440 * @brief Disable I2C master mode and enable slave mode.
441 *
442 * Register|BitsName
443 * ---------------|---------------
444 * CTRL | MASTER_ENABLE
445 * CTRL | SLAVE_DISABLE
446 * @param I2Cx I2C instance.
447 * @retval None.
448 */
449 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
450 {
451 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
452 }
453
454 /**
455 * @brief Check if I2C master mode is enabled or disabled.
456 *
457 * Register|BitsName
458 * ---------------|---------------
459 * CTRL | MASTER_ENABLE
460 * CTRL | SLAVE_DISABLE
461 *
462 * @param I2Cx I2C instance.
463 * @retval State of bit (1 or 0).
464 */
465 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
466 {
467 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS) == (I2C_CTRL_M_MODE | I2C_CTRL_S_DIS));
468 }
469
470 /**
471 * @brief Enable General Call(slave mode).
472 * @note When enabled, the Address 0x00 is ACKed.
473 *
474 * Register|BitsName
475 * ---------------|---------------
476 * ACK_GEN_CALL | ACK_GEN_CALL
477 *
478 * @param I2Cx I2C instance.
479 * @retval None.
480 */
481 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
482 {
483 SET_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
484 }
485
486 /**
487 * @brief Disable General Call(slave mode).
488 * @note When disabled, the Address 0x00 is NACKed.
489 *
490 * Register|BitsName
491 * ---------------|---------------
492 * ACK_GEN_CALL | ACK_GEN_CALL
493 *
494 * @param I2Cx I2C instance.
495 * @retval None.
496 */
497 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
498 {
499 CLEAR_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
500 }
501
502 /**
503 * @brief Check if General Call is enabled or disabled(slave mode).
504 *
505 * Register|BitsName
506 * ---------------|---------------
507 * ACK_GEN_CALL | ACK_GEN_CALL
508 *
509 * @param I2Cx I2C instance.
510 * @retval State of bit (1 or 0).
511 */
512 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
513 {
514 return (READ_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL) == (I2C_ACK_GEN_CALL_ACK_GEN_CALL));
515 }
516
517 /**
518 * @brief Enable Master Restart.
519 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
520 * This bit determines whether RESTART conditions may be sent when acting as a master.
521 * Some older slaves do not support handling RESTART conditions.
522 * When RESTART is disabled, the master is prohibited from performing the following functions:
523 * - Performing any high-speed mode operation.
524 * - Performing direction changes in combined format mode.
525 * - Performing a read operation with a 10-bit address.
526 *
527 * Register|BitsName
528 * ---------------|---------------
529 * CTRL | RESTART_EN
530 *
531 * @param I2Cx I2C instance.
532 * @retval None.
533 */
534 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
535 {
536 SET_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
537 }
538
539 /**
540 * @brief Disable Master Restart.
541 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
542 *
543 * Register|BitsName
544 * ---------------|---------------
545 * CTRL | RESTART_EN
546 *
547 * @param I2Cx I2C instance.
548 * @retval None.
549 */
550 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
551 {
552 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
553 }
554
555 /**
556 * @brief Check if Master Restart is enabled or disabled.
557 *
558 * Register|BitsName
559 * ---------------|---------------
560 * CTRL | RESTART_EN
561 *
562 * @param I2Cx I2C instance.
563 * @retval State of bit (1 or 0).
564 */
565 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
566 {
567 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN) == (I2C_CTRL_RESTART_EN));
568 }
569
570 /**
571 * @brief Enable Slave issues STOP_DET interrupt only if addressed function.
572 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
573 * During a general call address, the slave does not issue the STOP_DET interrupt if
574 * STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address
575 * by generating ACK. The STOP_DET interrupt is generated only when the transmitted
576 * address matches the slave address (SAR).
577 *
578 * Register|BitsName
579 * ---------------|---------------
580 * CTRL | STOP_DET_INT
581 *
582 * @param I2Cx I2C instance.
583 * @retval None.
584 */
585 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
586 {
587 SET_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
588 }
589
590 /**
591 * @brief Disable Slave issues STOP_DET interrupt only if addressed function.
592 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
593 *
594 * Register|BitsName
595 * ---------------|---------------
596 * CTRL | STOP_DET_INT
597 *
598 * @param I2Cx I2C instance.
599 * @retval None.
600 */
601 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
602 {
603 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
604 }
605
606 /**
607 * @brief Hold bus when the RX FIFO if full function.
608 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
609 *
610 * Register|BitsName
611 * ---------------|---------------
612 * CTRL | RXFIFO_FULL_HLD
613 *
614 * @param I2Cx I2C instance.
615 * @retval None.
616 */
617 __STATIC_INLINE void ll_i2c_hold_bus_if_rx_full(i2c_regs_t *I2Cx)
618 {
619 SET_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
620 }
621
622 /**
623 * @brief overflow when the RX FIFO if full function.
624 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
625 *
626 * Register|BitsName
627 * ---------------|---------------
628 * CTRL | RXFIFO_FULL_HLD
629 *
630 * @param I2Cx I2C instance.
631 * @retval None.
632 */
633 __STATIC_INLINE void ll_i2c_overflow_if_rx_full(i2c_regs_t *I2Cx)
634 {
635 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
636 }
637
638 /**
639 * @brief enable bus clear feature function.
640 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
641 *
642 * Register|BitsName
643 * ---------------|---------------
644 * CTRL | BUS_CLR_FEATURE
645 *
646 * @param I2Cx I2C instance.
647 * @retval None.
648 */
649 __STATIC_INLINE void ll_i2c_enable_bus_clear_feature(i2c_regs_t *I2Cx)
650 {
651 SET_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
652 }
653
654 /**
655 * @brief disable bus clear feature function.
656 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
657 *
658 * Register|BitsName
659 * ---------------|---------------
660 * CTRL | BUS_CLR_FEATURE
661 *
662 * @param I2Cx I2C instance.
663 * @retval None.
664 */
665 __STATIC_INLINE void ll_i2c_disable_bus_clear_feature(i2c_regs_t *I2Cx)
666 {
667 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
668 }
669
670 /**
671 * @brief check bus clear feature is enabled function.
672 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
673 *
674 * Register|BitsName
675 * ---------------|---------------
676 * CTRL | BUS_CLR_FEATURE
677 *
678 * @param I2Cx I2C instance.
679 * @retval None.
680 */
681 __STATIC_INLINE uint32_t ll_i2c_is_enabled_bus_clear_feature(i2c_regs_t *I2Cx)
682 {
683 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE) == (I2C_CTRL_BUS_CLR_FEATURE));
684 }
685
686 /**
687 * @brief Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
688 *
689 * Register|BitsName
690 * ---------------|---------------
691 * CTRL | STOP_DET_INT
692 *
693 * @param I2Cx I2C instance.
694 * @retval State of bit (1 or 0).
695 */
696 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
697 {
698 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT) == (I2C_CTRL_STOP_DET_INT));
699 }
700
701 /**
702 * @brief Configure the Master to transfers in 7-bit or 10-bit addressing mode.
703 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
704 *
705 * Register|BitsName
706 * ---------------|---------------
707 * CTRL | ADDR_BIT_M
708 *
709 * @param I2Cx I2C instance.
710 * @param addressing_mode This parameter can be one of the following values:
711 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
712 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
713 * @retval None.
714 */
715 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
716 {
717 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M, addressing_mode);
718 }
719
720 /**
721 * @brief Get the Master addressing mode.
722 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
723 *
724 * Register|BitsName
725 * ---------------|---------------
726 * CTRL | ADDR_BIT_M
727 *
728 * @param I2Cx I2C instance.
729 * @retval Returned value can be one of the following values:
730 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
731 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
732 */
733 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
734 {
735 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M));
736 }
737
738 /**
739 * @brief Set the Own Address.
740 * @note The register IC_CON and IC_SAR can only be programmed when the I2C is disabled (IC_ENABLE = 0).
741 *
742 * Register|BitsName
743 * ---------------|---------------
744 * CTRL | ADDR_BIT_S
745 * S_ADDR | SAR
746 *
747 * @param I2Cx I2C instance.
748 * @param own_address This parameter must be a value range between 0 ~ 0x3FF(10-bit mode) or 0 ~ 0x7F(7-bit mode).
749 * Reserved address 0x00 to 0x07, or 0x78 to 0x7f should not be configured.
750 * @param own_addr_size This parameter can be one of the following values:
751 * @arg @ref LL_I2C_OWNADDRESS_7BIT
752 * @arg @ref LL_I2C_OWNADDRESS_10BIT
753 * @retval None.
754 */
755 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
756 {
757 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_S, own_addr_size);
758 WRITE_REG(I2Cx->S_ADDR, own_address);
759 }
760
761 /**
762 * @brief Set the SCL clock high-period count for standard speed.
763 * @note The register IC_SS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
764 *
765 * Register|BitsName
766 * ---------------|---------------
767 * SS_CLK_HCOUNT | SS_SCL_HCNT
768 *
769 * @param I2Cx I2C instance.
770 * @param count This parameter must be a value range between 6 ~ 0xFFF5.
771 * @retval None.
772 */
773 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
774 {
775 WRITE_REG(I2Cx->SS_CLK_HCOUNT, count);
776 }
777
778 /**
779 * @brief Get the SCL clock high-period count for standard speed.
780 *
781 * Register|BitsName
782 * ---------------|---------------
783 * SS_CLK_HCOUNT | COUNT
784 *
785 * @param I2Cx I2C instance.
786 * @retval Value range between 0x6 and 0xFFF5.
787 */
788 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
789 {
790 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_HCOUNT, I2C_SS_CLK_HCOUNT_COUNT));
791 }
792
793 /**
794 * @brief Set the SCL clock low-period count for standard speed.
795 * @note The register IC_SS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
796 *
797 * Register|BitsName
798 * ---------------|---------------
799 * SS_CLK_LCOUNT | COUNT
800 *
801 * @param I2Cx I2C instance.
802 * @param count This parameter must be a value range between 0x8 and 0xFFFF.
803 * @retval None.
804 */
805 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
806 {
807 WRITE_REG(I2Cx->SS_CLK_LCOUNT, count);
808 }
809
810 /**
811 * @brief Get the SCL clock low-period count for standard speed.
812 *
813 * Register|BitsName
814 * ---------------|---------------
815 * SS_CLK_LCOUNT | COUNT
816 *
817 * @param I2Cx I2C instance.
818 * @retval Value range between 0x8 and 0xFFFF.
819 */
820 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
821 {
822 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_LCOUNT, I2C_SS_CLK_LCOUNT_COUNT));
823 }
824
825 /**
826 * @brief Set the SCL clock high-period count for fast speed.
827 * @note The register IC_FS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
828 *
829 * Register|BitsName
830 * ---------------|---------------
831 * FS_CLK_HCOUNT | COUNT
832 *
833 * @param I2Cx I2C instance.
834 * @param count range between 0x6 and 0xFFFF.
835 * @retval None.
836 */
837 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
838 {
839 WRITE_REG(I2Cx->FS_CLK_HCOUNT, count);
840 }
841
842 /**
843 * @brief Get the SCL clock high-period count for fast speed.
844 *
845 * Register|BitsName
846 * ---------------|---------------
847 * FS_CLK_HCOUNT | COUNT
848 *
849 * @param I2Cx I2C instance.
850 * @retval Value range between 0x6 and 0xFFFF.
851 */
852 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
853 {
854 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_HCOUNT, I2C_FS_CLK_HCOUNT_COUNT));
855 }
856
857 /**
858 * @brief Set the SCL clock low-period count for fast speed.
859 * @note The register IC_FS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
860 *
861 * Register|BitsName
862 * ---------------|---------------
863 * FS_CLK_LCOUNT | COUNT
864 *
865 * @param I2Cx I2C instance.
866 * @param count range between 0x8 and 0xFFFF
867 * @retval None.
868 */
869 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
870 {
871 WRITE_REG(I2Cx->FS_CLK_LCOUNT, count);
872 }
873
874 /**
875 * @brief Get the SCL clock low-period count for fast speed.
876 *
877 * Register|BitsName
878 * ---------------|---------------
879 * FS_CLK_LCOUNT | COUNT
880 *
881 * @param I2Cx I2C instance.
882 * @retval Value range between 0x8 and 0xFFFF.
883 */
884 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
885 {
886 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_LCOUNT, I2C_FS_CLK_LCOUNT_COUNT));
887 }
888
889 /**
890 * @brief Get the SCL clock high-period count for high speed.
891 * @note The register IC_HS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
892 *
893 * Register|BitsName
894 * ---------------|---------------
895 * HS_CLK_HCOUNT | COUNT
896 *
897 * @param I2Cx I2C instance.
898 * @param count range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 5.
899 * @retval None.
900 */
901 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
902 {
903 WRITE_REG(I2Cx->HS_CLK_HCOUNT, count);
904 }
905
906 /**
907 * @brief Get the SCL clock high-period count for high speed.
908 *
909 * Register|BitsName
910 * ---------------|---------------
911 * HS_CLK_HCOUNT | COUNT
912 *
913 * @param I2Cx I2C instance.
914 * @retval range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 7.
915 */
916 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
917 {
918 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_HCOUNT, I2C_HS_CLK_HCOUNT_COUNT));
919 }
920
921 /**
922 * @brief Get the SCL clock low-period count for high speed.
923 * @note The register IC_HS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
924 *
925 * Register|BitsName
926 * ---------------|---------------
927 * HS_CLK_LCOUNT | COUNT
928 *
929 * @param I2Cx I2C instance.
930 * @param count range between 0x8 and 0xFFFF
931 * @retval None.
932 */
933 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
934 {
935 WRITE_REG(I2Cx->HS_CLK_LCOUNT, count);
936 }
937
938 /**
939 * @brief Get the SCL clock low-period count for high speed.
940 *
941 * Register|BitsName
942 * ---------------|---------------
943 * HS_CLK_LCOUNT | COUNT
944 *
945 * @param I2Cx I2C instance.
946 * @retval Value range between 0x8 and 0xFFFF
947 */
948 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
949 {
950 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_LCOUNT, I2C_HS_CLK_LCOUNT_COUNT));
951 }
952
953 /**
954 * @brief Set the spike len in fast speed mode.
955 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
956 *
957 * Register|BitsName
958 * ---------------|---------------
959 * FS_SPKLEN | FS_SPKLEN
960 *
961 * @param I2Cx I2C instance.
962 * @param length Spike len.
963 * @retval None.
964 */
965 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
966 {
967 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
968 }
969
970 /**
971 * @brief Get the spike len in fast speed mode.
972 *
973 * Register|BitsName
974 * ---------------|---------------
975 * FS_SPKLEN | FS_SPKLEN
976 *
977 * @param I2Cx I2C instance.
978 * @retval Value range between 0x2 and 0xFF.
979 */
980 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
981 {
982 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
983 }
984
985 /**
986 * @brief Set the spike len in high speed mode.
987 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
988 *
989 * Register|BitsName
990 * ---------------|---------------
991 * HS_SPKLEN | HS_SPKLEN
992 *
993 * @param I2Cx I2C instance.
994 * @param length Spike len.
995 * @retval None.
996 */
997 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
998 {
999 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
1000 }
1001
1002 /**
1003 * @brief Get the spike len in high speed mode.
1004 *
1005 * Register|BitsName
1006 * ---------------|---------------
1007 * HS_SPKLEN | HS_SPKLEN
1008 *
1009 * @param I2Cx I2C instance.
1010 * @retval Value range between 0x2 and 0xFF.
1011 */
1012 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
1013 {
1014 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
1015 }
1016
1017 /**
1018 * @brief Set I2C Speed mode.
1019 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1020 *
1021 * Register|BitsName
1022 * ---------------|---------------
1023 * CTRL | SPEED
1024 *
1025 * @param I2Cx I2C instance.
1026 * @param speed_mode This parameter can be one of the following values:
1027 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1028 * @arg @ref LL_I2C_SPEED_MODE_FAST
1029 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1030 * @retval None.
1031 */
1032 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
1033 {
1034 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_SPEED, speed_mode);
1035 }
1036
1037 /**
1038 * @brief Get I2C Speed mode.
1039 *
1040 * Register|BitsName
1041 * ---------------|---------------
1042 * CTRL | SPEED
1043 *
1044 * @param I2Cx I2C instance.
1045 * @retval Value can be one of the following values:
1046 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1047 * @arg @ref LL_I2C_SPEED_MODE_FAST
1048 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1049 */
1050 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
1051 {
1052 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_SPEED));
1053 }
1054
1055 /**
1056 * @brief Set I2C High Speed Master Code Address.
1057 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1058 *
1059 * Register|BitsName
1060 * ---------------|---------------
1061 * M_HS_ADDR | HS_MAR
1062 *
1063 * @param I2Cx I2C instance.
1064 * @param code HS mode master code, range between 0x00 and 0x07.
1065 * @retval None.
1066 */
1067 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
1068 {
1069 WRITE_REG(I2Cx->M_HS_ADDR, code);
1070 }
1071
1072 /**
1073 * @brief Get I2C Speed mode.
1074 *
1075 * Register|BitsName
1076 * ---------------|---------------
1077 * M_HS_ADDR | HS_MAR
1078 *
1079 * @param I2Cx I2C instance.
1080 * @retval Returned value range between 0x00 and 0x07.
1081 */
1082 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
1083 {
1084 return (uint32_t)(READ_BITS(I2Cx->M_HS_ADDR, I2C_M_HS_ADDR_HS_ADDR));
1085 }
1086
1087 /**
1088 * @brief Set the required transmit SDA hold time in units of ic_clk period.
1089 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1090 *
1091 * Register|BitsName
1092 * ---------------|---------------
1093 * SDA_HOLD | TX_HOLD
1094 *
1095 * @param I2Cx I2C instance.
1096 * @param time SDA Tx hold time in units of ic_clk period.
1097 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1098 * @retval None.
1099 */
1100 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1101 {
1102 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_POS);
1103 }
1104
1105 /**
1106 * @brief Get the required transmit SDA hold time in units of ic_clk period.
1107 *
1108 * Register|BitsName
1109 * ---------------|---------------
1110 * SDA_HOLD | TX_HOLD
1111 *
1112 * @param I2Cx I2C instance.
1113 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1114 */
1115 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
1116 {
1117 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_POS);
1118 }
1119
1120 /**
1121 * @brief Set the required receive SDA hold time in units of ic_clk period.
1122 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1123 *
1124 * Register|BitsName
1125 * ---------------|---------------
1126 * SDA_HOLD | RX_HOLD
1127 *
1128 * @param I2Cx I2C instance.
1129 * @param time SDA Tx hold time in units of ic_clk period.
1130 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1131 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1132 */
1133 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1134 {
1135 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_POS);
1136 }
1137
1138 /**
1139 * @brief Get the required receive SDA hold time in units of ic_clk period.
1140 *
1141 * Register|BitsName
1142 * ---------------|---------------
1143 * SDA_HOLD | RX_HOLD
1144 *
1145 * @param I2Cx I2C instance.
1146 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1147 */
1148 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1149 {
1150 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_POS);
1151 }
1152
1153 /**
1154 * @brief Set the SDA setup time when operating as a slave transmitter.
1155 * @note The register IC_SDA_SETUP can only be programmed when the I2C is disabled (ENABLE = 0).
1156 * The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the
1157 * user requires 10 ic_clk periods of setup time, they should program a value of 11.
1158 *
1159 * Register|BitsName
1160 * ---------------|---------------
1161 * SDA_SETUP | SETUP
1162 *
1163 * @param I2Cx I2C instance.
1164 * @param time SDA data setup time in units of ic_clk period, range between 2 ~ 0xFF.
1165 * @retval None.
1166 */
1167 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1168 {
1169 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP, time);
1170 }
1171
1172 /**
1173 * @brief Get the SDA setup time when operating as a slave transmitter.
1174 *
1175 * Register|BitsName
1176 * ---------------|---------------
1177 * SDA_SETUP | SETUP
1178 *
1179 * @param I2Cx I2C instance.
1180 * @retval Value range between 0x02 and 0xFF.
1181 */
1182 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1183 {
1184 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP));
1185 }
1186
1187 /**
1188 * @brief Set threshold of entries (or below) that trigger the TX_EMPTY interrupt
1189 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1190 *
1191 * Register|BitsName
1192 * ---------------|---------------
1193 * TX_FIFO_THD | THD
1194 *
1195 * @param I2Cx I2C instance
1196 * @param threshold This parameter can be one of the following values:
1197 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1198 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1199 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1200 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1201 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1202 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1203 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1204 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1205 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_8
1206 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_9
1207 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_10
1208 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_11
1209 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_12
1210 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_13
1211 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_14
1212 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_15
1213 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_16
1214 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_17
1215 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_18
1216 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_19
1217 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_20
1218 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_21
1219 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_22
1220 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_23
1221 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_24
1222 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_25
1223 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_26
1224 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_27
1225 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_28
1226 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_29
1227 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_30
1228 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_31
1229 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_32
1230 * @retval None.
1231 */
1232 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1233 {
1234 WRITE_REG(I2Cx->TX_FIFO_THD, threshold);
1235 }
1236
1237 /**
1238 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
1239 *
1240 * Register|BitsName
1241 * ---------------|---------------
1242 * TX_FIFO_THD | THD
1243 *
1244 * @param I2Cx I2C instance
1245 * @retval Returned value can be one of the following values:
1246 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1247 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1248 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1249 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1250 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1251 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1252 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1253 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1254 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_8
1255 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_9
1256 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_10
1257 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_11
1258 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_12
1259 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_13
1260 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_14
1261 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_15
1262 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_16
1263 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_17
1264 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_18
1265 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_19
1266 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_20
1267 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_21
1268 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_22
1269 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_23
1270 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_24
1271 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_25
1272 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_26
1273 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_27
1274 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_28
1275 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_29
1276 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_30
1277 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_31
1278 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_32
1279 */
1280 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1281 {
1282 return (uint32_t)(READ_BITS(I2Cx->TX_FIFO_THD, I2C_TX_FIFO_THD_THD));
1283 }
1284
1285 /**
1286 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
1287 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1288 *
1289 * Register|BitsName
1290 * ---------------|---------------
1291 * RX_FIFO_THD | THD
1292 *
1293 * @param I2Cx I2C instance
1294 * @param threshold This parameter can be one of the following values:
1295 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1296 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1297 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1298 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1299 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1300 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1301 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1302 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_8
1303 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_9
1304 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_10
1305 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_11
1306 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_12
1307 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_13
1308 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_14
1309 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_15
1310 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_16
1311 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_17
1312 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_18
1313 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_19
1314 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_20
1315 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_21
1316 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_22
1317 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_23
1318 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_24
1319 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_25
1320 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_26
1321 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_27
1322 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_28
1323 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_29
1324 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_30
1325 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_31
1326 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_32
1327 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1328 * @retval None.
1329 */
1330 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1331 {
1332 WRITE_REG(I2Cx->RX_FIFO_THD, threshold);
1333 }
1334
1335 /**
1336 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
1337 *
1338 * Register|BitsName
1339 * ---------------|---------------
1340 * RX_FIFO_THD | THD
1341 *
1342 * @param I2Cx I2C instance
1343 * @retval Returned value can be one of the following values:
1344 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1345 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1346 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1347 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1348 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1349 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1350 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1351 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_8
1352 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_9
1353 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_10
1354 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_11
1355 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_12
1356 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_13
1357 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_14
1358 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_15
1359 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_16
1360 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_17
1361 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_18
1362 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_19
1363 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_20
1364 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_21
1365 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_22
1366 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_23
1367 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_24
1368 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_25
1369 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_26
1370 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_27
1371 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_28
1372 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_29
1373 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_30
1374 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_31
1375 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_32
1376 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1377 */
1378 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1379 {
1380 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_THD, I2C_RX_FIFO_THD_THD));
1381 }
1382
1383 /**
1384 * @brief Get FIFO Transmission Level
1385 *
1386 * Register|BitsName
1387 * ---------------|---------------
1388 * RX_FIFO_THD | LEVEL
1389 *
1390 * @param I2Cx I2C instance
1391 * @retval Value range between 0x0 and 0x1F.
1392 */
1393 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1394 {
1395 return (uint32_t)(READ_BITS(I2Cx->TX_FIFO_LEVEL, I2C_TX_FIFO_LEVEL_LEVEL));
1396 }
1397
1398 /**
1399 * @brief Get FIFO reception Level
1400 *
1401 * Register|BitsName
1402 * ---------------|---------------
1403 * RX_FIFO_THD | LEVEL
1404 *
1405 * @param I2Cx I2C instance
1406 * @retval Value range between 0x0 and 0x1F.
1407 */
1408 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1409 {
1410 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_LEVEL, I2C_RX_FIFO_LEVEL_LEVEL));
1411 }
1412
1413 /**
1414 * @brief Master initates the SDA stuck at low recovery mechanism.
1415 *
1416 * Register|BitsName
1417 * ---------------|---------------
1418 * EN | SDA_STUCK_RECOVERY
1419 *
1420 * @param I2Cx I2C instance
1421 */
1422 __STATIC_INLINE void ll_i2c_enable_sda_stuck_recovery(i2c_regs_t *I2Cx)
1423 {
1424 SET_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1425 }
1426
1427 /**
1428 * @brief Master disabled the SDA stuck at low recovery mechanism
1429 *
1430 * Register|BitsName
1431 * ---------------|---------------
1432 * EN | SDA_STUCK_RECOVERY
1433 *
1434 * @param I2Cx I2C instance
1435 */
1436 __STATIC_INLINE void ll_i2c_disable_sda_stuck_recovery(i2c_regs_t *I2Cx)
1437 {
1438 CLEAR_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1439 }
1440
1441 /**
1442 * @brief the SDA stuck at low recovery mechanism is enabled or disabled.
1443 *
1444 * Register|BitsName
1445 * ---------------|---------------
1446 * EN | SDA_STUCK_RECOVERY
1447 *
1448 * @param I2Cx I2C instance
1449 * @retval State of bit (1 or 0).
1450 */
1451 __STATIC_INLINE uint32_t ll_i2c_is_enabled_sda_stuck_recovery(i2c_regs_t *I2Cx)
1452 {
1453 return (READ_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY) == (I2C_EN_SDA_STUCK_RECOVERY));
1454 }
1455
1456 /**
1457 * @brief Enable DMA reception requests.
1458 *
1459 * Register|BitsName
1460 * ---------------|---------------
1461 * EN | ABORT
1462 *
1463 * @param I2Cx I2C instance.
1464 * @retval None.
1465 */
1466 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1467 {
1468 SET_BITS(I2Cx->EN, I2C_EN_ABORT);
1469 }
1470
1471 /**
1472 * @brief Check if DMA reception requests are enabled or disabled.
1473 *
1474 * Register|BitsName
1475 * ---------------|---------------
1476 * EN | ABORT
1477 *
1478 * @param I2Cx I2C instance.
1479 * @retval State of bit (1 or 0).
1480 */
1481 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1482 {
1483 return (READ_BITS(I2Cx->EN, I2C_EN_ABORT) == (I2C_EN_ABORT));
1484 }
1485
1486 /**
1487 * @brief Get the transmit abort source.
1488 * @note This can be used to retrieve source of TX_ABRT interrupt.
1489 *
1490 * Register|BitsName
1491 * ---------------|---------------
1492 * TX_ABORT_SRC | ABRT_USER_ABRT
1493 * TX_ABORT_SRC | ABRT_SLVRD_INTX
1494 * TX_ABORT_SRC | ABRT_SLV_ARBLOST
1495 * TX_ABORT_SRC | ABRT_SLVFLUSH_TXFIFO
1496 * TX_ABORT_SRC | ABRT_ARB_LOST
1497 * TX_ABORT_SRC | ABRT_MST_DIS
1498 * TX_ABORT_SRC | ABRT_10B_RD_NORSTRT
1499 * TX_ABORT_SRC | ABRT_SBYTE_NORSTRT
1500 * TX_ABORT_SRC | ABRT_HS_NORSTRT
1501 * TX_ABORT_SRC | ABRT_SBYTE_ACKDET
1502 * TX_ABORT_SRC | ABRT_HS_ACKDET
1503 * TX_ABORT_SRC | ABRT_GCALL_READ
1504 * TX_ABORT_SRC | ABRT_GCALL_NOACK
1505 * TX_ABORT_SRC | ABRT_TXDATA_NOACK
1506 * TX_ABORT_SRC | ABRT_10ADDR2_NOACK
1507 * TX_ABORT_SRC | ABRT_10ADDR1_NOACK
1508 * TX_ABORT_SRC | ABRT_7B_ADDR_NOACK
1509 *
1510 * @param I2Cx I2C instance
1511 * @retval Returned value can be a combination of the following values:
1512 * @arg @ref LL_I2C_ABRT_USER_ABRT
1513 * @arg @ref LL_I2C_ABRT_SLVRD_INTX
1514 * @arg @ref LL_I2C_ABRT_SLV_ARBLOST
1515 * @arg @ref LL_I2C_ABRT_SLVFLUSH_TXFIFO
1516 * @arg @ref LL_I2C_ABRT_ARB_LOST
1517 * @arg @ref LL_I2C_ABRT_MST_DIS
1518 * @arg @ref LL_I2C_ABRT_10B_RD_NORSTRT
1519 * @arg @ref LL_I2C_ABRT_SBYTE_NORSTRT
1520 * @arg @ref LL_I2C_ABRT_HS_NORSTRT
1521 * @arg @ref LL_I2C_ABRT_SBYTE_ACKDET
1522 * @arg @ref LL_I2C_ABRT_HS_ACKDET
1523 * @arg @ref LL_I2C_ABRT_GCALL_READ
1524 * @arg @ref LL_I2C_ABRT_GCALL_NOACK
1525 * @arg @ref LL_I2C_ABRT_TXDATA_NOACK
1526 * @arg @ref LL_I2C_ABRT_10ADDR2_NOACK
1527 * @arg @ref LL_I2C_ABRT_10ADDR1_NOACK
1528 * @arg @ref LL_I2C_ABRT_7B_ADDR_NOACK
1529 *
1530 * @note @arg @ref LL_I2C_ABRT_TX_FLUSH_CNT can be used as a mask to get the
1531 * number of Tx FIFO Data Commands which are flushed due to TX_ABRT
1532 * interrupt.
1533 */
1534 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1535 {
1536 return (uint32_t)(READ_REG(I2Cx->TX_ABORT_SRC) & (~I2C_TX_ABORT_SRC_TX_FLUSH_CNT));
1537 }
1538
1539 /**
1540 * @brief Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
1541 *
1542 * Register|BitsName
1543 * ---------------|---------------
1544 * TX_ABORT_SRC | TX_FLUSH_CNT
1545 *
1546 * @param I2Cx I2C instance
1547 * @retval Tx flush count.
1548 */
1549 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1550 {
1551 return (uint32_t)(READ_BITS(I2Cx->TX_ABORT_SRC, I2C_TX_ABORT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABORT_SRC_TX_FLUSH_CNT_POS);
1552 }
1553
1554 /** @} */
1555
1556 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1557 * @{
1558 */
1559
1560 /**
1561 * @brief Enable specified interrupts.
1562 *
1563 * Register|BitsName
1564 * ---------------|---------------
1565 * INT_MASK | MASK_GEN_CALL
1566 * INT_MASK | MASK_START_DET
1567 * INT_MASK | MASK_STOP_DET
1568 * INT_MASK | MASK_ACTIVITY
1569 * INT_MASK | MASK_RX_DONE
1570 * INT_MASK | MASK_TX_ABRT
1571 * INT_MASK | MASK_RD_REQ
1572 * INT_MASK | MASK_TX_EMPTY
1573 * INT_MASK | MASK_TX_OVER
1574 * INT_MASK | MASK_RX_FULL
1575 * INT_MASK | MASK_RX_OVER
1576 * INT_MASK | MASK_RX_UNDER
1577 *
1578 * @param I2Cx I2C instance.
1579 * @param mask This parameter can be a combination of the following values:
1580 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1581 * @arg @ref LL_I2C_INTR_MASK_START_DET
1582 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1583 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1584 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1585 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1586 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1587 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1588 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1589 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1590 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1591 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1592 * @retval None.
1593 */
1594 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1595 {
1596 SET_BITS(I2Cx->INT_MASK, mask);
1597 }
1598
1599 /**
1600 * @brief Disable specified interrupts.
1601 *
1602 * Register|BitsName
1603 * ---------------|---------------
1604 * INT_MASK | MASK_GEN_CALL
1605 * INT_MASK | MASK_START_DET
1606 * INT_MASK | MASK_STOP_DET
1607 * INT_MASK | MASK_ACTIVITY
1608 * INT_MASK | MASK_RX_DONE
1609 * INT_MASK | MASK_TX_ABRT
1610 * INT_MASK | MASK_RD_REQ
1611 * INT_MASK | MASK_TX_EMPTY
1612 * INT_MASK | MASK_TX_OVER
1613 * INT_MASK | MASK_RX_FULL
1614 * INT_MASK | MASK_RX_OVER
1615 * INT_MASK | MASK_RX_UNDER
1616 *
1617 * @param I2Cx I2C instance.
1618 * @param mask This parameter can be a combination of the following values:
1619 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1620 * @arg @ref LL_I2C_INTR_MASK_START_DET
1621 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1622 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1623 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1624 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1625 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1626 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1627 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1628 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1629 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1630 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1631 * @retval None.
1632 */
1633 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1634 {
1635 CLEAR_BITS(I2Cx->INT_MASK, mask);
1636 }
1637
1638 /**
1639 * @brief Check if the specified interrupts are enabled or disabled.
1640 *
1641 * Register|BitsName
1642 * ---------------|---------------
1643 * INT_MASK | MASK_GEN_CALL
1644 * INT_MASK | MASK_START_DET
1645 * INT_MASK | MASK_STOP_DET
1646 * INT_MASK | MASK_ACTIVITY
1647 * INT_MASK | MASK_RX_DONE
1648 * INT_MASK | MASK_TX_ABRT
1649 * INT_MASK | MASK_RD_REQ
1650 * INT_MASK | MASK_TX_EMPTY
1651 * INT_MASK | MASK_TX_OVER
1652 * INT_MASK | MASK_RX_FULL
1653 * INT_MASK | MASK_RX_OVER
1654 * INT_MASK | MASK_RX_UNDER
1655 *
1656 * @param I2Cx I2C instance.
1657 * @param mask This parameter can be a combination of the following values:
1658 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1659 * @arg @ref LL_I2C_INTR_MASK_START_DET
1660 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1661 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1662 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1663 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1664 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1665 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1666 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1667 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1668 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1669 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1670 * @retval State of bit (1 or 0).
1671 */
1672 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1673 {
1674 return (READ_BITS(I2Cx->INT_MASK, mask) == (mask));
1675 }
1676
1677 /**
1678 * @brief Enable SCL_STUCK_AT_LOW interrupt.
1679 *
1680 * Register|BitsName
1681 * ---------------|---------------
1682 * INT_MASK | SCL_STUCK_AT_LOW
1683 *
1684 * @param I2Cx I2C instance.
1685 * @retval None.
1686 */
1687 __STATIC_INLINE void ll_i2c_enable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1688 {
1689 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1690 }
1691 /**
1692 * @brief Disable SCL_STUCK_AT_LOW interrupt.
1693 *
1694 * Register|BitsName
1695 * ---------------|---------------
1696 * INT_MASK | SCL_STUCK_AT_LOW
1697 *
1698 * @param I2Cx I2C instance.
1699 * @retval None.
1700 */
1701 __STATIC_INLINE void ll_i2c_disable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1702 {
1703 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1704 }
1705 /**
1706 * @brief Check if the SCL_STUCK_AT_LOW Interrupt is enabled or disabled.
1707 *
1708 * Register|BitsName
1709 * ---------------|---------------
1710 * INT_MASK | SCL_STUCK_AT_LOW
1711 *
1712 * @param I2Cx I2C instance.
1713 * @retval State of bit (1 or 0).
1714 */
1715 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1716 {
1717 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW) == (I2C_INT_MASK_MASK_SCL_STUCKLOW));
1718 }
1719
1720
1721 /**
1722 * @brief Enable MASTER_ON_HOLD interrupt.
1723 *
1724 * Register|BitsName
1725 * ---------------|---------------
1726 * INT_MASK | M_HOLD
1727 *
1728 * @param I2Cx I2C instance.
1729 * @retval None.
1730 */
1731 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1732 {
1733 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1734 }
1735
1736 /**
1737 * @brief Disable MASTER_ON_HOLD interrupt.
1738 *
1739 * Register|BitsName
1740 * ---------------|---------------
1741 * INT_MASK | M_HOLD
1742 *
1743 * @param I2Cx I2C instance.
1744 * @retval None.
1745 */
1746 __STATIC_INLINE void ll_i2c_disable_it_master_on_hold(i2c_regs_t *I2Cx)
1747 {
1748 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1749 }
1750
1751 /**
1752 * @brief Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
1753 *
1754 * Register|BitsName
1755 * ---------------|---------------
1756 * INT_MASK | M_HOLD
1757 *
1758 * @param I2Cx I2C instance.
1759 * @retval State of bit (1 or 0).
1760 */
1761 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1762 {
1763 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD) == (I2C_INT_MASK_MASK_M_HOLD));
1764 }
1765
1766 /**
1767 * @brief Enable RESTART_DET interrupt.
1768 *
1769 * Register|BitsName
1770 * ---------------|---------------
1771 * INT_MASK | RESTART_DET
1772 *
1773 * @param I2Cx I2C instance.
1774 * @retval None.
1775 */
1776 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1777 {
1778 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1779 }
1780
1781 /**
1782 * @brief Disable RESTART_DET interrupt.
1783 *
1784 * Register|BitsName
1785 * ---------------|---------------
1786 * INT_MASK | RESTART_DET
1787 *
1788 * @param I2Cx I2C instance.
1789 * @retval None.
1790 */
1791 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1792 {
1793 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1794 }
1795
1796 /**
1797 * @brief Check if the RESTART_DET Interrupt is enabled or disabled.
1798 *
1799 * Register|BitsName
1800 * ---------------|---------------
1801 * INT_MASK | RESTART_DET
1802 *
1803 * @param I2Cx I2C instance.
1804 * @retval State of bit (1 or 0).
1805 */
1806 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1807 {
1808 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET) == (I2C_INT_MASK_MASK_RESTART_DET));
1809 }
1810
1811 /**
1812 * @brief Enable GEN_CALL interrupt.
1813 *
1814 * Register|BitsName
1815 * ---------------|---------------
1816 * INT_MASK | GEN_CALL
1817 *
1818 * @param I2Cx I2C instance.
1819 * @retval None.
1820 */
1821 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1822 {
1823 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1824 }
1825
1826 /**
1827 * @brief Disable GEN_CALL interrupt.
1828 *
1829 * Register|BitsName
1830 * ---------------|---------------
1831 * INT_MASK | GEN_CALL
1832 *
1833 * @param I2Cx I2C instance.
1834 * @retval None.
1835 */
1836 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1837 {
1838 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1839 }
1840
1841 /**
1842 * @brief Check if GEN_CALL interrupt is enabled or disabled.
1843 *
1844 * Register|BitsName
1845 * ---------------|---------------
1846 * INT_MASK | GEN_CALL
1847 *
1848 * @param I2Cx I2C instance.
1849 * @retval State of bit (1 or 0).
1850 */
1851 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1852 {
1853 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL) == (I2C_INT_MASK_MASK_GEN_CALL));
1854 }
1855
1856 /**
1857 * @brief Enable START_DET received interrupt.
1858 *
1859 * Register|BitsName
1860 * ---------------|---------------
1861 * INT_MASK | START_DET
1862 *
1863 * @param I2Cx I2C instance.
1864 * @retval None.
1865 */
1866 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1867 {
1868 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1869 }
1870
1871 /**
1872 * @brief Disable START_DET received interrupt.
1873 *
1874 * Register|BitsName
1875 * ---------------|---------------
1876 * INT_MASK | START_DET
1877 *
1878 * @param I2Cx I2C instance.
1879 * @retval None.
1880 */
1881 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1882 {
1883 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1884 }
1885
1886 /**
1887 * @brief Check if START_DET received interrupt is enabled or disabled.
1888 *
1889 * Register|BitsName
1890 * ---------------|---------------
1891 * INT_MASK | START_DET
1892 *
1893 * @param I2Cx I2C instance.
1894 * @retval State of bit (1 or 0).
1895 */
1896 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1897 {
1898 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET) == (I2C_INT_MASK_MASK_START_DET));
1899 }
1900
1901 /**
1902 * @brief Enable STOP_DET interrupt.
1903 *
1904 * Register|BitsName
1905 * ---------------|---------------
1906 * INT_MASK | STOP_DET
1907 *
1908 * @param I2Cx I2C instance.
1909 * @retval None.
1910 */
1911 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1912 {
1913 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1914 }
1915
1916 /**
1917 * @brief Disable STOP_DET interrupt.
1918 *
1919 * Register|BitsName
1920 * ---------------|---------------
1921 * INT_MASK | STOP_DET
1922 *
1923 * @param I2Cx I2C instance.
1924 * @retval None.
1925 */
1926 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1927 {
1928 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1929 }
1930
1931 /**
1932 * @brief Check if STOP_DET interrupt is enabled or disabled.
1933 *
1934 * Register|BitsName
1935 * ---------------|---------------
1936 * INT_MASK | STOP_DET
1937 *
1938 * @param I2Cx I2C instance.
1939 * @retval State of bit (1 or 0).
1940 */
1941 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1942 {
1943 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET) == (I2C_INT_MASK_MASK_STOP_DET));
1944 }
1945
1946 /**
1947 * @brief Enable ACTIVITY interrupt.
1948 *
1949 * Register|BitsName
1950 * ---------------|---------------
1951 * INT_MASK | ACTIVITY
1952 *
1953 * @param I2Cx I2C instance.
1954 * @retval None.
1955 */
1956 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1957 {
1958 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1959 }
1960
1961 /**
1962 * @brief Disable ACTIVITY interrupt.
1963 *
1964 * Register|BitsName
1965 * ---------------|---------------
1966 * INT_MASK | ACTIVITY
1967 *
1968 * @param I2Cx I2C instance.
1969 * @retval None.
1970 */
1971 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1972 {
1973 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1974 }
1975
1976 /**
1977 * @brief Check if ACTIVITY interrupt is enabled or disabled.
1978 *
1979 * Register|BitsName
1980 * ---------------|---------------
1981 * INT_MASK | ACTIVITY
1982 *
1983 * @param I2Cx I2C instance.
1984 * @retval State of bit (1 or 0).
1985 */
1986 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1987 {
1988 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY) == (I2C_INT_MASK_MASK_ACTIVITY));
1989 }
1990
1991 /**
1992 * @brief Enable RX_DONE interrupt.
1993 *
1994 * Register|BitsName
1995 * ---------------|---------------
1996 * INT_MASK | RX_DONE
1997 *
1998 * @param I2Cx I2C instance.
1999 * @retval State of bit (1 or 0).
2000 */
2001 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
2002 {
2003 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2004 }
2005
2006 /**
2007 * @brief Disable RX_DONE interrupt.
2008 *
2009 * Register|BitsName
2010 * ---------------|---------------
2011 * INT_MASK | RX_DONE
2012 *
2013 * @param I2Cx I2C instance.
2014 * @retval None.
2015 */
2016 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
2017 {
2018 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2019 }
2020
2021 /**
2022 * @brief Check if RX_DONE interrupt is enabled or disabled.
2023 *
2024 * Register|BitsName
2025 * ---------------|---------------
2026 * INT_MASK | RX_DONE
2027 *
2028 * @param I2Cx I2C instance.
2029 * @retval State of bit (1 or 0).
2030 */
2031 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
2032 {
2033 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE) == (I2C_INT_MASK_MASK_RX_DONE));
2034 }
2035
2036 /**
2037 * @brief Enable TX_ABRT interrupt.
2038 *
2039 * Register|BitsName
2040 * ---------------|---------------
2041 * INT_MASK | TX_ABORT
2042 *
2043 * @param I2Cx I2C instance.
2044 * @retval None.
2045 */
2046 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
2047 {
2048 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2049 }
2050
2051 /**
2052 * @brief Disable TX_ABRT interrupt.
2053 *
2054 * Register|BitsName
2055 * ---------------|---------------
2056 * INT_MASK | TX_ABORT
2057 *
2058 * @param I2Cx I2C instance.
2059 * @retval None.
2060 */
2061 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
2062 {
2063 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2064 }
2065
2066 /**
2067 * @brief Check if TX_ABRT interrupt is enabled or disabled.
2068 *
2069 * Register|BitsName
2070 * ---------------|---------------
2071 * INT_MASK | TX_ABORT
2072 *
2073 * @param I2Cx I2C instance.
2074 * @retval None.
2075 */
2076 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
2077 {
2078 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT) == (I2C_INT_MASK_MASK_TX_ABORT));
2079 }
2080
2081 /**
2082 * @brief Enable RD_REQ interrupt.
2083 *
2084 * Register|BitsName
2085 * ---------------|---------------
2086 * INT_MASK | RD_REQ
2087 *
2088 * @param I2Cx I2C instance.
2089 * @retval None.
2090 */
2091 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
2092 {
2093 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2094 }
2095
2096 /**
2097 * @brief Disable RD_REQ interrupt.
2098 *
2099 * Register|BitsName
2100 * ---------------|---------------
2101 * INT_MASK | RD_REQ
2102 *
2103 * @param I2Cx I2C instance.
2104 * @retval None.
2105 */
2106 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
2107 {
2108 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2109 }
2110
2111 /**
2112 * @brief Check if RD_REQ interrupt is enabled or disabled.
2113 *
2114 * Register|BitsName
2115 * ---------------|---------------
2116 * INT_MASK | RD_REQ
2117 *
2118 * @param I2Cx I2C instance.
2119 * @retval State of bit (1 or 0).
2120 */
2121 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
2122 {
2123 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ) == (I2C_INT_MASK_MASK_RD_REQ));
2124 }
2125
2126 /**
2127 * @brief Enable TX_EMPTY interrupt.
2128 *
2129 * Register|BitsName
2130 * ---------------|---------------
2131 * INT_MASK | TX_EMPTY
2132 *
2133 * @param I2Cx I2C instance.
2134 * @retval None.
2135 */
2136 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
2137 {
2138 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2139 }
2140
2141 /**
2142 * @brief Disable TX_EMPTY interrupt.
2143 *
2144 * Register|BitsName
2145 * ---------------|---------------
2146 * INT_MASK | TX_EMPTY
2147 *
2148 * @param I2Cx I2C instance.
2149 * @retval None.
2150 */
2151 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
2152 {
2153 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2154 }
2155
2156 /**
2157 * @brief Check if TX_EMPTY interrupt is enabled or disabled.
2158 *
2159 * Register|BitsName
2160 * ---------------|---------------
2161 * INT_MASK | TX_EMPTY
2162 *
2163 * @param I2Cx I2C instance.
2164 * @retval State of bit (1 or 0).
2165 */
2166 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
2167 {
2168 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY) == (I2C_INT_MASK_MASK_TX_EMPTY));
2169 }
2170
2171 /**
2172 * @brief Enable TX_OVER interrupt.
2173 *
2174 * Register|BitsName
2175 * ---------------|---------------
2176 * INT_MASK | TX_OVER
2177 *
2178 * @param I2Cx I2C instance.
2179 * @retval None.
2180 */
2181 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
2182 {
2183 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2184 }
2185
2186 /**
2187 * @brief Disable TX_OVER interrupt.
2188 *
2189 * Register|BitsName
2190 * ---------------|---------------
2191 * INT_MASK | TX_OVER
2192 *
2193 * @param I2Cx I2C instance.
2194 * @retval None.
2195 */
2196 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
2197 {
2198 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2199 }
2200
2201 /**
2202 * @brief Check if TX_OVER interrupt is enabled or disabled.
2203 *
2204 * Register|BitsName
2205 * ---------------|---------------
2206 * INT_MASK | TX_OVER
2207 *
2208 * @param I2Cx I2C instance.
2209 * @retval State of bit (1 or 0).
2210 */
2211 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
2212 {
2213 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER) == (I2C_INT_MASK_MASK_TX_OVER));
2214 }
2215
2216 /**
2217 * @brief Enable RX_FULL interrupt.
2218 *
2219 * Register|BitsName
2220 * ---------------|---------------
2221 * INT_MASK | RX_FULL
2222 *
2223 * @param I2Cx I2C instance.
2224 * @retval None.
2225 */
2226 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
2227 {
2228 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2229 }
2230
2231 /**
2232 * @brief Disable RX_FULL interrupt.
2233 *
2234 * Register|BitsName
2235 * ---------------|---------------
2236 * INT_MASK | RX_FULL
2237 *
2238 * @param I2Cx I2C instance.
2239 * @retval None.
2240 */
2241 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
2242 {
2243 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2244 }
2245
2246 /**
2247 * @brief Check if RX_FULL interrupt is enabled or disabled.
2248 *
2249 * Register|BitsName
2250 * ---------------|---------------
2251 * INT_MASK | RX_FULL
2252 *
2253 * @param I2Cx I2C instance.
2254 * @retval None.
2255 */
2256 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
2257 {
2258 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL) == (I2C_INT_MASK_MASK_RX_FULL));
2259 }
2260
2261 /**
2262 * @brief Enable RX_OVER interrupt.
2263 *
2264 * Register|BitsName
2265 * ---------------|---------------
2266 * INT_MASK | RX_OVER
2267 *
2268 * @param I2Cx I2C instance.
2269 * @retval None.
2270 */
2271 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
2272 {
2273 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2274 }
2275
2276 /**
2277 * @brief Disable RX_OVER interrupt.
2278 *
2279 * Register|BitsName
2280 * ---------------|---------------
2281 * INT_MASK | RX_OVER
2282 *
2283 * @param I2Cx I2C instance.
2284 * @retval None.
2285 */
2286 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
2287 {
2288 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2289 }
2290
2291 /**
2292 * @brief Check if RX_OVER interrupt is enabled or disabled.
2293 *
2294 * Register|BitsName
2295 * ---------------|---------------
2296 * INT_MASK | RX_OVER
2297 *
2298 * @param I2Cx I2C instance.
2299 * @retval None.
2300 */
2301 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
2302 {
2303 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER) == (I2C_INT_MASK_MASK_RX_OVER));
2304 }
2305
2306 /**
2307 * @brief Enable RX_UNDER interrupt.
2308 *
2309 * Register|BitsName
2310 * ---------------|---------------
2311 * INT_MASK | RX_UNDER
2312 *
2313 * @param I2Cx I2C instance.
2314 * @retval None.
2315 */
2316 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2317 {
2318 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2319 }
2320
2321 /**
2322 * @brief Disable RX_UNDER interrupt.
2323 *
2324 * Register|BitsName
2325 * ---------------|---------------
2326 * INT_MASK | RX_UNDER
2327 *
2328 * @param I2Cx I2C instance.
2329 * @retval None.
2330 */
2331 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2332 {
2333 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2334 }
2335
2336 /**
2337 * @brief Check if RX_UNDER interrupt is enabled or disabled.
2338 *
2339 * Register|BitsName
2340 * ---------------|---------------
2341 * INT_MASK | RX_UNDER
2342 *
2343 * @param I2Cx I2C instance.
2344 * @retval None.
2345 */
2346 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2347 {
2348 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2349 }
2350
2351 /** @} */
2352
2353 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
2354 * @{
2355 */
2356
2357 /**
2358 * @brief Get I2C interrupt flags
2359 *
2360 * Register|BitsName
2361 * ---------------|---------------
2362 * INT_STAT | MST_ON_HOLD
2363 * INT_STAT | RESTART_DET
2364 * INT_STAT | GEN_CALL
2365 * INT_STAT | START_DET
2366 * INT_STAT | STOP_DET
2367 * INT_STAT | ACTIVITY
2368 * INT_STAT | RX_DONE
2369 * INT_STAT | TX_ABRT
2370 * INT_STAT | RD_REQ
2371 * INT_STAT | TX_EMPTY
2372 * INT_STAT | TX_OVER
2373 * INT_STAT | RX_FULL
2374 * INT_STAT | RX_OVER
2375 * INT_STAT | RX_UNDER
2376 *
2377 * @param I2Cx I2C instance.
2378 * @retval Returned value can be one or combination of the following values:
2379 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2380 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2381 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2382 * @arg @ref LL_I2C_INTR_STAT_START_DET
2383 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2384 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2385 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2386 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2387 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2388 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2389 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2390 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2391 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2392 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2393 */
2394 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2395 {
2396 return (uint32_t)(READ_REG(I2Cx->INT_STAT));
2397 }
2398
2399 /**
2400 * @brief Get I2C RAW interrupt flags
2401 *
2402 * Register|BitsName
2403 * ---------------|---------------
2404 * RAW_INT_STAT | MST_ON_HOLD
2405 * RAW_INT_STAT | RESTART_DET
2406 * RAW_INT_STAT | GEN_CALL
2407 * RAW_INT_STAT | START_DET
2408 * RAW_INT_STAT | STOP_DET
2409 * RAW_INT_STAT | ACTIVITY
2410 * RAW_INT_STAT | RX_DONE
2411 * RAW_INT_STAT | TX_ABRT
2412 * RAW_INT_STAT | RD_REQ
2413 * RAW_INT_STAT | TX_EMPTY
2414 * RAW_INT_STAT | TX_OVER
2415 * RAW_INT_STAT | RX_FULL
2416 * RAW_INT_STAT | RX_OVER
2417 * RAW_INT_STAT | RX_UNDER
2418 *
2419 * @param I2Cx I2C instance.
2420 * @retval Returned value can be one or combination of the following values:
2421 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2422 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2423 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2424 * @arg @ref LL_I2C_INTR_STAT_START_DET
2425 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2426 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2427 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2428 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2429 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2430 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2431 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2432 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2433 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2434 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2435 */
2436 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2437 {
2438 return (uint32_t)(READ_REG(I2Cx->RAW_INT_STAT));
2439 }
2440
2441 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_scl_stuck_at_low(i2c_regs_t *I2Cx)
2442 {
2443 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_SCL_STUCKLOW) == (I2C_INT_STAT_RAW_SCL_STUCKLOW));
2444 }
2445
2446 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_scl_stuck_at_low(i2c_regs_t *I2Cx)
2447 {
2448 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_SCL_STUCKLOW) == (I2C_RAW_INT_STAT_SCL_STUCKLOW));
2449 }
2450
2451 /**
2452 * @brief Indicate the status of MST_ON_HOLD flag.
2453 * @note RESET: Clear default value.
2454 * SET : When MST_ON_HOLD interrupt is actived.
2455 *
2456 * Register|BitsName
2457 * ---------------|---------------
2458 * INT_STAT | M_HOLD
2459 *
2460 * @param I2Cx I2C instance.
2461 * @retval State of bit (1 or 0).
2462 */
2463 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2464 {
2465 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_M_HOLD) == (I2C_INT_STAT_RAW_M_HOLD));
2466 }
2467
2468 /**
2469 * @brief Indicate the status of RAW_MST_ON_HOLD flag.
2470 * @note RESET: Clear default value.
2471 * SET : When unmasked MST_ON_HOLD interrupt is actived.
2472 *
2473 * Register|BitsName
2474 * ---------------|---------------
2475 * RAW_INT_STAT | M_HOLD
2476 *
2477 * @param I2Cx I2C instance.
2478 * @retval State of bit (1 or 0).
2479 */
2480 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2481 {
2482 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_M_HOLD) == (I2C_RAW_INT_STAT_M_HOLD));
2483 }
2484
2485 /**
2486 * @brief Indicate the status of RESTART_DET flag.
2487 * @note RESET: Clear default value.
2488 * SET : When masked RESTART_DET interrupt is actived.
2489 *
2490 * Register|BitsName
2491 * ---------------|---------------
2492 * INT_STAT | RESTART_DET
2493 *
2494 * @param I2Cx I2C instance.
2495 * @retval State of bit (1 or 0).
2496 */
2497 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2498 {
2499 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RESTART_DET) == (I2C_INT_STAT_RAW_RESTART_DET));
2500 }
2501
2502 /**
2503 * @brief Indicate the status of RAW_RESTART_DET flag.
2504 * @note RESET: Clear default value.
2505 * SET : When unmasked RESTART_DET interrupt is actived.
2506 *
2507 * Register|BitsName
2508 * ---------------|---------------
2509 * RAW_INT_STAT | RESTART_DET
2510 *
2511 * @param I2Cx I2C instance.
2512 * @retval State of bit (1 or 0).
2513 */
2514 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2515 {
2516 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RESTART_DET) == (I2C_RAW_INT_STAT_RESTART_DET));
2517 }
2518
2519 /**
2520 * @brief Indicate the status of GEN_CALL flag.
2521 * @note RESET: Clear default value.
2522 * SET : When masked GEN_CALL interrupt is actived.
2523 *
2524 * Register|BitsName
2525 * ---------------|---------------
2526 * INT_STAT | GEN_CALL
2527 *
2528 * @param I2Cx I2C instance.
2529 * @retval State of bit (1 or 0).
2530 */
2531 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2532 {
2533 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_GEN_CALL) == (I2C_INT_STAT_RAW_GEN_CALL));
2534 }
2535
2536 /**
2537 * @brief Indicate the status of RAW_GEN_CALL flag.
2538 * @note RESET: Clear default value.
2539 * SET : When unmasked GEN_CALL interrupt is actived.
2540 *
2541 * Register|BitsName
2542 * ---------------|---------------
2543 * RAW_INT_STAT | GEN_CALL
2544 *
2545 * @param I2Cx I2C instance.
2546 * @retval State of bit (1 or 0).
2547 */
2548 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2549 {
2550 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_GEN_CALL) == (I2C_RAW_INT_STAT_GEN_CALL));
2551 }
2552
2553 /**
2554 * @brief Indicate the status of START_DET flag.
2555 * @note RESET: Clear default value.
2556 * SET : When masked START_DET interrupt is actived.
2557 *
2558 * Register|BitsName
2559 * ---------------|---------------
2560 * INT_STAT | START_DET
2561 *
2562 * @param I2Cx I2C instance.
2563 * @retval State of bit (1 or 0).
2564 */
2565 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2566 {
2567 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_START_DET) == (I2C_INT_STAT_RAW_START_DET));
2568 }
2569
2570 /**
2571 * @brief Indicate the status of RAW_START_DET flag.
2572 * @note RESET: Clear default value.
2573 * SET : When unmasked START_DET interrupt is actived.
2574 *
2575 * Register|BitsName
2576 * ---------------|---------------
2577 * RAW_INT_STAT | START_DET
2578 *
2579 * @param I2Cx I2C instance.
2580 * @retval State of bit (1 or 0).
2581 */
2582 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2583 {
2584 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_START_DET) == (I2C_RAW_INT_STAT_START_DET));
2585 }
2586
2587 /**
2588 * @brief Indicate the status of STOP_DET flag.
2589 * @note RESET: Clear default value.
2590 * SET : When masked STOP_DET interrupt is actived.
2591 *
2592 * Register|BitsName
2593 * ---------------|---------------
2594 * INT_STAT | STOP_DET
2595 *
2596 * @param I2Cx I2C instance.
2597 * @retval State of bit (1 or 0).
2598 */
2599 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2600 {
2601 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_STOP_DET) == (I2C_INT_STAT_RAW_STOP_DET));
2602 }
2603
2604 /**
2605 * @brief Indicate the status of RAW_STOP_DET flag.
2606 * @note RESET: Clear default value.
2607 * SET : When unmasked STOP_DET interrupt is actived.
2608 *
2609 * Register|BitsName
2610 * ---------------|---------------
2611 * RAW_INT_STAT | STOP_DET
2612 *
2613 * @param I2Cx I2C instance.
2614 * @retval State of bit (1 or 0).
2615 */
2616 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2617 {
2618 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_STOP_DET) == (I2C_RAW_INT_STAT_STOP_DET));
2619 }
2620
2621 /**
2622 * @brief Indicate the status of ACTIVITY flag.
2623 * @note RESET: Clear default value.
2624 * SET : When masked ACTIVITY interrupt is actived.
2625 *
2626 * Register|BitsName
2627 * ---------------|---------------
2628 * INT_STAT | ACTIVITY
2629 *
2630 * @param I2Cx I2C instance.
2631 * @retval State of bit (1 or 0).
2632 */
2633 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2634 {
2635 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_ACTIVITY) == (I2C_INT_STAT_RAW_ACTIVITY));
2636 }
2637
2638 /**
2639 * @brief Indicate the status of RAW_ACTIVITY flag.
2640 * @note RESET: Clear default value.
2641 * SET : When unmasked ACTIVITY interrupt is actived.
2642 *
2643 * Register|BitsName
2644 * ---------------|---------------
2645 * RAW_INT_STAT | ACTIVITY
2646 *
2647 * @param I2Cx I2C instance.
2648 * @retval State of bit (1 or 0).
2649 */
2650 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2651 {
2652 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_ACTIVITY) == (I2C_RAW_INT_STAT_ACTIVITY));
2653 }
2654
2655 /**
2656 * @brief Indicate the status of RX_DONE flag.
2657 * @note RESET: Clear default value.
2658 * SET : When masked RX_DONE interrupt is actived.
2659 *
2660 * Register|BitsName
2661 * ---------------|---------------
2662 * INT_STAT | RX_DONE
2663 *
2664 * @param I2Cx I2C instance.
2665 * @retval State of bit (1 or 0).
2666 */
2667 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2668 {
2669 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_DONE) == (I2C_INT_STAT_RAW_RX_DONE));
2670 }
2671
2672 /**
2673 * @brief Indicate the status of RAW_RX_DONE flag.
2674 * @note RESET: Clear default value.
2675 * SET : When unmasked RX_DONE interrupt is actived.
2676 *
2677 * Register|BitsName
2678 * ---------------|---------------
2679 * RAW_INT_STAT | RX_DONE
2680 *
2681 * @param I2Cx I2C instance.
2682 * @retval State of bit (1 or 0).
2683 */
2684 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2685 {
2686 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_DONE) == (I2C_RAW_INT_STAT_RX_DONE));
2687 }
2688
2689 /**
2690 * @brief Indicate the status of TX_ABRT flag.
2691 * @note RESET: Clear default value.
2692 * SET : When masked TX_ABRT interrupt is actived.
2693 *
2694 * Register|BitsName
2695 * ---------------|---------------
2696 * INT_STAT | TX_ABORT
2697 *
2698 * @param I2Cx I2C instance.
2699 * @retval State of bit (1 or 0).
2700 */
2701 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2702 {
2703 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_ABORT) == (I2C_INT_STAT_RAW_TX_ABORT));
2704 }
2705
2706 /**
2707 * @brief Indicate the status of RAW_TX_ABRT flag.
2708 * @note RESET: Clear default value.
2709 * SET : When unmasked TX_ABRT interrupt is actived.
2710 *
2711 * Register|BitsName
2712 * ---------------|---------------
2713 * RAW_INT_STAT | TX_ABORT
2714 *
2715 * @param I2Cx I2C instance.
2716 * @retval State of bit (1 or 0).
2717 */
2718 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2719 {
2720 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_ABORT) == (I2C_RAW_INT_STAT_TX_ABORT));
2721 }
2722
2723 /**
2724 * @brief Indicate the status of RD_REQ flag.
2725 * @note RESET: Clear default value.
2726 * SET : When masked RD_REQ interrupt is actived.
2727 *
2728 * Register|BitsName
2729 * ---------------|---------------
2730 * INT_STAT | RD_REQ
2731 *
2732 * @param I2Cx I2C instance.
2733 * @retval State of bit (1 or 0).
2734 */
2735 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2736 {
2737 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RD_REQ) == (I2C_INT_STAT_RAW_RD_REQ));
2738 }
2739
2740 /**
2741 * @brief Indicate the status of RAW_RD_REQ flag.
2742 * @note RESET: Clear default value.
2743 * SET : When unmasked RD_REQ interrupt is actived.
2744 *
2745 * Register|BitsName
2746 * ---------------|---------------
2747 * RAW_INT_STAT | RD_REQ
2748 *
2749 * @param I2Cx I2C instance.
2750 * @retval State of bit (1 or 0).
2751 */
2752 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2753 {
2754 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RD_REQ) == (I2C_RAW_INT_STAT_RD_REQ));
2755 }
2756
2757 /**
2758 * @brief Indicate the status of TX_EMPTY flag.
2759 * @note RESET: Clear default value.
2760 * SET : When masked TX_EMPTY interrupt is actived.
2761 *
2762 * Register|BitsName
2763 * ---------------|---------------
2764 * INT_STAT | TX_EMPTY
2765 *
2766 * @param I2Cx I2C instance.
2767 * @retval State of bit (1 or 0).
2768 */
2769 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2770 {
2771 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_EMPTY) == (I2C_INT_STAT_RAW_TX_EMPTY));
2772 }
2773
2774 /**
2775 * @brief Indicate the status of RAW_TX_EMPTY flag.
2776 * @note RESET: Clear default value.
2777 * SET : When unmasked TX_EMPTY interrupt is actived.
2778 *
2779 * Register|BitsName
2780 * ---------------|---------------
2781 * RAW_INT_STAT | TX_EMPTY
2782 *
2783 * @param I2Cx I2C instance.
2784 * @retval State of bit (1 or 0).
2785 */
2786 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2787 {
2788 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_EMPTY) == (I2C_RAW_INT_STAT_TX_EMPTY));
2789 }
2790
2791 /**
2792 * @brief Indicate the status of TX_OVER flag.
2793 * @note RESET: Clear default value.
2794 * SET : When masked TX_OVER interrupt is actived.
2795 *
2796 * Register|BitsName
2797 * ---------------|---------------
2798 * INT_STAT | TX_OVER
2799 *
2800 * @param I2Cx I2C instance.
2801 * @retval State of bit (1 or 0).
2802 */
2803 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2804 {
2805 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_OVER) == (I2C_INT_STAT_RAW_TX_OVER));
2806 }
2807
2808 /**
2809 * @brief Indicate the status of RAW_TX_OVER flag.
2810 * @note RESET: Clear default value.
2811 * SET : When unmasked TX_OVER interrupt is actived.
2812 *
2813 * Register|BitsName
2814 * ---------------|---------------
2815 * RAW_INT_STAT | TX_OVER
2816 *
2817 * @param I2Cx I2C instance.
2818 * @retval State of bit (1 or 0).
2819 */
2820 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2821 {
2822 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_OVER) == (I2C_RAW_INT_STAT_TX_OVER));
2823 }
2824
2825 /**
2826 * @brief Indicate the status of RX_FULL flag.
2827 * @note RESET: Clear default value.
2828 * SET : When masked RX_FULL interrupt is actived.
2829 *
2830 * Register|BitsName
2831 * ---------------|---------------
2832 * INT_STAT | RX_FULL
2833 *
2834 * @param I2Cx I2C instance.
2835 * @retval State of bit (1 or 0).
2836 */
2837 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
2838 {
2839 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_FULL) == (I2C_INT_STAT_RAW_RX_FULL));
2840 }
2841
2842 /**
2843 * @brief Indicate the status of RAW_RX_FULL flag.
2844 * @note RESET: Clear default value.
2845 * SET : When unmasked RX_FULL interrupt is actived.
2846 *
2847 * Register|BitsName
2848 * ---------------|---------------
2849 * RAW_INT_STAT | RX_FULL
2850 *
2851 * @param I2Cx I2C instance.
2852 * @retval State of bit (1 or 0).
2853 */
2854 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
2855 {
2856 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_FULL) == (I2C_RAW_INT_STAT_RX_FULL));
2857 }
2858
2859 /**
2860 * @brief Indicate the status of RX_OVER flag.
2861 * @note RESET: Clear default value.
2862 * SET : When masked RX_OVER interrupt is actived.
2863 *
2864 * Register|BitsName
2865 * ---------------|---------------
2866 * INT_STAT | RX_OVER
2867 *
2868 * @param I2Cx I2C instance.
2869 * @retval State of bit (1 or 0).
2870 */
2871 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
2872 {
2873 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_OVER) == (I2C_INT_STAT_RAW_RX_OVER));
2874 }
2875
2876 /**
2877 * @brief Indicate the status of RAW_RX_OVER flag.
2878 * @note RESET: Clear default value.
2879 * SET : When unmasked RX_OVER interrupt is actived.
2880 *
2881 * Register|BitsName
2882 * ---------------|---------------
2883 * RAW_INT_STAT | RX_OVER
2884 *
2885 * @param I2Cx I2C instance.
2886 * @retval State of bit (1 or 0).
2887 */
2888 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
2889 {
2890 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_OVER) == (I2C_RAW_INT_STAT_RX_OVER));
2891 }
2892
2893 /**
2894 * @brief Indicate the status of RX_UNDER flag.
2895 * @note RESET: Clear default value.
2896 * SET : When masked RX_UNDER interrupt is actived.
2897 *
2898 * Register|BitsName
2899 * ---------------|---------------
2900 * INT_STAT | RX_UNDER
2901 *
2902 * @param I2Cx I2C instance.
2903 * @retval State of bit (1 or 0).
2904 */
2905 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
2906 {
2907 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2908 }
2909
2910 /**
2911 * @brief Indicate the status of RAW_RX_UNDER flag.
2912 * @note RESET: Clear default value.
2913 * SET : When unmasked RX_UNDER interrupt is actived.
2914 *
2915 * Register|BitsName
2916 * ---------------|---------------
2917 * RAW_INT_STAT | RX_UNDER
2918 *
2919 * @param I2Cx I2C instance.
2920 * @retval State of bit (1 or 0).
2921 */
2922 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
2923 {
2924 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_UNDER) == (I2C_RAW_INT_STAT_RX_UNDER));
2925 }
2926
2927 /**
2928 * @brief Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
2929 *
2930 * Register|BitsName
2931 * ---------------|---------------
2932 * CLR_INT | CLR_INTR
2933 *
2934 * @param I2Cx I2C instance.
2935 * @retval None.
2936 */
2937 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
2938 {
2939 __IO uint32_t tmpreg;
2940 tmpreg = READ_REG(I2Cx->CLR_INT);
2941 (void) tmpreg;
2942 }
2943
2944 __STATIC_INLINE void ll_i2c_clear_flag_scl_stuck_det(i2c_regs_t *I2Cx)
2945 {
2946 __IO uint32_t tmpreg;
2947 tmpreg = READ_REG(I2Cx->CLR_SCL_STUCK_DET);
2948 (void) tmpreg;
2949 }
2950
2951 /**
2952 * @brief Clear GEN_CALL flag.
2953 *
2954 * Register|BitsName
2955 * ---------------|---------------
2956 * CLR_GEN_CALL | CLR_GEN_CALL
2957 *
2958 * @param I2Cx I2C instance.
2959 * @retval None.
2960 */
2961 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
2962 {
2963 __IO uint32_t tmpreg;
2964 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
2965 (void) tmpreg;
2966 }
2967
2968 /**
2969 * @brief Clear START_DET flag.
2970 *
2971 * Register|BitsName
2972 * ---------------|---------------
2973 * CLR_START_DET | CLR_START_DET
2974 *
2975 * @param I2Cx I2C instance.
2976 * @retval None.
2977 */
2978 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
2979 {
2980 __IO uint32_t tmpreg;
2981 tmpreg = READ_REG(I2Cx->CLR_START_DET);
2982 (void) tmpreg;
2983 }
2984
2985 /**
2986 * @brief Clear STOP_DET flag.
2987 *
2988 * Register|BitsName
2989 * ---------------|---------------
2990 * CLR_STOP_DET | CLR_STOP_DET
2991 *
2992 * @param I2Cx I2C instance.
2993 * @retval None.
2994 */
2995 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
2996 {
2997 __IO uint32_t tmpreg;
2998 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
2999 (void) tmpreg;
3000 }
3001
3002 /**
3003 * @brief Clear ACTIVITY flag.
3004 *
3005 * Register|BitsName
3006 * ---------------|---------------
3007 * CLR_ACTIVITY | CLR_ACTIVITY
3008 *
3009 * @param I2Cx I2C instance.
3010 * @retval None.
3011 */
3012 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
3013 {
3014 __IO uint32_t tmpreg;
3015 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
3016 (void) tmpreg;
3017 }
3018
3019 /**
3020 * @brief Clear RX_DONE flag.
3021 *
3022 * Register|BitsName
3023 * ---------------|---------------
3024 * CLR_RX_DONE | CLR_RX_DONE
3025 *
3026 * @param I2Cx I2C instance.
3027 * @retval None.
3028 */
3029 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
3030 {
3031 __IO uint32_t tmpreg;
3032 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
3033 (void) tmpreg;
3034 }
3035
3036 /**
3037 * @brief Clear TX_ABRT flag.
3038 *
3039 * Register|BitsName
3040 * ---------------|---------------
3041 * CLR_TX_ABORT | CLR_TX_ABRT
3042 *
3043 * @param I2Cx I2C instance.
3044 * @retval None.
3045 */
3046 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
3047 {
3048 __IO uint32_t tmpreg;
3049 tmpreg = READ_REG(I2Cx->CLR_TX_ABORT);
3050 (void) tmpreg;
3051 }
3052
3053 /**
3054 * @brief Clear RD_REQ flag.
3055 *
3056 * Register|BitsName
3057 * ---------------|---------------
3058 * CLR_RD_REQ | CLR_RD_REQ
3059 *
3060 * @param I2Cx I2C instance.
3061 * @retval None.
3062 */
3063 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
3064 {
3065 __IO uint32_t tmpreg;
3066 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
3067 (void) tmpreg;
3068 }
3069
3070 /**
3071 * @brief Clear TX_OVER flag.
3072 *
3073 * Register|BitsName
3074 * ---------------|---------------
3075 * CLR_TX_OVER | CLR_TX_OVER
3076 *
3077 * @param I2Cx I2C instance.
3078 * @retval None.
3079 */
3080 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
3081 {
3082 __IO uint32_t tmpreg;
3083 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
3084 (void) tmpreg;
3085 }
3086
3087 /**
3088 * @brief Clear RX_OVER flag.
3089 *
3090 * Register|BitsName
3091 * ---------------|---------------
3092 * CLR_RX_OVER | CLR_RX_OVER
3093 *
3094 * @param I2Cx I2C instance.
3095 * @retval None.
3096 */
3097 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
3098 {
3099 __IO uint32_t tmpreg;
3100 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
3101 (void) tmpreg;
3102 }
3103
3104 /**
3105 * @brief Clear RX_UNDER flag.
3106 *
3107 * Register|BitsName
3108 * ---------------|---------------
3109 * CLR_RX_UNDER | CLR_RX_UNDER
3110 *
3111 * @param I2Cx I2C instance.
3112 * @retval None.
3113 */
3114 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
3115 {
3116 __IO uint32_t tmpreg;
3117 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
3118 (void) tmpreg;
3119 }
3120
3121 /**
3122 * @brief Indicate the status of IC_STATUS SDA stuck at low is not recovered flag.
3123 * @note RESET: stuck at low is recovered.
3124 * SET : stuck at low is not recovered.
3125 *
3126 * Register|BitsName
3127 * ---------------|---------------
3128 * STAT | SDA_STUCK_RCVR
3129 *
3130 * @param I2Cx I2C instance.
3131 * @retval State of bit (1 or 0).
3132 */
3133 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_sda_stuck_not_recovered(i2c_regs_t *I2Cx)
3134 {
3135 return (READ_BITS(I2Cx->STAT, I2C_STAT_SDA_STUCK_RCVR) == (I2C_STAT_SDA_STUCK_RCVR));
3136 }
3137
3138 /**
3139 * @brief Indicate the status of IC_STATUS Slave FSM Activity Status flag.
3140 * @note RESET: Slave FSM is in IDLE state.
3141 * SET : When Slave FSM is not in IDLE state.
3142 *
3143 * Register|BitsName
3144 * ---------------|---------------
3145 * STAT | S_ACTIVITY
3146 *
3147 * @param I2Cx I2C instance.
3148 * @retval State of bit (1 or 0).
3149 */
3150 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
3151 {
3152 return (READ_BITS(I2Cx->STAT, I2C_STAT_S_ACTIVITY) == (I2C_STAT_S_ACTIVITY));
3153 }
3154
3155 /**
3156 * @brief Indicate the status of IC_STATUS Master FSM Activity Status flag.
3157 * @note RESET: Master FSM is in IDLE state.
3158 * SET : When Master FSM is not in IDLE state.
3159 *
3160 * Register|BitsName
3161 * ---------------|---------------
3162 * STAT | M_ACTIVITY
3163 *
3164 * @param I2Cx I2C instance.
3165 * @retval State of bit (1 or 0).
3166 */
3167 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
3168 {
3169 return (READ_BITS(I2Cx->STAT, I2C_STAT_M_ACTIVITY) == (I2C_STAT_M_ACTIVITY));
3170 }
3171
3172 /**
3173 * @brief Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
3174 * @note RESET: Receive FIFO is not full.
3175 * SET : When Receive FIFO is full.
3176 *
3177 * Register|BitsName
3178 * ---------------|---------------
3179 * STAT | RX_FIFO_CF
3180 *
3181 * @param I2Cx I2C instance.
3182 * @retval State of bit (1 or 0).
3183 */
3184 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
3185 {
3186 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_CF) == (I2C_STAT_RX_FIFO_CF));
3187 }
3188
3189 /**
3190 * @brief Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
3191 * @note RESET: Receive FIFO is empty.
3192 * SET : When Receive FIFO is not empty.
3193 *
3194 * Register|BitsName
3195 * ---------------|---------------
3196 * STAT | RX_FIFO_NE
3197 *
3198 * @param I2Cx I2C instance.
3199 * @retval State of bit (1 or 0).
3200 */
3201 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
3202 {
3203 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_NE) == (I2C_STAT_RX_FIFO_NE));
3204 }
3205
3206 /**
3207 * @brief Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
3208 * @note RESET: Transmit FIFO is not empty.
3209 * SET : When Transmit FIFO is empty.
3210 *
3211 * Register|BitsName
3212 * ---------------|---------------
3213 * STAT | TX_FIFO_CE
3214 *
3215 * @param I2Cx I2C instance.
3216 * @retval State of bit (1 or 0).
3217 */
3218 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
3219 {
3220 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_CE) == (I2C_STAT_TX_FIFO_CE));
3221 }
3222
3223 /**
3224 * @brief Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
3225 * @note RESET: Transmit FIFO is full.
3226 * SET : When Transmit FIFO is not full.
3227 *
3228 * Register|BitsName
3229 * ---------------|---------------
3230 * STAT | TX_FIFO_NF
3231 *
3232 * @param I2Cx I2C instance.
3233 * @retval State of bit (1 or 0).
3234 */
3235 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
3236 {
3237 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_NF) == (I2C_STAT_TX_FIFO_NF));
3238 }
3239
3240 /**
3241 * @brief Indicate the status of IC_STATUS ACTIVITY flag.
3242 * @note RESET: I2C is idle.
3243 * SET : When I2C is active.
3244 *
3245 * Register|BitsName
3246 * ---------------|---------------
3247 * STAT | ACTIVITY
3248 *
3249 * @param I2Cx I2C instance.
3250 * @retval State of bit (1 or 0).
3251 */
3252 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
3253 {
3254 return (READ_BITS(I2Cx->STAT, I2C_STAT_ACTIVITY) == (I2C_STAT_ACTIVITY));
3255 }
3256
3257 /**
3258 * @brief Indicate the status of Slave Received Data Lost flag.
3259 * @note RESET: Slave RX Data is not lost.
3260 * SET : Slave RX Data is lost.
3261 *
3262 * Register|BitsName
3263 * ---------------|---------------
3264 * EN_STAT | S_RX_DATA_LOST
3265 *
3266 * @param I2Cx I2C instance.
3267 * @retval State of bit (1 or 0).
3268 */
3269 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
3270 {
3271 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_RX_DATA_LOST) == (I2C_EN_STAT_S_RX_DATA_LOST));
3272 }
3273
3274 /**
3275 * @brief Indicate the status of Slave Disabled While Busy flag.
3276 * @note RESET: Slave is disabled when it is idle.
3277 * SET : Slave is disabled when it is active.
3278 *
3279 * Register|BitsName
3280 * ---------------|---------------
3281 * EN_STAT | S_DIS_BUSY
3282 *
3283 * @param I2Cx I2C instance.
3284 * @retval State of bit (1 or 0).
3285 */
3286 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
3287 {
3288 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_DIS_BUSY) == (I2C_EN_STAT_S_DIS_BUSY));
3289 }
3290 /** @} */
3291
3292 /** @defgroup I2C_LL_EF_DMA_Management DMA_Management
3293 * @{
3294 */
3295
3296 /**
3297 * @brief Enable DMA transmission requests.
3298 *
3299 * Register|BitsName
3300 * ---------------|---------------
3301 * DMA_CTRL | TX_EN
3302 *
3303 * @retval Value range between 0 ~ 0x8.
3304 * @retval None.
3305 */
3306 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
3307 {
3308 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3309 }
3310
3311 /**
3312 * @brief Disable DMA transmission requests.
3313 *
3314 * Register|BitsName
3315 * ---------------|---------------
3316 * DMA_CTRL | TX_EN
3317 *
3318 * @param I2Cx I2C instance.
3319 * @retval None.
3320 */
3321 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
3322 {
3323 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3324 }
3325
3326 /**
3327 * @brief Check if DMA transmission requests are enabled or disabled.
3328 *
3329 * Register|BitsName
3330 * ---------------|---------------
3331 * DMA_CTRL | TX_EN
3332 *
3333 * @param I2Cx I2C instance.
3334 * @retval State of bit (1 or 0).
3335 */
3336 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
3337 {
3338 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN) == (I2C_DMA_CTRL_TX_EN));
3339 }
3340
3341 /**
3342 * @brief Enable DMA reception requests.
3343 *
3344 * Register|BitsName
3345 * ---------------|---------------
3346 * DMA_CTRL | RX_EN
3347 *
3348 * @param I2Cx I2C instance.
3349 * @retval None.
3350 */
3351 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3352 {
3353 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3354 }
3355
3356 /**
3357 * @brief Disable DMA reception requests.
3358 *
3359 * Register|BitsName
3360 * ---------------|---------------
3361 * DMA_CTRL | RX_EN
3362 *
3363 * @param I2Cx I2C instance.
3364 * @retval None.
3365 */
3366 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3367 {
3368 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3369 }
3370
3371 /**
3372 * @brief Check if DMA reception requests are enabled or disabled.
3373 *
3374 * Register|BitsName
3375 * ---------------|---------------
3376 * DMA_CTRL | RX_EN
3377 *
3378 * @param I2Cx I2C instance.
3379 * @retval State of bit (1 or 0).
3380 */
3381 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3382 {
3383 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN) == (I2C_DMA_CTRL_RX_EN));
3384 }
3385
3386 /**
3387 * @brief Set level of TX FIFO that requests a DMA transmit.
3388 * @note TX data level should equal to the watermark level, that is, the dma_tx_req
3389 * signal is generated when the number of valid data entries in the transmit
3390 * FIFO is equal to or below this field value, and TDMAE = 1.
3391 *
3392 * Register|BitsName
3393 * ---------------|---------------
3394 * DMA_TX_LEVEL | LEVEL
3395 *
3396 * @param I2Cx I2C instance
3397 * @param level This parameter should range between 0x0 and 0x8.
3398 * @retval None.
3399 */
3400 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3401 {
3402 WRITE_REG(I2Cx->DMA_TX_LEVEL, level);
3403 }
3404
3405 /**
3406 * @brief Get level of TX FIFO that request a DMA transmit.
3407 *
3408 * Register|BitsName
3409 * ---------------|---------------
3410 * DMA_TX_LEVEL | LEVEL
3411 *
3412 * @param I2Cx I2C instance
3413 * @retval Returned value should range between 0x0 and 0x8.
3414 */
3415 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3416 {
3417 return (uint32_t)(READ_BITS(I2Cx->DMA_TX_LEVEL, I2C_DMA_TX_LEVEL_LEVEL));
3418 }
3419
3420 /**
3421 * @brief Set level of RX FIFO that requests a DMA receive.
3422 * @note The watermark level = DMARDL + 1, that is, dma_rx_req is generated when
3423 * the number of valid data entries in the receive FIFO is equal to or
3424 * more than this field value + 1, and RDMAE = 1. For instance, when DMARDL
3425 * is 0, then dma_rx_req is asserted when 1 or more data entries are present
3426 * in the receive FIFO.
3427 *
3428 * Register|BitsName
3429 * ---------------|---------------
3430 * DMA_RX_LEVEL | LEVEL
3431 *
3432 * @param I2Cx I2C instance
3433 * @param level This parameter should range between 0x0 and 0x8.
3434 * @retval None.
3435 */
3436 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3437 {
3438 WRITE_REG(I2Cx->DMA_RX_LEVEL, level);
3439 }
3440
3441 /**
3442 * @brief Get level of RX FIFO that request a DMA receive.
3443 *
3444 * Register|BitsName
3445 * ---------------|---------------
3446 * DMA_RX_LEVEL | LEVEL
3447 *
3448 * @param I2Cx I2C instance
3449 * @retval Returned value should range between 0x0 and 0x8.
3450 */
3451 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3452 {
3453 return (uint32_t)(READ_BITS(I2Cx->DMA_RX_LEVEL, I2C_DMA_RX_LEVEL_LEVEL));
3454 }
3455
3456 /**
3457 * @brief Get the data register address used for DMA transfer
3458 *
3459 * Register|BitsName
3460 * ---------------|---------------
3461 * DATA_CMD | DAT
3462 *
3463 * @param I2Cx I2C instance
3464 * @retval Address of data register
3465 */
3466 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3467 {
3468 return ((uint32_t) & (I2Cx->DATA_CMD));
3469 }
3470
3471
3472
3473 __STATIC_INLINE void ll_i2c_set_scl_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
3474 {
3475 WRITE_REG(I2Cx->SCL_STUCK_TIMEOUT, timeout);
3476 }
3477
3478 __STATIC_INLINE void ll_i2c_set_sda_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
3479 {
3480 WRITE_REG(I2Cx->SDA_STUCK_TIMEOUT, timeout);
3481 }
3482
3483
3484 /** @} */
3485
3486 /** @defgroup I2C_LL_EF_Data_Management Data_Management
3487 * @{
3488 */
3489
3490 /**
3491 * @brief Configure the slave address for transfer (master mode).
3492 * @note The register IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3493 *
3494 * Register|BitsName
3495 * ---------------|---------------
3496 * TARGET_ADDR | TAR_ADDR
3497 *
3498 * @param I2Cx I2C instance.
3499 * @param slave_addr This parameter must be a value between 0x00 and 0x3F.
3500 * @retval None.
3501 */
3502 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3503 {
3504 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3505 }
3506
3507 /**
3508 * @brief Get the slave address programmed for transfer (master mode).
3509 *
3510 * Register|BitsName
3511 * ---------------|---------------
3512 * TARGET_ADDR | TAR_ADDR
3513 *
3514 * @param I2Cx I2C instance.
3515 * @retval Value between 0x0 and0x3F
3516 */
3517 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3518 {
3519 return (uint32_t)(READ_BITS(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET) >> I2C_TARGET_ADDR_TARGET_POS);
3520 }
3521
3522 /**
3523 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
3524 * @note The register IC_CON and IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3525 *
3526 * Register|BitsName
3527 * ---------------|---------------
3528 * TARGET_ADDR | TAR_ADDR
3529 * CTRL | CON_10BITADDR_MST
3530 *
3531 * @param I2Cx I2C instance.
3532 * @param slave_addr Specifies the slave address to be programmed.
3533 * @param slave_addr_size This parameter can be one of the following values:
3534 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
3535 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
3536 * @note SlaveAddrSize in IC_CON register can only be programmed when the I2C is disabled (IC_ENABLE = 0).
3537 * @retval None.
3538 */
3539 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3540 {
3541 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3542 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3543 }
3544
3545 /**
3546 * @brief Read Receive Data register.
3547 *
3548 * Register|BitsName
3549 * ---------------|---------------
3550 * DATA_CMD | DATA
3551 *
3552 * @param I2Cx I2C instance.
3553 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3554 */
3555 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3556 {
3557 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DATA));
3558 }
3559
3560 /**
3561 * @brief Write in Transmit Data Register .
3562 *
3563 * Register|BitsName
3564 * ---------------|---------------
3565 * DATA_CMD | STOP
3566 * DATA_CMD | CMD
3567 * DATA_CMD | DATA
3568 *
3569 * @param I2Cx I2C instance.
3570 * @param data Value range between 0x00 and 0xFF.
3571 * @param cmd This parameter can be one of the following values:
3572 * @arg @ref LL_I2C_CMD_SLV_NONE
3573 * @arg @ref LL_I2C_CMD_MST_WRITE
3574 * @arg @ref LL_I2C_CMD_MST_READ
3575 * @arg @ref LL_I2C_CMD_MST_GEN_STOP
3576 * @arg @ref LL_I2C_CMD_MST_GEN_RESTART
3577 * @retval None.
3578 */
3579 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3580 {
3581 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3582 }
3583
3584 /** @} */
3585
3586 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
3587 * @{
3588 */
3589
3590 /**
3591 * @brief De-initialize I2C registers (Registers restored to their default values).
3592 * @param I2Cx I2C instance
3593 * @retval An error_status_t enumeration value:
3594 * - SUCCESS: I2C registers are de-initialized
3595 * - ERROR: I2C registers are not de-initialized
3596 */
3597 error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx);
3598
3599 /**
3600 * @brief Initialize I2C registers according to the specified
3601 * parameters in p_i2c_init.
3602 * @param I2Cx I2C instance
3603 * @param p_i2c_init Pointer to a ll_i2c_init_t structure that contains the configuration
3604 * information for the specified I2C peripheral.
3605 * @retval An error_status_t enumeration value:
3606 * - SUCCESS: I2C registers are initialized according to p_i2c_init content
3607 * - ERROR: Problem occurred during I2C Registers initialization
3608 */
3609 error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3610
3611 /**
3612 * @brief Set each field of a @ref ll_i2c_init_t type structure to default value.
3613 * @param p_i2c_init Pointer to a @ref ll_i2c_init_t structure
3614 * whose fields will be set to default values.
3615 * @retval None
3616 */
3617 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3618
3619 /** @} */
3620
3621 /** @} */
3622
3623 #endif /* I2C0 || I2C1 */
3624
3625 #ifdef __cplusplus
3626 }
3627 #endif
3628
3629 #endif /* __GR55xx_LL_I2C_H__ */
3630
3631 /** @} */
3632
3633 /** @} */
3634
3635 /** @} */
ll_i2c_is_active_flag_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2803
ll_i2c_enable
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
Definition: gr55xx_ll_i2c.h:384
_ll_i2c_init::own_addr_size
uint32_t own_addr_size
Specifies the device own address 1 size (7-bit or 10-bit).
Definition: gr55xx_ll_i2c.h:85
ll_i2c_enable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:585
ll_i2c_is_active_flag_status_tfnf
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
Definition: gr55xx_ll_i2c.h:3235
ll_i2c_is_enabled_transfer_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1481
ll_i2c_is_active_flag_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2667
ll_i2c_get_clock_low_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:884
ll_i2c_enable_sda_stuck_recovery
__STATIC_INLINE void ll_i2c_enable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master initates the SDA stuck at low recovery mechanism.
Definition: gr55xx_ll_i2c.h:1422
ll_i2c_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_i2c.h:1393
ll_i2c_is_enabled_it_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1941
ll_i2c_is_enabled_it_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1761
ll_i2c_set_speed_mode
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1032
ll_i2c_enable_it_tx_over
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2181
ll_i2c_disable_it_tx_over
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2196
ll_i2c_is_active_flag_status_master_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:3167
ll_i2c_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1378
ll_i2c_get_abort_source
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
Definition: gr55xx_ll_i2c.h:1534
ll_i2c_is_active_flag_raw_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2480
ll_i2c_is_active_flag_status_rfne
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
Definition: gr55xx_ll_i2c.h:3201
ll_i2c_clear_flag_rx_under
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:3114
ll_i2c_is_enabled_sda_stuck_recovery
__STATIC_INLINE uint32_t ll_i2c_is_enabled_sda_stuck_recovery(i2c_regs_t *I2Cx)
the SDA stuck at low recovery mechanism is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1451
ll_i2c_dma_get_register_address
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_i2c.h:3466
ll_i2c_clear_flag_tx_over
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
Definition: gr55xx_ll_i2c.h:3080
ll_i2c_disable_it_tx_empty
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:2151
ll_i2c_is_active_flag_raw_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2718
ll_i2c_enable_dma_req_tx
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:3306
ll_i2c_is_enabled_it_start_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1896
ll_i2c_is_enabled_stop_det_if_addressed
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
Definition: gr55xx_ll_i2c.h:696
ll_i2c_enable_it_start_det
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1866
ll_i2c_get_data_setup_time
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1182
ll_i2c_is_active_flag_raw_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2752
ll_i2c_is_active_flag_status_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:3252
ll_i2c_enable_transfer_abort
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:1466
ll_i2c_is_enabled_bus_clear_feature
__STATIC_INLINE uint32_t ll_i2c_is_enabled_bus_clear_feature(i2c_regs_t *I2Cx)
check bus clear feature is enabled function.
Definition: gr55xx_ll_i2c.h:681
ll_i2c_get_spike_len_fs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:980
ll_i2c_deinit
error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
ll_i2c_is_active_flag_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2905
ll_i2c_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1232
ll_i2c_is_active_flag_raw_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2650
ll_i2c_get_clock_low_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:948
ll_i2c_is_active_flag_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2599
ll_i2c_is_enabled_master_mode
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
Definition: gr55xx_ll_i2c.h:465
ll_i2c_disable_dma_req_tx
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:3321
ll_i2c_disable_it_rx_over
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2286
_ll_i2c_init::speed
uint32_t speed
Specifies the transfer speed.
Definition: gr55xx_ll_i2c.h:78
ll_i2c_enable_it_read_req
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:2091
ll_i2c_is_active_flag_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2871
ll_i2c_is_enabled_it_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2346
ll_i2c_enable_it_stop_det
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1911
ll_i2c_disable_dma_req_rx
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3366
ll_i2c_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1330
ll_i2c_is_active_flag_status_tfe
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
Definition: gr55xx_ll_i2c.h:3218
ll_i2c_set_sda_stuck_at_low_timeout
__STATIC_INLINE void ll_i2c_set_sda_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Definition: gr55xx_ll_i2c.h:3478
ll_i2c_is_active_flag_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2497
ll_i2c_overflow_if_rx_full
__STATIC_INLINE void ll_i2c_overflow_if_rx_full(i2c_regs_t *I2Cx)
overflow when the RX FIFO if full function.
Definition: gr55xx_ll_i2c.h:633
ll_i2c_enable_it_scl_stuck_at_low
__STATIC_INLINE void ll_i2c_enable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Enable SCL_STUCK_AT_LOW interrupt.
Definition: gr55xx_ll_i2c.h:1687
ll_i2c_set_dma_rx_data_level
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
Definition: gr55xx_ll_i2c.h:3436
ll_i2c_disable_it_restart_det
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1791
ll_i2c_is_active_flag_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2463
ll_i2c_disable_it
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
Definition: gr55xx_ll_i2c.h:1633
ll_i2c_disable_master_restart
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
Definition: gr55xx_ll_i2c.h:550
ll_i2c_get_clock_high_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:916
ll_i2c_disable_sda_stuck_recovery
__STATIC_INLINE void ll_i2c_disable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master disabled the SDA stuck at low recovery mechanism.
Definition: gr55xx_ll_i2c.h:1436
ll_i2c_clear_flag_intr
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: gr55xx_ll_i2c.h:2937
ll_i2c_is_enabled_it_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1806
ll_i2c_get_tx_flush_count
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1549
ll_i2c_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_i2c.h:1280
ll_i2c_disable_it_stop_det
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1926
ll_i2c_is_enabled_it_activity
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1986
ll_i2c_disable_it_scl_stuck_at_low
__STATIC_INLINE void ll_i2c_disable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Disable SCL_STUCK_AT_LOW interrupt.
Definition: gr55xx_ll_i2c.h:1701
ll_i2c_get_data_rx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1148
ll_i2c_get_clock_high_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:788
ll_i2c_init
error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
ll_i2c_disbale_it_rx_full
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:2241
ll_i2c_get_slave_address
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3517
ll_i2c_is_active_flag_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2837
ll_i2c_clear_flag_scl_stuck_det
__STATIC_INLINE void ll_i2c_clear_flag_scl_stuck_det(i2c_regs_t *I2Cx)
Definition: gr55xx_ll_i2c.h:2944
ll_i2c_enable_it_master_on_hold
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1731
ll_i2c_is_enabled_it_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2076
ll_i2c_set_own_address
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
Definition: gr55xx_ll_i2c.h:755
ll_i2c_clear_flag_start_det
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
Definition: gr55xx_ll_i2c.h:2978
ll_i2c_set_master_addressing_mode
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
Definition: gr55xx_ll_i2c.h:715
ll_i2c_disable_it_gen_call
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1836
ll_i2c_clear_flag_stop_det
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2995
ll_i2c_disable_it_start_det
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1881
ll_i2c_is_active_flag_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2633
ll_i2c_hold_bus_if_rx_full
__STATIC_INLINE void ll_i2c_hold_bus_if_rx_full(i2c_regs_t *I2Cx)
Hold bus when the RX FIFO if full function.
Definition: gr55xx_ll_i2c.h:617
ll_i2c_disable_master_mode
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
Definition: gr55xx_ll_i2c.h:449
ll_i2c_is_active_flag_raw_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2548
ll_i2c_get_master_addressing_mode
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
Definition: gr55xx_ll_i2c.h:733
ll_i2c_clear_flag_tx_abort
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:3046
ll_i2c_disable_it_activity
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1971
ll_i2c_is_active_flag_slave_rx_data_lost
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
Definition: gr55xx_ll_i2c.h:3269
_ll_i2c_init
LL I2C init Structure definition.
Definition: gr55xx_ll_i2c.h:77
ll_i2c_is_active_flag_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2701
ll_i2c_disable_it_read_req
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:2106
ll_i2c_is_enabled_general_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
Definition: gr55xx_ll_i2c.h:512
ll_i2c_get_dma_rx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
Definition: gr55xx_ll_i2c.h:3451
ll_i2c_enable_it
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
Definition: gr55xx_ll_i2c.h:1594
ll_i2c_is_active_flag_slave_dis_whl_busy
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
Definition: gr55xx_ll_i2c.h:3286
ll_i2c_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3336
ll_i2c_set_scl_stuck_at_low_timeout
__STATIC_INLINE void ll_i2c_set_scl_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Definition: gr55xx_ll_i2c.h:3473
ll_i2c_clear_flag_rx_done
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
Definition: gr55xx_ll_i2c.h:3029
ll_i2c_set_clock_low_period_ss
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:805
ll_i2c_clear_flag_rx_over
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
Definition: gr55xx_ll_i2c.h:3097
ll_i2c_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3381
ll_i2c_is_active_flag_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_scl_stuck_at_low(i2c_regs_t *I2Cx)
Definition: gr55xx_ll_i2c.h:2441
ll_i2c_enable_dma_req_rx
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3351
ll_i2c_is_active_flag_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2769
ll_i2c_is_active_flag_raw_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2786
ll_i2c_is_enabled_it_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2301
ll_i2c_receive_data8
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
Definition: gr55xx_ll_i2c.h:3555
ll_i2c_struct_init
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
ll_i2c_disable_general_call
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:497
ll_i2c_is_enabled_it_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2211
ll_i2c_set_data_rx_hold_time
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1133
ll_i2c_set_spike_len_hs
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:997
ll_i2c_is_active_flag_raw_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_scl_stuck_at_low(i2c_regs_t *I2Cx)
Definition: gr55xx_ll_i2c.h:2446
ll_i2c_enable_it_rx_under
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2316
ll_i2c_enable_general_call
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:481
ll_i2c_is_active_flag_status_slave_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:3150
ll_i2c_set_dma_tx_data_level
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
Definition: gr55xx_ll_i2c.h:3400
ll_i2c_is_enabled_it
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1672
ll_i2c_get_dma_tx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
Definition: gr55xx_ll_i2c.h:3415
ll_i2c_is_active_flag_raw_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2684
ll_i2c_get_high_speed_master_code
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1082
ll_i2c_set_clock_high_period_fs
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:837
ll_i2c_enable_it_rx_over
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2271
ll_i2c_enable_it_activity
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1956
ll_i2c_is_active_flag_raw_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
Definition: gr55xx_ll_i2c.h:2582
ll_i2c_ls_enabled_it_rx_full
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2256
ll_i2c_set_clock_high_period_hs
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:901
ll_i2c_get_data_tx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1115
ll_i2c_clear_flag_read_req
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
Definition: gr55xx_ll_i2c.h:3063
ll_i2c_is_active_flag_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2735
ll_i2c_get_spike_len_hs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:1012
ll_i2c_enable_it_rx_done
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:2001
ll_i2c_enable_master_restart
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
Definition: gr55xx_ll_i2c.h:534
ll_i2c_init_t
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
ll_i2c_is_enabled_it_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2166
ll_i2c_is_active_flag_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2531
ll_i2c_clear_flag_activity
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:3012
ll_i2c_is_active_flag_status_rff
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
Definition: gr55xx_ll_i2c.h:3184
ll_i2c_is_active_flag_status_sda_stuck_not_recovered
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_sda_stuck_not_recovered(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS SDA stuck at low is not recovered flag.
Definition: gr55xx_ll_i2c.h:3133
ll_i2c_set_data_setup_time
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1167
ll_i2c_enable_master_mode
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
Definition: gr55xx_ll_i2c.h:434
ll_i2c_set_clock_low_period_hs
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:933
ll_i2c_disable_bus_clear_feature
__STATIC_INLINE void ll_i2c_disable_bus_clear_feature(i2c_regs_t *I2Cx)
disable bus clear feature function.
Definition: gr55xx_ll_i2c.h:665
ll_i2c_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
Definition: gr55xx_ll_i2c.h:1408
ll_i2c_get_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
Definition: gr55xx_ll_i2c.h:2394
ll_i2c_is_active_flag_raw_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2514
ll_i2c_is_enabled_it_read_req
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2121
ll_i2c_enable_it_gen_call
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1821
ll_i2c_disable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:601
ll_i2c_is_enabled_master_restart
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
Definition: gr55xx_ll_i2c.h:565
ll_i2c_get_speed_mode
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1050
ll_i2c_enable_bus_clear_feature
__STATIC_INLINE void ll_i2c_enable_bus_clear_feature(i2c_regs_t *I2Cx)
enable bus clear feature function.
Definition: gr55xx_ll_i2c.h:649
ll_i2c_disable_it_master_on_hold
__STATIC_INLINE void ll_i2c_disable_it_master_on_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1746
ll_i2c_set_slave_address
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3502
ll_i2c_set_high_speed_master_code
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
Definition: gr55xx_ll_i2c.h:1067
ll_i2c_disable_it_rx_done
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:2016
ll_i2c_is_enabled
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
Definition: gr55xx_ll_i2c.h:419
ll_i2c_enable_it_restart_det
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1776
ll_i2c_is_active_flag_raw_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2854
ll_i2c_is_active_flag_raw_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2922
ll_i2c_set_clock_high_period_ss
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:773
ll_i2c_is_active_flag_raw_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2820
ll_i2c_is_active_flag_raw_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2616
ll_i2c_disable_it_rx_under
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2331
ll_i2c_set_clock_low_period_fs
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:869
ll_i2c_is_enable_it_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2031
ll_i2c_handle_transfer
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
Definition: gr55xx_ll_i2c.h:3539
ll_i2c_clear_flag_gen_call
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2961
ll_i2c_is_enabled_it_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Check if the SCL_STUCK_AT_LOW Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1715
ll_i2c_is_active_flag_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
Definition: gr55xx_ll_i2c.h:2565
ll_i2c_get_clock_high_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:852
ll_i2c_enable_it_rx_abort
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:2046
ll_i2c_enable_it_tx_empty
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:2136
ll_i2c_set_data_tx_hold_time
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1100
_ll_i2c_init::own_address
uint32_t own_address
Specifies the device own address.
Definition: gr55xx_ll_i2c.h:80
ll_i2c_disable
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
Definition: gr55xx_ll_i2c.h:404
ll_i2c_set_spike_len_fs
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:965
ll_i2c_is_enabled_it_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1851
ll_i2c_disable_it_tx_abort
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:2061
ll_i2c_is_active_flag_raw_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2888
ll_i2c_get_raw_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
Definition: gr55xx_ll_i2c.h:2436
ll_i2c_get_clock_low_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:820
ll_i2c_transmit_data8
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
Definition: gr55xx_ll_i2c.h:3579
ll_i2c_enable_it_rx_full
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:2226