gr55xx_ll_xqspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_xqspi.h
5 * @author BLE SDK Team
6 * @brief Header file containing functions prototypes of XQSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_XQSPI XQSPI
47 * @brief XQSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (XQSPI)
63
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief XQSPI High Performance mode init structures definition
75 */
76 typedef struct _ll_xqspi_hp_init_t
77 {
78 uint8_t xqspi_hp_enable; /**< Specifies If enable the HP mode for XQSPI.
79 This parameter can be a value of @ref XQSPI_HP_MODE_EN */
80
81 uint8_t xqspi_hp_cmd; /**< Specifies the command to enter HP mode for XQSPI. */
82
83 uint8_t xqspi_hp_end_dummy; /**< Specifies the end dummpy cycle in HP mode for XQSPI. */
84
85 } ll_xqspi_hp_init_t;
86
87 /**
88 * @brief XQSPI init structures definition
89 */
90 typedef struct _ll_xqspi_init_t
91 {
92 uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
93 This parameter can be a value of @ref XQSPI_LL_EC_MODE.*/
94
95 uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
96 This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
97
98 This feature can be modified afterwards using unitary function @ref ll_xqspi_enable_cache().*/
99
100 uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
101 This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
102
103 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cmd().*/
104
105 uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
106 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
107
108 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_datasize().*/
109
110 uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
111 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
112
113 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_data_order().*/
114
115 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
116 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_POLARITY in XIP mode or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
117
118 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol().*/
119
120 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
121 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_PHASE in XIP mode or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
122
123 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha().*/
124
125 uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and receive SCK clock.
126 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
127
128 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_speed().*/
129
130 uint32_t cache_direct_map_en; /**< Specifies the XQSPI Cache work on direct map or 4-way set associative.
131 This parameter can be a value of @ref XQSPI_LL_CACHE_DIRECT_MAP_EN.*/
132
133 uint32_t cache_flush; /**< Specifies the XQSPI Cache will be flushed or not.
134 This parameter can be a value of @ref LL_XQSPI_CACHE_FLUSH_EN.*/
135
136 ll_xqspi_hp_init_t hp_init; /**< Specifies the XQSPI HP mode Configuration.
137 This structures is defined @ref ll_xqspi_hp_init_t.*/
138
139 } ll_xqspi_init_t;
140
141 /** @} */
142
143 /** @} */
144
145 /**
146 * @defgroup XQSPI_LL_MACRO Defines
147 * @{
148 */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
152 * @{
153 */
154
155 /** @defgroup XQSPI_HP_MODE_EN XQSPI HP mode
156 * @{
157 */
158 #define LL_XQSPI_HP_MODE_DIS 0 /**< Disable XQSPI High Performance mode */
159 #define LL_XQSPI_HP_MODE_EN 1 /**< Enable XQSPI High Performance mode */
160 /** @} */
161
162 /** @defgroup XQSPI_1st_prefetch XQSPI 1st prefetch enable
163 * @{
164 */
165 #define LL_XQSPI_1ST_PREFETCH_DIS XQSPI_RG_1ST_PREFETCH_DIS_Msk /**< Disable XQSPI 1st prefetch */
166 #define LL_XQSPI_1ST_PREFETCH_EN 0 /**< Enable XQSPI 1st prefetch */
167 /** @} */
168
169 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
170 * @{
171 */
172 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
173 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
174 /** @} */
175
176 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
177 * @{
178 */
179 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
180 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
181 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
182 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
183 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
184 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
185 /** @} */
186
187 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
188 * @{
189 */
190 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
191 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
192 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
193 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
194 /** @} */
195
196 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
197 * @{
198 */
199 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
200 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
201 /** @} */
202
203 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
204 * @{
205 */
206 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
207 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
208 /** @} */
209
210 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
211 * @{
212 */
213 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
214 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
215 /** @} */
216
217 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
218 * @{
219 */
220 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
221 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
222 /** @} */
223
224 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
225 * @{
226 */
227 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
228 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
229 /** @} */
230
231 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
232 * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
233 * @{
234 */
235 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
236 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
237 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
238 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
239 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
240 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
241 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
242 /** @} */
243
244 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
245 * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
246 * @{
247 */
248 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
249 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
250 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt enable */
251 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt enable */
252 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
253
254 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
255 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
256 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
257 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt flag */
258 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
259 /** @} */
260
261 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
262 * @{
263 */
264 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
265 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
266 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
267 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
268 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL /**< FIFO full depth */
269 /** @} */
270
271 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
272 * @{
273 */
274 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
275 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format for transfer */
276 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format for transfer */
277 /** @} */
278
279 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
280 * @{
281 */
282 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
283 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
284 /** @} */
285
286 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
287 * @{
288 */
289 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI transfer: 4 bits */
290 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 8 bits */
291 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 12 bits */
292 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 16 bits */
293 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 20 bits */
294 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 24 bits */
295 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 28 bits */
296 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 32 bits */
297 /** @} */
298
299 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
300 * @{
301 */
302 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
303 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
304 /** @} */
305
306 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
307 * @{
308 */
309 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
310 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
311 /** @} */
312
313 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
314 * @{
315 */
316 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
317 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
318 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
319 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
320 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
321 /** @} */
322
323 /** @defgroup XQSPI_LL_CACHE_DIRECT_MAP_EN XQSPI Cache direct map enable
324 * @{
325 */
326 #define LL_XQSPI_CACHE_DIRECT_MAP_DIS 0 /**< Cache work on 4-Way Set Associative */
327 #define LL_XQSPI_CACHE_DIRECT_MAP_EN 1 /**< Cache work on Direct Map */
328 /** @} */
329
330 /** @defgroup XQSPI_LL_CACHE_FLUSH_EN XQSPI Cache flush enable
331 * @{
332 */
333 #define LL_XQSPI_CACHE_FLUSH_DIS 1 /**< Cache Flush Disable */
334 #define LL_XQSPI_CACHE_FLUSH_EN 0 /**< Cache Flush Enable */
335
336 /** @} */
337
338 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
339 * @{
340 */
341 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
342 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
343 /** @} */
344
345 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
346 * @{
347 */
348 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
349 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
350 /** @} */
351
352 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
353 * @{
354 */
355
356 /**
357 * @brief LL XQSPI InitStrcut default configuartion
358 */
359 #define LL_XQSPI_DEFAULT_CONFIG \
360 { \
361 .mode = LL_XQSPI_MODE_QSPI, \
362 .cache_mode = LL_XQSPI_CACHE_EN, \
363 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
364 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
365 .data_order = LL_XQSPI_QSPI_MSB, \
366 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
367 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
368 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
369 .cache_direct_map_en= LL_XQSPI_CACHE_DIRECT_MAP_DIS, \
370 .cache_flush = LL_XQSPI_CACHE_FLUSH_EN, \
371 }
372 /** @} */
373
374 /** @} */
375
376 /* Exported macro ------------------------------------------------------------*/
377 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
378 * @{
379 */
380
381 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
382 * @{
383 */
384
385 /**
386 * @brief Write a value in XQSPI register
387 * @param __instance__ XQSPI instance
388 * @param __REG__ Register to be written
389 * @param __VALUE__ Value to be written in the register
390 * @retval None
391 */
392 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
393
394 /**
395 * @brief Read a value in XQSPI register
396 * @param __instance__ XQSPI instance
397 * @param __REG__ Register to be read
398 * @retval Register value
399 */
400 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
401
402 /** @} */
403
404 /** @} */
405
406 /** @} */
407
408 /* Exported functions --------------------------------------------------------*/
409 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
410 * @{
411 */
412
413 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
414 * @{
415 */
416
417 /**
418 * @brief Enable cache function
419 * @note This bit should not be changed when XIP is ongoing.
420 *
421 * Register|BitsName
422 * --------|--------
423 * CTRL0 |EN
424 *
425 * @param XQSPIx XQSPI instance
426 * @retval None
427 */
428 __STATIC_FORCEINLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
429 {
430 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
431 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
432 }
433
434 /**
435 * @brief Disable cache function
436 * @note This bit should not be changed when XIP is ongoing.
437 *
438 * Register|BitsName
439 * --------|--------
440 * CTRL0 |EN
441 *
442 * @param XQSPIx XQSPI instance
443 * @retval None
444 */
445 __STATIC_FORCEINLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
446 {
447 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
448 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
449 }
450
451 /**
452 * @brief Check if cache function is enabled
453 *
454 * Register|BitsName
455 * --------|--------
456 * CTRL0 |EN
457 *
458 * @param XQSPIx XQSPI instance
459 * @retval State of bit (1 or 0).
460 */
461 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
462 {
463 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
464 }
465
466 /**
467 * @brief Enable cache direct map function
468 * @note This bit should not be changed when XIP is ongoing.
469 *
470 * Register|BitsName
471 * --------|--------
472 * CTRL0 |DIRECT_MAP
473 *
474 * @param XQSPIx XQSPI instance
475 * @retval None
476 */
477 __STATIC_FORCEINLINE void ll_xqspi_cache_direct_map_enable(xqspi_regs_t *XQSPIx)
478 {
479 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
480 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
481 }
482
483 /**
484 * @brief Disable cache direct map function
485 * @note This bit should not be changed when XIP is ongoing.
486 *
487 * Register|BitsName
488 * --------|--------
489 * CTRL0 |DIRECT_MAP
490 *
491 * @param XQSPIx XQSPI instance
492 * @retval None
493 */
494 __STATIC_FORCEINLINE void ll_xqspi_cache_direct_map_disable(xqspi_regs_t *XQSPIx)
495 {
496 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
497 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
498 }
499
500 /**
501 * @brief Check if cache direct map function is enabled
502 *
503 * Register|BitsName
504 * --------|--------
505 * CTRL0 |DIRECT_MAP
506 *
507 * @param XQSPIx XQSPI instance
508 * @retval State of bit (1 or 0).
509 */
510 __STATIC_FORCEINLINE uint32_t ll_xqspi_cache_direct_map_is_enabled(xqspi_regs_t *XQSPIx)
511 {
512 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN));
513 }
514
515 /**
516 * @brief Enable tag memory flush
517 * @note This bit should not be changed when XIP is ongoing.
518 *
519 * Register|BitsName
520 * --------|--------
521 * CTRL0 |TAG
522 *
523 * @param XQSPIx XQSPI instance
524 * @retval None
525 */
526 __STATIC_FORCEINLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
527 {
528 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
529 }
530
531 /**
532 * @brief Disable tag memory flush
533 * @note This bit should not be changed when XIP is ongoing.
534 *
535 * Register|BitsName
536 * --------|--------
537 * CTRL0 |TAG
538 *
539 * @param XQSPIx XQSPI instance
540 * @retval None
541 */
542 __STATIC_FORCEINLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
543 {
544 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
545 }
546
547 /**
548 * @brief Check if tag memory flush is enabled
549 *
550 * Register|BitsName
551 * --------|--------
552 * CTRL0 |TAG
553 *
554 * @param XQSPIx XQSPI instance
555 * @retval State of bit (1 or 0).
556 */
557 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
558 {
559 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
560 }
561
562 /**
563 * @brief Set cache gating dynamically
564 *
565 * Register|BitsName
566 * --------|--------
567 * CTRL0 |CLK_FORCE_EN
568 *
569 * @param XQSPIx XQSPI instance
570 * @retval None
571 */
572 __STATIC_FORCEINLINE void ll_xqspi_set_cache_clk_force_en(xqspi_regs_t *XQSPIx)
573 {
574 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_CLK_FORCE_EN, XQSPI_CACHE_CTRL0_CLK_FORCE_EN);
575 }
576
577 /**
578 * @brief Set FIFO mode
579 * @note This bit should not be changed when XIP is ongoing.
580 *
581 * Register|BitsName
582 * --------|--------
583 * CTRL0 |FIFO
584 *
585 * @param XQSPIx XQSPI instance
586 * @param mode This parameter can be one of the following values:
587 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
588 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
589 * @retval None
590 */
591 __STATIC_FORCEINLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
592 {
593 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
594 }
595
596 /**
597 * @brief Get FIFO mode
598 * @note This bit should not be changed when XIP is ongoing.
599 *
600 * Register|BitsName
601 * --------|--------
602 * CTRL0 |FIFO
603 *
604 * @param XQSPIx XQSPI instance
605 * @retval Returned Value can be one of the following values:
606 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
607 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
608 */
609 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
610 {
611 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
612 }
613
614 /**
615 * @brief Set HIT/MISS mode
616 * @note This bit should not be changed when XIP is ongoing.
617 *
618 * Register|BitsName
619 * --------|--------
620 * CTRL0 |HITMISS
621 *
622 * @param XQSPIx XQSPI instance
623 * @param mode This parameter can be one of the following values:
624 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
625 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
626 * @retval None
627 */
628 __STATIC_FORCEINLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
629 {
630 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
631 }
632
633 /**
634 * @brief Get HIT/MISS mode
635 * @note This bit should not be changed when XIP is ongoing.
636 *
637 * Register|BitsName
638 * --------|--------
639 * CTRL0 |HITMISS
640 *
641 * @param XQSPIx XQSPI instance
642 * @retval Returned Value can be one of the following values:
643 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
644 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
645 */
646 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
647 {
648 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
649 }
650
651 /**
652 * @brief Set debugbus configurations signals
653 * @note These bits should not be changed when XIP is ongoing.
654 *
655 * Register|BitsName
656 * --------|--------
657 * CTRL1 |DBGBUS_SEL
658 *
659 * @param XQSPIx XQSPI instance
660 * @param sel This parameter can between: 0 ~ 0x7
661 * @retval None
662 */
663 __STATIC_FORCEINLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
664 {
665 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
666 }
667
668 /**
669 * @brief Get debugbus configurations signals
670 *
671 * Register|BitsName
672 * --------|--------
673 * CTRL1 |DBGBUS_SEL
674 *
675 * @param XQSPIx XQSPI instance
676 * @retval Returned Value can between: 0 ~ 0x7
677 */
678 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
679 {
680 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
681 }
682
683 /**
684 * @brief Enable debug bus mux
685 * @note This bit should not be changed when XIP is ongoing.
686 *
687 * Register|BitsName
688 * --------|--------
689 * CTRL1 |DBGMUX_EN
690 *
691 * @param XQSPIx XQSPI instance
692 * @retval None
693 */
694 __STATIC_FORCEINLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
695 {
696 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
697 }
698
699 /**
700 * @brief Disable debug bus mux
701 * @note This bit should not be changed when XIP is ongoing.
702 *
703 * Register|BitsName
704 * --------|--------
705 * CTRL1 |DBGMUX_EN
706 *
707 * @param XQSPIx XQSPI instance
708 * @retval None
709 */
710 __STATIC_FORCEINLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
711 {
712 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
713 }
714
715 /**
716 * @brief Check if debug bus mux is enabled
717 *
718 * Register|BitsName
719 * --------|--------
720 * CTRL1 |DBGMUX_EN
721 *
722 * @param XQSPIx XQSPI instance
723 * @retval State of bit (1 or 0).
724 */
725 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
726 {
727 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
728 }
729
730 /**
731 * @brief Get hit counter
732 * @note This bit only be read.
733 *
734 * Register|BitsName
735 * --------|--------
736 * HIT_COUNT|HITCOUNT
737 *
738 * @param XQSPIx XQSPI instance
739 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
740 */
741 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
742 {
743 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
744 }
745
746 /**
747 * @brief Get miss counter
748 * @note This bit only be read.
749 *
750 * Register|BitsName
751 * --------|--------
752 * MISS_COUNT|MISSCOUNT
753 *
754 * @param XQSPIx XQSPI instance
755 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
756 */
757 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
758 {
759 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
760 }
761
762 /**
763 * @brief Get cache status
764 * @note This bit only be read.
765 *
766 * Register|BitsName
767 * --------|--------
768 * STAT |STAT
769 *
770 * @param XQSPIx XQSPI instance
771 * @retval Returned Value can between: 0 ~ 1
772 */
773 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
774 {
775 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
776 }
777
778 /** @} */
779
780 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
781 * @{
782 */
783
784 /**
785 * @brief Set read command
786 * @note These bits should not be changed when XIP is ongoing.
787 *
788 * Register|BitsName
789 * --------|--------
790 * CTRL0 |CFG_CMD
791 *
792 * @param XQSPIx XQSPI instance
793 * @param cmd This parameter can be one of the following values:
794 * @arg @ref LL_XQSPI_XIP_CMD_READ
795 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
796 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
797 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
798 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
799 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
800 * @retval None
801 */
802 __STATIC_FORCEINLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
803 {
804 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
805 }
806
807 /**
808 * @brief Get read command
809 *
810 * Register|BitsName
811 * --------|--------
812 * CTRL0 |CFG_CMD
813 *
814 * @param XQSPIx XQSPI instance
815 * @retval Returned Value can be one of the following values:
816 * @arg @ref LL_XQSPI_XIP_CMD_READ
817 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
818 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
819 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
820 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
821 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
822 */
823 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
824 {
825 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
826 }
827
828 /**
829 * @brief Enable high performance mode
830 * @note This bit should not be changed when XIP is ongoing.
831 *
832 * Register|BitsName
833 * --------|--------
834 * CTRL1 |CFG_HPEN
835 *
836 * @param XQSPIx XQSPI instance
837 * @retval None
838 */
839 __STATIC_FORCEINLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
840 {
841 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
842 }
843
844 __STATIC_FORCEINLINE void ll_xqspi_soft_rst_req(xqspi_regs_t *XQSPIx)
845 {
846 SET_BITS(XQSPIx->XIP.SOFT_RST, XQSPI_XIP_SOFT_RST);
847 }
848
849 /**
850 * @brief Disable high performance mode
851 * @note This bit should not be changed when XIP is ongoing.
852 *
853 * Register|BitsName
854 * --------|--------
855 * CTRL1 |CFG_HPEN
856 *
857 * @param XQSPIx XQSPI instance
858 * @retval None
859 */
860 __STATIC_FORCEINLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
861 {
862 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
863 }
864
865 /**
866 * @brief Check if high performance mode is enabled
867 *
868 * Register|BitsName
869 * --------|--------
870 * CTRL1 |CFG_HPEN
871 *
872 * @param XQSPIx XQSPI instance
873 * @retval State of bit (1 or 0).
874 */
875 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
876 {
877 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
878 }
879
880 /**
881 * @brief Set slave select
882 * @note These bits should not be changed when XIP is ongoing.
883 *
884 * Register|BitsName
885 * --------|--------
886 * CTRL1 |CFG_SS
887 *
888 * @param XQSPIx XQSPI instance
889 * @param ss This parameter can be one or more of the following values:
890 * @arg @ref LL_XQSPI_XIP_SS0
891 * @arg @ref LL_XQSPI_XIP_SS1
892 * @arg @ref LL_XQSPI_XIP_SS2
893 * @arg @ref LL_XQSPI_XIP_SS3
894 * @retval None
895 */
896 __STATIC_FORCEINLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
897 {
898 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
899 }
900
901 /**
902 * @brief Get slave select
903 *
904 * Register|BitsName
905 * --------|--------
906 * CTRL1 |CFG_SS
907 *
908 * @param XQSPIx XQSPI instance
909 * @retval Returned Value can be one of the following values:
910 * @arg @ref LL_XQSPI_XIP_SS0
911 * @arg @ref LL_XQSPI_XIP_SS1
912 * @arg @ref LL_XQSPI_XIP_SS2
913 * @arg @ref LL_XQSPI_XIP_SS3
914 */
915 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
916 {
917 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
918 }
919
920 /**
921 * @brief Set clock phase
922 * @note This bit should not be changed when XIP is ongoing.
923 *
924 * Register|BitsName
925 * --------|--------
926 * CTRL1 |CFG_CPHA
927 *
928 * @param XQSPIx XQSPI instance
929 * @param cpha This parameter can be one or more of the following values:
930 * @arg @ref LL_XQSPI_SCPHA_1EDGE
931 * @arg @ref LL_XQSPI_SCPHA_2EDGE
932 * @retval None
933 */
934 __STATIC_FORCEINLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
935 {
936 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
937 }
938
939 /**
940 * @brief Get clock phase
941 *
942 * Register|BitsName
943 * --------|--------
944 * CTRL1 |CFG_CPHA
945 *
946 * @param XQSPIx XQSPI instance
947 * @retval Returned Value can be one of the following values:
948 * @arg @ref LL_XQSPI_SCPHA_1EDGE
949 * @arg @ref LL_XQSPI_SCPHA_2EDGE
950 */
951 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
952 {
953 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
954 }
955
956 /**
957 * @brief Set clock polarity
958 * @note This bit should not be changed when XIP is ongoing.
959 *
960 * Register|BitsName
961 * --------|--------
962 * CTRL1 |CFG_CPOL
963 *
964 * @param XQSPIx XQSPI instance
965 * @param cpol This parameter can be one or more of the following values:
966 * @arg @ref LL_XQSPI_SCPOL_LOW
967 * @arg @ref LL_XQSPI_SCPOL_HIGH
968 * @retval None
969 */
970 __STATIC_FORCEINLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
971 {
972 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
973 }
974
975 /**
976 * @brief Get clock polarity
977 *
978 * Register|BitsName
979 * --------|--------
980 * CTRL1 |CFG_CPOL
981 *
982 * @param XQSPIx XQSPI instance
983 * @retval Returned Value can be one of the following values:
984 * @arg @ref LL_XQSPI_SCPOL_LOW
985 * @arg @ref LL_XQSPI_SCPOL_HIGH
986 */
987 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
988 {
989 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
990 }
991
992 /**
993 * @brief Set address bytes in command
994 * @note This bit should not be changed when XIP is ongoing.
995 *
996 * Register|BitsName
997 * --------|--------
998 * CTRL1 |CFG_ADDR4
999 *
1000 * @param XQSPIx XQSPI instance
1001 * @param size This parameter can be one or more of the following values:
1002 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1003 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1004 * @retval None
1005 */
1006 __STATIC_FORCEINLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
1007 {
1008 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
1009 }
1010
1011 /**
1012 * @brief Get address bytes in command
1013 *
1014 * Register|BitsName
1015 * --------|--------
1016 * CTRL1 |CFG_ADDR4
1017 *
1018 * @param XQSPIx XQSPI instance
1019 * @retval Returned Value can be one of the following values:
1020 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1021 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1022 */
1023 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
1024 {
1025 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
1026 }
1027
1028 /**
1029 * @brief Set endian in reading data
1030 * @note This bit should not be changed when XIP is ongoing.
1031 *
1032 * Register|BitsName
1033 * --------|--------
1034 * CTRL1 |CFG_LE32
1035 *
1036 * @param XQSPIx XQSPI instance
1037 * @param endian This parameter can be one or more of the following values:
1038 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1039 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1040 * @retval None
1041 */
1042 __STATIC_FORCEINLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
1043 {
1044 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
1045 }
1046
1047 /**
1048 * @brief Get endian in reading data
1049 *
1050 * Register|BitsName
1051 * --------|--------
1052 * CTRL1 |CFG_LE32
1053 *
1054 * @param XQSPIx XQSPI instance
1055 * @retval Returned Value can be one of the following values:
1056 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1057 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1058 */
1059 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
1060 {
1061 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
1062 }
1063
1064 /**
1065 * @brief Set high performance command
1066 * @note These bits should not be changed when XIP is ongoing.
1067 *
1068 * Register|BitsName
1069 * --------|--------
1070 * CTRL2 |CFG_HPMODE
1071 *
1072 * @param XQSPIx XQSPI instance
1073 * @param cmd This value is specified by different QSPI FLASH memory vendor to enter into its status register
1074 * to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF.
1075 * @retval None
1076 */
1077 __STATIC_FORCEINLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
1078 {
1079 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
1080 }
1081
1082 /**
1083 * @brief Get high performance command
1084 *
1085 * Register|BitsName
1086 * --------|--------
1087 * CTRL2 |CFG_HPMODE
1088 *
1089 * @param XQSPIx XQSPI instance
1090 * @retval Returned Value can between: 0 ~ 0xFF.
1091 */
1092 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
1093 {
1094 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
1095 }
1096
1097 /**
1098 * @brief Set dummy cycles in command
1099 * @note These bits should not be changed when XIP is ongoing.
1100 * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1101 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1102 * - Fast Read Dual Out: dummycycles = 8 * cycles
1103 * - Fast Read Quad Out: dummycycles = 8 * cycles
1104 *
1105 * Register|BitsName
1106 * --------|--------
1107 * CTRL2 |CFG_DUMMYCYCLES
1108 *
1109 * @param XQSPIx XQSPI instance
1110 * @param cycles This parameter can between: 0 ~ 0xF.
1111 * @retval None
1112 */
1113 __STATIC_FORCEINLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
1114 {
1115 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1116 }
1117
1118 /**
1119 * @brief Get dummy cycles in command
1120 * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1121 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1122 * - Fast Read Dual Out: dummycycles = 8 * cycles
1123 * - Fast Read Quad Out: dummycycles = 8 * cycles
1124 *
1125 * Register|BitsName
1126 * --------|--------
1127 * CTRL2 |CFG_DUMMYCYCLES
1128 *
1129 * @param XQSPIx XQSPI instance
1130 * @retval Returned Value can between: 0 ~ 0xF.
1131 */
1132 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1133 {
1134 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES) >> XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1135 }
1136 /**
1137 * @brief Set dummy cycles in high performance end
1138 * @note These bits should not be changed when XIP is ongoing.
1139 *
1140 * Register|BitsName
1141 * --------|--------
1142 * CTRL2 |CFG_ENDDUMMY
1143 *
1144 * @param XQSPIx XQSPI instance
1145 * @param cycles This parameter can between: 0 ~ 3.
1146 * @retval None
1147 */
1148 __STATIC_FORCEINLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1149 {
1150 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1151 }
1152
1153 /**
1154 * @brief Get dummy cycles in high performance end
1155 *
1156 * Register|BitsName
1157 * --------|--------
1158 * CTRL2 |CFG_ENDDUMMY
1159 *
1160 * @param XQSPIx XQSPI instance
1161 * @retval Returned Value can between: 0 ~ 3.
1162 */
1163 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1164 {
1165 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1166 }
1167
1168 /**
1169 * @brief Enable XIP mode
1170 *
1171 * Register|BitsName
1172 * --------|--------
1173 * CTRL3 |EN_REQ
1174 *
1175 * @param XQSPIx XQSPI instance
1176 * @retval None
1177 */
1178 __STATIC_FORCEINLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1179 {
1180 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1181 }
1182
1183 /**
1184 * @brief Disable XIP mode
1185 *
1186 * Register|BitsName
1187 * --------|--------
1188 * CTRL3 |EN_REQ
1189 *
1190 * @param XQSPIx XQSPI instance
1191 * @retval None
1192 */
1193 __STATIC_FORCEINLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1194 {
1195 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1196 }
1197
1198 /**
1199 * @brief Check if XIP mode is enabled
1200 * @note This bit should not be changed when XIP is ongoing.
1201 *
1202 * Register|BitsName
1203 * --------|--------
1204 * CTRL3 |EN_REQ
1205 *
1206 * @param XQSPIx XQSPI instance
1207 * @retval State of bit (1 or 0).
1208 */
1209 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1210 {
1211 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1212 }
1213
1214 /**
1215 * @brief Get XIP status
1216 * @note This bit is read-only.
1217 *
1218 * Register|BitsName
1219 * --------|--------
1220 * STAT |EN_OUT
1221 *
1222 * @param XQSPIx XQSPI instance
1223 * @retval Returned Value can between: 0 ~ 1
1224 */
1225 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1226 {
1227 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1228 }
1229
1230 /**
1231 * @brief Check if XIP interrupt is enabled
1232 * @note This bit is read-only.
1233 *
1234 * Register|BitsName
1235 * --------|--------
1236 * INTEN |INT_EN
1237 *
1238 * @param XQSPIx XQSPI instance
1239 * @retval Returned Value can between: 0 ~ 1
1240 */
1241 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1242 {
1243 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1244 }
1245
1246 /**
1247 * @brief Get XIP interrupt flag
1248 * @note This bit is read-only.
1249 *
1250 * Register|BitsName
1251 * --------|--------
1252 * INTSTAT |INT_STAT
1253 *
1254 * @param XQSPIx XQSPI instance
1255 * @retval Returned Value can between: 0 ~ 1
1256 */
1257 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1258 {
1259 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1260 }
1261
1262 /**
1263 * @brief Get XIP interrupt request
1264 * @note This bit is read-only.
1265 *
1266 * Register|BitsName
1267 * --------|--------
1268 * INTREQ |INT_REQ
1269 *
1270 * @param XQSPIx XQSPI instance
1271 * @retval Returned Value can between: 0 ~ 1
1272 */
1273 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1274 {
1275 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1276 }
1277
1278 /**
1279 * @brief Set XIP interrupt enable
1280 * @note This bit is write-only.
1281 *
1282 * Register|BitsName
1283 * --------|--------
1284 * INTSET |INT_SET
1285 *
1286 * @param XQSPIx XQSPI instance
1287 * @retval None
1288 */
1289 __STATIC_FORCEINLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1290 {
1291 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1292 }
1293
1294 /**
1295 * @brief Set XIP interrupt disable
1296 * @note This bit is write-only.
1297 *
1298 * Register|BitsName
1299 * --------|--------
1300 * INTCLR |INT_CLR
1301 *
1302 * @param XQSPIx XQSPI instance
1303 * @retval None
1304 */
1305 __STATIC_FORCEINLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1306 {
1307 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1308 }
1309
1310 /** @} */
1311
1312 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1313 * @{
1314 */
1315
1316 /**
1317 * @brief Write 8-bit in the data register
1318 *
1319 * Register|BitsName
1320 * --------|--------
1321 * TX_DATA | DATA
1322 *
1323 * @param XQSPIx XQSPI instance
1324 * @param tx_data This parameter can between: 0x00 ~ 0xFF
1325 * @retval None
1326 */
1327 __STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1328 {
1329 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1330 }
1331
1332 /**
1333 * @brief Write 16-bit in the data register
1334 *
1335 * Register|BitsName
1336 * --------|--------
1337 * TX_DATA | DATA
1338 *
1339 * @param XQSPIx XQSPI instance
1340 * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1341 * @retval None
1342 */
1343 __STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1344 {
1345 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1346 }
1347
1348 /**
1349 * @brief Write 32-bit in the data register
1350 *
1351 * Register|BitsName
1352 * --------|--------
1353 * TX_DATA | DATA
1354 *
1355 * @param XQSPIx XQSPI instance
1356 * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1357 * @retval None
1358 */
1359 __STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1360 {
1361 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1362 }
1363
1364 /**
1365 * @brief Read 8 bits in the data register
1366 *
1367 * Register|BitsName
1368 * --------|--------
1369 * RX_DATA | DATA
1370 *
1371 * @param XQSPIx XQSPI instance
1372 * @retval Returned Value between: 0x00 ~ 0xFF
1373 */
1374 __STATIC_FORCEINLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1375 {
1376 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1377 }
1378
1379 /**
1380 * @brief Read 16 bits in the data register
1381 *
1382 * Register|BitsName
1383 * --------|--------
1384 * RX_DATA | DATA
1385 *
1386 * @param XQSPIx XQSPI instance
1387 * @retval Returned Value between: 0x00 ~ 0xFFFF
1388 */
1389 __STATIC_FORCEINLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1390 {
1391 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1392 }
1393
1394 /**
1395 * @brief Read 32 bits in the data register
1396 *
1397 * Register|BitsName
1398 * --------|--------
1399 * RX_DATA | DATA
1400 *
1401 * @param XQSPIx XQSPI instance
1402 * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1403 */
1404 __STATIC_FORCEINLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1405 {
1406 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1407 }
1408
1409 /**
1410 * @brief Set TX FIFO threshold level
1411 * @note FIFO maximum depth is 16 units.
1412 *
1413 * Register|BitsName
1414 * --------|--------
1415 * CTRL |TXWMARK
1416 *
1417 * @param XQSPIx XQSPI instance
1418 * @param threshold This parameter can be one of the following values:
1419 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1420 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1421 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1422 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1423 * @retval None
1424 */
1425 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1426 {
1427 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1428 }
1429
1430 /**
1431 * @brief Get TX FIFO threshold level
1432 * @note FIFO maximum depth is 16 units.
1433 *
1434 * Register|BitsName
1435 * --------|--------
1436 * CTRL |TXWMARK
1437 *
1438 * @param XQSPIx XQSPI instance
1439 * @retval Returned Value can be one of the following values:
1440 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1441 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1442 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1443 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1444 */
1445 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1446 {
1447 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1448 }
1449
1450 /**
1451 * @brief Set RX FIFO threshold level
1452 * @note FIFO maximum depth is 16 units.
1453 *
1454 * Register|BitsName
1455 * --------|--------
1456 * CTRL |RXWMARK
1457 *
1458 * @param XQSPIx XQSPI instance
1459 * @param threshold This parameter can be one of the following values:
1460 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1461 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1462 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1463 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1464 * @retval None
1465 */
1466 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1467 {
1468 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1469 }
1470
1471 /**
1472 * @brief Get RX FIFO threshold level
1473 * @note FIFO maximum depth is 16 units.
1474 *
1475 * Register|BitsName
1476 * --------|--------
1477 * CTRL |RXWMARK
1478 *
1479 * @param XQSPIx XQSPI instance
1480 * @retval Returned Value can be one of the following values:
1481 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1482 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1483 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1484 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1485 */
1486 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1487 {
1488 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1489 }
1490
1491 /**
1492 * @brief Enable dummy cycles
1493 *
1494 * Register|BitsName
1495 * --------|--------
1496 * CTRL |MWAITEN
1497 *
1498 * @param XQSPIx XQSPI instance
1499 * @retval None
1500 */
1501 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1502 {
1503 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1504 }
1505
1506 /**
1507 * @brief Disable dummy cycles
1508 *
1509 * Register|BitsName
1510 * --------|--------
1511 * CTRL |MWAITEN
1512 *
1513 * @param XQSPIx XQSPI instance
1514 * @retval None
1515 */
1516 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1517 {
1518 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1519 }
1520
1521 /**
1522 * @brief Check if dummy cycles is enabled
1523 *
1524 * Register|BitsName
1525 * --------|--------
1526 * CTRL |MWAITEN
1527 *
1528 * @param XQSPIx XQSPI instance
1529 * @retval State of bit (1 or 0).
1530 */
1531 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1532 {
1533 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1534 }
1535
1536 /**
1537 * @brief Enable DMA mode
1538 *
1539 * Register|BitsName
1540 * --------|--------
1541 * CTRL |DMA
1542 *
1543 * @param XQSPIx XQSPI instance
1544 * @retval None
1545 */
1546 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1547 {
1548 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1549 }
1550
1551 /**
1552 * @brief Disable DMA mode
1553 *
1554 * Register|BitsName
1555 * --------|--------
1556 * CTRL |DMA
1557 *
1558 * @param XQSPIx XQSPI instance
1559 * @retval None
1560 */
1561 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1562 {
1563 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1564 }
1565
1566 /**
1567 * @brief Check if DMA mode is enabled
1568 *
1569 * Register|BitsName
1570 * --------|--------
1571 * CTRL |DMA
1572 *
1573 * @param XQSPIx XQSPI instance
1574 * @retval State of bit (1 or 0).
1575 */
1576 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1577 {
1578 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1579 }
1580
1581 /**
1582 * @brief Set clock polarity
1583 * @note This bit should not be changed when communication is ongoing.
1584 *
1585 * Register|BitsName
1586 * --------|--------
1587 * CTRL |CPOL
1588 *
1589 * @param XQSPIx XQSPI instance
1590 * @param cpol This parameter can be one of the following values:
1591 * @arg @ref LL_XQSPI_SCPOL_LOW
1592 * @arg @ref LL_XQSPI_SCPOL_HIGH
1593 * @retval None
1594 */
1595 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1596 {
1597 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1598 }
1599
1600 /**
1601 * @brief Get clock polarity
1602 *
1603 * Register|BitsName
1604 * --------|--------
1605 * CTRL |CPOL
1606 *
1607 * @param XQSPIx XQSPI instance
1608 * @retval Returned Value can be one of the following values:
1609 * @arg @ref LL_XQSPI_SCPOL_LOW
1610 * @arg @ref LL_XQSPI_SCPOL_HIGH
1611 */
1612 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1613 {
1614 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1615 }
1616
1617 /**
1618 * @brief Set clock phase
1619 * @note This bit should not be changed when communication is ongoing.
1620 *
1621 * Register|BitsName
1622 * --------|--------
1623 * CTRL |CPHA
1624 *
1625 * @param XQSPIx XQSPI instance
1626 * @param cpha This parameter can be one of the following values:
1627 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1628 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1629 * @retval None
1630 */
1631 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1632 {
1633 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1634 }
1635
1636 /**
1637 * @brief Get clock phase
1638 *
1639 * Register|BitsName
1640 * --------|--------
1641 * CTRL |CPHA
1642 *
1643 * @param XQSPIx XQSPI instance
1644 * @retval Returned Value can be one of the following values:
1645 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1646 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1647 */
1648 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1649 {
1650 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1651 }
1652
1653 /**
1654 * @brief Set serial data order
1655 *
1656 * Register|BitsName
1657 * --------|--------
1658 * CTRL |MSB1ST
1659 *
1660 * @param XQSPIx XQSPI instance
1661 * @param order This parameter can be one of the following values:
1662 * @arg @ref LL_XQSPI_QSPI_LSB
1663 * @arg @ref LL_XQSPI_QSPI_MSB
1664 * @retval None
1665 */
1666 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1667 {
1668 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1669 }
1670
1671 /**
1672 * @brief Get serial data order
1673 *
1674 * Register|BitsName
1675 * --------|--------
1676 * CTRL |MSB1ST
1677 *
1678 * @param XQSPIx XQSPI instance
1679 * @retval Returned Value can be one of the following values:
1680 * @arg @ref LL_XQSPI_QSPI_LSB
1681 * @arg @ref LL_XQSPI_QSPI_MSB
1682 */
1683 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1684 {
1685 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1686 }
1687
1688 /**
1689 * @brief Enable continuous transfer mode
1690 *
1691 * Register|BitsName
1692 * --------|--------
1693 * CTRL |CONTXFER
1694 *
1695 * @param XQSPIx XQSPI instance
1696 * @retval None
1697 */
1698 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1699 {
1700 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1701 }
1702
1703 /**
1704 * @brief Disable continuous transfer mode
1705 *
1706 * Register|BitsName
1707 * --------|--------
1708 * CTRL |CONTXFER
1709 *
1710 * @param XQSPIx XQSPI instance
1711 * @retval None
1712 */
1713 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1714 {
1715 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1716 }
1717
1718 /**
1719 * @brief Check if continuous transfer mode is enabled
1720 *
1721 * Register|BitsName
1722 * --------|--------
1723 * CTRL |CONTXFER
1724 *
1725 * @param XQSPIx XQSPI instance
1726 * @retval State of bit (1 or 0).
1727 */
1728 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1729 {
1730 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1731 }
1732
1733 /**
1734 * @brief Enable continuous transfer extend mode
1735 *
1736 * Register|BitsName
1737 * --------|--------
1738 * AUX_CTRL|CONTXFERX
1739 *
1740 * @param XQSPIx XQSPI instance
1741 * @retval None
1742 */
1743 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1744 {
1745 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1746 }
1747
1748 /**
1749 * @brief Disable continuous transfer extend mode
1750 *
1751 * Register|BitsName
1752 * --------|--------
1753 * AUX_CTRL|CONTXFERX
1754 *
1755 * @param XQSPIx XQSPI instance
1756 * @retval None
1757 */
1758 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1759 {
1760 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1761 }
1762
1763 /**
1764 * @brief Check if continuous transfer extend mode is enabled
1765 *
1766 * Register|BitsName
1767 * --------|--------
1768 * AUX_CTRL|CONTXFERX
1769 *
1770 * @param XQSPIx XQSPI instance
1771 * @retval State of bit (1 or 0).
1772 */
1773 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1774 {
1775 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1776 }
1777
1778 /**
1779 * @brief Set data size
1780 * @note These bits should not be changed when communication is ongoing.
1781 *
1782 * Register|BitsName
1783 * --------|--------
1784 * AUX_CTRL|BITSIZE
1785 *
1786 * @param XQSPIx XQSPI instance
1787 * @param szie This parameter can be one of the following values:
1788 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1789 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1790 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1791 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1792 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1793 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1794 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1795 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1796 * @retval None
1797 */
1798 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1799 {
1800 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1801 }
1802
1803 /**
1804 * @brief Get data size
1805 *
1806 * Register|BitsName
1807 * --------|--------
1808 * AUX_CTRL|BITSIZE
1809 *
1810 * @param XQSPIx XQSPI instance
1811 * @retval Returned Value can be one of the following values:
1812 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1813 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1814 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1815 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1816 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1817 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1818 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1819 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1820 */
1821 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1822 {
1823 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1824 }
1825
1826 /**
1827 * @brief Enable inhibt data input to RX FIFO
1828 *
1829 * Register|BitsName
1830 * --------|--------
1831 * AUX_CTRL|INHIBITDIN
1832 *
1833 * @param XQSPIx XQSPI instance
1834 * @retval None
1835 */
1836 __STATIC_FORCEINLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1837 {
1838 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1839 }
1840
1841 /**
1842 * @brief Disable inhibt data input to RX FIFO
1843 *
1844 * Register|BitsName
1845 * --------|--------
1846 * AUX_CTRL|INHIBITDIN
1847 *
1848 * @param XQSPIx XQSPI instance
1849 * @retval None
1850 */
1851 __STATIC_FORCEINLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1852 {
1853 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1854 }
1855
1856 /**
1857 * @brief Check if inhibt data input to RX FIFO is enabled
1858 *
1859 * Register|BitsName
1860 * --------|--------
1861 * AUX_CTRL|INHIBITDIN
1862 *
1863 * @param XQSPIx XQSPI instance
1864 * @retval State of bit (1 or 0).
1865 */
1866 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1867 {
1868 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1869 }
1870
1871 /**
1872 * @brief Enable inhibt data output to TX FIFO
1873 *
1874 * Register|BitsName
1875 * --------|--------
1876 * AUX_CTRL|INHIBITDOUT
1877 *
1878 * @param XQSPIx XQSPI instance
1879 * @retval None
1880 */
1881 __STATIC_FORCEINLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1882 {
1883 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1884 }
1885
1886 /**
1887 * @brief Disable inhibt data output to TX FIFO
1888 *
1889 * Register|BitsName
1890 * --------|--------
1891 * AUX_CTRL|INHIBITDOUT
1892 *
1893 * @param XQSPIx XQSPI instance
1894 * @retval None
1895 */
1896 __STATIC_FORCEINLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1897 {
1898 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1899 }
1900
1901 /**
1902 * @brief Check if inhibt data input to TX FIFO is enabled
1903 *
1904 * Register|BitsName
1905 * --------|--------
1906 * AUX_CTRL|INHIBITDOUT
1907 *
1908 * @param XQSPIx XQSPI instance
1909 * @retval State of bit (1 or 0).
1910 */
1911 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1912 {
1913 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1914 }
1915
1916 /**
1917 * @brief Set frame format
1918 * @note These bits should not be changed when communication is ongoing.
1919 *
1920 * Register|BitsName
1921 * --------|--------
1922 * AUX_CTRL|QMODE
1923 *
1924 * @param XQSPIx XQSPI instance
1925 * @param format This parameter can be one of the following values:
1926 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1927 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1928 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1929 * @retval None
1930 */
1931 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1932 {
1933 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1934 }
1935
1936 /**
1937 * @brief Get frame format
1938 *
1939 * Register|BitsName
1940 * --------|--------
1941 * AUX_CTRL|QMODE
1942 *
1943 * @param XQSPIx XQSPI instance
1944 * @retval Returned Value can be one even value:
1945 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1946 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1947 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1948 */
1949 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1950 {
1951 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1952 }
1953
1954 /**
1955 * @brief Get QSPI status
1956 *
1957 * Register|BitsName
1958 * --------|--------
1959 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1960 *
1961 * @param XQSPIx XQSPI instance
1962 * @retval Returned Value can be one or combination of the following values:
1963 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1964 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1965 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1966 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1967 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1968 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1969 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1970 */
1971 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1972 {
1973 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1974 }
1975
1976 /**
1977 * @brief Check active flag
1978 *
1979 * Register|BitsName
1980 * --------|--------
1981 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1982 *
1983 * @param XQSPIx XQSPI instance
1984 * @param flag This parameter can be one of the following values:
1985 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1986 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1987 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1988 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1989 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1990 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1991 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1992 * @retval State of bit (1 or 0).
1993 */
1994 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1995 {
1996 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
1997 }
1998
1999 /**
2000 * @brief Enable slave select output
2001 *
2002 * Register|BitsName
2003 * --------|--------
2004 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
2005 *
2006 * @param XQSPIx XQSPI instance
2007 * @param ssout This parameter can between: 0 ~ 0xFF
2008 * @retval None
2009 */
2010 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2011 {
2012 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2013 }
2014
2015 /**
2016 * @brief Disable slave select output
2017 *
2018 * Register|BitsName
2019 * --------|--------
2020 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
2021 *
2022 * @param XQSPIx XQSPI instance
2023 * @param ssout This parameter can between: 0 ~ 0xFF
2024 * @retval None
2025 */
2026 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2027 {
2028 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2029 }
2030
2031 /**
2032 * @brief Set slave select output polarity
2033 *
2034 * Register|BitsName
2035 * --------|--------
2036 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
2037 *
2038 * @param XQSPIx XQSPI instance
2039 * @param sspol This parameter can between: 0 ~ 0xFF
2040 * @retval None
2041 */
2042 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
2043 {
2044 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
2045 }
2046
2047 /**
2048 * @brief Get slave select output polarity
2049 *
2050 * Register|BitsName
2051 * --------|--------
2052 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
2053 *
2054 * @param XQSPIx XQSPI instance
2055 * @retval Returned Value can between: 0 ~ 0xFF
2056 */
2057 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
2058 {
2059 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
2060 }
2061
2062 /**
2063 * @brief Get FIFO Transmission Level
2064 *
2065 * Register|BitsName
2066 * --------|--------
2067 * TX_FIFO_LVL | TXFIFOLVL
2068 *
2069 * @param XQSPIx XQSPI instance
2070 * @retval Returned Value can between: 0 ~ 16
2071 */
2072 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
2073 {
2074 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
2075 }
2076
2077 /**
2078 * @brief Get FIFO reception Level
2079 *
2080 * Register|BitsName
2081 * --------|--------
2082 * RX_FIFO_LVL | RXFIFOLVL
2083 *
2084 * @param XQSPIx XQSPI instance
2085 * @retval Returned Value can between: 0 ~ 16
2086 */
2087 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
2088 {
2089 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
2090 }
2091
2092 /**
2093 * @brief Enable interrupt
2094 * @note This bit controls the generation of an interrupt when an event occurs.
2095 *
2096 * Register|BitsName
2097 * --------|--------
2098 * INTEN |INT_EN
2099 *
2100 * @param XQSPIx XQSPI instance
2101 * @param mask This parameter can be one of the following values:
2102 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2103 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2104 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2105 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2106 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2107 * @retval None
2108 */
2109 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2110 {
2111 SET_BITS(XQSPIx->QSPI.INTEN, mask);
2112 }
2113
2114 /**
2115 * @brief Disable interrupt
2116 * @note This bit controls the generation of an interrupt when an event occurs.
2117 *
2118 * Register|BitsName
2119 * --------|--------
2120 * INTEN |INT_EN
2121 *
2122 * @param XQSPIx XQSPI instance
2123 * @param mask This parameter can be one of the following values:
2124 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2125 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2126 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2127 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2128 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2129 * @retval None
2130 */
2131 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2132 {
2133 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2134 }
2135
2136 /**
2137 * @brief Check if interrupt is enabled
2138 *
2139 * Register|BitsName
2140 * --------|--------
2141 * INTEN |INT_EN
2142 *
2143 * @param XQSPIx XQSPI instance
2144 * @param mask This parameter can be one of the following values:
2145 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2146 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2147 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2148 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2149 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2150 * @retval State of bit (1 or 0).
2151 */
2152 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2153 {
2154 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2155 }
2156
2157 /**
2158 * @brief Get XQSPI interrupt flags
2159 *
2160 * Register|BitsName
2161 * --------|--------
2162 * INTSTAT |INT_STAT
2163 *
2164 * @param XQSPIx XQSPI instance
2165 * @retval Returned Value can be one or combination of the following values:
2166 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2167 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2168 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2169 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2170 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2171 */
2172 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2173 {
2174 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2175 }
2176
2177 /**
2178 * @brief Check interrupt flag
2179 *
2180 * Register|BitsName
2181 * --------|--------
2182 * INTSTAT | XFER_DPULSE
2183 * INTSTAT | RX_FPULSE
2184 * INTSTAT | RX_WPULSE
2185 * INTSTAT | TX_WPULSE
2186 * INTSTAT | TX_EPULSE
2187 *
2188 * @param XQSPIx XQSPI instance
2189 * @param flag This parameter can be one of the following values:
2190 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2191 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2192 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2193 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2194 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2195 * @retval State of bit (1 or 0).
2196 */
2197 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2198 {
2199 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2200 }
2201
2202 /**
2203 * @brief Clear interrupt flag
2204 * @note Clearing interrupt flag is done by writting INTCLR register
2205 *
2206 * Register|BitsName
2207 * --------|--------
2208 * INTCLR |INT_CLR
2209 *
2210 * @param XQSPIx XQSPI instance
2211 * @param flag This parameter can be one of the following values:
2212 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2213 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2214 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2215 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2216 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2217 * @retval None
2218 */
2219 __STATIC_FORCEINLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2220 {
2221 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2222 }
2223
2224 /**
2225 * @brief Set master inter-transfer delay
2226 *
2227 * Register|BitsName
2228 * --------|--------
2229 * MSTR_IT_DELAY | MWAIT
2230 *
2231 * @param XQSPIx XQSPI instance
2232 * @param wait This parameter can between: 0 ~ 255
2233 * @retval None
2234 */
2235 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2236 {
2237 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2238 }
2239
2240 /**
2241 * @brief Get master inter-transfer delay
2242 *
2243 * Register|BitsName
2244 * --------|--------
2245 * MSTR_IT_DELAY | MWAIT
2246 *
2247 * @param XQSPIx XQSPI instance
2248 * @retval Returned Value can between: 0 ~ 255
2249 */
2250 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2251 {
2252 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2253 }
2254
2255 /**
2256 * @brief Enable QSPI
2257 * @note This bit should not be enable when XIP is ongoing.
2258 *
2259 * Register|BitsName
2260 * --------|--------
2261 * SPIEN |EN
2262 *
2263 * @param XQSPIx XQSPI instance
2264 * @retval None
2265 */
2266 __STATIC_FORCEINLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2267 {
2268 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2269 }
2270
2271 /**
2272 * @brief Disable QSPI
2273 *
2274 * Register|BitsName
2275 * --------|--------
2276 * SPIEN |EN
2277 *
2278 * @param XQSPIx XQSPI instance
2279 * @retval None
2280 */
2281 __STATIC_FORCEINLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2282 {
2283 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2284 }
2285
2286 /**
2287 * @brief Check if QSPI is enabled
2288 *
2289 * Register|BitsName
2290 * --------|--------
2291 * SPIEN |EN
2292 *
2293 * @param XQSPIx XQSPI instance
2294 * @retval State of bit (1 or 0).
2295 */
2296 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2297 {
2298 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2299 }
2300
2301 /**
2302 * @brief Set QSPI Flash write bits
2303 *
2304 * Register|BitsName
2305 * --------|--------
2306 * FLASH_WRITE |FLASH_WRITE
2307 *
2308 * @param XQSPIx XQSPI instance
2309 * @param bits This parameter can be one of the following values:
2310 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2311 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2312 * @retval None
2313 */
2314 __STATIC_FORCEINLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2315 {
2316 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2317 }
2318
2319 /**
2320 * @brief Get QSPI Flash write bits
2321 *
2322 * Register|BitsName
2323 * --------|--------
2324 * FLASH_WRITE |FLASH_WRITE
2325 *
2326 * @param XQSPIx XQSPI instance
2327 * @retval Returned Value can be one of the following values:
2328 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2329 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2330 */
2331 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2332 {
2333 //GR551xx_C0 and future version.
2334 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2335 }
2336
2337 /**
2338 * @brief Set QSPI Present Bypass
2339 *
2340 * Register|BitsName
2341 * --------|--------
2342 * BYPASS |BYPASS
2343 *
2344 * @param XQSPIx XQSPI instance
2345 * @param bypass This parameter can be one of the following values:
2346 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2347 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2348 * @retval None
2349 */
2350 __STATIC_FORCEINLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2351 {
2352 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2353 }
2354
2355 /**
2356 * @brief Get QSPI Present Bypass
2357 *
2358 * Register|BitsName
2359 * --------|--------
2360 * BYPASS |BYPASS
2361 *
2362 * @param XQSPIx XQSPI instance
2363 * @retval Returned Value can be one of the following values:
2364 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2365 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2366 */
2367 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2368 {
2369 return READ_REG(XQSPIx->QSPI.BYPASS);
2370 }
2371
2372 /**
2373 * @brief CS keeps valid while not reading
2374 * @note This bit should not be changed when XIP is ongoing.
2375 *
2376 * Register |BitsName
2377 * -------------------|--------
2378 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_CS_IDLE_UNVLD_EN
2379 *
2380 * @param XQSPIx XQSPI instance
2381 * @retval None
2382 */
2383 __STATIC_FORCEINLINE void ll_xqspi_set_cs_idle_valid(xqspi_regs_t *XQSPIx)
2384 {
2385 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2386 }
2387
2388 /**
2389 * @brief CS keeps invalid while not reading
2390 * @note This bit should not be changed when XIP is ongoing.
2391 *
2392 * Register |BitsName
2393 * -------------------|--------
2394 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_CS_IDLE_UNVLD_EN
2395 *
2396 * @param XQSPIx XQSPI instance
2397 * @retval None
2398 */
2399 __STATIC_FORCEINLINE void ll_xqspi_set_cs_idle_invalid(xqspi_regs_t *XQSPIx)
2400 {
2401 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2402 }
2403
2404 /**
2405 * @brief enable 1st prefecth function
2406 * @note This bit should not be changed when XIP is ongoing.
2407 *
2408 * Register |BitsName
2409 * -------------------|--------
2410 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_1ST_PRETETCH_DIS
2411 *
2412 * @param XQSPIx XQSPI instance
2413 * @retval None
2414 */
2415 __STATIC_FORCEINLINE void ll_xqspi_enable_1st_prefecth(xqspi_regs_t *XQSPIx)
2416 {
2417 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2418 }
2419
2420 /**
2421 * @brief disable 1st prefecth function
2422 * @note This bit should not be changed when XIP is ongoing.
2423 *
2424 * Register |BitsName
2425 * -------------------|--------
2426 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_1ST_PRETETCH_DIS
2427 *
2428 * @param XQSPIx XQSPI instance
2429 * @retval None
2430 */
2431 __STATIC_FORCEINLINE void ll_xqspi_disable_1st_prefecth(xqspi_regs_t *XQSPIx)
2432 {
2433 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2434 }
2435
2436 /**
2437 * @brief enable key_pulse to interrupt rd_data state
2438 * @note This bit should not be changed when XIP is ongoing.
2439 *
2440 * Register |BitsName
2441 * -------------------|--------
2442 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_KEY_PULSE_DIS
2443 *
2444 * @param XQSPIx XQSPI instance
2445 * @retval None
2446 */
2447 __STATIC_FORCEINLINE void ll_xqspi_enable_key_pulse(xqspi_regs_t *XQSPIx)
2448 {
2449 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2450 }
2451
2452 /**
2453 * @brief disable key_pulse to interrupt rd_data state
2454 * @note This bit should not be changed when XIP is ongoing.
2455 *
2456 * Register |BitsName
2457 * -------------------|--------
2458 * CS_IDLE_UNVLD_EN |XQSPI_QSPI_KEY_PULSE_DIS
2459 *
2460 * @param XQSPIx XQSPI instance
2461 * @retval None
2462 */
2463 __STATIC_FORCEINLINE void ll_xqspi_disable_key_pulse(xqspi_regs_t *XQSPIx)
2464 {
2465 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2466 }
2467
2468 /**
2469 * @brief Reset XQSPI, internal logic generates active low reset for one HCLK cycle.
2470 *
2471 * Register|BitsName
2472 * --------|--------
2473 * SOFT_RST | SOFT_RST_N
2474 *
2475 * @retval State of bit (1 or 0).
2476 */
2477 __STATIC_FORCEINLINE void ll_xqspi_reset(xqspi_regs_t *XQSPIx)
2478 {
2479 CLEAR_REG(XQSPIx->XIP.SOFT_RST);
2480 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
2481 }
2482
2483 /**
2484 * @brief Enable exflash power
2485 * @note This bit should not be changed when XIP is ongoing.
2486 *
2487 * Register|BitsName
2488 * --------|--------
2489 * PWR_RET01 | EFLASH_PAD_EN
2490 *
2491 * @retval None
2492 */
2493 __STATIC_FORCEINLINE void ll_xqspi_enable_exflash_power(void)
2494 {
2495 SET_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN);
2496 }
2497
2498 /**
2499 * @brief Disable exflash power
2500 * @note This bit should not be changed when XIP is ongoing.
2501 *
2502 * Register|BitsName
2503 * --------|--------
2504 * PWR_RET01 | EFLASH_PAD_EN
2505 *
2506 * @retval None
2507 */
2508 __STATIC_FORCEINLINE void ll_xqspi_disable_exflash_power(void)
2509 {
2510 CLEAR_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN);
2511 }
2512
2513 /**
2514 * @brief Check if exflash power is enabled
2515 *
2516 * Register|BitsName
2517 * --------|--------
2518 * PWR_RET01 | EFLASH_PAD_EN
2519 *
2520 * @retval State of bit (1 or 0).
2521 */
2522 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2523 {
2524 return (READ_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN) == (AON_CTL_FLASH_CACHE_PAD_EN));
2525 }
2526
2527 /**
2528 * @brief Set XQSPI serial clock
2529 *
2530 * Register|BitsName
2531 * --------|--------
2532 * PWR_RET01 | XF_SCK_CLK_SEL
2533 *
2534 * @param speed This parameter can be one of the following values:
2535 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2536 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2537 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2538 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2539 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2540 * @retval None
2541 */
2542 __STATIC_FORCEINLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2543 {
2544 MODIFY_REG(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL, speed);
2545 }
2546
2547 /**
2548 * @brief Get XQSPI serial clock
2549 *
2550 * Register|BitsName
2551 * --------|--------
2552 * PWR_RET01 | XF_SCK_CLK_SEL
2553 *
2554 * @retval Returned Value can be one of the following values:
2555 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2556 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2557 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2558 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2559 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2560 */
2561 __STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_speed(void)
2562 {
2563 return (uint32_t)(READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL));
2564 }
2565
2566 /**
2567 * @brief Enable cache data retention.
2568 * @note This bit should not be changed when XIP is ongoing..
2569 *
2570 * Register|BitsName
2571 * --------|--------
2572 * PWR_RET01 | XF_TAG_RET
2573 *
2574 * @retval None
2575 */
2576 __STATIC_FORCEINLINE void ll_xqspi_enable_cache_retention(void)
2577 {
2578 SET_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2579 }
2580
2581 /**
2582 * @brief Disable cache data retention.
2583 * @note This bit should not be changed when XIP is ongoing.
2584 *
2585 * Register|BitsName
2586 * --------|--------
2587 * PWR_RET01 | XF_TAG_RET
2588 *
2589 * @retval None
2590 */
2591 __STATIC_FORCEINLINE void ll_xqspi_disable_cache_retention(void)
2592 {
2593 CLEAR_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2594 }
2595
2596 /**
2597 * @brief Check if tag memory retention is enabled
2598 *
2599 * Register|BitsName
2600 * --------|--------
2601 * PWR_RET01 | XF_TAG_RET
2602 *
2603 * @retval State of bit (1 or 0).
2604 */
2605 __STATIC_FORCEINLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2606 {
2607 return (READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET) == (AON_CTL_FLASH_CACHE_XF_TAG_RET));
2608 }
2609
2610 /** @} */
2611
2612 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2613 * @{
2614 */
2615
2616 /**
2617 * @brief De-initialize XQSPI registers (Registers restored to their default values).
2618 * @param XQSPIx XQSPI instance
2619 * @retval An error_status_t enumeration value:
2620 * - SUCCESS: XQSPI registers are de-initialized
2621 * - ERROR: XQSPI registers are not de-initialized
2622 */
2623 SECTION_RAM_CODE error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2624
2625 /**
2626 * @brief Initialize XQSPI registers according to the specified
2627 * parameters in default.
2628 * @param XQSPIx XQSPI instance
2629 * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2630 * information for the specified XQPSI peripheral.
2631 * @retval An error_status_t enumeration value:
2632 * - SUCCESS: XQSPI registers are initialized according to default
2633 * - ERROR: Problem occurred during XQSPI Registers initialization
2634 */
2635 SECTION_RAM_CODE error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2636
2637 /**
2638 * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2639 * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2640 * whose fields will be set to default values.
2641 * @retval None
2642 */
2643 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2644
2645 /** @} */
2646
2647 /** @} */
2648
2649 #endif /* XQSPI */
2650
2651 #ifdef __cplusplus
2652 }
2653 #endif
2654
2655 #endif /* __GR55xx_LL_XQSPI_H__ */
2656
2657 /** @} */
2658
2659 /** @} */
2660
2661 /** @} */
ll_xqspi_qspi_transmit_data16
__STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1343
ll_xqspi_qspi_transmit_data8
__STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1327
ll_xqspi_get_xip_dummy_hp
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1163
ll_xqspi_set_cache_dbgbus
__STATIC_FORCEINLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:663
ll_xqspi_enable_xip_it
__STATIC_FORCEINLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr55xx_ll_xqspi.h:1289
ll_xqspi_get_qspi_wait
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2250
ll_xqspi_get_flag_xip_it
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr55xx_ll_xqspi.h:1257
ll_xqspi_disable_qspi_contxfer_extend
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1758
ll_xqspi_is_enabled_qspi_it
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:2152
ll_xqspi_disable_cache_flush
__STATIC_FORCEINLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr55xx_ll_xqspi.h:542
_ll_xqspi_hp_init_t::xqspi_hp_cmd
uint8_t xqspi_hp_cmd
Specifies the command to enter HP mode for XQSPI.
Definition: gr55xx_ll_xqspi.h:81
ll_xqspi_is_enabled_cache
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr55xx_ll_xqspi.h:461
ll_xqspi_enable_qspi_contxfer
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1698
ll_xqspi_enable_qspi_ssout
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr55xx_ll_xqspi.h:2010
ll_xqspi_qspi_receive_data16
__STATIC_FORCEINLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1389
ll_xqspi_get_xip_addr_size
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr55xx_ll_xqspi.h:1023
ll_xqspi_is_enabled_qspi_contxfer
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr55xx_ll_xqspi.h:1728
ll_xqspi_disable_exflash_power
__STATIC_FORCEINLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr55xx_ll_xqspi.h:2508
ll_xqspi_is_enabled_xip_it
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:1241
ll_xqspi_get_req_xip_it
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr55xx_ll_xqspi.h:1273
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_xqspi.h:115
ll_xqspi_set_present_bypass
__STATIC_FORCEINLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
Set QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2350
ll_xqspi_disable_xip_it
__STATIC_FORCEINLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr55xx_ll_xqspi.h:1305
ll_xqspi_disable_cache_dbgmux
__STATIC_FORCEINLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr55xx_ll_xqspi.h:710
ll_xqspi_set_qspi_frf
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr55xx_ll_xqspi.h:1931
ll_xqspi_enable_cache_dbgmux
__STATIC_FORCEINLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr55xx_ll_xqspi.h:694
ll_xqspi_get_qspi_sspol
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr55xx_ll_xqspi.h:2057
ll_xqspi_get_qspi_tx_fifo_level
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_xqspi.h:2072
ll_xqspi_get_xip_dummycycles
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1132
ll_xqspi_set_xip_cmd
__STATIC_FORCEINLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr55xx_ll_xqspi.h:802
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate be used to configure the transmit and receive SCK clock.
Definition: gr55xx_ll_xqspi.h:125
ll_xqspi_get_xip_flag
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr55xx_ll_xqspi.h:1225
ll_xqspi_enable_qspi_dummy
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1501
ll_xqspi_set_xip_hp_cmd
__STATIC_FORCEINLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr55xx_ll_xqspi.h:1077
ll_xqspi_reset
__STATIC_FORCEINLINE void ll_xqspi_reset(xqspi_regs_t *XQSPIx)
Reset XQSPI, internal logic generates active low reset for one HCLK cycle.
Definition: gr55xx_ll_xqspi.h:2477
ll_xqspi_get_flash_write
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2331
ll_xqspi_cache_direct_map_disable
__STATIC_FORCEINLINE void ll_xqspi_cache_direct_map_disable(xqspi_regs_t *XQSPIx)
Disable cache direct map function.
Definition: gr55xx_ll_xqspi.h:494
ll_xqspi_get_xip_cpol
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:987
ll_xqspi_disable_inhibt_tx
__STATIC_FORCEINLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1896
ll_xqspi_get_qspi_datasize
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr55xx_ll_xqspi.h:1821
ll_xqspi_set_xip_cpol
__STATIC_FORCEINLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:970
ll_xqspi_set_cache_fifo
__STATIC_FORCEINLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr55xx_ll_xqspi.h:591
ll_xqspi_qspi_transmit_data32
__STATIC_FORCEINLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1359
ll_xqspi_enable_inhibt_tx
__STATIC_FORCEINLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1881
ll_xqspi_set_qspi_cpha
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:1631
ll_xqspi_enable_xip
__STATIC_FORCEINLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr55xx_ll_xqspi.h:1178
ll_xqspi_get_xip_endian
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr55xx_ll_xqspi.h:1059
ll_xqspi_set_xip_dummycycles
__STATIC_FORCEINLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1113
_ll_xqspi_init_t::data_order
uint32_t data_order
Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:110
ll_xqspi_disable_qspi_ssout
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr55xx_ll_xqspi.h:2026
ll_xqspi_enable_qspi
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr55xx_ll_xqspi.h:2266
ll_xqspi_get_qspi_frf
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr55xx_ll_xqspi.h:1949
ll_xqspi_get_xip_ss
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr55xx_ll_xqspi.h:915
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Specifies the cache mode in XIP mode.
Definition: gr55xx_ll_xqspi.h:95
ll_xqspi_set_qspi_cpol
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:1595
ll_xqspi_get_cache_dbgbus
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:678
ll_xqspi_set_qspi_sspol
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr55xx_ll_xqspi.h:2042
ll_xqspi_disable_1st_prefecth
__STATIC_FORCEINLINE void ll_xqspi_disable_1st_prefecth(xqspi_regs_t *XQSPIx)
disable 1st prefecth function
Definition: gr55xx_ll_xqspi.h:2431
ll_xqspi_get_qspi_data_order
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr55xx_ll_xqspi.h:1683
ll_xqspi_is_enabled_xip_hp
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr55xx_ll_xqspi.h:875
_ll_xqspi_hp_init_t
XQSPI High Performance mode init structures definition.
Definition: gr55xx_ll_xqspi.h:77
ll_xqspi_hp_init_t
struct _ll_xqspi_hp_init_t ll_xqspi_hp_init_t
XQSPI High Performance mode init structures definition.
ll_xqspi_disable_qspi_dummy
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1516
ll_xqspi_is_enabled_cache_flush
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr55xx_ll_xqspi.h:557
ll_xqspi_get_qspi_tft
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1445
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_cache_direct_map_enable
__STATIC_FORCEINLINE void ll_xqspi_cache_direct_map_enable(xqspi_regs_t *XQSPIx)
Enable cache direct map function.
Definition: gr55xx_ll_xqspi.h:477
ll_xqspi_set_qspi_wait
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2235
ll_xqspi_enable_exflash_power
__STATIC_FORCEINLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr55xx_ll_xqspi.h:2493
ll_xqspi_enable_cache
__STATIC_FORCEINLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr55xx_ll_xqspi.h:428
ll_xqspi_enable_inhibt_rx
__STATIC_FORCEINLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1836
ll_xqspi_get_xip_cmd
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr55xx_ll_xqspi.h:823
ll_xqspi_enable_cache_flush
__STATIC_FORCEINLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr55xx_ll_xqspi.h:526
ll_xqspi_is_enable_cache_retention
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr55xx_ll_xqspi.h:2605
ll_xqspi_is_enabled_qspi_contxfer_extend
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr55xx_ll_xqspi.h:1773
ll_xqspi_get_qspi_rx_fifo_level
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_xqspi.h:2087
ll_xqspi_is_enabled_cache_dbgmux
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr55xx_ll_xqspi.h:725
ll_xqspi_get_cache_flag
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr55xx_ll_xqspi.h:773
ll_xqspi_soft_rst_req
__STATIC_FORCEINLINE void ll_xqspi_soft_rst_req(xqspi_regs_t *XQSPIx)
Definition: gr55xx_ll_xqspi.h:844
ll_xqspi_get_present_bypass
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
Get QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2367
ll_xqspi_disable_qspi_it
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_xqspi.h:2131
_ll_xqspi_init_t::cache_direct_map_en
uint32_t cache_direct_map_en
Specifies the XQSPI Cache work on direct map or 4-way set associative.
Definition: gr55xx_ll_xqspi.h:130
ll_xqspi_disable_inhibt_rx
__STATIC_FORCEINLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1851
ll_xqspi_set_flash_write
__STATIC_FORCEINLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2314
ll_xqspi_enable_cache_retention
__STATIC_FORCEINLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr55xx_ll_xqspi.h:2576
ll_xqspi_qspi_receive_data8
__STATIC_FORCEINLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1374
ll_xqspi_is_enabled_xip
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr55xx_ll_xqspi.h:1209
ll_xqspi_set_cache_clk_force_en
__STATIC_FORCEINLINE void ll_xqspi_set_cache_clk_force_en(xqspi_regs_t *XQSPIx)
Set cache gating dynamically.
Definition: gr55xx_ll_xqspi.h:572
ll_xqspi_init
SECTION_RAM_CODE error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_set_xip_addr_size
__STATIC_FORCEINLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr55xx_ll_xqspi.h:1006
ll_xqspi_get_qspi_rft
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1486
ll_xqspi_get_qspi_status
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr55xx_ll_xqspi.h:1971
ll_xqspi_is_enabled_qspi_dma
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr55xx_ll_xqspi.h:1576
ll_xqspi_disable_xip
__STATIC_FORCEINLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr55xx_ll_xqspi.h:1193
ll_xqspi_disable_qspi
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr55xx_ll_xqspi.h:2281
ll_xqspi_is_enabled_inhibt_rx
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1866
ll_xqspi_enable_1st_prefecth
__STATIC_FORCEINLINE void ll_xqspi_enable_1st_prefecth(xqspi_regs_t *XQSPIx)
enable 1st prefecth function
Definition: gr55xx_ll_xqspi.h:2415
ll_xqspi_set_cache_hitmiss
__STATIC_FORCEINLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:628
ll_xqspi_get_cache_misscount
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr55xx_ll_xqspi.h:757
ll_xqspi_set_xip_endian
__STATIC_FORCEINLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr55xx_ll_xqspi.h:1042
ll_xqspi_disable_cache
__STATIC_FORCEINLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr55xx_ll_xqspi.h:445
ll_xqspi_enable_qspi_dma
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr55xx_ll_xqspi.h:1546
_ll_xqspi_init_t::mode
uint32_t mode
Specifies the work mode, XIP mode or QSPI mode.
Definition: gr55xx_ll_xqspi.h:92
ll_xqspi_set_qspi_tft
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1425
ll_xqspi_set_xip_ss
__STATIC_FORCEINLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr55xx_ll_xqspi.h:896
_ll_xqspi_hp_init_t::xqspi_hp_enable
uint8_t xqspi_hp_enable
Specifies If enable the HP mode for XQSPI.
Definition: gr55xx_ll_xqspi.h:78
ll_xqspi_get_cache_hitcount
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr55xx_ll_xqspi.h:741
ll_xqspi_get_qspi_speed
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2561
ll_xqspi_disable_xip_hp
__STATIC_FORCEINLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr55xx_ll_xqspi.h:860
ll_xqspi_disable_qspi_contxfer
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1713
ll_xqspi_get_xip_cpha
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:951
ll_xqspi_is_enabled_inhibt_tx
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1911
ll_xqspi_set_cs_idle_invalid
__STATIC_FORCEINLINE void ll_xqspi_set_cs_idle_invalid(xqspi_regs_t *XQSPIx)
CS keeps invalid while not reading.
Definition: gr55xx_ll_xqspi.h:2399
ll_xqspi_qspi_receive_data32
__STATIC_FORCEINLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1404
ll_xqspi_set_qspi_rft
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1466
ll_xqspi_enable_key_pulse
__STATIC_FORCEINLINE void ll_xqspi_enable_key_pulse(xqspi_regs_t *XQSPIx)
enable key_pulse to interrupt rd_data state
Definition: gr55xx_ll_xqspi.h:2447
ll_xqspi_set_xip_dummy_hp
__STATIC_FORCEINLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1148
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr55xx_ll_xqspi.h:91
ll_xqspi_disable_key_pulse
__STATIC_FORCEINLINE void ll_xqspi_disable_key_pulse(xqspi_regs_t *XQSPIx)
disable key_pulse to interrupt rd_data state
Definition: gr55xx_ll_xqspi.h:2463
ll_xqspi_set_cs_idle_valid
__STATIC_FORCEINLINE void ll_xqspi_set_cs_idle_valid(xqspi_regs_t *XQSPIx)
CS keeps valid while not reading.
Definition: gr55xx_ll_xqspi.h:2383
ll_xqspi_set_qspi_datasize
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr55xx_ll_xqspi.h:1798
_ll_xqspi_init_t::cache_flush
uint32_t cache_flush
Specifies the XQSPI Cache will be flushed or not.
Definition: gr55xx_ll_xqspi.h:133
ll_xqspi_enable_qspi_it
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_xqspi.h:2109
ll_xqspi_enable_xip_hp
__STATIC_FORCEINLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr55xx_ll_xqspi.h:839
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_xqspi.h:120
ll_xqspi_cache_direct_map_is_enabled
__STATIC_FORCEINLINE uint32_t ll_xqspi_cache_direct_map_is_enabled(xqspi_regs_t *XQSPIx)
Check if cache direct map function is enabled.
Definition: gr55xx_ll_xqspi.h:510
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Specifies the XQSPI read command in XIP mode.
Definition: gr55xx_ll_xqspi.h:100
ll_xqspi_set_xip_cpha
__STATIC_FORCEINLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:934
ll_xqspi_get_cache_fifo
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr55xx_ll_xqspi.h:609
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_enable_qspi_contxfer_extend
__STATIC_FORCEINLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1743
ll_xqspi_set_qspi_speed
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2542
ll_xqspi_clear_qspi_flag
__STATIC_FORCEINLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr55xx_ll_xqspi.h:2219
ll_xqspi_disable_qspi_dma
__STATIC_FORCEINLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr55xx_ll_xqspi.h:1561
ll_xqspi_get_qspi_cpol
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:1612
ll_xqspi_set_qspi_data_order
__STATIC_FORCEINLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr55xx_ll_xqspi.h:1666
ll_xqspi_is_qspi_it_flag
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_xqspi.h:2197
ll_xqspi_get_xip_hp_cmd
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr55xx_ll_xqspi.h:1092
ll_xqspi_get_qspi_cpha
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:1648
ll_xqspi_is_enabled_qspi
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr55xx_ll_xqspi.h:2296
_ll_xqspi_hp_init_t::xqspi_hp_end_dummy
uint8_t xqspi_hp_end_dummy
Specifies the end dummpy cycle in HP mode for XQSPI.
Definition: gr55xx_ll_xqspi.h:83
ll_xqspi_is_active_qspi_flag
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_xqspi.h:1994
ll_xqspi_deinit
SECTION_RAM_CODE error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_is_enable_exflash_power
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr55xx_ll_xqspi.h:2522
ll_xqspi_get_it_flag
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr55xx_ll_xqspi.h:2172
_ll_xqspi_init_t::data_size
uint32_t data_size
Specifies the XQSPI data width, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:105
ll_xqspi_get_cache_hitmiss
__STATIC_FORCEINLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:646
ll_xqspi_is_enabled_qspi_dummy
__STATIC_FORCEINLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr55xx_ll_xqspi.h:1531
ll_xqspi_disable_cache_retention
__STATIC_FORCEINLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr55xx_ll_xqspi.h:2591
_ll_xqspi_init_t::hp_init
ll_xqspi_hp_init_t hp_init
Specifies the XQSPI HP mode Configuration.
Definition: gr55xx_ll_xqspi.h:136