gr55xx_ll_clk.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_clk.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CLOCK LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_CLK CLK
47 * @brief CLOCK CALIBRATION LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CLK_H_
53 #define __GR55XX_LL_CLK_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61
62 /**
63 * @defgroup LL_CLK_MACRO Defines
64 * @{
65 */
66
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup LL_CLK_Exported_Constants CLK Exported Constants
69 * @{
70 */
71
72 /** @defgroup CLK_SOURCE Clock source select
73 * @{
74 */
75
76 #define LL_CLK_SEL_SOURCE_CPLL_CLK (0UL) /**< Select CPLL clk as the source of the 192MHz clock */
77 #define LL_CLK_SEL_SOURCE_HF_OSC_CLK (1UL) /**< Select hf osc clk as the source of the 192MHz clock */
78 #define LL_CLK_SEL_FAST_WAKEUP_CPLL_CLK (0UL) /**< Select CPLL clk as fast wakeup clk */
79 #define LL_CLK_SEL_FAST_WAKEUP_HF_OSC_CLK (AON_CTL_AON_CLK_WAKUP_FAST_CLK_SEL_Msk) /**< Select hf osc clk as fast wakeup clk */
80
81 /** @} */
82
83 /** @defgroup CLK_SELECT System clock frequency select
84 * @{
85 */
86 #define LL_CLK_CPLL_S96M_CLK AON_CTL_MCU_CLK_CTRL_SEL_96M /**< Select PLL/HF_OSC 96MHz clk as system clock */
87 #define LL_CLK_CPLL_S64M_CLK AON_CTL_MCU_CLK_CTRL_SEL_64M /**< Select PLL/HF_OSC 64MHz clk as system clock */
88 #define LL_CLK_XO_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_XO_16M /**< Select XO 16MHz clk as system clock */
89 #define LL_CLK_CPLL_F48M_CLK AON_CTL_MCU_CLK_CTRL_SEL_48M /**< Select PLL/HF_OSC 48MHz clk as system clock */
90 #define LL_CLK_CPLL_T24M_CLK AON_CTL_MCU_CLK_CTRL_SEL_24M /**< Select PLL/HF_OSC 24MHz clk as system clock */
91 #define LL_CLK_CPLL_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_16M /**< Select PLL/HF_OSC 16MHz clk as system clock */
92 #define LL_CLK_CPLL_T32M_CLK AON_CTL_MCU_CLK_CTRL_SEL_32M /**< Select PLL/HF_OSC 32MHz clk as system clock */
93
94 #define LL_CLK_AON_CLK_WAKUP_CLK_EN (1 << AON_CTL_AON_CLK_WAKUP_CLK_EN_Pos) /**< wakeup clock enable */
95 #define LL_CLK_AON_CLK_WAKUP_CLK_DIS 0 /**< wakeup clock disable */
96 /** @} */
97
98 /** @defgroup XO_PLL_STATE XO PLL state
99 * @{
100 */
101 #define LL_CLK_XO_PLL_PLL_STAT (1UL) /**< XO PLL state, PLL */
102 #define LL_CLK_XO_PLL_XO_STAT (2UL) /**< XO PLL state, XO */
103 #define LL_CLK_XO_PLL_HF_STAT (4UL) /**< XO PLL state, HF */
104 /** @} */
105
106 /** @} */
107 /** @} */
108
109 /** @defgroup LL_CLK_DRIVER_FUNCTIONS Functions
110 * @{
111 */
112
113 /**
114 * @brief Get system clock.
115 *
116 * Register|BitsName
117 * --------|--------
118 * MCU_CLK_CTRL | CLK_CTRL_SEL
119 *
120 * @retval None
121 *
122 */
123 __STATIC_INLINE uint32_t ll_clk_get_sys_clk(void)
124 {
125 return READ_BITS(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL);
126 }
127
128 /**
129 * @brief Set system clock.
130 *
131 * Register|BitsName
132 * --------|--------
133 * MCU_CLK_CTRL | CLK_CTRL_SEL
134 *
135 * @param clk_sel This parameter can be a combination of the following values:
136 * @arg @ref LL_CLK_CPLL_S96M_CLK
137 * @arg @ref LL_CLK_CPLL_S64M_CLK
138 * @arg @ref LL_CLK_XO_S16M_CLK
139 * @arg @ref LL_CLK_CPLL_F48M_CLK
140 * @arg @ref LL_CLK_CPLL_T24M_CLK
141 * @arg @ref LL_CLK_CPLL_S16M_CLK
142 * @arg @ref LL_CLK_CPLL_T32M_CLK
143 *
144 */
145 __STATIC_INLINE void ll_clk_set_sys_clk(uint32_t clk_sel)
146 {
147 // Need twice writing to ensure success for this register
148 MODIFY_REG(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL, clk_sel);
149 MODIFY_REG(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL, clk_sel);
150 }
151
152 /**
153 * @brief set AON_CTL_AON_CLK_WAKUP_CLK_EN bit
154 *
155 * Register|BitsName
156 * --------|--------
157 * AON_CLK | AON_CTL_AON_CLK_WAKUP_CLK_EN
158 *
159 * @param wakeup_clk_en This parameter can be a combination of the following values:
160 * @arg @ref LL_CLK_AON_CLK_WAKUP_CLK_EN
161 * @arg @ref LL_CLK_AON_CLK_WAKUP_CLK_DIS
162 *
163 */
164 __STATIC_INLINE void ll_clk_set_aon_clk_wakeup_clk_en(uint32_t wakeup_clk_en)
165 {
166 MODIFY_REG(AON_CTL->AON_CLK, AON_CTL_AON_CLK_WAKUP_CLK_EN, wakeup_clk_en);
167 }
168 /**
169 * @brief Select clock source.
170 *
171 * Register|BitsName
172 * --------|--------
173 * AON_CLK | CAL_FST_CLK
174 *
175 * @param src_sel This parameter can be a combination of the following values:
176 * @arg @ref LL_CLK_SEL_SOURCE_CPLL_CLK
177 * @arg @ref LL_CLK_SEL_SOURCE_HF_OSC_CLK
178 *
179 */
180 __STATIC_INLINE void ll_clk_select_source(uint32_t src_sel)
181 {
182 // Need twice writing to ensure success for this register
183 MODIFY_REG(AON_CTL->AON_CLK, AON_CTL_AON_CLK_CAL_FST_CLK, src_sel);
184 MODIFY_REG(AON_CTL->AON_CLK, AON_CTL_AON_CLK_CAL_FST_CLK, src_sel);
185 }
186 /**
187 * @brief Select clock source.
188 *
189 * Register|BitsName
190 * --------|--------
191 * AON_CLK | WAKUP_FAST_CLK_SEL
192 *
193 * @param src_sel This parameter can be a combination of the following values:
194 * @arg @ref LL_CLK_SEL_SOURCE_CPLL_CLK
195 * @arg @ref LL_CLK_SEL_SOURCE_HF_OSC_CLK
196 *
197 */
198 __STATIC_INLINE void ll_clk_select_fast_wakeup_source(uint32_t src_sel)
199 {
200 MODIFY_REG(AON_CTL->AON_CLK, AON_CTL_AON_CLK_WAKUP_FAST_CLK_SEL, src_sel);
201 }
202
203 /**
204 * @brief start XO and PLL
205 *
206 * Register|BitsName
207 * --------|--------
208 * AON_PWR | XO_PLL_SET
209 *
210 * @retval void.
211 *
212 */
213 __STATIC_INLINE void ll_clk_start_xo_pll(void)
214 {
215 MODIFY_REG(AON_PWR->XO_PLL_SET, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
216 }
217
218 /**
219 * @brief stop XO and PLL
220 *
221 * Register|BitsName
222 * --------|--------
223 * AON_PWR | XO_PLL_CLR
224 *
225 * @retval void.
226 *
227 */
228 __STATIC_INLINE void ll_clk_stop_xo_pll(void)
229 {
230 MODIFY_REG(AON_PWR->XO_PLL_CLR, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
231 }
232
233 /**
234 * @brief Get XO PLL status.
235 *
236 * Register|BitsName
237 * --------|--------
238 * AON_PWR | XO_PLL_STAT
239 *
240 * @retval xo pll status value.
241 *
242 */
243 __STATIC_INLINE uint32_t ll_clk_get_hf_status(void)
244 {
245 return READ_BITS(AON_PWR->XO_PLL_STAT, AON_PWR_XO_PLL_STAT_PLL_STAT |
246 AON_PWR_XO_PLL_STAT_XO_STAT |
247 AON_PWR_XO_PLL_STAT_HF_STAT);
248 }
249
250 /** @} */
251
252 #ifdef __cplusplus
253 }
254 #endif
255
256 #endif
257
258 /** @} */
259
260 /** @} */
261
262 /** @} */
ll_clk_set_sys_clk
__STATIC_INLINE void ll_clk_set_sys_clk(uint32_t clk_sel)
Set system clock.
Definition: gr55xx_ll_clk.h:145
ll_clk_start_xo_pll
__STATIC_INLINE void ll_clk_start_xo_pll(void)
start XO and PLL
Definition: gr55xx_ll_clk.h:213
ll_clk_get_sys_clk
__STATIC_INLINE uint32_t ll_clk_get_sys_clk(void)
Get system clock.
Definition: gr55xx_ll_clk.h:123
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_clk_select_fast_wakeup_source
__STATIC_INLINE void ll_clk_select_fast_wakeup_source(uint32_t src_sel)
Select clock source.
Definition: gr55xx_ll_clk.h:198
ll_clk_stop_xo_pll
__STATIC_INLINE void ll_clk_stop_xo_pll(void)
stop XO and PLL
Definition: gr55xx_ll_clk.h:228
ll_clk_select_source
__STATIC_INLINE void ll_clk_select_source(uint32_t src_sel)
Select clock source.
Definition: gr55xx_ll_clk.h:180
ll_clk_get_hf_status
__STATIC_INLINE uint32_t ll_clk_get_hf_status(void)
Get XO PLL status.
Definition: gr55xx_ll_clk.h:243
ll_clk_set_aon_clk_wakeup_clk_en
__STATIC_INLINE void ll_clk_set_aon_clk_wakeup_clk_en(uint32_t wakeup_clk_en)
set AON_CTL_AON_CLK_WAKUP_CLK_EN bit
Definition: gr55xx_ll_clk.h:164