gr55xx_hal_gpio_ex.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_gpio_ex.h
5 * @author BLE Driver Team
6 * @brief Header file containing extended macro of GPIO HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_GPIOEx GPIOEx
47 * @brief GPIOEx HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_GPIO_EX_H__
53 #define __GR55xx_HAL_GPIO_EX_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal_def.h"
61 #include "gr55xx_ll_gpio.h"
62
63 /* Exported types ------------------------------------------------------------*/
64
65 /**
66 * @defgroup HAL_GPIOEX_MACRO Defines
67 * @{
68 */
69
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
72 * @{
73 */
74
75 /** @defgroup GPIOEx_Mux_Mode GPIOEx Mux Mode definition
76 * @{
77 */
78 #define GPIO_MUX_0 LL_GPIO_MUX_0 /**< GPIO Mux mode 0 */
79 #define GPIO_MUX_1 LL_GPIO_MUX_1 /**< GPIO Mux mode 1 */
80 #define GPIO_MUX_2 LL_GPIO_MUX_2 /**< GPIO Mux mode 2 */
81 #define GPIO_MUX_3 LL_GPIO_MUX_3 /**< GPIO Mux mode 3 */
82 #define GPIO_MUX_4 LL_GPIO_MUX_4 /**< GPIO Mux mode 4 */
83 #define GPIO_MUX_5 LL_GPIO_MUX_5 /**< GPIO Mux mode 5 */
84 #define GPIO_MUX_6 LL_GPIO_MUX_6 /**< GPIO Mux mode 6 */
85 #define GPIO_MUX_7 LL_GPIO_MUX_7 /**< GPIO Mux mode 7 */
86 #define GPIO_MUX_8 LL_GPIO_MUX_8 /**< GPIO Mux mode 8 */
87 /** @} */
88
89 /** @defgroup GPIOEx_Mux_Function_Selection GPIOEx Mux function selection
90 * @{
91 */
92
93
94 #if defined (GR552xx)
95 /*---------------------------------- GR552xx ------------------------------*/
96
97 /** @defgroup GPIOEx_Common_Selection GPIO PIN common MUX selection(Available for all GPIO pins)
98 * @{
99 */
100 #define GPIO_PIN_MUX_TESTBUS GPIO_MUX_8 /**< GPIO PIN x Mux Select TESTBUS */
101
102 #define GPIO_PIN_MUX_GPIO GPIO_MUX_7 /**< GPIO PIN x Mux Select GPIO */
103
104 /** @} */
105
106 /** @defgroup GPIOEx_GPIO0_PIN0_Mux_Selection GPIO0_PIN0 MUX selection
107 * @{
108 */
109 #define GPIO0_PIN0_MUX_SWD_CLK GPIO_MUX_0 /**< GPIO0_PIN0 Mux Select SWD_CLK */
110 #define GPIO0_PIN0_MUX_I2C1_SCL GPIO_MUX_1 /**< GPIO0_PIN0 Mux Select I2C1_SCL */
111 #define GPIO0_PIN0_MUX_UART0_TX GPIO_MUX_2 /**< GPIO0_PIN0 Mux Select UART0_TX */
112 #define GPIO0_PIN0_MUX_UART1_CTS GPIO_MUX_3 /**< GPIO0_PIN0 Mux Select UART1_CTS */
113 #define GPIO0_PIN0_MUX_PWM1_C GPIO_MUX_4 /**< GPIO0_PIN0 Mux Select PWM1_C */
114 #define GPIO0_PIN0_MUX_PWM0_C GPIO_MUX_5 /**< GPIO0_PIN0 Mux Select PWM0_C */
115 #define GPIO0_PIN0_MUX_PDM_CLKO GPIO_MUX_6 /**< GPIO0_PIN0 Mux Select PDM_CLKO */
116 /** @} */
117
118 /** @defgroup GPIOEx_GPIO0_PIN1_Mux_Selection GPIO0_PIN1 MUX selection
119 * @{
120 */
121 #define GPIO0_PIN1_MUX_SWD_IO GPIO_MUX_0 /**< GPIO0_PIN1 Mux Select SWD_IO */
122 #define GPIO0_PIN1_MUX_I2C1_SDA GPIO_MUX_1 /**< GPIO0_PIN1 Mux Select I2C1_SDA */
123 #define GPIO0_PIN1_MUX_UART0_RX GPIO_MUX_2 /**< GPIO0_PIN1 Mux Select UART0_RX */
124 #define GPIO0_PIN1_MUX_UART1_RTS GPIO_MUX_3 /**< GPIO0_PIN1 Mux Select UART1_RTS */
125 #define GPIO0_PIN1_MUX_PWM1_B GPIO_MUX_4 /**< GPIO0_PIN1 Mux Select PWM1_B */
126 #define GPIO0_PIN1_MUX_PWM0_B GPIO_MUX_5 /**< GPIO0_PIN1 Mux Select PWM0_B */
127 #define GPIO0_PIN1_MUX_PDM_DI GPIO_MUX_6 /**< GPIO0_PIN1 Mux Select PDM_DI */
128 /** @} */
129
130 /** @defgroup GPIOEx_GPIO0_PIN2_Mux_Selection GPIO0_PIN2 MUX selection
131 * @{
132 */
133 #define GPIO0_PIN2_MUX_I2C0_SCL GPIO_MUX_0 /**< GPIO0_PIN2 Mux Select I2C0_SCL */
134 #define GPIO0_PIN2_MUX_PDM_CLKO GPIO_MUX_1 /**< GPIO0_PIN2 Mux Select PDM_CLKO */
135 #define GPIO0_PIN2_MUX_UART0_CTS GPIO_MUX_2 /**< GPIO0_PIN2 Mux Select UART0_CTS */
136 #define GPIO0_PIN2_MUX_UART1_TX GPIO_MUX_3 /**< GPIO0_PIN2 Mux Select UART1_TX */
137 #define GPIO0_PIN2_MUX_PWM1_A GPIO_MUX_4 /**< GPIO0_PIN2 Mux Select PWM1_A */
138 #define GPIO0_PIN2_MUX_PWM0_A GPIO_MUX_5 /**< GPIO0_PIN2 Mux Select PWM0_A */
139 #define GPIO0_PIN2_MUX_ISO_SYNC1_P GPIO_MUX_6 /**< GPIO0_PIN2 Mux Select ISO_SYNC1_P */
140 /** @} */
141
142 /** @defgroup GPIOEx_GPIO0_PIN3_Mux_Selection GPIO0_PIN3 MUX selection
143 * @{
144 */
145 #define GPIO0_PIN3_MUX_I2C0_SDA GPIO_MUX_0 /**< GPIO0_PIN3 Mux Select I2C0_SDA */
146 #define GPIO0_PIN3_MUX_PDM_DI GPIO_MUX_1 /**< GPIO0_PIN3 Mux Select PDM_DI */
147 #define GPIO0_PIN3_MUX_UART0_RTS GPIO_MUX_2 /**< GPIO0_PIN3 Mux Select UART0_RTS */
148 #define GPIO0_PIN3_MUX_UART1_RX GPIO_MUX_3 /**< GPIO0_PIN3 Mux Select UART1_RX */
149 #define GPIO0_PIN3_MUX_FERP_GPIO_TRIG GPIO_MUX_4 /**< GPIO0_PIN3 Mux Select FERP_GPIO_TRIG */
150 #define GPIO0_PIN3_MUX_SWO GPIO_MUX_5 /**< GPIO0_PIN3 Mux Select SWO */
151 #define GPIO0_PIN3_MUX_ISO_SYNC0_P GPIO_MUX_6 /**< GPIO0_PIN3 Mux Select ISO_SYNC0_P */
152 /** @} */
153
154 /** @defgroup GPIOEx_GPIO0_PIN4_Mux_Selection GPIO0_PIN4 MUX selection
155 * @{
156 */
157 #define GPIO0_PIN4_MUX_I2C4_SCL GPIO_MUX_0 /**< GPIO0_PIN4 Mux Select I2C4_SCL */
158 #define GPIO0_PIN4_MUX_SPI_M_CLK GPIO_MUX_1 /**< GPIO0_PIN4 Mux Select SPI_M_CLK */
159 #define GPIO0_PIN4_MUX_PWM0_A GPIO_MUX_2 /**< GPIO0_PIN4 Mux Select PWM0_A */
160 #define GPIO0_PIN4_MUX_UART3_TX GPIO_MUX_3 /**< GPIO0_PIN4 Mux Select UART3_TX */
161 #define GPIO0_PIN4_MUX_PDM_CLKO GPIO_MUX_4 /**< GPIO0_PIN4 Mux Select PDM_CLKO */
162 #define GPIO0_PIN4_MUX_DF_ANT_SWITCH_SEL_0 GPIO_MUX_5 /**< GPIO0_PIN4 Mux Select DF_ANT_SWITCH_SEL_0 */
163 #define GPIO0_PIN4_MUX_UART2_CTS GPIO_MUX_6 /**< GPIO0_PIN4 Mux Select UART2_CTS */
164 /** @} */
165
166 /** @defgroup GPIOEx_GPIO0_PIN5_Mux_Selection GPIO0_PIN5 MUX selection
167 * @{
168 */
169 #define GPIO0_PIN5_MUX_I2C4_SDA GPIO_MUX_0 /**< GPIO0_PIN5 Mux Select I2C4_SDA */
170 #define GPIO0_PIN5_MUX_SPI_M_MOSI GPIO_MUX_1 /**< GPIO0_PIN5 Mux Select SPI_M_MOSI */
171 #define GPIO0_PIN5_MUX_PWM0_B GPIO_MUX_2 /**< GPIO0_PIN5 Mux Select PWM0_B */
172 #define GPIO0_PIN5_MUX_UART3_RX GPIO_MUX_3 /**< GPIO0_PIN5 Mux Select UART3_RX */
173 #define GPIO0_PIN5_MUX_PDM_DI GPIO_MUX_4 /**< GPIO0_PIN5 Mux Select PDM_DI */
174 #define GPIO0_PIN5_MUX_DF_ANT_SWITCH_SEL_1 GPIO_MUX_5 /**< GPIO0_PIN5 Mux Select DF_ANT_SWITCH_SEL_1 */
175 #define GPIO0_PIN5_MUX_UART2_RTS GPIO_MUX_6 /**< GPIO0_PIN5 Mux Select UART2_RTS */
176
177 /** @} */
178
179 /** @defgroup GPIOEx_GPIO0_PIN6_Mux_Selection GPIO0_PIN6 MUX selection
180 * @{
181 */
182 #define GPIO0_PIN6_MUX_I2C3_SCL GPIO_MUX_0 /**< GPIO0_PIN6 Mux Select I2C3_SCL */
183 #define GPIO0_PIN6_MUX_SPI_M_MISO GPIO_MUX_1 /**< GPIO0_PIN6 Mux Select SPI_M_MISO */
184 #define GPIO0_PIN6_MUX_PWM0_C GPIO_MUX_2 /**< GPIO0_PIN6 Mux Select PWM0_C */
185 #define GPIO0_PIN6_MUX_I2S_WS GPIO_MUX_3 /**< GPIO0_PIN6 Mux Select I2S_WS */
186 #define GPIO0_PIN6_MUX_ISO_SYNC1_P GPIO_MUX_4 /**< GPIO0_PIN6 Mux Select ISO_SYNC1_P */
187 #define GPIO0_PIN6_MUX_SPI_S_CLK GPIO_MUX_5 /**< GPIO0_PIN6 Mux Select SPI_S_CLK */
188 #define GPIO0_PIN6_MUX_SIM_PRESENCE GPIO_MUX_6 /**< GPIO0_PIN6 Mux Select SIM_PRESENCE */
189 /** @} */
190
191 /** @defgroup GPIOEx_GPIO0_PIN7_Mux_Selection GPIO0_PIN7 MUX selection
192 * @{
193 */
194 #define GPIO0_PIN7_MUX_I2C3_SDA GPIO_MUX_0 /**< GPIO0_PIN7 Mux Select I2C3_SDA */
195 #define GPIO0_PIN7_MUX_SPI_M_CS0_N GPIO_MUX_1 /**< GPIO0_PIN7 Mux Select SPI_M_CS0_N */
196 #define GPIO0_PIN7_MUX_PWM1_A GPIO_MUX_2 /**< GPIO0_PIN7 Mux Select PWM1_A */
197 #define GPIO0_PIN7_MUX_I2S_TX_SDO GPIO_MUX_3 /**< GPIO0_PIN7 Mux Select I2S_TX_SDO */
198 #define GPIO0_PIN7_MUX_ISO_SYNC0_P GPIO_MUX_4 /**< GPIO0_PIN7 Mux Select ISO_SYNC0_P */
199 #define GPIO0_PIN7_MUX_SPI_S_MISO GPIO_MUX_5 /**< GPIO0_PIN7 Mux Select SPI_S_MISO */
200 #define GPIO0_PIN7_MUX_SIM_RST_N GPIO_MUX_6 /**< GPIO0_PIN7 Mux Select SIM_RST_N */
201 /** @} */
202
203 /** @defgroup GPIOEx_GPIO0_PIN8_Mux_Selection GPIO0_PIN8 MUX selection
204 * @{
205 */
206 #define GPIO0_PIN8_MUX_I2C5_SCL GPIO_MUX_0 /**< GPIO0_PIN8 Mux Select I2C5_SCL */
207 #define GPIO0_PIN8_MUX_UART2_TX GPIO_MUX_1 /**< GPIO0_PIN8 Mux Select UART2_TX */
208 #define GPIO0_PIN8_MUX_PWM1_B GPIO_MUX_2 /**< GPIO0_PIN8 Mux Select PWM1_B */
209 #define GPIO0_PIN8_MUX_I2S_RX_SDI GPIO_MUX_3 /**< GPIO0_PIN8 Mux Select I2S_RX_SDI */
210 #define GPIO0_PIN8_MUX_UART3_CTS GPIO_MUX_4 /**< GPIO0_PIN8 Mux Select UART3_CTS */
211 #define GPIO0_PIN8_MUX_SPI_S_MOSI GPIO_MUX_5 /**< GPIO0_PIN8 Mux Select SPI_S_MOSI */
212 #define GPIO0_PIN8_MUX_SIM_IO GPIO_MUX_6 /**< GPIO0_PIN8 Mux Select SIM_IO */
213 /** @} */
214
215 /** @defgroup GPIOEx_GPIO0_PIN9_Mux_Selection GPIO0_PIN9 MUX selection
216 * @{
217 */
218 #define GPIO0_PIN9_MUX_I2C5_SDA GPIO_MUX_0 /**< GPIO0_PIN9 Mux Select I2C5_SDA */
219 #define GPIO0_PIN9_MUX_UART2_RX GPIO_MUX_1 /**< GPIO0_PIN9 Mux Select UART2_RX */
220 #define GPIO0_PIN9_MUX_PWM1_C GPIO_MUX_2 /**< GPIO0_PIN9 Mux Select PWM1_C */
221 #define GPIO0_PIN9_MUX_I2S_SCLK GPIO_MUX_3 /**< GPIO0_PIN9 Mux Select I2S_SCLK */
222 #define GPIO0_PIN9_MUX_UART3_RTS GPIO_MUX_4 /**< GPIO0_PIN9 Mux Select UART3_RTS */
223 #define GPIO0_PIN9_MUX_SPI_S_CS_N GPIO_MUX_5 /**< GPIO0_PIN9 Mux Select SPI_S_CS_N */
224 #define GPIO0_PIN9_MUX_SIM_CLK GPIO_MUX_6 /**< GPIO0_PIN9 Mux Select SIM_CLK */
225 /** @} */
226
227 /** @defgroup GPIOEx_GPIO0_PIN10_Mux_Selection GPIO0_PIN10 MUX selection
228 * @{
229 */
230 #define GPIO0_PIN10_MUX_QSPI_M1_CS_N GPIO_MUX_0 /**< GPIO0_PIN10 Mux Select QSPI_M1_CS_N */
231 #define GPIO0_PIN10_MUX_I2S_S_WS GPIO_MUX_1 /**< GPIO0_PIN10 Mux Select I2S_S_WS */
232 #define GPIO0_PIN10_MUX_SPI_M_CS0_N GPIO_MUX_2 /**< GPIO0_PIN10 Mux Select SPI_M_CS0_N */
233 #define GPIO0_PIN10_MUX_UART4_CTS GPIO_MUX_3 /**< GPIO0_PIN10 Mux Select UART4_CTS */
234 #define GPIO0_PIN10_MUX_UART5_RX GPIO_MUX_4 /**< GPIO0_PIN10 Mux Select UART5_RX */
235 #define GPIO0_PIN10_MUX_PWM1_A GPIO_MUX_5 /**< GPIO0_PIN10 Mux Select PWM1_A */
236 #define GPIO0_PIN10_MUX_SPI_S_MOSI GPIO_MUX_6 /**< GPIO0_PIN10 Mux Select SPI_S_MOSI */
237
238 /** @} */
239
240 /** @defgroup GPIOEx_GPIO0_PIN11_Mux_Selection GPIO0_PIN11 MUX selection
241 * @{
242 */
243 #define GPIO0_PIN11_MUX_QSPI_M1_IO_3 GPIO_MUX_0 /**< GPIO0_PIN11 Mux Select QSPI_M1_IO_3 */
244 #define GPIO0_PIN11_MUX_I2S_S_TX_SDO GPIO_MUX_1 /**< GPIO0_PIN11 Mux Select I2S_S_TX_SDO */
245 #define GPIO0_PIN11_MUX_I2C3_SCL GPIO_MUX_2 /**< GPIO0_PIN11 Mux Select I2C3_SCL */
246 #define GPIO0_PIN11_MUX_UART4_RTS GPIO_MUX_3 /**< GPIO0_PIN11 Mux Select UART4_RTS */
247 #define GPIO0_PIN11_MUX_UART5_TX GPIO_MUX_4 /**< GPIO0_PIN11 Mux Select UART5_TX */
248 #define GPIO0_PIN11_MUX_PWM1_B GPIO_MUX_5 /**< GPIO0_PIN11 Mux Select PWM1_B */
249 #define GPIO0_PIN11_MUX_SPI_S_CLK GPIO_MUX_6 /**< GPIO0_PIN11 Mux Select SPI_S_CLK */
250 /** @} */
251
252 /** @defgroup GPIOEx_GPIO0_PIN12_Mux_Selection GPIO0_PIN12 MUX selection
253 * @{
254 */
255 #define GPIO0_PIN12_MUX_QSPI_M1_IO_2 GPIO_MUX_0 /**< GPIO0_PIN12 Mux Select QSPI_M1_IO_2 */
256 #define GPIO0_PIN12_MUX_I2S_S_RX_SDI GPIO_MUX_1 /**< GPIO0_PIN12 Mux Select I2S_S_RX_SDI */
257 #define GPIO0_PIN12_MUX_I2C3_SDA GPIO_MUX_2 /**< GPIO0_PIN12 Mux Select I2C3_SDA */
258 #define GPIO0_PIN12_MUX_UART4_TX GPIO_MUX_3 /**< GPIO0_PIN12 Mux Select UART4_TX */
259 #define GPIO0_PIN12_MUX_UART5_CTS GPIO_MUX_4 /**< GPIO0_PIN12 Mux Select UART5_CTS */
260 #define GPIO0_PIN12_MUX_PWM1_C GPIO_MUX_5 /**< GPIO0_PIN12 Mux Select PWM1_C */
261 #define GPIO0_PIN12_MUX_SPI_S_MISO GPIO_MUX_6 /**< GPIO0_PIN12 Mux Select SPI_S_MISO */
262 /** @} */
263
264 /** @defgroup GPIOEx_GPIO0_PIN13_Mux_Selection GPIO0_PIN13 MUX selection
265 * @{
266 */
267 #define GPIO0_PIN13_MUX_QSPI_M1_IO_1 GPIO_MUX_0 /**< GPIO0_PIN13 Mux Select QSPI_M1_IO_1 */
268 #define GPIO0_PIN13_MUX_I2S_S_SCLK GPIO_MUX_1 /**< GPIO0_PIN13 Mux Select I2S_S_SCLK */
269 #define GPIO0_PIN13_MUX_SPI_M_MISO GPIO_MUX_2 /**< GPIO0_PIN13 Mux Select SPI_M_MISO */
270 #define GPIO0_PIN13_MUX_UART4_RX GPIO_MUX_3 /**< GPIO0_PIN13 Mux Select UART4_RX */
271 #define GPIO0_PIN13_MUX_UART5_RTS GPIO_MUX_4 /**< GPIO0_PIN13 Mux Select UART5_RTS */
272 #define GPIO0_PIN13_MUX_FERP_GPIO_TRIG GPIO_MUX_5 /**< GPIO0_PIN13 Mux Select FERP_GPIO_TRIG */
273 #define GPIO0_PIN13_MUX_SPI_S_CS_N GPIO_MUX_6 /**< GPIO0_PIN13 Mux Select SPI_S_CS_N */
274 /** @} */
275
276 /** @defgroup GPIOEx_GPIO0_PIN14_Mux_Selection GPIO0_PIN14 MUX selection
277 * @{
278 */
279 #define GPIO0_PIN14_MUX_QSPI_M1_IO_0 GPIO_MUX_0 /**< GPIO0_PIN14 Mux Select QSPI_M1_IO_0 */
280 #define GPIO0_PIN14_MUX_I2C5_SCL GPIO_MUX_1 /**< GPIO0_PIN14 Mux Select I2C5_SCL */
281 #define GPIO0_PIN14_MUX_SPI_M_MOSI GPIO_MUX_2 /**< GPIO0_PIN14 Mux Select SPI_M_MOSI */
282 #define GPIO0_PIN14_MUX_PDM_CLKO GPIO_MUX_3 /**< GPIO0_PIN14 Mux Select PDM_CLKO */
283 #define GPIO0_PIN14_MUX_DF_ANT_SWITCH_SEL_2 GPIO_MUX_4 /**< GPIO0_PIN14 Mux Select DF_ANT_SWITCH_SEL_2 */
284 #define GPIO0_PIN14_MUX_UART0_TX GPIO_MUX_5 /**< GPIO0_PIN14 Mux Select UART0_TX */
285 #define GPIO0_PIN14_MUX_ISO_SYNC1_P GPIO_MUX_6 /**< GPIO0_PIN14 Mux Select ISO_SYNC1_P */
286 /** @} */
287
288 /** @defgroup GPIOEx_GPIO0_PIN15_Mux_Selection GPIO0_PIN15 MUX selection
289 * @{
290 */
291 #define GPIO0_PIN15_MUX_QSPI_M1_CLK GPIO_MUX_0 /**< GPIO0_PIN15 Mux Select QSPI_M1_CLK */
292 #define GPIO0_PIN15_MUX_I2C5_SDA GPIO_MUX_1 /**< GPIO0_PIN15 Mux Select I2C5_SDA */
293 #define GPIO0_PIN15_MUX_SPI_M_CLK GPIO_MUX_2 /**< GPIO0_PIN15 Mux Select SPI_M_CLK */
294 #define GPIO0_PIN15_MUX_PDM_DI GPIO_MUX_3 /**< GPIO0_PIN15 Mux Select PDM_DI */
295 #define GPIO0_PIN15_MUX_DF_ANT_SWITCH_SEL_3 GPIO_MUX_4 /**< GPIO0_PIN15 Mux Select DF_ANT_SWITCH_SEL_3 */
296 #define GPIO0_PIN15_MUX_UART0_RX GPIO_MUX_5 /**< GPIO0_PIN15 Mux Select UART0_RX */
297 #define GPIO0_PIN15_MUX_ISO_SYNC0_P GPIO_MUX_6 /**< GPIO0_PIN15 Mux Select ISO_SYNC0_P */
298 /** @} */
299
300 /** @defgroup GPIOEx_GPIO1_PIN0_Mux_Selection GPIO1_PIN0 MUX selection
301 * @{
302 */
303 #define GPIO1_PIN0_MUX_QSPI_M2_CLK GPIO_MUX_0 /**< GPIO1_PIN0 Mux Select QSPI_M2_CLK */
304 #define GPIO1_PIN0_MUX_DC_CLK GPIO_MUX_1 /**< GPIO1_PIN0 Mux Select DC_CLK */
305 #define GPIO1_PIN0_MUX_DSPI_SCK GPIO_MUX_2 /**< GPIO1_PIN0 Mux Select DSPI_SCK */
306 #define GPIO1_PIN0_MUX_SPI_M_CLK GPIO_MUX_3 /**< GPIO1_PIN0 Mux Select SPI_M_CLK */
307 #define GPIO1_PIN0_MUX_UART4_TX GPIO_MUX_4 /**< GPIO1_PIN0 Mux Select UART4_TX */
308 #define GPIO1_PIN0_MUX_PWM0_C GPIO_MUX_5 /**< GPIO1_PIN0 Mux Select PWM0_C */
309 #define GPIO1_PIN0_MUX_I2C0_SCL GPIO_MUX_6 /**< GPIO1_PIN0 Mux Select I2C0_SCL */
310 /** @} */
311
312 /** @defgroup GPIOEx_GPIO1_PIN1_Mux_Selection GPIO1_PIN1 MUX selection
313 * @{
314 */
315 #define GPIO1_PIN1_MUX_QSPI_M2_IO_0 GPIO_MUX_0 /**< GPIO1_PIN1 Mux Select QSPI_M2_IO_0 */
316 #define GPIO1_PIN1_MUX_DC_IO_0 GPIO_MUX_1 /**< GPIO1_PIN1 Mux Select DC_IO_0 */
317 #define GPIO1_PIN1_MUX_DSPI_MOSI GPIO_MUX_2 /**< GPIO1_PIN1 Mux Select DSPI_MOSI */
318 #define GPIO1_PIN1_MUX_SPI_M_MOSI GPIO_MUX_3 /**< GPIO1_PIN1 Mux Select SPI_M_MOSI */
319 #define GPIO1_PIN1_MUX_UART2_TX GPIO_MUX_4 /**< GPIO1_PIN1 Mux Select UART2_TX */
320 #define GPIO1_PIN1_MUX_UART3_CTS GPIO_MUX_5 /**< GPIO1_PIN1 Mux Select UART3_CTS */
321 #define GPIO1_PIN1_MUX_I2C0_SDA GPIO_MUX_6 /**< GPIO1_PIN1 Mux Select I2C0_SDA */
322 /** @} */
323
324 /** @defgroup GPIOEx_GPIO1_PIN2_Mux_Selection GPIO1_PIN2 MUX selection
325 * @{
326 */
327 #define GPIO1_PIN2_MUX_QSPI_M2_IO_1 GPIO_MUX_0 /**< GPIO1_PIN2 Mux Select QSPI_M2_IO_1 */
328 #define GPIO1_PIN2_MUX_DC_IO_1 GPIO_MUX_1 /**< GPIO1_PIN2 Mux Select DC_IO_1 */
329 #define GPIO1_PIN2_MUX_DSPI_MISO GPIO_MUX_2 /**< GPIO1_PIN2 Mux Select DSPI_MISO */
330 #define GPIO1_PIN2_MUX_SPI_M_MISO GPIO_MUX_3 /**< GPIO1_PIN2 Mux Select SPI_M_MISO */
331 #define GPIO1_PIN2_MUX_UART2_RX GPIO_MUX_4 /**< GPIO1_PIN2 Mux Select UART2_RX */
332 #define GPIO1_PIN2_MUX_UART3_RTS GPIO_MUX_5 /**< GPIO1_PIN2 Mux Select UART3_RTS */
333 #define GPIO1_PIN2_MUX_PWM1_A GPIO_MUX_6 /**< GPIO1_PIN2 Mux Select PWM1_A */
334 /** @} */
335
336 /** @defgroup GPIOEx_GPIO1_PIN3_Mux_Selection GPIO1_PIN3 MUX selection
337 * @{
338 */
339 #define GPIO1_PIN3_MUX_QSPI_M2_IO_2 GPIO_MUX_0 /**< GPIO1_PIN3 Mux Select QSPI_M2_IO_2 */
340 #define GPIO1_PIN3_MUX_DC_IO_2 GPIO_MUX_1 /**< GPIO1_PIN3 Mux Select DC_IO_2 */
341 #define GPIO1_PIN3_MUX_DSPI_DCX GPIO_MUX_2 /**< GPIO1_PIN3 Mux Select DSPI_DCX */
342 #define GPIO1_PIN3_MUX_SPI_M_CS0_N GPIO_MUX_3 /**< GPIO1_PIN3 Mux Select SPI_M_CS0_N */
343 #define GPIO1_PIN3_MUX_UART2_CTS GPIO_MUX_4 /**< GPIO1_PIN3 Mux Select UART2_CTS */
344 #define GPIO1_PIN3_MUX_UART3_TX GPIO_MUX_5 /**< GPIO1_PIN3 Mux Select UART3_TX */
345 #define GPIO1_PIN3_MUX_PWM1_B GPIO_MUX_6 /**< GPIO1_PIN3 Mux Select PWM1_B */
346 /** @} */
347
348 /** @defgroup GPIOEx_GPIO1_PIN4_Mux_Selection GPIO1_PIN4 MUX selection
349 * @{
350 */
351 #define GPIO1_PIN4_MUX_QSPI_M2_IO_3 GPIO_MUX_0 /**< GPIO1_PIN4 Mux Select QSPI_M2_IO_3 */
352 #define GPIO1_PIN4_MUX_DC_IO_3 GPIO_MUX_1 /**< GPIO1_PIN4 Mux Select DC_IO_3 */
353 #define GPIO1_PIN4_MUX_DSPI_CSS GPIO_MUX_2 /**< GPIO1_PIN4 Mux Select DSPI_CSS */
354 #define GPIO1_PIN4_MUX_SPI_M_CS1_N GPIO_MUX_3 /**< GPIO1_PIN4 Mux Select SPI_M_CS1_N */
355 #define GPIO1_PIN4_MUX_UART2_RTS GPIO_MUX_4 /**< GPIO1_PIN4 Mux Select UART2_RTS */
356 #define GPIO1_PIN4_MUX_UART3_RX GPIO_MUX_5 /**< GPIO1_PIN4 Mux Select UART3_RX */
357 #define GPIO1_PIN4_MUX_PWM1_C GPIO_MUX_6 /**< GPIO1_PIN4 Mux Select PWM1_C */
358 /** @} */
359
360 /** @defgroup GPIOEx_GPIO1_PIN5_Mux_Selection GPIO1_PIN5 MUX selection
361 * @{
362 */
363 #define GPIO1_PIN5_MUX_QSPI_M0_CLK GPIO_MUX_0 /**< GPIO1_PIN5 Mux Select QSPI_M0_CLK */
364 #define GPIO1_PIN5_MUX_SPI_M_CLK GPIO_MUX_1 /**< GPIO1_PIN5 Mux Select SPI_M_CLK */
365 #define GPIO1_PIN5_MUX_SIM_CLK GPIO_MUX_2 /**< GPIO1_PIN5 Mux Select SIM_CLK */
366 #define GPIO1_PIN5_MUX_I2S_SCLK GPIO_MUX_3 /**< GPIO1_PIN5 Mux Select I2S_SCLK */
367 #define GPIO1_PIN5_MUX_I2S_S_SCLK GPIO_MUX_4 /**< GPIO1_PIN5 Mux Select I2S_S_SCLK */
368 #define GPIO1_PIN5_MUX_SPI_S_CLK GPIO_MUX_5 /**< GPIO1_PIN5 Mux Select SPI_S_CLK */
369 #define GPIO1_PIN5_MUX_I2C3_SCL GPIO_MUX_6 /**< GPIO1_PIN5 Mux Select I2C3_SCL */
370 /** @} */
371
372 /** @defgroup GPIOEx_GPIO1_PIN6_Mux_Selection GPIO1_PIN6 MUX selection
373 * @{
374 */
375 #define GPIO1_PIN6_MUX_QSPI_M0_IO_0 GPIO_MUX_0 /**< GPIO1_PIN6 Mux Select QSPI_M0_IO_0 */
376 #define GPIO1_PIN6_MUX_SPI_M_MOSI GPIO_MUX_1 /**< GPIO1_PIN6 Mux Select SPI_M_MOSI */
377 #define GPIO1_PIN6_MUX_SIM_IO GPIO_MUX_2 /**< GPIO1_PIN6 Mux Select SIM_IO */
378 #define GPIO1_PIN6_MUX_I2S_RX_SDI GPIO_MUX_3 /**< GPIO1_PIN6 Mux Select I2S_RX_SDI */
379 #define GPIO1_PIN6_MUX_I2S_S_TX_SDO GPIO_MUX_4 /**< GPIO1_PIN6 Mux Select I2S_S_TX_SDO */
380 #define GPIO1_PIN6_MUX_SPI_S_MISO GPIO_MUX_5 /**< GPIO1_PIN6 Mux Select SPI_S_MISO */
381 #define GPIO1_PIN6_MUX_I2C3_SDA GPIO_MUX_6 /**< GPIO1_PIN6 Mux Select I2C3_SDA */
382 /** @} */
383
384 /** @defgroup GPIOEx_GPIO1_PIN7_Mux_Selection GPIO1_PIN7 MUX selection
385 * @{
386 */
387 #define GPIO1_PIN7_MUX_QSPI_M0_IO_1 GPIO_MUX_0 /**< GPIO1_PIN7 Mux Select QSPI_M0_IO_1 */
388 #define GPIO1_PIN7_MUX_SPI_M_MISO GPIO_MUX_1 /**< GPIO1_PIN7 Mux Select SPI_M_MISO */
389 #define GPIO1_PIN7_MUX_SIM_RST_N GPIO_MUX_2 /**< GPIO1_PIN7 Mux Select SIM_RST_N */
390 #define GPIO1_PIN7_MUX_I2S_TX_SDO GPIO_MUX_3 /**< GPIO1_PIN7 Mux Select I2S_TX_SDO */
391 #define GPIO1_PIN7_MUX_I2S_S_RX_SDI GPIO_MUX_4 /**< GPIO1_PIN7 Mux Select I2S_S_RX_SDI */
392 #define GPIO1_PIN7_MUX_SPI_S_MOSI GPIO_MUX_5 /**< GPIO1_PIN7 Mux Select SPI_S_MOSI */
393 #define GPIO1_PIN7_MUX_I2C2_SCL GPIO_MUX_6 /**< GPIO1_PIN7 Mux Select I2C2_SCL */
394 /** @} */
395
396 /** @defgroup GPIOEx_GPIO1_PIN8_Mux_Selection GPIO1_PIN8 MUX selection
397 * @{
398 */
399 #define GPIO1_PIN8_MUX_QSPI_M0_IO_2 GPIO_MUX_0 /**< GPIO1_PIN8 Mux Select QSPI_M0_IO_2 */
400 #define GPIO1_PIN8_MUX_SPI_M_CS0_N GPIO_MUX_1 /**< GPIO1_PIN8 Mux Select SPI_M_CS0_N */
401 #define GPIO1_PIN8_MUX_SIM_PRESENCE GPIO_MUX_2 /**< GPIO1_PIN8 Mux Select SIM_PRESENCE */
402 #define GPIO1_PIN8_MUX_I2S_WS GPIO_MUX_3 /**< GPIO1_PIN8 Mux Select I2S_WS */
403 #define GPIO1_PIN8_MUX_I2S_S_WS GPIO_MUX_4 /**< GPIO1_PIN8 Mux Select I2S_S_WS */
404 #define GPIO1_PIN8_MUX_SPI_S_CS_N GPIO_MUX_5 /**< GPIO1_PIN8 Mux Select SPI_S_CS_N */
405 #define GPIO1_PIN8_MUX_I2C2_SDA GPIO_MUX_6 /**< GPIO1_PIN8 Mux Select I2C2_SDA */
406 /** @} */
407
408 /** @defgroup GPIOEx_GPIO1_PIN9_Mux_Selection GPIO1_PIN9 MUX selection
409 * @{
410 */
411 #define GPIO1_PIN9_MUX_QSPI_M0_IO_3 GPIO_MUX_0 /**< GPIO1_PIN9 Mux Select QSPI_M0_IO_3 */
412 #define GPIO1_PIN9_MUX_SPI_M_CS1_N GPIO_MUX_1 /**< GPIO1_PIN9 Mux Select SPI_M_CS1_N */
413 #define GPIO1_PIN9_MUX_FERP_GPIO_TRIG GPIO_MUX_2 /**< GPIO1_PIN9 Mux Select FERP_GPIO_TRIG */
414 #define GPIO1_PIN9_MUX_UART4_RX GPIO_MUX_3 /**< GPIO1_PIN9 Mux Select UART4_RX */
415 #define GPIO1_PIN9_MUX_I2C3_SCL GPIO_MUX_4 /**< GPIO1_PIN9 Mux Select I2C3_SCL */
416 #define GPIO1_PIN9_MUX_I2C1_SCL GPIO_MUX_5 /**< GPIO1_PIN9 Mux Select I2C1_SCL */
417 #define GPIO1_PIN9_MUX_PWM0_A GPIO_MUX_6 /**< GPIO1_PIN9 Mux Select PWM0_A */
418 /** @} */
419
420 /** @defgroup GPIOEx_GPIO1_PIN10_Mux_Selection GPIO1_PIN10 MUX selection
421 * @{
422 */
423 #define GPIO1_PIN10_MUX_QSPI_M0_CS_N GPIO_MUX_0 /**< GPIO1_PIN10 Mux Select QSPI_M0_CS_N */
424 #define GPIO1_PIN10_MUX_SPI_M_CS0_N GPIO_MUX_1 /**< GPIO1_PIN10 Mux Select SPI_M_CS0_N */
425 #define GPIO1_PIN10_MUX_UART0_CTS GPIO_MUX_2 /**< GPIO1_PIN10 Mux Select UART0_CTS */
426 #define GPIO1_PIN10_MUX_SPI_M_CLK GPIO_MUX_3 /**< GPIO1_PIN10 Mux Select SPI_M_CLK */
427 #define GPIO1_PIN10_MUX_I2C3_SDA GPIO_MUX_4 /**< GPIO1_PIN10 Mux Select I2C3_SDA */
428 #define GPIO1_PIN10_MUX_I2C1_SDA GPIO_MUX_5 /**< GPIO1_PIN10 Mux Select I2C1_SDA */
429 #define GPIO1_PIN10_MUX_PWM0_B GPIO_MUX_6 /**< GPIO1_PIN10 Mux Select PWM0_B */
430 /** @} */
431
432 /** @defgroup GPIOEx_GPIO1_PIN11_Mux_Selection GPIO1_PIN11 MUX selection
433 * @{
434 */
435 #define GPIO1_PIN11_MUX_QSPI_M2_CS_N GPIO_MUX_0 /**< GPIO1_PIN11 Mux Select QSPI_M2_CS_N */
436 #define GPIO1_PIN11_MUX_DC_CS_N GPIO_MUX_1 /**< GPIO1_PIN11 Mux Select DC_CS_N */
437 #define GPIO1_PIN11_MUX_UART0_RTS GPIO_MUX_2 /**< GPIO1_PIN11 Mux Select UART0_RTS */
438 #define GPIO1_PIN11_MUX_SPI_M_MOSI GPIO_MUX_3 /**< GPIO1_PIN11 Mux Select SPI_M_MOSI */
439 #define GPIO1_PIN11_MUX_I2C2_SCL GPIO_MUX_4 /**< GPIO1_PIN11 Mux Select I2C2_SCL */
440 #define GPIO1_PIN11_MUX_I2C0_SCL GPIO_MUX_5 /**< GPIO1_PIN11 Mux Select I2C0_SCL */
441 #define GPIO1_PIN11_MUX_PWM0_C GPIO_MUX_6 /**< GPIO1_PIN11 Mux Select PWM0_C */
442 /** @} */
443
444 /** @defgroup GPIOEx_GPIO1_PIN12_Mux_Selection GPIO1_PIN12 MUX selection
445 * @{
446 */
447 #define GPIO1_PIN12_MUX_PDM_CLKO GPIO_MUX_0 /**< GPIO1_PIN12 Mux Select PDM_CLKO */
448 #define GPIO1_PIN12_MUX_ISO_SYNC1_P GPIO_MUX_1 /**< GPIO1_PIN12 Mux Select ISO_SYNC1_P */
449 #define GPIO1_PIN12_MUX_UART0_TX GPIO_MUX_2 /**< GPIO1_PIN12 Mux Select UART0_TX */
450 #define GPIO1_PIN12_MUX_SPI_M_MISO GPIO_MUX_3 /**< GPIO1_PIN12 Mux Select SPI_M_MISO */
451 #define GPIO1_PIN12_MUX_I2C2_SDA GPIO_MUX_4 /**< GPIO1_PIN12 Mux Select I2C2_SDA */
452 #define GPIO1_PIN12_MUX_I2C0_SDA GPIO_MUX_5 /**< GPIO1_PIN12 Mux Select I2C0_SDA */
453 #define GPIO1_PIN12_MUX_SPI_M_CLK GPIO_MUX_6 /**< GPIO1_PIN12 Mux Select SPI_M_CLK */
454 /** @} */
455
456 /** @defgroup GPIOEx_GPIO1_PIN13_Mux_Selection GPIO1_PIN13 MUX selection
457 * @{
458 */
459 #define GPIO1_PIN13_MUX_PDM_DI GPIO_MUX_0 /**< GPIO1_PIN13 Mux Select PDM_DI */
460 #define GPIO1_PIN13_MUX_ISO_SYNC0_P GPIO_MUX_1 /**< GPIO1_PIN13 Mux Select ISO_SYNC0_P */
461 #define GPIO1_PIN13_MUX_UART0_RX GPIO_MUX_2 /**< GPIO1_PIN13 Mux Select UART0_RX */
462 #define GPIO1_PIN13_MUX_SPI_M_CS0_N GPIO_MUX_3 /**< GPIO1_PIN13 Mux Select SPI_M_CS0_N */
463 #define GPIO1_PIN13_MUX_FERP_GPIO_TRIG GPIO_MUX_4 /**< GPIO1_PIN13 Mux Select FERP_GPIO_TRIG */
464 #define GPIO1_PIN13_MUX_DC_DCX GPIO_MUX_5 /**< GPIO1_PIN13 Mux Select DC_DCX */
465 #define GPIO1_PIN13_MUX_SPI_M_MOSI GPIO_MUX_6 /**< GPIO1_PIN13 Mux Select SPI_M_MOSI */
466 /** @} */
467
468 /** @defgroup GPIOEx_GPIO1_PIN14_Mux_Selection GPIO1_PIN14 MUX selection
469 * @{
470 */
471 #define GPIO1_PIN14_MUX_SPI_S_MOSI GPIO_MUX_0 /**< GPIO1_PIN14 Mux Select SPI_S_MOSI */
472 #define GPIO1_PIN14_MUX_I2S_SCLK GPIO_MUX_1 /**< GPIO1_PIN14 Mux Select I2S_SCLK */
473 #define GPIO1_PIN14_MUX_I2S_S_WS GPIO_MUX_2 /**< GPIO1_PIN14 Mux Select I2S_S_WS */
474 #define GPIO1_PIN14_MUX_I2C1_SCL GPIO_MUX_3 /**< GPIO1_PIN14 Mux Select I2C1_SCL */
475 #define GPIO1_PIN14_MUX_UART1_CTS GPIO_MUX_4 /**< GPIO1_PIN14 Mux Select UART1_CTS */
476 #define GPIO1_PIN14_MUX_I2C5_SCL GPIO_MUX_5 /**< GPIO1_PIN14 Mux Select I2C5_SCL */
477 #define GPIO1_PIN14_MUX_SPI_M_MISO GPIO_MUX_6 /**< GPIO1_PIN14 Mux Select SPI_M_MISO */
478 /** @} */
479
480 /** @defgroup GPIOEx_GPIO1_PIN15_Mux_Selection GPIO1_PIN15 MUX selection
481 * @{
482 */
483 #define GPIO1_PIN15_MUX_SPI_S_CLK GPIO_MUX_0 /**< GPIO1_PIN15 Mux Select SPI_S_CLK */
484 #define GPIO1_PIN15_MUX_I2S_RX_SDI GPIO_MUX_1 /**< GPIO1_PIN15 Mux Select I2S_RX_SDI */
485 #define GPIO1_PIN15_MUX_I2S_S_TX_SDO GPIO_MUX_2 /**< GPIO1_PIN15 Mux Select I2S_S_TX_SDO */
486 #define GPIO1_PIN15_MUX_I2C1_SDA GPIO_MUX_3 /**< GPIO1_PIN15 Mux Select I2C1_SDA */
487 #define GPIO1_PIN15_MUX_UART1_RTS GPIO_MUX_4 /**< GPIO1_PIN15 Mux Select UART1_RTS */
488 #define GPIO1_PIN15_MUX_I2C5_SDA GPIO_MUX_5 /**< GPIO1_PIN15 Mux Select I2C5_SDA */
489 #define GPIO1_PIN15_MUX_SPI_M_CS0_N GPIO_MUX_6 /**< GPIO1_PIN15 Mux Select SPI_M_CS0_N */
490 /** @} */
491
492 /** @defgroup GPIOEx_GPIO2_PIN0_Mux_Selection GPIO2_PIN0 MUX selection
493 * @{
494 */
495 #define GPIO2_PIN0_MUX_SPI_S_MISO GPIO_MUX_0 /**< GPIO2_PIN0 Mux Select SPI_S_MISO */
496 #define GPIO2_PIN0_MUX_I2S_TX_SDO GPIO_MUX_1 /**< GPIO2_PIN0 Mux Select I2S_TX_SDO */
497 #define GPIO2_PIN0_MUX_I2S_S_RX_SDI GPIO_MUX_2 /**< GPIO2_PIN0 Mux Select I2S_S_RX_SDI */
498 #define GPIO2_PIN0_MUX_PDM_CLKO GPIO_MUX_3 /**< GPIO2_PIN0 Mux Select PDM_CLKO */
499 #define GPIO2_PIN0_MUX_UART1_TX GPIO_MUX_4 /**< GPIO2_PIN0 Mux Select UART1_TX */
500 #define GPIO2_PIN0_MUX_PWM0_B GPIO_MUX_5 /**< GPIO2_PIN0 Mux Select PWM0_B */
501 #define GPIO2_PIN0_MUX_I2C0_SCL GPIO_MUX_6 /**< GPIO2_PIN0 Mux Select I2C0_SCL */
502 /** @} */
503
504 /** @defgroup GPIOEx_GPIO2_PIN1_Mux_Selection GPIO2_PIN1 MUX selection
505 * @{
506 */
507 #define GPIO2_PIN1_MUX_SPI_S_CS_N GPIO_MUX_0 /**< GPIO2_PIN1 Mux Select SPI_S_CS_N */
508 #define GPIO2_PIN1_MUX_I2S_WS GPIO_MUX_1 /**< GPIO2_PIN1 Mux Select I2S_WS */
509 #define GPIO2_PIN1_MUX_I2S_S_SCLK GPIO_MUX_2 /**< GPIO2_PIN1 Mux Select I2S_S_SCLK */
510 #define GPIO2_PIN1_MUX_PDM_DI GPIO_MUX_3 /**< GPIO2_PIN1 Mux Select PDM_DI */
511 #define GPIO2_PIN1_MUX_UART1_RX GPIO_MUX_4 /**< GPIO2_PIN1 Mux Select UART1_RX */
512 #define GPIO2_PIN1_MUX_PWM0_A GPIO_MUX_5 /**< GPIO2_PIN1 Mux Select PWM0_A */
513 #define GPIO2_PIN1_MUX_I2C0_SDA GPIO_MUX_6 /**< GPIO2_PIN1 Mux Select I2C0_SDA */
514 /** @} */
515
516 /**
517 * @brief Check if GPIO Mux mode is valid.
518 * @param __MUX__ GPIO mux mode.
519 * @retval SET (__ACTION__ is valid) or RESET (__ACTION__ is invalid)
520 */
521 #define IS_GPIO_MUX(__MUX__) (((__MUX__) <= GPIO_MUX_8))
522
523 /*------------------------------------------------------------------------------------------*/
524 #endif /* GR552xx */
525
526
527
528 /** @} */
529
530 /** @} */
531
532 /* Exported macro ------------------------------------------------------------*/
533 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
534 * @{
535 */
536
537 #ifdef __cplusplus
538 }
539 #endif
540
541 #endif /* __GR55xx_HAL_GPIO_EX_H__ */
542
543 /** @} */
544 /** @} */
545
546 /** @} */
547
548 /** @} */
549
550 /** @} */
gr55xx_ll_gpio.h
Header file containing functions prototypes of GPIO LL library.
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.