gr55xx_ll_qspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_QSPI QSPI
47 * @brief QSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_QSPI_H__
53 #define __GR55xx_LL_QSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (QSPI0) || defined (QSPI1) || defined (QSPI2)
63
64 /** @defgroup LL_QSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup LL_QSPI_ES_INIT QSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief QSPI init structures definition
75 */
76 typedef struct _ll_qspi_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the QSPI transfer or receive mode.
79 This parameter can be a value of @ref LL_QSPI_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_qspi_set_transfer_direction().*/
82
83 uint32_t instruction_size; /**< Specifies the QSPI instruction width.
84 This parameter can be a value of @ref LL_QSPI_EC_INSTRUCTIONSIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_qspi_set_instruction_size().*/
87
88 uint32_t address_size; /**< Specifies the QSPI address width.
89 This parameter can be a value of @ref LL_QSPI_EC_ADDRESSSIZE.
90
91 This feature can be modified afterwards using unitary function @ref ll_qspi_set_address_size().*/
92
93 uint32_t inst_addr_transfer_format; /**< Specifies the QSPI instruction and address transfer format.
94 This parameter can be a value of @ref LL_QSPI_EC_ADDRINSTTRNASFERFORMAT.
95
96 This feature can be modified afterwards using unitary function @ref ll_qspi_set_add_inst_transfer_format().*/
97
98 uint32_t wait_cycles; /**< Specifies the QSPI dummy clock.
99 This parameter can be one of the following values: 0 ~ 31.
100
101 This feature can be modified afterwards using unitary function @ref ll_qspi_set_wait_cycles().*/
102
103 uint32_t data_size; /**< Specifies the QSPI data width.
104 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
105
106 This feature can be modified afterwards using unitary function @ref ll_qspi_set_data_size().*/
107
108 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
109 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
110 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_polarity().*/
111
112 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
113 This parameter can be a value of @ref SPI_LL_EC_PHASE.
114
115 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_phase().*/
116
117 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
118 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
119 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
120
121 This feature can be modified afterwards using unitary function @ref ll_qspi_set_baud_rate_prescaler().*/
122
123 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
124 This parameter can be a number between 0 and 0x7 */
125
126 } ll_qspi_init_t;
127
128 typedef enum {
129 LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY = 0, /* Specifies mmap mode to read only */
130 LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE = 1, /* Specifies mmap mode to read and write */
131 } ll_qspi_memorymapped_mode_e;
132
133 typedef struct _ll_qspi_memorymapped_read_init_t
134 {
135 /*
136 * memorymapped read setting parameters
137 */
138
139 uint32_t x_dfs; /**< Specifies the QSPI data frame size in xip mode.
140 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_DFS. */
141
142 uint32_t x_dfs_hardcode_en; /**< Specifies whether to enable the HSIZE hardcoded to DFS feature in memorymapped(xip) mode.
143 @ref LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE
144 @ref LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
145 */
146
147 uint32_t x_instruction_en; /**< Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
148 @ref LL_QSPI_CONCURRENT_XIP_INST_ENABLE
149 @ref LL_QSPI_CONCURRENT_XIP_INST_DISABLE
150 */
151
152 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
153 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE.
154 */
155
156 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
157
158 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
159 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE.
160 */
161
162 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
163 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT.
164 */
165
166 uint32_t x_mode_bits_en; /**< Specifies whether to enable mode bits phase in memorymapped(xip) mode.
167 @ref LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE
168 @ref LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
169 */
170
171 uint32_t x_mode_bits_length; /**< Specifies mode bits length
172 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_MBL.
173 */
174
175 uint32_t x_mode_bits_data; /**< Specifies value of mode bits phase */
176
177 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
178 value range [0 ~ 31]
179 */
180
181 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
182 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_FRF
183 */
184
185 uint32_t x_prefetch_en; /**< Specifies whether to enable the prefetch feature.
186 @ref LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE
187 @ref LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
188 */
189
190 uint32_t x_continous_xfer_en; /**< Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
191 @ref LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE
192 @ref LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
193 */
194
195 uint32_t x_continous_xfer_toc; /**< Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
196 unit in terms of hclk, range [0, 255]
197 */
198
199 uint32_t x_endian_mode; /**< Specifies endian mode in memorymapped(xip) mode.
200 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE
201 */
202 } ll_qspi_memorymapped_read_init_t;
203
204
205
206 typedef struct _ll_qspi_memorymapped_write_init_t
207 {
208 /*
209 * memorymapped write setting parameters
210 */
211
212 uint32_t x_wr_instruction_size; /**< Specifies instruction size in memorymapped(xip) write mode.
213 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE.
214 */
215
216 uint32_t x_wr_instruction; /**< Specifies instruction in memorymapped(xip) write mode. */
217
218 uint32_t x_wr_address_size; /**< Specifies instruction size in memorymapped(xip) write mode.
219 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE.
220 */
221
222 uint32_t x_wr_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) write mode.
223 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT.
224 */
225
226 uint32_t x_wr_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) write mode.
227 value range [0 ~ 31]
228 */
229
230 uint32_t x_wr_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) write mode.
231 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_FRF
232 */
233 } ll_qspi_memorymapped_write_init_t;
234
235
236 typedef struct _ll_qspi_memorymapped_init_t
237 {
238 /*
239 * basical setting parameters
240 */
241
242 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
243 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
244 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_polarity().*/
245
246 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
247 This parameter can be a value of @ref SPI_LL_EC_PHASE.
248 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_phase().*/
249
250 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
251 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
252 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
253 This feature can be modified afterwards using unitary function @ref ll_qspi_set_baud_rate_prescaler().*/
254
255 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
256 This parameter can be a number between 0 and 0x7 */
257
258 ll_qspi_memorymapped_mode_e rw_mode; /**< Specifies the access mode for memorymapped: readonly or read&write */
259
260 ll_qspi_memorymapped_read_init_t rd; /**< Specifies the initized params for read, must set */
261
262 ll_qspi_memorymapped_write_init_t wr; /**< Specifies the initized params for write, if rw_mode is readonly, leave un-set */
263
264 } ll_qspi_memorymapped_init_t;
265
266 /** uint32_t clock_polarity; @} */
267
268 /** @} */
269
270 /**
271 * @defgroup LL_QSPI_MACRO Defines
272 * @{
273 */
274
275 /* Exported constants --------------------------------------------------------*/
276 /** @defgroup LL_QSPI_Exported_Constants QSPI Exported Constants
277 * @{
278 */
279
280 /** @defgroup LL_QSPI_FIFO_DEPTH FIFO Depth Defines
281 * @{
282 */
283 #define LL_QSPI_MAX_FIFO_DEPTH (32u) /**< FIFO Depth for QSPI Master */
284
285 #define LL_QSPI0_REG_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of Register Mode for QSPI0 Master */
286 #define LL_QSPI0_REG_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of Register Mode for QSPI0 Master */
287 #define LL_QSPI0_XIP_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of XIP Mode for QSPI0 Master */
288 #define LL_QSPI0_XIP_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of XIP Mode for QSPI0 Master */
289
290 #define LL_QSPI1_REG_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of Register Mode for QSPI1 Master */
291 #define LL_QSPI1_REG_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of Register Mode for QSPI1 Master */
292 #define LL_QSPI1_XIP_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of XIP Mode for QSPI1 Master */
293 #define LL_QSPI1_XIP_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of XIP Mode for QSPI1 Master */
294
295 #define LL_QSPI2_REG_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of Register Mode for QSPI2 Master */
296 #define LL_QSPI2_REG_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of Register Mode for QSPI2 Master */
297 #define LL_QSPI2_XIP_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of XIP Mode for QSPI2 Master */
298 #define LL_QSPI2_XIP_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of XIP Mode for QSPI2 Master */
299 /** @} */
300
301 /** @defgroup LL_QSPI_EC_GET_FLAG Get Flags Defines
302 * @brief Flags definitions which can be used with LL_QSPI_ReadReg function
303 * @{
304 */
305 #define LL_QSPI_SR_DCOL QSPI_STAT_DCOL /**< Data collision error flag */
306 #define LL_QSPI_SR_TXE QSPI_STAT_TXE /**< Transmission error flag */
307 #define LL_QSPI_SR_RFF QSPI_STAT_RFF /**< Rx FIFO full flag */
308 #define LL_QSPI_SR_RFNE QSPI_STAT_RFNE /**< Rx FIFO not empty flag */
309 #define LL_QSPI_SR_TFE QSPI_STAT_TFE /**< Tx FIFO empty flag */
310 #define LL_QSPI_SR_TFNF QSPI_STAT_TFNF /**< Tx FIFO not full flag */
311 #define LL_QSPI_SR_BUSY QSPI_STAT_BUSY /**< Busy flag */
312 /** @} */
313
314 /** @defgroup LL_QSPI_EC_IT IT Defines
315 * @brief Interrupt definitions which can be used with @ref LL_QSPI_ReadReg and @ref LL_QSPI_WriteReg functions
316 * @{
317 */
318 #define LL_QSPI_IM_SPITE QSPI_INTMASK_SPITEIM /**< SPI Transmit Error Interrupt enable */
319 #define LL_QSPI_IM_TXU QSPI_INTMASK_TXUIM /**< Transmit FIFO Underflow Interrupt enable */
320 #define LL_QSPI_IM_XRXO QSPI_INTMASK_XRXOIM /**< XIP Receive FIFO Overflow Interrupt enable */
321 #define LL_QSPI_IM_MST QSPI_INTMASK_MSTIM /**< Multi-Master Contention Interrupt enable */
322 #define LL_QSPI_IM_RXF QSPI_INTMASK_RXFIM /**< Receive FIFO Full Interrupt enable */
323 #define LL_QSPI_IM_RXO QSPI_INTMASK_RXOIM /**< Receive FIFO Overflow Interrupt enable */
324 #define LL_QSPI_IM_RXU QSPI_INTMASK_RXUIM /**< Receive FIFO Underflow Interrupt enable */
325 #define LL_QSPI_IM_TXO QSPI_INTMASK_TXOIM /**< Transmit FIFO Overflow Interrupt enable */
326 #define LL_QSPI_IM_TXE QSPI_INTMASK_TXEIM /**< Transmit FIFO Empty Interrupt enable */
327 #define LL_QSPI_IM_ALL (LL_QSPI_IM_SPITE| \
328 LL_QSPI_IM_TXU | \
329 LL_QSPI_IM_XRXO | \
330 LL_QSPI_IM_MST | \
331 LL_QSPI_IM_RXF | \
332 LL_QSPI_IM_RXO | \
333 LL_QSPI_IM_RXU | \
334 LL_QSPI_IM_TXO | \
335 LL_QSPI_IM_TXE)
336
337 #define LL_QSPI_IS_SPITE QSPI_INTMASK_SPITEIS /**< SPI Transmit Error Interrupt flag */
338 #define LL_QSPI_IS_TXU QSPI_INTMASK_TXUIS /**< Transmit FIFO Underflow Interrupt flag */
339 #define LL_QSPI_IS_XRXO QSPI_INTSTAT_XRXOIS /**< XIP Receive FIFO Overflow Interrupt flag */
340 #define LL_QSPI_IS_MST QSPI_INTSTAT_MSTIS /**< Multi-Master Contention Interrupt flag */
341 #define LL_QSPI_IS_RXF QSPI_INTSTAT_RXFIS /**< Receive FIFO Full Interrupt flag */
342 #define LL_QSPI_IS_RXO QSPI_INTSTAT_RXOIS /**< Receive FIFO Overflow Interrupt flag */
343 #define LL_QSPI_IS_RXU QSPI_INTSTAT_RXUIS /**< Receive FIFO Underflow Interrupt flag */
344 #define LL_QSPI_IS_TXO QSPI_INTSTAT_TXOIS /**< Transmit FIFO Overflow Interrupt flag */
345 #define LL_QSPI_IS_TXE QSPI_INTSTAT_TXEIS /**< Transmit FIFO Empty Interrupt flag */
346 #define LL_QSPI_IS_ALL (LL_QSPI_IS_SPITE| \
347 LL_QSPI_IS_TXU | \
348 LL_QSPI_IS_XRXO | \
349 LL_QSPI_IS_MST | \
350 LL_QSPI_IS_RXF | \
351 LL_QSPI_IS_RXO | \
352 LL_QSPI_IS_RXU | \
353 LL_QSPI_IS_TXO | \
354 LL_QSPI_IS_TXE)
355
356 #define LL_QSPI_RIS_SPITE QSPI_RAW_INTMASK_SPITEIR /**< SPI Transmit Error RAW Interrupt flag */
357 #define LL_QSPI_RIS_TXU QSPI_RAW_INTMASK_TXUIIR /**< Transmit FIFO Underflow RAW Interrupt flag */
358 #define LL_QSPI_RIS_XRXO QSPI_RAW_INTSTAT_XRXOIR /**< XIP Receive FIFO Overflow RAW Interrupt flag */
359 #define LL_QSPI_RIS_MST QSPI_RAW_INTSTAT_MSTIR /**< Multi-Master Contention RAW Interrupt flag */
360 #define LL_QSPI_RIS_RXF QSPI_RAW_INTSTAT_RXFIR /**< Receive FIFO Full RAW Interrupt flag */
361 #define LL_QSPI_RIS_RXO QSPI_RAW_INTSTAT_RXOIR /**< Receive FIFO Overflow RAW Interrupt flag */
362 #define LL_QSPI_RIS_RXU QSPI_RAW_INTSTAT_RXUIR /**< Receive FIFO Underflow RAW Interrupt flag */
363 #define LL_QSPI_RIS_TXO QSPI_RAW_INTSTAT_TXOIR /**< Transmit FIFO Overflow RAW Interrupt flag */
364 #define LL_QSPI_RIS_TXE QSPI_RAW_INTSTAT_TXEIR /**< Transmit FIFO Empty RAW Interrupt flag */
365 #define LL_QSPI_RIS_ALL (LL_QSPI_RIS_SPITE| \
366 LL_QSPI_RIS_TXU | \
367 LL_QSPI_RIS_XRXO | \
368 LL_QSPI_RIS_MST | \
369 LL_QSPI_RIS_RXF | \
370 LL_QSPI_RIS_RXO | \
371 LL_QSPI_RIS_RXU | \
372 LL_QSPI_RIS_TXO | \
373 LL_QSPI_RIS_TXE)
374
375 /** @} */
376
377 /** @defgroup LL_QSPI_EC_SPIFRAMEFORMAT SPI Frame Format
378 * @{
379 */
380 #define LL_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
381 #define LL_QSPI_FRF_DUALSPI (1UL << QSPI_CTRL0_SPIFRF_Pos) /**< Dual-SPI frame format for transfer */
382 #define LL_QSPI_FRF_QUADSPI (2UL << QSPI_CTRL0_SPIFRF_Pos) /**< Quad-SPI frame format for transfer */
383 /** @} */
384
385 /** @defgroup LL_QSPI_EC_DATASIZE Datawidth
386 * @{
387 */
388 #define LL_QSPI_DATASIZE_4BIT (3UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 4 bits */
389 #define LL_QSPI_DATASIZE_5BIT (4UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 5 bits */
390 #define LL_QSPI_DATASIZE_6BIT (5UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 6 bits */
391 #define LL_QSPI_DATASIZE_7BIT (6UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 7 bits */
392 #define LL_QSPI_DATASIZE_8BIT (7UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 8 bits */
393 #define LL_QSPI_DATASIZE_9BIT (8UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 9 bits */
394 #define LL_QSPI_DATASIZE_10BIT (9UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 10 bits */
395 #define LL_QSPI_DATASIZE_11BIT (10UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 11 bits */
396 #define LL_QSPI_DATASIZE_12BIT (11UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 12 bits */
397 #define LL_QSPI_DATASIZE_13BIT (12UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 13 bits */
398 #define LL_QSPI_DATASIZE_14BIT (13UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 14 bits */
399 #define LL_QSPI_DATASIZE_15BIT (14UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 15 bits */
400 #define LL_QSPI_DATASIZE_16BIT (15UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 16 bits */
401 #define LL_QSPI_DATASIZE_17BIT (16UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 17 bits */
402 #define LL_QSPI_DATASIZE_18BIT (17UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 18 bits */
403 #define LL_QSPI_DATASIZE_19BIT (18UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 19 bits */
404 #define LL_QSPI_DATASIZE_20BIT (19UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 20 bits */
405 #define LL_QSPI_DATASIZE_21BIT (20UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 21 bits */
406 #define LL_QSPI_DATASIZE_22BIT (21UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 22 bits */
407 #define LL_QSPI_DATASIZE_23BIT (22UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 23 bits */
408 #define LL_QSPI_DATASIZE_24BIT (23UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 24 bits */
409 #define LL_QSPI_DATASIZE_25BIT (24UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 25 bits */
410 #define LL_QSPI_DATASIZE_26BIT (25UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 26 bits */
411 #define LL_QSPI_DATASIZE_27BIT (26UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 27 bits */
412 #define LL_QSPI_DATASIZE_28BIT (27UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 28 bits */
413 #define LL_QSPI_DATASIZE_29BIT (28UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 29 bits */
414 #define LL_QSPI_DATASIZE_30BIT (29UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 30 bits */
415 #define LL_QSPI_DATASIZE_31BIT (30UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 31 bits */
416 #define LL_QSPI_DATASIZE_32BIT (31UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 32 bits */
417 /** @} */
418
419 /** @defgroup LL_QSPI_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
420 * @{
421 */
422 #define LL_QSPI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
423 #define LL_QSPI_MW_CMDSIZE_2BIT (1UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 2 bits */
424 #define LL_QSPI_MW_CMDSIZE_3BIT (2UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 3 bits */
425 #define LL_QSPI_MW_CMDSIZE_4BIT (3UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 4 bits */
426 #define LL_QSPI_MW_CMDSIZE_5BIT (4UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 5 bits */
427 #define LL_QSPI_MW_CMDSIZE_6BIT (5UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 6 bits */
428 #define LL_QSPI_MW_CMDSIZE_7BIT (6UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 7 bits */
429 #define LL_QSPI_MW_CMDSIZE_8BIT (7UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 8 bits */
430 #define LL_QSPI_MW_CMDSIZE_9BIT (8UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 9 bits */
431 #define LL_QSPI_MW_CMDSIZE_10BIT (9UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 10 bits */
432 #define LL_QSPI_MW_CMDSIZE_11BIT (10UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 11 bits */
433 #define LL_QSPI_MW_CMDSIZE_12BIT (11UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 12 bits */
434 #define LL_QSPI_MW_CMDSIZE_13BIT (12UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 13 bits */
435 #define LL_QSPI_MW_CMDSIZE_14BIT (13UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 14 bits */
436 #define LL_QSPI_MW_CMDSIZE_15BIT (14UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 15 bits */
437 #define LL_QSPI_MW_CMDSIZE_16BIT (15UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 16 bits */
438 /** @} */
439
440 /** @defgroup LL_QSPI_EC_TEST_MODE Test Mode
441 * @{
442 */
443 #define LL_QSPI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
444 #define LL_QSPI_TEST_MODE (1UL << QSPI_CTRL0_SRL_Pos) /**< Test mode for SPI transfer: Rx and Tx connected inside */
445 /** @} */
446
447 /** @defgroup LL_QSPI_EC_SLAVEOUT_ENABLE Slave Out Enable
448 * @{
449 */
450 #define LL_QSPI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
451 #define LL_QSPI_SLAVE_OUTEN (1UL << QSPI_CTRL0_SLVOE_Pos) /**< Output disable for SPI transfer as slave */
452 /** @} */
453
454 /** @defgroup LL_QSPI_EC_TRANSFER_MODE Transfer Mode
455 * @{
456 */
457 #define LL_QSPI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
458 #define LL_QSPI_SIMPLEX_TX (1UL << QSPI_CTRL0_TMOD_Pos) /**< Simplex Tx mode. Tx transfer only on 1 line */
459 #define LL_QSPI_SIMPLEX_RX (2UL << QSPI_CTRL0_TMOD_Pos) /**< Simplex Rx mode. Rx transfer only on 1 line */
460 #define LL_QSPI_READ_EEPROM (3UL << QSPI_CTRL0_TMOD_Pos) /**< Read EEPROM mode. Rx transfer only on 1 line */
461 /** @} */
462
463 /** @defgroup LL_QSPI_EC_PHASE Clock Phase
464 * @{
465 */
466 #define LL_QSPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
467 #define LL_QSPI_SCPHA_2EDGE (1UL << QSPI_CTRL0_SCPHA_Pos) /**< Second clock transition is the first data capture edge */
468 /** @} */
469
470 /** @defgroup LL_QSPI_EC_POLARITY Clock Polarity
471 * @{
472 */
473 #define LL_QSPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
474 #define LL_QSPI_SCPOL_HIGH (1UL << QSPI_CTRL0_SCPOL_Pos) /**< Clock to 1 when idle */
475 /** @} */
476
477 /** @defgroup LL_QSPI_EC_PROTOCOL Serial Protocol
478 * @{
479 */
480 #define LL_QSPI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
481 #define LL_QSPI_PROTOCOL_TI (1UL << QSPI_CTRL0_FRF_Pos) /**< TI mode */
482 #define LL_QSPI_PROTOCOL_MICROWIRE (2UL << QSPI_CTRL0_FRF_Pos) /**< Microwire mode */
483 /** @} */
484
485 /** @defgroup LL_QSPI_EC_MICROWIRECONTROL MicroWire Control
486 * @{
487 */
488 #define LL_QSPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
489 #define LL_QSPI_MICROWIRE_HANDSHAKE_EN (1UL << QSPI_MWC_MHS_Pos) /**< Disable Handshake for Microwire transfer */
490
491 #define LL_QSPI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
492 #define LL_QSPI_MICROWIRE_TX (1UL << QSPI_MWC_MDD_Pos) /**< Tx mode. Tx transfer at Microwire mode */
493
494 #define LL_QSPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
495 #define LL_QSPI_MICROWIRE_SEQUENTIAL (1UL << QSPI_MWC_MWMOD_Pos) /**< Sequential for Microwire transfer */
496 /** @} */
497
498 /** @defgroup LL_QSPI_EC_SLAVESELECT Slave Select
499 * @{
500 */
501 #define LL_QSPI_SLAVE1 QSPI_SE_SLAVE1 /**< Enable slave1 select pin for SPI transfer */
502 #define LL_QSPI_SLAVE0 QSPI_SE_SLAVE0 /**< Enable slave0 select pin for SPI transfer */
503 /** @} */
504
505 /** @defgroup LL_QSPI_EC_DMA DMA Defines
506 * @{
507 */
508 #define LL_QSPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
509 #define LL_QSPI_DMA_TX_EN QSPI_DMAC_TDMAE /**< Enable the transmit FIFO DMA channel */
510
511 #define LL_QSPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
512 #define LL_QSPI_DMA_RX_EN QSPI_DMAC_RDMAE /**< Enable the receive FIFO DMA channel */
513 /** @} */
514
515 /** @defgroup LL_QSPI_EC_INSTRUCTIONSIZE QSPI Instruction Size
516 * @{
517 */
518 #define LL_QSPI_INSTSIZE_0BIT 0x00000000UL /**< Instruction length for QSPI transfer: 0 bits */
519 #define LL_QSPI_INSTSIZE_4BIT (1UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 4 bits */
520 #define LL_QSPI_INSTSIZE_8BIT (2UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 8 bits */
521 #define LL_QSPI_INSTSIZE_16BIT (3UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 16 bits */
522 /** @} */
523
524 /** @defgroup LL_QSPI_EC_ADDRESSSIZE QSPI Address Size
525 * @{
526 */
527 #define LL_QSPI_ADDRSIZE_0BIT 0x00000000UL /**< Address length for QSPI transfer: 0 bits */
528 #define LL_QSPI_ADDRSIZE_4BIT (1UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 4 bits */
529 #define LL_QSPI_ADDRSIZE_8BIT (2UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 8 bits */
530 #define LL_QSPI_ADDRSIZE_12BIT (3UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 12 bits */
531 #define LL_QSPI_ADDRSIZE_16BIT (4UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 16 bits */
532 #define LL_QSPI_ADDRSIZE_20BIT (5UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 20 bits */
533 #define LL_QSPI_ADDRSIZE_24BIT (6UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 24 bits */
534 #define LL_QSPI_ADDRSIZE_28BIT (7UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 28 bits */
535 #define LL_QSPI_ADDRSIZE_32BIT (8UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 32 bits */
536 #define LL_QSPI_ADDRSIZE_36BIT (9UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 36 bits */
537 #define LL_QSPI_ADDRSIZE_40BIT (10UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 40 bits */
538 #define LL_QSPI_ADDRSIZE_44BIT (11UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 44 bits */
539 #define LL_QSPI_ADDRSIZE_48BIT (12UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 48 bits */
540 #define LL_QSPI_ADDRSIZE_52BIT (13UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 52 bits */
541 #define LL_QSPI_ADDRSIZE_56BIT (14UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 56 bits */
542 #define LL_QSPI_ADDRSIZE_60BIT (15UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 60 bits */
543 /** @} */
544
545 /** @defgroup LL_QSPI_RX_SAMPLE_EDGE QSPI RX SAMPLE EDGE
546 * @{
547 */
548 #define LL_QSPI_RX_SAMPLE_POSITIVE_EDGE (0U)
549 #define LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE (1U)
550 /** @} */
551
552 /** @defgroup LL_QSPI_EC_ADDRINSTTRNASFERFORMAT QSPI Address and Instruction Transfer Format
553 * @{
554 */
555 #define LL_QSPI_INST_ADDR_ALL_IN_SPI 0x00000000UL /**< Instruction and address are sent in SPI mode */
556 #define LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << QSPI_SCTRL0_TRANSTYPE_Pos) /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
557 #define LL_QSPI_INST_ADDR_ALL_IN_SPIFRF (2UL << QSPI_SCTRL0_TRANSTYPE_Pos) /**< Instruction and address are sent in Daul/Quad SPI mode */
558 /** @} */
559
560
561 /** @defgroup LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE Endian mode For XIP
562 * @brief Endian mode for qspi xip
563 * @{
564 */
565 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 0u /* Default endian order from AHB */
566 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 1u /* Re-order the read data as [23:16], [31:24], [7:0], [15:8] */
567 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 2u /* Re-order the read data as [7:0], [15:8], [23:16], [31:24] */
568 /** @} */
569
570 /** @defgroup LL_QSPI_CONCURRENT_XIP_SLAVE Slave For XIP
571 * @brief Which Slave to Enable in XIP
572 * @{
573 */
574 #define LL_QSPI_CONCURRENT_XIP_SLAVE0 QSPI_XIP_SLAVE0_EN
575 /** @} */
576
577 /** @defgroup LL_QSPI_CONCURRENT_XIP_DFS Data Frame Size For Xip
578 * @brief Data frame size in xip, take effect when enable DFS_HC
579 * @{
580 */
581 #define LL_QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_DATASIZE_8BIT
582 #define LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_DATASIZE_16BIT
583 #define LL_QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_DATASIZE_32BIT
584 /** @} */
585
586 /** @defgroup LL_QSPI_CONCURRENT_XIP_MBL Mode Bits Length For Xip
587 * @brief Mode bits length for xip mode
588 * @{
589 */
590 #define LL_QSPI_CONCURRENT_XIP_MBL_2 0x0 /* mode bits length equals to 2 bit */
591 #define LL_QSPI_CONCURRENT_XIP_MBL_4 0x1 /* mode bits length equals to 4 bit */
592 #define LL_QSPI_CONCURRENT_XIP_MBL_8 0x2 /* mode bits length equals to 8 bit */
593 #define LL_QSPI_CONCURRENT_XIP_MBL_16 0x3 /* mode bits length equals to 16 bit */
594 /** @} */
595
596 /** @defgroup LL_QSPI_CONCURRENT_XIP_INSTSIZE Instruction Size For Xip
597 * @brief Instruction size for concurrent xip mode
598 * @{
599 */
600 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT 0x0 /* no instruction */
601 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT 0x1 /* instruction size equals 4bits */
602 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT 0x2 /* instruction size equals 8bits */
603 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT 0x3 /* instruction size equals 16bits */
604 /** @} */
605
606 /** @defgroup LL_QSPI_CONCURRENT_XIP_ADDRSIZE Address Size For Xip
607 * @brief Address size for concurrent xip mode
608 * @{
609 */
610 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT 0x0 /**< Address length for QSPI XIP transfer: 0 bits */
611 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT 0x1 /**< Address length for QSPI XIP transfer: 4 bits */
612 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT 0x2 /**< Address length for QSPI XIP transfer: 8 bits */
613 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT 0x3 /**< Address length for QSPI XIP transfer: 12 bits */
614 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT 0x4 /**< Address length for QSPI XIP transfer: 16 bits */
615 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT 0x5 /**< Address length for QSPI XIP transfer: 20 bits */
616 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT 0x6 /**< Address length for QSPI XIP transfer: 24 bits */
617 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT 0x7 /**< Address length for QSPI XIP transfer: 28 bits */
618 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT 0x8 /**< Address length for QSPI XIP transfer: 32 bits */
619 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT 0x9 /**< Address length for QSPI XIP transfer: 36 bits */
620 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT 0xA /**< Address length for QSPI XIP transfer: 40 bits */
621 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT 0xB /**< Address length for QSPI XIP transfer: 44 bits */
622 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT 0xC /**< Address length for QSPI XIP transfer: 48 bits */
623 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT 0xD /**< Address length for QSPI XIP transfer: 52 bits */
624 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT 0xE /**< Address length for QSPI XIP transfer: 56 bits */
625 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT 0xF /**< Address length for QSPI XIP transfer: 60 bits */
626 /** @} */
627
628 /** @defgroup LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT Instruction And Address For Xip
629 * @brief Transfer of inst & address for concurrent xip mode
630 * @{
631 */
632 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI 0x0 /**< Instruction and address are sent in SPI mode */
633 #define LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF 0x1 /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
634 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF 0x2 /**< Instruction and address are sent in Daul/Quad SPI mode */
635 /** @} */
636
637 /** @defgroup LL_QSPI_CONCURRENT_XIP_FRF Frame Format For Xip
638 * @brief Frame format for concurrent xip mode
639 * @{
640 */
641 #define LL_QSPI_CONCURRENT_XIP_FRF_RSVD 0x0 /**< SPI Frame format : Reserved */
642 #define LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI 0x1 /**< SPI Frame format : DUAL */
643 #define LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI 0x2 /**< SPI Frame format : QUAD */
644 #define LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI 0x3 /**< SPI Frame format : OCTAL */
645 /** @} */
646
647 /** @defgroup LL_QSPI_XIP_CLK_STRETCH Mode Clock stretch mode
648 * @{
649 */
650 #define LL_QSPI_CLK_STRETCH_ENABLE 1u
651 #define LL_QSPI_CLK_STRETCH_DISABLE 0u
652 /** @} */
653
654 /** @defgroup LL_QSPI_XIP_PREFETCH Prefetch Defines
655 * @{
656 */
657 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE 1u
658 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE 0u
659 /** @} */
660
661 /** @defgroup LL_QSPI_XIP_CONT_XFERR CONT XFERR Defines
662 * @{
663 */
664 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE 1u
665 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE 0u
666 /** @} */
667
668 /** @defgroup LL_QSPI_XIP_INST_PHASE Instruction Defines
669 * @{
670 */
671 #define LL_QSPI_CONCURRENT_XIP_INST_ENABLE 1u
672 #define LL_QSPI_CONCURRENT_XIP_INST_DISABLE 0u
673 /** @} */
674
675 /** @defgroup LL_QSPI_XIP_MODE_BITS_PHASE Mode Bits Defines
676 * @{
677 */
678 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE 1u
679 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE 0u
680 /** @} */
681
682 /** @defgroup LL_QSPI_XIP_DFS_HC DFS Hardcode Defines
683 * @{
684 */
685 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE 1u
686 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE 0u
687 /** @} */
688
689 /** @defgroup LL_QSPI_CONCURRENT_XIP_INST_SENT_MODE Instruction Sent Mode
690 * @{
691 */
692 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS 0u /*!< Send instruction for every transaction */
693 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS 1u /*!< Send instruction only for first transaction */
694 /** @} */
695
696
697 /** @defgroup LL_QSPI_EC_DEFAULT_CONFIG InitStrcut default configuartion
698 * @{
699 */
700
701 /**
702 * @brief LL QSPI InitStrcut default configuartion
703 */
704 #define LL_QSPI_DEFAULT_CONFIG \
705 { \
706 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
707 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
708 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
709 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
710 .wait_cycles = 0, \
711 .data_size = LL_QSPI_DATASIZE_8BIT, \
712 .clock_polarity = LL_QSPI_SCPOL_LOW, \
713 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
714 .baud_rate = SystemCoreClock / 1000000, \
715 .rx_sample_delay = 0, \
716 }
717
718
719
720 #define LL_CONC_QSPI_DEFAULT_CONFIG \
721 { \
722 .baud_rate = SystemCoreClock / 1000000, \
723 .clock_polarity = LL_QSPI_SCPOL_LOW, \
724 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
725 .data_size = LL_QSPI_DATASIZE_8BIT, \
726 .clock_stretch_en = LL_QSPI_CLK_STRETCH_DISABLE, \
727 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
728 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
729 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
730 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
731 .wait_cycles = 0, \
732 .rx_sample_delay = 0, \
733 .data_beats = 0, \
734 .tx_start_fifo_threshold = 0, \
735 .tx_fifo_threshold = 0, \
736 .rx_fifo_threshold = 0, \
737 .dma_tx_fifo_level = 0, \
738 .dma_rx_fifo_level = 0, \
739 \
740 .x_prefetch_en = LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE, \
741 .x_continous_xfer_en = LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE, \
742 .x_continous_xfer_toc = 0x00, \
743 .x_dfs_hardcode_en = LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE, \
744 .x_mode_bits_en = LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE, \
745 .x_mode_bits_length = LL_QSPI_CONCURRENT_XIP_MBL_8, \
746 .x_mode_bits_data = 0x00, \
747 .x_instruction_en = LL_QSPI_CONCURRENT_XIP_INST_DISABLE, \
748 .x_instruction_size = LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT, \
749 .x_instruction = 0x00, \
750 .x_address_size = LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT,\
751 .x_inst_addr_transfer_format = LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF, \
752 .x_dummy_cycles = 0x00, \
753 .x_data_frame_format = LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI, \
754 }
755
756 /** @} */
757
758 /** @} */
759
760 /* Exported macro ------------------------------------------------------------*/
761 /** @defgroup LL_QSPI_Exported_Macros QSPI Exported Macros
762 * @{
763 */
764
765 /** @defgroup LL_QSPI_EM_WRITE_READ Common Write and read registers Macros
766 * @{
767 */
768
769 /**
770 * @brief Write a value in QSPI register
771 * @param __instance__ QSPI instance
772 * @param __REG__ Register to be written
773 * @param __VALUE__ Value to be written in the register
774 * @retval None
775 */
776 #define LL_QSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
777
778 /**
779 * @brief Read a value in QSPI register
780 * @param __instance__ QSPI instance
781 * @param __REG__ Register to be read
782 * @retval Register value
783 */
784 #define LL_QSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
785
786 /** @} */
787
788 /** @} */
789
790 /** @} */
791
792 /* Exported functions --------------------------------------------------------*/
793 /** @defgroup LL_QSPI_DRIVER_FUNCTIONS Functions
794 * @{
795 */
796
797 /** @defgroup LL_QSPI_EF_Configuration Configuration functions
798 * @{
799 */
800
801 /**
802 * @brief Enable slave select toggle
803 * @note This bit should not be changed when communication is ongoing.
804 *
805 * Register|BitsName
806 * --------|--------
807 * CTRL0 | SSTEN
808 *
809 * @param QSPIx QSPI instance
810 * @retval None
811 */
812 __STATIC_INLINE void ll_qspi_enable_ss_toggle(qspi_regs_t *QSPIx)
813 {
814 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
815 }
816
817 /**
818 * @brief Disable slave select toggle
819 * @note This bit should not be changed when communication is ongoing.
820 *
821 * Register|BitsName
822 * --------|--------
823 * CTRL0 | SSTEN
824 *
825 * @param QSPIx QSPI instance
826 * @retval None
827 */
828 __STATIC_INLINE void ll_qspi_disable_ss_toggle(qspi_regs_t *QSPIx)
829 {
830 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
831 }
832
833 /**
834 * @brief Check if slave select toggle is enabled
835 * @note This bit should not be changed when communication is ongoing.
836 *
837 * Register|BitsName
838 * --------|--------
839 * CTRL0 | SSTEN
840 *
841 * @param QSPIx QSPI instance
842 * @retval State of bit (1 or 0).
843 */
844 __STATIC_INLINE uint32_t ll_qspi_is_enabled_ss_toggle(qspi_regs_t *QSPIx)
845 {
846 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN) == (QSPI_CTRL0_SSTEN));
847 }
848
849 /**
850 * @brief Set data frame format for transmitting/receiving the data
851 * @note This bit should be written only when QSPI is disabled (QSPI_SSI_EN = 0) for correct operation.
852 *
853 * Register|BitsName
854 * --------|--------
855 * CTRL0 | SPIFRF
856 *
857 * @param QSPIx QSPI instance
858 * @param frf This parameter can be one of the following values:
859 * @arg @ref LL_QSPI_FRF_SPI
860 * @arg @ref LL_QSPI_FRF_DUALSPI
861 * @arg @ref LL_QSPI_FRF_QUADSPI
862 * @retval None
863 */
864 __STATIC_INLINE void ll_qspi_set_frame_format(qspi_regs_t *QSPIx, uint32_t frf)
865 {
866 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF, frf);
867 }
868
869 /**
870 * @brief Get data frame format for transmitting/receiving the data
871 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
872 *
873 * Register|BitsName
874 * --------|--------
875 * CTRL0 | SPIFRF
876 *
877 * @param QSPIx QSPI instance
878 * @retval Returned value can be one of the following values:
879 * @arg @ref LL_QSPI_FRF_SPI
880 * @arg @ref LL_QSPI_FRF_DUALSPI
881 * @arg @ref LL_QSPI_FRF_QUADSPI
882 */
883 __STATIC_INLINE uint32_t ll_qspi_get_frame_format(qspi_regs_t *QSPIx)
884 {
885 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF));
886 }
887
888 /**
889 * @brief Set frame data size
890 *
891 * Register|BitsName
892 * --------|--------
893 * CTRL0 | DFS32
894 *
895 * @param QSPIx QSPI instance
896 * @param size This parameter can be one of the following values:
897 * @arg @ref LL_QSPI_DATASIZE_4BIT
898 * @arg @ref LL_QSPI_DATASIZE_5BIT
899 * @arg @ref LL_QSPI_DATASIZE_6BIT
900 * @arg @ref LL_QSPI_DATASIZE_7BIT
901 * @arg @ref LL_QSPI_DATASIZE_8BIT
902 * @arg @ref LL_QSPI_DATASIZE_9BIT
903 * @arg @ref LL_QSPI_DATASIZE_10BIT
904 * @arg @ref LL_QSPI_DATASIZE_11BIT
905 * @arg @ref LL_QSPI_DATASIZE_12BIT
906 * @arg @ref LL_QSPI_DATASIZE_13BIT
907 * @arg @ref LL_QSPI_DATASIZE_14BIT
908 * @arg @ref LL_QSPI_DATASIZE_15BIT
909 * @arg @ref LL_QSPI_DATASIZE_16BIT
910 * @arg @ref LL_QSPI_DATASIZE_17BIT
911 * @arg @ref LL_QSPI_DATASIZE_18BIT
912 * @arg @ref LL_QSPI_DATASIZE_19BIT
913 * @arg @ref LL_QSPI_DATASIZE_20BIT
914 * @arg @ref LL_QSPI_DATASIZE_21BIT
915 * @arg @ref LL_QSPI_DATASIZE_22BIT
916 * @arg @ref LL_QSPI_DATASIZE_23BIT
917 * @arg @ref LL_QSPI_DATASIZE_24BIT
918 * @arg @ref LL_QSPI_DATASIZE_25BIT
919 * @arg @ref LL_QSPI_DATASIZE_26BIT
920 * @arg @ref LL_QSPI_DATASIZE_27BIT
921 * @arg @ref LL_QSPI_DATASIZE_28BIT
922 * @arg @ref LL_QSPI_DATASIZE_29BIT
923 * @arg @ref LL_QSPI_DATASIZE_30BIT
924 * @arg @ref LL_QSPI_DATASIZE_31BIT
925 * @arg @ref LL_QSPI_DATASIZE_32BIT
926 * @retval None
927 */
928 __STATIC_INLINE void ll_qspi_set_data_size(qspi_regs_t *QSPIx, uint32_t size)
929 {
930 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_DFS32, size);
931 }
932
933 /**
934 * @brief Get frame data size
935 *
936 * Register|BitsName
937 * --------|--------
938 * CTRL0 | DFS32
939 *
940 * @param QSPIx QSPI instance
941 * @retval Returned value can be one of the following values:
942 * @arg @ref LL_QSPI_DATASIZE_4BIT
943 * @arg @ref LL_QSPI_DATASIZE_5BIT
944 * @arg @ref LL_QSPI_DATASIZE_6BIT
945 * @arg @ref LL_QSPI_DATASIZE_7BIT
946 * @arg @ref LL_QSPI_DATASIZE_8BIT
947 * @arg @ref LL_QSPI_DATASIZE_9BIT
948 * @arg @ref LL_QSPI_DATASIZE_10BIT
949 * @arg @ref LL_QSPI_DATASIZE_11BIT
950 * @arg @ref LL_QSPI_DATASIZE_12BIT
951 * @arg @ref LL_QSPI_DATASIZE_13BIT
952 * @arg @ref LL_QSPI_DATASIZE_14BIT
953 * @arg @ref LL_QSPI_DATASIZE_15BIT
954 * @arg @ref LL_QSPI_DATASIZE_16BIT
955 * @arg @ref LL_QSPI_DATASIZE_17BIT
956 * @arg @ref LL_QSPI_DATASIZE_18BIT
957 * @arg @ref LL_QSPI_DATASIZE_19BIT
958 * @arg @ref LL_QSPI_DATASIZE_20BIT
959 * @arg @ref LL_QSPI_DATASIZE_21BIT
960 * @arg @ref LL_QSPI_DATASIZE_22BIT
961 * @arg @ref LL_QSPI_DATASIZE_23BIT
962 * @arg @ref LL_QSPI_DATASIZE_24BIT
963 * @arg @ref LL_QSPI_DATASIZE_25BIT
964 * @arg @ref LL_QSPI_DATASIZE_26BIT
965 * @arg @ref LL_QSPI_DATASIZE_27BIT
966 * @arg @ref LL_QSPI_DATASIZE_28BIT
967 * @arg @ref LL_QSPI_DATASIZE_29BIT
968 * @arg @ref LL_QSPI_DATASIZE_30BIT
969 * @arg @ref LL_QSPI_DATASIZE_31BIT
970 * @arg @ref LL_QSPI_DATASIZE_32BIT
971 */
972 __STATIC_INLINE uint32_t ll_qspi_get_data_size(qspi_regs_t *QSPIx)
973 {
974 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DFS32));
975 }
976
977 /**
978 * @brief Set the length of the control word for the Microwire frame format
979 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
980 *
981 * Register|BitsName
982 * --------|--------
983 * CTRL0 | CFS
984 *
985 * @param QSPIx QSPI instance
986 * @param size This parameter can be one of the following values:
987 * @arg @ref LL_QSPI_MW_CMDSIZE_1BIT
988 * @arg @ref LL_QSPI_MW_CMDSIZE_2BIT
989 * @arg @ref LL_QSPI_MW_CMDSIZE_3BIT
990 * @arg @ref LL_QSPI_MW_CMDSIZE_4BIT
991 * @arg @ref LL_QSPI_MW_CMDSIZE_5BIT
992 * @arg @ref LL_QSPI_MW_CMDSIZE_6BIT
993 * @arg @ref LL_QSPI_MW_CMDSIZE_7BIT
994 * @arg @ref LL_QSPI_MW_CMDSIZE_8BIT
995 * @arg @ref LL_QSPI_MW_CMDSIZE_9BIT
996 * @arg @ref LL_QSPI_MW_CMDSIZE_10BIT
997 * @arg @ref LL_QSPI_MW_CMDSIZE_11BIT
998 * @arg @ref LL_QSPI_MW_CMDSIZE_12BIT
999 * @arg @ref LL_QSPI_MW_CMDSIZE_13BIT
1000 * @arg @ref LL_QSPI_MW_CMDSIZE_14BIT
1001 * @arg @ref LL_QSPI_MW_CMDSIZE_15BIT
1002 * @arg @ref LL_QSPI_MW_CMDSIZE_16BIT
1003 * @retval None
1004 */
1005 __STATIC_INLINE void ll_qspi_set_control_frame_size(qspi_regs_t *QSPIx, uint32_t size)
1006 {
1007 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_CFS, size);
1008 }
1009
1010 /**
1011 * @brief Get the length of the control word for the Microwire frame format
1012 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
1013 *
1014 * Register|BitsName
1015 * --------|--------
1016 * CTRL0 | CFS
1017 *
1018 * @param QSPIx QSPI instance
1019 * @retval Returned value can be one of the following values:
1020 * @arg @ref LL_QSPI_MW_CMDSIZE_1BIT
1021 * @arg @ref LL_QSPI_MW_CMDSIZE_2BIT
1022 * @arg @ref LL_QSPI_MW_CMDSIZE_3BIT
1023 * @arg @ref LL_QSPI_MW_CMDSIZE_4BIT
1024 * @arg @ref LL_QSPI_MW_CMDSIZE_5BIT
1025 * @arg @ref LL_QSPI_MW_CMDSIZE_6BIT
1026 * @arg @ref LL_QSPI_MW_CMDSIZE_7BIT
1027 * @arg @ref LL_QSPI_MW_CMDSIZE_8BIT
1028 * @arg @ref LL_QSPI_MW_CMDSIZE_9BIT
1029 * @arg @ref LL_QSPI_MW_CMDSIZE_10BIT
1030 * @arg @ref LL_QSPI_MW_CMDSIZE_11BIT
1031 * @arg @ref LL_QSPI_MW_CMDSIZE_12BIT
1032 * @arg @ref LL_QSPI_MW_CMDSIZE_13BIT
1033 * @arg @ref LL_QSPI_MW_CMDSIZE_14BIT
1034 * @arg @ref LL_QSPI_MW_CMDSIZE_15BIT
1035 * @arg @ref LL_QSPI_MW_CMDSIZE_16BIT
1036 */
1037 __STATIC_INLINE uint32_t ll_qspi_get_control_frame_size(qspi_regs_t *QSPIx)
1038 {
1039 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_CFS));
1040 }
1041
1042 /**
1043 * @brief Enable SPI test mode
1044 *
1045 * Register|BitsName
1046 * --------|--------
1047 * CTRL0 | SRL
1048 *
1049 * @param QSPIx QSPI instance
1050 * @retval None
1051 */
1052 __STATIC_INLINE void ll_qspi_enable_test_mode(qspi_regs_t *QSPIx)
1053 {
1054 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1055 }
1056
1057 /**
1058 * @brief Disable SPI test mode
1059 *
1060 * Register|BitsName
1061 * --------|--------
1062 * CTRL0 | SRL
1063 *
1064 * @param QSPIx QSPI instance
1065 * @retval None
1066 */
1067 __STATIC_INLINE void ll_qspi_disable_test_mode(qspi_regs_t *QSPIx)
1068 {
1069 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1070 }
1071
1072 /**
1073 * @brief Check if SPI test mode is enabled
1074 *
1075 * Register|BitsName
1076 * --------|--------
1077 * CTRL0 | SRL
1078 *
1079 * @param QSPIx QSPI instance
1080 * @retval State of bit (1 or 0).
1081 */
1082 __STATIC_INLINE uint32_t ll_qspi_is_enabled_test_mode(qspi_regs_t *QSPIx)
1083 {
1084 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL) == (QSPI_CTRL0_SRL));
1085 }
1086
1087 /**
1088 * @brief Enable slave output
1089 *
1090 * Register|BitsName
1091 * --------|--------
1092 * CTRL0 | SLVOE
1093 *
1094 * @param QSPIx QSPI instance
1095 * @retval None
1096 */
1097 __STATIC_INLINE void ll_qspi_enable_slave_out(qspi_regs_t *QSPIx)
1098 {
1099 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1100 }
1101
1102 /**
1103 * @brief Disable slave output
1104 *
1105 * Register|BitsName
1106 * --------|--------
1107 * CTRL0 | SLVOE
1108 *
1109 * @param QSPIx QSPI instance
1110 * @retval None
1111 */
1112 __STATIC_INLINE void ll_qspi_disable_salve_out(qspi_regs_t *QSPIx)
1113 {
1114 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1115 }
1116
1117 /**
1118 * @brief Check if slave output is enabled
1119 *
1120 * Register|BitsName
1121 * --------|--------
1122 * CTRL0 | SLVOE
1123 *
1124 * @param QSPIx QSPI instance
1125 * @retval State of bit (1 or 0).
1126 */
1127 __STATIC_INLINE uint32_t ll_qspi_is_enabled_slave_out(qspi_regs_t *QSPIx)
1128 {
1129 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE) != (QSPI_CTRL0_SLVOE));
1130 }
1131
1132 /**
1133 * @brief Set transfer direction mode
1134 *
1135 * Register|BitsName
1136 * --------|--------
1137 * CTRL0 | TMOD
1138 *
1139 * @param QSPIx QSPI instance
1140 * @param transfer_direction This parameter can be one of the following values:
1141 * @arg @ref LL_QSPI_FULL_DUPLEX
1142 * @arg @ref LL_QSPI_SIMPLEX_TX
1143 * @arg @ref LL_QSPI_SIMPLEX_RX
1144 * @arg @ref LL_QSPI_READ_EEPROM
1145 * @retval None
1146 */
1147 __STATIC_INLINE void ll_qspi_set_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
1148 {
1149 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_TMOD, transfer_direction);
1150 }
1151
1152 /**
1153 * @brief Get transfer direction mode
1154 *
1155 * Register|BitsName
1156 * --------|--------
1157 * CTRL0 | TMOD
1158 *
1159 * @param QSPIx QSPI instance
1160 * @retval Returned value can be one of the following values:
1161 * @arg @ref LL_QSPI_FULL_DUPLEX
1162 * @arg @ref LL_QSPI_SIMPLEX_TX
1163 * @arg @ref LL_QSPI_SIMPLEX_RX
1164 * @arg @ref LL_QSPI_READ_EEPROM
1165 */
1166 __STATIC_INLINE uint32_t ll_qspi_get_transfer_direction(qspi_regs_t *QSPIx)
1167 {
1168 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_TMOD));
1169 }
1170
1171 /**
1172 * @brief Set clock polarity
1173 * @note This bit should not be changed when communication is ongoing.
1174 * This bit is not used in SPI TI mode.
1175 *
1176 * Register|BitsName
1177 * --------|--------
1178 * CTRL0 | SCPOL
1179 *
1180 * @param QSPIx QSPI instance
1181 * @param clock_polarity This parameter can be one of the following values:
1182 * @arg @ref LL_QSPI_SCPOL_LOW
1183 * @arg @ref LL_QSPI_SCPOL_HIGH
1184 * @retval None
1185 */
1186 __STATIC_INLINE void ll_qspi_set_clock_polarity(qspi_regs_t *QSPIx, uint32_t clock_polarity)
1187 {
1188 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPOL, clock_polarity);
1189 }
1190
1191 /**
1192 * @brief Get clock polarity
1193 *
1194 * Register|BitsName
1195 * --------|--------
1196 * CTRL0 | SCPOL
1197 *
1198 * @param QSPIx QSPI instance
1199 * @retval Returned value can be one of the following values:
1200 * @arg @ref LL_QSPI_SCPOL_LOW
1201 * @arg @ref LL_QSPI_SCPOL_HIGH
1202 */
1203 __STATIC_INLINE uint32_t ll_qspi_get_clock_polarity(qspi_regs_t *QSPIx)
1204 {
1205 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPOL));
1206 }
1207
1208 /**
1209 * @brief Set clock phase
1210 * @note This bit should not be changed when communication is ongoing.
1211 * This bit is not used in SPI TI mode.
1212 *
1213 * Register|BitsName
1214 * --------|--------
1215 * CTRL0 | SCPHA
1216 *
1217 * @param QSPIx QSPI instance
1218 * @param clock_phase This parameter can be one of the following values:
1219 * @arg @ref LL_QSPI_SCPHA_1EDGE
1220 * @arg @ref LL_QSPI_SCPHA_2EDGE
1221 * @retval None
1222 */
1223 __STATIC_INLINE void ll_qspi_set_clock_phase(qspi_regs_t *QSPIx, uint32_t clock_phase)
1224 {
1225 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPHA, clock_phase);
1226 }
1227
1228 /**
1229 * @brief Get clock phase
1230 *
1231 * Register|BitsName
1232 * --------|--------
1233 * CTRL0 | SCPHA
1234 *
1235 * @param QSPIx QSPI instance
1236 * @retval Returned value can be one of the following values:
1237 * @arg @ref LL_QSPI_SCPHA_1EDGE
1238 * @arg @ref LL_QSPI_SCPHA_2EDGE
1239 */
1240 __STATIC_INLINE uint32_t ll_qspi_get_clock_phase(qspi_regs_t *QSPIx)
1241 {
1242 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPHA));
1243 }
1244
1245 /**
1246 * @brief Set serial protocol used
1247 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
1248 *
1249 * Register|BitsName
1250 * --------|--------
1251 * CTRL0 | FRF
1252 *
1253 * @param QSPIx QSPI instance
1254 * @param standard This parameter can be one of the following values:
1255 * @arg @ref LL_QSPI_PROTOCOL_MOTOROLA
1256 * @arg @ref LL_QSPI_PROTOCOL_TI
1257 * @arg @ref LL_QSPI_PROTOCOL_MICROWIRE
1258 * @retval None
1259 */
1260 __STATIC_INLINE void ll_qspi_set_standard(qspi_regs_t *QSPIx, uint32_t standard)
1261 {
1262 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_FRF, standard);
1263 }
1264
1265 /**
1266 * @brief Get serial protocol used
1267 *
1268 * Register|BitsName
1269 * --------|--------
1270 * CTRL0 | FRF
1271 *
1272 * @param QSPIx QSPI instance
1273 * @retval Returned value can be one of the following values:
1274 * @arg @ref LL_QSPI_PROTOCOL_MOTOROLA
1275 * @arg @ref LL_QSPI_PROTOCOL_TI
1276 * @arg @ref LL_QSPI_PROTOCOL_MICROWIRE
1277 */
1278 __STATIC_INLINE uint32_t ll_qspi_get_standard(qspi_regs_t *QSPIx)
1279 {
1280 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_FRF));
1281 }
1282
1283 /**
1284 * @brief Set the number of data frames to be continuously received
1285 * @note These bits should not be changed when communication is ongoing.
1286 This bits are effect when TMOD = 2b10 or 2b11.
1287 This bits are not effect in SPIS.
1288 *
1289 * Register|BitsName
1290 * --------|--------
1291 * CTRL1 | NDF
1292 *
1293 * @param QSPIx QSPI instance
1294 * @param size This parameter can be one of the following values: 0 ~ 65535
1295 * @retval None
1296 */
1297 __STATIC_INLINE void ll_qspi_set_receive_size(qspi_regs_t *QSPIx, uint32_t size)
1298 {
1299 MODIFY_REG(QSPIx->CTRL1, QSPI_CTRL1_NDF, size);
1300 }
1301
1302 #define ll_qspi_set_xfer_size ll_qspi_set_receive_size
1303
1304 /**
1305 * @brief Get the number of data frames to be continuously received
1306 * @note These bits should not be changed when communication is ongoing.
1307 This bits are effect when TMOD = 2b10 or 2b11.
1308 This bits are not effect in SPIS.
1309 *
1310 * Register|BitsName
1311 * --------|--------
1312 * CTRL1 | NDF
1313 *
1314 * @param QSPIx QSPI instance
1315 * @retval Returned value can be one of the following values: 0 ~ 65535
1316 */
1317 __STATIC_INLINE uint32_t ll_qspi_get_receive_size(qspi_regs_t *QSPIx)
1318 {
1319 return (uint32_t)(READ_BITS(QSPIx->CTRL1, QSPI_CTRL1_NDF));
1320 }
1321
1322 /**
1323 * @brief Enable SPI peripheral
1324 *
1325 * Register|BitsName
1326 * --------|--------
1327 * QSPI_EN | EN
1328 *
1329 * @param QSPIx QSPI instance
1330 * @retval None
1331 */
1332 __STATIC_INLINE void ll_qspi_enable(qspi_regs_t *QSPIx)
1333 {
1334 SET_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1335 }
1336
1337 /**
1338 * @brief Disable SPI peripheral
1339 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
1340 *
1341 * Register|BitsName
1342 * --------|--------
1343 * QSPI_EN | EN
1344 *
1345 * @param QSPIx QSPI instance
1346 * @retval None
1347 */
1348 __STATIC_INLINE void ll_qspi_disable(qspi_regs_t *QSPIx)
1349 {
1350 CLEAR_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1351 }
1352
1353 /**
1354 * @brief Check if SPI peripheral is enabled
1355 *
1356 * Register|BitsName
1357 * --------|--------
1358 * QSPI_EN | EN
1359 *
1360 * @param QSPIx QSPI instance
1361 * @retval State of bit (1 or 0).
1362 */
1363 __STATIC_INLINE uint32_t ll_qspi_is_enabled(qspi_regs_t *QSPIx)
1364 {
1365 return (READ_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN) == (QSPI_SSI_EN));
1366 }
1367
1368 /**
1369 * @brief Enable Handshake in Microwire mode
1370 *
1371 * Register|BitsName
1372 * --------|--------
1373 * MWC | MHS
1374 *
1375 * @param QSPIx QSPI instance
1376 * @retval None
1377 */
1378 __STATIC_INLINE void ll_qspi_enable_micro_handshake(qspi_regs_t *QSPIx)
1379 {
1380 SET_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1381 }
1382
1383 /**
1384 * @brief Disable Handshake in Microwire mode
1385 *
1386 * Register|BitsName
1387 * --------|--------
1388 * MWC | MHS
1389 *
1390 * @param QSPIx QSPI instance
1391 * @retval None
1392 */
1393 __STATIC_INLINE void ll_qspi_disable_micro_handshake(qspi_regs_t *QSPIx)
1394 {
1395 CLEAR_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1396 }
1397
1398 /**
1399 * @brief Check if Handshake in Microwire mode is enabled
1400 *
1401 * Register|BitsName
1402 * --------|--------
1403 * MWC | MHS
1404 *
1405 * @param QSPIx QSPI instance
1406 * @retval State of bit (1 or 0).
1407 */
1408 __STATIC_INLINE uint32_t ll_qspi_is_enabled_micro_handshake(qspi_regs_t *QSPIx)
1409 {
1410 return (READ_BITS(QSPIx->MWC, QSPI_MWC_MHS) == (QSPI_MWC_MHS));
1411 }
1412
1413 /**
1414 * @brief Set transfer direction mode in Microwire mode
1415 * @note This bit should not be changed when communication is ongoing.
1416 *
1417 * Register|BitsName
1418 * --------|--------
1419 * MWC | MDD
1420 *
1421 * @param QSPIx QSPI instance
1422 * @param transfer_direction This parameter can be one of the following values:
1423 * @arg @ref LL_QSPI_MICROWIRE_RX
1424 * @arg @ref LL_QSPI_MICROWIRE_TX
1425 * @retval None
1426 */
1427 __STATIC_INLINE void ll_qspi_set_micro_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
1428 {
1429 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MDD, transfer_direction);
1430 }
1431
1432 /**
1433 * @brief Get transfer direction mode in Microwire mode
1434 * @note This bit should not be changed when communication is ongoing.
1435 *
1436 * Register|BitsName
1437 * --------|--------
1438 * MWC | MDD
1439 *
1440 * @param QSPIx QSPI instance
1441 * @retval Returned value can be one of the following values:
1442 * @arg @ref LL_QSPI_MICROWIRE_RX
1443 * @arg @ref LL_QSPI_MICROWIRE_TX
1444 */
1445 __STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_direction(qspi_regs_t *QSPIx)
1446 {
1447 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MDD));
1448 }
1449
1450 /**
1451 * @brief Set transfer mode in Microwire mode
1452 * @note This bit should not be changed when communication is ongoing.
1453 *
1454 * Register|BitsName
1455 * --------|--------
1456 * MWC | MWMOD
1457 *
1458 * @param QSPIx QSPI instance
1459 * @param transfer_mode This parameter can be one of the following values:
1460 * @arg @ref LL_QSPI_MICROWIRE_NON_SEQUENTIAL
1461 * @arg @ref LL_QSPI_MICROWIRE_SEQUENTIAL
1462 * @retval None
1463 */
1464 __STATIC_INLINE void ll_qspi_set_micro_transfer_mode(qspi_regs_t *QSPIx, uint32_t transfer_mode)
1465 {
1466 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MWMOD, transfer_mode);
1467 }
1468
1469 /**
1470 * @brief Get transfer mode in Microwire mode
1471 * @note This bit should not be changed when communication is ongoing.
1472 *
1473 * Register|BitsName
1474 * --------|--------
1475 * MWC | MWMOD
1476 *
1477 * @param QSPIx QSPI instance
1478 * @retval Returned value can be one of the following values:
1479 * @arg @ref LL_QSPI_MICROWIRE_NON_SEQUENTIAL
1480 * @arg @ref LL_QSPI_MICROWIRE_SEQUENTIAL
1481 */
1482 __STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_mode(qspi_regs_t *QSPIx)
1483 {
1484 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MWMOD));
1485 }
1486
1487 /**
1488 * @brief Enable slave select
1489 *
1490 * Register|BitsName
1491 * --------|--------
1492 * SE | SLAVE1
1493 * SE | SLAVE0
1494 *
1495 * @param QSPIx QSPI instance
1496 * @param ss This parameter can be one of the following values:
1497 * @arg @ref LL_QSPI_SLAVE1
1498 * @arg @ref LL_QSPI_SLAVE0
1499 * @retval None
1500 */
1501 __STATIC_INLINE void ll_qspi_enable_ss(qspi_regs_t *QSPIx, uint32_t ss)
1502 {
1503 SET_BITS(QSPIx->SE, ss);
1504 }
1505
1506 /**
1507 * @brief Disable slave select
1508 *
1509 * Register|BitsName
1510 * --------|--------
1511 * SE | SLAVE1
1512 * SE | SLAVE0
1513 *
1514 * @param QSPIx QSPI instance
1515 * @param ss This parameter can be one of the following values:
1516 * @arg @ref LL_QSPI_SLAVE1
1517 * @arg @ref LL_QSPI_SLAVE0
1518 * @retval None
1519 */
1520 __STATIC_INLINE void ll_qspi_disable_ss(qspi_regs_t *QSPIx, uint32_t ss)
1521 {
1522 CLEAR_BITS(QSPIx->SE, ss);
1523 }
1524
1525 /**
1526 * @brief Check if slave select is enabled
1527 *
1528 * Register|BitsName
1529 * --------|--------
1530 * SE | SLAVE1
1531 * SE | SLAVE0
1532 *
1533 * @param QSPIx QSPI instance
1534 * @param ss This parameter can be one of the following values:
1535 * @arg @ref LL_QSPI_SLAVE1
1536 * @arg @ref LL_QSPI_SLAVE0
1537 * @retval State of bit (1 or 0).
1538 */
1539 __STATIC_INLINE uint32_t ll_qspi_is_enabled_ss(qspi_regs_t *QSPIx, uint32_t ss)
1540 {
1541 return (READ_BITS(QSPIx->SE, ss) == ss);
1542 }
1543
1544 /**
1545 * @brief Set baud rate prescaler
1546 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1547 *
1548 * Register|BitsName
1549 * --------|--------
1550 * BAUD | SCKDIV
1551 *
1552 * @param QSPIx QSPI instance
1553 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1554 * @retval None
1555 */
1556 __STATIC_INLINE void ll_qspi_set_baud_rate_prescaler(qspi_regs_t *QSPIx, uint32_t baud_rate)
1557 {
1558 WRITE_REG(QSPIx->BAUD, baud_rate & QSPI_BAUD_SCKDIV);
1559 }
1560
1561 /**
1562 * @brief Get baud rate prescaler
1563 *
1564 * Register|BitsName
1565 * --------|--------
1566 * BAUD | SCKDIV
1567 *
1568 * @param QSPIx QSPI instance
1569 * @retval Returned value can be one even value between 2 and 65534.
1570 */
1571 __STATIC_INLINE uint32_t ll_qspi_get_baud_rate_prescaler(qspi_regs_t *QSPIx)
1572 {
1573 return (uint32_t)(READ_BITS(QSPIx->BAUD, QSPI_BAUD_SCKDIV));
1574 }
1575
1576 /**
1577 * @brief Set threshold of TX transfer start
1578 *
1579 * Register|BitsName
1580 * --------|--------
1581 * TXFTL | TXFTHR
1582 *
1583 * @param QSPIx QSPI instance
1584 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1585 * @retval None
1586 */
1587 __STATIC_INLINE void ll_qspi_set_tx_start_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1588 {
1589 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTHR_TFT, threshold << QSPI_TXFTHR_TFT_Pos);
1590 }
1591
1592 /**
1593 * @brief Get threshold of TX transfer start
1594 *
1595 * Register|BitsName
1596 * --------|--------
1597 * TXFTL | TXFTHR
1598 *
1599 * @param QSPIx QSPI instance
1600 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1601 */
1602 __STATIC_INLINE uint32_t ll_qspi_get_tx_start_fifo_threshold(qspi_regs_t *QSPIx)
1603 {
1604 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTHR_TFT) >> QSPI_TXFTHR_TFT_Pos);
1605 }
1606
1607 /**
1608 * @brief Set threshold of TXFIFO that triggers an TXE event
1609 *
1610 * Register|BitsName
1611 * --------|--------
1612 * TXFTL | TFT
1613 *
1614 * @param QSPIx QSPI instance
1615 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1616 * @retval None
1617 */
1618 __STATIC_INLINE void ll_qspi_set_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1619 {
1620 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTL_TFT, threshold << QSPI_TXFTL_TFT_Pos);
1621 }
1622
1623 /**
1624 * @brief Get threshold of TXFIFO that triggers an TXE event
1625 *
1626 * Register|BitsName
1627 * --------|--------
1628 * TXFTL | TFT
1629 *
1630 * @param QSPIx QSPI instance
1631 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1632 */
1633 __STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_threshold(qspi_regs_t *QSPIx)
1634 {
1635 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTL_TFT) >> QSPI_TXFTL_TFT_Pos);
1636 }
1637
1638 /**
1639 * @brief Set threshold of RXFIFO that triggers an RXNE event
1640 *
1641 * Register|BitsName
1642 * --------|--------
1643 * RXFTL | RFT
1644 *
1645 * @param QSPIx QSPI instance
1646 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1647 * @retval None
1648 */
1649 __STATIC_INLINE void ll_qspi_set_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1650 {
1651 WRITE_REG(QSPIx->RX_FTL, threshold);
1652 }
1653
1654 /**
1655 * @brief Get threshold of RXFIFO that triggers an RXNE event
1656 *
1657 * Register|BitsName
1658 * --------|--------
1659 * RXFTL | RFT
1660 *
1661 * @param QSPIx QSPI instance
1662 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1663 */
1664 __STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_threshold(qspi_regs_t *QSPIx)
1665 {
1666 return (uint32_t)(READ_BITS(QSPIx->RX_FTL, QSPI_RXFTL_RFT));
1667 }
1668
1669 /**
1670 * @brief Get FIFO Transmission Level
1671 *
1672 * Register|BitsName
1673 * --------|--------
1674 * TXFL | TXTFL
1675 *
1676 * @param QSPIx QSPI instance
1677 * @retval Returned value can be one of the following values: 0 ~ FIFO_DEPTH
1678 */
1679 __STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_level(qspi_regs_t *QSPIx)
1680 {
1681 return (uint32_t)(READ_BITS(QSPIx->TX_FL, QSPI_TXFL_TXTFL));
1682 }
1683
1684 /**
1685 * @brief Get FIFO reception Level
1686 *
1687 * Register|BitsName
1688 * --------|--------
1689 * RXFL | RXTFL
1690 *
1691 * @param QSPIx QSPI instance
1692 * @retval Returned value can be one of the following values: 0 ~ FIFO_DEPTH
1693 */
1694 __STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_level(qspi_regs_t *QSPIx)
1695 {
1696 return (uint32_t)(READ_BITS(QSPIx->RX_FL, QSPI_RXFL_RXTFL));
1697 }
1698
1699 /**
1700 * @brief Get ID code
1701 *
1702 * Register|BitsName
1703 * --------|--------
1704 * IDCODE | ID
1705 *
1706 * @param QSPIx QSPI instance
1707 * @retval Returned value is const.
1708 */
1709 __STATIC_INLINE uint32_t ll_qspi_get_id_code(qspi_regs_t *QSPIx)
1710 {
1711 return (uint32_t)(READ_BITS(QSPIx->ID, QSPI_IDCODE_ID));
1712 }
1713
1714 /**
1715 * @brief Get IP version
1716 *
1717 * Register|BitsName
1718 * --------|--------
1719 * COMP | VERSION
1720 *
1721 * @param QSPIx QSPI instance
1722 * @retval Returned value is const.
1723 */
1724 __STATIC_INLINE uint32_t ll_qspi_get_version(qspi_regs_t *QSPIx)
1725 {
1726 return (uint32_t)(READ_BITS(QSPIx->VERSION_ID, QSPI_COMP_VERSION));
1727 }
1728
1729 /** @} */
1730
1731 /** @defgroup LL_QSPI_EF_IT_Management IT_Management
1732 * @{
1733 */
1734
1735 /**
1736 * @brief Enable interrupt
1737 * @note This bit controls the generation of an interrupt when an event occurs.
1738 *
1739 * Register|BitsName
1740 * --------|--------
1741 * INTMASK | INTMASK
1742 *
1743 * @param QSPIx QSPI instance
1744 * @param mask This parameter can be one of the following values:
1745 * @arg @ref LL_QSPI_IM_SPITE
1746 * @arg @ref LL_QSPI_IM_TXU
1747 * @arg @ref LL_QSPI_IM_XRXO
1748 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1749 * @arg @ref LL_QSPI_IM_RXF
1750 * @arg @ref LL_QSPI_IM_RXO
1751 * @arg @ref LL_QSPI_IM_RXU
1752 * @arg @ref LL_QSPI_IM_TXO
1753 * @arg @ref LL_QSPI_IM_TXE
1754 * @retval None
1755 */
1756 __STATIC_INLINE void ll_qspi_enable_it(qspi_regs_t *QSPIx, uint32_t mask)
1757 {
1758 SET_BITS(QSPIx->INTMASK, mask);
1759 }
1760
1761 /**
1762 * @brief Disable interrupt
1763 * @note This bit controls the generation of an interrupt when an event occurs.
1764 *
1765 * Register|BitsName
1766 * --------|--------
1767 * INTMASK | INTMASK
1768 *
1769 * @param QSPIx QSPI instance
1770 * @param mask This parameter can be one of the following values:
1771 * @arg @ref LL_QSPI_IM_SPITE
1772 * @arg @ref LL_QSPI_IM_TXU
1773 * @arg @ref LL_QSPI_IM_XRXO
1774 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1775 * @arg @ref LL_QSPI_IM_RXF
1776 * @arg @ref LL_QSPI_IM_RXO
1777 * @arg @ref LL_QSPI_IM_RXU
1778 * @arg @ref LL_QSPI_IM_TXO
1779 * @arg @ref LL_QSPI_IM_TXE
1780 * @retval None
1781 */
1782 __STATIC_INLINE void ll_qspi_disable_it(qspi_regs_t *QSPIx, uint32_t mask)
1783 {
1784 CLEAR_BITS(QSPIx->INTMASK, mask);
1785 }
1786
1787 /**
1788 * @brief Check if interrupt is enabled
1789 *
1790 * Register|BitsName
1791 * --------|--------
1792 * INTMASK | INTMASK
1793 *
1794 * @param QSPIx QSPI instance
1795 * @param mask This parameter can be one of the following values:
1796 * @arg @ref LL_QSPI_IM_SPITE
1797 * @arg @ref LL_QSPI_IM_TXU
1798 * @arg @ref LL_QSPI_IM_XRXO
1799 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1800 * @arg @ref LL_QSPI_IM_RXF
1801 * @arg @ref LL_QSPI_IM_RXO
1802 * @arg @ref LL_QSPI_IM_RXU
1803 * @arg @ref LL_QSPI_IM_TXO
1804 * @arg @ref LL_QSPI_IM_TXE
1805 * @retval State of bit (1 or 0).
1806 */
1807 __STATIC_INLINE uint32_t ll_qspi_is_enabled_it(qspi_regs_t *QSPIx, uint32_t mask)
1808 {
1809 return (READ_BITS(QSPIx->INTMASK, mask) == mask);
1810 }
1811
1812 /** @} */
1813
1814 /** @defgroup LL_QSPI_EF_FLAG_Management FLAG_Management
1815 * @{
1816 */
1817
1818 /**
1819 * @brief Get SPI status
1820 *
1821 * Register|BitsName
1822 * --------|--------
1823 * STAT | STAT
1824 *
1825 * @param QSPIx QSPI instance
1826 * @retval Returned value can be one or combination of the following values:
1827 * @arg @ref LL_QSPI_SR_DCOL(no effect in SPIS)
1828 * @arg @ref LL_QSPI_SR_TXE
1829 * @arg @ref LL_QSPI_SR_RFF
1830 * @arg @ref LL_QSPI_SR_RFNE
1831 * @arg @ref LL_QSPI_SR_TFE
1832 * @arg @ref LL_QSPI_SR_TFNF
1833 * @arg @ref LL_QSPI_SR_BUSY
1834 */
1835 __STATIC_INLINE uint32_t ll_qspi_get_status(qspi_regs_t *QSPIx)
1836 {
1837 return (uint32_t)(READ_REG(QSPIx->STAT));
1838 }
1839
1840 /**
1841 * @brief Check active flag
1842 *
1843 * Register|BitsName
1844 * --------|--------
1845 * STAT | DCOL
1846 * STAT | TXE
1847 * STAT | RFF
1848 * STAT | RFNE
1849 * STAT | TFE
1850 * STAT | TFNF
1851 * STAT | BUSY
1852 *
1853 * @param QSPIx QSPI instance
1854 * @param flag This parameter can be one of the following values:
1855 * @arg @ref LL_QSPI_SR_DCOL(no effect in SPIS)
1856 * @arg @ref LL_QSPI_SR_TXE
1857 * @arg @ref LL_QSPI_SR_RFF
1858 * @arg @ref LL_QSPI_SR_RFNE
1859 * @arg @ref LL_QSPI_SR_TFE
1860 * @arg @ref LL_QSPI_SR_TFNF
1861 * @arg @ref LL_QSPI_SR_BUSY
1862 * @retval State of bit (1 or 0).
1863 */
1864 __STATIC_INLINE uint32_t ll_qspi_is_active_flag(qspi_regs_t *QSPIx, uint32_t flag)
1865 {
1866 return (READ_BITS(QSPIx->STAT, flag) == (flag));
1867 }
1868
1869 /**
1870 * @brief Get SPI interrupt flags
1871 *
1872 * Register|BitsName
1873 * --------|--------
1874 * INTSTAT | INTSTAT
1875 *
1876 * @param QSPIx QSPI instance
1877 * @retval Returned value can be one or combination of the following values:
1878 * @arg @ref LL_QSPI_IS_SPITE
1879 * @arg @ref LL_QSPI_IS_TXU
1880 * @arg @ref LL_QSPI_IS_XRXO
1881 * @arg @ref LL_QSPI_IS_MST(no effect in SPIS)
1882 * @arg @ref LL_QSPI_IS_RXF
1883 * @arg @ref LL_QSPI_IS_RXO
1884 * @arg @ref LL_QSPI_IS_RXU
1885 * @arg @ref LL_QSPI_IS_TXO
1886 * @arg @ref LL_QSPI_IS_TXE
1887 */
1888 __STATIC_INLINE uint32_t ll_qspi_get_it_flag(qspi_regs_t *QSPIx)
1889 {
1890 return (uint32_t)(READ_REG(QSPIx->INTSTAT));
1891 }
1892
1893 /**
1894 * @brief Check interrupt flag
1895 *
1896 * Register|BitsName
1897 * --------|--------
1898 * INTSTAT | MSTIS
1899 * INTSTAT | RXFIS
1900 * INTSTAT | RXOIS
1901 * INTSTAT | RXUIS
1902 * INTSTAT | TXOIS
1903 * INTSTAT | TXEIS
1904 *
1905 * @param QSPIx QSPI instance
1906 * @param flag This parameter can be one of the following values:
1907 * @arg @ref LL_QSPI_IS_SPITE
1908 * @arg @ref LL_QSPI_IS_TXU
1909 * @arg @ref LL_QSPI_IS_XRXO
1910 * @arg @ref LL_QSPI_IS_MST(no effect in SPIS)
1911 * @arg @ref LL_QSPI_IS_RXF
1912 * @arg @ref LL_QSPI_IS_RXO
1913 * @arg @ref LL_QSPI_IS_RXU
1914 * @arg @ref LL_QSPI_IS_TXO
1915 * @arg @ref LL_QSPI_IS_TXE
1916 * @retval State of bit (1 or 0).
1917 */
1918 __STATIC_INLINE uint32_t ll_qspi_is_it_flag(qspi_regs_t *QSPIx, uint32_t flag)
1919 {
1920 return (READ_BITS(QSPIx->INTSTAT, flag) == flag);
1921 }
1922
1923 /**
1924 * @brief Get SPI raw interrupt flags
1925 *
1926 * Register|BitsName
1927 * --------|--------
1928 * RAW_INTSTAT | RAW_INTSTAT
1929 *
1930 * @param QSPIx QSPI instance
1931 * @retval Returned value can be one or combination of the following values:
1932 * @arg @ref LL_QSPI_RIS_SPITE
1933 * @arg @ref LL_QSPI_RIS_TXU
1934 * @arg @ref LL_QSPI_RIS_XRXO
1935 * @arg @ref LL_QSPI_RIS_MST(no effect in SPIS)
1936 * @arg @ref LL_QSPI_RIS_RXF
1937 * @arg @ref LL_QSPI_RIS_RXO
1938 * @arg @ref LL_QSPI_RIS_RXU
1939 * @arg @ref LL_QSPI_RIS_TXO
1940 * @arg @ref LL_QSPI_RIS_TXE
1941 */
1942 __STATIC_INLINE uint32_t ll_qspi_get_raw_if_flag(qspi_regs_t *QSPIx)
1943 {
1944 return (uint32_t)(READ_REG(QSPIx->RAW_INTSTAT));
1945 }
1946
1947 /**
1948 * @brief Clear transmit FIFO overflow error flag
1949 * @note Clearing this flag is done by reading TXOIC register
1950 *
1951 * Register|BitsName
1952 * --------|--------
1953 * TXOIC | TXOIC
1954 *
1955 * @param QSPIx QSPI instance
1956 * @retval None
1957 */
1958 __STATIC_INLINE void ll_qspi_clear_flag_txo(qspi_regs_t *QSPIx)
1959 {
1960 __IOM uint32_t tmpreg;
1961 tmpreg = QSPIx->TXOIC;
1962 (void) tmpreg;
1963 }
1964
1965 /**
1966 * @brief Clear receive FIFO overflow error flag
1967 * @note Clearing this flag is done by reading RXOIC register
1968 *
1969 * Register|BitsName
1970 * --------|--------
1971 * RXOIC | RXOIC
1972 *
1973 * @param QSPIx QSPI instance
1974 * @retval None
1975 */
1976 __STATIC_INLINE void ll_qspi_clear_flag_rxo(qspi_regs_t *QSPIx)
1977 {
1978 __IOM uint32_t tmpreg;
1979 tmpreg = QSPIx->RXOIC;
1980 (void) tmpreg;
1981 }
1982
1983 /**
1984 * @brief Clear receive FIFO underflow error flag
1985 * @note Clearing this flag is done by reading RXUIC register
1986 *
1987 * Register|BitsName
1988 * --------|--------
1989 * RXUIC | RXUIC
1990 *
1991 * @param QSPIx QSPI instance
1992 * @retval None
1993 */
1994 __STATIC_INLINE void ll_qspi_clear_flag_rxu(qspi_regs_t *QSPIx)
1995 {
1996 __IOM uint32_t tmpreg;
1997 tmpreg = QSPIx->RXUIC;
1998 (void) tmpreg;
1999 }
2000
2001 /**
2002 * @brief Clear multi-master error flag
2003 * @note Clearing this flag is done by reading MSTIC register
2004 *
2005 * Register|BitsName
2006 * --------|--------
2007 * MSTIC | MSTIC
2008 *
2009 * @param QSPIx QSPI instance
2010 * @retval None
2011 */
2012 __STATIC_INLINE void ll_qspi_clear_flag_mst(qspi_regs_t *QSPIx)
2013 {
2014 __IOM uint32_t tmpreg;
2015 tmpreg = QSPIx->MSTIC;
2016 (void) tmpreg;
2017 }
2018
2019 /**
2020 * @brief Clear XIP receive FIFO overflow flag
2021 * @note Clearing this flag is done by reading XRXOIC register
2022 *
2023 * Register|BitsName
2024 * --------|--------
2025 * XRXOIC | XRXOIC
2026 *
2027 * @param QSPIx QSPI instance
2028 * @retval None
2029 */
2030 __STATIC_INLINE void ll_qspi_clear_flag_xrxo(qspi_regs_t *QSPIx)
2031 {
2032 __IOM uint32_t tmpreg;
2033 tmpreg = QSPIx->XIP_RXOICR;
2034 (void) tmpreg;
2035 }
2036
2037 /**
2038 * @brief Clear all error(txo,rxu,rxo,mst) flag
2039 * @note Clearing this flag is done by reading INTCLR register
2040 *
2041 * Register|BitsName
2042 * --------|--------
2043 * INTCLR | INTCLR
2044 *
2045 * @param QSPIx QSPI instance
2046 * @retval None
2047 */
2048 __STATIC_INLINE void ll_qspi_clear_flag_all(qspi_regs_t *QSPIx)
2049 {
2050 __IOM uint32_t tmpreg;
2051 tmpreg = QSPIx->INTCLR;
2052 (void) tmpreg;
2053 }
2054
2055 /** @} */
2056
2057 /** @defgroup LL_QSPI_EF_DMA_Management DMA_Management
2058 * @{
2059 */
2060
2061 /**
2062 * @brief Enable DMA Tx
2063 *
2064 * Register|BitsName
2065 * --------|--------
2066 * DMAC | TDMAE
2067 *
2068 * @param QSPIx QSPI instance
2069 * @retval None
2070 */
2071 __STATIC_INLINE void ll_qspi_enable_dma_req_tx(qspi_regs_t *QSPIx)
2072 {
2073 SET_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2074 }
2075
2076 /**
2077 * @brief Disable DMA Tx
2078 *
2079 * Register|BitsName
2080 * --------|--------
2081 * DMAC | TDMAE
2082 *
2083 * @param QSPIx QSPI instance
2084 * @retval None
2085 */
2086 __STATIC_INLINE void ll_qspi_disable_dma_req_tx(qspi_regs_t *QSPIx)
2087 {
2088 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2089 }
2090
2091 /**
2092 * @brief Check if DMA Tx is enabled
2093 *
2094 * Register|BitsName
2095 * --------|--------
2096 * DMAC | TDMAE
2097 *
2098 * @param QSPIx QSPI instance
2099 * @retval State of bit (1 or 0).
2100 */
2101 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_tx(qspi_regs_t *QSPIx)
2102 {
2103 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE) == (QSPI_DMAC_TDMAE));
2104 }
2105
2106 /**
2107 * @brief Enable DMA Rx
2108 *
2109 * Register|BitsName
2110 * --------|--------
2111 * DMAC | RDMAE
2112 *
2113 * @param QSPIx QSPI instance
2114 * @retval None
2115 */
2116 __STATIC_INLINE void ll_qspi_enable_dma_req_rx(qspi_regs_t *QSPIx)
2117 {
2118 SET_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2119 }
2120
2121 /**
2122 * @brief Disable DMA Rx
2123 *
2124 * Register|BitsName
2125 * --------|--------
2126 * DMAC | RDMAE
2127 *
2128 * @param QSPIx QSPI instance
2129 * @retval None
2130 */
2131 __STATIC_INLINE void ll_qspi_disable_dma_req_rx(qspi_regs_t *QSPIx)
2132 {
2133 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2134 }
2135
2136 /**
2137 * @brief Check if DMA Rx is enabled
2138 *
2139 * Register|BitsName
2140 * --------|--------
2141 * DMAC | RDMAE
2142 *
2143 * @param QSPIx QSPI instance
2144 * @retval State of bit (1 or 0).
2145 */
2146 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_rx(qspi_regs_t *QSPIx)
2147 {
2148 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE) == (QSPI_DMAC_RDMAE));
2149 }
2150
2151 /**
2152 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
2153 *
2154 * Register|BitsName
2155 * --------|--------
2156 * DMATDL | DMATDL
2157 *
2158 * @param QSPIx QSPI instance
2159 * @param threshold This parameter can be one of the following values: 0 ~ 7
2160 * @retval None
2161 */
2162 __STATIC_INLINE void ll_qspi_set_dma_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
2163 {
2164 WRITE_REG(QSPIx->DMA_TDL, threshold);
2165 }
2166
2167 /**
2168 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
2169 *
2170 * Register|BitsName
2171 * --------|--------
2172 * DMATDL | DMATDL
2173 *
2174 * @param QSPIx QSPI instance
2175 * @retval Returned value can be one of the following values: 0 ~ 7
2176 */
2177 __STATIC_INLINE uint32_t ll_qspi_get_dma_tx_fifo_threshold(qspi_regs_t *QSPIx)
2178 {
2179 return (uint32_t)(READ_BITS(QSPIx->DMA_TDL, QSPI_DMATDL_DMATDL));
2180 }
2181
2182 /**
2183 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
2184 *
2185 * Register|BitsName
2186 * --------|--------
2187 * DMARDL | DMARDL
2188 *
2189 * @param QSPIx QSPI instance
2190 * @param threshold This parameter can be one of the following values: 0 ~ 7
2191 * @retval None
2192 */
2193 __STATIC_INLINE void ll_qspi_set_dma_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
2194 {
2195 WRITE_REG(QSPIx->DMA_RDL, threshold);
2196 }
2197
2198 /**
2199 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
2200 *
2201 * Register|BitsName
2202 * --------|--------
2203 * DMARDL | DMARDL
2204 *
2205 * @param QSPIx QSPI instance
2206 * @retval Returned value can be one of the following values: 0 ~ 7
2207 */
2208 __STATIC_INLINE uint32_t ll_qspi_get_dma_rx_fifo_threshold(qspi_regs_t *QSPIx)
2209 {
2210 return (uint32_t)(READ_BITS(QSPIx->DMA_RDL, QSPI_DMARDL_DMARDL));
2211 }
2212
2213 /** @} */
2214
2215 /** @defgroup LL_QSPI_EF_Data_Management Data_Management
2216 * @{
2217 */
2218
2219 /**
2220 * @brief Write 8-Bits in the data register
2221 *
2222 * Register|BitsName
2223 * --------|--------
2224 * DATA | DATA
2225 *
2226 * @param QSPIx QSPI instance
2227 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
2228 * @retval None
2229 */
2230 __STATIC_INLINE void ll_qspi_transmit_data8(qspi_regs_t *QSPIx, uint8_t tx_data)
2231 {
2232 *((__IOM uint8_t *)&QSPIx->DATA) = tx_data;
2233 }
2234
2235 /**
2236 * @brief Write 16-Bits in the data register
2237 *
2238 * Register|BitsName
2239 * --------|--------
2240 * DATA | DATA
2241 *
2242 * @param QSPIx QSPI instance
2243 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
2244 * @retval None
2245 */
2246 __STATIC_INLINE void ll_qspi_transmit_data16(qspi_regs_t *QSPIx, uint16_t tx_data)
2247 {
2248 *((__IOM uint16_t *)&QSPIx->DATA) = tx_data;
2249 }
2250
2251 /**
2252 * @brief Write 32-Bits in the data register
2253 *
2254 * Register|BitsName
2255 * --------|--------
2256 * DATA | DATA
2257 *
2258 * @param QSPIx QSPI instance
2259 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2260 * @retval None
2261 */
2262 __STATIC_INLINE void ll_qspi_transmit_data32(qspi_regs_t *QSPIx, uint32_t tx_data)
2263 {
2264 *((__IOM uint32_t *)&QSPIx->DATA) = tx_data;
2265 }
2266
2267 /**
2268 * @brief Read 8-Bits in the data register
2269 *
2270 * Register|BitsName
2271 * --------|--------
2272 * DATA | DATA
2273 *
2274 * @param QSPIx QSPI instance
2275 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
2276 */
2277 __STATIC_INLINE uint8_t ll_qspi_receive_data8(qspi_regs_t *QSPIx)
2278 {
2279 return (uint8_t)(READ_REG(QSPIx->DATA));
2280 }
2281
2282 /**
2283 * @brief Read 16-Bits in the data register
2284 *
2285 * Register|BitsName
2286 * --------|--------
2287 * DATA | DATA
2288 *
2289 * @param QSPIx QSPI instance
2290 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
2291 */
2292 __STATIC_INLINE uint16_t ll_qspi_receive_data16(qspi_regs_t *QSPIx)
2293 {
2294 return (uint16_t)(READ_REG(QSPIx->DATA));
2295 }
2296
2297 /**
2298 * @brief Read 32-Bits in the data register
2299 *
2300 * Register|BitsName
2301 * --------|--------
2302 * DATA | DATA
2303 *
2304 * @param QSPIx QSPI instance
2305 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2306 */
2307 __STATIC_INLINE uint32_t ll_qspi_receive_data32(qspi_regs_t *QSPIx)
2308 {
2309 return (uint32_t)(READ_REG(QSPIx->DATA));
2310 }
2311
2312 /**
2313 * @brief Set the RX sample edge
2314 *
2315 * Register|BitsName
2316 * --------|--------
2317 * RX_SAMPLE_DELAY | SE
2318 *
2319 * @param QSPIx QSPI instance
2320 * @param edge - @ ref LL_QSPI_RX_SAMPLE_POSITIVE_EDGE
2321 * @ ref LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE
2322 * @retval none
2323 */
2324 __STATIC_INLINE void ll_qspi_set_rx_sample_edge(qspi_regs_t *QSPIx, uint32_t edge)
2325 {
2326 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE, edge << QSPI_RX_SAMPLE_EDGE_Pos);
2327 }
2328
2329 /**
2330 * @brief Get the RX sample edge
2331 *
2332 * Register|BitsName
2333 * --------|--------
2334 * RX_SAMPLE_DELAY | SE
2335 *
2336 * @param QSPIx QSPI instance
2337 * @retval edge - @ ref LL_QSPI_RX_SAMPLE_POSITIVE_EDGE
2338 * @ ref LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE
2339 */
2340 __STATIC_INLINE uint32_t ll_qspi_get_rx_sample_edge(qspi_regs_t *QSPIx)
2341 {
2342 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE) >> QSPI_RX_SAMPLE_EDGE_Pos);
2343 }
2344
2345 /**
2346 * @brief Set Rx sample delay
2347 * @note This bit should not be changed when communication is ongoing.
2348 *
2349 * Register|BitsName
2350 * --------|--------
2351 * RX_SAMPLEDLY | RX_SAMPLEDLY
2352 *
2353 * @param QSPIx QSPI instance
2354 * @param delay This parameter can be one of the following values: 0 ~ 256
2355 * @retval None
2356 */
2357 __STATIC_INLINE void ll_qspi_set_rx_sample_delay(qspi_regs_t *QSPIx, uint32_t delay)
2358 {
2359 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY, delay);
2360 }
2361
2362 /**
2363 * @brief Get Rx sample delay
2364 * @note This bit should not be changed when communication is ongoing.
2365 *
2366 * Register|BitsName
2367 * --------|--------
2368 * RX_SAMPLEDLY | RX_SAMPLEDLY
2369 *
2370 * @param QSPIx QSPI instance
2371 * @retval Returned value can be one of the following values: 0 ~ 256
2372 */
2373 __STATIC_INLINE uint32_t ll_qspi_get_rx_sample_delay(qspi_regs_t *QSPIx)
2374 {
2375 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY));
2376 }
2377
2378 /**
2379 * @brief Enable the clock stretch feature for Enhanced SPI
2380 * @note This bit should not be changed when communication is ongoing.
2381 *
2382 * Register|BitsName
2383 * --------|--------
2384 * SCTRL0 | CLK_STRETCH_EN
2385 *
2386 * @param QSPIx QSPI instance
2387 * @retval None
2388 */
2389 __STATIC_INLINE void ll_qspi_enable_clk_stretch(qspi_regs_t *QSPIx)
2390 {
2391 SET_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2392 }
2393
2394 /**
2395 * @brief Disable the clock stretch feature for Enhanced SPI
2396 * @note This bit should not be changed when communication is ongoing.
2397 *
2398 * Register|BitsName
2399 * --------|--------
2400 * SCTRL0 | CLK_STRETCH_EN
2401 *
2402 * @param QSPIx QSPI instance
2403 * @retval None
2404 */
2405 __STATIC_INLINE void ll_qspi_disable_clk_stretch(qspi_regs_t *QSPIx)
2406 {
2407 CLEAR_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2408 }
2409
2410 /**
2411 * @brief Check if the clock stretch feature is enabled or not for Enhanced SPI
2412 * @note This bit should not be changed when communication is ongoing.
2413 *
2414 * Register|BitsName
2415 * --------|--------
2416 * SCTRL0 | CLK_STRETCH_EN
2417 *
2418 * @param QSPIx QSPI instance
2419 * @retval None
2420 */
2421 __STATIC_INLINE uint32_t ll_qspi_is_enabled_clk_stretch(qspi_regs_t *QSPIx)
2422 {
2423 return (READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN) == (QSPI_SCTRL0_CLK_STRETCH_EN));
2424 }
2425
2426 /**
2427 * @brief Set number of wait cycles in Dual/Quad SPI mode
2428 * @note This bit should not be changed when communication is ongoing.
2429 *
2430 * Register|BitsName
2431 * --------|--------
2432 * SCTRL0 | WAITCYCLES
2433 *
2434 * @param QSPIx QSPI instance
2435 * @param wait_cycles This parameter can be one of the following values: 0 ~ 31
2436 * @retval None
2437 */
2438 __STATIC_INLINE void ll_qspi_set_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
2439 {
2440 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES, wait_cycles << QSPI_SCTRL0_WAITCYCLES_Pos);
2441 }
2442
2443 /**
2444 * @brief Get number of wait cycles in Dual/Quad SPI mode
2445 * @note This bit should not be changed when communication is ongoing.
2446 *
2447 * Register|BitsName
2448 * --------|--------
2449 * SCTRL0 | WAITCYCLES
2450 *
2451 * @param QSPIx QSPI instance
2452 * @retval Returned value can be one of the following values: 0 ~ 31
2453 */
2454 __STATIC_INLINE uint32_t ll_qspi_get_wait_cycles(qspi_regs_t *QSPIx)
2455 {
2456 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES) >> QSPI_SCTRL0_WAITCYCLES_Pos);
2457 }
2458
2459 /**
2460 * @brief Set Dual/Quad SPI mode instruction length in bits
2461 * @note This bit should not be changed when communication is ongoing.
2462 *
2463 * Register|BitsName
2464 * --------|--------
2465 * SCTRL0 | INSTL
2466 *
2467 * @param QSPIx QSPI instance
2468 * @param size This parameter can be one of the following values:
2469 * @arg @ref LL_QSPI_INSTSIZE_0BIT
2470 * @arg @ref LL_QSPI_INSTSIZE_4BIT
2471 * @arg @ref LL_QSPI_INSTSIZE_8BIT
2472 * @arg @ref LL_QSPI_INSTSIZE_16BIT
2473 * @retval None
2474 */
2475 __STATIC_INLINE void ll_qspi_set_instruction_size(qspi_regs_t *QSPIx, uint32_t size)
2476 {
2477 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL, size);
2478 }
2479
2480 /**
2481 * @brief Get Dual/Quad SPI mode instruction length in bits
2482 * @note This bit should not be changed when communication is ongoing.
2483 *
2484 * Register|BitsName
2485 * --------|--------
2486 * SCTRL0 | INSTL
2487 *
2488 * @param QSPIx QSPI instance
2489 * @retval Returned value can be one of the following values:
2490 * @arg @ref LL_QSPI_INSTSIZE_0BIT
2491 * @arg @ref LL_QSPI_INSTSIZE_4BIT
2492 * @arg @ref LL_QSPI_INSTSIZE_8BIT
2493 * @arg @ref LL_QSPI_INSTSIZE_16BIT
2494 */
2495 __STATIC_INLINE uint32_t ll_qspi_get_instruction_size(qspi_regs_t *QSPIx)
2496 {
2497 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL));
2498 }
2499
2500 /**
2501 * @brief Set Dual/Quad SPI mode address length in bits
2502 * @note This bit should not be changed when communication is ongoing.
2503 *
2504 * Register|BitsName
2505 * --------|--------
2506 * SCTRL0 | ADDRL
2507 *
2508 * @param QSPIx QSPI instance
2509 * @param size This parameter can be one of the following values:
2510 * @arg @ref LL_QSPI_ADDRSIZE_0BIT
2511 * @arg @ref LL_QSPI_ADDRSIZE_4BIT
2512 * @arg @ref LL_QSPI_ADDRSIZE_8BIT
2513 * @arg @ref LL_QSPI_ADDRSIZE_12BIT
2514 * @arg @ref LL_QSPI_ADDRSIZE_16BIT
2515 * @arg @ref LL_QSPI_ADDRSIZE_20BIT
2516 * @arg @ref LL_QSPI_ADDRSIZE_24BIT
2517 * @arg @ref LL_QSPI_ADDRSIZE_28BIT
2518 * @arg @ref LL_QSPI_ADDRSIZE_32BIT
2519 * @arg @ref LL_QSPI_ADDRSIZE_36BIT
2520 * @arg @ref LL_QSPI_ADDRSIZE_40BIT
2521 * @arg @ref LL_QSPI_ADDRSIZE_44BIT
2522 * @arg @ref LL_QSPI_ADDRSIZE_48BIT
2523 * @arg @ref LL_QSPI_ADDRSIZE_52BIT
2524 * @arg @ref LL_QSPI_ADDRSIZE_56BIT
2525 * @arg @ref LL_QSPI_ADDRSIZE_60BIT
2526 * @retval None
2527 */
2528 __STATIC_INLINE void ll_qspi_set_address_size(qspi_regs_t *QSPIx, uint32_t size)
2529 {
2530 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL, size);
2531 }
2532
2533 /**
2534 * @brief Get Dual/Quad SPI mode address length in bits
2535 * @note This bit should not be changed when communication is ongoing.
2536 *
2537 * Register|BitsName
2538 * --------|--------
2539 * SCTRL0 | ADDRL
2540 *
2541 * @param QSPIx QSPI instance
2542 * @retval Returned value can be one of the following values:
2543 * @arg @ref LL_QSPI_ADDRSIZE_0BIT
2544 * @arg @ref LL_QSPI_ADDRSIZE_4BIT
2545 * @arg @ref LL_QSPI_ADDRSIZE_8BIT
2546 * @arg @ref LL_QSPI_ADDRSIZE_12BIT
2547 * @arg @ref LL_QSPI_ADDRSIZE_16BIT
2548 * @arg @ref LL_QSPI_ADDRSIZE_20BIT
2549 * @arg @ref LL_QSPI_ADDRSIZE_24BIT
2550 * @arg @ref LL_QSPI_ADDRSIZE_28BIT
2551 * @arg @ref LL_QSPI_ADDRSIZE_32BIT
2552 * @arg @ref LL_QSPI_ADDRSIZE_36BIT
2553 * @arg @ref LL_QSPI_ADDRSIZE_40BIT
2554 * @arg @ref LL_QSPI_ADDRSIZE_44BIT
2555 * @arg @ref LL_QSPI_ADDRSIZE_48BIT
2556 * @arg @ref LL_QSPI_ADDRSIZE_52BIT
2557 * @arg @ref LL_QSPI_ADDRSIZE_56BIT
2558 * @arg @ref LL_QSPI_ADDRSIZE_60BIT
2559 */
2560 __STATIC_INLINE uint32_t ll_qspi_get_address_size(qspi_regs_t *QSPIx)
2561 {
2562 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL));
2563 }
2564
2565 /**
2566 * @brief Set Dual/Quad SPI mode address and instruction transfer format
2567 * @note This bit should not be changed when communication is ongoing.
2568 *
2569 * Register|BitsName
2570 * --------|--------
2571 * SCTRL0 | TRANSTYPE
2572 *
2573 * @param QSPIx QSPI instance
2574 * @param format This parameter can be one of the following values:
2575 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPI
2576 * @arg @ref LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
2577 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPIFRF
2578 * @retval None
2579 */
2580 __STATIC_INLINE void ll_qspi_set_add_inst_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
2581 {
2582 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE, format);
2583 }
2584
2585 /**
2586 * @brief Get Dual/Quad SPI mode address and instruction transfer format
2587 * @note This bit should not be changed when communication is ongoing.
2588 *
2589 * Register|BitsName
2590 * --------|--------
2591 * SCTRL0 | TRANSTYPE
2592 *
2593 * @param QSPIx QSPI instance
2594 * @retval Returned value can be one of the following values:
2595 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPI
2596 * @arg @ref LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
2597 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPIFRF
2598 */
2599 __STATIC_INLINE uint32_t ll_qspi_get_addr_inst_transfer_format(qspi_regs_t *QSPIx)
2600 {
2601 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE));
2602 }
2603
2604
2605
2606 /**
2607 * @brief Enable the mode bits phase for concurrent xip mode
2608 * @note This bit should not be changed when xip is ongoing.
2609 *
2610 * Register|BitsName
2611 * --------|--------
2612 * XIP_CTRL | MD_BITS_EN
2613 *
2614 * @param QSPIx - QSPI instance
2615 * @retval none
2616 */
2617 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_mode_bits(qspi_regs_t *QSPIx)
2618 {
2619 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2620 }
2621
2622 /**
2623 * @brief Disable the mode bits phase for concurrent xip mode
2624 * @note This bit should not be changed when xip is ongoing.
2625 *
2626 * Register|BitsName
2627 * --------|--------
2628 * XIP_CTRL | MD_BITS_EN
2629 *
2630 * @param QSPIx - QSPI instance
2631 * @retval none
2632 */
2633 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_mode_bits(qspi_regs_t *QSPIx)
2634 {
2635 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2636 }
2637
2638 /**
2639 * @brief Check if the mode bits phase is enabled or not for concurrent xip mode
2640 * @note This bit should not be changed when xip is ongoing.
2641 *
2642 * Register|BitsName
2643 * --------|--------
2644 * XIP_CTRL | MD_BITS_EN
2645 *
2646 * @param QSPIx - QSPI instance
2647 * @retval TRUE/FALSE
2648 */
2649 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_mode_bits(qspi_regs_t *QSPIx)
2650 {
2651 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN) == (QSPI_XCTRL_MD_BIT_EN));
2652 }
2653
2654 /**
2655 * @brief Set the length of mode bits phase for concurrent xip mode
2656 * @note This bit should not be changed when xip is ongoing.
2657 *
2658 * Register|BitsName
2659 * --------|--------
2660 * XIP_CTRL | XIP_MBL
2661 *
2662 * @param QSPIx - QSPI instance
2663 * @param mbl - @ref LL_QSPI_CONCURRENT_XIP_MBL_2
2664 * @ref LL_QSPI_CONCURRENT_XIP_MBL_4
2665 * @ref LL_QSPI_CONCURRENT_XIP_MBL_8
2666 * @ref LL_QSPI_CONCURRENT_XIP_MBL_16
2667 * @retval none
2668 */
2669 __STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_length(qspi_regs_t *QSPIx, uint32_t mbl)
2670 {
2671 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL, mbl << QSPI_XCTRL_XIP_MBL_Pos);
2672 }
2673
2674 /**
2675 * @brief Get the length of mode bits phase for concurrent xip mode
2676 * @note This bit should not be changed when xip is ongoing.
2677 *
2678 * Register|BitsName
2679 * --------|--------
2680 * XIP_CTRL | XIP_MBL
2681 *
2682 * @param QSPIx - QSPI instance
2683 * @retval mbl - @ref LL_QSPI_CONCURRENT_XIP_MBL_2
2684 * @ref LL_QSPI_CONCURRENT_XIP_MBL_4
2685 * @ref LL_QSPI_CONCURRENT_XIP_MBL_8
2686 * @ref LL_QSPI_CONCURRENT_XIP_MBL_16
2687 */
2688 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_length(qspi_regs_t *QSPIx)
2689 {
2690 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL) >> QSPI_XCTRL_XIP_MBL_Pos);
2691 }
2692
2693 /**
2694 * @brief set the mode phase (sent after address phase) value in xip mode
2695 * @note This bit should not be changed when xip is ongoing.
2696 *
2697 * Register|BitsName
2698 * --------|--------
2699 * XIP_MODE_BITS | XIP_MD_BITS
2700 *
2701 * @param QSPIx - QSPI instance
2702 * @param mode - mode value, [0 ~ 0xFFFF]
2703 * @retval None
2704 */
2705 __STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_data(qspi_regs_t *QSPIx, uint32_t mode)
2706 {
2707 MODIFY_REG(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS, mode << QSPI_XIP_MODE_BITS_Pos);
2708 }
2709
2710 /**
2711 * @brief get the mode phase (sent after address phase) value in xip mode
2712 * @note This bit should not be changed when xip is ongoing.
2713 *
2714 * Register|BitsName
2715 * --------|--------
2716 * XIP_MODE_BITS | XIP_MD_BITS
2717 *
2718 * @param QSPIx - QSPI instance
2719 * @retval mode value, [0 ~ 0xFFFF]
2720 */
2721 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_data(qspi_regs_t *QSPIx)
2722 {
2723 return (uint32_t)(READ_BITS(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS) >> QSPI_XIP_MODE_BITS_Pos);
2724 }
2725
2726 /**
2727 * @brief set the ahb-incr transfer instruction in xip mode
2728 * @note This bit should not be changed when xip is ongoing.
2729 *
2730 * Register|BitsName
2731 * --------|--------
2732 * XIP_INCR_INST | INCR_INST
2733 *
2734 * @param QSPIx - QSPI instance
2735 * @param inst - instruction op-code, [0 ~ 0xFFFF]
2736 * @retval None
2737 */
2738 __STATIC_INLINE void ll_qspi_concurrent_set_xip_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
2739 {
2740 MODIFY_REG(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST, inst << QSPI_XIP_INCR_INST_Pos);
2741 }
2742
2743 /**
2744 * @brief get the ahb-incr transfer instruction in xip mode
2745 * @note This bit should not be changed when xip is ongoing.
2746 *
2747 * Register|BitsName
2748 * --------|--------
2749 * XIP_INCR_INST | INCR_INST
2750 *
2751 * @param QSPIx - QSPI instance
2752 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
2753 */
2754 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_incr_inst(qspi_regs_t *QSPIx)
2755 {
2756 return (uint32_t)(READ_BITS(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST) >> QSPI_XIP_INCR_INST_Pos);
2757 }
2758
2759 /**
2760 * @brief set the ahb-wrap transfer instruction in xip mode
2761 * @note This bit should not be changed when xip is ongoing.
2762 *
2763 * Register|BitsName
2764 * --------|--------
2765 * XIP_WRAP_INST | WRAP_INST
2766 *
2767 * @param QSPIx - QSPI instance
2768 * @param inst - wrap instruction op-code, [0 ~ 0xFFFF]
2769 * @retval None
2770 */
2771 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
2772 {
2773 MODIFY_REG(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST, inst << QSPI_XIP_WRAP_INST_Pos);
2774 }
2775
2776 /**
2777 * @brief get the ahb-wrap transfer instruction in xip mode
2778 * @note This bit should not be changed when xip is ongoing.
2779 *
2780 * Register|BitsName
2781 * --------|--------
2782 * XIP_WRAP_INST | WRAP_INST
2783 *
2784 * @param QSPIx - QSPI instance
2785 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
2786 */
2787 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wrap_inst(qspi_regs_t *QSPIx)
2788 {
2789 return (uint32_t)(READ_BITS(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST) >> QSPI_XIP_WRAP_INST_Pos);
2790 }
2791
2792 /**
2793 * @brief Enable the slave in xip mode
2794 * @note This bit should not be changed when xip is ongoing.
2795 *
2796 * Register|BitsName
2797 * --------|--------
2798 * XIP_SER | SER
2799 *
2800 * @param QSPIx - QSPI instance
2801 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2802 * @retval None
2803 */
2804 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2805 {
2806 SET_BITS(QSPIx->XIP_SER, ss);
2807 }
2808
2809 /**
2810 * @brief Disable the slave in xip mode
2811 * @note This bit should not be changed when xip is ongoing.
2812 *
2813 * Register|BitsName
2814 * --------|--------
2815 * XIP_SER | SER
2816 *
2817 * @param QSPIx - QSPI instance
2818 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2819 * @retval None
2820 */
2821 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2822 {
2823 CLEAR_BITS(QSPIx->XIP_SER, ss);
2824 }
2825
2826 /**
2827 * @brief Check if the slave is enabled or not for concurrent xip mode
2828 * @note This bit should not be changed when xip is ongoing.
2829 *
2830 * Register|BitsName
2831 * --------|--------
2832 * XIP_SER | SER
2833 *
2834 * @param QSPIx - QSPI instance
2835 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2836 * @retval None
2837 */
2838 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2839 {
2840 return (READ_BITS(QSPIx->XIP_SER, ss) == ss);
2841 }
2842
2843 /**
2844 * @brief Set time out count for continuous transfer for xip mode
2845 * @note This bit should not be changed when xip is ongoing.
2846 *
2847 * Register|BitsName
2848 * --------|--------
2849 * XIP_CNT_TIME_OUT | XTOC
2850 *
2851 * @param QSPIx - QSPI instance
2852 * @param xtoc - time out counter value in terms of hclk [0 ~ 0xFF]
2853 * @retval None
2854 */
2855 __STATIC_INLINE void ll_qspi_concurrent_set_xip_toc(qspi_regs_t *QSPIx, uint32_t xtoc)
2856 {
2857 MODIFY_REG(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT, xtoc << QSPI_XIP_TOCNT_Pos);
2858 }
2859
2860 /**
2861 * @brief Get time out count for continuous transfer for xip mode
2862 * @note This bit should not be changed when xip is ongoing.
2863 *
2864 * Register|BitsName
2865 * --------|--------
2866 * XIP_CNT_TIME_OUT | XTOC
2867 *
2868 * @param QSPIx - QSPI instance
2869 * @retval xtoc - time out counter value in terms of hclk [0 ~ 0xFF]
2870 */
2871 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_toc(qspi_regs_t *QSPIx)
2872 {
2873 return (uint32_t)(READ_BITS(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT) >> QSPI_XIP_TOCNT_Pos);
2874 }
2875
2876 /**
2877 * @brief Enable the pre-fetch feature for concurrent xip mode
2878 * @note This bit should not be changed when xip is ongoing.
2879 *
2880 * Register|BitsName
2881 * --------|--------
2882 * XIP_CTRL | XIP_PREFETCH_EN
2883 *
2884 * @param QSPIx - QSPI instance
2885 * @retval none
2886 */
2887 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_prefetch(qspi_regs_t *QSPIx)
2888 {
2889 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2890 }
2891
2892 /**
2893 * @brief Disable the pre-fetch feature for concurrent xip mode
2894 * @note This bit should not be changed when xip is ongoing.
2895 *
2896 * Register|BitsName
2897 * --------|--------
2898 * XIP_CTRL | XIP_PREFETCH_EN
2899 *
2900 * @param QSPIx - QSPI instance
2901 * @retval none
2902 */
2903 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_prefetch(qspi_regs_t *QSPIx)
2904 {
2905 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2906 }
2907
2908 /**
2909 * @brief check if the pre-fetch feature is enabled or not for concurrent xip mode
2910 * @note This bit should not be changed when xip is ongoing.
2911 *
2912 * Register|BitsName
2913 * --------|--------
2914 * XIP_CTRL | XIP_PREFETCH_EN
2915 *
2916 * @param QSPIx - QSPI instance
2917 * @retval TRUE/FALSE
2918 */
2919 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_prefetch(qspi_regs_t *QSPIx)
2920 {
2921 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN) == (QSPI_XCTRL_XIP_PREFETCH_EN));
2922 }
2923
2924 /**
2925 * @brief Enable the continuous transfer feature for concurrent xip mode
2926 * @note This bit should not be changed when xip is ongoing.
2927 *
2928 * Register|BitsName
2929 * --------|--------
2930 * XIP_CTRL | CONT_XFER_EN
2931 *
2932 * @param QSPIx - QSPI instance
2933 * @retval none
2934 */
2935 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_continuous_xfer(qspi_regs_t *QSPIx)
2936 {
2937 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2938 }
2939
2940 /**
2941 * @brief Disable the continuous transfer feature for concurrent xip mode
2942 * @note This bit should not be changed when xip is ongoing.
2943 *
2944 * Register|BitsName
2945 * --------|--------
2946 * XIP_CTRL | CONT_XFER_EN
2947 *
2948 * @param QSPIx - QSPI instance
2949 * @retval none
2950 */
2951 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_continuous_xfer(qspi_regs_t *QSPIx)
2952 {
2953 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2954 }
2955
2956 /**
2957 * @brief Check if the continuous transfer feature is enabled or not for concurrent xip mode
2958 * @note This bit should not be changed when xip is ongoing.
2959 *
2960 * Register|BitsName
2961 * --------|--------
2962 * XIP_CTRL | CONT_XFER_EN
2963 *
2964 * @param QSPIx - QSPI instance
2965 * @retval TRUE/FALSE
2966 */
2967 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_continuous_xfer(qspi_regs_t *QSPIx)
2968 {
2969 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN) == (QSPI_XCTRL_CONT_XFER_EN));
2970 }
2971
2972 /**
2973 * @brief Enable the instruction phase for concurrent xip mode
2974 * @note This bit should not be changed when xip is ongoing.
2975 *
2976 * Register|BitsName
2977 * --------|--------
2978 * XIP_CTRL | INST_EN
2979 *
2980 * @param QSPIx - QSPI instance
2981 * @retval none
2982 */
2983 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_instruction(qspi_regs_t *QSPIx)
2984 {
2985 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
2986 }
2987
2988 /**
2989 * @brief Disable the instruction phase for concurrent xip mode
2990 * @note This bit should not be changed when xip is ongoing.
2991 *
2992 * Register|BitsName
2993 * --------|--------
2994 * XIP_CTRL | INST_EN
2995 *
2996 * @param QSPIx - QSPI instance
2997 * @retval none
2998 */
2999 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_instruction(qspi_regs_t *QSPIx)
3000 {
3001 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
3002 }
3003
3004 /**
3005 * @brief Check if the instruction phase is enabled or not for concurrent xip mode
3006 * @note This bit should not be changed when xip is ongoing.
3007 *
3008 * Register|BitsName
3009 * --------|--------
3010 * XIP_CTRL | INST_EN
3011 *
3012 * @param QSPIx - QSPI instance
3013 * @retval TRUE/FALSE
3014 */
3015 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_instruction(qspi_regs_t *QSPIx)
3016 {
3017 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN) == (QSPI_XCTRL_INST_EN));
3018 }
3019
3020 /**
3021 * @brief Set the instruction size for concurrent xip mode
3022 * @note This bit should not be changed when xip is ongoing.
3023 *
3024 * Register|BitsName
3025 * --------|--------
3026 * XIP_CTRL | INST_L
3027 *
3028 * @param QSPIx - QSPI instance
3029 * @param inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3030 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3031 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3032 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3033 * @retval none
3034 */
3035 __STATIC_INLINE void ll_qspi_concurrent_set_xip_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
3036 {
3037 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL, inst_size << QSPI_XCTRL_INSTL_Pos);
3038 }
3039
3040 /**
3041 * @brief Get the instruction size for concurrent xip mode
3042 * @note This bit should not be changed when xip is ongoing.
3043 *
3044 * Register|BitsName
3045 * --------|--------
3046 * XIP_CTRL | INST_L
3047 *
3048 * @param QSPIx - QSPI instance
3049 * @retval inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3050 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3051 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3052 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3053 */
3054 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_instruction_size(qspi_regs_t *QSPIx)
3055 {
3056 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL) >> QSPI_XCTRL_INSTL_Pos);
3057 }
3058
3059
3060 /**
3061 * @brief Enable the hardcoded DFS feature for concurrent xip mode
3062 * @note This bit should not be changed when xip is ongoing.
3063 *
3064 * Register|BitsName
3065 * --------|--------
3066 * XIP_CTRL | DFS_HC
3067 *
3068 * @param QSPIx - QSPI instance
3069 * @retval none
3070 */
3071 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3072 {
3073 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3074 }
3075
3076 /**
3077 * @brief Disable the hardcoded DFS feature for concurrent xip mode
3078 * @note This bit should not be changed when xip is ongoing.
3079 *
3080 * Register|BitsName
3081 * --------|--------
3082 * XIP_CTRL | DFS_HC
3083 *
3084 * @param QSPIx - QSPI instance
3085 * @retval none
3086 */
3087 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3088 {
3089 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3090 }
3091
3092 /**
3093 * @brief Check if the hardcoded DFS feature is enabled or not for concurrent xip mode
3094 * @note This bit should not be changed when xip is ongoing.
3095 *
3096 * Register|BitsName
3097 * --------|--------
3098 * XIP_CTRL | DFS_HC
3099 *
3100 * @param QSPIx - QSPI instance
3101 * @retval TRUE/FALSE
3102 */
3103 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3104 {
3105 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC) == (QSPI_XCTRL_DFS_HC));
3106 }
3107
3108 /**
3109 * @brief Set the wait(also called dummy) cycles for concurrent xip mode
3110 * @note This bit should not be changed when xip is ongoing.
3111 *
3112 * Register|BitsName
3113 * --------|--------
3114 * XIP_CTRL | WAIT_CYCLES
3115 *
3116 * @param QSPIx - QSPI instance
3117 * @param wait_cycles - 0 ~ 31
3118 * @retval none
3119 */
3120 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
3121 {
3122 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES, wait_cycles << QSPI_XCTRL_WAITCYCLES_Pos);
3123 }
3124
3125 /**
3126 * @brief Get the wait(also called dummy) cycles for concurrent xip mode
3127 * @note This bit should not be changed when xip is ongoing.
3128 *
3129 * Register|BitsName
3130 * --------|--------
3131 * XIP_CTRL | WAIT_CYCLES
3132 *
3133 * @param QSPIx - QSPI instance
3134 * @retval wait_cycles - 0 ~ 31
3135 */
3136 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wait_cycles(qspi_regs_t *QSPIx)
3137 {
3138 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES) >> QSPI_XCTRL_WAITCYCLES_Pos);
3139 }
3140
3141 /**
3142 * @brief Set the address size for concurrent xip mode
3143 * @note This bit should not be changed when xip is ongoing.
3144 *
3145 * Register|BitsName
3146 * --------|--------
3147 * XIP_CTRL | ADDR_L
3148 *
3149 * @param QSPIx - QSPI instance
3150 * @param addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3151 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3152 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3153 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3154 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3155 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3156 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3157 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3158 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3159 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
3160 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
3161 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
3162 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
3163 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
3164 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
3165 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
3166 *
3167 * @retval none
3168 */
3169 __STATIC_INLINE void ll_qspi_concurrent_set_xip_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
3170 {
3171 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL, addr_size << QSPI_XCTRL_ADDRL_Pos);
3172 }
3173
3174 /**
3175 * @brief Get the address size for concurrent xip mode
3176 * @note This bit should not be changed when xip is ongoing.
3177 *
3178 * Register|BitsName
3179 * --------|--------
3180 * XIP_CTRL | ADDR_L
3181 *
3182 * @param QSPIx - QSPI instance
3183 * @retval addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3184 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3185 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3186 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3187 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3188 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3189 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3190 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3191 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3192 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
3193 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
3194 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
3195 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
3196 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
3197 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
3198 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
3199 */
3200 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_address_size(qspi_regs_t *QSPIx)
3201 {
3202 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL) >> QSPI_XCTRL_ADDRL_Pos);
3203 }
3204
3205 /**
3206 * @brief Set the transfer format of inst & address for concurrent xip mode
3207 * @note This bit should not be changed when xip is ongoing.
3208 *
3209 * Register|BitsName
3210 * --------|--------
3211 * XIP_CTRL | TRANS_TYPE
3212 *
3213 * @param QSPIx - QSPI instance
3214 * @param format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3215 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3216 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3217 *
3218 * @retval none
3219 */
3220 __STATIC_INLINE void ll_qspi_concurrent_set_xip_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
3221 {
3222 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE, format << QSPI_XCTRL_TRANSTYPE_Pos);
3223 }
3224
3225 /**
3226 * @brief Get the transfer format of inst & address for concurrent xip mode
3227 * @note This bit should not be changed when xip is ongoing.
3228 *
3229 * Register|BitsName
3230 * --------|--------
3231 * XIP_CTRL | TRANS_TYPE
3232 *
3233 * @param QSPIx - QSPI instance
3234 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3235 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3236 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3237 */
3238 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_addr_inst_transfer_format(qspi_regs_t *QSPIx)
3239 {
3240 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE) >> QSPI_XCTRL_TRANSTYPE_Pos);
3241 }
3242
3243 /**
3244 * @brief Set the QSPI frame format for concurrent xip mode
3245 * @note This bit should not be changed when xip is ongoing.
3246 *
3247 * Register|BitsName
3248 * --------|--------
3249 * XIP_CTRL | FRF
3250 *
3251 * @param QSPIx - QSPI instance
3252 * @param format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3253 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3254 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3255 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3256 *
3257 * @retval none
3258 */
3259 __STATIC_INLINE void ll_qspi_concurrent_set_xip_frame_format(qspi_regs_t *QSPIx, uint32_t format)
3260 {
3261 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF, format << QSPI_XCTRL_FRF_Pos);
3262 }
3263
3264 /**
3265 * @brief Get the QSPI frame format for concurrent xip mode
3266 * @note This bit should not be changed when xip is ongoing.
3267 *
3268 * Register|BitsName
3269 * --------|--------
3270 * XIP_CTRL | FRF
3271 *
3272 * @param QSPIx - QSPI instance
3273 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3274 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3275 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3276 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3277 *
3278 */
3279 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_frame_format(qspi_regs_t *QSPIx)
3280 {
3281 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF) >> QSPI_XCTRL_FRF_Pos);
3282 }
3283
3284
3285 /**
3286 * @brief Enable qspi xip mode
3287 * @note This bit should not be changed when communication is ongoing.
3288 *
3289 * Register|BitsName
3290 * --------|--------
3291 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3292 *
3293 * @param QSPIx QSPI instance
3294 *
3295 * @retval None
3296 */
3297 void ll_qspi_enable_xip(qspi_regs_t * QSPIx);
3298
3299 /**
3300 * @brief Disable qspi xip mode
3301 * @note This bit should not be changed when communication is ongoing.
3302 *
3303 * Register|BitsName
3304 * --------|--------
3305 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3306 *
3307 * @param QSPIx QSPI instance
3308 *
3309 * @retval None
3310 */
3311 void ll_qspi_disable_xip(qspi_regs_t * QSPIx);
3312
3313 /**
3314 * @brief Check if qspi xip mode is enabled
3315 * @note This bit should not be changed when communication is ongoing.
3316 *
3317 * Register|BitsName
3318 * --------|--------
3319 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3320 *
3321 * @param QSPIx QSPI instance
3322 *
3323 * @retval None
3324 */
3325 uint32_t ll_qspi_is_enabled_xip(qspi_regs_t * QSPIx);
3326
3327 /**
3328 * @brief Set xip's endian mode
3329 * @note This bit should not be changed when communication is ongoing.
3330 *
3331 * Register|BitsName
3332 * --------|--------
3333 * QSPI_M_XIP : QSPI_M_XIP_M0_ENDIAN | QSPI_M_XIP_M1_ENDIAN | QSPI_M_XIP_M2_ENDIAN
3334 *
3335 * @param QSPIx QSPI instance
3336 *
3337 * @param mode - This parameter can be one of the following values:
3338 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
3339 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
3340 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
3341 *
3342 * @retval None
3343 */
3344 __STATIC_INLINE void ll_qspi_set_xip_endian_mode(qspi_regs_t * QSPIx, uint32_t mode)
3345 {
3346 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3347
3348 MODIFY_REG(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which), mode << which);
3349 }
3350
3351
3352 /**
3353 * @brief Get xip's endian mode
3354 * @note This bit should not be changed when communication is ongoing.
3355 *
3356 * Register|BitsName
3357 * --------|--------
3358 * QSPI_M_XIP : QSPI_M_XIP_M0_ENDIAN | QSPI_M_XIP_M1_ENDIAN | QSPI_M_XIP_M2_ENDIAN
3359 *
3360 * @param QSPIx QSPI instance
3361 *
3362 * @retval Returned value can be one of the following values:
3363 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
3364 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
3365 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
3366 *
3367 */
3368 __STATIC_INLINE uint32_t ll_qspi_get_xip_endian_mode(qspi_regs_t * QSPIx)
3369 {
3370 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3371
3372 return (READ_BITS(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which)) >> which );
3373 }
3374
3375 /************************* Add Following APIs from gr552xx-b0 *************************************/
3376
3377
3378 /**
3379 * @brief Enable dynamic of wait states for QSPI peripheral
3380 *
3381 * Register|BitsName
3382 * --------|--------
3383 * CTRL0 | DWS_EN
3384 *
3385 * @param QSPIx QSPI instance
3386 * @retval None
3387 */
3388 __STATIC_INLINE void ll_qspi_enable_dws(qspi_regs_t *QSPIx)
3389 {
3390 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3391 }
3392
3393 /**
3394 * @brief Disable dynamic of wait states for QSPI peripheral
3395 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
3396 *
3397 * Register|BitsName
3398 * --------|--------
3399 * CTRL0 | DWS_EN
3400 *
3401 * @param QSPIx QSPI instance
3402 * @retval None
3403 */
3404 __STATIC_INLINE void ll_qspi_disable_dws(qspi_regs_t *QSPIx)
3405 {
3406 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3407 }
3408
3409 /**
3410 * @brief Check if dynamic of wait states for QSPI peripheral is enabled
3411 *
3412 * Register|BitsName
3413 * --------|--------
3414 * CTRL0 | DWS_EN
3415 *
3416 * @param QSPIx QSPI instance
3417 * @retval State of bit (1 or 0).
3418 */
3419 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dws(qspi_regs_t *QSPIx)
3420 {
3421 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN) == (QSPI_CTRL0_DWS_EN));
3422 }
3423
3424 /**
3425 * @brief Clear QSPI Transmit Error interrupt
3426 * @note Clearing this flag is done by reading SPITEIC register
3427 *
3428 * Register|BitsName
3429 * --------|--------
3430 * SPI_TEIC | SPI_TEIC
3431 *
3432 * @param QSPIx QSPI instance
3433 * @retval None
3434 */
3435 __STATIC_INLINE void ll_qspi_clear_flag_spite(qspi_regs_t *QSPIx)
3436 {
3437 __IOM uint32_t tmpreg;
3438 tmpreg = QSPIx->SPI_TEIC;
3439 (void) tmpreg;
3440 }
3441
3442 /**
3443 * @brief set the max wait cycles per transaction for dynamic wait state
3444 * @note This bit should not be changed when QSPI is ongoing.
3445 *
3446 * Register|BitsName
3447 * --------|--------
3448 * SPI_CTRL1 | QSPI_SCTRL1_MAX_WS
3449 *
3450 * @param QSPIx - QSPI instance
3451 * @param max_ws - max wait cycles per transaction [0 ~ 15]
3452 * @retval None
3453 */
3454 __STATIC_INLINE void ll_qspi_set_max_wait_cycles(qspi_regs_t *QSPIx, uint32_t max_ws)
3455 {
3456 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS, max_ws << QSPI_SCTRL1_MAX_WS_Pos);
3457 }
3458
3459 /**
3460 * @brief get the max wait cycles per transaction for dynamic wait state
3461 * @note This bit should not be changed when QSPI is ongoing.
3462 *
3463 * Register|BitsName
3464 * --------|--------
3465 * SPI_CTRL1 | QSPI_SCTRL1_MAX_WS
3466 *
3467 * @param QSPIx - QSPI instance
3468 * @retval max wait cycles per transaction [0 ~ 15]
3469 */
3470 __STATIC_INLINE uint32_t ll_qspi_get_max_wait_cycles(qspi_regs_t *QSPIx)
3471 {
3472 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS) >> QSPI_SCTRL1_MAX_WS_Pos);
3473 }
3474
3475 /**
3476 * @brief set the value for dynamic wait state
3477 * @note This bit should not be changed when QSPI is ongoing.
3478 *
3479 * Register|BitsName
3480 * --------|--------
3481 * SPI_CTRL1 | QSPI_SCTRL1_DYN_WS
3482 *
3483 * @param QSPIx - QSPI instance
3484 * @param dyn_ws - dynamic wait state [0 ~ 7]
3485 * @retval None
3486 */
3487 __STATIC_INLINE void ll_qspi_set_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
3488 {
3489 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS, dyn_ws << QSPI_SCTRL1_DYN_WS_Pos);
3490 }
3491
3492 /**
3493 * @brief get the value for dynamic wait state
3494 * @note This bit should not be changed when QSPI is ongoing.
3495 *
3496 * Register|BitsName
3497 * --------|--------
3498 * SPI_CTRL1 | QSPI_SCTRL1_DYN_WS
3499 *
3500 * @param QSPIx - QSPI instance
3501 * @param dyn_ws - dynamic wait state [0 ~ 7]
3502 * @retval dynamic wait state [0 ~ 7]
3503 */
3504 __STATIC_INLINE uint32_t ll_qspi_get_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
3505 {
3506 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS) >> QSPI_SCTRL1_DYN_WS_Pos);
3507 }
3508
3509 /**
3510 * @brief set the ahb-incr transfer instruction for write in xip mode
3511 * @note This bit should not be changed when xip is ongoing.
3512 *
3513 * Register|BitsName
3514 * --------|--------
3515 * XIP_WR_INCR_INST | WR_INCR_INST
3516 *
3517 * @param QSPIx - QSPI instance
3518 * @param inst - instruction op-code, [0 ~ 0xFFFF]
3519 * @retval None
3520 */
3521 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
3522 {
3523 MODIFY_REG(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST, inst << QSPI_XIP_WR_INCR_INST_Pos);
3524 }
3525
3526 /**
3527 * @brief get the ahb-incr transfer instruction for write in xip mode
3528 * @note This bit should not be changed when xip is ongoing.
3529 *
3530 * Register|BitsName
3531 * --------|--------
3532 * XIP_WR_INCR_INST | WR_INCR_INST
3533 *
3534 * @param QSPIx - QSPI instance
3535 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
3536 */
3537 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_incr_inst(qspi_regs_t *QSPIx)
3538 {
3539 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST) >> QSPI_XIP_WR_INCR_INST_Pos);
3540 }
3541
3542 /**
3543 * @brief set the ahb-wrap transfer instruction for write in xip mode
3544 * @note This bit should not be changed when xip is ongoing.
3545 *
3546 * Register|BitsName
3547 * --------|--------
3548 * XIP_WR_WRAP_INST | WR_WRAP_INST
3549 *
3550 * @param QSPIx - QSPI instance
3551 * @param inst - wrap instruction op-code, [0 ~ 0xFFFF]
3552 * @retval None
3553 */
3554 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
3555 {
3556 MODIFY_REG(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST, inst << QSPI_XIP_WR_WRAP_INST_Pos);
3557 }
3558
3559 /**
3560 * @brief get the ahb-wrap transfer instruction for write in xip mode
3561 * @note This bit should not be changed when xip is ongoing.
3562 *
3563 * Register|BitsName
3564 * --------|--------
3565 * XIP_WR_WRAP_INST | WR_WRAP_INST
3566 *
3567 * @param QSPIx - QSPI instance
3568 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
3569 */
3570 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wrap_inst(qspi_regs_t *QSPIx)
3571 {
3572 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST) >> QSPI_XIP_WR_WRAP_INST_Pos);
3573 }
3574
3575
3576 /**
3577 * @brief Set the wait(also called dummy) cycles for concurrent xip write mode
3578 * @note This bit should not be changed when xip is ongoing.
3579 *
3580 * Register|BitsName
3581 * --------|--------
3582 * XIP_WR_CTRL | WAITCYCLES
3583 *
3584 * @param QSPIx - QSPI instance
3585 * @param wait_cycles - 0 ~ 31
3586 * @retval none
3587 */
3588 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
3589 {
3590 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES, wait_cycles << QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3591 }
3592
3593 /**
3594 * @brief Get the wait(also called dummy) cycles for concurrent xip write mode
3595 * @note This bit should not be changed when xip is ongoing.
3596 *
3597 * Register|BitsName
3598 * --------|--------
3599 * XIP_WR_CTRL | WAITCYCLES
3600 *
3601 * @param QSPIx - QSPI instance
3602 * @retval wait_cycles - 0 ~ 31
3603 */
3604 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wait_cycles(qspi_regs_t *QSPIx)
3605 {
3606 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES) >> QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3607 }
3608
3609
3610 /**
3611 * @brief Set the instruction size for concurrent xip write mode
3612 * @note This bit should not be changed when xip is ongoing.
3613 *
3614 * Register|BitsName
3615 * --------|--------
3616 * XIP_WR_CTRL | INSTL
3617 *
3618 * @param QSPIx - QSPI instance
3619 * @param inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3620 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3621 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3622 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3623 * @retval none
3624 */
3625 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
3626 {
3627 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL, inst_size << QSPI_XIP_WR_CTRL_INSTL_Pos);
3628 }
3629
3630 /**
3631 * @brief Get the instruction size for concurrent xip write mode
3632 * @note This bit should not be changed when xip is ongoing.
3633 *
3634 * Register|BitsName
3635 * --------|--------
3636 * XIP_WR_CTRL | INSTL
3637 *
3638 * @param QSPIx - QSPI instance
3639 * @retval inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3640 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3641 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3642 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3643 */
3644 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_instruction_size(qspi_regs_t *QSPIx)
3645 {
3646 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL) >> QSPI_XIP_WR_CTRL_INSTL_Pos);
3647 }
3648
3649
3650 /**
3651 * @brief Set the address size for concurrent xip write mode
3652 * @note This bit should not be changed when xip is ongoing.
3653 *
3654 * Register|BitsName
3655 * --------|--------
3656 * XIP_WR_CTRL | ADDRL
3657 *
3658 * @param QSPIx - QSPI instance
3659 * @param addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3660 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3661 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3662 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3663 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3664 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3665 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3666 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3667 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3668 *
3669 * @retval none
3670 */
3671 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
3672 {
3673 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL, addr_size << QSPI_XIP_WR_CTRL_ADDRL_Pos);
3674 }
3675
3676 /**
3677 * @brief Get the address size for concurrent xip write mode
3678 * @note This bit should not be changed when xip is ongoing.
3679 *
3680 * Register|BitsName
3681 * --------|--------
3682 * XIP_WR_CTRL | ADDRL
3683 *
3684 * @param QSPIx - QSPI instance
3685 * @retval addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3686 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3687 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3688 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3689 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3690 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3691 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3692 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3693 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3694 */
3695 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_address_size(qspi_regs_t *QSPIx)
3696 {
3697 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL) >> QSPI_XIP_WR_CTRL_ADDRL_Pos);
3698 }
3699
3700 /**
3701 * @brief Set the transfer format of inst & address for concurrent xip write mode
3702 * @note This bit should not be changed when xip is ongoing.
3703 *
3704 * Register|BitsName
3705 * --------|--------
3706 * XIP_WR_CTRL | TRANS_TYPE
3707 *
3708 * @param QSPIx - QSPI instance
3709 * @param format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3710 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3711 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3712 *
3713 * @retval none
3714 */
3715 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
3716 {
3717 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE, format << QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3718 }
3719
3720 /**
3721 * @brief Get the transfer format of inst & address for concurrent xip write mode
3722 * @note This bit should not be changed when xip is ongoing.
3723 *
3724 * Register|BitsName
3725 * --------|--------
3726 * XIP_WR_CTRL | TRANS_TYPE
3727 *
3728 * @param QSPIx - QSPI instance
3729 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3730 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3731 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3732 */
3733 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format(qspi_regs_t *QSPIx)
3734 {
3735 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE) >> QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3736 }
3737
3738 /**
3739 * @brief Set the QSPI frame format for concurrent xip write mode
3740 * @note This bit should not be changed when xip is ongoing.
3741 *
3742 * Register|BitsName
3743 * --------|--------
3744 * XIP_WR_CTRL | FRF
3745 *
3746 * @param QSPIx - QSPI instance
3747 * @param format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3748 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3749 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3750 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3751 *
3752 * @retval none
3753 */
3754 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_frame_format(qspi_regs_t *QSPIx, uint32_t format)
3755 {
3756 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF, format << QSPI_XIP_WR_CTRL_FRF_Pos);
3757 }
3758
3759 /**
3760 * @brief Get the QSPI frame format for concurrent xip write mode
3761 * @note This bit should not be changed when xip is ongoing.
3762 *
3763 * Register|BitsName
3764 * --------|--------
3765 * XIP_WR_CTRL | FRF
3766 *
3767 * @param QSPIx - QSPI instance
3768 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3769 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3770 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3771 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3772 *
3773 */
3774 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_frame_format(qspi_regs_t *QSPIx)
3775 {
3776 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF) >> QSPI_XIP_WR_CTRL_FRF_Pos);
3777 }
3778
3779 /**
3780 * @brief Enable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens
3781 * @note Just enable in debug mode, not enable in release code
3782 * Set 0 to get hardfault when generate hresp = 1
3783 * Set 1 to avoid hardfault and always mask the hresp to 0, 1 is default value after System Reset
3784 *
3785 * Register|BitsName
3786 * --------|--------
3787 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3788 *
3789 *
3790 * @retval none
3791 *
3792 */
3793 __STATIC_INLINE void ll_qspi_enable_hresp_err_debug_mode(void)
3794 {
3795 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 0);
3796 }
3797
3798 /**
3799 * @brief Disable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens
3800 * @note Just enable in debug mode, not enable in release code
3801 *
3802 * Register|BitsName
3803 * --------|--------
3804 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3805 *
3806 *
3807 * @retval none
3808 *
3809 */
3810 __STATIC_INLINE void ll_qspi_disable_hresp_err_debug_mode(void)
3811 {
3812 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 1);
3813 }
3814
3815 /**
3816 * @brief Check if the AHB Response Error Debug is enabled for all QSPI Modules.
3817 * @note
3818 *
3819 * Register|BitsName
3820 * --------|--------
3821 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3822 *
3823 *
3824 * @retval none
3825 *
3826 */
3827 __STATIC_INLINE uint32_t ll_qspi_is_hresp_err_debug_mode_enabled(void)
3828 {
3829 return (READ_BITS(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN) == (0));
3830 }
3831
3832 /**
3833 * @brief Set CS Setup Delay for QSPI
3834 * @note This bit should not be changed when communication is ongoing.
3835 *
3836 * Register|BitsName
3837 * --------|--------
3838 * QSPI_M_CS_SETUP_DLY : MCU_SUB_QSPI_M0_CS_SETUP_DLY | MCU_SUB_QSPI_M1_CS_SETUP_DLY | MCU_SUB_QSPI_M2_CS_SETUP_DLY
3839 *
3840 * @param QSPIx QSPI instance
3841 *
3842 * @param delay - the SLCK count to delay
3843 *
3844 * @retval None
3845 */
3846 __STATIC_INLINE void ll_qspi_set_cs_setup_delay(qspi_regs_t * QSPIx, uint32_t delay)
3847 {
3848 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3849 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3850
3851 MODIFY_REG(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which, (baudrate*delay) << which);
3852 }
3853
3854
3855 /**
3856 * @brief Get CS Setup Delay for QSPI
3857 * @note This bit should not be changed when communication is ongoing.
3858 *
3859 * Register|BitsName
3860 * --------|--------
3861 * QSPI_M_CS_SETUP_DLY : MCU_SUB_QSPI_M0_CS_SETUP_DLY | MCU_SUB_QSPI_M1_CS_SETUP_DLY | MCU_SUB_QSPI_M2_CS_SETUP_DLY
3862 *
3863 * @param QSPIx QSPI instance
3864 *
3865 * @retval the SLCK count to delay
3866 */
3867 __STATIC_INLINE uint32_t ll_qspi_get_cs_setup_delay(qspi_regs_t * QSPIx)
3868 {
3869 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3870 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3871
3872 if(0 == baudrate){
3873 return 0;
3874 }
3875
3876 return (READ_BITS(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which) >> which)/baudrate;
3877 }
3878
3879 /**
3880 * @brief Set CS Release Delay for QSPI
3881 * @note This bit should not be changed when communication is ongoing.
3882 *
3883 * Register|BitsName
3884 * --------|--------
3885 * QSPI_M_CS_RELEASE_DLY : MCU_SUB_QSPI_M0_CS_RELEASE_DLY | MCU_SUB_QSPI_M1_CS_RELEASE_DLY | MCU_SUB_QSPI_M2_CS_RELEASE_DLY
3886 *
3887 * @param QSPIx QSPI instance
3888 *
3889 * @param delay - the SLCK count to delay
3890 *
3891 * @retval None
3892 */
3893 __STATIC_INLINE void ll_qspi_set_cs_release_delay(qspi_regs_t * QSPIx, uint32_t delay)
3894 {
3895 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ((QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3896 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3897
3898 MODIFY_REG(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which, (baudrate*delay) << which);
3899 }
3900
3901
3902 /**
3903 * @brief Get CS Release Delay for QSPI
3904 * @note This bit should not be changed when communication is ongoing.
3905 *
3906 * Register|BitsName
3907 * --------|--------
3908 * QSPI_M_CS_RELEASE_DLY : MCU_SUB_QSPI_M0_CS_RELEASE_DLY | MCU_SUB_QSPI_M1_CS_RELEASE_DLY | MCU_SUB_QSPI_M2_CS_RELEASE_DLY
3909 *
3910 * @param QSPIx QSPI instance
3911 *
3912 * @retval the SLCK count to delay
3913 */
3914 __STATIC_INLINE uint32_t ll_qspi_get_cs_release_delay(qspi_regs_t * QSPIx)
3915 {
3916 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3917 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3918
3919 if(0 == baudrate){
3920 return 0;
3921 }
3922
3923 return (READ_BITS(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which) >> which)/baudrate;
3924 }
3925
3926 /**
3927 * @brief Enable qspi xip dynamic little-endian mode
3928 * @note This bit should not be changed when communication is ongoing.
3929 *
3930 * Register|BitsName
3931 * --------|--------
3932 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3933 *
3934 * @param QSPIx QSPI instance
3935 *
3936 * @retval None
3937 */
3938 __STATIC_INLINE void ll_qspi_enable_xip_dynamic_le(qspi_regs_t * QSPIx)
3939 {
3940 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3941 SET_BITS(MCU_SUB->QSPI_M_XIP, which);
3942 }
3943
3944 /**
3945 * @brief Disable qspi xip dynamic little-endian mode
3946 * @note This bit should not be changed when communication is ongoing.
3947 *
3948 * Register|BitsName
3949 * --------|--------
3950 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3951 *
3952 * @param QSPIx QSPI instance
3953 *
3954 * @retval None
3955 */
3956 __STATIC_INLINE void ll_qspi_disable_xip_dynamic_le(qspi_regs_t * QSPIx)
3957 {
3958 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3959 CLEAR_BITS(MCU_SUB->QSPI_M_XIP, which);
3960 }
3961
3962 /**
3963 * @brief Check if qspi xip dynamic little-endian mode is enabled
3964 * @note This bit should not be changed when communication is ongoing.
3965 *
3966 * Register|BitsName
3967 * --------|--------
3968 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3969 *
3970 * @param QSPIx QSPI instance
3971 *
3972 * @retval None
3973 */
3974 __STATIC_INLINE uint32_t ll_qspi_is_enabled_xip_dynamic_le(qspi_regs_t * QSPIx)
3975 {
3976 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3977 return (READ_BITS(MCU_SUB->QSPI_M_XIP, which) == (which));
3978 }
3979
3980 /**
3981 * @brief Get Receive FIFO Depth Of Register Mode
3982 * @note
3983 * @param QSPIx QSPI instance
3984 * @retval Receive FIFO Depth corresponded to QSPI instance
3985 */
3986 __STATIC_INLINE uint32_t ll_qspi_get_reg_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
3987 {
3988 if(QSPI0 == QSPIx) {
3989 return LL_QSPI0_REG_RX_FIFO_DEPTH;
3990 } else if(QSPI1 == QSPIx) {
3991 return LL_QSPI1_REG_RX_FIFO_DEPTH;
3992 } else {
3993 return LL_QSPI2_REG_RX_FIFO_DEPTH;
3994 }
3995 }
3996
3997 /**
3998 * @brief Get Transmit FIFO Depth Of Register Mode
3999 * @note
4000 * @param QSPIx QSPI instance
4001 * @retval Transmit FIFO Depth corresponded to QSPI instance
4002 */
4003 __STATIC_INLINE uint32_t ll_qspi_get_reg_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
4004 {
4005 if(QSPI0 == QSPIx) {
4006 return LL_QSPI0_REG_TX_FIFO_DEPTH;
4007 } else if(QSPI1 == QSPIx) {
4008 return LL_QSPI1_REG_TX_FIFO_DEPTH;
4009 } else {
4010 return LL_QSPI2_REG_TX_FIFO_DEPTH;
4011 }
4012 }
4013
4014 /**
4015 * @brief Get Receive FIFO Depth Of XIP Mode
4016 * @note
4017 * @param QSPIx QSPI instance
4018 * @retval Receive FIFO Depth corresponded to QSPI instance
4019 */
4020 __STATIC_INLINE uint32_t ll_qspi_get_xip_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
4021 {
4022 if(QSPI0 == QSPIx) {
4023 return LL_QSPI0_XIP_RX_FIFO_DEPTH;
4024 } else if(QSPI1 == QSPIx) {
4025 return LL_QSPI1_XIP_RX_FIFO_DEPTH;
4026 } else {
4027 return LL_QSPI2_XIP_RX_FIFO_DEPTH;
4028 }
4029 }
4030
4031 /**
4032 * @brief Get Transmit FIFO Depth Of XIP Mode
4033 * @note
4034 * @param QSPIx QSPI instance
4035 * @retval Transmit FIFO Depth corresponded to QSPI instance
4036 */
4037 __STATIC_INLINE uint32_t ll_qspi_get_xip_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
4038 {
4039 if(QSPI0 == QSPIx) {
4040 return LL_QSPI0_XIP_TX_FIFO_DEPTH;
4041 } else if(QSPI1 == QSPIx) {
4042 return LL_QSPI1_XIP_TX_FIFO_DEPTH;
4043 } else {
4044 return LL_QSPI2_XIP_TX_FIFO_DEPTH;
4045 }
4046 }
4047
4048 /**
4049 * @brief Get Transmit FIFO Depth Of XIP Mode
4050 * @note
4051 * @param QSPIx QSPI instance
4052 * @retval Transmit FIFO Depth corresponded to QSPI instance
4053 */
4054 __STATIC_INLINE uint32_t ll_qspi_get_xip_base_address(qspi_regs_t *QSPIx)
4055 {
4056 if(QSPI0 == QSPIx) {
4057 return QSPI0_XIP_BASE;
4058 } else if(QSPI1 == QSPIx) {
4059 return QSPI1_XIP_BASE;
4060 } else {
4061 return QSPI2_XIP_BASE;
4062 }
4063 }
4064 /** @} */
4065 /** @defgroup LL_QSPI_Init QSPI Initialization and de-initialization functions
4066 * @{
4067 */
4068
4069 /**
4070 * @brief De-initialize SSI registers (Registers restored to their default values).
4071 * @param QSPIx SSI instance
4072 * @retval An error_status_t enumeration value:
4073 * - SUCCESS: SSI registers are de-initialized
4074 * - ERROR: SSI registers are not de-initialized
4075 */
4076 error_status_t ll_qspi_deinit(qspi_regs_t *QSPIx);
4077
4078 /**
4079 * @brief Initialize SSI registers according to the specified
4080 * parameters in SPI_InitStruct.
4081 * @param QSPIx SSI instance
4082 * @param p_spi_init Pointer to a ll_qspi_init_t structure that contains the configuration
4083 * information for the specified QSPI peripheral.
4084 * @retval An error_status_t enumeration value:
4085 * - SUCCESS: SPI registers are initialized according to p_spi_init content
4086 * - ERROR: Problem occurred during SPI Registers initialization
4087 */
4088 error_status_t ll_qspi_init(qspi_regs_t *QSPIx, ll_qspi_init_t *p_spi_init);
4089
4090 /**
4091 * @brief Configure the qspi to memorymapped.
4092 * @param QSPIx QSPI instance
4093 * @param p_qspi_mmap_init pointer to a @ref ll_qspi_memorymapped_init_t structure
4094 * @retval An ErrorStatus enumeration value:
4095 * - SUCCESS: spi registers are de-initialized
4096 * - ERROR: not applicable
4097 */
4098 error_status_t ll_qspi_memorymapped(qspi_regs_t *QSPIx, ll_qspi_memorymapped_init_t * p_qspi_mmap_init);
4099
4100
4101 /**
4102 * @brief Set each field of a @ref ll_qspi_init_t type structure to default value.
4103 * @param p_spi_init Pointer to a @ref ll_qspi_init_t structure
4104 * whose fields will be set to default values.
4105 * @retval None
4106 */
4107 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
4108
4109 /** @} */
4110
4111 /** @} */
4112
4113 #endif /* QSPI0 || QSPI1 || QSPI2 */
4114
4115 #ifdef __cplusplus
4116 }
4117 #endif
4118
4119 #endif /* __GR55xx_LL_SPI_H__ */
4120
4121 /** @} */
4122
4123 /** @} */
4124
4125 /** @} */
LL_QSPI0_XIP_RX_FIFO_DEPTH
#define LL_QSPI0_XIP_RX_FIFO_DEPTH
Receive FIFO Depth Of XIP Mode for QSPI0 Master.
Definition: gr55xx_ll_qspi.h:287
ll_qspi_set_cs_release_delay
__STATIC_INLINE void ll_qspi_set_cs_release_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Release Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3893
ll_qspi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_qspi.h:1664
ll_qspi_concurrent_disable_xip_prefetch
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_prefetch(qspi_regs_t *QSPIx)
Disable the pre-fetch feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2903
ll_qspi_get_receive_size
__STATIC_INLINE uint32_t ll_qspi_get_receive_size(qspi_regs_t *QSPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_qspi.h:1317
ll_qspi_transmit_data32
__STATIC_INLINE void ll_qspi_transmit_data32(qspi_regs_t *QSPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2262
ll_qspi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_qspi_is_enabled_slave_out(qspi_regs_t *QSPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_qspi.h:1127
ll_qspi_enable_micro_handshake
__STATIC_INLINE void ll_qspi_enable_micro_handshake(qspi_regs_t *QSPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_qspi.h:1378
ll_qspi_is_active_flag
__STATIC_INLINE uint32_t ll_qspi_is_active_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_qspi.h:1864
ll_qspi_concurrent_enable_xip_dfs_hardcode
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Enable the hardcoded DFS feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3071
ll_qspi_concurrent_get_xip_instruction_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3054
ll_qspi_memorymapped
error_status_t ll_qspi_memorymapped(qspi_regs_t *QSPIx, ll_qspi_memorymapped_init_t *p_qspi_mmap_init)
Configure the qspi to memorymapped.
ll_qspi_get_standard
__STATIC_INLINE uint32_t ll_qspi_get_standard(qspi_regs_t *QSPIx)
Get serial protocol used.
Definition: gr55xx_ll_qspi.h:1278
ll_qspi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_delay(qspi_regs_t *QSPIx)
Get Rx sample delay.
Definition: gr55xx_ll_qspi.h:2373
ll_qspi_concurrent_is_enabled_xip_prefetch
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_prefetch(qspi_regs_t *QSPIx)
check if the pre-fetch feature is enabled or not for concurrent xip mode
Definition: gr55xx_ll_qspi.h:2919
ll_qspi_concurrent_set_xip_toc
__STATIC_INLINE void ll_qspi_concurrent_set_xip_toc(qspi_regs_t *QSPIx, uint32_t xtoc)
Set time out count for continuous transfer for xip mode.
Definition: gr55xx_ll_qspi.h:2855
ll_qspi_is_enabled_clk_stretch
__STATIC_INLINE uint32_t ll_qspi_is_enabled_clk_stretch(qspi_regs_t *QSPIx)
Check if the clock stretch feature is enabled or not for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2421
ll_qspi_concurrent_set_xip_mode_bits_data
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_data(qspi_regs_t *QSPIx, uint32_t mode)
set the mode phase (sent after address phase) value in xip mode
Definition: gr55xx_ll_qspi.h:2705
ll_qspi_set_standard
__STATIC_INLINE void ll_qspi_set_standard(qspi_regs_t *QSPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_qspi.h:1260
LL_QSPI1_XIP_TX_FIFO_DEPTH
#define LL_QSPI1_XIP_TX_FIFO_DEPTH
Transmit FIFO Depth Of XIP Mode for QSPI1 Master.
Definition: gr55xx_ll_qspi.h:293
ll_qspi_concurrent_get_xip_wr_address_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3695
ll_qspi_concurrent_set_xip_inst_addr_transfer_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3220
ll_qspi_transmit_data16
__STATIC_INLINE void ll_qspi_transmit_data16(qspi_regs_t *QSPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2246
ll_qspi_concurrent_disable_xip_ss
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable the slave in xip mode.
Definition: gr55xx_ll_qspi.h:2821
ll_qspi_disable_hresp_err_debug_mode
__STATIC_INLINE void ll_qspi_disable_hresp_err_debug_mode(void)
Disable the AHB Response Error Debug for all QSPI Modules.
Definition: gr55xx_ll_qspi.h:3810
ll_qspi_enable_dws
__STATIC_INLINE void ll_qspi_enable_dws(qspi_regs_t *QSPIx)
Enable dynamic of wait states for QSPI peripheral.
Definition: gr55xx_ll_qspi.h:3388
ll_qspi_concurrent_get_xip_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3238
_ll_qspi_init_t::instruction_size
uint32_t instruction_size
Specifies the QSPI instruction width.
Definition: gr55xx_ll_qspi.h:83
ll_qspi_receive_data32
__STATIC_INLINE uint32_t ll_qspi_receive_data32(qspi_regs_t *QSPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2307
ll_qspi_is_enabled_it
__STATIC_INLINE uint32_t ll_qspi_is_enabled_it(qspi_regs_t *QSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_qspi.h:1807
ll_qspi_enable_ss_toggle
__STATIC_INLINE void ll_qspi_enable_ss_toggle(qspi_regs_t *QSPIx)
Enable slave select toggle.
Definition: gr55xx_ll_qspi.h:812
ll_qspi_disable_test_mode
__STATIC_INLINE void ll_qspi_disable_test_mode(qspi_regs_t *QSPIx)
Disable SPI test mode.
Definition: gr55xx_ll_qspi.h:1067
ll_qspi_concurrent_get_xip_wr_instruction_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3644
LL_QSPI0_REG_RX_FIFO_DEPTH
#define LL_QSPI0_REG_RX_FIFO_DEPTH
Receive FIFO Depth Of Register Mode for QSPI0 Master.
Definition: gr55xx_ll_qspi.h:285
ll_qspi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_qspi.h:1694
ll_qspi_is_enabled
__STATIC_INLINE uint32_t ll_qspi_is_enabled(qspi_regs_t *QSPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_qspi.h:1363
ll_qspi_set_receive_size
__STATIC_INLINE void ll_qspi_set_receive_size(qspi_regs_t *QSPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_qspi.h:1297
ll_qspi_concurrent_get_xip_wr_frame_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3774
LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE
@ LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE
Definition: gr55xx_ll_qspi.h:130
ll_qspi_get_dynamic_wait_state
__STATIC_INLINE uint32_t ll_qspi_get_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
get the value for dynamic wait state
Definition: gr55xx_ll_qspi.h:3504
ll_qspi_enable
__STATIC_INLINE void ll_qspi_enable(qspi_regs_t *QSPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_qspi.h:1332
ll_qspi_get_transfer_direction
__STATIC_INLINE uint32_t ll_qspi_get_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode.
Definition: gr55xx_ll_qspi.h:1166
ll_qspi_is_enabled_xip
uint32_t ll_qspi_is_enabled_xip(qspi_regs_t *QSPIx)
Check if qspi xip mode is enabled.
LL_QSPI2_REG_RX_FIFO_DEPTH
#define LL_QSPI2_REG_RX_FIFO_DEPTH
Receive FIFO Depth Of Register Mode for QSPI2 Master.
Definition: gr55xx_ll_qspi.h:295
_ll_qspi_init_t::address_size
uint32_t address_size
Specifies the QSPI address width.
Definition: gr55xx_ll_qspi.h:88
ll_qspi_get_clock_polarity
__STATIC_INLINE uint32_t ll_qspi_get_clock_polarity(qspi_regs_t *QSPIx)
Get clock polarity.
Definition: gr55xx_ll_qspi.h:1203
ll_qspi_set_cs_setup_delay
__STATIC_INLINE void ll_qspi_set_cs_setup_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Setup Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3846
_ll_qspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_qspi.h:108
ll_qspi_concurrent_get_xip_wrap_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2787
ll_qspi_enable_hresp_err_debug_mode
__STATIC_INLINE void ll_qspi_enable_hresp_err_debug_mode(void)
Enable the AHB Response Error Debug for all QSPI Modules.
Definition: gr55xx_ll_qspi.h:3793
_ll_qspi_init_t::inst_addr_transfer_format
uint32_t inst_addr_transfer_format
Specifies the QSPI instruction and address transfer format.
Definition: gr55xx_ll_qspi.h:93
ll_qspi_concurrent_set_xip_wr_frame_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3754
ll_qspi_get_xip_base_address
__STATIC_INLINE uint32_t ll_qspi_get_xip_base_address(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4054
ll_qspi_get_max_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_get_max_wait_cycles(qspi_regs_t *QSPIx)
get the max wait cycles per transaction for dynamic wait state
Definition: gr55xx_ll_qspi.h:3470
LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY
@ LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY
Definition: gr55xx_ll_qspi.h:129
_ll_qspi_memorymapped_write_init_t::x_wr_dummy_cycles
uint32_t x_wr_dummy_cycles
Specifies wait(dummy) cycles in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:226
_ll_qspi_memorymapped_read_init_t::x_endian_mode
uint32_t x_endian_mode
Specifies endian mode in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:199
ll_qspi_enable_ss
__STATIC_INLINE void ll_qspi_enable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_qspi.h:1501
ll_qspi_set_tx_start_fifo_threshold
__STATIC_INLINE void ll_qspi_set_tx_start_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TX transfer start.
Definition: gr55xx_ll_qspi.h:1587
ll_qspi_clear_flag_all
__STATIC_INLINE void ll_qspi_clear_flag_all(qspi_regs_t *QSPIx)
Clear all error(txo,rxu,rxo,mst) flag.
Definition: gr55xx_ll_qspi.h:2048
ll_qspi_concurrent_set_xip_wr_address_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3671
ll_qspi_concurrent_is_enabled_xip_dfs_hardcode
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Check if the hardcoded DFS feature is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3103
_ll_qspi_memorymapped_read_init_t::x_prefetch_en
uint32_t x_prefetch_en
Specifies whether to enable the prefetch feature.
Definition: gr55xx_ll_qspi.h:185
_ll_qspi_memorymapped_read_init_t::x_dfs
uint32_t x_dfs
Specifies the QSPI data frame size in xip mode.
Definition: gr55xx_ll_qspi.h:139
ll_qspi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_qspi_is_enabled_micro_handshake(qspi_regs_t *QSPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_qspi.h:1408
_ll_qspi_memorymapped_write_init_t::x_wr_address_size
uint32_t x_wr_address_size
Specifies instruction size in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:218
ll_qspi_get_status
__STATIC_INLINE uint32_t ll_qspi_get_status(qspi_regs_t *QSPIx)
Get SPI status.
Definition: gr55xx_ll_qspi.h:1835
ll_qspi_disable_xip
void ll_qspi_disable_xip(qspi_regs_t *QSPIx)
Disable qspi xip mode.
ll_qspi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_qspi_get_baud_rate_prescaler(qspi_regs_t *QSPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_qspi.h:1571
_ll_qspi_memorymapped_read_init_t::x_instruction
uint32_t x_instruction
Specifies instruction in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:156
_ll_qspi_memorymapped_write_init_t
Definition: gr55xx_ll_qspi.h:207
ll_qspi_concurrent_disable_xip_dfs_hardcode
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Disable the hardcoded DFS feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3087
_ll_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_ll_qspi.h:123
ll_qspi_concurrent_set_xip_wr_wait_cycles
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3588
ll_qspi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_dma_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_qspi.h:2162
ll_qspi_enable_dma_req_rx
__STATIC_INLINE void ll_qspi_enable_dma_req_rx(qspi_regs_t *QSPIx)
Enable DMA Rx.
Definition: gr55xx_ll_qspi.h:2116
ll_qspi_concurrent_is_enabled_xip_mode_bits
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_mode_bits(qspi_regs_t *QSPIx)
Check if the mode bits phase is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2649
ll_qspi_disable_salve_out
__STATIC_INLINE void ll_qspi_disable_salve_out(qspi_regs_t *QSPIx)
Disable slave output.
Definition: gr55xx_ll_qspi.h:1112
_ll_qspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_qspi.h:112
ll_qspi_set_frame_format
__STATIC_INLINE void ll_qspi_set_frame_format(qspi_regs_t *QSPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_qspi.h:864
ll_qspi_concurrent_set_xip_instruction_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3035
_ll_qspi_memorymapped_read_init_t::x_dfs_hardcode_en
uint32_t x_dfs_hardcode_en
Specifies whether to enable the HSIZE hardcoded to DFS feature in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:142
ll_qspi_set_data_size
__STATIC_INLINE void ll_qspi_set_data_size(qspi_regs_t *QSPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_qspi.h:928
ll_qspi_get_cs_release_delay
__STATIC_INLINE uint32_t ll_qspi_get_cs_release_delay(qspi_regs_t *QSPIx)
Get CS Release Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3914
ll_qspi_get_clock_phase
__STATIC_INLINE uint32_t ll_qspi_get_clock_phase(qspi_regs_t *QSPIx)
Get clock phase.
Definition: gr55xx_ll_qspi.h:1240
ll_qspi_concurrent_set_xip_wr_wrap_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3554
ll_qspi_set_transfer_direction
__STATIC_INLINE void ll_qspi_set_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_qspi.h:1147
ll_qspi_concurrent_set_xip_wait_cycles
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3120
ll_qspi_concurrent_disable_xip_instruction
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_instruction(qspi_regs_t *QSPIx)
Disable the instruction phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2999
ll_qspi_concurrent_set_xip_wr_incr_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3521
_ll_qspi_memorymapped_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_qspi.h:250
_ll_qspi_init_t
QSPI init structures definition.
Definition: gr55xx_ll_qspi.h:77
LL_QSPI1_REG_RX_FIFO_DEPTH
#define LL_QSPI1_REG_RX_FIFO_DEPTH
Receive FIFO Depth Of Register Mode for QSPI1 Master.
Definition: gr55xx_ll_qspi.h:290
ll_qspi_clear_flag_xrxo
__STATIC_INLINE void ll_qspi_clear_flag_xrxo(qspi_regs_t *QSPIx)
Clear XIP receive FIFO overflow flag.
Definition: gr55xx_ll_qspi.h:2030
ll_qspi_set_wait_cycles
__STATIC_INLINE void ll_qspi_set_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_qspi.h:2438
ll_qspi_set_dynamic_wait_state
__STATIC_INLINE void ll_qspi_set_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
set the value for dynamic wait state
Definition: gr55xx_ll_qspi.h:3487
ll_qspi_disable_micro_handshake
__STATIC_INLINE void ll_qspi_disable_micro_handshake(qspi_regs_t *QSPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_qspi.h:1393
ll_qspi_set_add_inst_transfer_format
__STATIC_INLINE void ll_qspi_set_add_inst_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_qspi.h:2580
ll_qspi_set_rx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_qspi.h:1649
ll_qspi_disable_clk_stretch
__STATIC_INLINE void ll_qspi_disable_clk_stretch(qspi_regs_t *QSPIx)
Disable the clock stretch feature for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2405
ll_qspi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_qspi.h:1633
ll_qspi_clear_flag_mst
__STATIC_INLINE void ll_qspi_clear_flag_mst(qspi_regs_t *QSPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_qspi.h:2012
ll_qspi_concurrent_set_xip_wrap_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2771
ll_qspi_get_cs_setup_delay
__STATIC_INLINE uint32_t ll_qspi_get_cs_setup_delay(qspi_regs_t *QSPIx)
Get CS Setup Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3867
ll_qspi_get_frame_format
__STATIC_INLINE uint32_t ll_qspi_get_frame_format(qspi_regs_t *QSPIx)
Get data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_qspi.h:883
ll_qspi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_rx(qspi_regs_t *QSPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_qspi.h:2146
ll_qspi_concurrent_enable_xip_mode_bits
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_mode_bits(qspi_regs_t *QSPIx)
Enable the mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2617
_ll_qspi_memorymapped_write_init_t::x_wr_data_frame_format
uint32_t x_wr_data_frame_format
Specifies enhanced spi's frame format in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:230
ll_qspi_concurrent_disable_xip_continuous_xfer
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Disable the continuous transfer feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2951
ll_qspi_get_address_size
__STATIC_INLINE uint32_t ll_qspi_get_address_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_qspi.h:2560
ll_qspi_concurrent_enable_xip_instruction
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_instruction(qspi_regs_t *QSPIx)
Enable the instruction phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2983
_ll_qspi_memorymapped_read_init_t::x_data_frame_format
uint32_t x_data_frame_format
Specifies enhanced spi's frame format in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:181
ll_qspi_concurrent_set_xip_address_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3169
LL_QSPI2_REG_TX_FIFO_DEPTH
#define LL_QSPI2_REG_TX_FIFO_DEPTH
Transmit FIFO Depth Of Register Mode for QSPI2 Master.
Definition: gr55xx_ll_qspi.h:296
ll_qspi_get_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_get_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_qspi.h:2599
_ll_qspi_memorymapped_read_init_t
Definition: gr55xx_ll_qspi.h:134
ll_qspi_enable_it
__STATIC_INLINE void ll_qspi_enable_it(qspi_regs_t *QSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_qspi.h:1756
ll_qspi_enable_slave_out
__STATIC_INLINE void ll_qspi_enable_slave_out(qspi_regs_t *QSPIx)
Enable slave output.
Definition: gr55xx_ll_qspi.h:1097
ll_qspi_disable_dma_req_tx
__STATIC_INLINE void ll_qspi_disable_dma_req_tx(qspi_regs_t *QSPIx)
Disable DMA Tx.
Definition: gr55xx_ll_qspi.h:2086
ll_qspi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_dma_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_qspi.h:2208
ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3733
ll_qspi_receive_data8
__STATIC_INLINE uint8_t ll_qspi_receive_data8(qspi_regs_t *QSPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2277
ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3715
ll_qspi_get_id_code
__STATIC_INLINE uint32_t ll_qspi_get_id_code(qspi_regs_t *QSPIx)
Get ID code.
Definition: gr55xx_ll_qspi.h:1709
ll_qspi_concurrent_is_enabled_xip_continuous_xfer
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_continuous_xfer(qspi_regs_t *QSPIx)
Check if the continuous transfer feature is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2967
_ll_qspi_memorymapped_read_init_t::x_mode_bits_data
uint32_t x_mode_bits_data
Specifies value of mode bits phase.
Definition: gr55xx_ll_qspi.h:175
ll_qspi_disable_xip_dynamic_le
__STATIC_INLINE void ll_qspi_disable_xip_dynamic_le(qspi_regs_t *QSPIx)
Disable qspi xip dynamic little-endian mode.
Definition: gr55xx_ll_qspi.h:3956
ll_qspi_disable_dma_req_rx
__STATIC_INLINE void ll_qspi_disable_dma_req_rx(qspi_regs_t *QSPIx)
Disable DMA Rx.
Definition: gr55xx_ll_qspi.h:2131
_ll_qspi_memorymapped_init_t
Definition: gr55xx_ll_qspi.h:237
ll_qspi_is_enabled_dws
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dws(qspi_regs_t *QSPIx)
Check if dynamic of wait states for QSPI peripheral is enabled.
Definition: gr55xx_ll_qspi.h:3419
ll_qspi_enable_dma_req_tx
__STATIC_INLINE void ll_qspi_enable_dma_req_tx(qspi_regs_t *QSPIx)
Enable DMA Tx.
Definition: gr55xx_ll_qspi.h:2071
ll_qspi_concurrent_set_xip_mode_bits_length
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_length(qspi_regs_t *QSPIx, uint32_t mbl)
Set the length of mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2669
ll_qspi_enable_xip_dynamic_le
__STATIC_INLINE void ll_qspi_enable_xip_dynamic_le(qspi_regs_t *QSPIx)
Enable qspi xip dynamic little-endian mode.
Definition: gr55xx_ll_qspi.h:3938
_ll_qspi_memorymapped_read_init_t::x_continous_xfer_toc
uint32_t x_continous_xfer_toc
Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:195
_ll_qspi_memorymapped_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_ll_qspi.h:255
ll_qspi_get_xip_endian_mode
__STATIC_INLINE uint32_t ll_qspi_get_xip_endian_mode(qspi_regs_t *QSPIx)
Get xip's endian mode.
Definition: gr55xx_ll_qspi.h:3368
_ll_qspi_memorymapped_write_init_t::x_wr_instruction_size
uint32_t x_wr_instruction_size
Specifies instruction size in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:212
ll_qspi_concurrent_get_xip_address_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3200
ll_qspi_concurrent_enable_xip_ss
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable the slave in xip mode.
Definition: gr55xx_ll_qspi.h:2804
ll_qspi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_qspi_get_raw_if_flag(qspi_regs_t *QSPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_qspi.h:1942
ll_qspi_set_tx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_qspi.h:1618
ll_qspi_concurrent_get_xip_wr_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3604
_ll_qspi_memorymapped_read_init_t::x_address_size
uint32_t x_address_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:158
LL_QSPI0_XIP_TX_FIFO_DEPTH
#define LL_QSPI0_XIP_TX_FIFO_DEPTH
Transmit FIFO Depth Of XIP Mode for QSPI0 Master.
Definition: gr55xx_ll_qspi.h:288
_ll_qspi_memorymapped_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_qspi.h:242
ll_qspi_concurrent_set_xip_frame_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3259
ll_qspi_disable_ss
__STATIC_INLINE void ll_qspi_disable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_qspi.h:1520
ll_qspi_memorymapped_read_init_t
struct _ll_qspi_memorymapped_read_init_t ll_qspi_memorymapped_read_init_t
ll_qspi_get_version
__STATIC_INLINE uint32_t ll_qspi_get_version(qspi_regs_t *QSPIx)
Get IP version.
Definition: gr55xx_ll_qspi.h:1724
ll_qspi_concurrent_get_xip_wr_incr_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3537
ll_qspi_set_clock_polarity
__STATIC_INLINE void ll_qspi_set_clock_polarity(qspi_regs_t *QSPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_qspi.h:1186
_ll_qspi_memorymapped_read_init_t::x_instruction_size
uint32_t x_instruction_size
Specifies instruction size in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:152
ll_qspi_concurrent_disable_xip_mode_bits
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_mode_bits(qspi_regs_t *QSPIx)
Disable the mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2633
ll_qspi_concurrent_get_xip_toc
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_toc(qspi_regs_t *QSPIx)
Get time out count for continuous transfer for xip mode.
Definition: gr55xx_ll_qspi.h:2871
ll_qspi_deinit
error_status_t ll_qspi_deinit(qspi_regs_t *QSPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_qspi_concurrent_get_xip_mode_bits_data
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_data(qspi_regs_t *QSPIx)
get the mode phase (sent after address phase) value in xip mode
Definition: gr55xx_ll_qspi.h:2721
ll_qspi_concurrent_set_xip_wr_instruction_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3625
ll_qspi_concurrent_is_enabled_xip_instruction
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_instruction(qspi_regs_t *QSPIx)
Check if the instruction phase is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3015
_ll_qspi_memorymapped_read_init_t::x_dummy_cycles
uint32_t x_dummy_cycles
Specifies wait(dummy) cycles in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:177
_ll_qspi_memorymapped_init_t::wr
ll_qspi_memorymapped_write_init_t wr
Specifies the initized params for write, if rw_mode is readonly, leave un-set.
Definition: gr55xx_ll_qspi.h:262
ll_qspi_get_xip_mode_rx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4020
ll_qspi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_dma_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_qspi.h:2177
ll_qspi_concurrent_enable_xip_prefetch
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_prefetch(qspi_regs_t *QSPIx)
Enable the pre-fetch feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2887
ll_qspi_set_max_wait_cycles
__STATIC_INLINE void ll_qspi_set_max_wait_cycles(qspi_regs_t *QSPIx, uint32_t max_ws)
set the max wait cycles per transaction for dynamic wait state
Definition: gr55xx_ll_qspi.h:3454
ll_qspi_set_xip_endian_mode
__STATIC_INLINE void ll_qspi_set_xip_endian_mode(qspi_regs_t *QSPIx, uint32_t mode)
Set xip's endian mode.
Definition: gr55xx_ll_qspi.h:3344
ll_qspi_set_control_frame_size
__STATIC_INLINE void ll_qspi_set_control_frame_size(qspi_regs_t *QSPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_qspi.h:1005
_ll_qspi_init_t::transfer_direction
uint32_t transfer_direction
Specifies the QSPI transfer or receive mode.
Definition: gr55xx_ll_qspi.h:78
ll_qspi_get_control_frame_size
__STATIC_INLINE uint32_t ll_qspi_get_control_frame_size(qspi_regs_t *QSPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_qspi.h:1037
ll_qspi_get_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_get_wait_cycles(qspi_regs_t *QSPIx)
Get number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_qspi.h:2454
ll_qspi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_qspi_is_enabled_test_mode(qspi_regs_t *QSPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_qspi.h:1082
ll_qspi_is_it_flag
__STATIC_INLINE uint32_t ll_qspi_is_it_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_qspi.h:1918
ll_qspi_receive_data16
__STATIC_INLINE uint16_t ll_qspi_receive_data16(qspi_regs_t *QSPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2292
ll_qspi_transmit_data8
__STATIC_INLINE void ll_qspi_transmit_data8(qspi_regs_t *QSPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2230
ll_qspi_get_rx_sample_edge
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_edge(qspi_regs_t *QSPIx)
Get the RX sample edge.
Definition: gr55xx_ll_qspi.h:2340
ll_qspi_init
error_status_t ll_qspi_init(qspi_regs_t *QSPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
ll_qspi_concurrent_is_enabled_xip_ss
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if the slave is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2838
_ll_qspi_memorymapped_read_init_t::x_mode_bits_length
uint32_t x_mode_bits_length
Specifies mode bits length This parameter can be a value of Mode Bits Length For Xip.
Definition: gr55xx_ll_qspi.h:171
_ll_qspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_qspi.h:117
ll_qspi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_qspi.h:1679
ll_qspi_is_enabled_xip_dynamic_le
__STATIC_INLINE uint32_t ll_qspi_is_enabled_xip_dynamic_le(qspi_regs_t *QSPIx)
Check if qspi xip dynamic little-endian mode is enabled.
Definition: gr55xx_ll_qspi.h:3974
ll_qspi_disable_dws
__STATIC_INLINE void ll_qspi_disable_dws(qspi_regs_t *QSPIx)
Disable dynamic of wait states for QSPI peripheral.
Definition: gr55xx_ll_qspi.h:3404
ll_qspi_concurrent_get_xip_wr_wrap_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3570
ll_qspi_memorymapped_write_init_t
struct _ll_qspi_memorymapped_write_init_t ll_qspi_memorymapped_write_init_t
_ll_qspi_memorymapped_read_init_t::x_instruction_en
uint32_t x_instruction_en
Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:147
LL_QSPI2_XIP_TX_FIFO_DEPTH
#define LL_QSPI2_XIP_TX_FIFO_DEPTH
Transmit FIFO Depth Of XIP Mode for QSPI2 Master.
Definition: gr55xx_ll_qspi.h:298
ll_qspi_is_enabled_ss
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_qspi.h:1539
ll_qspi_set_rx_sample_delay
__STATIC_INLINE void ll_qspi_set_rx_sample_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_qspi.h:2357
_ll_qspi_memorymapped_write_init_t::x_wr_inst_addr_transfer_format
uint32_t x_wr_inst_addr_transfer_format
Specifies xfer format of inst & addr in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:222
_ll_qspi_memorymapped_read_init_t::x_mode_bits_en
uint32_t x_mode_bits_en
Specifies whether to enable mode bits phase in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:166
ll_qspi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_mode(qspi_regs_t *QSPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1482
ll_qspi_concurrent_set_xip_incr_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2738
ll_qspi_clear_flag_rxo
__STATIC_INLINE void ll_qspi_clear_flag_rxo(qspi_regs_t *QSPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_qspi.h:1976
ll_qspi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1445
ll_qspi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_tx(qspi_regs_t *QSPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_qspi.h:2101
ll_qspi_concurrent_get_xip_incr_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2754
ll_qspi_set_micro_transfer_direction
__STATIC_INLINE void ll_qspi_set_micro_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1427
ll_qspi_clear_flag_txo
__STATIC_INLINE void ll_qspi_clear_flag_txo(qspi_regs_t *QSPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_qspi.h:1958
ll_qspi_get_instruction_size
__STATIC_INLINE uint32_t ll_qspi_get_instruction_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_qspi.h:2495
LL_QSPI1_REG_TX_FIFO_DEPTH
#define LL_QSPI1_REG_TX_FIFO_DEPTH
Transmit FIFO Depth Of Register Mode for QSPI1 Master.
Definition: gr55xx_ll_qspi.h:291
ll_qspi_enable_clk_stretch
__STATIC_INLINE void ll_qspi_enable_clk_stretch(qspi_regs_t *QSPIx)
Enable the clock stretch feature for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2389
ll_qspi_set_instruction_size
__STATIC_INLINE void ll_qspi_set_instruction_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_qspi.h:2475
_ll_qspi_memorymapped_read_init_t::x_continous_xfer_en
uint32_t x_continous_xfer_en
Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:190
_ll_qspi_memorymapped_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_qspi.h:246
ll_qspi_memorymapped_mode_e
ll_qspi_memorymapped_mode_e
Definition: gr55xx_ll_qspi.h:128
_ll_qspi_init_t::wait_cycles
uint32_t wait_cycles
Specifies the QSPI dummy clock.
Definition: gr55xx_ll_qspi.h:98
ll_qspi_enable_test_mode
__STATIC_INLINE void ll_qspi_enable_test_mode(qspi_regs_t *QSPIx)
Enable SPI test mode.
Definition: gr55xx_ll_qspi.h:1052
ll_qspi_get_reg_mode_rx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of Register Mode.
Definition: gr55xx_ll_qspi.h:3986
ll_qspi_struct_init
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
ll_qspi_clear_flag_spite
__STATIC_INLINE void ll_qspi_clear_flag_spite(qspi_regs_t *QSPIx)
Clear QSPI Transmit Error interrupt.
Definition: gr55xx_ll_qspi.h:3435
ll_qspi_set_micro_transfer_mode
__STATIC_INLINE void ll_qspi_set_micro_transfer_mode(qspi_regs_t *QSPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1464
_ll_qspi_memorymapped_read_init_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Specifies xfer format of inst & addr in memorymapped(xip) mode.
Definition: gr55xx_ll_qspi.h:162
ll_qspi_get_reg_mode_tx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of Register Mode.
Definition: gr55xx_ll_qspi.h:4003
ll_qspi_set_clock_phase
__STATIC_INLINE void ll_qspi_set_clock_phase(qspi_regs_t *QSPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_qspi.h:1223
ll_qspi_is_hresp_err_debug_mode_enabled
__STATIC_INLINE uint32_t ll_qspi_is_hresp_err_debug_mode_enabled(void)
Check if the AHB Response Error Debug is enabled for all QSPI Modules.
Definition: gr55xx_ll_qspi.h:3827
_ll_qspi_memorymapped_init_t::rw_mode
ll_qspi_memorymapped_mode_e rw_mode
Specifies the access mode for memorymapped: readonly or read&write.
Definition: gr55xx_ll_qspi.h:258
ll_qspi_set_address_size
__STATIC_INLINE void ll_qspi_set_address_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_qspi.h:2528
ll_qspi_concurrent_get_xip_mode_bits_length
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_length(qspi_regs_t *QSPIx)
Get the length of mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2688
_ll_qspi_memorymapped_init_t::rd
ll_qspi_memorymapped_read_init_t rd
Specifies the initized params for read, must set.
Definition: gr55xx_ll_qspi.h:260
ll_qspi_get_xip_mode_tx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4037
ll_qspi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss_toggle(qspi_regs_t *QSPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_qspi.h:844
ll_qspi_disable_ss_toggle
__STATIC_INLINE void ll_qspi_disable_ss_toggle(qspi_regs_t *QSPIx)
Disable slave select toggle.
Definition: gr55xx_ll_qspi.h:828
ll_qspi_init_t
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
ll_qspi_set_baud_rate_prescaler
__STATIC_INLINE void ll_qspi_set_baud_rate_prescaler(qspi_regs_t *QSPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_qspi.h:1556
ll_qspi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_dma_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_qspi.h:2193
ll_qspi_disable_it
__STATIC_INLINE void ll_qspi_disable_it(qspi_regs_t *QSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_qspi.h:1782
ll_qspi_get_data_size
__STATIC_INLINE uint32_t ll_qspi_get_data_size(qspi_regs_t *QSPIx)
Get frame data size.
Definition: gr55xx_ll_qspi.h:972
ll_qspi_enable_xip
void ll_qspi_enable_xip(qspi_regs_t *QSPIx)
Enable qspi xip mode.
ll_qspi_set_rx_sample_edge
__STATIC_INLINE void ll_qspi_set_rx_sample_edge(qspi_regs_t *QSPIx, uint32_t edge)
Set the RX sample edge.
Definition: gr55xx_ll_qspi.h:2324
ll_qspi_memorymapped_init_t
struct _ll_qspi_memorymapped_init_t ll_qspi_memorymapped_init_t
_ll_qspi_memorymapped_write_init_t::x_wr_instruction
uint32_t x_wr_instruction
Specifies instruction in memorymapped(xip) write mode.
Definition: gr55xx_ll_qspi.h:216
ll_qspi_concurrent_get_xip_frame_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3279
LL_QSPI1_XIP_RX_FIFO_DEPTH
#define LL_QSPI1_XIP_RX_FIFO_DEPTH
Receive FIFO Depth Of XIP Mode for QSPI1 Master.
Definition: gr55xx_ll_qspi.h:292
LL_QSPI0_REG_TX_FIFO_DEPTH
#define LL_QSPI0_REG_TX_FIFO_DEPTH
Transmit FIFO Depth Of Register Mode for QSPI0 Master.
Definition: gr55xx_ll_qspi.h:286
_ll_qspi_init_t::data_size
uint32_t data_size
Specifies the QSPI data width.
Definition: gr55xx_ll_qspi.h:103
ll_qspi_get_it_flag
__STATIC_INLINE uint32_t ll_qspi_get_it_flag(qspi_regs_t *QSPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_qspi.h:1888
LL_QSPI2_XIP_RX_FIFO_DEPTH
#define LL_QSPI2_XIP_RX_FIFO_DEPTH
Receive FIFO Depth Of XIP Mode for QSPI2 Master.
Definition: gr55xx_ll_qspi.h:297
ll_qspi_get_tx_start_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_tx_start_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TX transfer start.
Definition: gr55xx_ll_qspi.h:1602
ll_qspi_disable
__STATIC_INLINE void ll_qspi_disable(qspi_regs_t *QSPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_qspi.h:1348
ll_qspi_concurrent_get_xip_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3136
ll_qspi_concurrent_enable_xip_continuous_xfer
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Enable the continuous transfer feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2935
ll_qspi_clear_flag_rxu
__STATIC_INLINE void ll_qspi_clear_flag_rxu(qspi_regs_t *QSPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_qspi.h:1994