gr55xx_ll_i2s.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2s.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2S LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2S I2S
47 * @brief I2S LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2S_M) || defined (I2S_S)
63
64 /** @defgroup LL_I2S_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2S_LL_ES_INIT I2S Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2S init structures definition
75 */
76 typedef struct _ll_i2s_init_t
77 {
78 uint32_t rxdata_size; /**< Specifies the I2S receive data size.
79 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
80
81 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rxsize().*/
82
83 uint32_t txdata_size; /**< Specifies the I2S transmit data size.
84 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_i2s_set_txsize().*/
87
88 uint32_t rx_threshold; /**< Specifies the I2S receive FIFO threshold.
89 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
90
91 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rx_fifo_threshold().*/
92
93 uint32_t tx_threshold; /**< Specifies the I2S transmit FIFO threshold.
94 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
95
96 This feature can be modified afterwards using unitary function @ref ll_i2s_set_tx_fifo_threshold().*/
97
98 uint32_t clock_source; /**< Specifies the source of the I2S clock.
99 This parameter can be a value of @ref I2S_LL_EC_CLOCK_SOURCE.
100
101 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_src().*/
102
103 uint32_t ws_cycles; /**< Specifies the I2S Word Select Line Cycles.
104 This parameter can be a value of @ref I2S_LL_EC_WS_CYCLES.
105 This feature can be modified afterwards using unitary function @ref ll_i2s_set_wss().*/
106
107 uint32_t audio_freq; /**< Specifies the frequency selected for the I2S communication.
108
109 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_div().*/
110
111 } ll_i2s_init_t;
112
113 /** @} */
114
115 /** @} */
116
117 /**
118 * @defgroup I2S_LL_MACRO Defines
119 * @{
120 */
121
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
124 * @{
125 */
126
127 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
128 * @brief Flags definitions which can be used with LL_I2S_ReadReg function
129 * @{
130 */
131 #define LL_I2S_STATUS_TXFO I2S_INT_STAT_TX_FIFO_OVER /**< TX FIFO write overflow flag */
132 #define LL_I2S_STATUS_TXFE I2S_INT_STAT_TX_FIFO_EMPTY /**< TX FIFO threshold level is not reached flag */
133 #define LL_I2S_STATUS_RXFO I2S_INT_STAT_RX_FIFO_OVER /**< RX FIFO receive overflow flag */
134 #define LL_I2S_STATUS_RXDA I2S_INT_STAT_RX_DATA_AVL /**< RX FIFO threshold level is reached flag */
135 /** @} */
136
137 /** @defgroup I2S_LL_EC_INTERRUPT Interrupt Defines
138 * @brief Interrupt definitions which can be used with LL_I2S_ReadReg and LL_I2S_WriteReg functions
139 * @{
140 */
141 #define LL_I2S_INT_TXFO I2S_INT_MASK_TX_FOM /**< TX FIFO write overflow interrupt */
142 #define LL_I2S_INT_TXFE I2S_INT_MASK_TX_FEM /**< TX FIFO threshold level is not reached interrupt */
143 #define LL_I2S_INT_RXFO I2S_INT_MASK_RX_FOM /**< RX FIFO receive overflow interrupt */
144 #define LL_I2S_INT_RXDA I2S_INT_MASK_RX_DAM /**< RX FIFO threshold level is reached interrupt */
145 /** @} */
146
147 /** @defgroup I2S_LL_EC_CLOCK_SOURCE I2S Clock Source
148 * @{
149 */
150 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL) /**< I2S clock source select: 96M */
151 #define LL_I2S_CLOCK_SRC_64M (1UL << 18) /**< I2S clock source select: 64M */
152 #define LL_I2S_CLOCK_SRC_32M (2UL << 18) /**< I2S clock source select: 32M */
153 /** @} */
154
155 /** @defgroup I2S_LL_EC_DATASIZE Transfer Data width
156 * @{
157 */
158 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL) /**< Data size for I2S transfer: 32 bits */
159 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RX_CFG_WORD_LEN_POS) /**< Data size for I2S transfer: 12 bits */
160 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RX_CFG_WORD_LEN_POS) /**< Data size for I2S transfer: 16 bits */
161 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RX_CFG_WORD_LEN_POS) /**< Data size for I2S transfer: 20 bits */
162 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RX_CFG_WORD_LEN_POS) /**< Data size for I2S transfer: 24 bits */
163 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RX_CFG_WORD_LEN_POS) /**< Data size for I2S transfer: 32 bits */
164 /** @} */
165
166 /** @defgroup I2S_LL_EC_TRANSFER_MODE Transfer Mode
167 * @{
168 */
169 #define LL_I2S_SIMPLEX_TX (1UL) /**< Simplex TX mode. */
170 #define LL_I2S_SIMPLEX_RX (2UL) /**< Simplex RX mode. */
171 #define LL_I2S_FULL_DUPLEX (3UL) /**< Full-Duplex mode. */
172 /** @} */
173
174 /** @defgroup I2S_LL_EC_FIFO_THRESHOLD FIFO Threshold
175 * @{
176 */
177 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL) /**< Trigger level for FIFO: 1 depth. */
178 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 2 depth. */
179 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 3 depth. */
180 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 4 depth. */
181 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 5 depth. */
182 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 6 depth. */
183 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 7 depth. */
184 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 8 depth. */
185 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 9 depth. */
186 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 10 depth. */
187 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 11 depth. */
188 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 12 depth. */
189 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 13 depth. */
190 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 14 depth. */
191 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 15 depth. */
192 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) /**< Trigger level for FIFO: 16 depth. */
193 /** @} */
194
195 /** @defgroup I2S_LL_EC_WS_CYCLES Word Select Line Cycles
196 * @{
197 */
198 #define LL_I2S_WS_CYCLES_16 (0x00000000UL) /**< 16 SCLK cycles in word select line. */
199 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_SCLK_CFG_WS_SCLK_POS) /**< 24 SCLK cycles in word select line. */
200 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_SCLK_CFG_WS_SCLK_POS) /**< 32 SCLK cycles in word select line. */
201 /** @} */
202
203 /** @defgroup I2S_LL_EC_SCLK_GATE SCLK Gate
204 * @{
205 */
206 #define LL_I2S_SCLKG_NONE (0x00000000UL) /**< Clock gating is disabled. */
207 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_SCLK_CFG_SCLK_GAT_POS) /**< Gating after 12 sclk cycles. */
208 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_SCLK_CFG_SCLK_GAT_POS) /**< Gating after 16 sclk cycles. */
209 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_SCLK_CFG_SCLK_GAT_POS) /**< Gating after 20 sclk cycles. */
210 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_SCLK_CFG_SCLK_GAT_POS) /**< Gating after 24 sclk cycles. */
211 /** @} */
212
213 /** @defgroup I2S_LL_EC_RESOLUTION RX/TX resolution of one channel
214 * @{
215 */
216 #define LL_I2S_RESOLUTION_12BIT (0UL) /**< 12 bits resolution. */
217 #define LL_I2S_RESOLUTION_16BIT (1UL) /**< 16 bits resolution. */
218 #define LL_I2S_RESOLUTION_20BIT (2UL) /**< 20 bits resolution. */
219 #define LL_I2S_RESOLUTION_24BIT (3UL) /**< 24 bits resolution. */
220 #define LL_I2S_RESOLUTION_32BIT (4UL) /**< 32 bits resolution. */
221 /** @} */
222
223 /** @defgroup I2S_LL_EC_CHANNELS the number of RX/TX channels
224 * @{
225 */
226 #define LL_I2S_CHANNEL_NUM_1 (0UL) /**< 1 channel. */
227 #define LL_I2S_CHANNEL_NUM_2 (1UL) /**< 2 channels. */
228 #define LL_I2S_CHANNEL_NUM_3 (2UL) /**< 3 channels. */
229 #define LL_I2S_CHANNEL_NUM_4 (3UL) /**< 4 channels. */
230 /** @} */
231
232 /** @defgroup I2S_LL_EC_FIFO_DEPTH RX/TX FIFO depth
233 * @{
234 */
235 #define LL_I2S_FIFO_DEPTH_2 (0UL) /**< FIFO depth is 2 . */
236 #define LL_I2S_FIFO_DEPTH_4 (1UL) /**< FIFO depth is 4 . */
237 #define LL_I2S_FIFO_DEPTH_8 (2UL) /**< FIFO depth is 8 . */
238 #define LL_I2S_FIFO_DEPTH_16 (3UL) /**< FIFO depth is 16. */
239 /** @} */
240
241 /** @defgroup I2S_LL_EC_APB_WIDTH APB data width
242 * @{
243 */
244 #define LL_I2S_APB_WIDTH_8BIT (0UL) /**< 8 bits APB data width. */
245 #define LL_I2S_APB_WIDTH_16BIT (1UL) /**< 16 bits APB data width. */
246 #define LL_I2S_APB_WIDTH_32BIT (2UL) /**< 32 bits APB data width. */
247 /** @} */
248
249 /** @defgroup I2S_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
250 * @{
251 */
252
253 /**
254 * @brief LL I2S InitStrcut default configuartion
255 */
256 #define LL_I2S_DEFAULT_CONFIG \
257 { \
258 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
259 .txdata_size = LL_I2S_DATASIZE_16BIT, \
260 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
261 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
262 .clock_source = LL_I2S_CLOCK_SRC_32M, \
263 .audio_freq = 48000 \
264 }
265
266 /** @} */
267
268 /** @} */
269
270 /* Exported macro ------------------------------------------------------------*/
271 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
272 * @{
273 */
274
275 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
276 * @{
277 */
278
279 /**
280 * @brief Write a value in I2S register
281 * @param __instance__ I2S instance
282 * @param __REG__ Register to be written
283 * @param __VALUE__ Value to be written in the register
284 * @retval None
285 */
286 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
287
288 /**
289 * @brief Read a value in I2S register
290 * @param __instance__ I2S instance
291 * @param __REG__ Register to be read
292 * @retval Register value
293 */
294 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
295
296 /** @} */
297
298 /** @} */
299
300 /** @} */
301
302 /* Exported functions --------------------------------------------------------*/
303 /** @defgroup I2S_LL_DRIVER_FUNCTIONS Functions
304 * @{
305 */
306
307 /** @defgroup I2S_LL_EF_Configuration Configuration functions
308 * @{
309 */
310
311 /**
312 * @brief Enable I2S
313 *
314 * Register|BitsName
315 * --------|--------
316 * ENABLE | EN
317 *
318 * @param I2Sx I2S instance
319 * @retval None
320 */
321 __STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
322 {
323 SET_BITS(I2Sx->EN, I2S_EN_I2S_EN);
324 }
325
326 /**
327 * @brief Disable I2S
328 *
329 * Register|BitsName
330 * --------|--------
331 * ENABLE | EN
332 *
333 * @param I2Sx I2S instance
334 * @retval None
335 */
336 __STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
337 {
338 CLEAR_BITS(I2Sx->EN, I2S_EN_I2S_EN);
339 }
340
341 /**
342 * @brief Check if I2S is enabled
343 *
344 * Register|BitsName
345 * --------|--------
346 * ENABLE | EN
347 *
348 * @param I2Sx I2S instance
349 * @retval State of bit (1 or 0).
350 */
351 __STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
352 {
353 return (READ_BITS(I2Sx->EN, I2S_EN_I2S_EN) == (I2S_EN_I2S_EN));
354 }
355
356 /**
357 * @brief Enable I2S RX block
358 *
359 * Register|BitsName
360 * --------|--------
361 * RBEN | EN
362 *
363 * @param I2Sx I2S instance
364 * @retval None
365 */
366 __STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
367 {
368 SET_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN);
369 }
370
371 /**
372 * @brief Disable I2S RX block
373 *
374 * Register|BitsName
375 * --------|--------
376 * RBEN | EN
377 *
378 * @param I2Sx I2S instance
379 * @retval None
380 */
381 __STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
382 {
383 CLEAR_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN);
384 }
385
386 /**
387 * @brief Check if I2S RX block is enabled
388 *
389 * Register|BitsName
390 * --------|--------
391 * RBEN | EN
392 *
393 * @param I2Sx I2S instance
394 * @retval State of bit (1 or 0).
395 */
396 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
397 {
398 return (READ_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN) == (I2S_RX_EN_RX_EN));
399 }
400
401 /**
402 * @brief Enable I2S TX block
403 *
404 * Register|BitsName
405 * --------|--------
406 * TBEN | EN
407 *
408 * @param I2Sx I2S instance
409 * @retval None
410 */
411 __STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
412 {
413 SET_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN);
414 }
415
416 /**
417 * @brief Disable I2S TX block
418 *
419 * Register|BitsName
420 * --------|--------
421 * TBEN | EN
422 *
423 * @param I2Sx I2S instance
424 * @retval None
425 */
426 __STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
427 {
428 CLEAR_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN);
429 }
430
431 /**
432 * @brief Check if I2S TX block is enabled
433 *
434 * Register|BitsName
435 * --------|--------
436 * TBEN | EN
437 *
438 * @param I2Sx I2S instance
439 * @retval State of bit (1 or 0).
440 */
441 __STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
442 {
443 return (READ_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN) == (I2S_TX_EN_TX_EN));
444 }
445
446 /**
447 * @brief Enable I2S clock
448 *
449 * Register|BitsName
450 * --------|--------
451 * CLKEN | EN
452 *
453 * @param I2Sx I2S instance
454 * @retval None
455 */
456 __STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
457 {
458 SET_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN);
459 }
460
461 /**
462 * @brief Disable I2S clock
463 *
464 * Register|BitsName
465 * --------|--------
466 * CLKEN | EN
467 *
468 * @param I2Sx I2S instance
469 * @retval None
470 */
471 __STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
472 {
473 CLEAR_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN);
474 }
475
476 /**
477 * @brief Check if I2S clock is enabled
478 *
479 * Register|BitsName
480 * --------|--------
481 * CLKEN | EN
482 *
483 * @param I2Sx I2S instance
484 * @retval State of bit (1 or 0).
485 */
486 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
487 {
488 return (READ_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN) == (I2S_CLK_EN_CLK_EN));
489 }
490
491 /**
492 * @brief Set word select line cycles for left or right sample
493 * @note This bit should be written only when I2S is disabled (I2S_EN = 0) for correct operation.
494 *
495 * Register|BitsName
496 * --------|--------
497 * CLKCONFIG | WSS
498 *
499 * @param I2Sx I2S instance
500 * @param cycles This parameter can be one of the following values:
501 * @arg @ref LL_I2S_WS_CYCLES_16
502 * @arg @ref LL_I2S_WS_CYCLES_24
503 * @arg @ref LL_I2S_WS_CYCLES_32
504 * @retval None
505 */
506 __STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
507 {
508 MODIFY_REG(I2Sx->SCLK_CFG, I2S_SCLK_CFG_WS_SCLK, cycles);
509 }
510
511 /**
512 * @brief Get word select line cycles for left or right sample
513 *
514 * Register|BitsName
515 * --------|--------
516 * CLKCONFIG | WSS
517 *
518 * @param I2Sx I2S instance
519 * @retval Returned Value can be one of the following values:
520 * @arg @ref LL_I2S_WS_CYCLES_16
521 * @arg @ref LL_I2S_WS_CYCLES_24
522 * @arg @ref LL_I2S_WS_CYCLES_32
523 */
524 __STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
525 {
526 return (uint32_t)(READ_BITS(I2Sx->SCLK_CFG, I2S_SCLK_CFG_WS_SCLK));
527 }
528
529 /**
530 * @brief Set the gating of sclk
531 *
532 * Register|BitsName
533 * --------|--------
534 * CLKCONFIG | SCLKG
535 *
536 * @param I2Sx I2S instance
537 * @param cycles This parameter can be one of the following values:
538 * @arg @ref LL_I2S_SCLKG_NONE
539 * @arg @ref LL_I2S_SCLKG_CYCLES_12
540 * @arg @ref LL_I2S_SCLKG_CYCLES_16
541 * @arg @ref LL_I2S_SCLKG_CYCLES_20
542 * @arg @ref LL_I2S_SCLKG_CYCLES_24
543 * @retval None
544 */
545 __STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
546 {
547 MODIFY_REG(I2Sx->SCLK_CFG, I2S_SCLK_CFG_SCLK_GAT, cycles);
548 }
549
550 /**
551 * @brief Get the gating of sclk
552 *
553 * Register|BitsName
554 * --------|--------
555 * CLKCONFIG | SCLKG
556 *
557 * @param I2Sx I2S instance
558 * @retval Returned Value can be one of the following values:
559 * @arg @ref LL_I2S_SCLKG_NONE
560 * @arg @ref LL_I2S_SCLKG_CYCLES_12
561 * @arg @ref LL_I2S_SCLKG_CYCLES_16
562 * @arg @ref LL_I2S_SCLKG_CYCLES_20
563 * @arg @ref LL_I2S_SCLKG_CYCLES_24
564 */
565 __STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
566 {
567 return (uint32_t)(READ_BITS(I2Sx->SCLK_CFG, I2S_SCLK_CFG_SCLK_GAT));
568 }
569
570 /**
571 * @brief Clear I2S RX FIFO in all channels
572 *
573 * Register|BitsName
574 * --------|--------
575 * RXFIFO_RST | RST
576 *
577 * @param I2Sx I2S instance
578 * @retval None
579 */
580 __STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
581 {
582 WRITE_REG(I2Sx->RX_FIFO_RST, I2S_RX_FIFO_RST_RX_FIFO_RST);
583 }
584
585 /**
586 * @brief Clear I2S TX FIFO in all channels
587 *
588 * Register|BitsName
589 * --------|--------
590 * TXFIFO_RST | RST
591 *
592 * @param I2Sx I2S instance
593 * @retval None
594 */
595 __STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
596 {
597 WRITE_REG(I2Sx->TX_FIFO_RST, I2S_TX_FIFO_RST_TX_FIFO_RST);
598 }
599
600 /**
601 * @brief Set I2S clock divider
602 *
603 * Register|BitsName
604 * --------|--------
605 * I2S_CLK_CFG | DIV
606 *
607 * @param div This parameter can between: 0 ~ 0xFFF
608 * @retval None
609 */
610 __STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
611 {
612 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
613 }
614
615 /**
616 * @brief Get I2S clock divider
617 *
618 * Register|BitsName
619 * --------|--------
620 * I2S_CLK_CFG | DIV
621 *
622 * @retval Returned Value can between: 0 ~ 0xFFF
623 */
624 __STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
625 {
626 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
627 }
628
629 /**
630 * @brief Enable I2S clock divider
631 *
632 * Register|BitsName
633 * --------|--------
634 * I2S_CLK_CFG | DIV_EN
635 *
636 * @retval None
637 */
638 __STATIC_INLINE void ll_i2s_enable_clock_div(void)
639 {
640 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
641 }
642
643 /**
644 * @brief Disable I2S clock divider
645 *
646 * Register|BitsName
647 * --------|--------
648 * I2S_CLK_CFG | DIV_EN
649 *
650 * @retval None
651 */
652 __STATIC_INLINE void ll_i2s_disable_clock_div(void)
653 {
654 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
655 }
656
657 /**
658 * @brief Check if I2S clock divider is enabled
659 *
660 * Register|BitsName
661 * --------|--------
662 * I2S_CLK_CFG | DIV_EN
663 *
664 * @retval State of bit (1 or 0).
665 */
666 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
667 {
668 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
669 }
670
671 /**
672 * @brief Set I2S clock source
673 *
674 * Register|BitsName
675 * --------|--------
676 * I2S_CLK_CFG | SRC
677 *
678 * @param src This parameter can be one of the following values:
679 * @arg @ref LL_I2S_CLOCK_SRC_96M
680 * @arg @ref LL_I2S_CLOCK_SRC_64M
681 * @arg @ref LL_I2S_CLOCK_SRC_32M
682 * @retval None
683 */
684 __STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
685 {
686 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
687 }
688
689 /**
690 * @brief Get I2S clock source
691 *
692 * Register|BitsName
693 * --------|--------
694 * I2S_CLK_CFG | SRC
695 *
696 * @retval Returned Value can be one of the following values:
697 * @arg @ref LL_I2S_CLOCK_SRC_96M
698 * @arg @ref LL_I2S_CLOCK_SRC_32M
699 */
700 __STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
701 {
702 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
703 }
704
705 /**
706 * @brief Enable I2S clock
707 *
708 * Register|BitsName
709 * --------|--------
710 * I2S_CLK_CFG | DIV_EN
711 *
712 * @retval None
713 */
714 __STATIC_INLINE void ll_i2s_enable_src_clock(void)
715 {
716 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN);
717 }
718
719 /**
720 * @brief Disable I2S clock divider
721 *
722 * Register|BitsName
723 * --------|--------
724 * I2S_CLK_CFG | DIV_EN
725 *
726 * @retval None
727 */
728 __STATIC_INLINE void ll_i2s_disable_src_clock(void)
729 {
730 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN);
731 }
732
733 /**
734 * @brief Check if I2S clock divider is enabled
735 *
736 * Register|BitsName
737 * --------|--------
738 * I2S_CLK_CFG | DIV_EN
739 *
740 * @retval State of bit (1 or 0).
741 */
742 __STATIC_INLINE uint32_t ll_i2s_is_enabled_src_clock(void)
743 {
744 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN) == (MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN));
745 }
746
747 /** @} */
748
749 /** @defgroup I2S_LL_EF_Channel Channel Configuration functions
750 * @{
751 */
752
753 /**
754 * @brief Read one data from left RX FIFO in a channel
755 *
756 * Register|BitsName
757 * --------|--------
758 * DATA_L | DATA
759 *
760 * @param I2Sx I2S instance
761 * @retval None
762 */
763 __STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx)
764 {
765 return (uint32_t)(READ_REG(I2Sx->LEFT_BUF));
766 }
767
768 /**
769 * @brief Read one data from right RX FIFO in a channel
770 *
771 * Register|BitsName
772 * --------|--------
773 * DATA_R | DATA
774 *
775 * @param I2Sx I2S instance
776 * @retval None
777 */
778 __STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx)
779 {
780 return (uint32_t)(READ_REG(I2Sx->RIGHT_BUF));
781 }
782
783 /**
784 * @brief Write one data to left TX FIFO in a channel
785 *
786 * Register|BitsName
787 * --------|--------
788 * DATA_L | DATA
789 *
790 * @param I2Sx I2S instance
791 * @param data The data to send
792 * @retval None
793 */
794 __STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint32_t data)
795 {
796 WRITE_REG(I2Sx->LEFT_BUF, data);
797 }
798
799 /**
800 * @brief Write one data to right TX FIFO in a channel
801 *
802 * Register|BitsName
803 * --------|--------
804 * DATA_R | DATA
805 *
806 * @param I2Sx I2S instance
807 * @param data The data to send
808 * @retval None
809 */
810 __STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint32_t data)
811 {
812 WRITE_REG(I2Sx->RIGHT_BUF, data);
813 }
814
815 /**
816 * @brief Enable RX in a channel
817 *
818 * Register|BitsName
819 * --------|--------
820 * RXEN | EN
821 *
822 * @param I2Sx I2S instance
823 * @retval None
824 */
825 __STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx)
826 {
827 SET_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN);
828 }
829
830 /**
831 * @brief Disable RX in a channel
832 *
833 * Register|BitsName
834 * --------|--------
835 * RXEN | EN
836 *
837 * @param I2Sx I2S instance
838 * @retval None
839 */
840 __STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx)
841 {
842 CLEAR_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN);
843 }
844
845 /**
846 * @brief Check if RX in a channel is enabled
847 *
848 * Register|BitsName
849 * --------|--------
850 * RXEN | EN
851 *
852 * @param I2Sx I2S instance
853 * @retval State of bit (1 or 0).
854 */
855 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx)
856 {
857 return (READ_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN) == (I2S_RX_CH_EN_RX_CH_EN));
858 }
859
860 /**
861 * @brief Enable TX in a channel
862 *
863 * Register|BitsName
864 * --------|--------
865 * TXEN | EN
866 *
867 * @param I2Sx I2S instance
868 * @retval None
869 */
870 __STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx)
871 {
872 SET_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN);
873 }
874
875 /**
876 * @brief Disable TX in a channel
877 *
878 * Register|BitsName
879 * --------|--------
880 * TXEN | EN
881 *
882 * @param I2Sx I2S instance
883 * @retval None
884 */
885 __STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx)
886 {
887 CLEAR_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN);
888 }
889
890 /**
891 * @brief Check if TX in a channel is enabled
892 *
893 * Register|BitsName
894 * --------|--------
895 * TXEN | EN
896 *
897 * @param I2Sx I2S instance
898 * @retval State of bit (1 or 0).
899 */
900 __STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx)
901 {
902 return (READ_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN) == (I2S_TX_CH_EN_TX_CH_EN));
903 }
904
905 /**
906 * @brief Set receive data width in a channel
907 * @note These bits should not be changed when channel is enabled.
908 *
909 * Register|BitsName
910 * --------|--------
911 * RXSIZE | WLEN
912 *
913 * @param I2Sx I2S instance
914 * @param size This parameter can be one of the following values:
915 * @arg @ref LL_I2S_DATASIZE_IGNORE
916 * @arg @ref LL_I2S_DATASIZE_12BIT
917 * @arg @ref LL_I2S_DATASIZE_16BIT
918 * @arg @ref LL_I2S_DATASIZE_20BIT
919 * @arg @ref LL_I2S_DATASIZE_24BIT
920 * @arg @ref LL_I2S_DATASIZE_32BIT
921 * @retval None
922 */
923 __STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint32_t size)
924 {
925 MODIFY_REG(I2Sx->RX_CFG, I2S_RX_CFG_WORD_LEN, size);
926 }
927
928 /**
929 * @brief Get receive data width in a channel
930 *
931 * Register|BitsName
932 * --------|--------
933 * RXSIZE | WLEN
934 *
935 * @param I2Sx I2S instance
936 * @retval Returned Value can be one of the following values:
937 * @arg @ref LL_I2S_DATASIZE_IGNORE
938 * @arg @ref LL_I2S_DATASIZE_12BIT
939 * @arg @ref LL_I2S_DATASIZE_16BIT
940 * @arg @ref LL_I2S_DATASIZE_20BIT
941 * @arg @ref LL_I2S_DATASIZE_24BIT
942 * @arg @ref LL_I2S_DATASIZE_32BIT
943 */
944 __STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx)
945 {
946 return (uint32_t)(READ_BITS(I2Sx->RX_CFG, I2S_RX_CFG_WORD_LEN));
947 }
948
949 /**
950 * @brief Set transmit data width in a channel
951 * @note These bits should not be changed when channel is enabled.
952 *
953 * Register|BitsName
954 * --------|--------
955 * TXSIZE | WLEN
956 *
957 * @param I2Sx I2S instance
958 * @param size This parameter can be one of the following values:
959 * @arg @ref LL_I2S_DATASIZE_IGNORE
960 * @arg @ref LL_I2S_DATASIZE_12BIT
961 * @arg @ref LL_I2S_DATASIZE_16BIT
962 * @arg @ref LL_I2S_DATASIZE_20BIT
963 * @arg @ref LL_I2S_DATASIZE_24BIT
964 * @arg @ref LL_I2S_DATASIZE_32BIT
965 * @retval None
966 */
967 __STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx,uint32_t size)
968 {
969 MODIFY_REG(I2Sx->TX_CFG, I2S_TX_CFG_WORD_LEN, size);
970 }
971
972 /**
973 * @brief Get transmit data width in a channel
974 *
975 * Register|BitsName
976 * --------|--------
977 * TXSIZE | WLEN
978 *
979 * @param I2Sx I2S instance
980 * @retval Returned Value can be one of the following values:
981 * @arg @ref LL_I2S_DATASIZE_IGNORE
982 * @arg @ref LL_I2S_DATASIZE_12BIT
983 * @arg @ref LL_I2S_DATASIZE_16BIT
984 * @arg @ref LL_I2S_DATASIZE_20BIT
985 * @arg @ref LL_I2S_DATASIZE_24BIT
986 * @arg @ref LL_I2S_DATASIZE_32BIT
987 */
988 __STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx)
989 {
990 return (uint32_t)(READ_BITS(I2Sx->TX_CFG, I2S_TX_CFG_WORD_LEN));
991 }
992
993 /**
994 * @brief Get interrupt flag in a channel
995 *
996 * Register|BitsName
997 * --------|--------
998 * INTSTAT | TXFO
999 * INTSTAT | TXFE
1000 * INTSTAT | RXFO
1001 * INTSTAT | RXDA
1002 *
1003 * @param I2Sx I2S instance
1004 * @retval Returned Value can be one or more of the following values:
1005 * @arg @ref LL_I2S_STATUS_TXFO
1006 * @arg @ref LL_I2S_STATUS_TXFE
1007 * @arg @ref LL_I2S_STATUS_RXFO
1008 * @arg @ref LL_I2S_STATUS_RXDA
1009 */
1010 __STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx)
1011 {
1012 return (uint32_t)(READ_BITS(I2Sx->INT_STAT, I2S_INT_STAT_TX_FIFO_OVER | I2S_INT_STAT_TX_FIFO_EMPTY | \
1013 I2S_INT_STAT_RX_FIFO_OVER | I2S_INT_STAT_RX_DATA_AVL));
1014 }
1015
1016 /**
1017 * @brief Check interrupt flag in a channel
1018 *
1019 * Register|BitsName
1020 * --------|--------
1021 * INTSTAT | TXFO
1022 * INTSTAT | TXFE
1023 * INTSTAT | RXFO
1024 * INTSTAT | RXDA
1025 *
1026 * @param I2Sx I2S instance
1027 * @param flag This parameter can be one or more of the following values:
1028 * @arg @ref LL_I2S_STATUS_TXFO
1029 * @arg @ref LL_I2S_STATUS_TXFE
1030 * @arg @ref LL_I2S_STATUS_RXFO
1031 * @arg @ref LL_I2S_STATUS_RXDA
1032 * @retval State of bit (1 or 0).
1033 */
1034 __STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint32_t flag)
1035 {
1036 return (uint32_t)(READ_BITS(I2Sx->INT_STAT, flag) == flag);
1037 }
1038
1039 /**
1040 * @brief Enable interrupt in a channel
1041 *
1042 * Register|BitsName
1043 * --------|--------
1044 * INTMASK | TXFO
1045 * INTMASK | TXFE
1046 * INTMASK | RXFO
1047 * INTMASK | RXDA
1048 *
1049 * @param I2Sx I2S instance
1050 * @param mask This parameter can be one or more of the following values:
1051 * @arg @ref LL_I2S_INT_TXFO
1052 * @arg @ref LL_I2S_INT_TXFE
1053 * @arg @ref LL_I2S_INT_RXFO
1054 * @arg @ref LL_I2S_INT_RXDA
1055 * @retval None
1056 */
1057 __STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint32_t mask)
1058 {
1059 CLEAR_BITS(I2Sx->INT_MASK, mask);
1060 }
1061
1062 /**
1063 * @brief Disable interrupt in a channel
1064 *
1065 * Register|BitsName
1066 * --------|--------
1067 * INTMASK | TXFO
1068 * INTMASK | TXFE
1069 * INTMASK | RXFO
1070 * INTMASK | RXDA
1071 *
1072 * @param I2Sx I2S instance
1073 * @param mask This parameter can be one or more of the following values:
1074 * @arg @ref LL_I2S_INT_TXFO
1075 * @arg @ref LL_I2S_INT_TXFE
1076 * @arg @ref LL_I2S_INT_RXFO
1077 * @arg @ref LL_I2S_INT_RXDA
1078 * @retval None
1079 */
1080 __STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint32_t mask)
1081 {
1082 SET_BITS(I2Sx->INT_MASK, mask);
1083 }
1084
1085 /**
1086 * @brief Check if interrupt in a channel is enabled
1087 *
1088 * Register|BitsName
1089 * --------|--------
1090 * INTMASK | TXFO
1091 * INTMASK | TXFE
1092 * INTMASK | RXFO
1093 * INTMASK | RXDA
1094 *
1095 * @param I2Sx I2S instance
1096 * @param mask This parameter can be one or more of the following values:
1097 * @arg @ref LL_I2S_INT_TXFO
1098 * @arg @ref LL_I2S_INT_TXFE
1099 * @arg @ref LL_I2S_INT_RXFO
1100 * @arg @ref LL_I2S_INT_RXDA
1101 * @retval State of bit (1 or 0).
1102 */
1103 __STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint32_t mask)
1104 {
1105 return ((READ_BITS(I2Sx->INT_MASK, mask) ^ (mask)) == (mask));
1106 }
1107
1108 /**
1109 * @brief Clear RX FIFO data overrun interrupt flag in a channel
1110 *
1111 * Register|BitsName
1112 * --------|--------
1113 * RXOVR | RXCHO
1114 *
1115 * @param I2Sx I2S instance
1116 * @retval State of bit (1 or 0).
1117 */
1118 __STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx)
1119 {
1120 return (READ_BITS(I2Sx->RX_OVER, I2S_RX_OVER_RX_CLR_FDO));
1121 }
1122
1123 /**
1124 * @brief Clear TX FIFO data overrun interrupt flag in a channel
1125 *
1126 * Register|BitsName
1127 * --------|--------
1128 * TXOVR | TXCHO
1129 *
1130 * @param I2Sx I2S instance
1131 * @retval State of bit (1 or 0).
1132 */
1133 __STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx)
1134 {
1135 return (READ_BITS(I2Sx->TX_OVER, I2S_TX_OVER_TX_CLR_FDO));
1136 }
1137
1138 /**
1139 * @brief Set threshold of RXFIFO in a channel that triggers an RXDA event
1140 *
1141 * Register|BitsName
1142 * --------|--------
1143 * RXFIFO_TL | TL
1144 *
1145 * @param I2Sx I2S instance
1146 * @param threshold This parameter can be one of the following values:
1147 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1148 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1149 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1150 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1151 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1152 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1153 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1154 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1155 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1156 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1157 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1158 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1159 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1160 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1161 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1162 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1163 * @retval None
1164 */
1165 __STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint32_t threshold)
1166 {
1167 WRITE_REG(I2Sx->RX_FIFO_CFG, threshold);
1168 }
1169
1170 /**
1171 * @brief Get threshold of RXFIFO in a channel that triggers an RXDA event
1172 *
1173 * Register|BitsName
1174 * --------|--------
1175 * RXFIFO_TL | TL
1176 *
1177 * @param I2Sx I2S instance
1178 * @retval Returned Value can be one of the following values:
1179 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1180 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1181 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1182 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1183 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1184 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1185 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1186 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1187 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1188 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1189 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1190 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1191 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1192 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1193 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1194 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1195 */
1196 __STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx)
1197 {
1198 return (uint32_t)(READ_BITS(I2Sx->RX_FIFO_CFG, I2S_RX_FIFO_CFG_RX_FIFO_TL));
1199 }
1200
1201 /**
1202 * @brief Set threshold of TXFIFO in a channel that triggers an TXFE event
1203 *
1204 * Register|BitsName
1205 * --------|--------
1206 * TXFIFO_TL | TL
1207 *
1208 * @param I2Sx I2S instance
1209 * @param threshold This parameter can be one of the following values:
1210 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1211 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1212 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1213 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1214 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1215 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1216 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1217 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1218 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1219 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1220 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1221 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1222 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1223 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1224 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1225 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1226 * @retval None
1227 */
1228 __STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint32_t threshold)
1229 {
1230 WRITE_REG(I2Sx->TX_FIFO_CFG, threshold);
1231 }
1232
1233 /**
1234 * @brief Get threshold of TXFIFO in a channel that triggers an TXFE event
1235 *
1236 * Register|BitsName
1237 * --------|--------
1238 * TXFIFO_TL | TL
1239 *
1240 * @param I2Sx I2S instance
1241 * @retval Returned Value can be one of the following values:
1242 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1243 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1244 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1245 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1246 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1247 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1248 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1249 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1250 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1251 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1252 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1253 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1254 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1255 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1256 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1257 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1258 */
1259 __STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx)
1260 {
1261 return (uint32_t)(READ_BITS(I2Sx->TX_FIFO_CFG, I2S_TX_FIFO_CFG_TX_FIFO_TL));
1262 }
1263
1264 /**
1265 * @brief Clear RX FIFO data in a channel
1266 *
1267 * Register|BitsName
1268 * --------|--------
1269 * RXFIFO_FLUSH | FLUSH
1270 *
1271 * @param I2Sx I2S instance
1272 * @retval None
1273 */
1274 __STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx)
1275 {
1276 WRITE_REG(I2Sx->RX_FIFO_FLUSH, I2S_RX_FIFO_FLUSH_RX_FIFO_RST);
1277 }
1278
1279 /**
1280 * @brief Clear TX FIFO data in a channel
1281 *
1282 * Register|BitsName
1283 * --------|--------
1284 * TXFIFO_FLUSH | FLUSH
1285 *
1286 * @param I2Sx I2S instance
1287 * @retval None
1288 */
1289 __STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx)
1290 {
1291 WRITE_REG(I2Sx->TX_FIFO_FLUSH, I2S_TX_FIFO_FLUSH_TX_FIFO_RST);
1292 }
1293
1294 /** @} */
1295
1296 /** @defgroup I2S_LL_EF_DMA_Management DMA Management Functions
1297 * @{
1298 */
1299
1300 /**
1301 * @brief Reset RX block DMA
1302 * @note The RX DMA can be reset to the lowest channel via this register.
1303 *
1304 * Register|BitsName
1305 * --------|--------
1306 * RXDMA_RST | RST
1307 *
1308 * @param I2Sx I2S instance
1309 * @retval None
1310 */
1311 __STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
1312 {
1313 WRITE_REG(I2Sx->RST_RX_DMA, I2S_RST_RX_DMA_RST_RX_DMA);
1314 }
1315
1316 /**
1317 * @brief Reset TX block DMA
1318 * @note The TX DMA can be reset to the lowest channel via this register.
1319 *
1320 * Register|BitsName
1321 * --------|--------
1322 * TXDMA_RST | RST
1323 *
1324 * @param I2Sx I2S instance
1325 * @retval None
1326 */
1327 __STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
1328 {
1329 WRITE_REG(I2Sx->RST_TX_DMA, I2S_RST_TX_DMA_RST_TX_DMA);
1330 }
1331
1332
1333 /**
1334 * @brief Enable I2S DMA
1335 *
1336 * Register|BitsName
1337 * --------|--------
1338 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1339 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1340 *
1341 * @param I2Sx I2S instance
1342 * @retval None
1343 */
1344 __STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
1345 {
1346 if (I2S_M == I2Sx)
1347 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1348 else
1349 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1350 }
1351
1352 /**
1353 * @brief Disable I2S DMA
1354 *
1355 * Register|BitsName
1356 * --------|--------
1357 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1358 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1359 *
1360 * @param I2Sx I2S instance
1361 * @retval None
1362 */
1363 __STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
1364 {
1365 if (I2S_M == I2Sx)
1366 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1367 else
1368 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1369 }
1370
1371 /**
1372 * @brief Check if I2S DMA is enabled
1373 *
1374 * Register|BitsName
1375 * --------|--------
1376 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1377 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1378 *
1379 * @param I2Sx I2S instance
1380 * @retval State of bit (1 or 0).
1381 */
1382 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
1383 {
1384 if (I2S_M == I2Sx)
1385 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET) == MCU_SUB_I2S_DMA_MODE_SET);
1386 else
1387 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET) == MCU_SUB_I2S_DMA_MODE_S_SET);
1388 }
1389
1390 /**
1391 * @brief Enable I2S DMA mode
1392 *
1393 * Register|BitsName
1394 * --------|--------
1395 * DMA_ACC_SEL | MCU_SUB_I2S_DMA_MODE_SET
1396 * DMA_ACC_SEL | MCU_SUB_I2S_DMA_MODE_S_SET
1397 *
1398 * @param I2Sx I2S instance
1399 * @retval None
1400 */
1401 __STATIC_INLINE void ll_i2s_enable_dma_mode(i2s_regs_t *I2Sx)
1402 {
1403 if (I2S_M == I2Sx)
1404 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1405 else
1406 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1407 }
1408
1409 /**
1410 * @brief Disable I2S DMA mode
1411 *
1412 * Register|BitsName
1413 * --------|--------
1414 * DMA_ACC_SEL | MCU_SUB_I2S_DMA_MODE_SET
1415 * DMA_ACC_SEL | MCU_SUB_I2S_DMA_MODE_S_SET
1416 *
1417 * @param I2Sx I2S instance
1418 * @retval None
1419 */
1420 __STATIC_INLINE void ll_i2s_disable_dma_mode(i2s_regs_t *I2Sx)
1421 {
1422 if (I2S_M == I2Sx)
1423 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1424 else
1425 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1426 }
1427
1428
1429 /**
1430 * @brief Check if I2S DMA mode is enabled
1431 *
1432 * Register|BitsName
1433 * --------|--------
1434 * DMA_ACC_SEL | MCU_SUB_I2S_DMA_MODE_SET
1435 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1436 *
1437 * @param I2Sx I2S instance
1438 * @retval State of bit (1 or 0).
1439 */
1440 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma_mode(i2s_regs_t *I2Sx)
1441 {
1442 if (I2S_M == I2Sx)
1443 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET) == MCU_SUB_I2S_DMA_MODE_SET);
1444 else
1445 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET) == MCU_SUB_I2S_DMA_MODE_S_SET);
1446 }
1447
1448 /** @} */
1449
1450 /** @defgroup I2S_LL_EF_Init I2S_M Initialization and de-initialization functions
1451 * @{
1452 */
1453
1454 /**
1455 * @brief De-initialize I2S registers (Registers restored to their default values).
1456 * @param I2Sx I2S instance
1457 * @retval An error_status_t enumeration value:
1458 * - SUCCESS: I2S registers are de-initialized
1459 * - ERROR: I2S registers are not de-initialized
1460 */
1461 error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx);
1462
1463 /**
1464 * @brief Initialize I2S_M registers according to the specified
1465 * parameters in p_i2s_init.
1466 * @param I2Sx I2S instance
1467 * @param p_i2s_init Pointer to a ll_i2s_init_t structure that contains the configuration
1468 * information for the specified I2S_M peripheral.
1469 * @retval An error_status_t enumeration value:
1470 * - SUCCESS: I2S registers are initialized according to p_i2s_init content
1471 * - ERROR: Problem occurred during I2S Registers initialization
1472 */
1473 error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init);
1474
1475 /**
1476 * @brief Set each field of a @ref ll_i2s_init_t type structure to default value.
1477 * @param p_i2s_init Pointer to a @ref ll_i2s_init_t structure
1478 * whose fields will be set to default values.
1479 * @retval None
1480 */
1481 void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init);
1482
1483 /** @} */
1484
1485 /** @} */
1486
1487 #endif /* I2S_M || I2S_S */
1488
1489 #ifdef __cplusplus
1490 }
1491 #endif
1492
1493 #endif /* __GR55xx_LL_I2S_H__ */
1494
1495 /** @} */
1496
1497 /** @} */
1498
1499 /** @} */
ll_i2s_enable_clock
__STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
Enable I2S clock.
Definition: gr55xx_ll_i2s.h:456
ll_i2s_enable
__STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
Enable I2S.
Definition: gr55xx_ll_i2s.h:321
ll_i2s_get_wss
__STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
Get word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:524
ll_i2s_is_enabled_clock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
Check if I2S clock is enabled.
Definition: gr55xx_ll_i2s.h:486
ll_i2s_disable_txblock
__STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
Disable I2S TX block.
Definition: gr55xx_ll_i2s.h:426
ll_i2s_set_txsize
__STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint32_t size)
Set transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:967
ll_i2s_disable_dma_mode
__STATIC_INLINE void ll_i2s_disable_dma_mode(i2s_regs_t *I2Sx)
Disable I2S DMA mode.
Definition: gr55xx_ll_i2s.h:1420
ll_i2s_enable_rx
__STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx)
Enable RX in a channel.
Definition: gr55xx_ll_i2s.h:825
ll_i2s_transmit_rdata
__STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint32_t data)
Write one data to right TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:810
ll_i2s_struct_init
void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init)
Set each field of a ll_i2s_init_t type structure to default value.
ll_i2s_clr_rxfifo_all
__STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
Clear I2S RX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:580
ll_i2s_clr_txfifo_all
__STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
Clear I2S TX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:595
_ll_i2s_init_t::ws_cycles
uint32_t ws_cycles
Specifies the I2S Word Select Line Cycles.
Definition: gr55xx_ll_i2s.h:103
ll_i2s_enable_dma_mode
__STATIC_INLINE void ll_i2s_enable_dma_mode(i2s_regs_t *I2Sx)
Enable I2S DMA mode.
Definition: gr55xx_ll_i2s.h:1401
ll_i2s_disable_dma
__STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
Disable I2S DMA.
Definition: gr55xx_ll_i2s.h:1363
ll_i2s_receive_ldata
__STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx)
Read one data from left RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:763
_ll_i2s_init_t::tx_threshold
uint32_t tx_threshold
Specifies the I2S transmit FIFO threshold.
Definition: gr55xx_ll_i2s.h:93
ll_i2s_set_wss
__STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
Set word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:506
ll_i2s_disable_rx
__STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx)
Disable RX in a channel.
Definition: gr55xx_ll_i2s.h:840
ll_i2s_clear_it_txovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx)
Clear TX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1133
_ll_i2s_init_t::clock_source
uint32_t clock_source
Specifies the source of the I2S clock.
Definition: gr55xx_ll_i2s.h:98
ll_i2s_enable_dma
__STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
Enable I2S DMA.
Definition: gr55xx_ll_i2s.h:1344
ll_i2s_clr_rxfifo_channel
__STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx)
Clear RX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1274
ll_i2s_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx)
Get threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1196
ll_i2s_is_active_it_flag
__STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint32_t flag)
Check interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1034
ll_i2s_is_enabled_src_clock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_src_clock(void)
Check if I2S clock divider is enabled.
Definition: gr55xx_ll_i2s.h:742
ll_i2s_rst_rxdma
__STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
Reset RX block DMA.
Definition: gr55xx_ll_i2s.h:1311
_ll_i2s_init_t::rx_threshold
uint32_t rx_threshold
Specifies the I2S receive FIFO threshold.
Definition: gr55xx_ll_i2s.h:88
ll_i2s_set_clock_src
__STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
Set I2S clock source.
Definition: gr55xx_ll_i2s.h:684
ll_i2s_disable_src_clock
__STATIC_INLINE void ll_i2s_disable_src_clock(void)
Disable I2S clock divider.
Definition: gr55xx_ll_i2s.h:728
ll_i2s_is_enabled_tx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx)
Check if TX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:900
_ll_i2s_init_t::rxdata_size
uint32_t rxdata_size
Specifies the I2S receive data size.
Definition: gr55xx_ll_i2s.h:78
_ll_i2s_init_t::txdata_size
uint32_t txdata_size
Specifies the I2S transmit data size.
Definition: gr55xx_ll_i2s.h:83
ll_i2s_is_enabled_clock_div
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
Check if I2S clock divider is enabled.
Definition: gr55xx_ll_i2s.h:666
ll_i2s_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx)
Get threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1259
ll_i2s_enable_rxblock
__STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
Enable I2S RX block.
Definition: gr55xx_ll_i2s.h:366
ll_i2s_enable_txblock
__STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
Enable I2S TX block.
Definition: gr55xx_ll_i2s.h:411
ll_i2s_enable_src_clock
__STATIC_INLINE void ll_i2s_enable_src_clock(void)
Enable I2S clock.
Definition: gr55xx_ll_i2s.h:714
_ll_i2s_init_t::audio_freq
uint32_t audio_freq
Specifies the frequency selected for the I2S communication.
Definition: gr55xx_ll_i2s.h:107
ll_i2s_get_clock_src
__STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
Get I2S clock source.
Definition: gr55xx_ll_i2s.h:700
ll_i2s_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint32_t threshold)
Set threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1228
ll_i2s_get_sclkg
__STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
Get the gating of sclk.
Definition: gr55xx_ll_i2s.h:565
ll_i2s_init
error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init)
Initialize I2S_M registers according to the specified parameters in p_i2s_init.
ll_i2s_disable_tx
__STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx)
Disable TX in a channel.
Definition: gr55xx_ll_i2s.h:885
ll_i2s_disable_rxblock
__STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
Disable I2S RX block.
Definition: gr55xx_ll_i2s.h:381
ll_i2s_is_enabled
__STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
Check if I2S is enabled.
Definition: gr55xx_ll_i2s.h:351
ll_i2s_rst_txdma
__STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
Reset TX block DMA.
Definition: gr55xx_ll_i2s.h:1327
ll_i2s_is_enabled_rxblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
Check if I2S RX block is enabled.
Definition: gr55xx_ll_i2s.h:396
ll_i2s_enable_clock_div
__STATIC_INLINE void ll_i2s_enable_clock_div(void)
Enable I2S clock divider.
Definition: gr55xx_ll_i2s.h:638
ll_i2s_set_sclkg
__STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
Set the gating of sclk.
Definition: gr55xx_ll_i2s.h:545
ll_i2s_init_t
struct _ll_i2s_init_t ll_i2s_init_t
LL I2S init structures definition.
ll_i2s_is_enabled_rx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx)
Check if RX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:855
ll_i2s_is_enabled_txblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
Check if I2S TX block is enabled.
Definition: gr55xx_ll_i2s.h:441
ll_i2s_is_enabled_dma
__STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
Check if I2S DMA is enabled.
Definition: gr55xx_ll_i2s.h:1382
ll_i2s_clear_it_rxovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx)
Clear RX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1118
ll_i2s_is_enabled_it
__STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint32_t mask)
Check if interrupt in a channel is enabled.
Definition: gr55xx_ll_i2s.h:1103
ll_i2s_set_rxsize
__STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint32_t size)
Set receive data width in a channel.
Definition: gr55xx_ll_i2s.h:923
ll_i2s_get_rxsize
__STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx)
Get receive data width in a channel.
Definition: gr55xx_ll_i2s.h:944
ll_i2s_enable_it
__STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint32_t mask)
Enable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1057
ll_i2s_receive_rdata
__STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx)
Read one data from right RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:778
ll_i2s_set_clock_div
__STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
Set I2S clock divider.
Definition: gr55xx_ll_i2s.h:610
ll_i2s_get_it_flag
__STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx)
Get interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1010
ll_i2s_transmit_ldata
__STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint32_t data)
Write one data to left TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:794
ll_i2s_disable_clock
__STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
Disable I2S clock.
Definition: gr55xx_ll_i2s.h:471
ll_i2s_is_enabled_dma_mode
__STATIC_INLINE uint32_t ll_i2s_is_enabled_dma_mode(i2s_regs_t *I2Sx)
Check if I2S DMA mode is enabled.
Definition: gr55xx_ll_i2s.h:1440
ll_i2s_get_txsize
__STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx)
Get transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:988
ll_i2s_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint32_t threshold)
Set threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1165
ll_i2s_enable_tx
__STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx)
Enable TX in a channel.
Definition: gr55xx_ll_i2s.h:870
ll_i2s_get_clock_div
__STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
Get I2S clock divider.
Definition: gr55xx_ll_i2s.h:624
ll_i2s_disable_it
__STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint32_t mask)
Disable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1080
_ll_i2s_init_t
LL I2S init structures definition.
Definition: gr55xx_ll_i2s.h:77
ll_i2s_clr_txfifo_channel
__STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx)
Clear TX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1289
ll_i2s_deinit
error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx)
De-initialize I2S registers (Registers restored to their default values).
ll_i2s_disable_clock_div
__STATIC_INLINE void ll_i2s_disable_clock_div(void)
Disable I2S clock divider.
Definition: gr55xx_ll_i2s.h:652
ll_i2s_disable
__STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
Disable I2S.
Definition: gr55xx_ll_i2s.h:336