gr55xx_hal_msio_ex.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_msio_ex.h
5 * @author BLE Driver Team
6 * @brief Header file containing extended macro of MSIO HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_MSIOEx MSIOEx
47 * @brief MSIOEx HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_MSIO_EX_H__
53 #define __GR55xx_HAL_MSIO_EX_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal_def.h"
61 #include "gr55xx_ll_msio.h"
62
63 /* Exported types ------------------------------------------------------------*/
64
65 /**
66 * @defgroup HAL_MSIOEX_MACRO Defines
67 * @{
68 */
69
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup MSIOEx_Exported_Constants MSIOEx Exported Constants
72 * @{
73 */
74
75 /** @defgroup MSIOEx_Mux_Mode MSIOEx Mux Mode definition
76 * @{
77 */
78 #define MSIO_MUX_0 LL_MSIO_MUX_0 /**< MSIO mux mode 0 */
79 #define MSIO_MUX_1 LL_MSIO_MUX_1 /**< MSIO mux mode 1 */
80 #define MSIO_MUX_2 LL_MSIO_MUX_2 /**< MSIO mux mode 2 */
81 #define MSIO_MUX_3 LL_MSIO_MUX_3 /**< MSIO mux mode 3 */
82 #define MSIO_MUX_4 LL_MSIO_MUX_4 /**< MSIO mux mode 4 */
83 #define MSIO_MUX_5 LL_MSIO_MUX_5 /**< MSIO mux mode 5 */
84 #define MSIO_MUX_6 LL_MSIO_MUX_6 /**< MSIO mux mode 6 */
85 #define MSIO_MUX_7 LL_MSIO_MUX_7 /**< MSIO mux mode 7 */
86 /** @} */
87
88 /** @defgroup MSIOEx_Mux_Function_Selection MSIOEx Mux function selection
89 * @{
90 */
91
92 #if defined (GR552xx)
93 /*---------------------------------- GR552xx ------------------------------*/
94
95 /** @defgroup MSIOEx_Common_Selection MSIO PIN common MUX selection(Available for all MSIO pins)
96 * @{
97 */
98
99 #define MSIO_PIN_MUX_GPIO MSIO_MUX_7 /**< MSIO PIN x Mux Select GPIO */
100
101 /** @} */
102
103 /** @defgroup MSIOEx_PIN0_Mux_Selection MSIOA_PIN0 MUX selection
104 * @{
105 */
106 #define MSIOA_PIN0_MUX_PWM0_A MSIO_MUX_0 /**< MSIOA_PIN0 Mux Select PWM0_A */
107 #define MSIOA_PIN0_MUX_SIM_CLK MSIO_MUX_1 /**< MSIOA_PIN0 Mux Select SIM_CLK */
108 #define MSIOA_PIN0_MUX_UART3_RX MSIO_MUX_2 /**< MSIOA_PIN0 Mux Select UART3_RX */
109 #define MSIOA_PIN0_MUX_I2S_SCLK MSIO_MUX_3 /**< MSIOA_PIN0 Mux Select I2S_SCLK */
110 #define MSIOA_PIN0_MUX_I2S_S_SCLK MSIO_MUX_4 /**< MSIOA_PIN0 Mux Select I2S_S_SCLK */
111 #define MSIOA_PIN0_MUX_PDM_DI MSIO_MUX_5 /**< MSIOA_PIN0 Mux Select PDM_DI */
112 /** @} */
113
114 /** @defgroup MSIOEx_PIN1_Mux_Selection MSIOA_PIN1 MUX selection
115 * @{
116 */
117 #define MSIOA_PIN1_MUX_PWM0_B MSIO_MUX_0 /**< MSIOA_PIN1 Mux Select PWM0_B */
118 #define MSIOA_PIN1_MUX_SIM_IO MSIO_MUX_1 /**< MSIOA_PIN1 Mux Select SIM_IO */
119 #define MSIOA_PIN1_MUX_UART3_TX MSIO_MUX_2 /**< MSIOA_PIN1 Mux Select UART3_TX */
120 #define MSIOA_PIN1_MUX_I2S_RX_SDI MSIO_MUX_3 /**< MSIOA_PIN1 Mux Select I2S_RX_SDI */
121 #define MSIOA_PIN1_MUX_I2S_S_RX_SDI MSIO_MUX_4 /**< MSIOA_PIN1 Mux Select I2S_S_RX_SDI */
122 #define MSIOA_PIN1_MUX_PDM_CLKO MSIO_MUX_5 /**< MSIOA_PIN1 Mux Select PDM_CLKO */
123 /** @} */
124
125 /** @defgroup MSIOEx_PIN2_Mux_Selection MSIOA_PIN2 MUX selection
126 * @{
127 */
128 #define MSIOA_PIN2_MUX_PWM0_C MSIO_MUX_0 /**< MSIOA_PIN2 Mux Select PWM0_C */
129 #define MSIOA_PIN2_MUX_SIM_RST_N MSIO_MUX_1 /**< MSIOA_PIN2 Mux Select SIM_RST_N */
130 #define MSIOA_PIN2_MUX_UART3_RTS MSIO_MUX_2 /**< MSIOA_PIN2 Mux Select UART3_RTS */
131 #define MSIOA_PIN2_MUX_I2S_TX_SDO MSIO_MUX_3 /**< MSIOA_PIN2 Mux Select I2S_TX_SDO */
132 #define MSIOA_PIN2_MUX_I2S_S_TX_SDO MSIO_MUX_4 /**< MSIOA_PIN2 Mux Select I2S_S_TX_SDO */
133 #define MSIOA_PIN2_MUX_COEX_WLAN_RX MSIO_MUX_5 /**< MSIOA_PIN2 Mux Select COEX_WLAN_RX */
134 /** @} */
135
136 /** @defgroup MSIOEx_PIN3_Mux_Selection MSIOA_PIN3 MUX selection
137 * @{
138 */
139 #define MSIOA_PIN3_MUX_PWM1_A MSIO_MUX_0 /**< MSIOA_PIN3 Mux Select PWM1_A */
140 #define MSIOA_PIN3_MUX_SIM_PRESENCE MSIO_MUX_1 /**< MSIOA_PIN3 Mux Select SIM_PRESENCE */
141 #define MSIOA_PIN3_MUX_UART3_CTS MSIO_MUX_2 /**< MSIOA_PIN3 Mux Select UART3_CTS */
142 #define MSIOA_PIN3_MUX_I2S_WS MSIO_MUX_3 /**< MSIOA_PIN3 Mux Select I2S_WS */
143 #define MSIOA_PIN3_MUX_I2S_S_WS MSIO_MUX_4 /**< MSIOA_PIN3 Mux Select I2S_S_WS */
144 #define MSIOA_PIN3_MUX_COEX_WLAN_TX MSIO_MUX_5 /**< MSIOA_PIN3 Mux Select COEX_WLAN_TX */
145 /** @} */
146
147 /** @defgroup MSIOEx_PIN4_Mux_Selection MSIOA_PIN4 MUX selection
148 * @{
149 */
150 #define MSIOA_PIN4_MUX_UART2_RTS MSIO_MUX_0 /**< MSIOA_PIN4 Mux Select UART2_RTS */
151 #define MSIOA_PIN4_MUX_PWM1_B MSIO_MUX_1 /**< MSIOA_PIN4 Mux Select PWM1_B */
152 #define MSIOA_PIN4_MUX_I2C3_SDA MSIO_MUX_2 /**< MSIOA_PIN4 Mux Select I2C3_SDA */
153 #define MSIOA_PIN4_MUX_I2C0_SDA MSIO_MUX_4 /**< MSIOA_PIN4 Mux Select I2C0_SDA */
154 #define MSIOA_PIN4_MUX_COEX_BLE_RX MSIO_MUX_5 /**< MSIOA_PIN4 Mux Select COEX_BLE_RX */
155 #define MSIOA_PIN4_MUX_ISO_SYNC0_P MSIO_MUX_6 /**< MSIOA_PIN4 Mux Select ISO_SYNC0_P */
156 /** @} */
157
158 /** @defgroup MSIOEx_PIN5_Mux_Selection MSIOA_PIN5 MUX selection
159 * @{
160 */
161 #define MSIOA_PIN5_MUX_UART2_CTS MSIO_MUX_0 /**< MSIOA_PIN5 Mux Select UART2_CTS */
162 #define MSIOA_PIN5_MUX_PWM1_C MSIO_MUX_1 /**< MSIOA_PIN5 Mux Select PWM1_C */
163 #define MSIOA_PIN5_MUX_I2C3_SCL MSIO_MUX_2 /**< MSIOA_PIN5 Mux Select I2C3_SCL */
164 #define MSIOA_PIN5_MUX_I2C0_SCL MSIO_MUX_4 /**< MSIOA_PIN5 Mux Select I2C0_SCL */
165 #define MSIOA_PIN5_MUX_COEX_BLE_TX MSIO_MUX_5 /**< MSIOA_PIN5 Mux Select COEX_BLE_TX */
166 #define MSIOA_PIN5_MUX_ISO_SYNC1_P MSIO_MUX_6 /**< MSIOA_PIN5 Mux Select ISO_SYNC1_P */
167 /** @} */
168
169 /** @defgroup MSIOEx_PIN6_Mux_Selection MSIOA_PIN6 MUX selection
170 * @{
171 */
172 #define MSIOA_PIN6_MUX_UART2_RX MSIO_MUX_0 /**< MSIOA_PIN6 Mux Select UART2_RX */
173 #define MSIOA_PIN6_MUX_PWM1_B MSIO_MUX_1 /**< MSIOA_PIN6 Mux Select PWM1_B */
174 #define MSIOA_PIN6_MUX_I2C4_SDA MSIO_MUX_2 /**< MSIOA_PIN6 Mux Select I2C4_SDA */
175 #define MSIOA_PIN6_MUX_I2C1_SDA MSIO_MUX_4 /**< MSIOA_PIN6 Mux Select I2C1_SDA */
176 #define MSIOA_PIN6_MUX_ISO_SYNC0_P MSIO_MUX_5 /**< MSIOA_PIN6 Mux Select ISO_SYNC0_P */
177 /** @} */
178
179 /** @defgroup MSIOEx_PIN7_Mux_Selection MSIOA_PIN7 MUX selection
180 * @{
181 */
182 #define MSIOA_PIN7_MUX_UART2_TX MSIO_MUX_0 /**< MSIOA_PIN7 Mux Select UART2_TX */
183 #define MSIOA_PIN7_MUX_PWM1_C MSIO_MUX_1 /**< MSIOA_PIN7 Mux Select PWM1_C */
184 #define MSIOA_PIN7_MUX_I2C4_SCL MSIO_MUX_2 /**< MSIOA_PIN7 Mux Select I2C4_SCL */
185 #define MSIOA_PIN7_MUX_I2C1_SCL MSIO_MUX_4 /**< MSIOA_PIN7 Mux Select I2C1_SCL */
186 #define MSIOA_PIN7_MUX_ISO_SYNC1_P MSIO_MUX_5 /**< MSIOA_PIN7 Mux Select ISO_SYNC1_P */
187 /** @} */
188
189 /**
190 * @brief Check if MSIO mux mode is valid.
191 * @param __MUX__ MSIO mux mode.
192 * @retval SET (__ACTION__ is valid) or RESET (__ACTION__ is invalid)
193 */
194 #define IS_MSIO_MUX(__MUX__) (((__MUX__) <= MSIO_MUX_7))
195
196 /*------------------------------------------------------------------------------------------*/
197 #endif /* GR552xx */
198
199 /** @} */
200
201 /** @} */
202
203 /** @} */
204
205 #ifdef __cplusplus
206 }
207 #endif
208
209 #endif /* __GR55xx_HAL_MSIO_EX_H__ */
210
211 /** @} */
212
213 /** @} */
214
215 /** @} */
216
gr55xx_ll_msio.h
Header file containing functions prototypes of MSIO LL library.
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.