gr55xx_ll_pwm.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef __GR55XX_LL_PWM_H__
52 #define __GR55XX_LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr55xx.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /** @defgroup PWM_LL_STRUCTURES Structures
63 * @{
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
68 * @{
69 */
70
71 /**
72 * @brief LL PWM Output Channel init Structure definition.
73 */
74 typedef struct _ll_pwm_channel_init_t
75 {
76 uint8_t duty; /**< Specifies the duty in PWM output mode.
77 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.
78
79 This feature can be modified afterwards using unitary function ll_pwm_set_compare_xn()
80 where X can be (A, B, C) and n can be (0, 1).*/
81
82 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
83 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
84
85 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
86 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
87
88 uint32_t flickerstop_lvl; /**< Specifies the IO level when channel flicker stop.
89 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
90 } ll_pwm_channel_init_t;
91
92 /**
93 * @brief LL PWM init Structure definition.
94 */
95 typedef struct _ll_pwm_init_t
96 {
97 uint32_t mode; /**< Specifies the PWM output mode.
98 This parameter can be a value of @ref PWM_LL_EC_MODE.
99
100 This feature can be modified afterwards using unitary function @ref ll_pwm_set_mode().*/
101
102 uint32_t align; /**< Specifies the PWM alignment pulses.
103 This parameter can be a value of @ref PWM_LL_EC_ALIGN.*/
104
105 uint32_t prescaler; /**< Specifies the prescaler value which will be used configure PWM output frequency.
106 This parameter must be a number ranges between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
107 This parameter should be larger than 128.
108
109 This feature can be modified afterwards using unitary function @ref ll_pwm_set_prescaler().*/
110
111 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
112 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
113 This parameter is recommended to be larger than 128*prescaler to guarantee an ideal breath effect.
114
115 This feature can be modified afterwards using unitary function @ref ll_pwm_set_breath_prescaler().*/
116
117 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
118 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFF.
119
120 This feature can be modified afterwards using unitary function @ref ll_pwm_set_hold_prescaler().*/
121
122 uint32_t breathstop_lvl; /**< Specifies the IO level when breath stop.
123 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
124
125 ll_pwm_channel_init_t channel_a; /**< Specifies the configuration of channelA.
126 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
127
128 ll_pwm_channel_init_t channel_b; /**< Specifies the configuration of channelB.
129 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
130
131 ll_pwm_channel_init_t channel_c; /**< Specifies the configuration of channelC.
132 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
133
134 } ll_pwm_init_t;
135
136 /** @} */
137
138 /** @} */
139
140 /**
141 * @defgroup PWM_LL_MACRO Defines
142 * @{
143 */
144
145 /* Exported constants --------------------------------------------------------*/
146 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
147 * @{
148 */
149
150 /** @defgroup PWM_LL_EC_MODE PWM mode
151 * @{
152 */
153 #define LL_PWM_FLICKER_MODE (0x00000000U) /**< PWM flicker mode */
154 #define LL_PWM_BREATH_MODE PWM_MODE_BREATHEN /**< PWM breath mode */
155 /** @} */
156
157 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
158 * @{
159 */
160 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
161 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
162 /** @} */
163
164 /** @defgroup PWM_LL_STOP_LVL PWM stop io level
165 * @{
166 */
167 #define LL_PWM_STOP_LVL_LOW (0x00000000U) /**< PWM stop in low io level */
168 #define LL_PWM_STOP_LVL_HIGH (0x00000001U) /**< PWM stop in high io level */
169 /** @} */
170
171 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
172 * @{
173 */
174 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
175 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
176 /** @} */
177
178 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
179 * @{
180 */
181 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
182 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
183 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
184 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
185 /** @} */
186
187 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
188 * @{
189 */
190 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
191 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
192 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
193 /** @} */
194
195 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
196 * @{
197 */
198
199 /**
200 * @brief LL PWM Channel InitStrcut default configuartion
201 */
202 #define LL_PWM_CHANNEL_DEFAULT_CONFIG \
203 { \
204 .duty = 50, \
205 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
206 .flickerstop_lvl = LL_PWM_STOP_LVL_LOW, \
207 }
208
209 /**
210 * @brief LL PWM InitStrcut default configuartion
211 */
212 #define LL_PWM_DEFAULT_CONFIG \
213 { \
214 .mode = LL_PWM_FLICKER_MODE, \
215 .align = LL_PWM_EDGE_ALIGNED, \
216 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
217 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
218 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
219 .breathstop_lvl = LL_PWM_STOP_LVL_LOW, \
220 .channel_a = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
221 .channel_b = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
222 .channel_c = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
223 }
224
225 /** @} */
226
227 /** @} */
228
229 /* Exported macro ------------------------------------------------------------*/
230 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
231 * @{
232 */
233
234 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
235 * @{
236 */
237
238 /**
239 * @brief Write a value in PWM register
240 * @param __instance__ PWM instance
241 * @param __REG__ Register to be written
242 * @param __VALUE__ Value to be written in the register
243 * @retval None
244 */
245 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
246
247 /**
248 * @brief Read a value in PWM register
249 * @param __instance__ PWM instance
250 * @param __REG__ Register to be read
251 * @retval Register value
252 */
253 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
254
255 /** @} */
256
257 /** @} */
258
259 /** @} */
260
261 /* Exported functions --------------------------------------------------------*/
262 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
263 * @{
264 */
265
266 /** @defgroup PWM_LL_EF_Configuration Configuration functions
267 * @{
268 */
269
270 /**
271 * @brief Enable PWM.
272 *
273 * Register|BitsName
274 * --------|--------
275 * MODE | EN
276 *
277 * @param PWMx PWM instance
278 * @retval None
279 */
280 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
281 {
282 SET_BITS(PWMx->MODE, PWM_MODE_EN);
283 }
284
285 /**
286 * @brief Disable PWM.
287 *
288 * Register|BitsName
289 * --------|--------
290 * MODE | EN
291 *
292 * @param PWMx PWM instance
293 * @retval None
294 */
295 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
296 {
297 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
298 }
299
300 /**
301 * @brief Indicate whether the PWM is enabled.
302 *
303 * Register|BitsName
304 * --------|--------
305 * MODE | EN
306 *
307 * @param PWMx PWM instance
308 * @retval State of bit (1 or 0).
309 */
310 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
311 {
312 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
313 }
314
315 /**
316 * @brief Enable PWM pause.
317 *
318 * Register|BitsName
319 * --------|--------
320 * MODE | PAUSE
321 *
322 * @param PWMx PWM instance
323 * @retval None
324 */
325 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
326 {
327 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
328 }
329
330 /**
331 * @brief Disable PWM pause.
332 *
333 * Register|BitsName
334 * --------|--------
335 * MODE | PAUSE
336 *
337 * @param PWMx PWM instance
338 * @retval None
339 */
340 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
341 {
342 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
343 }
344
345 /**
346 * @brief Indicate whether the PWM pause is enabled.
347 *
348 * Register|BitsName
349 * --------|--------
350 * MODE | PAUSE
351 *
352 * @param PWMx PWM instance
353 * @retval State of bit (1 or 0).
354 */
355 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
356 {
357 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
358 }
359
360 /**
361 * @brief Set PWM mode.
362 *
363 * Register|BitsName
364 * --------|--------
365 * MODE | BREATHEN
366 *
367 * @param PWMx PWM instance
368 * @param mode This parameter can be one of the following values:
369 * @arg @ref LL_PWM_FLICKER_MODE
370 * @arg @ref LL_PWM_BREATH_MODE
371 * @retval None
372 */
373 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
374 {
375 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, mode);
376 }
377
378 /**
379 * @brief Get PWM mode.
380 *
381 * Register|BitsName
382 * --------|--------
383 * MODE | BREATHEN
384 *
385 * @param PWMx PWM instance
386 * @retval Return value can be one of the following values:
387 * @arg @ref LL_PWM_FLICKER_MODE
388 * @arg @ref LL_PWM_BREATH_MODE
389 */
390 __STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
391 {
392 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN));
393 }
394
395 /**
396 * @brief Enable positive drive mode in channelA.
397 *
398 * Register|BitsName
399 * --------|--------
400 * MODE | DPENA
401 *
402 * @param PWMx PWM instance
403 * @retval None
404 */
405 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
406 {
407 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
408 }
409
410 /**
411 * @brief Disable positive drive mode in channelA.
412 *
413 * Register|BitsName
414 * --------|--------
415 * MODE | DPENA
416 *
417 * @param PWMx PWM instance
418 * @retval None
419 */
420 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
421 {
422 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
423 }
424
425 /**
426 * @brief Indicate whether the positive drive mode in channelA is enabled.
427 *
428 * Register|BitsName
429 * --------|--------
430 * MODE | DPENA
431 *
432 * @param PWMx PWM instance
433 * @retval State of bit (1 or 0).
434 */
435 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
436 {
437 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
438 }
439
440 /**
441 * @brief Enable positive drive mode in channelB.
442 *
443 * Register|BitsName
444 * --------|--------
445 * MODE | DPENB
446 *
447 * @param PWMx PWM instance
448 * @retval None
449 */
450 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
451 {
452 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
453 }
454
455 /**
456 * @brief Disable positive drive mode in channelB.
457 *
458 * Register|BitsName
459 * --------|--------
460 * MODE | DPENB
461 *
462 * @param PWMx PWM instance
463 * @retval None
464 */
465 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
466 {
467 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
468 }
469
470 /**
471 * @brief Indicate whether the positive drive mode in channelB is enabled.
472 *
473 * Register|BitsName
474 * --------|--------
475 * MODE | DPENB
476 *
477 * @param PWMx PWM instance
478 * @retval State of bit (1 or 0).
479 */
480 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
481 {
482 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
483 }
484
485 /**
486 * @brief Enable positive drive mode in channelC.
487 *
488 * Register|BitsName
489 * --------|--------
490 * MODE | DPENC
491 *
492 * @param PWMx PWM instance
493 * @retval None
494 */
495 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
496 {
497 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
498 }
499
500 /**
501 * @brief Disable positive drive mode in channelC.
502 *
503 * Register|BitsName
504 * --------|--------
505 * MODE | DPENC
506 *
507 * @param PWMx PWM instance
508 * @retval None
509 */
510 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
511 {
512 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
513 }
514
515 /**
516 * @brief Indicate whether the positive drive mode in channelC is enabled.
517 *
518 * Register|BitsName
519 * --------|--------
520 * MODE | DPENC
521 *
522 * @param PWMx PWM instance
523 * @retval State of bit (1 or 0).
524 */
525 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
526 {
527 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
528 }
529
530 /**
531 * @brief Set the channel_a stop level in flicker mode.
532 *
533 * Register|BitsName
534 * --------|--------
535 * MODE | FLICKER_PAUSE_LEVEL_A
536 *
537 * @param PWMx PWM flicker stop level
538 * @param flickerstop_lvl This parameter can be set with 0 or 1.
539 * @retval None
540 */
541 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
542 {
543 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_A_Pos);
544 }
545
546 /**
547 * @brief Get the channel_a stop level in flicker mode.
548 *
549 * Register|BitsName
550 * --------|--------
551 * MODE | FLICKER_PAUSE_LEVEL_A
552 *
553 * @param PWMx
554 * @retval Return value of 0 or 1.
555 */
556 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
557 {
558 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A));
559 }
560
561 /**
562 * @brief Set the channel_b stop level in flicker mode.
563 *
564 * Register|BitsName
565 * --------|--------
566 * MODE | FLICKER_PAUSE_LEVEL_B
567 *
568 * @param PWMx PWM flicker stop level
569 * @param flickerstop_lvl This parameter can be set with 0 or 1.
570 * @retval None
571 */
572 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
573 {
574 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_B_Pos);
575 }
576
577 /**
578 * @brief Get the channel_b stop level in flicker mode.
579 *
580 * Register|BitsName
581 * --------|--------
582 * MODE | FLICKER_PAUSE_LEVEL_B
583 *
584 * @param PWMx
585 * @retval Return value of 0 or 1.
586 */
587 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
588 {
589 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B));
590 }
591
592 /**
593 * @brief Set the channel_c stop level in flicker mode.
594 *
595 * Register|BitsName
596 * --------|--------
597 * MODE | FLICKER_PAUSE_LEVEL_C
598 *
599 * @param PWMx PWM flicker stop level
600 * @param flickerstop_lvl This parameter can be set with 0 or 1.
601 * @retval None
602 */
603 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
604 {
605 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_C_Pos);
606 }
607
608 /**
609 * @brief Get the channel_c stop level in flicker mode.
610 *
611 * Register|BitsName
612 * --------|--------
613 * MODE | FLICKER_PAUSE_LEVEL_C
614 *
615 * @param PWMx
616 * @retval Return value of 0 or 1.
617 */
618 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
619 {
620 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C));
621 }
622
623 /**
624 * @brief Check update active flag
625 *
626 * Register|BitsName
627 * --------|--------
628 * UPDATE | SAG
629 *
630 * @param PWMx PWM instance
631 * @retval State of bit (1 or 0).
632 */
633 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
634 {
635 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
636 }
637
638 /**
639 * @brief Enable update all parameters.
640 *
641 * Register|BitsName
642 * --------|--------
643 * UPDATE | SA
644 *
645 * @param PWMx PWM instance
646 * @retval None
647 */
648 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
649 {
650 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
651 }
652
653 /**
654 * @brief Disable update all parameters.
655 *
656 * Register|BitsName
657 * --------|--------
658 * UPDATE | SA
659 *
660 * @param PWMx PWM instance
661 * @retval None
662 */
663 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
664 {
665 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
666 }
667
668 /**
669 * @brief Indicate whether the update all parameters is enabled.
670 *
671 * Register|BitsName
672 * --------|--------
673 * UPDATE | SA
674 *
675 * @param PWMx PWM instance
676 * @retval State of bit (1 or 0).
677 */
678 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
679 {
680 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
681 }
682
683 /**
684 * @brief Enable update period.
685 *
686 * Register|BitsName
687 * --------|--------
688 * UPDATE | SSPRD
689 *
690 * @param PWMx PWM instance
691 * @retval None
692 */
693 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
694 {
695 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
696 }
697
698 /**
699 * @brief Disable update period.
700 *
701 * Register|BitsName
702 * --------|--------
703 * UPDATE | SSPRD
704 *
705 * @param PWMx PWM instance
706 * @retval None
707 */
708 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
709 {
710 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
711 }
712
713 /**
714 * @brief Indicate whether the update period is enabled.
715 *
716 * Register|BitsName
717 * --------|--------
718 * UPDATE | SSPRD
719 *
720 * @param PWMx PWM instance
721 * @retval State of bit (1 or 0).
722 */
723 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
724 {
725 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
726 }
727
728 /**
729 * @brief Enable update compareA0.
730 *
731 * Register|BitsName
732 * --------|--------
733 * UPDATE | SSCMPA0
734 *
735 * @param PWMx PWM instance
736 * @retval None
737 */
738 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
739 {
740 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
741 }
742
743 /**
744 * @brief Disable update compareA0.
745 *
746 * Register|BitsName
747 * --------|--------
748 * UPDATE | SSCMPA0
749 *
750 * @param PWMx PWM instance
751 * @retval None
752 */
753 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
754 {
755 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
756 }
757
758 /**
759 * @brief Indicate whether the update compareA0 is enabled.
760 *
761 * Register|BitsName
762 * --------|--------
763 * UPDATE | SSCMPA0
764 *
765 * @param PWMx PWM instance
766 * @retval State of bit (1 or 0).
767 */
768 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
769 {
770 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
771 }
772
773 /**
774 * @brief Enable update compareA1.
775 *
776 * Register|BitsName
777 * --------|--------
778 * UPDATE | SSCMPA1
779 *
780 * @param PWMx PWM instance
781 * @retval None
782 */
783 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
784 {
785 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
786 }
787
788 /**
789 * @brief Disable update compareA1.
790 *
791 * Register|BitsName
792 * --------|--------
793 * UPDATE | SSCMPA1
794 *
795 * @param PWMx PWM instance
796 * @retval None
797 */
798 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
799 {
800 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
801 }
802
803 /**
804 * @brief Indicate whether the update compareA1 is enabled.
805 *
806 * Register|BitsName
807 * --------|--------
808 * UPDATE | SSCMPA1
809 *
810 * @param PWMx PWM instance
811 * @retval State of bit (1 or 0).
812 */
813 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
814 {
815 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
816 }
817
818 /**
819 * @brief Enable update compareB0.
820 *
821 * Register|BitsName
822 * --------|--------
823 * UPDATE | SSCMPB0
824 *
825 * @param PWMx PWM instance
826 * @retval None
827 */
828 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
829 {
830 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
831 }
832
833 /**
834 * @brief Disable update compareB0.
835 *
836 * Register|BitsName
837 * --------|--------
838 * UPDATE | SSCMPB0
839 *
840 * @param PWMx PWM instance
841 * @retval None
842 */
843 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
844 {
845 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
846 }
847
848 /**
849 * @brief Indicate whether the update compareB0 is enabled.
850 *
851 * Register|BitsName
852 * --------|--------
853 * UPDATE | SSCMPB0
854 *
855 * @param PWMx PWM instance
856 * @retval State of bit (1 or 0).
857 */
858 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
859 {
860 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
861 }
862
863 /**
864 * @brief Enable update compareB1.
865 *
866 * Register|BitsName
867 * --------|--------
868 * UPDATE | SSCMPB1
869 *
870 * @param PWMx PWM instance
871 * @retval None
872 */
873 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
874 {
875 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
876 }
877
878 /**
879 * @brief Disable update compareB1.
880 *
881 * Register|BitsName
882 * --------|--------
883 * UPDATE | SSCMPB1
884 *
885 * @param PWMx PWM instance
886 * @retval None
887 */
888 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
889 {
890 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
891 }
892
893 /**
894 * @brief Indicate whether the update compareB1 is enabled.
895 *
896 * Register|BitsName
897 * --------|--------
898 * UPDATE | SSCMPB1
899 *
900 * @param PWMx PWM instance
901 * @retval State of bit (1 or 0).
902 */
903 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
904 {
905 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
906 }
907
908 /**
909 * @brief Enable update compareC0.
910 *
911 * Register|BitsName
912 * --------|--------
913 * UPDATE | SSCMPC0
914 *
915 * @param PWMx PWM instance
916 * @retval None
917 */
918 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
919 {
920 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
921 }
922
923 /**
924 * @brief Disable update compareC0.
925 *
926 * Register|BitsName
927 * --------|--------
928 * UPDATE | SSCMPC0
929 *
930 * @param PWMx PWM instance
931 * @retval None
932 */
933 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
934 {
935 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
936 }
937
938 /**
939 * @brief Indicate whether the update compareC0 is enabled.
940 *
941 * Register|BitsName
942 * --------|--------
943 * UPDATE | SSCMPC0
944 *
945 * @param PWMx PWM instance
946 * @retval State of bit (1 or 0).
947 */
948 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
949 {
950 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
951 }
952
953 /**
954 * @brief Enable update compareC1.
955 *
956 * Register|BitsName
957 * --------|--------
958 * UPDATE | SSCMPC1
959 *
960 * @param PWMx PWM instance
961 * @retval None
962 */
963 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
964 {
965 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
966 }
967
968 /**
969 * @brief Disable update compareC1.
970 *
971 * Register|BitsName
972 * --------|--------
973 * UPDATE | SSCMPC1
974 *
975 * @param PWMx PWM instance
976 * @retval None
977 */
978 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
979 {
980 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
981 }
982
983 /**
984 * @brief Indicate whether the update compareC1 is enabled.
985 *
986 * Register|BitsName
987 * --------|--------
988 * UPDATE | SSCMPC1
989 *
990 * @param PWMx PWM instance
991 * @retval State of bit (1 or 0).
992 */
993 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
994 {
995 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
996 }
997
998 /**
999 * @brief Enable update breath period.
1000 *
1001 * Register|BitsName
1002 * --------|--------
1003 * UPDATE | SSBRPRD
1004 *
1005 * @param PWMx PWM instance
1006 * @retval None
1007 */
1008 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
1009 {
1010 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1011 }
1012
1013 /**
1014 * @brief Disable update breath period.
1015 *
1016 * Register|BitsName
1017 * --------|--------
1018 * UPDATE | SSBRPRD
1019 *
1020 * @param PWMx PWM instance
1021 * @retval None
1022 */
1023 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
1024 {
1025 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1026 }
1027
1028 /**
1029 * @brief Indicate whether the update breath period is enabled.
1030 *
1031 * Register|BitsName
1032 * --------|--------
1033 * UPDATE | SSBRPRD
1034 *
1035 * @param PWMx PWM instance
1036 * @retval State of bit (1 or 0).
1037 */
1038 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
1039 {
1040 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
1041 }
1042
1043 /**
1044 * @brief Enable update hold period.
1045 *
1046 * Register|BitsName
1047 * --------|--------
1048 * UPDATE | SSHOLD
1049 *
1050 * @param PWMx PWM instance
1051 * @retval None
1052 */
1053 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
1054 {
1055 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1056 }
1057
1058 /**
1059 * @brief Disable update hold period.
1060 *
1061 * Register|BitsName
1062 * --------|--------
1063 * UPDATE | SSHOLD
1064 *
1065 * @param PWMx PWM instance
1066 * @retval None
1067 */
1068 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1069 {
1070 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1071 }
1072
1073 /**
1074 * @brief Indicate whether the update hold period is enabled.
1075 *
1076 * Register|BitsName
1077 * --------|--------
1078 * UPDATE | SSHOLD
1079 *
1080 * @param PWMx PWM instance
1081 * @retval State of bit (1 or 0).
1082 */
1083 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1084 {
1085 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1086 }
1087
1088 /**
1089 * @brief Enable update active event.
1090 *
1091 * Register|BitsName
1092 * --------|--------
1093 * UPDATE | SSAQCTRL
1094 *
1095 * @param PWMx PWM instance
1096 * @retval None
1097 */
1098 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1099 {
1100 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1101 }
1102
1103 /**
1104 * @brief Disable update active event.
1105 *
1106 * Register|BitsName
1107 * --------|--------
1108 * UPDATE | SSAQCTRL
1109 *
1110 * @param PWMx PWM instance
1111 * @retval None
1112 */
1113 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1114 {
1115 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1116 }
1117
1118 /**
1119 * @brief Indicate whether the update active event is enabled.
1120 *
1121 * Register|BitsName
1122 * --------|--------
1123 * UPDATE | SSAQCTRL
1124 *
1125 * @param PWMx PWM instance
1126 * @retval State of bit (1 or 0).
1127 */
1128 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1129 {
1130 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1131 }
1132
1133 /**
1134 * @brief Set the PWM prescaler.
1135 *
1136 * Register|BitsName
1137 * --------|--------
1138 * PRD | PRD
1139 *
1140 * @param PWMx PWM instance
1141 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1142 * @retval None
1143 */
1144 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1145 {
1146 WRITE_REG(PWMx->PRD, prescaler);
1147 }
1148
1149 /**
1150 * @brief Get the PWM prescaler.
1151 *
1152 * Register|BitsName
1153 * --------|--------
1154 * PRD | PRD
1155 *
1156 * @param PWMx PWM instance
1157 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1158 */
1159 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1160 {
1161 return (READ_REG(PWMx->PRD));
1162 }
1163
1164 /**
1165 * @brief Set the PWM compare counter A0.
1166 *
1167 * Register|BitsName
1168 * --------|--------
1169 * CMPA0 | CMPA0
1170 *
1171 * @param PWMx PWM instance
1172 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1173 * @retval None
1174 */
1175 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1176 {
1177 WRITE_REG(PWMx->CMPA0, compare);
1178 }
1179
1180 /**
1181 * @brief Get the PWM compare counter A0.
1182 *
1183 * Register|BitsName
1184 * --------|--------
1185 * CMPA0 | CMPA0
1186 *
1187 * @param PWMx PWM instance
1188 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1189 */
1190 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1191 {
1192 return (READ_REG(PWMx->CMPA0));
1193 }
1194
1195 /**
1196 * @brief Set the PWM compare counter A1.
1197 *
1198 * Register|BitsName
1199 * --------|--------
1200 * CMPA1 | CMPA1
1201 *
1202 * @param PWMx PWM instance
1203 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1204 * @retval None
1205 */
1206 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1207 {
1208 WRITE_REG(PWMx->CMPA1, compare);
1209 }
1210
1211 /**
1212 * @brief Get the PWM compare counter A1.
1213 *
1214 * Register|BitsName
1215 * --------|--------
1216 * CMPA1 | CMPA1
1217 *
1218 * @param PWMx PWM instance
1219 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1220 */
1221 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1222 {
1223 return (READ_REG(PWMx->CMPA1));
1224 }
1225
1226 /**
1227 * @brief Set the PWM compare counter B0.
1228 *
1229 * Register|BitsName
1230 * --------|--------
1231 * CMPB0 | CMPB0
1232 *
1233 * @param PWMx PWM instance
1234 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1235 * @retval None
1236 */
1237 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1238 {
1239 WRITE_REG(PWMx->CMPB0, compare);
1240 }
1241
1242 /**
1243 * @brief Get the PWM compare counter B0.
1244 *
1245 * Register|BitsName
1246 * --------|--------
1247 * CMPB0 | CMPB0
1248 *
1249 * @param PWMx PWM instance
1250 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1251 */
1252 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1253 {
1254 return (READ_REG(PWMx->CMPB0));
1255 }
1256
1257 /**
1258 * @brief Set the PWM compare counter B1.
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * CMPB1 | CMPB1
1263 *
1264 * @param PWMx PWM instance
1265 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1266 * @retval None
1267 */
1268 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1269 {
1270 WRITE_REG(PWMx->CMPB1, compare);
1271 }
1272
1273 /**
1274 * @brief Get the PWM compare counter B1.
1275 *
1276 * Register|BitsName
1277 * --------|--------
1278 * CMPB1 | CMPB1
1279 *
1280 * @param PWMx PWM instance
1281 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1282 */
1283 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1284 {
1285 return (READ_REG(PWMx->CMPB1));
1286 }
1287
1288 /**
1289 * @brief Set the PWM compare counter C0.
1290 *
1291 * Register|BitsName
1292 * --------|--------
1293 * CMPC0 | CMPC0
1294 *
1295 * @param PWMx PWM instance
1296 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1297 * @retval None
1298 */
1299 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1300 {
1301 WRITE_REG(PWMx->CMPC0, compare);
1302 }
1303
1304 /**
1305 * @brief Get the PWM compare counter C0.
1306 *
1307 * Register|BitsName
1308 * --------|--------
1309 * CMPC0 | CMPC0
1310 *
1311 * @param PWMx PWM instance
1312 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1313 */
1314 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1315 {
1316 return (READ_REG(PWMx->CMPC0));
1317 }
1318
1319 /**
1320 * @brief Set the PWM compare counter C1.
1321 *
1322 * Register|BitsName
1323 * --------|--------
1324 * CMPC1 | CMPC1
1325 *
1326 * @param PWMx PWM instance
1327 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1328 * @retval None
1329 */
1330 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1331 {
1332 WRITE_REG(PWMx->CMPC1, compare);
1333 }
1334
1335 /**
1336 * @brief Get the PWM compare counter C1.
1337 *
1338 * Register|BitsName
1339 * --------|--------
1340 * CMPC1 | CMPC1
1341 *
1342 * @param PWMx PWM instance
1343 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1344 */
1345 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1346 {
1347 return (READ_REG(PWMx->CMPC1));
1348 }
1349
1350 /**
1351 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1352 *
1353 * Register|BitsName
1354 * --------|--------
1355 * AQCTRL | A0
1356 *
1357 * @param PWMx PWM instance
1358 * @param action_event This parameter can be one of the following values:
1359 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1360 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1361 * @arg @ref LL_PWM_ACTIONEVENT_SET
1362 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1363 * @retval None
1364 */
1365 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1366 {
1367 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1368 }
1369
1370 /**
1371 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1372 *
1373 * Register|BitsName
1374 * --------|--------
1375 * AQCTRL | A0
1376 *
1377 * @param PWMx PWM instance
1378 * @retval Return value can be one of the following values:
1379 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1380 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1381 * @arg @ref LL_PWM_ACTIONEVENT_SET
1382 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1383 */
1384 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1385 {
1386 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1387 }
1388
1389 /**
1390 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1391 *
1392 * Register|BitsName
1393 * --------|--------
1394 * AQCTRL | A1
1395 *
1396 * @param PWMx PWM instance
1397 * @param action_event This parameter can be one of the following values:
1398 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1399 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1400 * @arg @ref LL_PWM_ACTIONEVENT_SET
1401 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1402 * @retval None
1403 */
1404 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1405 {
1406 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1407 }
1408
1409 /**
1410 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1411 *
1412 * Register|BitsName
1413 * --------|--------
1414 * AQCTRL | A1
1415 *
1416 * @param PWMx PWM instance
1417 * @retval Return value can be one of the following values:
1418 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1419 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1420 * @arg @ref LL_PWM_ACTIONEVENT_SET
1421 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1422 */
1423 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1424 {
1425 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1426 }
1427
1428 /**
1429 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1430 *
1431 * Register|BitsName
1432 * --------|--------
1433 * AQCTRL | B0
1434 *
1435 * @param PWMx PWM instance
1436 * @param action_event This parameter can be one of the following values:
1437 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1438 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1439 * @arg @ref LL_PWM_ACTIONEVENT_SET
1440 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1441 * @retval None
1442 */
1443 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1444 {
1445 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1446 }
1447
1448 /**
1449 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1450 *
1451 * Register|BitsName
1452 * --------|--------
1453 * AQCTRL | B0
1454 *
1455 * @param PWMx PWM instance
1456 * @retval Return value can be one of the following values:
1457 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1458 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1459 * @arg @ref LL_PWM_ACTIONEVENT_SET
1460 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1461 */
1462 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1463 {
1464 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1465 }
1466
1467 /**
1468 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1469 *
1470 * Register|BitsName
1471 * --------|--------
1472 * AQCTRL | B1
1473 *
1474 * @param PWMx PWM instance
1475 * @param action_event This parameter can be one of the following values:
1476 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1477 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1478 * @arg @ref LL_PWM_ACTIONEVENT_SET
1479 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1480 * @retval None
1481 */
1482 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1483 {
1484 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1485 }
1486
1487 /**
1488 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1489 *
1490 * Register|BitsName
1491 * --------|--------
1492 * AQCTRL | B1
1493 *
1494 * @param PWMx PWM instance
1495 * @retval Return value can be one of the following values:
1496 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1497 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1498 * @arg @ref LL_PWM_ACTIONEVENT_SET
1499 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1500 */
1501 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1502 {
1503 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1504 }
1505
1506 /**
1507 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1508 *
1509 * Register|BitsName
1510 * --------|--------
1511 * AQCTRL | C0
1512 *
1513 * @param PWMx PWM instance
1514 * @param action_event This parameter can be one of the following values:
1515 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1516 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1517 * @arg @ref LL_PWM_ACTIONEVENT_SET
1518 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1519 * @retval None
1520 */
1521 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1522 {
1523 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1524 }
1525
1526 /**
1527 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1528 *
1529 * Register|BitsName
1530 * --------|--------
1531 * AQCTRL | C0
1532 *
1533 * @param PWMx PWM instance
1534 * @retval Return value can be one of the following values:
1535 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1536 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1537 * @arg @ref LL_PWM_ACTIONEVENT_SET
1538 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1539 */
1540 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1541 {
1542 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1543 }
1544
1545 /**
1546 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1547 *
1548 * Register|BitsName
1549 * --------|--------
1550 * AQCTRL | C1
1551 *
1552 * @param PWMx PWM instance
1553 * @param action_event This parameter can be one of the following values:
1554 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1555 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1556 * @arg @ref LL_PWM_ACTIONEVENT_SET
1557 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1558 * @retval None
1559 */
1560 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1561 {
1562 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1563 }
1564
1565 /**
1566 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1567 *
1568 * Register|BitsName
1569 * --------|--------
1570 * AQCTRL | C1
1571 *
1572 * @param PWMx PWM instance
1573 * @retval Return value can be one of the following values:
1574 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1575 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1576 * @arg @ref LL_PWM_ACTIONEVENT_SET
1577 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1578 */
1579 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1580 {
1581 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1582 }
1583
1584 /**
1585 * @brief Set the breath prescaler in breath mode.
1586 *
1587 * Register|BitsName
1588 * --------|--------
1589 * BRPRD | BRPRD
1590 *
1591 * @param PWMx PWM instance
1592 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1593 * @retval None
1594 */
1595 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1596 {
1597 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1598 }
1599
1600 /**
1601 * @brief Get the breath prescaler in breath mode.
1602 *
1603 * Register|BitsName
1604 * --------|--------
1605 * BRPRD | BRPRD
1606 *
1607 * @param PWMx PWM instance
1608 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1609 */
1610 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1611 {
1612 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1613 }
1614
1615 /**
1616 * @brief Set the hold prescaler in breath mode.
1617 *
1618 * Register|BitsName
1619 * --------|--------
1620 * HOLD | HOLD
1621 *
1622 * @param PWMx PWM instance
1623 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1624 * @retval None
1625 */
1626 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1627 {
1628 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1629 }
1630
1631 /**
1632 * @brief Get the hold prescaler in breath mode.
1633 *
1634 * Register|BitsName
1635 * --------|--------
1636 * HOLD | HOLD
1637 *
1638 * @param PWMx PWM instance
1639 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1640 */
1641 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1642 {
1643 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1644 }
1645
1646 /**
1647 * @brief Set the stop level in breath mode.
1648 *
1649 * Register|BitsName
1650 * --------|--------
1651 * MODE | BREATH_PAUSE_LEVEL
1652 *
1653 * @param PWMx PWM breath stop level
1654 * @param breathstop_lvl This parameter can be set with 0 or 1.
1655 * @retval None
1656 */
1657 __STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
1658 {
1659 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL, breathstop_lvl << PWM_MODE_BREATH_PAUSE_LEVEL_Pos);
1660 }
1661
1662 /**
1663 * @brief Get the stop level in breath mode.
1664 *
1665 * Register|BitsName
1666 * --------|--------
1667 * MODE | BREATH_PAUSE_LEVEL
1668 *
1669 * @param PWMx PWM breath stop level
1670 * @retval Return value of 0 or 1.
1671 */
1672 __STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
1673 {
1674 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL));
1675 }
1676
1677 /** @} */
1678
1679 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
1680 * @{
1681 */
1682
1683 /**
1684 * @brief De-initialize PWM registers (Registers restored to their default values).
1685 * @param PWMx PWM instance
1686 * @retval An error_status_t enumeration value:
1687 * - SUCCESS: PWM registers are de-initialized
1688 * - ERROR: PWM registers are not de-initialized
1689 */
1690 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
1691
1692 /**
1693 * @brief Initialize PWM registers according to the specified
1694 * parameters in PWM_InitStruct.
1695 * @param PWMx PWM instance
1696 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
1697 * information for the specified PWM peripheral.
1698 * @retval An error_status_t enumeration value:
1699 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
1700 * - ERROR: Problem occurred during PWM Registers initialization
1701 */
1702 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
1703
1704 /**
1705 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
1706 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
1707 * whose fields will be set to default values.
1708 * @retval None
1709 */
1710 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
1711
1712 /** @} */
1713
1714 /** @} */
1715
1716 #endif /* PWM0 || PWM1 */
1717
1718 #ifdef __cplusplus
1719 }
1720 #endif
1721
1722 #endif /* __GR55XX_LL_PWM_H__ */
1723
1724 /** @} */
1725
1726 /** @} */
1727
1728 /** @} */
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: gr55xx_ll_pwm.h:978
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: gr55xx_ll_pwm.h:480
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1299
_ll_pwm_init_t::channel_c
ll_pwm_channel_init_t channel_c
Specifies the configuration of channelC.
Definition: gr55xx_ll_pwm.h:131
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1443
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1314
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1330
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1175
ll_pwm_get_flicker_stop_level_c
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
Get the channel_c stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:618
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1579
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: gr55xx_ll_pwm.h:96
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: gr55xx_ll_pwm.h:1113
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: gr55xx_ll_pwm.h:843
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: gr55xx_ll_pwm.h:648
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1159
_ll_pwm_init_t::breathstop_lvl
uint32_t breathstop_lvl
Specifies the IO level when breath stop.
Definition: gr55xx_ll_pwm.h:122
ll_pwm_init
error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1190
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1610
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: gr55xx_ll_pwm.h:1068
ll_pwm_deinit
error_status_t ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
_ll_pwm_channel_init_t::drive_polarity
uint8_t drive_polarity
Specifies the drive polarity in PWM output mode.
Definition: gr55xx_ll_pwm.h:82
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: gr55xx_ll_pwm.h:903
_ll_pwm_init_t::bprescaler
uint32_t bprescaler
Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
Definition: gr55xx_ll_pwm.h:111
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: gr55xx_ll_pwm.h:1098
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1365
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1206
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1283
ll_pwm_get_mode
__STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: gr55xx_ll_pwm.h:390
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: gr55xx_ll_pwm.h:678
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1482
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: gr55xx_ll_pwm.h:310
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: gr55xx_ll_pwm.h:933
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1462
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: gr55xx_ll_pwm.h:798
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: gr55xx_ll_pwm.h:325
_ll_pwm_channel_init_t::flickerstop_lvl
uint32_t flickerstop_lvl
Specifies the IO level when channel flicker stop.
Definition: gr55xx_ll_pwm.h:88
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: gr55xx_ll_pwm.h:1128
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: gr55xx_ll_pwm.h:768
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: gr55xx_ll_pwm.h:858
_ll_pwm_init_t::mode
uint32_t mode
Specifies the PWM output mode.
Definition: gr55xx_ll_pwm.h:97
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1252
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: gr55xx_ll_pwm.h:693
_ll_pwm_init_t::hprescaler
uint32_t hprescaler
Specifies the required prescaler in breath hold state.
Definition: gr55xx_ll_pwm.h:117
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: gr55xx_ll_pwm.h:1053
ll_pwm_set_breath_stop_level
__STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
Set the stop level in breath mode.
Definition: gr55xx_ll_pwm.h:1657
ll_pwm_set_flicker_stop_level_b
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_b stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:572
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1595
ll_pwm_get_breath_stop_level
__STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
Get the stop level in breath mode.
Definition: gr55xx_ll_pwm.h:1672
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: gr55xx_ll_pwm.h:355
_ll_pwm_init_t::channel_b
ll_pwm_channel_init_t channel_b
Specifies the configuration of channelB.
Definition: gr55xx_ll_pwm.h:128
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: gr55xx_ll_pwm.h:963
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: gr55xx_ll_pwm.h:888
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: gr55xx_ll_pwm.h:340
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: gr55xx_ll_pwm.h:435
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1560
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1221
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: gr55xx_ll_pwm.h:723
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: gr55xx_ll_pwm.h:1038
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: gr55xx_ll_pwm.h:828
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: gr55xx_ll_pwm.h:873
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: gr55xx_ll_pwm.h:708
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1641
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: gr55xx_ll_pwm.h:753
ll_pwm_set_flicker_stop_level_c
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_c stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:603
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: gr55xx_ll_pwm.h:1008
_ll_pwm_init_t::align
uint32_t align
Specifies the PWM alignment pulses.
Definition: gr55xx_ll_pwm.h:102
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: gr55xx_ll_pwm.h:738
ll_pwm_channel_init_t
struct _ll_pwm_channel_init_t ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: gr55xx_ll_pwm.h:1083
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1423
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: gr55xx_ll_pwm.h:663
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: gr55xx_ll_pwm.h:633
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1626
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: gr55xx_ll_pwm.h:948
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:510
_ll_pwm_init_t::channel_a
ll_pwm_channel_init_t channel_a
Specifies the configuration of channelA.
Definition: gr55xx_ll_pwm.h:125
_ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr55xx_ll_pwm.h:75
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1268
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: gr55xx_ll_pwm.h:993
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:450
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: gr55xx_ll_pwm.h:280
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:465
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: gr55xx_ll_pwm.h:295
_ll_pwm_init_t::prescaler
uint32_t prescaler
Specifies the prescaler value which will be used configure PWM output frequency.
Definition: gr55xx_ll_pwm.h:105
ll_pwm_get_flicker_stop_level_a
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
Get the channel_a stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:556
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1237
ll_pwm_set_flicker_stop_level_a
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_a stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:541
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:420
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1521
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:495
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1404
ll_pwm_get_flicker_stop_level_b
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
Get the channel_b stop level in flicker mode.
Definition: gr55xx_ll_pwm.h:587
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1345
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: gr55xx_ll_pwm.h:1023
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1384
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: gr55xx_ll_pwm.h:783
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1144
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1501
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: gr55xx_ll_pwm.h:918
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: gr55xx_ll_pwm.h:525
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
Set PWM mode.
Definition: gr55xx_ll_pwm.h:373
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: gr55xx_ll_pwm.h:813
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1540
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:405
_ll_pwm_channel_init_t::duty
uint8_t duty
Specifies the duty in PWM output mode.
Definition: gr55xx_ll_pwm.h:76