gr55xx_ll_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (DMA) || defined (DMA0) || defined (DMA1)
63
64
65 /** @defgroup DMA_LL_STRUCTURES Structures
66 * @{
67 */
68
69 /* Exported types ------------------------------------------------------------*/
70 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
71 * @{
72 */
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init
77 {
78 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
79
80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
81
82 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory or form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t mode; /**< Specifies the Single block or Multi-block operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref ll_dma_set_mode(). */
98
99 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
100 This parameter can be a value of @ref DMA_LL_EC_SOURCE
101
102 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_increment_mode(). */
103
104 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
105 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
106
107 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_increment_mode(). */
108
109 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
110 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
111
112 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_width(). */
113
114 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
115 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_width(). */
118
119 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
120 The data unit is equal to the source buffer configuration set in src_data_width parameters.
121 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFF
122
123 This feature can be modified afterwards using unitary function @ref ll_dma_set_block_size(). */
124
125 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
126 This parameter can be a value of @ref DMA_LL_EC_PERIPH
127
128 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_peripheral(). */
129
130 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
131 This parameter can be a value of @ref DMA_LL_EC_PERIPH
132
133 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_peripheral(). */
134
135 uint32_t priority; /**< Specifies the channel priority level.
136 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref ll_dma_set_channel_priority_level(). */
139 } ll_dma_init_t;
140
141 /** @} */
142
143 /** @} */
144
145 /**
146 * @defgroup DMA_LL_MACRO Defines
147 * @{
148 */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
152 * @{
153 */
154
155 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
156 * @{
157 */
158 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
159 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
160 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
161 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
162 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
163 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /**< DMA Channel 5 */
164 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /**< DMA Channel 6 */
165 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /**< DMA Channel 7 */
166 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all (used only for function @ref ll_dma_deinit(). */
167 /** @} */
168
169 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
170 * @{
171 */
172 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
173 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
174 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
175 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
176 /** @} */
177
178
179 /** @defgroup DMA_LL_EC_MODE Transfer mode
180 * @{
181 */
182 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U) /**< Single block */
183 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC /**< Multi-block: src address reload, dst address contiguous */
184 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST /**< Multi-block: src address contiguous, dst address reload */
185 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST) /**< Multi-block: src address reload, dst address reload */
186 /** @} */
187
188 /** @defgroup DMA_LL_EC_LLP_DST Destination LLP Enable
189 * @{
190 */
191 #define LL_DMA_LLP_DST_ENABLE DMA_CTLL_LLP_DST_EN_ENABLE /**< Destination LLP Enable */
192 #define LL_DMA_LLP_DST_DISABLE DMA_CTLL_LLP_DST_EN_DISABLE /**< Destination LLP Disable */
193 /** @} */
194
195 /** @defgroup DMA_LL_EC_LLP_SRC Source LLP Enable
196 * @{
197 */
198 #define LL_DMA_LLP_SRC_ENABLE DMA_CTLL_LLP_SRC_EN_ENABLE /**< Source LLP Enable */
199 #define LL_DMA_LLP_SRC_DISABLE DMA_CTLL_LLP_SRC_EN_DISABLE /**< Source LLP Disable */
200 /** @} */
201
202 /** @defgroup LL_DMA_DST_STAT_UPDATE_EN Destination Status Update Enable
203 * @{
204 */
205 #define LL_DMA_SRC_STAT_UPDATE_ENABLE DMA_CFGH_SS_UPD_ENABLE /**< Destination Status Update Enable */
206 #define LL_DMA_SRC_STAT_UPDATE_DISABLE DMA_CFGH_SS_UPD_DISABLE /**< Destination Status Update Enable */
207 /** @} */
208
209 /** @defgroup LL_DMA_SRC_STAT_UPDATE_EN Source Status Update Enable
210 * @{
211 */
212 #define LL_DMA_DST_STAT_UPDATE_ENABLE DMA_CFGH_DS_UPD_ENABLE /**< Source Status Update Enable */
213 #define LL_DMA_DST_STAT_UPDATE_DISABLE DMA_CFGH_DS_UPD_DISABLE /**< Source Status Update Enable */
214 /** @} */
215
216 /** @defgroup DMA_LL_EC_DST_SCATTER Destination Scatter Enable
217 * @{
218 */
219 #define LL_DMA_DST_SCATTER_ENABLE DMA_CTLL_DST_SCATTER_EN_ENABLE /**< Destination Scatter Enable */
220 #define LL_DMA_DST_SCATTER_DISABLE DMA_CTLL_DST_SCATTER_EN_DISABLE /**< Destination Scatter Disable */
221 /** @} */
222
223 /** @defgroup DMA_LL_EC_SRC_GATHER Source Gather Enable
224 * @{
225 */
226 #define LL_DMA_SRC_GATHER_ENABLE DMA_CTLL_SRC_GATHER_EN_ENABLE /**< Source Gather Enable */
227 #define LL_DMA_SRC_GATHER_DISABLE DMA_CTLL_SRC_GATHER_EN_DISABLE /**< Source Gather Disable */
228 /** @} */
229
230
231 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
232 * @{
233 */
234 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
235 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
236 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
237 /** @} */
238
239 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
240 * @{
241 */
242 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
243 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
244 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
245 /** @} */
246
247 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
248 * @{
249 */
250 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
251 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
252 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
253 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
254 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
255 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
256 /** @} */
257
258 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
259 * @{
260 */
261 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
262 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
263 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
264 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
265 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
266 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
267 /** @} */
268
269 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
270 * @{
271 */
272 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
273 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
274 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
275 /** @} */
276
277 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
278 * @{
279 */
280 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
281 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
282 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
283 /** @} */
284
285 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
286 * @{
287 */
288 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
289 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
290 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
291 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
292 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
293 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
294 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
295 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
296 /** @} */
297
298 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
299 * @{
300 */
301 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
302 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
303 /** @} */
304
305 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
306 * @{
307 */
308 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
309 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
310 /** @} */
311
312 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
313 * @{
314 */
315 /********************************* definition for DMA0 **************************************/
316 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU) /**< DMA peripheral type is Memory */
317
318 /********************************* definition for DMA0 HS0 **************************************/
319 #define LL_DMA0_PERIPH_QSPI0_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is QSPIM0 TX */
320 #define LL_DMA0_PERIPH_QSPI0_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is QSPIM0 RX */
321 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIM TX */
322 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIM RX */
323 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is SPIS TX */
324 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is SPIS RX */
325 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is UART0 TX */
326 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is UART0 RX */
327 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is UART1 TX */
328 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is UART1 RX */
329 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU) /**< DMA peripheral type is SNSADC */
330 #define LL_DMA0_PERIPH_OSPI_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is OSPIM TX */
331 #define LL_DMA0_PERIPH_OSPI_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is OSPIM RX */
332 #define LL_DMA0_PERIPH_UART2_TX ((uint32_t)0x0000000EU) /**< DMA Peripheral type is UART2 TX */
333 #define LL_DMA0_PERIPH_UART2_RX ((uint32_t)0x0000000FU) /**< DMA Peripheral type is UART2 RX */
334
335 /********************************* definition for DMA0 HS1**************************************/
336 #define LL_DMA0_PERIPH_I2C2_TX ((uint32_t)0x00000012U) /**< DMA Peripheral type is I2C2 TX */
337 #define LL_DMA0_PERIPH_I2C2_RX ((uint32_t)0x00000013U) /**< DMA Peripheral type is I2C2 RX */
338 #define LL_DMA0_PERIPH_UART3_TX ((uint32_t)0x00000014U) /**< DMA Peripheral type is UART3 TX */
339 #define LL_DMA0_PERIPH_UART3_RX ((uint32_t)0x00000015U) /**< DMA Peripheral type is UART3 RX */
340 #define LL_DMA0_PERIPH_I2C5_TX ((uint32_t)0x00000016U) /**< DMA Peripheral type is I2C5 TX */
341 #define LL_DMA0_PERIPH_I2C5_RX ((uint32_t)0x00000017U) /**< DMA Peripheral type is I2C5 RX */
342 #define LL_DMA0_PERIPH_I2C4_TX ((uint32_t)0x00000018U) /**< DMA Peripheral type is I2C4 TX */
343 #define LL_DMA0_PERIPH_I2C4_RX ((uint32_t)0x00000019U) /**< DMA Peripheral type is I2C5 RX */
344 #define LL_DMA0_PERIPH_UART4_TX ((uint32_t)0x0000001AU) /**< DMA Peripheral type is UART4 TX */
345 #define LL_DMA0_PERIPH_UART4_RX ((uint32_t)0x0000001BU) /**< DMA Peripheral type is UART4 RX */
346 #define LL_DMA0_PERIPH_QSPI1_TX ((uint32_t)0x0000001CU) /**< DMA Peripheral type is QSPIM1 TX */
347 #define LL_DMA0_PERIPH_QSPI1_RX ((uint32_t)0x0000001DU) /**< DMA Peripheral type is QSPIM1 RX */
348 #define LL_DMA0_PERIPH_I2C3_TX ((uint32_t)0x0000001EU) /**< DMA Peripheral type is I2C3 TX */
349 #define LL_DMA0_PERIPH_I2C3_RX ((uint32_t)0x0000001FU) /**< DMA Peripheral type is I2C3 RX */
350
351 /********************************* definition for DMA1**************************************/
352 #define LL_DMA1_PERIPH_MEM ((uint32_t)0x00000009U) /**< DMA peripheral type is Memory */
353
354 /********************************* definition for DMA1 HS0 **************************************/
355 #define LL_DMA1_PERIPH_OSPI_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is OSPIM TX */
356 #define LL_DMA1_PERIPH_OSPI_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is OSPIM RX */
357 #define LL_DMA1_PERIPH_QSPI2_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is QSPIM2 TX */
358 #define LL_DMA1_PERIPH_QSPI2_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is QSPIM2 RX */
359 #define LL_DMA1_PERIPH_I2S_M_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is IIS_M TX */
360 #define LL_DMA1_PERIPH_I2S_M_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is IIS_M RX */
361 #define LL_DMA1_PERIPH_I2S_S_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is IIS_S TX */
362 #define LL_DMA1_PERIPH_I2S_S_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is IIS_S RX */
363 #define LL_DMA1_PERIPH_PDM_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is PDM TX */
364 #define LL_DMA1_PERIPH_QSPI1_TX ((uint32_t)0x0000000AU) /**< DMA Peripheral type is QSPIM1 TX */
365 #define LL_DMA1_PERIPH_QSPI1_RX ((uint32_t)0x0000000BU) /**< DMA Peripheral type is QSPIM1 RX */
366
367 #define LL_DMA1_PERIPH_I2C0_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is I2C0 TX */
368 #define LL_DMA1_PERIPH_I2C0_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is I2C0 RX */
369 #define LL_DMA1_PERIPH_I2C1_TX ((uint32_t)0x0000000EU) /**< DMA Peripheral type is I2C1 TX */
370 #define LL_DMA1_PERIPH_I2C1_RX ((uint32_t)0x0000000FU) /**< DMA Peripheral type is I2C1 RX */
371
372 /********************************* definition for DMA1 HS1 **************************************/
373 #define LL_DMA1_PERIPH_SPIM_TX ((uint32_t)0x00000010U) /**< DMA Peripheral type is SPIM TX */
374 #define LL_DMA1_PERIPH_SPIM_RX ((uint32_t)0x00000011U) /**< DMA Peripheral type is SPIM RX */
375 #define LL_DMA1_PERIPH_DSPIM_TX ((uint32_t)0x00000012U) /**< DMA Peripheral type is DSPIM TX */
376 #define LL_DMA1_PERIPH_DSPIM_RX ((uint32_t)0x00000013U) /**< DMA Peripheral type is DSPIM RX */
377 #define LL_DMA1_PERIPH_QSPI1_TX_2 ((uint32_t)0x00000014U) /**< DMA Peripheral type is QSPI1 TX */
378 #define LL_DMA1_PERIPH_QSPI1_RX_2 ((uint32_t)0x00000015U) /**< DMA Peripheral type is QSPI1 RX */
379 #define LL_DMA1_PERIPH_UART3_TX ((uint32_t)0x00000016U) /**< DMA Peripheral type is UART3 TX */
380 #define LL_DMA1_PERIPH_UART3_RX ((uint32_t)0x00000017U) /**< DMA Peripheral type is UART3 RX */
381 #define LL_DMA1_PERIPH_UART4_TX ((uint32_t)0x00000018U) /**< DMA Peripheral type is UART4 TX */
382 #define LL_DMA1_PERIPH_UART4_RX ((uint32_t)0x00000019U) /**< DMA Peripheral type is UART4 RX */
383 #define LL_DMA1_PERIPH_UART5_TX ((uint32_t)0x0000001AU) /**< DMA Peripheral type is UART5 TX */
384 #define LL_DMA1_PERIPH_UART5_RX ((uint32_t)0x0000001BU) /**< DMA Peripheral type is UART5 RX */
385 #define LL_DMA1_PERIPH_UART0_TX ((uint32_t)0x0000001EU) /**< DMA Peripheral type is UART0 TX */
386 #define LL_DMA1_PERIPH_UART0_RX ((uint32_t)0x0000001FU) /**< DMA Peripheral type is UART0 RX */
387
388 /** @} */
389
390 /** @} */
391
392 /* Exported macro ------------------------------------------------------------*/
393 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
394 * @{
395 */
396
397 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
398 * @{
399 */
400
401 /**
402 * @brief Write a value in DMA register
403 * @param __instance__ DMA instance
404 * @param __REG__ Register to be written
405 * @param __VALUE__ Value to be written in the register
406 * @retval None
407 */
408 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
409
410 /**
411 * @brief Read a value in DMA register
412 * @param __instance__ DMA instance
413 * @param __REG__ Register to be read
414 * @retval Register value
415 */
416 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
417
418 /** @} */
419
420 /** @} */
421
422 /** @} */
423
424 /* Exported functions --------------------------------------------------------*/
425 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
426 * @{
427 */
428
429 /** @defgroup DMA_LL_EF_Configuration Configuration functions
430 * @{
431 */
432
433 /**
434 * @brief Enable DMA Module.
435 * @note This function is used to enable the DMA Module, which must be done before any
436 * channel activity can begin.
437 *
438 * Register|BitsName
439 * --------|--------
440 * CFG_REG | CFG_EN
441 *
442 * @param DMAx DMA instance.
443 * @retval None
444 */
445 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
446 {
447 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
448 }
449
450 /**
451 * @brief Disable DMA Module.
452 * @note If the ll_dma_disable() function is called while any dma channel is still active,
453 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
454 * still active until hardware has terminated all cativity on all channels, at which
455 * point the ll_dma_is_enable() function returns 0.
456 *
457 * Register|BitsName
458 * --------|--------
459 * CFG_REG | CFG_EN
460 *
461 * @param DMAx DMA instance.
462 * @retval None
463 */
464 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
465 {
466 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
467 }
468
469 /**
470 * @brief Check if DMA Module is enabled or disabled.
471 *
472 * Register|BitsName
473 * --------|--------
474 * CFG_REG | CFG_EN
475 *
476 * @param DMAx DMA instance.
477 * @retval State of bit (1 or 0).
478 */
479 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
480 {
481 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
482 }
483
484 /**
485 * @brief Enable DMA channel.
486 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
487 * is ignored and call ll_dma_disable_channel() function will always returns 0.
488 *
489 * Register|BitsName
490 * --------|--------
491 * CH_EN_REG | CH_EN_WE&CH_EN
492 *
493 * @param DMAx DMA instance.
494 * @param channel This parameter can be one of the following values:
495 * @arg @ref LL_DMA_CHANNEL_0
496 * @arg @ref LL_DMA_CHANNEL_1
497 * @arg @ref LL_DMA_CHANNEL_2
498 * @arg @ref LL_DMA_CHANNEL_3
499 * @arg @ref LL_DMA_CHANNEL_4
500 * @arg @ref LL_DMA_CHANNEL_5
501 * @arg @ref LL_DMA_CHANNEL_6
502 * @arg @ref LL_DMA_CHANNEL_7
503 * @retval None
504 */
505 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
506 {
507 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
508 }
509
510 /**
511 * @brief Disable DMA channel.
512 *
513 * Register|BitsName
514 * --------|--------
515 * CH_EN_REG | CH_EN_WE&CH_EN
516 *
517 * @param DMAx DMA instance.
518 * @param channel This parameter can be one of the following values:
519 * @arg @ref LL_DMA_CHANNEL_0
520 * @arg @ref LL_DMA_CHANNEL_1
521 * @arg @ref LL_DMA_CHANNEL_2
522 * @arg @ref LL_DMA_CHANNEL_3
523 * @arg @ref LL_DMA_CHANNEL_4
524 * @arg @ref LL_DMA_CHANNEL_5
525 * @arg @ref LL_DMA_CHANNEL_6
526 * @arg @ref LL_DMA_CHANNEL_7
527 * @retval None
528 */
529 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
530 {
531 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
532 }
533
534 /**
535 * @brief Check if DMA channel is enabled or disabled.
536 * @note Software can therefore poll this function to determine when channel is free
537 * for a new DMA transfer.
538 *
539 * Register|BitsName
540 * --------|--------
541 * CH_EN_REG | CH_EN_WE&CH_EN
542 *
543 * @param DMAx DMA instance.
544 * @param channel This parameter can be one of the following values:
545 * @arg @ref LL_DMA_CHANNEL_0
546 * @arg @ref LL_DMA_CHANNEL_1
547 * @arg @ref LL_DMA_CHANNEL_2
548 * @arg @ref LL_DMA_CHANNEL_3
549 * @arg @ref LL_DMA_CHANNEL_4
550 * @arg @ref LL_DMA_CHANNEL_5
551 * @arg @ref LL_DMA_CHANNEL_6
552 * @arg @ref LL_DMA_CHANNEL_7
553 * @retval State of bit (1 or 0).
554 */
555 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
556 {
557 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
558 }
559
560 /**
561 * @brief Suspend a DMA channel transfer.
562 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
563 * function is called. The function may be called after enabling the DMA channel.
564 *
565 * Register|BitsName
566 * --------|--------
567 * CFGL | CH_SUSP
568 *
569 * @param DMAx DMA instance.
570 * @param channel This parameter can be one of the following values:
571 * @arg @ref LL_DMA_CHANNEL_0
572 * @arg @ref LL_DMA_CHANNEL_1
573 * @arg @ref LL_DMA_CHANNEL_2
574 * @arg @ref LL_DMA_CHANNEL_3
575 * @arg @ref LL_DMA_CHANNEL_4
576 * @arg @ref LL_DMA_CHANNEL_5
577 * @arg @ref LL_DMA_CHANNEL_6
578 * @arg @ref LL_DMA_CHANNEL_7
579 * @retval None
580 */
581 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
582 {
583 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
584 }
585
586 /**
587 * @brief Resume a DMA channel.
588 * @note The function may be called after enabling the DMA channel.
589 *
590 * Register|BitsName
591 * --------|--------
592 * CFGL | CH_SUSP
593 *
594 * @param DMAx DMA instance.
595 * @param channel This parameter can be one of the following values:
596 * @arg @ref LL_DMA_CHANNEL_0
597 * @arg @ref LL_DMA_CHANNEL_1
598 * @arg @ref LL_DMA_CHANNEL_2
599 * @arg @ref LL_DMA_CHANNEL_3
600 * @arg @ref LL_DMA_CHANNEL_4
601 * @arg @ref LL_DMA_CHANNEL_5
602 * @arg @ref LL_DMA_CHANNEL_6
603 * @arg @ref LL_DMA_CHANNEL_7
604 * @retval None
605 */
606 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
607 {
608 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
609 }
610
611 /**
612 * @brief Check if DMA channel is suspended or resumed.
613 *
614 * Register|BitsName
615 * --------|--------
616 * CFGL | CH_SUSP
617 *
618 * @param DMAx DMA instance.
619 * @param channel This parameter can be one of the following values:
620 * @arg @ref LL_DMA_CHANNEL_0
621 * @arg @ref LL_DMA_CHANNEL_1
622 * @arg @ref LL_DMA_CHANNEL_2
623 * @arg @ref LL_DMA_CHANNEL_3
624 * @arg @ref LL_DMA_CHANNEL_4
625 * @arg @ref LL_DMA_CHANNEL_5
626 * @arg @ref LL_DMA_CHANNEL_6
627 * @arg @ref LL_DMA_CHANNEL_7
628 * @retval State of bit (1 or 0).
629 */
630 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
631 {
632 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
633 }
634
635 /**
636 * @brief Check if DMA channel FIFO is empty.
637 *
638 * Register|BitsName
639 * --------|--------
640 * CFGL | FIFO_EMPTY
641 *
642 * @param DMAx DMA instance.
643 * @param channel This parameter can be one of the following values:
644 * @arg @ref LL_DMA_CHANNEL_0
645 * @arg @ref LL_DMA_CHANNEL_1
646 * @arg @ref LL_DMA_CHANNEL_2
647 * @arg @ref LL_DMA_CHANNEL_3
648 * @arg @ref LL_DMA_CHANNEL_4
649 * @arg @ref LL_DMA_CHANNEL_5
650 * @arg @ref LL_DMA_CHANNEL_6
651 * @arg @ref LL_DMA_CHANNEL_7
652 * @retval State of bit (1 or 0).
653 */
654 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
655 {
656 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
657 }
658
659 /**
660 * @brief Configure all parameters link to DMA transfer.
661 *
662 * Register|BitsName
663 * --------|--------
664 * CCR | DIR
665 * CCR | MEM2MEM
666 * CCR | CIRC
667 * CCR | PINC
668 * CCR | MINC
669 * CCR | PSIZE
670 * CCR | MSIZE
671 * CCR | PL
672 *
673 * @param DMAx DMAx instance
674 * @param channel This parameter can be one of the following values:
675 * @arg @ref LL_DMA_CHANNEL_0
676 * @arg @ref LL_DMA_CHANNEL_1
677 * @arg @ref LL_DMA_CHANNEL_2
678 * @arg @ref LL_DMA_CHANNEL_3
679 * @arg @ref LL_DMA_CHANNEL_4
680 * @arg @ref LL_DMA_CHANNEL_5
681 * @arg @ref LL_DMA_CHANNEL_6
682 * @arg @ref LL_DMA_CHANNEL_7
683 * @param configuration This parameter must be a combination of all the following values:
684 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK or @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
685 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
686 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
687 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
688 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
689 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
690 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
691 * @retval None
692 */
693 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
694 {
695 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
696 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
697 }
698
699 /**
700 * @brief Set Data transfer direction (read from peripheral or from memory).
701 *
702 * Register|BitsName
703 * --------|--------
704 * CTL_LO | TT_FC
705 *
706 * @param DMAx DMAx instance
707 * @param channel This parameter can be one of the following values:
708 * @arg @ref LL_DMA_CHANNEL_0
709 * @arg @ref LL_DMA_CHANNEL_1
710 * @arg @ref LL_DMA_CHANNEL_2
711 * @arg @ref LL_DMA_CHANNEL_3
712 * @arg @ref LL_DMA_CHANNEL_4
713 * @arg @ref LL_DMA_CHANNEL_5
714 * @arg @ref LL_DMA_CHANNEL_6
715 * @arg @ref LL_DMA_CHANNEL_7
716 * @param direction This parameter can be one of the following values:
717 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
718 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
719 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
720 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
721 * @retval None
722 */
723 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
724 {
725 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
726 }
727
728 /**
729 * @brief Get Data transfer direction (read from peripheral or from memory).
730 *
731 * Register|BitsName
732 * --------|--------
733 * CTL_LO | TT_FC
734 *
735 * @param DMAx DMAx instance
736 * @param channel This parameter can be one of the following values:
737 * @arg @ref LL_DMA_CHANNEL_0
738 * @arg @ref LL_DMA_CHANNEL_1
739 * @arg @ref LL_DMA_CHANNEL_2
740 * @arg @ref LL_DMA_CHANNEL_3
741 * @arg @ref LL_DMA_CHANNEL_4
742 * @arg @ref LL_DMA_CHANNEL_5
743 * @arg @ref LL_DMA_CHANNEL_6
744 * @arg @ref LL_DMA_CHANNEL_7
745 * @retval Returned value can be one of the following values:
746 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
747 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
748 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
749 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
750 */
751 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
752 {
753 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
754 }
755
756 /**
757 * @brief Set DMA mode Single block or Multi block.
758 * @note The circular buffer mode cannot be used if the memory-to-memory
759 * data transfer is configured on the selected Channel.
760 *
761 * Register|BitsName
762 * --------|--------
763 * CFG_LO | RELOAD_DST
764 *
765 * @param DMAx DMAx instance
766 * @param channel This parameter can be one of the following values:
767 * @arg @ref LL_DMA_CHANNEL_0
768 * @arg @ref LL_DMA_CHANNEL_1
769 * @arg @ref LL_DMA_CHANNEL_2
770 * @arg @ref LL_DMA_CHANNEL_3
771 * @arg @ref LL_DMA_CHANNEL_4
772 * @arg @ref LL_DMA_CHANNEL_5
773 * @arg @ref LL_DMA_CHANNEL_6
774 * @arg @ref LL_DMA_CHANNEL_7
775 * @param mode This parameter can be one of the following values:
776 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
777 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
778 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
779 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
780 * @retval None
781 */
782 __STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
783 {
784 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
785 }
786
787
788 /**
789 * @brief Get DMA mode circular or normal.
790 *
791 * Register|BitsName
792 * --------|--------
793 * CFG_LO | RELOAD_DST
794 *
795 * @param DMAx DMAx instance
796 * @param channel This parameter can be one of the following values:
797 * @arg @ref LL_DMA_CHANNEL_0
798 * @arg @ref LL_DMA_CHANNEL_1
799 * @arg @ref LL_DMA_CHANNEL_2
800 * @arg @ref LL_DMA_CHANNEL_3
801 * @arg @ref LL_DMA_CHANNEL_4
802 * @arg @ref LL_DMA_CHANNEL_5
803 * @arg @ref LL_DMA_CHANNEL_6
804 * @arg @ref LL_DMA_CHANNEL_7
805 * @retval Returned value can be one of the following values:
806 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
807 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
808 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
809 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
810 */
811 __STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
812 {
813 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
814 }
815
816 /**
817 * @brief Set Maximum AMBA Burst Length.
818 *
819 * Register|BitsName
820 * --------|--------
821 * CFG_LO | MAX_ABRST
822 *
823 * @param DMAx DMAx instance
824 * @param channel This parameter can be one of the following values:
825 * @arg @ref LL_DMA_CHANNEL_0
826 * @arg @ref LL_DMA_CHANNEL_1
827 * @arg @ref LL_DMA_CHANNEL_2
828 * @arg @ref LL_DMA_CHANNEL_3
829 * @arg @ref LL_DMA_CHANNEL_4
830 * @arg @ref LL_DMA_CHANNEL_5
831 * @arg @ref LL_DMA_CHANNEL_6
832 * @arg @ref LL_DMA_CHANNEL_7
833 * @param beats This parameter can be one of the following values:
834 Between Min_Data = 0 and Max_Data = 0x3FFU.
835 * @retval None
836 */
837 __STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
838 {
839 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
840 }
841
842 /**
843 * @brief Get source status after each block tranfer completed.
844 *
845 * Register|BitsName
846 * --------|--------
847 * SSTAT | SSTAT
848 *
849 * @param DMAx DMAx instance
850 * @param channel This parameter can be one of the following values:
851 * @arg @ref LL_DMA_CHANNEL_0
852 * @arg @ref LL_DMA_CHANNEL_1
853 * @arg @ref LL_DMA_CHANNEL_2
854 * @arg @ref LL_DMA_CHANNEL_3
855 * @arg @ref LL_DMA_CHANNEL_4
856 * @arg @ref LL_DMA_CHANNEL_5
857 * @arg @ref LL_DMA_CHANNEL_6
858 * @arg @ref LL_DMA_CHANNEL_7
859 * @retval Returned value can be one of the following values:
860 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
861 * @retval None
862 */
863 __STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
864 {
865 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
866 }
867
868 /**
869 * @brief Set source status after each block tranfer completed.
870 *
871 * Register|BitsName
872 * --------|--------
873 * SSTAT | SSTAT
874 *
875 * @param DMAx DMAx instance
876 * @param channel This parameter can be one of the following values:
877 * @arg @ref LL_DMA_CHANNEL_0
878 * @arg @ref LL_DMA_CHANNEL_1
879 * @arg @ref LL_DMA_CHANNEL_2
880 * @arg @ref LL_DMA_CHANNEL_3
881 * @arg @ref LL_DMA_CHANNEL_4
882 * @arg @ref LL_DMA_CHANNEL_5
883 * @arg @ref LL_DMA_CHANNEL_6
884 * @arg @ref LL_DMA_CHANNEL_7
885 * @param sstat This parameter can be one of the following values:
886 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
887 * @retval None
888 */
889 __STATIC_INLINE void ll_dma_set_sstat(dma_regs_t *DMAx, uint32_t channel, uint32_t sstat)
890 {
891 MODIFY_REG(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT, sstat);
892 }
893
894 /**
895 * @brief Get source status after each block tranfer completed.
896 *
897 * Register|BitsName
898 * --------|--------
899 * SSTAT | SSTAT
900 *
901 * @param DMAx DMAx instance
902 * @param channel This parameter can be one of the following values:
903 * @arg @ref LL_DMA_CHANNEL_0
904 * @arg @ref LL_DMA_CHANNEL_1
905 * @arg @ref LL_DMA_CHANNEL_2
906 * @arg @ref LL_DMA_CHANNEL_3
907 * @arg @ref LL_DMA_CHANNEL_4
908 * @arg @ref LL_DMA_CHANNEL_5
909 * @arg @ref LL_DMA_CHANNEL_6
910 * @arg @ref LL_DMA_CHANNEL_7
911 * @retval Returned value can be one of the following values:
912 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
913 * @retval None
914 */
915 __STATIC_INLINE uint32_t ll_dma_get_sstat(dma_regs_t *DMAx, uint32_t channel)
916 {
917 return READ_BITS(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT);
918 }
919
920 /**
921 * @brief Set deatination status after each block tranfer completed.
922 *
923 * Register|BitsName
924 * --------|--------
925 * DSTAT | DSTAT
926 *
927 * @param DMAx DMAx instance
928 * @param channel This parameter can be one of the following values:
929 * @arg @ref LL_DMA_CHANNEL_0
930 * @arg @ref LL_DMA_CHANNEL_1
931 * @arg @ref LL_DMA_CHANNEL_2
932 * @arg @ref LL_DMA_CHANNEL_3
933 * @arg @ref LL_DMA_CHANNEL_4
934 * @arg @ref LL_DMA_CHANNEL_5
935 * @arg @ref LL_DMA_CHANNEL_6
936 * @arg @ref LL_DMA_CHANNEL_7
937 * @param dstat This parameter can be one of the following values:
938 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
939 * @retval None
940 */
941 __STATIC_INLINE void ll_dma_set_dstat(dma_regs_t *DMAx, uint32_t channel, uint32_t dstat)
942 {
943 MODIFY_REG(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT, dstat);
944 }
945
946 /**
947 * @brief Get deatination status after each block tranfer completed.
948 *
949 * Register|BitsName
950 * --------|--------
951 * DSTAT | DSTAT
952 *
953 * @param DMAx DMAx instance
954 * @param channel This parameter can be one of the following values:
955 * @arg @ref LL_DMA_CHANNEL_0
956 * @arg @ref LL_DMA_CHANNEL_1
957 * @arg @ref LL_DMA_CHANNEL_2
958 * @arg @ref LL_DMA_CHANNEL_3
959 * @arg @ref LL_DMA_CHANNEL_4
960 * @arg @ref LL_DMA_CHANNEL_5
961 * @arg @ref LL_DMA_CHANNEL_6
962 * @arg @ref LL_DMA_CHANNEL_7
963 * @retval Returned value can be one of the following values:
964 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
965 */
966 __STATIC_INLINE uint32_t ll_dma_get_dstat(dma_regs_t *DMAx, uint32_t channel)
967 {
968 return READ_BITS(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT);
969 }
970
971 /**
972 * @brief Set source status address after each block tranfer completed.
973 *
974 * Register|BitsName
975 * --------|--------
976 * SSTATAR | SSTATAR
977 *
978 * @param DMAx DMAx instance
979 * @param channel This parameter can be one of the following values:
980 * @arg @ref LL_DMA_CHANNEL_0
981 * @arg @ref LL_DMA_CHANNEL_1
982 * @arg @ref LL_DMA_CHANNEL_2
983 * @arg @ref LL_DMA_CHANNEL_3
984 * @arg @ref LL_DMA_CHANNEL_4
985 * @arg @ref LL_DMA_CHANNEL_5
986 * @arg @ref LL_DMA_CHANNEL_6
987 * @arg @ref LL_DMA_CHANNEL_7
988 * @param sstatar This parameter can be one of the following values:
989 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
990 * @retval None
991 */
992 __STATIC_INLINE void ll_dma_set_sstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t sstatar)
993 {
994 MODIFY_REG(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR, sstatar);
995 }
996
997 /**
998 * @brief Get source status address after each block tranfer completed.
999 *
1000 * Register|BitsName
1001 * --------|--------
1002 * SSTATAR | SSTATAR
1003 *
1004 * @param DMAx DMAx instance
1005 * @param channel This parameter can be one of the following values:
1006 * @arg @ref LL_DMA_CHANNEL_0
1007 * @arg @ref LL_DMA_CHANNEL_1
1008 * @arg @ref LL_DMA_CHANNEL_2
1009 * @arg @ref LL_DMA_CHANNEL_3
1010 * @arg @ref LL_DMA_CHANNEL_4
1011 * @arg @ref LL_DMA_CHANNEL_5
1012 * @arg @ref LL_DMA_CHANNEL_6
1013 * @arg @ref LL_DMA_CHANNEL_7
1014 * @retval Returned value can be one of the following values:
1015 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1016 */
1017 __STATIC_INLINE uint32_t ll_dma_get_sstatar(dma_regs_t *DMAx, uint32_t channel)
1018 {
1019 return READ_BITS(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR);
1020 }
1021
1022 /**
1023 * @brief Set deatination status address after each block tranfer completed.
1024 *
1025 * Register|BitsName
1026 * --------|--------
1027 * DSTATAR | DSTATAR
1028 *
1029 * @param DMAx DMAx instance
1030 * @param channel This parameter can be one of the following values:
1031 * @arg @ref LL_DMA_CHANNEL_0
1032 * @arg @ref LL_DMA_CHANNEL_1
1033 * @arg @ref LL_DMA_CHANNEL_2
1034 * @arg @ref LL_DMA_CHANNEL_3
1035 * @arg @ref LL_DMA_CHANNEL_4
1036 * @arg @ref LL_DMA_CHANNEL_5
1037 * @arg @ref LL_DMA_CHANNEL_6
1038 * @arg @ref LL_DMA_CHANNEL_7
1039 * @param dstatar This parameter can be one of the following values:
1040 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1041 * @retval None
1042 */
1043 __STATIC_INLINE void ll_dma_set_dstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t dstatar)
1044 {
1045 MODIFY_REG(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR, dstatar);
1046 }
1047
1048 /**
1049 * @brief Get deatination status address after each block tranfer completed.
1050 *
1051 * Register|BitsName
1052 * --------|--------
1053 * DSTATAR | DSTATAR
1054 *
1055 * @param DMAx DMAx instance
1056 * @param channel This parameter can be one of the following values:
1057 * @arg @ref LL_DMA_CHANNEL_0
1058 * @arg @ref LL_DMA_CHANNEL_1
1059 * @arg @ref LL_DMA_CHANNEL_2
1060 * @arg @ref LL_DMA_CHANNEL_3
1061 * @arg @ref LL_DMA_CHANNEL_4
1062 * @arg @ref LL_DMA_CHANNEL_5
1063 * @arg @ref LL_DMA_CHANNEL_6
1064 * @arg @ref LL_DMA_CHANNEL_7
1065 * @retval Returned value can be one of the following values:
1066 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1067 */
1068 __STATIC_INLINE uint32_t ll_dma_get_dstatar(dma_regs_t *DMAx, uint32_t channel)
1069 {
1070 return READ_BITS(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR);
1071 }
1072
1073 /**
1074 * @brief Set LLP loc.
1075 *
1076 * Register|BitsName
1077 * --------|--------
1078 * CTL_LO | LOC
1079 *
1080 * @param DMAx DMAx instance
1081 * @param channel This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_CHANNEL_0
1083 * @arg @ref LL_DMA_CHANNEL_1
1084 * @arg @ref LL_DMA_CHANNEL_2
1085 * @arg @ref LL_DMA_CHANNEL_3
1086 * @arg @ref LL_DMA_CHANNEL_4
1087 * @arg @ref LL_DMA_CHANNEL_5
1088 * @arg @ref LL_DMA_CHANNEL_6
1089 * @arg @ref LL_DMA_CHANNEL_7
1090 * @param llp_loc This parameter can be one of the following values:
1091 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)
1092 * @retval None
1093 */
1094 __STATIC_INLINE void ll_dma_set_llp_loc(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_loc)
1095 {
1096 MODIFY_REG(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC, llp_loc);
1097 }
1098
1099 /**
1100 * @brief Get LLP loc.
1101 *
1102 * Register|BitsName
1103 * --------|--------
1104 * CTL_LO | LOC
1105 *
1106 * @param DMAx DMAx instance
1107 * @param channel This parameter can be one of the following values:
1108 * @arg @ref LL_DMA_CHANNEL_0
1109 * @arg @ref LL_DMA_CHANNEL_1
1110 * @arg @ref LL_DMA_CHANNEL_2
1111 * @arg @ref LL_DMA_CHANNEL_3
1112 * @arg @ref LL_DMA_CHANNEL_4
1113 * @arg @ref LL_DMA_CHANNEL_5
1114 * @arg @ref LL_DMA_CHANNEL_6
1115 * @arg @ref LL_DMA_CHANNEL_7
1116 * @retval Returned value can be one of the following values:
1117 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)
1118 */
1119 __STATIC_INLINE uint32_t ll_dma_get_llp_loc(dma_regs_t *DMAx, uint32_t channel)
1120 {
1121 return READ_BITS(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC);
1122 }
1123
1124 /**
1125 * @brief Set destination LLP enable.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * CTL_LO | LLP_DST_EN
1130 *
1131 * @param DMAx DMAx instance
1132 * @param channel This parameter can be one of the following values:
1133 * @arg @ref LL_DMA_CHANNEL_0
1134 * @arg @ref LL_DMA_CHANNEL_1
1135 * @arg @ref LL_DMA_CHANNEL_2
1136 * @arg @ref LL_DMA_CHANNEL_3
1137 * @arg @ref LL_DMA_CHANNEL_4
1138 * @arg @ref LL_DMA_CHANNEL_5
1139 * @arg @ref LL_DMA_CHANNEL_6
1140 * @arg @ref LL_DMA_CHANNEL_7
1141 * @param llp_dst_en This parameter can be one of the following values:
1142 * @arg @ref LL_DMA_LLP_DST_ENABLE
1143 * @arg @ref LL_DMA_LLP_DST_DISABLE
1144 * @retval None
1145 */
1146 __STATIC_INLINE void ll_dma_set_llp_dst_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_dst_en)
1147 {
1148 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN, llp_dst_en);
1149 }
1150
1151 /**
1152 * @brief Get destination LLP enable.
1153 *
1154 * Register|BitsName
1155 * --------|--------
1156 * CTL_LO | LLP_DST_EN
1157 *
1158 * @param DMAx DMAx instance
1159 * @param channel This parameter can be one of the following values:
1160 * @arg @ref LL_DMA_CHANNEL_0
1161 * @arg @ref LL_DMA_CHANNEL_1
1162 * @arg @ref LL_DMA_CHANNEL_2
1163 * @arg @ref LL_DMA_CHANNEL_3
1164 * @arg @ref LL_DMA_CHANNEL_4
1165 * @arg @ref LL_DMA_CHANNEL_5
1166 * @arg @ref LL_DMA_CHANNEL_6
1167 * @arg @ref LL_DMA_CHANNEL_7
1168 * @retval Returned value can be one of the following values:
1169 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1170 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1171 */
1172 __STATIC_INLINE uint32_t ll_dma_get_llp_dst_en(dma_regs_t *DMAx, uint32_t channel)
1173 {
1174 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN);
1175 }
1176
1177 /**
1178 * @brief Set source LLP enable.
1179 *
1180 * Register|BitsName
1181 * --------|--------
1182 * CTL_LO | LLP_SRC_EN
1183 *
1184 * @param DMAx DMAx instance
1185 * @param channel This parameter can be one of the following values:
1186 * @arg @ref LL_DMA_CHANNEL_0
1187 * @arg @ref LL_DMA_CHANNEL_1
1188 * @arg @ref LL_DMA_CHANNEL_2
1189 * @arg @ref LL_DMA_CHANNEL_3
1190 * @arg @ref LL_DMA_CHANNEL_4
1191 * @arg @ref LL_DMA_CHANNEL_5
1192 * @arg @ref LL_DMA_CHANNEL_6
1193 * @arg @ref LL_DMA_CHANNEL_7
1194 * @param llp_src_en This parameter can be one of the following values:
1195 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1196 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1197 * @retval None
1198 */
1199 __STATIC_INLINE void ll_dma_set_llp_src_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_src_en)
1200 {
1201 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN, llp_src_en);
1202 }
1203
1204 /**
1205 * @brief Get source LLP enable.
1206 *
1207 * Register|BitsName
1208 * --------|--------
1209 * CTL_LO | LLP_SRC_EN
1210 *
1211 * @param DMAx DMAx instance
1212 * @param channel This parameter can be one of the following values:
1213 * @arg @ref LL_DMA_CHANNEL_0
1214 * @arg @ref LL_DMA_CHANNEL_1
1215 * @arg @ref LL_DMA_CHANNEL_2
1216 * @arg @ref LL_DMA_CHANNEL_3
1217 * @arg @ref LL_DMA_CHANNEL_4
1218 * @arg @ref LL_DMA_CHANNEL_5
1219 * @arg @ref LL_DMA_CHANNEL_6
1220 * @arg @ref LL_DMA_CHANNEL_7
1221 * @retval Returned value can be one of the following values:
1222 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1223 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1224 */
1225 __STATIC_INLINE uint32_t ll_dma_get_llp_src_en(dma_regs_t *DMAx, uint32_t channel)
1226 {
1227 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN);
1228 }
1229
1230 /**
1231 * @brief Set destination scatter enable.
1232 *
1233 * Register|BitsName
1234 * --------|--------
1235 * CTL_LO | DST_SCATTER_EN
1236 *
1237 * @param DMAx DMAx instance
1238 * @param channel This parameter can be one of the following values:
1239 * @arg @ref LL_DMA_CHANNEL_0
1240 * @arg @ref LL_DMA_CHANNEL_1
1241 * @arg @ref LL_DMA_CHANNEL_2
1242 * @arg @ref LL_DMA_CHANNEL_3
1243 * @arg @ref LL_DMA_CHANNEL_4
1244 * @arg @ref LL_DMA_CHANNEL_5
1245 * @arg @ref LL_DMA_CHANNEL_6
1246 * @arg @ref LL_DMA_CHANNEL_7
1247 * @param dst_scatter_en This parameter can be one of the following values:
1248 * @arg @ref LL_DMA_DST_SCATTER_ENABLE
1249 * @arg @ref LL_DMA_DST_SCATTER_DISABLE
1250 * @retval None
1251 */
1252 __STATIC_INLINE void ll_dma_set_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_en)
1253 {
1254 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN, dst_scatter_en);
1255 }
1256
1257 /**
1258 * @brief Get destination scatter enable.
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * CTL_LO | DST_SCATTER_EN
1263 *
1264 * @param DMAx DMAx instance
1265 * @param channel This parameter can be one of the following values:
1266 * @arg @ref LL_DMA_CHANNEL_0
1267 * @arg @ref LL_DMA_CHANNEL_1
1268 * @arg @ref LL_DMA_CHANNEL_2
1269 * @arg @ref LL_DMA_CHANNEL_3
1270 * @arg @ref LL_DMA_CHANNEL_4
1271 * @arg @ref LL_DMA_CHANNEL_5
1272 * @arg @ref LL_DMA_CHANNEL_6
1273 * @arg @ref LL_DMA_CHANNEL_7
1274 * @retval Returned value can be one of the following values:
1275 * @arg @ref LL_DMA_DST_SCATTER_ENABLE
1276 * @arg @ref LL_DMA_DST_SCATTER_DISABLE
1277 */
1278 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel)
1279 {
1280 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN);
1281 }
1282
1283 /**
1284 * @brief Set source gather enable.
1285 *
1286 * Register|BitsName
1287 * --------|--------
1288 * CTL_LO | SRC_GATHER_EN
1289 *
1290 * @param DMAx DMAx instance
1291 * @param channel This parameter can be one of the following values:
1292 * @arg @ref LL_DMA_CHANNEL_0
1293 * @arg @ref LL_DMA_CHANNEL_1
1294 * @arg @ref LL_DMA_CHANNEL_2
1295 * @arg @ref LL_DMA_CHANNEL_3
1296 * @arg @ref LL_DMA_CHANNEL_4
1297 * @arg @ref LL_DMA_CHANNEL_5
1298 * @arg @ref LL_DMA_CHANNEL_6
1299 * @arg @ref LL_DMA_CHANNEL_7
1300 * @param src_gather_en This parameter can be one of the following values:
1301 * @arg @ref LL_DMA_SRC_GATHER_ENABLE
1302 * @arg @ref LL_DMA_SRC_GATHER_DISABLE
1303 * @retval None
1304 */
1305 __STATIC_INLINE void ll_dma_set_src_gather_en(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_en)
1306 {
1307 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN, src_gather_en);
1308 }
1309
1310 /**
1311 * @brief Get source gather enable.
1312 *
1313 * Register|BitsName
1314 * --------|--------
1315 * CTL_LO | SRC_GATHER_EN
1316 *
1317 * @param DMAx DMAx instance
1318 * @param channel This parameter can be one of the following values:
1319 * @arg @ref LL_DMA_CHANNEL_0
1320 * @arg @ref LL_DMA_CHANNEL_1
1321 * @arg @ref LL_DMA_CHANNEL_2
1322 * @arg @ref LL_DMA_CHANNEL_3
1323 * @arg @ref LL_DMA_CHANNEL_4
1324 * @arg @ref LL_DMA_CHANNEL_5
1325 * @arg @ref LL_DMA_CHANNEL_6
1326 * @arg @ref LL_DMA_CHANNEL_7
1327 * @retval Returned value can be one of the following values:
1328 * @arg @ref LL_DMA_SRC_GATHER_ENABLE
1329 * @arg @ref LL_DMA_SRC_GATHER_DISABLE
1330 */
1331 __STATIC_INLINE uint32_t ll_dma_get_src_gather_en(dma_regs_t *DMAx, uint32_t channel)
1332 {
1333 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN);
1334 }
1335
1336 /**
1337 * @brief Set Source increment mode.
1338 *
1339 * Register|BitsName
1340 * --------|--------
1341 * CTL_LO | SINC
1342 *
1343 * @param DMAx DMAx instance
1344 * @param channel This parameter can be one of the following values:
1345 * @arg @ref LL_DMA_CHANNEL_0
1346 * @arg @ref LL_DMA_CHANNEL_1
1347 * @arg @ref LL_DMA_CHANNEL_2
1348 * @arg @ref LL_DMA_CHANNEL_3
1349 * @arg @ref LL_DMA_CHANNEL_4
1350 * @arg @ref LL_DMA_CHANNEL_5
1351 * @arg @ref LL_DMA_CHANNEL_6
1352 * @arg @ref LL_DMA_CHANNEL_7
1353 * @param src_increment_mode This parameter can be one of the following values:
1354 * @arg @ref LL_DMA_SRC_INCREMENT
1355 * @arg @ref LL_DMA_SRC_DECREMENT
1356 * @arg @ref LL_DMA_SRC_NO_CHANGE
1357 * @retval None
1358 */
1359 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
1360 {
1361 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
1362 }
1363
1364 /**
1365 * @brief Get Source increment mode.
1366 *
1367 * Register|BitsName
1368 * --------|--------
1369 * CTL_LO | SINC
1370 *
1371 * @param DMAx DMAx instance
1372 * @param channel This parameter can be one of the following values:
1373 * @arg @ref LL_DMA_CHANNEL_0
1374 * @arg @ref LL_DMA_CHANNEL_1
1375 * @arg @ref LL_DMA_CHANNEL_2
1376 * @arg @ref LL_DMA_CHANNEL_3
1377 * @arg @ref LL_DMA_CHANNEL_4
1378 * @arg @ref LL_DMA_CHANNEL_5
1379 * @arg @ref LL_DMA_CHANNEL_6
1380 * @arg @ref LL_DMA_CHANNEL_7
1381 * @retval Returned value can be one of the following values:
1382 * @arg @ref LL_DMA_SRC_INCREMENT
1383 * @arg @ref LL_DMA_SRC_DECREMENT
1384 * @arg @ref LL_DMA_SRC_NO_CHANGE
1385 */
1386 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
1387 {
1388 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
1389 }
1390
1391 /**
1392 * @brief Set Destination increment mode.
1393 *
1394 * Register|BitsName
1395 * --------|--------
1396 * CTL_LO | DINC
1397 *
1398 * @param DMAx DMAx instance
1399 * @param channel This parameter can be one of the following values:
1400 * @arg @ref LL_DMA_CHANNEL_0
1401 * @arg @ref LL_DMA_CHANNEL_1
1402 * @arg @ref LL_DMA_CHANNEL_2
1403 * @arg @ref LL_DMA_CHANNEL_3
1404 * @arg @ref LL_DMA_CHANNEL_4
1405 * @arg @ref LL_DMA_CHANNEL_5
1406 * @arg @ref LL_DMA_CHANNEL_6
1407 * @arg @ref LL_DMA_CHANNEL_7
1408 * @param dst_increment_mode This parameter can be one of the following values:
1409 * @arg @ref LL_DMA_DST_INCREMENT
1410 * @arg @ref LL_DMA_DST_DECREMENT
1411 * @arg @ref LL_DMA_DST_NO_CHANGE
1412 * @retval None
1413 */
1414 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
1415 {
1416 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
1417 }
1418
1419 /**
1420 * @brief Get Destination increment mode.
1421 *
1422 * Register|BitsName
1423 * --------|--------
1424 * CTL_LO | DINC
1425 *
1426 * @param DMAx DMAx instance
1427 * @param channel This parameter can be one of the following values:
1428 * @arg @ref LL_DMA_CHANNEL_0
1429 * @arg @ref LL_DMA_CHANNEL_1
1430 * @arg @ref LL_DMA_CHANNEL_2
1431 * @arg @ref LL_DMA_CHANNEL_3
1432 * @arg @ref LL_DMA_CHANNEL_4
1433 * @arg @ref LL_DMA_CHANNEL_5
1434 * @arg @ref LL_DMA_CHANNEL_6
1435 * @arg @ref LL_DMA_CHANNEL_7
1436 * @retval Returned value can be one of the following values:
1437 * @arg @ref LL_DMA_DST_INCREMENT
1438 * @arg @ref LL_DMA_DST_DECREMENT
1439 * @arg @ref LL_DMA_DST_NO_CHANGE
1440 */
1441 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
1442 {
1443 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
1444 }
1445
1446 /**
1447 * @brief Set Source transfer width.
1448 *
1449 * Register|BitsName
1450 * --------|--------
1451 * CTL_LO | SRC_TR_WIDTH
1452 *
1453 * @param DMAx DMAx instance
1454 * @param channel This parameter can be one of the following values:
1455 * @arg @ref LL_DMA_CHANNEL_0
1456 * @arg @ref LL_DMA_CHANNEL_1
1457 * @arg @ref LL_DMA_CHANNEL_2
1458 * @arg @ref LL_DMA_CHANNEL_3
1459 * @arg @ref LL_DMA_CHANNEL_4
1460 * @arg @ref LL_DMA_CHANNEL_5
1461 * @arg @ref LL_DMA_CHANNEL_6
1462 * @arg @ref LL_DMA_CHANNEL_7
1463 * @param src_width This parameter can be one of the following values:
1464 * @arg @ref LL_DMA_SDATAALIGN_BYTE
1465 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
1466 * @arg @ref LL_DMA_SDATAALIGN_WORD
1467 * @retval None
1468 */
1469 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
1470 {
1471 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
1472 }
1473
1474 /**
1475 * @brief Get Source transfer width.
1476 *
1477 * Register|BitsName
1478 * --------|--------
1479 * CTL_LO | SRC_TR_WIDTH
1480 *
1481 * @param DMAx DMAx instance
1482 * @param channel This parameter can be one of the following values:
1483 * @arg @ref LL_DMA_CHANNEL_0
1484 * @arg @ref LL_DMA_CHANNEL_1
1485 * @arg @ref LL_DMA_CHANNEL_2
1486 * @arg @ref LL_DMA_CHANNEL_3
1487 * @arg @ref LL_DMA_CHANNEL_4
1488 * @arg @ref LL_DMA_CHANNEL_5
1489 * @arg @ref LL_DMA_CHANNEL_6
1490 * @arg @ref LL_DMA_CHANNEL_7
1491 * @retval Returned value can be one of the following values:
1492 * @arg @ref LL_DMA_SDATAALIGN_BYTE
1493 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
1494 * @arg @ref LL_DMA_SDATAALIGN_WORD
1495 */
1496 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
1497 {
1498 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
1499 }
1500
1501 /**
1502 * @brief Set Destination transfer width.
1503 *
1504 * Register|BitsName
1505 * --------|--------
1506 * CTL_LO | DST_TR_WIDTH
1507 *
1508 * @param DMAx DMAx instance
1509 * @param channel This parameter can be one of the following values:
1510 * @arg @ref LL_DMA_CHANNEL_0
1511 * @arg @ref LL_DMA_CHANNEL_1
1512 * @arg @ref LL_DMA_CHANNEL_2
1513 * @arg @ref LL_DMA_CHANNEL_3
1514 * @arg @ref LL_DMA_CHANNEL_4
1515 * @arg @ref LL_DMA_CHANNEL_5
1516 * @arg @ref LL_DMA_CHANNEL_6
1517 * @arg @ref LL_DMA_CHANNEL_7
1518 * @param dst_width This parameter can be one of the following values:
1519 * @arg @ref LL_DMA_DDATAALIGN_BYTE
1520 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
1521 * @arg @ref LL_DMA_DDATAALIGN_WORD
1522 * @retval None
1523 */
1524 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
1525 {
1526 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1527 }
1528
1529 /**
1530 * @brief Get Destination transfer width.
1531 *
1532 * Register|BitsName
1533 * --------|--------
1534 * CTL_LO | DST_TR_WIDTH
1535 *
1536 * @param DMAx DMAx instance
1537 * @param channel This parameter can be one of the following values:
1538 * @arg @ref LL_DMA_CHANNEL_0
1539 * @arg @ref LL_DMA_CHANNEL_1
1540 * @arg @ref LL_DMA_CHANNEL_2
1541 * @arg @ref LL_DMA_CHANNEL_3
1542 * @arg @ref LL_DMA_CHANNEL_4
1543 * @arg @ref LL_DMA_CHANNEL_5
1544 * @arg @ref LL_DMA_CHANNEL_6
1545 * @arg @ref LL_DMA_CHANNEL_7
1546 * @retval Returned value can be one of the following values:
1547 * @arg @ref LL_DMA_DDATAALIGN_BYTE
1548 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
1549 * @arg @ref LL_DMA_DDATAALIGN_WORD
1550 */
1551 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
1552 {
1553 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1554 }
1555
1556 /**
1557 * @brief Set Source Burst Transaction Length.
1558 *
1559 * Register|BitsName
1560 * --------|--------
1561 * CTL_LO | SRC_MSIZE
1562 *
1563 * @param DMAx DMAx instance
1564 * @param channel This parameter can be one of the following values:
1565 * @arg @ref LL_DMA_CHANNEL_0
1566 * @arg @ref LL_DMA_CHANNEL_1
1567 * @arg @ref LL_DMA_CHANNEL_2
1568 * @arg @ref LL_DMA_CHANNEL_3
1569 * @arg @ref LL_DMA_CHANNEL_4
1570 * @arg @ref LL_DMA_CHANNEL_5
1571 * @arg @ref LL_DMA_CHANNEL_6
1572 * @arg @ref LL_DMA_CHANNEL_7
1573 * @param burst_length This parameter can be one of the following values:
1574 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1575 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1576 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1577 * @retval None
1578 */
1579 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1580 {
1581 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1582 }
1583
1584 /**
1585 * @brief Get Burst Transaction Length.
1586 *
1587 * Register|BitsName
1588 * --------|--------
1589 * CTL_LO | SRC_MSIZE
1590 *
1591 * @param DMAx DMAx instance
1592 * @param channel This parameter can be one of the following values:
1593 * @arg @ref LL_DMA_CHANNEL_0
1594 * @arg @ref LL_DMA_CHANNEL_1
1595 * @arg @ref LL_DMA_CHANNEL_2
1596 * @arg @ref LL_DMA_CHANNEL_3
1597 * @arg @ref LL_DMA_CHANNEL_4
1598 * @arg @ref LL_DMA_CHANNEL_5
1599 * @arg @ref LL_DMA_CHANNEL_6
1600 * @arg @ref LL_DMA_CHANNEL_7
1601 * @retval Returned value can be one of the following values:
1602 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1603 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1604 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1605 */
1606 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
1607 {
1608 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1609 }
1610
1611 /**
1612 * @brief Set Destination Burst Transaction Length.
1613 *
1614 * Register|BitsName
1615 * --------|--------
1616 * CTL_LO | DST_MSIZE
1617 *
1618 * @param DMAx DMAx instance
1619 * @param channel This parameter can be one of the following values:
1620 * @arg @ref LL_DMA_CHANNEL_0
1621 * @arg @ref LL_DMA_CHANNEL_1
1622 * @arg @ref LL_DMA_CHANNEL_2
1623 * @arg @ref LL_DMA_CHANNEL_3
1624 * @arg @ref LL_DMA_CHANNEL_4
1625 * @arg @ref LL_DMA_CHANNEL_5
1626 * @arg @ref LL_DMA_CHANNEL_6
1627 * @arg @ref LL_DMA_CHANNEL_7
1628 * @param burst_length This parameter can be one of the following values:
1629 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1630 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1631 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1632 * @retval None
1633 */
1634 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1635 {
1636 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1637 }
1638
1639 /**
1640 * @brief Get Destination Burst Transaction Length.
1641 *
1642 * Register|BitsName
1643 * --------|--------
1644 * CTL_LO | DST_MSIZE
1645 *
1646 * @param DMAx DMAx instance
1647 * @param channel This parameter can be one of the following values:
1648 * @arg @ref LL_DMA_CHANNEL_0
1649 * @arg @ref LL_DMA_CHANNEL_1
1650 * @arg @ref LL_DMA_CHANNEL_2
1651 * @arg @ref LL_DMA_CHANNEL_3
1652 * @arg @ref LL_DMA_CHANNEL_4
1653 * @arg @ref LL_DMA_CHANNEL_5
1654 * @arg @ref LL_DMA_CHANNEL_6
1655 * @arg @ref LL_DMA_CHANNEL_7
1656 * @retval Returned value can be one of the following values:
1657 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1658 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1659 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1660 */
1661 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
1662 {
1663 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1664 }
1665
1666 /**
1667 * @brief Set Channel priority level.
1668 *
1669 * Register|BitsName
1670 * --------|--------
1671 * CFG_LO | CH_PRIOR
1672 *
1673 * @param DMAx DMAx instance
1674 * @param channel This parameter can be one of the following values:
1675 * @arg @ref LL_DMA_CHANNEL_0
1676 * @arg @ref LL_DMA_CHANNEL_1
1677 * @arg @ref LL_DMA_CHANNEL_2
1678 * @arg @ref LL_DMA_CHANNEL_3
1679 * @arg @ref LL_DMA_CHANNEL_4
1680 * @arg @ref LL_DMA_CHANNEL_5
1681 * @arg @ref LL_DMA_CHANNEL_6
1682 * @arg @ref LL_DMA_CHANNEL_7
1683 * @param priority This parameter can be one of the following values:
1684 * @arg @ref LL_DMA_PRIORITY_0
1685 * @arg @ref LL_DMA_PRIORITY_1
1686 * @arg @ref LL_DMA_PRIORITY_2
1687 * @arg @ref LL_DMA_PRIORITY_3
1688 * @arg @ref LL_DMA_PRIORITY_4
1689 * @arg @ref LL_DMA_PRIORITY_5
1690 * @arg @ref LL_DMA_PRIORITY_6
1691 * @arg @ref LL_DMA_PRIORITY_7
1692 * @retval None
1693 */
1694 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
1695 {
1696 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1697 }
1698
1699 /**
1700 * @brief Get Channel priority level.
1701 *
1702 * Register|BitsName
1703 * --------|--------
1704 * CFG_LO | CH_PRIOR
1705 *
1706 * @param DMAx DMAx instance
1707 * @param channel This parameter can be one of the following values:
1708 * @arg @ref LL_DMA_CHANNEL_0
1709 * @arg @ref LL_DMA_CHANNEL_1
1710 * @arg @ref LL_DMA_CHANNEL_2
1711 * @arg @ref LL_DMA_CHANNEL_3
1712 * @arg @ref LL_DMA_CHANNEL_4
1713 * @arg @ref LL_DMA_CHANNEL_5
1714 * @arg @ref LL_DMA_CHANNEL_6
1715 * @arg @ref LL_DMA_CHANNEL_7
1716 * @retval Returned value can be one of the following values:
1717 * @arg @ref LL_DMA_PRIORITY_0
1718 * @arg @ref LL_DMA_PRIORITY_1
1719 * @arg @ref LL_DMA_PRIORITY_2
1720 * @arg @ref LL_DMA_PRIORITY_3
1721 * @arg @ref LL_DMA_PRIORITY_4
1722 * @arg @ref LL_DMA_PRIORITY_5
1723 * @arg @ref LL_DMA_PRIORITY_6
1724 * @arg @ref LL_DMA_PRIORITY_7
1725 */
1726 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
1727 {
1728 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1729 }
1730
1731 /**
1732 * @brief Set the block size of a transfer.
1733 * @note This action has no effect if channel is enabled.
1734 *
1735 * Register|BitsName
1736 * --------|--------
1737 * CTL_HI | BLOCK_TS
1738 *
1739 * @param DMAx DMAx instance
1740 * @param channel This parameter can be one of the following values:
1741 * @arg @ref LL_DMA_CHANNEL_0
1742 * @arg @ref LL_DMA_CHANNEL_1
1743 * @arg @ref LL_DMA_CHANNEL_2
1744 * @arg @ref LL_DMA_CHANNEL_3
1745 * @arg @ref LL_DMA_CHANNEL_4
1746 * @arg @ref LL_DMA_CHANNEL_5
1747 * @arg @ref LL_DMA_CHANNEL_6
1748 * @arg @ref LL_DMA_CHANNEL_7
1749 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1750 * @retval None
1751 */
1752 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1753 {
1754 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1755 }
1756
1757 /**
1758 * @brief Get the block size of a transfer.
1759 * @note Once the channel is enabled, the return value indicate the
1760 * remaining bytes to be transmitted.
1761 *
1762 * Register|BitsName
1763 * --------|--------
1764 * CTL_HI | BLOCK_TS
1765 *
1766 * @param DMAx DMAx instance
1767 * @param channel This parameter can be one of the following values:
1768 * @arg @ref LL_DMA_CHANNEL_0
1769 * @arg @ref LL_DMA_CHANNEL_1
1770 * @arg @ref LL_DMA_CHANNEL_2
1771 * @arg @ref LL_DMA_CHANNEL_3
1772 * @arg @ref LL_DMA_CHANNEL_4
1773 * @arg @ref LL_DMA_CHANNEL_5
1774 * @arg @ref LL_DMA_CHANNEL_6
1775 * @arg @ref LL_DMA_CHANNEL_7
1776 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1777 */
1778 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1779 {
1780 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1781 }
1782
1783 /**
1784 * @brief Configure the Source and Destination addresses.
1785 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1786 *
1787 * Register|BitsName
1788 * --------|--------
1789 * SAR | SAR
1790 * DAR | DAR
1791 * CTL_LO | TT_FC
1792 *
1793 * @param DMAx DMAx instance
1794 * @param channel This parameter can be one of the following values:
1795 * @arg @ref LL_DMA_CHANNEL_0
1796 * @arg @ref LL_DMA_CHANNEL_1
1797 * @arg @ref LL_DMA_CHANNEL_2
1798 * @arg @ref LL_DMA_CHANNEL_3
1799 * @arg @ref LL_DMA_CHANNEL_4
1800 * @arg @ref LL_DMA_CHANNEL_5
1801 * @arg @ref LL_DMA_CHANNEL_6
1802 * @arg @ref LL_DMA_CHANNEL_7
1803 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1804 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1805 * @param direction This parameter can be one of the following values:
1806 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1807 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1808 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1809 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1810 * @retval None
1811 */
1812 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx,
1813 uint32_t channel,
1814 uint32_t src_address,
1815 uint32_t dst_address,
1816 uint32_t direction)
1817 {
1818 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1819 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1820 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1821 }
1822
1823 /**
1824 * @brief Set the Source address.
1825 *
1826 * Register|BitsName
1827 * --------|--------
1828 * SAR | SAR
1829 *
1830 * @param DMAx DMAx instance
1831 * @param channel This parameter can be one of the following values:
1832 * @arg @ref LL_DMA_CHANNEL_0
1833 * @arg @ref LL_DMA_CHANNEL_1
1834 * @arg @ref LL_DMA_CHANNEL_2
1835 * @arg @ref LL_DMA_CHANNEL_3
1836 * @arg @ref LL_DMA_CHANNEL_4
1837 * @arg @ref LL_DMA_CHANNEL_5
1838 * @arg @ref LL_DMA_CHANNEL_6
1839 * @arg @ref LL_DMA_CHANNEL_7
1840 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1841 * @retval None
1842 */
1843 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1844 {
1845 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1846 }
1847
1848 /**
1849 * @brief Set the Destination address.
1850 *
1851 * Register|BitsName
1852 * --------|--------
1853 * DAR | DAR
1854 *
1855 * @param DMAx DMAx instance
1856 * @param channel This parameter can be one of the following values:
1857 * @arg @ref LL_DMA_CHANNEL_0
1858 * @arg @ref LL_DMA_CHANNEL_1
1859 * @arg @ref LL_DMA_CHANNEL_2
1860 * @arg @ref LL_DMA_CHANNEL_3
1861 * @arg @ref LL_DMA_CHANNEL_4
1862 * @arg @ref LL_DMA_CHANNEL_5
1863 * @arg @ref LL_DMA_CHANNEL_6
1864 * @arg @ref LL_DMA_CHANNEL_7
1865 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1866 * @retval None
1867 */
1868 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1869 {
1870 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1871 }
1872
1873 /**
1874 * @brief Get Source address.
1875 *
1876 * Register|BitsName
1877 * --------|--------
1878 * SAR | SAR
1879 *
1880 * @param DMAx DMAx instance
1881 * @param channel This parameter can be one of the following values:
1882 * @arg @ref LL_DMA_CHANNEL_0
1883 * @arg @ref LL_DMA_CHANNEL_1
1884 * @arg @ref LL_DMA_CHANNEL_2
1885 * @arg @ref LL_DMA_CHANNEL_3
1886 * @arg @ref LL_DMA_CHANNEL_4
1887 * @arg @ref LL_DMA_CHANNEL_5
1888 * @arg @ref LL_DMA_CHANNEL_6
1889 * @arg @ref LL_DMA_CHANNEL_7
1890 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1891 */
1892 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1893 {
1894 return READ_REG(DMAx->CHANNEL[channel].SAR);
1895 }
1896
1897 /**
1898 * @brief Get Destination address.
1899 *
1900 * Register|BitsName
1901 * --------|--------
1902 * DAR | DAR
1903 *
1904 * @param DMAx DMAx instance
1905 * @param channel This parameter can be one of the following values:
1906 * @arg @ref LL_DMA_CHANNEL_0
1907 * @arg @ref LL_DMA_CHANNEL_1
1908 * @arg @ref LL_DMA_CHANNEL_2
1909 * @arg @ref LL_DMA_CHANNEL_3
1910 * @arg @ref LL_DMA_CHANNEL_4
1911 * @arg @ref LL_DMA_CHANNEL_5
1912 * @arg @ref LL_DMA_CHANNEL_6
1913 * @arg @ref LL_DMA_CHANNEL_7
1914 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1915 */
1916 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1917 {
1918 return READ_REG(DMAx->CHANNEL[channel].DAR);
1919 }
1920
1921 /**
1922 * @brief Set the Memory to Memory Source address.
1923 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1924 *
1925 * Register|BitsName
1926 * --------|--------
1927 * SAR | SAR
1928 * CTL_LO | TT_FC
1929 * @param DMAx DMAx instance
1930 * @param channel This parameter can be one of the following values:
1931 * @arg @ref LL_DMA_CHANNEL_0
1932 * @arg @ref LL_DMA_CHANNEL_1
1933 * @arg @ref LL_DMA_CHANNEL_2
1934 * @arg @ref LL_DMA_CHANNEL_3
1935 * @arg @ref LL_DMA_CHANNEL_4
1936 * @arg @ref LL_DMA_CHANNEL_5
1937 * @arg @ref LL_DMA_CHANNEL_6
1938 * @arg @ref LL_DMA_CHANNEL_7
1939 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1940 * @retval None
1941 */
1942 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1943 {
1944 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1945 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1946 }
1947
1948 /**
1949 * @brief Set the Memory to Memory Destination address.
1950 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1951 *
1952 * Register|BitsName
1953 * --------|--------
1954 * DAR | DAR
1955 * CTL_LO | TT_FC
1956 *
1957 * @param DMAx DMAx instance
1958 * @param channel This parameter can be one of the following values:
1959 * @arg @ref LL_DMA_CHANNEL_0
1960 * @arg @ref LL_DMA_CHANNEL_1
1961 * @arg @ref LL_DMA_CHANNEL_2
1962 * @arg @ref LL_DMA_CHANNEL_3
1963 * @arg @ref LL_DMA_CHANNEL_4
1964 * @arg @ref LL_DMA_CHANNEL_5
1965 * @arg @ref LL_DMA_CHANNEL_6
1966 * @arg @ref LL_DMA_CHANNEL_7
1967 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1968 * @retval None
1969 */
1970 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1971 {
1972 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1973 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1974 }
1975
1976 /**
1977 * @brief Get the Memory to Memory Source address.
1978 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1979 *
1980 * Register|BitsName
1981 * --------|--------
1982 * SAR | SAR
1983 *
1984 * @param DMAx DMAx instance
1985 * @param channel This parameter can be one of the following values:
1986 * @arg @ref LL_DMA_CHANNEL_0
1987 * @arg @ref LL_DMA_CHANNEL_1
1988 * @arg @ref LL_DMA_CHANNEL_2
1989 * @arg @ref LL_DMA_CHANNEL_3
1990 * @arg @ref LL_DMA_CHANNEL_4
1991 * @arg @ref LL_DMA_CHANNEL_5
1992 * @arg @ref LL_DMA_CHANNEL_6
1993 * @arg @ref LL_DMA_CHANNEL_7
1994 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1995 */
1996 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1997 {
1998 return READ_REG(DMAx->CHANNEL[channel].SAR);
1999 }
2000
2001 /**
2002 * @brief Get the Memory to Memory Destination address.
2003 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
2004 *
2005 * Register|BitsName
2006 * --------|--------
2007 * DAR | DAR
2008 *
2009 * @param DMAx DMAx instance
2010 * @param channel This parameter can be one of the following values:
2011 * @arg @ref LL_DMA_CHANNEL_0
2012 * @arg @ref LL_DMA_CHANNEL_1
2013 * @arg @ref LL_DMA_CHANNEL_2
2014 * @arg @ref LL_DMA_CHANNEL_3
2015 * @arg @ref LL_DMA_CHANNEL_4
2016 * @arg @ref LL_DMA_CHANNEL_5
2017 * @arg @ref LL_DMA_CHANNEL_6
2018 * @arg @ref LL_DMA_CHANNEL_7
2019 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
2020 */
2021 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
2022 {
2023 return READ_REG(DMAx->CHANNEL[channel].DAR);
2024 }
2025
2026 /**
2027 * @brief Enable Source Status Update Enable for DMA instance on Channel x.
2028 *
2029 * Register|BitsName
2030 * --------|--------
2031 * CFG_HI | SS_UPD_EN
2032 *
2033 * @param DMAx DMAx instance
2034 * @param channel This parameter can be one of the following values:
2035 * @arg @ref LL_DMA_CHANNEL_0
2036 * @arg @ref LL_DMA_CHANNEL_1
2037 * @arg @ref LL_DMA_CHANNEL_2
2038 * @arg @ref LL_DMA_CHANNEL_3
2039 * @arg @ref LL_DMA_CHANNEL_4
2040 * @arg @ref LL_DMA_CHANNEL_5
2041 * @arg @ref LL_DMA_CHANNEL_6
2042 * @arg @ref LL_DMA_CHANNEL_7
2043 * @retval None
2044 */
2045 __STATIC_INLINE void ll_dma_enable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
2046 {
2047 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN,LL_DMA_SRC_STAT_UPDATE_ENABLE);
2048 }
2049
2050 /**
2051 * @brief Disable Source Status Update Enable for DMA instance on Channel x.
2052 *
2053 * Register|BitsName
2054 * --------|--------
2055 * CFG_HI | SS_UPD_EN
2056 *
2057 * @param DMAx DMAx instance
2058 * @param channel This parameter can be one of the following values:
2059 * @arg @ref LL_DMA_CHANNEL_0
2060 * @arg @ref LL_DMA_CHANNEL_1
2061 * @arg @ref LL_DMA_CHANNEL_2
2062 * @arg @ref LL_DMA_CHANNEL_3
2063 * @arg @ref LL_DMA_CHANNEL_4
2064 * @arg @ref LL_DMA_CHANNEL_5
2065 * @arg @ref LL_DMA_CHANNEL_6
2066 * @arg @ref LL_DMA_CHANNEL_7
2067 * @retval None
2068 */
2069 __STATIC_INLINE void ll_dma_disable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
2070 {
2071 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN,LL_DMA_SRC_STAT_UPDATE_DISABLE);
2072 }
2073
2074 /**
2075 * @brief Check if Source Status Update Enable
2076 *
2077 * Register|BitsName
2078 * --------|--------
2079 * CFG_HI | SS_UPD_EN
2080 *
2081 * @param DMAx DMA instance.
2082 * @param channel This parameter can be one of the following values:
2083 * @arg @ref LL_DMA_CHANNEL_0
2084 * @arg @ref LL_DMA_CHANNEL_1
2085 * @arg @ref LL_DMA_CHANNEL_2
2086 * @arg @ref LL_DMA_CHANNEL_3
2087 * @arg @ref LL_DMA_CHANNEL_4
2088 * @arg @ref LL_DMA_CHANNEL_5
2089 * @arg @ref LL_DMA_CHANNEL_6
2090 * @arg @ref LL_DMA_CHANNEL_7
2091 * @retval State of bit (1 or 0).
2092 */
2093 __STATIC_INLINE uint32_t ll_dma_src_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
2094 {
2095 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN) == LL_DMA_SRC_STAT_UPDATE_ENABLE);
2096 }
2097
2098 /**
2099 * @brief Enable Destination Status Update Enable for DMA instance on Channel x.
2100 *
2101 * Register|BitsName
2102 * --------|--------
2103 * CFG_HI | DS_UPD_EN
2104 *
2105 * @param DMAx DMAx instance
2106 * @param channel This parameter can be one of the following values:
2107 * @arg @ref LL_DMA_CHANNEL_0
2108 * @arg @ref LL_DMA_CHANNEL_1
2109 * @arg @ref LL_DMA_CHANNEL_2
2110 * @arg @ref LL_DMA_CHANNEL_3
2111 * @arg @ref LL_DMA_CHANNEL_4
2112 * @arg @ref LL_DMA_CHANNEL_5
2113 * @arg @ref LL_DMA_CHANNEL_6
2114 * @arg @ref LL_DMA_CHANNEL_7
2115 * @retval None
2116 */
2117 __STATIC_INLINE void ll_dma_enable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
2118 {
2119 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN,LL_DMA_DST_STAT_UPDATE_ENABLE);
2120 }
2121
2122 /**
2123 * @brief Disable Destination Status Update Enable for DMA instance on Channel x.
2124 *
2125 * Register|BitsName
2126 * --------|--------
2127 * CFG_HI | DS_UPD_EN
2128 *
2129 * @param DMAx DMAx instance
2130 * @param channel This parameter can be one of the following values:
2131 * @arg @ref LL_DMA_CHANNEL_0
2132 * @arg @ref LL_DMA_CHANNEL_1
2133 * @arg @ref LL_DMA_CHANNEL_2
2134 * @arg @ref LL_DMA_CHANNEL_3
2135 * @arg @ref LL_DMA_CHANNEL_4
2136 * @arg @ref LL_DMA_CHANNEL_5
2137 * @arg @ref LL_DMA_CHANNEL_6
2138 * @arg @ref LL_DMA_CHANNEL_7
2139 * @retval None
2140 */
2141 __STATIC_INLINE void ll_dma_disable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
2142 {
2143 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN,LL_DMA_DST_STAT_UPDATE_DISABLE);
2144 }
2145
2146 /**
2147 * @brief Check if Destination Status Update Enable
2148 *
2149 * Register|BitsName
2150 * --------|--------
2151 * CFG_HI | SS_UPD_EN
2152 *
2153 * @param DMAx DMA instance.
2154 * @param channel This parameter can be one of the following values:
2155 * @arg @ref LL_DMA_CHANNEL_0
2156 * @arg @ref LL_DMA_CHANNEL_1
2157 * @arg @ref LL_DMA_CHANNEL_2
2158 * @arg @ref LL_DMA_CHANNEL_3
2159 * @arg @ref LL_DMA_CHANNEL_4
2160 * @arg @ref LL_DMA_CHANNEL_5
2161 * @arg @ref LL_DMA_CHANNEL_6
2162 * @arg @ref LL_DMA_CHANNEL_7
2163 * @retval State of bit (1 or 0).
2164 */
2165 __STATIC_INLINE uint32_t ll_dma_dst_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
2166 {
2167 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN) == LL_DMA_DST_STAT_UPDATE_ENABLE);
2168 }
2169
2170 /**
2171 * @brief Set source peripheral for DMA instance on Channel x.
2172 *
2173 * Register|BitsName
2174 * --------|--------
2175 * CFG_HI | SRC_PER
2176 *
2177 * @param DMAx DMAx instance
2178 * @param channel This parameter can be one of the following values:
2179 * @arg @ref LL_DMA_CHANNEL_0
2180 * @arg @ref LL_DMA_CHANNEL_1
2181 * @arg @ref LL_DMA_CHANNEL_2
2182 * @arg @ref LL_DMA_CHANNEL_3
2183 * @arg @ref LL_DMA_CHANNEL_4
2184 * @arg @ref LL_DMA_CHANNEL_5
2185 * @arg @ref LL_DMA_CHANNEL_6
2186 * @arg @ref LL_DMA_CHANNEL_7
2187 * @param peripheral This parameter can be one of the following values:
2188 * @arg @ref LL_DMA0_PERIPH_QSPI0_TX
2189 * @arg @ref LL_DMA0_PERIPH_QSPI0_RX
2190 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
2191 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
2192 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2193 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2194 * @arg @ref LL_DMA0_PERIPH_UART0_TX
2195 * @arg @ref LL_DMA0_PERIPH_UART0_RX
2196 * @arg @ref LL_DMA0_PERIPH_UART1_TX
2197 * @arg @ref LL_DMA0_PERIPH_UART1_RX
2198 * @arg @ref LL_DMA0_PERIPH_SNSADC
2199 * @arg @ref LL_DMA0_PERIPH_OSPI_TX
2200 * @arg @ref LL_DMA0_PERIPH_OSPI_RX
2201 * @arg @ref LL_DMA0_PERIPH_UART2_TX
2202 * @arg @ref LL_DMA0_PERIPH_UART2_RX
2203 * @arg @ref LL_DMA0_PERIPH_I2C2_TX
2204 * @arg @ref LL_DMA0_PERIPH_I2C2_RX
2205 * @arg @ref LL_DMA0_PERIPH_UART3_TX
2206 * @arg @ref LL_DMA0_PERIPH_UART3_RX
2207 * @arg @ref LL_DMA0_PERIPH_I2C5_TX
2208 * @arg @ref LL_DMA0_PERIPH_I2C5_RX
2209 * @arg @ref LL_DMA0_PERIPH_I2C4_TX
2210 * @arg @ref LL_DMA0_PERIPH_I2C4_RX
2211 * @arg @ref LL_DMA0_PERIPH_UART4_TX
2212 * @arg @ref LL_DMA0_PERIPH_UART4_RX
2213 * @arg @ref LL_DMA0_PERIPH_QSPI1_TX
2214 * @arg @ref LL_DMA0_PERIPH_QSPI1_RX
2215 * @arg @ref LL_DMA0_PERIPH_I2C3_TX
2216 * @arg @ref LL_DMA0_PERIPH_I2C3_RX
2217 * @arg @ref LL_DMA1_PERIPH_OSPI_TX
2218 * @arg @ref LL_DMA1_PERIPH_OSPI_RX
2219 * @arg @ref LL_DMA1_PERIPH_QSPI2_TX
2220 * @arg @ref LL_DMA1_PERIPH_QSPI2_RX
2221 * @arg @ref LL_DMA1_PERIPH_I2S_M_TX
2222 * @arg @ref LL_DMA1_PERIPH_I2S_M_RX
2223 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2224 * @arg @ref LL_DMA1_PERIPH_I2S_S_RX
2225 * @arg @ref LL_DMA1_PERIPH_PDM_TX
2226 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX
2227 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX
2228 * @arg @ref LL_DMA1_PERIPH_I2C0_TX
2229 * @arg @ref LL_DMA1_PERIPH_I2C0_RX
2230 * @arg @ref LL_DMA1_PERIPH_I2C1_TX
2231 * @arg @ref LL_DMA1_PERIPH_I2C1_RX
2232 * @arg @ref LL_DMA1_PERIPH_SPIM_TX
2233 * @arg @ref LL_DMA1_PERIPH_SPIM_RX
2234 * @arg @ref LL_DMA1_PERIPH_DSPIM_TX
2235 * @arg @ref LL_DMA1_PERIPH_DSPIM_RX
2236 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX_2
2237 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX_2
2238 * @arg @ref LL_DMA1_PERIPH_UART3_TX
2239 * @arg @ref LL_DMA1_PERIPH_UART3_RX
2240 * @arg @ref LL_DMA1_PERIPH_UART4_TX
2241 * @arg @ref LL_DMA1_PERIPH_UART4_RX
2242 * @arg @ref LL_DMA1_PERIPH_UART5_TX
2243 * @arg @ref LL_DMA1_PERIPH_UART5_RX
2244 * @arg @ref LL_DMA1_PERIPH_UART0_TX
2245 * @arg @ref LL_DMA1_PERIPH_UART0_RX
2246 * @retval None
2247 */
2248 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
2249 {
2250 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
2251 }
2252
2253 /**
2254 * @brief Get source peripheral for DMA instance on Channel x.
2255 *
2256 * Register|BitsName
2257 * --------|--------
2258 * CFG_HI | SRC_PER
2259 *
2260 * @param DMAx DMAx instance
2261 * @param channel This parameter can be one of the following values:
2262 * @arg @ref LL_DMA_CHANNEL_0
2263 * @arg @ref LL_DMA_CHANNEL_1
2264 * @arg @ref LL_DMA_CHANNEL_2
2265 * @arg @ref LL_DMA_CHANNEL_3
2266 * @arg @ref LL_DMA_CHANNEL_4
2267 * @arg @ref LL_DMA_CHANNEL_5
2268 * @arg @ref LL_DMA_CHANNEL_6
2269 * @arg @ref LL_DMA_CHANNEL_7
2270 */
2271 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
2272 {
2273 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
2274 }
2275
2276 /**
2277 * @brief Set destination peripheral for DMA instance on Channel x.
2278 *
2279 * Register|BitsName
2280 * --------|--------
2281 * CFG_HI | DST_PER
2282 *
2283 * @param DMAx DMAx instance
2284 * @param channel This parameter can be one of the following values:
2285 * @arg @ref LL_DMA_CHANNEL_0
2286 * @arg @ref LL_DMA_CHANNEL_1
2287 * @arg @ref LL_DMA_CHANNEL_2
2288 * @arg @ref LL_DMA_CHANNEL_3
2289 * @arg @ref LL_DMA_CHANNEL_4
2290 * @arg @ref LL_DMA_CHANNEL_5
2291 * @arg @ref LL_DMA_CHANNEL_6
2292 * @arg @ref LL_DMA_CHANNEL_7
2293 * @param peripheral This parameter can be one of the following values:
2294 * @arg @ref LL_DMA0_PERIPH_QSPI0_TX
2295 * @arg @ref LL_DMA0_PERIPH_QSPI0_RX
2296 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
2297 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
2298 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2299 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2300 * @arg @ref LL_DMA0_PERIPH_UART0_TX
2301 * @arg @ref LL_DMA0_PERIPH_UART0_RX
2302 * @arg @ref LL_DMA0_PERIPH_UART1_TX
2303 * @arg @ref LL_DMA0_PERIPH_UART1_RX
2304 * @arg @ref LL_DMA0_PERIPH_SNSADC
2305 * @arg @ref LL_DMA0_PERIPH_OSPI_TX
2306 * @arg @ref LL_DMA0_PERIPH_OSPI_RX
2307 * @arg @ref LL_DMA0_PERIPH_UART2_TX
2308 * @arg @ref LL_DMA0_PERIPH_UART2_RX
2309 * @arg @ref LL_DMA0_PERIPH_I2C2_TX
2310 * @arg @ref LL_DMA0_PERIPH_I2C2_RX
2311 * @arg @ref LL_DMA0_PERIPH_UART3_TX
2312 * @arg @ref LL_DMA0_PERIPH_UART3_RX
2313 * @arg @ref LL_DMA0_PERIPH_I2C5_TX
2314 * @arg @ref LL_DMA0_PERIPH_I2C5_RX
2315 * @arg @ref LL_DMA0_PERIPH_I2C4_TX
2316 * @arg @ref LL_DMA0_PERIPH_I2C4_RX
2317 * @arg @ref LL_DMA0_PERIPH_UART4_TX
2318 * @arg @ref LL_DMA0_PERIPH_UART4_RX
2319 * @arg @ref LL_DMA0_PERIPH_QSPI1_TX
2320 * @arg @ref LL_DMA0_PERIPH_QSPI1_RX
2321 * @arg @ref LL_DMA0_PERIPH_I2C3_TX
2322 * @arg @ref LL_DMA0_PERIPH_I2C3_RX
2323 * @arg @ref LL_DMA1_PERIPH_OSPI_TX
2324 * @arg @ref LL_DMA1_PERIPH_OSPI_RX
2325 * @arg @ref LL_DMA1_PERIPH_QSPI2_TX
2326 * @arg @ref LL_DMA1_PERIPH_QSPI2_RX
2327 * @arg @ref LL_DMA1_PERIPH_I2S_M_TX
2328 * @arg @ref LL_DMA1_PERIPH_I2S_M_RX
2329 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2330 * @arg @ref LL_DMA1_PERIPH_I2S_S_RX
2331 * @arg @ref LL_DMA1_PERIPH_PDM_TX
2332 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX
2333 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX
2334 * @arg @ref LL_DMA1_PERIPH_I2C0_TX
2335 * @arg @ref LL_DMA1_PERIPH_I2C0_RX
2336 * @arg @ref LL_DMA1_PERIPH_I2C1_TX
2337 * @arg @ref LL_DMA1_PERIPH_I2C1_RX
2338 * @arg @ref LL_DMA1_PERIPH_SPIM_TX
2339 * @arg @ref LL_DMA1_PERIPH_SPIM_RX
2340 * @arg @ref LL_DMA1_PERIPH_DSPIM_TX
2341 * @arg @ref LL_DMA1_PERIPH_DSPIM_RX
2342 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX_2
2343 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX_2
2344 * @arg @ref LL_DMA1_PERIPH_UART3_TX
2345 * @arg @ref LL_DMA1_PERIPH_UART3_RX
2346 * @arg @ref LL_DMA1_PERIPH_UART4_TX
2347 * @arg @ref LL_DMA1_PERIPH_UART4_RX
2348 * @arg @ref LL_DMA1_PERIPH_UART5_TX
2349 * @arg @ref LL_DMA1_PERIPH_UART5_RX
2350 * @arg @ref LL_DMA1_PERIPH_UART0_TX
2351 * @arg @ref LL_DMA1_PERIPH_UART0_RX
2352 * @retval None
2353 */
2354 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
2355 {
2356 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
2357 }
2358
2359 /**
2360 * @brief Get destination peripheral for DMA instance on Channel x.
2361 *
2362 * Register|BitsName
2363 * --------|--------
2364 * CFG_HI | DST_PER
2365 *
2366 * @param DMAx DMAx instance
2367 * @param channel This parameter can be one of the following values:
2368 * @arg @ref LL_DMA_CHANNEL_0
2369 * @arg @ref LL_DMA_CHANNEL_1
2370 * @arg @ref LL_DMA_CHANNEL_2
2371 * @arg @ref LL_DMA_CHANNEL_3
2372 * @arg @ref LL_DMA_CHANNEL_4
2373 * @arg @ref LL_DMA_CHANNEL_5
2374 * @arg @ref LL_DMA_CHANNEL_6
2375 * @arg @ref LL_DMA_CHANNEL_7
2376 */
2377 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
2378 {
2379 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
2380 }
2381
2382 /**
2383 * @brief Set source and destination source handshaking interface.
2384 *
2385 * Register|BitsName
2386 * --------|--------
2387 * CFG_HI | DST_PER
2388 *
2389 * @param DMAx DMAx instance
2390 * @param channel This parameter can be one of the following values:
2391 * @arg @ref LL_DMA_CHANNEL_0
2392 * @arg @ref LL_DMA_CHANNEL_1
2393 * @arg @ref LL_DMA_CHANNEL_2
2394 * @arg @ref LL_DMA_CHANNEL_3
2395 * @arg @ref LL_DMA_CHANNEL_4
2396 * @arg @ref LL_DMA_CHANNEL_5
2397 * @arg @ref LL_DMA_CHANNEL_6
2398 * @arg @ref LL_DMA_CHANNEL_7
2399 * @param src_handshaking This parameter can be one of the following values:
2400 * @arg @ref LL_DMA_SHANDSHAKING_HW
2401 * @arg @ref LL_DMA_SHANDSHAKING_HW
2402 * @param dst_handshaking This parameter can be one of the following values:
2403 * @arg @ref LL_DMA_DHANDSHAKING_HW
2404 * @arg @ref LL_DMA_DHANDSHAKING_HW
2405 * @retval None
2406 */
2407 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
2408 {
2409 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
2410 src_handshaking | dst_handshaking);
2411 }
2412
2413 /**
2414 * @brief Set source gather interval.
2415 *
2416 * Register|BitsName
2417 * --------|--------
2418 * SGR | SGI
2419 *
2420 * @param DMAx DMAx instance.
2421 * @param channel This parameter can be one of the following values:
2422 * @arg @ref LL_DMA_CHANNEL_0
2423 * @arg @ref LL_DMA_CHANNEL_1
2424 * @arg @ref LL_DMA_CHANNEL_2
2425 * @arg @ref LL_DMA_CHANNEL_3
2426 * @arg @ref LL_DMA_CHANNEL_4
2427 * @arg @ref LL_DMA_CHANNEL_5
2428 * @arg @ref LL_DMA_CHANNEL_6
2429 * @arg @ref LL_DMA_CHANNEL_7
2430 * @param src_gather_sgi This parameter can be one of the following values:
2431 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2432 * @retval None
2433 */
2434 __STATIC_INLINE void ll_dma_set_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgi)
2435 {
2436 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI, src_gather_sgi << DMA_SGR_SGI_Pos );
2437 }
2438
2439 /**
2440 * @brief Get source gather interval.
2441 *
2442 * Register|BitsName
2443 * --------|--------
2444 * SGR | SGI
2445 *
2446 * @param DMAx DMAx instance
2447 * @param channel This parameter can be one of the following values:
2448 * @arg @ref LL_DMA_CHANNEL_0
2449 * @arg @ref LL_DMA_CHANNEL_1
2450 * @arg @ref LL_DMA_CHANNEL_2
2451 * @arg @ref LL_DMA_CHANNEL_3
2452 * @arg @ref LL_DMA_CHANNEL_4
2453 * @arg @ref LL_DMA_CHANNEL_5
2454 * @arg @ref LL_DMA_CHANNEL_6
2455 * @arg @ref LL_DMA_CHANNEL_7
2456 * @retval Returned value can be one of the following values:
2457 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2458 */
2459 __STATIC_INLINE uint32_t ll_dma_get_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel)
2460 {
2461 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI) >> DMA_SGR_SGI_Pos);
2462 }
2463
2464 /**
2465 * @brief Set source gather count.
2466 *
2467 * Register|BitsName
2468 * --------|--------
2469 * SGR | SGC
2470 *
2471 * @param DMAx DMAx instance
2472 * @param channel This parameter can be one of the following values:
2473 * @arg @ref LL_DMA_CHANNEL_0
2474 * @arg @ref LL_DMA_CHANNEL_1
2475 * @arg @ref LL_DMA_CHANNEL_2
2476 * @arg @ref LL_DMA_CHANNEL_3
2477 * @arg @ref LL_DMA_CHANNEL_4
2478 * @arg @ref LL_DMA_CHANNEL_5
2479 * @arg @ref LL_DMA_CHANNEL_6
2480 * @arg @ref LL_DMA_CHANNEL_7
2481 * @param src_gather_sgc This parameter can be one of the following values:
2482 Between Min_Data = 0 and Max_Data = 0xFFF.
2483 * @retval None
2484 */
2485 __STATIC_INLINE void ll_dma_set_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgc)
2486 {
2487 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC, src_gather_sgc << DMA_SGR_SGC_Pos );
2488 }
2489
2490 /**
2491 * @brief Get source gather count.
2492 *
2493 * Register|BitsName
2494 * --------|--------
2495 * SGR | SGC
2496 *
2497 * @param DMAx DMAx instance
2498 * @param channel This parameter can be one of the following values:
2499 * @arg @ref LL_DMA_CHANNEL_0
2500 * @arg @ref LL_DMA_CHANNEL_1
2501 * @arg @ref LL_DMA_CHANNEL_2
2502 * @arg @ref LL_DMA_CHANNEL_3
2503 * @arg @ref LL_DMA_CHANNEL_4
2504 * @arg @ref LL_DMA_CHANNEL_5
2505 * @arg @ref LL_DMA_CHANNEL_6
2506 * @arg @ref LL_DMA_CHANNEL_7
2507 * @retval Returned value can be one of the following values:
2508 Between Min_Data = 0 and Max_Data = 0xFFF.
2509 */
2510 __STATIC_INLINE uint32_t ll_dma_get_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel)
2511 {
2512 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC) >> DMA_SGR_SGC_Pos);
2513 }
2514
2515 /**
2516 * @brief Set destination scatter interval.
2517 *
2518 * Register|BitsName
2519 * --------|--------
2520 * DSR | DSI
2521 *
2522 * @param DMAx DMAx instance.
2523 * @param channel This parameter can be one of the following values:
2524 * @arg @ref LL_DMA_CHANNEL_0
2525 * @arg @ref LL_DMA_CHANNEL_1
2526 * @arg @ref LL_DMA_CHANNEL_2
2527 * @arg @ref LL_DMA_CHANNEL_3
2528 * @arg @ref LL_DMA_CHANNEL_4
2529 * @arg @ref LL_DMA_CHANNEL_5
2530 * @arg @ref LL_DMA_CHANNEL_6
2531 * @arg @ref LL_DMA_CHANNEL_7
2532 * @param dst_scatter_dsi This parameter can be one of the following values:
2533 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2534 * @retval None
2535 */
2536 __STATIC_INLINE void ll_dma_set_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsi)
2537 {
2538 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI, dst_scatter_dsi << DMA_DSR_DSI_Pos );
2539 }
2540
2541 /**
2542 * @brief Get Set destination scatter interval.
2543 *
2544 * Register|BitsName
2545 * --------|--------
2546 * DSR | DSI
2547 *
2548 * @param DMAx DMAx instance
2549 * @param channel This parameter can be one of the following values:
2550 * @arg @ref LL_DMA_CHANNEL_0
2551 * @arg @ref LL_DMA_CHANNEL_1
2552 * @arg @ref LL_DMA_CHANNEL_2
2553 * @arg @ref LL_DMA_CHANNEL_3
2554 * @arg @ref LL_DMA_CHANNEL_4
2555 * @arg @ref LL_DMA_CHANNEL_5
2556 * @arg @ref LL_DMA_CHANNEL_6
2557 * @arg @ref LL_DMA_CHANNEL_7
2558 * @retval Returned value can be one of the following values:
2559 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2560 */
2561 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel)
2562 {
2563 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI) >> DMA_DSR_DSI_Pos);
2564 }
2565
2566 /**
2567 * @brief Set destination scatter count.
2568 *
2569 * Register|BitsName
2570 * --------|--------
2571 * DSR | DSC
2572 *
2573 * @param DMAx DMAx instance
2574 * @param channel This parameter can be one of the following values:
2575 * @arg @ref LL_DMA_CHANNEL_0
2576 * @arg @ref LL_DMA_CHANNEL_1
2577 * @arg @ref LL_DMA_CHANNEL_2
2578 * @arg @ref LL_DMA_CHANNEL_3
2579 * @arg @ref LL_DMA_CHANNEL_4
2580 * @arg @ref LL_DMA_CHANNEL_5
2581 * @arg @ref LL_DMA_CHANNEL_6
2582 * @arg @ref LL_DMA_CHANNEL_7
2583 * @param dst_scatter_dsc This parameter can be one of the following values:
2584 Between Min_Data = 0 and Max_Data = 0xFFF.
2585 * @retval None
2586 */
2587 __STATIC_INLINE void ll_dma_set_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsc)
2588 {
2589 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC, dst_scatter_dsc << DMA_DSR_DSC_Pos );
2590 }
2591
2592 /**
2593 * @brief Get destination scatter count..
2594 *
2595 * Register|BitsName
2596 * --------|--------
2597 * DSR | DSC
2598 *
2599 * @param DMAx DMAx instance
2600 * @param channel This parameter can be one of the following values:
2601 * @arg @ref LL_DMA_CHANNEL_0
2602 * @arg @ref LL_DMA_CHANNEL_1
2603 * @arg @ref LL_DMA_CHANNEL_2
2604 * @arg @ref LL_DMA_CHANNEL_3
2605 * @arg @ref LL_DMA_CHANNEL_4
2606 * @arg @ref LL_DMA_CHANNEL_5
2607 * @arg @ref LL_DMA_CHANNEL_6
2608 * @arg @ref LL_DMA_CHANNEL_7
2609 * @retval Returned value can be one of the following values:
2610 Between Min_Data = 0 and Max_Data = 0xFFF.
2611 */
2612 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel)
2613 {
2614 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC) >> DMA_DSR_DSC_Pos);
2615 }
2616
2617 /**
2618 * @brief Source Single Transaction Request.
2619 *
2620 * Register|BitsName
2621 * --------|--------
2622 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
2623 * REQ_SRC | SRC_WE&SRC
2624 *
2625 * @param DMAx DMA instance.
2626 * @param channel This parameter can be one of the following values:
2627 * @arg @ref LL_DMA_CHANNEL_0
2628 * @arg @ref LL_DMA_CHANNEL_1
2629 * @arg @ref LL_DMA_CHANNEL_2
2630 * @arg @ref LL_DMA_CHANNEL_3
2631 * @arg @ref LL_DMA_CHANNEL_4
2632 * @arg @ref LL_DMA_CHANNEL_5
2633 * @arg @ref LL_DMA_CHANNEL_6
2634 * @arg @ref LL_DMA_CHANNEL_7
2635 * @retval None
2636 */
2637 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2638 {
2639 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2640 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2641 }
2642
2643 /**
2644 * @brief Source Burst Transaction Request.
2645 *
2646 * Register|BitsName
2647 * --------|--------
2648 * REQ_SRC | SRC_WE&SRC
2649 *
2650 * @param DMAx DMA instance.
2651 * @param channel This parameter can be one of the following values:
2652 * @arg @ref LL_DMA_CHANNEL_0
2653 * @arg @ref LL_DMA_CHANNEL_1
2654 * @arg @ref LL_DMA_CHANNEL_2
2655 * @arg @ref LL_DMA_CHANNEL_3
2656 * @arg @ref LL_DMA_CHANNEL_4
2657 * @arg @ref LL_DMA_CHANNEL_5
2658 * @arg @ref LL_DMA_CHANNEL_6
2659 * @arg @ref LL_DMA_CHANNEL_7
2660 * @retval None
2661 */
2662 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2663 {
2664 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2665 }
2666
2667 /**
2668 * @brief Source Last Single Transaction Request.
2669 *
2670 * Register|BitsName
2671 * --------|--------
2672 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
2673 * LST_SRC | LST_SRC_WE&LST_SRC
2674 * REQ_SRC | SRC_WE&SRC
2675 *
2676 * @param DMAx DMA instance.
2677 * @param channel This parameter can be one of the following values:
2678 * @arg @ref LL_DMA_CHANNEL_0
2679 * @arg @ref LL_DMA_CHANNEL_1
2680 * @arg @ref LL_DMA_CHANNEL_2
2681 * @arg @ref LL_DMA_CHANNEL_3
2682 * @arg @ref LL_DMA_CHANNEL_4
2683 * @arg @ref LL_DMA_CHANNEL_5
2684 * @arg @ref LL_DMA_CHANNEL_6
2685 * @arg @ref LL_DMA_CHANNEL_7
2686 * @retval None
2687 */
2688 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2689 {
2690 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2691 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2692 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2693 }
2694
2695 /**
2696 * @brief Source Last Burst Transaction Request.
2697 *
2698 * Register|BitsName
2699 * --------|--------
2700 * LST_SRC | LST_SRC_WE&LST_SRC
2701 * REQ_SRC | SRC_WE&SRC
2702 *
2703 * @param DMAx DMA instance.
2704 * @param channel This parameter can be one of the following values:
2705 * @arg @ref LL_DMA_CHANNEL_0
2706 * @arg @ref LL_DMA_CHANNEL_1
2707 * @arg @ref LL_DMA_CHANNEL_2
2708 * @arg @ref LL_DMA_CHANNEL_3
2709 * @arg @ref LL_DMA_CHANNEL_4
2710 * @arg @ref LL_DMA_CHANNEL_5
2711 * @arg @ref LL_DMA_CHANNEL_6
2712 * @arg @ref LL_DMA_CHANNEL_7
2713 * @retval None
2714 */
2715 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2716 {
2717 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2718 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2719 }
2720
2721 /**
2722 * @brief Destination Single Transaction Request.
2723 *
2724 * Register|BitsName
2725 * --------|--------
2726 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
2727 * REQ_DST | DST_WE&DST
2728 *
2729 * @param DMAx DMA instance.
2730 * @param channel This parameter can be one of the following values:
2731 * @arg @ref LL_DMA_CHANNEL_0
2732 * @arg @ref LL_DMA_CHANNEL_1
2733 * @arg @ref LL_DMA_CHANNEL_2
2734 * @arg @ref LL_DMA_CHANNEL_3
2735 * @arg @ref LL_DMA_CHANNEL_4
2736 * @arg @ref LL_DMA_CHANNEL_5
2737 * @arg @ref LL_DMA_CHANNEL_6
2738 * @arg @ref LL_DMA_CHANNEL_7
2739 * @retval None
2740 */
2741 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2742 {
2743 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2744 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2745 }
2746
2747 /**
2748 * @brief Destination Burst Transaction Request.
2749 *
2750 * Register|BitsName
2751 * --------|--------
2752 * REQ_DST | DST_WE&DST
2753 *
2754 * @param DMAx DMA instance.
2755 * @param channel This parameter can be one of the following values:
2756 * @arg @ref LL_DMA_CHANNEL_0
2757 * @arg @ref LL_DMA_CHANNEL_1
2758 * @arg @ref LL_DMA_CHANNEL_2
2759 * @arg @ref LL_DMA_CHANNEL_3
2760 * @arg @ref LL_DMA_CHANNEL_4
2761 * @arg @ref LL_DMA_CHANNEL_5
2762 * @arg @ref LL_DMA_CHANNEL_6
2763 * @arg @ref LL_DMA_CHANNEL_7
2764 * @retval None
2765 */
2766 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2767 {
2768 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2769 }
2770
2771 /**
2772 * @brief Destination Last Single Transaction Request.
2773 *
2774 * Register|BitsName
2775 * --------|--------
2776 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
2777 * LST_DST | LST_DST_WE&LST_DST
2778 * REQ_DST | DST_WE&DST
2779 *
2780 * @param DMAx DMA instance.
2781 * @param channel This parameter can be one of the following values:
2782 * @arg @ref LL_DMA_CHANNEL_0
2783 * @arg @ref LL_DMA_CHANNEL_1
2784 * @arg @ref LL_DMA_CHANNEL_2
2785 * @arg @ref LL_DMA_CHANNEL_3
2786 * @arg @ref LL_DMA_CHANNEL_4
2787 * @arg @ref LL_DMA_CHANNEL_5
2788 * @arg @ref LL_DMA_CHANNEL_6
2789 * @arg @ref LL_DMA_CHANNEL_7
2790 * @retval None
2791 */
2792 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2793 {
2794 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2795 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2796 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2797 }
2798
2799 /**
2800 * @brief Destination Last Burst Transaction Request.
2801 *
2802 * Register|BitsName
2803 * --------|--------
2804 * LST_DST | LST_DST_WE&LST_DST
2805 * REQ_DST | DST_WE&DST
2806 *
2807 * @param DMAx DMA instance.
2808 * @param channel This parameter can be one of the following values:
2809 * @arg @ref LL_DMA_CHANNEL_0
2810 * @arg @ref LL_DMA_CHANNEL_1
2811 * @arg @ref LL_DMA_CHANNEL_2
2812 * @arg @ref LL_DMA_CHANNEL_3
2813 * @arg @ref LL_DMA_CHANNEL_4
2814 * @arg @ref LL_DMA_CHANNEL_5
2815 * @arg @ref LL_DMA_CHANNEL_6
2816 * @arg @ref LL_DMA_CHANNEL_7
2817 * @retval None
2818 */
2819 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2820 {
2821 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2822 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2823 }
2824
2825 /** @} */
2826
2827 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2828 * @{
2829 */
2830
2831 /**
2832 * @brief Get DMA Module global transfer complete interrupt status.
2833 *
2834 * Register|BitsName
2835 * --------|--------
2836 * STATUS_INT | TFR
2837 *
2838 * @param DMAx DMAx instance
2839 * @retval State of bit (1 or 0).
2840 */
2841 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
2842 {
2843 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2844 }
2845
2846 /**
2847 * @brief Get DMA Module global block complete interrupt status.
2848 *
2849 * Register|BitsName
2850 * --------|--------
2851 * STATUS_INT | BLOCK
2852 *
2853 * @param DMAx DMAx instance
2854 * @retval State of bit (1 or 0).
2855 */
2856 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
2857 {
2858 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2859 }
2860
2861 /**
2862 * @brief Get DMA Module global source transaction complete interrupt status.
2863 *
2864 * Register|BitsName
2865 * --------|--------
2866 * STATUS_INT | SRCT
2867 *
2868 * @param DMAx DMAx instance
2869 * @retval State of bit (1 or 0).
2870 */
2871 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
2872 {
2873 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2874 }
2875
2876 /**
2877 * @brief Get DMA Module global destination transaction complete interrupt status.
2878 *
2879 * Register|BitsName
2880 * --------|--------
2881 * STATUS_INT | DSTT
2882 *
2883 * @param DMAx DMAx instance
2884 * @retval State of bit (1 or 0).
2885 */
2886 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
2887 {
2888 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2889 }
2890
2891 /**
2892 * @brief Get DMA Module global error interrupt status.
2893 *
2894 * Register|BitsName
2895 * --------|--------
2896 * STATUS_INT | ERR
2897 *
2898 * @param DMAx DMAx instance
2899 * @retval State of bit (1 or 0).
2900 */
2901 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
2902 {
2903 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2904 }
2905
2906 /**
2907 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
2908 *
2909 * Register|BitsName
2910 * --------|--------
2911 * RAW_TFR | RAW
2912 *
2913 * @param DMAx DMAx instance
2914 * @param channel This parameter can be one of the following values:
2915 * @arg @ref LL_DMA_CHANNEL_0
2916 * @arg @ref LL_DMA_CHANNEL_1
2917 * @arg @ref LL_DMA_CHANNEL_2
2918 * @arg @ref LL_DMA_CHANNEL_3
2919 * @arg @ref LL_DMA_CHANNEL_4
2920 * @arg @ref LL_DMA_CHANNEL_5
2921 * @arg @ref LL_DMA_CHANNEL_6
2922 * @arg @ref LL_DMA_CHANNEL_7
2923 * @retval State of bit (1 or 0).
2924 */
2925 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
2926 {
2927 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2928 }
2929
2930 /**
2931 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
2932 *
2933 * Register|BitsName
2934 * --------|--------
2935 * RAW_BLK | RAW
2936 *
2937 * @param DMAx DMAx instance
2938 * @param channel This parameter can be one of the following values:
2939 * @arg @ref LL_DMA_CHANNEL_0
2940 * @arg @ref LL_DMA_CHANNEL_1
2941 * @arg @ref LL_DMA_CHANNEL_2
2942 * @arg @ref LL_DMA_CHANNEL_3
2943 * @arg @ref LL_DMA_CHANNEL_4
2944 * @arg @ref LL_DMA_CHANNEL_5
2945 * @arg @ref LL_DMA_CHANNEL_6
2946 * @arg @ref LL_DMA_CHANNEL_7
2947 * @retval State of bit (1 or 0).
2948 */
2949 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
2950 {
2951 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2952 }
2953
2954 /**
2955 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
2956 *
2957 * Register|BitsName
2958 * --------|--------
2959 * RAW_SRC_TRN | RAW
2960 *
2961 * @param DMAx DMAx instance
2962 * @param channel This parameter can be one of the following values:
2963 * @arg @ref LL_DMA_CHANNEL_0
2964 * @arg @ref LL_DMA_CHANNEL_1
2965 * @arg @ref LL_DMA_CHANNEL_2
2966 * @arg @ref LL_DMA_CHANNEL_3
2967 * @arg @ref LL_DMA_CHANNEL_4
2968 * @arg @ref LL_DMA_CHANNEL_5
2969 * @arg @ref LL_DMA_CHANNEL_6
2970 * @arg @ref LL_DMA_CHANNEL_7
2971 * @retval State of bit (1 or 0).
2972 */
2973 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
2974 {
2975 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2976 }
2977
2978 /**
2979 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
2980 *
2981 * Register|BitsName
2982 * --------|--------
2983 * RAW_DST_TRN | RAW
2984 *
2985 * @param DMAx DMAx instance
2986 * @param channel This parameter can be one of the following values:
2987 * @arg @ref LL_DMA_CHANNEL_0
2988 * @arg @ref LL_DMA_CHANNEL_1
2989 * @arg @ref LL_DMA_CHANNEL_2
2990 * @arg @ref LL_DMA_CHANNEL_3
2991 * @arg @ref LL_DMA_CHANNEL_4
2992 * @arg @ref LL_DMA_CHANNEL_5
2993 * @arg @ref LL_DMA_CHANNEL_6
2994 * @arg @ref LL_DMA_CHANNEL_7
2995 * @retval State of bit (1 or 0).
2996 */
2997 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
2998 {
2999 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
3000 }
3001
3002 /**
3003 * @brief Indicate the Raw Status of IntErr Interrupt flag.
3004 *
3005 * Register|BitsName
3006 * --------|--------
3007 * RAW_ERR | RAW
3008 *
3009 * @param DMAx DMAx instance
3010 * @param channel This parameter can be one of the following values:
3011 * @arg @ref LL_DMA_CHANNEL_0
3012 * @arg @ref LL_DMA_CHANNEL_1
3013 * @arg @ref LL_DMA_CHANNEL_2
3014 * @arg @ref LL_DMA_CHANNEL_3
3015 * @arg @ref LL_DMA_CHANNEL_4
3016 * @arg @ref LL_DMA_CHANNEL_5
3017 * @arg @ref LL_DMA_CHANNEL_6
3018 * @arg @ref LL_DMA_CHANNEL_7
3019 * @retval State of bit (1 or 0).
3020 */
3021 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
3022 {
3023 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
3024 }
3025
3026 /**
3027 * @brief Indicate the status of DMA Channel transfer complete flag.
3028 *
3029 * Register|BitsName
3030 * --------|--------
3031 * STAT_TFR | STATUS
3032 *
3033 * @param DMAx DMAx instance
3034 * @param channel This parameter can be one of the following values:
3035 * @arg @ref LL_DMA_CHANNEL_0
3036 * @arg @ref LL_DMA_CHANNEL_1
3037 * @arg @ref LL_DMA_CHANNEL_2
3038 * @arg @ref LL_DMA_CHANNEL_3
3039 * @arg @ref LL_DMA_CHANNEL_4
3040 * @arg @ref LL_DMA_CHANNEL_5
3041 * @arg @ref LL_DMA_CHANNEL_6
3042 * @arg @ref LL_DMA_CHANNEL_7
3043 * @retval State of bit (1 or 0).
3044 */
3045 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
3046 {
3047 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
3048 }
3049
3050 /**
3051 * @brief Indicate the status of Channel 0 transfer complete flag.
3052 *
3053 * Register|BitsName
3054 * --------|--------
3055 * STAT_TFR | STATUS
3056 *
3057 * @param DMAx DMAx instance
3058 * @retval State of bit (1 or 0).
3059 */
3060 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
3061 {
3062 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
3063 }
3064
3065 /**
3066 * @brief Indicate the status of Channel 1 transfer complete flag.
3067 *
3068 * Register|BitsName
3069 * --------|--------
3070 * STAT_TFR | STATUS
3071 *
3072 * @param DMAx DMAx instance
3073 * @retval State of bit (1 or 0).
3074 */
3075 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
3076 {
3077 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
3078 }
3079
3080 /**
3081 * @brief Indicate the status of Channel 2 transfer complete flag.
3082 *
3083 * Register|BitsName
3084 * --------|--------
3085 * STAT_TFR | STATUS
3086 *
3087 * @param DMAx DMAx instance
3088 * @retval State of bit (1 or 0).
3089 */
3090 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
3091 {
3092 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
3093 }
3094
3095 /**
3096 * @brief Indicate the status of Channel 3 transfer complete flag.
3097 *
3098 * Register|BitsName
3099 * --------|--------
3100 * STAT_TFR | STATUS
3101 *
3102 * @param DMAx DMAx instance
3103 * @retval State of bit (1 or 0).
3104 */
3105 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
3106 {
3107 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
3108 }
3109
3110 /**
3111 * @brief Indicate the status of Channel 4 transfer complete flag.
3112 *
3113 * Register|BitsName
3114 * --------|--------
3115 * STAT_TFR | STATUS
3116 *
3117 * @param DMAx DMAx instance
3118 * @retval State of bit (1 or 0).
3119 */
3120 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
3121 {
3122 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
3123 }
3124
3125 /**
3126 * @brief Indicate the status of Channel 5 transfer complete flag.
3127 *
3128 * Register|BitsName
3129 * --------|--------
3130 * STAT_TFR | STATUS
3131 *
3132 * @param DMAx DMAx instance
3133 * @retval State of bit (1 or 0).
3134 */
3135 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
3136 {
3137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
3138 }
3139
3140 /**
3141 * @brief Indicate the status of Channel 6 transfer complete flag.
3142 *
3143 * Register|BitsName
3144 * --------|--------
3145 * STAT_TFR | STATUS
3146 *
3147 * @param DMAx DMAx instance
3148 * @retval State of bit (1 or 0).
3149 */
3150 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
3151 {
3152 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
3153 }
3154
3155 /**
3156 * @brief Indicate the status of Channel 7 transfer complete flag.
3157 *
3158 * Register|BitsName
3159 * --------|--------
3160 * STAT_TFR | STATUS
3161 *
3162 * @param DMAx DMAx instance
3163 * @retval State of bit (1 or 0).
3164 */
3165 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
3166 {
3167 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
3168 }
3169
3170 /**
3171 * @brief Indicate the status of DMA Channel block complete flag.
3172 *
3173 * Register|BitsName
3174 * --------|--------
3175 * STAT_BLK | STATUS
3176 *
3177 * @param DMAx DMAx instance
3178 * @param channel This parameter can be one of the following values:
3179 * @arg @ref LL_DMA_CHANNEL_0
3180 * @arg @ref LL_DMA_CHANNEL_1
3181 * @arg @ref LL_DMA_CHANNEL_2
3182 * @arg @ref LL_DMA_CHANNEL_3
3183 * @arg @ref LL_DMA_CHANNEL_4
3184 * @arg @ref LL_DMA_CHANNEL_5
3185 * @arg @ref LL_DMA_CHANNEL_6
3186 * @arg @ref LL_DMA_CHANNEL_7
3187 * @retval State of bit (1 or 0).
3188 */
3189 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
3190 {
3191 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
3192 }
3193
3194 /**
3195 * @brief Indicate the status of Channel 0 block complete flag.
3196 *
3197 * Register|BitsName
3198 * --------|--------
3199 * STAT_BLK | STATUS
3200 *
3201 * @param DMAx DMAx instance
3202 * @retval State of bit (1 or 0).
3203 */
3204 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
3205 {
3206 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
3207 }
3208
3209 /**
3210 * @brief Indicate the status of Channel 1 block complete flag.
3211 *
3212 * Register|BitsName
3213 * --------|--------
3214 * STAT_BLK | STATUS
3215 *
3216 * @param DMAx DMAx instance
3217 * @retval State of bit (1 or 0).
3218 */
3219 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
3220 {
3221 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
3222 }
3223
3224 /**
3225 * @brief Indicate the status of Channel 2 block complete flag.
3226 *
3227 * Register|BitsName
3228 * --------|--------
3229 * STAT_BLK | STATUS
3230 *
3231 * @param DMAx DMAx instance
3232 * @retval State of bit (1 or 0).
3233 */
3234 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
3235 {
3236 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
3237 }
3238
3239 /**
3240 * @brief Indicate the status of Channel 3 block complete flag.
3241 *
3242 * Register|BitsName
3243 * --------|--------
3244 * STAT_BLK | STATUS
3245 *
3246 * @param DMAx DMAx instance
3247 * @retval State of bit (1 or 0).
3248 */
3249 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
3250 {
3251 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
3252 }
3253
3254 /**
3255 * @brief Indicate the status of Channel 4 block complete flag.
3256 *
3257 * Register|BitsName
3258 * --------|--------
3259 * STAT_BLK | STATUS
3260 *
3261 * @param DMAx DMAx instance
3262 * @retval State of bit (1 or 0).
3263 */
3264 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
3265 {
3266 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
3267 }
3268
3269 /**
3270 * @brief Indicate the status of Channel 5 block complete flag.
3271 *
3272 * Register|BitsName
3273 * --------|--------
3274 * STAT_BLK | STATUS
3275 *
3276 * @param DMAx DMAx instance
3277 * @retval State of bit (1 or 0).
3278 */
3279 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
3280 {
3281 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
3282 }
3283
3284 /**
3285 * @brief Indicate the status of Channel 6 block complete flag.
3286 *
3287 * Register|BitsName
3288 * --------|--------
3289 * STAT_BLK | STATUS
3290 *
3291 * @param DMAx DMAx instance
3292 * @retval State of bit (1 or 0).
3293 */
3294 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
3295 {
3296 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
3297 }
3298
3299 /**
3300 * @brief Indicate the status of Channel 7 block complete flag.
3301 *
3302 * Register|BitsName
3303 * --------|--------
3304 * STAT_BLK | STATUS
3305 *
3306 * @param DMAx DMAx instance
3307 * @retval State of bit (1 or 0).
3308 */
3309 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
3310 {
3311 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
3312 }
3313
3314 /**
3315 * @brief Indicate the status of DMA Channel source transaction complete flag.
3316 *
3317 * Register|BitsName
3318 * --------|--------
3319 * STAT_SRC_TRN | STATUS
3320 *
3321 * @param DMAx DMAx instance
3322 * @param channel This parameter can be one of the following values:
3323 * @arg @ref LL_DMA_CHANNEL_0
3324 * @arg @ref LL_DMA_CHANNEL_1
3325 * @arg @ref LL_DMA_CHANNEL_2
3326 * @arg @ref LL_DMA_CHANNEL_3
3327 * @arg @ref LL_DMA_CHANNEL_4
3328 * @arg @ref LL_DMA_CHANNEL_5
3329 * @arg @ref LL_DMA_CHANNEL_6
3330 * @arg @ref LL_DMA_CHANNEL_7
3331 * @retval State of bit (1 or 0).
3332 */
3333 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
3334 {
3335 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
3336 }
3337
3338 /**
3339 * @brief Indicate the status of Channel 0 source transaction complete flag.
3340 *
3341 * Register|BitsName
3342 * --------|--------
3343 * STAT_SRC_TRN | STATUS
3344 *
3345 * @param DMAx DMAx instance
3346 * @retval State of bit (1 or 0).
3347 */
3348 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
3349 {
3350 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
3351 }
3352
3353 /**
3354 * @brief Indicate the status of Channel 1 source transaction complete flag.
3355 *
3356 * Register|BitsName
3357 * --------|--------
3358 * STAT_SRC_TRN | STATUS
3359 *
3360 * @param DMAx DMAx instance
3361 * @retval State of bit (1 or 0).
3362 */
3363 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
3364 {
3365 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
3366 }
3367
3368 /**
3369 * @brief Indicate the status of Channel 2 source transaction complete flag.
3370 *
3371 * Register|BitsName
3372 * --------|--------
3373 * STAT_SRC_TRN | STATUS
3374 *
3375 * @param DMAx DMAx instance
3376 * @retval State of bit (1 or 0).
3377 */
3378 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
3379 {
3380 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
3381 }
3382
3383 /**
3384 * @brief Indicate the status of Channel 3 source transaction complete flag.
3385 *
3386 * Register|BitsName
3387 * --------|--------
3388 * STAT_SRC_TRN | STATUS
3389 *
3390 * @param DMAx DMAx instance
3391 * @retval State of bit (1 or 0).
3392 */
3393 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
3394 {
3395 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
3396 }
3397
3398 /**
3399 * @brief Indicate the status of Channel 4 source transaction complete flag.
3400 *
3401 * Register|BitsName
3402 * --------|--------
3403 * STAT_SRC_TRN | STATUS
3404 *
3405 * @param DMAx DMAx instance
3406 * @retval State of bit (1 or 0).
3407 */
3408 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
3409 {
3410 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
3411 }
3412
3413 /**
3414 * @brief Indicate the status of Channel 5 source transaction complete flag.
3415 *
3416 * Register|BitsName
3417 * --------|--------
3418 * STAT_SRC_TRN | STATUS
3419 *
3420 * @param DMAx DMAx instance
3421 * @retval State of bit (1 or 0).
3422 */
3423 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
3424 {
3425 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
3426 }
3427
3428 /**
3429 * @brief Indicate the status of Channel 6 source transaction complete flag.
3430 *
3431 * Register|BitsName
3432 * --------|--------
3433 * STAT_SRC_TRN | STATUS
3434 *
3435 * @param DMAx DMAx instance
3436 * @retval State of bit (1 or 0).
3437 */
3438 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
3439 {
3440 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
3441 }
3442
3443 /**
3444 * @brief Indicate the status of Channel 7 source transaction complete flag.
3445 *
3446 * Register|BitsName
3447 * --------|--------
3448 * STAT_SRC_TRN | STATUS
3449 *
3450 * @param DMAx DMAx instance
3451 * @retval State of bit (1 or 0).
3452 */
3453 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
3454 {
3455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
3456 }
3457
3458 /**
3459 * @brief Indicate the status of DMA Channel destination transaction complete flag.
3460 *
3461 * Register|BitsName
3462 * --------|--------
3463 * STAT_DST_TRN | STATUS
3464 *
3465 * @param DMAx DMAx instance
3466 * @param channel This parameter can be one of the following values:
3467 * @arg @ref LL_DMA_CHANNEL_0
3468 * @arg @ref LL_DMA_CHANNEL_1
3469 * @arg @ref LL_DMA_CHANNEL_2
3470 * @arg @ref LL_DMA_CHANNEL_3
3471 * @arg @ref LL_DMA_CHANNEL_4
3472 * @arg @ref LL_DMA_CHANNEL_5
3473 * @arg @ref LL_DMA_CHANNEL_6
3474 * @arg @ref LL_DMA_CHANNEL_7
3475 * @retval State of bit (1 or 0).
3476 */
3477 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
3478 {
3479 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
3480 }
3481
3482 /**
3483 * @brief Indicate the status of Channel 0 destination transaction complete flag.
3484 *
3485 * Register|BitsName
3486 * --------|--------
3487 * STAT_DST_TRN | STATUS
3488 *
3489 * @param DMAx DMAx instance
3490 * @retval State of bit (1 or 0).
3491 */
3492 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
3493 {
3494 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
3495 }
3496
3497 /**
3498 * @brief Indicate the status of Channel 1 destination transaction complete flag.
3499 *
3500 * Register|BitsName
3501 * --------|--------
3502 * STAT_DST_TRN | STATUS
3503 *
3504 * @param DMAx DMAx instance
3505 * @retval State of bit (1 or 0).
3506 */
3507 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
3508 {
3509 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
3510 }
3511
3512 /**
3513 * @brief Indicate the status of Channel 2 destination transaction complete flag.
3514 *
3515 * Register|BitsName
3516 * --------|--------
3517 * STAT_DST_TRN | STATUS
3518 *
3519 * @param DMAx DMAx instance
3520 * @retval State of bit (1 or 0).
3521 */
3522 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
3523 {
3524 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
3525 }
3526
3527 /**
3528 * @brief Indicate the status of Channel 3 destination transaction complete flag.
3529 *
3530 * Register|BitsName
3531 * --------|--------
3532 * STAT_DST_TRN | STATUS
3533 *
3534 * @param DMAx DMAx instance
3535 * @retval State of bit (1 or 0).
3536 */
3537 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
3538 {
3539 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
3540 }
3541
3542 /**
3543 * @brief Indicate the status of Channel 4 destination transaction complete flag.
3544 *
3545 * Register|BitsName
3546 * --------|--------
3547 * STAT_DST_TRN | STATUS
3548 *
3549 * @param DMAx DMAx instance
3550 * @retval State of bit (1 or 0).
3551 */
3552 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
3553 {
3554 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
3555 }
3556
3557 /**
3558 * @brief Indicate the status of Channel 5 destination transaction complete flag.
3559 *
3560 * Register|BitsName
3561 * --------|--------
3562 * STAT_DST_TRN | STATUS
3563 *
3564 * @param DMAx DMAx instance
3565 * @retval State of bit (1 or 0).
3566 */
3567 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
3568 {
3569 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
3570 }
3571
3572 /**
3573 * @brief Indicate the status of Channel 6 destination transaction complete flag.
3574 *
3575 * Register|BitsName
3576 * --------|--------
3577 * STAT_DST_TRN | STATUS
3578 *
3579 * @param DMAx DMAx instance
3580 * @retval State of bit (1 or 0).
3581 */
3582 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
3583 {
3584 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
3585 }
3586
3587 /**
3588 * @brief Indicate the status of Channel 7 destination transaction complete flag.
3589 *
3590 * Register|BitsName
3591 * --------|--------
3592 * STAT_DST_TRN | STATUS
3593 *
3594 * @param DMAx DMAx instance
3595 * @retval State of bit (1 or 0).
3596 */
3597 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
3598 {
3599 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
3600 }
3601
3602 /**
3603 * @brief Indicate the status of DMA Channel error flag.
3604 *
3605 * Register|BitsName
3606 * --------|--------
3607 * STAT_ERR | STATUS
3608 *
3609 * @param DMAx DMAx instance
3610 * @param channel This parameter can be one of the following values:
3611 * @arg @ref LL_DMA_CHANNEL_0
3612 * @arg @ref LL_DMA_CHANNEL_1
3613 * @arg @ref LL_DMA_CHANNEL_2
3614 * @arg @ref LL_DMA_CHANNEL_3
3615 * @arg @ref LL_DMA_CHANNEL_4
3616 * @arg @ref LL_DMA_CHANNEL_5
3617 * @arg @ref LL_DMA_CHANNEL_6
3618 * @arg @ref LL_DMA_CHANNEL_7
3619 * @retval State of bit (1 or 0).
3620 */
3621 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
3622 {
3623 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3624 }
3625
3626 /**
3627 * @brief Indicate the status of Channel 0 error flag.
3628 *
3629 * Register|BitsName
3630 * --------|--------
3631 * STAT_ERR | STATUS
3632 *
3633 * @param DMAx DMAx instance
3634 * @retval State of bit (1 or 0).
3635 */
3636 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
3637 {
3638 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3639 }
3640
3641 /**
3642 * @brief Indicate the status of Channel 1 error flag.
3643 *
3644 * Register|BitsName
3645 * --------|--------
3646 * STAT_ERR | STATUS
3647 *
3648 * @param DMAx DMAx instance
3649 * @retval State of bit (1 or 0).
3650 */
3651 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
3652 {
3653 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3654 }
3655
3656 /**
3657 * @brief Indicate the status of Channel 2 error flag.
3658 *
3659 * Register|BitsName
3660 * --------|--------
3661 * STAT_ERR | STATUS
3662 *
3663 * @param DMAx DMAx instance
3664 * @retval State of bit (1 or 0).
3665 */
3666 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
3667 {
3668 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3669 }
3670
3671 /**
3672 * @brief Indicate the status of Channel 3 error flag.
3673 *
3674 * Register|BitsName
3675 * --------|--------
3676 * STAT_ERR | STATUS
3677 *
3678 * @param DMAx DMAx instance
3679 * @retval State of bit (1 or 0).
3680 */
3681 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
3682 {
3683 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3684 }
3685
3686 /**
3687 * @brief Indicate the status of Channel 4 error flag.
3688 *
3689 * Register|BitsName
3690 * --------|--------
3691 * STAT_ERR | STATUS
3692 *
3693 * @param DMAx DMAx instance
3694 * @retval State of bit (1 or 0).
3695 */
3696 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
3697 {
3698 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3699 }
3700
3701 /**
3702 * @brief Indicate the status of Channel 5 error flag.
3703 *
3704 * Register|BitsName
3705 * --------|--------
3706 * STAT_ERR | STATUS
3707 *
3708 * @param DMAx DMAx instance
3709 * @retval State of bit (1 or 0).
3710 */
3711 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
3712 {
3713 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3714 }
3715
3716 /**
3717 * @brief Indicate the status of Channel 6 error flag.
3718 *
3719 * Register|BitsName
3720 * --------|--------
3721 * STAT_ERR | STATUS
3722 *
3723 * @param DMAx DMAx instance
3724 * @retval State of bit (1 or 0).
3725 */
3726 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
3727 {
3728 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3729 }
3730
3731 /**
3732 * @brief Indicate the status of Channel 7 error flag.
3733 *
3734 * Register|BitsName
3735 * --------|--------
3736 * STAT_ERR | STATUS
3737 *
3738 * @param DMAx DMAx instance
3739 * @retval State of bit (1 or 0).
3740 */
3741 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
3742 {
3743 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3744 }
3745
3746 /**
3747 * @brief Clear DMA Channel transfer complete flag.
3748 *
3749 * Register|BitsName
3750 * --------|--------
3751 * CLR_TFR | CLEAR
3752 *
3753 * @param DMAx DMAx instance
3754 * @param channel This parameter can be one of the following values:
3755 * @arg @ref LL_DMA_CHANNEL_0
3756 * @arg @ref LL_DMA_CHANNEL_1
3757 * @arg @ref LL_DMA_CHANNEL_2
3758 * @arg @ref LL_DMA_CHANNEL_3
3759 * @arg @ref LL_DMA_CHANNEL_4
3760 * @arg @ref LL_DMA_CHANNEL_5
3761 * @arg @ref LL_DMA_CHANNEL_6
3762 * @arg @ref LL_DMA_CHANNEL_7
3763 * @retval None.
3764 */
3765 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
3766 {
3767 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3768 }
3769
3770 /**
3771 * @brief Clear Channel 0 transfer complete flag.
3772 *
3773 * Register|BitsName
3774 * --------|--------
3775 * CLR_TFR | CLEAR
3776 *
3777 * @param DMAx DMAx instance
3778 * @retval None.
3779 */
3780 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
3781 {
3782 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3783 }
3784
3785 /**
3786 * @brief Clear Channel 1 transfer complete flag.
3787 *
3788 * Register|BitsName
3789 * --------|--------
3790 * CLR_TFR | CLEAR
3791 *
3792 * @param DMAx DMAx instance
3793 * @retval None.
3794 */
3795 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
3796 {
3797 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3798 }
3799
3800 /**
3801 * @brief Clear Channel 2 transfer complete flag.
3802 *
3803 * Register|BitsName
3804 * --------|--------
3805 * CLR_TFR | CLEAR
3806 *
3807 * @param DMAx DMAx instance
3808 * @retval None.
3809 */
3810 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
3811 {
3812 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3813 }
3814
3815 /**
3816 * @brief Clear Channel 3 transfer complete flag.
3817 *
3818 * Register|BitsName
3819 * --------|--------
3820 * CLR_TFR | CLEAR
3821 *
3822 * @param DMAx DMAx instance
3823 * @retval None.
3824 */
3825 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
3826 {
3827 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3828 }
3829
3830 /**
3831 * @brief Clear Channel 4 transfer complete flag.
3832 *
3833 * Register|BitsName
3834 * --------|--------
3835 * CLR_TFR | CLEAR
3836 *
3837 * @param DMAx DMAx instance
3838 * @retval None.
3839 */
3840 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
3841 {
3842 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3843 }
3844
3845 /**
3846 * @brief Clear Channel 5 transfer complete flag.
3847 *
3848 * Register|BitsName
3849 * --------|--------
3850 * CLR_TFR | CLEAR
3851 *
3852 * @param DMAx DMAx instance
3853 * @retval None.
3854 */
3855 __STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
3856 {
3857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3858 }
3859
3860 /**
3861 * @brief Clear Channel 6 transfer complete flag.
3862 *
3863 * Register|BitsName
3864 * --------|--------
3865 * CLR_TFR | CLEAR
3866 *
3867 * @param DMAx DMAx instance
3868 * @retval None.
3869 */
3870 __STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
3871 {
3872 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3873 }
3874
3875 /**
3876 * @brief Clear Channel 7 transfer complete flag.
3877 *
3878 * Register|BitsName
3879 * --------|--------
3880 * CLR_TFR | CLEAR
3881 *
3882 * @param DMAx DMAx instance
3883 * @retval None.
3884 */
3885 __STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
3886 {
3887 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3888 }
3889
3890 /**
3891 * @brief Clear DMA Channel block complete flag.
3892 *
3893 * Register|BitsName
3894 * --------|--------
3895 * CLR_BLK | CLEAR
3896 *
3897 * @param DMAx DMAx instance
3898 * @param channel This parameter can be one of the following values:
3899 * @arg @ref LL_DMA_CHANNEL_0
3900 * @arg @ref LL_DMA_CHANNEL_1
3901 * @arg @ref LL_DMA_CHANNEL_2
3902 * @arg @ref LL_DMA_CHANNEL_3
3903 * @arg @ref LL_DMA_CHANNEL_4
3904 * @arg @ref LL_DMA_CHANNEL_5
3905 * @arg @ref LL_DMA_CHANNEL_6
3906 * @arg @ref LL_DMA_CHANNEL_7
3907 * @retval None.
3908 */
3909 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
3910 {
3911 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3912 }
3913
3914 /**
3915 * @brief Clear Channel 0 Block Complete flag.
3916 *
3917 * Register|BitsName
3918 * --------|--------
3919 * CLR_BLK | CLEAR
3920 *
3921 * @param DMAx DMAx instance
3922 * @retval None.
3923 */
3924 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
3925 {
3926 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3927 }
3928
3929 /**
3930 * @brief Clear Channel 1 Block Complete flag.
3931 *
3932 * Register|BitsName
3933 * --------|--------
3934 * CLR_BLK | CLEAR
3935 *
3936 * @param DMAx DMAx instance
3937 * @retval None.
3938 */
3939 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
3940 {
3941 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3942 }
3943
3944 /**
3945 * @brief Clear Channel 2 Block Complete flag.
3946 *
3947 * Register|BitsName
3948 * --------|--------
3949 * CLR_BLK | CLEAR
3950 *
3951 * @param DMAx DMAx instance
3952 * @retval None.
3953 */
3954 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
3955 {
3956 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3957 }
3958
3959 /**
3960 * @brief Clear Channel 3 Block Complete flag.
3961 *
3962 * Register|BitsName
3963 * --------|--------
3964 * CLR_BLK | CLEAR
3965 *
3966 * @param DMAx DMAx instance
3967 * @retval None.
3968 */
3969 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
3970 {
3971 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3972 }
3973
3974 /**
3975 * @brief Clear Channel 4 Block Complete flag.
3976 *
3977 * Register|BitsName
3978 * --------|--------
3979 * CLR_BLK | CLEAR
3980 *
3981 * @param DMAx DMAx instance
3982 * @retval None.
3983 */
3984 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
3985 {
3986 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
3987 }
3988
3989 /**
3990 * @brief Clear Channel 5 Block Complete flag.
3991 *
3992 * Register|BitsName
3993 * --------|--------
3994 * CLR_BLK | CLEAR
3995 *
3996 * @param DMAx DMAx instance
3997 * @retval None.
3998 */
3999 __STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
4000 {
4001 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
4002 }
4003
4004 /**
4005 * @brief Clear Channel 6 Block Cmplete flag.
4006 *
4007 * Register|BitsName
4008 * --------|--------
4009 * CLR_BLK | CLEAR
4010 *
4011 * @param DMAx DMAx instance
4012 * @retval None.
4013 */
4014 __STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
4015 {
4016 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
4017 }
4018
4019 /**
4020 * @brief Clear Channel 7 Block Complete flag.
4021 *
4022 * Register|BitsName
4023 * --------|--------
4024 * CLR_BLK | CLEAR
4025 *
4026 * @param DMAx DMAx instance
4027 * @retval None.
4028 */
4029 __STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
4030 {
4031 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
4032 }
4033
4034 /**
4035 * @brief Clear DMA Channel source transaction Complete flag.
4036 *
4037 * Register|BitsName
4038 * --------|--------
4039 * CLR_SRC_TRN | CLEAR
4040 *
4041 * @param DMAx DMAx instance
4042 * @param channel This parameter can be one of the following values:
4043 * @arg @ref LL_DMA_CHANNEL_0
4044 * @arg @ref LL_DMA_CHANNEL_1
4045 * @arg @ref LL_DMA_CHANNEL_2
4046 * @arg @ref LL_DMA_CHANNEL_3
4047 * @arg @ref LL_DMA_CHANNEL_4
4048 * @arg @ref LL_DMA_CHANNEL_5
4049 * @arg @ref LL_DMA_CHANNEL_6
4050 * @arg @ref LL_DMA_CHANNEL_7
4051 * @retval None.
4052 */
4053 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
4054 {
4055 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
4056 }
4057
4058 /**
4059 * @brief Clear Channel 0 source transaction Complete flag.
4060 *
4061 * Register|BitsName
4062 * --------|--------
4063 * CLR_SRC_TRN | CLEAR
4064 *
4065 * @param DMAx DMAx instance
4066 * @retval None.
4067 */
4068 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
4069 {
4070 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
4071 }
4072
4073 /**
4074 * @brief Clear Channel 1 source transaction Complete flag.
4075 *
4076 * Register|BitsName
4077 * --------|--------
4078 * CLR_SRC_TRN | CLEAR
4079 *
4080 * @param DMAx DMAx instance
4081 * @retval None.
4082 */
4083 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
4084 {
4085 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
4086 }
4087
4088 /**
4089 * @brief Clear Channel 2 source transaction Complete flag.
4090 *
4091 * Register|BitsName
4092 * --------|--------
4093 * CLR_SRC_TRN | CLEAR
4094 *
4095 * @param DMAx DMAx instance
4096 * @retval None.
4097 */
4098 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
4099 {
4100 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
4101 }
4102
4103 /**
4104 * @brief Clear Channel 3 source transaction Complete flag.
4105 *
4106 * Register|BitsName
4107 * --------|--------
4108 * CLR_SRC_TRN | CLEAR
4109 *
4110 * @param DMAx DMAx instance
4111 * @retval None.
4112 */
4113 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
4114 {
4115 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
4116 }
4117
4118 /**
4119 * @brief Clear Channel 4 source transaction Complete flag.
4120 *
4121 * Register|BitsName
4122 * --------|--------
4123 * CLR_SRC_TRN | CLEAR
4124 *
4125 * @param DMAx DMAx instance
4126 * @retval None.
4127 */
4128 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
4129 {
4130 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
4131 }
4132
4133 /**
4134 * @brief Clear Channel 5 source transaction Complete flag.
4135 *
4136 * Register|BitsName
4137 * --------|--------
4138 * CLR_SRC_TRN | CLEAR
4139 *
4140 * @param DMAx DMAx instance
4141 * @retval None.
4142 */
4143 __STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
4144 {
4145 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
4146 }
4147
4148 /**
4149 * @brief Clear Channel 6 source transaction Complete flag.
4150 *
4151 * Register|BitsName
4152 * --------|--------
4153 * CLR_SRC_TRN | CLEAR
4154 *
4155 * @param DMAx DMAx instance
4156 * @retval None.
4157 */
4158 __STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
4159 {
4160 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
4161 }
4162
4163 /**
4164 * @brief Clear Channel 7 source transaction Complete flag.
4165 *
4166 * Register|BitsName
4167 * --------|--------
4168 * CLR_SRC_TRN | CLEAR
4169 *
4170 * @param DMAx DMAx instance
4171 * @retval None.
4172 */
4173 __STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
4174 {
4175 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
4176 }
4177
4178 /**
4179 * @brief Clear DMA Channel destination transaction Complete flag.
4180 *
4181 * Register|BitsName
4182 * --------|--------
4183 * CLR_DST_TRN | CLEAR
4184 *
4185 * @param DMAx DMAx instance
4186 * @param channel This parameter can be one of the following values:
4187 * @arg @ref LL_DMA_CHANNEL_0
4188 * @arg @ref LL_DMA_CHANNEL_1
4189 * @arg @ref LL_DMA_CHANNEL_2
4190 * @arg @ref LL_DMA_CHANNEL_3
4191 * @arg @ref LL_DMA_CHANNEL_4
4192 * @arg @ref LL_DMA_CHANNEL_5
4193 * @arg @ref LL_DMA_CHANNEL_6
4194 * @arg @ref LL_DMA_CHANNEL_7
4195 * @retval None.
4196 */
4197 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
4198 {
4199 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
4200 }
4201
4202 /**
4203 * @brief Clear Channel 0 destination transaction Complete status.
4204 *
4205 * Register|BitsName
4206 * --------|--------
4207 * CLR_DST_TRN | CLEAR
4208 *
4209 * @param DMAx DMAx instance
4210 * @retval None.
4211 */
4212 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
4213 {
4214 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
4215 }
4216
4217 /**
4218 * @brief Clear Channel 1 destination transaction Complete flag.
4219 *
4220 * Register|BitsName
4221 * --------|--------
4222 * CLR_DST_TRN | CLEAR
4223 *
4224 * @param DMAx DMAx instance
4225 * @retval None.
4226 */
4227 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
4228 {
4229 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
4230 }
4231
4232 /**
4233 * @brief Clear Channel 2 destination transaction Complete flag.
4234 *
4235 * Register|BitsName
4236 * --------|--------
4237 * CLR_DST_TRN | CLEAR
4238 *
4239 * @param DMAx DMAx instance
4240 * @retval None.
4241 */
4242 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
4243 {
4244 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
4245 }
4246
4247 /**
4248 * @brief Clear Channel 3 destination transaction Complete flag.
4249 *
4250 * Register|BitsName
4251 * --------|--------
4252 * CLR_DST_TRN | CLEAR
4253 *
4254 * @param DMAx DMAx instance
4255 * @retval None.
4256 */
4257 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
4258 {
4259 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
4260 }
4261
4262 /**
4263 * @brief Clear Channel 4 destination transaction Complete flag.
4264 *
4265 * Register|BitsName
4266 * --------|--------
4267 * CLR_DST_TRN | CLEAR
4268 *
4269 * @param DMAx DMAx instance
4270 * @retval None.
4271 */
4272 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
4273 {
4274 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
4275 }
4276
4277 /**
4278 * @brief Clear Channel 5 destination transaction Complete flag.
4279 *
4280 * Register|BitsName
4281 * --------|--------
4282 * CLR_DST_TRN | CLEAR
4283 *
4284 * @param DMAx DMAx instance
4285 * @retval None.
4286 */
4287 __STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
4288 {
4289 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
4290 }
4291
4292 /**
4293 * @brief Clear Channel 6 destination transaction Complete flag.
4294 *
4295 * Register|BitsName
4296 * --------|--------
4297 * CLR_DST_TRN | CLEAR
4298 *
4299 * @param DMAx DMAx instance
4300 * @retval None.
4301 */
4302 __STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
4303 {
4304 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
4305 }
4306
4307 /**
4308 * @brief Clear Channel 7 destination transaction Complete flag.
4309 *
4310 * Register|BitsName
4311 * --------|--------
4312 * CLR_DST_TRN | CLEAR
4313 *
4314 * @param DMAx DMAx instance
4315 * @retval None.
4316 */
4317 __STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
4318 {
4319 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
4320 }
4321
4322 /**
4323 * @brief Clear DMA Channel error flag.
4324 *
4325 * Register|BitsName
4326 * --------|--------
4327 * CLR_ERR | CLEAR
4328 *
4329 * @param DMAx DMAx instance
4330 * @param channel This parameter can be one of the following values:
4331 * @arg @ref LL_DMA_CHANNEL_0
4332 * @arg @ref LL_DMA_CHANNEL_1
4333 * @arg @ref LL_DMA_CHANNEL_2
4334 * @arg @ref LL_DMA_CHANNEL_3
4335 * @arg @ref LL_DMA_CHANNEL_4
4336 * @arg @ref LL_DMA_CHANNEL_5
4337 * @arg @ref LL_DMA_CHANNEL_6
4338 * @arg @ref LL_DMA_CHANNEL_7
4339 * @retval None.
4340 */
4341 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
4342 {
4343 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
4344 }
4345
4346 /**
4347 * @brief Clear Channel 0 error flag.
4348 *
4349 * Register|BitsName
4350 * --------|--------
4351 * CLR_ERR | CLEAR
4352 *
4353 * @param DMAx DMAx instance
4354 * @retval None.
4355 */
4356 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
4357 {
4358 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
4359 }
4360
4361 /**
4362 * @brief Clear Channel 1 error flag.
4363 *
4364 * Register|BitsName
4365 * --------|--------
4366 * CLR_ERR | CLEAR
4367 *
4368 * @param DMAx DMAx instance
4369 * @retval None.
4370 */
4371 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
4372 {
4373 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
4374 }
4375
4376 /**
4377 * @brief Clear Channel 2 error flag.
4378 *
4379 * Register|BitsName
4380 * --------|--------
4381 * CLR_ERR | CLEAR
4382 *
4383 * @param DMAx DMAx instance
4384 * @retval None.
4385 */
4386 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
4387 {
4388 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
4389 }
4390
4391 /**
4392 * @brief Clear Channel 3 error flag.
4393 *
4394 * Register|BitsName
4395 * --------|--------
4396 * CLR_ERR | CLEAR
4397 *
4398 * @param DMAx DMAx instance
4399 * @retval None.
4400 */
4401 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
4402 {
4403 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4404 }
4405
4406 /**
4407 * @brief Clear Channel 4 error flag.
4408 *
4409 * Register|BitsName
4410 * --------|--------
4411 * CLR_ERR | CLEAR
4412 *
4413 * @param DMAx DMAx instance
4414 * @retval None.
4415 */
4416 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
4417 {
4418 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4419 }
4420
4421 /**
4422 * @brief Clear Channel 5 error flag.
4423 *
4424 * Register|BitsName
4425 * --------|--------
4426 * CLR_ERR | CLEAR
4427 *
4428 * @param DMAx DMAx instance
4429 * @retval None.
4430 */
4431 __STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
4432 {
4433 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4434 }
4435
4436 /**
4437 * @brief Clear Channel 6 error flag.
4438 *
4439 * Register|BitsName
4440 * --------|--------
4441 * CLR_ERR | CLEAR
4442 *
4443 * @param DMAx DMAx instance
4444 * @retval None.
4445 */
4446 __STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
4447 {
4448 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4449 }
4450
4451 /**
4452 * @brief Clear Channel 7 error flag.
4453 *
4454 * Register|BitsName
4455 * --------|--------
4456 * CLR_ERR | CLEAR
4457 *
4458 * @param DMAx DMAx instance
4459 * @retval None.
4460 */
4461 __STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
4462 {
4463 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4464 }
4465
4466 /** @} */
4467
4468 /** @defgroup DMA_LL_EF_IT_Management IT_Management
4469 * @{
4470 */
4471
4472 /**
4473 * @brief Enable Transfer Complete interrupt.
4474 *
4475 * Register|BitsName
4476 * --------|--------
4477 * MASK_TFR | TFR_WE&TFR
4478 *
4479 * @param DMAx DMAx instance
4480 * @param channel This parameter can be one of the following values:
4481 * @arg @ref LL_DMA_CHANNEL_0
4482 * @arg @ref LL_DMA_CHANNEL_1
4483 * @arg @ref LL_DMA_CHANNEL_2
4484 * @arg @ref LL_DMA_CHANNEL_3
4485 * @arg @ref LL_DMA_CHANNEL_4
4486 * @arg @ref LL_DMA_CHANNEL_5
4487 * @arg @ref LL_DMA_CHANNEL_6
4488 * @arg @ref LL_DMA_CHANNEL_7
4489 * @retval None
4490 */
4491 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4492 {
4493 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4494 }
4495
4496 /**
4497 * @brief Enable Block Complete interrupt.
4498 *
4499 * Register|BitsName
4500 * --------|--------
4501 * MASK_BLK | BLK_WE&BLK
4502 *
4503 * @param DMAx DMAx instance
4504 * @param channel This parameter can be one of the following values:
4505 * @arg @ref LL_DMA_CHANNEL_0
4506 * @arg @ref LL_DMA_CHANNEL_1
4507 * @arg @ref LL_DMA_CHANNEL_2
4508 * @arg @ref LL_DMA_CHANNEL_3
4509 * @arg @ref LL_DMA_CHANNEL_4
4510 * @arg @ref LL_DMA_CHANNEL_5
4511 * @arg @ref LL_DMA_CHANNEL_6
4512 * @arg @ref LL_DMA_CHANNEL_7
4513 * @retval None
4514 */
4515 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4516 {
4517 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4518 }
4519
4520 /**
4521 * @brief Enable source transaction Complete interrupt.
4522 *
4523 * Register|BitsName
4524 * --------|--------
4525 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
4526 *
4527 * @param DMAx DMAx instance
4528 * @param channel This parameter can be one of the following values:
4529 * @arg @ref LL_DMA_CHANNEL_0
4530 * @arg @ref LL_DMA_CHANNEL_1
4531 * @arg @ref LL_DMA_CHANNEL_2
4532 * @arg @ref LL_DMA_CHANNEL_3
4533 * @arg @ref LL_DMA_CHANNEL_4
4534 * @arg @ref LL_DMA_CHANNEL_5
4535 * @arg @ref LL_DMA_CHANNEL_6
4536 * @arg @ref LL_DMA_CHANNEL_7
4537 * @retval None
4538 */
4539 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4540 {
4541 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4542 }
4543
4544 /**
4545 * @brief Enable destination transaction Complete interrupt.
4546 *
4547 * Register|BitsName
4548 * --------|--------
4549 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
4550 *
4551 * @param DMAx DMAx instance
4552 * @param channel This parameter can be one of the following values:
4553 * @arg @ref LL_DMA_CHANNEL_0
4554 * @arg @ref LL_DMA_CHANNEL_1
4555 * @arg @ref LL_DMA_CHANNEL_2
4556 * @arg @ref LL_DMA_CHANNEL_3
4557 * @arg @ref LL_DMA_CHANNEL_4
4558 * @arg @ref LL_DMA_CHANNEL_5
4559 * @arg @ref LL_DMA_CHANNEL_6
4560 * @arg @ref LL_DMA_CHANNEL_7
4561 * @retval None
4562 */
4563 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4564 {
4565 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4566 }
4567
4568 /**
4569 * @brief Enable error interrupt.
4570 *
4571 * Register|BitsName
4572 * --------|--------
4573 * MASK_ERR | ERR_WE&ERR
4574 *
4575 * @param DMAx DMAx instance
4576 * @param channel This parameter can be one of the following values:
4577 * @arg @ref LL_DMA_CHANNEL_0
4578 * @arg @ref LL_DMA_CHANNEL_1
4579 * @arg @ref LL_DMA_CHANNEL_2
4580 * @arg @ref LL_DMA_CHANNEL_3
4581 * @arg @ref LL_DMA_CHANNEL_4
4582 * @arg @ref LL_DMA_CHANNEL_5
4583 * @arg @ref LL_DMA_CHANNEL_6
4584 * @arg @ref LL_DMA_CHANNEL_7
4585 * @retval None
4586 */
4587 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4588 {
4589 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4590 }
4591
4592 /**
4593 * @brief Disable Transfer Complete interrupt.
4594 *
4595 * Register|BitsName
4596 * --------|--------
4597 * MASK_TFR | TFR_WE&TFR
4598 *
4599 * @param DMAx DMAx instance
4600 * @param channel This parameter can be one of the following values:
4601 * @arg @ref LL_DMA_CHANNEL_0
4602 * @arg @ref LL_DMA_CHANNEL_1
4603 * @arg @ref LL_DMA_CHANNEL_2
4604 * @arg @ref LL_DMA_CHANNEL_3
4605 * @arg @ref LL_DMA_CHANNEL_4
4606 * @arg @ref LL_DMA_CHANNEL_5
4607 * @arg @ref LL_DMA_CHANNEL_6
4608 * @arg @ref LL_DMA_CHANNEL_7
4609 * @retval None
4610 */
4611 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4612 {
4613 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4614 }
4615
4616 /**
4617 * @brief Disable Block Complete interrupt.
4618 *
4619 * Register|BitsName
4620 * --------|--------
4621 * MASK_BLK | BLK_WE&BLK
4622 *
4623 * @param DMAx DMAx instance
4624 * @param channel This parameter can be one of the following values:
4625 * @arg @ref LL_DMA_CHANNEL_0
4626 * @arg @ref LL_DMA_CHANNEL_1
4627 * @arg @ref LL_DMA_CHANNEL_2
4628 * @arg @ref LL_DMA_CHANNEL_3
4629 * @arg @ref LL_DMA_CHANNEL_4
4630 * @arg @ref LL_DMA_CHANNEL_5
4631 * @arg @ref LL_DMA_CHANNEL_6
4632 * @arg @ref LL_DMA_CHANNEL_7
4633 * @retval None
4634 */
4635 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4636 {
4637 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4638 }
4639
4640 /**
4641 * @brief Disable source transaction Complete interrupt.
4642 *
4643 * Register|BitsName
4644 * --------|--------
4645 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
4646 *
4647 * @param DMAx DMAx instance
4648 * @param channel This parameter can be one of the following values:
4649 * @arg @ref LL_DMA_CHANNEL_0
4650 * @arg @ref LL_DMA_CHANNEL_1
4651 * @arg @ref LL_DMA_CHANNEL_2
4652 * @arg @ref LL_DMA_CHANNEL_3
4653 * @arg @ref LL_DMA_CHANNEL_4
4654 * @arg @ref LL_DMA_CHANNEL_5
4655 * @arg @ref LL_DMA_CHANNEL_6
4656 * @arg @ref LL_DMA_CHANNEL_7
4657 * @retval None
4658 */
4659 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4660 {
4661 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4662 }
4663
4664 /**
4665 * @brief Disable destination transaction Complete interrupt.
4666 *
4667 * Register|BitsName
4668 * --------|--------
4669 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
4670 *
4671 * @param DMAx DMAx instance
4672 * @param channel This parameter can be one of the following values:
4673 * @arg @ref LL_DMA_CHANNEL_0
4674 * @arg @ref LL_DMA_CHANNEL_1
4675 * @arg @ref LL_DMA_CHANNEL_2
4676 * @arg @ref LL_DMA_CHANNEL_3
4677 * @arg @ref LL_DMA_CHANNEL_4
4678 * @arg @ref LL_DMA_CHANNEL_5
4679 * @arg @ref LL_DMA_CHANNEL_6
4680 * @arg @ref LL_DMA_CHANNEL_7
4681 * @retval None
4682 */
4683 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4684 {
4685 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4686 }
4687
4688 /**
4689 * @brief Disable error interrupt.
4690 *
4691 * Register|BitsName
4692 * --------|--------
4693 * MASK_ERR | ERR_WE&ERR
4694 *
4695 * @param DMAx DMAx instance
4696 * @param channel This parameter can be one of the following values:
4697 * @arg @ref LL_DMA_CHANNEL_0
4698 * @arg @ref LL_DMA_CHANNEL_1
4699 * @arg @ref LL_DMA_CHANNEL_2
4700 * @arg @ref LL_DMA_CHANNEL_3
4701 * @arg @ref LL_DMA_CHANNEL_4
4702 * @arg @ref LL_DMA_CHANNEL_5
4703 * @arg @ref LL_DMA_CHANNEL_6
4704 * @arg @ref LL_DMA_CHANNEL_7
4705 * @retval None
4706 */
4707 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
4708 {
4709 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4710 }
4711
4712 /**
4713 * @brief Check if DMA Transfer interrupt is enabled or disabled.
4714 *
4715 * Register|BitsName
4716 * --------|--------
4717 * MASK_TFR | TFR
4718 *
4719 * @param DMAx DMA instance.
4720 * @param channel This parameter can be one of the following values:
4721 * @arg @ref LL_DMA_CHANNEL_0
4722 * @arg @ref LL_DMA_CHANNEL_1
4723 * @arg @ref LL_DMA_CHANNEL_2
4724 * @arg @ref LL_DMA_CHANNEL_3
4725 * @arg @ref LL_DMA_CHANNEL_4
4726 * @arg @ref LL_DMA_CHANNEL_5
4727 * @arg @ref LL_DMA_CHANNEL_6
4728 * @arg @ref LL_DMA_CHANNEL_7
4729 * @retval State of bit (1 or 0).
4730 */
4731 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4732 {
4733 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4734 }
4735
4736 /**
4737 * @brief Check if DMA block interrupt is enabled or disabled.
4738 *
4739 * Register|BitsName
4740 * --------|--------
4741 * MASK_BLK | BLK_WE&BLK
4742 *
4743 * @param DMAx DMA instance.
4744 * @param channel This parameter can be one of the following values:
4745 * @arg @ref LL_DMA_CHANNEL_0
4746 * @arg @ref LL_DMA_CHANNEL_1
4747 * @arg @ref LL_DMA_CHANNEL_2
4748 * @arg @ref LL_DMA_CHANNEL_3
4749 * @arg @ref LL_DMA_CHANNEL_4
4750 * @arg @ref LL_DMA_CHANNEL_5
4751 * @arg @ref LL_DMA_CHANNEL_6
4752 * @arg @ref LL_DMA_CHANNEL_7
4753 * @retval State of bit (1 or 0).
4754 */
4755 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4756 {
4757 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4758 }
4759
4760 /**
4761 * @brief Check if DMA source transaction interrupt is enabled or disabled.
4762 *
4763 * Register|BitsName
4764 * --------|--------
4765 * MASK_SRC_TRN | SRC_TRN
4766 *
4767 * @param DMAx DMA instance.
4768 * @param channel This parameter can be one of the following values:
4769 * @arg @ref LL_DMA_CHANNEL_0
4770 * @arg @ref LL_DMA_CHANNEL_1
4771 * @arg @ref LL_DMA_CHANNEL_2
4772 * @arg @ref LL_DMA_CHANNEL_3
4773 * @arg @ref LL_DMA_CHANNEL_4
4774 * @arg @ref LL_DMA_CHANNEL_5
4775 * @arg @ref LL_DMA_CHANNEL_6
4776 * @arg @ref LL_DMA_CHANNEL_7
4777 * @retval State of bit (1 or 0).
4778 */
4779 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4780 {
4781 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4782 }
4783
4784 /**
4785 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
4786 *
4787 * Register|BitsName
4788 * --------|--------
4789 * MASK_DST_TRN | DST_TRN
4790 *
4791 * @param DMAx DMA instance.
4792 * @param channel This parameter can be one of the following values:
4793 * @arg @ref LL_DMA_CHANNEL_0
4794 * @arg @ref LL_DMA_CHANNEL_1
4795 * @arg @ref LL_DMA_CHANNEL_2
4796 * @arg @ref LL_DMA_CHANNEL_3
4797 * @arg @ref LL_DMA_CHANNEL_4
4798 * @arg @ref LL_DMA_CHANNEL_5
4799 * @arg @ref LL_DMA_CHANNEL_6
4800 * @arg @ref LL_DMA_CHANNEL_7
4801 * @retval State of bit (1 or 0).
4802 */
4803 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4804 {
4805 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4806 }
4807
4808 /**
4809 * @brief Check if DMA error interrupt is enabled or disabled.
4810 *
4811 * Register|BitsName
4812 * --------|--------
4813 * MASK_ERR | ERR
4814 *
4815 * @param DMAx DMA instance.
4816 * @param channel This parameter can be one of the following values:
4817 * @arg @ref LL_DMA_CHANNEL_0
4818 * @arg @ref LL_DMA_CHANNEL_1
4819 * @arg @ref LL_DMA_CHANNEL_2
4820 * @arg @ref LL_DMA_CHANNEL_3
4821 * @arg @ref LL_DMA_CHANNEL_4
4822 * @arg @ref LL_DMA_CHANNEL_5
4823 * @arg @ref LL_DMA_CHANNEL_6
4824 * @arg @ref LL_DMA_CHANNEL_7
4825 * @retval State of bit (1 or 0).
4826 */
4827 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4828 {
4829 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4830 }
4831
4832 /**
4833 * @brief Enable DMA channel interrupt.
4834 *
4835 * Register|BitsName
4836 * --------|--------
4837 * CTLL | INI_EN
4838 *
4839 * @param DMAx DMA instance.
4840 * @param channel This parameter can be one of the following values:
4841 * @arg @ref LL_DMA_CHANNEL_0
4842 * @arg @ref LL_DMA_CHANNEL_1
4843 * @arg @ref LL_DMA_CHANNEL_2
4844 * @arg @ref LL_DMA_CHANNEL_3
4845 * @arg @ref LL_DMA_CHANNEL_4
4846 * @arg @ref LL_DMA_CHANNEL_5
4847 * @arg @ref LL_DMA_CHANNEL_6
4848 * @arg @ref LL_DMA_CHANNEL_7
4849 * @retval None
4850 */
4851 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
4852 {
4853 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4854 }
4855
4856 /**
4857 * @brief Disable DMA channel interrupt.
4858 *
4859 * Register|BitsName
4860 * --------|--------
4861 * CTLL | INI_EN
4862 *
4863 * @param DMAx DMA instance.
4864 * @param channel This parameter can be one of the following values:
4865 * @arg @ref LL_DMA_CHANNEL_0
4866 * @arg @ref LL_DMA_CHANNEL_1
4867 * @arg @ref LL_DMA_CHANNEL_2
4868 * @arg @ref LL_DMA_CHANNEL_3
4869 * @arg @ref LL_DMA_CHANNEL_4
4870 * @arg @ref LL_DMA_CHANNEL_5
4871 * @arg @ref LL_DMA_CHANNEL_6
4872 * @arg @ref LL_DMA_CHANNEL_7
4873 * @retval None
4874 */
4875 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
4876 {
4877 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
4878 }
4879
4880 /**
4881 * @brief Check if DMA interrupt is enabled or disabled.
4882 *
4883 * Register|BitsName
4884 * --------|--------
4885 * CTL_LO | INT_EN
4886 *
4887 * @param DMAx DMA instance.
4888 * @param channel This parameter can be one of the following values:
4889 * @arg @ref LL_DMA_CHANNEL_0
4890 * @arg @ref LL_DMA_CHANNEL_1
4891 * @arg @ref LL_DMA_CHANNEL_2
4892 * @arg @ref LL_DMA_CHANNEL_3
4893 * @arg @ref LL_DMA_CHANNEL_4
4894 * @arg @ref LL_DMA_CHANNEL_5
4895 * @arg @ref LL_DMA_CHANNEL_6
4896 * @arg @ref LL_DMA_CHANNEL_7
4897 * @retval State of bit (1 or 0).
4898 */
4899 __STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
4900 {
4901 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
4902 }
4903
4904 /** @} */
4905
4906 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
4907 * @{
4908 */
4909
4910 /**
4911 * @brief De-initialize the DMA registers to their default reset values.
4912 * @param DMAx DMAx instance
4913 * @param channel This parameter can be one of the following values:
4914 * @arg @ref LL_DMA_CHANNEL_0
4915 * @arg @ref LL_DMA_CHANNEL_1
4916 * @arg @ref LL_DMA_CHANNEL_2
4917 * @arg @ref LL_DMA_CHANNEL_3
4918 * @arg @ref LL_DMA_CHANNEL_4
4919 * @arg @ref LL_DMA_CHANNEL_5
4920 * @arg @ref LL_DMA_CHANNEL_6
4921 * @arg @ref LL_DMA_CHANNEL_7
4922 * @retval An error_status_t enumeration value:
4923 * - SUCCESS: DMA registers are de-initialized
4924 * - ERROR: DMA registers are not de-initialized
4925 */
4926 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
4927
4928 /**
4929 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
4930 * @param DMAx DMAx instance
4931 * @param channel This parameter can be one of the following values:
4932 * @arg @ref LL_DMA_CHANNEL_0
4933 * @arg @ref LL_DMA_CHANNEL_1
4934 * @arg @ref LL_DMA_CHANNEL_2
4935 * @arg @ref LL_DMA_CHANNEL_3
4936 * @arg @ref LL_DMA_CHANNEL_4
4937 * @arg @ref LL_DMA_CHANNEL_5
4938 * @arg @ref LL_DMA_CHANNEL_6
4939 * @arg @ref LL_DMA_CHANNEL_7
4940 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
4941 * @retval An error_status_t enumeration value:
4942 * - SUCCESS: DMA registers are initialized
4943 * - ERROR: Not applicable
4944 */
4945 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
4946
4947 /**
4948 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
4949 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
4950 * whose fields will be set to default values.
4951 * @retval None
4952 */
4953 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
4954
4955 /**
4956 * @brief Initialize the DMA HS choice according to the specified parameters.
4957 * @param DMAx DMAx instance
4958 * @param src_peripheral src_peripheral
4959 * @param dst_peripheral dst_peripheral
4960 * @retval An error_status_t enumeration value:
4961 * - SUCCESS: DMA hs choice are initialized
4962 * - ERROR: Error DMA instance
4963 */
4964 error_status_t ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral);
4965 /** @} */
4966
4967 /** @} */
4968
4969 #endif /* DMA */
4970
4971 #ifdef __cplusplus
4972 }
4973 #endif
4974
4975 #endif /* __GR55xx_LL_DMA_H__ */
4976
4977 /** @} */
4978
4979 /** @} */
4980
4981 /** @} */
ll_dma_clear_flag_err
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: gr55xx_ll_dma.h:4341
ll_dma_get_source_burst_length
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1606
_ll_dma_init::mode
uint32_t mode
Specifies the Single block or Multi-block operation mode.
Definition: gr55xx_ll_dma.h:92
ll_dma_get_mode
__STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
Get DMA mode circular or normal.
Definition: gr55xx_ll_dma.h:811
_ll_dma_init::src_address
uint32_t src_address
Specifies the Source base address for DMA transfer.
Definition: gr55xx_ll_dma.h:78
ll_dma_get_source_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: gr55xx_ll_dma.h:1386
ll_dma_get_channel_priority_level
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: gr55xx_ll_dma.h:1726
ll_dma_disable_it_err
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: gr55xx_ll_dma.h:4707
ll_dma_clear_flag_srct3
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4113
ll_dma_is_active_flag_dstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3477
ll_dma_clear_flag_tfr0
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:3780
ll_dma_clear_flag_tfr3
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:3825
ll_dma_get_dst_scatter_en
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel)
Get destination scatter enable.
Definition: gr55xx_ll_dma.h:1278
ll_dma_clear_flag_blk3
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: gr55xx_ll_dma.h:3969
ll_dma_clear_flag_err7
__STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
Clear Channel 7 error flag.
Definition: gr55xx_ll_dma.h:4461
ll_dma_disable_channel
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: gr55xx_ll_dma.h:529
ll_dma_is_active_flag_tfr4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:3120
ll_dma_set_max_amba_burst
__STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
Set Maximum AMBA Burst Length.
Definition: gr55xx_ll_dma.h:837
ll_dma_is_active_flag_dstt3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3537
ll_dma_clear_flag_dstt3
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4257
ll_dma_is_active_flag_blk0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: gr55xx_ll_dma.h:3204
ll_dma_init
error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
ll_dma_is_active_flag_err0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3636
ll_dma_clear_flag_srct
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4053
ll_dma_disable
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: gr55xx_ll_dma.h:464
ll_dma_is_active_flag_err1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3651
ll_dma_clear_flag_err4
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: gr55xx_ll_dma.h:4416
ll_dma_get_source_width
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: gr55xx_ll_dma.h:1496
LL_DMA_DST_STAT_UPDATE_DISABLE
#define LL_DMA_DST_STAT_UPDATE_DISABLE
Source Status Update Enable.
Definition: gr55xx_ll_dma.h:213
ll_dma_clear_flag_srct1
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4083
ll_dma_set_dstatar
__STATIC_INLINE void ll_dma_set_dstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t dstatar)
Set deatination status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1043
ll_dma_get_source_peripheral
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2271
ll_dma_config_transfer
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: gr55xx_ll_dma.h:693
ll_dma_is_active_flag_srct0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3348
ll_dma_get_destination_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: gr55xx_ll_dma.h:1441
ll_dma_set_m2m_dst_address
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1970
ll_dma_deinit
error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
ll_dma_set_llp_dst_en
__STATIC_INLINE void ll_dma_set_llp_dst_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_dst_en)
Set destination LLP enable.
Definition: gr55xx_ll_dma.h:1146
ll_dma_is_empty_fifo
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: gr55xx_ll_dma.h:654
ll_dma_clear_flag_srct4
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4128
ll_dma_disable_it_dstt
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4683
ll_dma_clear_flag_blk1
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: gr55xx_ll_dma.h:3939
ll_dma_get_llp_src_en
__STATIC_INLINE uint32_t ll_dma_get_llp_src_en(dma_regs_t *DMAx, uint32_t channel)
Get source LLP enable.
Definition: gr55xx_ll_dma.h:1225
ll_dma_clear_flag_tfr
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:3765
ll_dma_disable_it_srct
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4659
ll_dma_set_destination_width
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: gr55xx_ll_dma.h:1524
ll_dma_clear_flag_dstt4
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4272
ll_dma_get_dstatar
__STATIC_INLINE uint32_t ll_dma_get_dstatar(dma_regs_t *DMAx, uint32_t channel)
Get deatination status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1068
ll_dma_is_enabled_channel
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: gr55xx_ll_dma.h:555
ll_dma_get_m2m_src_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1996
ll_dma_get_destination_burst_length
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1661
ll_dma_get_sstatar
__STATIC_INLINE uint32_t ll_dma_get_sstatar(dma_regs_t *DMAx, uint32_t channel)
Get source status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1017
ll_dma_clear_flag_blk6
__STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
Clear Channel 6 Block Cmplete flag.
Definition: gr55xx_ll_dma.h:4014
ll_dma_is_active_flag_dstt7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
Indicate the status of Channel 7 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3597
ll_dma_clear_flag_err0
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: gr55xx_ll_dma.h:4356
ll_dma_clear_flag_dstt5
__STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
Clear Channel 5 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4287
ll_dma_clear_flag_err3
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: gr55xx_ll_dma.h:4401
ll_dma_set_sstat
__STATIC_INLINE void ll_dma_set_sstat(dma_regs_t *DMAx, uint32_t channel, uint32_t sstat)
Set source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:889
ll_dma_is_enable_it_dstt
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4803
ll_dma_clear_flag_tfr1
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:3795
ll_dma_req_src_burst_transaction
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2662
ll_dma_set_source_peripheral
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2248
ll_dma_set_block_size
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: gr55xx_ll_dma.h:1752
ll_dma_get_src_gather_sgi
__STATIC_INLINE uint32_t ll_dma_get_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel)
Get source gather interval.
Definition: gr55xx_ll_dma.h:2459
ll_dma_set_source_address
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: gr55xx_ll_dma.h:1843
ll_dma_is_active_flag_rdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: gr55xx_ll_dma.h:2997
ll_dma_set_dst_scatter_dsi
__STATIC_INLINE void ll_dma_set_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsi)
Set destination scatter interval.
Definition: gr55xx_ll_dma.h:2536
ll_dma_is_active_flag_dstt0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3492
ll_dma_dst_stat_update_is_enable
__STATIC_INLINE uint32_t ll_dma_dst_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
Check if Destination Status Update Enable.
Definition: gr55xx_ll_dma.h:2165
ll_dma_get_m2m_dst_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:2021
ll_dma_is_active_flag_dstt4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3552
ll_dma_is_active_flag_srct7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
Indicate the status of Channel 7 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3453
ll_dma_config_address
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: gr55xx_ll_dma.h:1812
ll_dma_is_active_flag_tfr5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
Indicate the status of Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:3135
ll_dma_is_active_flag_srct5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
Indicate the status of Channel 5 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3423
ll_dma_req_dst_last_single_transaction
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:2792
ll_dma_disable_it_tfr
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4611
ll_dma_is_active_flag_dstt5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
Indicate the status of Channel 5 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3567
ll_dma_get_dst_scatter_dsi
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel)
Get Set destination scatter interval.
Definition: gr55xx_ll_dma.h:2561
ll_dma_set_destination_increment_mode
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: gr55xx_ll_dma.h:1414
ll_dma_is_active_flag_blk1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: gr55xx_ll_dma.h:3219
ll_dma_is_enable_it_blk
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4755
ll_dma_disable_it
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4875
ll_dma_is_active_flag_srct1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3363
_ll_dma_init
LL DMA init Structure definition.
Definition: gr55xx_ll_dma.h:77
ll_dma_clear_flag_dstt6
__STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
Clear Channel 6 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4302
ll_dma_get_dstat
__STATIC_INLINE uint32_t ll_dma_get_dstat(dma_regs_t *DMAx, uint32_t channel)
Get deatination status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:966
ll_dma_is_active_flag_err3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3681
ll_dma_is_active_flag_err5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
Indicate the status of Channel 5 error flag.
Definition: gr55xx_ll_dma.h:3711
ll_dma_struct_init
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
ll_dma_is_active_flag_tfr1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:3075
ll_dma_get_destination_address
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: gr55xx_ll_dma.h:1916
ll_dma_is_active_flag_err
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3621
ll_dma_disable_dst_stat_update
__STATIC_INLINE void ll_dma_disable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
Disable Destination Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2141
ll_dma_set_llp_src_en
__STATIC_INLINE void ll_dma_set_llp_src_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_src_en)
Set source LLP enable.
Definition: gr55xx_ll_dma.h:1199
ll_dma_req_src_single_transaction
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: gr55xx_ll_dma.h:2637
ll_dma_set_llp_loc
__STATIC_INLINE void ll_dma_set_llp_loc(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_loc)
Set LLP loc.
Definition: gr55xx_ll_dma.h:1094
ll_dma_clear_flag_tfr2
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:3810
ll_dma_is_enable_it_tfr
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4731
ll_dma_is_active_flag_srct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: gr55xx_ll_dma.h:3333
ll_dma_clear_flag_srct0
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4068
ll_dma_is_active_flag_dstt2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3522
ll_dma_is_active_flag_blk2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: gr55xx_ll_dma.h:3234
ll_dma_enable_it_tfr
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4491
ll_dma_req_dst_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2766
ll_dma_set_sstatar
__STATIC_INLINE void ll_dma_set_sstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t sstatar)
Set source status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:992
ll_dma_enable_channel
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: gr55xx_ll_dma.h:505
ll_dma_set_src_gather_en
__STATIC_INLINE void ll_dma_set_src_gather_en(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_en)
Set source gather enable.
Definition: gr55xx_ll_dma.h:1305
ll_dma_clear_flag_blk7
__STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
Clear Channel 7 Block Complete flag.
Definition: gr55xx_ll_dma.h:4029
ll_dma_set_source_burst_length
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1579
ll_dma_is_active_flag_dstt1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3507
ll_dma_is_active_flag_srct4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3408
ll_dma_is_active_flag_tfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:3045
ll_dma_is_active_flag_srct2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3378
ll_dma_get_max_amba_burst
__STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
Get source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:863
ll_dma_is_active_flag_gsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2871
ll_dma_get_sstat
__STATIC_INLINE uint32_t ll_dma_get_sstat(dma_regs_t *DMAx, uint32_t channel)
Get source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:915
ll_dma_is_active_flag_err2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3666
ll_dma_is_active_flag_tfr7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
Indicate the status of Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:3165
_ll_dma_init::block_size
uint32_t block_size
Specifies the number of data to transfer, in data unit.
Definition: gr55xx_ll_dma.h:119
ll_dma_get_source_address
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: gr55xx_ll_dma.h:1892
ll_dma_select_handshaking
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: gr55xx_ll_dma.h:2407
ll_dma_is_active_flag_blk7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
Indicate the status of Channel 7 block complete flag.
Definition: gr55xx_ll_dma.h:3309
_ll_dma_init::src_peripheral
uint32_t src_peripheral
Specifies the Source peripheral type.
Definition: gr55xx_ll_dma.h:125
LL_DMA_DST_STAT_UPDATE_ENABLE
#define LL_DMA_DST_STAT_UPDATE_ENABLE
Source Status Update Enable.
Definition: gr55xx_ll_dma.h:212
ll_dma_is_active_flag_blk4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: gr55xx_ll_dma.h:3264
ll_dma_clear_flag_tfr5
__STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
Clear Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:3855
ll_dma_set_destination_peripheral
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2354
ll_dma_get_destination_width
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: gr55xx_ll_dma.h:1551
ll_dma_enable_src_stat_update
__STATIC_INLINE void ll_dma_enable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
Enable Source Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2045
_ll_dma_init::dst_data_width
uint32_t dst_data_width
Specifies the Destination transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:114
ll_dma_is_active_flag_gerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: gr55xx_ll_dma.h:2901
ll_dma_set_source_increment_mode
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: gr55xx_ll_dma.h:1359
ll_dma_is_active_flag_gtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: gr55xx_ll_dma.h:2841
ll_dma_set_destination_address
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: gr55xx_ll_dma.h:1868
ll_dma_req_src_last_single_transaction
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:2688
ll_dma_is_active_flag_err7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
Indicate the status of Channel 7 error flag.
Definition: gr55xx_ll_dma.h:3741
ll_dma_is_active_flag_blk6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
Indicate the status of Channel 6 block complete flag.
Definition: gr55xx_ll_dma.h:3294
ll_dma_clear_flag_err5
__STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
Clear Channel 5 error flag.
Definition: gr55xx_ll_dma.h:4431
ll_dma_resume_channel
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: gr55xx_ll_dma.h:606
ll_dma_clear_flag_dstt0
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: gr55xx_ll_dma.h:4212
_ll_dma_init::src_data_width
uint32_t src_data_width
Specifies the Souce transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:109
ll_dma_clear_flag_err2
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: gr55xx_ll_dma.h:4386
ll_dma_set_mode
__STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
Set DMA mode Single block or Multi block.
Definition: gr55xx_ll_dma.h:782
ll_dma_set_m2m_src_address
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1942
ll_dma_is_active_flag_srct6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
Indicate the status of Channel 6 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3438
ll_dma_enable_it_blk
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4515
_ll_dma_init::direction
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
Definition: gr55xx_ll_dma.h:86
ll_dma_clear_flag_tfr6
__STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
Clear Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:3870
ll_dma_clear_flag_dstt
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4197
ll_dma_enable
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: gr55xx_ll_dma.h:445
ll_dma_clear_flag_blk0
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: gr55xx_ll_dma.h:3924
ll_dma_clear_flag_dstt2
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4242
_ll_dma_init::dst_peripheral
uint32_t dst_peripheral
Specifies the Destination peripheral type.
Definition: gr55xx_ll_dma.h:130
ll_dma_set_dst_scatter_en
__STATIC_INLINE void ll_dma_set_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_en)
Set destination scatter enable.
Definition: gr55xx_ll_dma.h:1252
ll_dma_disable_it_blk
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4635
ll_dma_src_stat_update_is_enable
__STATIC_INLINE uint32_t ll_dma_src_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
Check if Source Status Update Enable.
Definition: gr55xx_ll_dma.h:2093
_ll_dma_init::priority
uint32_t priority
Specifies the channel priority level.
Definition: gr55xx_ll_dma.h:135
ll_dma_is_active_flag_err4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: gr55xx_ll_dma.h:3696
ll_dma_is_active_flag_gdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2886
ll_dma_req_dst_single_transaction
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: gr55xx_ll_dma.h:2741
ll_dma_get_data_transfer_direction
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:751
ll_dma_enable_it_err
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: gr55xx_ll_dma.h:4587
ll_dma_req_dst_last_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2819
ll_dma_set_src_gather_sgc
__STATIC_INLINE void ll_dma_set_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgc)
Set source gather count.
Definition: gr55xx_ll_dma.h:2485
ll_dma_set_src_gather_sgi
__STATIC_INLINE void ll_dma_set_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgi)
Set source gather interval.
Definition: gr55xx_ll_dma.h:2434
ll_dma_clear_flag_dstt7
__STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
Clear Channel 7 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4317
ll_dma_get_src_gather_en
__STATIC_INLINE uint32_t ll_dma_get_src_gather_en(dma_regs_t *DMAx, uint32_t channel)
Get source gather enable.
Definition: gr55xx_ll_dma.h:1331
ll_dma_is_active_flag_err6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
Indicate the status of Channel 6 error flag.
Definition: gr55xx_ll_dma.h:3726
ll_dma_clear_flag_tfr7
__STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
Clear Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:3885
ll_dma_is_active_flag_rerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: gr55xx_ll_dma.h:3021
_ll_dma_init::dst_increment_mode
uint32_t dst_increment_mode
Specifies whether the Destination address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:104
ll_dma_clear_flag_tfr4
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:3840
ll_dma_clear_flag_srct2
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4098
LL_DMA_SRC_STAT_UPDATE_ENABLE
#define LL_DMA_SRC_STAT_UPDATE_ENABLE
Destination Status Update Enable.
Definition: gr55xx_ll_dma.h:205
ll_dma_is_enable_it_srct
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4779
_ll_dma_init::dst_address
uint32_t dst_address
Specifies the Destination base address for DMA transfer.
Definition: gr55xx_ll_dma.h:82
ll_dma_clear_flag_srct6
__STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
Clear Channel 6 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4158
ll_dma_get_dst_scatter_dsc
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel)
Get destination scatter count.
Definition: gr55xx_ll_dma.h:2612
ll_dma_clear_flag_err6
__STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
Clear Channel 6 error flag.
Definition: gr55xx_ll_dma.h:4446
ll_dma_clear_flag_srct5
__STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
Clear Channel 5 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4143
ll_dma_enable_dst_stat_update
__STATIC_INLINE void ll_dma_enable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
Enable Destination Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2117
ll_dma_is_active_flag_tfr2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:3090
ll_dma_is_active_flag_tfr6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
Indicate the status of Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:3150
ll_dma_is_enable
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: gr55xx_ll_dma.h:479
ll_dma_get_destination_peripheral
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2377
LL_DMA_SRC_STAT_UPDATE_DISABLE
#define LL_DMA_SRC_STAT_UPDATE_DISABLE
Destination Status Update Enable.
Definition: gr55xx_ll_dma.h:206
ll_dma_clear_flag_blk2
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: gr55xx_ll_dma.h:3954
ll_dma_set_destination_burst_length
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1634
ll_dma_req_src_last_burst_transaction
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2715
ll_dma_get_llp_dst_en
__STATIC_INLINE uint32_t ll_dma_get_llp_dst_en(dma_regs_t *DMAx, uint32_t channel)
Get destination LLP enable.
Definition: gr55xx_ll_dma.h:1172
ll_dma_enable_it_dstt
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4563
_ll_dma_init::src_increment_mode
uint32_t src_increment_mode
Specifies whether the Source address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:99
ll_dma_set_data_transfer_direction
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:723
ll_dma_set_dst_scatter_dsc
__STATIC_INLINE void ll_dma_set_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsc)
Set destination scatter count.
Definition: gr55xx_ll_dma.h:2587
ll_dma_is_active_flag_tfr0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:3060
ll_dma_clear_flag_srct7
__STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
Clear Channel 7 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4173
ll_dma_get_llp_loc
__STATIC_INLINE uint32_t ll_dma_get_llp_loc(dma_regs_t *DMAx, uint32_t channel)
Get LLP loc.
Definition: gr55xx_ll_dma.h:1119
ll_dma_is_active_flag_tfr3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:3105
ll_dma_set_dstat
__STATIC_INLINE void ll_dma_set_dstat(dma_regs_t *DMAx, uint32_t channel, uint32_t dstat)
Set deatination status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:941
ll_dma_is_suspended
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: gr55xx_ll_dma.h:630
ll_dma_init_t
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
ll_dma_clear_flag_blk5
__STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
Clear Channel 5 Block Complete flag.
Definition: gr55xx_ll_dma.h:3999
ll_dma_set_source_width
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: gr55xx_ll_dma.h:1469
ll_dma_is_active_flag_rsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: gr55xx_ll_dma.h:2973
ll_dma_clear_flag_blk4
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: gr55xx_ll_dma.h:3984
ll_dma_is_active_flag_blk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:3189
ll_dma_is_active_flag_rtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: gr55xx_ll_dma.h:2925
ll_dma_is_active_flag_dstt6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
Indicate the status of Channel 6 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3582
ll_dma_suspend_channel
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: gr55xx_ll_dma.h:581
ll_dma_get_src_gather_sgc
__STATIC_INLINE uint32_t ll_dma_get_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel)
Get source gather count.
Definition: gr55xx_ll_dma.h:2510
ll_dma_clear_flag_dstt1
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4227
ll_dma_clear_flag_blk
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:3909
ll_dma_is_active_flag_blk5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
Indicate the status of Channel 5 block complete flag.
Definition: gr55xx_ll_dma.h:3279
ll_dma_enable_it
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4851
ll_dma_is_active_flag_blk3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: gr55xx_ll_dma.h:3249
ll_dma_hs_choice
error_status_t ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral)
Initialize the DMA HS choice according to the specified parameters.
ll_dma_is_active_flag_rblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: gr55xx_ll_dma.h:2949
ll_dma_set_channel_priority_level
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: gr55xx_ll_dma.h:1694
ll_dma_get_block_size
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: gr55xx_ll_dma.h:1778
ll_dma_is_active_flag_gblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: gr55xx_ll_dma.h:2856
ll_dma_enable_it_srct
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4539
ll_dma_is_enable_it_err
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4827
ll_dma_clear_flag_err1
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: gr55xx_ll_dma.h:4371
ll_dma_disable_src_stat_update
__STATIC_INLINE void ll_dma_disable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
Disable Source Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2069
ll_dma_is_enable_it
__STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
Check if DMA interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4899
ll_dma_is_active_flag_srct3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3393