gr55xx_efuse_layout.h
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1 #ifndef __GR55XX_EFUSE_LAYOUT_H__
2 #define __GR55XX_EFUSE_LAYOUT_H__
3
4 #include<stdio.h>
5 #include<stdint.h>
6
7 #define EFUSE_BT_ADDR_SIZE (6)
8 #define EFUSE_CHIP_UID_SIZE (16)
9 #define EFUSE_CHIP_ID_SIZE (6)
10 #define EFUSE_PRODUCT_ID_SIZE (2)
11 #define FW_PUBLIC_KEY_HASH_SIZE (16)
12 #define ROOT_PUBLIC_KEY_HASH_SIZE (16)
13
14 #define EFUSE_TRIM_PATTERN (0x4744)
15
16 #define EFUSE_IO_LDO_SEL_MASK (0x01)
17 #define EFUSE_IO_LDO_BYPASS_MASK (0x02)
18
19 /* Make sure it is same with the one in \boot_security\BL0\inc\efuse.h. */
20 typedef struct _usb_trim_t
21 {
22 uint16_t usb_rg_xcvr_rtrimp : 4;
23 uint16_t usb_rg_xcvr_rtrimn: 4;
24 uint16_t usb_rg_ldo33_vesl : 4;
25 uint16_t usb_rh_ldo33_bias: 4;
26 } __attribute__ ((packed)) usb_trim_t;
27
28 typedef struct _efuse_trim0_t
29 {
30 uint8_t chip_uid[EFUSE_CHIP_UID_SIZE];
31 uint8_t ate_version;
32 uint8_t reserved0[2];
33 uint8_t io_ldo_sel;
34 uint8_t bt_addr[EFUSE_BT_ADDR_SIZE];
35 uint16_t xo_offset;
36 uint16_t pattern;
37 uint16_t trim_sum;
38 uint16_t hw_version;
39 uint16_t chip_id;
40 uint16_t package;
41 uint16_t flash_size;
42 uint16_t ram_size;
43 uint8_t reserved1[2];
44 uint8_t dcdc_vout1p15;
45 uint8_t dcdc_vout1p05;
46 uint8_t dig_ldo_0p9;
47 uint8_t dig_ldo_1p05;
48 uint8_t io_ldo_1p8;
49 uint8_t io_ldo_3p0;
50 uint8_t reserved2[4];
51 uint8_t tx_power;
52 uint8_t rssi_cali;
53 uint8_t lp_gain_offset_2m;
54 uint8_t reserved3;
55 usb_trim_t usb_trim;
56 } __attribute__ ((packed)) efuse_trim0_t;
57
58
59 typedef struct _efuse_exflash_timing_t
60 {
61 uint8_t flash_tVSL; /* tVSL: VCC(min.) to device operation. min 10us, unit: 10us */
62 uint8_t flash_tESL; /* tESL: Erase suspend latency. max 30us, unit: 5us */
63 uint8_t flash_tPSL; /* tPSL: Program suspend latency. max 30us, unit: 5us */
64 uint8_t flash_tPRS; /* tPRS: Latency between program resume and next suspend. max 30us, unit: 5us */
65 uint8_t flash_tERS; /* tERS: Latency between erase resume and next suspend. max 30us, unit: 5us */
66 uint8_t flash_tDP; /* tDP: CS# High to Deep Power-down Mode. unit: 5us */
67 uint8_t flash_tRES2; /* tRES2: CS# High To Standby Mode With Electronic Signature Read max 8us, unit: 5us */
68 uint8_t flash_tRDINT; /* tRDINT: Read status register interval after write opertion. Uint: 5us */
69 } __attribute__ ((packed)) efuse_exflash_timing_t;
70
71
72 typedef struct _efuse_sadc_trim_t
73 {
74 uint16_t offset_int_0p8;
75 uint16_t slope_int_0p8;
76 uint16_t offset_int_1p2;
77 uint16_t slope_int_1p2;
78 uint16_t offset_int_1p6;
79 uint16_t slope_int_1p6;
80 uint16_t offset_ext_1p0;
81 uint16_t slope_ext_1p0;
82 uint16_t temp;
83 } __attribute__ ((packed)) efuse_sadc_trim_t;
84
85 typedef struct _efuse_comp_trim_t
86 {
87 uint16_t slope_int_no1;
88 uint16_t slope_int_no2;
89 } __attribute__ ((packed)) efuse_comp_trim_t;
90
91 typedef struct _efuse_trim1_t
92 {
93 efuse_sadc_trim_t sadc_trim;
94 efuse_exflash_timing_t flash_timing;
95 efuse_comp_trim_t comp_trim;
96 uint16_t temp_ref;
97 uint8_t reserved[28];
98 } __attribute__ ((packed)) efuse_trim1_t;
99
100
101 typedef struct {
102 /* Configurations 4Byte*/
103 uint32_t isp_uart_bypass : 1; // 1: Not Support UART ISP Process, 0: Support UART ISP Process
104 uint32_t isp_usb_bypass : 1; // 1: Not Support USB ISP Process, 0: Support USB ISP Process
105 uint32_t isp_jlink_bypass : 1; // 1: Not Support JLINK ISP Process, 0: Support JLINK ISP Process
106 uint32_t enc_boot_system_clk : 3; // 0: XO-16M, 1: PLL-64M, 2: PLL-96M, 3: PLL-48M, 4: PLL-24M, 5: PLL-16M, 6: PLL-32M
107 uint32_t enc_boot_flash_clk : 3; // 0: 16MHz, 1: 48MHz, 2: 32MHz, 3: 24MHz, 4:64MHz
108 uint32_t enc_boot_xip_read_cmd : 8; // 0x03, 0x0B, 0x3B, 0xBB, 0x6B, 0xEB
109 uint32_t memory_power_size : 1; // 0: 512KB, 1: 288KB
110 uint32_t reserved : 14;
111 } __attribute__ ((packed)) config_t;
112
113 typedef struct {
114 /* Configurations 4Byte*/
115 config_t config;
116
117 uint16_t swd_disable;
118 uint16_t enc_mode;
119 uint32_t crc32;
120
121 uint8_t chip_id[EFUSE_CHIP_ID_SIZE];
122 uint8_t product_id[EFUSE_PRODUCT_ID_SIZE];
123 uint8_t fw_public_key_hash[FW_PUBLIC_KEY_HASH_SIZE];
124 uint8_t root_public_key_hash[ROOT_PUBLIC_KEY_HASH_SIZE];
125 } __attribute__ ((packed)) bl_efuse_info_t;
126
127 #endif //__GR55XX_EFUSE_LAYOUT_H__
_efuse_trim0_t::chip_id
uint16_t chip_id
Definition: gr55xx_efuse_layout.h:39
_efuse_trim0_t::dig_ldo_0p9
uint8_t dig_ldo_0p9
Definition: gr55xx_efuse_layout.h:46
EFUSE_CHIP_UID_SIZE
#define EFUSE_CHIP_UID_SIZE
Definition: gr55xx_efuse_layout.h:8
__attribute__::enc_boot_system_clk
uint32_t enc_boot_system_clk
Definition: gr55xx_efuse_layout.h:106
_efuse_trim0_t::chip_uid
uint8_t chip_uid[EFUSE_CHIP_UID_SIZE]
Definition: gr55xx_efuse_layout.h:30
EFUSE_PRODUCT_ID_SIZE
#define EFUSE_PRODUCT_ID_SIZE
Definition: gr55xx_efuse_layout.h:10
__attribute__::swd_disable
uint16_t swd_disable
Definition: gr55xx_efuse_layout.h:117
_efuse_sadc_trim_t::offset_int_0p8
uint16_t offset_int_0p8
Definition: gr55xx_efuse_layout.h:74
_efuse_trim0_t::tx_power
uint8_t tx_power
Definition: gr55xx_efuse_layout.h:51
_efuse_trim0_t::flash_size
uint16_t flash_size
Definition: gr55xx_efuse_layout.h:41
_efuse_trim0_t::dig_ldo_1p05
uint8_t dig_ldo_1p05
Definition: gr55xx_efuse_layout.h:47
_efuse_exflash_timing_t::flash_tRES2
uint8_t flash_tRES2
Definition: gr55xx_efuse_layout.h:67
_efuse_sadc_trim_t::slope_int_1p2
uint16_t slope_int_1p2
Definition: gr55xx_efuse_layout.h:77
_efuse_exflash_timing_t::flash_tERS
uint8_t flash_tERS
Definition: gr55xx_efuse_layout.h:65
chip_id
uint16_t chip_id
Definition: gr55xx_efuse_layout.h:9
_efuse_trim0_t::io_ldo_sel
uint8_t io_ldo_sel
Definition: gr55xx_efuse_layout.h:33
__attribute__::reserved
uint32_t reserved
Definition: gr55xx_efuse_layout.h:110
_efuse_trim0_t::dcdc_vout1p05
uint8_t dcdc_vout1p05
Definition: gr55xx_efuse_layout.h:45
EFUSE_CHIP_ID_SIZE
#define EFUSE_CHIP_ID_SIZE
Definition: gr55xx_efuse_layout.h:9
_efuse_sadc_trim_t::temp
uint16_t temp
Definition: gr55xx_efuse_layout.h:82
_efuse_trim0_t::io_ldo_1p8
uint8_t io_ldo_1p8
Definition: gr55xx_efuse_layout.h:48
_efuse_trim0_t::rssi_cali
uint8_t rssi_cali
Definition: gr55xx_efuse_layout.h:52
FW_PUBLIC_KEY_HASH_SIZE
#define FW_PUBLIC_KEY_HASH_SIZE
Definition: gr55xx_efuse_layout.h:11
_efuse_trim0_t::hw_version
uint16_t hw_version
Definition: gr55xx_efuse_layout.h:38
__attribute__::memory_power_size
uint32_t memory_power_size
Definition: gr55xx_efuse_layout.h:109
__attribute__::config
config_t config
Definition: gr55xx_efuse_layout.h:115
_efuse_trim1_t::sadc_trim
efuse_sadc_trim_t sadc_trim
Definition: gr55xx_efuse_layout.h:93
_efuse_sadc_trim_t
Definition: gr55xx_efuse_layout.h:73
_efuse_trim0_t::xo_offset
uint16_t xo_offset
Definition: gr55xx_efuse_layout.h:35
_efuse_exflash_timing_t
Definition: gr55xx_efuse_layout.h:60
__attribute__::isp_usb_bypass
uint32_t isp_usb_bypass
Definition: gr55xx_efuse_layout.h:104
_efuse_sadc_trim_t::offset_int_1p6
uint16_t offset_int_1p6
Definition: gr55xx_efuse_layout.h:78
_efuse_trim0_t::bt_addr
uint8_t bt_addr[EFUSE_BT_ADDR_SIZE]
Definition: gr55xx_efuse_layout.h:34
_efuse_exflash_timing_t::flash_tPRS
uint8_t flash_tPRS
Definition: gr55xx_efuse_layout.h:64
_efuse_trim0_t::package
uint16_t package
Definition: gr55xx_efuse_layout.h:40
_efuse_trim0_t::ram_size
uint16_t ram_size
Definition: gr55xx_efuse_layout.h:42
_efuse_trim1_t::reserved
uint8_t reserved[28]
Definition: gr55xx_efuse_layout.h:97
_efuse_sadc_trim_t::slope_int_1p6
uint16_t slope_int_1p6
Definition: gr55xx_efuse_layout.h:79
_efuse_trim0_t::ate_version
uint8_t ate_version
Definition: gr55xx_efuse_layout.h:31
_efuse_trim1_t
Definition: gr55xx_efuse_layout.h:92
_efuse_trim0_t
Definition: gr55xx_efuse_layout.h:29
EFUSE_BT_ADDR_SIZE
#define EFUSE_BT_ADDR_SIZE
Definition: gr55xx_efuse_layout.h:7
_efuse_comp_trim_t::slope_int_no1
uint16_t slope_int_no1
Definition: gr55xx_efuse_layout.h:87
ROOT_PUBLIC_KEY_HASH_SIZE
#define ROOT_PUBLIC_KEY_HASH_SIZE
Definition: gr55xx_efuse_layout.h:12
__attribute__
typedef __attribute__
_efuse_trim0_t::io_ldo_3p0
uint8_t io_ldo_3p0
Definition: gr55xx_efuse_layout.h:49
_efuse_exflash_timing_t::flash_tRDINT
uint8_t flash_tRDINT
Definition: gr55xx_efuse_layout.h:68
_efuse_comp_trim_t
Definition: gr55xx_efuse_layout.h:86
_usb_trim_t::usb_rg_xcvr_rtrimp
uint16_t usb_rg_xcvr_rtrimp
Definition: gr55xx_efuse_layout.h:22
_efuse_trim0_t::pattern
uint16_t pattern
Definition: gr55xx_efuse_layout.h:36
_efuse_sadc_trim_t::offset_ext_1p0
uint16_t offset_ext_1p0
Definition: gr55xx_efuse_layout.h:80
_efuse_trim0_t::reserved1
uint8_t reserved1[2]
Definition: gr55xx_efuse_layout.h:43
_efuse_sadc_trim_t::offset_int_1p2
uint16_t offset_int_1p2
Definition: gr55xx_efuse_layout.h:76
_efuse_trim0_t::trim_sum
uint16_t trim_sum
Definition: gr55xx_efuse_layout.h:37
__attribute__::enc_mode
uint16_t enc_mode
Definition: gr55xx_efuse_layout.h:118
_efuse_trim0_t::dcdc_vout1p15
uint8_t dcdc_vout1p15
Definition: gr55xx_efuse_layout.h:44
_efuse_sadc_trim_t::slope_int_0p8
uint16_t slope_int_0p8
Definition: gr55xx_efuse_layout.h:75
_efuse_exflash_timing_t::flash_tESL
uint8_t flash_tESL
Definition: gr55xx_efuse_layout.h:62
__attribute__::isp_uart_bypass
uint32_t isp_uart_bypass
Definition: gr55xx_efuse_layout.h:103
__attribute__::enc_boot_xip_read_cmd
uint32_t enc_boot_xip_read_cmd
Definition: gr55xx_efuse_layout.h:108
_efuse_trim0_t::reserved0
uint8_t reserved0[2]
Definition: gr55xx_efuse_layout.h:32
_usb_trim_t::usb_rg_xcvr_rtrimn
uint16_t usb_rg_xcvr_rtrimn
Definition: gr55xx_efuse_layout.h:23
_efuse_exflash_timing_t::flash_tVSL
uint8_t flash_tVSL
Definition: gr55xx_efuse_layout.h:61
_efuse_trim0_t::usb_trim
usb_trim_t usb_trim
Definition: gr55xx_efuse_layout.h:55
__attribute__::crc32
uint32_t crc32
Definition: gr55xx_efuse_layout.h:119
_usb_trim_t::usb_rh_ldo33_bias
uint16_t usb_rh_ldo33_bias
Definition: gr55xx_efuse_layout.h:25
_efuse_comp_trim_t::slope_int_no2
uint16_t slope_int_no2
Definition: gr55xx_efuse_layout.h:88
_efuse_sadc_trim_t::slope_ext_1p0
uint16_t slope_ext_1p0
Definition: gr55xx_efuse_layout.h:81
_efuse_trim0_t::lp_gain_offset_2m
uint8_t lp_gain_offset_2m
Definition: gr55xx_efuse_layout.h:53
_efuse_trim0_t::reserved3
uint8_t reserved3
Definition: gr55xx_efuse_layout.h:54
__attribute__::enc_boot_flash_clk
uint32_t enc_boot_flash_clk
Definition: gr55xx_efuse_layout.h:107
_usb_trim_t::usb_rg_ldo33_vesl
uint16_t usb_rg_ldo33_vesl
Definition: gr55xx_efuse_layout.h:24
_efuse_trim1_t::comp_trim
efuse_comp_trim_t comp_trim
Definition: gr55xx_efuse_layout.h:95
_efuse_trim1_t::temp_ref
uint16_t temp_ref
Definition: gr55xx_efuse_layout.h:96
_efuse_exflash_timing_t::flash_tDP
uint8_t flash_tDP
Definition: gr55xx_efuse_layout.h:66
_efuse_exflash_timing_t::flash_tPSL
uint8_t flash_tPSL
Definition: gr55xx_efuse_layout.h:63
_usb_trim_t
Definition: gr55xx_efuse_layout.h:21
_efuse_trim0_t::reserved2
uint8_t reserved2[4]
Definition: gr55xx_efuse_layout.h:50
__attribute__::isp_jlink_bypass
uint32_t isp_jlink_bypass
Definition: gr55xx_efuse_layout.h:105
_efuse_trim1_t::flash_timing
efuse_exflash_timing_t flash_timing
Definition: gr55xx_efuse_layout.h:94