gr55xx_ll_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_GPIO GPIO
47 * @brief GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPIO_H__
53 #define __GR55XX_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (GPIO0) || defined (GPIO1) || defined(MCU_RET)
63
64 /** @defgroup GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup GPIO_LL_ES_INIT GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL GPIO init configuration definition
75 */
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin; /*!< Specifies the GPIO pins to be GPIO_InitStructured.
79 This parameter can be any value of @ref GPIO_LL_EC_PIN */
80
81 uint32_t mode; /*!< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref GPIO_LL_EC_MODE.
83
84 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_mode(). */
85
86 uint32_t pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref GPIO_LL_EC_PULL.
88
89 GPIO HW configuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref GPIO_LL_EC_MUX.
93
94 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
95 ll_gpio_set_mux_pin_0_7() and ll_gpio_set_mux_pin_8_15(). */
96
97 uint32_t trigger; /*!< Specifies the trigger signal active edge.
98 This parameter can be a value of @ref GPIO_LL_EC_TRIGGER. */
99
100 } ll_gpio_init_t;
101
102 /** @} */
103
104 /** @} */
105
106 /**
107 * @defgroup GPIO_LL_MACRO Defines
108 * @{
109 */
110
111 /* Exported constants --------------------------------------------------------*/
112 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
113 * @{
114 */
115
116 /** @defgroup GPIO_LL_EC_PIN PIN
117 * @{
118 */
119 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U) /*!< Select pin 0 */
120 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U) /*!< Select pin 1 */
121 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U) /*!< Select pin 2 */
122 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U) /*!< Select pin 3 */
123 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U) /*!< Select pin 4 */
124 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U) /*!< Select pin 5 */
125 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U) /*!< Select pin 6 */
126 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U) /*!< Select pin 7 */
127 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U) /*!< Select pin 8 */
128 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U) /*!< Select pin 9 */
129 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U) /*!< Select pin 10 */
130 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U) /*!< Select pin 11 */
131 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U) /*!< Select pin 12 */
132 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U) /*!< Select pin 13 */
133 #define LL_GPIO_PIN_14 ((uint32_t)0x4000U) /*!< Select pin 14 */
134 #define LL_GPIO_PIN_15 ((uint32_t)0x8000U) /*!< Select pin 15 */
135 #define LL_GPIO_PIN_ALL ((uint32_t)0xFFFFU) /*!< Select all pins */
136 /** @} */
137
138 /** @defgroup GPIO_LL_EC_MODE Mode
139 * @{
140 */
141 #define LL_GPIO_MODE_INPUT ((uint32_t)0x0U) /*!< Select input mode */
142 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /*!< Select output mode */
143 #define LL_GPIO_MODE_MUX ((uint32_t)0x2U) /*!< Select mux peripheral mode */
144 /** @} */
145
146 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
147 * @{
148 */
149 #define LL_GPIO_PULL_NO LL_GPIO_RE_N /*!< Select I/O no pull */
150 #define LL_GPIO_PULL_UP LL_GPIO_RTYP /*!< Select I/O pull up */
151 #define LL_GPIO_PULL_DOWN ((uint32_t)0x0U) /*!< Select I/O pull down */
152 /** @} */
153
154 /** @defgroup GPIO_LL_EC_MUX Alternate Function
155 * @{
156 */
157 #define LL_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
158 #define LL_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
159 #define LL_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
160 #define LL_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
161 #define LL_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
162 #define LL_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
163 #define LL_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
164 #define LL_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
165 #define LL_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
166 /** @} */
167
168 /** @defgroup GPIO_LL_EC_TRIGGER Interrupt Trigger
169 * @{
170 */
171 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /*!< No Trigger Mode */
172 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /*!< Trigger Rising Mode */
173 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /*!< Trigger Falling Mode */
174 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /*!< Trigger High Mode */
175 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /*!< Trigger Low Mode */
176 #define LL_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /*!< Trigger Both Rising and Falling Mode */
177
178 /** @} */
179
180 /** @defgroup GPIO_LL_REG_ADDR Address of GPIOx Registers
181 * @attention x=0/1/2
182 * @{
183 */
184 #define GPIO_DATA_ADDR(x) (GPIO##x##_BASE+0x00) /*!< GPIOx_DATA_ADDR */
185 #define GPIO_DATAOUT_ADDR(x) (GPIO##x##_BASE+0x04) /*!< GPIOx_DATAOUT_ADDR */
186 #define GPIO_OUTENSET_ADDR(x) (GPIO##x##_BASE+0x10) /*!< GPIOx_OUTENSET_ADDR */
187 #define GPIO_OUTENCLR_ADDR(x) (GPIO##x##_BASE+0x14) /*!< GPIOx_OUTENCLR_ADDR */
188 #define GPIO_ALTFUNCSET_ADDR(x) (GPIO##x##_BASE+0x18) /*!< GPIOx_ALTFUNCSET_ADDR */
189 #define GPIO_ALTFUNCCLR_ADDR(x) (GPIO##x##_BASE+0x1c) /*!< GPIOx_ALTFUNCCLR_ADDR */
190 #define GPIO_INTENSET_ADDR(x) (GPIO##x##_BASE+0x20) /*!< GPIOx_INTENSET_ADDR */
191 #define GPIO_INTENCLR_ADDR(x) (GPIO##x##_BASE+0x24) /*!< GPIOx_INTENCLR_ADDR */
192 #define GPIO_INTTYPESET_ADDR(x) (GPIO##x##_BASE+0x28) /*!< GPIOx_INTTYPESET_ADDR */
193 #define GPIO_INTTYPECLR_ADDR(x) (GPIO##x##_BASE+0x2c) /*!< GPIOx_INTTYPECLR_ADDR */
194 #define GPIO_INTPOLSET_ADDR(x) (GPIO##x##_BASE+0x30) /*!< GPIOx_INTPOLSET_ADDR */
195 #define GPIO_INTPOLCLR_ADDR(x) (GPIO##x##_BASE+0x34) /*!< GPIOx_INTPOLCLR_ADDR */
196 #define GPIO_INTSTAT_ADDR(x) (GPIO##x##_BASE+0x38) /*!< GPIOx_INTSTAT_ADDR */
197 #define GPIO_INTDBESET_ADDR(x) (GPIO##x##_BASE+0x40) /*!< GPIOx_INTDBESET_ADDR */
198 #define GPIO_INTDBECLR_ADDR(x) (GPIO##x##_BASE+0x44) /*!< GPIOx_INTDBECLR_ADDR */
199 /** @} */
200
201 /** @defgroup GPIO_LL_BITBAND_SET Set nth bit for GPIOx register 0 or 1
202 * @attention x=0/1/2,0<=n<=31
203 * @{
204 */
205 #define SET_GPIO_DATA(x,n) BIT_ADDR(GPIO_DATA_ADDR(x),n) /*!< BITBAND GPIOx_DATA_ADDR */
206 #define SET_GPIO_DATAOUT(x,n) BIT_ADDR(GPIO_DATAOUT_ADDR(x),n) /*!< BITBAND GPIOx_DATAOUT_ADDR */
207 #define SET_GPIO_OUTENSET(x,n) BIT_ADDR(GPIO_OUTENSET_ADDR(x),n) /*!< BITBAND GPIOx_OUTENSET_ADDR */
208 #define SET_GPIO_OUTENCLR(x,n) BIT_ADDR(GPIO_OUTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_OUTENCLR_ADDR */
209 #define SET_GPIO_ALTFUNCSET(x,n) BIT_ADDR(GPIO_ALTFUNCSET_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCSET_ADDR */
210 #define SET_GPIO_ALTFUNCCLR(x,n) BIT_ADDR(GPIO_ALTFUNCCLR_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCCLR_ADDR */
211 #define SET_GPIO_INTENSET(x,n) BIT_ADDR(GPIO_INTENSET_ADDR(x),n) /*!< BITBAND GPIOx_INTENSET_ADDR */
212 #define SET_GPIO_INTENCLR(x,n) BIT_ADDR(GPIO_INTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTENCLR_ADDR */
213 #define SET_GPIO_INTTYPESET(x,n) BIT_ADDR(GPIO_INTTYPESET_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPESET_ADDR */
214 #define SET_GPIO_INTTYPECLR(x,n) BIT_ADDR(GPIO_INTTYPECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPECLR_ADDR */
215 #define SET_GPIO_INTPOLSET(x,n) BIT_ADDR(GPIO_INTPOLSET_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLSET_ADDR */
216 #define SET_GPIO_INTPOLCLR(x,n) BIT_ADDR(GPIO_INTPOLCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLCLR_ADDR */
217 #define SET_GPIO_INTSTAT(x,n) BIT_ADDR(GPIO_INTSTAT_ADDR(x),n) /*!< BITBAND GPIOx_INTSTAT_ADDR */
218 #define SET_GPIO_INTDBESET(x,n) BIT_ADDR(GPIO_INTDBESET_ADDR(x),n) /*!< BITBAND GPIOx_INTDBESET_ADDR */
219 #define SET_GPIO_INTDBECLR(x,n) BIT_ADDR(GPIO_INTDBECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTDBECLR_ADDR */
220 /** @} */
221
222 /** @defgroup GPIO_LL_EC_DEFAULT_CONFIG InitStrcut default configuration
223 * @{
224 */
225
226 /**
227 * @brief LL GPIO InitStrcut default configuration
228 */
229 #define LL_GPIO_DEFAULT_CONFIG \
230 { \
231 .pin = LL_GPIO_PIN_ALL, \
232 .mode = LL_GPIO_MODE_INPUT, \
233 .pull = LL_GPIO_PULL_DOWN, \
234 .mux = LL_GPIO_MUX_7, \
235 .trigger = LL_GPIO_TRIGGER_NONE, \
236 }
237 /** @} */
238
239 /** @} */
240
241 /* Exported macro ------------------------------------------------------------*/
242 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
243 * @{
244 */
245
246 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
247 * @{
248 */
249
250 /**
251 * @brief Write a value in GPIO register
252 * @param __instance__ GPIO instance
253 * @param __REG__ Register to be written
254 * @param __VALUE__ Value to be written in the register
255 * @retval None
256 */
257 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
258
259 /**
260 * @brief Read a value in GPIO register
261 * @param __instance__ GPIO instance
262 * @param __REG__ Register to be read
263 * @retval Register value
264 */
265 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
266
267 /** @} */
268
269 /** @} */
270
271 /* Private types -------------------------------------------------------------*/
272 /* Private variables ---------------------------------------------------------*/
273 /* Private constants ---------------------------------------------------------*/
274 /* Private macros ------------------------------------------------------------*/
275 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
276 * @{
277 */
278
279 /** @defgroup GPIO_LL_PM_RESISTOR Resistor Enable
280 * @{
281 */
282 #define LL_GPIO_RE_N_Pos 0 /**< Resistor Enable bits position */
283 #define LL_GPIO_RE_N_Msk (0x1U << LL_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
284 #define LL_GPIO_RE_N LL_GPIO_RE_N_Msk /**< Resistor Enable bits */
285 /** @} */
286
287 /** @defgroup GPIO_LL_PM_RESISTOR_TYPE Resistor Type
288 * @{
289 */
290 #define LL_GPIO_RTYP_Pos 1 /**< Resistor Type bits position */
291 #define LL_GPIO_RTYP_Msk (0x1U << LL_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
292 #define LL_GPIO_RTYP LL_GPIO_RTYP_Msk /**< Resistor Type bits */
293 /** @} */
294
295 /** @} */
296
297 /** @} */
298
299 /* Exported functions --------------------------------------------------------*/
300 /** @defgroup GPIO_LL_DRIVER_FUNCTIONS Functions
301 * @{
302 */
303
304 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
305 * @{
306 */
307
308 /**
309 * @brief Set several pins to input/output mode on dedicated port.
310 *
311 * Register|BitsName
312 * --------|--------
313 * OUTENSET | OUTENSET
314 * OUTENCLR | OUTENCLR
315 *
316 * @param GPIOx GPIO Port
317 * @param pin_mask This parameter can be a combination of the following values:
318 * @arg @ref LL_GPIO_PIN_0
319 * @arg @ref LL_GPIO_PIN_1
320 * @arg @ref LL_GPIO_PIN_2
321 * @arg @ref LL_GPIO_PIN_3
322 * @arg @ref LL_GPIO_PIN_4
323 * @arg @ref LL_GPIO_PIN_5
324 * @arg @ref LL_GPIO_PIN_6
325 * @arg @ref LL_GPIO_PIN_7
326 * @arg @ref LL_GPIO_PIN_8
327 * @arg @ref LL_GPIO_PIN_9
328 * @arg @ref LL_GPIO_PIN_10
329 * @arg @ref LL_GPIO_PIN_11
330 * @arg @ref LL_GPIO_PIN_12
331 * @arg @ref LL_GPIO_PIN_13
332 * @arg @ref LL_GPIO_PIN_14
333 * @arg @ref LL_GPIO_PIN_15
334 * @arg @ref LL_GPIO_PIN_ALL
335 * @param mode This parameter can be one of the following values:
336 * @arg @ref LL_GPIO_MODE_INPUT
337 * @arg @ref LL_GPIO_MODE_OUTPUT
338 * @arg @ref LL_GPIO_MODE_MUX
339 * @retval None
340 */
341 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
342 {
343 if (mode == LL_GPIO_MODE_OUTPUT)
344 {
345 WRITE_REG(GPIOx->OUTENSET, pin_mask);
346 if(GPIO2 == GPIOx)
347 {
348 SET_BITS(MCU_RET->DPAD_IE_N_BUS_1, pin_mask);
349 }
350 else
351 {
352 pin_mask <<= ((GPIOx == GPIO0) ? 0 : 16);
353 SET_BITS(MCU_RET->DPAD_IE_N_BUS_0, pin_mask);
354 }
355 }
356 else if((mode == LL_GPIO_MODE_INPUT) || (mode == LL_GPIO_MODE_MUX))
357 {
358 WRITE_REG(GPIOx->OUTENCLR, pin_mask);
359 if(GPIO2 == GPIOx)
360 {
361 CLEAR_BITS(MCU_RET->DPAD_IE_N_BUS_1, pin_mask);
362 }
363 else
364 {
365 pin_mask <<= ((GPIOx == GPIO0) ? 0 : 16);
366 CLEAR_BITS(MCU_RET->DPAD_IE_N_BUS_0, pin_mask);
367 }
368 }
369 }
370
371 /**
372 * @brief Return gpio mode for a dedicated pin on dedicated port.
373 * @note I/O mode can be Input mode, General purpose output.
374 * @note Warning: only one pin can be passed as parameter.
375 *
376 * Register|BitsName
377 * --------|--------
378 * OUTENSET | OUTENSET
379 *
380 * @param GPIOx GPIO Port
381 * @param pin This parameter can be one of the following values:
382 * @arg @ref LL_GPIO_PIN_0
383 * @arg @ref LL_GPIO_PIN_1
384 * @arg @ref LL_GPIO_PIN_2
385 * @arg @ref LL_GPIO_PIN_3
386 * @arg @ref LL_GPIO_PIN_4
387 * @arg @ref LL_GPIO_PIN_5
388 * @arg @ref LL_GPIO_PIN_6
389 * @arg @ref LL_GPIO_PIN_7
390 * @arg @ref LL_GPIO_PIN_8
391 * @arg @ref LL_GPIO_PIN_9
392 * @arg @ref LL_GPIO_PIN_10
393 * @arg @ref LL_GPIO_PIN_11
394 * @arg @ref LL_GPIO_PIN_12
395 * @arg @ref LL_GPIO_PIN_13
396 * @arg @ref LL_GPIO_PIN_14
397 * @arg @ref LL_GPIO_PIN_15
398 * @retval Returned value can be one of the following values:
399 * @arg @ref LL_GPIO_MODE_INPUT
400 * @arg @ref LL_GPIO_MODE_OUTPUT
401 */
402 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
403 {
404 return (uint32_t)(READ_BITS(GPIOx->OUTENSET, pin) != RESET);
405 }
406
407 /**
408 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
409 *
410 * Register|BitsName
411 * --------|--------
412 * DPAD_RE_N_BUS | RE_N
413 * DPAD_RTYP_BUS | RTYP
414 *
415 * @param GPIOx GPIO Port
416 * @param pin_mask This parameter can be a combination of the following values:
417 * @arg @ref LL_GPIO_PIN_0
418 * @arg @ref LL_GPIO_PIN_1
419 * @arg @ref LL_GPIO_PIN_2
420 * @arg @ref LL_GPIO_PIN_3
421 * @arg @ref LL_GPIO_PIN_4
422 * @arg @ref LL_GPIO_PIN_5
423 * @arg @ref LL_GPIO_PIN_6
424 * @arg @ref LL_GPIO_PIN_7
425 * @arg @ref LL_GPIO_PIN_8
426 * @arg @ref LL_GPIO_PIN_9
427 * @arg @ref LL_GPIO_PIN_10
428 * @arg @ref LL_GPIO_PIN_11
429 * @arg @ref LL_GPIO_PIN_12
430 * @arg @ref LL_GPIO_PIN_13
431 * @arg @ref LL_GPIO_PIN_14
432 * @arg @ref LL_GPIO_PIN_15
433 * @param pull This parameter can be one of the following values:
434 * @arg @ref LL_GPIO_PULL_NO
435 * @arg @ref LL_GPIO_PULL_UP
436 * @arg @ref LL_GPIO_PULL_DOWN
437 * @retval None
438 */
439 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
440 {
441 /* Get pin mask in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
442 if(GPIO2 == GPIOx)
443 {
444 MODIFY_REG(MCU_RET->DPAD_RTYP_BUS_1, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
445 MODIFY_REG(MCU_RET->DPAD_RE_N_BUS_1, pin_mask, (pull == LL_GPIO_PULL_NO) ? pin_mask : 0x0000U);
446 }
447 else
448 {
449 pin_mask <<= ((GPIOx == GPIO0) ? 0 : 16);
450 MODIFY_REG(MCU_RET->DPAD_RTYP_BUS_0, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
451 MODIFY_REG(MCU_RET->DPAD_RE_N_BUS_0, pin_mask, (pull == LL_GPIO_PULL_NO) ? pin_mask : 0x0000U);
452 }
453 }
454
455 /**
456 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
457 * @note Warning: only one pin can be passed as parameter.
458 *
459 * Register|BitsName
460 * --------|--------
461 * DPAD_RE_N_BUS | RE_N
462 * DPAD_RTYP_BUS | RTYP
463 *
464 * @param GPIOx GPIO Port
465 * @param pin This parameter can be one of the following values:
466 * @arg @ref LL_GPIO_PIN_0
467 * @arg @ref LL_GPIO_PIN_1
468 * @arg @ref LL_GPIO_PIN_2
469 * @arg @ref LL_GPIO_PIN_3
470 * @arg @ref LL_GPIO_PIN_4
471 * @arg @ref LL_GPIO_PIN_5
472 * @arg @ref LL_GPIO_PIN_6
473 * @arg @ref LL_GPIO_PIN_7
474 * @arg @ref LL_GPIO_PIN_8
475 * @arg @ref LL_GPIO_PIN_9
476 * @arg @ref LL_GPIO_PIN_10
477 * @arg @ref LL_GPIO_PIN_11
478 * @arg @ref LL_GPIO_PIN_12
479 * @arg @ref LL_GPIO_PIN_13
480 * @arg @ref LL_GPIO_PIN_14
481 * @arg @ref LL_GPIO_PIN_15
482 * @retval Returned value can be one of the following values:
483 * @arg @ref LL_GPIO_PULL_NO
484 * @arg @ref LL_GPIO_PULL_UP
485 * @arg @ref LL_GPIO_PULL_DOWN
486 */
487 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
488 {
489 /* Get pin position in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
490 if(GPIO2 == GPIOx)
491 {
492 return ((READ_BITS(MCU_RET->DPAD_RE_N_BUS_1, pin) != RESET) ? LL_GPIO_PULL_NO :
493 ((READ_BITS(MCU_RET->DPAD_RTYP_BUS_1, pin) != RESET) ? LL_GPIO_PULL_UP : LL_GPIO_PULL_DOWN));
494 }
495 else
496 {
497 pin <<= ((GPIOx == GPIO0) ? 0 : 16);
498 return ((READ_BITS(MCU_RET->DPAD_RE_N_BUS_0, pin) != RESET) ? LL_GPIO_PULL_NO :
499 ((READ_BITS(MCU_RET->DPAD_RTYP_BUS_0, pin) != RESET) ? LL_GPIO_PULL_UP : LL_GPIO_PULL_DOWN));
500 }
501 }
502
503 /**
504 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
505 * @note Possible values are from AF0 to AF15 depending on target.
506 * @note Warning: only one pin can be passed as parameter.
507 *
508 * Register|BitsName
509 * --------|--------
510 * DPAD_MUX_CTRL0_7 | CTRL0_7
511 * DPAD_MUX_CTRL16_23 | CTRL16_23
512 *
513 * @param GPIOx GPIO Port
514 * @param pin This parameter can be one of the following values:
515 * @arg @ref LL_GPIO_PIN_0
516 * @arg @ref LL_GPIO_PIN_1
517 * @arg @ref LL_GPIO_PIN_2
518 * @arg @ref LL_GPIO_PIN_3
519 * @arg @ref LL_GPIO_PIN_4
520 * @arg @ref LL_GPIO_PIN_5
521 * @arg @ref LL_GPIO_PIN_6
522 * @arg @ref LL_GPIO_PIN_7
523 * @arg @ref LL_GPIO_PIN_8
524 * @arg @ref LL_GPIO_PIN_9
525 * @arg @ref LL_GPIO_PIN_10
526 * @arg @ref LL_GPIO_PIN_11
527 * @arg @ref LL_GPIO_PIN_12
528 * @arg @ref LL_GPIO_PIN_13
529 * @arg @ref LL_GPIO_PIN_14
530 * @arg @ref LL_GPIO_PIN_15
531 * @param mux This parameter can be one of the following values:
532 * @arg @ref LL_GPIO_MUX_0
533 * @arg @ref LL_GPIO_MUX_1
534 * @arg @ref LL_GPIO_MUX_2
535 * @arg @ref LL_GPIO_MUX_3
536 * @arg @ref LL_GPIO_MUX_4
537 * @arg @ref LL_GPIO_MUX_5
538 * @arg @ref LL_GPIO_MUX_6
539 * @arg @ref LL_GPIO_MUX_7
540 * @arg @ref LL_GPIO_MUX_8
541 * @retval None
542 */
543 __STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
544 {
545 volatile uint32_t* GPIO_MUX_REG_BASE = &(MCU_RET->DPAD_MUX_CTL_00_07);
546 uint8_t offset;
547 uint32_t pos;
548
549 pin = POSITION_VAL(pin);
550 pos = (pin & 7) << 2; /* pos = (pin % 8) * 4 */
551
552 if(GPIO0 == GPIOx)
553 {
554 offset = pin >> 3; /* offset = pin / 8 */
555 }
556 else if(GPIO1 == GPIOx)
557 {
558 offset = (pin >> 3) + 2; /* offset = pin / 8 + 2*/
559 }
560 else //GPIO2
561 {
562 offset = 6; /* DPAD_MUX_CTL_32_39 - DPAD_MUX_CTL_00_07 */
563 }
564
565 MODIFY_REG(*(GPIO_MUX_REG_BASE + offset), 0xF << pos, mux << pos);
566 }
567
568 /**
569 * @brief Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
570 * @note Possible values are from AF0 to AF15 depending on target.
571 *
572 * Register|BitsName
573 * --------|--------
574 * DPAD_MUX_CTRL8_15 | CTRL8_15
575 * DPAD_MUX_CTRL24_31 | CTRL24_31
576 *
577 * @param GPIOx GPIO Port
578 * @param pin This parameter can be one of the following values:
579 * @arg @ref LL_GPIO_PIN_0
580 * @arg @ref LL_GPIO_PIN_1
581 * @arg @ref LL_GPIO_PIN_2
582 * @arg @ref LL_GPIO_PIN_3
583 * @arg @ref LL_GPIO_PIN_4
584 * @arg @ref LL_GPIO_PIN_5
585 * @arg @ref LL_GPIO_PIN_6
586 * @arg @ref LL_GPIO_PIN_7
587 * @arg @ref LL_GPIO_PIN_8
588 * @arg @ref LL_GPIO_PIN_9
589 * @arg @ref LL_GPIO_PIN_10
590 * @arg @ref LL_GPIO_PIN_11
591 * @arg @ref LL_GPIO_PIN_12
592 * @arg @ref LL_GPIO_PIN_13
593 * @arg @ref LL_GPIO_PIN_14
594 * @arg @ref LL_GPIO_PIN_15
595 * @retval Returned value can be one of the following values:
596 * @arg @ref LL_GPIO_MUX_0
597 * @arg @ref LL_GPIO_MUX_1
598 * @arg @ref LL_GPIO_MUX_2
599 * @arg @ref LL_GPIO_MUX_3
600 * @arg @ref LL_GPIO_MUX_4
601 * @arg @ref LL_GPIO_MUX_5
602 * @arg @ref LL_GPIO_MUX_6
603 * @arg @ref LL_GPIO_MUX_7
604 * @arg @ref LL_GPIO_MUX_8
605 */
606 __STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
607 {
608 uint32_t pos = POSITION_VAL(pin) << 2;
609 if(GPIO0 == GPIOx)
610 {
611 if(pin < LL_GPIO_PIN_8)
612 {
613 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_00_07, 0xF << pos) >> pos);
614 }
615 else
616 {
617 pos = POSITION_VAL(pin >> 8) << 2;
618 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_08_15, 0xF << pos) >> pos);
619 }
620 }
621 else if(GPIO1 == GPIOx)
622 {
623 if(pin < LL_GPIO_PIN_8)
624 {
625 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_16_23, 0xF << pos) >> pos);
626 }
627 else
628 {
629 pos = POSITION_VAL(pin >> 8) << 2;
630 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_24_31, 0xF << pos) >> pos);
631 }
632 }
633 else
634 {
635 if(pin < LL_GPIO_PIN_8)
636 {
637 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_32_39, 0xF << pos) >> pos);
638 }
639 }
640 return 0;
641 }
642 /** @} */
643
644 /** @defgroup GPIO_LL_EF_Data_Access Data Access
645 * @{
646 */
647
648 /**
649 * @brief Return full input data register value for a dedicated port.
650 *
651 * Register|BitsName
652 * --------|--------
653 * DATA | DATA
654 *
655 * @param GPIOx GPIO Port
656 * @retval Input data register value of port
657 */
658 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
659 {
660 return (uint32_t)(READ_REG(GPIOx->DATA));
661 }
662
663 /**
664 * @brief Return if input data level for several pins of dedicated port is high or low.
665 *
666 * Register|BitsName
667 * --------|--------
668 * DATA | DATA
669 *
670 * @param GPIOx GPIO Port
671 * @param pin_mask This parameter can be a combination of the following values:
672 * @arg @ref LL_GPIO_PIN_0
673 * @arg @ref LL_GPIO_PIN_1
674 * @arg @ref LL_GPIO_PIN_2
675 * @arg @ref LL_GPIO_PIN_3
676 * @arg @ref LL_GPIO_PIN_4
677 * @arg @ref LL_GPIO_PIN_5
678 * @arg @ref LL_GPIO_PIN_6
679 * @arg @ref LL_GPIO_PIN_7
680 * @arg @ref LL_GPIO_PIN_8
681 * @arg @ref LL_GPIO_PIN_9
682 * @arg @ref LL_GPIO_PIN_10
683 * @arg @ref LL_GPIO_PIN_11
684 * @arg @ref LL_GPIO_PIN_12
685 * @arg @ref LL_GPIO_PIN_13
686 * @arg @ref LL_GPIO_PIN_14
687 * @arg @ref LL_GPIO_PIN_15
688 * @arg @ref LL_GPIO_PIN_ALL
689 * @retval State of bit (1 or 0).
690 */
691 __STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
692 {
693 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
694 }
695
696 /**
697 * @brief Write output data register for the port.
698 *
699 * Register|BitsName
700 * --------|--------
701 * DATAOUT | DATAOUT
702 *
703 * @param GPIOx GPIO Port
704 * @param port_value Level value for each pin of the port
705 * @retval None
706 */
707 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
708 {
709 WRITE_REG(GPIOx->DATAOUT, port_value);
710 }
711
712 /**
713 * @brief Return full output data register value for a dedicated port.
714 *
715 * Register|BitsName
716 * --------|--------
717 * DATAOUT | DATAOUT
718 *
719 * @param GPIOx GPIO Port
720 * @retval Output data register value of port
721 */
722 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
723 {
724 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
725 }
726
727 /**
728 * @brief Return if output data level for several pins of dedicated port is high or low.
729 *
730 * Register|BitsName
731 * --------|--------
732 * DATA | DATAOUT
733 *
734 * @param GPIOx GPIO Port
735 * @param pin_mask This parameter can be a combination of the following values:
736 * @arg @ref LL_GPIO_PIN_0
737 * @arg @ref LL_GPIO_PIN_1
738 * @arg @ref LL_GPIO_PIN_2
739 * @arg @ref LL_GPIO_PIN_3
740 * @arg @ref LL_GPIO_PIN_4
741 * @arg @ref LL_GPIO_PIN_5
742 * @arg @ref LL_GPIO_PIN_6
743 * @arg @ref LL_GPIO_PIN_7
744 * @arg @ref LL_GPIO_PIN_8
745 * @arg @ref LL_GPIO_PIN_9
746 * @arg @ref LL_GPIO_PIN_10
747 * @arg @ref LL_GPIO_PIN_11
748 * @arg @ref LL_GPIO_PIN_12
749 * @arg @ref LL_GPIO_PIN_13
750 * @arg @ref LL_GPIO_PIN_14
751 * @arg @ref LL_GPIO_PIN_15
752 * @arg @ref LL_GPIO_PIN_ALL
753 * @retval State of bit (1 or 0).
754 */
755 __STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
756 {
757 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
758 }
759
760 /**
761 * @brief Set several pins to high level on dedicated gpio port.
762 *
763 * Register|BitsName
764 * --------|--------
765 * DATAOUT | DATAOUT
766 *
767 * @param GPIOx GPIO Port
768 * @param pin_mask This parameter can be a combination of the following values:
769 * @arg @ref LL_GPIO_PIN_0
770 * @arg @ref LL_GPIO_PIN_1
771 * @arg @ref LL_GPIO_PIN_2
772 * @arg @ref LL_GPIO_PIN_3
773 * @arg @ref LL_GPIO_PIN_4
774 * @arg @ref LL_GPIO_PIN_5
775 * @arg @ref LL_GPIO_PIN_6
776 * @arg @ref LL_GPIO_PIN_7
777 * @arg @ref LL_GPIO_PIN_8
778 * @arg @ref LL_GPIO_PIN_9
779 * @arg @ref LL_GPIO_PIN_10
780 * @arg @ref LL_GPIO_PIN_11
781 * @arg @ref LL_GPIO_PIN_12
782 * @arg @ref LL_GPIO_PIN_13
783 * @arg @ref LL_GPIO_PIN_14
784 * @arg @ref LL_GPIO_PIN_15
785 * @arg @ref LL_GPIO_PIN_ALL
786 * @retval None
787 */
788 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
789 {
790 #ifdef USE_GPIO_MASK_REGISTER
791 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
792 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
793 pin_mask & GPIO_MASKHIGHBYTE_DATA);
794 #else
795 SET_BITS(GPIOx->DATAOUT, pin_mask);
796 #endif
797 }
798
799 /**
800 * @brief Set several pins to low level on dedicated gpio port.
801 *
802 * Register|BitsName
803 * --------|--------
804 * DATAOUT | DATAOUT
805 *
806 * @param GPIOx GPIO Port
807 * @param pin_mask This parameter can be a combination of the following values:
808 * @arg @ref LL_GPIO_PIN_0
809 * @arg @ref LL_GPIO_PIN_1
810 * @arg @ref LL_GPIO_PIN_2
811 * @arg @ref LL_GPIO_PIN_3
812 * @arg @ref LL_GPIO_PIN_4
813 * @arg @ref LL_GPIO_PIN_5
814 * @arg @ref LL_GPIO_PIN_6
815 * @arg @ref LL_GPIO_PIN_7
816 * @arg @ref LL_GPIO_PIN_8
817 * @arg @ref LL_GPIO_PIN_9
818 * @arg @ref LL_GPIO_PIN_10
819 * @arg @ref LL_GPIO_PIN_11
820 * @arg @ref LL_GPIO_PIN_12
821 * @arg @ref LL_GPIO_PIN_13
822 * @arg @ref LL_GPIO_PIN_14
823 * @arg @ref LL_GPIO_PIN_15
824 * @arg @ref LL_GPIO_PIN_ALL
825 * @retval None
826 */
827 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
828 {
829 #ifdef USE_GPIO_MASK_REGISTER
830 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
831 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
832 #else
833 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
834 #endif
835 }
836
837 /**
838 * @brief Toggle data value for several pin of dedicated port.
839 *
840 * Register|BitsName
841 * --------|--------
842 * DATAOUT | DATAOUT
843 *
844 * @param GPIOx GPIO Port
845 * @param pin_mask This parameter can be a combination of the following values:
846 * @arg @ref LL_GPIO_PIN_0
847 * @arg @ref LL_GPIO_PIN_1
848 * @arg @ref LL_GPIO_PIN_2
849 * @arg @ref LL_GPIO_PIN_3
850 * @arg @ref LL_GPIO_PIN_4
851 * @arg @ref LL_GPIO_PIN_5
852 * @arg @ref LL_GPIO_PIN_6
853 * @arg @ref LL_GPIO_PIN_7
854 * @arg @ref LL_GPIO_PIN_8
855 * @arg @ref LL_GPIO_PIN_9
856 * @arg @ref LL_GPIO_PIN_10
857 * @arg @ref LL_GPIO_PIN_11
858 * @arg @ref LL_GPIO_PIN_12
859 * @arg @ref LL_GPIO_PIN_13
860 * @arg @ref LL_GPIO_PIN_14
861 * @arg @ref LL_GPIO_PIN_15
862 * @arg @ref LL_GPIO_PIN_ALL
863 * @retval None
864 */
865 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
866 {
867 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
868 }
869
870 /** @} */
871
872 /** @defgroup GPIO_LL_EF_IT_Management IT_Management
873 * @{
874 */
875
876 /**
877 * @brief Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
878 * @note
879 *
880 * Register|BitsName
881 * --------|--------
882 * INTPOLCLR | INTPOLCLR
883 * INTTYPESET | INTTYPESET
884 *
885 * @param GPIOx GPIO instance.
886 * @param pin_mask This parameter can be a combination of the following values:
887 * @arg @ref LL_GPIO_PIN_0
888 * @arg @ref LL_GPIO_PIN_1
889 * @arg @ref LL_GPIO_PIN_2
890 * @arg @ref LL_GPIO_PIN_3
891 * @arg @ref LL_GPIO_PIN_4
892 * @arg @ref LL_GPIO_PIN_5
893 * @arg @ref LL_GPIO_PIN_6
894 * @arg @ref LL_GPIO_PIN_7
895 * @arg @ref LL_GPIO_PIN_8
896 * @arg @ref LL_GPIO_PIN_9
897 * @arg @ref LL_GPIO_PIN_10
898 * @arg @ref LL_GPIO_PIN_11
899 * @arg @ref LL_GPIO_PIN_12
900 * @arg @ref LL_GPIO_PIN_13
901 * @arg @ref LL_GPIO_PIN_14
902 * @arg @ref LL_GPIO_PIN_15
903 * @arg @ref LL_GPIO_PIN_ALL
904 * @retval None
905 */
906 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
907 {
908 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
909 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
910 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
911 }
912
913 /**
914 * @brief Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
915 * @note
916 *
917 * Register|BitsName
918 * --------|--------
919 * INTPOLSET | INTPOLSET
920 * INTTYPESET | INTTYPESET
921 *
922 * @param GPIOx GPIO instance.
923 * @param pin_mask This parameter can be a combination of the following values:
924 * @arg @ref LL_GPIO_PIN_0
925 * @arg @ref LL_GPIO_PIN_1
926 * @arg @ref LL_GPIO_PIN_2
927 * @arg @ref LL_GPIO_PIN_3
928 * @arg @ref LL_GPIO_PIN_4
929 * @arg @ref LL_GPIO_PIN_5
930 * @arg @ref LL_GPIO_PIN_6
931 * @arg @ref LL_GPIO_PIN_7
932 * @arg @ref LL_GPIO_PIN_8
933 * @arg @ref LL_GPIO_PIN_9
934 * @arg @ref LL_GPIO_PIN_10
935 * @arg @ref LL_GPIO_PIN_11
936 * @arg @ref LL_GPIO_PIN_12
937 * @arg @ref LL_GPIO_PIN_13
938 * @arg @ref LL_GPIO_PIN_14
939 * @arg @ref LL_GPIO_PIN_15
940 * @arg @ref LL_GPIO_PIN_ALL
941 * @retval None
942 */
943 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
944 {
945 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
946 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
947 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
948 }
949
950 /**
951 * @brief Enable GPIO High Level Trigger for pins in the range of 0 to 15.
952 * @note
953 *
954 * Register|BitsName
955 * --------|--------
956 * INTPOLSET | INTPOLSET
957 * INTTYPECLR | INTTYPECLR
958 *
959 * @param GPIOx GPIO instance.
960 * @param pin_mask This parameter can be a combination of the following values:
961 * @arg @ref LL_GPIO_PIN_0
962 * @arg @ref LL_GPIO_PIN_1
963 * @arg @ref LL_GPIO_PIN_2
964 * @arg @ref LL_GPIO_PIN_3
965 * @arg @ref LL_GPIO_PIN_4
966 * @arg @ref LL_GPIO_PIN_5
967 * @arg @ref LL_GPIO_PIN_6
968 * @arg @ref LL_GPIO_PIN_7
969 * @arg @ref LL_GPIO_PIN_8
970 * @arg @ref LL_GPIO_PIN_9
971 * @arg @ref LL_GPIO_PIN_10
972 * @arg @ref LL_GPIO_PIN_11
973 * @arg @ref LL_GPIO_PIN_12
974 * @arg @ref LL_GPIO_PIN_13
975 * @arg @ref LL_GPIO_PIN_14
976 * @arg @ref LL_GPIO_PIN_15
977 * @arg @ref LL_GPIO_PIN_ALL
978 * @retval None
979 */
980 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
981 {
982 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
983 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
984 }
985
986 /**
987 * @brief Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
988 * @note
989 *
990 * Register|BitsName
991 * --------|--------
992 * INTPOLCLR | INTPOLCLR
993 * INTTYPECLR | INTTYPECLR
994 *
995 * @param GPIOx GPIO instance.
996 * @param pin_mask This parameter can be a combination of the following values:
997 * @arg @ref LL_GPIO_PIN_0
998 * @arg @ref LL_GPIO_PIN_1
999 * @arg @ref LL_GPIO_PIN_2
1000 * @arg @ref LL_GPIO_PIN_3
1001 * @arg @ref LL_GPIO_PIN_4
1002 * @arg @ref LL_GPIO_PIN_5
1003 * @arg @ref LL_GPIO_PIN_6
1004 * @arg @ref LL_GPIO_PIN_7
1005 * @arg @ref LL_GPIO_PIN_8
1006 * @arg @ref LL_GPIO_PIN_9
1007 * @arg @ref LL_GPIO_PIN_10
1008 * @arg @ref LL_GPIO_PIN_11
1009 * @arg @ref LL_GPIO_PIN_12
1010 * @arg @ref LL_GPIO_PIN_13
1011 * @arg @ref LL_GPIO_PIN_14
1012 * @arg @ref LL_GPIO_PIN_15
1013 * @arg @ref LL_GPIO_PIN_ALL
1014 * @retval None
1015 */
1016 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1017 {
1018 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1019 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1020 }
1021
1022 /**
1023 * @brief Enable GPIO both edge Trigger for pins in the range of 0 to 15.
1024 * @note
1025 *
1026 * Register|BitsName
1027 * --------|--------
1028 * INTPOLCLR | INTPOLCLR
1029 * INTTYPESET | INTTYPESET
1030 * INTTYPESET | INTTYPESET
1031 *
1032 * @param GPIOx GPIO instance.
1033 * @param pin_mask This parameter can be a combination of the following values:
1034 * @arg @ref LL_GPIO_PIN_0
1035 * @arg @ref LL_GPIO_PIN_1
1036 * @arg @ref LL_GPIO_PIN_2
1037 * @arg @ref LL_GPIO_PIN_3
1038 * @arg @ref LL_GPIO_PIN_4
1039 * @arg @ref LL_GPIO_PIN_5
1040 * @arg @ref LL_GPIO_PIN_6
1041 * @arg @ref LL_GPIO_PIN_7
1042 * @arg @ref LL_GPIO_PIN_8
1043 * @arg @ref LL_GPIO_PIN_9
1044 * @arg @ref LL_GPIO_PIN_10
1045 * @arg @ref LL_GPIO_PIN_11
1046 * @arg @ref LL_GPIO_PIN_12
1047 * @arg @ref LL_GPIO_PIN_13
1048 * @arg @ref LL_GPIO_PIN_14
1049 * @arg @ref LL_GPIO_PIN_15
1050 * @arg @ref LL_GPIO_PIN_ALL
1051 * @retval None
1052 */
1053 __STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1054 {
1055 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1056 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1057 WRITE_REG(GPIOx->INTDBESET, pin_mask);
1058 }
1059
1060 /**
1061 * @brief Get trigger type for pins in the range of 0 to 15
1062 * @note
1063 *
1064 * Register|BitsName
1065 * --------|--------
1066 * INTPOLCLR | INTPOLCLR
1067 * INTTYPECLR | INTTYPECLR
1068 * INTTYPESET | INTTYPESET
1069 *
1070 * @param GPIOx GPIO instance.
1071 * @param pin_mask This parameter can be a combination of the following values:
1072 * @arg @ref LL_GPIO_PIN_0
1073 * @arg @ref LL_GPIO_PIN_1
1074 * @arg @ref LL_GPIO_PIN_2
1075 * @arg @ref LL_GPIO_PIN_3
1076 * @arg @ref LL_GPIO_PIN_4
1077 * @arg @ref LL_GPIO_PIN_5
1078 * @arg @ref LL_GPIO_PIN_6
1079 * @arg @ref LL_GPIO_PIN_7
1080 * @arg @ref LL_GPIO_PIN_8
1081 * @arg @ref LL_GPIO_PIN_9
1082 * @arg @ref LL_GPIO_PIN_10
1083 * @arg @ref LL_GPIO_PIN_11
1084 * @arg @ref LL_GPIO_PIN_12
1085 * @arg @ref LL_GPIO_PIN_13
1086 * @arg @ref LL_GPIO_PIN_14
1087 * @arg @ref LL_GPIO_PIN_15
1088 * @retval Returned value can be one of the following values:
1089 * @arg @ref LL_GPIO_TRIGGER_RISING
1090 * @arg @ref LL_GPIO_TRIGGER_FALLING
1091 * @arg @ref LL_GPIO_TRIGGER_HIGH
1092 * @arg @ref LL_GPIO_TRIGGER_LOW
1093 * @arg @ref LL_GPIO_TRIGGER_BOTH_EDGE
1094 */
1095 __STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
1096 {
1097 /* INTTYPESET INTPOLSET INTDBESET
1098 TRIGGER_FALLING 1 0 0
1099 TRIGGER_RISING 1 1 0
1100 TRIGGER_BOTH_EDGE 1 X 1
1101 TRIGGER_HIGH 0 1 X
1102 TRIGGER_LOW 0 0 X
1103 */
1104 #define TYPE_SET ((uint32_t)0x4U) /**< GPIO INTTYPESET is set */
1105 #define POL_SET ((uint32_t)0x2U) /**< GPIO INTPOLSET is set */
1106 #define DBE_SET ((uint32_t)0x1U) /**< GPIO INTDBESET is set */
1107
1108 uint32_t pos = POSITION_VAL(pin_mask);
1109 uint32_t type = (READ_BITS(GPIOx->INTTYPESET, pin_mask) >> pos ) << 2;
1110 uint32_t pol = (READ_BITS(GPIOx->INTPOLSET, pin_mask) >> pos) << 1;
1111 uint32_t both_egde = (READ_BITS(GPIOx->INTDBESET, pin_mask) >> pos);
1112
1113 switch (type | pol | both_egde)
1114 {
1115 case TYPE_SET:
1116 return LL_GPIO_TRIGGER_FALLING;
1117 case TYPE_SET | POL_SET:
1118 return LL_GPIO_TRIGGER_RISING;
1119 case TYPE_SET | DBE_SET:
1120 return LL_GPIO_TRIGGER_BOTH_EDGE;
1121 case TYPE_SET | POL_SET | DBE_SET:
1122 return LL_GPIO_TRIGGER_BOTH_EDGE;
1123 case POL_SET:
1124 return LL_GPIO_TRIGGER_HIGH;
1125 default:
1126 return LL_GPIO_TRIGGER_LOW;
1127 }
1128 }
1129
1130 /**
1131 * @brief Enable GPIO interrupts for pins in the range of 0 to 15.
1132 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1133 *
1134 * Register|BitsName
1135 * --------|--------
1136 * INTENSET | INTENSET
1137 *
1138 * @param GPIOx GPIO instance.
1139 * @param pin_mask This parameter can be a combination of the following values:
1140 * @arg @ref LL_GPIO_PIN_0
1141 * @arg @ref LL_GPIO_PIN_1
1142 * @arg @ref LL_GPIO_PIN_2
1143 * @arg @ref LL_GPIO_PIN_3
1144 * @arg @ref LL_GPIO_PIN_4
1145 * @arg @ref LL_GPIO_PIN_5
1146 * @arg @ref LL_GPIO_PIN_6
1147 * @arg @ref LL_GPIO_PIN_7
1148 * @arg @ref LL_GPIO_PIN_8
1149 * @arg @ref LL_GPIO_PIN_9
1150 * @arg @ref LL_GPIO_PIN_10
1151 * @arg @ref LL_GPIO_PIN_11
1152 * @arg @ref LL_GPIO_PIN_12
1153 * @arg @ref LL_GPIO_PIN_13
1154 * @arg @ref LL_GPIO_PIN_14
1155 * @arg @ref LL_GPIO_PIN_15
1156 * @arg @ref LL_GPIO_PIN_ALL
1157 * @retval None
1158 */
1159 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1160 {
1161 WRITE_REG(GPIOx->INTENSET, pin_mask);
1162 }
1163
1164 /**
1165 * @brief Disable GPIO interrupts for pins in the range of 0 to 15.
1166 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1167 *
1168 * Register|BitsName
1169 * --------|--------
1170 * INTENCLR | INTENCLR
1171 *
1172 * @param GPIOx GPIO instance.
1173 * @param pin_mask This parameter can be a combination of the following values:
1174 * @arg @ref LL_GPIO_PIN_0
1175 * @arg @ref LL_GPIO_PIN_1
1176 * @arg @ref LL_GPIO_PIN_2
1177 * @arg @ref LL_GPIO_PIN_3
1178 * @arg @ref LL_GPIO_PIN_4
1179 * @arg @ref LL_GPIO_PIN_5
1180 * @arg @ref LL_GPIO_PIN_6
1181 * @arg @ref LL_GPIO_PIN_7
1182 * @arg @ref LL_GPIO_PIN_8
1183 * @arg @ref LL_GPIO_PIN_9
1184 * @arg @ref LL_GPIO_PIN_10
1185 * @arg @ref LL_GPIO_PIN_11
1186 * @arg @ref LL_GPIO_PIN_12
1187 * @arg @ref LL_GPIO_PIN_13
1188 * @arg @ref LL_GPIO_PIN_14
1189 * @arg @ref LL_GPIO_PIN_15
1190 * @arg @ref LL_GPIO_PIN_ALL
1191 * @retval None
1192 */
1193 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1194 {
1195 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1196 }
1197
1198 /**
1199 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1200 *
1201 * Register|BitsName
1202 * --------|--------
1203 * INTENSET | INTENSET
1204 *
1205 * @param GPIOx GPIO instance.
1206 * @param pin_mask This parameter can be a combination of the following values:
1207 * @arg @ref LL_GPIO_PIN_0
1208 * @arg @ref LL_GPIO_PIN_1
1209 * @arg @ref LL_GPIO_PIN_2
1210 * @arg @ref LL_GPIO_PIN_3
1211 * @arg @ref LL_GPIO_PIN_4
1212 * @arg @ref LL_GPIO_PIN_5
1213 * @arg @ref LL_GPIO_PIN_6
1214 * @arg @ref LL_GPIO_PIN_7
1215 * @arg @ref LL_GPIO_PIN_8
1216 * @arg @ref LL_GPIO_PIN_9
1217 * @arg @ref LL_GPIO_PIN_10
1218 * @arg @ref LL_GPIO_PIN_11
1219 * @arg @ref LL_GPIO_PIN_12
1220 * @arg @ref LL_GPIO_PIN_13
1221 * @arg @ref LL_GPIO_PIN_14
1222 * @arg @ref LL_GPIO_PIN_15
1223 * @arg @ref LL_GPIO_PIN_ALL
1224 * @retval State of bit (1 or 0).
1225 */
1226 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1227 {
1228 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1229 }
1230
1231 /** @} */
1232
1233 /** @defgroup GPIO_LL_EF_Flag_Management Flag_Management
1234 * @{
1235 */
1236
1237 /**
1238 * @brief Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15
1239 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1240 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1241 *
1242 * Register|BitsName
1243 * --------|--------
1244 * INTSTATUS | INTSTATUS
1245 *
1246 * @param GPIOx GPIO instance.
1247 * @param pin_mask This parameter can be a combination of the following values:
1248 * @arg @ref LL_GPIO_PIN_0
1249 * @arg @ref LL_GPIO_PIN_1
1250 * @arg @ref LL_GPIO_PIN_2
1251 * @arg @ref LL_GPIO_PIN_3
1252 * @arg @ref LL_GPIO_PIN_4
1253 * @arg @ref LL_GPIO_PIN_5
1254 * @arg @ref LL_GPIO_PIN_6
1255 * @arg @ref LL_GPIO_PIN_7
1256 * @arg @ref LL_GPIO_PIN_8
1257 * @arg @ref LL_GPIO_PIN_9
1258 * @arg @ref LL_GPIO_PIN_10
1259 * @arg @ref LL_GPIO_PIN_11
1260 * @arg @ref LL_GPIO_PIN_12
1261 * @arg @ref LL_GPIO_PIN_13
1262 * @arg @ref LL_GPIO_PIN_14
1263 * @arg @ref LL_GPIO_PIN_15
1264 * @arg @ref LL_GPIO_PIN_ALL
1265 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1266 */
1267 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1268 {
1269 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1270 }
1271
1272 /**
1273 * @brief Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
1274 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1275 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1276 *
1277 * Register|BitsName
1278 * --------|--------
1279 * INTSTATUS | INTSTATUS
1280 *
1281 * @param GPIOx GPIO instance.
1282 * @param pin_mask This parameter can be a combination of the following values:
1283 * @arg @ref LL_GPIO_PIN_0
1284 * @arg @ref LL_GPIO_PIN_1
1285 * @arg @ref LL_GPIO_PIN_2
1286 * @arg @ref LL_GPIO_PIN_3
1287 * @arg @ref LL_GPIO_PIN_4
1288 * @arg @ref LL_GPIO_PIN_5
1289 * @arg @ref LL_GPIO_PIN_6
1290 * @arg @ref LL_GPIO_PIN_7
1291 * @arg @ref LL_GPIO_PIN_8
1292 * @arg @ref LL_GPIO_PIN_9
1293 * @arg @ref LL_GPIO_PIN_10
1294 * @arg @ref LL_GPIO_PIN_11
1295 * @arg @ref LL_GPIO_PIN_12
1296 * @arg @ref LL_GPIO_PIN_13
1297 * @arg @ref LL_GPIO_PIN_14
1298 * @arg @ref LL_GPIO_PIN_15
1299 * @arg @ref LL_GPIO_PIN_ALL
1300 * @retval State of bit (1 or 0).
1301 */
1302 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1303 {
1304 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1305 }
1306
1307 /**
1308 * @brief Clear Interrupt Status flag for pins in the range of 0 to 15.
1309 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1310 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1311 *
1312 * Register|BitsName
1313 * --------|--------
1314 * INTSTATUS | INTSTATUS
1315 *
1316 * @param GPIOx GPIO instance.
1317 * @param pin_mask This parameter can be a combination of the following values:
1318 * @arg @ref LL_GPIO_PIN_0
1319 * @arg @ref LL_GPIO_PIN_1
1320 * @arg @ref LL_GPIO_PIN_2
1321 * @arg @ref LL_GPIO_PIN_3
1322 * @arg @ref LL_GPIO_PIN_4
1323 * @arg @ref LL_GPIO_PIN_5
1324 * @arg @ref LL_GPIO_PIN_6
1325 * @arg @ref LL_GPIO_PIN_7
1326 * @arg @ref LL_GPIO_PIN_8
1327 * @arg @ref LL_GPIO_PIN_9
1328 * @arg @ref LL_GPIO_PIN_10
1329 * @arg @ref LL_GPIO_PIN_11
1330 * @arg @ref LL_GPIO_PIN_12
1331 * @arg @ref LL_GPIO_PIN_13
1332 * @arg @ref LL_GPIO_PIN_14
1333 * @arg @ref LL_GPIO_PIN_15
1334 * @arg @ref LL_GPIO_PIN_ALL
1335 * @retval None
1336 */
1337 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1338 {
1339 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1340 }
1341
1342 /** @} */
1343
1344 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
1345 * @{
1346 */
1347 /**
1348 * @brief Initialize GPIO registers according to the specified
1349 * parameters in p_gpio_init.
1350 * @param GPIOx GPIO instance.
1351 * @param p_gpio_init Pointer to a ll_gpio_init_t structure that contains the configuration
1352 * information for the specified GPIO peripheral.
1353 * @retval An error_status_t enumeration value:
1354 * - SUCCESS: GPIO registers are initialized according to p_gpio_init content
1355 * - ERROR: Problem occurred during GPIO Registers initialization
1356 */
1357 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1358 /** @} */
1359
1360 /** @} */
1361
1362 #endif /* defined (GPIO0) || defined (GPIO1) */
1363
1364 #ifdef __cplusplus
1365 }
1366 #endif
1367
1368 #endif /* __GR55xx_LL_GPIO_H__ */
1369
1370 /** @} */
1371
1372 /** @} */
1373
1374 /** @} */
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:658
_ll_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_gpio.h:78
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr55xx_ll_gpio.h:149
LL_GPIO_TRIGGER_RISING
#define LL_GPIO_TRIGGER_RISING
Definition: gr55xx_ll_gpio.h:172
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:980
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_gpio.h:1226
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr55xx_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
LL_GPIO_MODE_MUX
#define LL_GPIO_MODE_MUX
Definition: gr55xx_ll_gpio.h:143
ll_gpio_read_input_pin
__STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:691
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr55xx_ll_gpio.h:150
_ll_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_gpio.h:91
ll_gpio_read_output_pin
__STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if output data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:755
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_gpio.h:97
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:722
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:788
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:943
ll_gpio_enable_both_edge_trigger
__STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO both edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1053
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1302
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1159
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:402
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:487
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:827
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr55xx_ll_gpio.h:151
LL_GPIO_TRIGGER_LOW
#define LL_GPIO_TRIGGER_LOW
Definition: gr55xx_ll_gpio.h:175
LL_GPIO_TRIGGER_HIGH
#define LL_GPIO_TRIGGER_HIGH
Definition: gr55xx_ll_gpio.h:174
LL_GPIO_TRIGGER_FALLING
#define LL_GPIO_TRIGGER_FALLING
Definition: gr55xx_ll_gpio.h:173
LL_GPIO_PIN_8
#define LL_GPIO_PIN_8
Definition: gr55xx_ll_gpio.h:127
TYPE_SET
#define TYPE_SET
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr55xx_ll_gpio.h:865
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr55xx_ll_gpio.h:707
LL_GPIO_TRIGGER_BOTH_EDGE
#define LL_GPIO_TRIGGER_BOTH_EDGE
Definition: gr55xx_ll_gpio.h:176
ll_gpio_get_trigger_type
__STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
Get trigger type for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1095
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr55xx_ll_gpio.h:141
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1016
_ll_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_gpio.h:81
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_gpio.h:142
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr55xx_ll_gpio.h:341
_ll_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_gpio.h:86
POL_SET
#define POL_SET
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1267
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:906
DBE_SET
#define DBE_SET
ll_gpio_set_pin_mux
__STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:543
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1193
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:439
ll_gpio_get_pin_mux
__STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:606
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1337