gr55xx_ll_aon_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_IO) || defined(MCU_RET)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
79 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
80
81 uint32_t mode; /**< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
83
84 AON_GPIO HW configuration can be modified afterwards using unitary function
85 @ref ll_aon_gpio_set_pin_mode(). */
86
87 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
88 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
89
90 AON_GPIO HW configuration can be modified afterwards using unitary function
91 @ref ll_aon_gpio_set_pin_pull(). */
92
93 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
94 This parameter can be a value of @ref AON_GPIO_LL_EC_MUX.
95
96 AON_GPIO HW configuration can be modified afterwards using unitary function
97 @ref ll_aon_gpio_set_pin_mux(). */
98
99 uint32_t trigger; /**< Specifies the trigger signal active edge.
100 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
101 } ll_aon_gpio_init_t;
102
103 /** @} */
104
105 /** @} */
106
107 /**
108 * @defgroup AON_GPIO_LL_MACRO Defines
109 * @{
110 */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
114 * @{
115 */
116
117 /** @defgroup AON_GPIO_LL_EC_PIN PIN
118 * @{
119 */
120 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
121 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
122 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
123 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
124 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
125 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
126 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
127 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
128 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
129 /** @} */
130
131 /** @defgroup AON_GPIO_LL_EC_MODE Mode
132 * @{
133 */
134 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U) /**< Select input mode */
135 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /**< Select output mode */
136 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U) /**< Select mux peripheral mode */
137 /** @} */
138
139 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
140 * @{
141 */
142 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N /**< Select I/O no pull */
143 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP /**< Select I/O pull up */
144 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U) /**< Select I/O pull down */
145 /** @} */
146
147 /** @defgroup AON_GPIO_LL_EC_MUX Alternate Function
148 * @{
149 */
150 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
151 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
152 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
153 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
154 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
155 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
156 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
157 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
158 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
159 /** @} */
160
161
162 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
163 * @{
164 */
165 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
166 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
167 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
168 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
169 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
170 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /**< Trigger both edge */
171 /** @} */
172
173
174 /** @defgroup AON_GPIO_LL_CLOCK_OUT Select clock output via AON_GPIO_4
175 * @{
176 */
177 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U) /**< RNG_OSC_32K */
178 #define LL_CLK_RNG_OSC_2MHZ ((uint32_t)0x01U) /**< RNG_OSC_2MHz */
179 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U) /**< RC_OSC_CLK */
180 #define LL_CLK_RTC_CLK ((uint32_t)0x03U) /**< RTC_CLK */
181 /** @} */
182
183
184 /** @} */
185
186 /* Exported macro ------------------------------------------------------------*/
187 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
188 * @{
189 */
190
191 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
192 * @{
193 */
194
195 /**
196 * @brief Write a value in AON_GPIO register
197 * @param __instance__ AON_GPIO instance
198 * @param __REG__ Register to be written
199 * @param __VALUE__ Value to be written in the register
200 * @retval None
201 */
202 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
203
204 /**
205 * @brief Read a value in AON_GPIO register
206 * @param __instance__ AON_GPIO instance
207 * @param __REG__ Register to be read
208 * @retval Register value
209 */
210 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
211
212 /** @} */
213
214 /** @} */
215
216 /* Private types -------------------------------------------------------------*/
217 /* Private variables ---------------------------------------------------------*/
218 /* Private constants ---------------------------------------------------------*/
219 /* Private macros ------------------------------------------------------------*/
220 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
221 * @{
222 */
223 /** @defgroup AON_GPIO_LL_PM_RESISTOR Resistor Enable
224 * @{
225 */
226 #define LL_AON_GPIO_RE_N_Pos AON_IO_AON_PAD_CTRL0_R_EN_POS /**< Resistor Enable bits position */
227 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
228 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk /**< Resistor Enable bits */
229 /** @} */
230
231 /** @defgroup AON_GPIO_LL_PM_RESISTOR_TYPE Resistor Type
232 * @{
233 */
234 #define LL_AON_GPIO_RTYP_Pos AON_IO_AON_PAD_CTRL0_R_TYPE_POS /**< Resistor Type bits position */
235 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
236 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk /**< Resistor Type bits */
237 /** @} */
238
239 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
240 * @{
241 */
242
243 /**
244 * @brief LL AON_GPIO InitStrcut default configuartion
245 */
246 #define LL_AON_GPIO_DEFAULT_CONFIG \
247 { \
248 .pin = LL_AON_GPIO_PIN_ALL, \
249 .mode = LL_AON_GPIO_MODE_INPUT, \
250 .pull = LL_AON_GPIO_PULL_DOWN, \
251 .mux = LL_AON_GPIO_MUX_7, \
252 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
253 }
254 /** @} */
255
256 /** @} */
257
258 /** @} */
259
260 /* Exported functions --------------------------------------------------------*/
261 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
262 * @{
263 */
264
265 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
266 * @{
267 */
268
269 /**
270 * @brief Set several AON_GPIO pins to input/output mode.
271 *
272 * Register|BitsName
273 * --------|--------
274 * AON_PAD_CTL1 | AON_GPO_OE_N
275 *
276 * @param pin_mask This parameter can be a combination of the following values:
277 * @arg @ref LL_AON_GPIO_PIN_0
278 * @arg @ref LL_AON_GPIO_PIN_1
279 * @arg @ref LL_AON_GPIO_PIN_2
280 * @arg @ref LL_AON_GPIO_PIN_3
281 * @arg @ref LL_AON_GPIO_PIN_4
282 * @arg @ref LL_AON_GPIO_PIN_5
283 * @arg @ref LL_AON_GPIO_PIN_6
284 * @arg @ref LL_AON_GPIO_PIN_7
285 * @arg @ref LL_AON_GPIO_PIN_ALL
286 * @param mode This parameter can be one of the following values:
287 * @arg @ref LL_AON_GPIO_MODE_INPUT
288 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
289 * @retval None
290 */
291 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
292 {
293 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_EN_POS) & AON_IO_AON_PAD_CTRL1_OUT_EN;
294 MODIFY_REG(AON_IO->AON_PAD_CTRL1, pin_mask, (mode == LL_AON_GPIO_MODE_INPUT) ? pin_mask : 0);
295 }
296
297 /**
298 * @brief Return gpio mode for a AON_GPIO pin.
299 * @note I/O mode can be Input mode. General purpose output.
300 * @note Warning: only one pin can be passed as parameter.
301 *
302 * Register|BitsName
303 * --------|--------
304 * AON_PAD_CTL1 | AON_GPO_OE_N
305 *
306 * @param pin This parameter can be one of the following values:
307 * @arg @ref LL_AON_GPIO_PIN_0
308 * @arg @ref LL_AON_GPIO_PIN_1
309 * @arg @ref LL_AON_GPIO_PIN_2
310 * @arg @ref LL_AON_GPIO_PIN_3
311 * @arg @ref LL_AON_GPIO_PIN_4
312 * @arg @ref LL_AON_GPIO_PIN_5
313 * @arg @ref LL_AON_GPIO_PIN_6
314 * @arg @ref LL_AON_GPIO_PIN_7
315 * @retval Returned value can be one of the following values:
316 * @arg @ref LL_AON_GPIO_MODE_INPUT
317 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
318 */
319 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
320 {
321 pin = (pin << AON_IO_AON_PAD_CTRL1_OUT_EN_POS) & AON_IO_AON_PAD_CTRL1_OUT_EN;
322 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin) == pin) ?
323 LL_AON_GPIO_MODE_INPUT : LL_AON_GPIO_MODE_OUTPUT);
324 }
325
326 /**
327 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
328 * @note Warning: only one pin can be passed as parameter.
329 *
330 * Register|BitsName
331 * --------|--------
332 * AON_PAD_CTL0 | GPO_RE_N
333 * AON_PAD_CTL0 | GPO_RTYPE
334 *
335 * @param pin_mask This parameter can be a combination of the following values:
336 * @arg @ref LL_AON_GPIO_PIN_0
337 * @arg @ref LL_AON_GPIO_PIN_1
338 * @arg @ref LL_AON_GPIO_PIN_2
339 * @arg @ref LL_AON_GPIO_PIN_3
340 * @arg @ref LL_AON_GPIO_PIN_4
341 * @arg @ref LL_AON_GPIO_PIN_5
342 * @arg @ref LL_AON_GPIO_PIN_6
343 * @arg @ref LL_AON_GPIO_PIN_7
344 * @arg @ref LL_AON_GPIO_PIN_ALL
345 * @param pull This parameter can be one of the following values:
346 * @arg @ref LL_AON_GPIO_PULL_NO
347 * @arg @ref LL_AON_GPIO_PULL_UP
348 * @arg @ref LL_AON_GPIO_PULL_DOWN
349 * @retval None
350 */
351 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
352 {
353 uint32_t RTypeMask = (pin_mask << AON_IO_AON_PAD_CTRL0_R_TYPE_POS) & AON_IO_AON_PAD_CTRL0_R_TYPE;
354 uint32_t REnMask = (pin_mask << AON_IO_AON_PAD_CTRL0_R_EN_POS) & AON_IO_AON_PAD_CTRL0_R_EN;
355 uint32_t RType = (pull == LL_AON_GPIO_PULL_UP) ? RTypeMask : 0x0000U;
356 uint32_t REn = (pull == LL_AON_GPIO_PULL_NO) ? REnMask : 0x0000U;
357 MODIFY_REG(AON_IO->AON_PAD_CTRL0, REnMask | RTypeMask, REn | RType);
358 }
359
360 /**
361 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
362 * @note Warning: only one pin can be passed as parameter.
363 *
364 * Register|BitsName
365 * --------|--------
366 * AON_PAD_CTL0 | GPO_RE_N
367 * AON_PAD_CTL0 | GPO_RTYPE
368 *
369 * @param pin This parameter can be one of the following values:
370 * @arg @ref LL_AON_GPIO_PIN_0
371 * @arg @ref LL_AON_GPIO_PIN_1
372 * @arg @ref LL_AON_GPIO_PIN_2
373 * @arg @ref LL_AON_GPIO_PIN_3
374 * @arg @ref LL_AON_GPIO_PIN_4
375 * @arg @ref LL_AON_GPIO_PIN_5
376 * @arg @ref LL_AON_GPIO_PIN_6
377 * @arg @ref LL_AON_GPIO_PIN_7
378 * @retval Returned value can be one of the following values:
379 * @arg @ref LL_AON_GPIO_PULL_NO
380 * @arg @ref LL_AON_GPIO_PULL_UP
381 * @arg @ref LL_AON_GPIO_PULL_DOWN
382 */
383 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
384 {
385 uint32_t RTypeMask = (pin << AON_IO_AON_PAD_CTRL0_R_TYPE_POS) & AON_IO_AON_PAD_CTRL0_R_TYPE;
386 uint32_t REnMask = (pin << AON_IO_AON_PAD_CTRL0_R_EN_POS) & AON_IO_AON_PAD_CTRL0_R_EN;
387 return ((READ_BITS(AON_IO->AON_PAD_CTRL0, REnMask) != RESET) ? LL_AON_GPIO_PULL_NO :
388 ((READ_BITS(AON_IO->AON_PAD_CTRL0, RTypeMask) != RESET) ? LL_AON_GPIO_PULL_UP : LL_AON_GPIO_PULL_DOWN));
389 }
390
391 /**
392 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
393 * @note Possible values are from AF0 to AF15 depending on target.
394 * @note Warning: only one pin can be passed as parameter.
395 *
396 * Register|BitsName
397 * --------|--------
398 * AON_PAD_MUX_CTRL | CTRL0_7
399 * AON_PAD_CTL_0 | MCU_OVR
400 *
401 * @param pin This parameter can be one of the following values:
402 * @arg @ref LL_AON_GPIO_PIN_0
403 * @arg @ref LL_AON_GPIO_PIN_1
404 * @arg @ref LL_AON_GPIO_PIN_2
405 * @arg @ref LL_AON_GPIO_PIN_3
406 * @arg @ref LL_AON_GPIO_PIN_4
407 * @arg @ref LL_AON_GPIO_PIN_5
408 * @arg @ref LL_AON_GPIO_PIN_6
409 * @arg @ref LL_AON_GPIO_PIN_7
410 * @param mux This parameter can be one of the following values:
411 * @arg @ref LL_AON_GPIO_MUX_0
412 * @arg @ref LL_AON_GPIO_MUX_1
413 * @arg @ref LL_AON_GPIO_MUX_2
414 * @arg @ref LL_AON_GPIO_MUX_3
415 * @arg @ref LL_AON_GPIO_MUX_4
416 * @arg @ref LL_AON_GPIO_MUX_5
417 * @arg @ref LL_AON_GPIO_MUX_6
418 * @arg @ref LL_AON_GPIO_MUX_7
419 * @arg @ref LL_AON_GPIO_MUX_8
420 * @retval None
421 */
422 __STATIC_INLINE void ll_aon_gpio_set_pin_mux(uint32_t pin, uint32_t mux)
423 {
424 uint32_t pos = POSITION_VAL(pin) << 2;
425 if(LL_AON_GPIO_MUX_7 == mux)
426 {
427 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
428 }
429 else
430 {
431 MODIFY_REG(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
432 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
433 }
434 }
435
436 /**
437 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
438 *
439 * Register|BitsName
440 * --------|--------
441 * AON_PAD_MUX_CTRL | CTRL0_7
442 * AON_PAD_CTL_0 | MCU_OVR
443 *
444 * @param pin This parameter can be one of the following values:
445 * @arg @ref LL_AON_GPIO_PIN_0
446 * @arg @ref LL_AON_GPIO_PIN_1
447 * @arg @ref LL_AON_GPIO_PIN_2
448 * @arg @ref LL_AON_GPIO_PIN_3
449 * @arg @ref LL_AON_GPIO_PIN_4
450 * @arg @ref LL_AON_GPIO_PIN_5
451 * @arg @ref LL_AON_GPIO_PIN_6
452 * @arg @ref LL_AON_GPIO_PIN_7
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_AON_GPIO_MUX_0
455 * @arg @ref LL_AON_GPIO_MUX_1
456 * @arg @ref LL_AON_GPIO_MUX_2
457 * @arg @ref LL_AON_GPIO_MUX_3
458 * @arg @ref LL_AON_GPIO_MUX_4
459 * @arg @ref LL_AON_GPIO_MUX_5
460 * @arg @ref LL_AON_GPIO_MUX_6
461 * @arg @ref LL_AON_GPIO_MUX_7
462 * @arg @ref LL_AON_GPIO_MUX_8
463 */
464 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mux(uint32_t pin)
465 {
466 if(READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
467 {
468 uint32_t pos = POSITION_VAL(pin) << 2;
469 return (READ_BITS(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
470 }
471 else
472 {
473 return LL_AON_GPIO_MUX_7;
474 }
475 }
476
477 /**
478 * @brief Enable clock output on AON_GPIO_PIN4.
479 *
480 * Register|BitsName
481 * --------|--------
482 * AON_PAD_CLK | AON_PAD_CLK
483 *
484 * @param clk_sel This parameter can be the following values:
485 * @arg @ref LL_CLK_RNG_OSC_32K
486 * @arg @ref LL_CLK_RNG_OSC_2MHZ
487 * @arg @ref LL_CLK_RC_OSC_CLK
488 * @arg @ref LL_CLK_RTC_CLK
489 * @retval None
490 */
491 __STATIC_INLINE void ll_aon_gpio4_enable_clk_output(uint32_t clk_sel)
492 {
493 MODIFY_REG(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
494 AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_CTL_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
495 }
496
497 /**
498 * @brief Disable clock output on AON_GPIO_PIN4.
499 *
500 * Register|BitsName
501 * --------|--------
502 * AON_PAD_CLK | AON_PAD_CLK
503 *
504 * @retval None
505 */
506 __STATIC_INLINE void ll_aon_gpio4_disable_clk_output(void)
507 {
508 CLEAR_BITS(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN);
509 }
510
511 /**
512 * @brief Check if clock output on AON_GPIO_PIN4 is enabled or disabled.
513 *
514 * Register|BitsName
515 * --------|--------
516 * AON_PAD_CLK | AON_PAD_CLK
517 *
518 * @retval State of bit (1 or 0).
519 */
520 __STATIC_INLINE uint32_t ll_aon_gpio4_is_enabled_clk_output(void)
521 {
522 return (READ_BITS(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN);
523 }
524
525 /**
526 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
527 *
528 * Register|BitsName
529 * --------|--------
530 * PWR_RET01 | XO_2MHZ_ENA
531 *
532 * @retval None
533 */
534 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
535 {
536 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
537 }
538
539 /**
540 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
541 *
542 * Register|BitsName
543 * --------|--------
544 * PWR_RET01 | XO_2MHZ_ENA
545 *
546 * @retval None
547 */
548 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
549 {
550 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
551 }
552
553 /**
554 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
555 *
556 * Register|BitsName
557 * --------|--------
558 * PWR_RET01 | XO_2MHZ_ENA
559 *
560 * @retval None
561 */
562 __STATIC_FORCEINLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
563 {
564 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
565 }
566
567 /** @} */
568
569 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
570 * @{
571 */
572
573 /**
574 * @brief Return full input data register value of AON_GPIO.
575 *
576 * Register|BitsName
577 * --------|--------
578 * AON_PAD_CTL1 | O_AON_GPI
579 *
580 * @retval Input data register value of port
581 */
582 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
583 {
584 uint32_t pin_mask = (LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
585 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) >> AON_IO_AON_PAD_CTRL1_IN_VAL_POS);
586 }
587
588 /**
589 * @brief Return if input data level of several AON_GPIO pins is high or low.
590 *
591 * Register|BitsName
592 * --------|--------
593 * AON_PAD_CTL1 | O_AON_GPI
594 *
595 * @param pin_mask This parameter can be a combination of the following values:
596 * @arg @ref LL_AON_GPIO_PIN_0
597 * @arg @ref LL_AON_GPIO_PIN_1
598 * @arg @ref LL_AON_GPIO_PIN_2
599 * @arg @ref LL_AON_GPIO_PIN_3
600 * @arg @ref LL_AON_GPIO_PIN_4
601 * @arg @ref LL_AON_GPIO_PIN_5
602 * @arg @ref LL_AON_GPIO_PIN_6
603 * @arg @ref LL_AON_GPIO_PIN_7
604 * @arg @ref LL_AON_GPIO_PIN_ALL
605 * @retval State of bit (1 or 0).
606 */
607 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_pin(uint32_t pin_mask)
608 {
609 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
610 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
611 }
612
613 /**
614 * @brief Return if output data level of several AON_GPIO pins is high or low.
615 *
616 * Register|BitsName
617 * --------|--------
618 * AON_PAD_CTL1 | AON_GPIO
619 *
620 * @param pin_mask This parameter can be a combination of the following values:
621 * @arg @ref LL_AON_GPIO_PIN_0
622 * @arg @ref LL_AON_GPIO_PIN_1
623 * @arg @ref LL_AON_GPIO_PIN_2
624 * @arg @ref LL_AON_GPIO_PIN_3
625 * @arg @ref LL_AON_GPIO_PIN_4
626 * @arg @ref LL_AON_GPIO_PIN_5
627 * @arg @ref LL_AON_GPIO_PIN_6
628 * @arg @ref LL_AON_GPIO_PIN_7
629 * @arg @ref LL_AON_GPIO_PIN_ALL
630 * @retval State of bit (1 or 0).
631 */
632 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_pin(uint32_t pin_mask)
633 {
634 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
635 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
636 }
637 /**
638 * @brief Write output data register of AON_GPIO.
639 *
640 * Register|BitsName
641 * --------|--------
642 * AON_PAD_CTL1 | AON_GPO
643 *
644 * @param port_value Level value for each pin of the port
645 * @retval None
646 */
647 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
648 {
649 MODIFY_REG(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL, (port_value << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
650 }
651
652 /**
653 * @brief Return full output data register value of AON_GPIO.
654 *
655 * Register|BitsName
656 * --------|--------
657 * AON_PAD_CTL1 | AON_GPO
658 *
659 * @retval Output data register value of port
660 */
661 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
662 {
663 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL) >> AON_IO_AON_PAD_CTRL1_OUT_VAL_POS);
664 }
665
666
667 /**
668 * @brief Set specified AON_GPIO pins to high level
669 *
670 * Register|BitsName
671 * --------|--------
672 * AON_PAD_CTL1 | AON_GPO
673 *
674 * @param pin_mask This parameter can be a combination of the following values:
675 * @arg @ref LL_AON_GPIO_PIN_0
676 * @arg @ref LL_AON_GPIO_PIN_1
677 * @arg @ref LL_AON_GPIO_PIN_2
678 * @arg @ref LL_AON_GPIO_PIN_3
679 * @arg @ref LL_AON_GPIO_PIN_4
680 * @arg @ref LL_AON_GPIO_PIN_5
681 * @arg @ref LL_AON_GPIO_PIN_6
682 * @arg @ref LL_AON_GPIO_PIN_7
683 * @arg @ref LL_AON_GPIO_PIN_ALL
684 * @retval None
685 */
686 __STATIC_FORCEINLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
687 {
688 SET_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
689 }
690
691 /**
692 * @brief Set specified AON_GPIO pins to low level.
693 *
694 * Register|BitsName
695 * --------|--------
696 * AON_PAD_CTL1 | AON_GPO
697 *
698 * @param pin_mask This parameter can be a combination of the following values:
699 * @arg @ref LL_AON_GPIO_PIN_0
700 * @arg @ref LL_AON_GPIO_PIN_1
701 * @arg @ref LL_AON_GPIO_PIN_2
702 * @arg @ref LL_AON_GPIO_PIN_3
703 * @arg @ref LL_AON_GPIO_PIN_4
704 * @arg @ref LL_AON_GPIO_PIN_5
705 * @arg @ref LL_AON_GPIO_PIN_6
706 * @arg @ref LL_AON_GPIO_PIN_7
707 * @arg @ref LL_AON_GPIO_PIN_ALL
708 * @retval None
709 */
710 __STATIC_FORCEINLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
711 {
712 CLEAR_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
713 }
714
715 /**
716 * @brief Toggle data value of specified AON_GPIO pins.
717 *
718 * Register|BitsName
719 * --------|--------
720 * AON_PAD_CTL1 | AON_GPO
721 *
722 * @param pin_mask This parameter can be a combination of the following values:
723 * @arg @ref LL_AON_GPIO_PIN_0
724 * @arg @ref LL_AON_GPIO_PIN_1
725 * @arg @ref LL_AON_GPIO_PIN_2
726 * @arg @ref LL_AON_GPIO_PIN_3
727 * @arg @ref LL_AON_GPIO_PIN_4
728 * @arg @ref LL_AON_GPIO_PIN_5
729 * @arg @ref LL_AON_GPIO_PIN_6
730 * @arg @ref LL_AON_GPIO_PIN_7
731 * @arg @ref LL_AON_GPIO_PIN_ALL
732 * @retval None
733 */
734 __STATIC_FORCEINLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
735 {
736 WRITE_REG(AON_IO->AON_PAD_CTRL1, (READ_REG(AON_IO->AON_PAD_CTRL1)
737 ^ ((pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL)));
738 }
739
740 /** @} */
741
742 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
743 * @{
744 */
745
746 /**
747 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
748 *
749 * Register|BitsName
750 * --------|--------
751 * INTPOLCLR | INTPOLCLR
752 * INTTYPESET | INTTYPESET
753 *
754 * @param pin_mask This parameter can be a combination of the following values:
755 * @arg @ref LL_AON_GPIO_PIN_0
756 * @arg @ref LL_AON_GPIO_PIN_1
757 * @arg @ref LL_AON_GPIO_PIN_2
758 * @arg @ref LL_AON_GPIO_PIN_3
759 * @arg @ref LL_AON_GPIO_PIN_4
760 * @arg @ref LL_AON_GPIO_PIN_5
761 * @arg @ref LL_AON_GPIO_PIN_6
762 * @arg @ref LL_AON_GPIO_PIN_7
763 * @arg @ref LL_AON_GPIO_PIN_ALL
764 * @retval None
765 */
766 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
767 {
768 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
769 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
770 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
771 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
772 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
773 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
774 }
775
776 /**
777 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
778 *
779 * Register|BitsName
780 * --------|--------
781 * INTPOLCLR | INTPOLCLR
782 * INTTYPESET | INTTYPESET
783 *
784 * @param pin_mask This parameter can be a combination of the following values:
785 * @arg @ref LL_AON_GPIO_PIN_0
786 * @arg @ref LL_AON_GPIO_PIN_1
787 * @arg @ref LL_AON_GPIO_PIN_2
788 * @arg @ref LL_AON_GPIO_PIN_3
789 * @arg @ref LL_AON_GPIO_PIN_4
790 * @arg @ref LL_AON_GPIO_PIN_5
791 * @arg @ref LL_AON_GPIO_PIN_6
792 * @arg @ref LL_AON_GPIO_PIN_7
793 * @arg @ref LL_AON_GPIO_PIN_ALL
794 * @retval State of bit (1 or 0)
795 */
796 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
797 {
798 uint32_t invert = ((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
799 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
800 uint32_t edge_type = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
801 return (invert && edge_en && edge_type);
802 }
803
804 /**
805 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
806 *
807 * Register|BitsName
808 * --------|--------
809 * INTPOLSET | INTPOLSET
810 * INTTYPESET | INTTYPESET
811 *
812 * @param pin_mask This parameter can be a combination of the following values:
813 * @arg @ref LL_AON_GPIO_PIN_0
814 * @arg @ref LL_AON_GPIO_PIN_1
815 * @arg @ref LL_AON_GPIO_PIN_2
816 * @arg @ref LL_AON_GPIO_PIN_3
817 * @arg @ref LL_AON_GPIO_PIN_4
818 * @arg @ref LL_AON_GPIO_PIN_5
819 * @arg @ref LL_AON_GPIO_PIN_6
820 * @arg @ref LL_AON_GPIO_PIN_7
821 * @arg @ref LL_AON_GPIO_PIN_ALL
822 * @retval None
823 */
824 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
825 {
826 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
827 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
828 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
829 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
830 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
831 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
832 }
833
834 /**
835 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
836 * @note Please check each device line mapping for AON_GPIO Line availability
837 *
838 * Register|BitsName
839 * --------|--------
840 * INTPOLSET | INTPOLSET
841 * INTTYPESET | INTTYPESET
842 *
843 * @param pin_mask This parameter can be a combination of the following values:
844 * @arg @ref LL_AON_GPIO_PIN_0
845 * @arg @ref LL_AON_GPIO_PIN_1
846 * @arg @ref LL_AON_GPIO_PIN_2
847 * @arg @ref LL_AON_GPIO_PIN_3
848 * @arg @ref LL_AON_GPIO_PIN_4
849 * @arg @ref LL_AON_GPIO_PIN_5
850 * @arg @ref LL_AON_GPIO_PIN_6
851 * @arg @ref LL_AON_GPIO_PIN_7
852 * @arg @ref LL_AON_GPIO_PIN_ALL
853 * @retval State of bit (1 or 0).
854 */
855 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
856 {
857 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
858 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
859 uint32_t edge_type = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
860 return (invert && edge_en && edge_type);
861 }
862
863 /**
864 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
865 *
866 * Register|BitsName
867 * --------|--------
868 * INTPOLSET | INTPOLSET
869 * INTTYPECLR | INTTYPECLR
870 *
871 * @param pin_mask This parameter can be a combination of the following values:
872 * @arg @ref LL_AON_GPIO_PIN_0
873 * @arg @ref LL_AON_GPIO_PIN_1
874 * @arg @ref LL_AON_GPIO_PIN_2
875 * @arg @ref LL_AON_GPIO_PIN_3
876 * @arg @ref LL_AON_GPIO_PIN_4
877 * @arg @ref LL_AON_GPIO_PIN_5
878 * @arg @ref LL_AON_GPIO_PIN_6
879 * @arg @ref LL_AON_GPIO_PIN_7
880 * @arg @ref LL_AON_GPIO_PIN_ALL
881 * @retval None
882 */
883 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
884 {
885 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
886 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
887 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
888 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
889 }
890
891 /**
892 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
893 *
894 * Register|BitsName
895 * --------|--------
896 * INTPOLSET | INTPOLSET
897 * INTTYPECLR | INTTYPECLR
898 *
899 * @param pin_mask This parameter can be a combination of the following values:
900 * @arg @ref LL_AON_GPIO_PIN_0
901 * @arg @ref LL_AON_GPIO_PIN_1
902 * @arg @ref LL_AON_GPIO_PIN_2
903 * @arg @ref LL_AON_GPIO_PIN_3
904 * @arg @ref LL_AON_GPIO_PIN_4
905 * @arg @ref LL_AON_GPIO_PIN_5
906 * @arg @ref LL_AON_GPIO_PIN_6
907 * @arg @ref LL_AON_GPIO_PIN_7
908 * @arg @ref LL_AON_GPIO_PIN_ALL
909 * @retval State of bit (1 or 0).
910 */
911 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
912 {
913 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
914 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
915 return (invert && edge_en );
916 }
917
918 /**
919 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
920 *
921 * Register|BitsName
922 * --------|--------
923 * INTPOLCLR | INTPOLCLR
924 * INTTYPECLR | INTTYPECLR
925 *
926 * @param pin_mask This parameter can be a combination of the following values:
927 * @arg @ref LL_AON_GPIO_PIN_0
928 * @arg @ref LL_AON_GPIO_PIN_1
929 * @arg @ref LL_AON_GPIO_PIN_2
930 * @arg @ref LL_AON_GPIO_PIN_3
931 * @arg @ref LL_AON_GPIO_PIN_4
932 * @arg @ref LL_AON_GPIO_PIN_5
933 * @arg @ref LL_AON_GPIO_PIN_6
934 * @arg @ref LL_AON_GPIO_PIN_7
935 * @arg @ref LL_AON_GPIO_PIN_ALL
936 * @retval None
937 */
938 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
939 {
940 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
941 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
942 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
943 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
944 }
945
946 /**
947 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
948 *
949 * Register|BitsName
950 * --------|--------
951 * INTPOLCLR | INTPOLCLR
952 * INTTYPECLR | INTTYPECLR
953 *
954 * @param pin_mask This parameter can be a combination of the following values:
955 * @arg @ref LL_AON_GPIO_PIN_0
956 * @arg @ref LL_AON_GPIO_PIN_1
957 * @arg @ref LL_AON_GPIO_PIN_2
958 * @arg @ref LL_AON_GPIO_PIN_3
959 * @arg @ref LL_AON_GPIO_PIN_4
960 * @arg @ref LL_AON_GPIO_PIN_5
961 * @arg @ref LL_AON_GPIO_PIN_6
962 * @arg @ref LL_AON_GPIO_PIN_7
963 * @arg @ref LL_AON_GPIO_PIN_ALL
964 * @retval State of bit (1 or 0).
965 */
966 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
967 {
968 uint32_t invert = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
969 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
970 return (invert && edge_en);
971 }
972
973 /**
974 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
975 *
976 * Register|BitsName
977 * --------|--------
978 * INTPOLCLR | INTPOLCLR
979 * INTTYPECLR | INTTYPECLR
980 *
981 * @param pin_mask This parameter can be a combination of the following values:
982 * @arg @ref LL_AON_GPIO_PIN_0
983 * @arg @ref LL_AON_GPIO_PIN_1
984 * @arg @ref LL_AON_GPIO_PIN_2
985 * @arg @ref LL_AON_GPIO_PIN_3
986 * @arg @ref LL_AON_GPIO_PIN_4
987 * @arg @ref LL_AON_GPIO_PIN_5
988 * @arg @ref LL_AON_GPIO_PIN_6
989 * @arg @ref LL_AON_GPIO_PIN_7
990 * @arg @ref LL_AON_GPIO_PIN_ALL
991 * @retval None
992 */
993 __STATIC_INLINE void ll_aon_gpio_enable_both_trigger(uint32_t pin_mask)
994 {
995 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
996 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
997 SET_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en | both);
998 }
999
1000 /**
1001 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
1002 *
1003 * Register|BitsName
1004 * --------|--------
1005 * INTPOLCLR | INTPOLCLR
1006 * INTTYPECLR | INTTYPECLR
1007 *
1008 * @param pin_mask This parameter can be a combination of the following values:
1009 * @arg @ref LL_AON_GPIO_PIN_0
1010 * @arg @ref LL_AON_GPIO_PIN_1
1011 * @arg @ref LL_AON_GPIO_PIN_2
1012 * @arg @ref LL_AON_GPIO_PIN_3
1013 * @arg @ref LL_AON_GPIO_PIN_4
1014 * @arg @ref LL_AON_GPIO_PIN_5
1015 * @arg @ref LL_AON_GPIO_PIN_6
1016 * @arg @ref LL_AON_GPIO_PIN_7
1017 * @arg @ref LL_AON_GPIO_PIN_ALL
1018 * @retval State of bit (1 or 0)
1019 */
1020 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_both_trigger(uint32_t pin_mask)
1021 {
1022 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1023 uint32_t edge_both = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1024 return ( edge_en && edge_both);
1025 }
1026
1027 /**
1028 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
1029 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1030 *
1031 * Register|BitsName
1032 * --------|--------
1033 * INTENSET | INTENSET
1034 *
1035 * @param pin_mask This parameter can be a combination of the following values:
1036 * @arg @ref LL_AON_GPIO_PIN_0
1037 * @arg @ref LL_AON_GPIO_PIN_1
1038 * @arg @ref LL_AON_GPIO_PIN_2
1039 * @arg @ref LL_AON_GPIO_PIN_3
1040 * @arg @ref LL_AON_GPIO_PIN_4
1041 * @arg @ref LL_AON_GPIO_PIN_5
1042 * @arg @ref LL_AON_GPIO_PIN_6
1043 * @arg @ref LL_AON_GPIO_PIN_7
1044 * @arg @ref LL_AON_GPIO_PIN_ALL
1045 * @retval None
1046 */
1047 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
1048 {
1049 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1050 }
1051
1052 /**
1053 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
1054 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1055 *
1056 * Register|BitsName
1057 * --------|--------
1058 * INTENCLR | INTENCLR
1059 *
1060 * @param pin_mask This parameter can be a combination of the following values:
1061 * @arg @ref LL_AON_GPIO_PIN_0
1062 * @arg @ref LL_AON_GPIO_PIN_1
1063 * @arg @ref LL_AON_GPIO_PIN_2
1064 * @arg @ref LL_AON_GPIO_PIN_3
1065 * @arg @ref LL_AON_GPIO_PIN_4
1066 * @arg @ref LL_AON_GPIO_PIN_5
1067 * @arg @ref LL_AON_GPIO_PIN_6
1068 * @arg @ref LL_AON_GPIO_PIN_7
1069 * @arg @ref LL_AON_GPIO_PIN_ALL
1070 * @retval None
1071 */
1072 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
1073 {
1074 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1075 }
1076
1077 /**
1078 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1079 *
1080 * Register|BitsName
1081 * --------|--------
1082 * INTENSET | INTENSET
1083 *
1084 * @param pin_mask This parameter can be a combination of the following values:
1085 * @arg @ref LL_AON_GPIO_PIN_0
1086 * @arg @ref LL_AON_GPIO_PIN_1
1087 * @arg @ref LL_AON_GPIO_PIN_2
1088 * @arg @ref LL_AON_GPIO_PIN_3
1089 * @arg @ref LL_AON_GPIO_PIN_4
1090 * @arg @ref LL_AON_GPIO_PIN_5
1091 * @arg @ref LL_AON_GPIO_PIN_6
1092 * @arg @ref LL_AON_GPIO_PIN_7
1093 * @arg @ref LL_AON_GPIO_PIN_ALL
1094 * @retval State of bit (1 or 0).
1095 */
1096 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1097 {
1098 return ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1099 }
1100
1101 /**
1102 * @brief Get aon gpio enable pins.
1103 *
1104 * Register|BitsName
1105 * --------|--------
1106 * INTENSET | INTENSET
1107 * @retval Returned value can be one of the following values:
1108 * @arg @ref LL_AON_GPIO_PIN_0
1109 * @arg @ref LL_AON_GPIO_PIN_1
1110 * @arg @ref LL_AON_GPIO_PIN_2
1111 * @arg @ref LL_AON_GPIO_PIN_3
1112 * @arg @ref LL_AON_GPIO_PIN_4
1113 * @arg @ref LL_AON_GPIO_PIN_5
1114 * @arg @ref LL_AON_GPIO_PIN_6
1115 * @arg @ref LL_AON_GPIO_PIN_7
1116 * @arg @ref LL_AON_GPIO_PIN_ALL
1117 */
1118 __STATIC_INLINE uint32_t ll_aon_gpio_get_enabled_pin(void)
1119 {
1120 return (READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1121 }
1122
1123 /** @} */
1124
1125 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
1126 * @{
1127 */
1128
1129 /**
1130 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
1131 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1132 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1133 *
1134 * Register|BitsName
1135 * --------|--------
1136 * INTSTATUS | INTSTATUS
1137 *
1138 * @param pin_mask This parameter can be a combination of the following values:
1139 * @arg @ref LL_AON_GPIO_PIN_0
1140 * @arg @ref LL_AON_GPIO_PIN_1
1141 * @arg @ref LL_AON_GPIO_PIN_2
1142 * @arg @ref LL_AON_GPIO_PIN_3
1143 * @arg @ref LL_AON_GPIO_PIN_4
1144 * @arg @ref LL_AON_GPIO_PIN_5
1145 * @arg @ref LL_AON_GPIO_PIN_6
1146 * @arg @ref LL_AON_GPIO_PIN_7
1147 * @arg @ref LL_AON_GPIO_PIN_ALL
1148 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1149 */
1150 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1151 {
1152 return (READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1153 }
1154
1155 /**
1156 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1157 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1158 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1159 *
1160 * Register|BitsName
1161 * --------|--------
1162 * INTSTATUS | INTSTATUS
1163 *
1164 * @param pin_mask This parameter can be a combination of the following values:
1165 * @arg @ref LL_AON_GPIO_PIN_0
1166 * @arg @ref LL_AON_GPIO_PIN_1
1167 * @arg @ref LL_AON_GPIO_PIN_2
1168 * @arg @ref LL_AON_GPIO_PIN_3
1169 * @arg @ref LL_AON_GPIO_PIN_4
1170 * @arg @ref LL_AON_GPIO_PIN_5
1171 * @arg @ref LL_AON_GPIO_PIN_6
1172 * @arg @ref LL_AON_GPIO_PIN_7
1173 * @arg @ref LL_AON_GPIO_PIN_ALL
1174 * @retval State of bit (1 or 0).
1175 */
1176 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1177 {
1178 return ((READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1179 }
1180
1181 /**
1182 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1183 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1184 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1185 *
1186 * Register|BitsName
1187 * --------|--------
1188 * INTSTATUS | INTSTATUS
1189 *
1190 * @param pin_mask This parameter can be a combination of the following values:
1191 * @arg @ref LL_AON_GPIO_PIN_0
1192 * @arg @ref LL_AON_GPIO_PIN_1
1193 * @arg @ref LL_AON_GPIO_PIN_2
1194 * @arg @ref LL_AON_GPIO_PIN_3
1195 * @arg @ref LL_AON_GPIO_PIN_4
1196 * @arg @ref LL_AON_GPIO_PIN_5
1197 * @arg @ref LL_AON_GPIO_PIN_6
1198 * @arg @ref LL_AON_GPIO_PIN_7
1199 * @arg @ref LL_AON_GPIO_PIN_ALL
1200 * @retval None
1201 */
1202 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1203 {
1204 CLEAR_BITS(AON_IO->EXT_WAKEUP_STAT, pin_mask);
1205 }
1206
1207 /**
1208 * @brief Indicate if the AON GPIO event flag is set or not.
1209 * @note This bit is set by hardware when system wakeup by AON GPIO.
1210 * It can be cleared by writing 0 to this bit.
1211 *
1212 * Register|BitsName
1213 * --------|--------
1214 * SLP_EVENT | AON GPIO
1215 *
1216 * @retval State of bit (1 or 0).
1217 */
1218 __STATIC_INLINE uint32_t ll_aon_gpio_read_event_flag_it(void)
1219 {
1220 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1221 }
1222
1223 /**
1224 * @brief Clear AON GPIO event interrupt flag.
1225 *
1226 * Register|BitsName
1227 * --------|--------
1228 * SLP_EVENT| AON GPIO
1229 *
1230 * @retval None
1231 */
1232 __STATIC_INLINE void ll_aon_gpio_clear_event_flag_it(void)
1233 {
1234 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);
1235 }
1236
1237 /** @} */
1238
1239 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1240 * @{
1241 */
1242 /**
1243 * @brief Initialize AON_GPIO registers according to the specified.
1244 * parameters in p_aon_gpio_init.
1245 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1246 * information for the specified AON_GPIO peripheral.
1247 * @retval An error_status_t enumeration value:
1248 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1249 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1250 */
1251 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1252
1253 /** @} */
1254
1255 /** @} */
1256
1257 #endif /* AON */
1258
1259 #ifdef __cplusplus
1260 }
1261 #endif
1262
1263 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1264
1265 /** @} */
1266
1267 /** @} */
1268
1269 /** @} */