gr55xx_hal_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_DMA DMA
47 * @brief DMA HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_dma.h"
61 #include "gr55xx_hal_def.h"
62 #include <stdbool.h>
63
64 /* Exported types ------------------------------------------------------------*/
65 /** @addtogroup HAL_DMA_ENUMERATIONS Enumerations
66 * @{
67 */
68
69 /** @defgroup HAL_DMA_state HAL DMA state
70 * @{
71 */
72
73 /**
74 * @brief HAL DMA State Enumerations definition
75 */
76 typedef enum
77 {
78 HAL_DMA_STATE_RESET = 0x00U, /**< DMA not yet initialized or disabled */
79 HAL_DMA_STATE_READY = 0x01U, /**< DMA process success and ready for use */
80 HAL_DMA_STATE_BUSY = 0x02U, /**< DMA process is ongoing */
81 HAL_DMA_STATE_TIMEOUT = 0x03U, /**< DMA timeout state */
82 HAL_DMA_STATE_ERROR = 0x04U, /**< DMA error state */
83 } hal_dma_state_t;
84 /** @} */
85
86 /** @defgroup HAL_DMA_channel HAL DMA channel
87 * @{
88 */
89
90 /**
91 * @brief HAL DMA Channel Enumerations definition
92 */
93 typedef enum
94 {
95 DMA_Channel0 = 0U, /**< Channel 0 */
96 DMA_Channel1 = 1U, /**< Channel 1 */
97 DMA_Channel2 = 2U, /**< Channel 2 */
98 DMA_Channel3 = 3U, /**< Channel 3 */
99 DMA_Channel4 = 4U, /**< Channel 4 */
100 DMA_Channel5 = 5U, /**< Channel 5 */
101 DMA_Channel_NUM_MAX /**< Only for check parameter, not used as input parameters. */
102 } dma_channel_t;
103 /** @} */
104
105 /** @defgroup HAL_DMA_callback_ID HAL DMA callback ID
106 * @{
107 */
108
109 /**
110 * @brief HAL DMA Callback ID Enumerations definition
111 */
112 typedef enum
113 {
114 HAL_DMA_XFER_TFR_CB_ID = 0x00, /**< Full transfer */
115 HAL_DMA_XFER_BLK_CB_ID = 0x01, /**< Block transfer */
116 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /**< Error */
117 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /**< Abort */
118 HAL_DMA_XFER_ALL_CB_ID = 0x04 /**< All */
119 } hal_dma_callback_id_t;
120 /** @} */
121
122 /** @} */
123
124
125 /** @addtogroup HAL_DMA_STRUCTURES Structures
126 * @{
127 */
128
129 /** @defgroup DMA_Configuration DMA Configuration
130 * @{
131 */
132
133 /**
134 * @brief LL DMA block definition
135 */
136 typedef struct dma_block_config
137 {
138
139 uint32_t src_address; /**< Specifies the Destination base address for DMA transfer.
140 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
141
142 uint32_t dst_address; /**< Specifies the Source base address for DMA transfer.
143 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
144
145 struct dma_block_config *p_lli; /**< Specifies the linked list point for DMA transfer.
146 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
147
148 uint32_t CTL_L; /**< Specifies the CRL[31:0] for DMA transfer.
149 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
150
151 uint32_t CTL_H; /**< Specifies the CRL[63:32] for DMA transfer.
152 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
153
154 uint32_t src_status; /**< Specifies the Destination base address for DMA transfer.
155 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
156
157 uint32_t dst_status; /**< Specifies the Source base address for DMA transfer.
158 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
159 }dma_block_config_t;
160
161 /**
162 * @brief LL DMA scatter config definition
163 */
164 typedef struct dma_scatter_config
165 {
166
167 uint32_t dst_scatter_en; /**< Specifies the destination scatter function enable.
168 This parameter can be a value of @ref DMA_DST_SCATTER_EN.*/
169
170 uint32_t dst_dsi; /**< Specifies the destination scatter tnterval.
171 This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFF.*/
172
173 uint32_t dst_dsc; /**< Specifies the destination scatter count.
174 This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF.*/
175 }dma_scatter_config_t;
176
177 /**
178 * @brief LL DMA gather config definition
179 */
180 typedef struct dma_gather_config
181 {
182
183 uint32_t src_gather_en; /**< Specifies the channel source gather function enable.
184 This parameter can be a value of @ref DMA_SRC_GATHER_EN. */
185
186 uint32_t src_sgi; /**< Specifies the channel source gather interval.
187 This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFF. */
188
189 uint32_t src_sgc; /**< Specifies the channel source gather count.
190 This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF. */
191 }dma_gather_config_t;
192
193 /**
194 * @brief LL DMA llp config definition
195 */
196 typedef struct dma_llp_config
197 {
198
199 uint32_t llp_src_en; /**< Specifies the source block chaining enable.
200 This parameter can be a value DMA_LLP_SRC_EN.*/
201
202 uint32_t llp_src_writeback; /**< Specifies the source writeback the source status information.
203 This parameter can be a value between 0x0 and 0xFFFFFFFF*/
204
205 uint32_t llp_dst_en; /**< Specifies the destination writeback the source status information.
206 This parameter can be a value DMA_LLP_DST_EN.*/
207
208 uint32_t llp_dst_writeback; /**< Specifies the detination block chaining enable.
209 This parameter can be a value between 0x0 and 0xFFFFFFFF*/
210
211 struct dma_block_config *head_lli; /**< Specifies the linked list pointer.
212 This parameter can be a value between 0x0 and 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)*/
213 }dma_llp_config_t;
214
215 /**
216 * @brief LL DMA sg and llp config definition
217 */
218 typedef struct dma_sg_llp_config
219 {
220
221 dma_scatter_config_t scatter_config; /**< Specifies the source block chaining enable.
222 This parameter can be a value DMA_LLP_SRC_EN.*/
223
224 dma_gather_config_t gather_config; /**< Specifies the destination block chaining enable.
225 This parameter can be a value DMA_LLP_DST_EN.*/
226
227 dma_llp_config_t llp_config; /**< Specifies the linked list pointer.
228 This parameter can be a value between 0x0 and 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)*/
229 }dma_sg_llp_config_t;
230
231 /**
232 * @brief DMA Configuration Structure definition
233 */
234 typedef struct _dma_init
235 {
236 uint32_t src_request; /**< Specifies the source request selected for the specified channel.
237 This parameter can be a value of @ref DMA_request */
238
239 uint32_t dst_request; /**< Specifies the destination request selected for the specified channel.
240 This parameter can be a value of @ref DMA_request */
241
242 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
243 from memory to memory or from peripheral to memory.
244 This parameter can be a value of @ref DMA_Data_transfer_direction */
245
246 uint32_t src_increment; /**< Specifies whether the srouce address register should be incremented or decrement or not.
247 This parameter can be a value of @ref DMA_Source_incremented_mode */
248
249 uint32_t dst_increment; /**< Specifies whether the destination address register should be incremented or decrement or not.
250 This parameter can be a value of @ref DMA_Destination_incremented_mode */
251
252 uint32_t src_data_alignment; /**< Specifies the source data width.
253 This parameter can be a value of @ref DMA_Source_data_size */
254
255 uint32_t dst_data_alignment; /**< Specifies the destination data width.
256 This parameter can be a value of @ref DMA_Destination_data_size */
257
258 uint32_t mode; /**< Specifies the operation mode of the DMA Channel(Normal or Circular).
259 This parameter can be a value of @ref DMA_mode
260 @note The circular buffer mode cannot be used if the memory-to-memory
261 data transfer is configured on the selected Channel */
262
263 uint32_t priority; /**< Specifies the software priority for the DMA Channel.
264 This parameter can be a value of @ref DMA_Priority_level */
265 } dma_init_t;
266
267 /** @} */
268
269 /** @defgroup DMA_handle DMA handle
270 * @{
271 */
272
273 /**
274 * @brief DMA handle Structure definition
275 */
276 typedef struct _dma_handle
277 {
278 dma_regs_t *p_instance; /**< DMA registers base address */
279
280 dma_channel_t channel; /**< DMA Channel Number */
281
282 dma_init_t init; /**< DMA communication parameters */
283
284 hal_lock_t lock; /**< DMA locking object */
285
286 __IO hal_dma_state_t state; /**< DMA transfer state */
287
288 void *p_parent; /**< Parent object state */
289
290 void (* xfer_tfr_callback)(struct _dma_handle *p_dma); /**< DMA transfer complete callback */
291
292 void (* xfer_blk_callback)(struct _dma_handle *p_dma); /**< DMA block complete callback */
293
294 void (* xfer_error_callback)(struct _dma_handle *p_dma); /**< DMA transfer error callback */
295
296 void (* xfer_abort_callback)(struct _dma_handle *p_dma); /**< DMA transfer abort callback */
297
298 __IO uint32_t error_code; /**< DMA Error code */
299
300 uint32_t retention[7]; /**< DMA important register information. */
301 } dma_handle_t;
302
303 /** @} */
304
305 /** @} */
306
307
308 /**
309 * @defgroup HAL_DMA_MACRO Defines
310 * @{
311 */
312
313 /* Exported constants --------------------------------------------------------*/
314 /** @defgroup DMA_Exported_Constants DMA Exported Constants
315 * @{
316 */
317
318 /** @defgroup DMA_Error_Code DMA Error Code
319 * @{
320 */
321 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /**< No error */
322 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /**< Transfer error */
323 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /**< no ongoing transfer */
324 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /**< Timeout error */
325 #define HAL_DMA_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /**< Invalid parameters error */
326 /** @} */
327
328 /** @defgroup DMA_request DMA request definitions
329 * @{
330 */
331 /********************************* definition for DMA0 HS **************************************/
332 #define DMA0_REQUEST_OSPI_TX LL_DMA0_PERIPH_OSPI_TX /**< DMA OSPI transmit request */
333 #define DMA0_REQUEST_OSPI_RX LL_DMA0_PERIPH_OSPI_RX /**< DMA OSPI transmit request */
334 #define DMA0_REQUEST_QSPI0_TX LL_DMA0_PERIPH_QSPI0_TX /**< DMA QSPIM0 transmit request */
335 #define DMA0_REQUEST_QSPI0_RX LL_DMA0_PERIPH_QSPI0_RX /**< DMA QSPIM0 transmit request */
336 #define DMA0_REQUEST_QSPI1_TX LL_DMA0_PERIPH_QSPI1_TX /**< DMA QSPIM1 TX transmit request */
337 #define DMA0_REQUEST_QSPI1_RX LL_DMA0_PERIPH_QSPI1_RX /**< DMA QSPIM1 RX transmit request */
338 #define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
339 #define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX /**< DMA SPIM RX transmit request */
340 #define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX /**< DMA SPIS TX transmit request */
341 #define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX /**< DMA SPIS RX transmit request */
342 #define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX /**< DMA UART0 TX transmit request */
343 #define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX /**< DMA UART0 RX transmit request */
344 #define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX /**< DMA UART1 TX transmit request */
345 #define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX /**< DMA UART1 RX transmit request */
346 #define DMA0_REQUEST_UART2_TX LL_DMA0_PERIPH_UART2_TX /**< DMA UART2 TX transmit request */
347 #define DMA0_REQUEST_UART2_RX LL_DMA0_PERIPH_UART2_RX /**< DMA UART2 RX transmit request */
348 #define DMA0_REQUEST_UART3_TX LL_DMA0_PERIPH_UART3_TX /**< DMA UART3 TX transmit request */
349 #define DMA0_REQUEST_UART3_RX LL_DMA0_PERIPH_UART3_RX /**< DMA UART3 RX transmit request */
350 #define DMA0_REQUEST_UART4_TX LL_DMA0_PERIPH_UART4_TX /**< DMA UART4 TX transmit request */
351 #define DMA0_REQUEST_UART4_RX LL_DMA0_PERIPH_UART4_RX /**< DMA UART4 RX transmit request */
352 #define DMA0_REQUEST_I2C2_TX LL_DMA0_PERIPH_I2C2_TX /**< DMA I2C2 TX transmit request */
353 #define DMA0_REQUEST_I2C2_RX LL_DMA0_PERIPH_I2C2_RX /**< DMA I2C2 RX transmit request */
354 #define DMA0_REQUEST_I2C3_TX LL_DMA0_PERIPH_I2C3_TX /**< DMA I2C3 TX transmit request */
355 #define DMA0_REQUEST_I2C3_RX LL_DMA0_PERIPH_I2C3_RX /**< DMA I2C3 RX transmit request */
356 #define DMA0_REQUEST_I2C4_TX LL_DMA0_PERIPH_I2C4_TX /**< DMA I2C4 TX transmit request */
357 #define DMA0_REQUEST_I2C4_RX LL_DMA0_PERIPH_I2C4_RX /**< DMA I2C4 RX transmit request */
358 #define DMA0_REQUEST_I2C5_TX LL_DMA0_PERIPH_I2C5_TX /**< DMA I2C5 TX transmit request */
359 #define DMA0_REQUEST_I2C5_RX LL_DMA0_PERIPH_I2C5_RX /**< DMA I2C5 RX transmit request */
360 #define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC /**< DMA SNSADC transmit request */
361 #define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM /**< DMA is Memory transmit request */
362
363 /********************************* definition for DMA1 HS**************************************/
364 #define DMA1_REQUEST_OSPI_TX LL_DMA1_PERIPH_OSPI_TX /**< DMA OSPI transmit request */
365 #define DMA1_REQUEST_OSPI_RX LL_DMA1_PERIPH_OSPI_RX /**< DMA OSPI transmit request */
366 #define DMA1_REQUEST_QSPI1_TX LL_DMA1_PERIPH_QSPI1_TX /**< DMA QSPIM1 TX transmit request */
367 #define DMA1_REQUEST_QSPI1_RX LL_DMA1_PERIPH_QSPI1_RX /**< DMA QSPIM1 RX transmit request */
368 #define DMA1_REQUEST_QSPI2_TX LL_DMA1_PERIPH_QSPI2_TX /**< DMA QSPIM2 TX transmit request */
369 #define DMA1_REQUEST_QSPI2_RX LL_DMA1_PERIPH_QSPI2_RX /**< DMA QSPIM2 RX transmit request */
370 #define DMA1_REQUEST_SPIM_TX LL_DMA1_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
371 #define DMA1_REQUEST_SPIM_RX LL_DMA1_PERIPH_SPIM_RX /**< DMA SPIM RX transmit request */
372 #define DMA1_REQUEST_DSPIM_TX LL_DMA1_PERIPH_DSPIM_TX /**< DMA DSPIM TX transmit request */
373 #define DMA1_REQUEST_DSPIM_RX LL_DMA1_PERIPH_DSPIM_RX /**< DMA DSPIM RX transmit request */
374 #define DMA1_REQUEST_I2S_M_TX LL_DMA1_PERIPH_I2S_M_TX /**< DMA I2S_M TX transmit request */
375 #define DMA1_REQUEST_I2S_M_RX LL_DMA1_PERIPH_I2S_M_RX /**< DMA I2S_M RX transmit request */
376 #define DMA1_REQUEST_I2S_S_TX LL_DMA1_PERIPH_I2S_S_TX /**< DMA I2S_S TX transmit request */
377 #define DMA1_REQUEST_I2S_S_RX LL_DMA1_PERIPH_I2S_S_RX /**< DMA I2S_S RX transmit request */
378 #define DMA1_REQUEST_PDM_TX LL_DMA1_PERIPH_PDM_TX /**< DMA PDM TX transmit request */
379 #define DMA1_REQUEST_I2C0_TX LL_DMA1_PERIPH_I2C0_TX /**< DMA I2C0 TX transmit request */
380 #define DMA1_REQUEST_I2C0_RX LL_DMA1_PERIPH_I2C0_RX /**< DMA I2C0 RX transmit request */
381 #define DMA1_REQUEST_I2C1_TX LL_DMA1_PERIPH_I2C1_TX /**< DMA I2C1 TX transmit request */
382 #define DMA1_REQUEST_I2C1_RX LL_DMA1_PERIPH_I2C1_RX /**< DMA I2C1 RX transmit request */
383 #define DMA1_REQUEST_UART0_TX LL_DMA1_PERIPH_UART0_TX /**< DMA UART0 TX transmit request */
384 #define DMA1_REQUEST_UART0_RX LL_DMA1_PERIPH_UART0_RX /**< DMA UART0 RX transmit request */
385 #define DMA1_REQUEST_UART3_TX LL_DMA1_PERIPH_UART3_TX /**< DMA UART3 TX transmit request */
386 #define DMA1_REQUEST_UART3_RX LL_DMA1_PERIPH_UART3_RX /**< DMA UART3 RX transmit request */
387 #define DMA1_REQUEST_UART4_TX LL_DMA1_PERIPH_UART4_TX /**< DMA UART4 TX transmit request */
388 #define DMA1_REQUEST_UART4_RX LL_DMA1_PERIPH_UART4_RX /**< DMA UART4 RX transmit request */
389 #define DMA1_REQUEST_UART5_TX LL_DMA1_PERIPH_UART5_TX /**< DMA UART5 TX transmit request */
390 #define DMA1_REQUEST_UART5_RX LL_DMA1_PERIPH_UART5_RX /**< DMA UART5 RX transmit request */
391 #define DMA1_REQUEST_MEM LL_DMA1_PERIPH_MEM /**< DMA is Memory transmit request */
392 /** @} */
393
394 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
395 * @{
396 */
397 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /**< Memory to memory direction */
398 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /**< Memory to peripheral direction */
399 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /**< Peripheral to memory direction */
400 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH /**< Peripheral to Peripheral direction */
401 /** @} */
402
403 /** @defgroup DMA_Source_incremented_mode DMA Source Incremented Mode
404 * @{
405 */
406 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT /**< Source increment mode */
407 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT /**< Source decrement mode */
408 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE /**< Source no change mode */
409 /** @} */
410
411 /** @defgroup DMA_Destination_incremented_mode DMA Destination Incremented Mode
412 * @{
413 */
414 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT /**< Destination increment mode */
415 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT /**< Destination decrement mode */
416 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE /**< Destination no change mode */
417 /** @} */
418
419 /** @defgroup DMA_Source_data_size DMA Source Data Size Alignment
420 * @{
421 */
422 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE /**< Source data alignment : Byte */
423 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD /**< Source data alignment : HalfWord */
424 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD /**< Source data alignment : Word */
425 /** @} */
426
427 /** @defgroup DMA_Destination_data_size DMA Destination Data Size Alignment
428 * @{
429 */
430 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE /**< Destination data alignment : Byte */
431 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD /**< Destination data alignment : HalfWord */
432 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD /**< Destination data alignment : Word */
433 /** @} */
434
435 /** @defgroup DMA_mode DMA Mode
436 * @{
437 */
438 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK /**< Normal Mode */
439 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD /**< Circular Mode */
440
441 /** @} */
442
443 /** @defgroup DMA_Priority_level DMA Priority Level
444 * @{
445 */
446 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0 /**< Priority level : Low */
447 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_1 /**< Priority level : Medium */
448 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_2 /**< Priority level : High */
449 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_3 /**< Priority level : Very High */
450
451 /** @} */
452
453 /** @defgroup DMA_LLP_DST_EN Destination LLP Enable
454 * @{
455 */
456 #define DMA_LLP_DST_ENABLE LL_DMA_LLP_DST_ENABLE /**< Destination LLP Enable */
457 #define DMA_LLP_DST_DISABLE LL_DMA_LLP_DST_DISABLE /**< Destination LLP Disable */
458 /** @} */
459
460 /** @defgroup DMA_LLP_SRC_EN Source LLP Enable
461 * @{
462 */
463 #define DMA_LLP_SRC_ENABLE LL_DMA_LLP_SRC_ENABLE /**< Source LLP Enable */
464 #define DMA_LLP_SRC_DISABLE LL_DMA_LLP_SRC_DISABLE /**< Source LLP Disable */
465 /** @} */
466
467 /** @defgroup DMA_DST_SCATTER_EN Destination Scatter Enable
468 * @{
469 */
470 #define DMA_DST_SCATTER_ENABLE LL_DMA_DST_SCATTER_ENABLE /**< Destination Scatter Enable */
471 #define DMA_DST_SCATTER_DISABLE LL_DMA_DST_SCATTER_DISABLE /**< Destination Scatter Disable */
472 /** @} */
473
474 /** @defgroup DMA_SRC_GATHER_EN Source Gather Enable
475 * @{
476 */
477 #define DMA_SRC_GATHER_ENABLE LL_DMA_SRC_GATHER_ENABLE /**< Source Gather Enable */
478 #define DMA_SRC_GATHER_DISABLE LL_DMA_SRC_GATHER_DISABLE /**< Source Gather Disable */
479 /** @} */
480
481 /** @} */
482
483 /* Private macros ------------------------------------------------------------*/
484 /** @defgroup DMA_Private_Macro DMA Private Macros
485 * @{
486 */
487
488 /** @brief Check if DMA instance is valid.
489 * @param __p_instance__ DMA instance.
490 * @retval SET (__p_instance__ is valid) or RESET (__p_instance__ is invalid)
491 */
492 #define IS_DMA_ALL_P_INSTANCE(__p_instance__) (((__p_instance__) == DMA0) || \
493 ((__p_instance__) == DMA1))
494 /** @brief Check if DMA channel instance is valid.
495 * @param __instance__ DMA channel instance.
496 * @retval SET (__instance__ is valid) or RESET (__instance__ is invalid)
497 */
498
499 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
500 ((__instance__) == DMA_Channel1) || \
501 ((__instance__) == DMA_Channel2) || \
502 ((__instance__) == DMA_Channel3) || \
503 ((__instance__) == DMA_Channel4) || \
504 ((__instance__) == DMA_Channel5))
505
506
507 /** @brief Check if DMA request is valid.
508 * @param __REQUEST__ DMA request.
509 * @retval SET (__REQUEST__ is valid) or RESET (__REQUEST__ is invalid)
510 */
511
512 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA0_REQUEST_QSPI0_TX) || \
513 ((__REQUEST__) == DMA0_REQUEST_QSPI0_RX) || \
514 ((__REQUEST__) == DMA0_REQUEST_SPIM_TX) || \
515 ((__REQUEST__) == DMA0_REQUEST_SPIM_RX) || \
516 ((__REQUEST__) == DMA0_REQUEST_SPIS_TX) || \
517 ((__REQUEST__) == DMA0_REQUEST_SPIS_RX) || \
518 ((__REQUEST__) == DMA0_REQUEST_UART0_TX) || \
519 ((__REQUEST__) == DMA0_REQUEST_UART0_RX) || \
520 ((__REQUEST__) == DMA0_REQUEST_UART1_TX) || \
521 ((__REQUEST__) == DMA0_REQUEST_UART1_RX) || \
522 ((__REQUEST__) == DMA0_REQUEST_SNSADC) || \
523 ((__REQUEST__) == DMA0_REQUEST_QSPI1_TX) || \
524 ((__REQUEST__) == DMA0_REQUEST_QSPI1_RX) || \
525 ((__REQUEST__) == DMA0_REQUEST_MEM) || \
526 ((__REQUEST__) == DMA1_REQUEST_QSPI1_TX) || \
527 ((__REQUEST__) == DMA1_REQUEST_QSPI1_RX) || \
528 ((__REQUEST__) == DMA1_REQUEST_QSPI2_TX) || \
529 ((__REQUEST__) == DMA1_REQUEST_QSPI2_RX) || \
530 ((__REQUEST__) == DMA1_REQUEST_SPIM_TX) || \
531 ((__REQUEST__) == DMA1_REQUEST_SPIM_RX) || \
532 ((__REQUEST__) == DMA1_REQUEST_DSPIM_TX) || \
533 ((__REQUEST__) == DMA1_REQUEST_DSPIM_RX) || \
534 ((__REQUEST__) == DMA1_REQUEST_I2S_M_TX) || \
535 ((__REQUEST__) == DMA1_REQUEST_I2S_M_RX) || \
536 ((__REQUEST__) == DMA1_REQUEST_I2S_S_TX) || \
537 ((__REQUEST__) == DMA1_REQUEST_I2S_S_RX) || \
538 ((__REQUEST__) == DMA1_REQUEST_PDM_TX) || \
539 ((__REQUEST__) == DMA1_REQUEST_GPADC) || \
540 ((__REQUEST__) == DMA1_REQUEST_I2C0_TX) || \
541 ((__REQUEST__) == DMA1_REQUEST_I2C0_RX) || \
542 ((__REQUEST__) == DMA1_REQUEST_I2C1_TX) || \
543 ((__REQUEST__) == DMA1_REQUEST_I2C1_RX) || \
544 ((__REQUEST__) == DMA1_REQUEST_MEM))
545
546 /** @brief Check if DMA direction is valid.
547 * @param __DIRECTION__ DMA direction.
548 * @retval SET (__DIRECTION__ is valid) or RESET (__DIRECTION__ is invalid)
549 */
550 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
551 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
552 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
553 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
554
555 /** @brief Check if DMA buffer size is valid.
556 * @param __SIZE__ DMA buffer size.
557 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
558 */
559 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) <= 0xFFF))
560
561 /** @brief Check if DMA source address increment state is valid.
562 * @param __STATE__ DMA source address increment state.
563 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
564 */
565 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
566 ((__STATE__) == DMA_SRC_DECREMENT) || \
567 ((__STATE__) == DMA_SRC_NO_CHANGE))
568
569 /** @brief Check if DMA destination address increment state is valid.
570 * @param __STATE__ DMA destination address increment state.
571 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
572 */
573 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
574 ((__STATE__) == DMA_DST_DECREMENT) || \
575 ((__STATE__) == DMA_DST_NO_CHANGE))
576
577 /** @brief Check if DMA source data size is valid.
578 * @param __SIZE__ DMA source data size.
579 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
580 */
581 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
582 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
583 ((__SIZE__) == DMA_SDATAALIGN_WORD))
584
585 /** @brief Check if DMA destination data size is valid.
586 * @param __SIZE__ DMA destination data size.
587 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
588 */
589 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
590 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
591 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
592
593 /** @brief Check if DMA mode is valid.
594 * @param __MODE__ DMA mode.
595 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
596 */
597 #define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_NORMAL ) || \
598 ((__MODE__) == DMA_CIRCULAR))
599
600 /** @brief Check if DMA priority is valid.
601 * @param __PRIORITY__ DMA priority.
602 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid)
603 */
604 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
605 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
606 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
607 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
608
609 /** @brief Check if DMA Source Gather Enable is valid.
610 * @param __VALUE__ DMA SRC_GATHER_EN.
611 * @retval SET (__VALUE__ is valid) or RESET (__VALUE__ is invalid)
612 */
613 #define IS_DMA_SRC_GATHER_EN(__VALUE__) (((__VALUE__) == DMA_SRC_GATHER_DISABLE) || \
614 ((__VALUE__) == DMA_SRC_GATHER_ENABLE))
615
616 /** @brief Check if DMA Destination Scatter Enable is valid.
617 * @param __VALUE__ DMA DST_SCATTER.
618 * @retval SET (__VALUE__ is valid) or RESET (__VALUE__ is invalid)
619 */
620 #define IS_DMA_DST_SCATTER_EN(__VALUE__) (((__VALUE__) == DMA_DST_SCATTER_DISABLE) || \
621 ((__VALUE__) == DMA_DST_SCATTER_ENABLE))
622
623 /** @brief Check if DMA Source LLP Enable is valid.
624 * @param __VALUE__ DMA LLP_SRC_EN.
625 * @retval SET (__VALUE__ is valid) or RESET (__VALUE__ is invalid)
626 */
627 #define IS_DMA_LLP_SRC_EN(__VALUE__) (((__VALUE__) ==DMA_LLP_SRC_DISABLE) || \
628 ((__VALUE__) ==DMA_LLP_SRC_ENABLE))
629
630 /** @brief Check if DMA Destination LLP Enable is valid.
631 * @param __VALUE__ DMA LLP_DST_EN.
632 * @retval SET (__VALUE__ is valid) or RESET (__VALUE__ is invalid)
633 */
634 #define IS_DMA_LLP_DST_EN(__VALUE__) (((__VALUE__) ==DMA_LLP_DST_DISABLE) || \
635 ((__VALUE__) ==DMA_LLP_DST_ENABLE))
636
637 /** @} */
638
639 /** @} */
640
641
642 /* Exported functions --------------------------------------------------------*/
643 /** @addtogroup HAL_DMA_DRIVER_FUNCTIONS Functions
644 * @{
645 */
646
647 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
648 * @brief Initialization and de-initialization functions
649 *
650 @verbatim
651 ===============================================================================
652 ##### Initialization and de-initialization functions #####
653 ===============================================================================
654 [..]
655 This section provides functions allowing to initialize the DMA Channel source
656 and destination addresses, incrementation and data sizes, transfer direction,
657 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
658 [..]
659 The hal_dma_init() function follows the DMA configuration procedures as described in
660 reference manual.
661
662 @endverbatim
663 * @{
664 */
665
666 /**
667 ****************************************************************************************
668 * @brief Initialize the DMA according to the specified
669 * parameters in the dma_init_t and initialize the associated handle.
670 *
671 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
672 *
673 * @retval ::HAL_OK: Operation is OK.
674 * @retval ::HAL_ERROR: Parameter error or operation not supported.
675 * @retval ::HAL_BUSY: Driver is busy.
676 * @retval ::HAL_TIMEOUT: Timeout occurred.
677 ****************************************************************************************
678 */
679 hal_status_t hal_dma_init(dma_handle_t *p_dma);
680
681 /**
682 ****************************************************************************************
683 * @brief De-initialize the DMA peripheral.
684 *
685 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
686 *
687 * @retval ::HAL_OK: Operation is OK.
688 * @retval ::HAL_ERROR: Parameter error or operation not supported.
689 * @retval ::HAL_BUSY: Driver is busy.
690 * @retval ::HAL_TIMEOUT: Timeout occurred.
691 ****************************************************************************************
692 */
693 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
694
695 /** @} */
696
697
698 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
699 * @brief Input and Output operation functions
700 *
701 @verbatim
702 ===============================================================================
703 ##### IO operation functions #####
704 ===============================================================================
705 [..] This section provides functions allowing to:
706 (+) Configure the source, destination address and data length and Start DMA transfer
707 (+) Configure the source, destination address and data length and
708 Start DMA transfer with interrupt
709 (+) Abort DMA transfer
710 (+) Poll for transfer complete
711 (+) Handle DMA interrupt request
712
713 @endverbatim
714 * @{
715 */
716
717 /**
718 ****************************************************************************************
719 * @brief Start the DMA Transfer.
720 *
721 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
722 * @param[in] src_address: The source memory Buffer address
723 * @param[in] dst_address: The destination memory Buffer address
724 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
725 *
726 * @retval ::HAL_OK: Operation is OK.
727 * @retval ::HAL_ERROR: Parameter error or operation not supported.
728 * @retval ::HAL_BUSY: Driver is busy.
729 * @retval ::HAL_TIMEOUT: Timeout occurred.
730 ****************************************************************************************
731 */
732 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
733
734 /**
735 ****************************************************************************************
736 * @brief Start the DMA Transfer.
737 *
738 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
739 * @param[in] src_address: The source memory Buffer address
740 * @param[in] dst_address: The destination memory Buffer address
741 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
742 * @param[in] sg_llp_config: The config of source and destination.
743
744 * @retval ::HAL_OK: Operation is OK.
745 * @retval ::HAL_ERROR: Parameter error or operation not supported.
746 * @retval ::HAL_BUSY: Driver is busy.
747 * @retval ::HAL_TIMEOUT: Timeout occurred.
748 ****************************************************************************************
749 */
750 hal_status_t hal_dma_start_sg_llp (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config);
751
752 /**
753 ****************************************************************************************
754 * @brief Start the DMA Transfer with interrupt enabled & Channel Diabled.
755 *
756 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
757 * @param[in] src_address: The source memory Buffer address
758 * @param[in] dst_address: The destination memory Buffer address
759 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
760 *
761 * @retval ::HAL_OK: Operation is OK.
762 * @retval ::HAL_ERROR: Parameter error or operation not supported.
763 * @retval ::HAL_BUSY: Driver is busy.
764 * @retval ::HAL_TIMEOUT: Timeout occurred.
765 ****************************************************************************************
766 */
767 hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
768
769 /**
770 ****************************************************************************************
771 * @brief Start the DMA Transfer with interrupt enabled & Channel Enabled.
772 *
773 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
774 * @param[in] src_address: The source memory Buffer address
775 * @param[in] dst_address: The destination memory Buffer address
776 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
777 *
778 * @retval ::HAL_OK: Operation is OK.
779 * @retval ::HAL_ERROR: Parameter error or operation not supported.
780 * @retval ::HAL_BUSY: Driver is busy.
781 * @retval ::HAL_TIMEOUT: Timeout occurred.
782 ****************************************************************************************
783 */
784 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
785
786
787 /**
788 ****************************************************************************************
789 * @brief Start the DMA Transfer with Channel Disabled.
790 *
791 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
792 * @param[in] src_address: The source memory Buffer address
793 * @param[in] dst_address: The destination memory Buffer address
794 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
795 * @param[in] sg_llp_config: The config of source and destination.
796
797 * @retval ::HAL_OK: Operation is OK.
798 * @retval ::HAL_ERROR: Parameter error or operation not supported.
799 * @retval ::HAL_BUSY: Driver is busy.
800 * @retval ::HAL_TIMEOUT: Timeout occurred.
801 ****************************************************************************************
802 */
803 hal_status_t hal_dma_start_sg_llp_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config);
804 /**
805 ****************************************************************************************
806 * @brief Start the DMA Transfer with Channel Enabled.
807 *
808 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
809 * @param[in] src_address: The source memory Buffer address
810 * @param[in] dst_address: The destination memory Buffer address
811 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
812 * @param[in] sg_llp_config: The config of source and destination.
813
814 * @retval ::HAL_OK: Operation is OK.
815 * @retval ::HAL_ERROR: Parameter error or operation not supported.
816 * @retval ::HAL_BUSY: Driver is busy.
817 * @retval ::HAL_TIMEOUT: Timeout occurred.
818 ****************************************************************************************
819 */
820 hal_status_t hal_dma_start_sg_llp_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config);
821
822 /**
823 ****************************************************************************************
824 * @brief Abort the DMA Transfer.
825 *
826 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
827 *
828 * @retval ::HAL_OK: Operation is OK.
829 * @retval ::HAL_ERROR: Parameter error or operation not supported.
830 * @retval ::HAL_BUSY: Driver is busy.
831 * @retval ::HAL_TIMEOUT: Timeout occurred.
832 ****************************************************************************************
833 */
834 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
835
836 /**
837 ****************************************************************************************
838 * @brief Aborts the DMA Transfer in Interrupt mode.
839 *
840 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
841 *
842 * @retval ::HAL_OK: Operation is OK.
843 * @retval ::HAL_ERROR: Parameter error or operation not supported.
844 * @retval ::HAL_BUSY: Driver is busy.
845 * @retval ::HAL_TIMEOUT: Timeout occurred.
846 ****************************************************************************************
847 */
848 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
849
850 /**
851 ****************************************************************************************
852 * @brief Polling for transfer complete.
853 *
854 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
855 * @param[in] timeout: Timeout duration.
856 *
857 * @retval ::HAL_OK: Operation is OK.
858 * @retval ::HAL_ERROR: Parameter error or operation not supported.
859 * @retval ::HAL_BUSY: Driver is busy.
860 * @retval ::HAL_TIMEOUT: Timeout occurred.
861 ****************************************************************************************
862 */
863 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
864
865 /** @} */
866
867 /** @addtogroup DMA_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
868 * @brief IRQ Handler and Callbacks functions
869 * @{
870 */
871
872 /**
873 ****************************************************************************************
874 * @brief Handle DMA interrupt request.
875 *
876 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
877 ****************************************************************************************
878 */
879 void hal_dma_irq_handler(dma_handle_t *p_dma);
880
881 /**
882 ****************************************************************************************
883 * @brief Register callbacks
884 *
885 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
886 * @param[in] id: User Callback identifer. This parameter can be one of the following values:
887 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
888 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
889 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
890 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
891 * @param[in] callback: Pointer to private callbacsk function which has pointer to a dma_handle_t structure as parameter.
892 *
893 * @retval ::HAL_OK: Operation is OK.
894 * @retval ::HAL_ERROR: Parameter error or operation not supported.
895 * @retval ::HAL_BUSY: Driver is busy.
896 * @retval ::HAL_TIMEOUT: Timeout occurred.
897 ****************************************************************************************
898 */
899 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void (* callback)( dma_handle_t * p_dma));
900
901 /**
902 ****************************************************************************************
903 * @brief UnRegister callbacks
904 *
905 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
906 * @param[in] id: User Callback identifer. This parameter can be a combiantion of the following values:
907 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
908 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
909 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
910 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
911 * @arg @ref HAL_DMA_XFER_ALL_CB_ID
912 *
913 * @retval ::HAL_OK: Operation is OK.
914 * @retval ::HAL_ERROR: Parameter error or operation not supported.
915 * @retval ::HAL_BUSY: Driver is busy.
916 * @retval ::HAL_TIMEOUT: Timeout occurred.
917 ****************************************************************************************
918 */
919 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
920
921 /** @} */
922
923 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
924 * @brief Peripheral State and Errors functions
925 *
926 @verbatim
927 ===============================================================================
928 ##### Peripheral State and Errors functions #####
929 ===============================================================================
930 [..]
931 This subsection provides functions allowing to
932 (+) Check the DMA state
933 (+) Get error code
934
935 @endverbatim
936 * @{
937 */
938
939 /**
940 ****************************************************************************************
941 * @brief Return the DMA hande state.
942 *
943 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
944 *
945 * @retval ::HAL_DMA_STATE_RESET: DMA not yet initialized or disabled.
946 * @retval ::HAL_DMA_STATE_READY: DMA process succeeded and ready for use.
947 * @retval ::HAL_DMA_STATE_BUSY: DMA process is ongoing.
948 * @retval ::HAL_DMA_STATE_TIMEOUT: DMA timeout state.
949 * @retval ::HAL_DMA_STATE_ERROR: DMA error state.
950 ****************************************************************************************
951 */
952 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
953
954 /**
955 ****************************************************************************************
956 * @brief Return the DMA error code.
957 *
958 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
959 *
960 * @return DMA Error Code
961 ****************************************************************************************
962 */
963 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
964
965 /**
966 ****************************************************************************************
967 * @brief Suspend some registers related to DMA configuration before sleep.
968 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
969 * information for the specified DMA module.
970 * @retval ::HAL_OK: Operation is OK.
971 * @retval ::HAL_ERROR: Parameter error or operation not supported.
972 * @retval ::HAL_BUSY: Driver is busy.
973 * @retval ::HAL_TIMEOUT: Timeout occurred.
974 ****************************************************************************************
975 */
976 hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma);
977
978 /**
979 ****************************************************************************************
980 * @brief Restore some registers related to DMA configuration after sleep.
981 * This function must be used in conjunction with the hal_dma_resume_reg().
982 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
983 * information for the specified DMA module.
984 * @retval ::HAL_OK: Operation is OK.
985 * @retval ::HAL_ERROR: Parameter error or operation not supported.
986 * @retval ::HAL_BUSY: Driver is busy.
987 * @retval ::HAL_TIMEOUT: Timeout occurred.
988 ****************************************************************************************
989 */
990 hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma);
991
992 /**
993 ****************************************************************************************
994 * @brief set the flag if DMAn has been used before sleep
995 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
996 * information for the specified DMA module.
997 * @retval ::None
998 ****************************************************************************************
999 */
1000 void dma_set_renew_flag(dma_handle_t *p_dma);
1001
1002 /**
1003 ****************************************************************************************
1004 * @brief resume dma regs before using if just waked up from sleep /only need to clear sleep_flag
1005 * if on initial or deinitial state.
1006 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
1007 * information for the specified DMA module.
1008 * @param[in] init_flag: true: use in init function or deinit function
1009 * fault: not use in init function or deinit function
1010 * @retval ::None
1011 ****************************************************************************************
1012 */
1013 void dma_resume_before_using(dma_handle_t *p_dma, bool init_flag);
1014
1015 /** @} */
1016
1017 /** @} */
1018
1019 #ifdef __cplusplus
1020 }
1021 #endif
1022
1023 #endif /* __GR55xx_HAL_DMA_H__*/
1024
1025 /** @} */
1026
1027 /** @} */
1028
1029 /** @} */
dma_block_config::CTL_L
uint32_t CTL_L
Specifies the CRL[31:0] for DMA transfer.
Definition: gr55xx_hal_dma.h:148
dma_gather_config::src_sgi
uint32_t src_sgi
Specifies the channel source gather interval.
Definition: gr55xx_hal_dma.h:186
DMA_Channel4
@ DMA_Channel4
Channel 4
Definition: gr55xx_hal_dma.h:99
HAL_DMA_XFER_TFR_CB_ID
@ HAL_DMA_XFER_TFR_CB_ID
Full transfer
Definition: gr55xx_hal_dma.h:114
dma_gather_config::src_gather_en
uint32_t src_gather_en
Specifies the channel source gather function enable.
Definition: gr55xx_hal_dma.h:183
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
_dma_handle::p_instance
dma_regs_t * p_instance
DMA registers base address
Definition: gr55xx_hal_dma.h:278
hal_dma_get_error
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA_Channel1
@ DMA_Channel1
Channel 1
Definition: gr55xx_hal_dma.h:96
dma_block_config::CTL_H
uint32_t CTL_H
Specifies the CRL[63:32] for DMA transfer.
Definition: gr55xx_hal_dma.h:151
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
DMA timeout state
Definition: gr55xx_hal_dma.h:81
_dma_init
DMA Configuration Structure definition.
Definition: gr55xx_hal_dma.h:235
hal_dma_start_sg_llp_it_dc
hal_status_t hal_dma_start_sg_llp_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer with Channel Disabled.
dma_scatter_config::dst_dsc
uint32_t dst_dsc
Specifies the destination scatter count.
Definition: gr55xx_hal_dma.h:173
_dma_handle::error_code
__IO uint32_t error_code
DMA Error code
Definition: gr55xx_hal_dma.h:298
DMA_Channel0
@ DMA_Channel0
Channel 0
Definition: gr55xx_hal_dma.h:95
dma_llp_config::llp_dst_writeback
uint32_t llp_dst_writeback
Specifies the detination block chaining enable.
Definition: gr55xx_hal_dma.h:208
dma_handle_t
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
hal_dma_state_t
HAL DMA State Enumerations definition.
Definition: gr55xx_hal_dma.h:77
hal_dma_start_it
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Enabled.
hal_dma_abort_it
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
dma_block_config
LL DMA block definition.
Definition: gr55xx_hal_dma.h:137
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
DMA process success and ready for use
Definition: gr55xx_hal_dma.h:79
_dma_init::dst_increment
uint32_t dst_increment
Specifies whether the destination address register should be incremented or decrement or not.
Definition: gr55xx_hal_dma.h:249
DMA_Channel5
@ DMA_Channel5
Channel 5
Definition: gr55xx_hal_dma.h:100
_dma_handle::init
dma_init_t init
DMA communication parameters
Definition: gr55xx_hal_dma.h:282
DMA_Channel2
@ DMA_Channel2
Channel 2
Definition: gr55xx_hal_dma.h:97
dma_sg_llp_config
LL DMA sg and llp config definition.
Definition: gr55xx_hal_dma.h:219
dma_sg_llp_config_t
struct dma_sg_llp_config dma_sg_llp_config_t
LL DMA sg and llp config definition.
hal_dma_irq_handler
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
_dma_handle::xfer_blk_callback
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
DMA block complete callback
Definition: gr55xx_hal_dma.h:292
hal_dma_suspend_reg
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
dma_scatter_config::dst_scatter_en
uint32_t dst_scatter_en
Specifies the destination scatter function enable.
Definition: gr55xx_hal_dma.h:167
dma_llp_config::llp_dst_en
uint32_t llp_dst_en
Specifies the destination writeback the source status information.
Definition: gr55xx_hal_dma.h:205
gr55xx_ll_dma.h
Header file containing functions prototypes of DMA LL library.
_dma_init::priority
uint32_t priority
Specifies the software priority for the DMA Channel.
Definition: gr55xx_hal_dma.h:263
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Abort
Definition: gr55xx_hal_dma.h:117
hal_dma_register_callback
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
All
Definition: gr55xx_hal_dma.h:118
dma_gather_config::src_sgc
uint32_t src_sgc
Specifies the channel source gather count.
Definition: gr55xx_hal_dma.h:189
dma_llp_config::head_lli
struct dma_block_config * head_lli
Specifies the linked list pointer.
Definition: gr55xx_hal_dma.h:211
_dma_handle::retention
uint32_t retention[7]
DMA important register information.
Definition: gr55xx_hal_dma.h:300
dma_scatter_config
LL DMA scatter config definition.
Definition: gr55xx_hal_dma.h:165
_dma_init::dst_request
uint32_t dst_request
Specifies the destination request selected for the specified channel.
Definition: gr55xx_hal_dma.h:239
hal_dma_poll_for_transfer
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_dma_start
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
dma_block_config::dst_address
uint32_t dst_address
Specifies the Source base address for DMA transfer.
Definition: gr55xx_hal_dma.h:142
hal_dma_resume_reg
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep.
_dma_handle::state
__IO hal_dma_state_t state
DMA transfer state
Definition: gr55xx_hal_dma.h:286
dma_block_config::p_lli
struct dma_block_config * p_lli
Specifies the linked list point for DMA transfer.
Definition: gr55xx_hal_dma.h:145
hal_dma_init
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
_dma_handle::xfer_error_callback
void(* xfer_error_callback)(struct _dma_handle *p_dma)
DMA transfer error callback
Definition: gr55xx_hal_dma.h:294
HAL_DMA_XFER_BLK_CB_ID
@ HAL_DMA_XFER_BLK_CB_ID
Block transfer
Definition: gr55xx_hal_dma.h:115
dma_set_renew_flag
void dma_set_renew_flag(dma_handle_t *p_dma)
set the flag if DMAn has been used before sleep
hal_dma_start_it_dc
hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Diabled.
hal_dma_callback_id_t
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
Definition: gr55xx_hal_dma.h:113
DMA_Channel3
@ DMA_Channel3
Channel 3
Definition: gr55xx_hal_dma.h:98
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
DMA error state
Definition: gr55xx_hal_dma.h:82
_dma_handle::xfer_tfr_callback
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
DMA transfer complete callback
Definition: gr55xx_hal_dma.h:290
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
DMA process is ongoing
Definition: gr55xx_hal_dma.h:80
_dma_handle::xfer_abort_callback
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
DMA transfer abort callback
Definition: gr55xx_hal_dma.h:296
dma_init_t
struct _dma_init dma_init_t
DMA Configuration Structure definition.
hal_dma_start_sg_llp
hal_status_t hal_dma_start_sg_llp(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer.
dma_scatter_config_t
struct dma_scatter_config dma_scatter_config_t
LL DMA scatter config definition.
dma_llp_config::llp_src_writeback
uint32_t llp_src_writeback
Specifies the source writeback the source status information.
Definition: gr55xx_hal_dma.h:202
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
_dma_init::direction
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
Definition: gr55xx_hal_dma.h:242
hal_dma_get_state
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
_dma_init::mode
uint32_t mode
Specifies the operation mode of the DMA Channel(Normal or Circular).
Definition: gr55xx_hal_dma.h:258
dma_gather_config_t
struct dma_gather_config dma_gather_config_t
LL DMA gather config definition.
DMA_Channel_NUM_MAX
@ DMA_Channel_NUM_MAX
Only for check parameter, not used as input parameters.
Definition: gr55xx_hal_dma.h:101
hal_dma_unregister_callback
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
_dma_handle::channel
dma_channel_t channel
DMA Channel Number
Definition: gr55xx_hal_dma.h:280
_dma_init::dst_data_alignment
uint32_t dst_data_alignment
Specifies the destination data width.
Definition: gr55xx_hal_dma.h:255
dma_llp_config
LL DMA llp config definition.
Definition: gr55xx_hal_dma.h:197
dma_block_config::src_status
uint32_t src_status
Specifies the Destination base address for DMA transfer.
Definition: gr55xx_hal_dma.h:154
_dma_handle::lock
hal_lock_t lock
DMA locking object
Definition: gr55xx_hal_dma.h:284
dma_block_config_t
struct dma_block_config dma_block_config_t
LL DMA block definition.
dma_llp_config_t
struct dma_llp_config dma_llp_config_t
LL DMA llp config definition.
dma_block_config::dst_status
uint32_t dst_status
Specifies the Source base address for DMA transfer.
Definition: gr55xx_hal_dma.h:157
dma_gather_config
LL DMA gather config definition.
Definition: gr55xx_hal_dma.h:181
_dma_handle::p_parent
void * p_parent
Parent object state
Definition: gr55xx_hal_dma.h:288
dma_scatter_config::dst_dsi
uint32_t dst_dsi
Specifies the destination scatter tnterval.
Definition: gr55xx_hal_dma.h:170
hal_dma_start_sg_llp_it
hal_status_t hal_dma_start_sg_llp_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer with Channel Enabled.
hal_dma_abort
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Error
Definition: gr55xx_hal_dma.h:116
dma_sg_llp_config::gather_config
dma_gather_config_t gather_config
Specifies the destination block chaining enable.
Definition: gr55xx_hal_dma.h:224
dma_resume_before_using
void dma_resume_before_using(dma_handle_t *p_dma, bool init_flag)
resume dma regs before using if just waked up from sleep /only need to clear sleep_flag if on initial...
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
DMA not yet initialized or disabled.
Definition: gr55xx_hal_dma.h:78
_dma_init::src_request
uint32_t src_request
Specifies the source request selected for the specified channel.
Definition: gr55xx_hal_dma.h:236
dma_sg_llp_config::llp_config
dma_llp_config_t llp_config
Specifies the linked list pointer.
Definition: gr55xx_hal_dma.h:227
dma_sg_llp_config::scatter_config
dma_scatter_config_t scatter_config
Specifies the source block chaining enable.
Definition: gr55xx_hal_dma.h:221
_dma_init::src_data_alignment
uint32_t src_data_alignment
Specifies the source data width.
Definition: gr55xx_hal_dma.h:252
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:277
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_dma_deinit
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr55xx_hal_dma.h:94
_dma_init::src_increment
uint32_t src_increment
Specifies whether the srouce address register should be incremented or decrement or not.
Definition: gr55xx_hal_dma.h:246
dma_llp_config::llp_src_en
uint32_t llp_src_en
Specifies the source block chaining enable.
Definition: gr55xx_hal_dma.h:199
dma_block_config::src_address
uint32_t src_address
Specifies the Destination base address for DMA transfer.
Definition: gr55xx_hal_dma.h:139