var group___q_s_p_i___exported___constants =
[
    [ "Set DMA Control Register", "d9/de4/group___q_s_p_i___d_m_a___c_t_r_l___r_e_g_i_s_t_e_r___c_f_g.html", "d9/de4/group___q_s_p_i___d_m_a___c_t_r_l___r_e_g_i_s_t_e_r___c_f_g" ],
    [ "Fifo Depth", "dd/d3d/group___h_a_l___q_s_p_i___f_i_f_o___d_e_p_t_h.html", "dd/d3d/group___h_a_l___q_s_p_i___f_i_f_o___d_e_p_t_h" ],
    [ "QSPI Error Code", "d0/d1a/group___q_s_p_i___error___code.html", "d0/d1a/group___q_s_p_i___error___code" ],
    [ "QSPI Clock Mode", "d0/d34/group___q_s_p_i___clock___mode.html", "d0/d34/group___q_s_p_i___clock___mode" ],
    [ "QSPI Data Mode", "d3/dfd/group___q_s_p_i___data___mode.html", "d3/dfd/group___q_s_p_i___data___mode" ],
    [ "QSPI Instruction Size", "d1/de6/group___q_s_p_i___instruction___size.html", "d1/de6/group___q_s_p_i___instruction___size" ],
    [ "QSPI Address Size", "d0/d6a/group___q_s_p_i___address___size.html", "d0/d6a/group___q_s_p_i___address___size" ],
    [ "Data Width", "d7/de8/group___q_s_p_i___data___size.html", "d7/de8/group___q_s_p_i___data___size" ],
    [ "QSPI Instruction and Address Mode", "d4/de0/group___q_s_p_i___inst___addr___mode.html", "d4/de0/group___q_s_p_i___inst___addr___mode" ],
    [ "QSPI Flags", "de/d4e/group___q_s_p_i___flags.html", "de/d4e/group___q_s_p_i___flags" ],
    [ "QSPI Interrupts", "d8/dd5/group___q_s_p_i___interrupts.html", "d8/dd5/group___q_s_p_i___interrupts" ],
    [ "QSPI Timeout_definition", "db/d57/group___q_s_p_i___timeout__definition.html", "db/d57/group___q_s_p_i___timeout__definition" ],
    [ "endian mode for qspi xip", "d7/d34/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___e_n_d_i_a_n___m_o_d_e.html", "d7/d34/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___e_n_d_i_a_n___m_o_d_e" ],
    [ "Which Slave to Enable in XIP", "dc/d8b/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___s_l_a_v_e.html", "dc/d8b/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___s_l_a_v_e" ],
    [ "data frame size in xip, take effect when enable DFS_HC", "db/de8/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s.html", "db/de8/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s" ],
    [ "mode bits length for xip mode", "d7/d4e/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_b_l.html", "d7/d4e/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_b_l" ],
    [ "instruction size for concurrent xip mode", "da/d82/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t_s_i_z_e.html", "da/d82/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t_s_i_z_e" ],
    [ "address size for concurrent xip mode", "d9/d51/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___a_d_d_r_s_i_z_e.html", "d9/d51/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___a_d_d_r_s_i_z_e" ],
    [ "transfer of inst & address for concurrent xip mode", "dd/de5/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___a_d_d_r___t_r_a_n_s_f_e_r___f_o_r_m_a_t.html", "dd/de5/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___a_d_d_r___t_r_a_n_s_f_e_r___f_o_r_m_a_t" ],
    [ "frame format for concurrent xip mode", "da/db7/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___f_r_f.html", "da/db7/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___f_r_f" ],
    [ "Mode Clock stretch mode", "db/d79/group___q_s_p_i___x_i_p___c_l_k___s_t_r_e_t_c_h.html", "db/d79/group___q_s_p_i___x_i_p___c_l_k___s_t_r_e_t_c_h" ],
    [ "Prefetch for concurrent xip mode", "dc/df4/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___p_r_e_f_e_t_c_h.html", "dc/df4/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___p_r_e_f_e_t_c_h" ],
    [ "Cont transfer for concurrent xip mode", "d2/d51/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___c_o_n_t___x_f_e_r.html", "d2/d51/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___c_o_n_t___x_f_e_r" ],
    [ "Instruction phase for concurrent xip mode", "d2/d39/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___p_h_a_s_e.html", "d2/d39/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___p_h_a_s_e" ],
    [ "Bits phase for concurrent xip mode", "d6/df2/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_o_d_e___b_i_t_s___p_h_a_s_e.html", "d6/df2/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_o_d_e___b_i_t_s___p_h_a_s_e" ],
    [ "DFS hardcore for concurrent xip mode", "de/dec/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s___h_a_r_d_c_o_d_e.html", "de/dec/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s___h_a_r_d_c_o_d_e" ],
    [ "Instruction sent mode for concurrent xip mode", "d7/dc7/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___s_e_n_t___m_o_d_e.html", "d7/dc7/group___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___s_e_n_t___m_o_d_e" ],
    [ "BLOCK Mode for LLP", "df/d99/group___q_s_p_i___p_s_r_a_m___d_a_t_a___i_n___l_l_p___m_o_d_e.html", "df/d99/group___q_s_p_i___p_s_r_a_m___d_a_t_a___i_n___l_l_p___m_o_d_e" ],
    [ "BLOCK SHAPE for DMA LLP", "d8/d9f/group___q_s_p_i___p_s_r_a_m___d_a_t_a___b_l_o_c_k___s_h_a_p_e.html", "d8/d9f/group___q_s_p_i___p_s_r_a_m___d_a_t_a___b_l_o_c_k___s_h_a_p_e" ]
];