app_qspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file app_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI app library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup APP_DRIVER APP DRIVER
43 * @{
44 */
45
46 /** @defgroup APP_QSPI QSPI
47 * @brief QSPI APP module driver.
48 * @{
49 */
50
51
52 #ifndef _APP_QSPI_H_
53 #define _APP_QSPI_H_
54
55 #include "app_drv_config.h"
56 #if (APP_DRIVER_CHIP_TYPE != APP_DRIVER_GR5405) && (APP_DRIVER_CHIP_TYPE != APP_DRIVER_GR5332X)
57 #include "gr55xx_hal.h"
58 #endif
59
60 #include "app_io.h"
61 #include "app_dma.h"
62 #include "app_drv_error.h"
63 #include "app_drv_config.h"
64 #include "stdbool.h"
65 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
66 #include "app_qspi_user_config.h"
67 #endif
68 #ifdef __cplusplus
69 extern "C" {
70 #endif
71
72 #ifdef HAL_QSPI_MODULE_ENABLED
73
74 /**
75 * @defgroup APP_QSPI_MACRO Defines
76 * @{
77 */
78
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup APP_QSPI_Exported_Constants QSPI Exported Constants
81 * @{
82 */
83
84 /** @addtogroup APP_QSPI_PIN Qspi pin defines
85 * @{
86 */
87 #define APP_QSPI_PIN_ENABLE 1 /**< QSPI pin enable */
88 #define APP_QSPI_PIN_DISABLE 0 /**< QSPI pin disable */
89 /** @} */
90
91 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
92 /** @defgroup APP_MAX_XFER MAX_XREF Defines
93 * @{
94 */
95 #define QSPI_MAX_XFER_SIZE_ONCE (0xFFFCu) /**< max xfer beat in every qspi xfer */
96 #define DMA_MAX_XFER_SIZE_ONCE (4095u) /**< max xfer beat in every dma xfer */
97 /** @} */
98
99 //#define APP_STORAGE_RAM_ID 0xf /**< Special ID to handle RAM Source */
100 #endif
101
102 /** @addtogroup QSPI_SMART_CS_ENABLE smart cs enable defines. NOTE: If QSPI_DATA_MODE_SPI, enable smart cs
103 * @{
104 */
105 #ifndef QSPI_SMART_CS_ENABLE
106 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
107 #define QSPI_SMART_CS_ENABLE 1 /**< CS pin is controlled by software */
108 #else
109 #define QSPI_SMART_CS_ENABLE 0 /**< CS pin is controlled by hardware */
110 #endif
111 #endif
112
113 #if QSPI_SMART_CS_ENABLE
114 #define QSPI_SMART_CS_LOW(id) \
115 do { \
116 if(p_qspi_env[id]->p_pin_cfg->cs.enable == APP_QSPI_PIN_ENABLE) \
117 { \
118 app_io_write_pin(p_qspi_env[id]->p_pin_cfg->cs.type, \
119 p_qspi_env[id]->p_pin_cfg->cs.pin, \
120 APP_IO_PIN_RESET); \
121 } \
122 } while(0)
123
124 #define QSPI_SMART_CS_HIGH(id) \
125 do { \
126 if(p_qspi_env[id]->p_pin_cfg->cs.enable == APP_QSPI_PIN_ENABLE) \
127 { \
128 app_io_write_pin(p_qspi_env[id]->p_pin_cfg->cs.type, \
129 p_qspi_env[id]->p_pin_cfg->cs.pin, \
130 APP_IO_PIN_SET); \
131 } \
132 } while(0)
133 #else
134 #define QSPI_SMART_CS_LOW(id)
135 #define QSPI_SMART_CS_HIGH(id)
136 #endif /* QSPI_SMART_CS_ENABLE */
137 /** @} */
138
139 /** @} */
140
141 /** @} */
142
143
144 /** @addtogroup APP_QSPI_ENUM Enumerations
145 * @{
146 */
147
148 /**
149 * @brief QSPI module Enumerations definition
150 */
151 typedef enum
152 {
153 APP_QSPI_ID_0, /**< QSPI module 0 */
154 APP_QSPI_ID_1, /**< QSPI module 1 */
155 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
156 APP_QSPI_ID_2, /**< QSPI module 2 */
157 #endif
158 APP_QSPI_ID_MAX, /**< Only for check parameter, not used as input parameters. */
159
160 APP_STORAGE_RAM_ID = 0xf,
161 } app_qspi_id_t;
162
163 /**
164 * @brief APP QSPI Event Type
165 */
166 typedef enum
167 {
168 APP_QSPI_EVT_ERROR, /**< Error reported by QSPI peripheral. */
169 APP_QSPI_EVT_TX_CPLT, /**< Requested TX transfer completed. */
170 APP_QSPI_EVT_RX_DATA, /**< Requested RX transfer completed. */
171 APP_QSPI_EVT_ABORT, /**< Abort reported by QSPI peripheral. */
172 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
173 APP_QSPI_EVT_ASYNC_WR_SCRN_CPLT, /**< ASYNC-Write Quad Screen Complete */
174 APP_QSPI_EVT_ASYNC_WR_SCRN_FAIL, /**< ASYNC-Write Quad Screen Fail */
175 #endif
176 } app_qspi_evt_type_t;
177
178 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
179 /**
180 * @brief QSPI Memory-Mapped Endian Mode
181 */
182 typedef enum {
183 APP_QSPI_MMAP_ENDIAN_MODE_0 = 0, /**< MMAP Endian Mode 0 */
184 APP_QSPI_MMAP_ENDIAN_MODE_1, /**< MMAP Endian Mode 1 */
185 APP_QSPI_MMAP_ENDIAN_MODE_2, /**< MMAP Endian Mode 2 */
186 } app_qspi_mmap_endian_mode_e;
187
188 /**
189 * @brief QSPI Device supporting Memory-Mapped Mode
190 */
191 typedef enum {
192 APP_QSPI_DEVICE_UNSET = 0, /**< UnSet Device */
193 APP_QSPI_DEVICE_FLASH = 1, /**< Flash Device */
194 APP_QSPI_DEVICE_PSRAM = 2, /**< PSRAM Device */
195 } app_qspi_device_e;
196
197 /**
198 * @brief Define PSRAM's Read Command for Memory-Mapped Mode
199 */
200 typedef enum {
201 PSRAM_MMAP_CMD_QREAD_0BH = 0x00, /**< 0BH in Quad */
202 PSRAM_MMAP_CMD_QREAD_EBH = 0x01, /**< EBH in Quad */
203 PSRAM_MMAP_CMD_READ_MAX
204 } app_qspi_psram_mmap_rd_cmd_e;
205
206 /**
207 * @brief Define PSRAM's Write Command for Memory-Mapped Mode
208 */
209 typedef enum {
210 PSRAM_MMAP_CMD_QWRITE_02H = 0x00, /**< 02H in Quad */
211 PSRAM_MMAP_CMD_QWRITE_38H = 0x01, /**< 38H in Quad */
212 PSRAM_MMAP_CMD_WRITE_MAX
213 } app_qspi_psram_mmap_wr_cmd_e;
214
215 /**
216 * @brief Define Flash's Read Command for Memory-Mapped Mode
217 */
218 typedef enum {
219 FLASH_MMAP_CMD_DREAD_3BH = 0x00, /**< 3BH in Dual */
220 FLASH_MMAP_CMD_2READ_BBH = 0x01, /**< BBH in 2Read */
221 FLASH_MMAP_CMD_2READ_BBH_SIOO = 0x02, /**< BBH in 2Read with SIOO mode */
222
223 FLASH_MMAP_CMD_QREAD_6BH = 0x03, /**< 6BH in QRead */
224 FLASH_MMAP_CMD_4READ_EBH = 0x04, /**< EBH in 4Read */
225 FLASH_MMAP_CMD_4READ_EBH_SIOO = 0x05, /**< EBH in 4Read with SIOO mode */
226 FLASH_MMAP_CMD_READ_MAX,
227 } app_qspi_flash_mmap_rd_cmd_e;
228
229 /**
230 * @brief APP QSPI interface type when drawing screen
231 */
232 typedef enum {
233 DRAW_TYPE_IF_NONE = 0x00,
234 DRAW_TYPE_IF_DUAL_SCREEN,
235 DRAW_TYPE_IF_VERI_LINKED_SCREEN,
236 } app_qspi_draw_screen_interface_type_e;
237
238 /**
239 * @brief Define Pin Groups for QSPI
240 */
241 typedef enum {
242
243 QSPI0_PIN_GROUP_0 = 0x00, /**< QSPI0 Pinmux Group */
244 /* CS : GPIO_26.MUX0 */
245 /* CLK : GPIO_21.MUX0 */
246 /* IO0 : GPIO_22.MUX0 */
247 /* IO1 : GPIO_23.MUX0 */
248 /* IO2 : GPIO_24.MUX0 */
249 /* IO3 : GPIO_25.MUX0 */
250
251 QSPI1_PIN_GROUP_0 = 0x01, /**< QSPI1 Pinmux Group 0 */
252 /* CS : GPIO_10.MUX0 */
253 /* CLK : GPIO_15.MUX0 */
254 /* IO0 : GPIO_11.MUX0 */
255 /* IO1 : GPIO_12.MUX0 */
256 /* IO2 : GPIO_13.MUX0 */
257 /* IO3 : GPIO_14.MUX0 */
258
259 QSPI2_PIN_GROUP_0 = 0x02, /**< QSPI2 Pinmux Group 0 */
260 /* CS : GPIO_27.MUX0 */
261 /* CLK : GPIO_16.MUX0 */
262 /* IO0 : GPIO_17.MUX0 */
263 /* IO1 : GPIO_18.MUX0 */
264 /* IO2 : GPIO_19.MUX0 */
265 /* IO3 : GPIO_20.MUX0 */
266 QSPIx_PIN_GROUP_MAX,
267 } qspi_pins_group_e;
268
269 /**
270 * @brief Define BLIT Mode By DMA
271 */
272 typedef enum {
273 BLIT_BY_DMA_SG = 0, /**< need enable BLIT_IMAGE_FEATURE_SUPPORT */
274 BLIT_BY_DMA_LLP = 1, /**< need enable PSRAM_LLP_FEATURE_SUPPORT */
275 } blit_xfer_type_e;
276
277 /** @} */
278
279 /** @addtogroup APP_QSPI_STRUCTURES Structures
280 * @{
281 */
282
283 /**
284 * @brief QSPI memory-mapped configuration Structures
285 */
286 typedef struct {
287 app_qspi_device_e dev_type; /**< Specifies the device type of QSPI */
288 app_qspi_psram_mmap_wr_cmd_e psram_wr; /**< Specifies the write command for PSRAM, Flash does not support this */
289 union {
290 app_qspi_flash_mmap_rd_cmd_e flash_rd; /**< Read command for flash device */
291 app_qspi_psram_mmap_rd_cmd_e psram_rd; /**< Read command for psram device */
292 } rd; /**< Specifies read command by real device */
293 void * set; /**< Reserved */
294 } app_qspi_mmap_device_t;
295 #endif
296
297 /**
298 * @brief QSPI IO configuration Structures
299 */
300 typedef struct
301 {
302 app_io_type_t type; /**< Specifies the type of QSPI IO. */
303 app_io_mux_t mux; /**< Specifies the Peripheral to be connected to the selected pins. */
304 uint32_t pin; /**< Specifies the IO pins to be configured.
305 This parameter can be any value of @ref GR5xxx_pins. */
306 app_io_mode_t mode; /**< Specifies the IO Mode for pins. */
307 app_io_pull_t pull; /**< Specifies the Pull-up or Pull-Down activation for the selected pins. */
308 uint8_t enable; /**< Enable or disable the pin. */
309 } app_qspi_pin_t;
310
311 /**
312 * @brief QSPI configuration Structures
313 */
314 typedef struct
315 {
316 app_qspi_pin_t cs; /**< Set the configuration of QSPI CS pin. */
317 app_qspi_pin_t clk; /**< Set the configuration of QSPI CLK pin. */
318 app_qspi_pin_t io_0; /**< Set the configuration of QSPI IO0 pin. */
319 app_qspi_pin_t io_1; /**< Set the configuration of QSPI IO1 pin. */
320 app_qspi_pin_t io_2; /**< Set the configuration of QSPI IO2 pin. */
321 app_qspi_pin_t io_3; /**< Set the configuration of QSPI IO3 pin. */
322 } app_qspi_pin_cfg_t;
323
324 /**
325 * @brief QSPI DMA configuration structure definition
326 */
327 typedef struct
328 {
329 dma_regs_t * dma_instance; /**< Specifies the dma instance of QSPI. */
330 dma_channel_t dma_channel; /**< Specifies the dma channel of QSPI. */
331 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
332 uint32_t wait_timeout_ms; /**< Specifies timeout time of polling and dead wait, ms. */
333 uint32_t extend; /**< Specifies extend segment, to use */
334 #endif
335 } app_qspi_dma_cfg_t;
336 /** @} */
337
338 /** @addtogroup APP_QSPI_TYPEDEFS Type Definitions
339 * @{
340 */
341
342 /**
343 * @brief QSPI command structure definition
344 */
345 typedef qspi_command_t app_qspi_command_t;
346 /** @} */
347
348 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
349 /** @addtogroup APP_QSPI_STRUCTURES Structures
350 * @{
351 */
352 typedef struct
353 {
354 uint32_t instruction; /**< Specifies the Instruction to be sent.
355 This parameter can be a value (8-bit) between 0x00 and 0xFF. */
356
357 uint32_t leading_address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
358 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
359
360 uint32_t ongoing_address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
361 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
362
363 uint32_t instruction_size; /**< Specifies the Instruction Size.
364 This parameter can be a value of @ref QSPI_Instruction_Size. */
365
366 uint32_t address_size; /**< Specifies the Address Size.
367 This parameter can be a value of @ref QSPI_Address_Size. */
368
369 uint32_t dummy_cycles; /**< Specifies the Number of Dummy Cycles.
370 This parameter can be a number between 0 and 31. */
371
372 uint32_t data_size; /**< Specifies the QSPI address width.
373 This parameter can be a value of @ref QSPI_Data_Size. */
374
375 uint32_t instruction_address_mode; /**< Specifies the Instruction and Address Mode.
376 This parameter can be a value of @ref QSPI_Inst_Addr_Mode. */
377
378 uint32_t data_mode; /**< Specifies the Data Mode (used for dummy cycles and data phases).
379 This parameter can be a value of @ref QSPI_Data_Mode. */
380
381 bool is_one_take_cs; /**< Sent all data in one take CS or in multiple independent CS */
382
383 } app_qspi_screen_command_t;
384 /** @} */
385 #endif
386
387 /** @addtogroup APP_QSPI_STRUCTURES Structures
388 * @{
389 */
390 /**
391 * @brief QSPI event structure definition
392 */
393 typedef struct
394 {
395 app_qspi_evt_type_t type; /**< Type of event. */
396 union
397 {
398 uint32_t error_code; /**< QSPI Error code . */
399 uint16_t size; /**< QSPI transmitted/received counter. */
400 } data; /**< Event data. */
401 } app_qspi_evt_t;
402
403 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
404 /**
405 * @brief Screen Info. structure definition
406 */
407 typedef struct {
408 unsigned int scrn_pixel_stride; /**< screen pixel stride, such as 390 */
409 unsigned int scrn_pixel_width; /**< screen pixel width, such as 390, width must be less or equal than stride */
410 unsigned int scrn_pixel_height; /**< screen pixel height, such as 390 */
411 unsigned int scrn_pixel_depth; /**< pixel depth, unit: byte, such as 2 */
412 } app_qspi_screen_info_t;
413
414
415 /**
416 * @brief Scroll-Screen structure definition
417 */
418 typedef struct {
419 uint32_t first_frame_start_address; /**< if scroll the screen horizontally : first stands for left image, second stands for right image */
420 uint32_t second_frame_start_address; /**< if scroll the screen vertically : first stands for up image, second stands for down image */
421 uint32_t scroll_coordinate; /**< scroll to where , must be even number, belongs to [0, SCREEN_PIXEL_WIDTH] */
422 bool is_horizontal_scroll; /**< true : screen horizontally ; false : screen vertically */
423 } app_qspi_screen_scroll_t;
424
425 /**
426 * @brief Vertical Scroll-Screen Linked List Structure
427 */
428 typedef struct _screen_veri_link_scroll_t {
429 uint32_t frame_ahb_start_address; /**< Start AHB address for current frame */
430 uint32_t frame_offset_lines; /**< Offset lines for current frame */
431 uint32_t frame_draw_lines; /**< Drawing lines (start from offset line) for current frame */
432 struct _screen_veri_link_scroll_t * next; /**< Linked to next node, if empty, Set NULL */
433 } app_qspi_screen_veri_link_scroll_t;
434
435 /**
436 * @brief One block of screen Structure
437 */
438 typedef struct {
439 uint32_t frame_ahb_start_address; /**< Start AHB address for current block */
440 uint32_t frame_offset_lines; /**< Offset lines for current block */
441 uint32_t frame_draw_lines; /**< Drawing lines (start from offset line) for current block */
442 } app_qspi_screen_block_t;
443
444 /**
445 * @brief Dual Screen (HOR/VER) Scroll Structure, just used for inner driver
446 */
447 typedef struct {
448 app_qspi_screen_scroll_t scroll_config; /**< Start AHB address for current frame */
449 uint32_t image_1_ahb_address; /**< Record first frame starting AHB address */
450 uint32_t image_2_ahb_address; /**< Record second frame starting AHB address */
451 uint32_t this_send_lines; /**< Record current sent lines */
452 uint32_t total_sent_lines; /**< Record total sent lines already */
453 uint32_t sent_line_order; /**< Record current line order */
454 } dual_screen_scroll_t;
455
456 /**
457 * @brief Vertical Linked List Screen-Scroll Structure, just used for inner driver
458 */
459 typedef struct {
460 app_qspi_screen_veri_link_scroll_t vl_scroll; /**< Start AHB address for current frame */
461 app_qspi_screen_veri_link_scroll_t * p_cur_scroll; /**< Record current linked node */
462 uint32_t total_sent_lines; /**< Record total sent lines */
463 } veri_linked_screen_scroll_t;
464
465 /**
466 * @brief Async Draw Screen Structure, just used for inner driver
467 */
468 typedef struct {
469 app_qspi_draw_screen_interface_type_e if_type; /**< drawing interface type */
470 app_qspi_id_t screen_id; /**< Specify the Screen ID */
471 app_qspi_id_t storage_id; /**< Specify the Memory ID */
472 uint32_t llp_cfg_right_shift_bit; /**< Record the llp shift bit configure */
473 uint32_t llp_cfg_ctrl_low; /**< Record the llp control bits configure */
474 app_qspi_screen_info_t screen_info; /**< Record the basic screen info */
475 app_qspi_screen_command_t qspi_screen_command; /**< Record the basic screen command */
476 union {
477 dual_screen_scroll_t dual_ss; /**< info for dual screen-scroll */
478 veri_linked_screen_scroll_t veri_linked_ss; /**< info for veri linked screen-scroll */
479 } ss; /**< union record */
480 } app_qspi_async_draw_screen_info_t;
481
482
483 /**
484 * @brief Blit Image structure definition
485 */
486 typedef struct {
487 uint32_t src_img_address; /**< source address, just offset in storage device */
488 uint32_t src_img_w; /**< pixel width of source image */
489 uint32_t src_img_h; /**< pixel height of source image */
490 uint32_t src_img_x; /**< x-coordinate of source image, left-top point is Coordinate origin */
491 uint32_t src_img_x_delta; /**< blit image width in pixel, do not multiple pixel depth */
492 uint32_t src_img_y; /**< y-coordinate of source image, left-top point is Coordinate origin */
493 uint32_t src_img_y_delta; /**< blit image height in pixel, do not multiple pixel depth */
494 uint32_t dst_buff_address; /**< destination buffer address */
495 uint32_t dst_buff_width; /**< pixel width of destination buffer */
496 uint32_t dst_buff_height; /**< pixel height of destination buffer */
497 uint32_t dst_buff_x; /**< x-coordinate of destination buffer, left-top point is Coordinate origin */
498 uint32_t dst_buff_y; /**< y-coordinate of destination buffer, left-top point is Coordinate origin */
499 uint32_t pixel_depth; /**< pixel depth in byte */
500 } blit_image_config_t;
501 #endif
502 /** @} */
503
504 /** @addtogroup APP_QSPI_TYPEDEFS Type Definitions
505 * @{
506 */
507
508 /**
509 * @brief QSPI event callback definition
510 */
511 typedef void (*app_qspi_evt_handler_t)(app_qspi_evt_t *p_evt);
512 /** @} */
513
514 /** @addtogroup APP_QSPI_ENUM Enumerations
515 * @{
516 */
517 /**@brief App qspi state types. */
518 typedef enum
519 {
520 APP_QSPI_INVALID = 0,
521 APP_QSPI_ACTIVITY,
522 #ifdef APP_DRIVER_WAKEUP_CALL_FUN
523 APP_QSPI_SLEEP,
524 #endif
525 } app_qspi_state_t;
526
527 /**@brief App qspi dma_state types. */
528 typedef enum
529 {
530 APP_QSPI_DMA_INVALID = 0,
531 APP_QSPI_DMA_ACTIVITY,
532 } app_qspi_dma_state_t;
533
534 /** @} */
535
536 /** @addtogroup APP_QSPI_STRUCTURES Structures
537 * @{
538 */
539
540 /**
541 * @brief QSPI device structure definition
542 */
543 typedef struct {
544 qspi_handle_t handle; /**< QSPI handle Structure. */
545 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
546 app_qspi_dma_cfg_t dma_cfg; /**< QSPI DMA configuration structure. */
547 #endif
548 app_qspi_pin_cfg_t *p_pin_cfg; /**< QSPI configuration Structures. */
549 dma_id_t dma_id; /**< DMA id. */
550 app_qspi_state_t qspi_state; /**< App qspi state types. */
551 app_qspi_dma_state_t qspi_dma_state; /**< App qspi dma_state types. */
552 volatile bool start_flag; /**< start flag. */
553 app_qspi_evt_handler_t evt_handler; /**< QSPI event callback. */
554 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
555 app_qspi_mmap_device_t mounted_mmap_device; /**< QSPI memory-mapped configuration Structures. */
556
557 volatile uint8_t mmap_endian_mode; /**< mmap endian mode. */
558 volatile bool is_mmap_inited; /**< mmap inited. */
559 volatile bool is_mmap_prefetch_en; /**< mmap prefetch. */
560 #endif
561 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
562 volatile bool is_used_dma; /**< used dma. */
563 volatile bool is_dma_mode_m2m; /**< dma mode. */
564 #endif
565 volatile bool is_rx_done; /**< rx done. */
566 volatile bool is_tx_done; /**< tx done. */
567 volatile bool is_xfer_err; /**< xfer err. */
568 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
569 volatile bool is_dma_done; /**< dma done. */
570 volatile bool is_async_write_screen; /**< async write screen. */
571 #endif
572 }qspi_env_t;
573
574 /**
575 * @brief QSPI parameters structure definition
576 */
577 typedef struct
578 {
579 app_qspi_id_t id; /**< specified QSPI module ID. */
580 app_qspi_pin_cfg_t pin_cfg; /**< the pin configuration information for the specified QSPI module. */
581 app_qspi_dma_cfg_t dma_cfg; /**< QSPI DMA configuration. */
582 qspi_init_t init; /**< QSPI communication parameters. */
583 qspi_env_t qspi_env; /**< QSPI device structure definition. */
584 } app_qspi_params_t;
585 /** @} */
586
587
588 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
589 /** @addtogroup HAL_APP_QSPI_DRIVER_CONSTANTS Constants
590 * @{
591 */
592
593 /**
594 * @brief The Reference to pin groups define
595 */
596 extern const app_qspi_pin_cfg_t g_qspi_pin_groups[QSPIx_PIN_GROUP_MAX];
597
598 /** @} */
599 #endif
600
601
602 /* Exported functions --------------------------------------------------------*/
603 /** @addtogroup HAL_APP_QSPI_DRIVER_FUNCTIONS Functions
604 * @{
605 */
606 /**
607 ****************************************************************************************
608 * @brief Initialize the APP QSPI DRIVER according to the specified parameters
609 * in the app_qspi_params_t and app_qspi_evt_handler_t.
610 * @note If interrupt mode is set, you can use blocking mode. Conversely, if blocking mode
611 * is set, you can't use interrupt mode.
612 *
613 * @param[in] p_params: Pointer to app_qspi_params_t parameter which contains the
614 * configuration information for the specified QSPI module.
615 * @param[in] evt_handler: QSPI user callback function.
616 *
617 * @return Result of initialization.
618 ****************************************************************************************
619 */
620 uint16_t app_qspi_init(app_qspi_params_t *p_params, app_qspi_evt_handler_t evt_handler);
621
622 /**
623 ****************************************************************************************
624 * @brief De-initialize the APP QSPI DRIVER peripheral.
625 *
626 * @param[in] id: De-initialize for a specific ID.
627 *
628 * @return Result of De-initialization.
629 ****************************************************************************************
630 */
631 uint16_t app_qspi_deinit(app_qspi_id_t id);
632
633 /**
634 ****************************************************************************************
635 * @brief Abort qspi communication with Interrupt.
636 *
637 * @param[in] id: QSPI module ID.
638 *
639 * @return Result of operation.
640 ****************************************************************************************
641 */
642 uint16_t app_qspi_abort(app_qspi_id_t id);
643
644 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
645 /**
646 ****************************************************************************************
647 * @brief Config the memory mapped mode (also called XIP mode) and Active the mode
648 *
649 * @param[in] id : QSPI module ID.
650 * @param[in] dev: device config for mmapped mode
651 *
652 * @return true/false
653 ****************************************************************************************
654 */
655 bool app_qspi_config_memory_mappped(app_qspi_id_t id, app_qspi_mmap_device_t dev);
656
657 /**
658 ****************************************************************************************
659 * @brief Active or Deactive memory mapped mode (also called XIP mode)
660 *
661 * @param[in] id : QSPI module ID.
662 * @param[in] is_active: true - Active the mode; false - Deactive the mode
663 *
664 * @return true/false
665 ****************************************************************************************
666 */
667 bool app_qspi_active_memory_mappped(app_qspi_id_t id, bool is_active);
668 #endif
669
670 /**
671 ****************************************************************************************
672 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
673 * @note This function is used only in Indirect Read Mode.
674 * @param[in] id: which QSPI module want to receive.
675 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
676 * @param[out] p_data: Pointer to data buffer
677 * @param[in] timeout: Timeout duration
678 *
679 * @return Result of operation.
680 ****************************************************************************************
681 */
682 uint16_t app_qspi_command_receive_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
683
684 /**
685 ****************************************************************************************
686 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
687 * @note This function is used only in Indirect Read Mode.
688 * @param[in] id: which QSPI module want to receive.
689 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
690 * @param[out] p_data: Pointer to data buffer
691 *
692 * @return Result of operation.
693 ****************************************************************************************
694 */
695 uint16_t app_qspi_command_receive_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data);
696
697 /**
698 ****************************************************************************************
699 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
700 * @note This function is used only in Indirect Read Mode.
701 * @param[in] id: which QSPI module want to transmit.
702 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
703 * @param[out] p_data: Pointer to data buffer
704 * @param[in] timeout: Timeout duration
705 *
706 * @return Result of operation.
707 ****************************************************************************************
708 */
709 uint16_t app_qspi_command_transmit_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
710
711 /**
712 ****************************************************************************************
713 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
714 * @note This function is used only in Indirect Read Mode.
715 * @param[in] id: which QSPI module want to transmit.
716 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
717 * @param[out] p_data: Pointer to data buffer
718 *
719 * @return Result of operation.
720 ****************************************************************************************
721 */
722 uint16_t app_qspi_command_transmit_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data);
723
724 /**
725 ****************************************************************************************
726 * @brief Transmit only instruction in blocking mode.
727 * @note This function is used only in Indirect Write Mode.
728 * @param[in] id: which QSPI module want to transmit command.
729 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
730 * @param[in] timeout: Timeout duration
731 *
732 * @return Result of operation.
733 ****************************************************************************************
734 */
735 uint16_t app_qspi_command_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint32_t timeout);
736
737 /**
738 ****************************************************************************************
739 * @brief Transmit instruction in non-blocking mode with Interrupt.
740 * @note This function is used only in Indirect Write Mode.
741 * @param[in] id: which QSPI module want to transmit command.
742 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
743 *
744 * @return Result of operation.
745 ****************************************************************************************
746 */
747 uint16_t app_qspi_command_async(app_qspi_id_t id, app_qspi_command_t *p_cmd);
748
749 /**
750 ****************************************************************************************
751 * @brief Transmit data without command, support std/dual/quad mode
752 *
753 * @param[in] id : QSPI module ID.
754 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
755 * @ref QSPI_DATA_MODE_DUALSPI
756 * @ref QSPI_DATA_MODE_QUADSPI
757 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
758 * @ref QSPI_DATASIZE_16_BITS
759 * @ref QSPI_DATASIZE_32_BITS
760 * @param[in] p_data : data Pointer to transmit
761 * @param[in] length : byte length of data
762 * @param[in] timeout: Timeout duration
763 *
764 * @return true/false
765 ****************************************************************************************
766 */
767 uint16_t app_qspi_transmit_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout);
768
769 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
770 /**
771 ****************************************************************************************
772 * @brief Transmit an amount of data in blocking mode with standard SPI.
773 * @note This function is used only in Indirect Write Mode.
774 * @param[in] id: which QSPI module want to transmit.
775 * @param[in] p_data: Pointer to data buffer
776 * @param[in] length: Amount of data to be sent in bytes
777 * @param[in] timeout: Timeout duration
778 *
779 * @return Result of operation.
780 ****************************************************************************************
781 */
782 uint16_t app_qspi_transmit_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout);
783 #endif
784
785 /**
786 ****************************************************************************************
787 * @brief Transmit data without command, support std/dual/quad mode
788 *
789 * @param[in] id : QSPI module ID.
790 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
791 * @ref QSPI_DATA_MODE_DUALSPI
792 * @ref QSPI_DATA_MODE_QUADSPI
793 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
794 * @ref QSPI_DATASIZE_16_BITS
795 * @ref QSPI_DATASIZE_32_BITS
796 * @param[in] p_data : data Pointer to transmit
797 * @param[in] length : byte length of data
798 *
799 * @return true/false
800 ****************************************************************************************
801 */
802 uint16_t app_qspi_transmit_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length);
803
804 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
805 /**
806 ****************************************************************************************
807 * @brief Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
808 * @note This function is used only in Indirect Write Mode.
809 * @param[in] id: which QSPI module want to transmit.
810 * @param[in] p_data: Pointer to data buffer
811 * @param[in] length: Amount of data to be sent in bytes
812 *
813 * @return Result of operation.
814 ****************************************************************************************
815 */
816 uint16_t app_qspi_transmit_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length);
817 #endif
818
819 /**
820 ****************************************************************************************
821 * @brief Receive data without command, support std/dual/quad mode
822 *
823 * @param[in] id : QSPI module ID.
824 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
825 * @ref QSPI_DATA_MODE_DUALSPI
826 * @ref QSPI_DATA_MODE_QUADSPI
827 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
828 * @ref QSPI_DATASIZE_16_BITS
829 * @ref QSPI_DATASIZE_32_BITS
830 * @param[in] p_data : data Pointer to transmit
831 * @param[in] length : byte length of data
832 * @param[in] timeout: Timeout duration
833 *
834 * @return true/false
835 ****************************************************************************************
836 */
837 uint16_t app_qspi_receive_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout);
838
839 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
840 /**
841 ****************************************************************************************
842 * @brief Receive an amount of data in blocking mode with standard SPI.
843 * @note This function is used only in Indirect Read Mode.
844 * @param[in] id: which QSPI module want to receive.
845 * @param[out] p_data: Pointer to data buffer
846 * @param[in] length: Amount of data to be received in bytes
847 * @param[in] timeout: Timeout duration
848 *
849 * @return Result of operation.
850 ****************************************************************************************
851 */
852 uint16_t app_qspi_receive_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout);
853 #endif
854
855 /**
856 ****************************************************************************************
857 * @brief Receive data without command, support std/dual/quad mode
858 *
859 * @param[in] id : QSPI module ID.
860 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
861 * @ref QSPI_DATA_MODE_DUALSPI
862 * @ref QSPI_DATA_MODE_QUADSPI
863 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
864 * @ref QSPI_DATASIZE_16_BITS
865 * @ref QSPI_DATASIZE_32_BITS
866 * @param[in] p_data : data Pointer to transmit
867 * @param[in] length : byte length of data
868 *
869 * @return true/false
870 ****************************************************************************************
871 */
872 uint16_t app_qspi_receive_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length);
873
874 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
875 /**
876 ****************************************************************************************
877 * @brief Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
878 * @note This function is used only in Indirect Read Mode.
879 * @param[in] id: which QSPI module want to receive.
880 * @param[out] p_data: Pointer to data buffer
881 * @param[in] length: Amount of data to be received in bytes
882 *
883 * @return Result of operation.
884 ****************************************************************************************
885 */
886 uint16_t app_qspi_receive_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length);
887 #endif
888
889 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
890 /**
891 ****************************************************************************************
892 * @brief Set Data Endian Mode to Read in Memory mapped Mode(XIP Mode)
893 *
894 * @param[in] id : QSPI module ID.
895 * @param[in] mode : endian mode
896 * @return true/false
897 ****************************************************************************************
898 */
899 bool app_qspi_mmap_set_endian_mode(app_qspi_id_t id, app_qspi_mmap_endian_mode_e mode);
900
901 /**
902 ****************************************************************************************
903 * @brief Read U8 Data in Memory mapped Mode(XIP Mode), can be used in flash/psram device
904 *
905 * @param[in] id : QSPI module ID.
906 * @param[in] address : the address of device connected to QSPI, start from 0x000000
907 * @return the read data
908 ****************************************************************************************
909 */
910 uint8_t app_qspi_mmap_read_u8(app_qspi_id_t id, uint32_t address) ;
911
912 /**
913 ****************************************************************************************
914 * @brief Read U16 Data in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
915 *
916 * @param[in] id : QSPI module ID.
917 * @param[in] address : the address of device connected to QSPI, start from 0x000000
918 * @return the read data
919 ****************************************************************************************
920 */
921 uint16_t app_qspi_mmap_read_u16(app_qspi_id_t id, uint32_t address);
922
923 /**
924 ****************************************************************************************
925 * @brief Read U32 Data in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
926 *
927 * @param[in] id : QSPI module ID.
928 * @param[in] address : the address of device connected to QSPI, start from 0x000000
929 * @return the read data
930 ****************************************************************************************
931 */
932 uint32_t app_qspi_mmap_read_u32(app_qspi_id_t id, uint32_t address);
933
934 /**
935 ****************************************************************************************
936 * @brief Read data block in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
937 *
938 * @param[in] id : QSPI module ID.
939 * @param[in] address : the address of device connected to QSPI, start from 0x000000
940 * @param[in] buffer : memory pointer to save the read data
941 * @param[in] length : the read length in byte
942 * @return true/false
943 ****************************************************************************************
944 */
945 bool app_qspi_mmap_read_block(app_qspi_id_t id, uint32_t address, uint8_t * buffer, uint32_t length);
946
947 /**
948 ****************************************************************************************
949 * @brief Return the XIP Base Address of QSPI Instance.
950 *
951 * @param[in] id: QSPI module ID.
952 *
953 * @return The XIP base address.
954 ****************************************************************************************
955 */
956 uint32_t app_qspi_get_xip_base_address(app_qspi_id_t id);
957
958 #endif
959
960 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
961 /**
962 ****************************************************************************************
963 * @brief Transmit an amount of data in QPI mode (Async Mode).
964 * @param[in] id: Which QSPI module want to Transmit.
965 * @param[in] data_width: Just support @ref QSPI_DATASIZE_08_BITS @ref QSPI_DATASIZE_16_BITS @ref QSPI_DATASIZE_32_BITS
966 * @param[in] p_data: Pointer to data buffer
967 * @param[in] length: Amount of data to be transmitted in bytes
968 *
969 * @return Result of operation.
970 ****************************************************************************************
971 */
972 uint16_t app_qspi_transmit_in_qpi_async(app_qspi_id_t id, uint32_t data_width, uint8_t *p_data, uint32_t length);
973 #endif
974
975 /**
976 ****************************************************************************************
977 * @brief Return the QSPI handle.
978 *
979 * @param[in] id: QSPI module ID.
980 *
981 * @return Pointer to the specified ID's QSPI handle.
982 ****************************************************************************************
983 */
984 qspi_handle_t *app_qspi_get_handle(app_qspi_id_t id);
985
986 /** @} */
987
988 #endif
989
990 #ifdef __cplusplus
991 }
992 #endif
993
994 #endif
995
996 /** @} */
997
998 /** @} */
999
1000 /** @} */
app_qspi_command_receive_sync
uint16_t app_qspi_command_receive_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
app_qspi_command_t
qspi_command_t app_qspi_command_t
QSPI command structure definition.
Definition: app_qspi.h:345
app_qspi_evt_t::size
uint16_t size
QSPI transmitted/received counter.
Definition: app_qspi.h:399
app_qspi_get_handle
qspi_handle_t * app_qspi_get_handle(app_qspi_id_t id)
Return the QSPI handle.
app_qspi_pin_t::pull
app_io_pull_t pull
Specifies the Pull-up or Pull-Down activation for the selected pins.
Definition: app_qspi.h:307
qspi_env_t::handle
qspi_handle_t handle
QSPI handle Structure.
Definition: app_qspi.h:544
app_qspi_params_t::id
app_qspi_id_t id
specified QSPI module ID.
Definition: app_qspi.h:579
APP_QSPI_ID_1
@ APP_QSPI_ID_1
QSPI module 1.
Definition: app_qspi.h:154
qspi_env_t::qspi_dma_state
app_qspi_dma_state_t qspi_dma_state
App qspi dma_state types.
Definition: app_qspi.h:551
app_qspi_transmit_sync_ex
uint16_t app_qspi_transmit_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit data without command, support std/dual/quad mode.
app_qspi_transmit_async
uint16_t app_qspi_transmit_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
qspi_env_t
QSPI device structure definition.
Definition: app_qspi.h:543
app_qspi_pin_cfg_t::io_3
app_qspi_pin_t io_3
Set the configuration of QSPI IO3 pin.
Definition: app_qspi.h:321
app_qspi_pin_t
QSPI IO configuration Structures.
Definition: app_qspi.h:301
app_qspi_command_transmit_async
uint16_t app_qspi_command_transmit_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
app_qspi_state_t
app_qspi_state_t
App qspi state types.
Definition: app_qspi.h:519
APP_QSPI_ID_0
@ APP_QSPI_ID_0
QSPI module 0.
Definition: app_qspi.h:153
app_qspi_params_t::qspi_env
qspi_env_t qspi_env
QSPI device structure definition.
Definition: app_qspi.h:583
app_qspi_evt_t
QSPI event structure definition.
Definition: app_qspi.h:394
app_io_pull_t
app_io_pull_t
GPIO pull Enumerations definition.
Definition: app_io.h:183
app_io_type_t
app_io_type_t
GPIO type Enumerations definition.
Definition: app_io.h:147
app_qspi_deinit
uint16_t app_qspi_deinit(app_qspi_id_t id)
De-initialize the APP QSPI DRIVER peripheral.
_qspi_init_t
QSPI init Structure definition.
Definition: gr55xx_hal_qspi.h:137
APP_QSPI_EVT_ERROR
@ APP_QSPI_EVT_ERROR
Error reported by QSPI peripheral.
Definition: app_qspi.h:168
app_qspi_receive_sync_ex
uint16_t app_qspi_receive_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive data without command, support std/dual/quad mode.
qspi_env_t::is_tx_done
volatile bool is_tx_done
tx done.
Definition: app_qspi.h:566
app_qspi_pin_cfg_t::cs
app_qspi_pin_t cs
Set the configuration of QSPI CS pin.
Definition: app_qspi.h:316
app_qspi_evt_t::error_code
uint32_t error_code
QSPI Error code .
Definition: app_qspi.h:398
_qspi_command_t
QSPI command Structure definition.
Definition: gr55xx_hal_qspi.h:200
app_qspi_pin_t::mux
app_io_mux_t mux
Specifies the Peripheral to be connected to the selected pins.
Definition: app_qspi.h:303
app_io_mode_t
app_io_mode_t
GPIO mode Enumerations definition.
Definition: app_io.h:163
APP_QSPI_EVT_RX_DATA
@ APP_QSPI_EVT_RX_DATA
Requested RX transfer completed.
Definition: app_qspi.h:170
qspi_env_t::is_rx_done
volatile bool is_rx_done
rx done.
Definition: app_qspi.h:565
app_qspi_id_t
app_qspi_id_t
QSPI module Enumerations definition.
Definition: app_qspi.h:152
app_qspi_dma_cfg_t
QSPI DMA configuration structure definition.
Definition: app_qspi.h:328
app_io.h
Header file containing functions prototypes of GPIO app library.
app_qspi_abort
uint16_t app_qspi_abort(app_qspi_id_t id)
Abort qspi communication with Interrupt.
app_qspi_pin_cfg_t
QSPI configuration Structures.
Definition: app_qspi.h:315
app_qspi_evt_handler_t
void(* app_qspi_evt_handler_t)(app_qspi_evt_t *p_evt)
QSPI event callback definition.
Definition: app_qspi.h:511
app_qspi_command_receive_async
uint16_t app_qspi_command_receive_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
app_qspi_command_sync
uint16_t app_qspi_command_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
app_qspi_pin_t::pin
uint32_t pin
Specifies the IO pins to be configured.
Definition: app_qspi.h:304
APP_QSPI_DMA_INVALID
@ APP_QSPI_DMA_INVALID
Definition: app_qspi.h:530
app_qspi_dma_state_t
app_qspi_dma_state_t
App qspi dma_state types.
Definition: app_qspi.h:529
qspi_env_t::dma_id
dma_id_t dma_id
DMA id.
Definition: app_qspi.h:549
APP_QSPI_EVT_ABORT
@ APP_QSPI_EVT_ABORT
Abort reported by QSPI peripheral.
Definition: app_qspi.h:171
app_qspi_receive_async_ex
uint16_t app_qspi_receive_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length)
Receive data without command, support std/dual/quad mode.
app_qspi_transmit_async_ex
uint16_t app_qspi_transmit_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length)
Transmit data without command, support std/dual/quad mode.
app_qspi_user_config.h
app_qspi_pin_t::enable
uint8_t enable
Enable or disable the pin.
Definition: app_qspi.h:308
app_qspi_receive_sync
uint16_t app_qspi_receive_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
APP_QSPI_ACTIVITY
@ APP_QSPI_ACTIVITY
Definition: app_qspi.h:521
app_qspi_pin_cfg_t::io_1
app_qspi_pin_t io_1
Set the configuration of QSPI IO1 pin.
Definition: app_qspi.h:319
APP_QSPI_EVT_TX_CPLT
@ APP_QSPI_EVT_TX_CPLT
Requested TX transfer completed.
Definition: app_qspi.h:169
app_qspi_params_t::init
qspi_init_t init
QSPI communication parameters.
Definition: app_qspi.h:582
APP_STORAGE_RAM_ID
@ APP_STORAGE_RAM_ID
Definition: app_qspi.h:160
qspi_env_t::p_pin_cfg
app_qspi_pin_cfg_t * p_pin_cfg
QSPI configuration Structures.
Definition: app_qspi.h:548
app_qspi_params_t::pin_cfg
app_qspi_pin_cfg_t pin_cfg
the pin configuration information for the specified QSPI module.
Definition: app_qspi.h:580
qspi_env_t::qspi_state
app_qspi_state_t qspi_state
App qspi state types.
Definition: app_qspi.h:550
app_dma.h
Header file containing functions prototypes of DMA app library.
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
app_qspi_command_async
uint16_t app_qspi_command_async(app_qspi_id_t id, app_qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
app_qspi_receive_async
uint16_t app_qspi_receive_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
app_qspi_transmit_in_qpi_async
uint16_t app_qspi_transmit_in_qpi_async(app_qspi_id_t id, uint32_t data_width, uint8_t *p_data, uint32_t length)
Transmit an amount of data in QPI mode (Async Mode).
app_qspi_pin_cfg_t::clk
app_qspi_pin_t clk
Set the configuration of QSPI CLK pin.
Definition: app_qspi.h:317
APP_QSPI_ID_MAX
@ APP_QSPI_ID_MAX
Only for check parameter, not used as input parameters.
Definition: app_qspi.h:158
app_qspi_evt_type_t
app_qspi_evt_type_t
APP QSPI Event Type.
Definition: app_qspi.h:167
app_qspi_params_t::dma_cfg
app_qspi_dma_cfg_t dma_cfg
QSPI DMA configuration.
Definition: app_qspi.h:581
app_qspi_dma_cfg_t::dma_instance
dma_regs_t * dma_instance
Specifies the dma instance of QSPI.
Definition: app_qspi.h:329
app_io_mux_t
app_io_mux_t
GPIO mux Enumerations definition.
Definition: app_io.h:255
qspi_env_t::evt_handler
app_qspi_evt_handler_t evt_handler
QSPI event callback.
Definition: app_qspi.h:553
APP_QSPI_DMA_ACTIVITY
@ APP_QSPI_DMA_ACTIVITY
Definition: app_qspi.h:531
app_qspi_evt_t::type
app_qspi_evt_type_t type
Type of event.
Definition: app_qspi.h:395
app_qspi_pin_t::mode
app_io_mode_t mode
Specifies the IO Mode for pins.
Definition: app_qspi.h:306
app_qspi_transmit_sync
uint16_t app_qspi_transmit_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
app_qspi_pin_cfg_t::io_2
app_qspi_pin_t io_2
Set the configuration of QSPI IO2 pin.
Definition: app_qspi.h:320
app_drv_error.h
Header file of app driver error code.
app_drv_config.h
Header file of app driver config code.
app_qspi_pin_t::type
app_io_type_t type
Specifies the type of QSPI IO.
Definition: app_qspi.h:302
app_qspi_init
uint16_t app_qspi_init(app_qspi_params_t *p_params, app_qspi_evt_handler_t evt_handler)
Initialize the APP QSPI DRIVER according to the specified parameters in the app_qspi_params_t and app...
_qspi_handle
QSPI handle Structure definition.
Definition: gr55xx_hal_qspi.h:157
qspi_env_t::is_xfer_err
volatile bool is_xfer_err
xfer err.
Definition: app_qspi.h:567
app_qspi_command_transmit_sync
uint16_t app_qspi_command_transmit_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
app_qspi_params_t
QSPI parameters structure definition.
Definition: app_qspi.h:578
dma_id_t
int16_t dma_id_t
DMA id definition.
Definition: app_dma.h:98
app_qspi_pin_cfg_t::io_0
app_qspi_pin_t io_0
Set the configuration of QSPI IO0 pin.
Definition: app_qspi.h:318
app_qspi_dma_cfg_t::dma_channel
dma_channel_t dma_channel
Specifies the dma channel of QSPI.
Definition: app_qspi.h:330
qspi_env_t::start_flag
volatile bool start_flag
start flag.
Definition: app_qspi.h:552
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr55xx_hal_dma.h:94
APP_QSPI_INVALID
@ APP_QSPI_INVALID
Definition: app_qspi.h:520