gr55xx_ll_aon_rf.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_rf.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON RF LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_RF AON_RF
47 * @brief AON RF LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_RF_H_
53 #define __GR55XX_LL_AON_RF_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61
62 /** @defgroup AON_RF_LL_DRIVER_FUNCTIONS Functions
63 * @{
64 */
65
66 /**
67 * @brief Enable the test mux 0 tri state
68 *
69 * Register|BitsName
70 * --------|--------
71 * RF5 | TEST_MUX_EN
72 *
73 */
74 __STATIC_INLINE void ll_aon_rf_enable_test_mux(void)
75 {
76 SET_BITS(AON_RF->RF5, AON_RF_RF5_TEST_MUX_EN);
77 }
78
79 /**
80 * @brief Disable the test mux 0 tri state
81 *
82 * Register|BitsName
83 * --------|--------
84 * RF5 | TEST_MUX_EN
85 *
86 */
87 __STATIC_INLINE void ll_aon_rf_disable_test_mux(void)
88 {
89 CLEAR_BITS(AON_RF->RF5, AON_RF_RF5_TEST_MUX_EN);
90 }
91
92 /**
93 * @brief Enable the cpll reset
94 *
95 * Register|BitsName
96 * --------|--------
97 * RF6 | CPLL_CP_EN
98 *
99 */
100 __STATIC_INLINE void ll_aon_rf_enable_cpll_cp_reset(void)
101 {
102 SET_BITS(AON_RF->RF6, AON_RF_RF6_CPLL_CP_EN);
103 }
104
105 /**
106 * @brief Disable the cpll reset
107 *
108 * Register|BitsName
109 * --------|--------
110 * RF6 | CPLL_CP_EN
111 *
112 */
113 __STATIC_INLINE void ll_aon_rf_disable_cpll_cp_reset(void)
114 {
115 CLEAR_BITS(AON_RF->RF6, AON_RF_RF6_CPLL_CP_EN);
116 }
117
118 /**
119 * @brief Enable the cpll drift detection
120 *
121 * Register|BitsName
122 * --------|--------
123 * RF6 | PLL_LOCK_DET_EN
124 *
125 */
126 __STATIC_INLINE void ll_aon_rf_enable_cpll_drift_detection(void)
127 {
128 SET_BITS(AON_RF->RF6, AON_RF_RF6_PLL_LOCK_DET_EN);
129 }
130
131 /**
132 * @brief Disable the cpll drift detection
133 *
134 * Register|BitsName
135 * --------|--------
136 * RF6 | PLL_LOCK_DET_EN
137 *
138 */
139 __STATIC_INLINE void ll_aon_rf_disable_cpll_drift_detection(void)
140 {
141 CLEAR_BITS(AON_RF->RF6, AON_RF_RF6_PLL_LOCK_DET_EN);
142 }
143
144 /**
145 * @brief Set the cpll m div,Pre division before CP (00- no division / 11 divide by 16).
146 *
147 * Register|BitsName
148 * --------|--------
149 * RF6 | CPLL_M_DIV_CTRL
150 *
151 * @param value: The cpll m div value.
152 *
153 */
154 __STATIC_INLINE void ll_aon_rf_set_cpll_m_div(uint32_t value)
155 {
156 MODIFY_REG(AON_RF->RF6, AON_RF_RF6_CPLL_M_DIV_CTRL, (value << AON_RF_RF6_CPLL_M_DIV_CTRL_Pos));
157 }
158
159 /**
160 * @brief Set the cpll drift detection.
161 *
162 * Register|BitsName
163 * --------|--------
164 * RF7 | L_H_THRESHOLD
165 *
166 * @param l_threshold: L Threshold.
167 * @param h_threshold: H Threshold.
168 *
169 */
170 __STATIC_INLINE void ll_aon_rf_set_threshold(uint32_t l_threshold, uint32_t h_threshold)
171 {
172 MODIFY_REG(AON_RF->RF7, AON_RF_RF7_L_H_THRESHOLD, (((h_threshold << 2) | l_threshold) << AON_RF_RF7_L_H_THRESHOLD_Pos));
173 }
174
175 /**
176 * @brief Set the cpll drift CPLL VCO KVCO control.
177 *
178 * Register|BitsName
179 * --------|--------
180 * RF7 | cpll_kvco_dig_ctrl_2_0
181 *
182 * @param code
183 *
184 */
185 __STATIC_INLINE void ll_aon_rf_set_cpll_kvco_ctrl(uint32_t code)
186 {
187 MODIFY_REG(AON_RF->RF7, AON_RF_RF7_CPLL_KVOC_CTRL, (code << AON_RF_RF7_CPLL_KVOC_CTRL_Pos));
188 }
189 /**
190 * @brief Set XO core current programmability.
191 *
192 * Register|BitsName
193 * --------|--------
194 * RF8 | XO_IBIAS_CTRL_4_0
195 *
196 * @param hi_value
197 * @param lo_value
198 * @retval None
199 *
200 */
201 __STATIC_INLINE void ll_aon_rf_set_xo_ibias(uint32_t hi_value,uint32_t lo_value)
202 {
203 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_BIAS_HI, (hi_value << AON_RF_XO_BIAS_HI_Pos));
204 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_BIAS_LO, (lo_value << AON_RF_XO_BIAS_LO_Pos));
205 }
206
207 /**
208 * @brief Set the RF_REG9
209 *
210 * Register|BitsName
211 * --------|--------
212 * RF9 | ALL
213 *
214 * @param value: The RF_REG9 value.
215 *
216 */
217 __STATIC_INLINE void ll_aon_rf_set_rf_reg9(uint32_t value)
218 {
219 WRITE_REG(AON_RF->RF9, value);
220 }
221
222 /**
223 * @brief Get the RF_REG9
224 *
225 * Register|BitsName
226 * --------|--------
227 * RF9 | ALL
228 *
229 * @retval The RF_REG9 value.
230 *
231 */
232 __STATIC_INLINE uint32_t ll_aon_rf_get_rf_reg9(void)
233 {
234 return READ_REG(AON_RF->RF9);
235 }
236
237
238 /**
239 * @brief Set the xo cap value,cload programmability from 50fF to 26pF on each side.
240 *
241 * Register|BitsName
242 * --------|--------
243 * RF9 | XO_CAP
244 *
245 * @param hi_value: The xo cap value.
246 * @param lo_value: The xo cap value.
247 */
248 __STATIC_INLINE void ll_aon_rf_set_xo_cap(uint32_t hi_value,uint32_t lo_value)
249 {
250 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_CAP_HI, (hi_value << AON_RF_XO_CAP_HI_Pos));
251 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_CAP_LO, (lo_value << AON_RF_XO_CAP_LO_Pos));
252 }
253
254 /**
255 * @brief Get the cpll crscde
256 *
257 * Register|BitsName
258 * --------|--------
259 * RF_RD_REG_0 | CPLL_CRSCDE
260 *
261 * @retval cpll crscde.
262 *
263 */
264 __STATIC_INLINE uint32_t ll_aon_rf_get_cpll_crscde(void)
265 {
266 return (READ_BITS(AON_RF->RF_RD_REG_0, AON_RF_RF_RD_REG_0_CPLL_CRSCDE) >> AON_RF_RF_RD_REG_0_CPLL_CRSCDE_Pos);
267 }
268 /**
269 * @brief Set SU enable.
270 *
271 * Register|BitsName
272 * --------|--------
273 * RF8 | SU_ENABLE
274 *
275 * @retval None
276 *
277 */
278 __STATIC_INLINE void ll_aon_rf_set_su_enable(void)
279 {
280 SET_BITS(AON_RF->RF8, AON_RF_RF8_SU_EN);
281 }
282 /**
283 * @brief Set cpll drift irq enable.
284 *
285 * Register|BitsName
286 * --------|--------
287 * CPLL_IRQ_CFG | MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN
288 *
289 * @retval None
290 *
291 */
292 __STATIC_INLINE void ll_mcu_set_cpll_drift_irq_enable(void)
293 {
294 SET_BITS(MCU_SUB->CPLL_IRQ_CFG, MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN);
295 }
296
297 /**
298 * @brief Set cpll drift irq disable.
299 *
300 * Register|BitsName
301 * --------|--------
302 * CPLL_IRQ_CFG | MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN
303 *
304 * @retval None
305 *
306 */
307 __STATIC_INLINE void ll_mcu_set_cpll_drift_irq_disable(void)
308 {
309 CLEAR_BITS(MCU_SUB->CPLL_IRQ_CFG, MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN);
310 }
311
312 /**
313 * @brief clear cpll drift irq.
314 *
315 * Register|BitsName
316 * --------|--------
317 * CPLL_IRQ_CFG | cpll_drift_irq_clr
318 *
319 * @retval None
320 *
321 */
322 __STATIC_INLINE void ll_mcu_clear_cpll_drift_irq(void)
323 {
324 SET_BITS(MCU_SUB->CPLL_IRQ_CFG, MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_CLR);
325 }
326
327 /** @} */
328 #endif
329
330 /** @} */
331 /** @} */
332 /** @} */
333
ll_aon_rf_disable_cpll_cp_reset
__STATIC_INLINE void ll_aon_rf_disable_cpll_cp_reset(void)
Disable the cpll reset.
Definition: gr55xx_ll_aon_rf.h:113
ll_mcu_set_cpll_drift_irq_enable
__STATIC_INLINE void ll_mcu_set_cpll_drift_irq_enable(void)
Set cpll drift irq enable.
Definition: gr55xx_ll_aon_rf.h:292
ll_aon_rf_get_rf_reg9
__STATIC_INLINE uint32_t ll_aon_rf_get_rf_reg9(void)
Get the RF_REG9.
Definition: gr55xx_ll_aon_rf.h:232
ll_aon_rf_set_rf_reg9
__STATIC_INLINE void ll_aon_rf_set_rf_reg9(uint32_t value)
Set the RF_REG9.
Definition: gr55xx_ll_aon_rf.h:217
ll_aon_rf_enable_cpll_cp_reset
__STATIC_INLINE void ll_aon_rf_enable_cpll_cp_reset(void)
Enable the cpll reset.
Definition: gr55xx_ll_aon_rf.h:100
ll_aon_rf_set_threshold
__STATIC_INLINE void ll_aon_rf_set_threshold(uint32_t l_threshold, uint32_t h_threshold)
Set the cpll drift detection.
Definition: gr55xx_ll_aon_rf.h:170
ll_mcu_set_cpll_drift_irq_disable
__STATIC_INLINE void ll_mcu_set_cpll_drift_irq_disable(void)
Set cpll drift irq disable.
Definition: gr55xx_ll_aon_rf.h:307
ll_mcu_clear_cpll_drift_irq
__STATIC_INLINE void ll_mcu_clear_cpll_drift_irq(void)
clear cpll drift irq.
Definition: gr55xx_ll_aon_rf.h:322
ll_aon_rf_get_cpll_crscde
__STATIC_INLINE uint32_t ll_aon_rf_get_cpll_crscde(void)
Get the cpll crscde.
Definition: gr55xx_ll_aon_rf.h:264
ll_aon_rf_set_cpll_m_div
__STATIC_INLINE void ll_aon_rf_set_cpll_m_div(uint32_t value)
Set the cpll m div,Pre division before CP (00- no division / 11 divide by 16).
Definition: gr55xx_ll_aon_rf.h:154
ll_aon_rf_enable_test_mux
__STATIC_INLINE void ll_aon_rf_enable_test_mux(void)
Enable the test mux 0 tri state.
Definition: gr55xx_ll_aon_rf.h:74
ll_aon_rf_set_cpll_kvco_ctrl
__STATIC_INLINE void ll_aon_rf_set_cpll_kvco_ctrl(uint32_t code)
Set the cpll drift CPLL VCO KVCO control.
Definition: gr55xx_ll_aon_rf.h:185
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_aon_rf_enable_cpll_drift_detection
__STATIC_INLINE void ll_aon_rf_enable_cpll_drift_detection(void)
Enable the cpll drift detection.
Definition: gr55xx_ll_aon_rf.h:126
ll_aon_rf_set_su_enable
__STATIC_INLINE void ll_aon_rf_set_su_enable(void)
Set SU enable.
Definition: gr55xx_ll_aon_rf.h:278
ll_aon_rf_set_xo_ibias
__STATIC_INLINE void ll_aon_rf_set_xo_ibias(uint32_t hi_value, uint32_t lo_value)
Set XO core current programmability.
Definition: gr55xx_ll_aon_rf.h:201
ll_aon_rf_set_xo_cap
__STATIC_INLINE void ll_aon_rf_set_xo_cap(uint32_t hi_value, uint32_t lo_value)
Set the xo cap value,cload programmability from 50fF to 26pF on each side.
Definition: gr55xx_ll_aon_rf.h:248
ll_aon_rf_disable_cpll_drift_detection
__STATIC_INLINE void ll_aon_rf_disable_cpll_drift_detection(void)
Disable the cpll drift detection.
Definition: gr55xx_ll_aon_rf.h:139
ll_aon_rf_disable_test_mux
__STATIC_INLINE void ll_aon_rf_disable_test_mux(void)
Disable the test mux 0 tri state.
Definition: gr55xx_ll_aon_rf.h:87