gr55xx_ll_aes.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aes.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AES LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AES AES
47 * @brief AES LL module driver.
48 * @{
49 */
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "gr55xx.h"
60
61 #if defined (AES)
62
63 /** @defgroup AES_LL_STRUCTURES Structures
64 * @{
65 */
66
67 /* Exported types ------------------------------------------------------------*/
68 /** @defgroup AES_LL_ES_INIT AES Exported Init structures
69 * @{
70 */
71
72 /**
73 * @brief LL AES Init Structure definition
74 */
75 typedef struct _ll_aes_init
76 {
77 uint32_t key_size; /**< 128, 192 or 256-bit key length.
78 This parameter can be a value of @ref AES_LL_EC_KEY_SIZE */
79
80 uint32_t *p_key; /**< Encryption/Decryption Key */
81
82 uint32_t *p_init_vector; /**< Initialization Vector used for CBC modes */
83
84 uint32_t *p_seed; /**< Random seeds */
85
86 } ll_aes_init_t;
87
88 /** @} */
89
90 /** @} */
91
92 /**
93 * @defgroup AES_LL_MACRO Defines
94 * @{
95 */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup AES_LL_Exported_Constants AES Exported Constants
99 * @{
100 */
101
102 /** @defgroup AES_LL_EC_GET_FLAG Get Flag Defines
103 * @brief Flag definitions which can be used with LL_AES_ReadReg function
104 * @{
105 */
106 #define LL_AES_FLAG_DATAREADY AES_STAT_READY /**< AES result data out ready */
107 #define LL_AES_FLAG_DMA_DONE AES_STAT_DMA_XFE_CPLT /**< AES dma transfer done */
108 #define LL_AES_FLAG_DMA_ERR AES_STAT_DMA_XFE_ERR /**< AES dma transfer error */
109 #define LL_AES_FLAG_KEY_VALID AES_STAT_KEY_STAT /**< AES has fetched key */
110 /** @} */
111
112 /** @defgroup AES_LL_EC_KEY_SIZE Key Size
113 * @{
114 */
115 #define LL_AES_KEY_SIZE_128 0x00000000U /**< 128 bits */
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CFG_KEY_MODE_POS) /**< 192 bits */
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CFG_KEY_MODE_POS) /**< 256 bits */
118 /** @} */
119
120 /** @defgroup AES_LL_EC_OPERATION_MODE Operation Mode
121 * @{
122 */
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U /**< Electronic codebook (ECB) mode */
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CFG_OPT_MODE_POS) /**< Cipher block chaining (CBC) mode */
125 /** @} */
126
127 /** @defgroup AES_LL_EC_KEY_TYPE Key Type
128 * @{
129 */
130 #define LL_AES_KEYTYPE_MCU 0x00000000U /**< MCU */
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CFG_KEY_TYPE_POS) /**< AHB master */
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CFG_KEY_TYPE_POS) /**< Key Port */
133 /** @} */
134
135 /** @defgroup AES_LL_EC_TRANSFER_SIZE Transfer Size
136 * @{
137 */
138 #define LL_AES_DMA_TRANSIZE_MIN (1) /**< Min size = 1 block */
139 #define LL_AES_DMA_TRANSIZE_MAX (2048) /**< Max size = 2048 blocks */
140 /** @} */
141
142 /** @} */
143
144 /* Exported macro ------------------------------------------------------------*/
145 /** @defgroup AES_LL_Exported_Macros AES Exported Macros
146 * @{
147 */
148
149 /** @defgroup AES_LL_EM_WRITE_READ Common Write and read registers Macros
150 * @{
151 */
152
153 /**
154 * @brief Write a value in AES register
155 * @param __INSTANCE__ AES Instance
156 * @param __REG__ Register to be written
157 * @param __VALUE__ Value to be written in the register
158 * @retval None
159 */
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
161
162 /**
163 * @brief Read a value in AES register
164 * @param __INSTANCE__ AES Instance
165 * @param __REG__ Register to be read
166 * @retval Register value
167 */
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
169
170 /** @} */
171
172 /** @} */
173
174 /** @} */
175
176 /* Exported functions --------------------------------------------------------*/
177 /** @defgroup AES_LL_DRIVER_FUNCTIONS Functions
178 * @{
179 */
180
181 /** @defgroup AES_LL_EF_Configuration Configuration functions
182 * @{
183 */
184
185 /**
186 * @brief Enable AES.
187 *
188 * Register|BitsName
189 * ---------------|---------------
190 * CTRL | MODULE_EN
191 *
192 * @param AESx AES instance
193 * @retval None
194 */
195 __STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
196 {
197 SET_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
198 }
199
200 /**
201 * @brief Disable AES.
202 *
203 * Register|BitsName
204 * ---------------|---------------
205 * CTRL | MODULE_EN
206 *
207 * @param AESx AES instance
208 * @retval None
209 */
210 __STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
211 {
212 CLEAR_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
213 }
214
215 /**
216 * @brief Indicate whether the AES is enabled.
217 *
218 * Register|BitsName
219 * ---------------|---------------
220 * CTRL | MODULE_EN
221 *
222 * @param AESx AES instance
223 * @retval State of bit (1 or 0).
224 */
225 __STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
226 {
227 return (READ_BITS(AESx->CTRL, AES_CTRL_MODULE_EN) == (AES_CTRL_MODULE_EN));
228 }
229
230 /**
231 * @brief Enable AES start in MCU mode.
232 *
233 * Register|BitsName
234 * ---------------|---------------
235 * CTRL | MCU_MODE_EN
236 *
237 * @param AESx AES instance
238 * @retval None
239 */
240 __STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
241 {
242 SET_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
243 }
244
245 /**
246 * @brief Disable AES start in MCU mode.
247 *
248 * Register|BitsName
249 * ---------------|---------------
250 * CTRL | MCU_MODE_EN
251 *
252 * @param AESx AES instance
253 * @retval None
254 */
255 __STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
256 {
257 CLEAR_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
258 }
259
260 /**
261 * @brief Indicate whether the AES start in MCU mode is enabled.
262 *
263 * Register|BitsName
264 * ---------------|---------------
265 * CTRL | MCU_MODE_EN
266 *
267 * @param AESx AES instance
268 * @retval State of bit (1 or 0).
269 */
270 __STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
271 {
272 return (READ_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN) == (AES_CTRL_MCU_MODE_EN));
273 }
274
275 /**
276 * @brief Enable AES DMA mode.
277 *
278 * Register|BitsName
279 * ---------------|---------------
280 * CTRL | DMA_MODE_EN
281 *
282 * @param AESx AES instance
283 * @retval None
284 */
285 __STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
286 {
287 SET_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
288 }
289
290 /**
291 * @brief Disable AES DMA mode.
292 *
293 * Register|BitsName
294 * ---------------|---------------
295 * CTRL | DMA_MODE_EN
296 *
297 * @param AESx AES instance
298 * @retval None
299 */
300 __STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
301 {
302 CLEAR_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
303 }
304
305 /**
306 * @brief Indicate whether the AES DMA mode is enabled.
307 *
308 * Register|BitsName
309 * ---------------|---------------
310 * CTRL | DMA_MODE_EN
311 *
312 * @param AESx AES instance
313 * @retval State of bit (1 or 0).
314 */
315 __STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
316 {
317 return (READ_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN) == (AES_CTRL_DMA_MODE_EN));
318 }
319
320 /**
321 * @brief Enable fetch key through AHB/key port.
322 *
323 * Register|BitsName
324 * ---------------|---------------
325 * CTRL | FKEY_EN
326 *
327 * @param AESx AES instance
328 * @retval None
329 */
330 __STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
331 {
332 SET_BITS(AESx->CTRL, AES_CTRL_FKEY_EN);
333 }
334
335 /**
336 * @brief Set AES key size.
337 *
338 * Register|BitsName
339 * ---------------|---------------
340 * CFG | KEY_MODE
341 *
342 * @param AESx AES instance
343 * @param size This parameter can be one of the following values:
344 * @arg @ref LL_AES_KEY_SIZE_128
345 * @arg @ref LL_AES_KEY_SIZE_192
346 * @arg @ref LL_AES_KEY_SIZE_256
347 * @retval None
348 */
349 __STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
350 {
351 MODIFY_REG(AESx->CFG, AES_CFG_KEY_MODE, size);
352 }
353
354 /**
355 * @brief Get AES key size.
356 *
357 * Register|BitsName
358 * ---------------|---------------
359 * CFG | KEY_MODE
360 *
361 * @param AESx AES instance
362 * @retval Returned value can be one of the following values:
363 * @arg @ref LL_AES_KEY_SIZE_128
364 * @arg @ref LL_AES_KEY_SIZE_192
365 * @arg @ref LL_AES_KEY_SIZE_256
366 */
367 __STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
368 {
369 return (READ_BITS(AESx->CFG, AES_CFG_KEY_MODE));
370 }
371
372 /**
373 * @brief Enable AES full mask.
374 *
375 * Register|BitsName
376 * ---------------|---------------
377 * CFG | FULL_MASK_EN
378 *
379 * @param AESx AES instance
380 * @retval None
381 */
382 __STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
383 {
384 SET_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
385 }
386
387 /**
388 * @brief Disable AES full mask.
389 *
390 * Register|BitsName
391 * ---------------|---------------
392 * CFG | FULL_MASK_EN
393 *
394 * @param AESx AES instance
395 * @retval None
396 */
397 __STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
398 {
399 CLEAR_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
400 }
401
402 /**
403 * @brief Indicate whether the AES full mask is enabled.
404 *
405 * Register|BitsName
406 * ---------------|---------------
407 * CFG | FULL_MASK_EN
408 *
409 * @param AESx AES instance
410 * @retval State of bit (1 or 0).
411 */
412 __STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
413 {
414 return (READ_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN) == (AES_CFG_FULL_MASK_EN));
415 }
416
417 /**
418 * @brief Enable AES encryption mode.
419 *
420 * Register|BitsName
421 * ---------------|---------------
422 * CFG | DEC_ENC_SEL
423 *
424 * @param AESx AES instance
425 * @retval None
426 */
427 __STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
428 {
429 SET_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
430 }
431
432 /**
433 * @brief Disable AES encryption mode.
434 *
435 * Register|BitsName
436 * ---------------|---------------
437 * CFG | DEC_ENC_SEL
438 *
439 * @param AESx AES instance
440 * @retval None
441 */
442 __STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
443 {
444 CLEAR_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
445 }
446
447 /**
448 * @brief Indicate whether the AES encryption mode is enabled.
449 *
450 * Register|BitsName
451 * ---------------|---------------
452 * CFG | DEC_ENC_SEL
453 *
454 * @param AESx AES instance
455 * @retval State of bit (1 or 0).
456 */
457 __STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
458 {
459 return (READ_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL) == (AES_CFG_DEC_ENC_SEL));
460 }
461
462 /**
463 * @brief Set AES to load seed for LFSR.
464 *
465 * Register|BitsName
466 * ---------------|---------------
467 * CFG | LOAD_SEED
468 *
469 * @param AESx AES instance
470 * @retval None
471 */
472 __STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
473 {
474 SET_BITS(AESx->CFG, AES_CFG_LOAD_SEED);
475 }
476
477 /**
478 * @brief Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
479 *
480 * Register|BitsName
481 * ---------------|---------------
482 * CFG | FIRST_BLK
483 *
484 * @param AESx AES instance
485 * @retval None
486 */
487 __STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
488 {
489 SET_BITS(AESx->CFG, AES_CFG_FIRST_BLK);
490 }
491
492 /**
493 * @brief Enable AES in little endian.
494 *
495 * Register|BitsName
496 * ---------------|---------------
497 * CFG | ENDIAN
498 *
499 * @param AESx AES instance
500 * @retval None
501 */
502 __STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
503 {
504 SET_BITS(AESx->CFG, AES_CFG_ENDIAN);
505 }
506
507 /**
508 * @brief Disable AES in little endian.
509 *
510 * Register|BitsName
511 * ---------------|---------------
512 * CFG | ENDIAN
513 *
514 * @param AESx AES instance
515 * @retval None
516 */
517 __STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
518 {
519 CLEAR_BITS(AESx->CFG, AES_CFG_ENDIAN);
520 }
521
522 /**
523 * @brief Indicate whether the AES is in little endian.
524 *
525 * Register|BitsName
526 * ---------------|---------------
527 * CFG | ENDIAN
528 *
529 * @param AESx AES instance
530 * @retval State of bit (1 or 0).
531 */
532 __STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
533 {
534 return (READ_BITS(AESx->CFG, AES_CFG_ENDIAN) == (AES_CFG_ENDIAN));
535 }
536
537 /**
538 * @brief Set AES operation mode.
539 *
540 * Register|BitsName
541 * ---------------|---------------
542 * CFG | OPT_MODE
543 *
544 * @param AESx AES instance
545 * @param mode This parameter can be one of the following values:
546 * @arg @ref LL_AES_OPERATION_MODE_ECB
547 * @arg @ref LL_AES_OPERATION_MODE_CBC
548 * @retval None
549 */
550 __STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
551 {
552 MODIFY_REG(AESx->CFG, AES_CFG_OPT_MODE, mode);
553 }
554
555 /**
556 * @brief Get AES operation mode.
557 *
558 * Register|BitsName
559 * ---------------|---------------
560 * CFG | OPT_MODE
561 *
562 * @param AESx AES instance
563 * @retval Returned value can be one of the following values:
564 * @arg @ref LL_AES_OPERATION_MODE_ECB
565 * @arg @ref LL_AES_OPERATION_MODE_CBC
566 */
567 __STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
568 {
569 return (READ_BITS(AESx->CFG, AES_CFG_OPT_MODE));
570 }
571
572 /**
573 * @brief Set ways to obtain AES key.
574 *
575 * Register|BitsName
576 * ---------------|---------------
577 * CFG | KEY_TYPE
578 *
579 * @param AESx AES instance
580 * @param Type This parameter can be one of the following values:
581 * @arg @ref LL_AES_KEYTYPE_MCU
582 * @arg @ref LL_AES_KEYTYPE_AHB
583 * @arg @ref LL_AES_KEYTYPE_KRAM
584 * @retval None
585 */
586 __STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
587 {
588 MODIFY_REG(AESx->CFG, AES_CFG_KEY_TYPE, Type);
589 }
590
591 /**
592 * @brief Get ways to obtain AES key.
593 *
594 * Register|BitsName
595 * ---------------|---------------
596 * CFG | KEY_TYPE
597 *
598 * @param AESx AES instance
599 * @retval Returned value can be one of the following values:
600 * @arg @ref LL_AES_KEYTYPE_MCU
601 * @arg @ref LL_AES_KEYTYPE_AHB
602 * @arg @ref LL_AES_KEYTYPE_KRAM
603 */
604 __STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
605 {
606 return (READ_BITS(AESx->CFG, AES_CFG_KEY_TYPE));
607 }
608
609 /** @} */
610
611 /** @defgroup AES_LL_EF_IT_Management IT_Management
612 * @{
613 */
614
615 /**
616 * @brief Enable AES the done interrupt.
617 *
618 * Register|BitsName
619 * ---------------|---------------
620 * INT | CPLT_INT_EN
621 *
622 * @param AESx AES instance
623 * @retval None
624 */
625 __STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
626 {
627 SET_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
628 }
629
630 /**
631 * @brief Disable AES the done interrupt.
632 *
633 * Register|BitsName
634 * ---------------|---------------
635 * INT | CPLT_INT_EN
636 *
637 * @param AESx AES instance
638 * @retval None
639 */
640 __STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
641 {
642 CLEAR_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
643 }
644
645 /**
646 * @brief Indicate whether the done interrupt is enabled.
647 *
648 * Register|BitsName
649 * ---------------|---------------
650 * INT | CPLT_INT_EN
651 *
652 * @param AESx AES instance
653 * @retval State of bit (1 or 0).
654 */
655 __STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
656 {
657 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_EN) == (AES_INT_CPLT_INT_EN));
658 }
659
660 /** @} */
661
662 /** @defgroup AES_LL_EF_FLAG_Management FLAG_Management
663 * @{
664 */
665
666 /**
667 * @brief Indicate whether the ready flag is set.
668 *
669 * Register|BitsName
670 * ---------------|---------------
671 * STAT | READY
672 *
673 * @param AESx AES instance
674 * @retval State of bit (1 or 0).
675 */
676 __STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
677 {
678 return (READ_BITS(AESx->STAT, AES_STAT_READY) == AES_STAT_READY);
679 }
680
681 /**
682 * @brief Indicate whether the DMA transfer done flag is set.
683 *
684 * Register|BitsName
685 * ---------------|---------------
686 * STAT | DMA_XFE_CPLT
687 *
688 * @param AESx AES instance
689 * @retval State of bit (1 or 0).
690 */
691 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
692 {
693 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_CPLT) == AES_STAT_DMA_XFE_CPLT);
694 }
695
696 /**
697 * @brief Indicate whether the DMA transfer error flag is set.
698 *
699 * Register|BitsName
700 * ---------------|---------------
701 * STAT | DMA_XFE_ERR
702 *
703 * @param AESx AES instance
704 * @retval State of bit (1 or 0).
705 */
706 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
707 {
708 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_ERR) == AES_STAT_DMA_XFE_ERR);
709 }
710
711 /**
712 * @brief Indicate whether the key valid flag is set.
713 *
714 * Register|BitsName
715 * ---------------|---------------
716 * STAT | KEY_STAT
717 *
718 * @param AESx AES instance
719 * @retval State of bit (1 or 0).
720 */
721 __STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
722 {
723 return (READ_BITS(AESx->STAT, AES_STAT_KEY_STAT) == AES_STAT_KEY_STAT);
724 }
725
726 /**
727 * @brief Indicate whether the done interrupt flag is set.
728 *
729 * Register|BitsName
730 * ---------------|---------------
731 * INT | CPLT_INT_FLAG
732 *
733 * @param AESx AES instance
734 * @retval State of bit (1 or 0).
735 */
736 __STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
737 {
738 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG) == AES_INT_CPLT_INT_FLAG);
739 }
740
741 /**
742 * @brief Clear the done interrupt flag.
743 *
744 * Register|BitsName
745 * ---------------|---------------
746 * INT | CPLT_INT_FLAG
747 *
748 * @param AESx AES instance
749 * @retval None
750 */
751 __STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
752 {
753 SET_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG);
754 }
755
756 /** @} */
757
758 /** @defgroup AES_LL_EF_DMA_Management DMA_Management
759 * @{
760 */
761
762 /**
763 * @brief Set AES transfer blocks in DMA mode.
764 *
765 * Register|BitsName
766 * ---------------|---------------
767 * XFE_SIZE | SIZE
768 *
769 * @param AESx AES instance
770 * @param block This parameter can be one of the following values: 1 ~ 2048.
771 * @retval None
772 */
773 __STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
774 {
775 MODIFY_REG(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE, (block << 4) - 1);
776 }
777
778 /**
779 * @brief Get AES transfer blocks in DMA mode.
780 *
781 * Register|BitsName
782 * ---------------|---------------
783 * XFE_SIZE | SIZE
784 *
785 * @param AESx AES instance
786 * @retval Return value between 1 and 2048.
787 */
788 __STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
789 {
790 return ((READ_BITS(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE) + 1) >> 4);
791 }
792
793 /**
794 * @brief Set AES read address of RAM in DMA mode.
795 * @note This read address of RAM requires 4 byte alignment.
796 *
797 * Register|BitsName
798 * ---------------|---------------
799 * RD_START_ADDR | ADDR
800 *
801 * @param AESx AES instance
802 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
803 * @retval None
804 */
805 __STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
806 {
807 WRITE_REG(AESx->RD_START_ADDR, address);
808 }
809
810 /**
811 * @brief Get AES read address of RAM in DMA mode.
812 *
813 * Register|BitsName
814 * ---------------|---------------
815 * RD_START_ADDR | ADDR
816 *
817 * @param AESx AES instance
818 * @retval Returned value is the read address in RAM.
819 */
820 __STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
821 {
822 return (READ_REG(AESx->RD_START_ADDR));
823 }
824
825 /**
826 * @brief Set AES write address of RAM in DMA mode.
827 * @note This write address of RAM requires 4 byte alignment.
828 *
829 * Register|BitsName
830 * ---------------|---------------
831 * WR_START_ADDR | ADDR
832 *
833 * @param AESx AES instance
834 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
835 * @retval None
836 */
837 __STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
838 {
839 WRITE_REG(AESx->WR_START_ADDR, address);
840 }
841
842 /**
843 * @brief Get AES write address of RAM in DMA mode.
844 *
845 * Register|BitsName
846 * ---------------|---------------
847 * WR_START_ADDR | ADDR
848 *
849 * @param AESx AES instance
850 * @retval Returned value is the wrute address in RAM
851 */
852 __STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
853 {
854 return (READ_REG(AESx->WR_START_ADDR));
855 }
856
857 /** @} */
858
859 /** @defgroup AES_LL_EF_Data_Management Data_Management
860 * @{
861 */
862
863 /**
864 * @brief Set AES key address in memory.
865 *
866 * Register|BitsName
867 * ---------------|---------------
868 * KEY_ADDR | ADDR
869 *
870 * @param AESx AES instance
871 * @param address This parameter can be one of the address in RAM
872 * @retval None
873 */
874 __STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
875 {
876 WRITE_REG(AESx->KEY_ADDR, address);
877 }
878
879 /**
880 * @brief Get AES key address in memory.
881 *
882 * Register|BitsName
883 * ---------------|---------------
884 * KEY_ADDR | ADDR
885 *
886 * @param AESx AES instance
887 * @retval Returned value is the key address in RAM.
888 */
889 __STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
890 {
891 return (READ_REG(AESx->KEY_ADDR));
892 }
893
894 /**
895 * @brief Get AES output data[127:96].
896 *
897 * Register|BitsName
898 * ---------------|---------------
899 * DATA_OUT0 | DATA
900 *
901 * @param AESx AES instance
902 * @retval Output Data[127:96]
903 */
904 __STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
905 {
906 return (READ_REG(AESx->DATA_OUT0));
907 }
908
909 /**
910 * @brief Get AES output data[95:64].
911 *
912 * Register|BitsName
913 * ---------------|---------------
914 * DATA_OUT1 | DATA
915 *
916 * @param AESx AES instance
917 * @retval Output Data[95:64]
918 */
919 __STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
920 {
921 return (READ_REG(AESx->DATA_OUT1));
922 }
923
924 /**
925 * @brief Get AES output data[63:32].
926 *
927 * Register|BitsName
928 * ---------------|---------------
929 * DATA_OUT2 | DATA
930 *
931 * @param AESx AES instance
932 * @retval Output Data[63:32]
933 */
934 __STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
935 {
936 return (READ_REG(AESx->DATA_OUT2));
937 }
938
939 /**
940 * @brief Get AES output data[31:0].
941 *
942 * Register|BitsName
943 * ---------------|---------------
944 * DATA_OUT3 | DATA
945 *
946 * @param AESx AES instance
947 * @retval Output Data[31:0]
948 */
949 __STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
950 {
951 return (READ_REG(AESx->DATA_OUT3));
952 }
953
954 /**
955 * @brief Set AES key[255:224].
956 *
957 * Register|BitsName
958 * ---------------|---------------
959 * KEY0 | KEY
960 *
961 * @param AESx AES instance
962 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
963 * @retval None
964 */
965 __STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
966 {
967 WRITE_REG(AESx->KEY0, key);
968 }
969
970 /**
971 * @brief Set AES key[223:192].
972 *
973 * Register|BitsName
974 * ---------------|---------------
975 * KEY1 | KEY
976 *
977 * @param AESx AES instance
978 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
979 * @retval None
980 */
981 __STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
982 {
983 WRITE_REG(AESx->KEY1, key);
984 }
985
986 /**
987 * @brief Set AES key[191:160].
988 *
989 * Register|BitsName
990 * ---------------|---------------
991 * KEY2 | KEY
992 *
993 * @param AESx AES instance
994 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
995 * @retval None
996 */
997 __STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
998 {
999 WRITE_REG(AESx->KEY2, key);
1000 }
1001
1002 /**
1003 * @brief Set AES key[159:128].
1004 *
1005 * Register|BitsName
1006 * ---------------|---------------
1007 * KEY3 | KEY
1008 *
1009 * @param AESx AES instance
1010 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1011 * @retval None
1012 */
1013 __STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
1014 {
1015 WRITE_REG(AESx->KEY3, key);
1016 }
1017
1018 /**
1019 * @brief Set AES key[127:96].
1020 *
1021 * Register|BitsName
1022 * ---------------|---------------
1023 * KEY4 | KEY
1024 *
1025 * @param AESx AES instance
1026 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1027 * @retval None
1028 */
1029 __STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
1030 {
1031 WRITE_REG(AESx->KEY4, key);
1032 }
1033
1034 /**
1035 * @brief Set AES key[95:64].
1036 *
1037 * Register|BitsName
1038 * ---------------|---------------
1039 * KEY5 | KEY
1040 *
1041 * @param AESx AES instance
1042 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1043 * @retval None
1044 */
1045 __STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
1046 {
1047 WRITE_REG(AESx->KEY5, key);
1048 }
1049
1050 /**
1051 * @brief Set AES key[63:32].
1052 *
1053 * Register|BitsName
1054 * ---------------|---------------
1055 * KEY6 | KEY
1056 *
1057 * @param AESx AES instance
1058 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1059 * @retval None
1060 */
1061 __STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
1062 {
1063 WRITE_REG(AESx->KEY6, key);
1064 }
1065
1066 /**
1067 * @brief Set AES key[31:0].
1068 *
1069 * Register|BitsName
1070 * ---------------|---------------
1071 * KEY7 | KEY
1072 *
1073 * @param AESx AES instance
1074 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1075 * @retval None
1076 */
1077 __STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
1078 {
1079 WRITE_REG(AESx->KEY7, key);
1080 }
1081
1082 /**
1083 * @brief Set AES input seed.
1084 *
1085 * Register|BitsName
1086 * ---------------|---------------
1087 * INIT_SSI | SEED_IN
1088 *
1089 * @param AESx AES instance
1090 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1091 * @retval None
1092 */
1093 __STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
1094 {
1095 WRITE_REG(AESx->INIT_SSI, seed);
1096 }
1097
1098 /**
1099 * @brief Get AES input seed.
1100 *
1101 * Register|BitsName
1102 * ---------------|---------------
1103 * INIT_SSI | SEED_IN
1104 *
1105 * @param AESx AES instance
1106 * @retval Returned value is the input seed.
1107 */
1108 __STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
1109 {
1110 return (READ_REG(AESx->INIT_SSI));
1111 }
1112
1113 /**
1114 * @brief Set AES output seed.
1115 *
1116 * Register|BitsName
1117 * ---------------|---------------
1118 * INIT_SSO | SEED_OUT
1119 *
1120 * @param AESx AES instance
1121 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1122 * @retval None
1123 */
1124 __STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
1125 {
1126 WRITE_REG(AESx->INIT_SSO, seed);
1127 }
1128
1129 /**
1130 * @brief Get AES output seed.
1131 *
1132 * Register|BitsName
1133 * ---------------|---------------
1134 * INIT_SSO | SEED_OUT
1135 *
1136 * @param AESx AES instance
1137 * @retval Returned value is the output seed.
1138 */
1139 __STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
1140 {
1141 return (READ_REG(AESx->INIT_SSO));
1142 }
1143
1144 /**
1145 * @brief Set sbox input data's mask.
1146 *
1147 * Register|BitsName
1148 * ---------------|---------------
1149 * MASK_SSI | SEED_IMASK
1150 *
1151 * @param AESx AES instance
1152 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1153 * @retval None
1154 */
1155 __STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
1156 {
1157 WRITE_REG(AESx->MASK_SSI, mask);
1158 }
1159
1160 /**
1161 * @brief Get sbox input data's mask.
1162 *
1163 * Register|BitsName
1164 * ---------------|---------------
1165 * MASK_SSI | SEED_IMASK
1166 *
1167 * @param AESx AES instance
1168 * @retval Returned value is the input data's mask.
1169 */
1170 __STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
1171 {
1172 return (READ_REG(AESx->MASK_SSI));
1173 }
1174
1175 /**
1176 * @brief Set sbox output data's mask.
1177 *
1178 * Register|BitsName
1179 * ---------------|---------------
1180 * MASK_SSO | SEED_OSBOX
1181 *
1182 * @param AESx AES instance
1183 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1184 * @retval None
1185 */
1186 __STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
1187 {
1188 WRITE_REG(AESx->MASK_SSO, mask);
1189 }
1190
1191 /**
1192 * @brief Get sbox output data's mask.
1193 *
1194 * Register|BitsName
1195 * ---------------|---------------
1196 * MASK_SSO | SEED_OSBOX
1197 *
1198 * @param AESx AES instance
1199 * @retval Returned value is the output data's mask.
1200 */
1201 __STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
1202 {
1203 return (READ_REG(AESx->MASK_SSO));
1204 }
1205
1206 /**
1207 * @brief Set AES initialization vector[127:96].
1208 *
1209 * Register|BitsName
1210 * ---------------|---------------
1211 * INIT_V0 | VECTOR_INIT
1212 *
1213 * @param AESx AES instance
1214 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1215 * @retval None
1216 */
1217 __STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
1218 {
1219 WRITE_REG(AESx->INIT_V0, vector);
1220 }
1221
1222 /**
1223 * @brief Set AES initialization vector[95:64].
1224 *
1225 * Register|BitsName
1226 * ---------------|---------------
1227 * INIT_V1 | VECTOR_INIT
1228 *
1229 * @param AESx AES instance
1230 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1231 * @retval None
1232 */
1233 __STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
1234 {
1235 WRITE_REG(AESx->INIT_V1, vector);
1236 }
1237
1238 /**
1239 * @brief Set AES initialization vector[63:32].
1240 *
1241 * Register|BitsName
1242 * ---------------|---------------
1243 * INIT_V2 | VECTOR_INIT
1244 *
1245 * @param AESx AES instance
1246 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1247 * @retval None
1248 */
1249 __STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
1250 {
1251 WRITE_REG(AESx->INIT_V2, vector);
1252 }
1253
1254 /**
1255 * @brief Set AES initialization vector[31:0].
1256 *
1257 * Register|BitsName
1258 * ---------------|---------------
1259 * INIT_V3 | VECTOR_INIT
1260 *
1261 * @param AESx AES instance
1262 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1263 * @retval None
1264 */
1265 __STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
1266 {
1267 WRITE_REG(AESx->INIT_V3, vector);
1268 }
1269
1270 /**
1271 * @brief Set AES input data[127:96].
1272 *
1273 * Register|BitsName
1274 * ---------------|---------------
1275 * DATA_IN0 | DATA_IN
1276 *
1277 * @param AESx AES instance
1278 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1279 * @retval None
1280 */
1281 __STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
1282 {
1283 WRITE_REG(AESx->DATA_IN0, data);
1284 }
1285
1286 /**
1287 * @brief Set AES input data[95:64].
1288 *
1289 * Register|BitsName
1290 * ---------------|---------------
1291 * DATA_IN1 | DATA_IN
1292 *
1293 * @param AESx AES instance
1294 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1295 * @retval None
1296 */
1297 __STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
1298 {
1299 WRITE_REG(AESx->DATA_IN1, data);
1300 }
1301
1302 /**
1303 * @brief Set AES input data[63:32].
1304 *
1305 * Register|BitsName
1306 * ---------------|---------------
1307 * DATA_IN2 | DATA_IN
1308 *
1309 * @param AESx AES instance
1310 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1311 * @retval None
1312 */
1313 __STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
1314 {
1315 WRITE_REG(AESx->DATA_IN2, data);
1316 }
1317
1318 /**
1319 * @brief Set AES input data[31:0].
1320 *
1321 * Register|BitsName
1322 * ---------------|---------------
1323 * DATA_IN3 | DATA_IN
1324 *
1325 * @param AESx AES instance
1326 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1327 * @retval None
1328 */
1329 __STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
1330 {
1331 WRITE_REG(AESx->DATA_IN3, data);
1332 }
1333
1334 /**
1335 * @brief Set AES fetch key port mask.
1336 *
1337 * Register|BitsName
1338 * ---------------|---------------
1339 * KEYPORT_MASK | KPORT_MASK
1340 *
1341 * @param AESx AES instance
1342 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1343 * @retval None
1344 */
1345 __STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
1346 {
1347 WRITE_REG(AESx->KEYPORT_MASK, mask);
1348 }
1349
1350 /** @} */
1351
1352 /** @defgroup AES_LL_EF_Init Initialization and de-initialization functions
1353 * @{
1354 */
1355
1356 /**
1357 * @brief De-initialize AES registers (Registers restored to their default values).
1358 * @param AESx AES Instance
1359 * @retval An error_status_t enumeration value:
1360 * - SUCCESS: AES registers are de-initialized
1361 * - ERROR: AES registers are not de-initialized
1362 */
1363 error_status_t ll_aes_deinit(aes_regs_t *AESx);
1364
1365 /**
1366 * @brief Initialize AES registers according to the specified
1367 * parameters in p_aes_init.
1368 * @param AESx AES Instance
1369 * @param p_aes_init Pointer to a ll_aes_init_t structure that contains the configuration
1370 * information for the specified AES peripheral.
1371 * @retval An error_status_t enumeration value:
1372 * - SUCCESS: AES registers are initialized according to p_aes_init content
1373 * - ERROR: Problem occurred during AES Registers initialization
1374 */
1375 error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init);
1376
1377 /**
1378 * @brief Set each field of a @ref ll_aes_init_t type structure to default value.
1379 * @param p_aes_init Pointer to a @ref ll_aes_init_t structure
1380 * whose fields will be set to default values.
1381 * @retval None
1382 */
1383 void ll_aes_struct_init(ll_aes_init_t *p_aes_init);
1384
1385 /** @} */
1386
1387 /** @} */
1388
1389 #endif /* AES */
1390
1391 #ifdef __cplusplus
1392 }
1393 #endif
1394
1395 #endif /* __GR55XX_LL_AES_H__ */
1396
1397 /** @} */
1398
1399 /** @} */
1400
1401 /** @} */
ll_aes_enable_read_key
__STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
Enable fetch key through AHB/key port.
Definition: gr55xx_ll_aes.h:330
ll_aes_enable_encryption
__STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
Enable AES encryption mode.
Definition: gr55xx_ll_aes.h:427
ll_aes_disable_encryption
__STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
Disable AES encryption mode.
Definition: gr55xx_ll_aes.h:442
ll_aes_set_vector_127_96
__STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[127:96].
Definition: gr55xx_ll_aes.h:1217
_ll_aes_init::p_key
uint32_t * p_key
Encryption/Decryption Key.
Definition: gr55xx_ll_aes.h:80
ll_aes_disable_start
__STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
Disable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:255
ll_aes_get_data_63_32
__STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
Get AES output data[63:32].
Definition: gr55xx_ll_aes.h:934
ll_aes_get_data_127_96
__STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
Get AES output data[127:96].
Definition: gr55xx_ll_aes.h:904
ll_aes_set_key_type
__STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
Set ways to obtain AES key.
Definition: gr55xx_ll_aes.h:586
ll_aes_disable
__STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
Disable AES.
Definition: gr55xx_ll_aes.h:210
ll_aes_set_data_63_32
__STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
Set AES input data[63:32].
Definition: gr55xx_ll_aes.h:1313
ll_aes_set_key_95_64
__STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
Set AES key[95:64].
Definition: gr55xx_ll_aes.h:1045
ll_aes_init_t
struct _ll_aes_init ll_aes_init_t
LL AES Init Structure definition.
ll_aes_get_data_95_64
__STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
Get AES output data[95:64].
Definition: gr55xx_ll_aes.h:919
ll_aes_get_dma_write_address
__STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
Get AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:852
ll_aes_is_action_flag_dma_error
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
Indicate whether the DMA transfer error flag is set.
Definition: gr55xx_ll_aes.h:706
ll_aes_set_operation_mode
__STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
Set AES operation mode.
Definition: gr55xx_ll_aes.h:550
ll_aes_set_key_31_0
__STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
Set AES key[31:0].
Definition: gr55xx_ll_aes.h:1077
ll_aes_is_enabled_it_done
__STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt is enabled.
Definition: gr55xx_ll_aes.h:655
ll_aes_set_vector_63_32
__STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[63:32].
Definition: gr55xx_ll_aes.h:1249
ll_aes_set_vector_31_0
__STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[31:0].
Definition: gr55xx_ll_aes.h:1265
ll_aes_is_action_flag_ready
__STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
Indicate whether the ready flag is set.
Definition: gr55xx_ll_aes.h:676
ll_aes_is_enabled_full_mask
__STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
Indicate whether the AES full mask is enabled.
Definition: gr55xx_ll_aes.h:412
ll_aes_set_seed_in
__STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
Set AES input seed.
Definition: gr55xx_ll_aes.h:1093
ll_aes_enable_full_mask
__STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
Enable AES full mask.
Definition: gr55xx_ll_aes.h:382
ll_aes_deinit
error_status_t ll_aes_deinit(aes_regs_t *AESx)
De-initialize AES registers (Registers restored to their default values).
_ll_aes_init
LL AES Init Structure definition.
Definition: gr55xx_ll_aes.h:76
ll_aes_disable_dma_start
__STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
Disable AES DMA mode.
Definition: gr55xx_ll_aes.h:300
ll_aes_is_enabled_little_endian
__STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
Indicate whether the AES is in little endian.
Definition: gr55xx_ll_aes.h:532
ll_aes_enable_start
__STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
Enable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:240
_ll_aes_init::p_init_vector
uint32_t * p_init_vector
Initialization Vector used for CBC modes.
Definition: gr55xx_ll_aes.h:82
ll_aes_set_key_191_160
__STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
Set AES key[191:160].
Definition: gr55xx_ll_aes.h:997
ll_aes_set_dma_write_address
__STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
Set AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:837
ll_aes_get_key_size
__STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
Get AES key size.
Definition: gr55xx_ll_aes.h:367
ll_aes_get_seed_Imask
__STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
Get sbox input data's mask.
Definition: gr55xx_ll_aes.h:1170
ll_aes_init
error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init)
Initialize AES registers according to the specified parameters in p_aes_init.
ll_aes_is_action_flag_dma_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
Indicate whether the DMA transfer done flag is set.
Definition: gr55xx_ll_aes.h:691
ll_aes_set_first_block
__STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
Definition: gr55xx_ll_aes.h:487
ll_aes_get_key_type
__STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
Get ways to obtain AES key.
Definition: gr55xx_ll_aes.h:604
ll_aes_set_data_95_64
__STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
Set AES input data[95:64].
Definition: gr55xx_ll_aes.h:1297
ll_aes_is_action_flag_it_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt flag is set.
Definition: gr55xx_ll_aes.h:736
ll_aes_set_data_127_96
__STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
Set AES input data[127:96].
Definition: gr55xx_ll_aes.h:1281
ll_aes_set_key_63_32
__STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
Set AES key[63:32].
Definition: gr55xx_ll_aes.h:1061
ll_aes_set_key_address
__STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
Set AES key address in memory.
Definition: gr55xx_ll_aes.h:874
ll_aes_disable_little_endian
__STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
Disable AES in little endian.
Definition: gr55xx_ll_aes.h:517
ll_aes_is_enabled_encryption
__STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
Indicate whether the AES encryption mode is enabled.
Definition: gr55xx_ll_aes.h:457
ll_aes_set_vector_95_64
__STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[95:64].
Definition: gr55xx_ll_aes.h:1233
ll_aes_set_key_159_128
__STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
Set AES key[159:128].
Definition: gr55xx_ll_aes.h:1013
ll_aes_get_dma_read_address
__STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
Get AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:820
ll_aes_is_action_flag_key_valid
__STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
Indicate whether the key valid flag is set.
Definition: gr55xx_ll_aes.h:721
ll_aes_get_seed_out
__STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
Get AES output seed.
Definition: gr55xx_ll_aes.h:1139
ll_aes_get_seed_Osbox
__STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
Get sbox output data's mask.
Definition: gr55xx_ll_aes.h:1201
ll_aes_struct_init
void ll_aes_struct_init(ll_aes_init_t *p_aes_init)
Set each field of a ll_aes_init_t type structure to default value.
ll_aes_disable_it_done
__STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
Disable AES the done interrupt.
Definition: gr55xx_ll_aes.h:640
ll_aes_enable_little_endian
__STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
Enable AES in little endian.
Definition: gr55xx_ll_aes.h:502
ll_aes_set_dma_read_address
__STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
Set AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:805
ll_aes_enable_it_done
__STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
Enable AES the done interrupt.
Definition: gr55xx_ll_aes.h:625
ll_aes_set_seed_out
__STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
Set AES output seed.
Definition: gr55xx_ll_aes.h:1124
_ll_aes_init::key_size
uint32_t key_size
128, 192 or 256-bit key length.
Definition: gr55xx_ll_aes.h:77
ll_aes_set_data_31_0
__STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
Set AES input data[31:0].
Definition: gr55xx_ll_aes.h:1329
ll_aes_get_operation_mode
__STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
Get AES operation mode.
Definition: gr55xx_ll_aes.h:567
ll_aes_get_key_address
__STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
Get AES key address in memory.
Definition: gr55xx_ll_aes.h:889
ll_aes_set_seed_Imask
__STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
Set sbox input data's mask.
Definition: gr55xx_ll_aes.h:1155
ll_aes_get_data_31_0
__STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
Get AES output data[31:0].
Definition: gr55xx_ll_aes.h:949
ll_aes_disable_full_mask
__STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
Disable AES full mask.
Definition: gr55xx_ll_aes.h:397
ll_aes_set_key_255_224
__STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
Set AES key[255:224].
Definition: gr55xx_ll_aes.h:965
ll_aes_is_enabled_dma_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
Indicate whether the AES DMA mode is enabled.
Definition: gr55xx_ll_aes.h:315
ll_aes_set_dma_transfer_block
__STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
Set AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:773
ll_aes_set_key_port_mask
__STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
Set AES fetch key port mask.
Definition: gr55xx_ll_aes.h:1345
ll_aes_get_seed_in
__STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
Get AES input seed.
Definition: gr55xx_ll_aes.h:1108
ll_aes_clear_flag_it_done
__STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
Clear the done interrupt flag.
Definition: gr55xx_ll_aes.h:751
ll_aes_enable_dma_start
__STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
Enable AES DMA mode.
Definition: gr55xx_ll_aes.h:285
ll_aes_set_seed_Osbox
__STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
Set sbox output data's mask.
Definition: gr55xx_ll_aes.h:1186
ll_aes_enable
__STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
Enable AES.
Definition: gr55xx_ll_aes.h:195
ll_aes_set_key_127_96
__STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
Set AES key[127:96].
Definition: gr55xx_ll_aes.h:1029
ll_aes_set_load_seed
__STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
Set AES to load seed for LFSR.
Definition: gr55xx_ll_aes.h:472
ll_aes_is_enabled_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
Indicate whether the AES start in MCU mode is enabled.
Definition: gr55xx_ll_aes.h:270
ll_aes_is_enabled
__STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
Indicate whether the AES is enabled.
Definition: gr55xx_ll_aes.h:225
ll_aes_set_key_223_192
__STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
Set AES key[223:192].
Definition: gr55xx_ll_aes.h:981
ll_aes_set_key_size
__STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
Set AES key size.
Definition: gr55xx_ll_aes.h:349
_ll_aes_init::p_seed
uint32_t * p_seed
Random seeds.
Definition: gr55xx_ll_aes.h:84
ll_aes_get_dma_transfer_block
__STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
Get AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:788