gr55xx_ll_aon_pmu.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_pmu.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PMU LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PMU AON_PMU
47 * @brief PMU LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_PMU_H_
53 #define __GR55XX_LL_PMU_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61
62 /** @defgroup LL_PMU_DRIVER_FUNCTIONS Functions
63 * @{
64 */
65 /**
66 * @brief Enable the RTC
67 *
68 * Register|BitsName
69 * --------|--------
70 * RF_REG_0 | RTC_EN
71 *
72 * @retval None
73 *
74 */
75 __STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
76 {
77 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
78 }
79 /**
80 * @brief Enable the RTC
81 *
82 * Register|BitsName
83 * --------|--------
84 * RF_REG_0 | RTC_EN
85 * | CGM_MODE
86 *
87 * @retval None
88 *
89 */
90 __STATIC_INLINE void ll_aon_pmu_enable_rtc_cgm(void)
91 {
92 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
93 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN_BGM);
94 }
95
96 /**
97 * @brief Disable the RTC
98 *
99 * Register|BitsName
100 * --------|--------
101 * RF_REG_0 | RTC_EN
102 *
103 */
104 __STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
105 {
106 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
107 }
108
109 /**
110 * @brief Set RTC GM
111 *
112 * Register|BitsName
113 * --------|--------
114 * RF_REG_0 | EN
115 *
116 * @param value: The rtc gm value.
117 *
118 */
119 __STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
120 {
121 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_GM, (value << AON_PMU_RF_REG_0_RTC_GM_Pos));
122 }
123
124 /**
125 * @brief Set lv,default is set to 1.8V,LSB = 8.5mv
126 *
127 * Register|BitsName
128 * --------|--------
129 * RF_REG_0 | EN
130 *
131 * @param value: The io ldo vout value.
132 *
133 */
134 __STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
135 {
136 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1, (value << AON_PMU_RF_REG_0_IO_LDO_REG1_Pos));
137 }
138
139 /**
140 * @brief Set retention level
141 *
142 * Register|BitsName
143 * --------|--------
144 * RF_REG_0 | ctrl_ret
145 *
146 * @param value: The retention level value.
147 *
148 */
149 __STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
150 {
151 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET, (value << AON_PMU_RF_REG_0_CTRL_RET_Pos));
152 }
153
154 /**
155 * @brief Get retention level
156 *
157 * Register|BitsName
158 * --------|--------
159 * RF_REG_0 | ctrl_ret
160 *
161 * @retval The current retention level.
162 *
163 */
164 __STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
165 {
166 return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET) >> AON_PMU_RF_REG_0_CTRL_RET_Pos);
167 }
168
169 /**
170 * @brief Set dcdc the ton value
171 *
172 * Register|BitsName
173 * --------|--------
174 * RF_REG_1 | TON
175 *
176 * @param value: The dcdc ton value.
177 *
178 */
179 __STATIC_INLINE void ll_aon_pmu_set_dcdc_ton(uint32_t value)
180 {
181 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_TON, (value << AON_PMU_RF_REG_1_TON_Pos));
182 }
183
184 /**
185 * @brief Get dcdc the ton value
186 *
187 * Register|BitsName
188 * --------|--------
189 * RF_REG_1 | TON
190 *
191 * @retval The dcdc ton value.
192 *
193 */
194 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_ton(void)
195 {
196 return (READ_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_TON) >> AON_PMU_RF_REG_1_TON_Pos);
197 }
198
199 /**
200 * @brief Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
201 *
202 * Register|BitsName
203 * --------|--------
204 * RF_REG_4 | AON_PMU_RF_REG_4_DCDC_VREF
205 *
206 * @param value: the dcdc vreg value.
207 *
208 */
209 __STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
210 {
211 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DCDC_VREF, (value << AON_PMU_RF_REG_4_DCDC_VREF_Pos));
212 }
213
214 /**
215 * @brief Get dcdc vreg
216 *
217 * Register|BitsName
218 * --------|--------
219 * RF_REG_4 | AON_PMU_RF_REG_4_DCDC_VREF
220 *
221 * @retval The dcdc vreg value.
222 *
223 */
224 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
225 {
226 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DCDC_VREF) >> AON_PMU_RF_REG_4_DCDC_VREF_Pos);
227 }
228
229 /**
230 * @brief Set dcdc reg_sel_aon_pmu_dcore_vref, default from AON.
231 *
232 * Register|BitsName
233 * --------|--------
234 * PMU_DCORE_VREF | REG_SEL_AON_PMU_DCORE_VREF
235 *
236 * @param sel: the dcore vref source control.
237 *
238 */
239 __STATIC_INLINE void ll_aon_pmu_set_dcore_sel(uint8_t sel)
240 {
241 MODIFY_REG(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_SEL, (sel << AON_PMU_DCORE_VREF_REG_SEL_Pos));
242 }
243
244
245 /**
246 * @brief Enable the io ldo bypass
247 *
248 * Register|BitsName
249 * --------|--------
250 * RF_REG_3 | BYPASS_EN
251 *
252 */
253 __STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
254 {
255 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_IO_LDO_BYPASS);
256 }
257
258 /**
259 * @brief Disable the io ldo bypass
260 *
261 * Register|BitsName
262 * --------|--------
263 * RF_REG_3 | BYPASS_EN
264 *
265 */
266 __STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
267 {
268 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_IO_LDO_BYPASS);
269 }
270
271
272 /**
273 * @brief Enable the dig ldo bleed
274 *
275 * Register|BitsName
276 * --------|--------
277 * RF_REG_4 | EN
278 *
279 */
280 __STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
281 {
282 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
283 }
284
285 /**
286 * @brief Disable the dig ldo bleed
287 *
288 * Register|BitsName
289 * --------|--------
290 * RF_REG_4 | EN
291 *
292 */
293 __STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
294 {
295 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
296 }
297
298 /**
299 * @brief Set dig ldo out
300 *
301 * Register|BitsName
302 * --------|--------
303 * PMU_DCORE_VREF | DIG_LDO_OUT
304 *
305 * @param value: The dig ldo out value.
306 *
307 */
308 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
309 {
310 MODIFY_REG(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_DIG_OUT, (value << AON_PMU_DCORE_VREF_REG_DIG_OUT_Pos));
311 }
312
313 /**
314 * @brief Get dig ldo out value
315 *
316 * Register|BitsName
317 * --------|--------
318 * PMU_DCORE_VREF | DIG_LDO_OUT
319 *
320 *
321 */
322 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
323 {
324 return (READ_BITS(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_DIG_OUT) >> AON_PMU_DCORE_VREF_REG_DIG_OUT_Pos);
325 }
326
327 /**
328 * @brief Enable the dig ldo bypass
329 *
330 * Register|BitsName
331 * --------|--------
332 * RF_REG_4 | BYPASS_EN
333 *
334 */
335 __STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
336 {
337 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
338 }
339
340 /**
341 * @brief Disable the dig ldo bypass
342 *
343 * Register|BitsName
344 * --------|--------
345 * RF_REG_4 | BYPASS_EN
346 *
347 */
348 __STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
349 {
350 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
351 }
352
353 /**
354 * @brief Set the dig ldo bypass
355 *
356 * Register|BitsName
357 * --------|--------
358 * RF_REG_4 | BYPASS_EN
359 *
360 */
361 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
362 {
363 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN, (enable << AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos));
364 }
365
366 /**
367 * @brief Get the dig ldo bypass
368 *
369 * Register|BitsName
370 * --------|--------
371 * RF_REG_4 | BYPASS_EN
372 *
373 * @retval The dig ldo bypass enable value.
374 *
375 */
376 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
377 {
378 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN) >> AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos);
379 }
380
381 /**
382 * @brief Set clk period
383 *
384 * Register|BitsName
385 * --------|--------
386 * RF_REG_4 | CLK_PERIOD
387 *
388 * @param value: The clock period value.
389 * @retval None
390 *
391 */
392 __STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
393 {
394 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CLK_PERIOD, (value << AON_PMU_RF_REG_4_CLK_PERIOD_Pos));
395 }
396
397 /**
398 * @brief Get clk period
399 *
400 * Register|BitsName
401 * --------|--------
402 * RF_REG_4 | CLK_PERIOD
403 *
404 * @retval The clock period value.
405 *
406 */
407 __STATIC_INLINE uint32_t ll_aon_pmu_get_clk_period(void)
408 {
409 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CLK_PERIOD) >> AON_PMU_RF_REG_4_CLK_PERIOD_Pos);
410 }
411
412 /**
413 * @brief Enables clock injection from XO to ring oscillator.
414 *
415 * Register|BitsName
416 * --------|--------
417 * RF_REG_1 | EN_INJ_ON
418 *
419 * @retval None
420 *
421 */
422 __STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
423 {
424 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_EN_INJ_ON);
425 }
426
427 /**
428 * @brief Disables clock injection from XO to ring oscillator.
429 *
430 * Register|BitsName
431 * --------|--------
432 * RF_REG_1 | EN_INJ_ON
433 *
434 * @retval None
435 *
436 */
437 __STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
438 {
439 CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_EN_INJ_ON);
440 }
441
442 /**
443 * @brief Enable the dcdc ton startup
444 *
445 * Register|BitsName
446 * --------|--------
447 * DCDC_LDO_REG_0 | TON_STARTUP
448 *
449 */
450 __STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
451 {
452 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TON_STARTUP);
453 }
454
455 /**
456 * @brief Enable clock detection override
457 *
458 * Register|BitsName
459 * --------|--------
460 * DCDC_LDO_REG_0 | CLK_DET_OVR
461 *
462 * @retval None
463 *
464 */
465 __STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr(void)
466 {
467 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR);
468 }
469
470 /**
471 * @brief Disable clock detection override
472 *
473 * Register|BitsName
474 * --------|--------
475 * DCDC_LDO_REG_0 | CLK_DET_OVR
476 *
477 * @retval None
478 *
479 */
480 __STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr(void)
481 {
482 CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR);
483 }
484
485
486 /**
487 * @brief Enable clock detection override source as XO
488 *
489 * Register|BitsName
490 * --------|--------
491 * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
492 *
493 * @retval None
494 *
495 */
496 __STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr_src_xo(void)
497 {
498 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC);
499 }
500
501 /**
502 * @brief Disable clock detection override source XO ---- means set as RING
503 *
504 * Register|BitsName
505 * --------|--------
506 * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
507 *
508 * @retval None
509 *
510 */
511 __STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr_src_xo(void)
512 {
513 CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC);
514 }
515
516 /**
517 * @brief Set clock detection override source
518 *
519 * Register|BitsName
520 * --------|--------
521 * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
522 *
523 * @param value: the clock detection override source value.
524 * @retval None
525 *
526 */
527 __STATIC_INLINE void ll_aon_pmu_set_clk_det_ovr_src(uint32_t value)
528 {
529 MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC, (value << AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC_Pos));
530 }
531
532
533 /**
534 * @brief Enable use_xo
535 *
536 * Register|BitsName
537 * --------|--------
538 * DCDC_LDO_REG_0 | USE_XO
539 *
540 * @retval None
541 *
542 */
543 __STATIC_INLINE void ll_aon_pmu_enable_use_xo(void)
544 {
545 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_USE_XO);
546 }
547
548 /**
549 * @brief Disable use_xo
550 *
551 * Register|BitsName
552 * --------|--------
553 * DCDC_LDO_REG_0 | USE_XO
554 *
555 * @retval None
556 *
557 */
558 __STATIC_INLINE void ll_aon_pmu_disable_use_xo(void)
559 {
560 CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_USE_XO);
561 }
562
563
564 /**
565 * @brief Enable the digital io ldo.
566 *
567 * Register|BitsName
568 * --------|--------
569 * DCDC_LDO_REG_0 | EN_DIG_IO_LDO
570 *
571 * @retval None
572 *
573 */
574 __STATIC_INLINE void ll_aon_pmu_enable_dig_io_ldo(void)
575 {
576 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_EN_DIG_IO_LDO);
577 }
578
579 /**
580 * @brief Disable the tristate ldo.
581 *
582 * Register|BitsName
583 * --------|--------
584 * DCDC_LDO_REG_0 | TRISTATE_LD
585 *
586 * @retval None
587 *
588 */
589 __STATIC_INLINE void ll_aon_pmu_disable_tristate_ldo(void)
590 {
591 CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TRISTATE_LDO);
592 }
593
594 /**
595 * @brief Disable the tristate analog ldo.
596 *
597 * Register|BitsName
598 * --------|--------
599 * DCDC_LDO_REG_0 | TRISTATE_ANA_IO_LDO
600 *
601 * @retval None
602 *
603 */
604 __STATIC_INLINE void ll_aon_pmu_enable_tristate_ana_io_ldo(void)
605 {
606 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TRISTATE_ANA_IO_LDO);
607 }
608
609 /**
610 * @brief Set ldo control_override.
611 *
612 * Register|BitsName
613 * --------|--------
614 * DCDC_LDO_REG_0 | REG0_LDO_CTRL_OV
615 *
616 * @retval None
617 *
618 */
619 __STATIC_INLINE void ll_aon_pmu_set_ldo_control_override(void)
620 {
621 SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_LDO_CTRL_OV);
622 }
623
624 /**
625 * @brief Set boost step.
626 *
627 * Register|BitsName
628 * --------|--------
629 * DCDC_LDO_REG_0 | BOOST_STEP
630 *
631 * @param value: The boost step value.
632 * @retval None
633 *
634 */
635 __STATIC_INLINE void ll_aon_pmu_set_boost_step(uint32_t value)
636 {
637 MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_BOOST_STEP, (value << AON_PMU_DCDC_LDO_REG0_BOOST_STEP_Pos));
638 }
639
640 /**
641 * @brief Set digital io ldo divider.
642 *
643 * Register|BitsName
644 * --------|--------
645 * DCDC_LDO_REG_0 | CLK_DIV_SEL
646 *
647 * @param value: The dig ldo div value.
648 * @retval None
649 *
650 */
651 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_div(uint32_t value)
652 {
653 MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DIV_SEL, (value << AON_PMU_DCDC_LDO_REG0_CLK_DIV_SEL_Pos));
654 }
655
656 /**
657 * @brief Set the rtc cur cap
658 *
659 * Register|BitsName
660 * --------|--------
661 * RC_RTC_REG_0 | RTC_CAP
662 *
663 * @param value: The rtc current cap value.
664 *
665 */
666 __STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
667 {
668 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CS, (value << AON_PMU_RC_RTC_REG0_RTC_CS_Pos));
669 }
670 /**
671 * @brief Set the rtc on MSIO A6/7 en pad sw
672 *
673 * Register|BitsName
674 * --------|--------
675 * RC_RTC_REG_0 | EN_PAD_SW
676 *
677 *
678 */
679 __STATIC_INLINE void ll_aon_pmu_enable_pad_sw(void)
680 {
681 SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_EN_PAD_SW);
682 }
683
684
685 /**
686 * @brief Set clock detection option
687 *
688 * Register|BitsName
689 * --------|--------
690 * RC_RTC_REG_0 | CLK_DET_OPT
691 *
692 * @param value: clock detection option value, 0: use clk_det, 1: use glitch free MUX.
693 * @retval None
694 *
695 */
696 __STATIC_INLINE void ll_aon_pmu_set_clk_det_opt(uint32_t value)
697 {
698 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_CLK_DET_OPT, (value << AON_PMU_RC_RTC_REG0_CLK_DET_OPT_Pos));
699 }
700
701 /**
702 * @brief Set the rtc cur cap
703 *
704 * Register|BitsName
705 * --------|--------
706 * RC_RTC_REG_0 | RTC_CAP
707 *
708 * @param value: The rtc current cap value.
709 *
710 */
711 __STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
712 {
713 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP, (value << AON_PMU_RC_RTC_REG0_RTC_CAP_Pos));
714 }
715
716 /**
717 * @brief Get the rtc cur cap
718 *
719 * Register|BitsName
720 * --------|--------
721 * RC_RTC_REG_0 | RTC_CAP
722 *
723 * @retval The rtc current cap value.
724 *
725 */
726 __STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
727 {
728 return (READ_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP) >> AON_PMU_RC_RTC_REG0_RTC_CAP_Pos);
729 }
730
731 /**
732 * @brief Enable the RCOSC
733 *
734 * Register|BitsName
735 * --------|--------
736 * RC_RTC_REG_0 | RCOSC
737 *
738 */
739 __STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
740 {
741 SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
742 }
743
744 /**
745 * @brief Disable the RCOSC
746 *
747 * Register|BitsName
748 * --------|--------
749 * RC_RTC_REG_0 | RCOSC
750 *
751 */
752 __STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
753 {
754 CLEAR_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
755 }
756
757 /**
758 * @brief enable the ret ldo
759 *
760 * Register|BitsName
761 * --------|--------
762 * RET_LDO_REG | RET_LDO_EN
763 *
764 */
765 __STATIC_INLINE void ll_aon_pmu_enable_ret_ldo(void)
766 {
767 SET_BITS(AON_PMU->RET_LDO, AON_PMU_RET_LDO_EN);
768 }
769
770 /**
771 * @brief modify ret ldo ctrl level
772 *
773 * Register|BitsName
774 * --------|--------
775 * RET_LDO_REG | RET_LDO_CTRL_5_1
776 *
777 */
778 __STATIC_INLINE void ll_aon_pmu_set_ret_ldo_ctrl_lvl(uint32_t value)
779 {
780 MODIFY_REG(AON_PMU->RET_LDO, AON_PMU_RET_LDO_OUT, (value << AON_PMU_RET_LDO_OUT_Pos));
781 }
782
783 /**
784 * @brief modify lpd active
785 *
786 * Register|BitsName
787 * --------|--------
788 * PMU_LPD_CFG | LPD_VAON_ACTIVE
789 *
790 */
791 __STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
792 {
793 MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_ACTIVE, (value << AON_PMU_LPD_VAON_ACTIVE_Pos));
794 }
795
796 /**
797 * @brief Get lpd active value
798 *
799 * Register|BitsName
800 * --------|--------
801 * PMU_LPD_CFG | LPD_VAON_ACTIVE
802 *
803 * @retval The current lpd active value.
804 *
805 */
806 __STATIC_INLINE uint32_t ll_aon_pmu_get_lpd_active(void)
807 {
808 return (READ_BITS(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_ACTIVE) >> AON_PMU_LPD_VAON_ACTIVE_Pos);
809 }
810
811 /**
812 * @brief modify lpd sleep
813 *
814 * Register|BitsName
815 * --------|--------
816 * PMU_LPD_CFG | LPD_VAON_SLEEP
817 *
818 */
819 __STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
820 {
821 MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_SLEEP, (value << AON_PMU_LPD_VAON_SLEEP_Pos));
822 }
823 /**
824 * @brief modify ton on
825 *
826 * Register|BitsName
827 * --------|--------
828 * PMU_TON_CFG | AON_PMU_TON_CTRL_ON
829 *
830 */
831 __STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
832 {
833 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_ON, (value << AON_PMU_TON_CTRL_ON_Pos));
834 }
835 /**
836 * @brief modify ton off
837 *
838 * Register|BitsName
839 * --------|--------
840 * PMU_TON_CFG | AON_PMU_TON_CTRL_OFF
841 *
842 */
843 __STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
844 {
845 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_OFF, (value << AON_PMU_TON_CTRL_OFF_Pos));
846 }
847 /**
848 * @brief set rng freq
849 *
850 * Register|BitsName
851 * --------|--------
852 * RF_REG0 | AON_PMU_RF_REG_0_RNG_FREQ_CONT
853 *
854 */
855 __STATIC_INLINE void ll_aon_pmu_set_rng_req(uint32_t value)
856 {
857 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_FREQ_CONT, (value << AON_PMU_RF_REG_0_RNG_FREQ_CONT_Pos));
858 }
859 /**
860 * @brief set rng freq
861 *
862 * Register|BitsName
863 * --------|--------
864 * RF_REG0 | AON_PMU_RF_REG_0_RNG_FREQ_CONT
865 *
866 */
867 __STATIC_INLINE void ll_aon_pmu_set_rng_freq_bump_enable(void)
868 {
869 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_FREQ_BUMP);
870 }
871 /**
872 * @brief Enable short aon digcore
873 *
874 * Register|BitsName
875 * --------|--------
876 * RF_REG2 | SHORT_AON_DIGCORE
877 *
878 * @retval None
879 *
880 */
881 __STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
882 {
883 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_SHORT_AON_DIGCORE);
884 }
885
886 /**
887 * @brief Disable short aon digcore
888 *
889 * Register|BitsName
890 * --------|--------
891 * RF_REG2 | SHORT_AON_DIGCORE
892 *
893 * @retval None
894 *
895 */
896 __STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
897 {
898 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_SHORT_AON_DIGCORE);
899 }
900 /** @} */
901
902 #endif
903
904 /** @} */
905
906 /** @} */
907
908 /** @} */
ll_aon_pmu_enable_clk_det_ovr_src_xo
__STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr_src_xo(void)
Enable clock detection override source as XO.
Definition: gr55xx_ll_aon_pmu.h:496
ll_aon_pmu_disable_clk_inject
__STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
Disables clock injection from XO to ring oscillator.
Definition: gr55xx_ll_aon_pmu.h:437
ll_aon_pmu_set_clk_det_ovr_src
__STATIC_INLINE void ll_aon_pmu_set_clk_det_ovr_src(uint32_t value)
Set clock detection override source.
Definition: gr55xx_ll_aon_pmu.h:527
ll_aon_pmu_disable_clk_det_ovr_src_xo
__STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr_src_xo(void)
Disable clock detection override source XO -— means set as RING.
Definition: gr55xx_ll_aon_pmu.h:511
ll_aon_pmu_set_clk_det_opt
__STATIC_INLINE void ll_aon_pmu_set_clk_det_opt(uint32_t value)
Set clock detection option.
Definition: gr55xx_ll_aon_pmu.h:696
ll_aon_pmu_set_dig_ldo_div
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_div(uint32_t value)
Set digital io ldo divider.
Definition: gr55xx_ll_aon_pmu.h:651
ll_aon_pmu_set_clk_period
__STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
Set clk period.
Definition: gr55xx_ll_aon_pmu.h:392
ll_aon_pmu_enable_pad_sw
__STATIC_INLINE void ll_aon_pmu_enable_pad_sw(void)
Set the rtc on MSIO A6/7 en pad sw.
Definition: gr55xx_ll_aon_pmu.h:679
ll_aon_pmu_set_lpd_active
__STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
modify lpd active
Definition: gr55xx_ll_aon_pmu.h:791
ll_aon_pmu_enable_clk_det_ovr
__STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr(void)
Enable clock detection override.
Definition: gr55xx_ll_aon_pmu.h:465
ll_aon_pmu_set_retention_level
__STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
Set retention level.
Definition: gr55xx_ll_aon_pmu.h:149
ll_aon_pmu_get_retention_level
__STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
Get retention level.
Definition: gr55xx_ll_aon_pmu.h:164
ll_aon_pmu_get_lpd_active
__STATIC_INLINE uint32_t ll_aon_pmu_get_lpd_active(void)
Get lpd active value.
Definition: gr55xx_ll_aon_pmu.h:806
ll_aon_pmu_enable_ton_startup_overide
__STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
Enable the dcdc ton startup.
Definition: gr55xx_ll_aon_pmu.h:450
ll_aon_pmu_enable_bleed
__STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
Enable the dig ldo bleed.
Definition: gr55xx_ll_aon_pmu.h:280
ll_aon_pmu_set_dcore_sel
__STATIC_INLINE void ll_aon_pmu_set_dcore_sel(uint8_t sel)
Set dcdc reg_sel_aon_pmu_dcore_vref, default from AON.
Definition: gr55xx_ll_aon_pmu.h:239
ll_aon_pmu_set_ldo_control_override
__STATIC_INLINE void ll_aon_pmu_set_ldo_control_override(void)
Set ldo control_override.
Definition: gr55xx_ll_aon_pmu.h:619
ll_aon_pmu_disable_rcosc
__STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
Disable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:752
ll_aon_pmu_set_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
modify ton on
Definition: gr55xx_ll_aon_pmu.h:831
ll_aon_pmu_disable_clk_det_ovr
__STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr(void)
Disable clock detection override.
Definition: gr55xx_ll_aon_pmu.h:480
ll_aon_pmu_disable_tristate_ldo
__STATIC_INLINE void ll_aon_pmu_disable_tristate_ldo(void)
Disable the tristate ldo.
Definition: gr55xx_ll_aon_pmu.h:589
ll_aon_pmu_set_rtc_cs
__STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:666
ll_aon_pmu_set_lpd_sleep
__STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
modify lpd sleep
Definition: gr55xx_ll_aon_pmu.h:819
ll_aon_pmu_enable_rtc
__STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
Enable the RTC.
Definition: gr55xx_ll_aon_pmu.h:75
ll_aon_pmu_disable_use_xo
__STATIC_INLINE void ll_aon_pmu_disable_use_xo(void)
Disable use_xo.
Definition: gr55xx_ll_aon_pmu.h:558
ll_aon_pmu_disable_bleed
__STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
Disable the dig ldo bleed.
Definition: gr55xx_ll_aon_pmu.h:293
ll_aon_pmu_enable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
Enable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:253
ll_aon_pmu_get_dcdc_ton
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_ton(void)
Get dcdc the ton value.
Definition: gr55xx_ll_aon_pmu.h:194
ll_aon_pmu_enable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
Enable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:335
ll_aon_pmu_set_ret_ldo_ctrl_lvl
__STATIC_INLINE void ll_aon_pmu_set_ret_ldo_ctrl_lvl(uint32_t value)
modify ret ldo ctrl level
Definition: gr55xx_ll_aon_pmu.h:778
ll_aon_pmu_enable_rcosc
__STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
Enable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:739
ll_aon_pmu_set_rng_freq_bump_enable
__STATIC_INLINE void ll_aon_pmu_set_rng_freq_bump_enable(void)
set rng freq
Definition: gr55xx_ll_aon_pmu.h:867
ll_aon_pmu_enable_ret_ldo
__STATIC_INLINE void ll_aon_pmu_enable_ret_ldo(void)
enable the ret ldo
Definition: gr55xx_ll_aon_pmu.h:765
ll_aon_pmu_set_rtc_gm
__STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
Set RTC GM.
Definition: gr55xx_ll_aon_pmu.h:119
ll_aon_pmu_set_dcdc_ton
__STATIC_INLINE void ll_aon_pmu_set_dcdc_ton(uint32_t value)
Set dcdc the ton value.
Definition: gr55xx_ll_aon_pmu.h:179
ll_aon_pmu_disable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
Disable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:896
ll_aon_pmu_set_dig_ldo_out
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
Set dig ldo out.
Definition: gr55xx_ll_aon_pmu.h:308
ll_aon_pmu_get_dig_ldo_out
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
Get dig ldo out value.
Definition: gr55xx_ll_aon_pmu.h:322
ll_aon_pmu_disable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
Disable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:348
ll_aon_pmu_set_rtc_cap
__STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:711
ll_aon_pmu_disable_rtc
__STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
Disable the RTC.
Definition: gr55xx_ll_aon_pmu.h:104
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_aon_pmu_enable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
Enable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:881
ll_aon_pmu_get_rtc_cap
__STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
Get the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:726
ll_aon_pmu_set_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
Set the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:361
ll_aon_pmu_set_non_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
modify ton off
Definition: gr55xx_ll_aon_pmu.h:843
ll_aon_pmu_set_rng_req
__STATIC_INLINE void ll_aon_pmu_set_rng_req(uint32_t value)
set rng freq
Definition: gr55xx_ll_aon_pmu.h:855
ll_aon_pmu_set_boost_step
__STATIC_INLINE void ll_aon_pmu_set_boost_step(uint32_t value)
Set boost step.
Definition: gr55xx_ll_aon_pmu.h:635
ll_aon_pmu_get_clk_period
__STATIC_INLINE uint32_t ll_aon_pmu_get_clk_period(void)
Get clk period.
Definition: gr55xx_ll_aon_pmu.h:407
ll_aon_pmu_enable_dig_io_ldo
__STATIC_INLINE void ll_aon_pmu_enable_dig_io_ldo(void)
Enable the digital io ldo.
Definition: gr55xx_ll_aon_pmu.h:574
ll_aon_pmu_set_io_ldo_vout
__STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
Set lv,default is set to 1.8V,LSB = 8.5mv.
Definition: gr55xx_ll_aon_pmu.h:134
ll_aon_pmu_disable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
Disable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:266
ll_aon_pmu_enable_use_xo
__STATIC_INLINE void ll_aon_pmu_enable_use_xo(void)
Enable use_xo.
Definition: gr55xx_ll_aon_pmu.h:543
ll_aon_pmu_enable_clk_inject
__STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
Enables clock injection from XO to ring oscillator.
Definition: gr55xx_ll_aon_pmu.h:422
ll_aon_pmu_enable_tristate_ana_io_ldo
__STATIC_INLINE void ll_aon_pmu_enable_tristate_ana_io_ldo(void)
Disable the tristate analog ldo.
Definition: gr55xx_ll_aon_pmu.h:604
ll_aon_pmu_get_dig_ldo_bypass
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
Get the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:376
ll_aon_pmu_get_dcdc_vreg
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
Get dcdc vreg.
Definition: gr55xx_ll_aon_pmu.h:224
ll_aon_pmu_set_dcdc_vreg
__STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
Definition: gr55xx_ll_aon_pmu.h:209
ll_aon_pmu_enable_rtc_cgm
__STATIC_INLINE void ll_aon_pmu_enable_rtc_cgm(void)
Enable the RTC.
Definition: gr55xx_ll_aon_pmu.h:90