gr55xx_ll_ospi_x.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_ospi_x.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2021 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_OSPI OSPI
47 * @brief OSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_OSPI_X_H__
53 #define __GR55xx_LL_OSPI_X_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 #include "math.h"
62
63
64 #if defined (OSPI0)
65
66 /** @defgroup LL_OSPI_X_DRIVER_STRUCTURES Structures
67 * @{
68 */
69 /** @brief OSPI init structure. */
70 typedef struct _ll_ospi_x_init_t {
71
72 uint32_t clock_freq; /**< Specifies the Clock Freq for OSPI */
73
74 uint32_t dqs_timeout_ns; /**< DQS timeout in ns */
75
76 uint32_t mem_base_address; /**< memory base address */
77
78 uint32_t mem_top_address; /**< memory top address, max 0x1FFFFFF */
79
80 uint32_t mem_page_size; /**< memory page size */
81
82 uint32_t timing_max_tCEM_us; /**< max tCEM time in us */
83
84 uint32_t timing_min_tRST_us; /**< min tRST time in us */
85
86 uint32_t timing_min_tCPH_ns; /**< min tCPH time in ns */
87
88 uint32_t timing_min_tRC_ns; /**< min tRC time in ns */
89
90 uint32_t timing_min_tXPDPD_ns; /**< min tXPDPD time in ns */
91
92 uint32_t timing_min_tXDPD_us; /**< min tXDPD time in us */
93
94 uint32_t timing_min_tXPHS_ns; /**< min tXPHS time in ns */
95
96 uint32_t timing_min_tXHS_us; /**< min tXHS time in us */
97
98 uint8_t is_tcem_ignore; /**< let controller ignore the tCEM or not */
99
100 uint8_t is_txdpd_ignore; /**< let controller ignore the txdpd or not */
101
102 uint8_t is_txhs_ignore; /**< let controller ignore the txhs or not */
103
104 uint8_t cmd_linear_burst_rd; /**< Linear Burst Read Command */
105
106 uint8_t cmd_linear_burst_wr; /**< Linear Burst Write Command */
107
108 uint8_t cmd_sync_rd; /**< Sync Read Command */
109
110 uint8_t cmd_sync_wr; /**< Sync Write Command */
111
112 uint8_t cmd_mode_register_rd; /**< Register Mode Read Command */
113
114 uint8_t cmd_mode_register_wr; /**< Register Mode Write Command */
115
116 uint8_t cmd_global_reset; /**< Global Reset Command */
117
118 } ll_ospi_x_init_t;
119 /** @} */
120
121 /** @defgroup LL_OSPI_X_DRIVER_DEFINES Defines
122 * @{
123 */
124 /** @defgroup LL_OSPI_X_TCEM_TIME_IGNORE tCEM time ignore enable
125 * @brief Ignore the tCEM or not
126 * @{
127 */
128 #define LL_OSPI_X_TCEM_TIME_IGNORE_DISABLE 0x00
129 #define LL_OSPI_X_TCEM_TIME_IGNORE_ENABLE 0x01
130 /** @} */
131
132 /** @defgroup LL_OSPI_X_TXHS_TIME_IGNORE tXHS time ognore enable
133 * @brief Ignore the tXHS or not
134 * @{
135 */
136 #define LL_OSPI_X_TXHS_TIME_IGNORE_DISABLE 0x00
137 #define LL_OSPI_X_TXHS_TIME_IGNORE_ENABLE 0x01
138 /** @} */
139
140 /** @defgroup LL_OSPI_X_ACCESS_TYPE PSRAM access type
141 * @brief Access type for PSRAM
142 * @{
143 */
144 #define LL_OSPI_X_ACCESS_TYPE_MEMORY_ARRAY 0x00
145 #define LL_OSPI_X_ACCESS_TYPE_MODE_REGISTER 0x01
146 /** @} */
147
148 /** @defgroup LL_OSPI_X_TXDPD_TIME_IGNORE Ignore the tXDPD enable
149 * @brief Ignore the tXDPD or not
150 * @{
151 */
152 #define LL_OSPI_X_TXDPD_TIME_IGNORE_DISABLE 0x00
153 #define LL_OSPI_X_TXDPD_TIME_IGNORE_ENABLE 0x01
154 /** @} */
155
156 /** @defgroup LL_OSPI_X_READ_PREFETCH Read prefetch enable
157 * @brief Enable the read prefetch or not
158 * @{
159 */
160 #define LL_OSPI_X_READ_PREFETCH_DISABLE 0x00
161 #define LL_OSPI_X_READ_PREFETCH_ENABLE 0x01
162 /** @} */
163
164 /** @defgroup LL_OSPI_X_INTERRUPT OSPI Interrupt enable
165 * @brief Enable/Disable the OSPI Interrupt
166 * @{
167 */
168 #define LL_OSPI_X_INTERRUPT_DISABLE 0x00
169 #define LL_OSPI_X_INTERRUPT_ENABLE 0x01
170 /** @} */
171
172 /** @defgroup LL_OSPI_X_MEM_PAGE_SIZE Page Size for PSRAM
173 * @brief Page Size for PSRAM
174 * @{
175 */
176 #define LL_OSPI_X_MEM_PAGE_SIZE_64Bytes 0x06
177 #define LL_OSPI_X_MEM_PAGE_SIZE_128Bytes 0x07
178 #define LL_OSPI_X_MEM_PAGE_SIZE_256Bytes 0x08
179 #define LL_OSPI_X_MEM_PAGE_SIZE_512Bytes 0x09
180 #define LL_OSPI_X_MEM_PAGE_SIZE_1024Bytes 0x0A
181 #define LL_OSPI_X_MEM_PAGE_SIZE_2048Bytes 0x0B
182 #define LL_OSPI_X_MEM_PAGE_SIZE_4096Bytes 0x0C
183 /** @} */
184 /** @} */
185
186 /** @defgroup LL_OSPI_X_DRIVER_FUNCTIONS Functions
187 * @{
188 */
189 /**
190 * @brief Set memory base address
191 *--------------------------
192 * @param OSPIx OSPI instance
193 * @param base_address - base address
194 * @retval none
195 */
196 __STATIC_INLINE void ll_ospi_x_set_mem_base_address(ospi_x_regs_t * OSPIx, uint32_t base_address)
197 {
198 MODIFY_REG(OSPIx->MEM_BASE_ADDR, OSPI_X_MEM_BASE_ADDR, base_address << OSPI_X_MEM_BASE_ADDR_POS);
199 }
200
201 /**
202 * @brief Get memory base address
203 *--------------------------
204 * @param OSPIx OSPI instance
205 * @retval base address
206 */
207 __STATIC_INLINE uint32_t ll_ospi_x_get_mem_base_address(ospi_x_regs_t * OSPIx)
208 {
209 return (uint32_t)(READ_BITS(OSPIx->MEM_BASE_ADDR, OSPI_X_MEM_BASE_ADDR) >> OSPI_X_MEM_BASE_ADDR_POS);
210 }
211
212 /**
213 * @brief Set memory top address
214 *--------------------------
215 * @param OSPIx OSPI instance
216 * @param top_address - top address
217 * @retval none
218 */
219 __STATIC_INLINE void ll_ospi_x_set_mem_top_address(ospi_x_regs_t * OSPIx, uint32_t top_address)
220 {
221 MODIFY_REG(OSPIx->MEM_TOP_ADDR, OSPI_X_MEM_TOP_ADDR, top_address << OSPI_X_MEM_TOP_ADDR_POS);
222 }
223
224 /**
225 * @brief Get memory top address
226 *--------------------------
227 * @param OSPIx OSPI instance
228 * @retval top address
229 */
230 __STATIC_INLINE uint32_t ll_ospi_x_get_mem_top_address(ospi_x_regs_t * OSPIx)
231 {
232 return (uint32_t)(READ_BITS(OSPIx->MEM_TOP_ADDR, OSPI_X_MEM_TOP_ADDR) >> OSPI_X_MEM_TOP_ADDR_POS);
233 }
234
235 /**
236 * @brief Set clock count for tRST
237 *--------------------------
238 * @param OSPIx OSPI instance
239 * @param trst_cnt - clock count for tRST
240 * @retval none
241 */
242 __STATIC_INLINE void ll_ospi_x_set_trst_count(ospi_x_regs_t * OSPIx, uint32_t trst_cnt)
243 {
244 MODIFY_REG(OSPIx->GLOBAL_RESET, OSPI_X_TRST_CNT, trst_cnt << OSPI_X_TRST_CNT_POS);
245 }
246
247 /**
248 * @brief Get clock count for tRST
249 *--------------------------
250 * @param OSPIx OSPI instance
251 * @retval none
252 */
253 __STATIC_INLINE uint32_t ll_ospi_x_get_trst_count(ospi_x_regs_t * OSPIx)
254 {
255 return (uint32_t)(READ_BITS(OSPIx->GLOBAL_RESET, OSPI_X_TRST_CNT) >> OSPI_X_TRST_CNT_POS);
256 }
257
258 /**
259 * @brief Trigger Global Reset Command
260 *--------------------------
261 * @param OSPIx OSPI instance
262 * @retval none
263 */
264 __STATIC_INLINE void ll_ospi_x_enable_global_reset(ospi_x_regs_t * OSPIx)
265 {
266 MODIFY_REG(OSPIx->GLOBAL_RESET, OSPI_X_GLOBAL_RST_EN, 1 << OSPI_X_GLOBAL_RST_EN_POS);
267 }
268
269 /**
270 * @brief Set access type for PSRAM
271 *--------------------------
272 * @param OSPIx OSPI instance
273 * @param access_type - @ref LL_OSPI_X_ACCESS_TYPE
274 * @retval none
275 */
276 __STATIC_INLINE void ll_ospi_x_set_access_type(ospi_x_regs_t * OSPIx, uint32_t access_type)
277 {
278 MODIFY_REG(OSPIx->ACCESS_TYPE, OSPI_X_ACCESS_TYPE, access_type << OSPI_X_ACCESS_TYPE_POS);
279 }
280
281 /**
282 * @brief Get access type for PSRAM
283 *--------------------------
284 * @param OSPIx OSPI instance
285 * @retval LL_OSPI_X_ACCESS_TYPE
286 */
287 __STATIC_INLINE uint32_t ll_ospi_x_get_access_type(ospi_x_regs_t * OSPIx)
288 {
289 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TYPE, OSPI_X_ACCESS_TYPE) >> OSPI_X_ACCESS_TYPE_POS);
290 }
291
292 /**
293 * @brief Set ignoring the tcem or not
294 *--------------------------
295 * @param OSPIx OSPI instance
296 * @param is_ignore - LL_OSPI_X_TCEM_TIME_IGNORE
297 * @retval none
298 */
299 __STATIC_INLINE void ll_ospi_x_set_tcem_ignore(ospi_x_regs_t * OSPIx, uint32_t is_ignore)
300 {
301 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_IGNORE, is_ignore << OSPI_X_TCEM_IGNORE_POS);
302 }
303
304 /**
305 * @brief Get whether ignoring the tcem or not
306 *--------------------------
307 * @param OSPIx OSPI instance
308 * @retval LL_OSPI_X_TCEM_TIME_IGNORE
309 */
310 __STATIC_INLINE uint32_t ll_ospi_x_get_tcem_ignore(ospi_x_regs_t * OSPIx)
311 {
312 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_IGNORE) >> OSPI_X_TCEM_IGNORE_POS);
313 }
314
315 /**
316 * @brief Set clock count for the tcem
317 *--------------------------
318 * @param OSPIx OSPI instance
319 * @param tcem_cnt - clock count for the tcem
320 * @retval none
321 */
322 __STATIC_INLINE void ll_ospi_x_set_tcem_count(ospi_x_regs_t * OSPIx, uint32_t tcem_cnt)
323 {
324 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_CNT, tcem_cnt << OSPI_X_TCEM_CNT_POS);
325 }
326
327 /**
328 * @brief Get clock count for the tcem
329 *--------------------------
330 * @param OSPIx OSPI instance
331 * @retval clock count for the tcem
332 */
333 __STATIC_INLINE uint32_t ll_ospi_x_get_tcem_count(ospi_x_regs_t * OSPIx)
334 {
335 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_CNT) >> OSPI_X_TCEM_CNT_POS);
336 }
337
338 /**
339 * @brief Set clock count for the tRC
340 *--------------------------
341 * @param OSPIx OSPI instance
342 * @param trc_cnt - clock count for the tRC
343 * @retval none
344 */
345 __STATIC_INLINE void ll_ospi_x_set_trc_count(ospi_x_regs_t * OSPIx, uint32_t trc_cnt)
346 {
347 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TRC_CNT, trc_cnt << OSPI_X_TRC_CNT_POS);
348 }
349
350 /**
351 * @brief Get clock count for the tRC
352 *--------------------------
353 * @param OSPIx OSPI instance
354 * @retval clock count for the tRC
355 */
356 __STATIC_INLINE uint32_t ll_ospi_x_get_trc_count(ospi_x_regs_t * OSPIx)
357 {
358 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TRC_CNT) >> OSPI_X_TRC_CNT_POS);
359 }
360
361 /**
362 * @brief Set clock count for the tCPH
363 *--------------------------
364 * @param OSPIx OSPI instance
365 * @param tcph_cnt - clock count for the tCPH
366 * @retval none
367 */
368 __STATIC_INLINE void ll_ospi_x_set_tcph_count(ospi_x_regs_t * OSPIx, uint32_t tcph_cnt)
369 {
370 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCPH_CNT, tcph_cnt << OSPI_X_TCPH_CNT_POS);
371 }
372
373 /**
374 * @brief Get clock count for the tCPH
375 *--------------------------
376 * @param OSPIx OSPI instance
377 * @retval clock count for the tCPH
378 */
379 __STATIC_INLINE uint32_t ll_ospi_x_get_tcph_count(ospi_x_regs_t * OSPIx)
380 {
381 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCPH_CNT) >> OSPI_X_TCPH_CNT_POS);
382 }
383
384 /**
385 * @brief Set memory page size
386 *--------------------------
387 * @param OSPIx OSPI instance
388 * @param mem_page_size - LL_OSPI_X_MEM_PAGE_SIZE
389 * @retval none
390 */
391 __STATIC_INLINE void ll_ospi_x_set_mem_page_size(ospi_x_regs_t * OSPIx, uint32_t mem_page_size)
392 {
393 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_MEM_PAGE_SIZE, mem_page_size << OSPI_X_MEM_PAGE_SIZE_POS);
394 }
395
396 /**
397 * @brief Get memory page size
398 *--------------------------
399 * @param OSPIx OSPI instance
400 * @retval LL_OSPI_X_MEM_PAGE_SIZE
401 */
402 __STATIC_INLINE uint32_t ll_ospi_x_get_mem_page_size(ospi_x_regs_t * OSPIx)
403 {
404 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_MEM_PAGE_SIZE) >> OSPI_X_MEM_PAGE_SIZE_POS);
405 }
406
407 /**
408 * @brief Trigger the entry deep power down command
409 *--------------------------
410 * @param OSPIx OSPI instance
411 * @retval none
412 */
413 __STATIC_INLINE void ll_ospi_x_entry_dpd(ospi_x_regs_t * OSPIx)
414 {
415 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_DPD_ENTRY, 0x01 << OSPI_X_DPD_ENTRY_POS);
416 }
417
418 /**
419 * @brief Trigger the exit deep power down command
420 *--------------------------
421 * @param OSPIx OSPI instance
422 * @retval none
423 */
424 __STATIC_INLINE void ll_ospi_x_exit_dpd(ospi_x_regs_t * OSPIx)
425 {
426 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_DPD_EXIT, 0x01 << OSPI_X_DPD_EXIT_POS);
427 }
428
429 /**
430 * @brief Set ignoring the txdpd or not
431 *--------------------------
432 * @param OSPIx OSPI instance
433 * @param is_ignore - LL_OSPI_X_TXDPD_TIME_IGNORE
434 * @retval none
435 */
436 __STATIC_INLINE void ll_ospi_x_set_txdpd_ignore(ospi_x_regs_t * OSPIx, uint32_t is_ignore)
437 {
438 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_TIME_IGNORE, is_ignore << OSPI_X_TXDPD_TIME_IGNORE_POS);
439 }
440
441 /**
442 * @brief Get whether ignoring the txdpd or not
443 *--------------------------
444 * @param OSPIx OSPI instance
445 * @retval LL_OSPI_X_TXDPD_TIME_IGNORE
446 */
447 __STATIC_INLINE uint32_t ll_ospi_x_get_txdpd_ignore(ospi_x_regs_t * OSPIx)
448 {
449 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_TIME_IGNORE) >> OSPI_X_TXDPD_TIME_IGNORE_POS);
450 }
451
452 /**
453 * @brief Set clock count for the tXDPD
454 *--------------------------
455 * @param OSPIx OSPI instance
456 * @param txdpd_cnt - clock count for the tXDPD
457 * @retval none
458 */
459 __STATIC_INLINE void ll_ospi_x_set_txdpd_count(ospi_x_regs_t * OSPIx, uint32_t txdpd_cnt)
460 {
461 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_CNT, txdpd_cnt << OSPI_X_TXDPD_CNT_POS);
462 }
463
464 /**
465 * @brief Get clock count for the tXDPD
466 *--------------------------
467 * @param OSPIx OSPI instance
468 * @retval clock count for the tXDPD
469 */
470 __STATIC_INLINE uint32_t ll_ospi_x_get_txdpd_count(ospi_x_regs_t * OSPIx)
471 {
472 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_CNT) >> OSPI_X_TXDPD_CNT_POS);
473 }
474
475 /**
476 * @brief Set clock count for the tXPDPD
477 *--------------------------
478 * @param OSPIx OSPI instance
479 * @param txpdpd_cnt - clock count for the tXPDPD
480 * @retval none
481 */
482 __STATIC_INLINE void ll_ospi_x_set_txpdpd_count(ospi_x_regs_t * OSPIx, uint32_t txpdpd_cnt)
483 {
484 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXPDPD_CNT, txpdpd_cnt << OSPI_X_DPD_EXIT_CYCLE_CNT_POS);
485 }
486
487 /**
488 * @brief Get clock count for the tXPDPD
489 *--------------------------
490 * @param OSPIx OSPI instance
491 * @retval clock count for the tXPDPD
492 */
493 __STATIC_INLINE uint32_t ll_ospi_x_get_txpdpd_count(ospi_x_regs_t * OSPIx)
494 {
495 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXPDPD_CNT) >> OSPI_X_DPD_EXIT_CYCLE_CNT_POS);
496 }
497
498 /**
499 * @brief Trigger the entry half sleep command
500 *--------------------------
501 * @param OSPIx OSPI instance
502 * @retval none
503 */
504 __STATIC_INLINE void ll_ospi_x_entry_half_sleep(ospi_x_regs_t * OSPIx)
505 {
506 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_ENTRY, 0x01 << OSPI_X_HS_ENTRY_POS);
507 }
508
509 /**
510 * @brief Trigger the exit half sleep command
511 *--------------------------
512 * @param OSPIx OSPI instance
513 * @retval none
514 */
515 __STATIC_INLINE void ll_ospi_x_exit_half_sleep(ospi_x_regs_t * OSPIx)
516 {
517 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT, 0x01 << OSPI_X_HS_EXIT_POS);
518 }
519
520 /**
521 * @brief Set ignoring the tXHS or not
522 *--------------------------
523 * @param OSPIx OSPI instance
524 * @param is_ignore - LL_OSPI_X_TXHS_TIME_IGNORE
525 * @retval none
526 */
527 __STATIC_INLINE void ll_ospi_x_set_txhs_ignore(ospi_x_regs_t * OSPIx, uint32_t is_ignore)
528 {
529 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_TIME_IGNORE, is_ignore << OSPI_X_TXHS_TIME_IGNORE_POS);
530 }
531
532 /**
533 * @brief Get whether ignoring the tXHS or not
534 *--------------------------
535 * @param OSPIx OSPI instance
536 * @retval LL_OSPI_X_TXHS_TIME_IGNORE
537 */
538 __STATIC_INLINE uint32_t ll_ospi_x_get_txhs_ignore(ospi_x_regs_t * OSPIx)
539 {
540 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_TIME_IGNORE) >> OSPI_X_TXHS_TIME_IGNORE_POS);
541 }
542
543 /**
544 * @brief Set clock count for the tXHS
545 *--------------------------
546 * @param OSPIx OSPI instance
547 * @param txhs_count - clock count for the tXHS
548 * @retval none
549 */
550 __STATIC_INLINE void ll_ospi_x_set_txhs_count(ospi_x_regs_t * OSPIx, uint32_t txhs_count)
551 {
552 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_CNT, txhs_count << OSPI_X_TXHS_CNT_POS);
553 }
554
555 /**
556 * @brief Get clock count for the tXHS
557 *--------------------------
558 * @param OSPIx OSPI instance
559 * @retval clock count for the tXHS
560 */
561 __STATIC_INLINE uint32_t ll_ospi_x_get_txhs_count(ospi_x_regs_t * OSPIx)
562 {
563 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_CNT) >> OSPI_X_TXHS_CNT_POS);
564 }
565
566 /**
567 * @brief Set clock count for the tXPHS
568 *--------------------------
569 * @param OSPIx OSPI instance
570 * @param txphs_count - clock count for the tXPHS
571 * @retval none
572 */
573 __STATIC_INLINE void ll_ospi_x_set_txphs_count(ospi_x_regs_t * OSPIx, uint32_t txphs_count)
574 {
575 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT_CYCLE_CNT, txphs_count << OSPI_X_HS_EXIT_CYCLE_CNT_POS);
576 }
577
578 /**
579 * @brief Get clock count for the tXPHS
580 *--------------------------
581 * @param OSPIx OSPI instance
582 * @retval clock count for the tXPHS
583 */
584 __STATIC_INLINE uint32_t ll_ospi_x_get_txphs_count(ospi_x_regs_t * OSPIx)
585 {
586 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT_CYCLE_CNT) >> OSPI_X_HS_EXIT_CYCLE_CNT_POS);
587 }
588
589 /**
590 * @brief Enable the global reset interrupt or not
591 *--------------------------
592 * @param OSPIx OSPI instance
593 * @param intr - LL_OSPI_X_INTERRUPT
594 * @retval none
595 */
596 __STATIC_INLINE void ll_ospi_x_set_global_rst_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
597 {
598 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_GLOBAL_RST_IE, intr << OSPI_X_GLOBAL_RST_IE_POS);
599 }
600
601 /**
602 * @brief Check whether the global reset interrupt is enabled or not
603 *--------------------------
604 * @param OSPIx OSPI instance
605 * @retval LL_OSPI_X_INTERRUPT
606 */
607 __STATIC_INLINE uint32_t ll_ospi_x_is_global_rst_interrupt_enabled(ospi_x_regs_t * OSPIx)
608 {
609 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_GLOBAL_RST_IE) == OSPI_X_GLOBAL_RST_IE) ? 1 : 0;
610 }
611
612 /**
613 * @brief Enable the half sleep entry interrupt or not
614 *--------------------------
615 * @param OSPIx OSPI instance
616 * @param intr - LL_OSPI_X_INTERRUPT
617 * @retval none
618 */
619 __STATIC_INLINE void ll_ospi_x_set_half_sleep_entry_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
620 {
621 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_ENTRY_IE, intr << OSPI_X_HS_ENTRY_IE_POS);
622 }
623
624 /**
625 * @brief Check whether the half sleep entry interrupt is enabled or not
626 *--------------------------
627 * @param OSPIx OSPI instance
628 * @retval LL_OSPI_X_INTERRUPT
629 */
630 __STATIC_INLINE uint32_t ll_ospi_x_is_half_sleep_entry_interrupt_enabled(ospi_x_regs_t * OSPIx)
631 {
632 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_ENTRY_IE) == OSPI_X_HS_ENTRY_IE) ? 1 : 0;
633 }
634
635 /**
636 * @brief Enable the half sleep exit interrupt or not
637 *--------------------------
638 * @param OSPIx OSPI instance
639 * @param intr - LL_OSPI_X_INTERRUPT
640 * @retval none
641 */
642 __STATIC_INLINE void ll_ospi_x_set_half_sleep_exit_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
643 {
644 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_EXIT_IE, intr << OSPI_X_HS_EXIT_IE_POS);
645 }
646
647 /**
648 * @brief Check whether the half sleep exit interrupt is enabled or not
649 *--------------------------
650 * @param OSPIx OSPI instance
651 * @retval LL_OSPI_X_INTERRUPT
652 */
653 __STATIC_INLINE uint32_t ll_ospi_x_is_half_sleep_exit_interrupt_enabled(ospi_x_regs_t * OSPIx)
654 {
655 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_EXIT_IE) == OSPI_X_HS_EXIT_IE) ? 1 : 0;
656 }
657
658 /**
659 * @brief Enable the deep power down entry interrupt or not
660 *--------------------------
661 * @param OSPIx OSPI instance
662 * @param intr - LL_OSPI_X_INTERRUPT
663 * @retval none
664 */
665 __STATIC_INLINE void ll_ospi_x_set_dpd_entry_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
666 {
667 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_ENTRY_IE, intr << OSPI_X_DPD_ENTRY_IE_POS);
668 }
669
670 /**
671 * @brief Check whether the deep power down entry interrupt is enabled or not
672 *--------------------------
673 * @param OSPIx OSPI instance
674 * @retval LL_OSPI_X_INTERRUPT
675 */
676 __STATIC_INLINE uint32_t ll_ospi_x_is_dpd_entry_interrupt_enabled(ospi_x_regs_t * OSPIx)
677 {
678 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_ENTRY_IE) == OSPI_X_DPD_ENTRY_IE) ? 1 : 0;
679 }
680
681 /**
682 * @brief Enable the deep power down exit interrupt or not
683 *--------------------------
684 * @param OSPIx OSPI instance
685 * @param intr - LL_OSPI_X_INTERRUPT
686 * @retval none
687 */
688 __STATIC_INLINE void ll_ospi_x_set_dpd_exit_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
689 {
690 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_EXIT_IE, intr << OSPI_X_DPD_EXIT_IE_POS);
691 }
692
693 /**
694 * @brief Check whether the deep power down exit interrupt is enabled or not
695 *--------------------------
696 * @param OSPIx OSPI instance
697 * @retval LL_OSPI_X_INTERRUPT
698 */
699 __STATIC_INLINE uint32_t ll_ospi_x_is_dpd_exit_interrupt_enabled(ospi_x_regs_t * OSPIx)
700 {
701 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_EXIT_IE) == OSPI_X_DPD_EXIT_IE) ? 1 : 0;
702 }
703
704 /**
705 * @brief Enable the dqs timeout interrupt or not
706 *--------------------------
707 * @param OSPIx OSPI instance
708 * @param intr - LL_OSPI_X_INTERRUPT
709 * @retval none
710 */
711 __STATIC_INLINE void ll_ospi_x_set_dqs_timeout_interrupt(ospi_x_regs_t * OSPIx, uint32_t intr)
712 {
713 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DQS_TIMEOUT_IE, intr << OSPI_X_DQS_TIMEOUT_IE_POS);
714 }
715
716 /**
717 * @brief Check whether the dqs timeout interrupt is enabled or not
718 *--------------------------
719 * @param OSPIx OSPI instance
720 * @retval LL_OSPI_X_INTERRUPT
721 */
722 __STATIC_INLINE uint32_t ll_ospi_x_is_dqs_timeout_interrupt_enabled(ospi_x_regs_t * OSPIx)
723 {
724 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DQS_TIMEOUT_IE) == OSPI_X_DQS_TIMEOUT_IE) ? 1 : 0;
725 }
726
727 /**
728 * @brief Check whether the global reset is done or not
729 *--------------------------
730 * @param OSPIx OSPI instance
731 * @retval 1 - done ; 0 - not done
732 */
733 __STATIC_INLINE uint32_t ll_ospi_x_is_global_rst_done(ospi_x_regs_t * OSPIx)
734 {
735 uint32_t status = OSPIx->XFER_STATUS;
736 return ((status & 0x01) > 0 ? 1 : 0);
737 }
738
739 /**
740 * @brief Check whether the half sleep entry operation is done or not
741 *--------------------------
742 * @param OSPIx OSPI instance
743 * @retval 1 - done ; 0 - not done
744 */
745 __STATIC_INLINE uint32_t ll_ospi_x_is_half_sleep_entry_done(ospi_x_regs_t * OSPIx)
746 {
747 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_HS_ENTRY_DONE) == OSPI_X_HS_ENTRY_DONE) ? 1 : 0;
748 }
749
750 /**
751 * @brief Check whether the half sleep exit operation is done or not
752 *--------------------------
753 * @param OSPIx OSPI instance
754 * @retval 1 - done ; 0 - not done
755 */
756 __STATIC_INLINE uint32_t ll_ospi_x_is_half_sleep_exit_done(ospi_x_regs_t * OSPIx)
757 {
758 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_HS_EXIT_DONE) == OSPI_X_HS_EXIT_DONE) ? 1 : 0;
759 }
760
761 /**
762 * @brief Check whether the deep power down entry operation is done or not
763 *--------------------------
764 * @param OSPIx OSPI instance
765 * @retval 1 - done ; 0 - not done
766 */
767 __STATIC_INLINE uint32_t ll_ospi_x_is_dpd_entry_done(ospi_x_regs_t * OSPIx)
768 {
769 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DPD_ENTRY_DONE) == OSPI_X_DPD_ENTRY_DONE) ? 1 : 0;
770 }
771
772 /**
773 * @brief Check whether the deep power down exit operation is done or not
774 *--------------------------
775 * @param OSPIx OSPI instance
776 * @retval 1 - done ; 0 - not done
777 */
778 __STATIC_INLINE uint32_t ll_ospi_x_is_dpd_exit_done(ospi_x_regs_t * OSPIx)
779 {
780 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DPD_EXIT_DONE) == OSPI_X_DPD_EXIT_DONE) ? 1 : 0;
781 }
782
783 /**
784 * @brief Check whether the dqs timeout error happen or not
785 *--------------------------
786 * @param OSPIx OSPI instance
787 * @retval 1 - happen ; 0 - not happen
788 */
789 __STATIC_INLINE uint32_t ll_ospi_x_is_dqs_timeout_err(ospi_x_regs_t * OSPIx)
790 {
791 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DQS_NON_TOGGLE_ERR) == OSPI_X_DQS_NON_TOGGLE_ERR) ? 1 : 0;
792 }
793
794 /**
795 * @brief Set sync read command
796 *--------------------------
797 * @param OSPIx OSPI instance
798 * @param cmd sync read command
799 * @retval none
800 */
801 __STATIC_INLINE void ll_ospi_x_set_sync_read_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
802 {
803 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_RD, cmd << OSPI_X_CMD_SYNC_RD_POS);
804 }
805
806 /**
807 * @brief Get sync read command
808 *--------------------------
809 * @param OSPIx OSPI instance
810 * @retval sync read command
811 */
812 __STATIC_INLINE uint32_t ll_ospi_x_get_sync_read_cmd(ospi_x_regs_t * OSPIx)
813 {
814 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_RD) >> OSPI_X_CMD_SYNC_RD_POS);
815 }
816
817 /**
818 * @brief Set sync write command
819 *--------------------------
820 * @param OSPIx OSPI instance
821 * @param cmd sync write command
822 * @retval none
823 */
824 __STATIC_INLINE void ll_ospi_x_set_sync_write_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
825 {
826 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_WR, cmd << OSPI_X_CMD_SYNC_WR_POS);
827 }
828
829 /**
830 * @brief Get sync write command
831 *--------------------------
832 * @param OSPIx OSPI instance
833 * @retval sync write command
834 */
835 __STATIC_INLINE uint32_t ll_ospi_x_get_sync_write_cmd(ospi_x_regs_t * OSPIx)
836 {
837 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_WR) >> OSPI_X_CMD_SYNC_WR_POS);
838 }
839
840 /**
841 * @brief Set linear burst read command
842 *--------------------------
843 * @param OSPIx: OSPI instance
844 * @param cmd: Linear burst read command
845 * @retval none
846 */
847 __STATIC_INLINE void ll_ospi_x_set_burst_read_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
848 {
849 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_RD, cmd << OSPI_X_CMD_BURST_RD_POS);
850 }
851
852 /**
853 * @brief Get linear burst read command
854 *--------------------------
855 * @param OSPIx OSPI instance
856 * @retval linear burst read command
857 */
858 __STATIC_INLINE uint32_t ll_ospi_x_get_burst_read_cmd(ospi_x_regs_t * OSPIx)
859 {
860 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_RD) >> OSPI_X_CMD_BURST_RD_POS);
861 }
862
863 /**
864 * @brief Set linear burst write command
865 *--------------------------
866 * @param OSPIx: OSPI instance
867 * @param cmd: Linear burst write command
868 * @retval none
869 */
870 __STATIC_INLINE void ll_ospi_x_set_burst_write_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
871 {
872 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_WR, cmd << OSPI_X_CMD_BURST_WR_POS);
873 }
874
875 /**
876 * @brief Get linear burst write command
877 *--------------------------
878 * @param OSPIx OSPI instance
879 * @retval linear burst write command
880 */
881 __STATIC_INLINE uint32_t ll_ospi_x_get_burst_write_cmd(ospi_x_regs_t * OSPIx)
882 {
883 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_WR) >> OSPI_X_CMD_BURST_WR_POS);
884 }
885
886 /**
887 * @brief Set register mode read command
888 *--------------------------
889 * @param OSPIx OSPI instance
890 * @param cmd register mode read
891 * @retval none
892 */
893 __STATIC_INLINE void ll_ospi_x_set_register_read_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
894 {
895 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_RD, cmd << OSPI_X_CMD_REG_RD_POS);
896 }
897
898 /**
899 * @brief Get register mode read command
900 *--------------------------
901 * @param OSPIx OSPI instance
902 * @retval register mode read command
903 */
904 __STATIC_INLINE uint32_t ll_ospi_x_get_register_read_cmd(ospi_x_regs_t * OSPIx)
905 {
906 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_RD) >> OSPI_X_CMD_REG_RD_POS);
907 }
908
909 /**
910 * @brief Set register mode write command
911 *--------------------------
912 * @param OSPIx OSPI instance
913 * @param cmd register mode write command
914 * @retval none
915 */
916 __STATIC_INLINE void ll_ospi_x_set_register_write_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
917 {
918 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_WR, cmd << OSPI_X_CMD_REG_WR_POS);
919 }
920
921 /**
922 * @brief Get register mode write command
923 *--------------------------
924 * @param OSPIx OSPI instance
925 * @retval register mode write command
926 */
927 __STATIC_INLINE uint32_t ll_ospi_x_get_register_write_cmd(ospi_x_regs_t * OSPIx)
928 {
929 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_WR) >> OSPI_X_CMD_REG_WR_POS);
930 }
931
932 /**
933 * @brief Set global reset command
934 *--------------------------
935 * @param OSPIx OSPI instance
936 * @param cmd sync read command
937 * @retval none
938 */
939 __STATIC_INLINE void ll_ospi_x_set_global_rst_cmd(ospi_x_regs_t * OSPIx, uint32_t cmd)
940 {
941 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_GLOBAL_RST, cmd << OSPI_X_CMD_GLOBAL_RST_POS);
942 }
943
944 /**
945 * @brief Get global reset command
946 *--------------------------
947 * @param OSPIx OSPI instance
948 * @retval global reset command
949 */
950 __STATIC_INLINE uint32_t ll_ospi_x_get_global_rst_cmd(ospi_x_regs_t * OSPIx)
951 {
952 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_GLOBAL_RST) >> OSPI_X_CMD_GLOBAL_RST_POS);
953 }
954
955 /**
956 * @brief Set clock count for DQS timeout
957 *--------------------------
958 * @param OSPIx OSPI instance
959 * @param timeout_clk clock count for DQS timeout
960 * @retval none
961 */
962 __STATIC_INLINE void ll_ospi_x_set_dqs_timeout(ospi_x_regs_t * OSPIx, uint32_t timeout_clk)
963 {
964 timeout_clk = (timeout_clk > 31) ? 31 : timeout_clk;
965 MODIFY_REG(OSPIx->DQS_TIMEOUT, OSPI_X_DQS_NON_TGL_TIMEOUT, timeout_clk << OSPI_X_DQS_NON_TGL_TIMEOUT_POS);
966 }
967
968 /**
969 * @brief Get clock count for DQS timeout
970 *--------------------------
971 * @param OSPIx OSPI instance
972 * @retval clock count for DQS timeout
973 */
974 __STATIC_INLINE uint32_t ll_ospi_x_get_dqs_timeout(ospi_x_regs_t * OSPIx)
975 {
976 return (uint32_t)(READ_BITS(OSPIx->DQS_TIMEOUT, OSPI_X_DQS_NON_TGL_TIMEOUT) >> OSPI_X_DQS_NON_TGL_TIMEOUT_POS);
977 }
978
979 /**
980 * @brief Enable the read prefetch feature or not
981 *--------------------------
982 * @param OSPIx OSPI instance
983 * @param is_prefetch - LL_OSPI_X_READ_PREFETCH
984 * @retval none
985 */
986 __STATIC_INLINE void ll_ospi_x_set_read_prefetch(ospi_x_regs_t * OSPIx, uint32_t is_prefetch)
987 {
988 MODIFY_REG(OSPIx->READ_PREFETCH, OSPI_X_RD_DATA_PREFETCH, is_prefetch << OSPI_X_RD_DATA_PREFETCH_POS);
989 }
990
991 /**
992 * @brief Check whether the read prefetch feature is enabled or not
993 *--------------------------
994 * @param OSPIx OSPI instance
995 * @retval LL_OSPI_X_READ_PREFETCH
996 */
997 __STATIC_INLINE uint32_t ll_ospi_x_is_read_prefetch_enabled(ospi_x_regs_t * OSPIx)
998 {
999 return (READ_BITS(OSPIx->READ_PREFETCH, OSPI_X_RD_DATA_PREFETCH) == OSPI_X_RD_DATA_PREFETCH) ? 1 : 0;
1000 }
1001
1002 /**
1003 * @brief Set the Phy Delay TAP
1004 *--------------------------
1005 * @param OSPIx OSPI instance
1006 * @param phy_delay
1007 * @retval none
1008 */
1009 __STATIC_INLINE void ll_ospi_x_set_phy_delay(ospi_x_regs_t * OSPIx, uint32_t phy_delay)
1010 {
1011 MODIFY_REG(OSPIx->PHY_CNTRL_0, 0xFF, phy_delay);
1012 }
1013
1014 /**
1015 * @brief Get the Phy Delay TAP
1016 *--------------------------
1017 * @param OSPIx OSPI instance
1018 * @retval LL_OSPI_X_READ_PREFETCH
1019 */
1020 __STATIC_INLINE uint32_t ll_ospi_x_get_phy_delay(ospi_x_regs_t * OSPIx)
1021 {
1022 return READ_BITS(OSPIx->PHY_CNTRL_0, 0xFF);
1023 }
1024
1025 /**
1026 * @brief Get memory starting address in AHB
1027 *--------------------------
1028 * @param OSPIx OSPI instance
1029 * @retval OSPI0_XIP_BASE
1030 */
1031 __STATIC_INLINE uint32_t ll_ospi_x_get_xip_base_address(ospi_x_regs_t * OSPIx) {
1032 return OSPI0_XIP_BASE;
1033 }
1034
1035 /**
1036 * @brief Configure the ospi_x unit.
1037 * @param OSPIx OSPI instance
1038 * @param p_ospi_x_init pointer to a @ref ll_ospi_x_init_t structure
1039 * @retval An ErrorStatus enumeration value:
1040 * - SUCCESS: spi registers are de-initialized
1041 * - ERROR: not applicable
1042 */
1043 error_status_t ll_ospi_x_init(ospi_x_regs_t * OSPIx, ll_ospi_x_init_t * p_ospi_x_init);
1044
1045 /**
1046 * @brief Set OSPI registers to their reset values.
1047 * @param OSPIx OSPI instance
1048 * @retval An ErrorStatus enumeration value:
1049 * - SUCCESS: spi registers are de-initialized
1050 * - ERROR: invalid spi instance
1051 */
1052 error_status_t ll_ospi_x_deinit(ospi_x_regs_t * OSPIx);
1053 /** @} */
1054 #endif /* OSPI0 */
1055
1056 #ifdef __cplusplus
1057 }
1058 #endif
1059
1060 #endif /* __GR55xx_LL_OSPI_X_H__ */
1061
1062 /** @} */
1063
1064 /** @} */
1065
1066 /** @} */