hal_gdc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file hal_gdc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of Graphics library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup GRAPHICS_SDK Graphics
39 * @{
40 */
41
42 /** @addtogroup HAL_DC HAL DC
43 * @{
44 */
45
46 /** @defgroup HAL_GDC GDC
47 * @brief DC HAL module driver.
48 * @{
49 */
50
51 #ifndef HAL_GDC_H__
52 #define HAL_GDC_H__
53
54 #include "hal_gfx_sys_defs.h"
55 #include "hal_gdc_hal.h"
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 /**
62 * @addtogroup HAL_GDC_MACRO Defines
63 * @{
64 */
65 /** @defgroup HAL_GDC_REG_CFG The DC register configure defines
66 * @{
67 */
68 #define HAL_GDC_CFG_LAYER_EXISTS(i) (1U << (8 + (i)*4)) /**< Configure layer-existence for specifical DC layer */
69 #define HAL_GDC_CFG_LAYER_BLENDER(i) (1U << (8 + (i)*4 + 1)) /**< Configure blender for specifical DC layer */
70 #define HAL_GDC_CFG_LAYER_SCALER(i) (1U << (8 + (i)*4 + 2)) /**< Configure scaler for specifical DC layer */
71 #define HAL_GDC_CFG_LAYER_GAMMA(i) (1U << (8 + (i)*4 + 3)) /**< Configure gamma for specifical DC layer */
72
73 #define HAL_GDC_LAYER_ENABLE (1U << 31) /**< Enable Layer */
74 #define HAL_GDC_ENABLE (1U << 31) /**< Enable DC */
75 #define HAL_GDC_CFG_L3_YUVMEM (1U << 31) /**< Cfg L3 YUV */
76 #define HAL_GDC_EN_L3PIX (1U << 31) /**< Ignore */
77 #define DC_STATUS_rsrvd_0 (1U << 31) /**< Resrved */
78 #define hal_gdc_clkctrl_cg_l3_bus_clk (1U << 31) /**< Ignore */
79 /** @} */
80
81 /** @} */
82
83 /** @addtogroup HAL_GDC_ENUM Enumerations
84 * @{
85 */
86 /**
87 * @brief Layer control definition
88 */
89 typedef enum
90 {
91 HAL_GDC_LAYER_DISABLE = 0, /**< Disable Layer */
92 HAL_GDC_FORCE_A = 1U << 30, /**< Force Alpha */
93 HAL_GDC_SCALE_NN = 1U << 29, /**< Activate Bilinear Filter */
94 HAL_GDC_MODULATE_A = 1U << 28, /**< Modulate Alpha */
95 HAL_GDC_LAYER_AHBLOCK = 1U << 27, /**< Activate HLOCK signal on AHB DMAs */
96 HAL_GDC_LAYER_GAMMALUT_EN = 1U << 26, /**< Enable Gamma Look Up Table */
97 } hal_gdc_layer_ctrl_t;
98
99 /**
100 * @brief Layer blending factor definition
101 */
102 typedef enum
103 {
104 HAL_GDC_BF_ZERO = 0x0, /**< Black */
105 HAL_GDC_BF_ONE = 0x1, /**< White */
106 HAL_GDC_BF_SRCALPHA = 0x2, /**< Alpha Source */
107 HAL_GDC_BF_GLBALPHA = 0x3, /**< Alpha Global */
108 HAL_GDC_BF_SRCGBLALPHA = 0x4, /**< Alpha Source And Alpha Global */
109 HAL_GDC_BF_INVSRCALPHA = 0x5, /**< Inverted Source */
110 HAL_GDC_BF_INVGBLALPHA = 0x6, /**< Inverted Global */
111 HAL_GDC_BF_INVSRCGBLALPHA = 0x7, /**< Inverted Source And Global */
112 HAL_GDC_BF_DSTALPHA = 0xa, /**< Alpha Destination */
113 HAL_GDC_BF_INVDSTALPHA = 0xb, /**< Inverted Destination */
114 } hal_gdc_blend_factors_t;
115
116 /**
117 * @brief Layer blending mode definition
118 */
119 typedef enum
120 {
121 HAL_GDC_BL_SIMPLE = (HAL_GDC_BF_SRCALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)), /**< Sa * Sa + Da * (1 - Sa) */
122 HAL_GDC_BL_CLEAR = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_ZERO <<4)), /**< 0 */
123 HAL_GDC_BL_SRC = (HAL_GDC_BF_ONE | (HAL_GDC_BF_ZERO <<4)), /**< Sa */
124 HAL_GDC_BL_SRC_OVER = (HAL_GDC_BF_ONE | (HAL_GDC_BF_INVSRCALPHA <<4)), /**< Sa + Da * (1 - Sa) */
125 HAL_GDC_BL_DST_OVER = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_ONE <<4)), /**< Sa * (1 - Da) + Da */
126 HAL_GDC_BL_SRC_IN = (HAL_GDC_BF_DSTALPHA | (HAL_GDC_BF_ZERO <<4)), /**< Sa * Da */
127 HAL_GDC_BL_DST_IN = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_SRCALPHA <<4)), /**< Da * Sa */
128 HAL_GDC_BL_SRC_OUT = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_ZERO <<4)), /**< Sa * (1 - Da) */
129 HAL_GDC_BL_DST_OUT = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_INVSRCALPHA <<4)), /**< Da * (1 - Sa) */
130 HAL_GDC_BL_SRC_ATOP = (HAL_GDC_BF_DSTALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)), /**< Sa * Da + Da * (1 - Sa) */
131 HAL_GDC_BL_DST_ATOP = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_SRCALPHA <<4)), /**< Sa * (1 - Da) + Da * Sa */
132 HAL_GDC_BL_ADD = (HAL_GDC_BF_ONE | (HAL_GDC_BF_ONE <<4)), /**< Sa + Da */
133 HAL_GDC_BL_XOR = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)), /**< Sa * (1 - Da) + Da * (1 - Sa) */
134 } hal_gdc_blend_mode_t;
135
136 /**
137 * @brief Layer color mode definition
138 */
139 typedef enum
140 {
141 HAL_GDC_RGBA5551 = 0x01, /**< RGBA5551 */
142 HAL_GDC_ABGR8888 = 0x02, /**< ABGR8888 */
143 HAL_GDC_RGB332 = 0x04, /**< RGB332 */
144 HAL_GDC_RGB565 = 0x05, /**< RGB565 */
145 HAL_GDC_BGRA8888 = 0x06, /**< BGRA8888 */
146 HAL_GDC_L8 = 0x07, /**< L8 */
147 HAL_GDC_L1 = 0x08, /**< L1 */
148 HAL_GDC_L4 = 0x09, /**< L4 */
149 HAL_GDC_YUYV = 0x0a, /**< YUYV */
150 HAL_GDC_RGB24 = 0x0b, /**< RGB24 */
151 HAL_GDC_YUY2 = 0x0c, /**< YUY2 */
152 HAL_GDC_RGBA8888 = 0x0d, /**< RGBA8888 */
153 HAL_GDC_ARGB8888 = 0x0e, /**< ARGB8888 */
154 HAL_GDC_V_YUV420 = 0x10, /**< V_YUV420 */
155 HAL_GDC_TLYUV420 = 0x11, /**< TLYUV420 */
156 HAL_GDC_TSC4 = 0x12, /**< TSC4 */
157 HAL_GDC_TSC6 = 0x13, /**< TSC6 */
158 HAL_GDC_TSC6A = 0x14, /**< TSC6A */
159 HAL_GDC_RGBA4444 = 0x15, /**< RGBA4444 */
160 HAL_GDC_ARGB4444 = 0x18, /**< ARGB4444 */
161 } hal_gdc_format_t;
162
163 /**
164 * @brief Layer video mode definition
165 */
166 typedef enum
167 {
168 HAL_GDC_DISABLE = 0, /**< DISABLE */
169 HAL_GDC_CURSOR = 1U << 30, /**< CURSOR */
170 HAL_GDC_NEG_V = 1U << 28, /**< NEG_V */
171 HAL_GDC_NEG_H = 1U << 27, /**< NEG_H */
172 HAL_GDC_NEG_DE = 1U << 26, /**< NEG_DE */
173 HAL_GDC_DITHER = 1U << 24, /**< DITHER 18-bit */
174 HAL_GDC_DITHER16 = 2U << 24, /**< DITHER 16-bit */
175 HAL_GDC_DITHER15 = 3U << 24, /**< DITHER 15-bit */
176 HAL_GDC_SINGLEV = 1U << 23, /**< SINGLEV */
177 HAL_GDC_INVPIXCLK = 1U << 22, /**< INVPIXCLK */
178 HAL_GDC_PALETTE = 1U << 20, /**< PALETTE */
179 HAL_GDC_GAMMA = 1U << 20, /**< GAMMA */
180 HAL_GDC_BLANK = 1U << 19, /**< BLANK */
181 HAL_GDC_INTERLACE = 1U << 18, /**< INTERLACE */
182 HAL_GDC_ONE_FRAME = 1U << 17, /**< ONE_FRAME */
183 HAL_GDC_P_RGB3_18B = 1U << 12, /**< P_RGB3 */
184 HAL_GDC_P_RGB3_18B1= 2U << 12, /**< P_RGB3 */
185 HAL_GDC_P_RGB3_16B = 3U << 12, /**< P_RGB3 */
186 HAL_GDC_P_RGB3_16B1= 4U << 12, /**< P_RGB3 */
187 HAL_GDC_P_RGB3_16B2= 5U << 12, /**< P_RGB3 */
188 HAL_GDC_CLKOUTDIV = 1U << 11, /**< CLKOUTDIV */
189 HAL_GDC_LVDSPADS = 1U << 10, /**< LVDSPADS */
190 HAL_GDC_YUVOUT = 1U << 9, /**< YUVOUT */
191 HAL_GDC_MIPI_OFF = 1U << 4, /**< MIPI_OFF */
192 HAL_GDC_OUTP_OFF = 1U << 3, /**< OUTP_OFF */
193 HAL_GDC_LVDS_OFF = 1U << 2, /**< LVDS_OFF */
194 HAL_GDC_SCANDOUBLE = 1U << 1, /**< SCANDOUBLE */
195 HAL_GDC_TESTMODE = 1U << 0, /**< TESTMODE */
196 HAL_GDC_P_RGB3 = 0U << 5, /**< P_RGB3 */
197 HAL_GDC_S_RGBX4 = 1U << 5, /**< S_RGBX4 */
198 HAL_GDC_S_RGB3 = 2U << 5, /**< S_RGB3 */
199 HAL_GDC_S_12BIT = 3U << 5, /**< S_12BIT */
200 HAL_GDC_LVDS_ISP68 = 4U << 5, /**< LVDS_ISP68 */
201 HAL_GDC_LVDS_ISP8 = 5U << 5, /**< LVDS_ISP8 */
202 HAL_GDC_T_16BIT = 6U << 5, /**< T_16BIT */
203 HAL_GDC_BT656 = 7U << 5, /**< BT656 */
204 HAL_GDC_JDIMIP = 8U << 5, /**< JDIMIP */
205 HAL_GDC_LUT8 = 1U << 20 /**< LUT8 */
206 } hal_gdc_videomode_t;
207
208 /**
209 * @brief Layer configuration definition
210 */
211 typedef enum
212 {
213 HAL_GDC_CFG_PALETTE = 1U << 0, /**< Global Gamma enabled */
214 HAL_GDC_CFG_FIXED_CURSOR = 1U << 1, /**< Fixed Cursor enabled */
215 HAL_GDC_CFG_PROGR_CURSOR = 1U << 2, /**< Programmable Cursor enabled */
216 HAL_GDC_CFG_DITHERING = 1U << 3, /**< Dithering enabled */
217 HAL_GDC_CFG_FORMAT = 1U << 4, /**< Formatting enabled */
218 HAL_GDC_CFG_HiQ_YUV = 1U << 5, /**< High Quality YUV converted enabled */
219 HAL_GDC_CFG_DBIB = 1U << 6, /**< DBI Type-B interface enabled */
220 HAL_GDC_CFG_YUVOUT = 1U << 7, /**< RGB to YUV converted */
221 HAL_GDC_CFG_L0_ENABLED = 1U << 8, /**< Layer 0 enabled */
222 HAL_GDC_CFG_L0_BLENDER = 1U << 9, /**< Layer 0 has blender */
223 HAL_GDC_CFG_L0_SCALER = 1U << 10, /**< Layer 0 has scaler */
224 HAL_GDC_CFG_L0_GAMMA = 1U << 11, /**< Layer 0 has gamma LUT */
225 HAL_GDC_CFG_L1_ENABLED = 1U << 12, /**< Layer 1 enabled */
226 HAL_GDC_CFG_L1_BLENDER = 1U << 13, /**< Layer 1 has blender */
227 HAL_GDC_CFG_L1_SCALER = 1U << 14, /**< Layer 1 has scaler */
228 HAL_GDC_CFG_L1_GAMMA = 1U << 15, /**< Layer 1 has gamma LUT */
229 HAL_GDC_CFG_L2_ENABLED = 1U << 16, /**< Layer 2 enabled */
230 HAL_GDC_CFG_L2_BLENDER = 1U << 17, /**< Layer 2 has blender */
231 HAL_GDC_CFG_L2_SCALER = 1U << 18, /**< Layer 2 has scaler */
232 HAL_GDC_CFG_L2_GAMMA = 1U << 19, /**< Layer 2 has gamma LUT */
233 HAL_GDC_CFG_L3_ENABLED = 1U << 20, /**< Layer 3 enabled */
234 HAL_GDC_CFG_L3_BLENDER = 1U << 21, /**< Layer 3 has blender */
235 HAL_GDC_CFG_L3_SCALER = 1U << 22, /**< Layer 3 has scaler */
236 HAL_GDC_CFG_L3_GAMMA = 1U << 23, /**< Layer 3 has gamma LUT */
237 HAL_GDC_CFG_SPI = 1U << 24, /**< SPI interface is enabled */
238 HAL_GDC_CFG_L0_YUVMEM = 1U << 28, /**< layer 0 has YUV Memory */
239 HAL_GDC_CFG_L1_YUVMEM = 1U << 29, /**< layer 1 has YUV Memory */
240 HAL_GDC_CFG_L2_YUVMEM = 1U << 30, /**< layer 2 has YUV Memory */
241 } hal_gdc_config_t;
242
243 /**
244 * @brief DC status definition
245 */
246 typedef enum
247 {
248 DC_STATUS_rsrvd_1 = (1U<<30), /**< Reserved bit */
249 DC_STATUS_rsrvd_2 = (1U<<29), /**< Reserved bit */
250 DC_STATUS_rsrvd_3 = (1U<<28), /**< Reserved bit */
251 DC_STATUS_rsrvd_4 = (1U<<27), /**< Reserved bit */
252 DC_STATUS_rsrvd_5 = (1U<<26), /**< Reserved bit */
253 DC_STATUS_rsrvd_6 = (1U<<25), /**< Reserved bit */
254 DC_STATUS_rsrvd_7 = (1U<<24), /**< Reserved bit */
255 DC_STATUS_rsrvd_8 = (1U<<23), /**< Reserved bit */
256 DC_STATUS_rsrvd_9 = (1U<<22), /**< Reserved bit */
257 DC_STATUS_rsrvd_10 = (1U<<21), /**< Reserved bit */
258 DC_STATUS_rsrvd_11 = (1U<<20), /**< Reserved bit */
259 DC_STATUS_rsrvd_12 = (1U<<19), /**< Reserved bit */
260 DC_STATUS_rsrvd_13 = (1U<<18), /**< Reserved bit */
261 DC_STATUS_rsrvd_14 = (1U<<17), /**< Reserved bit */
262 DC_STATUS_rsrvd_15 = (1U<<16), /**< Reserved bit */
263 DC_STATUS_dbi_cmd_ready = (1U<<15), /**< DBI i/f fifo full */
264 DC_STATUS_dbi_cs = (1U<<14), /**< DBI/SPI i/f active transaction */
265 DC_STATUS_frame_end = (1U<<13), /**< End of frame pulse */
266 DC_STATUS_dbi_pending_trans = (1U<<12), /**< pending command/data transaction */
267 DC_STATUS_dbi_pending_cmd = (1U<<11), /**< pending command */
268 DC_STATUS_dbi_pending_data = (1U<<10), /**< pending pixel data */
269 DC_STATUS_dbi_busy =((1U<<16)|(1U<<14)|(1U<<13)|(1U<<12)|(1U<<11)|(1U<<10)), /**< DBI i/f busy */
270 DC_STATUS_mmu_error = (1U<< 9), /**< not implemented */
271 DC_STATUS_te = (1U<< 8), /**< tearing */
272 DC_STATUS_sticky = (1U<< 7), /**< underflow flag */
273 DC_STATUS_underflow = (1U<< 6), /**< underflow signal */
274 DC_STATUS_LASTROW = (1U<< 5), /**< last scan-row */
275 DC_STATUS_DPI_Csync = (1U<< 4), /**< DPI C-sync */
276 DC_STATUS_vsync_te = (1U<< 3), /**< Vsync or Tearing */
277 DC_STATUS_hsync = (1U<< 2), /**< Hsync */
278 DC_STATUS_framegen_busy = (1U<< 1), /**< Frame-generation in-progress */
279 DC_STATUS_ACTIVE = (1U<< 0), /**< active */
280 } hal_gdc_status_t;
281
282 /**
283 * @brief DC clock control definition
284 */
285 typedef enum
286 {
287 HAL_GDC_EN_PIXCLK = (1U<<22), /**< Resolution X */
288 HAL_GDC_EN_CFCLK = (1U<<23), /**< RegFile clock-gaters bypass */
289 HAL_GDC_EN_L0BUS = (1U<<24), /**< layer 0 bus clock clock-gater bypass */
290 HAL_GDC_EN_L0PIX = (1U<<25), /**< layer 0 pixel clock clock-gater bypass */
291 HAL_GDC_EN_L1BUS = (1U<<26), /**< layer 1 bus clock clock-gater bypass */
292 HAL_GDC_EN_L1PIX = (1U<<27), /**< layer 1 pixel clock clock-gater bypass */
293 HAL_GDC_EN_L2BUS = (1U<<28), /**< layer 2 bus clock clock-gater bypass */
294 HAL_GDC_EN_L2PIX = (1U<<29), /**< layer 2 pixel clock clock-gater bypass */
295 HAL_GDC_EN_L3BUS = (1U<<30), /**< layer 3 bus clock clock-gater bypass */
296 } hal_gdc_clkctrl_t;
297
298 /**
299 * @brief DC clock cg control definition
300 */
301 typedef enum
302 {
303 hal_gdc_clkctrl_cg_l3_pix_clk = (1U<<30), /**< layer 3 bus clock clock-gater bypass */
304 hal_gdc_clkctrl_cg_l2_bus_clk = (1U<<29), /**< layer 2 bus clock clock-gater bypass */
305 hal_gdc_clkctrl_cg_l2_pix_clk = (1U<<28), /**< layer 2 pixel clock clock-gater bypass */
306 hal_gdc_clkctrl_cg_l1_bus_clk = (1U<<27), /**< layer 1 bus clock clock-gater bypass */
307 hal_gdc_clkctrl_cg_l1_pix_clk = (1U<<26), /**< layer 1 pixel clock clock-gater bypass */
308 hal_gdc_clkctrl_cg_l0_bus_clk = (1U<<25), /**< layer 0 bus clock clock-gater bypass */
309 hal_gdc_clkctrl_cg_l0_pix_clk = (1U<<24), /**< layer 0 pixel clock clock-gater bypass */
310 hal_gdc_clkctrl_cg_regfil_clk = (1U<<23), /**< RegFile clock-gaters bypass */
311 hal_gdc_clkctrl_cg_bypass_clk = (1U<<22), /**< Clock-gaters bypass */
312 hal_gdc_clkctrl_cg_rsrvd_21 = (1U<<21), /**< Reserved bit */
313 hal_gdc_clkctrl_cg_rsrvd_20 = (1U<<20), /**< Reserved bit */
314 hal_gdc_clkctrl_cg_rsrvd_19 = (1U<<19), /**< Reserved bit */
315 hal_gdc_clkctrl_cg_rsrvd_18 = (1U<<18), /**< Reserved bit */
316 hal_gdc_clkctrl_cg_rsrvd_17 = (1U<<17), /**< Reserved bit */
317 hal_gdc_clkctrl_cg_rsrvd_16 = (1U<<16), /**< Reserved bit */
318 hal_gdc_clkctrl_cg_rsrvd_15 = (1U<<15), /**< Reserved bit */
319 hal_gdc_clkctrl_cg_rsrvd_14 = (1U<<14), /**< Reserved bit */
320 hal_gdc_clkctrl_cg_rsrvd_13 = (1U<<13), /**< Reserved bit */
321 hal_gdc_clkctrl_cg_rsrvd_12 = (1U<<12), /**< Reserved bit */
322 hal_gdc_clkctrl_cg_rsrvd_11 = (1U<<11), /**< Reserved bit */
323 hal_gdc_clkctrl_cg_rsrvd_10 = (1U<<10), /**< Reserved bit */
324 hal_gdc_clkctrl_cg_rsrvd_9 = (1U<< 9), /**< Reserved bit */
325 hal_gdc_clkctrl_cg_rsrvd_8 = (1U<< 8), /**< Reserved bit */
326 hal_gdc_clkctrl_cg_rsrvd_7 = (1U<< 7), /**< Reserved bit */
327 hal_gdc_clkctrl_cg_rsrvd_6 = (1U<< 6), /**< Reserved bit */
328 hal_gdc_clkctrl_cg_rsrvd_5 = (1U<< 5), /**< Reserved bit */
329 hal_gdc_clkctrl_cg_rsrvd_4 = (1U<< 4), /**< Reserved bit */
330 hal_gdc_clkctrl_cg_rsrvd_3 = (1U<< 3), /**< Reserved bit */
331 hal_gdc_clkctrl_cg_clk_swap = (1U<< 2), /**< Pixel generation and format clock swap */
332 hal_gdc_clkctrl_cg_clk_inv = (1U<< 1), /**< Invert (ouput) clock polarity */
333 hal_gdc_clkctrl_cg_clk_en = (1U<< 0), /**< Enable clock divider */
334
335 } hal_gdc_clkctrl_cg_t;
336
337 /** @} */
338
339 /** @addtogroup HAL_DC_STRUCTURES Structures
340 * @{
341 */
342 /**
343 * @brief Display parameters definition
344 */
345 typedef struct __hal_gdc_display_t
346 {
347 uint32_t resx ; /**< Resolution X */
348 uint32_t resy ; /**< Resolution Y */
349 uint32_t fpx ; /**< Front Porch X */
350 uint32_t fpy ; /**< Front Porch Y */
351 uint32_t bpx ; /**< Back Porch X */
352 uint32_t bpy ; /**< Back Porch Y */
353 uint32_t blx ; /**< Blanking X */
354 uint32_t bly ; /**< Blanking Y */
355 } hal_gdc_display_t;
356
357 /**
358 * @brief Layer parameters definition
359 */
360 typedef struct __hal_gdc_layer_t
361 {
362 void *baseaddr_virt ; /**< Virtual Address */
363 uintptr_t baseaddr_phys ; /**< Physical Address */
364 uint32_t resx ; /**< Resolution X */
365 uint32_t resy ; /**< Resolution Y */
366 int32_t stride ; /**< Stride */
367 int32_t startx ; /**< Start X */
368 int32_t starty ; /**< Start Y */
369 uint32_t sizex ; /**< Size X */
370 uint32_t sizey ; /**< Size Y */
371 uint8_t alpha ; /**< Alpha */
372 uint8_t blendmode ; /**< Blending Mode */
373 uint8_t buscfg ; /**< bugcfg */
374 hal_gdc_format_t format ; /**< Format */
375 uint32_t mode ; /**< Mode */
376 uint32_t u_base ; /**< U Base */
377 uint32_t v_base ; /**< Y Base */
378 uint32_t u_stride ; /**< U Stride */
379 uint32_t v_stride ; /**< V Stride */
380 } hal_gdc_layer_t;
381
382 /** @} */
383
384 /**
385 * @addtogroup HAL_GDC_FUNCTION Functions
386 * @{
387 */
388 /**
389 *****************************************************************************************
390 * @brief Initialize hal_gdc library.
391 *
392 * @return -1 on error
393 *****************************************************************************************
394 */
395 int hal_gdc_init(void);
396
397 /**
398 *****************************************************************************************
399 * @brief Read Configuration Register.
400 *
401 * @return Configuration Register Value
402 *****************************************************************************************
403 */
404 uint32_t hal_gdc_get_config(void);
405
406 /**
407 *****************************************************************************************
408 * @brief Read CRC Checksum Register.
409 *
410 * @return CRC checksum value of last frame. For testing purposes
411 *****************************************************************************************
412 */
413 uint32_t hal_gdc_get_crc(void);
414
415 /**
416 *****************************************************************************************
417 * @brief Set hal_gdc Background Color.
418 *
419 * @param[in] rgba: a 32-bit rgba value (0xRRGGBBXX - Red: color[31:24], Green: color[23:16], Blue: color[15:8])
420 *****************************************************************************************
421 */
422 void hal_gdc_set_bgcolor(uint32_t rgba);
423
424 /**
425 *****************************************************************************************
426 * @brief Set Display timing parameters.
427 *
428 * @param[in] resx: Resolution X
429 * @param[in] fpx: Front Porch X
430 * @param[in] blx: Blanking X
431 * @param[in] bpx: Back Porch X
432 * @param[in] resy: Resolution Y
433 * @param[in] fpy: Front Porch Y
434 * @param[in] bly: Blanking Y
435 * @param[in] bpy: Back Porch Y
436 *****************************************************************************************
437 */
438 void hal_gdc_timing(int resx, int fpx, int blx, int bpx, int resy, int fpy, int bly, int bpy);
439
440 /**
441 *****************************************************************************************
442 * @brief Get stride size in bytes.
443 *
444 * @param[in] format: Texture color format
445 * @param[in] width: Texture width
446 *
447 * @return Stride in bytes
448 *****************************************************************************************
449 */
450 int hal_gdc_stride_size(hal_gdc_format_t format, int width);
451
452 /**
453 *****************************************************************************************
454 * @brief Set the built-in Clock Dividers and DMA Line Prefetch. (See Configuration Register 0x4)
455 *
456 * @param[in] div: Set Divider 1
457 * @param[in] div2: Set Divider 2
458 * @param[in] dma_prefetch: Set number of lines for the dma to prefetch
459 * @param[in] phase: Clock phase shift
460 *****************************************************************************************
461 */
462 void hal_gdc_clkdiv(int div, int div2, int dma_prefetch, int phase);
463
464 /**
465 *****************************************************************************************
466 * @brief Control the clock gaters
467 *
468 * @param[in] ctrl: struct control
469 *****************************************************************************************
470 */
471 void hal_gdc_clkctrl(hal_gdc_clkctrl_t ctrl);
472
473 /**
474 *****************************************************************************************
475 * @brief Set operation mode
476 *
477 * @param[in] mode: Mode of operation (See Register 0)
478 *****************************************************************************************
479 */
480 void hal_gdc_set_mode(int mode);
481
482 /**
483 *****************************************************************************************
484 * @brief Get status from Status Register
485 *
486 * @return Status of DC
487 *****************************************************************************************
488 */
489 uint32_t hal_gdc_get_status (void);
490
491 /**
492 *****************************************************************************************
493 * @brief Request a VSync Interrupt without blocking
494 *
495 * @return Status of DC
496 *****************************************************************************************
497 */
498 void hal_gdc_request_vsync_non_blocking(void);
499
500 /**
501 *****************************************************************************************
502 * @brief Set the Layer Mode. This function can enable a layer and set attributes to it
503 *
504 * @param[in] layer_no: The layer number
505 * @param[in] layer: Attributes struct
506 *****************************************************************************************
507 */
508 void hal_gdc_set_layer (int layer_no, hal_gdc_layer_t *layer);
509
510 /**
511 *****************************************************************************************
512 * @brief Set the physical address of a layer.
513 *
514 * @param[in] layer_no: The layer number
515 * @param[in] addr: Layer Physical Address
516 *****************************************************************************************
517 */
518 void hal_gdc_set_layer_addr(int layer_no, uintptr_t addr);
519
520 /**
521 *****************************************************************************************
522 * @brief Set the physical address of a layer.
523 *
524 * @param[in] layer: Layer number
525 * @param[in] index: Layer Physical Address
526 * @param[in] colour: 32-bit RGBA color value or gamma index
527 *****************************************************************************************
528 */
529 void hal_gdc_set_layer_gamma_lut(int layer, int index, int colour);
530
531 /**
532 *****************************************************************************************
533 * @brief Get an entry in the lut8 Palette Gamma table for a layer
534 *
535 * @param[in] layer: Layer number
536 * @param[in] index: Color Index
537 *
538 * @return Palette index
539 *****************************************************************************************
540 */
541 int hal_gdc_get_layer_gamma_lut(int layer, int index);
542
543 /**
544 *****************************************************************************************
545 * @brief Sets an entry in the lut8 Palatte Gamma table.
546 *
547 * @param[in] index: Color Index
548 * @param[in] colour: 32-bit RGBA colour value or Gamma index
549 *****************************************************************************************
550 */
551 void hal_gdc_set_palette(uint32_t index, uint32_t colour);
552
553 /**
554 *****************************************************************************************
555 * @brief Reads an entry from the lut8 Palatte Gamma table
556 *
557 * @param[in] index: Color Index
558 *
559 * @return Colour for given palette index
560 *****************************************************************************************
561 */
562 int hal_gdc_get_palette(uint32_t index);
563
564 /**
565 *****************************************************************************************
566 * @brief Disable layer
567 *
568 * @param[in] layer_no: Layer Number
569 *****************************************************************************************
570 */
571 void hal_gdc_layer_disable(int layer_no);
572
573 /**
574 *****************************************************************************************
575 * @brief Enable layer
576 *
577 * @param[in] layer_no: Layer Number
578 *****************************************************************************************
579 */
580 void hal_gdc_layer_enable(int layer_no);
581
582 /**
583 *****************************************************************************************
584 * @brief Enable or Disable fixed cursor
585 *
586 * @param[in] enable: 1 for enable or 0 for disable cursor
587 *****************************************************************************************
588 */
589 void hal_gdc_cursor_enable(int enable);
590
591 /**
592 *****************************************************************************************
593 * @brief Set the location of the cursor
594 *
595 * @param[in] x: Cursor X coordinate
596 * @param[in] y: Cursor Y coordinate
597 *****************************************************************************************
598 */
599 void hal_gdc_cursor_xy(int x, int y);
600
601 /**
602 *****************************************************************************************
603 * @brief Set programmable cursor image (32x32 pixels)
604 *
605 * @param[in] img: Base address of the 32x32 Cursor Image
606 *****************************************************************************************
607 */
608 void hal_gdc_set_cursor_img(unsigned char *img);
609
610 /**
611 *****************************************************************************************
612 * @brief Set a color for the Cursor LUT
613 *
614 * @param[in] index: Color index
615 * @param[in] color: 32-bit RGBA value
616 *****************************************************************************************
617 */
618 void hal_gdc_set_cursor_lut(uint32_t index, uint32_t color);
619
620 /**
621 *****************************************************************************************
622 * @brief Check whether hal_gdc supports a specific characteristic
623 *
624 * @param[in] flag: Flag to query
625 *
626 * @return True if the characteristic is supported
627 *****************************************************************************************
628 */
629 unsigned char hal_gdc_check_config(hal_gdc_config_t flag);
630
631 /**
632 *****************************************************************************************
633 * @brief Read Color Mode Register
634 *
635 * @return Color mode register
636 *****************************************************************************************
637 */
638 uint32_t hal_gdc_get_col_mode(void);
639
640 /**
641 *****************************************************************************************
642 * @brief Get the number of layers available
643 *
644 * @return Number of layers
645 *****************************************************************************************
646 */
647 int hal_gdc_get_layer_count(void);
648
649 /** @} */
650
651 #ifdef __cplusplus
652 }
653 #endif
654
655 #endif
656 /** @} */
657 /** @} */
658 /** @} */
659
__hal_gdc_layer_t::baseaddr_phys
uintptr_t baseaddr_phys
Physical Address.
Definition: hal_gdc.h:363
HAL_GDC_EN_L2BUS
@ HAL_GDC_EN_L2BUS
layer 2 bus clock clock-gater bypass
Definition: hal_gdc.h:293
HAL_GDC_TSC6
@ HAL_GDC_TSC6
TSC6.
Definition: hal_gdc.h:157
HAL_GDC_LAYER_AHBLOCK
@ HAL_GDC_LAYER_AHBLOCK
Activate HLOCK signal on AHB DMAs.
Definition: hal_gdc.h:95
HAL_GDC_CFG_PROGR_CURSOR
@ HAL_GDC_CFG_PROGR_CURSOR
Programmable Cursor enabled.
Definition: hal_gdc.h:215
HAL_GDC_CFG_PALETTE
@ HAL_GDC_CFG_PALETTE
Global Gamma enabled.
Definition: hal_gdc.h:213
hal_gdc_cursor_xy
void hal_gdc_cursor_xy(int x, int y)
Set the location of the cursor.
hal_gdc_clkctrl_cg_rsrvd_8
@ hal_gdc_clkctrl_cg_rsrvd_8
Reserved bit.
Definition: hal_gdc.h:325
hal_gdc_clkctrl_cg_rsrvd_19
@ hal_gdc_clkctrl_cg_rsrvd_19
Reserved bit.
Definition: hal_gdc.h:314
DC_STATUS_dbi_cs
@ DC_STATUS_dbi_cs
DBI/SPI i/f active transaction.
Definition: hal_gdc.h:264
__hal_gdc_layer_t::u_stride
uint32_t u_stride
U Stride.
Definition: hal_gdc.h:378
__hal_gdc_display_t::resy
uint32_t resy
Resolution Y.
Definition: hal_gdc.h:348
HAL_GDC_EN_L3BUS
@ HAL_GDC_EN_L3BUS
layer 3 bus clock clock-gater bypass
Definition: hal_gdc.h:295
hal_gdc_init
int hal_gdc_init(void)
Initialize hal_gdc library.
hal_gdc_clkctrl_cg_rsrvd_15
@ hal_gdc_clkctrl_cg_rsrvd_15
Reserved bit.
Definition: hal_gdc.h:318
hal_gdc_blend_mode_t
hal_gdc_blend_mode_t
Layer blending mode definition.
Definition: hal_gdc.h:120
DC_STATUS_LASTROW
@ DC_STATUS_LASTROW
last scan-row
Definition: hal_gdc.h:274
HAL_GDC_S_12BIT
@ HAL_GDC_S_12BIT
S_12BIT.
Definition: hal_gdc.h:199
hal_gdc_hal.h
Header file containing functions prototypes of Graphics library.
hal_gdc_clkctrl_cg_rsrvd_13
@ hal_gdc_clkctrl_cg_rsrvd_13
Reserved bit.
Definition: hal_gdc.h:320
DC_STATUS_rsrvd_1
@ DC_STATUS_rsrvd_1
Reserved bit.
Definition: hal_gdc.h:248
hal_gdc_set_cursor_img
void hal_gdc_set_cursor_img(unsigned char *img)
Set programmable cursor image (32x32 pixels)
__hal_gdc_layer_t::v_stride
uint32_t v_stride
V Stride.
Definition: hal_gdc.h:379
__hal_gdc_display_t
Display parameters definition.
Definition: hal_gdc.h:346
HAL_GDC_BL_CLEAR
@ HAL_GDC_BL_CLEAR
0
Definition: hal_gdc.h:122
hal_gdc_clkctrl_cg_l2_pix_clk
@ hal_gdc_clkctrl_cg_l2_pix_clk
layer 2 pixel clock clock-gater bypass
Definition: hal_gdc.h:305
DC_STATUS_rsrvd_9
@ DC_STATUS_rsrvd_9
Reserved bit.
Definition: hal_gdc.h:256
HAL_GDC_BL_SRC
@ HAL_GDC_BL_SRC
Sa.
Definition: hal_gdc.h:123
HAL_GDC_NEG_H
@ HAL_GDC_NEG_H
NEG_H.
Definition: hal_gdc.h:171
__hal_gdc_display_t::bpx
uint32_t bpx
Back Porch X.
Definition: hal_gdc.h:351
HAL_GDC_EN_L0PIX
@ HAL_GDC_EN_L0PIX
layer 0 pixel clock clock-gater bypass
Definition: hal_gdc.h:290
hal_gdc_get_crc
uint32_t hal_gdc_get_crc(void)
Read CRC Checksum Register.
hal_gdc_get_config
uint32_t hal_gdc_get_config(void)
Read Configuration Register.
HAL_GDC_BL_SRC_OVER
@ HAL_GDC_BL_SRC_OVER
Sa + Da * (1 - Sa)
Definition: hal_gdc.h:124
HAL_GDC_CFG_L1_YUVMEM
@ HAL_GDC_CFG_L1_YUVMEM
layer 1 has YUV Memory
Definition: hal_gdc.h:239
__hal_gdc_display_t::fpy
uint32_t fpy
Front Porch Y.
Definition: hal_gdc.h:350
__hal_gdc_layer_t::resy
uint32_t resy
Resolution Y.
Definition: hal_gdc.h:365
HAL_GDC_LVDSPADS
@ HAL_GDC_LVDSPADS
LVDSPADS.
Definition: hal_gdc.h:189
hal_gdc_videomode_t
hal_gdc_videomode_t
Layer video mode definition.
Definition: hal_gdc.h:167
hal_gdc_clkctrl_cg_bypass_clk
@ hal_gdc_clkctrl_cg_bypass_clk
Clock-gaters bypass.
Definition: hal_gdc.h:311
hal_gdc_config_t
hal_gdc_config_t
Layer configuration definition.
Definition: hal_gdc.h:212
DC_STATUS_dbi_cmd_ready
@ DC_STATUS_dbi_cmd_ready
DBI i/f fifo full.
Definition: hal_gdc.h:263
DC_STATUS_DPI_Csync
@ DC_STATUS_DPI_Csync
DPI C-sync.
Definition: hal_gdc.h:275
HAL_GDC_T_16BIT
@ HAL_GDC_T_16BIT
T_16BIT.
Definition: hal_gdc.h:202
hal_gdc_clkctrl_cg_l1_pix_clk
@ hal_gdc_clkctrl_cg_l1_pix_clk
layer 1 pixel clock clock-gater bypass
Definition: hal_gdc.h:307
hal_gdc_format_t
hal_gdc_format_t
Layer color mode definition.
Definition: hal_gdc.h:140
hal_gdc_get_col_mode
uint32_t hal_gdc_get_col_mode(void)
Read Color Mode Register.
DC_STATUS_rsrvd_12
@ DC_STATUS_rsrvd_12
Reserved bit.
Definition: hal_gdc.h:259
HAL_GDC_CFG_SPI
@ HAL_GDC_CFG_SPI
SPI interface is enabled.
Definition: hal_gdc.h:237
HAL_GDC_DITHER15
@ HAL_GDC_DITHER15
DITHER 15-bit.
Definition: hal_gdc.h:175
__hal_gdc_layer_t::starty
int32_t starty
Start Y.
Definition: hal_gdc.h:368
DC_STATUS_mmu_error
@ DC_STATUS_mmu_error
not implemented
Definition: hal_gdc.h:270
__hal_gdc_display_t::fpx
uint32_t fpx
Front Porch X.
Definition: hal_gdc.h:349
HAL_GDC_P_RGB3_16B
@ HAL_GDC_P_RGB3_16B
P_RGB3.
Definition: hal_gdc.h:185
HAL_GDC_EN_PIXCLK
@ HAL_GDC_EN_PIXCLK
Resolution X.
Definition: hal_gdc.h:287
hal_gdc_clkctrl_cg_clk_en
@ hal_gdc_clkctrl_cg_clk_en
Enable clock divider.
Definition: hal_gdc.h:333
HAL_GDC_L4
@ HAL_GDC_L4
L4.
Definition: hal_gdc.h:148
hal_gdc_clkdiv
void hal_gdc_clkdiv(int div, int div2, int dma_prefetch, int phase)
Set the built-in Clock Dividers and DMA Line Prefetch.
HAL_GDC_CFG_L2_BLENDER
@ HAL_GDC_CFG_L2_BLENDER
Layer 2 has blender.
Definition: hal_gdc.h:230
HAL_GDC_BF_INVGBLALPHA
@ HAL_GDC_BF_INVGBLALPHA
Inverted Global.
Definition: hal_gdc.h:110
hal_gdc_clkctrl_cg_l0_bus_clk
@ hal_gdc_clkctrl_cg_l0_bus_clk
layer 0 bus clock clock-gater bypass
Definition: hal_gdc.h:308
hal_gdc_clkctrl_cg_l0_pix_clk
@ hal_gdc_clkctrl_cg_l0_pix_clk
layer 0 pixel clock clock-gater bypass
Definition: hal_gdc.h:309
HAL_GDC_OUTP_OFF
@ HAL_GDC_OUTP_OFF
OUTP_OFF.
Definition: hal_gdc.h:192
__hal_gdc_layer_t::stride
int32_t stride
Stride.
Definition: hal_gdc.h:366
hal_gdc_stride_size
int hal_gdc_stride_size(hal_gdc_format_t format, int width)
Get stride size in bytes.
hal_gdc_clkctrl_t
hal_gdc_clkctrl_t
DC clock control definition.
Definition: hal_gdc.h:286
hal_gdc_clkctrl_cg_rsrvd_20
@ hal_gdc_clkctrl_cg_rsrvd_20
Reserved bit.
Definition: hal_gdc.h:313
DC_STATUS_rsrvd_6
@ DC_STATUS_rsrvd_6
Reserved bit.
Definition: hal_gdc.h:253
DC_STATUS_dbi_busy
@ DC_STATUS_dbi_busy
DBI i/f busy.
Definition: hal_gdc.h:269
HAL_GDC_S_RGB3
@ HAL_GDC_S_RGB3
S_RGB3.
Definition: hal_gdc.h:198
HAL_GDC_L1
@ HAL_GDC_L1
L1.
Definition: hal_gdc.h:147
HAL_GDC_CFG_DITHERING
@ HAL_GDC_CFG_DITHERING
Dithering enabled.
Definition: hal_gdc.h:216
hal_gdc_clkctrl_cg_rsrvd_12
@ hal_gdc_clkctrl_cg_rsrvd_12
Reserved bit.
Definition: hal_gdc.h:321
DC_STATUS_vsync_te
@ DC_STATUS_vsync_te
Vsync or Tearing.
Definition: hal_gdc.h:276
__hal_gdc_layer_t::alpha
uint8_t alpha
Alpha.
Definition: hal_gdc.h:371
HAL_GDC_LVDS_ISP8
@ HAL_GDC_LVDS_ISP8
LVDS_ISP8.
Definition: hal_gdc.h:201
DC_STATUS_frame_end
@ DC_STATUS_frame_end
End of frame pulse.
Definition: hal_gdc.h:265
hal_gdc_request_vsync_non_blocking
void hal_gdc_request_vsync_non_blocking(void)
Request a VSync Interrupt without blocking.
__hal_gdc_layer_t::resx
uint32_t resx
Resolution X.
Definition: hal_gdc.h:364
HAL_GDC_NEG_V
@ HAL_GDC_NEG_V
NEG_V.
Definition: hal_gdc.h:170
hal_gdc_clkctrl_cg_regfil_clk
@ hal_gdc_clkctrl_cg_regfil_clk
RegFile clock-gaters bypass.
Definition: hal_gdc.h:310
DC_STATUS_rsrvd_11
@ DC_STATUS_rsrvd_11
Reserved bit.
Definition: hal_gdc.h:258
hal_gdc_clkctrl_cg_l2_bus_clk
@ hal_gdc_clkctrl_cg_l2_bus_clk
layer 2 bus clock clock-gater bypass
Definition: hal_gdc.h:304
HAL_GDC_CFG_L0_BLENDER
@ HAL_GDC_CFG_L0_BLENDER
Layer 0 has blender.
Definition: hal_gdc.h:222
__hal_gdc_layer_t
Layer parameters definition.
Definition: hal_gdc.h:361
DC_STATUS_hsync
@ DC_STATUS_hsync
Hsync.
Definition: hal_gdc.h:277
__hal_gdc_layer_t::baseaddr_virt
void * baseaddr_virt
Virtual Address.
Definition: hal_gdc.h:362
HAL_GDC_SCALE_NN
@ HAL_GDC_SCALE_NN
Activate Bilinear Filter.
Definition: hal_gdc.h:93
__hal_gdc_layer_t::u_base
uint32_t u_base
U Base.
Definition: hal_gdc.h:376
DC_STATUS_rsrvd_2
@ DC_STATUS_rsrvd_2
Reserved bit.
Definition: hal_gdc.h:249
hal_gdc_clkctrl_cg_rsrvd_16
@ hal_gdc_clkctrl_cg_rsrvd_16
Reserved bit.
Definition: hal_gdc.h:317
HAL_GDC_FORCE_A
@ HAL_GDC_FORCE_A
Force Alpha.
Definition: hal_gdc.h:92
HAL_GDC_ARGB8888
@ HAL_GDC_ARGB8888
ARGB8888.
Definition: hal_gdc.h:153
hal_gfx_sys_defs.h
HAL_GDC_CFG_L2_YUVMEM
@ HAL_GDC_CFG_L2_YUVMEM
layer 2 has YUV Memory
Definition: hal_gdc.h:240
hal_gdc_status_t
hal_gdc_status_t
DC status definition.
Definition: hal_gdc.h:247
DC_STATUS_rsrvd_14
@ DC_STATUS_rsrvd_14
Reserved bit.
Definition: hal_gdc.h:261
HAL_GDC_P_RGB3
@ HAL_GDC_P_RGB3
P_RGB3.
Definition: hal_gdc.h:196
HAL_GDC_NEG_DE
@ HAL_GDC_NEG_DE
NEG_DE.
Definition: hal_gdc.h:172
DC_STATUS_rsrvd_10
@ DC_STATUS_rsrvd_10
Reserved bit.
Definition: hal_gdc.h:257
hal_gdc_set_bgcolor
void hal_gdc_set_bgcolor(uint32_t rgba)
Set hal_gdc Background Color.
HAL_GDC_LAYER_DISABLE
@ HAL_GDC_LAYER_DISABLE
Disable Layer.
Definition: hal_gdc.h:91
DC_STATUS_rsrvd_15
@ DC_STATUS_rsrvd_15
Reserved bit.
Definition: hal_gdc.h:262
HAL_GDC_CFG_L0_GAMMA
@ HAL_GDC_CFG_L0_GAMMA
Layer 0 has gamma LUT.
Definition: hal_gdc.h:224
__hal_gdc_display_t::bly
uint32_t bly
Blanking Y.
Definition: hal_gdc.h:354
hal_gdc_clkctrl_cg_rsrvd_14
@ hal_gdc_clkctrl_cg_rsrvd_14
Reserved bit.
Definition: hal_gdc.h:319
__hal_gdc_layer_t::buscfg
uint8_t buscfg
bugcfg
Definition: hal_gdc.h:373
HAL_GDC_CLKOUTDIV
@ HAL_GDC_CLKOUTDIV
CLKOUTDIV.
Definition: hal_gdc.h:188
HAL_GDC_PALETTE
@ HAL_GDC_PALETTE
PALETTE.
Definition: hal_gdc.h:178
HAL_GDC_BGRA8888
@ HAL_GDC_BGRA8888
BGRA8888.
Definition: hal_gdc.h:145
__hal_gdc_display_t::blx
uint32_t blx
Blanking X.
Definition: hal_gdc.h:353
DC_STATUS_rsrvd_3
@ DC_STATUS_rsrvd_3
Reserved bit.
Definition: hal_gdc.h:250
hal_gdc_clkctrl_cg_rsrvd_5
@ hal_gdc_clkctrl_cg_rsrvd_5
Reserved bit.
Definition: hal_gdc.h:328
HAL_GDC_TSC4
@ HAL_GDC_TSC4
TSC4.
Definition: hal_gdc.h:156
HAL_GDC_RGBA8888
@ HAL_GDC_RGBA8888
RGBA8888.
Definition: hal_gdc.h:152
HAL_GDC_BL_SRC_IN
@ HAL_GDC_BL_SRC_IN
Sa * Da.
Definition: hal_gdc.h:126
hal_gdc_clkctrl_cg_rsrvd_6
@ hal_gdc_clkctrl_cg_rsrvd_6
Reserved bit.
Definition: hal_gdc.h:327
HAL_GDC_CFG_FORMAT
@ HAL_GDC_CFG_FORMAT
Formatting enabled.
Definition: hal_gdc.h:217
HAL_GDC_CFG_L1_ENABLED
@ HAL_GDC_CFG_L1_ENABLED
Layer 1 enabled.
Definition: hal_gdc.h:225
__hal_gdc_layer_t::mode
uint32_t mode
Mode.
Definition: hal_gdc.h:375
hal_gdc_clkctrl_cg_rsrvd_3
@ hal_gdc_clkctrl_cg_rsrvd_3
Reserved bit.
Definition: hal_gdc.h:330
HAL_GDC_EN_L1BUS
@ HAL_GDC_EN_L1BUS
layer 1 bus clock clock-gater bypass
Definition: hal_gdc.h:291
HAL_GDC_P_RGB3_18B1
@ HAL_GDC_P_RGB3_18B1
P_RGB3.
Definition: hal_gdc.h:184
HAL_GDC_RGB24
@ HAL_GDC_RGB24
RGB24.
Definition: hal_gdc.h:150
DC_STATUS_rsrvd_5
@ DC_STATUS_rsrvd_5
Reserved bit.
Definition: hal_gdc.h:252
HAL_GDC_EN_L0BUS
@ HAL_GDC_EN_L0BUS
layer 0 bus clock clock-gater bypass
Definition: hal_gdc.h:289
hal_gdc_set_layer_addr
void hal_gdc_set_layer_addr(int layer_no, uintptr_t addr)
Set the physical address of a layer.
HAL_GDC_YUY2
@ HAL_GDC_YUY2
YUY2.
Definition: hal_gdc.h:151
HAL_GDC_BF_INVDSTALPHA
@ HAL_GDC_BF_INVDSTALPHA
Inverted Destination.
Definition: hal_gdc.h:113
HAL_GDC_MIPI_OFF
@ HAL_GDC_MIPI_OFF
MIPI_OFF.
Definition: hal_gdc.h:191
HAL_GDC_CFG_L1_SCALER
@ HAL_GDC_CFG_L1_SCALER
Layer 1 has scaler.
Definition: hal_gdc.h:227
__hal_gdc_layer_t::blendmode
uint8_t blendmode
Blending Mode.
Definition: hal_gdc.h:372
HAL_GDC_BT656
@ HAL_GDC_BT656
BT656.
Definition: hal_gdc.h:203
hal_gdc_clkctrl_cg_rsrvd_17
@ hal_gdc_clkctrl_cg_rsrvd_17
Reserved bit.
Definition: hal_gdc.h:316
HAL_GDC_CURSOR
@ HAL_GDC_CURSOR
CURSOR.
Definition: hal_gdc.h:169
DC_STATUS_underflow
@ DC_STATUS_underflow
underflow signal
Definition: hal_gdc.h:273
HAL_GDC_GAMMA
@ HAL_GDC_GAMMA
GAMMA.
Definition: hal_gdc.h:179
HAL_GDC_CFG_DBIB
@ HAL_GDC_CFG_DBIB
DBI Type-B interface enabled.
Definition: hal_gdc.h:219
DC_STATUS_dbi_pending_cmd
@ DC_STATUS_dbi_pending_cmd
pending command
Definition: hal_gdc.h:267
DC_STATUS_ACTIVE
@ DC_STATUS_ACTIVE
active
Definition: hal_gdc.h:279
HAL_GDC_RGBA4444
@ HAL_GDC_RGBA4444
RGBA4444.
Definition: hal_gdc.h:159
HAL_GDC_YUVOUT
@ HAL_GDC_YUVOUT
YUVOUT.
Definition: hal_gdc.h:190
HAL_GDC_CFG_L3_SCALER
@ HAL_GDC_CFG_L3_SCALER
Layer 3 has scaler.
Definition: hal_gdc.h:235
HAL_GDC_BL_DST_OVER
@ HAL_GDC_BL_DST_OVER
Sa * (1 - Da) + Da.
Definition: hal_gdc.h:125
HAL_GDC_CFG_L0_SCALER
@ HAL_GDC_CFG_L0_SCALER
Layer 0 has scaler.
Definition: hal_gdc.h:223
HAL_GDC_EN_L1PIX
@ HAL_GDC_EN_L1PIX
layer 1 pixel clock clock-gater bypass
Definition: hal_gdc.h:292
DC_STATUS_rsrvd_4
@ DC_STATUS_rsrvd_4
Reserved bit.
Definition: hal_gdc.h:251
hal_gdc_clkctrl_cg_l1_bus_clk
@ hal_gdc_clkctrl_cg_l1_bus_clk
layer 1 bus clock clock-gater bypass
Definition: hal_gdc.h:306
HAL_GDC_CFG_YUVOUT
@ HAL_GDC_CFG_YUVOUT
RGB to YUV converted.
Definition: hal_gdc.h:220
hal_gdc_clkctrl_cg_rsrvd_10
@ hal_gdc_clkctrl_cg_rsrvd_10
Reserved bit.
Definition: hal_gdc.h:323
HAL_GDC_BL_DST_IN
@ HAL_GDC_BL_DST_IN
Da * Sa.
Definition: hal_gdc.h:127
HAL_GDC_RGB565
@ HAL_GDC_RGB565
RGB565.
Definition: hal_gdc.h:144
hal_gdc_get_palette
int hal_gdc_get_palette(uint32_t index)
Reads an entry from the lut8 Palatte Gamma table.
hal_gdc_timing
void hal_gdc_timing(int resx, int fpx, int blx, int bpx, int resy, int fpy, int bly, int bpy)
Set Display timing parameters.
hal_gdc_layer_t
struct __hal_gdc_layer_t hal_gdc_layer_t
Layer parameters definition.
hal_gdc_get_layer_count
int hal_gdc_get_layer_count(void)
Get the number of layers available.
HAL_GDC_BL_DST_OUT
@ HAL_GDC_BL_DST_OUT
Da * (1 - Sa)
Definition: hal_gdc.h:129
hal_gdc_clkctrl_cg_l3_pix_clk
@ hal_gdc_clkctrl_cg_l3_pix_clk
layer 3 bus clock clock-gater bypass
Definition: hal_gdc.h:303
HAL_GDC_BF_GLBALPHA
@ HAL_GDC_BF_GLBALPHA
Alpha Global.
Definition: hal_gdc.h:107
HAL_GDC_EN_CFCLK
@ HAL_GDC_EN_CFCLK
RegFile clock-gaters bypass.
Definition: hal_gdc.h:288
hal_gdc_set_cursor_lut
void hal_gdc_set_cursor_lut(uint32_t index, uint32_t color)
Set a color for the Cursor LUT.
HAL_GDC_BF_INVSRCGBLALPHA
@ HAL_GDC_BF_INVSRCGBLALPHA
Inverted Source And Global.
Definition: hal_gdc.h:111
hal_gdc_display_t
struct __hal_gdc_display_t hal_gdc_display_t
Display parameters definition.
hal_gdc_get_status
uint32_t hal_gdc_get_status(void)
Get status from Status Register.
__hal_gdc_layer_t::format
hal_gdc_format_t format
Format.
Definition: hal_gdc.h:374
HAL_GDC_BF_ZERO
@ HAL_GDC_BF_ZERO
Black.
Definition: hal_gdc.h:104
HAL_GDC_SINGLEV
@ HAL_GDC_SINGLEV
SINGLEV.
Definition: hal_gdc.h:176
HAL_GDC_CFG_L3_GAMMA
@ HAL_GDC_CFG_L3_GAMMA
Layer 3 has gamma LUT.
Definition: hal_gdc.h:236
HAL_GDC_P_RGB3_16B1
@ HAL_GDC_P_RGB3_16B1
P_RGB3.
Definition: hal_gdc.h:186
DC_STATUS_framegen_busy
@ DC_STATUS_framegen_busy
Frame-generation in-progress.
Definition: hal_gdc.h:278
__hal_gdc_layer_t::v_base
uint32_t v_base
Y Base.
Definition: hal_gdc.h:377
HAL_GDC_BF_INVSRCALPHA
@ HAL_GDC_BF_INVSRCALPHA
Inverted Source.
Definition: hal_gdc.h:109
DC_STATUS_rsrvd_7
@ DC_STATUS_rsrvd_7
Reserved bit.
Definition: hal_gdc.h:254
HAL_GDC_BL_XOR
@ HAL_GDC_BL_XOR
Sa * (1 - Da) + Da * (1 - Sa)
Definition: hal_gdc.h:133
HAL_GDC_CFG_L0_YUVMEM
@ HAL_GDC_CFG_L0_YUVMEM
layer 0 has YUV Memory
Definition: hal_gdc.h:238
HAL_GDC_P_RGB3_18B
@ HAL_GDC_P_RGB3_18B
P_RGB3.
Definition: hal_gdc.h:183
hal_gdc_clkctrl_cg_rsrvd_18
@ hal_gdc_clkctrl_cg_rsrvd_18
Reserved bit.
Definition: hal_gdc.h:315
__hal_gdc_display_t::bpy
uint32_t bpy
Back Porch Y.
Definition: hal_gdc.h:352
HAL_GDC_ONE_FRAME
@ HAL_GDC_ONE_FRAME
ONE_FRAME.
Definition: hal_gdc.h:182
HAL_GDC_BL_SRC_OUT
@ HAL_GDC_BL_SRC_OUT
Sa * (1 - Da)
Definition: hal_gdc.h:128
HAL_GDC_BF_ONE
@ HAL_GDC_BF_ONE
White.
Definition: hal_gdc.h:105
HAL_GDC_BF_SRCALPHA
@ HAL_GDC_BF_SRCALPHA
Alpha Source.
Definition: hal_gdc.h:106
HAL_GDC_BL_DST_ATOP
@ HAL_GDC_BL_DST_ATOP
Sa * (1 - Da) + Da * Sa.
Definition: hal_gdc.h:131
hal_gdc_set_layer
void hal_gdc_set_layer(int layer_no, hal_gdc_layer_t *layer)
Set the Layer Mode.
hal_gdc_clkctrl_cg_clk_inv
@ hal_gdc_clkctrl_cg_clk_inv
Invert (ouput) clock polarity.
Definition: hal_gdc.h:332
HAL_GDC_BF_DSTALPHA
@ HAL_GDC_BF_DSTALPHA
Alpha Destination.
Definition: hal_gdc.h:112
HAL_GDC_CFG_L2_GAMMA
@ HAL_GDC_CFG_L2_GAMMA
Layer 2 has gamma LUT.
Definition: hal_gdc.h:232
hal_gdc_layer_enable
void hal_gdc_layer_enable(int layer_no)
Enable layer.
HAL_GDC_INTERLACE
@ HAL_GDC_INTERLACE
INTERLACE.
Definition: hal_gdc.h:181
HAL_GDC_TSC6A
@ HAL_GDC_TSC6A
TSC6A.
Definition: hal_gdc.h:158
HAL_GDC_BLANK
@ HAL_GDC_BLANK
BLANK.
Definition: hal_gdc.h:180
hal_gdc_clkctrl
void hal_gdc_clkctrl(hal_gdc_clkctrl_t ctrl)
Control the clock gaters.
hal_gdc_layer_disable
void hal_gdc_layer_disable(int layer_no)
Disable layer.
HAL_GDC_RGBA5551
@ HAL_GDC_RGBA5551
RGBA5551.
Definition: hal_gdc.h:141
hal_gdc_clkctrl_cg_clk_swap
@ hal_gdc_clkctrl_cg_clk_swap
Pixel generation and format clock swap.
Definition: hal_gdc.h:331
HAL_GDC_LUT8
@ HAL_GDC_LUT8
LUT8.
Definition: hal_gdc.h:205
hal_gdc_cursor_enable
void hal_gdc_cursor_enable(int enable)
Enable or Disable fixed cursor.
HAL_GDC_DISABLE
@ HAL_GDC_DISABLE
DISABLE.
Definition: hal_gdc.h:168
HAL_GDC_ABGR8888
@ HAL_GDC_ABGR8888
ABGR8888.
Definition: hal_gdc.h:142
HAL_GDC_LAYER_GAMMALUT_EN
@ HAL_GDC_LAYER_GAMMALUT_EN
Enable Gamma Look Up Table.
Definition: hal_gdc.h:96
HAL_GDC_LVDS_ISP68
@ HAL_GDC_LVDS_ISP68
LVDS_ISP68.
Definition: hal_gdc.h:200
HAL_GDC_MODULATE_A
@ HAL_GDC_MODULATE_A
Modulate Alpha.
Definition: hal_gdc.h:94
HAL_GDC_CFG_L2_ENABLED
@ HAL_GDC_CFG_L2_ENABLED
Layer 2 enabled.
Definition: hal_gdc.h:229
__hal_gdc_layer_t::sizex
uint32_t sizex
Size X.
Definition: hal_gdc.h:369
HAL_GDC_DITHER16
@ HAL_GDC_DITHER16
DITHER 16-bit.
Definition: hal_gdc.h:174
hal_gdc_clkctrl_cg_t
hal_gdc_clkctrl_cg_t
DC clock cg control definition.
Definition: hal_gdc.h:302
hal_gdc_blend_factors_t
hal_gdc_blend_factors_t
Layer blending factor definition.
Definition: hal_gdc.h:103
DC_STATUS_dbi_pending_data
@ DC_STATUS_dbi_pending_data
pending pixel data
Definition: hal_gdc.h:268
HAL_GDC_EN_L2PIX
@ HAL_GDC_EN_L2PIX
layer 2 pixel clock clock-gater bypass
Definition: hal_gdc.h:294
DC_STATUS_rsrvd_8
@ DC_STATUS_rsrvd_8
Reserved bit.
Definition: hal_gdc.h:255
hal_gdc_clkctrl_cg_rsrvd_4
@ hal_gdc_clkctrl_cg_rsrvd_4
Reserved bit.
Definition: hal_gdc.h:329
__hal_gdc_layer_t::startx
int32_t startx
Start X.
Definition: hal_gdc.h:367
HAL_GDC_CFG_L3_ENABLED
@ HAL_GDC_CFG_L3_ENABLED
Layer 3 enabled.
Definition: hal_gdc.h:233
hal_gdc_clkctrl_cg_rsrvd_9
@ hal_gdc_clkctrl_cg_rsrvd_9
Reserved bit.
Definition: hal_gdc.h:324
HAL_GDC_CFG_FIXED_CURSOR
@ HAL_GDC_CFG_FIXED_CURSOR
Fixed Cursor enabled.
Definition: hal_gdc.h:214
DC_STATUS_dbi_pending_trans
@ DC_STATUS_dbi_pending_trans
pending command/data transaction
Definition: hal_gdc.h:266
HAL_GDC_LVDS_OFF
@ HAL_GDC_LVDS_OFF
LVDS_OFF.
Definition: hal_gdc.h:193
HAL_GDC_CFG_L3_BLENDER
@ HAL_GDC_CFG_L3_BLENDER
Layer 3 has blender.
Definition: hal_gdc.h:234
HAL_GDC_CFG_L1_BLENDER
@ HAL_GDC_CFG_L1_BLENDER
Layer 1 has blender.
Definition: hal_gdc.h:226
HAL_GDC_P_RGB3_16B2
@ HAL_GDC_P_RGB3_16B2
P_RGB3.
Definition: hal_gdc.h:187
hal_gdc_get_layer_gamma_lut
int hal_gdc_get_layer_gamma_lut(int layer, int index)
Get an entry in the lut8 Palette Gamma table for a layer.
HAL_GDC_YUYV
@ HAL_GDC_YUYV
YUYV.
Definition: hal_gdc.h:149
HAL_GDC_S_RGBX4
@ HAL_GDC_S_RGBX4
S_RGBX4.
Definition: hal_gdc.h:197
DC_STATUS_te
@ DC_STATUS_te
tearing
Definition: hal_gdc.h:271
HAL_GDC_BL_SRC_ATOP
@ HAL_GDC_BL_SRC_ATOP
Sa * Da + Da * (1 - Sa)
Definition: hal_gdc.h:130
HAL_GDC_CFG_L2_SCALER
@ HAL_GDC_CFG_L2_SCALER
Layer 2 has scaler.
Definition: hal_gdc.h:231
HAL_GDC_JDIMIP
@ HAL_GDC_JDIMIP
JDIMIP.
Definition: hal_gdc.h:204
HAL_GDC_CFG_L1_GAMMA
@ HAL_GDC_CFG_L1_GAMMA
Layer 1 has gamma LUT.
Definition: hal_gdc.h:228
DC_STATUS_sticky
@ DC_STATUS_sticky
underflow flag
Definition: hal_gdc.h:272
HAL_GDC_INVPIXCLK
@ HAL_GDC_INVPIXCLK
INVPIXCLK.
Definition: hal_gdc.h:177
__hal_gdc_display_t::resx
uint32_t resx
Resolution X.
Definition: hal_gdc.h:347
HAL_GDC_RGB332
@ HAL_GDC_RGB332
RGB332.
Definition: hal_gdc.h:143
HAL_GDC_SCANDOUBLE
@ HAL_GDC_SCANDOUBLE
SCANDOUBLE.
Definition: hal_gdc.h:194
HAL_GDC_BL_SIMPLE
@ HAL_GDC_BL_SIMPLE
Sa * Sa + Da * (1 - Sa)
Definition: hal_gdc.h:121
HAL_GDC_TLYUV420
@ HAL_GDC_TLYUV420
TLYUV420.
Definition: hal_gdc.h:155
HAL_GDC_BF_SRCGBLALPHA
@ HAL_GDC_BF_SRCGBLALPHA
Alpha Source And Alpha Global.
Definition: hal_gdc.h:108
__hal_gdc_layer_t::sizey
uint32_t sizey
Size Y.
Definition: hal_gdc.h:370
hal_gdc_check_config
unsigned char hal_gdc_check_config(hal_gdc_config_t flag)
Check whether hal_gdc supports a specific characteristic.
hal_gdc_set_layer_gamma_lut
void hal_gdc_set_layer_gamma_lut(int layer, int index, int colour)
Set the physical address of a layer.
HAL_GDC_CFG_HiQ_YUV
@ HAL_GDC_CFG_HiQ_YUV
High Quality YUV converted enabled.
Definition: hal_gdc.h:218
HAL_GDC_L8
@ HAL_GDC_L8
L8.
Definition: hal_gdc.h:146
DC_STATUS_rsrvd_13
@ DC_STATUS_rsrvd_13
Reserved bit.
Definition: hal_gdc.h:260
hal_gdc_clkctrl_cg_rsrvd_21
@ hal_gdc_clkctrl_cg_rsrvd_21
Reserved bit.
Definition: hal_gdc.h:312
hal_gdc_layer_ctrl_t
hal_gdc_layer_ctrl_t
Layer control definition.
Definition: hal_gdc.h:90
HAL_GDC_BL_ADD
@ HAL_GDC_BL_ADD
Sa + Da.
Definition: hal_gdc.h:132
hal_gdc_clkctrl_cg_rsrvd_11
@ hal_gdc_clkctrl_cg_rsrvd_11
Reserved bit.
Definition: hal_gdc.h:322
HAL_GDC_CFG_L0_ENABLED
@ HAL_GDC_CFG_L0_ENABLED
Layer 0 enabled.
Definition: hal_gdc.h:221
hal_gdc_set_mode
void hal_gdc_set_mode(int mode)
Set operation mode.
HAL_GDC_DITHER
@ HAL_GDC_DITHER
DITHER 18-bit.
Definition: hal_gdc.h:173
HAL_GDC_V_YUV420
@ HAL_GDC_V_YUV420
V_YUV420.
Definition: hal_gdc.h:154
HAL_GDC_TESTMODE
@ HAL_GDC_TESTMODE
TESTMODE.
Definition: hal_gdc.h:195
HAL_GDC_ARGB4444
@ HAL_GDC_ARGB4444
ARGB4444.
Definition: hal_gdc.h:160
hal_gdc_clkctrl_cg_rsrvd_7
@ hal_gdc_clkctrl_cg_rsrvd_7
Reserved bit.
Definition: hal_gdc.h:326
hal_gdc_set_palette
void hal_gdc_set_palette(uint32_t index, uint32_t colour)
Sets an entry in the lut8 Palatte Gamma table.