Macros
QSPI-XIP Private Macros
Peripheral Driver » HAL Driver » QSPI » Defines
Collaboration diagram for QSPI-XIP Private Macros:

## Macros
#define | IS_QSPI_CONC_XIP_SIOO_MODE(_SIOO_)
| Check if QSPI.XIP SIOO Mode is valid. More...
#define | IS_QSPI_CONC_XIP_DFS(_DFS_)
| Check if QSPI.XIP DFS Value is valid. More...
#define | IS_QSPI_CONC_XIP_DFS_HC_EN(_HC_EN_)
| Check if QSPI.XIP DFS_HC Switch Value is valid. More...
#define | IS_QSPI_CONC_XIP_INST_EN(_INST_EN_)
| Check if QSPI.XIP inst Switch is valid. More...
#define | IS_QSPI_CONC_XIP_INST_SIZE(_INST_SIZE_)
| Check if QSPI.XIP inst size is valid. More...
#define | IS_QSPI_CONC_XIP_INST(_INST_) ((_INST_) <= 0xFFFF )
| Check if QSPI.XIP inst is valid. More...
#define | IS_QSPI_CONC_XIP_ADDR_SIZE(_ADDR_SIZE_)
| Check if QSPI.XIP Address Size is valid. More...
#define | IS_QSPI_CONC_INST_ADDR_XFER_FORMAT(_FORMAT_)
| Check if QSPI.XIP Addr Xfer format is valid. More...
#define | IS_QSPI_CONC_XIP_MODE_BITS_EN(_MD_EN_)
| Check if QSPI.XIP Mode bits Switch is valid. More...
#define | IS_QSPI_CONC_XIP_MODE_BITS_SIZE(_MD_SIZE_)
| Check if QSPI.XIP Mode Bits size is valid. More...
#define | IS_QSPI_CONC_XIP_MODE_BITS(_MD_BITS_) ( (_MD_BITS_) <= 0xFFFF)
| Check if QSPI.XIP Mode Bits is valid. More...
#define | IS_QSPI_CONC_XIP_DUMMY_CYCLES(__DCY__) ( (__DCY__) <= 31)
| Check if QSPI.XIP dummy cycles is valid. More...
#define | IS_QSPI_CONC_XIP_DATA_FRF(_XIP_FRF_)
| Check if QSPI.XIP frame format is valid. More...
#define | IS_QSPI_CONC_XIP_PREFETCH_EN(_PREFETCH_EN_)
| Check if QSPI.XIP prefetch switch is valid. More...
#define | IS_QSPI_CONC_XIP_CONT_XFER_EN(_CONT_XFER_EN_)
| Check if QSPI.XIP cont xfer switch is valid. More...
#define | IS_QSPI_CONC_XIP_CONT_XFER_TOC(_TOC_) ( (_TOC_) <= 0xFF)
| Check if QSPI.XIP timeout count of cont xfer is valid. More...
#define | IS_QSPI_CONC_XIP_ENDIAN_MODE(_MODE_)
| Check if QSPI.XIP Data endian Mode is valid. More...

## Detailed Description

## Macro Definition Documentation

## ◆ IS_QSPI_CONC_INST_ADDR_XFER_FORMAT

#define IS_QSPI_CONC_INST_ADDR_XFER_FORMAT | ( |  | _FORMAT_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI == (_FORMAT_)) || \
(QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF == (_FORMAT_)) || \
(QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF == (_FORMAT_)) )

Check if QSPI.XIP Addr Xfer format is valid.

Parameters

  <em>FORMAT</em> | QSPI.XIP Addr Xfer format.

Return values

  SET | (FORMAT is valid) or RESET (FORMAT is invalid)

Definition at line 1011 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_ADDR_SIZE

#define IS_QSPI_CONC_XIP_ADDR_SIZE | ( |  | _ADDR_SIZE_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT == (_ADDR_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT == (_ADDR_SIZE_) ) )

Check if QSPI.XIP Address Size is valid.

Parameters

  <em>ADDR_SIZE</em> | QSPI.XIP Address Size.

Return values

  SET | (ADDR_SIZE is valid) or RESET (ADDR_SIZE is invalid)

Definition at line 990 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_CONT_XFER_EN

#define IS_QSPI_CONC_XIP_CONT_XFER_EN | ( |  | _CONT_XFER_EN_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE == (_CONT_XFER_EN_)) || \
(QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE == (_CONT_XFER_EN_)) )

Check if QSPI.XIP cont xfer switch is valid.

Parameters

  <em>CONT_XFER_EN</em> | QSPI.XIP cont xfer switch.

Return values

  SET | (CONT_XFER_EN is valid) or RESET (CONT_XFER_EN is invalid)

Definition at line 1061 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_CONT_XFER_TOC

#define IS_QSPI_CONC_XIP_CONT_XFER_TOC | ( |  | _TOC_ | ) | ( (_TOC_) <= 0xFF)

Check if QSPI.XIP timeout count of cont xfer is valid.

Parameters

  <em>TOC</em> | QSPI.XIP timeout count of cont xfer.

Return values

  SET | (TOC is valid) or RESET (TOC is invalid)

Definition at line 1068 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_DATA_FRF

#define IS_QSPI_CONC_XIP_DATA_FRF | ( |  | _XIP_FRF_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_FRF_DUAL_SPI == (_XIP_FRF_)) || \
(QSPI_CONCURRENT_XIP_FRF_QUAD_SPI == (_XIP_FRF_)) )

Check if QSPI.XIP frame format is valid.

Parameters

  <em>XIP_FRF</em> | QSPI.XIP frame format.

Return values

  SET | (XIP_FRF is valid) or RESET (XIP_FRF is invalid)

Definition at line 1047 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_DFS

#define IS_QSPI_CONC_XIP_DFS | ( |  | _DFS_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_DFS_BYTE == (_DFS_)) || \
(QSPI_CONCURRENT_XIP_DFS_HALFWORD == (_DFS_)) || \
(QSPI_CONCURRENT_XIP_DFS_WORD == (_DFS_)) )

Check if QSPI.XIP DFS Value is valid.

Parameters

  <em>DFS</em> | QSPI.XIP DFS Value

Return values

  SET | (DFS is valid) or RESET (DFS is invalid)

Definition at line 953 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_DFS_HC_EN

#define IS_QSPI_CONC_XIP_DFS_HC_EN | ( |  | _HC_EN_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE == (_HC_EN_)) || \
(QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE == (_HC_EN_)) )

Check if QSPI.XIP DFS_HC Switch Value is valid.

Parameters

  <em>HC_EN</em> | QSPI.XIP DFS Hardcode Switch.

Return values

  SET | (HC_EN is valid) or RESET (HC_EN is invalid)

Definition at line 961 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_DUMMY_CYCLES

#define IS_QSPI_CONC_XIP_DUMMY_CYCLES | ( |  | __DCY__ | ) | ( (__DCY__) <= 31)

Check if QSPI.XIP dummy cycles is valid.

Parameters

  <strong>DCY</strong> | QSPI.XIPdummy cycles.

Return values

  SET | (DCY is valid) or RESET (DCY is invalid)

Definition at line 1041 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_ENDIAN_MODE

#define IS_QSPI_CONC_XIP_ENDIAN_MODE | ( |  | _MODE_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 == (_MODE_)) || \
(QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 == (_MODE_)) || \
(QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 == (_MODE_)) )

Check if QSPI.XIP Data endian Mode is valid.

Parameters

  <em>MODE</em> | QSPI.XIP Data endian Mode.

Return values

  SET | (MODE is valid) or RESET (MODE is invalid)

Definition at line 1074 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_INST

#define IS_QSPI_CONC_XIP_INST | ( |  | _INST_ | ) | ((_INST_) <= 0xFFFF )

Check if QSPI.XIP inst is valid.

Parameters

  <em>INST</em> | QSPI.XIP inst.

Return values

  SET | (INST is valid) or RESET (INST is invalid)

Definition at line 984 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_INST_EN

#define IS_QSPI_CONC_XIP_INST_EN | ( |  | _INST_EN_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_INST_ENABLE == (_INST_EN_)) || \
(QSPI_CONCURRENT_XIP_INST_DISABLE == (_INST_EN_)) )

Check if QSPI.XIP inst Switch is valid.

Parameters

  <em>INST_EN</em> | QSPI.XIP inst en/dis.

Return values

  SET | (INST_EN is valid) or RESET (INST_EN is invalid)

Definition at line 968 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_INST_SIZE

#define IS_QSPI_CONC_XIP_INST_SIZE | ( |  | _INST_SIZE_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_INSTSIZE_0BIT == (_INST_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_INSTSIZE_4BIT == (_INST_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_INSTSIZE_8BIT == (_INST_SIZE_) ) || \
(QSPI_CONCURRENT_XIP_INSTSIZE_16BIT == (_INST_SIZE_) ) )

Check if QSPI.XIP inst size is valid.

Parameters

  <em>INST_SIZE</em> | QSPI.XIP inst size.

Return values

  SET | (INST_SIZE is valid) or RESET (INST_SIZE is invalid)

Definition at line 975 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_MODE_BITS

#define IS_QSPI_CONC_XIP_MODE_BITS | ( |  | _MD_BITS_ | ) | ( (_MD_BITS_) <= 0xFFFF)

Check if QSPI.XIP Mode Bits is valid.

Parameters

  <em>MD_BITS</em> | QSPI.XIP Mode Bits.

Return values

  SET | (MD_BITS is valid) or RESET (MD_BITS is invalid)

Definition at line 1035 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_MODE_BITS_EN

#define IS_QSPI_CONC_XIP_MODE_BITS_EN | ( |  | _MD_EN_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE == (_MD_EN_) ) || \
(QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE == (_MD_EN_) ))

Check if QSPI.XIP Mode bits Switch is valid.

Parameters

  <em>MD_EN</em> | QSPI.XIP Mode bits Switch.

Return values

  SET | (MD_EN is valid) or RESET (MD_EN is invalid)

Definition at line 1019 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_MODE_BITS_SIZE

#define IS_QSPI_CONC_XIP_MODE_BITS_SIZE | ( |  | _MD_SIZE_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_MBL_2 == (_MD_SIZE_)) || \
(QSPI_CONCURRENT_XIP_MBL_4 == (_MD_SIZE_)) || \
(QSPI_CONCURRENT_XIP_MBL_8 == (_MD_SIZE_)) || \
(QSPI_CONCURRENT_XIP_MBL_16 == (_MD_SIZE_)) )

Check if QSPI.XIP Mode Bits size is valid.

Parameters

  <em>MD_SIZE</em> | QSPI.XIP Mode Bits size.

Return values

  SET | (MD_SIZE is valid) or RESET (MD_SIZE is invalid)

Definition at line 1026 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_PREFETCH_EN

#define IS_QSPI_CONC_XIP_PREFETCH_EN | ( |  | _PREFETCH_EN_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_PREFETCH_ENABLE == (_PREFETCH_EN_)) || \
(QSPI_CONCURRENT_XIP_PREFETCH_DISABLE == (_PREFETCH_EN_)) )

Check if QSPI.XIP prefetch switch is valid.

Parameters

  <em>PREFETCH_EN</em> | QSPI.XIP prefetch switch.

Return values

  SET | (PREFETCH_EN is valid) or RESET (PREFETCH_EN is invalid)

Definition at line 1054 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CONC_XIP_SIOO_MODE

#define IS_QSPI_CONC_XIP_SIOO_MODE | ( |  | _SIOO_ | ) |

Value:
( (QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS == (_SIOO_)) || \
(QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS == (_SIOO_)) )

Check if QSPI.XIP SIOO Mode is valid.

Parameters

  <em>SIOO</em> | QSPI.XIP Data Mode.

Return values

  SET | (SIOO is valid) or RESET (SIOO is invalid)

Definition at line 946 of file gr55xx_hal_qspi.h.

QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
#define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
Instruction and address are sent in SPI mode.
Definition: gr55xx_hal_qspi.h:630
QSPI_CONCURRENT_XIP_MBL_2
#define QSPI_CONCURRENT_XIP_MBL_2
mode bits length equals to 2 bit.
Definition: gr55xx_hal_qspi.h:591
QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS
#define QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS
Definition: gr55xx_hal_qspi.h:690
QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE
#define QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE
Enable DFS Hardcode.
Definition: gr55xx_hal_qspi.h:682
QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
Address length for QSPI XIP transfer: 4 bits.
Definition: gr55xx_hal_qspi.h:610
QSPI_CONCURRENT_XIP_INST_ENABLE
#define QSPI_CONCURRENT_XIP_INST_ENABLE
Enable Instruction phase.
Definition: gr55xx_hal_qspi.h:668
QSPI_CONCURRENT_XIP_MBL_16
#define QSPI_CONCURRENT_XIP_MBL_16
mode bits length equals to 16 bit.
Definition: gr55xx_hal_qspi.h:594
QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
#define QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
Disable Bits phase.
Definition: gr55xx_hal_qspi.h:676
QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
#define QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
Disable Cont trasfer.
Definition: gr55xx_hal_qspi.h:662
QSPI_CONCURRENT_XIP_PREFETCH_ENABLE
#define QSPI_CONCURRENT_XIP_PREFETCH_ENABLE
Enable Prefetch.
Definition: gr55xx_hal_qspi.h:654
QSPI_CONCURRENT_XIP_DFS_BYTE
#define QSPI_CONCURRENT_XIP_DFS_BYTE
Set data frame size as byte.
Definition: gr55xx_hal_qspi.h:583
QSPI_CONCURRENT_XIP_DFS_HALFWORD
#define QSPI_CONCURRENT_XIP_DFS_HALFWORD
Set data frame size as halfword.
Definition: gr55xx_hal_qspi.h:584
QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
Address length for QSPI XIP transfer: 60 bits.
Definition: gr55xx_hal_qspi.h:624
QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
Address length for QSPI XIP transfer: 36 bits.
Definition: gr55xx_hal_qspi.h:618
QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
Address length for QSPI XIP transfer: 0 bits.
Definition: gr55xx_hal_qspi.h:609
QSPI_CONCURRENT_XIP_INST_DISABLE
#define QSPI_CONCURRENT_XIP_INST_DISABLE
Disable Instruction phase.
Definition: gr55xx_hal_qspi.h:669
QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
#define QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
Re-order the read data as [23:16], [31:24], [7:0], [15:8].
Definition: gr55xx_hal_qspi.h:570
QSPI_CONCURRENT_XIP_MBL_4
#define QSPI_CONCURRENT_XIP_MBL_4
mode bits length equals to 4 bit.
Definition: gr55xx_hal_qspi.h:592
QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
Address length for QSPI XIP transfer: 24 bits.
Definition: gr55xx_hal_qspi.h:615
QSPI_CONCURRENT_XIP_DFS_WORD
#define QSPI_CONCURRENT_XIP_DFS_WORD
Set data frame size as word.
Definition: gr55xx_hal_qspi.h:585
QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
#define QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
instruction size equals 4bits
Definition: gr55xx_hal_qspi.h:601
QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
#define QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
SPI Frame format : QUAD.
Definition: gr55xx_hal_qspi.h:640
QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
Address length for QSPI XIP transfer: 32 bits.
Definition: gr55xx_hal_qspi.h:617
QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE
#define QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE
Enable Cont trasfer.
Definition: gr55xx_hal_qspi.h:661
QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE
#define QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE
Enable Bits phase.
Definition: gr55xx_hal_qspi.h:675
QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
Address length for QSPI XIP transfer: 12 bits.
Definition: gr55xx_hal_qspi.h:612
QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
#define QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode.
Definition: gr55xx_hal_qspi.h:631
QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
Address length for QSPI XIP transfer: 44 bits.
Definition: gr55xx_hal_qspi.h:620
QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
Address length for QSPI XIP transfer: 8 bits.
Definition: gr55xx_hal_qspi.h:611
QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS
#define QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS
Definition: gr55xx_hal_qspi.h:689
QSPI_CONCURRENT_XIP_MBL_8
#define QSPI_CONCURRENT_XIP_MBL_8
mode bits length equals to 8 bit.
Definition: gr55xx_hal_qspi.h:593
QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
#define QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
Default endian order from AHB.
Definition: gr55xx_hal_qspi.h:569
QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
#define QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
SPI Frame format : DUAL.
Definition: gr55xx_hal_qspi.h:639
QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
#define QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
instruction size equals 8bits
Definition: gr55xx_hal_qspi.h:602
QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
#define QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
instruction size equals 16bits
Definition: gr55xx_hal_qspi.h:603
QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
#define QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
no instruction
Definition: gr55xx_hal_qspi.h:600
QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
Address length for QSPI XIP transfer: 28 bits.
Definition: gr55xx_hal_qspi.h:616
QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
Address length for QSPI XIP transfer: 52 bits.
Definition: gr55xx_hal_qspi.h:622
QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
#define QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
Disable Prefetch.
Definition: gr55xx_hal_qspi.h:655
QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
#define QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
Disable DFS Hardcode.
Definition: gr55xx_hal_qspi.h:683
QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
#define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
Instruction and address are sent in Daul/Quad SPI mode.
Definition: gr55xx_hal_qspi.h:632
QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
Address length for QSPI XIP transfer: 48 bits.
Definition: gr55xx_hal_qspi.h:621
QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
#define QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
Re-order the read data as [7:0], [15:8], [23:16], [31:24].
Definition: gr55xx_hal_qspi.h:571
QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
Address length for QSPI XIP transfer: 56 bits.
Definition: gr55xx_hal_qspi.h:623
QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
Address length for QSPI XIP transfer: 40 bits.
Definition: gr55xx_hal_qspi.h:619
QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
Address length for QSPI XIP transfer: 16 bits.
Definition: gr55xx_hal_qspi.h:613
QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
#define QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
Address length for QSPI XIP transfer: 20 bits.
Definition: gr55xx_hal_qspi.h:614