gr55xx_ll_rtc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_rtc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CALENDAR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_RTC RTC
47 * @brief RTC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_RTC_H__
53 #define __GR55XX_LL_RTC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 /**
63 * @defgroup LL_RTC_MACRO Defines
64 * @{
65 */
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup LL_RTC_Exported_Constants RTC Exported Constants
68 * @{
69 */
70 /** @defgroup LL_RTC_EC_CLOCK_DIV Clock divider
71 * @{
72 */
73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U) /**< Select SLP_CLK */
74 #define LL_RTC_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
75 #define LL_RTC_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
76 #define LL_RTC_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
77 #define LL_RTC_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
78 #define LL_RTC_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos) /**< Select 1/64 divider */
79 #define LL_RTC_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos) /**< Select 1/128 divider */
80 #define LL_RTC_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos) /**< Select 1/256 divider */
81 /** @} */
82
83 /** @defgroup LL_RTC_TIMER_CLK_SEL RTC Timer clock select defines
84 * @{
85 */
86 #define LL_RTC_TIMER_CLK_SEL_RNG (0x0U << RTC_CLK_SEL_Pos) /**< Select RNG clcok source */
87 #define LL_RTC_TIMER_CLK_SEL_XO (0x1U << RTC_CLK_SEL_Pos) /**< Select XO clcok source */
88 #define LL_RTC_TIMER_CLK_SEL_RNG2 (0x2U << RTC_CLK_SEL_Pos) /**< Select RNG2 clcok source */
89 #define LL_RTC_TIMER_CLK_SEL_RTC (0x3U << RTC_CLK_SEL_Pos) /**< Select RTC clcok source */
90 /** @} */
91
92 /** @defgroup LL_RTC_TIMER_PERIODIC_SEL RTC Periodic timer select defines
93 * @{
94 */
95 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U) /**< Select periodic alarm one-time */
96 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U) /**< Select periodic alarm auto-reload */
97 /** @} */
98
99 /** @} */
100
101 /** @defgroup LL_RTC_Exported_Macros RTC Exported Macros
102 * @{
103 */
104 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
105 RTC_CFG0_ALARM_EN | \
106 RTC_CFG0_TICK_EN | \
107 RTC_CFG0_TICK_MDOE))
108
109 /** @} */
110
111 /** @} */
112
113 /* Exported functions --------------------------------------------------------*/
114 /** @defgroup LL_RTC_DRIVER_FUNCTIONS Functions
115 * @{
116 */
117
118 /** @defgroup LL_RTC_EF_Configuration Configuration functions
119 * @{
120 */
121 /**
122 * @brief Set the RTC Timer clock
123 *
124 * Register|BitsName
125 * --------|--------
126 * RTC_CLK | RTC_timer_clk_sel
127
128 * @param RTCx
129 * @param value This parameter can be a one of the following values:
130 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG
131 * @arg @ref LL_RTC_TIMER_CLK_SEL_XO
132 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG2
133 * @arg @ref LL_RTC_TIMER_CLK_SEL_RTC
134 * @retval None
135 */
136 __STATIC_INLINE void ll_rtc_timer_set_clk(rtc_regs_t* RTCx,uint32_t value)
137 {
138 MODIFY_REG(RTCx->CLK, RTC_CLK_SEL, value);
139 }
140
141 /**
142 * @brief Get the RTC Timer clock
143 *
144 * Register|BitsName
145 * --------|--------
146 * RTC_CLK | RTC_timer_clk_sel
147
148 * @retval RTC Timer clock source,the value can be the one of the following:
149 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG
150 * @arg @ref LL_RTC_TIMER_CLK_SEL_XO
151 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG2
152 * @arg @ref LL_RTC_TIMER_CLK_SEL_RTC
153 */
154 __STATIC_INLINE uint32_t ll_rtc1_timer_get_clk(rtc_regs_t* RTCx)
155 {
156 return (READ_BITS(RTCx->CLK, RTC_CLK_SEL));
157 }
158
159 /**
160 * @brief Enable RTC counter.
161 *
162 * Register|BitsName
163 * --------|--------
164 * RTC_CFG0 | EN
165 *
166 *
167 */
168 __STATIC_INLINE void ll_rtc_enable(rtc_regs_t* RTCx)
169 {
170 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
171 }
172
173 /**
174 * @brief Disable RTC counter.
175 *
176 * Register|BitsName
177 * --------|--------
178 * RTC_CFG0 | EN
179 *
180 * @retval None
181 */
182 __STATIC_INLINE void ll_rtc_disable(rtc_regs_t* RTCx)
183 {
184 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
185 }
186
187 /**
188 * @brief Check if the RTC peripheral is enabled or disabled.
189 *
190 * Register|BitsName
191 * --------|--------
192 * RTC_CFG0 | EN
193 *
194 * @retval State of bit (1 or 0).
195 */
196 __STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t* RTCx)
197 {
198 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
199 }
200
201 /**
202 * @brief Reloads RTC counter.
203 *
204 * Register|BitsName
205 * --------|--------
206 * RTC_TIMER_W | TIMER_VALUE
207 *
208 * @retval None
209 */
210 __STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t* RTCx, uint32_t counter)
211 {
212 WRITE_REG(RTCx->TIMER_W, counter);
213 }
214
215 /**
216 * @brief Reloads RTC counter and request.
217 *
218 * Register|BitsName
219 * --------|--------
220 * RTC_TIMER_W | TIMER_VALUE
221 * RTC_CFG0 | VAL_LOAD
222 *
223 * @retval None
224 */
225 __STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t* RTCx, uint32_t start_value)
226 {
227 WRITE_REG(RTCx->TIMER_W, start_value);
228 SET_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
229 }
230
231 __STATIC_INLINE void ll_rtc_clear_counter_set(rtc_regs_t* RTCx)
232 {
233 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
234 }
235
236 /**
237 * @brief Reloads RTC alarm.
238 *
239 * Register|BitsName
240 * --------|--------
241 * RTC_TIMER_W | ALARM_VAL_LOAD
242 *
243 * @retval None
244 */
245 //__STATIC_INLINE void ll_rtc_set_alarm_value(rtc_regs_t* RTCx, uint32_t value)
246 //{
247 // WRITE_REG(RTCx->ALARM_W, value);
248 // CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
249 // SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET);
250 //}
251
252 /**
253 * @brief Reloads RTC alarm and request.
254 *
255 * Register|BitsName
256 * --------|--------
257 * RTC_ALARM_W | ALARM_VAL_LOAD
258 * RTC_CFG0 | ALARM_VALUE
259 *
260 */
261 __STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t* RTCx, uint32_t alarm_value)
262 {
263 WRITE_REG(RTCx->ALARM_W, alarm_value);
264 SET_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
265 }
266
267 /**
268 * @brief Reloads RTC perd_alarm.
269 *
270 * Register|BitsName
271 * --------|--------
272 * RTC_TIMER_W | ALARM_VAL_LOAD
273 *
274 * @retval None
275 */
276 __STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t* RTCx, uint32_t tick)
277 {
278 WRITE_REG(RTCx->TICK_W, tick);
279 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
280 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET);
281 }
282
283 /**
284 * @brief Read the RTC counter config value.
285 *
286 * Register|BitsName
287 * --------|--------
288 * RTC_TIMER_W | TIMER_VAL_READ
289 *
290 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
291 */
292 __STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t* RTCx)
293 {
294 return (uint32_t)READ_REG(RTCx->TIMER_W);
295 }
296
297 /**
298 * @brief Read the RTC counter current value.
299 *
300 * Register|BitsName
301 * --------|--------
302 * RTC_TIMER_R | TIMER_VAL_READ
303 *
304 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
305 */
306 __STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t* RTCx)
307 {
308 return (uint32_t)READ_REG(RTCx->TIMER_R);
309 }
310
311 /**
312 * @brief Read the RTC counter config alarm value.
313 *
314 * Register|BitsName
315 * --------|--------
316 * RTC_ALARM_W | CAL_ALARM
317 *
318 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
319 */
320 __STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t* RTCx)
321 {
322 return (uint32_t)READ_REG(RTCx->ALARM_W);
323 }
324
325 /**
326 * @brief Read the RTC counter current alarm value.
327 *
328 * Register|BitsName
329 * --------|--------
330 * RTC_ALARM_R | CAL_ALARM
331 *
332 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
333 */
334 __STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t* RTCx)
335 {
336 return (uint32_t)READ_REG(RTCx->ALARM_R);
337 }
338
339 __STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t* RTCx)
340 {
341 return (uint32_t)READ_REG(RTCx->TICK_W);
342 }
343
344 __STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t* RTCx)
345 {
346 return (uint32_t)READ_REG(RTCx->TICK_R);
347 }
348
349 /**
350 * @brief Get the RTC wrap-around value.
351 * @note The value should be read multiple times until get the same value in at least two reads.
352 *
353 * Register|BitsName
354 * --------|--------
355 * RTC_STAT | WRAP_CNT
356 *
357 * @retval Value between Min_Data=0 and Max_Data=0xF
358 */
359 __STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t* RTCx)
360 {
361 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
362 }
363
364 /**
365 * @brief The RTC is busy.
366 *
367 * Register|BitsName
368 * --------|--------
369 * RTC_STAT | BUSY
370 *
371 * @retval Value between Min_Data=0 and Max_Data=0xF
372 */
373 __STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t* RTCx)
374 {
375 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
376 }
377
378 /**
379 * @brief The RTC is running.
380 *
381 * Register|BitsName
382 * --------|--------
383 * RTC_STAT | RUNNING
384 *
385 * @retval Value between Min_Data=0 and Max_Data=0xF
386 */
387 __STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t* RTCx)
388 {
389 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
390 }
391
392 /**
393 * @brief CLear RTC wrap.
394 *
395 * Register|BitsName
396 * --------|--------
397 * RTC_CFG0 | Wrap counter clear
398 *
399 * @retval None
400 */
401
402 __STATIC_INLINE void ll_rtc_clear_wrap(rtc_regs_t* RTCx)
403 {
404 SET_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
405 }
406
407 __STATIC_INLINE void ll_rtc_clear_wrap_set(rtc_regs_t* RTCx)
408 {
409 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
410 }
411
412 /**
413 * @brief Select the RTC clock divider.
414 *
415 * Register|BitsName
416 * --------|--------
417 * RTC_CFG1 | CLK_SEL
418 *
419 * @param RTCx
420 * @param div This parameter can be one of the following values:
421 * @arg @ref LL_RTC_DIV_NONE
422 * @arg @ref LL_RTC_DIV_2
423 * @arg @ref LL_RTC_DIV_4
424 * @arg @ref LL_RTC_DIV_8
425 * @arg @ref LL_RTC_DIV_16
426 * @arg @ref LL_RTC_DIV_32
427 * @arg @ref LL_RTC_DIV_64
428 * @arg @ref LL_RTC_DIV_128
429 * @retval None
430 */
431 __STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t* RTCx, uint32_t div)
432 {
433 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
434 }
435
436 /**
437 * @brief Enable RTC alarm.
438 *
439 * Register|BitsName
440 * --------|--------
441 * RTC_TIMER_CTL | ALARM_EN
442 *
443 * @retval None
444 */
445 __STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t* RTCx,uint32_t value)
446 {
447 WRITE_REG(RTCx->ALARM_W, value);
448 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET);
449 }
450
451 __STATIC_INLINE void ll_rtc_clear_alarm_set(rtc_regs_t* RTCx)
452 {
453 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
454 }
455
456 /**
457 * @brief Enable RTC alarm interrupt.
458 *
459 * Register|BitsName
460 * --------|--------
461 * RTC_TIMER_CTL | ALARM_INT_EN
462 *
463 * @retval None
464 */
465 __STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t* RTCx)
466 {
467 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
468 }
469
470 /**
471 * @brief Disable RTC alarm.
472 *
473 * Register|BitsName
474 * --------|--------
475 * RTC_TIMER_CTL | ALARM_DISBALE
476 *
477 * @retval None
478 */
479 __STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t* RTCx)
480 {
481 CLEAR_BITS(RTCx->CFG0,RTC_CFG0_ALARM_SET | RTC_CFG0_ALARM_EN);
482 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
483 }
484
485 /**
486 * @brief Disable RTC alarm interrupt.
487 *
488 * Register|BitsName
489 * --------|--------
490 * RTC_INT_EN | ALARM_INT_EN
491 *
492 * @retval None
493 */
494 __STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t* RTCx)
495 {
496 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
497 }
498
499 /**
500 * @brief Check if the RTC alarm interrupt is enabled or disabled.
501 *
502 * Register|BitsName
503 * --------|--------
504 * RTC_TIMER_CTL | ALARM_INT_EN
505 *
506 * @retval State of bit (1 or 0).
507 */
508 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t* RTCx)
509 {
510 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
511 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
512 }
513
514 /**
515 * @brief Set RTCx tick mode.
516 *
517 * Register|BitsName
518 * --------|--------
519 * RTCx_TIMER_CTL | TICK_EN
520 *
521 * @retval None
522 */
523 __STATIC_INLINE void ll_rtc_enable_tick(rtc_regs_t* RTCx)
524 {
525 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
526 SET_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
527 }
528
529 /**
530 * @brief Set RTCx alarm_mode.
531 *
532 * Register|BitsName
533 * --------|--------
534 * RTCx_TIMER_CTL | TICK_EN
535 *
536 * @param RTCx
537 * @param tick_mode This parameter can be a one of the following values:
538 * @arg @ref LL_RTC_TIMER_TICK_TYPE_SINGLE
539 * @arg @ref LL_RTC_TIMER_TICK_TYPE_AUTO
540 * @retval None
541 */
542 __STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t* RTCx, uint8_t tick_mode)
543 {
544 if(0 == tick_mode)
545 {
546 CLEAR_BITS(RTCx->CFG0,((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
547 }
548 else
549 {
550 SET_BITS(RTCx->CFG0,(tick_mode << RTC_CFG0_TICK_MDOE_Pos));
551 }
552 }
553
554 /**
555 * @brief Enable RTC tick interrupt.
556 *
557 * Register|BitsName
558 * --------|--------
559 * RTC_INT_EN | TICK_INT_EN
560 * @retval None
561 */
562 __STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t* RTCx)
563 {
564 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
565 }
566
567 /**
568 * @brief Disable RTCx tick.
569 *
570 * Register|BitsName
571 * --------|--------
572 * RTCx_TIMER_CTL | TICK_EN
573 * @retval None
574 */
575 __STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t* RTCx)
576 {
577 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
578 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
579 }
580
581 /**
582 * @brief Disable RTC tick interrupt.
583 *
584 * Register|BitsName
585 * --------|--------
586 * RTC_INT_EN | TICK0_INT_EN
587 * @retval None
588 */
589 __STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t* RTCx)
590 {
591 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
592 }
593
594 /**
595 * @brief Check if the RTC alarm interrupt is enabled or disabled.
596 *
597 * Register|BitsName
598 * --------|--------
599 * RTC_TIMER_CTL | TICK_EN
600 * RTC_INT_EN | TICK_INT_EN
601 * @retval State of bit (1 or 0).
602 */
603 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t* RTCx)
604 {
605 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
606 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
607 }
608
609 /**
610 * @brief Reloads RTCx tick counter and request.
611 *
612 * Register|BitsName
613 * --------|--------
614 * RTCx_TIMER_W | TIMER_VALUE
615 * RTCx_CFG0 | VAL_LOAD
616 * @retval None
617 */
618 __STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t* RTCx, uint32_t tick_reload)
619 {
620 WRITE_REG(RTCx->TICK_W, tick_reload);
621 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET);
622 }
623
624 /**
625 * @brief Restart RTCx tick counter and request.
626 *
627 * Register|BitsName
628 * --------|--------
629 * RTCx_CFG0 | RTC_CFG0_TICK_EN
630 * @retval None
631 */
632 __STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t* RTCx)
633 {
634 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET); /* clear alarm setting bit to avoid alarm value setting*/
635 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN);
636 }
637
638 /**
639 * @brief Disable RTCx tick value setting.
640 *
641 * Register|BitsName
642 * --------|--------
643 * RTCx_CFG0 | RTC_CFG0_TICK_EN
644 * @retval None
645 */
646 __STATIC_INLINE void ll_rtc_clear_tick_set(rtc_regs_t* RTCx)
647 {
648 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
649 }
650
651 /**
652 * @brief Enable RTC wrap interrupt.
653 *
654 * Register|BitsName
655 * --------|--------
656 * RTC_TIMER_CTL | WRAP_INT_EN
657 *
658 * @retval None
659 */
660 __STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t* RTCx)
661 {
662 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
663 }
664
665 /**
666 * @brief Disable RTC wrap interrupt.
667 *
668 * Register|BitsName
669 * --------|--------
670 * RTC_TIMER_CTL | WRAP_INT_EN
671 *
672 * @retval None
673 */
674 __STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t* RTCx)
675 {
676 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
677 }
678
679 /**
680 * @brief Check if the RTC wrap interrupt is enabled or disabled.
681 *
682 * Register|BitsName
683 * --------|--------
684 * RTC_TIMER_CTL | WRAP_INT_EN
685 *
686 * @retval State of bit (1 or 0).
687 */
688 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t* RTCx)
689 {
690 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
691 }
692
693 /** @} */
694
695 /** @defgroup LL_RTC_EF_FLAG_Management FLAG_Management
696 * @{
697 */
698
699 /**
700 * @brief Indicate if the RTC alarm event flag is set or not.
701 * @note This bit is set by hardware when the counter has reached alarm value.
702 * It can be cleared by writing 0 to this bit.
703 *
704 * Register|BitsName
705 * --------|--------
706 * SLP_EVENT | RTC_TIMER_ALARM
707 *
708 * @retval State of bit (1 or 0).
709 */
710 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t* RTCx)
711 {
712 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
713 }
714
715 /**
716 * @brief Indicate if the RTC wrap event flag is set or not.
717 * @note This bit is set by hardware when the counter has overflow.
718 * It can be cleared by writing 0 to this bit.
719 *
720 * Register|BitsName
721 * --------|--------
722 * SLP_EVENT | CALENDAR_TIMER_WRAP
723 *
724 * @retval State of bit (1 or 0).
725 */
726 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t* RTCx)
727 {
728 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
729 }
730
731 /**
732 * @brief Indicate if the RTC tick event flag is set or not.
733 * @note This bit is set by hardware when the counter has reached to 0.
734 * It can be cleared by writing 1 to this bit.
735 *
736 * Register|BitsName
737 * --------|--------
738 * RTC_INT_STAT | TICK_INT_STAT
739 *
740 * @retval State of bit (1 or 0).
741 */
742 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t* RTCx)
743 {
744 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
745 }
746
747 /**
748 * @brief Clear RTC alarm interrupt flag.
749 *
750 * Register|BitsName
751 * --------|--------
752 * SLP_EVENT| RTC_TIMER_ALARM
753 *
754 * @retval None
755 */
756 __STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t* RTCx)
757 {
758 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
759 }
760
761 /**
762 * @brief Clear RTC wrap interrupt flag.
763 *
764 * Register|BitsName
765 * --------|--------
766 * RTC_INT_STAT| RTC_TICK
767 *
768 * @retval None
769 */
770 __STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t* RTCx)
771 {
772 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
773 }
774
775
776 /**
777 * @brief Clear RTC tick interrupt flag.
778 *
779 * Register|BitsName
780 * --------|--------
781 * SLP_EVENT| RTC_TIMER_WRAP
782 *
783 * @retval None
784 */
785 __STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t* RTCx)
786 {
787 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
788 }
789
790 __STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t* RTCx)
791 {
792 if(RTCx == CALENDAR)
793 {
794 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
795 }
796 else if(RTCx == RTC1)
797 {
798 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
799 }
800 }
801
802 __STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t* RTCx)
803 {
804 if(RTCx == CALENDAR)
805 {
806 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
807 }
808 else if(RTCx == RTC1)
809 {
810 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
811 }
812 }
813
814 /**
815 * @brief Enable RTC alarm wakeup interrupt.
816 *
817 * Register|BitsName
818 * --------|--------
819 * AON_MISC | MCU_WAKEUP_CTRL
820 *
821 * @retval None
822 */
823 __STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t* RTCx)
824 {
825 if(RTCx == CALENDAR)
826 {
827 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
828 }
829 else if(RTCx == RTC1)
830 {
831 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
832 }
833 }
834
835 /**
836 * @brief Disable RTC alarm wakeup interrupt.
837 *
838 * Register|BitsName
839 * --------|--------
840 * AON_MISC | MCU_WAKEUP_CTRL
841 *
842 * @retval None
843 */
844 __STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t* RTCx)
845 {
846 if(RTCx == CALENDAR)
847 {
848 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
849 }
850 else if(RTCx == RTC1)
851 {
852 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
853 }
854 }
855
856 /** @} */
857
858 /** @} */
859
860
861 #ifdef __cplusplus
862 }
863 #endif
864
865 #endif /* __GR55XX_LL_RTC_H__ */
866
867 /** @} */
868
869 /** @} */
870
871 /** @} */
ll_rtc_it_enable_tick
__STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t *RTCx)
Enable RTC tick interrupt.
Definition: gr55xx_ll_rtc.h:562
ll_rtc_enable
__STATIC_INLINE void ll_rtc_enable(rtc_regs_t *RTCx)
Enable RTC counter.
Definition: gr55xx_ll_rtc.h:168
ll_rtc_clear_flag_wrap
__STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t *RTCx)
Clear RTC wrap interrupt flag.
Definition: gr55xx_ll_rtc.h:770
ll_rtc1_timer_get_clk
__STATIC_INLINE uint32_t ll_rtc1_timer_get_clk(rtc_regs_t *RTCx)
Get the RTC Timer clock.
Definition: gr55xx_ll_rtc.h:154
ll_rtc_clear_counter_set
__STATIC_INLINE void ll_rtc_clear_counter_set(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:231
ll_rtc_set_alarm
__STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t *RTCx, uint32_t value)
Enable RTC alarm.
Definition: gr55xx_ll_rtc.h:445
ll_rtc_clear_flag_tick
__STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t *RTCx)
Clear RTC tick interrupt flag.
Definition: gr55xx_ll_rtc.h:785
ll_rtc_it_disable_tick
__STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t *RTCx)
Disable RTC tick interrupt.
Definition: gr55xx_ll_rtc.h:589
ll_rtc_alarm_value_set_and_request
__STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t *RTCx, uint32_t alarm_value)
Reloads RTC alarm.
Definition: gr55xx_ll_rtc.h:261
ll_rtc_clear_wrap
__STATIC_INLINE void ll_rtc_clear_wrap(rtc_regs_t *RTCx)
CLear RTC wrap.
Definition: gr55xx_ll_rtc.h:402
ll_rtc_is_active_flag_wrap
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t *RTCx)
Indicate if the RTC wrap event flag is set or not.
Definition: gr55xx_ll_rtc.h:726
ll_rtc_it_enable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t *RTCx)
Enable RTC alarm wakeup interrupt.
Definition: gr55xx_ll_rtc.h:823
ll_rtc_get_read_counter
__STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t *RTCx)
Read the RTC counter current value.
Definition: gr55xx_ll_rtc.h:306
ll_rtc_clear_tick_it_event
__STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:802
ll_rtc_reload_tick_and_request
__STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t *RTCx, uint32_t tick_reload)
Reloads RTCx tick counter and request.
Definition: gr55xx_ll_rtc.h:618
ll_rtc_set_tick_mode
__STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t *RTCx, uint8_t tick_mode)
Set RTCx alarm_mode.
Definition: gr55xx_ll_rtc.h:542
ll_rtc_reload_counter
__STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t *RTCx, uint32_t counter)
Reloads RTC counter.
Definition: gr55xx_ll_rtc.h:210
ll_rtc_get_write_alarm
__STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t *RTCx)
Read the RTC counter config alarm value.
Definition: gr55xx_ll_rtc.h:320
ll_rtc_reload_tick
__STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t *RTCx, uint32_t tick)
Reloads RTC perd_alarm.
Definition: gr55xx_ll_rtc.h:276
ll_rtc_is_active_flag_alarm
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t *RTCx)
Indicate if the RTC alarm event flag is set or not.
Definition: gr55xx_ll_rtc.h:710
ll_rtc_is_active_flag_tick
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t *RTCx)
Indicate if the RTC tick event flag is set or not.
Definition: gr55xx_ll_rtc.h:742
ll_rtc_start_value_set_and_request
__STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t *RTCx, uint32_t start_value)
Reloads RTC counter and request.
Definition: gr55xx_ll_rtc.h:225
ll_rtc_is_enabled
__STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t *RTCx)
Check if the RTC peripheral is enabled or disabled.
Definition: gr55xx_ll_rtc.h:196
ll_rtc_it_is_enabled_alarm
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:508
ll_rtc_disable
__STATIC_INLINE void ll_rtc_disable(rtc_regs_t *RTCx)
Disable RTC counter.
Definition: gr55xx_ll_rtc.h:182
ll_rtc_it_disable_alarm
__STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm interrupt.
Definition: gr55xx_ll_rtc.h:494
ll_rtc_clear_it_event
__STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:790
ll_rtc_timer_set_clk
__STATIC_INLINE void ll_rtc_timer_set_clk(rtc_regs_t *RTCx, uint32_t value)
Set the RTC Timer clock.
Definition: gr55xx_ll_rtc.h:136
ll_rtc_set_clock_div
__STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t *RTCx, uint32_t div)
Select the RTC clock divider.
Definition: gr55xx_ll_rtc.h:431
ll_rtc_enable_tick
__STATIC_INLINE void ll_rtc_enable_tick(rtc_regs_t *RTCx)
Set RTCx tick mode.
Definition: gr55xx_ll_rtc.h:523
ll_rtc_get_write_counter
__STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t *RTCx)
Read the RTC counter config value.
Definition: gr55xx_ll_rtc.h:292
ll_rtc_clear_alarm_set
__STATIC_INLINE void ll_rtc_clear_alarm_set(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:451
ll_rtc_get_wrapcnt
__STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t *RTCx)
Get the RTC wrap-around value.
Definition: gr55xx_ll_rtc.h:359
ll_rtc_restart_tick
__STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t *RTCx)
Restart RTCx tick counter and request.
Definition: gr55xx_ll_rtc.h:632
ll_rtc_clear_flag_alarm
__STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t *RTCx)
Clear RTC alarm interrupt flag.
Definition: gr55xx_ll_rtc.h:756
ll_rtc_clear_wrap_set
__STATIC_INLINE void ll_rtc_clear_wrap_set(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:407
ll_rtc_it_enable_alarm
__STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t *RTCx)
Enable RTC alarm interrupt.
Definition: gr55xx_ll_rtc.h:465
ll_rtc_get_read_alarm
__STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t *RTCx)
Read the RTC counter current alarm value.
Definition: gr55xx_ll_rtc.h:334
ll_rtc_it_enable_wrap
__STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t *RTCx)
Enable RTC wrap interrupt.
Definition: gr55xx_ll_rtc.h:660
ll_rtc_disable_alarm
__STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm.
Definition: gr55xx_ll_rtc.h:479
ll_rtc_is_busy
__STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t *RTCx)
The RTC is busy.
Definition: gr55xx_ll_rtc.h:373
ll_rtc_disable_tick
__STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t *RTCx)
Disable RTCx tick.
Definition: gr55xx_ll_rtc.h:575
ll_rtc_it_is_enabled_tick
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:603
ll_rtc_clear_tick_set
__STATIC_INLINE void ll_rtc_clear_tick_set(rtc_regs_t *RTCx)
Disable RTCx tick value setting.
Definition: gr55xx_ll_rtc.h:646
ll_rtc_it_disable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t *RTCx)
Disable RTC alarm wakeup interrupt.
Definition: gr55xx_ll_rtc.h:844
ll_rtc_get_read_tick
__STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:344
ll_rtc_it_disable_wrap
__STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t *RTCx)
Disable RTC wrap interrupt.
Definition: gr55xx_ll_rtc.h:674
ll_rtc_it_is_enabled_wrap
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t *RTCx)
Check if the RTC wrap interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:688
ll_rtc_is_running
__STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t *RTCx)
The RTC is running.
Definition: gr55xx_ll_rtc.h:387
ll_rtc_get_write_tick
__STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:339