gr55xx_ll_spi.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (SPIM) || defined (SPIS)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
87
88 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
89 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
90
91 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
92
93 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
94 This parameter can be a value of @ref SPI_LL_EC_PHASE.
95
96 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
97
98 uint32_t slave_select; /**< Specifies the SPI slave select.
99 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
100
101 This feature can be modified afterwards using unitary function @ref ll_spi_enable_ss().*/
102
103 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
104 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
105 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
108 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
109 This parameter can be a number between 0 and 0x7 */
110 } ll_spim_init_t;
111
112 /**
113 * @brief SPIS init structures definition
114 */
115 typedef struct _ll_spis_init_t
116 {
117 uint32_t data_size; /**< Specifies the SPI data width.
118 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
119
120 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
121
122 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
123 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
124
125 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
126
127 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
128 This parameter can be a value of @ref SPI_LL_EC_PHASE.
129
130 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
131
132 } ll_spis_init_t;
133
134 /** @} */
135
136 /** @} */
137
138 /**
139 * @defgroup SPI_LL_MACRO Defines
140 * @{
141 */
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
145 * @{
146 */
147
148 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
149 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
150 * @{
151 */
152 #define LL_SPI_SR_DCOL SPI_STAT_DATA_COLN_ERR /**< Data collision error flag */
153 #define LL_SPI_SR_TXE SPI_STAT_TX_ERR /**< Transmission error flag */
154 #define LL_SPI_SR_RFF SPI_STAT_RX_FIFO_FULL /**< Rx FIFO full flag */
155 #define LL_SPI_SR_RFNE SPI_STAT_RX_FIFO_NE /**< Rx FIFO not empty flag */
156 #define LL_SPI_SR_TFE SPI_STAT_TX_FIFO_EMPTY /**< Tx FIFO empty flag */
157 #define LL_SPI_SR_TFNF SPI_STAT_TX_FIFO_NF /**< Tx FIFO not full flag */
158 #define LL_SPI_SR_BUSY SPI_STAT_SSI_BUSY /**< Busy flag */
159 /** @} */
160
161 /** @defgroup SPI_LL_EC_IT IT Defines
162 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
163 * @{
164 */
165 #define LL_SPI_IM_MST SPI_INT_MASK_MULTI_M_CIM /**< Multi-Master Contention Interrupt enable */
166 #define LL_SPI_IM_RXF SPI_INT_MASK_RX_FIFO_FIM /**< Receive FIFO Full Interrupt enable */
167 #define LL_SPI_IM_RXO SPI_INT_MASK_RX_FIFO_OIM /**< Receive FIFO Overflow Interrupt enable */
168 #define LL_SPI_IM_RXU SPI_INT_MASK_RX_FIFO_UIM /**< Receive FIFO Underflow Interrupt enable */
169 #define LL_SPI_IM_TXO SPI_INT_MASK_TX_FIFO_OIM /**< Transmit FIFO Overflow Interrupt enable */
170 #define LL_SPI_IM_TXE SPI_INT_MASK_TX_FIFO_EIM /**< Transmit FIFO Empty Interrupt enable */
171
172 #define LL_SPI_IS_MST SPI_INT_STAT_MULTI_M_CIS /**< Multi-Master Contention Interrupt flag */
173 #define LL_SPI_IS_RXF SPI_INT_STAT_RX_FIFO_FIS /**< Receive FIFO Full Interrupt flag */
174 #define LL_SPI_IS_RXO SPI_INT_STAT_RX_FIFO_OIS /**< Receive FIFO Overflow Interrupt flag */
175 #define LL_SPI_IS_RXU SPI_INT_STAT_RX_FIFO_UIS /**< Receive FIFO Underflow Interrupt flag */
176 #define LL_SPI_IS_TXO SPI_INT_STAT_TX_FIFO_OIS /**< Transmit FIFO Overflow Interrupt flag */
177 #define LL_SPI_IS_TXE SPI_INT_STAT_TX_FIFO_EIS /**< Transmit FIFO Empty Interrupt flag */
178
179 #define LL_SPI_RIS_MST SPI_RAW_INT_STAT_MULTI_M_CRIS /**< Multi-Master Contention RAW Interrupt flag */
180 #define LL_SPI_RIS_RXF SPI_RAW_INT_STAT_RX_FIFO_FRIS /**< Receive FIFO Full RAW Interrupt flag */
181 #define LL_SPI_RIS_RXO SPI_RAW_INT_STAT_RX_FIFO_ORIS /**< Receive FIFO Overflow RAW Interrupt flag */
182 #define LL_SPI_RIS_RXU SPI_RAW_INT_STAT_RX_FIFO_URIS /**< Receive FIFO Underflow RAW Interrupt flag */
183 #define LL_SPI_RIS_TXO SPI_RAW_INT_STAT_TX_FIFO_ORIS /**< Transmit FIFO Overflow RAW Interrupt flag */
184 #define LL_SPI_RIS_TXE SPI_RAW_INT_STAT_TX_FIFO_ERIS /**< Transmit FIFO Empty RAW Interrupt flag */
185 /** @} */
186
187 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
188 * @{
189 */
190 #define LL_SPI_DATASIZE_4BIT (3UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 4 bits */
191 #define LL_SPI_DATASIZE_5BIT (4UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 5 bits */
192 #define LL_SPI_DATASIZE_6BIT (5UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 6 bits */
193 #define LL_SPI_DATASIZE_7BIT (6UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 7 bits */
194 #define LL_SPI_DATASIZE_8BIT (7UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 8 bits */
195 #define LL_SPI_DATASIZE_9BIT (8UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 9 bits */
196 #define LL_SPI_DATASIZE_10BIT (9UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 10 bits */
197 #define LL_SPI_DATASIZE_11BIT (10UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 11 bits */
198 #define LL_SPI_DATASIZE_12BIT (11UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 12 bits */
199 #define LL_SPI_DATASIZE_13BIT (12UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 13 bits */
200 #define LL_SPI_DATASIZE_14BIT (13UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 14 bits */
201 #define LL_SPI_DATASIZE_15BIT (14UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 15 bits */
202 #define LL_SPI_DATASIZE_16BIT (15UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 16 bits */
203 #define LL_SPI_DATASIZE_17BIT (16UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 17 bits */
204 #define LL_SPI_DATASIZE_18BIT (17UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 18 bits */
205 #define LL_SPI_DATASIZE_19BIT (18UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 19 bits */
206 #define LL_SPI_DATASIZE_20BIT (19UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 20 bits */
207 #define LL_SPI_DATASIZE_21BIT (20UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 21 bits */
208 #define LL_SPI_DATASIZE_22BIT (21UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 22 bits */
209 #define LL_SPI_DATASIZE_23BIT (22UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 23 bits */
210 #define LL_SPI_DATASIZE_24BIT (23UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 24 bits */
211 #define LL_SPI_DATASIZE_25BIT (24UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 25 bits */
212 #define LL_SPI_DATASIZE_26BIT (25UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 26 bits */
213 #define LL_SPI_DATASIZE_27BIT (26UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 27 bits */
214 #define LL_SPI_DATASIZE_28BIT (27UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 28 bits */
215 #define LL_SPI_DATASIZE_29BIT (28UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 29 bits */
216 #define LL_SPI_DATASIZE_30BIT (29UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 30 bits */
217 #define LL_SPI_DATASIZE_31BIT (30UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 31 bits */
218 #define LL_SPI_DATASIZE_32BIT (31UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 32 bits */
219 /** @} */
220
221 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
222 * @{
223 */
224 #define LL_SPI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
225 #define LL_SPI_MW_CMDSIZE_2BIT (1UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 2 bits */
226 #define LL_SPI_MW_CMDSIZE_3BIT (2UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 3 bits */
227 #define LL_SPI_MW_CMDSIZE_4BIT (3UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 4 bits */
228 #define LL_SPI_MW_CMDSIZE_5BIT (4UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 5 bits */
229 #define LL_SPI_MW_CMDSIZE_6BIT (5UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 6 bits */
230 #define LL_SPI_MW_CMDSIZE_7BIT (6UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 7 bits */
231 #define LL_SPI_MW_CMDSIZE_8BIT (7UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 8 bits */
232 #define LL_SPI_MW_CMDSIZE_9BIT (8UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 9 bits */
233 #define LL_SPI_MW_CMDSIZE_10BIT (9UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 10 bits */
234 #define LL_SPI_MW_CMDSIZE_11BIT (10UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 11 bits */
235 #define LL_SPI_MW_CMDSIZE_12BIT (11UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 12 bits */
236 #define LL_SPI_MW_CMDSIZE_13BIT (12UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 13 bits */
237 #define LL_SPI_MW_CMDSIZE_14BIT (13UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 14 bits */
238 #define LL_SPI_MW_CMDSIZE_15BIT (14UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 15 bits */
239 #define LL_SPI_MW_CMDSIZE_16BIT (15UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 16 bits */
240 /** @} */
241
242 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
243 * @{
244 */
245 #define LL_SPI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
246 #define LL_SPI_TEST_MODE (1UL << SPI_CTRL0_SHIFT_REG_LOOP_POS) /**< Test mode for SPI transfer: Rx and Tx connected inside */
247 /** @} */
248
249 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
250 * @{
251 */
252 #define LL_SPI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
253 #define LL_SPI_SLAVE_OUTEN (1UL << SPI_CTRL0_S_OUT_EN_POS) /**< Output disable for SPI transfer as slave */
254 /** @} */
255
256 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
257 * @{
258 */
259 #define LL_SPI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
260 #define LL_SPI_SIMPLEX_TX (1UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Tx mode. Tx transfer only on 1 line */
261 #define LL_SPI_SIMPLEX_RX (2UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Rx mode. Rx transfer only on 1 line */
262 #define LL_SPI_READ_EEPROM (3UL << SPI_CTRL0_XFE_MODE_POS) /**< Read EEPROM mode. Rx transfer only on 1 line */
263 /** @} */
264
265 /** @defgroup SPI_LL_EC_PHASE Clock Phase
266 * @{
267 */
268 #define LL_SPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
269 #define LL_SPI_SCPHA_2EDGE (1UL << SPI_CTRL0_SERIAL_CLK_PHASE_POS) /**< Second clock transition is the first data capture edge */
270 /** @} */
271
272 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
273 * @{
274 */
275 #define LL_SPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
276 #define LL_SPI_SCPOL_HIGH (1UL << SPI_CTRL0_SERIAL_CLK_POL_POS) /**< Clock to 1 when idle */
277 /** @} */
278
279 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
280 * @{
281 */
282 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
283 #define LL_SPI_PROTOCOL_TI (1UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< TI mode */
284 #define LL_SPI_PROTOCOL_MICROWIRE (2UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< Microwire mode */
285 /** @} */
286
287 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
288 * @{
289 */
290 #define LL_SPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
291 #define LL_SPI_MICROWIRE_HANDSHAKE_EN (1UL << SPI_MW_CTRL_MW_HSG_POS) /**< Disable Handshake for Microwire transfer */
292
293 #define LL_SPI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
294 #define LL_SPI_MICROWIRE_TX (1UL << SPI_MW_CTRL_MW_DIR_DW_POS) /**< Tx mode. Tx transfer at Microwire mode */
295
296 #define LL_SPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
297 #define LL_SPI_MICROWIRE_SEQUENTIAL (1UL << SPI_MW_CTRL_MW_XFE_MODE_POS) /**< Sequential for Microwire transfer */
298 /** @} */
299
300 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
301 * @{
302 */
303 #define LL_SPI_SLAVE1 SPI_SLA_S1_SEL_EN /**< Enable slave1 select pin for SPI transfer */
304 #define LL_SPI_SLAVE0 SPI_SLA_S0_SEL_EN /**< Enable slave0 select pin for SPI transfer */
305 /** @} */
306
307 /** @defgroup SPI_LL_EC_DMA DMA Defines
308 * @{
309 */
310 #define LL_SPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
311 #define LL_SPI_DMA_TX_EN SPI_DMA_CTRL_TX_DMA_EN /**< Enable the transmit FIFO DMA channel */
312
313 #define LL_SPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
314 #define LL_SPI_DMA_RX_EN SPI_DMA_CTRL_RX_DMA_EN /**< Enable the receive FIFO DMA channel */
315 /** @} */
316
317 /** @defgroup LL_SPI_x_FIFO_DEPTH Defines
318 * @{
319 */
320 #define LL_SPI_M_FIFO_DEPTH (16u) /**< FIFO Depth for SPI Master */
321 #define LL_SPI_S_FIFO_DEPTH (16u) /**< FIFO Depth for SPI Slave */
322 /** @} */
323
324 /** @defgroup SPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
325 * @{
326 */
327
328 /**
329 * @brief LL SPIM InitStrcut default configuartion
330 */
331 #define LL_SPIM_DEFAULT_CONFIG \
332 { \
333 .transfer_direction = LL_SPI_FULL_DUPLEX, \
334 .data_size = LL_SPI_DATASIZE_8BIT, \
335 .clock_polarity = LL_SPI_SCPOL_LOW, \
336 .clock_phase = LL_SPI_SCPHA_1EDGE, \
337 .slave_select = LL_SPI_SLAVE0, \
338 .baud_rate = SystemCoreClock / 2000000, \
339 .rx_sample_delay = 0, \
340 }
341
342 /**
343 * @brief LL SPIS InitStrcut default configuartion
344 */
345 #define LL_SPIS_DEFAULT_CONFIG \
346 { \
347 .data_size = LL_SPI_DATASIZE_8BIT, \
348 .clock_polarity = LL_SPI_SCPOL_LOW, \
349 .clock_phase = LL_SPI_SCPHA_1EDGE, \
350 }
351 /** @} */
352
353 /** @} */
354
355
356 /* Exported macro ------------------------------------------------------------*/
357 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
358 * @{
359 */
360
361 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
362 * @{
363 */
364
365 /**
366 * @brief Write a value in SPI register
367 * @param __instance__ SPI instance
368 * @param __REG__ Register to be written
369 * @param __VALUE__ Value to be written in the register
370 * @retval None
371 */
372 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
373
374 /**
375 * @brief Read a value in SPI register
376 * @param __instance__ SPI instance
377 * @param __REG__ Register to be read
378 * @retval Register value
379 */
380 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
381
382 /** @} */
383
384 /** @} */
385
386 /** @} */
387
388 /* Exported functions --------------------------------------------------------*/
389 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
390 * @{
391 */
392
393 /** @defgroup SPI_LL_EF_Configuration Configuration functions
394 * @{
395 */
396
397 /**
398 * @brief Enable slave select toggle
399 * @note This bit should not be changed when communication is ongoing.
400 *
401 * Register|BitsName
402 * --------|--------
403 * CTRL0 | SSTEN
404 *
405 * @param SPIx SPI instance
406 * @retval None
407 */
408 __STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
409 {
410 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
411 }
412
413 /**
414 * @brief Disable slave select toggle
415 * @note This bit should not be changed when communication is ongoing.
416 *
417 * Register|BitsName
418 * --------|--------
419 * CTRL0 | SSTEN
420 *
421 * @param SPIx SPI instance
422 * @retval None
423 */
424 __STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
425 {
426 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
427 }
428
429 /**
430 * @brief Check if slave select toggle is enabled
431 * @note This bit should not be changed when communication is ongoing.
432 *
433 * Register|BitsName
434 * --------|--------
435 * CTRL0 | SSTEN
436 *
437 * @param SPIx SPI instance
438 * @retval State of bit (1 or 0).
439 */
440 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
441 {
442 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN) == (SPI_CTRL0_S_ST_EN));
443 }
444
445 /**
446 * @brief Set frame data size
447 *
448 * Register|BitsName
449 * --------|--------
450 * CTRL0 | DFS32
451 *
452 * @param SPIx SPI instance
453 * @param size This parameter can be one of the following values:
454 * @arg @ref LL_SPI_DATASIZE_4BIT
455 * @arg @ref LL_SPI_DATASIZE_5BIT
456 * @arg @ref LL_SPI_DATASIZE_6BIT
457 * @arg @ref LL_SPI_DATASIZE_7BIT
458 * @arg @ref LL_SPI_DATASIZE_8BIT
459 * @arg @ref LL_SPI_DATASIZE_9BIT
460 * @arg @ref LL_SPI_DATASIZE_10BIT
461 * @arg @ref LL_SPI_DATASIZE_11BIT
462 * @arg @ref LL_SPI_DATASIZE_12BIT
463 * @arg @ref LL_SPI_DATASIZE_13BIT
464 * @arg @ref LL_SPI_DATASIZE_14BIT
465 * @arg @ref LL_SPI_DATASIZE_15BIT
466 * @arg @ref LL_SPI_DATASIZE_16BIT
467 * @arg @ref LL_SPI_DATASIZE_17BIT
468 * @arg @ref LL_SPI_DATASIZE_18BIT
469 * @arg @ref LL_SPI_DATASIZE_19BIT
470 * @arg @ref LL_SPI_DATASIZE_20BIT
471 * @arg @ref LL_SPI_DATASIZE_21BIT
472 * @arg @ref LL_SPI_DATASIZE_22BIT
473 * @arg @ref LL_SPI_DATASIZE_23BIT
474 * @arg @ref LL_SPI_DATASIZE_24BIT
475 * @arg @ref LL_SPI_DATASIZE_25BIT
476 * @arg @ref LL_SPI_DATASIZE_26BIT
477 * @arg @ref LL_SPI_DATASIZE_27BIT
478 * @arg @ref LL_SPI_DATASIZE_28BIT
479 * @arg @ref LL_SPI_DATASIZE_29BIT
480 * @arg @ref LL_SPI_DATASIZE_30BIT
481 * @arg @ref LL_SPI_DATASIZE_31BIT
482 * @arg @ref LL_SPI_DATASIZE_32BIT
483 * @retval None
484 */
485 __STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
486 {
487 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE, size);
488 }
489
490 /**
491 * @brief Get frame data size
492 *
493 * Register|BitsName
494 * --------|--------
495 * CTRL0 | DFS32
496 *
497 * @param SPIx SPI instance
498 * @retval Returned value can be one of the following values:
499 * @arg @ref LL_SPI_DATASIZE_4BIT
500 * @arg @ref LL_SPI_DATASIZE_5BIT
501 * @arg @ref LL_SPI_DATASIZE_6BIT
502 * @arg @ref LL_SPI_DATASIZE_7BIT
503 * @arg @ref LL_SPI_DATASIZE_8BIT
504 * @arg @ref LL_SPI_DATASIZE_9BIT
505 * @arg @ref LL_SPI_DATASIZE_10BIT
506 * @arg @ref LL_SPI_DATASIZE_11BIT
507 * @arg @ref LL_SPI_DATASIZE_12BIT
508 * @arg @ref LL_SPI_DATASIZE_13BIT
509 * @arg @ref LL_SPI_DATASIZE_14BIT
510 * @arg @ref LL_SPI_DATASIZE_15BIT
511 * @arg @ref LL_SPI_DATASIZE_16BIT
512 * @arg @ref LL_SPI_DATASIZE_17BIT
513 * @arg @ref LL_SPI_DATASIZE_18BIT
514 * @arg @ref LL_SPI_DATASIZE_19BIT
515 * @arg @ref LL_SPI_DATASIZE_20BIT
516 * @arg @ref LL_SPI_DATASIZE_21BIT
517 * @arg @ref LL_SPI_DATASIZE_22BIT
518 * @arg @ref LL_SPI_DATASIZE_23BIT
519 * @arg @ref LL_SPI_DATASIZE_24BIT
520 * @arg @ref LL_SPI_DATASIZE_25BIT
521 * @arg @ref LL_SPI_DATASIZE_26BIT
522 * @arg @ref LL_SPI_DATASIZE_27BIT
523 * @arg @ref LL_SPI_DATASIZE_28BIT
524 * @arg @ref LL_SPI_DATASIZE_29BIT
525 * @arg @ref LL_SPI_DATASIZE_30BIT
526 * @arg @ref LL_SPI_DATASIZE_31BIT
527 * @arg @ref LL_SPI_DATASIZE_32BIT
528 */
529 __STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
530 {
531 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE));
532 }
533
534 /**
535 * @brief Set the length of the control word for the Microwire frame format
536 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
537 *
538 * Register|BitsName
539 * --------|--------
540 * CTRL0 | CFS
541 *
542 * @param SPIx SPI instance
543 * @param size This parameter can be one of the following values:
544 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
545 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
546 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
547 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
548 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
549 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
550 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
551 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
552 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
553 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
554 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
555 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
556 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
557 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
558 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
559 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
560 * @retval None
561 */
562 __STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
563 {
564 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE, size);
565 }
566
567 /**
568 * @brief Get the length of the control word for the Microwire frame format
569 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
570 *
571 * Register|BitsName
572 * --------|--------
573 * CTRL0 | CFS
574 *
575 * @param SPIx SPI instance
576 * @retval Returned value can be one of the following values:
577 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
578 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
579 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
580 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
581 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
582 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
583 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
584 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
585 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
586 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
587 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
588 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
589 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
590 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
591 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
592 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
593 */
594 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
595 {
596 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE));
597 }
598
599 /**
600 * @brief Enable SPI test mode
601 *
602 * Register|BitsName
603 * --------|--------
604 * CTRL0 | SRL
605 *
606 * @param SPIx SPI instance
607 * @retval None
608 */
609 __STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
610 {
611 SET_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
612 }
613
614 /**
615 * @brief Disable SPI test mode
616 *
617 * Register|BitsName
618 * --------|--------
619 * CTRL0 | SRL
620 *
621 * @param SPIx SPI instance
622 * @retval None
623 */
624 __STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
625 {
626 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
627 }
628
629 /**
630 * @brief Check if SPI test mode is enabled
631 *
632 * Register|BitsName
633 * --------|--------
634 * CTRL0 | SRL
635 *
636 * @param SPIx SPI instance
637 * @retval State of bit (1 or 0).
638 */
639 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
640 {
641 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP) == (SPI_CTRL0_SHIFT_REG_LOOP));
642 }
643
644 /**
645 * @brief Enable slave output
646 *
647 * Register|BitsName
648 * --------|--------
649 * CTRL0 | SLVOE
650 *
651 * @param SPIx SPI instance
652 * @retval None
653 */
654 __STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
655 {
656 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
657 }
658
659 /**
660 * @brief Disable slave output
661 *
662 * Register|BitsName
663 * --------|--------
664 * CTRL0 | SLVOE
665 *
666 * @param SPIx SPI instance
667 * @retval None
668 */
669 __STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
670 {
671 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
672 }
673
674 /**
675 * @brief Check if slave output is enabled
676 *
677 * Register|BitsName
678 * --------|--------
679 * CTRL0 | SLVOE
680 *
681 * @param SPIx SPI instance
682 * @retval State of bit (1 or 0).
683 */
684 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
685 {
686 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN) != (SPI_CTRL0_S_OUT_EN));
687 }
688
689 /**
690 * @brief Set transfer direction mode
691 *
692 * Register|BitsName
693 * --------|--------
694 * CTRL0 | TMOD
695 *
696 * @param SPIx SPI instance
697 * @param transfer_direction This parameter can be one of the following values:
698 * @arg @ref LL_SPI_FULL_DUPLEX
699 * @arg @ref LL_SPI_SIMPLEX_TX
700 * @arg @ref LL_SPI_SIMPLEX_RX
701 * @arg @ref LL_SPI_READ_EEPROM
702 * @retval None
703 */
704 __STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
705 {
706 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_XFE_MODE, transfer_direction);
707 }
708
709 /**
710 * @brief Get transfer direction mode
711 *
712 * Register|BitsName
713 * --------|--------
714 * CTRL0 | TMOD
715 *
716 * @param SPIx SPI instance
717 * @retval Returned value can be one of the following values:
718 * @arg @ref LL_SPI_FULL_DUPLEX
719 * @arg @ref LL_SPI_SIMPLEX_TX
720 * @arg @ref LL_SPI_SIMPLEX_RX
721 * @arg @ref LL_SPI_READ_EEPROM
722 */
723 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
724 {
725 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_XFE_MODE));
726 }
727
728 /**
729 * @brief Set clock polarity
730 * @note This bit should not be changed when communication is ongoing.
731 * This bit is not used in SPI TI mode.
732 *
733 * Register|BitsName
734 * --------|--------
735 * CTRL0 | SCPOL
736 *
737 * @param SPIx SPI instance
738 * @param clock_polarity This parameter can be one of the following values:
739 * @arg @ref LL_SPI_SCPOL_LOW
740 * @arg @ref LL_SPI_SCPOL_HIGH
741 * @retval None
742 */
743 __STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
744 {
745 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL, clock_polarity);
746 }
747
748 /**
749 * @brief Get clock polarity
750 *
751 * Register|BitsName
752 * --------|--------
753 * CTRL0 | SCPOL
754 *
755 * @param SPIx SPI instance
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_SPI_SCPOL_LOW
758 * @arg @ref LL_SPI_SCPOL_HIGH
759 */
760 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
761 {
762 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL));
763 }
764
765 /**
766 * @brief Set clock phase
767 * @note This bit should not be changed when communication is ongoing.
768 * This bit is not used in SPI TI mode.
769 *
770 * Register|BitsName
771 * --------|--------
772 * CTRL0 | SCPHA
773 *
774 * @param SPIx SPI instance
775 * @param clock_phase This parameter can be one of the following values:
776 * @arg @ref LL_SPI_SCPHA_1EDGE
777 * @arg @ref LL_SPI_SCPHA_2EDGE
778 * @retval None
779 */
780 __STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
781 {
782 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE, clock_phase);
783 }
784
785 /**
786 * @brief Get clock phase
787 *
788 * Register|BitsName
789 * --------|--------
790 * CTRL0 | SCPHA
791 *
792 * @param SPIx SPI instance
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_SPI_SCPHA_1EDGE
795 * @arg @ref LL_SPI_SCPHA_2EDGE
796 */
797 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
798 {
799 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE));
800 }
801
802 /**
803 * @brief Set serial protocol used
804 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
805 *
806 * Register|BitsName
807 * --------|--------
808 * CTRL0 | FRF
809 *
810 * @param SPIx SPI instance
811 * @param standard This parameter can be one of the following values:
812 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
813 * @arg @ref LL_SPI_PROTOCOL_TI
814 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
815 * @retval None
816 */
817 __STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
818 {
819 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT, standard);
820 }
821
822 /**
823 * @brief Get serial protocol used
824 *
825 * Register|BitsName
826 * --------|--------
827 * CTRL0 | FRF
828 *
829 * @param SPIx SPI instance
830 * @retval Returned value can be one of the following values:
831 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
832 * @arg @ref LL_SPI_PROTOCOL_TI
833 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
834 */
835 __STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
836 {
837 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT));
838 }
839
840 /**
841 * @brief Set the number of data frames to be continuously received
842 * @note These bits should not be changed when communication is ongoing.
843 This bits are effect when TMOD = 2b10 or 2b11.
844 This bits are not effect in SPIS.
845 *
846 * Register|BitsName
847 * --------|--------
848 * CTRL1 | NDF
849 *
850 * @param SPIx SPI instance
851 * @param size This parameter can be one of the following values: 0 ~ 65535
852 * @retval None
853 */
854 __STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
855 {
856 MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME, size);
857 }
858
859 /**
860 * @brief Get the number of data frames to be continuously received
861 * @note These bits should not be changed when communication is ongoing.
862 This bits are effect when TMOD = 2b10 or 2b11.
863 This bits are not effect in SPIS.
864 *
865 * Register|BitsName
866 * --------|--------
867 * CTRL1 | NDF
868 *
869 * @param SPIx SPI instance
870 * @retval Returned value can be one of the following values: 0 ~ 65535
871 */
872 __STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
873 {
874 return (uint32_t)(READ_BITS(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME));
875 }
876
877 /**
878 * @brief Enable SPI peripheral
879 *
880 * Register|BitsName
881 * --------|--------
882 * SSI_EN | EN
883 *
884 * @param SPIx SPI instance
885 * @retval None
886 */
887 __STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
888 {
889 SET_BITS(SPIx->SSI_EN, SPI_SSI_EN);
890 }
891
892 /**
893 * @brief Disable SPI peripheral
894 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
895 *
896 * Register|BitsName
897 * --------|--------
898 * SSI_EN | EN
899 *
900 * @param SPIx SPI instance
901 * @retval None
902 */
903 __STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
904 {
905 CLEAR_BITS(SPIx->SSI_EN, SPI_SSI_EN);
906 }
907
908 /**
909 * @brief Check if SPI peripheral is enabled
910 *
911 * Register|BitsName
912 * --------|--------
913 * SSI_EN | EN
914 *
915 * @param SPIx SPI instance
916 * @retval State of bit (1 or 0).
917 */
918 __STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
919 {
920 return (READ_BITS(SPIx->SSI_EN, SPI_SSI_EN) == (SPI_SSI_EN));
921 }
922
923 /**
924 * @brief Enable Handshake in Microwire mode
925 *
926 * Register|BitsName
927 * --------|--------
928 * MWC | MHS
929 *
930 * @param SPIx SPI instance
931 * @retval None
932 */
933 __STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
934 {
935 SET_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
936 }
937
938 /**
939 * @brief Disable Handshake in Microwire mode
940 *
941 * Register|BitsName
942 * --------|--------
943 * MWC | MHS
944 *
945 * @param SPIx SPI instance
946 * @retval None
947 */
948 __STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
949 {
950 CLEAR_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
951 }
952
953 /**
954 * @brief Check if Handshake in Microwire mode is enabled
955 *
956 * Register|BitsName
957 * --------|--------
958 * MWC | MHS
959 *
960 * @param SPIx SPI instance
961 * @retval State of bit (1 or 0).
962 */
963 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
964 {
965 return (READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG) == (SPI_MW_CTRL_MW_HSG));
966 }
967
968 /**
969 * @brief Set transfer direction mode in Microwire mode
970 * @note This bit should not be changed when communication is ongoing.
971 *
972 * Register|BitsName
973 * --------|--------
974 * MWC | MDD
975 *
976 * @param SPIx SPI instance
977 * @param transfer_direction This parameter can be one of the following values:
978 * @arg @ref LL_SPI_MICROWIRE_RX
979 * @arg @ref LL_SPI_MICROWIRE_TX
980 * @retval None
981 */
982 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
983 {
984 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW, transfer_direction);
985 }
986
987 /**
988 * @brief Get transfer direction mode in Microwire mode
989 * @note This bit should not be changed when communication is ongoing.
990 *
991 * Register|BitsName
992 * --------|--------
993 * MWC | MDD
994 *
995 * @param SPIx SPI instance
996 * @retval Returned value can be one of the following values:
997 * @arg @ref LL_SPI_MICROWIRE_RX
998 * @arg @ref LL_SPI_MICROWIRE_TX
999 */
1000 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
1001 {
1002 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW));
1003 }
1004
1005 /**
1006 * @brief Set transfer mode in Microwire mode
1007 * @note This bit should not be changed when communication is ongoing.
1008 *
1009 * Register|BitsName
1010 * --------|--------
1011 * MWC | MWMOD
1012 *
1013 * @param SPIx SPI instance
1014 * @param transfer_mode This parameter can be one of the following values:
1015 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1016 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1017 * @retval None
1018 */
1019 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
1020 {
1021 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE, transfer_mode);
1022 }
1023
1024 /**
1025 * @brief Get transfer mode in Microwire mode
1026 * @note This bit should not be changed when communication is ongoing.
1027 *
1028 * Register|BitsName
1029 * --------|--------
1030 * MWC | MWMOD
1031 *
1032 * @param SPIx SPI instance
1033 * @retval Returned value can be one of the following values:
1034 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1035 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1036 */
1037 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
1038 {
1039 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE));
1040 }
1041
1042 /**
1043 * @brief Enable slave select
1044 *
1045 * Register|BitsName
1046 * --------|--------
1047 * SE | SLAVE1
1048 * SE | SLAVE0
1049 *
1050 * @param SPIx SPI instance
1051 * @param ss This parameter can be one of the following values:
1052 * @arg @ref LL_SPI_SLAVE1
1053 * @arg @ref LL_SPI_SLAVE0
1054 * @retval None
1055 */
1056 __STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
1057 {
1058 SET_BITS(SPIx->S_EN, ss);
1059 }
1060
1061 /**
1062 * @brief Disable slave select
1063 *
1064 * Register|BitsName
1065 * --------|--------
1066 * SE | SLAVE1
1067 * SE | SLAVE0
1068 *
1069 * @param SPIx SPI instance
1070 * @param ss This parameter can be one of the following values:
1071 * @arg @ref LL_SPI_SLAVE1
1072 * @arg @ref LL_SPI_SLAVE0
1073 * @retval None
1074 */
1075 __STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
1076 {
1077 CLEAR_BITS(SPIx->S_EN, ss);
1078 }
1079
1080 /**
1081 * @brief Check if slave select is enabled
1082 *
1083 * Register|BitsName
1084 * --------|--------
1085 * SE | SLAVE1
1086 * SE | SLAVE0
1087 *
1088 * @param SPIx SPI instance
1089 * @param ss This parameter can be one of the following values:
1090 * @arg @ref LL_SPI_SLAVE1
1091 * @arg @ref LL_SPI_SLAVE0
1092 * @retval State of bit (1 or 0).
1093 */
1094 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
1095 {
1096 return (READ_BITS(SPIx->S_EN, ss) == ss);
1097 }
1098
1099 /**
1100 * @brief Set baud rate prescaler
1101 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1102 *
1103 * Register|BitsName
1104 * --------|--------
1105 * BAUD | SCKDIV
1106 *
1107 * @param SPIx SPI instance
1108 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1109 * @retval None
1110 */
1111 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
1112 {
1113 WRITE_REG(SPIx->BAUD, baud_rate);
1114 }
1115
1116 /**
1117 * @brief Get baud rate prescaler
1118 *
1119 * Register|BitsName
1120 * --------|--------
1121 * BAUD | SCKDIV
1122 *
1123 * @param SPIx SPI instance
1124 * @retval Returned value can be one even value between 2 and 65534.
1125 */
1126 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
1127 {
1128 return (uint32_t)(READ_BITS(SPIx->BAUD, SPI_BAUD_CLK_DIV));
1129 }
1130
1131 /**
1132 * @brief Set threshold of TXFIFO that triggers an TXE event
1133 *
1134 * Register|BitsName
1135 * --------|--------
1136 * TXFTL | TFT
1137 *
1138 * @param SPIx SPI instance
1139 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1140 * @retval None
1141 */
1142 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1143 {
1144 WRITE_REG(SPIx->TX_FIFO_TL, threshold);
1145 }
1146
1147 /**
1148 * @brief Get threshold of TXFIFO that triggers an TXE event
1149 *
1150 * Register|BitsName
1151 * --------|--------
1152 * TXFTL | TFT
1153 *
1154 * @param SPIx SPI instance
1155 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1156 */
1157 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
1158 {
1159 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_TL, SPI_TX_FIFO_TL_TX_FIFO_THD));
1160 }
1161
1162 /**
1163 * @brief Set threshold of RXFIFO that triggers an RXNE event
1164 *
1165 * Register|BitsName
1166 * --------|--------
1167 * RXFTL | RFT
1168 *
1169 * @param SPIx SPI instance
1170 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1171 * @retval None
1172 */
1173 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1174 {
1175 WRITE_REG(SPIx->RX_FIFO_TL, threshold);
1176 }
1177
1178 /**
1179 * @brief Get threshold of RXFIFO that triggers an RXNE event
1180 *
1181 * Register|BitsName
1182 * --------|--------
1183 * RXFTL | RFT
1184 *
1185 * @param SPIx SPI instance
1186 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1187 */
1188 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
1189 {
1190 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_TL, SPI_RX_FIFO_TL_RX_FIFO_THD));
1191 }
1192
1193 /**
1194 * @brief Get FIFO Transmission Level
1195 *
1196 * Register|BitsName
1197 * --------|--------
1198 * TXFL | TXTFL
1199 *
1200 * @param SPIx SPI instance
1201 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1202 */
1203 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
1204 {
1205 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_LEVEL, SPI_TX_FIFO_LEVEL_TX_FIFO_LEVEL));
1206 }
1207
1208 /**
1209 * @brief Get FIFO reception Level
1210 *
1211 * Register|BitsName
1212 * --------|--------
1213 * RXFL | RXTFL
1214 *
1215 * @param SPIx SPI instance
1216 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1217 */
1218 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
1219 {
1220 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_LEVEL, SPI_RX_FIFO_LEVEL_RX_FIFO_LEVEL));
1221 }
1222
1223 /** @} */
1224
1225 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1226 * @{
1227 */
1228
1229 /**
1230 * @brief Enable interrupt
1231 * @note This bit controls the generation of an interrupt when an event occurs.
1232 *
1233 * Register|BitsName
1234 * --------|--------
1235 * INTMASK | INTMASK
1236 *
1237 * @param SPIx SPI instance
1238 * @param mask This parameter can be one of the following values:
1239 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1240 * @arg @ref LL_SPI_IM_RXF
1241 * @arg @ref LL_SPI_IM_RXO
1242 * @arg @ref LL_SPI_IM_RXU
1243 * @arg @ref LL_SPI_IM_TXO
1244 * @arg @ref LL_SPI_IM_TXE
1245 * @retval None
1246 */
1247 __STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
1248 {
1249 SET_BITS(SPIx->INT_MASK, mask);
1250 }
1251
1252 /**
1253 * @brief Disable interrupt
1254 * @note This bit controls the generation of an interrupt when an event occurs.
1255 *
1256 * Register|BitsName
1257 * --------|--------
1258 * INTMASK | INTMASK
1259 *
1260 * @param SPIx SPI instance
1261 * @param mask This parameter can be one of the following values:
1262 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1263 * @arg @ref LL_SPI_IM_RXF
1264 * @arg @ref LL_SPI_IM_RXO
1265 * @arg @ref LL_SPI_IM_RXU
1266 * @arg @ref LL_SPI_IM_TXO
1267 * @arg @ref LL_SPI_IM_TXE
1268 * @retval None
1269 */
1270 __STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
1271 {
1272 CLEAR_BITS(SPIx->INT_MASK, mask);
1273 }
1274
1275 /**
1276 * @brief Check if interrupt is enabled
1277 *
1278 * Register|BitsName
1279 * --------|--------
1280 * INTMASK | INTMASK
1281 *
1282 * @param SPIx SPI instance
1283 * @param mask This parameter can be one of the following values:
1284 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1285 * @arg @ref LL_SPI_IM_RXF
1286 * @arg @ref LL_SPI_IM_RXO
1287 * @arg @ref LL_SPI_IM_RXU
1288 * @arg @ref LL_SPI_IM_TXO
1289 * @arg @ref LL_SPI_IM_TXE
1290 * @retval State of bit (1 or 0).
1291 */
1292 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
1293 {
1294 return (READ_BITS(SPIx->INT_MASK, mask) == mask);
1295 }
1296
1297 /** @} */
1298
1299 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1300 * @{
1301 */
1302
1303 /**
1304 * @brief Get SPI status
1305 *
1306 * Register|BitsName
1307 * --------|--------
1308 * STAT | STAT
1309 *
1310 * @param SPIx SPI instance
1311 * @retval Returned value can be one or combination of the following values:
1312 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1313 * @arg @ref LL_SPI_SR_TXE
1314 * @arg @ref LL_SPI_SR_RFF
1315 * @arg @ref LL_SPI_SR_RFNE
1316 * @arg @ref LL_SPI_SR_TFE
1317 * @arg @ref LL_SPI_SR_TFNF
1318 * @arg @ref LL_SPI_SR_BUSY
1319 */
1320 __STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
1321 {
1322 return (uint32_t)(READ_REG(SPIx->STAT));
1323 }
1324
1325 /**
1326 * @brief Check active flag
1327 *
1328 * Register|BitsName
1329 * --------|--------
1330 * STAT | DCOL
1331 * STAT | TXE
1332 * STAT | RFF
1333 * STAT | RFNE
1334 * STAT | TFE
1335 * STAT | TFNF
1336 * STAT | BUSY
1337 *
1338 * @param SPIx SPI instance
1339 * @param flag This parameter can be one of the following values:
1340 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1341 * @arg @ref LL_SPI_SR_TXE
1342 * @arg @ref LL_SPI_SR_RFF
1343 * @arg @ref LL_SPI_SR_RFNE
1344 * @arg @ref LL_SPI_SR_TFE
1345 * @arg @ref LL_SPI_SR_TFNF
1346 * @arg @ref LL_SPI_SR_BUSY
1347 * @retval State of bit (1 or 0).
1348 */
1349 __STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
1350 {
1351 return (READ_BITS(SPIx->STAT, flag) == (flag));
1352 }
1353
1354 /**
1355 * @brief Get SPI interrupt flags
1356 *
1357 * Register|BitsName
1358 * --------|--------
1359 * INTSTAT | INTSTAT
1360 *
1361 * @param SPIx SPI instance
1362 * @retval Returned value can be one or combination of the following values:
1363 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1364 * @arg @ref LL_SPI_IM_RXF
1365 * @arg @ref LL_SPI_IM_RXO
1366 * @arg @ref LL_SPI_IM_RXU
1367 * @arg @ref LL_SPI_IM_TXO
1368 * @arg @ref LL_SPI_IM_TXE
1369 */
1370 __STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
1371 {
1372 return (uint32_t)(READ_REG(SPIx->INT_STAT));
1373 }
1374
1375 /**
1376 * @brief Check interrupt flag
1377 *
1378 * Register|BitsName
1379 * --------|--------
1380 * INTSTAT | MSTIS
1381 * INTSTAT | RXFIS
1382 * INTSTAT | RXOIS
1383 * INTSTAT | RXUIS
1384 * INTSTAT | TXOIS
1385 * INTSTAT | TXEIS
1386 *
1387 * @param SPIx SPI instance
1388 * @param flag This parameter can be one of the following values:
1389 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1390 * @arg @ref LL_SPI_IM_RXF
1391 * @arg @ref LL_SPI_IM_RXO
1392 * @arg @ref LL_SPI_IM_RXU
1393 * @arg @ref LL_SPI_IM_TXO
1394 * @arg @ref LL_SPI_IM_TXE
1395 * @retval State of bit (1 or 0).
1396 */
1397 __STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
1398 {
1399 return (READ_BITS(SPIx->INT_STAT, flag) == flag);
1400 }
1401
1402 /**
1403 * @brief Get SPI raw interrupt flags
1404 *
1405 * Register|BitsName
1406 * --------|--------
1407 * RAW_INTSTAT | RAW_INTSTAT
1408 *
1409 * @param SPIx SPI instance
1410 * @retval Returned value can be one or combination of the following values:
1411 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1412 * @arg @ref LL_SPI_IM_RXF
1413 * @arg @ref LL_SPI_IM_RXO
1414 * @arg @ref LL_SPI_IM_RXU
1415 * @arg @ref LL_SPI_IM_TXO
1416 * @arg @ref LL_SPI_IM_TXE
1417 */
1418 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
1419 {
1420 return (uint32_t)(READ_REG(SPIx->RAW_INT_STAT));
1421 }
1422
1423 /**
1424 * @brief Clear transmit FIFO overflow error flag
1425 * @note Clearing this flag is done by reading TXOIC register
1426 *
1427 * Register|BitsName
1428 * --------|--------
1429 * TXOIC | TXOIC
1430 *
1431 * @param SPIx SPI instance
1432 * @retval None
1433 */
1434 __STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
1435 {
1436 __IOM uint32_t tmpreg;
1437 tmpreg = SPIx->TX_FIFO_OIC;
1438 (void) tmpreg;
1439 }
1440
1441 /**
1442 * @brief Clear receive FIFO overflow error flag
1443 * @note Clearing this flag is done by reading RXOIC register
1444 *
1445 * Register|BitsName
1446 * --------|--------
1447 * RXOIC | RXOIC
1448 *
1449 * @param SPIx SPI instance
1450 * @retval None
1451 */
1452 __STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
1453 {
1454 __IOM uint32_t tmpreg;
1455 tmpreg = SPIx->RX_FIFO_OIC;
1456 (void) tmpreg;
1457 }
1458
1459 /**
1460 * @brief Clear receive FIFO underflow error flag
1461 * @note Clearing this flag is done by reading RXUIC register
1462 *
1463 * Register|BitsName
1464 * --------|--------
1465 * RXUIC | RXUIC
1466 *
1467 * @param SPIx SPI instance
1468 * @retval None
1469 */
1470 __STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
1471 {
1472 __IOM uint32_t tmpreg;
1473 tmpreg = SPIx->RX_FIFO_UIC;
1474 (void) tmpreg;
1475 }
1476
1477 /**
1478 * @brief Clear multi-master error flag
1479 * @note Clearing this flag is done by reading MSTIC register
1480 *
1481 * Register|BitsName
1482 * --------|--------
1483 * MSTIC | MSTIC
1484 *
1485 * @param SPIx SPI instance
1486 * @retval None
1487 */
1488 __STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
1489 {
1490 __IOM uint32_t tmpreg;
1491 tmpreg = SPIx->MULTI_M_IC;
1492 (void) tmpreg;
1493 }
1494
1495 /**
1496 * @brief Clear all error flag
1497 * @note Clearing this flag is done by reading INTCLR register
1498 *
1499 * Register|BitsName
1500 * --------|--------
1501 * INTCLR | INTCLR
1502 *
1503 * @param SPIx SPI instance
1504 * @retval None
1505 */
1506 __STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
1507 {
1508 __IOM uint32_t tmpreg;
1509 tmpreg = SPIx->INT_CLR;
1510 (void) tmpreg;
1511 }
1512
1513 /** @} */
1514
1515 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1516 * @{
1517 */
1518
1519 /**
1520 * @brief Enable DMA Tx
1521 *
1522 * Register|BitsName
1523 * --------|--------
1524 * DMAC | TDMAE
1525 *
1526 * @param SPIx SPI instance
1527 * @retval None
1528 */
1529 __STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
1530 {
1531 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1532 }
1533
1534 /**
1535 * @brief Disable DMA Tx
1536 *
1537 * Register|BitsName
1538 * --------|--------
1539 * DMAC | TDMAE
1540 *
1541 * @param SPIx SPI instance
1542 * @retval None
1543 */
1544 __STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
1545 {
1546 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1547 }
1548
1549 /**
1550 * @brief Check if DMA Tx is enabled
1551 *
1552 * Register|BitsName
1553 * --------|--------
1554 * DMAC | TDMAE
1555 *
1556 * @param SPIx SPI instance
1557 * @retval State of bit (1 or 0).
1558 */
1559 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
1560 {
1561 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN) == (SPI_DMA_CTRL_TX_DMA_EN));
1562 }
1563
1564 /**
1565 * @brief Enable DMA Rx
1566 *
1567 * Register|BitsName
1568 * --------|--------
1569 * DMAC | RDMAE
1570 *
1571 * @param SPIx SPI instance
1572 * @retval None
1573 */
1574 __STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
1575 {
1576 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1577 }
1578
1579 /**
1580 * @brief Disable DMA Rx
1581 *
1582 * Register|BitsName
1583 * --------|--------
1584 * DMAC | RDMAE
1585 *
1586 * @param SPIx SPI instance
1587 * @retval None
1588 */
1589 __STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
1590 {
1591 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1592 }
1593
1594 /**
1595 * @brief Check if DMA Rx is enabled
1596 *
1597 * Register|BitsName
1598 * --------|--------
1599 * DMAC | RDMAE
1600 *
1601 * @param SPIx SPI instance
1602 * @retval State of bit (1 or 0).
1603 */
1604 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
1605 {
1606 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN) == (SPI_DMA_CTRL_RX_DMA_EN));
1607 }
1608
1609 /**
1610 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
1611 *
1612 * Register|BitsName
1613 * --------|--------
1614 * DMATDL | DMATDL
1615 *
1616 * @param SPIx SPI instance
1617 * @param threshold This parameter can be one of the following values: 0 ~ 7
1618 * @retval None
1619 */
1620 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1621 {
1622 WRITE_REG(SPIx->DMA_TX_DL, threshold);
1623 }
1624
1625 /**
1626 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
1627 *
1628 * Register|BitsName
1629 * --------|--------
1630 * DMATDL | DMATDL
1631 *
1632 * @param SPIx SPI instance
1633 * @retval Returned value can be one of the following values: 0 ~ 7
1634 */
1635 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
1636 {
1637 return (uint32_t)(READ_BITS(SPIx->DMA_TX_DL, SPI_DMA_TX_DL_DMA_TX_DL));
1638 }
1639
1640 /**
1641 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
1642 *
1643 * Register|BitsName
1644 * --------|--------
1645 * DMARDL | DMARDL
1646 *
1647 * @param SPIx SPI instance
1648 * @param threshold This parameter can be one of the following values: 0 ~ 7
1649 * @retval None
1650 */
1651 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1652 {
1653 WRITE_REG(SPIx->DMA_RX_DL, threshold);
1654 }
1655
1656 /**
1657 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
1658 *
1659 * Register|BitsName
1660 * --------|--------
1661 * DMARDL | DMARDL
1662 *
1663 * @param SPIx SPI instance
1664 * @retval Returned value can be one of the following values: 0 ~ 7
1665 */
1666 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
1667 {
1668 return (uint32_t)(READ_BITS(SPIx->DMA_RX_DL, SPI_DMA_RX_DL_DMA_RX_DL));
1669 }
1670
1671 /** @} */
1672
1673 /** @defgroup SPI_LL_EF_Data_Management Data_Management
1674 * @{
1675 */
1676
1677 /**
1678 * @brief Write 8-Bits in the data register
1679 *
1680 * Register|BitsName
1681 * --------|--------
1682 * DATA | DATA
1683 *
1684 * @param SPIx SPI instance
1685 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
1686 * @retval None
1687 */
1688 __STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
1689 {
1690 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1691 }
1692
1693 /**
1694 * @brief Write 16-Bits in the data register
1695 *
1696 * Register|BitsName
1697 * --------|--------
1698 * DATA | DATA
1699 *
1700 * @param SPIx SPI instance
1701 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
1702 * @retval None
1703 */
1704 __STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
1705 {
1706 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1707 }
1708
1709 /**
1710 * @brief Write 32-Bits in the data register
1711 *
1712 * Register|BitsName
1713 * --------|--------
1714 * DATA | DATA
1715 *
1716 * @param SPIx SPI instance
1717 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1718 * @retval None
1719 */
1720 __STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
1721 {
1722 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1723 }
1724
1725 /**
1726 * @brief Read 8-Bits in the data register
1727 *
1728 * Register|BitsName
1729 * --------|--------
1730 * DATA | DATA
1731 *
1732 * @param SPIx SPI instance
1733 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
1734 */
1735 __STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
1736 {
1737 return (uint8_t)(READ_REG(SPIx->DATA));
1738 }
1739
1740 /**
1741 * @brief Read 16-Bits in the data register
1742 *
1743 * Register|BitsName
1744 * --------|--------
1745 * DATA | DATA
1746 *
1747 * @param SPIx SPI instance
1748 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
1749 */
1750 __STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
1751 {
1752 return (uint16_t)(READ_REG(SPIx->DATA));
1753 }
1754
1755 /**
1756 * @brief Read 32-Bits in the data register
1757 *
1758 * Register|BitsName
1759 * --------|--------
1760 * DATA | DATA
1761 *
1762 * @param SPIx SPI instance
1763 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1764 */
1765 __STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
1766 {
1767 return (uint32_t)(READ_REG(SPIx->DATA));
1768 }
1769
1770 /**
1771 * @brief Set Rx sample delay
1772 * @note This bit should not be changed when communication is ongoing.
1773 *
1774 * Register|BitsName
1775 * --------|--------
1776 * RX_SAMPLEDLY | RX_SAMPLEDLY
1777 *
1778 * @param SPIx SPI instance
1779 * @param delay This parameter can be one of the following values: 0 ~ 7
1780 * @retval None
1781 */
1782 __STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
1783 {
1784 MODIFY_REG(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY, delay);
1785 }
1786
1787 /**
1788 * @brief Get Rx sample delay
1789 * @note This bit should not be changed when communication is ongoing.
1790 *
1791 * Register|BitsName
1792 * --------|--------
1793 * RX_SAMPLEDLY | RX_SAMPLEDLY
1794 *
1795 * @param SPIx SPI instance
1796 * @retval Returned value can be one of the following values: 0 ~ 7
1797 */
1798 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
1799 {
1800 return (uint32_t)(READ_BITS(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY));
1801 }
1802
1803 /** @} */
1804
1805 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
1806 * @{
1807 */
1808
1809 /**
1810 * @brief De-initialize SSI registers (Registers restored to their default values).
1811 * @param SPIx SSI instance
1812 * @retval An error_status_t enumeration value:
1813 * - SUCCESS: SSI registers are de-initialized
1814 * - ERROR: SSI registers are not de-initialized
1815 */
1816 error_status_t ll_spim_deinit(spi_regs_t *SPIx);
1817
1818 /**
1819 * @brief Initialize SPIM registers according to the specified
1820 * parameters in p_spi_init.
1821 * @param SPIx SSI instance
1822 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
1823 * information for the specified SPIM peripheral.
1824 * @retval An error_status_t enumeration value:
1825 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1826 * - ERROR: Problem occurred during SSI Registers initialization
1827 */
1828 error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
1829
1830 /**
1831 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
1832 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
1833 * whose fields will be set to default values.
1834 * @retval None
1835 */
1836 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
1837
1838 /** @} */
1839
1840 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
1841 * @{
1842 */
1843
1844 /**
1845 * @brief De-initialize SSI registers (Registers restored to their default values).
1846 * @param SPIx SSI instance
1847 * @retval An error_status_t enumeration value:
1848 * - SUCCESS: SSI registers are de-initialized
1849 * - ERROR: SSI registers are not de-initialized
1850 */
1851 error_status_t ll_spis_deinit(spi_regs_t *SPIx);
1852
1853 /**
1854 * @brief Initialize SSI registers according to the specified
1855 * parameters in p_spi_init.
1856 * @param SPIx SSI instance
1857 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
1858 * information for the specified SPIS peripheral.
1859 * @retval An error_status_t enumeration value:
1860 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1861 * - ERROR: Problem occurred during SPI Registers initialization
1862 */
1863 error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
1864
1865 /**
1866 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
1867 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
1868 * whose fields will be set to default values.
1869 * @retval None
1870 */
1871 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
1872 /** @} */
1873
1874 /** @} */
1875
1876 #endif /* SPIM || SPIS */
1877
1878 #ifdef __cplusplus
1879 }
1880 #endif
1881
1882 #endif /* __GR55xx_LL_SPI_H__ */
1883
1884 /** @} */
1885
1886 /** @} */
1887
1888 /** @} */
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr55xx_ll_spi.h:1574
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_spi.h:639
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1142
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1688
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr55xx_ll_spi.h:1798
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr55xx_ll_spi.h:1589
_ll_spis_init_t
SPIS init structures definition.
Definition: gr55xx_ll_spi.h:116
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1157
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1666
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Specifies the SPI data width.
Definition: gr55xx_ll_spi.h:117
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_spi.h:1056
ll_spis_init
error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr55xx_ll_spi.h:408
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_spi.h:1247
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr55xx_ll_spi.h:609
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1620
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr55xx_ll_spi.h:77
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
Enable slave output.
Definition: gr55xx_ll_spi.h:654
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:854
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_spi.h:1782
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_spi.h:1349
ll_spim_init
error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_spi.h:887
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
Clear all error flag.
Definition: gr55xx_ll_spi.h:1506
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1188
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:933
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr55xx_ll_spi.h:424
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:88
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_spi.h:1418
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
Disable slave output.
Definition: gr55xx_ll_spi.h:669
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:122
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_spi.h:1370
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1651
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_spi.h:903
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1765
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_spi.h:1111
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1635
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1000
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_spi.h:103
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_spi.h:963
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:594
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Specifies the SPI unidirectional or bidirectional data mode.
Definition: gr55xx_ll_spi.h:78
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1704
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_spi.h:817
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Specifies the SPI data size.
Definition: gr55xx_ll_spi.h:83
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
Get SPI status.
Definition: gr55xx_ll_spi.h:1320
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
Get frame data size.
Definition: gr55xx_ll_spi.h:529
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1037
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_spi.h:743
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:982
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_spi.h:1203
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_spi.h:1559
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_spi.h:918
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_spi.h:485
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr55xx_ll_spi.h:1529
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_spi.h:1075
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1173
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:948
_ll_spim_init_t::slave_select
uint32_t slave_select
Specifies the SPI slave select.
Definition: gr55xx_ll_spi.h:98
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:872
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
Get clock phase.
Definition: gr55xx_ll_spi.h:797
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_spi.h:1218
ll_spim_deinit
error_status_t ll_spim_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr55xx_ll_spi.h:1544
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_spi.h:1126
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1750
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_spi.h:684
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_spi.h:440
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
Get serial protocol used.
Definition: gr55xx_ll_spi.h:835
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1452
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1434
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1720
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr55xx_ll_spi.h:723
_ll_spim_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_ll_spi.h:108
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_spi.h:1397
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:127
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:93
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:562
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1735
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_spi.h:1604
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_spi.h:780
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_spi.h:1270
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1019
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_spi.h:1094
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_spi.h:1292
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_spi.h:704
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr55xx_ll_spi.h:624
ll_spis_deinit
error_status_t ll_spis_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_spi.h:1488
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
Get clock polarity.
Definition: gr55xx_ll_spi.h:760
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_spi.h:1470