gr55xx_ll_adc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_adc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of ADC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_ADC ADC
47 * @brief ADC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_ADC_H__
53 #define __GR55XX_LL_ADC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_CTL)
63
64 /** @defgroup LL_ADC_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup LL_ADC_ES_INIT ADC Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL ADC init Structure definition
75 */
76 typedef struct _ll_adc_init
77 {
78 uint32_t channel_p; /**< Specifies the input source to ADC channel P.
79 This parameter can be any value of @ref LL_ADC_EC_INPUT_SRC.
80
81 This parament can be modified afterwards using unitary function @ref ll_adc_set_channelp(). */
82
83 uint32_t channel_n; /**< Specifies the input source to ADC channel N.
84 This parameter can be any value of @ref LL_ADC_EC_INPUT_SRC.
85
86 This parament can be modified afterwards using unitary function @ref ll_adc_set_channeln(). */
87
88 uint32_t input_mode; /**< Specifies the operation mode for the ADC sample.
89 This parameter can be a value of @ref LL_ADC_EC_INPUT_MODE.
90
91 This parament can be modified afterwards using unitary function @ref ll_adc_set_input_mode(). */
92
93 uint32_t ref_source; /**< Specifies the source of the ADC reference.
94 This parameter can be a value of @ref LL_ADC_EC_REFERENCE_SRC.
95
96 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref().*/
97
98 uint32_t ref_value; /*!< Specifies the value of the ADC buffered reference.
99 This parameter can be a value of @ref LL_ADC_EC_REFERENCE.
100
101 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref_value().*/
102
103 uint32_t clock; /**< Specifies the clock of ADC.
104 This parameter can be a value of @ref LL_ADC_EC_CLK.
105
106 This parament can be modified afterwards using unitary function @ref ll_adc_set_clock().*/
107
108 } ll_adc_init_t;
109
110 /** @} */
111
112 /** @} */
113
114 /**
115 * @defgroup LL_ADC_MACRO Defines
116 * @{
117 */
118
119 /* Exported constants --------------------------------------------------------*/
120 /** @defgroup LL_ADC_Exported_Constants ADC Exported Constants
121 * @{
122 */
123
124 /** @defgroup LL_ADC_EC_CLK ADC CLOCK
125 * @{
126 */
127 #if defined(GR552xx)
128 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16 MHz */
129 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8 MHz */
130 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4 MHz */
131 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 1 MHz */
132 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16KHz */
133 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8KHz */
134 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4KHz */
135 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< Close Clock*/
136 #endif
137 /** @} */
138
139 /** @defgroup LL_ADC_EC_REFERENCE ADC Buffered Internal Reference Value
140 * @{
141 */
142 #define LL_ADC_REF_VALUE_0P8 (0x3UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 0.85 V */
143 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.28 V */
144 #define LL_ADC_REF_VALUE_1P6 (0xAUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.60 V */
145 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 2.00 V */
146 /** @} */
147
148 /** @defgroup LL_ADC_EC_INPUT_MODE ADC Input Mode
149 * @{
150 */
151 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos) /**< Single ended mode */
152 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL) /**< Differential mode */
153 /** @} */
154
155 /** @defgroup LL_ADC_EC_INPUT_SRC ADC Input Source
156 * @{
157 */
158 #define LL_ADC_INPUT_SRC_IO0 (0UL) /**< Select MSIO0 as input */
159 #define LL_ADC_INPUT_SRC_IO1 (1UL) /**< Select MSIO1 as input */
160 #define LL_ADC_INPUT_SRC_IO2 (2UL) /**< Select MSIO2 as input */
161 #define LL_ADC_INPUT_SRC_IO3 (3UL) /**< Select MSIO3 as input */
162 #define LL_ADC_INPUT_SRC_IO4 (4UL) /**< Select MSIO4 as input */
163 #define LL_ADC_INPUT_SRC_IO5 (5UL) /**< Select MSIO5 as input */
164 #define LL_ADC_INPUT_SRC_IO6 (6UL) /**< Select MSIO6 as input */
165 #define LL_ADC_INPUT_SRC_IO7 (7UL) /**< Select MSIO7 as input */
166 #define LL_ADC_INPUT_SRC_TMP (13UL) /**< Select temperature as input */
167 #define LL_ADC_INPUT_SRC_BAT (14UL) /**< Select Vbattery as input */
168 #define LL_ADC_INPUT_SRC_REF (15UL) /**< Select reference as input */
169
170 /** @} */
171
172 /** @defgroup LL_ADC_EC_REFERENCE_SRC ADC Reference Source
173 * @{
174 */
175 #if defined(GR552xx)
176 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL) /**< Select buffered internal reference as reference */
177 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO0 as reference */
178 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO1 as reference */
179 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO2 as reference */
180 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO3 as reference */
181 #endif
182 /** @} */
183
184 /** @} */
185
186 /* Exported macro ------------------------------------------------------------*/
187 /** @defgroup LL_ADC_Exported_Macros ADC Exported Macros
188 * @{
189 */
190
191 /** @defgroup LL_ADC_EM_WRITE_READ Common Write and read registers Macros
192 * @{
193 */
194
195 /**
196 * @brief Write a value in ADC register
197 * @param __instance__ ADC instance
198 * @param __REG__ Register to be written
199 * @param __VALUE__ Value to be written in the register
200 * @retval None
201 */
202 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
203
204 /**
205 * @brief Read a value in ADC register
206 * @param __instance__ ADC instance
207 * @param __REG__ Register to be read
208 * @retval Register value
209 */
210 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
211
212 /** @} */
213
214 /** @} */
215
216 /* Private types -------------------------------------------------------------*/
217 /* Private variables ---------------------------------------------------------*/
218 /* Private constants ---------------------------------------------------------*/
219 /* Private macros ------------------------------------------------------------*/
220 /** @defgroup LL_ADC_Private_Macros ADC Private Macros
221 * @{
222 */
223
224 /** @defgroup LL_ADC_EC_DEFAULT_CONFIG InitStruct default configuartion
225 * @{
226 */
227
228 /**
229 * @brief LL ADC InitStrcut default configuartion
230 */
231 #if defined(GR552xx)
232 #define LL_ADC_DEFAULT_CONFIG \
233 { \
234 .channel_p = LL_ADC_INPUT_SRC_IO0, \
235 .channel_n = LL_ADC_INPUT_SRC_IO1, \
236 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
237 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
238 .ref_value = LL_ADC_REF_VALUE_1P2, \
239 .clock = LL_ADC_CLK_16M \
240 }
241 #else
242 #define LL_ADC_DEFAULT_CONFIG \
243 { \
244 .channel_p = LL_ADC_INPUT_SRC_IO0, \
245 .channel_n = LL_ADC_INPUT_SRC_IO1, \
246 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
247 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
248 .ref_value = LL_ADC_REF_VALUE_1P2, \
249 .clock = LL_ADC_CLK_16 \
250 }
251 #endif
252 /** @} */
253
254 /** @} */
255
256 /** @} */
257
258 /* Exported functions --------------------------------------------------------*/
259 /** @defgroup LL_ADC_DRIVER_FUNCTIONS Functions
260 * @{
261 */
262
263 /** @defgroup LL_ADC_EF_Configuration Basic Configuration
264 * @{
265 */
266
267 /**
268 * @brief Enable ADC module.
269 *
270 * Register|BitsName
271 * --------|--------
272 * SNSADC_CFG | REG4
273 *
274 * @retval None
275 */
276 __STATIC_INLINE void ll_adc_enable(void)
277 {
278 #if defined(GR552xx)
279 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
280 #endif
281 }
282
283 /**
284 * @brief Disable ADC module.
285 *
286 * Register|BitsName
287 * --------|--------
288 * SNSADC_CFG | REG4
289 *
290 * @retval None
291 */
292 __STATIC_INLINE void ll_adc_disable(void)
293 {
294 #if defined(GR552xx)
295 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
296 #endif
297 }
298
299 /**
300 * @brief Check if ADC module is enabled.
301 *
302 * Register|BitsName
303 * --------|--------
304 * SNSADC_CFG | REG4
305 *
306 * @retval State of bit (1 or 0).
307 */
308 __STATIC_INLINE uint32_t ll_adc_is_enabled(void)
309 {
310 #if defined(GR552xx)
311 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
312 #endif
313 }
314
315 /**
316 * @brief Disable ADC clock.
317 *
318 * Register|BitsName
319 * --------|--------
320 * MSIO_PAD_CFG_1 | ADC_CLK_EN
321 *
322 * @retval None
323 */
324 __STATIC_INLINE void ll_adc_disable_clock(void)
325 {
326 #if defined(GR552xx)
327 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
328 #endif
329 }
330
331 /**
332 * @brief Check if ADC clock is enabled.
333 *
334 * Register|BitsName
335 * --------|--------
336 * MSIO_PAD_CFG_1 | ADC_CLK_EN
337 *
338 * @retval State of bit (1 or 0).
339 */
340 __STATIC_INLINE uint32_t ll_adc_is_enabled_clock(void)
341 {
342 #if defined(GR552xx)
343 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
344 #endif
345 }
346
347 /**
348 * @brief Set ADC clock source.
349 *
350 * Register|BitsName
351 * --------|--------
352 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
353 *
354 * @param clk This parameter can be one of the following values:
355 * @arg @ref LL_ADC_CLK_16M
356 * @arg @ref LL_ADC_CLK_8M
357 * @arg @ref LL_ADC_CLK_4M
358 * @arg @ref LL_ADC_CLK_1M
359 * @arg @ref LL_ADC_CLK_16K
360 * @arg @ref LL_ADC_CLK_8K
361 * @arg @ref LL_ADC_CLK_4K
362 * @retval None
363 */
364 __STATIC_INLINE void ll_adc_set_clock(uint32_t clk)
365 {
366 #if defined(GR552xx)
367 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
368 #endif
369 }
370
371 /**
372 * @brief Return source for ADC clock.
373 *
374 * Register|BitsName
375 * --------|--------
376 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
377 *
378 * @retval Returned value can be one of the following values:
379 * @arg @ref LL_ADC_CLK_16M
380 * @arg @ref LL_ADC_CLK_8M
381 * @arg @ref LL_ADC_CLK_4M
382 * @arg @ref LL_ADC_CLK_1M
383 * @arg @ref LL_ADC_CLK_16K
384 * @arg @ref LL_ADC_CLK_8K
385 * @arg @ref LL_ADC_CLK_4K
386 */
387 __STATIC_INLINE uint32_t ll_adc_get_clock(void)
388 {
389 #if defined(GR552xx)
390 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
391 #endif
392 }
393
394 /**
395 * @brief Set ADC bias reference.
396 *
397 * Register|BitsName
398 * --------|--------
399 * SNSADC_CFG | REG1
400 *
401 * @param value This parameter can be one of the following values:
402 * @arg @ref LL_ADC_REF_VALUE_0P8
403 * @arg @ref LL_ADC_REF_VALUE_1P2
404 * @arg @ref LL_ADC_REF_VALUE_1P6
405 * @arg @ref LL_ADC_REF_VALUE_2P0
406 * @retval None
407 */
408 __STATIC_INLINE void ll_adc_set_ref_value(uint32_t value)
409 {
410 #if defined(GR552xx)
411 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
412 #endif
413 }
414
415 /**
416 * @brief Return ADC bias reference.
417 *
418 * Register|BitsName
419 * --------|--------
420 * SNSADC_CFG | REG1
421 *
422 * @retval Returned value can be one of the following values:
423 * @arg @ref LL_ADC_REF_VALUE_0P8
424 * @arg @ref LL_ADC_REF_VALUE_1P2
425 * @arg @ref LL_ADC_REF_VALUE_1P6
426 * @arg @ref LL_ADC_REF_VALUE_2P0
427 */
428 __STATIC_INLINE uint32_t ll_adc_get_ref_value(void)
429 {
430 #if defined(GR552xx)
431 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
432 #endif
433 }
434
435 /**
436 * @brief Enable temperature sensor.
437 *
438 * Register|BitsName
439 * --------|--------
440 * SNSADC_CFG | REG2
441 *
442 * @retval None
443 */
444 __STATIC_INLINE void ll_adc_enable_temp(void)
445 {
446 #if defined(GR552xx)
447 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
448 #endif
449 }
450
451 /**
452 * @brief Disable temperature sensor.
453 *
454 * Register|BitsName
455 * --------|--------
456 * SNSADC_CFG | REG2
457 *
458 * @retval None
459 */
460 __STATIC_INLINE void ll_adc_disable_temp(void)
461 {
462 #if defined(GR552xx)
463 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
464 #endif
465 }
466
467 /**
468 * @brief Check if temperature sensor is enabled.
469 *
470 * Register|BitsName
471 * --------|--------
472 * SNSADC_CFG | REG2
473 *
474 * @retval State of bit (1 or 0).
475 */
476 __STATIC_INLINE uint32_t ll_adc_is_enabled_temp(void)
477 {
478 #if defined(GR552xx)
479 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
480 #endif
481 }
482
483 /**
484 * @brief Enable Vbattery sensor.
485 *
486 * Register|BitsName
487 * --------|--------
488 * SNSADC_CFG | REG2
489 *
490 * @retval None
491 */
492 __STATIC_INLINE void ll_adc_enable_vbat(void)
493 {
494 #if defined(GR552xx)
495 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
496 #endif
497 }
498
499 /**
500 * @brief Disable Vbattery sensor.
501 *
502 * Register|BitsName
503 * --------|--------
504 * SNSADC_CFG | REG2
505 *
506 * @retval None
507 */
508 __STATIC_INLINE void ll_adc_disable_vbat(void)
509 {
510 #if defined(GR552xx)
511 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
512 #endif
513 }
514
515 /**
516 * @brief Check if Vbattery sensor is enabled.
517 *
518 * Register|BitsName
519 * --------|--------
520 * SNSADC_CFG | REG2
521 *
522 * @retval State of bit (1 or 0).
523 */
524 __STATIC_INLINE uint32_t ll_adc_is_enabled_vbat(void)
525 {
526 #if defined(GR552xx)
527 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
528 #endif
529 }
530
531 /**
532 * @brief Set ADC input mode.
533 *
534 * Register|BitsName
535 * --------|--------
536 * SNSADC_CFG | REG2
537 *
538 * @param mode This parameter can be one of the following values:
539 * @arg @ref LL_ADC_INPUT_SINGLE
540 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
541 * @retval None
542 */
543 __STATIC_INLINE void ll_adc_set_input_mode(uint32_t mode)
544 {
545 #if defined(GR552xx)
546 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
547 #endif
548 }
549
550 /**
551 * @brief Return ADC input mode.
552 *
553 * Register|BitsName
554 * --------|--------
555 * SNSADC_CFG | REG2
556 *
557 * @retval Returned value can be one of the following values:
558 * @arg @ref LL_ADC_INPUT_SINGLE
559 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
560 */
561 __STATIC_INLINE uint32_t ll_adc_get_input_mode(void)
562 {
563 #if defined(GR552xx)
564 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk) >> AON_PMU_SNSADC_CFG_SINGLE_EN_Pos);
565 #endif
566 }
567
568 /**
569 * @brief Enable offset calibration.
570 * @note Enable offset calibration, used to swap inputs of comparator for offset
571 * calibration.
572 *
573 * Register|BitsName
574 * --------|--------
575 * SNSADC_CFG | REG2
576 *
577 * @retval None
578 */
579 __STATIC_INLINE void ll_adc_enable_ofs_cal(void)
580 {
581 #if defined(GR552xx)
582 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
583 #endif
584 }
585
586 /**
587 * @brief Disable offset calibration.
588 *
589 * Register|BitsName
590 * --------|--------
591 * SNSADC_CFG | REG2
592 *
593 * @retval None
594 */
595 __STATIC_INLINE void ll_adc_disable_ofs_cal(void)
596 {
597 #if defined(GR552xx)
598 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
599 #endif
600 }
601
602 /**
603 * @brief Check if offset calibration is enabled.
604 *
605 * Register|BitsName
606 * --------|--------
607 * SNSADC_CFG | REG2
608 *
609 * @retval State of bit (1 or 0).
610 */
611 __STATIC_INLINE uint32_t ll_adc_is_enabled_ofs_cal(void)
612 {
613 #if defined(GR552xx)
614 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
615 #endif
616 }
617
618 /**
619 * @brief Set dynamic rang of ADC.
620 * @note When higher input signal frequencies close to Nyquist rate, you should set 1.
621 *
622 * Register|BitsName
623 * --------|--------
624 * SNSADC_CFG | REG2
625 *
626 * @param rang This parameter can be a value between: 1 ~ 7
627 * @retval None
628 */
629 __STATIC_INLINE void ll_adc_set_dynamic_rang(uint32_t rang)
630 {
631 #if defined(GR552xx)
632 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
633 #endif
634 }
635
636 /**
637 * @brief Return ADC dynamic rang.
638 *
639 * Register|BitsName
640 * --------|--------
641 * SNSADC_CFG | REG2
642 *
643 * @retval Returned value can be a value between: 1 ~ 7
644 */
645 __STATIC_INLINE uint32_t ll_adc_get_dynamic_rang(void)
646 {
647 #if defined(GR552xx)
648 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
649 #endif
650 }
651
652 /**
653 * @brief Set source of ADC input channelP.
654 *
655 * Register|BitsName
656 * --------|--------
657 * SNSADC_CFG | REG3
658 *
659 * @param source This parameter can be one of the following values:
660 * @arg @ref LL_ADC_INPUT_SRC_IO0
661 * @arg @ref LL_ADC_INPUT_SRC_IO1
662 * @arg @ref LL_ADC_INPUT_SRC_IO2
663 * @arg @ref LL_ADC_INPUT_SRC_IO3
664 * @arg @ref LL_ADC_INPUT_SRC_IO4
665 * @arg @ref LL_ADC_INPUT_SRC_TMP
666 * @arg @ref LL_ADC_INPUT_SRC_BAT
667 * @retval None
668 */
669 __STATIC_INLINE void ll_adc_set_channelp(uint32_t source)
670 {
671 #if defined(GR552xx)
672 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
673 #endif
674 }
675
676 /**
677 * @brief Return source of ADC input channelP.
678 *
679 * Register|BitsName
680 * --------|--------
681 * SNSADC_CFG | REG3
682 *
683 * @retval Returned value can be one of the following values:
684 * @arg @ref LL_ADC_INPUT_SRC_IO0
685 * @arg @ref LL_ADC_INPUT_SRC_IO1
686 * @arg @ref LL_ADC_INPUT_SRC_IO2
687 * @arg @ref LL_ADC_INPUT_SRC_IO3
688 * @arg @ref LL_ADC_INPUT_SRC_IO4
689 * @arg @ref LL_ADC_INPUT_SRC_TMP
690 * @arg @ref LL_ADC_INPUT_SRC_BAT
691 */
692 __STATIC_INLINE uint32_t ll_adc_get_channelp(void)
693 {
694 #if defined(GR552xx)
695 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
696 #endif
697 }
698
699 /**
700 * @brief Set source of ADC input channelN.
701 *
702 * Register|BitsName
703 * --------|--------
704 * SNSADC_CFG | REG3
705 *
706 * @param source This parameter can be one of the following values:
707 * @arg @ref LL_ADC_INPUT_SRC_IO0
708 * @arg @ref LL_ADC_INPUT_SRC_IO1
709 * @arg @ref LL_ADC_INPUT_SRC_IO2
710 * @arg @ref LL_ADC_INPUT_SRC_IO3
711 * @arg @ref LL_ADC_INPUT_SRC_IO4
712 * @arg @ref LL_ADC_INPUT_SRC_TMP
713 * @arg @ref LL_ADC_INPUT_SRC_BAT
714 * @retval None
715 */
716 __STATIC_INLINE void ll_adc_set_channeln(uint32_t source)
717 {
718 #if defined(GR552xx)
719 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
720 #endif
721 }
722
723 /**
724 * @brief Return source of ADC input channelN.
725 *
726 * Register|BitsName
727 * --------|--------
728 * SNSADC_CFG | REG3
729 *
730 * @retval Returned value can be one of the following values:
731 * @arg @ref LL_ADC_INPUT_SRC_IO0
732 * @arg @ref LL_ADC_INPUT_SRC_IO1
733 * @arg @ref LL_ADC_INPUT_SRC_IO2
734 * @arg @ref LL_ADC_INPUT_SRC_IO3
735 * @arg @ref LL_ADC_INPUT_SRC_IO4
736 * @arg @ref LL_ADC_INPUT_SRC_TMP
737 * @arg @ref LL_ADC_INPUT_SRC_BAT
738 */
739 __STATIC_INLINE uint32_t ll_adc_get_channeln(void)
740 {
741 #if defined(GR552xx)
742 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
743 #endif
744 }
745
746 /**
747 * @brief Enable ADC MAS_RST.
748 *
749 * Register|BitsName
750 * --------|--------
751 * SNSADC_CFG | REG4
752 *
753 * @retval None
754 */
755 __STATIC_INLINE void ll_adc_enable_mas_rst(void)
756 {
757 #if defined(GR552xx)
758 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
759 #endif
760 }
761
762 /**
763 * @brief Disable ADC MAS_RST.
764 *
765 * Register|BitsName
766 * --------|--------
767 * SNSADC_CFG | REG4
768 *
769 * @retval None
770 */
771 __STATIC_INLINE void ll_adc_disable_mas_rst(void)
772 {
773 #if defined(GR552xx)
774 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
775 #endif
776 }
777
778 /**
779 * @brief Check if ADC MAS_RST is enabled.
780 *
781 * Register|BitsName
782 * --------|--------
783 * SNSADC_CFG | REG4
784 *
785 * @retval State of bit (1 or 0).
786 */
787 __STATIC_INLINE uint32_t ll_adc_is_enabled_mas_rst(void)
788 {
789 #if defined(GR552xx)
790 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
791 #endif
792 }
793
794 /**
795 * @brief Set source of ADC reference.
796 *
797 * Register|BitsName
798 * --------|--------
799 * SNSADC_CFG | REG4
800 *
801 * @param source This parameter can be one of the following values:
802 * @arg @ref LL_ADC_REF_SRC_BUF_INT
803 * @arg @ref LL_ADC_REF_SRC_IO0
804 * @arg @ref LL_ADC_REF_SRC_IO1
805 * @arg @ref LL_ADC_REF_SRC_IO2
806 * @arg @ref LL_ADC_REF_SRC_IO3
807 * @retval None
808 */
809 __STATIC_INLINE void ll_adc_set_ref(uint32_t source)
810 {
811 #if defined(GR552xx)
812 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
813 #endif
814 }
815
816 /**
817 * @brief Return source of ADC reference.
818 *
819 * Register|BitsName
820 * --------|--------
821 * SNSADC_CFG | REG4
822 *
823 * @retval Returned value can be one of the following values:
824 * @arg @ref LL_ADC_REF_SRC_BUF_INT
825 * @arg @ref LL_ADC_REF_SRC_IO0
826 * @arg @ref LL_ADC_REF_SRC_IO1
827 * @arg @ref LL_ADC_REF_SRC_IO2
828 * @arg @ref LL_ADC_REF_SRC_IO3
829 */
830 __STATIC_INLINE uint32_t ll_adc_get_ref(void)
831 {
832 #if defined(GR552xx)
833 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
834 #endif
835 }
836
837 /**
838 * @brief Set current of ADC reference circuit.
839 * @note When samples at 100kbps, you should set 0.
840 * When samples at 1mbps, you should set 7.
841 *
842 * Register|BitsName
843 * --------|--------
844 * SNSADC_CFG | REG4
845 *
846 * @param source This parameter can be a value between: 0 ~ 7
847 * @retval None
848 */
849 __STATIC_INLINE void ll_adc_set_ref_current(uint32_t source)
850 {
851 #if defined(GR552xx)
852 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
853 #endif
854 }
855
856 /**
857 * @brief Return current of ADC reference circuit.
858 *
859 * Register|BitsName
860 * --------|--------
861 * SNSADC_CFG | REG4
862 *
863 * @retval Returned value can be a value between: 0 ~ 7
864 */
865 __STATIC_INLINE uint32_t ll_adc_get_ref_current(void)
866 {
867 #if defined(GR552xx)
868 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
869 #endif
870 }
871
872 /** @} */
873
874 /** @defgroup LL_ADC_EF_FIFO_Access FIFO Access
875 * @{
876 */
877
878 /**
879 * @brief Return samples value of ADC by reading FIFO.
880 * @note There are two value in the register, both of them is 16bits.
881 *
882 * Register|BitsName
883 * --------|--------
884 * SENSE_ADC_FIFO | SENSE_ADC_FIFO
885 *
886 * @retval Smaples value of input
887 */
888 __STATIC_INLINE uint32_t ll_adc_read_fifo(void)
889 {
890 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
891 }
892
893 /**
894 * @brief Set threshold of ADC FIFO.
895 *
896 * Register|BitsName
897 * --------|--------
898 * SENSE_FF_THRESH | SENSE_FF_THRESH
899 *
900 * @param thresh This parameter can be a value between: 0 ~ 64
901 * @retval None
902 */
903 __STATIC_INLINE void ll_adc_set_thresh(uint32_t thresh)
904 {
905 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
906 }
907
908 /**
909 * @brief Return threshold of ADC FIFO.
910 *
911 * Register|BitsName
912 * --------|--------
913 * SENSE_FF_THRESH | SENSE_FF_THRESH
914 *
915 * @retval Returned value can be a value between: 0 ~ 64
916 */
917 __STATIC_INLINE uint32_t ll_adc_get_thresh(void)
918 {
919 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
920 }
921
922 /**
923 * @brief Enable ADC dma_req.
924 *
925 * Register|BitsName
926 * --------|--------
927 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
928 *
929 * @retval None
930 */
931 __STATIC_INLINE void ll_adc_enable_dma_req(void)
932 {
933 #if defined(GR552xx)
934 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
935 #endif
936 }
937
938 /**
939 * @brief Disable ADC dma_req.
940 *
941 * Register|BitsName
942 * --------|--------
943 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
944 *
945 * @retval None
946 */
947 __STATIC_INLINE void ll_adc_disable_dma_req(void)
948 {
949 #if defined(GR552xx)
950 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
951 #endif
952 }
953
954
955 /**
956 * @brief Check if dma_req is enabled.
957 *
958 * Register|BitsName
959 * --------|--------
960 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
961 *
962 * @retval State of bit (1 or 0).
963 */
964 __STATIC_INLINE uint32_t ll_adc_is_enabled_dma_req(void)
965 {
966 #if defined(GR552xx)
967 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
968 #endif
969 }
970
971 /**
972 * @brief Check if ADC FIFO is not empty.
973 *
974 * Register|BitsName
975 * --------|--------
976 * SENSE_ADC_STAT | VAL
977 *
978 * @retval State of bit (1 or 0).
979 */
980 __STATIC_INLINE uint32_t ll_adc_is_fifo_notempty(void)
981 {
982 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
983 }
984
985 /**
986 * @brief Return count of ADC FIFO.
987 *
988 * Register|BitsName
989 * --------|--------
990 * SENSE_ADC_STAT | FF_COUNT
991 *
992 * @retval Returned value can be a value between: 0 ~ 64
993 */
994 __STATIC_INLINE uint32_t ll_adc_get_fifo_count(void)
995 {
996 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
997 }
998
999 /**
1000 * @brief Flush ADC FIFO.
1001 *
1002 * Register|BitsName
1003 * --------|--------
1004 * SENSE_ADC_STAT | FF_FLUSH
1005 *
1006 * @retval void
1007 */
1008 __STATIC_INLINE void ll_adc_flush_fifo(void)
1009 {
1010 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
1011 }
1012
1013 /**
1014 * @brief Try to lock sw token.
1015 *
1016 * Register|BitsName
1017 * --------|--------
1018 * SENSE_ADC_GET_TKN_SW
1019 *
1020 * @retval Returned true if sw lock adc token success; return false if sw lock adc token fail
1021 */
1022 __STATIC_INLINE uint32_t ll_adc_try_lock_sw_token(void)
1023 {
1024 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
1025 }
1026
1027 /**
1028 * @brief Release sw token.
1029 *
1030 * Register|BitsName
1031 * --------|--------
1032 * SENSE_ADC_RET_TKN_SW | SW_RELEASE_Msk
1033 *
1034 * @retval none
1035 */
1036 __STATIC_INLINE void ll_adc_release_sw_token(void)
1037 {
1038 CLEAR_BITS(MCU_SUB->SENSE_ADC_RET_TKN_SW, MCU_SUB_SNSADC_RET_TKN_SW_RELEASE_Msk);
1039 }
1040
1041 /**
1042 * @brief get adc token state.
1043 *
1044 * Register|BitsName
1045 * --------|--------
1046 * SENSE_ADC_TKN_STS
1047 *
1048 * @retval Returned value from SENSE_ADC_TKN_STS reg
1049 */
1050 __STATIC_INLINE uint32_t ll_adc_get_token_state(void)
1051 {
1052 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);
1053 }
1054
1055 /** @} */
1056
1057 /** @defgroup LL_ADC_EF_Init Initialization and de-initialization functions
1058 * @{
1059 */
1060
1061 /**
1062 * @brief De-initialize ADC registers (Registers restored to their default values).
1063 * @retval An error_status_t enumeration value:
1064 * - SUCCESS: ADC registers are de-initialized
1065 * - ERROR: ADC registers are not de-initialized
1066 */
1067 error_status_t ll_adc_deinit(void);
1068
1069 /**
1070 * @brief Initialize ADC registers according to the specified.
1071 * parameters in p_adc_init.
1072 * @param p_adc_init Pointer to a ll_adc_init_t structure that contains the configuration
1073 * information for the specified ADC peripheral.
1074 * @retval An error_status_t enumeration value:
1075 * - SUCCESS: ADC registers are initialized according to p_adc_init content
1076 * - ERROR: Problem occurred during ADC Registers initialization
1077 */
1078 error_status_t ll_adc_init(ll_adc_init_t *p_adc_init);
1079
1080 /**
1081 * @brief Set each field of a @ref ll_adc_init_t type structure to default value.
1082 * @param p_adc_init Pointer to a @ref ll_adc_init_t structure
1083 * whose fields will be set to default values.
1084 * @retval None
1085 */
1086 void ll_adc_struct_init(ll_adc_init_t *p_adc_init);
1087
1088 /** @} */
1089
1090 /** @} */
1091
1092 #endif /* AON */
1093
1094 #ifdef __cplusplus
1095 }
1096 #endif
1097
1098 #endif /* __GR55XX_LL_ADC_H__ */
1099
1100 /** @} */
1101
1102 /** @} */
1103
1104 /** @} */