gr55xx_ll_uart.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (UART0) || defined (UART1) || \
63 defined (UART2) || defined (UART3) || \
64 defined (UART4) || defined (UART5)
65
66 /** @defgroup UART_LL_STRUCTURES Structures
67 * @{
68 */
69
70 /* Exported types ------------------------------------------------------------*/
71 /** @defgroup UART_LL_ES_INIT UART Exported init structures
72 * @{
73 */
74
75 /**
76 * @brief LL UART init Structure definition
77 */
78 typedef struct _ll_uart_init_t
79 {
80 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
81
82 This feature can be modified afterwards using unitary function @ref ll_uart_set_baud_rate().*/
83
84 uint32_t data_bits; /**< Specifies the number of data bits transmitted or received in a frame.
85 This parameter can be a value of @ref UART_LL_EC_DATABITS.
86
87 This feature can be modified afterwards using unitary function @ref ll_uart_set_data_bits_length().*/
88
89 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
90 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
91
92 This feature can be modified afterwards using unitary function @ref ll_uart_set_stop_bits_length().*/
93
94 uint32_t parity; /**< Specifies the parity mode.
95 This parameter can be a value of @ref UART_LL_EC_PARITY.
96
97 This feature can be modified afterwards using unitary function @ref ll_uart_set_parity().*/
98
99 uint32_t hw_flow_ctrl; /**< Specifies whether the hardware flow control mode is enabled or disabled.
100 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
101
102 This feature can be modified afterwards using unitary function @ref ll_uart_set_hw_flow_ctrl().*/
103 } ll_uart_init_t;
104
105 /** @} */
106
107 /** @} */
108
109 /**
110 * @defgroup UART_LL_MACRO Defines
111 * @{
112 */
113
114 /* Exported constants --------------------------------------------------------*/
115 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
116 * @{
117 */
118
119 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
120 * @brief Flags definitions which can be used with LL_UART_ReadReg function
121 * @{
122 */
123 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
124 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
125 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
126 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
127 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register empty flag */
128 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
129 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
130
131 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
132 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
133 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
134 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
135 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
136 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
137
138 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
139 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
140 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
141 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
142 /** @} */
143
144 /** @defgroup UART_LL_EC_IT IT Defines
145 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
146 * @{
147 */
148 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status Interrupt */
149 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line Status Interrupt */
150 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding Register Empty Interrupt */
151 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available Interrupt and Character Timeout Interrupt */
152 /** @} */
153
154 /** @defgroup UART_LL_EC_PARITY Parity Control
155 * @{
156 */
157 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
158 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and Odd Parity is selected */
159 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and Even Parity is selected */
160 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and Stick Parity 0 is selected */
161 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and Stick Parity 1 is selected */
162 /** @} */
163
164 /** @defgroup UART_LL_EC_DATABITS Data Bits
165 * @{
166 */
167 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit, 5 data bits, n stop bits */
168 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit, 6 data bits, n stop bits */
169 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit, 7 data bits, n stop bits */
170 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit, 8 data bits, n stop bits */
171 /** @} */
172
173 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
174 * @{
175 */
176 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
177 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
178 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
179 /** @} */
180
181 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
182 * @{
183 */
184 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow control disabled */
185 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow control enabled */
186 /** @} */
187
188 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
189 * @{
190 */
191 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
192 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
193 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
194 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
195 /** @} */
196
197 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
198 * @{
199 */
200 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
201 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
202 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
203 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
204 /** @} */
205
206 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
207 * @{
208 */
209 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
210 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
211 /** @} */
212
213 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
214 * @{
215 */
216 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
217 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
218 /** @} */
219
220 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
221 * @{
222 */
223
224 /**
225 * @brief LL UART InitStrcut default configuartion
226 */
227 #define LL_UART_DEFAULT_CONFIG \
228 { \
229 .baud_rate = 9600U, \
230 .data_bits = LL_UART_DATABITS_8B, \
231 .stop_bits = LL_UART_STOPBITS_1, \
232 .parity = LL_UART_PARITY_NONE, \
233 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
234 }
235 /** @} */
236
237 /** @} */
238
239 /* Exported macro ------------------------------------------------------------*/
240 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
241 * @{
242 */
243
244 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
245 * @{
246 */
247
248 /**
249 * @brief Write a value in UART register
250 * @param __instance__ UART instance
251 * @param __REG__ Register to be written
252 * @param __VALUE__ Value to be written in the register
253 * @retval None
254 */
255 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
256
257 /**
258 * @brief Read a value in UART register
259 * @param __instance__ UART instance
260 * @param __REG__ Register to be read
261 * @retval Register value
262 */
263 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
264
265 /** @} */
266
267 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
268 * @{
269 */
270
271 /**
272 * @brief Compute UARTDIV value according to Peripheral Clock and
273 * expected Baud Rate (32 bits value of UARTDIV is returned)
274 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
275 * @param __BAUDRATE__ Baud rate value to achieve
276 * @retval UARTDIV value to be used for DLL,DLH registers
277 */
278 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
279
280 /**
281 * @brief Compute UARTDLF value according to Peripheral Clock and
282 * expected Baud Rate (32 bits value of UARTDLF is returned)
283 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
284 * @param __BAUDRATE__ Baud rate value to achieve
285 * @retval UARTDLF value to be used for DLL,DLH registers
286 */
287 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
288
289 /** @} */
290
291 /** @} */
292
293 /** @} */
294
295 /* Exported functions --------------------------------------------------------*/
296 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
297 * @{
298 */
299
300 /** @defgroup UART_LL_EF_Configuration Configuration functions
301 * @{
302 */
303
304 /**
305 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
306 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
307 * (Baud rate value != 0)
308 *
309 * Register|BitsName
310 * --------|--------
311 * DLL | DLL
312 * DLH | DLH
313 *
314 * @param UARTx UART instance
315 * @param peripheral_clock Peripheral Clock
316 * @param baud_rate Baud Rate
317 * @retval None
318 */
319 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
320 {
321 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
322
323 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
324 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
325 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
326 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
327 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
328 }
329
330 /**
331 * @brief Return current Baud Rate value
332 * @note In case of non-initialized or invalid value stored in DLL,DLH and DLF register, the value 0 will be returned..
333 *
334 * Register|BitsName
335 * --------|--------
336 * DLL | DLL
337 * DLH | DLH
338 *
339 * @param UARTx UART instance
340 * @param peripheral_clock Peripheral Clock
341 * @retval Baud Rate
342 */
343 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
344 {
345 register uint32_t uartdiv = 0x0U;
346 register uint32_t baud = 0x0U;
347
348 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
349 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
350 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
351
352 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
353 {
354 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
355 }
356
357 return baud;
358 }
359
360 /**
361 * @brief Set the length of the data bits
362 *
363 * Register|BitsName
364 * --------|--------
365 * LCR | DLS
366 *
367 * @param UARTx UART instance
368 * @param data_bits This parameter can be one of the following values:
369 * @arg @ref LL_UART_DATABITS_5B
370 * @arg @ref LL_UART_DATABITS_6B
371 * @arg @ref LL_UART_DATABITS_7B
372 * @arg @ref LL_UART_DATABITS_8B
373 *
374 * @retval None
375 */
376 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
377 {
378 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
379 }
380
381 /**
382 * @brief Return the length of the data bits
383 *
384 * Register|BitsName
385 * --------|--------
386 * LCR | DLS
387 *
388 * @param UARTx UART instance
389 * @retval Returned value can be one of the following values:
390 * @arg @ref LL_UART_DATABITS_5B
391 * @arg @ref LL_UART_DATABITS_6B
392 * @arg @ref LL_UART_DATABITS_7B
393 * @arg @ref LL_UART_DATABITS_8B
394 */
395 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
396 {
397 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
398 }
399
400 /**
401 * @brief Set the length of the stop bits
402 *
403 * Register|BitsName
404 * --------|--------
405 * LCR | STOP
406 *
407 * @param UARTx UART instance
408 * @param stop_bits This parameter can be one of the following values:
409 * @arg @ref LL_UART_STOPBITS_1
410 * @arg @ref LL_UART_STOPBITS_1_5 (*)
411 * @arg @ref LL_UART_STOPBITS_2 (*)
412 *
413 * (*) STOPBITS_1_5 only valid when DataBits = 5
414 * (*) STOPBITS_2 is invalid when DataBits = 5
415 * @retval None
416 */
417 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
418 {
419 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
420 }
421
422 /**
423 * @brief Retrieve the length of the stop bits
424 *
425 * Register|BitsName
426 * --------|--------
427 * LCR | STOP
428 *
429 * @param UARTx UART instance
430 * @retval Returned value can be one of the following values:
431 * @arg @ref LL_UART_STOPBITS_1
432 * @arg @ref LL_UART_STOPBITS_1_5
433 * @arg @ref LL_UART_STOPBITS_2
434 */
435 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
436 {
437 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
438 }
439
440 /**
441 * @brief Configure Parity.
442 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
443 * When the parity control is enabled (Odd,Even,0,1), computed parity bit is inserted at the MSB position
444 * and parity is checked on the received data.
445 *
446 * Register|BitsName
447 * --------|--------
448 * LCR | SP
449 * LCR | EPS
450 * LCR | PEN
451 *
452 * @param UARTx UART instance
453 * @param parity This parameter can be one of the following values:
454 * @arg @ref LL_UART_PARITY_NONE
455 * @arg @ref LL_UART_PARITY_EVEN
456 * @arg @ref LL_UART_PARITY_ODD
457 * @arg @ref LL_UART_PARITY_SP0
458 * @arg @ref LL_UART_PARITY_SP1
459 * @retval None
460 */
461 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
462 {
463 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
464 }
465
466 /**
467 * @brief Return Parity configuration
468 *
469 * Register|BitsName
470 * --------|--------
471 * LCR | SP
472 * LCR | EPS
473 * LCR | PEN
474 *
475 * @param UARTx UART instance
476 * @retval Returned value can be one of the following values:
477 * @arg @ref LL_UART_PARITY_NONE
478 * @arg @ref LL_UART_PARITY_EVEN
479 * @arg @ref LL_UART_PARITY_ODD
480 * @arg @ref LL_UART_PARITY_SP0
481 * @arg @ref LL_UART_PARITY_SP1
482 */
483 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
484 {
485 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
486 }
487
488 /**
489 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
490 * @note This function call is equivalent to the following function call sequence :
491 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
492 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
493 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
494 *
495 * Register|BitsName
496 * --------|--------
497 * LCR | PS
498 * LCR | EPS
499 * LCR | PEN
500 * LCR | STOP
501 * LCR | DLS
502 *
503 * @param UARTx UART instance
504 * @param data_bits This parameter can be one of the following values:
505 * @arg @ref LL_UART_DATABITS_5B
506 * @arg @ref LL_UART_DATABITS_6B
507 * @arg @ref LL_UART_DATABITS_7B
508 * @arg @ref LL_UART_DATABITS_8B
509 * @param parity This parameter can be one of the following values:
510 * @arg @ref LL_UART_PARITY_NONE
511 * @arg @ref LL_UART_PARITY_EVEN
512 * @arg @ref LL_UART_PARITY_ODD
513 * @arg @ref LL_UART_PARITY_SP0
514 * @arg @ref LL_UART_PARITY_SP1
515 * @param stop_bits This parameter can be one of the following values:
516 * @arg @ref LL_UART_STOPBITS_1
517 * @arg @ref LL_UART_STOPBITS_1_5 (*)
518 * @arg @ref LL_UART_STOPBITS_2 (*)
519 *
520 * (*) STOPBITS_1_5 only valid when DataBits = 5
521 * (*) STOPBITS_2 is invalid when DataBits = 5
522 * @retval None
523 */
524 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
525 uint32_t data_bits,
526 uint32_t parity,
527 uint32_t stop_bits)
528 {
529 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
530 }
531
532 /**
533 * @brief Set UART RTS pin state to Active/Inactive
534 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
535 *
536 * Register|BitsName
537 * --------|--------
538 * SRTS | SRTS
539 * MCR | RTS
540 *
541 * @param UARTx UART instance
542 * @param pin_state This parameter can be one of the following values:
543 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
544 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
545 * @retval None
546 */
547 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
548 {
549 WRITE_REG(UARTx->SRTS, pin_state);
550 }
551
552 /**
553 * @brief Get UART RTS pin state
554 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
555 *
556 * Register|BitsName
557 * --------|--------
558 * SRTS | SRTS
559 * MCR | RTS
560 *
561 * @param UARTx UART instance
562 * @retval Returned value can be one of the following values:
563 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
564 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
565 */
566 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
567 {
568 return (uint32_t)(READ_REG(UARTx->SRTS));
569 }
570
571 /**
572 * @brief Get UART CTS pin state
573 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
574 *
575 * Register|BitsName
576 * --------|--------
577 * MSR | CTS
578 *
579 * @param UARTx UART instance
580 * @retval Returned value can be one of the following values:
581 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
582 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
583 */
584 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
585 {
586 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
587 }
588
589 /**
590 * @brief Indicate if CTS is changed since the last time the MSR was read
591 *
592 * Register|BitsName
593 * --------|--------
594 * MSR | DCTS
595 *
596 * @param UARTx UART instance
597 * @retval State of bit (1 or 0).
598 */
599 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
600 {
601 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
602 }
603
604 /**
605 * @brief Configure SIR mode enable
606 * @note This function is used to Enable UART SIR mode.
607 *
608 * Register|BitsName
609 * --------|--------
610 * MCR | SIRE
611 *
612 * @param UARTx UART instance
613 * @retval None
614 */
615 __STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
616 {
617 SET_BITS(UARTx->MCR, UART_MCR_SIRE);
618 }
619
620 /**
621 * @brief Configure SIR mode disable
622 * @note This function is used to Disable UART SIR mode.
623 *
624 * Register|BitsName
625 * --------|--------
626 * MCR | SIRE
627 *
628 * @param UARTx UART instance
629 * @retval None
630 */
631 __STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
632 {
633 CLEAR_BITS(UARTx->MCR, UART_MCR_SIRE);
634 }
635
636 /**
637 * @brief Return SIR mode state
638 * @note This function is used to return UART SIR mode state.
639 *
640 * Register|BitsName
641 * --------|--------
642 * MCR | SIRE
643 *
644 * @param UARTx UART instance
645 * @retval State of bit (1 or 0).
646 */
647 __STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
648 {
649 return (READ_BITS(UARTx->MCR, UART_MCR_SIRE) == UART_MCR_SIRE);
650 }
651
652 /**
653 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
654 * @note This function is used to Enable/Disable UART Auto Flow Control.
655 *
656 * Register|BitsName
657 * --------|--------
658 * MCR | AFCE
659 * MCR | RTS
660 *
661 * @param UARTx UART instance
662 * @param hw_flow_ctrl This parameter can be one of the following values:
663 * @arg @ref LL_UART_HWCONTROL_NONE
664 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
665 * @retval None
666 */
667 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
668 {
669 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
670 }
671
672 /**
673 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
674 *
675 * Register|BitsName
676 * --------|--------
677 * MCR | AFCE
678 * MCR | RTS
679 *
680 * @param UARTx UART instance
681 * @retval Returned value can be one of the following values:
682 * @arg @ref LL_UART_HWCONTROL_NONE
683 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
684 */
685 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
686 {
687 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
688 }
689
690 /**
691 * @brief Enable Break sending
692 *
693 * Register|BitsName
694 * --------|--------
695 * LCR | BC
696 *
697 * @param UARTx UART instance
698 * @retval None
699 */
700 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
701 {
702 WRITE_REG(UARTx->SBCR, 0x1U);
703 }
704
705 /**
706 * @brief Disable Break sending
707 *
708 * Register|BitsName
709 * --------|--------
710 * LCR | BC
711 *
712 * @param UARTx UART instance
713 * @retval None
714 */
715 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
716 {
717 WRITE_REG(UARTx->SBCR, 0x0U);
718 }
719
720 /**
721 * @brief Indicate if Break sending is enabled
722 *
723 * Register|BitsName
724 * --------|--------
725 * LCR | BC
726 *
727 * @param UARTx UART instance
728 * @retval State of bit (1 or 0).
729 */
730 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
731 {
732 return READ_REG(UARTx->SBCR);
733 }
734
735 /**
736 * @brief Enable TX FIFO and RX FIFO
737 *
738 * Register|BitsName
739 * --------|--------
740 * SFE | SFE
741 *
742 * @param UARTx UART instance
743 * @retval None
744 */
745 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
746 {
747 WRITE_REG(UARTx->SFE, 0x1U);
748 }
749
750 /**
751 * @brief Disable TX FIFO and RX FIFO
752 *
753 * Register|BitsName
754 * --------|--------
755 * SFE | SFE
756 *
757 * @param UARTx UART instance
758 * @retval None
759 */
760 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
761 {
762 WRITE_REG(UARTx->SFE, 0x0U);
763 }
764
765 /**
766 * @brief Indicate if TX FIFO and RX FIFO is enabled
767 *
768 * Register|BitsName
769 * --------|--------
770 * SFE | SFE
771 *
772 * @param UARTx UART instance
773 * @retval State of bit (1 or 0).
774 */
775 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
776 {
777 return READ_REG(UARTx->SFE);
778 }
779
780 /**
781 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
782 *
783 * Register|BitsName
784 * --------|--------
785 * STET | STET
786 *
787 * @param UARTx UART instance
788 * @param threshold This parameter can be one of the following values:
789 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
790 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
791 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
792 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
793 * @retval None
794 */
795 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
796 {
797 WRITE_REG(UARTx->STET, threshold);
798 }
799
800 /**
801 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
802 *
803 * Register|BitsName
804 * --------|--------
805 * STET | STET
806 *
807 * @param UARTx UART instance
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
810 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
811 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
812 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
813 */
814 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
815 {
816 return (uint32_t)(READ_REG(UARTx->STET));
817 }
818
819 /**
820 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
821 *
822 * Register|BitsName
823 * --------|--------
824 * SRT | SRT
825 *
826 * @param UARTx UART instance
827 * @param threshold This parameter can be one of the following values:
828 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
829 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
830 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
831 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
832 * @retval None
833 */
834 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
835 {
836 WRITE_REG(UARTx->SRT, threshold);
837 }
838
839 /**
840 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
841 *
842 * Register|BitsName
843 * --------|--------
844 * SRT | SRT
845 *
846 * @param UARTx UART instance
847 * @retval Returned value can be one of the following values:
848 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
849 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
850 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
851 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
852 */
853 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
854 {
855 return (uint32_t)(READ_REG(UARTx->SRT));
856 }
857
858 /**
859 * @brief Get FIFO Transmission Level
860 *
861 * Register|BitsName
862 * --------|--------
863 * TFL | TFL
864 *
865 * @param UARTx UART instance
866 * @retval Returned value can be one of the following values:
867 */
868 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
869 {
870 return (uint32_t)(READ_REG(UARTx->TFL));
871 }
872
873 /**
874 * @brief Get FIFO reception Level
875 *
876 * Register|BitsName
877 * --------|--------
878 * RFL | RFL
879 *
880 * @param UARTx UART instance
881 * @retval Returned value can be one of the following values:
882 */
883 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
884 {
885 return (uint32_t)(READ_REG(UARTx->RFL));
886 }
887
888 /**
889 * @brief Flush Receive FIFO
890 *
891 * Register|BitsName
892 * --------|--------
893 * SRR | RFR
894 *
895 * @param UARTx UART instance
896 * @retval None
897 */
898 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
899 {
900 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
901 }
902
903 /**
904 * @brief Flush Transmit FIFO
905 *
906 * Register|BitsName
907 * --------|--------
908 * SRR | XFR
909 *
910 * @param UARTx UART instance
911 * @retval None
912 */
913 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
914 {
915 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
916 }
917
918 /**
919 * @brief Reset UART
920 * @note This function asynchronously resets the DW_apb_uart and synchronously
921 * removes the reset assertion. For a two clock implementation, both pclk
922 * and sclk domains will be reset.
923 *
924 * Register|BitsName
925 * --------|--------
926 * SRR | UR
927 *
928 * @param UARTx UART instance
929 * @retval None
930 */
931 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
932 {
933 WRITE_REG(UARTx->SRR, UART_SRR_UR);
934 }
935
936 /** @} */
937
938 /** @defgroup UART_LL_EF_IT_Management IT_Management
939 * @{
940 */
941
942 /**
943 * @brief Enable Modem Status Interrupt
944 *
945 * Register|BitsName
946 * --------|--------
947 * IER | EDSSI
948 *
949 * @param UARTx UART instance
950 * @retval None
951 */
952 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
953 {
954 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
955 }
956
957 /**
958 * @brief Enable Receiver Line Status Interrupt
959 *
960 * Register|BitsName
961 * --------|--------
962 * IER | RLS
963 *
964 * @param UARTx UART instance
965 * @retval None
966 */
967 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
968 {
969 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
970 }
971
972 /**
973 * @brief Enable Transmit Holding Register Empty Interrupt
974 *
975 * Register|BitsName
976 * --------|--------
977 * IER | PTIME
978 * IER | ETBEI
979 *
980 * @param UARTx UART instance
981 * @retval None
982 */
983 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
984 {
985 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
986 }
987
988 /**
989 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
990 *
991 * Register|BitsName
992 * --------|--------
993 * IER | ERBFI
994 *
995 * @param UARTx UART instance
996 * @retval None
997 */
998 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
999 {
1000 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1001 }
1002
1003 /**
1004 * @brief Disable Modem Status Interrupt
1005 *
1006 * Register|BitsName
1007 * --------|--------
1008 * IER | EDSSI
1009 *
1010 * @param UARTx UART instance
1011 * @retval None
1012 */
1013 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
1014 {
1015 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1016 }
1017
1018 /**
1019 * @brief Disable Receiver Line Status Interrupt
1020 *
1021 * Register|BitsName
1022 * --------|--------
1023 * IER | RLS
1024 *
1025 * @param UARTx UART instance
1026 * @retval None
1027 */
1028 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
1029 {
1030 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1031 }
1032
1033 /**
1034 * @brief Disable Transmit Holding Register Empty Interrupt
1035 *
1036 * Register|BitsName
1037 * --------|--------
1038 * IER | PTIME
1039 * IER | ETBEI
1040 *
1041 * @param UARTx UART instance
1042 * @retval None
1043 */
1044 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
1045 {
1046 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1047 }
1048
1049 /**
1050 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1051 *
1052 * Register|BitsName
1053 * --------|--------
1054 * IER | ERBFI
1055 *
1056 * @param UARTx UART instance
1057 * @retval None
1058 */
1059 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1060 {
1061 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1062 }
1063
1064 /**
1065 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * IER | EDSSI
1070 *
1071 * @param UARTx UART instance
1072 * @retval State of bit (1 or 0).
1073 */
1074 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1075 {
1076 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1077 }
1078
1079 /**
1080 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1081 *
1082 * Register|BitsName
1083 * --------|--------
1084 * IER | RLS
1085 *
1086 * @param UARTx UART instance
1087 * @retval State of bit (1 or 0).
1088 */
1089 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1090 {
1091 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1092 }
1093
1094 /**
1095 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1096 *
1097 * Register|BitsName
1098 * --------|--------
1099 * IER | PTIME
1100 * IER | ETBEI
1101 *
1102 * @param UARTx UART instance
1103 * @retval State of bit (1 or 0).
1104 */
1105 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1106 {
1107 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1108 }
1109
1110 /**
1111 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1112 * is enabled or disabled.
1113 *
1114 * Register|BitsName
1115 * --------|--------
1116 * IER | ERBFI
1117 *
1118 * @param UARTx UART instance
1119 * @retval State of bit (1 or 0).
1120 */
1121 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1122 {
1123 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1124 }
1125
1126 /**
1127 * @brief Enable the specified UART Interrupt.
1128 *
1129 * Register|BitsName
1130 * --------|--------
1131 * IER | EDSSI
1132 * IER | ERLS
1133 * IER | PTIME
1134 * IER | ETBEI
1135 * IER | ERBFI
1136 *
1137 * @param UARTx UART instance
1138 * @param mask This parameter can be a combination of the following values:
1139 * @arg @ref LL_UART_IER_MS
1140 * @arg @ref LL_UART_IER_RLS
1141 * @arg @ref LL_UART_IER_THRE
1142 * @arg @ref LL_UART_IER_RDA
1143 * @retval None
1144 */
1145 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1146 {
1147 SET_BITS(UARTx->DLH_IER.IER, mask);
1148 }
1149
1150 /**
1151 * @brief Disable the specified UART Interrupt.
1152 *
1153 * Register|BitsName
1154 * --------|--------
1155 * IER | EDSSI
1156 * IER | ERLS
1157 * IER | PTIME
1158 * IER | ETBEI
1159 * IER | ERBFI
1160 *
1161 * @param UARTx UART instance
1162 * @param mask This parameter can be a combination of the following values:
1163 * @arg @ref LL_UART_IER_MS
1164 * @arg @ref LL_UART_IER_RLS
1165 * @arg @ref LL_UART_IER_THRE
1166 * @arg @ref LL_UART_IER_RDA
1167 * @retval None
1168 */
1169 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1170 {
1171 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1172 }
1173
1174 /**
1175 * @brief Check if the specified UART Interrupt is enabled or disabled.
1176 *
1177 * Register|BitsName
1178 * --------|--------
1179 * IER | EDSSI
1180 * IER | ERLS
1181 * IER | PTIME
1182 * IER | ETBEI
1183 * IER | ERBFI
1184 *
1185 * @param UARTx UART instance
1186 * @param mask This parameter can be a combination of the following values:
1187 * @arg @ref LL_UART_IER_MS
1188 * @arg @ref LL_UART_IER_RLS
1189 * @arg @ref LL_UART_IER_THRE
1190 * @arg @ref LL_UART_IER_RDA
1191 * @retval State of bit (1 or 0).
1192 */
1193 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1194 {
1195 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1196 }
1197
1198 /** @} */
1199
1200 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1201 * @{
1202 */
1203
1204 /**
1205 * @brief Get UART Receive Line Status Flag
1206 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1207 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1208 *
1209 * Register|BitsName
1210 * --------|--------
1211 * LSR | OE
1212 * LSR | PE
1213 * LSR | FE
1214 * LSR | BI
1215 * LSR | THRE
1216 * LSR | TEMT
1217 * LSR | RFE
1218 *
1219 * @param UARTx UART instance
1220 * @retval Returned value can be a combination of the following values:
1221 * @arg @ref LL_UART_LSR_OE
1222 * @arg @ref LL_UART_LSR_PE
1223 * @arg @ref LL_UART_LSR_FE
1224 * @arg @ref LL_UART_LSR_BI
1225 * @arg @ref LL_UART_LSR_THRE
1226 * @arg @ref LL_UART_LSR_TEMT
1227 * @arg @ref LL_UART_LSR_RFE
1228 */
1229 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1230 {
1231 return ((uint32_t)READ_REG(UARTx->LSR));
1232 }
1233
1234 /**
1235 * @brief Clear UART Receive Line Status Flag
1236 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1237 *
1238 * Register|BitsName
1239 * --------|--------
1240 * LSR | OE
1241 * LSR | PE
1242 * LSR | FE
1243 * LSR | BI
1244 * LSR | RFE
1245 *
1246 * @param UARTx UART instance
1247 * @retval None
1248 */
1249 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1250 {
1251 __IO uint32_t tmpreg;
1252 tmpreg = READ_REG(UARTx->LSR);
1253 (void) tmpreg;
1254 }
1255
1256 /**
1257 * @brief Check if the UART Receive FIFO Full Flag is set or not
1258 *
1259 * Register|BitsName
1260 * --------|--------
1261 * USR | RFF
1262 *
1263 * @param UARTx UART instance
1264 * @retval State of bit (1 or 0).
1265 */
1266 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1267 {
1268 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1269 }
1270
1271 /**
1272 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1273 *
1274 * Register|BitsName
1275 * --------|--------
1276 * USR | RFNE
1277 *
1278 * @param UARTx UART instance
1279 * @retval State of bit (1 or 0).
1280 */
1281 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1282 {
1283 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1284 }
1285
1286 /**
1287 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1288 *
1289 * Register|BitsName
1290 * --------|--------
1291 * USR | TFE
1292 *
1293 * @param UARTx UART instance
1294 * @retval State of bit (1 or 0).
1295 */
1296 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1297 {
1298 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1299 }
1300
1301 /**
1302 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1303 *
1304 * Register|BitsName
1305 * --------|--------
1306 * USR | TFNF
1307 *
1308 * @param UARTx UART instance
1309 * @retval State of bit (1 or 0).
1310 */
1311 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1312 {
1313 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1314 }
1315
1316 /**
1317 * @brief Get UART interrupt flags
1318 * @note The interrupt flags will be cleared after reading IIR.
1319 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1320 * and No Interrupt Pending Flag will be RESET, read IIR again can get the pended interrupt
1321 *
1322 * Register|BitsName
1323 * --------|--------
1324 * IIR | IID
1325 *
1326 * @param UARTx UART instance
1327 * @retval Returned value can be one or combination of the following values:
1328 * @arg @ref LL_UART_IIR_MS
1329 * @arg @ref LL_UART_IIR_NIP
1330 * @arg @ref LL_UART_IIR_THRE
1331 * @arg @ref LL_UART_IIR_RDA
1332 * @arg @ref LL_UART_IIR_RLS
1333 * @arg @ref LL_UART_IIR_CTO
1334 */
1335 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1336 {
1337 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1338 }
1339
1340 /** @} */
1341
1342 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1343 * @{
1344 */
1345
1346 /**
1347 * @brief Get the data register address used for DMA transfer
1348 * @note The address of data register RBR is the same as the address of THR.
1349 *
1350 * Register|BitsName
1351 * --------|--------
1352 * RBR | RBR
1353 * THR | THR
1354 *
1355 * @param UARTx UART instance
1356 * @retval Address of data register
1357 */
1358 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1359 {
1360 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1361 }
1362
1363 /** @} */
1364
1365 /** @defgroup UART_LL_EF_Data_Management Data_Management
1366 * @{
1367 */
1368
1369 /**
1370 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1371 *
1372 * Register|BitsName
1373 * --------|--------
1374 * RBR | RBR
1375 *
1376 * @param UARTx UART instance
1377 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1378 */
1379 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1380 {
1381 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1382 }
1383
1384 /**
1385 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1386 *
1387 * Register|BitsName
1388 * --------|--------
1389 * THR | THR
1390 *
1391 * @param UARTx UART instance
1392 * @param value between Min_Data=0x00 and Max_Data=0xFF
1393 * @retval None
1394 */
1395 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1396 {
1397 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1398 }
1399
1400 /** @} */
1401
1402 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1403 * @{
1404 */
1405
1406 /**
1407 * @brief De-initialize UART registers (Registers restored to their default values).
1408 * @param UARTx UART instance
1409 * @retval An error_status_t enumeration value:
1410 * - SUCCESS: UART registers are de-initialized
1411 * - ERROR: UART registers are not de-initialized
1412 */
1413 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1414
1415 /**
1416 * @brief Initialize UART registers according to the specified
1417 * parameters in p_uart_init.
1418 * @param UARTx UART instance
1419 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1420 * information for the specified UART peripheral.
1421 * @retval An error_status_t enumeration value:
1422 * - SUCCESS: UART registers are initialized according to p_uart_init content
1423 * - ERROR: Problem occurred during UART Registers initialization
1424 */
1425 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1426
1427 /**
1428 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1429 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1430 * whose fields will be set to default values.
1431 * @retval None
1432 */
1433 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1434
1435 /** @} */
1436
1437 /** @} */
1438
1439 #endif /* UART0 || UART1 || UART2 || UART3 || UART4 || UART5*/
1440
1441 #ifdef __cplusplus
1442 }
1443 #endif
1444
1445 #endif /* __GR55xx_LL_UART_H__ */
1446
1447 /** @} */
1448
1449 /** @} */
1450
1451 /** @} */
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1281
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1074
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: gr55xx_ll_uart.h:547
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: gr55xx_ll_uart.h:730
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:1044
ll_uart_enable_sir
__STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
Configure SIR mode enable.
Definition: gr55xx_ll_uart.h:615
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: gr55xx_ll_uart.h:417
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: gr55xx_ll_uart.h:319
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: gr55xx_ll_uart.h:775
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:983
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_uart.h:1358
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:952
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: gr55xx_ll_uart.h:461
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1059
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: gr55xx_ll_uart.h:287
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_uart.h:868
_ll_uart_init_t
LL UART init Structure definition.
Definition: gr55xx_ll_uart.h:79
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:853
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: gr55xx_ll_uart.h:566
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:967
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: gr55xx_ll_uart.h:715
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1105
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1266
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1145
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1229
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: gr55xx_ll_uart.h:700
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:760
ll_uart_init
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: gr55xx_ll_uart.h:395
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: gr55xx_ll_uart.h:584
_ll_uart_init_t::data_bits
uint32_t data_bits
Specifies the number of data bits transmitted or received in a frame.
Definition: gr55xx_ll_uart.h:84
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1089
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1249
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:998
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: gr55xx_ll_uart.h:343
_ll_uart_init_t::baud_rate
uint32_t baud_rate
This field defines expected Usart communication baud rate.
Definition: gr55xx_ll_uart.h:80
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: gr55xx_ll_uart.h:1121
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1395
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1169
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:685
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:667
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:814
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:1013
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:834
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: gr55xx_ll_uart.h:913
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1379
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: gr55xx_ll_uart.h:483
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: gr55xx_ll_uart.h:931
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:1028
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Specifies the number of stop bits transmitted.
Definition: gr55xx_ll_uart.h:89
_ll_uart_init_t::parity
uint32_t parity
Specifies the parity mode.
Definition: gr55xx_ll_uart.h:94
ll_uart_disable_sir
__STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
Configure SIR mode disable.
Definition: gr55xx_ll_uart.h:631
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: gr55xx_ll_uart.h:883
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Specifies whether the hardware flow control mode is enabled or disabled.
Definition: gr55xx_ll_uart.h:99
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1296
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: gr55xx_ll_uart.h:524
ll_uart_deinit
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:745
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:795
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: gr55xx_ll_uart.h:435
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: gr55xx_ll_uart.h:599
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1193
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1311
ll_uart_is_enabled_sir
__STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
Return SIR mode state.
Definition: gr55xx_ll_uart.h:647
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: gr55xx_ll_uart.h:898
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: gr55xx_ll_uart.h:278
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: gr55xx_ll_uart.h:376
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: gr55xx_ll_uart.h:1335