Enumerations
Enumerations
Graphics » HAL DC » GDC
Collaboration diagram for Enumerations:

## Enumerations
enum | hal_gdc_layer_ctrl_t { HAL_GDC_LAYER_DISABLE = 0, HAL_GDC_FORCE_A = 1U << 30, HAL_GDC_SCALE_NN = 1U << 29, HAL_GDC_MODULATE_A = 1U << 28, HAL_GDC_LAYER_AHBLOCK = 1U << 27, HAL_GDC_LAYER_GAMMALUT_EN = 1U << 26 }
| Layer control definition. More...
enum | hal_gdc_blend_factors_t { HAL_GDC_BF_ZERO = 0x0, HAL_GDC_BF_ONE = 0x1, HAL_GDC_BF_SRCALPHA = 0x2, HAL_GDC_BF_GLBALPHA = 0x3, HAL_GDC_BF_SRCGBLALPHA = 0x4, HAL_GDC_BF_INVSRCALPHA = 0x5, HAL_GDC_BF_INVGBLALPHA = 0x6, HAL_GDC_BF_INVSRCGBLALPHA = 0x7, HAL_GDC_BF_DSTALPHA = 0xa, HAL_GDC_BF_INVDSTALPHA = 0xb }
| Layer blending factor definition. More...
enum | hal_gdc_blend_mode_t { HAL_GDC_BL_SIMPLE = (HAL_GDC_BF_SRCALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)), HAL_GDC_BL_CLEAR = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_ZERO <<4)), HAL_GDC_BL_SRC = (HAL_GDC_BF_ONE | (HAL_GDC_BF_ZERO <<4)), HAL_GDC_BL_SRC_OVER = (HAL_GDC_BF_ONE | (HAL_GDC_BF_INVSRCALPHA <<4)), HAL_GDC_BL_DST_OVER = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_ONE <<4)), HAL_GDC_BL_SRC_IN = (HAL_GDC_BF_DSTALPHA | (HAL_GDC_BF_ZERO <<4)), HAL_GDC_BL_DST_IN = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_SRCALPHA <<4)), HAL_GDC_BL_SRC_OUT = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_ZERO <<4)), HAL_GDC_BL_DST_OUT = (HAL_GDC_BF_ZERO | (HAL_GDC_BF_INVSRCALPHA <<4)), HAL_GDC_BL_SRC_ATOP = (HAL_GDC_BF_DSTALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)), HAL_GDC_BL_DST_ATOP = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_SRCALPHA <<4)), HAL_GDC_BL_ADD = (HAL_GDC_BF_ONE | (HAL_GDC_BF_ONE <<4)), HAL_GDC_BL_XOR = (HAL_GDC_BF_INVDSTALPHA | (HAL_GDC_BF_INVSRCALPHA <<4)) }
| Layer blending mode definition. More...
enum | hal_gdc_format_t { HAL_GDC_RGBA5551 = 0x01, HAL_GDC_ABGR8888 = 0x02, HAL_GDC_RGB332 = 0x04, HAL_GDC_RGB565 = 0x05, HAL_GDC_BGRA8888 = 0x06, HAL_GDC_L8 = 0x07, HAL_GDC_L1 = 0x08, HAL_GDC_L4 = 0x09, HAL_GDC_YUYV = 0x0a, HAL_GDC_RGB24 = 0x0b, HAL_GDC_YUY2 = 0x0c, HAL_GDC_RGBA8888 = 0x0d, HAL_GDC_ARGB8888 = 0x0e, HAL_GDC_V_YUV420 = 0x10, HAL_GDC_TLYUV420 = 0x11, HAL_GDC_TSC4 = 0x12, HAL_GDC_TSC6 = 0x13, HAL_GDC_TSC6A = 0x14, HAL_GDC_RGBA4444 = 0x15, HAL_GDC_ARGB4444 = 0x18 }
| Layer color mode definition. More...
enum | hal_gdc_videomode_t { HAL_GDC_DISABLE = 0, HAL_GDC_CURSOR = 1U << 30, HAL_GDC_NEG_V = 1U << 28, HAL_GDC_NEG_H = 1U << 27, HAL_GDC_NEG_DE = 1U << 26, HAL_GDC_DITHER = 1U << 24, HAL_GDC_DITHER16 = 2U << 24, HAL_GDC_DITHER15 = 3U << 24, HAL_GDC_SINGLEV = 1U << 23, HAL_GDC_INVPIXCLK = 1U << 22, HAL_GDC_PALETTE = 1U << 20, HAL_GDC_GAMMA = 1U << 20, HAL_GDC_BLANK = 1U << 19, HAL_GDC_INTERLACE = 1U << 18, HAL_GDC_ONE_FRAME = 1U << 17, HAL_GDC_P_RGB3_18B = 1U << 12, HAL_GDC_P_RGB3_18B1 = 2U << 12, HAL_GDC_P_RGB3_16B = 3U << 12, HAL_GDC_P_RGB3_16B1 = 4U << 12, HAL_GDC_P_RGB3_16B2 = 5U << 12, HAL_GDC_CLKOUTDIV = 1U << 11, HAL_GDC_LVDSPADS = 1U << 10, HAL_GDC_YUVOUT = 1U << 9, HAL_GDC_MIPI_OFF = 1U << 4, HAL_GDC_OUTP_OFF = 1U << 3, HAL_GDC_LVDS_OFF = 1U << 2, HAL_GDC_SCANDOUBLE = 1U << 1, HAL_GDC_TESTMODE = 1U << 0, HAL_GDC_P_RGB3 = 0U << 5, HAL_GDC_S_RGBX4 = 1U << 5, HAL_GDC_S_RGB3 = 2U << 5, HAL_GDC_S_12BIT = 3U << 5, HAL_GDC_LVDS_ISP68 = 4U << 5, HAL_GDC_LVDS_ISP8 = 5U << 5, HAL_GDC_T_16BIT = 6U << 5, HAL_GDC_BT656 = 7U << 5, HAL_GDC_JDIMIP = 8U << 5, HAL_GDC_LUT8 = 1U << 20 }
| Layer video mode definition. More...
enum | hal_gdc_config_t { HAL_GDC_CFG_PALETTE = 1U << 0, HAL_GDC_CFG_FIXED_CURSOR = 1U << 1, HAL_GDC_CFG_PROGR_CURSOR = 1U << 2, HAL_GDC_CFG_DITHERING = 1U << 3, HAL_GDC_CFG_FORMAT = 1U << 4, HAL_GDC_CFG_HiQ_YUV = 1U << 5, HAL_GDC_CFG_DBIB = 1U << 6, HAL_GDC_CFG_YUVOUT = 1U << 7, HAL_GDC_CFG_L0_ENABLED = 1U << 8, HAL_GDC_CFG_L0_BLENDER = 1U << 9, HAL_GDC_CFG_L0_SCALER = 1U << 10, HAL_GDC_CFG_L0_GAMMA = 1U << 11, HAL_GDC_CFG_L1_ENABLED = 1U << 12, HAL_GDC_CFG_L1_BLENDER = 1U << 13, HAL_GDC_CFG_L1_SCALER = 1U << 14, HAL_GDC_CFG_L1_GAMMA = 1U << 15, HAL_GDC_CFG_L2_ENABLED = 1U << 16, HAL_GDC_CFG_L2_BLENDER = 1U << 17, HAL_GDC_CFG_L2_SCALER = 1U << 18, HAL_GDC_CFG_L2_GAMMA = 1U << 19, HAL_GDC_CFG_L3_ENABLED = 1U << 20, HAL_GDC_CFG_L3_BLENDER = 1U << 21, HAL_GDC_CFG_L3_SCALER = 1U << 22, HAL_GDC_CFG_L3_GAMMA = 1U << 23, HAL_GDC_CFG_SPI = 1U << 24, HAL_GDC_CFG_L0_YUVMEM = 1U << 28, HAL_GDC_CFG_L1_YUVMEM = 1U << 29, HAL_GDC_CFG_L2_YUVMEM = 1U << 30 }
| Layer configuration definition. More...
enum | hal_gdc_status_t { DC_STATUS_rsrvd_1 = (1U<<30), DC_STATUS_rsrvd_2 = (1U<<29), DC_STATUS_rsrvd_3 = (1U<<28), DC_STATUS_rsrvd_4 = (1U<<27), DC_STATUS_rsrvd_5 = (1U<<26), DC_STATUS_rsrvd_6 = (1U<<25), DC_STATUS_rsrvd_7 = (1U<<24), DC_STATUS_rsrvd_8 = (1U<<23), DC_STATUS_rsrvd_9 = (1U<<22), DC_STATUS_rsrvd_10 = (1U<<21), DC_STATUS_rsrvd_11 = (1U<<20), DC_STATUS_rsrvd_12 = (1U<<19), DC_STATUS_rsrvd_13 = (1U<<18), DC_STATUS_rsrvd_14 = (1U<<17), DC_STATUS_rsrvd_15 = (1U<<16), DC_STATUS_dbi_cmd_ready = (1U<<15), DC_STATUS_dbi_cs = (1U<<14), DC_STATUS_frame_end = (1U<<13), DC_STATUS_dbi_pending_trans = (1U<<12), DC_STATUS_dbi_pending_cmd = (1U<<11), DC_STATUS_dbi_pending_data = (1U<<10), DC_STATUS_dbi_busy =((1U<<16)|(1U<<14)|(1U<<13)|(1U<<12)|(1U<<11)|(1U<<10)), DC_STATUS_mmu_error = (1U<< 9), DC_STATUS_te = (1U<< 8), DC_STATUS_sticky = (1U<< 7), DC_STATUS_underflow = (1U<< 6), DC_STATUS_LASTROW = (1U<< 5), DC_STATUS_DPI_Csync = (1U<< 4), DC_STATUS_vsync_te = (1U<< 3), DC_STATUS_hsync = (1U<< 2), DC_STATUS_framegen_busy = (1U<< 1), DC_STATUS_ACTIVE = (1U<< 0) }
| DC status definition. More...
enum | hal_gdc_clkctrl_t { HAL_GDC_EN_PIXCLK = (1U<<22), HAL_GDC_EN_CFCLK = (1U<<23), HAL_GDC_EN_L0BUS = (1U<<24), HAL_GDC_EN_L0PIX = (1U<<25), HAL_GDC_EN_L1BUS = (1U<<26), HAL_GDC_EN_L1PIX = (1U<<27), HAL_GDC_EN_L2BUS = (1U<<28), HAL_GDC_EN_L2PIX = (1U<<29), HAL_GDC_EN_L3BUS = (1U<<30) }
| DC clock control definition. More...
enum | hal_gdc_clkctrl_cg_t { hal_gdc_clkctrl_cg_l3_pix_clk = (1U<<30), hal_gdc_clkctrl_cg_l2_bus_clk = (1U<<29), hal_gdc_clkctrl_cg_l2_pix_clk = (1U<<28), hal_gdc_clkctrl_cg_l1_bus_clk = (1U<<27), hal_gdc_clkctrl_cg_l1_pix_clk = (1U<<26), hal_gdc_clkctrl_cg_l0_bus_clk = (1U<<25), hal_gdc_clkctrl_cg_l0_pix_clk = (1U<<24), hal_gdc_clkctrl_cg_regfil_clk = (1U<<23), hal_gdc_clkctrl_cg_bypass_clk = (1U<<22), hal_gdc_clkctrl_cg_rsrvd_21 = (1U<<21), hal_gdc_clkctrl_cg_rsrvd_20 = (1U<<20), hal_gdc_clkctrl_cg_rsrvd_19 = (1U<<19), hal_gdc_clkctrl_cg_rsrvd_18 = (1U<<18), hal_gdc_clkctrl_cg_rsrvd_17 = (1U<<17), hal_gdc_clkctrl_cg_rsrvd_16 = (1U<<16), hal_gdc_clkctrl_cg_rsrvd_15 = (1U<<15), hal_gdc_clkctrl_cg_rsrvd_14 = (1U<<14), hal_gdc_clkctrl_cg_rsrvd_13 = (1U<<13), hal_gdc_clkctrl_cg_rsrvd_12 = (1U<<12), hal_gdc_clkctrl_cg_rsrvd_11 = (1U<<11), hal_gdc_clkctrl_cg_rsrvd_10 = (1U<<10), hal_gdc_clkctrl_cg_rsrvd_9 = (1U<< 9), hal_gdc_clkctrl_cg_rsrvd_8 = (1U<< 8), hal_gdc_clkctrl_cg_rsrvd_7 = (1U<< 7), hal_gdc_clkctrl_cg_rsrvd_6 = (1U<< 6), hal_gdc_clkctrl_cg_rsrvd_5 = (1U<< 5), hal_gdc_clkctrl_cg_rsrvd_4 = (1U<< 4), hal_gdc_clkctrl_cg_rsrvd_3 = (1U<< 3), hal_gdc_clkctrl_cg_clk_swap = (1U<< 2), hal_gdc_clkctrl_cg_clk_inv = (1U<< 1), hal_gdc_clkctrl_cg_clk_en = (1U<< 0) }
| DC clock cg control definition. More...

## Detailed Description

## Enumeration Type Documentation

## ◆ hal_gdc_blend_factors_t

enum hal_gdc_blend_factors_t

Layer blending factor definition.

Enumerator
HAL_GDC_BF_ZERO | Black.
HAL_GDC_BF_ONE | White.
HAL_GDC_BF_SRCALPHA | Alpha Source.
HAL_GDC_BF_GLBALPHA | Alpha Global.
HAL_GDC_BF_SRCGBLALPHA | Alpha Source And Alpha Global.
HAL_GDC_BF_INVSRCALPHA | Inverted Source.
HAL_GDC_BF_INVGBLALPHA | Inverted Global.
HAL_GDC_BF_INVSRCGBLALPHA | Inverted Source And Global.
HAL_GDC_BF_DSTALPHA | Alpha Destination.
HAL_GDC_BF_INVDSTALPHA | Inverted Destination.

Definition at line 102 of file hal_gdc.h.

## ◆ hal_gdc_blend_mode_t

enum hal_gdc_blend_mode_t

Layer blending mode definition.

Enumerator
HAL_GDC_BL_SIMPLE | Sa * Sa + Da * (1 - Sa)
HAL_GDC_BL_CLEAR | 0
HAL_GDC_BL_SRC | Sa.
HAL_GDC_BL_SRC_OVER | Sa + Da * (1 - Sa)
HAL_GDC_BL_DST_OVER | Sa * (1 - Da) + Da.
HAL_GDC_BL_SRC_IN | Sa * Da.
HAL_GDC_BL_DST_IN | Da * Sa.
HAL_GDC_BL_SRC_OUT | Sa * (1 - Da)
HAL_GDC_BL_DST_OUT | Da * (1 - Sa)
HAL_GDC_BL_SRC_ATOP | Sa * Da + Da * (1 - Sa)
HAL_GDC_BL_DST_ATOP | Sa * (1 - Da) + Da * Sa.
HAL_GDC_BL_ADD | Sa + Da.
HAL_GDC_BL_XOR | Sa * (1 - Da) + Da * (1 - Sa)

Definition at line 119 of file hal_gdc.h.

## ◆ hal_gdc_clkctrl_cg_t

enum hal_gdc_clkctrl_cg_t

DC clock cg control definition.

Enumerator
hal_gdc_clkctrl_cg_l3_pix_clk | layer 3 bus clock clock-gater bypass
hal_gdc_clkctrl_cg_l2_bus_clk | layer 2 bus clock clock-gater bypass
hal_gdc_clkctrl_cg_l2_pix_clk | layer 2 pixel clock clock-gater bypass
hal_gdc_clkctrl_cg_l1_bus_clk | layer 1 bus clock clock-gater bypass
hal_gdc_clkctrl_cg_l1_pix_clk | layer 1 pixel clock clock-gater bypass
hal_gdc_clkctrl_cg_l0_bus_clk | layer 0 bus clock clock-gater bypass
hal_gdc_clkctrl_cg_l0_pix_clk | layer 0 pixel clock clock-gater bypass
hal_gdc_clkctrl_cg_regfil_clk | RegFile clock-gaters bypass.
hal_gdc_clkctrl_cg_bypass_clk | Clock-gaters bypass.
hal_gdc_clkctrl_cg_rsrvd_21 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_20 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_19 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_18 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_17 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_16 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_15 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_14 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_13 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_12 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_11 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_10 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_9 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_8 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_7 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_6 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_5 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_4 | Reserved bit.
hal_gdc_clkctrl_cg_rsrvd_3 | Reserved bit.
hal_gdc_clkctrl_cg_clk_swap | Pixel generation and format clock swap.
hal_gdc_clkctrl_cg_clk_inv | Invert (ouput) clock polarity.
hal_gdc_clkctrl_cg_clk_en | Enable clock divider.

Definition at line 301 of file hal_gdc.h.

## ◆ hal_gdc_clkctrl_t

enum hal_gdc_clkctrl_t

DC clock control definition.

Enumerator
HAL_GDC_EN_PIXCLK | Resolution X.
HAL_GDC_EN_CFCLK | RegFile clock-gaters bypass.
HAL_GDC_EN_L0BUS | layer 0 bus clock clock-gater bypass
HAL_GDC_EN_L0PIX | layer 0 pixel clock clock-gater bypass
HAL_GDC_EN_L1BUS | layer 1 bus clock clock-gater bypass
HAL_GDC_EN_L1PIX | layer 1 pixel clock clock-gater bypass
HAL_GDC_EN_L2BUS | layer 2 bus clock clock-gater bypass
HAL_GDC_EN_L2PIX | layer 2 pixel clock clock-gater bypass
HAL_GDC_EN_L3BUS | layer 3 bus clock clock-gater bypass

Definition at line 285 of file hal_gdc.h.

## ◆ hal_gdc_config_t

enum hal_gdc_config_t

Layer configuration definition.

Enumerator
HAL_GDC_CFG_PALETTE | Global Gamma enabled.
HAL_GDC_CFG_FIXED_CURSOR | Fixed Cursor enabled.
HAL_GDC_CFG_PROGR_CURSOR | Programmable Cursor enabled.
HAL_GDC_CFG_DITHERING | Dithering enabled.
HAL_GDC_CFG_FORMAT | Formatting enabled.
HAL_GDC_CFG_HiQ_YUV | High Quality YUV converted enabled.
HAL_GDC_CFG_DBIB | DBI Type-B interface enabled.
HAL_GDC_CFG_YUVOUT | RGB to YUV converted.
HAL_GDC_CFG_L0_ENABLED | Layer 0 enabled.
HAL_GDC_CFG_L0_BLENDER | Layer 0 has blender.
HAL_GDC_CFG_L0_SCALER | Layer 0 has scaler.
HAL_GDC_CFG_L0_GAMMA | Layer 0 has gamma LUT.
HAL_GDC_CFG_L1_ENABLED | Layer 1 enabled.
HAL_GDC_CFG_L1_BLENDER | Layer 1 has blender.
HAL_GDC_CFG_L1_SCALER | Layer 1 has scaler.
HAL_GDC_CFG_L1_GAMMA | Layer 1 has gamma LUT.
HAL_GDC_CFG_L2_ENABLED | Layer 2 enabled.
HAL_GDC_CFG_L2_BLENDER | Layer 2 has blender.
HAL_GDC_CFG_L2_SCALER | Layer 2 has scaler.
HAL_GDC_CFG_L2_GAMMA | Layer 2 has gamma LUT.
HAL_GDC_CFG_L3_ENABLED | Layer 3 enabled.
HAL_GDC_CFG_L3_BLENDER | Layer 3 has blender.
HAL_GDC_CFG_L3_SCALER | Layer 3 has scaler.
HAL_GDC_CFG_L3_GAMMA | Layer 3 has gamma LUT.
HAL_GDC_CFG_SPI | SPI interface is enabled.
HAL_GDC_CFG_L0_YUVMEM | layer 0 has YUV Memory
HAL_GDC_CFG_L1_YUVMEM | layer 1 has YUV Memory
HAL_GDC_CFG_L2_YUVMEM | layer 2 has YUV Memory

Definition at line 211 of file hal_gdc.h.

## ◆ hal_gdc_format_t

enum hal_gdc_format_t

Layer color mode definition.

Enumerator
HAL_GDC_RGBA5551 | RGBA5551.
HAL_GDC_ABGR8888 | ABGR8888.
HAL_GDC_RGB332 | RGB332.
HAL_GDC_RGB565 | RGB565.
HAL_GDC_BGRA8888 | BGRA8888.
HAL_GDC_L8 | L8.
HAL_GDC_L1 | L1.
HAL_GDC_L4 | L4.
HAL_GDC_YUYV | YUYV.
HAL_GDC_RGB24 | RGB24.
HAL_GDC_YUY2 | YUY2.
HAL_GDC_RGBA8888 | RGBA8888.
HAL_GDC_ARGB8888 | ARGB8888.
HAL_GDC_V_YUV420 | V_YUV420.
HAL_GDC_TLYUV420 | TLYUV420.
HAL_GDC_TSC4 | TSC4.
HAL_GDC_TSC6 | TSC6.
HAL_GDC_TSC6A | TSC6A.
HAL_GDC_RGBA4444 | RGBA4444.
HAL_GDC_ARGB4444 | ARGB4444.

Definition at line 139 of file hal_gdc.h.

## ◆ hal_gdc_layer_ctrl_t

enum hal_gdc_layer_ctrl_t

Layer control definition.

Enumerator
HAL_GDC_LAYER_DISABLE | Disable Layer.
HAL_GDC_FORCE_A | Force Alpha.
HAL_GDC_SCALE_NN | Activate Bilinear Filter.
HAL_GDC_MODULATE_A | Modulate Alpha.
HAL_GDC_LAYER_AHBLOCK | Activate HLOCK signal on AHB DMAs.
HAL_GDC_LAYER_GAMMALUT_EN | Enable Gamma Look Up Table.

Definition at line 89 of file hal_gdc.h.

## ◆ hal_gdc_status_t

enum hal_gdc_status_t

DC status definition.

Enumerator
DC_STATUS_rsrvd_1 | Reserved bit.
DC_STATUS_rsrvd_2 | Reserved bit.
DC_STATUS_rsrvd_3 | Reserved bit.
DC_STATUS_rsrvd_4 | Reserved bit.
DC_STATUS_rsrvd_5 | Reserved bit.
DC_STATUS_rsrvd_6 | Reserved bit.
DC_STATUS_rsrvd_7 | Reserved bit.
DC_STATUS_rsrvd_8 | Reserved bit.
DC_STATUS_rsrvd_9 | Reserved bit.
DC_STATUS_rsrvd_10 | Reserved bit.
DC_STATUS_rsrvd_11 | Reserved bit.
DC_STATUS_rsrvd_12 | Reserved bit.
DC_STATUS_rsrvd_13 | Reserved bit.
DC_STATUS_rsrvd_14 | Reserved bit.
DC_STATUS_rsrvd_15 | Reserved bit.
DC_STATUS_dbi_cmd_ready | DBI i/f fifo full.
DC_STATUS_dbi_cs | DBI/SPI i/f active transaction.
DC_STATUS_frame_end | End of frame pulse.
DC_STATUS_dbi_pending_trans | pending command/data transaction
DC_STATUS_dbi_pending_cmd | pending command
DC_STATUS_dbi_pending_data | pending pixel data
DC_STATUS_dbi_busy | DBI i/f busy.
DC_STATUS_mmu_error | not implemented
DC_STATUS_te | tearing
DC_STATUS_sticky | underflow flag
DC_STATUS_underflow | underflow signal
DC_STATUS_LASTROW | last scan-row
DC_STATUS_DPI_Csync | DPI C-sync.
DC_STATUS_vsync_te | Vsync or Tearing.
DC_STATUS_hsync | Hsync.
DC_STATUS_framegen_busy | Frame-generation in-progress.
DC_STATUS_ACTIVE | active

Definition at line 246 of file hal_gdc.h.

## ◆ hal_gdc_videomode_t

enum hal_gdc_videomode_t

Layer video mode definition.

Enumerator
HAL_GDC_DISABLE | DISABLE.
HAL_GDC_CURSOR | CURSOR.
HAL_GDC_NEG_V | NEG_V.
HAL_GDC_NEG_H | NEG_H.
HAL_GDC_NEG_DE | NEG_DE.
HAL_GDC_DITHER | DITHER 18-bit.
HAL_GDC_DITHER16 | DITHER 16-bit.
HAL_GDC_DITHER15 | DITHER 15-bit.
HAL_GDC_SINGLEV | SINGLEV.
HAL_GDC_INVPIXCLK | INVPIXCLK.
HAL_GDC_PALETTE | PALETTE.
HAL_GDC_GAMMA | GAMMA.
HAL_GDC_BLANK | BLANK.
HAL_GDC_INTERLACE | INTERLACE.
HAL_GDC_ONE_FRAME | ONE_FRAME.
HAL_GDC_P_RGB3_18B | P_RGB3.
HAL_GDC_P_RGB3_18B1 | P_RGB3.
HAL_GDC_P_RGB3_16B | P_RGB3.
HAL_GDC_P_RGB3_16B1 | P_RGB3.
HAL_GDC_P_RGB3_16B2 | P_RGB3.
HAL_GDC_CLKOUTDIV | CLKOUTDIV.
HAL_GDC_LVDSPADS | LVDSPADS.
HAL_GDC_YUVOUT | YUVOUT.
HAL_GDC_MIPI_OFF | MIPI_OFF.
HAL_GDC_OUTP_OFF | OUTP_OFF.
HAL_GDC_LVDS_OFF | LVDS_OFF.
HAL_GDC_SCANDOUBLE | SCANDOUBLE.
HAL_GDC_TESTMODE | TESTMODE.
HAL_GDC_P_RGB3 | P_RGB3.
HAL_GDC_S_RGBX4 | S_RGBX4.
HAL_GDC_S_RGB3 | S_RGB3.
HAL_GDC_S_12BIT | S_12BIT.
HAL_GDC_LVDS_ISP68 | LVDS_ISP68.
HAL_GDC_LVDS_ISP8 | LVDS_ISP8.
HAL_GDC_T_16BIT | T_16BIT.
HAL_GDC_BT656 | BT656.
HAL_GDC_JDIMIP | JDIMIP.
HAL_GDC_LUT8 | LUT8.

Definition at line 166 of file hal_gdc.h.