Macros
Default System Clock Specify
Peripheral Driver » LL Driver » CGC » Defines » CGC Exported Constants

Specify the default system clock when the system is initialized. More...

+ Collaboration diagram for Default System Clock Specify:

Macros

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0
 Hclk0 for the system default clock WFI/WFE. More...
 
#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1
 Hclk1 for the system default clock WFI/WFE. More...
 
#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK
 Hclk for the system default clock
More...
 
#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK1   (MCU_SUB_FORCE_SECU_DIV4_PCLK)
 Hclk for the system default clock
More...
 
#define LL_CGC_MCU_PERIPH_CG_DEFAULT
 pclk for the system default periph clock
More...
 
#define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT
 pclk for the system default periph wfi clock
More...
 
#define CGC_CLOCK_ENABLE   (1)
 Bit segment address enable
More...
 
#define CGC_CLOCK_DISABLE   (0)
 Bit segment address disable
More...
 
#define BIT_BAND(addr, bitnum)   (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2))
 Bit segment address calculation
More...
 
#define MEMORY_ADDR(addr)   (*((volatile uint32_t *)(addr)))
 Bit segment address type conversion
More...
 
#define BIT_SEGMENT_VALUE(addr, bitnum)   MEMORY_ADDR(BIT_BAND(addr, bitnum))
 Bit segment address value manipulation
More...
 

Detailed Description

Specify the default system clock when the system is initialized.

Macro Definition Documentation

◆ BIT_BAND

#define BIT_BAND (   addr,
  bitnum 
)    (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2))

Bit segment address calculation

Definition at line 333 of file gr55xx_ll_cgc.h.

◆ BIT_SEGMENT_VALUE

#define BIT_SEGMENT_VALUE (   addr,
  bitnum 
)    MEMORY_ADDR(BIT_BAND(addr, bitnum))

Bit segment address value manipulation

Definition at line 335 of file gr55xx_ll_cgc.h.

◆ CGC_CLOCK_DISABLE

#define CGC_CLOCK_DISABLE   (0)

Bit segment address disable

Definition at line 325 of file gr55xx_ll_cgc.h.

◆ CGC_CLOCK_ENABLE

#define CGC_CLOCK_ENABLE   (1)

Bit segment address enable

Definition at line 324 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_PERIPH_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_CG_DEFAULT
Value:
(LL_CGC_FRC_UART0_PCLK |\
LL_CGC_FRC_UART1_PCLK |\
LL_CGC_FRC_UART2_PCLK |\
LL_CGC_FRC_UART3_PCLK |\
LL_CGC_FRC_UART4_PCLK |\
LL_CGC_FRC_UART5_PCLK |\
LL_CGC_FRC_I2C0_PCLK |\
LL_CGC_FRC_I2C1_PCLK |\
LL_CGC_FRC_I2C2_PCLK |\
LL_CGC_FRC_I2C3_PCLK |\
LL_CGC_FRC_I2C4_PCLK |\
LL_CGC_FRC_I2C5_PCLK |\
LL_CGC_FRC_QSPI0_PCLK |\
LL_CGC_FRC_QSPI1_PCLK |\
LL_CGC_FRC_QSPI2_PCLK |\
LL_CGC_FRC_SPI_M_PCLK |\
LL_CGC_FRC_SPI_S_PCLK |\
LL_CGC_FRC_I2S_HCLK |\
LL_CGC_FRC_I2S_S_PCLK |\
LL_CGC_FRC_DSPI_PCLK |\
LL_CGC_FRC_PDM_PCLK |\
LL_CGC_FRC_PWM_0_PCLK |\
LL_CGC_FRC_PWM_1_PCLK)

pclk for the system default periph clock

Definition at line 298 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT
Value:
(MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART4 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART5 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PDM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5)

pclk for the system default periph wfi clock

Definition at line 322 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_SUBSYS_DEFAULT_CLK

#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK
Value:
(LL_CGC_FRC_SECU_HCLK |\
LL_CGC_FRC_SIM_HCLK |\
LL_CGC_FRC_SNSADC_HCLK |\
LL_CGC_FRC_SERIAL_HCLK)

Hclk for the system default clock

Definition at line 271 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_SUBSYS_DEFAULT_CLK1

#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK1   (MCU_SUB_FORCE_SECU_DIV4_PCLK)

Hclk for the system default clock

Definition at line 273 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0
Value:
(LL_CGC_WFI_SECU_HCLK |\
LL_CGC_WFI_SIM_HCLK |\
LL_CGC_WFI_PWM_HCLK |\
LL_CGC_WFI_SNSADC_HCLK |\
LL_CGC_WFI_GPIO_HCLK |\
LL_CGC_WFI_BLE_BRG_HCLK |\
LL_CGC_WFI_SERIAL_HCLK)

Hclk0 for the system default clock WFI/WFE.

Definition at line 261 of file gr55xx_ll_cgc.h.

◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1
Value:
(LL_CGC_WFI_AON_MCUSUB_HCLK |\
LL_CGC_WFI_XF_XQSPI_HCLK |\
LL_CGC_WFI_SRAM_HCLK)

Hclk1 for the system default clock WFI/WFE.

Definition at line 265 of file gr55xx_ll_cgc.h.

◆ MEMORY_ADDR

#define MEMORY_ADDR (   addr)    (*((volatile uint32_t *)(addr)))

Bit segment address type conversion

Definition at line 334 of file gr55xx_ll_cgc.h.

LL_CGC_WFI_SECU_HCLK
#define LL_CGC_WFI_SECU_HCLK
Hclk for all security blocks
Definition: gr55xx_ll_cgc.h:74
LL_CGC_FRC_SECU_HCLK
#define LL_CGC_FRC_SECU_HCLK
Hclk for all security blocks
Definition: gr55xx_ll_cgc.h:111
LL_CGC_WFI_AON_MCUSUB_HCLK
#define LL_CGC_WFI_AON_MCUSUB_HCLK
Hclk for Always-on register
Definition: gr55xx_ll_cgc.h:91
LL_CGC_FRC_UART0_PCLK
#define LL_CGC_FRC_UART0_PCLK
Pclk for uart0
Definition: gr55xx_ll_cgc.h:137