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| enum | hal_gdc_colormode_check_t {
HAL_GDC_DBIB_STALL_CHK = 1 << 31,
HAL_GDC_OPENLDI_CHK = 1U << 30,
HAL_GDC_JDIMIP_CHK = 1U << 29,
HAL_GDC_ARGB4444_CHK = 1U << 22,
HAL_GDC_RGBA4444_CHK = 1U << 21,
HAL_GDC_GPI_CHK = 1U << 20,
HAL_GDC_EXTRCTRL_CHK = 1U << 19,
HAL_GDC_TSC6_CHK = 1U << 18,
HAL_GDC_TSC_CHK = 1U << 17,
HAL_GDC_LUT8_CHK = 1U << 16,
HAL_GDC_RGBA5551_CHK = 1U << 15,
HAL_GDC_ABGR8888_CHK = 1U << 14,
HAL_GDC_RGB332_CHK = 1U << 13,
HAL_GDC_RGB565_CHK = 1U << 12,
HAL_GDC_BGRA8888_CHK = 1U << 11,
HAL_GDC_L8_CHK = 1U << 10,
HAL_GDC_L1_CHK = 1U << 9,
HAL_GDC_L4_CHK = 1U << 8,
HAL_GDC_YUVV_CHK = 1U << 7,
HAL_GDC_RGB24_CHK = 1U << 6,
HAL_GDC_YUY2_CHK = 1U << 5,
HAL_GDC_RGBA8888_CHK = 1U << 4,
HAL_GDC_ARGB8888_CHK = 1U << 3,
HAL_GDC_V_YUV420_CHK = 1U << 2,
HAL_GDC_TLYUV420_CHK = 1U << 1,
HAL_GDC_BLOCK4X4_CHK = 1U << 0
} |
| | DC's color mode check definition. More...
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| |
| enum | hal_gdc_AXI_cfg_t {
HAL_GDC_AXI_16BEAT = 0x0,
HAL_GDC_AXI_2BEAT = 0x1,
HAL_GDC_AXI_4BEAT = 0x2,
HAL_GDC_AXI_8BEAT = 0x3,
HAL_GDC_AXI_32BEAT = 0x5,
HAL_GDC_AXI_64BEAT = 0x6,
HAL_GDC_AXI_128BEAT = 0x7,
HAL_GDC_AXI_FT_HF = 0x0U << 3,
HAL_GDC_AXI_FT_2B = 0x1U << 3,
HAL_GDC_AXI_FT_4B = 0x2U << 3,
HAL_GDC_AXI_FT_8B = 0x3U << 3
} |
| | AXI control definition. More...
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| |
| enum | dc_mipi_cmd_t {
hal_gdc_snapshot = 0xff,
hal_gdc_store_base_addr = (1 <<31),
hal_gdc_DBI_cmd = (1U<<30),
hal_gdc_wcmd16 = (1U<<28),
hal_gdc_wcmd24 = (1U<<29),
hal_gdc_wcmd32 = (1U<<29)|(1U<<28),
hal_gdc_rcmd16 = (1U<<28),
hal_gdc_rcmd24 = (1U<<29),
hal_gdc_rcmd32 = (1U<<29)|(1U<<28),
hal_gdc_mask_qspi = (1U<<27),
hal_gdc_DBI_ge = (1U<<27),
hal_gdc_DBI_read = (1U<<26),
hal_gdc_ext_ctrl = (1U<<25),
hal_gdc_sline_cmd = (1U<<24),
hal_gdc_read_byte = (0U<<30),
hal_gdc_read_2byte = (1U<<30),
hal_gdc_read_3byte = (2 <<30),
hal_gdc_read_4byte = (3 <<30)
} |
| | MIPI CMD definition. More...
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| |
Collaboration diagram for Enumerations: