Header file containing functions prototypes of I2S LL library. More...
#include "gr55xx.h"
Include dependency graph for gr55xx_ll_i2s.h: This graph shows which files directly or indirectly include this file:Go to the source code of this file.
Classes | |
| struct | _ll_i2s_init_t |
| LL I2S init structures definition. More... | |
Macros | |
| #define | LL_I2S_STATUS_TXFO I2S_INT_STAT_TX_FIFO_OVER |
| TX FIFO write overflow flag More... | |
| #define | LL_I2S_STATUS_TXFE I2S_INT_STAT_TX_FIFO_EMPTY |
| TX FIFO threshold level is not reached flag. More... | |
| #define | LL_I2S_STATUS_RXFO I2S_INT_STAT_RX_FIFO_OVER |
| RX FIFO receive overflow flag More... | |
| #define | LL_I2S_STATUS_RXDA I2S_INT_STAT_RX_DATA_AVL |
| RX FIFO threshold level is reached flag More... | |
| #define | LL_I2S_INT_TXFO I2S_INT_MASK_TX_FOM |
| TX FIFO write overflow interrupt More... | |
| #define | LL_I2S_INT_TXFE I2S_INT_MASK_TX_FEM |
| TX FIFO threshold level is not reached interrupt. More... | |
| #define | LL_I2S_INT_RXFO I2S_INT_MASK_RX_FOM |
| RX FIFO receive overflow interrupt More... | |
| #define | LL_I2S_INT_RXDA I2S_INT_MASK_RX_DAM |
| RX FIFO threshold level is reached interrupt More... | |
| #define | LL_I2S_CLOCK_SRC_96M (0x00000000UL) |
| I2S clock source select: 96M More... | |
| #define | LL_I2S_CLOCK_SRC_64M (1UL << 18) |
| I2S clock source select: 64M More... | |
| #define | LL_I2S_CLOCK_SRC_32M (2UL << 18) |
| I2S clock source select: 32M More... | |
| #define | LL_I2S_DATASIZE_IGNORE (0x00000000UL) |
| Data size for I2S transfer: 32 bits. More... | |
| #define | LL_I2S_DATASIZE_12BIT (1UL << I2S_RX_CFG_WORD_LEN_POS) |
| Data size for I2S transfer: 12 bits. More... | |
| #define | LL_I2S_DATASIZE_16BIT (2UL << I2S_RX_CFG_WORD_LEN_POS) |
| Data size for I2S transfer: 16 bits. More... | |
| #define | LL_I2S_DATASIZE_20BIT (3UL << I2S_RX_CFG_WORD_LEN_POS) |
| Data size for I2S transfer: 20 bits. More... | |
| #define | LL_I2S_DATASIZE_24BIT (4UL << I2S_RX_CFG_WORD_LEN_POS) |
| Data size for I2S transfer: 24 bits. More... | |
| #define | LL_I2S_DATASIZE_32BIT (5UL << I2S_RX_CFG_WORD_LEN_POS) |
| Data size for I2S transfer: 32 bits. More... | |
| #define | LL_I2S_SIMPLEX_TX (1UL) |
| Simplex TX mode. More... | |
| #define | LL_I2S_SIMPLEX_RX (2UL) |
| Simplex RX mode. More... | |
| #define | LL_I2S_FULL_DUPLEX (3UL) |
| Full-Duplex mode. More... | |
| #define | LL_I2S_THRESHOLD_1FIFO (0x00000000UL) |
| Trigger level for FIFO: 1 depth. More... | |
| #define | LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 2 depth. More... | |
| #define | LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 3 depth. More... | |
| #define | LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 4 depth. More... | |
| #define | LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 5 depth. More... | |
| #define | LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 6 depth. More... | |
| #define | LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 7 depth. More... | |
| #define | LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 8 depth. More... | |
| #define | LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 9 depth. More... | |
| #define | LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 10 depth. More... | |
| #define | LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 11 depth. More... | |
| #define | LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 12 depth. More... | |
| #define | LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 13 depth. More... | |
| #define | LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 14 depth. More... | |
| #define | LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 15 depth. More... | |
| #define | LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS) |
| Trigger level for FIFO: 16 depth. More... | |
| #define | LL_I2S_WS_CYCLES_16 (0x00000000UL) |
| 16 SCLK cycles in word select line. More... | |
| #define | LL_I2S_WS_CYCLES_24 (0x1UL << I2S_SCLK_CFG_WS_SCLK_POS) |
| 24 SCLK cycles in word select line. More... | |
| #define | LL_I2S_WS_CYCLES_32 (0x2UL << I2S_SCLK_CFG_WS_SCLK_POS) |
| 32 SCLK cycles in word select line. More... | |
| #define | LL_I2S_SCLKG_NONE (0x00000000UL) |
| Clock gating is disabled. More... | |
| #define | LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_SCLK_CFG_SCLK_GAT_POS) |
| Gating after 12 sclk cycles. More... | |
| #define | LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_SCLK_CFG_SCLK_GAT_POS) |
| Gating after 16 sclk cycles. More... | |
| #define | LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_SCLK_CFG_SCLK_GAT_POS) |
| Gating after 20 sclk cycles. More... | |
| #define | LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_SCLK_CFG_SCLK_GAT_POS) |
| Gating after 24 sclk cycles. More... | |
| #define | LL_I2S_RESOLUTION_12BIT (0UL) |
| 12 bits resolution. More... | |
| #define | LL_I2S_RESOLUTION_16BIT (1UL) |
| 16 bits resolution. More... | |
| #define | LL_I2S_RESOLUTION_20BIT (2UL) |
| 20 bits resolution. More... | |
| #define | LL_I2S_RESOLUTION_24BIT (3UL) |
| 24 bits resolution. More... | |
| #define | LL_I2S_RESOLUTION_32BIT (4UL) |
| 32 bits resolution. More... | |
| #define | LL_I2S_CHANNEL_NUM_1 (0UL) |
| 1 channel. More... | |
| #define | LL_I2S_CHANNEL_NUM_2 (1UL) |
| 2 channels. More... | |
| #define | LL_I2S_CHANNEL_NUM_3 (2UL) |
| 3 channels. More... | |
| #define | LL_I2S_CHANNEL_NUM_4 (3UL) |
| 4 channels. More... | |
| #define | LL_I2S_FIFO_DEPTH_2 (0UL) |
| FIFO depth is 2 . More... | |
| #define | LL_I2S_FIFO_DEPTH_4 (1UL) |
| FIFO depth is 4 . More... | |
| #define | LL_I2S_FIFO_DEPTH_8 (2UL) |
| FIFO depth is 8 . More... | |
| #define | LL_I2S_FIFO_DEPTH_16 (3UL) |
| FIFO depth is 16. More... | |
| #define | LL_I2S_APB_WIDTH_8BIT (0UL) |
| 8 bits APB data width. More... | |
| #define | LL_I2S_APB_WIDTH_16BIT (1UL) |
| 16 bits APB data width. More... | |
| #define | LL_I2S_APB_WIDTH_32BIT (2UL) |
| 32 bits APB data width. More... | |
| #define | LL_I2S_DEFAULT_CONFIG |
| LL I2S InitStrcut default configuartion. More... | |
| #define | LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__)) |
| Write a value in I2S register. More... | |
| #define | LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__) |
| Read a value in I2S register. More... | |
Typedefs | |
| typedef struct _ll_i2s_init_t | ll_i2s_init_t |
| LL I2S init structures definition. More... | |
Functions | |
| __STATIC_INLINE void | ll_i2s_enable (i2s_regs_t *I2Sx) |
| Enable I2S. More... | |
| __STATIC_INLINE void | ll_i2s_disable (i2s_regs_t *I2Sx) |
| Disable I2S. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled (i2s_regs_t *I2Sx) |
| Check if I2S is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_enable_rxblock (i2s_regs_t *I2Sx) |
| Enable I2S RX block. More... | |
| __STATIC_INLINE void | ll_i2s_disable_rxblock (i2s_regs_t *I2Sx) |
| Disable I2S RX block. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_rxblock (i2s_regs_t *I2Sx) |
| Check if I2S RX block is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_enable_txblock (i2s_regs_t *I2Sx) |
| Enable I2S TX block. More... | |
| __STATIC_INLINE void | ll_i2s_disable_txblock (i2s_regs_t *I2Sx) |
| Disable I2S TX block. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_txblock (i2s_regs_t *I2Sx) |
| Check if I2S TX block is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_enable_clock (i2s_regs_t *I2Sx) |
| Enable I2S clock. More... | |
| __STATIC_INLINE void | ll_i2s_disable_clock (i2s_regs_t *I2Sx) |
| Disable I2S clock. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_clock (i2s_regs_t *I2Sx) |
| Check if I2S clock is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_set_wss (i2s_regs_t *I2Sx, uint32_t cycles) |
| Set word select line cycles for left or right sample. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_wss (i2s_regs_t *I2Sx) |
| Get word select line cycles for left or right sample. More... | |
| __STATIC_INLINE void | ll_i2s_set_sclkg (i2s_regs_t *I2Sx, uint32_t cycles) |
| Set the gating of sclk. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_sclkg (i2s_regs_t *I2Sx) |
| Get the gating of sclk. More... | |
| __STATIC_INLINE void | ll_i2s_clr_rxfifo_all (i2s_regs_t *I2Sx) |
| Clear I2S RX FIFO in all channels. More... | |
| __STATIC_INLINE void | ll_i2s_clr_txfifo_all (i2s_regs_t *I2Sx) |
| Clear I2S TX FIFO in all channels. More... | |
| __STATIC_INLINE void | ll_i2s_set_clock_div (uint32_t div) |
| Set I2S clock divider. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_clock_div (void) |
| Get I2S clock divider. More... | |
| __STATIC_INLINE void | ll_i2s_enable_clock_div (void) |
| Enable I2S clock divider. More... | |
| __STATIC_INLINE void | ll_i2s_disable_clock_div (void) |
| Disable I2S clock divider. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_clock_div (void) |
| Check if I2S clock divider is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_set_clock_src (uint32_t src) |
| Set I2S clock source. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_clock_src (void) |
| Get I2S clock source. More... | |
| __STATIC_INLINE void | ll_i2s_enable_src_clock (void) |
| Enable I2S clock. More... | |
| __STATIC_INLINE void | ll_i2s_disable_src_clock (void) |
| Disable I2S clock divider. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_src_clock (void) |
| Check if I2S clock divider is enabled. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_receive_ldata (i2s_regs_t *I2Sx) |
| Read one data from left RX FIFO in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_receive_rdata (i2s_regs_t *I2Sx) |
| Read one data from right RX FIFO in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_transmit_ldata (i2s_regs_t *I2Sx, uint32_t data) |
| Write one data to left TX FIFO in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_transmit_rdata (i2s_regs_t *I2Sx, uint32_t data) |
| Write one data to right TX FIFO in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_enable_rx (i2s_regs_t *I2Sx) |
| Enable RX in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_disable_rx (i2s_regs_t *I2Sx) |
| Disable RX in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_rx (i2s_regs_t *I2Sx) |
| Check if RX in a channel is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_enable_tx (i2s_regs_t *I2Sx) |
| Enable TX in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_disable_tx (i2s_regs_t *I2Sx) |
| Disable TX in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_tx (i2s_regs_t *I2Sx) |
| Check if TX in a channel is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_set_rxsize (i2s_regs_t *I2Sx, uint32_t size) |
| Set receive data width in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_rxsize (i2s_regs_t *I2Sx) |
| Get receive data width in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_set_txsize (i2s_regs_t *I2Sx, uint32_t size) |
| Set transmit data width in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_txsize (i2s_regs_t *I2Sx) |
| Get transmit data width in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_it_flag (i2s_regs_t *I2Sx) |
| Get interrupt flag in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_active_it_flag (i2s_regs_t *I2Sx, uint32_t flag) |
| Check interrupt flag in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_enable_it (i2s_regs_t *I2Sx, uint32_t mask) |
| Enable interrupt in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_disable_it (i2s_regs_t *I2Sx, uint32_t mask) |
| Disable interrupt in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_it (i2s_regs_t *I2Sx, uint32_t mask) |
| Check if interrupt in a channel is enabled. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_clear_it_rxovr (i2s_regs_t *I2Sx) |
| Clear RX FIFO data overrun interrupt flag in a channel. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_clear_it_txovr (i2s_regs_t *I2Sx) |
| Clear TX FIFO data overrun interrupt flag in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_set_rx_fifo_threshold (i2s_regs_t *I2Sx, uint32_t threshold) |
| Set threshold of RXFIFO in a channel that triggers an RXDA event. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_rx_fifo_threshold (i2s_regs_t *I2Sx) |
| Get threshold of RXFIFO in a channel that triggers an RXDA event. More... | |
| __STATIC_INLINE void | ll_i2s_set_tx_fifo_threshold (i2s_regs_t *I2Sx, uint32_t threshold) |
| Set threshold of TXFIFO in a channel that triggers an TXFE event. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_get_tx_fifo_threshold (i2s_regs_t *I2Sx) |
| Get threshold of TXFIFO in a channel that triggers an TXFE event. More... | |
| __STATIC_INLINE void | ll_i2s_clr_rxfifo_channel (i2s_regs_t *I2Sx) |
| Clear RX FIFO data in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_clr_txfifo_channel (i2s_regs_t *I2Sx) |
| Clear TX FIFO data in a channel. More... | |
| __STATIC_INLINE void | ll_i2s_rst_rxdma (i2s_regs_t *I2Sx) |
| Reset RX block DMA. More... | |
| __STATIC_INLINE void | ll_i2s_rst_txdma (i2s_regs_t *I2Sx) |
| Reset TX block DMA. More... | |
| __STATIC_INLINE void | ll_i2s_enable_dma (i2s_regs_t *I2Sx) |
| Enable I2S DMA. More... | |
| __STATIC_INLINE void | ll_i2s_disable_dma (i2s_regs_t *I2Sx) |
| Disable I2S DMA. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_dma (i2s_regs_t *I2Sx) |
| Check if I2S DMA is enabled. More... | |
| __STATIC_INLINE void | ll_i2s_enable_dma_mode (i2s_regs_t *I2Sx) |
| Enable I2S DMA mode. More... | |
| __STATIC_INLINE void | ll_i2s_disable_dma_mode (i2s_regs_t *I2Sx) |
| Disable I2S DMA mode. More... | |
| __STATIC_INLINE uint32_t | ll_i2s_is_enabled_dma_mode (i2s_regs_t *I2Sx) |
| Check if I2S DMA mode is enabled. More... | |
| error_status_t | ll_i2s_deinit (i2s_regs_t *I2Sx) |
| De-initialize I2S registers (Registers restored to their default values). More... | |
| error_status_t | ll_i2s_init (i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init) |
| Initialize I2S_M registers according to the specified parameters in p_i2s_init. More... | |
| void | ll_i2s_struct_init (ll_i2s_init_t *p_i2s_init) |
| Set each field of a ll_i2s_init_t type structure to default value. More... | |
Header file containing functions prototypes of I2S LL library.
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Definition in file gr55xx_ll_i2s.h.