52 #ifndef __GR55XX_LL_DDVS_H_
53 #define __GR55XX_LL_DDVS_H_
69 #define LL_DDVS_DIS (0U)
70 #define LL_DDVS_EN (1U)
76 #define LL_DDVS_AUTO_MODE (0U)
77 #define LL_DDVS_MALNUAL_MODE (1U)
83 #define LL_DDVS_RINGO_0_EN (1<<0U)
84 #define LL_DDVS_RINGO_1_EN (1<<1U)
85 #define LL_DDVS_RINGO_2_EN (1<<2U)
86 #define LL_DDVS_RINGO_3_EN (1<<3U)
87 #define LL_DDVS_RINGO_ALL_EN (0xFU)
88 #define LL_DDVS_RINGO_ALL_DIS (0x0U)
94 #define LL_DDVS_DIVIDE_FACTOR_8K (0U)
95 #define LL_DDVS_DIVIDE_FACTOR_4K (1U)
96 #define LL_DDVS_DIVIDE_FACTOR_16K (2U)
102 #define LL_DDVS_CLK_SEL_XO_32M (0U)
103 #define LL_DDVS_CLK_SEL_XO_16M (1U)
104 #define LL_DDVS_CLK_SEL_SYS_32M (2U)
105 #define LL_DDVS_CLK_SEL_SYS_16M (3U)
111 #define LL_DDVS_CLK_DIS (0U)
112 #define LL_DDVS_CLK_EN (1U)
129 MODIFY_REG(DDVS_CTRL->DDVS_EN, DDVS_CTRL_CONF_DDVS_EN, (enable << DDVS_CTRL_CONF_DDVS_EN_POS));
141 return ((READ_BITS(DDVS_CTRL->DDVS_EN, DDVS_CTRL_CONF_DDVS_EN)) >> DDVS_CTRL_CONF_DDVS_EN_POS);
154 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE, (mode << DDVS_CFG_1_CONF_DDVS_MODE_POS));
167 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE)) >> DDVS_CFG_1_CONF_DDVS_MODE_POS);
179 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_THRESHOLD_SLOW, (threshold << DDVS_CFG_1_CONF_THRESHOLD_SLOW_POS));
191 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_THRESHOLD_SLOW)) >> DDVS_CFG_1_CONF_THRESHOLD_SLOW_POS);
203 MODIFY_REG(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_TARGET_CNT, (target_cnt << DDVS_CFG_2_CONF_TARGET_CNT_POS));
215 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_TARGET_CNT)) >> DDVS_CFG_2_CONF_TARGET_CNT_POS);
227 MODIFY_REG(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_THRESHOLD_FAST, (threshold << DDVS_CFG_2_CONF_THRESHOLD_FAST_POS));
239 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_THRESHOLD_FAST)) >> DDVS_CFG_2_CONF_THRESHOLD_FAST_POS);
251 SET_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_INT_EN);
263 CLEAR_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_INT_EN);
276 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE, (
LL_DDVS_MALNUAL_MODE << DDVS_CFG_1_CONF_DDVS_MODE_POS));
277 CLEAR_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_ERR_INT);
289 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_VREF_MANUAL, (vref << DDVS_CFG_1_CONF_VREF_MANUAL_POS));
301 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_VREF_MANUAL)) >> DDVS_CFG_1_CONF_VREF_MANUAL_POS);
314 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_RINGO_EN, (ringo_bits << DDVS_CFG_1_CONF_RINGO_EN_POS));
327 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_RINGO_EN)) >> DDVS_CFG_1_CONF_RINGO_EN_POS);
342 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DIV_FACTOR, (factor<<DDVS_CFG_1_CONF_DIV_FACTOR_POS));
357 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DIV_FACTOR)) >> DDVS_CFG_1_CONF_DIV_FACTOR_POS);
368 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_01, DDVS_RINGO_CNT_01_RINGO_0_CNT)) >> DDVS_RINGO_CNT_01_RINGO_0_CNT_POS);
379 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_01, DDVS_RINGO_CNT_01_RINGO_1_CNT)) >> DDVS_RINGO_CNT_01_RINGO_1_CNT_POS);
390 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_23, DDVS_RINGO_CNT_23_RINGO_2_CNT)) >> DDVS_RINGO_CNT_23_RINGO_2_CNT_POS);
401 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_23, DDVS_RINGO_CNT_23_RINGO_3_CNT)) >> DDVS_RINGO_CNT_23_RINGO_3_CNT_POS);
412 return ((READ_BITS(DDVS_CTRL->DDVS_FSM, DDVS_FSM_STS_FSM_CURR)) >> DDVS_FSM_STS_FSM_CURR_POS);
423 MODIFY_REG(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_EN, (enable << DDVS_CLK_CTRL_DDVS_CLK_EN_POS));
434 return ((READ_BITS(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_EN)) >> DDVS_CLK_CTRL_DDVS_CLK_EN_POS);
446 MODIFY_REG(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_SEL, (clk_sel<<DDVS_CLK_CTRL_DDVS_CLK_SEL_POS));
458 return ((READ_BITS(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_SEL)) >> DDVS_CLK_CTRL_DDVS_CLK_SEL_POS);