gr55xx_ll_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (DMA) || defined (DMA0) || defined (DMA1)
63
64
65 /** @defgroup DMA_LL_STRUCTURES Structures
66 * @{
67 */
68
69 /* Exported types ------------------------------------------------------------*/
70 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
71 * @{
72 */
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init
77 {
78 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
79
80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
81
82 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory or form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t mode; /**< Specifies the Single block or Multi-block operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref ll_dma_set_mode(). */
98
99 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
100 This parameter can be a value of @ref DMA_LL_EC_SOURCE
101
102 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_increment_mode(). */
103
104 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
105 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
106
107 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_increment_mode(). */
108
109 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
110 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
111
112 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_width(). */
113
114 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
115 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_width(). */
118
119 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
120 The data unit is equal to the source buffer configuration set in src_data_width parameters.
121 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFF
122
123 This feature can be modified afterwards using unitary function @ref ll_dma_set_block_size(). */
124
125 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
126 This parameter can be a value of @ref DMA_LL_EC_PERIPH
127
128 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_peripheral(). */
129
130 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
131 This parameter can be a value of @ref DMA_LL_EC_PERIPH
132
133 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_peripheral(). */
134
135 uint32_t priority; /**< Specifies the channel priority level.
136 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref ll_dma_set_channel_priority_level(). */
139 } ll_dma_init_t;
140
141 /** @} */
142
143 /** @} */
144
145 /**
146 * @defgroup DMA_LL_MACRO Defines
147 * @{
148 */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
152 * @{
153 */
154
155 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
156 * @{
157 */
158 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
159 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
160 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
161 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
162 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
163 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /**< DMA Channel 5 */
164 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /**< DMA Channel 6 */
165 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /**< DMA Channel 7 */
166 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all (used only for function @ref ll_dma_deinit(). */
167 /** @} */
168
169 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
170 * @{
171 */
172 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
173 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
174 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
175 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
176 /** @} */
177
178
179 /** @defgroup DMA_LL_EC_MODE Transfer mode
180 * @{
181 */
182 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U) /**< Single block */
183 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC /**< Multi-block: src address reload, dst address contiguous */
184 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST /**< Multi-block: src address contiguous, dst address reload */
185 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST) /**< Multi-block: src address reload, dst address reload */
186 /** @} */
187
188 /** @defgroup DMA_LL_EC_LLP_DST Destination LLP Enable
189 * @{
190 */
191 #define LL_DMA_LLP_DST_ENABLE DMA_CTLL_LLP_DST_EN_ENABLE /**< Destination LLP Enable */
192 #define LL_DMA_LLP_DST_DISABLE DMA_CTLL_LLP_DST_EN_DISABLE /**< Destination LLP Disable */
193 /** @} */
194
195 /** @defgroup DMA_LL_EC_LLP_SRC Source LLP Enable
196 * @{
197 */
198 #define LL_DMA_LLP_SRC_ENABLE DMA_CTLL_LLP_SRC_EN_ENABLE /**< Source LLP Enable */
199 #define LL_DMA_LLP_SRC_DISABLE DMA_CTLL_LLP_SRC_EN_DISABLE /**< Source LLP Disable */
200 /** @} */
201
202 /** @defgroup LL_DMA_DST_STAT_UPDATE_EN Destination Status Update Enable
203 * @{
204 */
205 #define LL_DMA_SRC_STAT_UPDATE_ENABLE DMA_CFGH_SS_UPD_ENABLE /**< Destination Status Update Enable */
206 #define LL_DMA_SRC_STAT_UPDATE_DISABLE DMA_CFGH_SS_UPD_DISABLE /**< Destination Status Update Enable */
207 /** @} */
208
209 /** @defgroup LL_DMA_SRC_STAT_UPDATE_EN Source Status Update Enable
210 * @{
211 */
212 #define LL_DMA_DST_STAT_UPDATE_ENABLE DMA_CFGH_DS_UPD_ENABLE /**< Source Status Update Enable */
213 #define LL_DMA_DST_STAT_UPDATE_DISABLE DMA_CFGH_DS_UPD_DISABLE /**< Source Status Update Enable */
214 /** @} */
215
216 /** @defgroup DMA_LL_EC_DST_SCATTER Destination Scatter Enable
217 * @{
218 */
219 #define LL_DMA_DST_SCATTER_ENABLE DMA_CTLL_DST_SCATTER_EN_ENABLE /**< Destination Scatter Enable */
220 #define LL_DMA_DST_SCATTER_DISABLE DMA_CTLL_DST_SCATTER_EN_DISABLE /**< Destination Scatter Disable */
221 /** @} */
222
223 /** @defgroup DMA_LL_EC_SRC_GATHER Source Gather Enable
224 * @{
225 */
226 #define LL_DMA_SRC_GATHER_ENABLE DMA_CTLL_SRC_GATHER_EN_ENABLE /**< Source Gather Enable */
227 #define LL_DMA_SRC_GATHER_DISABLE DMA_CTLL_SRC_GATHER_EN_DISABLE /**< Source Gather Disable */
228 /** @} */
229
230
231 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
232 * @{
233 */
234 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
235 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
236 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
237 /** @} */
238
239 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
240 * @{
241 */
242 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
243 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
244 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
245 /** @} */
246
247 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
248 * @{
249 */
250 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
251 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
252 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
253 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
254 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
255 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
256 /** @} */
257
258 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
259 * @{
260 */
261 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
262 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
263 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
264 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
265 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
266 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
267 /** @} */
268
269 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
270 * @{
271 */
272 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
273 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
274 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
275 /** @} */
276
277 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
278 * @{
279 */
280 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
281 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
282 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
283 /** @} */
284
285 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
286 * @{
287 */
288 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
289 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
290 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
291 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
292 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
293 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
294 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
295 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
296 /** @} */
297
298 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
299 * @{
300 */
301 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
302 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
303 /** @} */
304
305 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
306 * @{
307 */
308 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
309 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
310 /** @} */
311
312 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
313 * @{
314 */
315 /********************************* definition for DMA0 **************************************/
316 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU) /**< DMA peripheral type is Memory */
317
318 /********************************* definition for DMA0 HS0 **************************************/
319 #define LL_DMA0_PERIPH_QSPI0_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is QSPIM0 TX */
320 #define LL_DMA0_PERIPH_QSPI0_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is QSPIM0 RX */
321 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIM TX */
322 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIM RX */
323 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is SPIS TX */
324 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is SPIS RX */
325 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is UART0 TX */
326 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is UART0 RX */
327 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is UART1 TX */
328 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is UART1 RX */
329 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU) /**< DMA peripheral type is SNSADC */
330 #define LL_DMA0_PERIPH_OSPI_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is OSPIM TX */
331 #define LL_DMA0_PERIPH_OSPI_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is OSPIM RX */
332 #define LL_DMA0_PERIPH_UART2_TX ((uint32_t)0x0000000EU) /**< DMA Peripheral type is UART2 TX */
333 #define LL_DMA0_PERIPH_UART2_RX ((uint32_t)0x0000000FU) /**< DMA Peripheral type is UART2 RX */
334
335 /********************************* definition for DMA0 HS1**************************************/
336 #define LL_DMA0_PERIPH_I2C2_TX ((uint32_t)0x00000012U) /**< DMA Peripheral type is I2C2 TX */
337 #define LL_DMA0_PERIPH_I2C2_RX ((uint32_t)0x00000013U) /**< DMA Peripheral type is I2C2 RX */
338 #define LL_DMA0_PERIPH_UART3_TX ((uint32_t)0x00000014U) /**< DMA Peripheral type is UART3 TX */
339 #define LL_DMA0_PERIPH_UART3_RX ((uint32_t)0x00000015U) /**< DMA Peripheral type is UART3 RX */
340 #define LL_DMA0_PERIPH_I2C5_TX ((uint32_t)0x00000016U) /**< DMA Peripheral type is I2C5 TX */
341 #define LL_DMA0_PERIPH_I2C5_RX ((uint32_t)0x00000017U) /**< DMA Peripheral type is I2C5 RX */
342 #define LL_DMA0_PERIPH_I2C4_TX ((uint32_t)0x00000018U) /**< DMA Peripheral type is I2C4 TX */
343 #define LL_DMA0_PERIPH_I2C4_RX ((uint32_t)0x00000019U) /**< DMA Peripheral type is I2C5 RX */
344 #define LL_DMA0_PERIPH_UART4_TX ((uint32_t)0x0000001AU) /**< DMA Peripheral type is UART4 TX */
345 #define LL_DMA0_PERIPH_UART4_RX ((uint32_t)0x0000001BU) /**< DMA Peripheral type is UART4 RX */
346 #define LL_DMA0_PERIPH_QSPI1_TX ((uint32_t)0x0000001CU) /**< DMA Peripheral type is QSPIM1 TX */
347 #define LL_DMA0_PERIPH_QSPI1_RX ((uint32_t)0x0000001DU) /**< DMA Peripheral type is QSPIM1 RX */
348 #define LL_DMA0_PERIPH_I2C3_TX ((uint32_t)0x0000001EU) /**< DMA Peripheral type is I2C3 TX */
349 #define LL_DMA0_PERIPH_I2C3_RX ((uint32_t)0x0000001FU) /**< DMA Peripheral type is I2C3 RX */
350
351 /********************************* definition for DMA1**************************************/
352 #define LL_DMA1_PERIPH_MEM ((uint32_t)0x00000009U) /**< DMA peripheral type is Memory */
353
354 /********************************* definition for DMA1 HS0 **************************************/
355 #define LL_DMA1_PERIPH_OSPI_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is OSPIM TX */
356 #define LL_DMA1_PERIPH_OSPI_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is OSPIM RX */
357 #define LL_DMA1_PERIPH_QSPI2_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is QSPIM2 TX */
358 #define LL_DMA1_PERIPH_QSPI2_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is QSPIM2 RX */
359 #define LL_DMA1_PERIPH_I2S_M_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is IIS_M TX */
360 #define LL_DMA1_PERIPH_I2S_M_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is IIS_M RX */
361 #define LL_DMA1_PERIPH_I2S_S_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is IIS_S TX */
362 #define LL_DMA1_PERIPH_I2S_S_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is IIS_S RX */
363 #define LL_DMA1_PERIPH_PDM_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is PDM TX */
364 #define LL_DMA1_PERIPH_QSPI1_TX ((uint32_t)0x0000000AU) /**< DMA Peripheral type is QSPIM1 TX */
365 #define LL_DMA1_PERIPH_QSPI1_RX ((uint32_t)0x0000000BU) /**< DMA Peripheral type is QSPIM1 RX */
366 #define LL_DMA1_PERIPH_I2C0_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is I2C0 TX */
367 #define LL_DMA1_PERIPH_I2C0_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is I2C0 RX */
368 #define LL_DMA1_PERIPH_I2C1_TX ((uint32_t)0x0000000EU) /**< DMA Peripheral type is I2C1 TX */
369 #define LL_DMA1_PERIPH_I2C1_RX ((uint32_t)0x0000000FU) /**< DMA Peripheral type is I2C1 RX */
370
371 /********************************* definition for DMA1 HS1 **************************************/
372 #define LL_DMA1_PERIPH_SPIM_TX ((uint32_t)0x00000010U) /**< DMA Peripheral type is SPIM TX */
373 #define LL_DMA1_PERIPH_SPIM_RX ((uint32_t)0x00000011U) /**< DMA Peripheral type is SPIM RX */
374 #define LL_DMA1_PERIPH_DSPIM_TX ((uint32_t)0x00000012U) /**< DMA Peripheral type is DSPIM TX */
375 #define LL_DMA1_PERIPH_DSPIM_RX ((uint32_t)0x00000013U) /**< DMA Peripheral type is DSPIM RX */
376 #define LL_DMA1_PERIPH_QSPI1_TX_2 ((uint32_t)0x00000014U) /**< DMA Peripheral type is QSPI1 TX */
377 #define LL_DMA1_PERIPH_QSPI1_RX_2 ((uint32_t)0x00000015U) /**< DMA Peripheral type is QSPI1 RX */
378 #define LL_DMA1_PERIPH_UART3_TX ((uint32_t)0x00000016U) /**< DMA Peripheral type is UART3 TX */
379 #define LL_DMA1_PERIPH_UART3_RX ((uint32_t)0x00000017U) /**< DMA Peripheral type is UART3 RX */
380 #define LL_DMA1_PERIPH_UART4_TX ((uint32_t)0x00000018U) /**< DMA Peripheral type is UART4 TX */
381 #define LL_DMA1_PERIPH_UART4_RX ((uint32_t)0x00000019U) /**< DMA Peripheral type is UART4 RX */
382 #define LL_DMA1_PERIPH_UART5_TX ((uint32_t)0x0000001AU) /**< DMA Peripheral type is UART5 TX */
383 #define LL_DMA1_PERIPH_UART5_RX ((uint32_t)0x0000001BU) /**< DMA Peripheral type is UART5 RX */
384 #define LL_DMA1_PERIPH_UART0_TX ((uint32_t)0x0000001EU) /**< DMA Peripheral type is UART0 TX */
385 #define LL_DMA1_PERIPH_UART0_RX ((uint32_t)0x0000001FU) /**< DMA Peripheral type is UART0 RX */
386
387 /** @} */
388
389 /** @} */
390
391 /* Exported macro ------------------------------------------------------------*/
392 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
393 * @{
394 */
395
396 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
397 * @{
398 */
399
400 /**
401 * @brief Write a value in DMA register
402 * @param __instance__ DMA instance
403 * @param __REG__ Register to be written
404 * @param __VALUE__ Value to be written in the register
405 * @retval None
406 */
407 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
408
409 /**
410 * @brief Read a value in DMA register
411 * @param __instance__ DMA instance
412 * @param __REG__ Register to be read
413 * @retval Register value
414 */
415 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
416
417 /** @} */
418
419 /** @} */
420
421 /** @} */
422
423 /* Exported functions --------------------------------------------------------*/
424 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
425 * @{
426 */
427
428 /** @defgroup DMA_LL_EF_Configuration Configuration functions
429 * @{
430 */
431
432 /**
433 * @brief Enable DMA Module.
434 * @note This function is used to enable the DMA Module, which must be done before any
435 * channel activity can begin.
436 *
437 * Register|BitsName
438 * --------|--------
439 * CFG_REG | CFG_EN
440 *
441 * @param DMAx DMA instance.
442 * @retval None
443 */
444 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
445 {
446 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
447 }
448
449 /**
450 * @brief Disable DMA Module.
451 * @note If the ll_dma_disable() function is called while any dma channel is still active,
452 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
453 * still active until hardware has terminated all cativity on all channels, at which
454 * point the ll_dma_is_enable() function returns 0.
455 *
456 * Register|BitsName
457 * --------|--------
458 * CFG_REG | CFG_EN
459 *
460 * @param DMAx DMA instance.
461 * @retval None
462 */
463 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
464 {
465 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
466 }
467
468 /**
469 * @brief Check if DMA Module is enabled or disabled.
470 *
471 * Register|BitsName
472 * --------|--------
473 * CFG_REG | CFG_EN
474 *
475 * @param DMAx DMA instance.
476 * @retval State of bit (1 or 0).
477 */
478 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
479 {
480 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
481 }
482
483 /**
484 * @brief Enable DMA channel.
485 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
486 * is ignored and call ll_dma_disable_channel() function will always returns 0.
487 *
488 * Register|BitsName
489 * --------|--------
490 * CH_EN_REG | CH_EN_WE&CH_EN
491 *
492 * @param DMAx DMA instance.
493 * @param channel This parameter can be one of the following values:
494 * @arg @ref LL_DMA_CHANNEL_0
495 * @arg @ref LL_DMA_CHANNEL_1
496 * @arg @ref LL_DMA_CHANNEL_2
497 * @arg @ref LL_DMA_CHANNEL_3
498 * @arg @ref LL_DMA_CHANNEL_4
499 * @arg @ref LL_DMA_CHANNEL_5
500 * @arg @ref LL_DMA_CHANNEL_6
501 * @arg @ref LL_DMA_CHANNEL_7
502 * @retval None
503 */
504 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
505 {
506 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
507 }
508
509 /**
510 * @brief Disable DMA channel.
511 *
512 * Register|BitsName
513 * --------|--------
514 * CH_EN_REG | CH_EN_WE&CH_EN
515 *
516 * @param DMAx DMA instance.
517 * @param channel This parameter can be one of the following values:
518 * @arg @ref LL_DMA_CHANNEL_0
519 * @arg @ref LL_DMA_CHANNEL_1
520 * @arg @ref LL_DMA_CHANNEL_2
521 * @arg @ref LL_DMA_CHANNEL_3
522 * @arg @ref LL_DMA_CHANNEL_4
523 * @arg @ref LL_DMA_CHANNEL_5
524 * @arg @ref LL_DMA_CHANNEL_6
525 * @arg @ref LL_DMA_CHANNEL_7
526 * @retval None
527 */
528 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
529 {
530 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
531 }
532
533 /**
534 * @brief Check if DMA channel is enabled or disabled.
535 * @note Software can therefore poll this function to determine when channel is free
536 * for a new DMA transfer.
537 *
538 * Register|BitsName
539 * --------|--------
540 * CH_EN_REG | CH_EN_WE&CH_EN
541 *
542 * @param DMAx DMA instance.
543 * @param channel This parameter can be one of the following values:
544 * @arg @ref LL_DMA_CHANNEL_0
545 * @arg @ref LL_DMA_CHANNEL_1
546 * @arg @ref LL_DMA_CHANNEL_2
547 * @arg @ref LL_DMA_CHANNEL_3
548 * @arg @ref LL_DMA_CHANNEL_4
549 * @arg @ref LL_DMA_CHANNEL_5
550 * @arg @ref LL_DMA_CHANNEL_6
551 * @arg @ref LL_DMA_CHANNEL_7
552 * @retval State of bit (1 or 0).
553 */
554 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
555 {
556 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
557 }
558
559 /**
560 * @brief Suspend a DMA channel transfer.
561 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
562 * function is called. The function may be called after enabling the DMA channel.
563 *
564 * Register|BitsName
565 * --------|--------
566 * CFGL | CH_SUSP
567 *
568 * @param DMAx DMA instance.
569 * @param channel This parameter can be one of the following values:
570 * @arg @ref LL_DMA_CHANNEL_0
571 * @arg @ref LL_DMA_CHANNEL_1
572 * @arg @ref LL_DMA_CHANNEL_2
573 * @arg @ref LL_DMA_CHANNEL_3
574 * @arg @ref LL_DMA_CHANNEL_4
575 * @arg @ref LL_DMA_CHANNEL_5
576 * @arg @ref LL_DMA_CHANNEL_6
577 * @arg @ref LL_DMA_CHANNEL_7
578 * @retval None
579 */
580 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
581 {
582 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
583 }
584
585 /**
586 * @brief Resume a DMA channel.
587 * @note The function may be called after enabling the DMA channel.
588 *
589 * Register|BitsName
590 * --------|--------
591 * CFGL | CH_SUSP
592 *
593 * @param DMAx DMA instance.
594 * @param channel This parameter can be one of the following values:
595 * @arg @ref LL_DMA_CHANNEL_0
596 * @arg @ref LL_DMA_CHANNEL_1
597 * @arg @ref LL_DMA_CHANNEL_2
598 * @arg @ref LL_DMA_CHANNEL_3
599 * @arg @ref LL_DMA_CHANNEL_4
600 * @arg @ref LL_DMA_CHANNEL_5
601 * @arg @ref LL_DMA_CHANNEL_6
602 * @arg @ref LL_DMA_CHANNEL_7
603 * @retval None
604 */
605 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
606 {
607 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
608 }
609
610 /**
611 * @brief Check if DMA channel is suspended or resumed.
612 *
613 * Register|BitsName
614 * --------|--------
615 * CFGL | CH_SUSP
616 *
617 * @param DMAx DMA instance.
618 * @param channel This parameter can be one of the following values:
619 * @arg @ref LL_DMA_CHANNEL_0
620 * @arg @ref LL_DMA_CHANNEL_1
621 * @arg @ref LL_DMA_CHANNEL_2
622 * @arg @ref LL_DMA_CHANNEL_3
623 * @arg @ref LL_DMA_CHANNEL_4
624 * @arg @ref LL_DMA_CHANNEL_5
625 * @arg @ref LL_DMA_CHANNEL_6
626 * @arg @ref LL_DMA_CHANNEL_7
627 * @retval State of bit (1 or 0).
628 */
629 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
630 {
631 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
632 }
633
634 /**
635 * @brief Check if DMA channel FIFO is empty.
636 *
637 * Register|BitsName
638 * --------|--------
639 * CFGL | FIFO_EMPTY
640 *
641 * @param DMAx DMA instance.
642 * @param channel This parameter can be one of the following values:
643 * @arg @ref LL_DMA_CHANNEL_0
644 * @arg @ref LL_DMA_CHANNEL_1
645 * @arg @ref LL_DMA_CHANNEL_2
646 * @arg @ref LL_DMA_CHANNEL_3
647 * @arg @ref LL_DMA_CHANNEL_4
648 * @arg @ref LL_DMA_CHANNEL_5
649 * @arg @ref LL_DMA_CHANNEL_6
650 * @arg @ref LL_DMA_CHANNEL_7
651 * @retval State of bit (1 or 0).
652 */
653 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
654 {
655 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
656 }
657
658 /**
659 * @brief Configure all parameters link to DMA transfer.
660 *
661 * Register|BitsName
662 * --------|--------
663 * CCR | DIR
664 * CCR | MEM2MEM
665 * CCR | CIRC
666 * CCR | PINC
667 * CCR | MINC
668 * CCR | PSIZE
669 * CCR | MSIZE
670 * CCR | PL
671 *
672 * @param DMAx DMAx instance
673 * @param channel This parameter can be one of the following values:
674 * @arg @ref LL_DMA_CHANNEL_0
675 * @arg @ref LL_DMA_CHANNEL_1
676 * @arg @ref LL_DMA_CHANNEL_2
677 * @arg @ref LL_DMA_CHANNEL_3
678 * @arg @ref LL_DMA_CHANNEL_4
679 * @arg @ref LL_DMA_CHANNEL_5
680 * @arg @ref LL_DMA_CHANNEL_6
681 * @arg @ref LL_DMA_CHANNEL_7
682 * @param configuration This parameter must be a combination of all the following values:
683 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK or @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
684 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
685 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
686 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
687 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
688 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
689 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
690 * @retval None
691 */
692 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
693 {
694 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
695 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
696 }
697
698 /**
699 * @brief Set Data transfer direction (read from peripheral or from memory).
700 *
701 * Register|BitsName
702 * --------|--------
703 * CTL_LO | TT_FC
704 *
705 * @param DMAx DMAx instance
706 * @param channel This parameter can be one of the following values:
707 * @arg @ref LL_DMA_CHANNEL_0
708 * @arg @ref LL_DMA_CHANNEL_1
709 * @arg @ref LL_DMA_CHANNEL_2
710 * @arg @ref LL_DMA_CHANNEL_3
711 * @arg @ref LL_DMA_CHANNEL_4
712 * @arg @ref LL_DMA_CHANNEL_5
713 * @arg @ref LL_DMA_CHANNEL_6
714 * @arg @ref LL_DMA_CHANNEL_7
715 * @param direction This parameter can be one of the following values:
716 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
717 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
718 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
719 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
720 * @retval None
721 */
722 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
723 {
724 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
725 }
726
727 /**
728 * @brief Get Data transfer direction (read from peripheral or from memory).
729 *
730 * Register|BitsName
731 * --------|--------
732 * CTL_LO | TT_FC
733 *
734 * @param DMAx DMAx instance
735 * @param channel This parameter can be one of the following values:
736 * @arg @ref LL_DMA_CHANNEL_0
737 * @arg @ref LL_DMA_CHANNEL_1
738 * @arg @ref LL_DMA_CHANNEL_2
739 * @arg @ref LL_DMA_CHANNEL_3
740 * @arg @ref LL_DMA_CHANNEL_4
741 * @arg @ref LL_DMA_CHANNEL_5
742 * @arg @ref LL_DMA_CHANNEL_6
743 * @arg @ref LL_DMA_CHANNEL_7
744 * @retval Returned value can be one of the following values:
745 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
746 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
747 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
748 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
749 */
750 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
751 {
752 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
753 }
754
755 /**
756 * @brief Set DMA mode Single block or Multi block.
757 * @note The circular buffer mode cannot be used if the memory-to-memory
758 * data transfer is configured on the selected Channel.
759 *
760 * Register|BitsName
761 * --------|--------
762 * CFG_LO | RELOAD_DST
763 *
764 * @param DMAx DMAx instance
765 * @param channel This parameter can be one of the following values:
766 * @arg @ref LL_DMA_CHANNEL_0
767 * @arg @ref LL_DMA_CHANNEL_1
768 * @arg @ref LL_DMA_CHANNEL_2
769 * @arg @ref LL_DMA_CHANNEL_3
770 * @arg @ref LL_DMA_CHANNEL_4
771 * @arg @ref LL_DMA_CHANNEL_5
772 * @arg @ref LL_DMA_CHANNEL_6
773 * @arg @ref LL_DMA_CHANNEL_7
774 * @param mode This parameter can be one of the following values:
775 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
776 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
777 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
778 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
779 * @retval None
780 */
781 __STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
782 {
783 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
784 }
785
786
787 /**
788 * @brief Get DMA mode circular or normal.
789 *
790 * Register|BitsName
791 * --------|--------
792 * CFG_LO | RELOAD_DST
793 *
794 * @param DMAx DMAx instance
795 * @param channel This parameter can be one of the following values:
796 * @arg @ref LL_DMA_CHANNEL_0
797 * @arg @ref LL_DMA_CHANNEL_1
798 * @arg @ref LL_DMA_CHANNEL_2
799 * @arg @ref LL_DMA_CHANNEL_3
800 * @arg @ref LL_DMA_CHANNEL_4
801 * @arg @ref LL_DMA_CHANNEL_5
802 * @arg @ref LL_DMA_CHANNEL_6
803 * @arg @ref LL_DMA_CHANNEL_7
804 * @retval Returned value can be one of the following values:
805 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
806 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
807 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
808 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
809 */
810 __STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
811 {
812 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
813 }
814
815 /**
816 * @brief Set Maximum AMBA Burst Length.
817 *
818 * Register|BitsName
819 * --------|--------
820 * CFG_LO | MAX_ABRST
821 *
822 * @param DMAx DMAx instance
823 * @param channel This parameter can be one of the following values:
824 * @arg @ref LL_DMA_CHANNEL_0
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @arg @ref LL_DMA_CHANNEL_5
830 * @arg @ref LL_DMA_CHANNEL_6
831 * @arg @ref LL_DMA_CHANNEL_7
832 * @param beats This parameter can be one of the following values:
833 Between Min_Data = 0 and Max_Data = 0x3FFU.
834 * @retval None
835 */
836 __STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
837 {
838 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
839 }
840
841 /**
842 * @brief Get source status after each block tranfer completed.
843 *
844 * Register|BitsName
845 * --------|--------
846 * SSTAT | SSTAT
847 *
848 * @param DMAx DMAx instance
849 * @param channel This parameter can be one of the following values:
850 * @arg @ref LL_DMA_CHANNEL_0
851 * @arg @ref LL_DMA_CHANNEL_1
852 * @arg @ref LL_DMA_CHANNEL_2
853 * @arg @ref LL_DMA_CHANNEL_3
854 * @arg @ref LL_DMA_CHANNEL_4
855 * @arg @ref LL_DMA_CHANNEL_5
856 * @arg @ref LL_DMA_CHANNEL_6
857 * @arg @ref LL_DMA_CHANNEL_7
858 * @retval Returned value can be one of the following values:
859 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
860 * @retval None
861 */
862 __STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
863 {
864 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
865 }
866
867 /**
868 * @brief Set source status after each block tranfer completed.
869 *
870 * Register|BitsName
871 * --------|--------
872 * SSTAT | SSTAT
873 *
874 * @param DMAx DMAx instance
875 * @param channel This parameter can be one of the following values:
876 * @arg @ref LL_DMA_CHANNEL_0
877 * @arg @ref LL_DMA_CHANNEL_1
878 * @arg @ref LL_DMA_CHANNEL_2
879 * @arg @ref LL_DMA_CHANNEL_3
880 * @arg @ref LL_DMA_CHANNEL_4
881 * @arg @ref LL_DMA_CHANNEL_5
882 * @arg @ref LL_DMA_CHANNEL_6
883 * @arg @ref LL_DMA_CHANNEL_7
884 * @param sstat This parameter can be one of the following values:
885 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
886 * @retval None
887 */
888 __STATIC_INLINE void ll_dma_set_sstat(dma_regs_t *DMAx, uint32_t channel, uint32_t sstat)
889 {
890 MODIFY_REG(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT, sstat);
891 }
892
893 /**
894 * @brief Get source status after each block tranfer completed.
895 *
896 * Register|BitsName
897 * --------|--------
898 * SSTAT | SSTAT
899 *
900 * @param DMAx DMAx instance
901 * @param channel This parameter can be one of the following values:
902 * @arg @ref LL_DMA_CHANNEL_0
903 * @arg @ref LL_DMA_CHANNEL_1
904 * @arg @ref LL_DMA_CHANNEL_2
905 * @arg @ref LL_DMA_CHANNEL_3
906 * @arg @ref LL_DMA_CHANNEL_4
907 * @arg @ref LL_DMA_CHANNEL_5
908 * @arg @ref LL_DMA_CHANNEL_6
909 * @arg @ref LL_DMA_CHANNEL_7
910 * @retval Returned value can be one of the following values:
911 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
912 * @retval None
913 */
914 __STATIC_INLINE uint32_t ll_dma_get_sstat(dma_regs_t *DMAx, uint32_t channel)
915 {
916 return READ_BITS(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT);
917 }
918
919 /**
920 * @brief Set deatination status after each block tranfer completed.
921 *
922 * Register|BitsName
923 * --------|--------
924 * DSTAT | DSTAT
925 *
926 * @param DMAx DMAx instance
927 * @param channel This parameter can be one of the following values:
928 * @arg @ref LL_DMA_CHANNEL_0
929 * @arg @ref LL_DMA_CHANNEL_1
930 * @arg @ref LL_DMA_CHANNEL_2
931 * @arg @ref LL_DMA_CHANNEL_3
932 * @arg @ref LL_DMA_CHANNEL_4
933 * @arg @ref LL_DMA_CHANNEL_5
934 * @arg @ref LL_DMA_CHANNEL_6
935 * @arg @ref LL_DMA_CHANNEL_7
936 * @param dstat This parameter can be one of the following values:
937 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
938 * @retval None
939 */
940 __STATIC_INLINE void ll_dma_set_dstat(dma_regs_t *DMAx, uint32_t channel, uint32_t dstat)
941 {
942 MODIFY_REG(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT, dstat);
943 }
944
945 /**
946 * @brief Get deatination status after each block tranfer completed.
947 *
948 * Register|BitsName
949 * --------|--------
950 * DSTAT | DSTAT
951 *
952 * @param DMAx DMAx instance
953 * @param channel This parameter can be one of the following values:
954 * @arg @ref LL_DMA_CHANNEL_0
955 * @arg @ref LL_DMA_CHANNEL_1
956 * @arg @ref LL_DMA_CHANNEL_2
957 * @arg @ref LL_DMA_CHANNEL_3
958 * @arg @ref LL_DMA_CHANNEL_4
959 * @arg @ref LL_DMA_CHANNEL_5
960 * @arg @ref LL_DMA_CHANNEL_6
961 * @arg @ref LL_DMA_CHANNEL_7
962 * @retval Returned value can be one of the following values:
963 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
964 */
965 __STATIC_INLINE uint32_t ll_dma_get_dstat(dma_regs_t *DMAx, uint32_t channel)
966 {
967 return READ_BITS(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT);
968 }
969
970 /**
971 * @brief Set source status address after each block tranfer completed.
972 *
973 * Register|BitsName
974 * --------|--------
975 * SSTATAR | SSTATAR
976 *
977 * @param DMAx DMAx instance
978 * @param channel This parameter can be one of the following values:
979 * @arg @ref LL_DMA_CHANNEL_0
980 * @arg @ref LL_DMA_CHANNEL_1
981 * @arg @ref LL_DMA_CHANNEL_2
982 * @arg @ref LL_DMA_CHANNEL_3
983 * @arg @ref LL_DMA_CHANNEL_4
984 * @arg @ref LL_DMA_CHANNEL_5
985 * @arg @ref LL_DMA_CHANNEL_6
986 * @arg @ref LL_DMA_CHANNEL_7
987 * @param sstatar This parameter can be one of the following values:
988 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
989 * @retval None
990 */
991 __STATIC_INLINE void ll_dma_set_sstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t sstatar)
992 {
993 MODIFY_REG(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR, sstatar);
994 }
995
996 /**
997 * @brief Get source status address after each block tranfer completed.
998 *
999 * Register|BitsName
1000 * --------|--------
1001 * SSTATAR | SSTATAR
1002 *
1003 * @param DMAx DMAx instance
1004 * @param channel This parameter can be one of the following values:
1005 * @arg @ref LL_DMA_CHANNEL_0
1006 * @arg @ref LL_DMA_CHANNEL_1
1007 * @arg @ref LL_DMA_CHANNEL_2
1008 * @arg @ref LL_DMA_CHANNEL_3
1009 * @arg @ref LL_DMA_CHANNEL_4
1010 * @arg @ref LL_DMA_CHANNEL_5
1011 * @arg @ref LL_DMA_CHANNEL_6
1012 * @arg @ref LL_DMA_CHANNEL_7
1013 * @retval Returned value can be one of the following values:
1014 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1015 */
1016 __STATIC_INLINE uint32_t ll_dma_get_sstatar(dma_regs_t *DMAx, uint32_t channel)
1017 {
1018 return READ_BITS(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR);
1019 }
1020
1021 /**
1022 * @brief Set deatination status address after each block tranfer completed.
1023 *
1024 * Register|BitsName
1025 * --------|--------
1026 * DSTATAR | DSTATAR
1027 *
1028 * @param DMAx DMAx instance
1029 * @param channel This parameter can be one of the following values:
1030 * @arg @ref LL_DMA_CHANNEL_0
1031 * @arg @ref LL_DMA_CHANNEL_1
1032 * @arg @ref LL_DMA_CHANNEL_2
1033 * @arg @ref LL_DMA_CHANNEL_3
1034 * @arg @ref LL_DMA_CHANNEL_4
1035 * @arg @ref LL_DMA_CHANNEL_5
1036 * @arg @ref LL_DMA_CHANNEL_6
1037 * @arg @ref LL_DMA_CHANNEL_7
1038 * @param dstatar This parameter can be one of the following values:
1039 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1040 * @retval None
1041 */
1042 __STATIC_INLINE void ll_dma_set_dstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t dstatar)
1043 {
1044 MODIFY_REG(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR, dstatar);
1045 }
1046
1047 /**
1048 * @brief Get deatination status address after each block tranfer completed.
1049 *
1050 * Register|BitsName
1051 * --------|--------
1052 * DSTATAR | DSTATAR
1053 *
1054 * @param DMAx DMAx instance
1055 * @param channel This parameter can be one of the following values:
1056 * @arg @ref LL_DMA_CHANNEL_0
1057 * @arg @ref LL_DMA_CHANNEL_1
1058 * @arg @ref LL_DMA_CHANNEL_2
1059 * @arg @ref LL_DMA_CHANNEL_3
1060 * @arg @ref LL_DMA_CHANNEL_4
1061 * @arg @ref LL_DMA_CHANNEL_5
1062 * @arg @ref LL_DMA_CHANNEL_6
1063 * @arg @ref LL_DMA_CHANNEL_7
1064 * @retval Returned value can be one of the following values:
1065 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1066 */
1067 __STATIC_INLINE uint32_t ll_dma_get_dstatar(dma_regs_t *DMAx, uint32_t channel)
1068 {
1069 return READ_BITS(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR);
1070 }
1071
1072 /**
1073 * @brief Set LLP loc.
1074 *
1075 * Register|BitsName
1076 * --------|--------
1077 * CTL_LO | LOC
1078 *
1079 * @param DMAx DMAx instance
1080 * @param channel This parameter can be one of the following values:
1081 * @arg @ref LL_DMA_CHANNEL_0
1082 * @arg @ref LL_DMA_CHANNEL_1
1083 * @arg @ref LL_DMA_CHANNEL_2
1084 * @arg @ref LL_DMA_CHANNEL_3
1085 * @arg @ref LL_DMA_CHANNEL_4
1086 * @arg @ref LL_DMA_CHANNEL_5
1087 * @arg @ref LL_DMA_CHANNEL_6
1088 * @arg @ref LL_DMA_CHANNEL_7
1089 * @param llp_loc This parameter can be one of the following values:
1090 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)
1091 * @retval None
1092 */
1093 __STATIC_INLINE void ll_dma_set_llp_loc(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_loc)
1094 {
1095 MODIFY_REG(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC, llp_loc);
1096 }
1097
1098 /**
1099 * @brief Get LLP loc.
1100 *
1101 * Register|BitsName
1102 * --------|--------
1103 * CTL_LO | LOC
1104 *
1105 * @param DMAx DMAx instance
1106 * @param channel This parameter can be one of the following values:
1107 * @arg @ref LL_DMA_CHANNEL_0
1108 * @arg @ref LL_DMA_CHANNEL_1
1109 * @arg @ref LL_DMA_CHANNEL_2
1110 * @arg @ref LL_DMA_CHANNEL_3
1111 * @arg @ref LL_DMA_CHANNEL_4
1112 * @arg @ref LL_DMA_CHANNEL_5
1113 * @arg @ref LL_DMA_CHANNEL_6
1114 * @arg @ref LL_DMA_CHANNEL_7
1115 * @retval Returned value can be one of the following values:
1116 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.(LLI accesses are always 32-bit accesses)
1117 */
1118 __STATIC_INLINE uint32_t ll_dma_get_llp_loc(dma_regs_t *DMAx, uint32_t channel)
1119 {
1120 return READ_BITS(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC);
1121 }
1122
1123 /**
1124 * @brief Set destination LLP enable.
1125 *
1126 * Register|BitsName
1127 * --------|--------
1128 * CTL_LO | LLP_DST_EN
1129 *
1130 * @param DMAx DMAx instance
1131 * @param channel This parameter can be one of the following values:
1132 * @arg @ref LL_DMA_CHANNEL_0
1133 * @arg @ref LL_DMA_CHANNEL_1
1134 * @arg @ref LL_DMA_CHANNEL_2
1135 * @arg @ref LL_DMA_CHANNEL_3
1136 * @arg @ref LL_DMA_CHANNEL_4
1137 * @arg @ref LL_DMA_CHANNEL_5
1138 * @arg @ref LL_DMA_CHANNEL_6
1139 * @arg @ref LL_DMA_CHANNEL_7
1140 * @param llp_dst_en This parameter can be one of the following values:
1141 * @arg @ref LL_DMA_LLP_DST_ENABLE
1142 * @arg @ref LL_DMA_LLP_DST_DISABLE
1143 * @retval None
1144 */
1145 __STATIC_INLINE void ll_dma_set_llp_dst_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_dst_en)
1146 {
1147 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN, llp_dst_en);
1148 }
1149
1150 /**
1151 * @brief Get destination LLP enable.
1152 *
1153 * Register|BitsName
1154 * --------|--------
1155 * CTL_LO | LLP_DST_EN
1156 *
1157 * @param DMAx DMAx instance
1158 * @param channel This parameter can be one of the following values:
1159 * @arg @ref LL_DMA_CHANNEL_0
1160 * @arg @ref LL_DMA_CHANNEL_1
1161 * @arg @ref LL_DMA_CHANNEL_2
1162 * @arg @ref LL_DMA_CHANNEL_3
1163 * @arg @ref LL_DMA_CHANNEL_4
1164 * @arg @ref LL_DMA_CHANNEL_5
1165 * @arg @ref LL_DMA_CHANNEL_6
1166 * @arg @ref LL_DMA_CHANNEL_7
1167 * @retval Returned value can be one of the following values:
1168 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1169 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1170 */
1171 __STATIC_INLINE uint32_t ll_dma_get_llp_dst_en(dma_regs_t *DMAx, uint32_t channel)
1172 {
1173 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN);
1174 }
1175
1176 /**
1177 * @brief Set source LLP enable.
1178 *
1179 * Register|BitsName
1180 * --------|--------
1181 * CTL_LO | LLP_SRC_EN
1182 *
1183 * @param DMAx DMAx instance
1184 * @param channel This parameter can be one of the following values:
1185 * @arg @ref LL_DMA_CHANNEL_0
1186 * @arg @ref LL_DMA_CHANNEL_1
1187 * @arg @ref LL_DMA_CHANNEL_2
1188 * @arg @ref LL_DMA_CHANNEL_3
1189 * @arg @ref LL_DMA_CHANNEL_4
1190 * @arg @ref LL_DMA_CHANNEL_5
1191 * @arg @ref LL_DMA_CHANNEL_6
1192 * @arg @ref LL_DMA_CHANNEL_7
1193 * @param llp_src_en This parameter can be one of the following values:
1194 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1195 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1196 * @retval None
1197 */
1198 __STATIC_INLINE void ll_dma_set_llp_src_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_src_en)
1199 {
1200 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN, llp_src_en);
1201 }
1202
1203 /**
1204 * @brief Get source LLP enable.
1205 *
1206 * Register|BitsName
1207 * --------|--------
1208 * CTL_LO | LLP_SRC_EN
1209 *
1210 * @param DMAx DMAx instance
1211 * @param channel This parameter can be one of the following values:
1212 * @arg @ref LL_DMA_CHANNEL_0
1213 * @arg @ref LL_DMA_CHANNEL_1
1214 * @arg @ref LL_DMA_CHANNEL_2
1215 * @arg @ref LL_DMA_CHANNEL_3
1216 * @arg @ref LL_DMA_CHANNEL_4
1217 * @arg @ref LL_DMA_CHANNEL_5
1218 * @arg @ref LL_DMA_CHANNEL_6
1219 * @arg @ref LL_DMA_CHANNEL_7
1220 * @retval Returned value can be one of the following values:
1221 * @arg @ref LL_DMA_LLP_SRC_ENABLE
1222 * @arg @ref LL_DMA_LLP_SRC_DISABLE
1223 */
1224 __STATIC_INLINE uint32_t ll_dma_get_llp_src_en(dma_regs_t *DMAx, uint32_t channel)
1225 {
1226 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN);
1227 }
1228
1229 /**
1230 * @brief Set destination scatter enable.
1231 *
1232 * Register|BitsName
1233 * --------|--------
1234 * CTL_LO | DST_SCATTER_EN
1235 *
1236 * @param DMAx DMAx instance
1237 * @param channel This parameter can be one of the following values:
1238 * @arg @ref LL_DMA_CHANNEL_0
1239 * @arg @ref LL_DMA_CHANNEL_1
1240 * @arg @ref LL_DMA_CHANNEL_2
1241 * @arg @ref LL_DMA_CHANNEL_3
1242 * @arg @ref LL_DMA_CHANNEL_4
1243 * @arg @ref LL_DMA_CHANNEL_5
1244 * @arg @ref LL_DMA_CHANNEL_6
1245 * @arg @ref LL_DMA_CHANNEL_7
1246 * @param dst_scatter_en This parameter can be one of the following values:
1247 * @arg @ref LL_DMA_DST_SCATTER_ENABLE
1248 * @arg @ref LL_DMA_DST_SCATTER_DISABLE
1249 * @retval None
1250 */
1251 __STATIC_INLINE void ll_dma_set_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_en)
1252 {
1253 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN, dst_scatter_en);
1254 }
1255
1256 /**
1257 * @brief Get destination scatter enable.
1258 *
1259 * Register|BitsName
1260 * --------|--------
1261 * CTL_LO | DST_SCATTER_EN
1262 *
1263 * @param DMAx DMAx instance
1264 * @param channel This parameter can be one of the following values:
1265 * @arg @ref LL_DMA_CHANNEL_0
1266 * @arg @ref LL_DMA_CHANNEL_1
1267 * @arg @ref LL_DMA_CHANNEL_2
1268 * @arg @ref LL_DMA_CHANNEL_3
1269 * @arg @ref LL_DMA_CHANNEL_4
1270 * @arg @ref LL_DMA_CHANNEL_5
1271 * @arg @ref LL_DMA_CHANNEL_6
1272 * @arg @ref LL_DMA_CHANNEL_7
1273 * @retval Returned value can be one of the following values:
1274 * @arg @ref LL_DMA_DST_SCATTER_ENABLE
1275 * @arg @ref LL_DMA_DST_SCATTER_DISABLE
1276 */
1277 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel)
1278 {
1279 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN);
1280 }
1281
1282 /**
1283 * @brief Set source gather enable.
1284 *
1285 * Register|BitsName
1286 * --------|--------
1287 * CTL_LO | SRC_GATHER_EN
1288 *
1289 * @param DMAx DMAx instance
1290 * @param channel This parameter can be one of the following values:
1291 * @arg @ref LL_DMA_CHANNEL_0
1292 * @arg @ref LL_DMA_CHANNEL_1
1293 * @arg @ref LL_DMA_CHANNEL_2
1294 * @arg @ref LL_DMA_CHANNEL_3
1295 * @arg @ref LL_DMA_CHANNEL_4
1296 * @arg @ref LL_DMA_CHANNEL_5
1297 * @arg @ref LL_DMA_CHANNEL_6
1298 * @arg @ref LL_DMA_CHANNEL_7
1299 * @param src_gather_en This parameter can be one of the following values:
1300 * @arg @ref LL_DMA_SRC_GATHER_ENABLE
1301 * @arg @ref LL_DMA_SRC_GATHER_DISABLE
1302 * @retval None
1303 */
1304 __STATIC_INLINE void ll_dma_set_src_gather_en(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_en)
1305 {
1306 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN, src_gather_en);
1307 }
1308
1309 /**
1310 * @brief Get source gather enable.
1311 *
1312 * Register|BitsName
1313 * --------|--------
1314 * CTL_LO | SRC_GATHER_EN
1315 *
1316 * @param DMAx DMAx instance
1317 * @param channel This parameter can be one of the following values:
1318 * @arg @ref LL_DMA_CHANNEL_0
1319 * @arg @ref LL_DMA_CHANNEL_1
1320 * @arg @ref LL_DMA_CHANNEL_2
1321 * @arg @ref LL_DMA_CHANNEL_3
1322 * @arg @ref LL_DMA_CHANNEL_4
1323 * @arg @ref LL_DMA_CHANNEL_5
1324 * @arg @ref LL_DMA_CHANNEL_6
1325 * @arg @ref LL_DMA_CHANNEL_7
1326 * @retval Returned value can be one of the following values:
1327 * @arg @ref LL_DMA_SRC_GATHER_ENABLE
1328 * @arg @ref LL_DMA_SRC_GATHER_DISABLE
1329 */
1330 __STATIC_INLINE uint32_t ll_dma_get_src_gather_en(dma_regs_t *DMAx, uint32_t channel)
1331 {
1332 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN);
1333 }
1334
1335 /**
1336 * @brief Set Source increment mode.
1337 *
1338 * Register|BitsName
1339 * --------|--------
1340 * CTL_LO | SINC
1341 *
1342 * @param DMAx DMAx instance
1343 * @param channel This parameter can be one of the following values:
1344 * @arg @ref LL_DMA_CHANNEL_0
1345 * @arg @ref LL_DMA_CHANNEL_1
1346 * @arg @ref LL_DMA_CHANNEL_2
1347 * @arg @ref LL_DMA_CHANNEL_3
1348 * @arg @ref LL_DMA_CHANNEL_4
1349 * @arg @ref LL_DMA_CHANNEL_5
1350 * @arg @ref LL_DMA_CHANNEL_6
1351 * @arg @ref LL_DMA_CHANNEL_7
1352 * @param src_increment_mode This parameter can be one of the following values:
1353 * @arg @ref LL_DMA_SRC_INCREMENT
1354 * @arg @ref LL_DMA_SRC_DECREMENT
1355 * @arg @ref LL_DMA_SRC_NO_CHANGE
1356 * @retval None
1357 */
1358 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
1359 {
1360 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
1361 }
1362
1363 /**
1364 * @brief Get Source increment mode.
1365 *
1366 * Register|BitsName
1367 * --------|--------
1368 * CTL_LO | SINC
1369 *
1370 * @param DMAx DMAx instance
1371 * @param channel This parameter can be one of the following values:
1372 * @arg @ref LL_DMA_CHANNEL_0
1373 * @arg @ref LL_DMA_CHANNEL_1
1374 * @arg @ref LL_DMA_CHANNEL_2
1375 * @arg @ref LL_DMA_CHANNEL_3
1376 * @arg @ref LL_DMA_CHANNEL_4
1377 * @arg @ref LL_DMA_CHANNEL_5
1378 * @arg @ref LL_DMA_CHANNEL_6
1379 * @arg @ref LL_DMA_CHANNEL_7
1380 * @retval Returned value can be one of the following values:
1381 * @arg @ref LL_DMA_SRC_INCREMENT
1382 * @arg @ref LL_DMA_SRC_DECREMENT
1383 * @arg @ref LL_DMA_SRC_NO_CHANGE
1384 */
1385 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
1386 {
1387 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
1388 }
1389
1390 /**
1391 * @brief Set Destination increment mode.
1392 *
1393 * Register|BitsName
1394 * --------|--------
1395 * CTL_LO | DINC
1396 *
1397 * @param DMAx DMAx instance
1398 * @param channel This parameter can be one of the following values:
1399 * @arg @ref LL_DMA_CHANNEL_0
1400 * @arg @ref LL_DMA_CHANNEL_1
1401 * @arg @ref LL_DMA_CHANNEL_2
1402 * @arg @ref LL_DMA_CHANNEL_3
1403 * @arg @ref LL_DMA_CHANNEL_4
1404 * @arg @ref LL_DMA_CHANNEL_5
1405 * @arg @ref LL_DMA_CHANNEL_6
1406 * @arg @ref LL_DMA_CHANNEL_7
1407 * @param dst_increment_mode This parameter can be one of the following values:
1408 * @arg @ref LL_DMA_DST_INCREMENT
1409 * @arg @ref LL_DMA_DST_DECREMENT
1410 * @arg @ref LL_DMA_DST_NO_CHANGE
1411 * @retval None
1412 */
1413 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
1414 {
1415 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
1416 }
1417
1418 /**
1419 * @brief Get Destination increment mode.
1420 *
1421 * Register|BitsName
1422 * --------|--------
1423 * CTL_LO | DINC
1424 *
1425 * @param DMAx DMAx instance
1426 * @param channel This parameter can be one of the following values:
1427 * @arg @ref LL_DMA_CHANNEL_0
1428 * @arg @ref LL_DMA_CHANNEL_1
1429 * @arg @ref LL_DMA_CHANNEL_2
1430 * @arg @ref LL_DMA_CHANNEL_3
1431 * @arg @ref LL_DMA_CHANNEL_4
1432 * @arg @ref LL_DMA_CHANNEL_5
1433 * @arg @ref LL_DMA_CHANNEL_6
1434 * @arg @ref LL_DMA_CHANNEL_7
1435 * @retval Returned value can be one of the following values:
1436 * @arg @ref LL_DMA_DST_INCREMENT
1437 * @arg @ref LL_DMA_DST_DECREMENT
1438 * @arg @ref LL_DMA_DST_NO_CHANGE
1439 */
1440 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
1441 {
1442 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
1443 }
1444
1445 /**
1446 * @brief Set Source transfer width.
1447 *
1448 * Register|BitsName
1449 * --------|--------
1450 * CTL_LO | SRC_TR_WIDTH
1451 *
1452 * @param DMAx DMAx instance
1453 * @param channel This parameter can be one of the following values:
1454 * @arg @ref LL_DMA_CHANNEL_0
1455 * @arg @ref LL_DMA_CHANNEL_1
1456 * @arg @ref LL_DMA_CHANNEL_2
1457 * @arg @ref LL_DMA_CHANNEL_3
1458 * @arg @ref LL_DMA_CHANNEL_4
1459 * @arg @ref LL_DMA_CHANNEL_5
1460 * @arg @ref LL_DMA_CHANNEL_6
1461 * @arg @ref LL_DMA_CHANNEL_7
1462 * @param src_width This parameter can be one of the following values:
1463 * @arg @ref LL_DMA_SDATAALIGN_BYTE
1464 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
1465 * @arg @ref LL_DMA_SDATAALIGN_WORD
1466 * @retval None
1467 */
1468 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
1469 {
1470 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
1471 }
1472
1473 /**
1474 * @brief Get Source transfer width.
1475 *
1476 * Register|BitsName
1477 * --------|--------
1478 * CTL_LO | SRC_TR_WIDTH
1479 *
1480 * @param DMAx DMAx instance
1481 * @param channel This parameter can be one of the following values:
1482 * @arg @ref LL_DMA_CHANNEL_0
1483 * @arg @ref LL_DMA_CHANNEL_1
1484 * @arg @ref LL_DMA_CHANNEL_2
1485 * @arg @ref LL_DMA_CHANNEL_3
1486 * @arg @ref LL_DMA_CHANNEL_4
1487 * @arg @ref LL_DMA_CHANNEL_5
1488 * @arg @ref LL_DMA_CHANNEL_6
1489 * @arg @ref LL_DMA_CHANNEL_7
1490 * @retval Returned value can be one of the following values:
1491 * @arg @ref LL_DMA_SDATAALIGN_BYTE
1492 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
1493 * @arg @ref LL_DMA_SDATAALIGN_WORD
1494 */
1495 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
1496 {
1497 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
1498 }
1499
1500 /**
1501 * @brief Set Destination transfer width.
1502 *
1503 * Register|BitsName
1504 * --------|--------
1505 * CTL_LO | DST_TR_WIDTH
1506 *
1507 * @param DMAx DMAx instance
1508 * @param channel This parameter can be one of the following values:
1509 * @arg @ref LL_DMA_CHANNEL_0
1510 * @arg @ref LL_DMA_CHANNEL_1
1511 * @arg @ref LL_DMA_CHANNEL_2
1512 * @arg @ref LL_DMA_CHANNEL_3
1513 * @arg @ref LL_DMA_CHANNEL_4
1514 * @arg @ref LL_DMA_CHANNEL_5
1515 * @arg @ref LL_DMA_CHANNEL_6
1516 * @arg @ref LL_DMA_CHANNEL_7
1517 * @param dst_width This parameter can be one of the following values:
1518 * @arg @ref LL_DMA_DDATAALIGN_BYTE
1519 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
1520 * @arg @ref LL_DMA_DDATAALIGN_WORD
1521 * @retval None
1522 */
1523 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
1524 {
1525 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1526 }
1527
1528 /**
1529 * @brief Get Destination transfer width.
1530 *
1531 * Register|BitsName
1532 * --------|--------
1533 * CTL_LO | DST_TR_WIDTH
1534 *
1535 * @param DMAx DMAx instance
1536 * @param channel This parameter can be one of the following values:
1537 * @arg @ref LL_DMA_CHANNEL_0
1538 * @arg @ref LL_DMA_CHANNEL_1
1539 * @arg @ref LL_DMA_CHANNEL_2
1540 * @arg @ref LL_DMA_CHANNEL_3
1541 * @arg @ref LL_DMA_CHANNEL_4
1542 * @arg @ref LL_DMA_CHANNEL_5
1543 * @arg @ref LL_DMA_CHANNEL_6
1544 * @arg @ref LL_DMA_CHANNEL_7
1545 * @retval Returned value can be one of the following values:
1546 * @arg @ref LL_DMA_DDATAALIGN_BYTE
1547 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
1548 * @arg @ref LL_DMA_DDATAALIGN_WORD
1549 */
1550 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
1551 {
1552 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1553 }
1554
1555 /**
1556 * @brief Set Source Burst Transaction Length.
1557 *
1558 * Register|BitsName
1559 * --------|--------
1560 * CTL_LO | SRC_MSIZE
1561 *
1562 * @param DMAx DMAx instance
1563 * @param channel This parameter can be one of the following values:
1564 * @arg @ref LL_DMA_CHANNEL_0
1565 * @arg @ref LL_DMA_CHANNEL_1
1566 * @arg @ref LL_DMA_CHANNEL_2
1567 * @arg @ref LL_DMA_CHANNEL_3
1568 * @arg @ref LL_DMA_CHANNEL_4
1569 * @arg @ref LL_DMA_CHANNEL_5
1570 * @arg @ref LL_DMA_CHANNEL_6
1571 * @arg @ref LL_DMA_CHANNEL_7
1572 * @param burst_length This parameter can be one of the following values:
1573 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1574 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1575 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1576 * @retval None
1577 */
1578 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1579 {
1580 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1581 }
1582
1583 /**
1584 * @brief Get Burst Transaction Length.
1585 *
1586 * Register|BitsName
1587 * --------|--------
1588 * CTL_LO | SRC_MSIZE
1589 *
1590 * @param DMAx DMAx instance
1591 * @param channel This parameter can be one of the following values:
1592 * @arg @ref LL_DMA_CHANNEL_0
1593 * @arg @ref LL_DMA_CHANNEL_1
1594 * @arg @ref LL_DMA_CHANNEL_2
1595 * @arg @ref LL_DMA_CHANNEL_3
1596 * @arg @ref LL_DMA_CHANNEL_4
1597 * @arg @ref LL_DMA_CHANNEL_5
1598 * @arg @ref LL_DMA_CHANNEL_6
1599 * @arg @ref LL_DMA_CHANNEL_7
1600 * @retval Returned value can be one of the following values:
1601 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1602 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1603 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1604 */
1605 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
1606 {
1607 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1608 }
1609
1610 /**
1611 * @brief Set Destination Burst Transaction Length.
1612 *
1613 * Register|BitsName
1614 * --------|--------
1615 * CTL_LO | DST_MSIZE
1616 *
1617 * @param DMAx DMAx instance
1618 * @param channel This parameter can be one of the following values:
1619 * @arg @ref LL_DMA_CHANNEL_0
1620 * @arg @ref LL_DMA_CHANNEL_1
1621 * @arg @ref LL_DMA_CHANNEL_2
1622 * @arg @ref LL_DMA_CHANNEL_3
1623 * @arg @ref LL_DMA_CHANNEL_4
1624 * @arg @ref LL_DMA_CHANNEL_5
1625 * @arg @ref LL_DMA_CHANNEL_6
1626 * @arg @ref LL_DMA_CHANNEL_7
1627 * @param burst_length This parameter can be one of the following values:
1628 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1629 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1630 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1631 * @retval None
1632 */
1633 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1634 {
1635 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1636 }
1637
1638 /**
1639 * @brief Get Destination Burst Transaction Length.
1640 *
1641 * Register|BitsName
1642 * --------|--------
1643 * CTL_LO | DST_MSIZE
1644 *
1645 * @param DMAx DMAx instance
1646 * @param channel This parameter can be one of the following values:
1647 * @arg @ref LL_DMA_CHANNEL_0
1648 * @arg @ref LL_DMA_CHANNEL_1
1649 * @arg @ref LL_DMA_CHANNEL_2
1650 * @arg @ref LL_DMA_CHANNEL_3
1651 * @arg @ref LL_DMA_CHANNEL_4
1652 * @arg @ref LL_DMA_CHANNEL_5
1653 * @arg @ref LL_DMA_CHANNEL_6
1654 * @arg @ref LL_DMA_CHANNEL_7
1655 * @retval Returned value can be one of the following values:
1656 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1657 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1658 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1659 */
1660 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
1661 {
1662 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1663 }
1664
1665 /**
1666 * @brief Set Channel priority level.
1667 *
1668 * Register|BitsName
1669 * --------|--------
1670 * CFG_LO | CH_PRIOR
1671 *
1672 * @param DMAx DMAx instance
1673 * @param channel This parameter can be one of the following values:
1674 * @arg @ref LL_DMA_CHANNEL_0
1675 * @arg @ref LL_DMA_CHANNEL_1
1676 * @arg @ref LL_DMA_CHANNEL_2
1677 * @arg @ref LL_DMA_CHANNEL_3
1678 * @arg @ref LL_DMA_CHANNEL_4
1679 * @arg @ref LL_DMA_CHANNEL_5
1680 * @arg @ref LL_DMA_CHANNEL_6
1681 * @arg @ref LL_DMA_CHANNEL_7
1682 * @param priority This parameter can be one of the following values:
1683 * @arg @ref LL_DMA_PRIORITY_0
1684 * @arg @ref LL_DMA_PRIORITY_1
1685 * @arg @ref LL_DMA_PRIORITY_2
1686 * @arg @ref LL_DMA_PRIORITY_3
1687 * @arg @ref LL_DMA_PRIORITY_4
1688 * @arg @ref LL_DMA_PRIORITY_5
1689 * @arg @ref LL_DMA_PRIORITY_6
1690 * @arg @ref LL_DMA_PRIORITY_7
1691 * @retval None
1692 */
1693 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
1694 {
1695 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1696 }
1697
1698 /**
1699 * @brief Get Channel priority level.
1700 *
1701 * Register|BitsName
1702 * --------|--------
1703 * CFG_LO | CH_PRIOR
1704 *
1705 * @param DMAx DMAx instance
1706 * @param channel This parameter can be one of the following values:
1707 * @arg @ref LL_DMA_CHANNEL_0
1708 * @arg @ref LL_DMA_CHANNEL_1
1709 * @arg @ref LL_DMA_CHANNEL_2
1710 * @arg @ref LL_DMA_CHANNEL_3
1711 * @arg @ref LL_DMA_CHANNEL_4
1712 * @arg @ref LL_DMA_CHANNEL_5
1713 * @arg @ref LL_DMA_CHANNEL_6
1714 * @arg @ref LL_DMA_CHANNEL_7
1715 * @retval Returned value can be one of the following values:
1716 * @arg @ref LL_DMA_PRIORITY_0
1717 * @arg @ref LL_DMA_PRIORITY_1
1718 * @arg @ref LL_DMA_PRIORITY_2
1719 * @arg @ref LL_DMA_PRIORITY_3
1720 * @arg @ref LL_DMA_PRIORITY_4
1721 * @arg @ref LL_DMA_PRIORITY_5
1722 * @arg @ref LL_DMA_PRIORITY_6
1723 * @arg @ref LL_DMA_PRIORITY_7
1724 */
1725 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
1726 {
1727 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1728 }
1729
1730 /**
1731 * @brief Set the block size of a transfer.
1732 * @note This action has no effect if channel is enabled.
1733 *
1734 * Register|BitsName
1735 * --------|--------
1736 * CTL_HI | BLOCK_TS
1737 *
1738 * @param DMAx DMAx instance
1739 * @param channel This parameter can be one of the following values:
1740 * @arg @ref LL_DMA_CHANNEL_0
1741 * @arg @ref LL_DMA_CHANNEL_1
1742 * @arg @ref LL_DMA_CHANNEL_2
1743 * @arg @ref LL_DMA_CHANNEL_3
1744 * @arg @ref LL_DMA_CHANNEL_4
1745 * @arg @ref LL_DMA_CHANNEL_5
1746 * @arg @ref LL_DMA_CHANNEL_6
1747 * @arg @ref LL_DMA_CHANNEL_7
1748 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1749 * @retval None
1750 */
1751 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1752 {
1753 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1754 }
1755
1756 /**
1757 * @brief Get the block size of a transfer.
1758 * @note Once the channel is enabled, the return value indicate the
1759 * remaining bytes to be transmitted.
1760 *
1761 * Register|BitsName
1762 * --------|--------
1763 * CTL_HI | BLOCK_TS
1764 *
1765 * @param DMAx DMAx instance
1766 * @param channel This parameter can be one of the following values:
1767 * @arg @ref LL_DMA_CHANNEL_0
1768 * @arg @ref LL_DMA_CHANNEL_1
1769 * @arg @ref LL_DMA_CHANNEL_2
1770 * @arg @ref LL_DMA_CHANNEL_3
1771 * @arg @ref LL_DMA_CHANNEL_4
1772 * @arg @ref LL_DMA_CHANNEL_5
1773 * @arg @ref LL_DMA_CHANNEL_6
1774 * @arg @ref LL_DMA_CHANNEL_7
1775 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1776 */
1777 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1778 {
1779 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1780 }
1781
1782 /**
1783 * @brief Configure the Source and Destination addresses.
1784 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1785 *
1786 * Register|BitsName
1787 * --------|--------
1788 * SAR | SAR
1789 * DAR | DAR
1790 * CTL_LO | TT_FC
1791 *
1792 * @param DMAx DMAx instance
1793 * @param channel This parameter can be one of the following values:
1794 * @arg @ref LL_DMA_CHANNEL_0
1795 * @arg @ref LL_DMA_CHANNEL_1
1796 * @arg @ref LL_DMA_CHANNEL_2
1797 * @arg @ref LL_DMA_CHANNEL_3
1798 * @arg @ref LL_DMA_CHANNEL_4
1799 * @arg @ref LL_DMA_CHANNEL_5
1800 * @arg @ref LL_DMA_CHANNEL_6
1801 * @arg @ref LL_DMA_CHANNEL_7
1802 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1803 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1804 * @param direction This parameter can be one of the following values:
1805 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1806 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1807 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1808 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1809 * @retval None
1810 */
1811 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx,
1812 uint32_t channel,
1813 uint32_t src_address,
1814 uint32_t dst_address,
1815 uint32_t direction)
1816 {
1817 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1818 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1819 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1820 }
1821
1822 /**
1823 * @brief Set the Source address.
1824 *
1825 * Register|BitsName
1826 * --------|--------
1827 * SAR | SAR
1828 *
1829 * @param DMAx DMAx instance
1830 * @param channel This parameter can be one of the following values:
1831 * @arg @ref LL_DMA_CHANNEL_0
1832 * @arg @ref LL_DMA_CHANNEL_1
1833 * @arg @ref LL_DMA_CHANNEL_2
1834 * @arg @ref LL_DMA_CHANNEL_3
1835 * @arg @ref LL_DMA_CHANNEL_4
1836 * @arg @ref LL_DMA_CHANNEL_5
1837 * @arg @ref LL_DMA_CHANNEL_6
1838 * @arg @ref LL_DMA_CHANNEL_7
1839 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1840 * @retval None
1841 */
1842 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1843 {
1844 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1845 }
1846
1847 /**
1848 * @brief Set the Destination address.
1849 *
1850 * Register|BitsName
1851 * --------|--------
1852 * DAR | DAR
1853 *
1854 * @param DMAx DMAx instance
1855 * @param channel This parameter can be one of the following values:
1856 * @arg @ref LL_DMA_CHANNEL_0
1857 * @arg @ref LL_DMA_CHANNEL_1
1858 * @arg @ref LL_DMA_CHANNEL_2
1859 * @arg @ref LL_DMA_CHANNEL_3
1860 * @arg @ref LL_DMA_CHANNEL_4
1861 * @arg @ref LL_DMA_CHANNEL_5
1862 * @arg @ref LL_DMA_CHANNEL_6
1863 * @arg @ref LL_DMA_CHANNEL_7
1864 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1865 * @retval None
1866 */
1867 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1868 {
1869 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1870 }
1871
1872 /**
1873 * @brief Get Source address.
1874 *
1875 * Register|BitsName
1876 * --------|--------
1877 * SAR | SAR
1878 *
1879 * @param DMAx DMAx instance
1880 * @param channel This parameter can be one of the following values:
1881 * @arg @ref LL_DMA_CHANNEL_0
1882 * @arg @ref LL_DMA_CHANNEL_1
1883 * @arg @ref LL_DMA_CHANNEL_2
1884 * @arg @ref LL_DMA_CHANNEL_3
1885 * @arg @ref LL_DMA_CHANNEL_4
1886 * @arg @ref LL_DMA_CHANNEL_5
1887 * @arg @ref LL_DMA_CHANNEL_6
1888 * @arg @ref LL_DMA_CHANNEL_7
1889 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1890 */
1891 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1892 {
1893 return READ_REG(DMAx->CHANNEL[channel].SAR);
1894 }
1895
1896 /**
1897 * @brief Get Destination address.
1898 *
1899 * Register|BitsName
1900 * --------|--------
1901 * DAR | DAR
1902 *
1903 * @param DMAx DMAx instance
1904 * @param channel This parameter can be one of the following values:
1905 * @arg @ref LL_DMA_CHANNEL_0
1906 * @arg @ref LL_DMA_CHANNEL_1
1907 * @arg @ref LL_DMA_CHANNEL_2
1908 * @arg @ref LL_DMA_CHANNEL_3
1909 * @arg @ref LL_DMA_CHANNEL_4
1910 * @arg @ref LL_DMA_CHANNEL_5
1911 * @arg @ref LL_DMA_CHANNEL_6
1912 * @arg @ref LL_DMA_CHANNEL_7
1913 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1914 */
1915 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1916 {
1917 return READ_REG(DMAx->CHANNEL[channel].DAR);
1918 }
1919
1920 /**
1921 * @brief Set the Memory to Memory Source address.
1922 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1923 *
1924 * Register|BitsName
1925 * --------|--------
1926 * SAR | SAR
1927 * CTL_LO | TT_FC
1928 * @param DMAx DMAx instance
1929 * @param channel This parameter can be one of the following values:
1930 * @arg @ref LL_DMA_CHANNEL_0
1931 * @arg @ref LL_DMA_CHANNEL_1
1932 * @arg @ref LL_DMA_CHANNEL_2
1933 * @arg @ref LL_DMA_CHANNEL_3
1934 * @arg @ref LL_DMA_CHANNEL_4
1935 * @arg @ref LL_DMA_CHANNEL_5
1936 * @arg @ref LL_DMA_CHANNEL_6
1937 * @arg @ref LL_DMA_CHANNEL_7
1938 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1939 * @retval None
1940 */
1941 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1942 {
1943 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1944 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1945 }
1946
1947 /**
1948 * @brief Set the Memory to Memory Destination address.
1949 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1950 *
1951 * Register|BitsName
1952 * --------|--------
1953 * DAR | DAR
1954 * CTL_LO | TT_FC
1955 *
1956 * @param DMAx DMAx instance
1957 * @param channel This parameter can be one of the following values:
1958 * @arg @ref LL_DMA_CHANNEL_0
1959 * @arg @ref LL_DMA_CHANNEL_1
1960 * @arg @ref LL_DMA_CHANNEL_2
1961 * @arg @ref LL_DMA_CHANNEL_3
1962 * @arg @ref LL_DMA_CHANNEL_4
1963 * @arg @ref LL_DMA_CHANNEL_5
1964 * @arg @ref LL_DMA_CHANNEL_6
1965 * @arg @ref LL_DMA_CHANNEL_7
1966 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1967 * @retval None
1968 */
1969 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1970 {
1971 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1972 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1973 }
1974
1975 /**
1976 * @brief Get the Memory to Memory Source address.
1977 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1978 *
1979 * Register|BitsName
1980 * --------|--------
1981 * SAR | SAR
1982 *
1983 * @param DMAx DMAx instance
1984 * @param channel This parameter can be one of the following values:
1985 * @arg @ref LL_DMA_CHANNEL_0
1986 * @arg @ref LL_DMA_CHANNEL_1
1987 * @arg @ref LL_DMA_CHANNEL_2
1988 * @arg @ref LL_DMA_CHANNEL_3
1989 * @arg @ref LL_DMA_CHANNEL_4
1990 * @arg @ref LL_DMA_CHANNEL_5
1991 * @arg @ref LL_DMA_CHANNEL_6
1992 * @arg @ref LL_DMA_CHANNEL_7
1993 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1994 */
1995 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1996 {
1997 return READ_REG(DMAx->CHANNEL[channel].SAR);
1998 }
1999
2000 /**
2001 * @brief Get the Memory to Memory Destination address.
2002 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
2003 *
2004 * Register|BitsName
2005 * --------|--------
2006 * DAR | DAR
2007 *
2008 * @param DMAx DMAx instance
2009 * @param channel This parameter can be one of the following values:
2010 * @arg @ref LL_DMA_CHANNEL_0
2011 * @arg @ref LL_DMA_CHANNEL_1
2012 * @arg @ref LL_DMA_CHANNEL_2
2013 * @arg @ref LL_DMA_CHANNEL_3
2014 * @arg @ref LL_DMA_CHANNEL_4
2015 * @arg @ref LL_DMA_CHANNEL_5
2016 * @arg @ref LL_DMA_CHANNEL_6
2017 * @arg @ref LL_DMA_CHANNEL_7
2018 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
2019 */
2020 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
2021 {
2022 return READ_REG(DMAx->CHANNEL[channel].DAR);
2023 }
2024
2025 /**
2026 * @brief Enable Source Status Update Enable for DMA instance on Channel x.
2027 *
2028 * Register|BitsName
2029 * --------|--------
2030 * CFG_HI | SS_UPD_EN
2031 *
2032 * @param DMAx DMAx instance
2033 * @param channel This parameter can be one of the following values:
2034 * @arg @ref LL_DMA_CHANNEL_0
2035 * @arg @ref LL_DMA_CHANNEL_1
2036 * @arg @ref LL_DMA_CHANNEL_2
2037 * @arg @ref LL_DMA_CHANNEL_3
2038 * @arg @ref LL_DMA_CHANNEL_4
2039 * @arg @ref LL_DMA_CHANNEL_5
2040 * @arg @ref LL_DMA_CHANNEL_6
2041 * @arg @ref LL_DMA_CHANNEL_7
2042 * @retval None
2043 */
2044 __STATIC_INLINE void ll_dma_enable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
2045 {
2046 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN,LL_DMA_SRC_STAT_UPDATE_ENABLE);
2047 }
2048
2049 /**
2050 * @brief Disable Source Status Update Enable for DMA instance on Channel x.
2051 *
2052 * Register|BitsName
2053 * --------|--------
2054 * CFG_HI | SS_UPD_EN
2055 *
2056 * @param DMAx DMAx instance
2057 * @param channel This parameter can be one of the following values:
2058 * @arg @ref LL_DMA_CHANNEL_0
2059 * @arg @ref LL_DMA_CHANNEL_1
2060 * @arg @ref LL_DMA_CHANNEL_2
2061 * @arg @ref LL_DMA_CHANNEL_3
2062 * @arg @ref LL_DMA_CHANNEL_4
2063 * @arg @ref LL_DMA_CHANNEL_5
2064 * @arg @ref LL_DMA_CHANNEL_6
2065 * @arg @ref LL_DMA_CHANNEL_7
2066 * @retval None
2067 */
2068 __STATIC_INLINE void ll_dma_disable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
2069 {
2070 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN,LL_DMA_SRC_STAT_UPDATE_DISABLE);
2071 }
2072
2073 /**
2074 * @brief Check if Source Status Update Enable
2075 *
2076 * Register|BitsName
2077 * --------|--------
2078 * CFG_HI | SS_UPD_EN
2079 *
2080 * @param DMAx DMA instance.
2081 * @param channel This parameter can be one of the following values:
2082 * @arg @ref LL_DMA_CHANNEL_0
2083 * @arg @ref LL_DMA_CHANNEL_1
2084 * @arg @ref LL_DMA_CHANNEL_2
2085 * @arg @ref LL_DMA_CHANNEL_3
2086 * @arg @ref LL_DMA_CHANNEL_4
2087 * @arg @ref LL_DMA_CHANNEL_5
2088 * @arg @ref LL_DMA_CHANNEL_6
2089 * @arg @ref LL_DMA_CHANNEL_7
2090 * @retval State of bit (1 or 0).
2091 */
2092 __STATIC_INLINE uint32_t ll_dma_src_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
2093 {
2094 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SS_UPD_EN) == LL_DMA_SRC_STAT_UPDATE_ENABLE);
2095 }
2096
2097 /**
2098 * @brief Enable Destination Status Update Enable for DMA instance on Channel x.
2099 *
2100 * Register|BitsName
2101 * --------|--------
2102 * CFG_HI | DS_UPD_EN
2103 *
2104 * @param DMAx DMAx instance
2105 * @param channel This parameter can be one of the following values:
2106 * @arg @ref LL_DMA_CHANNEL_0
2107 * @arg @ref LL_DMA_CHANNEL_1
2108 * @arg @ref LL_DMA_CHANNEL_2
2109 * @arg @ref LL_DMA_CHANNEL_3
2110 * @arg @ref LL_DMA_CHANNEL_4
2111 * @arg @ref LL_DMA_CHANNEL_5
2112 * @arg @ref LL_DMA_CHANNEL_6
2113 * @arg @ref LL_DMA_CHANNEL_7
2114 * @retval None
2115 */
2116 __STATIC_INLINE void ll_dma_enable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
2117 {
2118 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN,LL_DMA_DST_STAT_UPDATE_ENABLE);
2119 }
2120
2121 /**
2122 * @brief Disable Destination Status Update Enable for DMA instance on Channel x.
2123 *
2124 * Register|BitsName
2125 * --------|--------
2126 * CFG_HI | DS_UPD_EN
2127 *
2128 * @param DMAx DMAx instance
2129 * @param channel This parameter can be one of the following values:
2130 * @arg @ref LL_DMA_CHANNEL_0
2131 * @arg @ref LL_DMA_CHANNEL_1
2132 * @arg @ref LL_DMA_CHANNEL_2
2133 * @arg @ref LL_DMA_CHANNEL_3
2134 * @arg @ref LL_DMA_CHANNEL_4
2135 * @arg @ref LL_DMA_CHANNEL_5
2136 * @arg @ref LL_DMA_CHANNEL_6
2137 * @arg @ref LL_DMA_CHANNEL_7
2138 * @retval None
2139 */
2140 __STATIC_INLINE void ll_dma_disable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
2141 {
2142 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN,LL_DMA_DST_STAT_UPDATE_DISABLE);
2143 }
2144
2145 /**
2146 * @brief Check if Destination Status Update Enable
2147 *
2148 * Register|BitsName
2149 * --------|--------
2150 * CFG_HI | SS_UPD_EN
2151 *
2152 * @param DMAx DMA instance.
2153 * @param channel This parameter can be one of the following values:
2154 * @arg @ref LL_DMA_CHANNEL_0
2155 * @arg @ref LL_DMA_CHANNEL_1
2156 * @arg @ref LL_DMA_CHANNEL_2
2157 * @arg @ref LL_DMA_CHANNEL_3
2158 * @arg @ref LL_DMA_CHANNEL_4
2159 * @arg @ref LL_DMA_CHANNEL_5
2160 * @arg @ref LL_DMA_CHANNEL_6
2161 * @arg @ref LL_DMA_CHANNEL_7
2162 * @retval State of bit (1 or 0).
2163 */
2164 __STATIC_INLINE uint32_t ll_dma_dst_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
2165 {
2166 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DS_UPD_EN) == LL_DMA_DST_STAT_UPDATE_ENABLE);
2167 }
2168
2169 /**
2170 * @brief Set source peripheral for DMA instance on Channel x.
2171 *
2172 * Register|BitsName
2173 * --------|--------
2174 * CFG_HI | SRC_PER
2175 *
2176 * @param DMAx DMAx instance
2177 * @param channel This parameter can be one of the following values:
2178 * @arg @ref LL_DMA_CHANNEL_0
2179 * @arg @ref LL_DMA_CHANNEL_1
2180 * @arg @ref LL_DMA_CHANNEL_2
2181 * @arg @ref LL_DMA_CHANNEL_3
2182 * @arg @ref LL_DMA_CHANNEL_4
2183 * @arg @ref LL_DMA_CHANNEL_5
2184 * @arg @ref LL_DMA_CHANNEL_6
2185 * @arg @ref LL_DMA_CHANNEL_7
2186 * @param peripheral This parameter can be one of the following values:
2187 * @arg @ref LL_DMA0_PERIPH_QSPI0_TX
2188 * @arg @ref LL_DMA0_PERIPH_QSPI0_RX
2189 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
2190 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
2191 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2192 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2193 * @arg @ref LL_DMA0_PERIPH_UART0_TX
2194 * @arg @ref LL_DMA0_PERIPH_UART0_RX
2195 * @arg @ref LL_DMA0_PERIPH_UART1_TX
2196 * @arg @ref LL_DMA0_PERIPH_UART1_RX
2197 * @arg @ref LL_DMA0_PERIPH_SNSADC
2198 * @arg @ref LL_DMA0_PERIPH_OSPI_TX
2199 * @arg @ref LL_DMA0_PERIPH_OSPI_RX
2200 * @arg @ref LL_DMA0_PERIPH_UART2_TX
2201 * @arg @ref LL_DMA0_PERIPH_UART2_RX
2202 * @arg @ref LL_DMA0_PERIPH_I2C2_TX
2203 * @arg @ref LL_DMA0_PERIPH_I2C2_RX
2204 * @arg @ref LL_DMA0_PERIPH_UART3_TX
2205 * @arg @ref LL_DMA0_PERIPH_UART3_RX
2206 * @arg @ref LL_DMA0_PERIPH_I2C5_TX
2207 * @arg @ref LL_DMA0_PERIPH_I2C5_RX
2208 * @arg @ref LL_DMA0_PERIPH_I2C4_TX
2209 * @arg @ref LL_DMA0_PERIPH_I2C4_RX
2210 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2211 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2212 * @arg @ref LL_DMA0_PERIPH_UART4_TX
2213 * @arg @ref LL_DMA0_PERIPH_UART4_RX
2214 * @arg @ref LL_DMA0_PERIPH_QSPI1_TX
2215 * @arg @ref LL_DMA0_PERIPH_QSPI1_RX
2216 * @arg @ref LL_DMA0_PERIPH_I2C3_TX
2217 * @arg @ref LL_DMA0_PERIPH_I2C3_RX
2218 * @arg @ref LL_DMA1_PERIPH_MEM
2219 * @arg @ref LL_DMA1_PERIPH_OSPI_TX
2220 * @arg @ref LL_DMA1_PERIPH_OSPI_RX
2221 * @arg @ref LL_DMA1_PERIPH_QSPI2_TX
2222 * @arg @ref LL_DMA1_PERIPH_QSPI2_RX
2223 * @arg @ref LL_DMA1_PERIPH_I2S_M_TX
2224 * @arg @ref LL_DMA1_PERIPH_I2S_M_RX
2225 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2226 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2227 * @arg @ref LL_DMA1_PERIPH_PDM_TX
2228 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX
2229 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX
2230 * @arg @ref LL_DMA1_PERIPH_I2C0_TX
2231 * @arg @ref LL_DMA1_PERIPH_I2C0_RX
2232 * @arg @ref LL_DMA1_PERIPH_I2C1_TX
2233 * @arg @ref LL_DMA1_PERIPH_I2C1_RX
2234 * @arg @ref LL_DMA1_PERIPH_SPIM_TX
2235 * @arg @ref LL_DMA1_PERIPH_SPIM_RX
2236 * @arg @ref LL_DMA1_PERIPH_DSPIM_TX
2237 * @arg @ref LL_DMA1_PERIPH_DSPIM_RX
2238 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX_2
2239 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX_2
2240 * @arg @ref LL_DMA1_PERIPH_UART3_TX
2241 * @arg @ref LL_DMA1_PERIPH_UART3_RX
2242 * @arg @ref LL_DMA1_PERIPH_UART4_TX
2243 * @arg @ref LL_DMA1_PERIPH_UART4_RX
2244 * @arg @ref LL_DMA1_PERIPH_UART5_TX
2245 * @arg @ref LL_DMA1_PERIPH_UART5_RX
2246 * @arg @ref LL_DMA1_PERIPH_UART0_TX
2247 * @arg @ref LL_DMA1_PERIPH_UART0_RX
2248 * @retval None
2249 */
2250 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
2251 {
2252 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
2253 }
2254
2255 /**
2256 * @brief Get source peripheral for DMA instance on Channel x.
2257 *
2258 * Register|BitsName
2259 * --------|--------
2260 * CFG_HI | SRC_PER
2261 *
2262 * @param DMAx DMAx instance
2263 * @param channel This parameter can be one of the following values:
2264 * @arg @ref LL_DMA_CHANNEL_0
2265 * @arg @ref LL_DMA_CHANNEL_1
2266 * @arg @ref LL_DMA_CHANNEL_2
2267 * @arg @ref LL_DMA_CHANNEL_3
2268 * @arg @ref LL_DMA_CHANNEL_4
2269 * @arg @ref LL_DMA_CHANNEL_5
2270 * @arg @ref LL_DMA_CHANNEL_6
2271 * @arg @ref LL_DMA_CHANNEL_7
2272 */
2273 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
2274 {
2275 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
2276 }
2277
2278 /**
2279 * @brief Set destination peripheral for DMA instance on Channel x.
2280 *
2281 * Register|BitsName
2282 * --------|--------
2283 * CFG_HI | DST_PER
2284 *
2285 * @param DMAx DMAx instance
2286 * @param channel This parameter can be one of the following values:
2287 * @arg @ref LL_DMA_CHANNEL_0
2288 * @arg @ref LL_DMA_CHANNEL_1
2289 * @arg @ref LL_DMA_CHANNEL_2
2290 * @arg @ref LL_DMA_CHANNEL_3
2291 * @arg @ref LL_DMA_CHANNEL_4
2292 * @arg @ref LL_DMA_CHANNEL_5
2293 * @arg @ref LL_DMA_CHANNEL_6
2294 * @arg @ref LL_DMA_CHANNEL_7
2295 * @param peripheral This parameter can be one of the following values:
2296 * @arg @ref LL_DMA0_PERIPH_QSPI0_TX
2297 * @arg @ref LL_DMA0_PERIPH_QSPI0_RX
2298 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
2299 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
2300 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2301 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2302 * @arg @ref LL_DMA0_PERIPH_UART0_TX
2303 * @arg @ref LL_DMA0_PERIPH_UART0_RX
2304 * @arg @ref LL_DMA0_PERIPH_UART1_TX
2305 * @arg @ref LL_DMA0_PERIPH_UART1_RX
2306 * @arg @ref LL_DMA0_PERIPH_SNSADC
2307 * @arg @ref LL_DMA0_PERIPH_OSPI_TX
2308 * @arg @ref LL_DMA0_PERIPH_OSPI_RX
2309 * @arg @ref LL_DMA0_PERIPH_UART2_TX
2310 * @arg @ref LL_DMA0_PERIPH_UART2_RX
2311 * @arg @ref LL_DMA0_PERIPH_I2C2_TX
2312 * @arg @ref LL_DMA0_PERIPH_I2C2_RX
2313 * @arg @ref LL_DMA0_PERIPH_UART3_TX
2314 * @arg @ref LL_DMA0_PERIPH_UART3_RX
2315 * @arg @ref LL_DMA0_PERIPH_I2C5_TX
2316 * @arg @ref LL_DMA0_PERIPH_I2C5_RX
2317 * @arg @ref LL_DMA0_PERIPH_I2C4_TX
2318 * @arg @ref LL_DMA0_PERIPH_I2C4_RX
2319 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
2320 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
2321 * @arg @ref LL_DMA0_PERIPH_UART4_TX
2322 * @arg @ref LL_DMA0_PERIPH_UART4_RX
2323 * @arg @ref LL_DMA0_PERIPH_QSPI1_TX
2324 * @arg @ref LL_DMA0_PERIPH_QSPI1_RX
2325 * @arg @ref LL_DMA0_PERIPH_I2C3_TX
2326 * @arg @ref LL_DMA0_PERIPH_I2C3_RX
2327 * @arg @ref LL_DMA1_PERIPH_MEM
2328 * @arg @ref LL_DMA1_PERIPH_OSPI_TX
2329 * @arg @ref LL_DMA1_PERIPH_OSPI_RX
2330 * @arg @ref LL_DMA1_PERIPH_QSPI2_TX
2331 * @arg @ref LL_DMA1_PERIPH_QSPI2_RX
2332 * @arg @ref LL_DMA1_PERIPH_I2S_M_TX
2333 * @arg @ref LL_DMA1_PERIPH_I2S_M_RX
2334 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2335 * @arg @ref LL_DMA1_PERIPH_I2S_S_TX
2336 * @arg @ref LL_DMA1_PERIPH_PDM_TX
2337 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX
2338 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX
2339 * @arg @ref LL_DMA1_PERIPH_I2C0_TX
2340 * @arg @ref LL_DMA1_PERIPH_I2C0_RX
2341 * @arg @ref LL_DMA1_PERIPH_I2C1_TX
2342 * @arg @ref LL_DMA1_PERIPH_I2C1_RX
2343 * @arg @ref LL_DMA1_PERIPH_SPIM_TX
2344 * @arg @ref LL_DMA1_PERIPH_SPIM_RX
2345 * @arg @ref LL_DMA1_PERIPH_DSPIM_TX
2346 * @arg @ref LL_DMA1_PERIPH_DSPIM_RX
2347 * @arg @ref LL_DMA1_PERIPH_QSPI1_TX_2
2348 * @arg @ref LL_DMA1_PERIPH_QSPI1_RX_2
2349 * @arg @ref LL_DMA1_PERIPH_UART3_TX
2350 * @arg @ref LL_DMA1_PERIPH_UART3_RX
2351 * @arg @ref LL_DMA1_PERIPH_UART4_TX
2352 * @arg @ref LL_DMA1_PERIPH_UART4_RX
2353 * @arg @ref LL_DMA1_PERIPH_UART5_TX
2354 * @arg @ref LL_DMA1_PERIPH_UART5_RX
2355 * @arg @ref LL_DMA1_PERIPH_UART0_TX
2356 * @arg @ref LL_DMA1_PERIPH_UART0_RX
2357 * @retval None
2358 */
2359 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
2360 {
2361 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
2362 }
2363
2364 /**
2365 * @brief Get destination peripheral for DMA instance on Channel x.
2366 *
2367 * Register|BitsName
2368 * --------|--------
2369 * CFG_HI | DST_PER
2370 *
2371 * @param DMAx DMAx instance
2372 * @param channel This parameter can be one of the following values:
2373 * @arg @ref LL_DMA_CHANNEL_0
2374 * @arg @ref LL_DMA_CHANNEL_1
2375 * @arg @ref LL_DMA_CHANNEL_2
2376 * @arg @ref LL_DMA_CHANNEL_3
2377 * @arg @ref LL_DMA_CHANNEL_4
2378 * @arg @ref LL_DMA_CHANNEL_5
2379 * @arg @ref LL_DMA_CHANNEL_6
2380 * @arg @ref LL_DMA_CHANNEL_7
2381 */
2382 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
2383 {
2384 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
2385 }
2386
2387 /**
2388 * @brief Set source and destination source handshaking interface.
2389 *
2390 * Register|BitsName
2391 * --------|--------
2392 * CFG_HI | DST_PER
2393 *
2394 * @param DMAx DMAx instance
2395 * @param channel This parameter can be one of the following values:
2396 * @arg @ref LL_DMA_CHANNEL_0
2397 * @arg @ref LL_DMA_CHANNEL_1
2398 * @arg @ref LL_DMA_CHANNEL_2
2399 * @arg @ref LL_DMA_CHANNEL_3
2400 * @arg @ref LL_DMA_CHANNEL_4
2401 * @arg @ref LL_DMA_CHANNEL_5
2402 * @arg @ref LL_DMA_CHANNEL_6
2403 * @arg @ref LL_DMA_CHANNEL_7
2404 * @param src_handshaking This parameter can be one of the following values:
2405 * @arg @ref LL_DMA_SHANDSHAKING_HW
2406 * @arg @ref LL_DMA_SHANDSHAKING_HW
2407 * @param dst_handshaking This parameter can be one of the following values:
2408 * @arg @ref LL_DMA_DHANDSHAKING_HW
2409 * @arg @ref LL_DMA_DHANDSHAKING_HW
2410 * @retval None
2411 */
2412 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
2413 {
2414 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
2415 src_handshaking | dst_handshaking);
2416 }
2417
2418 /**
2419 * @brief Set source gather interval.
2420 *
2421 * Register|BitsName
2422 * --------|--------
2423 * SGR | SGI
2424 *
2425 * @param DMAx DMAx instance.
2426 * @param channel This parameter can be one of the following values:
2427 * @arg @ref LL_DMA_CHANNEL_0
2428 * @arg @ref LL_DMA_CHANNEL_1
2429 * @arg @ref LL_DMA_CHANNEL_2
2430 * @arg @ref LL_DMA_CHANNEL_3
2431 * @arg @ref LL_DMA_CHANNEL_4
2432 * @arg @ref LL_DMA_CHANNEL_5
2433 * @arg @ref LL_DMA_CHANNEL_6
2434 * @arg @ref LL_DMA_CHANNEL_7
2435 * @param src_gather_sgi This parameter can be one of the following values:
2436 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2437 * @retval None
2438 */
2439 __STATIC_INLINE void ll_dma_set_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgi)
2440 {
2441 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI, src_gather_sgi << DMA_SGR_SGI_Pos );
2442 }
2443
2444 /**
2445 * @brief Get source gather interval.
2446 *
2447 * Register|BitsName
2448 * --------|--------
2449 * SGR | SGI
2450 *
2451 * @param DMAx DMAx instance
2452 * @param channel This parameter can be one of the following values:
2453 * @arg @ref LL_DMA_CHANNEL_0
2454 * @arg @ref LL_DMA_CHANNEL_1
2455 * @arg @ref LL_DMA_CHANNEL_2
2456 * @arg @ref LL_DMA_CHANNEL_3
2457 * @arg @ref LL_DMA_CHANNEL_4
2458 * @arg @ref LL_DMA_CHANNEL_5
2459 * @arg @ref LL_DMA_CHANNEL_6
2460 * @arg @ref LL_DMA_CHANNEL_7
2461 * @retval Returned value can be one of the following values:
2462 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2463 */
2464 __STATIC_INLINE uint32_t ll_dma_get_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel)
2465 {
2466 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI) >> DMA_SGR_SGI_Pos);
2467 }
2468
2469 /**
2470 * @brief Set source gather count.
2471 *
2472 * Register|BitsName
2473 * --------|--------
2474 * SGR | SGC
2475 *
2476 * @param DMAx DMAx instance
2477 * @param channel This parameter can be one of the following values:
2478 * @arg @ref LL_DMA_CHANNEL_0
2479 * @arg @ref LL_DMA_CHANNEL_1
2480 * @arg @ref LL_DMA_CHANNEL_2
2481 * @arg @ref LL_DMA_CHANNEL_3
2482 * @arg @ref LL_DMA_CHANNEL_4
2483 * @arg @ref LL_DMA_CHANNEL_5
2484 * @arg @ref LL_DMA_CHANNEL_6
2485 * @arg @ref LL_DMA_CHANNEL_7
2486 * @param src_gather_sgc This parameter can be one of the following values:
2487 Between Min_Data = 0 and Max_Data = 0xFFF.
2488 * @retval None
2489 */
2490 __STATIC_INLINE void ll_dma_set_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgc)
2491 {
2492 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC, src_gather_sgc << DMA_SGR_SGC_Pos );
2493 }
2494
2495 /**
2496 * @brief Get source gather count.
2497 *
2498 * Register|BitsName
2499 * --------|--------
2500 * SGR | SGC
2501 *
2502 * @param DMAx DMAx instance
2503 * @param channel This parameter can be one of the following values:
2504 * @arg @ref LL_DMA_CHANNEL_0
2505 * @arg @ref LL_DMA_CHANNEL_1
2506 * @arg @ref LL_DMA_CHANNEL_2
2507 * @arg @ref LL_DMA_CHANNEL_3
2508 * @arg @ref LL_DMA_CHANNEL_4
2509 * @arg @ref LL_DMA_CHANNEL_5
2510 * @arg @ref LL_DMA_CHANNEL_6
2511 * @arg @ref LL_DMA_CHANNEL_7
2512 * @retval Returned value can be one of the following values:
2513 Between Min_Data = 0 and Max_Data = 0xFFF.
2514 */
2515 __STATIC_INLINE uint32_t ll_dma_get_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel)
2516 {
2517 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC) >> DMA_SGR_SGC_Pos);
2518 }
2519
2520 /**
2521 * @brief Set destination scatter interval.
2522 *
2523 * Register|BitsName
2524 * --------|--------
2525 * DSR | DSI
2526 *
2527 * @param DMAx DMAx instance.
2528 * @param channel This parameter can be one of the following values:
2529 * @arg @ref LL_DMA_CHANNEL_0
2530 * @arg @ref LL_DMA_CHANNEL_1
2531 * @arg @ref LL_DMA_CHANNEL_2
2532 * @arg @ref LL_DMA_CHANNEL_3
2533 * @arg @ref LL_DMA_CHANNEL_4
2534 * @arg @ref LL_DMA_CHANNEL_5
2535 * @arg @ref LL_DMA_CHANNEL_6
2536 * @arg @ref LL_DMA_CHANNEL_7
2537 * @param dst_scatter_dsi This parameter can be one of the following values:
2538 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2539 * @retval None
2540 */
2541 __STATIC_INLINE void ll_dma_set_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsi)
2542 {
2543 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI, dst_scatter_dsi << DMA_DSR_DSI_Pos );
2544 }
2545
2546 /**
2547 * @brief Get Set destination scatter interval.
2548 *
2549 * Register|BitsName
2550 * --------|--------
2551 * DSR | DSI
2552 *
2553 * @param DMAx DMAx instance
2554 * @param channel This parameter can be one of the following values:
2555 * @arg @ref LL_DMA_CHANNEL_0
2556 * @arg @ref LL_DMA_CHANNEL_1
2557 * @arg @ref LL_DMA_CHANNEL_2
2558 * @arg @ref LL_DMA_CHANNEL_3
2559 * @arg @ref LL_DMA_CHANNEL_4
2560 * @arg @ref LL_DMA_CHANNEL_5
2561 * @arg @ref LL_DMA_CHANNEL_6
2562 * @arg @ref LL_DMA_CHANNEL_7
2563 * @retval Returned value can be one of the following values:
2564 Between Min_Data = 0 and Max_Data = 0xFFFFF.
2565 */
2566 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel)
2567 {
2568 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI) >> DMA_DSR_DSI_Pos);
2569 }
2570
2571 /**
2572 * @brief Set destination scatter count.
2573 *
2574 * Register|BitsName
2575 * --------|--------
2576 * DSR | DSC
2577 *
2578 * @param DMAx DMAx instance
2579 * @param channel This parameter can be one of the following values:
2580 * @arg @ref LL_DMA_CHANNEL_0
2581 * @arg @ref LL_DMA_CHANNEL_1
2582 * @arg @ref LL_DMA_CHANNEL_2
2583 * @arg @ref LL_DMA_CHANNEL_3
2584 * @arg @ref LL_DMA_CHANNEL_4
2585 * @arg @ref LL_DMA_CHANNEL_5
2586 * @arg @ref LL_DMA_CHANNEL_6
2587 * @arg @ref LL_DMA_CHANNEL_7
2588 * @param dst_scatter_dsc This parameter can be one of the following values:
2589 Between Min_Data = 0 and Max_Data = 0xFFF.
2590 * @retval None
2591 */
2592 __STATIC_INLINE void ll_dma_set_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsc)
2593 {
2594 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC, dst_scatter_dsc << DMA_DSR_DSC_Pos );
2595 }
2596
2597 /**
2598 * @brief Get destination scatter count..
2599 *
2600 * Register|BitsName
2601 * --------|--------
2602 * DSR | DSC
2603 *
2604 * @param DMAx DMAx instance
2605 * @param channel This parameter can be one of the following values:
2606 * @arg @ref LL_DMA_CHANNEL_0
2607 * @arg @ref LL_DMA_CHANNEL_1
2608 * @arg @ref LL_DMA_CHANNEL_2
2609 * @arg @ref LL_DMA_CHANNEL_3
2610 * @arg @ref LL_DMA_CHANNEL_4
2611 * @arg @ref LL_DMA_CHANNEL_5
2612 * @arg @ref LL_DMA_CHANNEL_6
2613 * @arg @ref LL_DMA_CHANNEL_7
2614 * @retval Returned value can be one of the following values:
2615 Between Min_Data = 0 and Max_Data = 0xFFF.
2616 */
2617 __STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel)
2618 {
2619 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC) >> DMA_DSR_DSC_Pos);
2620 }
2621
2622 /**
2623 * @brief Source Single Transaction Request.
2624 *
2625 * Register|BitsName
2626 * --------|--------
2627 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
2628 * REQ_SRC | SRC_WE&SRC
2629 *
2630 * @param DMAx DMA instance.
2631 * @param channel This parameter can be one of the following values:
2632 * @arg @ref LL_DMA_CHANNEL_0
2633 * @arg @ref LL_DMA_CHANNEL_1
2634 * @arg @ref LL_DMA_CHANNEL_2
2635 * @arg @ref LL_DMA_CHANNEL_3
2636 * @arg @ref LL_DMA_CHANNEL_4
2637 * @arg @ref LL_DMA_CHANNEL_5
2638 * @arg @ref LL_DMA_CHANNEL_6
2639 * @arg @ref LL_DMA_CHANNEL_7
2640 * @retval None
2641 */
2642 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2643 {
2644 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2645 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2646 }
2647
2648 /**
2649 * @brief Source Burst Transaction Request.
2650 *
2651 * Register|BitsName
2652 * --------|--------
2653 * REQ_SRC | SRC_WE&SRC
2654 *
2655 * @param DMAx DMA instance.
2656 * @param channel This parameter can be one of the following values:
2657 * @arg @ref LL_DMA_CHANNEL_0
2658 * @arg @ref LL_DMA_CHANNEL_1
2659 * @arg @ref LL_DMA_CHANNEL_2
2660 * @arg @ref LL_DMA_CHANNEL_3
2661 * @arg @ref LL_DMA_CHANNEL_4
2662 * @arg @ref LL_DMA_CHANNEL_5
2663 * @arg @ref LL_DMA_CHANNEL_6
2664 * @arg @ref LL_DMA_CHANNEL_7
2665 * @retval None
2666 */
2667 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2668 {
2669 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2670 }
2671
2672 /**
2673 * @brief Source Last Single Transaction Request.
2674 *
2675 * Register|BitsName
2676 * --------|--------
2677 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
2678 * LST_SRC | LST_SRC_WE&LST_SRC
2679 * REQ_SRC | SRC_WE&SRC
2680 *
2681 * @param DMAx DMA instance.
2682 * @param channel This parameter can be one of the following values:
2683 * @arg @ref LL_DMA_CHANNEL_0
2684 * @arg @ref LL_DMA_CHANNEL_1
2685 * @arg @ref LL_DMA_CHANNEL_2
2686 * @arg @ref LL_DMA_CHANNEL_3
2687 * @arg @ref LL_DMA_CHANNEL_4
2688 * @arg @ref LL_DMA_CHANNEL_5
2689 * @arg @ref LL_DMA_CHANNEL_6
2690 * @arg @ref LL_DMA_CHANNEL_7
2691 * @retval None
2692 */
2693 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2694 {
2695 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2696 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2697 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2698 }
2699
2700 /**
2701 * @brief Source Last Burst Transaction Request.
2702 *
2703 * Register|BitsName
2704 * --------|--------
2705 * LST_SRC | LST_SRC_WE&LST_SRC
2706 * REQ_SRC | SRC_WE&SRC
2707 *
2708 * @param DMAx DMA instance.
2709 * @param channel This parameter can be one of the following values:
2710 * @arg @ref LL_DMA_CHANNEL_0
2711 * @arg @ref LL_DMA_CHANNEL_1
2712 * @arg @ref LL_DMA_CHANNEL_2
2713 * @arg @ref LL_DMA_CHANNEL_3
2714 * @arg @ref LL_DMA_CHANNEL_4
2715 * @arg @ref LL_DMA_CHANNEL_5
2716 * @arg @ref LL_DMA_CHANNEL_6
2717 * @arg @ref LL_DMA_CHANNEL_7
2718 * @retval None
2719 */
2720 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2721 {
2722 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2723 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2724 }
2725
2726 /**
2727 * @brief Destination Single Transaction Request.
2728 *
2729 * Register|BitsName
2730 * --------|--------
2731 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
2732 * REQ_DST | DST_WE&DST
2733 *
2734 * @param DMAx DMA instance.
2735 * @param channel This parameter can be one of the following values:
2736 * @arg @ref LL_DMA_CHANNEL_0
2737 * @arg @ref LL_DMA_CHANNEL_1
2738 * @arg @ref LL_DMA_CHANNEL_2
2739 * @arg @ref LL_DMA_CHANNEL_3
2740 * @arg @ref LL_DMA_CHANNEL_4
2741 * @arg @ref LL_DMA_CHANNEL_5
2742 * @arg @ref LL_DMA_CHANNEL_6
2743 * @arg @ref LL_DMA_CHANNEL_7
2744 * @retval None
2745 */
2746 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2747 {
2748 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2749 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2750 }
2751
2752 /**
2753 * @brief Destination Burst Transaction Request.
2754 *
2755 * Register|BitsName
2756 * --------|--------
2757 * REQ_DST | DST_WE&DST
2758 *
2759 * @param DMAx DMA instance.
2760 * @param channel This parameter can be one of the following values:
2761 * @arg @ref LL_DMA_CHANNEL_0
2762 * @arg @ref LL_DMA_CHANNEL_1
2763 * @arg @ref LL_DMA_CHANNEL_2
2764 * @arg @ref LL_DMA_CHANNEL_3
2765 * @arg @ref LL_DMA_CHANNEL_4
2766 * @arg @ref LL_DMA_CHANNEL_5
2767 * @arg @ref LL_DMA_CHANNEL_6
2768 * @arg @ref LL_DMA_CHANNEL_7
2769 * @retval None
2770 */
2771 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2772 {
2773 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2774 }
2775
2776 /**
2777 * @brief Destination Last Single Transaction Request.
2778 *
2779 * Register|BitsName
2780 * --------|--------
2781 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
2782 * LST_DST | LST_DST_WE&LST_DST
2783 * REQ_DST | DST_WE&DST
2784 *
2785 * @param DMAx DMA instance.
2786 * @param channel This parameter can be one of the following values:
2787 * @arg @ref LL_DMA_CHANNEL_0
2788 * @arg @ref LL_DMA_CHANNEL_1
2789 * @arg @ref LL_DMA_CHANNEL_2
2790 * @arg @ref LL_DMA_CHANNEL_3
2791 * @arg @ref LL_DMA_CHANNEL_4
2792 * @arg @ref LL_DMA_CHANNEL_5
2793 * @arg @ref LL_DMA_CHANNEL_6
2794 * @arg @ref LL_DMA_CHANNEL_7
2795 * @retval None
2796 */
2797 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2798 {
2799 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2800 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2801 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2802 }
2803
2804 /**
2805 * @brief Destination Last Burst Transaction Request.
2806 *
2807 * Register|BitsName
2808 * --------|--------
2809 * LST_DST | LST_DST_WE&LST_DST
2810 * REQ_DST | DST_WE&DST
2811 *
2812 * @param DMAx DMA instance.
2813 * @param channel This parameter can be one of the following values:
2814 * @arg @ref LL_DMA_CHANNEL_0
2815 * @arg @ref LL_DMA_CHANNEL_1
2816 * @arg @ref LL_DMA_CHANNEL_2
2817 * @arg @ref LL_DMA_CHANNEL_3
2818 * @arg @ref LL_DMA_CHANNEL_4
2819 * @arg @ref LL_DMA_CHANNEL_5
2820 * @arg @ref LL_DMA_CHANNEL_6
2821 * @arg @ref LL_DMA_CHANNEL_7
2822 * @retval None
2823 */
2824 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2825 {
2826 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2827 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2828 }
2829
2830 /** @} */
2831
2832 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2833 * @{
2834 */
2835
2836 /**
2837 * @brief Get DMA Module global transfer complete interrupt status.
2838 *
2839 * Register|BitsName
2840 * --------|--------
2841 * STATUS_INT | TFR
2842 *
2843 * @param DMAx DMAx instance
2844 * @retval State of bit (1 or 0).
2845 */
2846 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
2847 {
2848 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2849 }
2850
2851 /**
2852 * @brief Get DMA Module global block complete interrupt status.
2853 *
2854 * Register|BitsName
2855 * --------|--------
2856 * STATUS_INT | BLOCK
2857 *
2858 * @param DMAx DMAx instance
2859 * @retval State of bit (1 or 0).
2860 */
2861 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
2862 {
2863 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2864 }
2865
2866 /**
2867 * @brief Get DMA Module global source transaction complete interrupt status.
2868 *
2869 * Register|BitsName
2870 * --------|--------
2871 * STATUS_INT | SRCT
2872 *
2873 * @param DMAx DMAx instance
2874 * @retval State of bit (1 or 0).
2875 */
2876 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
2877 {
2878 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2879 }
2880
2881 /**
2882 * @brief Get DMA Module global destination transaction complete interrupt status.
2883 *
2884 * Register|BitsName
2885 * --------|--------
2886 * STATUS_INT | DSTT
2887 *
2888 * @param DMAx DMAx instance
2889 * @retval State of bit (1 or 0).
2890 */
2891 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
2892 {
2893 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2894 }
2895
2896 /**
2897 * @brief Get DMA Module global error interrupt status.
2898 *
2899 * Register|BitsName
2900 * --------|--------
2901 * STATUS_INT | ERR
2902 *
2903 * @param DMAx DMAx instance
2904 * @retval State of bit (1 or 0).
2905 */
2906 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
2907 {
2908 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2909 }
2910
2911 /**
2912 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
2913 *
2914 * Register|BitsName
2915 * --------|--------
2916 * RAW_TFR | RAW
2917 *
2918 * @param DMAx DMAx instance
2919 * @param channel This parameter can be one of the following values:
2920 * @arg @ref LL_DMA_CHANNEL_0
2921 * @arg @ref LL_DMA_CHANNEL_1
2922 * @arg @ref LL_DMA_CHANNEL_2
2923 * @arg @ref LL_DMA_CHANNEL_3
2924 * @arg @ref LL_DMA_CHANNEL_4
2925 * @arg @ref LL_DMA_CHANNEL_5
2926 * @arg @ref LL_DMA_CHANNEL_6
2927 * @arg @ref LL_DMA_CHANNEL_7
2928 * @retval State of bit (1 or 0).
2929 */
2930 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
2931 {
2932 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2933 }
2934
2935 /**
2936 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
2937 *
2938 * Register|BitsName
2939 * --------|--------
2940 * RAW_BLK | RAW
2941 *
2942 * @param DMAx DMAx instance
2943 * @param channel This parameter can be one of the following values:
2944 * @arg @ref LL_DMA_CHANNEL_0
2945 * @arg @ref LL_DMA_CHANNEL_1
2946 * @arg @ref LL_DMA_CHANNEL_2
2947 * @arg @ref LL_DMA_CHANNEL_3
2948 * @arg @ref LL_DMA_CHANNEL_4
2949 * @arg @ref LL_DMA_CHANNEL_5
2950 * @arg @ref LL_DMA_CHANNEL_6
2951 * @arg @ref LL_DMA_CHANNEL_7
2952 * @retval State of bit (1 or 0).
2953 */
2954 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
2955 {
2956 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2957 }
2958
2959 /**
2960 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
2961 *
2962 * Register|BitsName
2963 * --------|--------
2964 * RAW_SRC_TRN | RAW
2965 *
2966 * @param DMAx DMAx instance
2967 * @param channel This parameter can be one of the following values:
2968 * @arg @ref LL_DMA_CHANNEL_0
2969 * @arg @ref LL_DMA_CHANNEL_1
2970 * @arg @ref LL_DMA_CHANNEL_2
2971 * @arg @ref LL_DMA_CHANNEL_3
2972 * @arg @ref LL_DMA_CHANNEL_4
2973 * @arg @ref LL_DMA_CHANNEL_5
2974 * @arg @ref LL_DMA_CHANNEL_6
2975 * @arg @ref LL_DMA_CHANNEL_7
2976 * @retval State of bit (1 or 0).
2977 */
2978 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
2979 {
2980 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2981 }
2982
2983 /**
2984 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
2985 *
2986 * Register|BitsName
2987 * --------|--------
2988 * RAW_DST_TRN | RAW
2989 *
2990 * @param DMAx DMAx instance
2991 * @param channel This parameter can be one of the following values:
2992 * @arg @ref LL_DMA_CHANNEL_0
2993 * @arg @ref LL_DMA_CHANNEL_1
2994 * @arg @ref LL_DMA_CHANNEL_2
2995 * @arg @ref LL_DMA_CHANNEL_3
2996 * @arg @ref LL_DMA_CHANNEL_4
2997 * @arg @ref LL_DMA_CHANNEL_5
2998 * @arg @ref LL_DMA_CHANNEL_6
2999 * @arg @ref LL_DMA_CHANNEL_7
3000 * @retval State of bit (1 or 0).
3001 */
3002 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
3003 {
3004 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
3005 }
3006
3007 /**
3008 * @brief Indicate the Raw Status of IntErr Interrupt flag.
3009 *
3010 * Register|BitsName
3011 * --------|--------
3012 * RAW_ERR | RAW
3013 *
3014 * @param DMAx DMAx instance
3015 * @param channel This parameter can be one of the following values:
3016 * @arg @ref LL_DMA_CHANNEL_0
3017 * @arg @ref LL_DMA_CHANNEL_1
3018 * @arg @ref LL_DMA_CHANNEL_2
3019 * @arg @ref LL_DMA_CHANNEL_3
3020 * @arg @ref LL_DMA_CHANNEL_4
3021 * @arg @ref LL_DMA_CHANNEL_5
3022 * @arg @ref LL_DMA_CHANNEL_6
3023 * @arg @ref LL_DMA_CHANNEL_7
3024 * @retval State of bit (1 or 0).
3025 */
3026 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
3027 {
3028 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
3029 }
3030
3031 /**
3032 * @brief Indicate the status of DMA Channel transfer complete flag.
3033 *
3034 * Register|BitsName
3035 * --------|--------
3036 * STAT_TFR | STATUS
3037 *
3038 * @param DMAx DMAx instance
3039 * @param channel This parameter can be one of the following values:
3040 * @arg @ref LL_DMA_CHANNEL_0
3041 * @arg @ref LL_DMA_CHANNEL_1
3042 * @arg @ref LL_DMA_CHANNEL_2
3043 * @arg @ref LL_DMA_CHANNEL_3
3044 * @arg @ref LL_DMA_CHANNEL_4
3045 * @arg @ref LL_DMA_CHANNEL_5
3046 * @arg @ref LL_DMA_CHANNEL_6
3047 * @arg @ref LL_DMA_CHANNEL_7
3048 * @retval State of bit (1 or 0).
3049 */
3050 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
3051 {
3052 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
3053 }
3054
3055 /**
3056 * @brief Indicate the status of Channel 0 transfer complete flag.
3057 *
3058 * Register|BitsName
3059 * --------|--------
3060 * STAT_TFR | STATUS
3061 *
3062 * @param DMAx DMAx instance
3063 * @retval State of bit (1 or 0).
3064 */
3065 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
3066 {
3067 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
3068 }
3069
3070 /**
3071 * @brief Indicate the status of Channel 1 transfer complete flag.
3072 *
3073 * Register|BitsName
3074 * --------|--------
3075 * STAT_TFR | STATUS
3076 *
3077 * @param DMAx DMAx instance
3078 * @retval State of bit (1 or 0).
3079 */
3080 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
3081 {
3082 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
3083 }
3084
3085 /**
3086 * @brief Indicate the status of Channel 2 transfer complete flag.
3087 *
3088 * Register|BitsName
3089 * --------|--------
3090 * STAT_TFR | STATUS
3091 *
3092 * @param DMAx DMAx instance
3093 * @retval State of bit (1 or 0).
3094 */
3095 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
3096 {
3097 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
3098 }
3099
3100 /**
3101 * @brief Indicate the status of Channel 3 transfer complete flag.
3102 *
3103 * Register|BitsName
3104 * --------|--------
3105 * STAT_TFR | STATUS
3106 *
3107 * @param DMAx DMAx instance
3108 * @retval State of bit (1 or 0).
3109 */
3110 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
3111 {
3112 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
3113 }
3114
3115 /**
3116 * @brief Indicate the status of Channel 4 transfer complete flag.
3117 *
3118 * Register|BitsName
3119 * --------|--------
3120 * STAT_TFR | STATUS
3121 *
3122 * @param DMAx DMAx instance
3123 * @retval State of bit (1 or 0).
3124 */
3125 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
3126 {
3127 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
3128 }
3129
3130 /**
3131 * @brief Indicate the status of Channel 5 transfer complete flag.
3132 *
3133 * Register|BitsName
3134 * --------|--------
3135 * STAT_TFR | STATUS
3136 *
3137 * @param DMAx DMAx instance
3138 * @retval State of bit (1 or 0).
3139 */
3140 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
3141 {
3142 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
3143 }
3144
3145 /**
3146 * @brief Indicate the status of Channel 6 transfer complete flag.
3147 *
3148 * Register|BitsName
3149 * --------|--------
3150 * STAT_TFR | STATUS
3151 *
3152 * @param DMAx DMAx instance
3153 * @retval State of bit (1 or 0).
3154 */
3155 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
3156 {
3157 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
3158 }
3159
3160 /**
3161 * @brief Indicate the status of Channel 7 transfer complete flag.
3162 *
3163 * Register|BitsName
3164 * --------|--------
3165 * STAT_TFR | STATUS
3166 *
3167 * @param DMAx DMAx instance
3168 * @retval State of bit (1 or 0).
3169 */
3170 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
3171 {
3172 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
3173 }
3174
3175 /**
3176 * @brief Indicate the status of DMA Channel block complete flag.
3177 *
3178 * Register|BitsName
3179 * --------|--------
3180 * STAT_BLK | STATUS
3181 *
3182 * @param DMAx DMAx instance
3183 * @param channel This parameter can be one of the following values:
3184 * @arg @ref LL_DMA_CHANNEL_0
3185 * @arg @ref LL_DMA_CHANNEL_1
3186 * @arg @ref LL_DMA_CHANNEL_2
3187 * @arg @ref LL_DMA_CHANNEL_3
3188 * @arg @ref LL_DMA_CHANNEL_4
3189 * @arg @ref LL_DMA_CHANNEL_5
3190 * @arg @ref LL_DMA_CHANNEL_6
3191 * @arg @ref LL_DMA_CHANNEL_7
3192 * @retval State of bit (1 or 0).
3193 */
3194 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
3195 {
3196 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
3197 }
3198
3199 /**
3200 * @brief Indicate the status of Channel 0 block complete flag.
3201 *
3202 * Register|BitsName
3203 * --------|--------
3204 * STAT_BLK | STATUS
3205 *
3206 * @param DMAx DMAx instance
3207 * @retval State of bit (1 or 0).
3208 */
3209 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
3210 {
3211 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
3212 }
3213
3214 /**
3215 * @brief Indicate the status of Channel 1 block complete flag.
3216 *
3217 * Register|BitsName
3218 * --------|--------
3219 * STAT_BLK | STATUS
3220 *
3221 * @param DMAx DMAx instance
3222 * @retval State of bit (1 or 0).
3223 */
3224 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
3225 {
3226 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
3227 }
3228
3229 /**
3230 * @brief Indicate the status of Channel 2 block complete flag.
3231 *
3232 * Register|BitsName
3233 * --------|--------
3234 * STAT_BLK | STATUS
3235 *
3236 * @param DMAx DMAx instance
3237 * @retval State of bit (1 or 0).
3238 */
3239 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
3240 {
3241 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
3242 }
3243
3244 /**
3245 * @brief Indicate the status of Channel 3 block complete flag.
3246 *
3247 * Register|BitsName
3248 * --------|--------
3249 * STAT_BLK | STATUS
3250 *
3251 * @param DMAx DMAx instance
3252 * @retval State of bit (1 or 0).
3253 */
3254 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
3255 {
3256 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
3257 }
3258
3259 /**
3260 * @brief Indicate the status of Channel 4 block complete flag.
3261 *
3262 * Register|BitsName
3263 * --------|--------
3264 * STAT_BLK | STATUS
3265 *
3266 * @param DMAx DMAx instance
3267 * @retval State of bit (1 or 0).
3268 */
3269 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
3270 {
3271 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
3272 }
3273
3274 /**
3275 * @brief Indicate the status of Channel 5 block complete flag.
3276 *
3277 * Register|BitsName
3278 * --------|--------
3279 * STAT_BLK | STATUS
3280 *
3281 * @param DMAx DMAx instance
3282 * @retval State of bit (1 or 0).
3283 */
3284 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
3285 {
3286 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
3287 }
3288
3289 /**
3290 * @brief Indicate the status of Channel 6 block complete flag.
3291 *
3292 * Register|BitsName
3293 * --------|--------
3294 * STAT_BLK | STATUS
3295 *
3296 * @param DMAx DMAx instance
3297 * @retval State of bit (1 or 0).
3298 */
3299 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
3300 {
3301 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
3302 }
3303
3304 /**
3305 * @brief Indicate the status of Channel 7 block complete flag.
3306 *
3307 * Register|BitsName
3308 * --------|--------
3309 * STAT_BLK | STATUS
3310 *
3311 * @param DMAx DMAx instance
3312 * @retval State of bit (1 or 0).
3313 */
3314 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
3315 {
3316 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
3317 }
3318
3319 /**
3320 * @brief Indicate the status of DMA Channel source transaction complete flag.
3321 *
3322 * Register|BitsName
3323 * --------|--------
3324 * STAT_SRC_TRN | STATUS
3325 *
3326 * @param DMAx DMAx instance
3327 * @param channel This parameter can be one of the following values:
3328 * @arg @ref LL_DMA_CHANNEL_0
3329 * @arg @ref LL_DMA_CHANNEL_1
3330 * @arg @ref LL_DMA_CHANNEL_2
3331 * @arg @ref LL_DMA_CHANNEL_3
3332 * @arg @ref LL_DMA_CHANNEL_4
3333 * @arg @ref LL_DMA_CHANNEL_5
3334 * @arg @ref LL_DMA_CHANNEL_6
3335 * @arg @ref LL_DMA_CHANNEL_7
3336 * @retval State of bit (1 or 0).
3337 */
3338 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
3339 {
3340 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
3341 }
3342
3343 /**
3344 * @brief Indicate the status of Channel 0 source transaction complete flag.
3345 *
3346 * Register|BitsName
3347 * --------|--------
3348 * STAT_SRC_TRN | STATUS
3349 *
3350 * @param DMAx DMAx instance
3351 * @retval State of bit (1 or 0).
3352 */
3353 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
3354 {
3355 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
3356 }
3357
3358 /**
3359 * @brief Indicate the status of Channel 1 source transaction complete flag.
3360 *
3361 * Register|BitsName
3362 * --------|--------
3363 * STAT_SRC_TRN | STATUS
3364 *
3365 * @param DMAx DMAx instance
3366 * @retval State of bit (1 or 0).
3367 */
3368 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
3369 {
3370 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
3371 }
3372
3373 /**
3374 * @brief Indicate the status of Channel 2 source transaction complete flag.
3375 *
3376 * Register|BitsName
3377 * --------|--------
3378 * STAT_SRC_TRN | STATUS
3379 *
3380 * @param DMAx DMAx instance
3381 * @retval State of bit (1 or 0).
3382 */
3383 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
3384 {
3385 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
3386 }
3387
3388 /**
3389 * @brief Indicate the status of Channel 3 source transaction complete flag.
3390 *
3391 * Register|BitsName
3392 * --------|--------
3393 * STAT_SRC_TRN | STATUS
3394 *
3395 * @param DMAx DMAx instance
3396 * @retval State of bit (1 or 0).
3397 */
3398 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
3399 {
3400 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
3401 }
3402
3403 /**
3404 * @brief Indicate the status of Channel 4 source transaction complete flag.
3405 *
3406 * Register|BitsName
3407 * --------|--------
3408 * STAT_SRC_TRN | STATUS
3409 *
3410 * @param DMAx DMAx instance
3411 * @retval State of bit (1 or 0).
3412 */
3413 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
3414 {
3415 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
3416 }
3417
3418 /**
3419 * @brief Indicate the status of Channel 5 source transaction complete flag.
3420 *
3421 * Register|BitsName
3422 * --------|--------
3423 * STAT_SRC_TRN | STATUS
3424 *
3425 * @param DMAx DMAx instance
3426 * @retval State of bit (1 or 0).
3427 */
3428 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
3429 {
3430 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
3431 }
3432
3433 /**
3434 * @brief Indicate the status of Channel 6 source transaction complete flag.
3435 *
3436 * Register|BitsName
3437 * --------|--------
3438 * STAT_SRC_TRN | STATUS
3439 *
3440 * @param DMAx DMAx instance
3441 * @retval State of bit (1 or 0).
3442 */
3443 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
3444 {
3445 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
3446 }
3447
3448 /**
3449 * @brief Indicate the status of Channel 7 source transaction complete flag.
3450 *
3451 * Register|BitsName
3452 * --------|--------
3453 * STAT_SRC_TRN | STATUS
3454 *
3455 * @param DMAx DMAx instance
3456 * @retval State of bit (1 or 0).
3457 */
3458 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
3459 {
3460 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
3461 }
3462
3463 /**
3464 * @brief Indicate the status of DMA Channel destination transaction complete flag.
3465 *
3466 * Register|BitsName
3467 * --------|--------
3468 * STAT_DST_TRN | STATUS
3469 *
3470 * @param DMAx DMAx instance
3471 * @param channel This parameter can be one of the following values:
3472 * @arg @ref LL_DMA_CHANNEL_0
3473 * @arg @ref LL_DMA_CHANNEL_1
3474 * @arg @ref LL_DMA_CHANNEL_2
3475 * @arg @ref LL_DMA_CHANNEL_3
3476 * @arg @ref LL_DMA_CHANNEL_4
3477 * @arg @ref LL_DMA_CHANNEL_5
3478 * @arg @ref LL_DMA_CHANNEL_6
3479 * @arg @ref LL_DMA_CHANNEL_7
3480 * @retval State of bit (1 or 0).
3481 */
3482 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
3483 {
3484 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
3485 }
3486
3487 /**
3488 * @brief Indicate the status of Channel 0 destination transaction complete flag.
3489 *
3490 * Register|BitsName
3491 * --------|--------
3492 * STAT_DST_TRN | STATUS
3493 *
3494 * @param DMAx DMAx instance
3495 * @retval State of bit (1 or 0).
3496 */
3497 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
3498 {
3499 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
3500 }
3501
3502 /**
3503 * @brief Indicate the status of Channel 1 destination transaction complete flag.
3504 *
3505 * Register|BitsName
3506 * --------|--------
3507 * STAT_DST_TRN | STATUS
3508 *
3509 * @param DMAx DMAx instance
3510 * @retval State of bit (1 or 0).
3511 */
3512 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
3513 {
3514 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
3515 }
3516
3517 /**
3518 * @brief Indicate the status of Channel 2 destination transaction complete flag.
3519 *
3520 * Register|BitsName
3521 * --------|--------
3522 * STAT_DST_TRN | STATUS
3523 *
3524 * @param DMAx DMAx instance
3525 * @retval State of bit (1 or 0).
3526 */
3527 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
3528 {
3529 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
3530 }
3531
3532 /**
3533 * @brief Indicate the status of Channel 3 destination transaction complete flag.
3534 *
3535 * Register|BitsName
3536 * --------|--------
3537 * STAT_DST_TRN | STATUS
3538 *
3539 * @param DMAx DMAx instance
3540 * @retval State of bit (1 or 0).
3541 */
3542 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
3543 {
3544 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
3545 }
3546
3547 /**
3548 * @brief Indicate the status of Channel 4 destination transaction complete flag.
3549 *
3550 * Register|BitsName
3551 * --------|--------
3552 * STAT_DST_TRN | STATUS
3553 *
3554 * @param DMAx DMAx instance
3555 * @retval State of bit (1 or 0).
3556 */
3557 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
3558 {
3559 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
3560 }
3561
3562 /**
3563 * @brief Indicate the status of Channel 5 destination transaction complete flag.
3564 *
3565 * Register|BitsName
3566 * --------|--------
3567 * STAT_DST_TRN | STATUS
3568 *
3569 * @param DMAx DMAx instance
3570 * @retval State of bit (1 or 0).
3571 */
3572 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
3573 {
3574 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
3575 }
3576
3577 /**
3578 * @brief Indicate the status of Channel 6 destination transaction complete flag.
3579 *
3580 * Register|BitsName
3581 * --------|--------
3582 * STAT_DST_TRN | STATUS
3583 *
3584 * @param DMAx DMAx instance
3585 * @retval State of bit (1 or 0).
3586 */
3587 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
3588 {
3589 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
3590 }
3591
3592 /**
3593 * @brief Indicate the status of Channel 7 destination transaction complete flag.
3594 *
3595 * Register|BitsName
3596 * --------|--------
3597 * STAT_DST_TRN | STATUS
3598 *
3599 * @param DMAx DMAx instance
3600 * @retval State of bit (1 or 0).
3601 */
3602 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
3603 {
3604 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
3605 }
3606
3607 /**
3608 * @brief Indicate the status of DMA Channel error flag.
3609 *
3610 * Register|BitsName
3611 * --------|--------
3612 * STAT_ERR | STATUS
3613 *
3614 * @param DMAx DMAx instance
3615 * @param channel This parameter can be one of the following values:
3616 * @arg @ref LL_DMA_CHANNEL_0
3617 * @arg @ref LL_DMA_CHANNEL_1
3618 * @arg @ref LL_DMA_CHANNEL_2
3619 * @arg @ref LL_DMA_CHANNEL_3
3620 * @arg @ref LL_DMA_CHANNEL_4
3621 * @arg @ref LL_DMA_CHANNEL_5
3622 * @arg @ref LL_DMA_CHANNEL_6
3623 * @arg @ref LL_DMA_CHANNEL_7
3624 * @retval State of bit (1 or 0).
3625 */
3626 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
3627 {
3628 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3629 }
3630
3631 /**
3632 * @brief Indicate the status of Channel 0 error flag.
3633 *
3634 * Register|BitsName
3635 * --------|--------
3636 * STAT_ERR | STATUS
3637 *
3638 * @param DMAx DMAx instance
3639 * @retval State of bit (1 or 0).
3640 */
3641 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
3642 {
3643 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3644 }
3645
3646 /**
3647 * @brief Indicate the status of Channel 1 error flag.
3648 *
3649 * Register|BitsName
3650 * --------|--------
3651 * STAT_ERR | STATUS
3652 *
3653 * @param DMAx DMAx instance
3654 * @retval State of bit (1 or 0).
3655 */
3656 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
3657 {
3658 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3659 }
3660
3661 /**
3662 * @brief Indicate the status of Channel 2 error flag.
3663 *
3664 * Register|BitsName
3665 * --------|--------
3666 * STAT_ERR | STATUS
3667 *
3668 * @param DMAx DMAx instance
3669 * @retval State of bit (1 or 0).
3670 */
3671 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
3672 {
3673 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3674 }
3675
3676 /**
3677 * @brief Indicate the status of Channel 3 error flag.
3678 *
3679 * Register|BitsName
3680 * --------|--------
3681 * STAT_ERR | STATUS
3682 *
3683 * @param DMAx DMAx instance
3684 * @retval State of bit (1 or 0).
3685 */
3686 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
3687 {
3688 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3689 }
3690
3691 /**
3692 * @brief Indicate the status of Channel 4 error flag.
3693 *
3694 * Register|BitsName
3695 * --------|--------
3696 * STAT_ERR | STATUS
3697 *
3698 * @param DMAx DMAx instance
3699 * @retval State of bit (1 or 0).
3700 */
3701 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
3702 {
3703 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3704 }
3705
3706 /**
3707 * @brief Indicate the status of Channel 5 error flag.
3708 *
3709 * Register|BitsName
3710 * --------|--------
3711 * STAT_ERR | STATUS
3712 *
3713 * @param DMAx DMAx instance
3714 * @retval State of bit (1 or 0).
3715 */
3716 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
3717 {
3718 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3719 }
3720
3721 /**
3722 * @brief Indicate the status of Channel 6 error flag.
3723 *
3724 * Register|BitsName
3725 * --------|--------
3726 * STAT_ERR | STATUS
3727 *
3728 * @param DMAx DMAx instance
3729 * @retval State of bit (1 or 0).
3730 */
3731 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
3732 {
3733 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3734 }
3735
3736 /**
3737 * @brief Indicate the status of Channel 7 error flag.
3738 *
3739 * Register|BitsName
3740 * --------|--------
3741 * STAT_ERR | STATUS
3742 *
3743 * @param DMAx DMAx instance
3744 * @retval State of bit (1 or 0).
3745 */
3746 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
3747 {
3748 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3749 }
3750
3751 /**
3752 * @brief Clear DMA Channel transfer complete flag.
3753 *
3754 * Register|BitsName
3755 * --------|--------
3756 * CLR_TFR | CLEAR
3757 *
3758 * @param DMAx DMAx instance
3759 * @param channel This parameter can be one of the following values:
3760 * @arg @ref LL_DMA_CHANNEL_0
3761 * @arg @ref LL_DMA_CHANNEL_1
3762 * @arg @ref LL_DMA_CHANNEL_2
3763 * @arg @ref LL_DMA_CHANNEL_3
3764 * @arg @ref LL_DMA_CHANNEL_4
3765 * @arg @ref LL_DMA_CHANNEL_5
3766 * @arg @ref LL_DMA_CHANNEL_6
3767 * @arg @ref LL_DMA_CHANNEL_7
3768 * @retval None.
3769 */
3770 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
3771 {
3772 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3773 }
3774
3775 /**
3776 * @brief Clear Channel 0 transfer complete flag.
3777 *
3778 * Register|BitsName
3779 * --------|--------
3780 * CLR_TFR | CLEAR
3781 *
3782 * @param DMAx DMAx instance
3783 * @retval None.
3784 */
3785 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
3786 {
3787 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3788 }
3789
3790 /**
3791 * @brief Clear Channel 1 transfer complete flag.
3792 *
3793 * Register|BitsName
3794 * --------|--------
3795 * CLR_TFR | CLEAR
3796 *
3797 * @param DMAx DMAx instance
3798 * @retval None.
3799 */
3800 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
3801 {
3802 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3803 }
3804
3805 /**
3806 * @brief Clear Channel 2 transfer complete flag.
3807 *
3808 * Register|BitsName
3809 * --------|--------
3810 * CLR_TFR | CLEAR
3811 *
3812 * @param DMAx DMAx instance
3813 * @retval None.
3814 */
3815 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
3816 {
3817 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3818 }
3819
3820 /**
3821 * @brief Clear Channel 3 transfer complete flag.
3822 *
3823 * Register|BitsName
3824 * --------|--------
3825 * CLR_TFR | CLEAR
3826 *
3827 * @param DMAx DMAx instance
3828 * @retval None.
3829 */
3830 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
3831 {
3832 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3833 }
3834
3835 /**
3836 * @brief Clear Channel 4 transfer complete flag.
3837 *
3838 * Register|BitsName
3839 * --------|--------
3840 * CLR_TFR | CLEAR
3841 *
3842 * @param DMAx DMAx instance
3843 * @retval None.
3844 */
3845 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
3846 {
3847 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3848 }
3849
3850 /**
3851 * @brief Clear Channel 5 transfer complete flag.
3852 *
3853 * Register|BitsName
3854 * --------|--------
3855 * CLR_TFR | CLEAR
3856 *
3857 * @param DMAx DMAx instance
3858 * @retval None.
3859 */
3860 __STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
3861 {
3862 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3863 }
3864
3865 /**
3866 * @brief Clear Channel 6 transfer complete flag.
3867 *
3868 * Register|BitsName
3869 * --------|--------
3870 * CLR_TFR | CLEAR
3871 *
3872 * @param DMAx DMAx instance
3873 * @retval None.
3874 */
3875 __STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
3876 {
3877 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3878 }
3879
3880 /**
3881 * @brief Clear Channel 7 transfer complete flag.
3882 *
3883 * Register|BitsName
3884 * --------|--------
3885 * CLR_TFR | CLEAR
3886 *
3887 * @param DMAx DMAx instance
3888 * @retval None.
3889 */
3890 __STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
3891 {
3892 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3893 }
3894
3895 /**
3896 * @brief Clear DMA Channel block complete flag.
3897 *
3898 * Register|BitsName
3899 * --------|--------
3900 * CLR_BLK | CLEAR
3901 *
3902 * @param DMAx DMAx instance
3903 * @param channel This parameter can be one of the following values:
3904 * @arg @ref LL_DMA_CHANNEL_0
3905 * @arg @ref LL_DMA_CHANNEL_1
3906 * @arg @ref LL_DMA_CHANNEL_2
3907 * @arg @ref LL_DMA_CHANNEL_3
3908 * @arg @ref LL_DMA_CHANNEL_4
3909 * @arg @ref LL_DMA_CHANNEL_5
3910 * @arg @ref LL_DMA_CHANNEL_6
3911 * @arg @ref LL_DMA_CHANNEL_7
3912 * @retval None.
3913 */
3914 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
3915 {
3916 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3917 }
3918
3919 /**
3920 * @brief Clear Channel 0 Block Complete flag.
3921 *
3922 * Register|BitsName
3923 * --------|--------
3924 * CLR_BLK | CLEAR
3925 *
3926 * @param DMAx DMAx instance
3927 * @retval None.
3928 */
3929 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
3930 {
3931 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3932 }
3933
3934 /**
3935 * @brief Clear Channel 1 Block Complete flag.
3936 *
3937 * Register|BitsName
3938 * --------|--------
3939 * CLR_BLK | CLEAR
3940 *
3941 * @param DMAx DMAx instance
3942 * @retval None.
3943 */
3944 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
3945 {
3946 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3947 }
3948
3949 /**
3950 * @brief Clear Channel 2 Block Complete flag.
3951 *
3952 * Register|BitsName
3953 * --------|--------
3954 * CLR_BLK | CLEAR
3955 *
3956 * @param DMAx DMAx instance
3957 * @retval None.
3958 */
3959 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
3960 {
3961 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3962 }
3963
3964 /**
3965 * @brief Clear Channel 3 Block Complete flag.
3966 *
3967 * Register|BitsName
3968 * --------|--------
3969 * CLR_BLK | CLEAR
3970 *
3971 * @param DMAx DMAx instance
3972 * @retval None.
3973 */
3974 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
3975 {
3976 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3977 }
3978
3979 /**
3980 * @brief Clear Channel 4 Block Complete flag.
3981 *
3982 * Register|BitsName
3983 * --------|--------
3984 * CLR_BLK | CLEAR
3985 *
3986 * @param DMAx DMAx instance
3987 * @retval None.
3988 */
3989 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
3990 {
3991 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
3992 }
3993
3994 /**
3995 * @brief Clear Channel 5 Block Complete flag.
3996 *
3997 * Register|BitsName
3998 * --------|--------
3999 * CLR_BLK | CLEAR
4000 *
4001 * @param DMAx DMAx instance
4002 * @retval None.
4003 */
4004 __STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
4005 {
4006 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
4007 }
4008
4009 /**
4010 * @brief Clear Channel 6 Block Cmplete flag.
4011 *
4012 * Register|BitsName
4013 * --------|--------
4014 * CLR_BLK | CLEAR
4015 *
4016 * @param DMAx DMAx instance
4017 * @retval None.
4018 */
4019 __STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
4020 {
4021 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
4022 }
4023
4024 /**
4025 * @brief Clear Channel 7 Block Complete flag.
4026 *
4027 * Register|BitsName
4028 * --------|--------
4029 * CLR_BLK | CLEAR
4030 *
4031 * @param DMAx DMAx instance
4032 * @retval None.
4033 */
4034 __STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
4035 {
4036 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
4037 }
4038
4039 /**
4040 * @brief Clear DMA Channel source transaction Complete flag.
4041 *
4042 * Register|BitsName
4043 * --------|--------
4044 * CLR_SRC_TRN | CLEAR
4045 *
4046 * @param DMAx DMAx instance
4047 * @param channel This parameter can be one of the following values:
4048 * @arg @ref LL_DMA_CHANNEL_0
4049 * @arg @ref LL_DMA_CHANNEL_1
4050 * @arg @ref LL_DMA_CHANNEL_2
4051 * @arg @ref LL_DMA_CHANNEL_3
4052 * @arg @ref LL_DMA_CHANNEL_4
4053 * @arg @ref LL_DMA_CHANNEL_5
4054 * @arg @ref LL_DMA_CHANNEL_6
4055 * @arg @ref LL_DMA_CHANNEL_7
4056 * @retval None.
4057 */
4058 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
4059 {
4060 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
4061 }
4062
4063 /**
4064 * @brief Clear Channel 0 source transaction Complete flag.
4065 *
4066 * Register|BitsName
4067 * --------|--------
4068 * CLR_SRC_TRN | CLEAR
4069 *
4070 * @param DMAx DMAx instance
4071 * @retval None.
4072 */
4073 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
4074 {
4075 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
4076 }
4077
4078 /**
4079 * @brief Clear Channel 1 source transaction Complete flag.
4080 *
4081 * Register|BitsName
4082 * --------|--------
4083 * CLR_SRC_TRN | CLEAR
4084 *
4085 * @param DMAx DMAx instance
4086 * @retval None.
4087 */
4088 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
4089 {
4090 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
4091 }
4092
4093 /**
4094 * @brief Clear Channel 2 source transaction Complete flag.
4095 *
4096 * Register|BitsName
4097 * --------|--------
4098 * CLR_SRC_TRN | CLEAR
4099 *
4100 * @param DMAx DMAx instance
4101 * @retval None.
4102 */
4103 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
4104 {
4105 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
4106 }
4107
4108 /**
4109 * @brief Clear Channel 3 source transaction Complete flag.
4110 *
4111 * Register|BitsName
4112 * --------|--------
4113 * CLR_SRC_TRN | CLEAR
4114 *
4115 * @param DMAx DMAx instance
4116 * @retval None.
4117 */
4118 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
4119 {
4120 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
4121 }
4122
4123 /**
4124 * @brief Clear Channel 4 source transaction Complete flag.
4125 *
4126 * Register|BitsName
4127 * --------|--------
4128 * CLR_SRC_TRN | CLEAR
4129 *
4130 * @param DMAx DMAx instance
4131 * @retval None.
4132 */
4133 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
4134 {
4135 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
4136 }
4137
4138 /**
4139 * @brief Clear Channel 5 source transaction Complete flag.
4140 *
4141 * Register|BitsName
4142 * --------|--------
4143 * CLR_SRC_TRN | CLEAR
4144 *
4145 * @param DMAx DMAx instance
4146 * @retval None.
4147 */
4148 __STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
4149 {
4150 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
4151 }
4152
4153 /**
4154 * @brief Clear Channel 6 source transaction Complete flag.
4155 *
4156 * Register|BitsName
4157 * --------|--------
4158 * CLR_SRC_TRN | CLEAR
4159 *
4160 * @param DMAx DMAx instance
4161 * @retval None.
4162 */
4163 __STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
4164 {
4165 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
4166 }
4167
4168 /**
4169 * @brief Clear Channel 7 source transaction Complete flag.
4170 *
4171 * Register|BitsName
4172 * --------|--------
4173 * CLR_SRC_TRN | CLEAR
4174 *
4175 * @param DMAx DMAx instance
4176 * @retval None.
4177 */
4178 __STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
4179 {
4180 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
4181 }
4182
4183 /**
4184 * @brief Clear DMA Channel destination transaction Complete flag.
4185 *
4186 * Register|BitsName
4187 * --------|--------
4188 * CLR_DST_TRN | CLEAR
4189 *
4190 * @param DMAx DMAx instance
4191 * @param channel This parameter can be one of the following values:
4192 * @arg @ref LL_DMA_CHANNEL_0
4193 * @arg @ref LL_DMA_CHANNEL_1
4194 * @arg @ref LL_DMA_CHANNEL_2
4195 * @arg @ref LL_DMA_CHANNEL_3
4196 * @arg @ref LL_DMA_CHANNEL_4
4197 * @arg @ref LL_DMA_CHANNEL_5
4198 * @arg @ref LL_DMA_CHANNEL_6
4199 * @arg @ref LL_DMA_CHANNEL_7
4200 * @retval None.
4201 */
4202 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
4203 {
4204 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
4205 }
4206
4207 /**
4208 * @brief Clear Channel 0 destination transaction Complete status.
4209 *
4210 * Register|BitsName
4211 * --------|--------
4212 * CLR_DST_TRN | CLEAR
4213 *
4214 * @param DMAx DMAx instance
4215 * @retval None.
4216 */
4217 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
4218 {
4219 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
4220 }
4221
4222 /**
4223 * @brief Clear Channel 1 destination transaction Complete flag.
4224 *
4225 * Register|BitsName
4226 * --------|--------
4227 * CLR_DST_TRN | CLEAR
4228 *
4229 * @param DMAx DMAx instance
4230 * @retval None.
4231 */
4232 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
4233 {
4234 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
4235 }
4236
4237 /**
4238 * @brief Clear Channel 2 destination transaction Complete flag.
4239 *
4240 * Register|BitsName
4241 * --------|--------
4242 * CLR_DST_TRN | CLEAR
4243 *
4244 * @param DMAx DMAx instance
4245 * @retval None.
4246 */
4247 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
4248 {
4249 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
4250 }
4251
4252 /**
4253 * @brief Clear Channel 3 destination transaction Complete flag.
4254 *
4255 * Register|BitsName
4256 * --------|--------
4257 * CLR_DST_TRN | CLEAR
4258 *
4259 * @param DMAx DMAx instance
4260 * @retval None.
4261 */
4262 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
4263 {
4264 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
4265 }
4266
4267 /**
4268 * @brief Clear Channel 4 destination transaction Complete flag.
4269 *
4270 * Register|BitsName
4271 * --------|--------
4272 * CLR_DST_TRN | CLEAR
4273 *
4274 * @param DMAx DMAx instance
4275 * @retval None.
4276 */
4277 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
4278 {
4279 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
4280 }
4281
4282 /**
4283 * @brief Clear Channel 5 destination transaction Complete flag.
4284 *
4285 * Register|BitsName
4286 * --------|--------
4287 * CLR_DST_TRN | CLEAR
4288 *
4289 * @param DMAx DMAx instance
4290 * @retval None.
4291 */
4292 __STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
4293 {
4294 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
4295 }
4296
4297 /**
4298 * @brief Clear Channel 6 destination transaction Complete flag.
4299 *
4300 * Register|BitsName
4301 * --------|--------
4302 * CLR_DST_TRN | CLEAR
4303 *
4304 * @param DMAx DMAx instance
4305 * @retval None.
4306 */
4307 __STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
4308 {
4309 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
4310 }
4311
4312 /**
4313 * @brief Clear Channel 7 destination transaction Complete flag.
4314 *
4315 * Register|BitsName
4316 * --------|--------
4317 * CLR_DST_TRN | CLEAR
4318 *
4319 * @param DMAx DMAx instance
4320 * @retval None.
4321 */
4322 __STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
4323 {
4324 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
4325 }
4326
4327 /**
4328 * @brief Clear DMA Channel error flag.
4329 *
4330 * Register|BitsName
4331 * --------|--------
4332 * CLR_ERR | CLEAR
4333 *
4334 * @param DMAx DMAx instance
4335 * @param channel This parameter can be one of the following values:
4336 * @arg @ref LL_DMA_CHANNEL_0
4337 * @arg @ref LL_DMA_CHANNEL_1
4338 * @arg @ref LL_DMA_CHANNEL_2
4339 * @arg @ref LL_DMA_CHANNEL_3
4340 * @arg @ref LL_DMA_CHANNEL_4
4341 * @arg @ref LL_DMA_CHANNEL_5
4342 * @arg @ref LL_DMA_CHANNEL_6
4343 * @arg @ref LL_DMA_CHANNEL_7
4344 * @retval None.
4345 */
4346 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
4347 {
4348 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
4349 }
4350
4351 /**
4352 * @brief Clear Channel 0 error flag.
4353 *
4354 * Register|BitsName
4355 * --------|--------
4356 * CLR_ERR | CLEAR
4357 *
4358 * @param DMAx DMAx instance
4359 * @retval None.
4360 */
4361 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
4362 {
4363 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
4364 }
4365
4366 /**
4367 * @brief Clear Channel 1 error flag.
4368 *
4369 * Register|BitsName
4370 * --------|--------
4371 * CLR_ERR | CLEAR
4372 *
4373 * @param DMAx DMAx instance
4374 * @retval None.
4375 */
4376 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
4377 {
4378 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
4379 }
4380
4381 /**
4382 * @brief Clear Channel 2 error flag.
4383 *
4384 * Register|BitsName
4385 * --------|--------
4386 * CLR_ERR | CLEAR
4387 *
4388 * @param DMAx DMAx instance
4389 * @retval None.
4390 */
4391 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
4392 {
4393 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
4394 }
4395
4396 /**
4397 * @brief Clear Channel 3 error flag.
4398 *
4399 * Register|BitsName
4400 * --------|--------
4401 * CLR_ERR | CLEAR
4402 *
4403 * @param DMAx DMAx instance
4404 * @retval None.
4405 */
4406 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
4407 {
4408 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4409 }
4410
4411 /**
4412 * @brief Clear Channel 4 error flag.
4413 *
4414 * Register|BitsName
4415 * --------|--------
4416 * CLR_ERR | CLEAR
4417 *
4418 * @param DMAx DMAx instance
4419 * @retval None.
4420 */
4421 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
4422 {
4423 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4424 }
4425
4426 /**
4427 * @brief Clear Channel 5 error flag.
4428 *
4429 * Register|BitsName
4430 * --------|--------
4431 * CLR_ERR | CLEAR
4432 *
4433 * @param DMAx DMAx instance
4434 * @retval None.
4435 */
4436 __STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
4437 {
4438 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4439 }
4440
4441 /**
4442 * @brief Clear Channel 6 error flag.
4443 *
4444 * Register|BitsName
4445 * --------|--------
4446 * CLR_ERR | CLEAR
4447 *
4448 * @param DMAx DMAx instance
4449 * @retval None.
4450 */
4451 __STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
4452 {
4453 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4454 }
4455
4456 /**
4457 * @brief Clear Channel 7 error flag.
4458 *
4459 * Register|BitsName
4460 * --------|--------
4461 * CLR_ERR | CLEAR
4462 *
4463 * @param DMAx DMAx instance
4464 * @retval None.
4465 */
4466 __STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
4467 {
4468 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4469 }
4470
4471 /** @} */
4472
4473 /** @defgroup DMA_LL_EF_IT_Management IT_Management
4474 * @{
4475 */
4476
4477 /**
4478 * @brief Enable Transfer Complete interrupt.
4479 *
4480 * Register|BitsName
4481 * --------|--------
4482 * MASK_TFR | TFR_WE&TFR
4483 *
4484 * @param DMAx DMAx instance
4485 * @param channel This parameter can be one of the following values:
4486 * @arg @ref LL_DMA_CHANNEL_0
4487 * @arg @ref LL_DMA_CHANNEL_1
4488 * @arg @ref LL_DMA_CHANNEL_2
4489 * @arg @ref LL_DMA_CHANNEL_3
4490 * @arg @ref LL_DMA_CHANNEL_4
4491 * @arg @ref LL_DMA_CHANNEL_5
4492 * @arg @ref LL_DMA_CHANNEL_6
4493 * @arg @ref LL_DMA_CHANNEL_7
4494 * @retval None
4495 */
4496 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4497 {
4498 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4499 }
4500
4501 /**
4502 * @brief Enable Block Complete interrupt.
4503 *
4504 * Register|BitsName
4505 * --------|--------
4506 * MASK_BLK | BLK_WE&BLK
4507 *
4508 * @param DMAx DMAx instance
4509 * @param channel This parameter can be one of the following values:
4510 * @arg @ref LL_DMA_CHANNEL_0
4511 * @arg @ref LL_DMA_CHANNEL_1
4512 * @arg @ref LL_DMA_CHANNEL_2
4513 * @arg @ref LL_DMA_CHANNEL_3
4514 * @arg @ref LL_DMA_CHANNEL_4
4515 * @arg @ref LL_DMA_CHANNEL_5
4516 * @arg @ref LL_DMA_CHANNEL_6
4517 * @arg @ref LL_DMA_CHANNEL_7
4518 * @retval None
4519 */
4520 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4521 {
4522 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4523 }
4524
4525 /**
4526 * @brief Enable source transaction Complete interrupt.
4527 *
4528 * Register|BitsName
4529 * --------|--------
4530 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
4531 *
4532 * @param DMAx DMAx instance
4533 * @param channel This parameter can be one of the following values:
4534 * @arg @ref LL_DMA_CHANNEL_0
4535 * @arg @ref LL_DMA_CHANNEL_1
4536 * @arg @ref LL_DMA_CHANNEL_2
4537 * @arg @ref LL_DMA_CHANNEL_3
4538 * @arg @ref LL_DMA_CHANNEL_4
4539 * @arg @ref LL_DMA_CHANNEL_5
4540 * @arg @ref LL_DMA_CHANNEL_6
4541 * @arg @ref LL_DMA_CHANNEL_7
4542 * @retval None
4543 */
4544 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4545 {
4546 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4547 }
4548
4549 /**
4550 * @brief Enable destination transaction Complete interrupt.
4551 *
4552 * Register|BitsName
4553 * --------|--------
4554 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
4555 *
4556 * @param DMAx DMAx instance
4557 * @param channel This parameter can be one of the following values:
4558 * @arg @ref LL_DMA_CHANNEL_0
4559 * @arg @ref LL_DMA_CHANNEL_1
4560 * @arg @ref LL_DMA_CHANNEL_2
4561 * @arg @ref LL_DMA_CHANNEL_3
4562 * @arg @ref LL_DMA_CHANNEL_4
4563 * @arg @ref LL_DMA_CHANNEL_5
4564 * @arg @ref LL_DMA_CHANNEL_6
4565 * @arg @ref LL_DMA_CHANNEL_7
4566 * @retval None
4567 */
4568 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4569 {
4570 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4571 }
4572
4573 /**
4574 * @brief Enable error interrupt.
4575 *
4576 * Register|BitsName
4577 * --------|--------
4578 * MASK_ERR | ERR_WE&ERR
4579 *
4580 * @param DMAx DMAx instance
4581 * @param channel This parameter can be one of the following values:
4582 * @arg @ref LL_DMA_CHANNEL_0
4583 * @arg @ref LL_DMA_CHANNEL_1
4584 * @arg @ref LL_DMA_CHANNEL_2
4585 * @arg @ref LL_DMA_CHANNEL_3
4586 * @arg @ref LL_DMA_CHANNEL_4
4587 * @arg @ref LL_DMA_CHANNEL_5
4588 * @arg @ref LL_DMA_CHANNEL_6
4589 * @arg @ref LL_DMA_CHANNEL_7
4590 * @retval None
4591 */
4592 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4593 {
4594 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4595 }
4596
4597 /**
4598 * @brief Disable Transfer Complete interrupt.
4599 *
4600 * Register|BitsName
4601 * --------|--------
4602 * MASK_TFR | TFR_WE&TFR
4603 *
4604 * @param DMAx DMAx instance
4605 * @param channel This parameter can be one of the following values:
4606 * @arg @ref LL_DMA_CHANNEL_0
4607 * @arg @ref LL_DMA_CHANNEL_1
4608 * @arg @ref LL_DMA_CHANNEL_2
4609 * @arg @ref LL_DMA_CHANNEL_3
4610 * @arg @ref LL_DMA_CHANNEL_4
4611 * @arg @ref LL_DMA_CHANNEL_5
4612 * @arg @ref LL_DMA_CHANNEL_6
4613 * @arg @ref LL_DMA_CHANNEL_7
4614 * @retval None
4615 */
4616 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4617 {
4618 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4619 }
4620
4621 /**
4622 * @brief Disable Block Complete interrupt.
4623 *
4624 * Register|BitsName
4625 * --------|--------
4626 * MASK_BLK | BLK_WE&BLK
4627 *
4628 * @param DMAx DMAx instance
4629 * @param channel This parameter can be one of the following values:
4630 * @arg @ref LL_DMA_CHANNEL_0
4631 * @arg @ref LL_DMA_CHANNEL_1
4632 * @arg @ref LL_DMA_CHANNEL_2
4633 * @arg @ref LL_DMA_CHANNEL_3
4634 * @arg @ref LL_DMA_CHANNEL_4
4635 * @arg @ref LL_DMA_CHANNEL_5
4636 * @arg @ref LL_DMA_CHANNEL_6
4637 * @arg @ref LL_DMA_CHANNEL_7
4638 * @retval None
4639 */
4640 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4641 {
4642 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4643 }
4644
4645 /**
4646 * @brief Disable source transaction Complete interrupt.
4647 *
4648 * Register|BitsName
4649 * --------|--------
4650 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
4651 *
4652 * @param DMAx DMAx instance
4653 * @param channel This parameter can be one of the following values:
4654 * @arg @ref LL_DMA_CHANNEL_0
4655 * @arg @ref LL_DMA_CHANNEL_1
4656 * @arg @ref LL_DMA_CHANNEL_2
4657 * @arg @ref LL_DMA_CHANNEL_3
4658 * @arg @ref LL_DMA_CHANNEL_4
4659 * @arg @ref LL_DMA_CHANNEL_5
4660 * @arg @ref LL_DMA_CHANNEL_6
4661 * @arg @ref LL_DMA_CHANNEL_7
4662 * @retval None
4663 */
4664 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4665 {
4666 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4667 }
4668
4669 /**
4670 * @brief Disable destination transaction Complete interrupt.
4671 *
4672 * Register|BitsName
4673 * --------|--------
4674 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
4675 *
4676 * @param DMAx DMAx instance
4677 * @param channel This parameter can be one of the following values:
4678 * @arg @ref LL_DMA_CHANNEL_0
4679 * @arg @ref LL_DMA_CHANNEL_1
4680 * @arg @ref LL_DMA_CHANNEL_2
4681 * @arg @ref LL_DMA_CHANNEL_3
4682 * @arg @ref LL_DMA_CHANNEL_4
4683 * @arg @ref LL_DMA_CHANNEL_5
4684 * @arg @ref LL_DMA_CHANNEL_6
4685 * @arg @ref LL_DMA_CHANNEL_7
4686 * @retval None
4687 */
4688 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4689 {
4690 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4691 }
4692
4693 /**
4694 * @brief Disable error interrupt.
4695 *
4696 * Register|BitsName
4697 * --------|--------
4698 * MASK_ERR | ERR_WE&ERR
4699 *
4700 * @param DMAx DMAx instance
4701 * @param channel This parameter can be one of the following values:
4702 * @arg @ref LL_DMA_CHANNEL_0
4703 * @arg @ref LL_DMA_CHANNEL_1
4704 * @arg @ref LL_DMA_CHANNEL_2
4705 * @arg @ref LL_DMA_CHANNEL_3
4706 * @arg @ref LL_DMA_CHANNEL_4
4707 * @arg @ref LL_DMA_CHANNEL_5
4708 * @arg @ref LL_DMA_CHANNEL_6
4709 * @arg @ref LL_DMA_CHANNEL_7
4710 * @retval None
4711 */
4712 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
4713 {
4714 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4715 }
4716
4717 /**
4718 * @brief Check if DMA Transfer interrupt is enabled or disabled.
4719 *
4720 * Register|BitsName
4721 * --------|--------
4722 * MASK_TFR | TFR
4723 *
4724 * @param DMAx DMA instance.
4725 * @param channel This parameter can be one of the following values:
4726 * @arg @ref LL_DMA_CHANNEL_0
4727 * @arg @ref LL_DMA_CHANNEL_1
4728 * @arg @ref LL_DMA_CHANNEL_2
4729 * @arg @ref LL_DMA_CHANNEL_3
4730 * @arg @ref LL_DMA_CHANNEL_4
4731 * @arg @ref LL_DMA_CHANNEL_5
4732 * @arg @ref LL_DMA_CHANNEL_6
4733 * @arg @ref LL_DMA_CHANNEL_7
4734 * @retval State of bit (1 or 0).
4735 */
4736 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4737 {
4738 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4739 }
4740
4741 /**
4742 * @brief Check if DMA block interrupt is enabled or disabled.
4743 *
4744 * Register|BitsName
4745 * --------|--------
4746 * MASK_BLK | BLK_WE&BLK
4747 *
4748 * @param DMAx DMA instance.
4749 * @param channel This parameter can be one of the following values:
4750 * @arg @ref LL_DMA_CHANNEL_0
4751 * @arg @ref LL_DMA_CHANNEL_1
4752 * @arg @ref LL_DMA_CHANNEL_2
4753 * @arg @ref LL_DMA_CHANNEL_3
4754 * @arg @ref LL_DMA_CHANNEL_4
4755 * @arg @ref LL_DMA_CHANNEL_5
4756 * @arg @ref LL_DMA_CHANNEL_6
4757 * @arg @ref LL_DMA_CHANNEL_7
4758 * @retval State of bit (1 or 0).
4759 */
4760 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4761 {
4762 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4763 }
4764
4765 /**
4766 * @brief Check if DMA source transaction interrupt is enabled or disabled.
4767 *
4768 * Register|BitsName
4769 * --------|--------
4770 * MASK_SRC_TRN | SRC_TRN
4771 *
4772 * @param DMAx DMA instance.
4773 * @param channel This parameter can be one of the following values:
4774 * @arg @ref LL_DMA_CHANNEL_0
4775 * @arg @ref LL_DMA_CHANNEL_1
4776 * @arg @ref LL_DMA_CHANNEL_2
4777 * @arg @ref LL_DMA_CHANNEL_3
4778 * @arg @ref LL_DMA_CHANNEL_4
4779 * @arg @ref LL_DMA_CHANNEL_5
4780 * @arg @ref LL_DMA_CHANNEL_6
4781 * @arg @ref LL_DMA_CHANNEL_7
4782 * @retval State of bit (1 or 0).
4783 */
4784 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4785 {
4786 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4787 }
4788
4789 /**
4790 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
4791 *
4792 * Register|BitsName
4793 * --------|--------
4794 * MASK_DST_TRN | DST_TRN
4795 *
4796 * @param DMAx DMA instance.
4797 * @param channel This parameter can be one of the following values:
4798 * @arg @ref LL_DMA_CHANNEL_0
4799 * @arg @ref LL_DMA_CHANNEL_1
4800 * @arg @ref LL_DMA_CHANNEL_2
4801 * @arg @ref LL_DMA_CHANNEL_3
4802 * @arg @ref LL_DMA_CHANNEL_4
4803 * @arg @ref LL_DMA_CHANNEL_5
4804 * @arg @ref LL_DMA_CHANNEL_6
4805 * @arg @ref LL_DMA_CHANNEL_7
4806 * @retval State of bit (1 or 0).
4807 */
4808 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4809 {
4810 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4811 }
4812
4813 /**
4814 * @brief Check if DMA error interrupt is enabled or disabled.
4815 *
4816 * Register|BitsName
4817 * --------|--------
4818 * MASK_ERR | ERR
4819 *
4820 * @param DMAx DMA instance.
4821 * @param channel This parameter can be one of the following values:
4822 * @arg @ref LL_DMA_CHANNEL_0
4823 * @arg @ref LL_DMA_CHANNEL_1
4824 * @arg @ref LL_DMA_CHANNEL_2
4825 * @arg @ref LL_DMA_CHANNEL_3
4826 * @arg @ref LL_DMA_CHANNEL_4
4827 * @arg @ref LL_DMA_CHANNEL_5
4828 * @arg @ref LL_DMA_CHANNEL_6
4829 * @arg @ref LL_DMA_CHANNEL_7
4830 * @retval State of bit (1 or 0).
4831 */
4832 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4833 {
4834 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4835 }
4836
4837 /**
4838 * @brief Enable DMA channel interrupt.
4839 *
4840 * Register|BitsName
4841 * --------|--------
4842 * CTLL | INI_EN
4843 *
4844 * @param DMAx DMA instance.
4845 * @param channel This parameter can be one of the following values:
4846 * @arg @ref LL_DMA_CHANNEL_0
4847 * @arg @ref LL_DMA_CHANNEL_1
4848 * @arg @ref LL_DMA_CHANNEL_2
4849 * @arg @ref LL_DMA_CHANNEL_3
4850 * @arg @ref LL_DMA_CHANNEL_4
4851 * @arg @ref LL_DMA_CHANNEL_5
4852 * @arg @ref LL_DMA_CHANNEL_6
4853 * @arg @ref LL_DMA_CHANNEL_7
4854 * @retval None
4855 */
4856 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
4857 {
4858 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4859 }
4860
4861 /**
4862 * @brief Disable DMA channel interrupt.
4863 *
4864 * Register|BitsName
4865 * --------|--------
4866 * CTLL | INI_EN
4867 *
4868 * @param DMAx DMA instance.
4869 * @param channel This parameter can be one of the following values:
4870 * @arg @ref LL_DMA_CHANNEL_0
4871 * @arg @ref LL_DMA_CHANNEL_1
4872 * @arg @ref LL_DMA_CHANNEL_2
4873 * @arg @ref LL_DMA_CHANNEL_3
4874 * @arg @ref LL_DMA_CHANNEL_4
4875 * @arg @ref LL_DMA_CHANNEL_5
4876 * @arg @ref LL_DMA_CHANNEL_6
4877 * @arg @ref LL_DMA_CHANNEL_7
4878 * @retval None
4879 */
4880 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
4881 {
4882 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
4883 }
4884
4885 /**
4886 * @brief Check if DMA interrupt is enabled or disabled.
4887 *
4888 * Register|BitsName
4889 * --------|--------
4890 * CTL_LO | INT_EN
4891 *
4892 * @param DMAx DMA instance.
4893 * @param channel This parameter can be one of the following values:
4894 * @arg @ref LL_DMA_CHANNEL_0
4895 * @arg @ref LL_DMA_CHANNEL_1
4896 * @arg @ref LL_DMA_CHANNEL_2
4897 * @arg @ref LL_DMA_CHANNEL_3
4898 * @arg @ref LL_DMA_CHANNEL_4
4899 * @arg @ref LL_DMA_CHANNEL_5
4900 * @arg @ref LL_DMA_CHANNEL_6
4901 * @arg @ref LL_DMA_CHANNEL_7
4902 * @retval State of bit (1 or 0).
4903 */
4904 __STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
4905 {
4906 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
4907 }
4908
4909 /** @} */
4910
4911 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
4912 * @{
4913 */
4914
4915 /**
4916 * @brief De-initialize the DMA registers to their default reset values.
4917 * @param DMAx DMAx instance
4918 * @param channel This parameter can be one of the following values:
4919 * @arg @ref LL_DMA_CHANNEL_0
4920 * @arg @ref LL_DMA_CHANNEL_1
4921 * @arg @ref LL_DMA_CHANNEL_2
4922 * @arg @ref LL_DMA_CHANNEL_3
4923 * @arg @ref LL_DMA_CHANNEL_4
4924 * @arg @ref LL_DMA_CHANNEL_5
4925 * @arg @ref LL_DMA_CHANNEL_6
4926 * @arg @ref LL_DMA_CHANNEL_7
4927 * @retval An error_status_t enumeration value:
4928 * - SUCCESS: DMA registers are de-initialized
4929 * - ERROR: DMA registers are not de-initialized
4930 */
4931 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
4932
4933 /**
4934 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
4935 * @param DMAx DMAx instance
4936 * @param channel This parameter can be one of the following values:
4937 * @arg @ref LL_DMA_CHANNEL_0
4938 * @arg @ref LL_DMA_CHANNEL_1
4939 * @arg @ref LL_DMA_CHANNEL_2
4940 * @arg @ref LL_DMA_CHANNEL_3
4941 * @arg @ref LL_DMA_CHANNEL_4
4942 * @arg @ref LL_DMA_CHANNEL_5
4943 * @arg @ref LL_DMA_CHANNEL_6
4944 * @arg @ref LL_DMA_CHANNEL_7
4945 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
4946 * @retval An error_status_t enumeration value:
4947 * - SUCCESS: DMA registers are initialized
4948 * - ERROR: Not applicable
4949 */
4950 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
4951
4952 /**
4953 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
4954 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
4955 * whose fields will be set to default values.
4956 * @retval None
4957 */
4958 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
4959
4960 /**
4961 * @brief Initialize the DMA HS choice according to the specified parameters.
4962 * @param DMAx DMAx instance
4963 * @param src_peripheral src_peripheral
4964 * @param dst_peripheral dst_peripheral
4965 * @retval An error_status_t enumeration value:
4966 * - SUCCESS: DMA hs choice are initialized
4967 * - ERROR: Error DMA instance
4968 */
4969 error_status_t ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral);
4970 /** @} */
4971
4972 /** @} */
4973
4974 #endif /* DMA */
4975
4976 #ifdef __cplusplus
4977 }
4978 #endif
4979
4980 #endif /* __GR55xx_LL_DMA_H__ */
4981
4982 /** @} */
4983
4984 /** @} */
4985
4986 /** @} */
ll_dma_clear_flag_err
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: gr55xx_ll_dma.h:4346
ll_dma_get_source_burst_length
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1605
_ll_dma_init::mode
uint32_t mode
Definition: gr55xx_ll_dma.h:92
ll_dma_get_mode
__STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
Get DMA mode circular or normal.
Definition: gr55xx_ll_dma.h:810
_ll_dma_init::src_address
uint32_t src_address
Definition: gr55xx_ll_dma.h:78
ll_dma_get_source_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: gr55xx_ll_dma.h:1385
ll_dma_get_channel_priority_level
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: gr55xx_ll_dma.h:1725
ll_dma_disable_it_err
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: gr55xx_ll_dma.h:4712
ll_dma_clear_flag_srct3
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4118
ll_dma_is_active_flag_dstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3482
ll_dma_clear_flag_tfr0
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:3785
ll_dma_clear_flag_tfr3
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:3830
ll_dma_get_dst_scatter_en
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel)
Get destination scatter enable.
Definition: gr55xx_ll_dma.h:1277
ll_dma_clear_flag_blk3
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: gr55xx_ll_dma.h:3974
ll_dma_clear_flag_err7
__STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
Clear Channel 7 error flag.
Definition: gr55xx_ll_dma.h:4466
ll_dma_disable_channel
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: gr55xx_ll_dma.h:528
ll_dma_is_active_flag_tfr4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:3125
ll_dma_set_max_amba_burst
__STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
Set Maximum AMBA Burst Length.
Definition: gr55xx_ll_dma.h:836
ll_dma_is_active_flag_dstt3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3542
ll_dma_clear_flag_dstt3
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4262
ll_dma_is_active_flag_blk0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: gr55xx_ll_dma.h:3209
ll_dma_init
error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
ll_dma_is_active_flag_err0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3641
ll_dma_clear_flag_srct
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4058
ll_dma_disable
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: gr55xx_ll_dma.h:463
ll_dma_is_active_flag_err1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3656
ll_dma_clear_flag_err4
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: gr55xx_ll_dma.h:4421
ll_dma_get_source_width
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: gr55xx_ll_dma.h:1495
LL_DMA_DST_STAT_UPDATE_DISABLE
#define LL_DMA_DST_STAT_UPDATE_DISABLE
Definition: gr55xx_ll_dma.h:213
ll_dma_clear_flag_srct1
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4088
ll_dma_set_dstatar
__STATIC_INLINE void ll_dma_set_dstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t dstatar)
Set deatination status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1042
ll_dma_get_source_peripheral
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2273
ll_dma_config_transfer
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: gr55xx_ll_dma.h:692
ll_dma_is_active_flag_srct0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3353
ll_dma_get_destination_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: gr55xx_ll_dma.h:1440
ll_dma_set_m2m_dst_address
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1969
ll_dma_deinit
error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
ll_dma_set_llp_dst_en
__STATIC_INLINE void ll_dma_set_llp_dst_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_dst_en)
Set destination LLP enable.
Definition: gr55xx_ll_dma.h:1145
ll_dma_is_empty_fifo
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: gr55xx_ll_dma.h:653
ll_dma_clear_flag_srct4
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4133
ll_dma_disable_it_dstt
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4688
ll_dma_clear_flag_blk1
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: gr55xx_ll_dma.h:3944
ll_dma_get_llp_src_en
__STATIC_INLINE uint32_t ll_dma_get_llp_src_en(dma_regs_t *DMAx, uint32_t channel)
Get source LLP enable.
Definition: gr55xx_ll_dma.h:1224
ll_dma_clear_flag_tfr
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:3770
ll_dma_disable_it_srct
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4664
ll_dma_set_destination_width
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: gr55xx_ll_dma.h:1523
ll_dma_clear_flag_dstt4
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4277
ll_dma_get_dstatar
__STATIC_INLINE uint32_t ll_dma_get_dstatar(dma_regs_t *DMAx, uint32_t channel)
Get deatination status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1067
ll_dma_is_enabled_channel
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: gr55xx_ll_dma.h:554
ll_dma_get_m2m_src_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1995
ll_dma_get_destination_burst_length
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1660
ll_dma_get_sstatar
__STATIC_INLINE uint32_t ll_dma_get_sstatar(dma_regs_t *DMAx, uint32_t channel)
Get source status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:1016
ll_dma_clear_flag_blk6
__STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
Clear Channel 6 Block Cmplete flag.
Definition: gr55xx_ll_dma.h:4019
ll_dma_is_active_flag_dstt7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
Indicate the status of Channel 7 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3602
ll_dma_clear_flag_err0
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: gr55xx_ll_dma.h:4361
ll_dma_clear_flag_dstt5
__STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
Clear Channel 5 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4292
ll_dma_clear_flag_err3
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: gr55xx_ll_dma.h:4406
ll_dma_set_sstat
__STATIC_INLINE void ll_dma_set_sstat(dma_regs_t *DMAx, uint32_t channel, uint32_t sstat)
Set source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:888
ll_dma_is_enable_it_dstt
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4808
ll_dma_clear_flag_tfr1
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:3800
ll_dma_req_src_burst_transaction
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2667
ll_dma_set_source_peripheral
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2250
ll_dma_set_block_size
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: gr55xx_ll_dma.h:1751
ll_dma_get_src_gather_sgi
__STATIC_INLINE uint32_t ll_dma_get_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel)
Get source gather interval.
Definition: gr55xx_ll_dma.h:2464
ll_dma_set_source_address
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: gr55xx_ll_dma.h:1842
ll_dma_is_active_flag_rdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: gr55xx_ll_dma.h:3002
ll_dma_set_dst_scatter_dsi
__STATIC_INLINE void ll_dma_set_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsi)
Set destination scatter interval.
Definition: gr55xx_ll_dma.h:2541
ll_dma_is_active_flag_dstt0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3497
ll_dma_dst_stat_update_is_enable
__STATIC_INLINE uint32_t ll_dma_dst_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
Check if Destination Status Update Enable.
Definition: gr55xx_ll_dma.h:2164
ll_dma_get_m2m_dst_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:2020
ll_dma_is_active_flag_dstt4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3557
ll_dma_is_active_flag_srct7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
Indicate the status of Channel 7 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3458
ll_dma_config_address
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: gr55xx_ll_dma.h:1811
ll_dma_is_active_flag_tfr5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
Indicate the status of Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:3140
ll_dma_is_active_flag_srct5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
Indicate the status of Channel 5 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3428
ll_dma_req_dst_last_single_transaction
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:2797
ll_dma_disable_it_tfr
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4616
ll_dma_is_active_flag_dstt5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
Indicate the status of Channel 5 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3572
ll_dma_get_dst_scatter_dsi
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsi(dma_regs_t *DMAx, uint32_t channel)
Get Set destination scatter interval.
Definition: gr55xx_ll_dma.h:2566
ll_dma_set_destination_increment_mode
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: gr55xx_ll_dma.h:1413
ll_dma_is_active_flag_blk1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: gr55xx_ll_dma.h:3224
ll_dma_is_enable_it_blk
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4760
ll_dma_disable_it
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4880
ll_dma_is_active_flag_srct1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3368
_ll_dma_init
LL DMA init Structure definition.
Definition: gr55xx_ll_dma.h:77
ll_dma_clear_flag_dstt6
__STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
Clear Channel 6 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4307
ll_dma_get_dstat
__STATIC_INLINE uint32_t ll_dma_get_dstat(dma_regs_t *DMAx, uint32_t channel)
Get deatination status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:965
ll_dma_is_active_flag_err3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3686
ll_dma_is_active_flag_err5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
Indicate the status of Channel 5 error flag.
Definition: gr55xx_ll_dma.h:3716
ll_dma_struct_init
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
ll_dma_is_active_flag_tfr1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:3080
ll_dma_get_destination_address
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: gr55xx_ll_dma.h:1915
ll_dma_is_active_flag_err
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3626
ll_dma_disable_dst_stat_update
__STATIC_INLINE void ll_dma_disable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
Disable Destination Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2140
ll_dma_set_llp_src_en
__STATIC_INLINE void ll_dma_set_llp_src_en(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_src_en)
Set source LLP enable.
Definition: gr55xx_ll_dma.h:1198
ll_dma_req_src_single_transaction
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: gr55xx_ll_dma.h:2642
ll_dma_set_llp_loc
__STATIC_INLINE void ll_dma_set_llp_loc(dma_regs_t *DMAx, uint32_t channel, uint32_t llp_loc)
Set LLP loc.
Definition: gr55xx_ll_dma.h:1093
ll_dma_clear_flag_tfr2
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:3815
ll_dma_is_enable_it_tfr
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4736
ll_dma_is_active_flag_srct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: gr55xx_ll_dma.h:3338
ll_dma_clear_flag_srct0
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4073
ll_dma_is_active_flag_dstt2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3527
ll_dma_is_active_flag_blk2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: gr55xx_ll_dma.h:3239
ll_dma_enable_it_tfr
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4496
ll_dma_req_dst_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2771
ll_dma_set_sstatar
__STATIC_INLINE void ll_dma_set_sstatar(dma_regs_t *DMAx, uint32_t channel, uint32_t sstatar)
Set source status address after each block tranfer completed.
Definition: gr55xx_ll_dma.h:991
ll_dma_enable_channel
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: gr55xx_ll_dma.h:504
ll_dma_set_src_gather_en
__STATIC_INLINE void ll_dma_set_src_gather_en(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_en)
Set source gather enable.
Definition: gr55xx_ll_dma.h:1304
ll_dma_clear_flag_blk7
__STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
Clear Channel 7 Block Complete flag.
Definition: gr55xx_ll_dma.h:4034
ll_dma_set_source_burst_length
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1578
ll_dma_is_active_flag_dstt1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3512
ll_dma_is_active_flag_srct4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3413
ll_dma_is_active_flag_tfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:3050
ll_dma_is_active_flag_srct2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3383
ll_dma_get_max_amba_burst
__STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
Get source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:862
ll_dma_is_active_flag_gsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2876
ll_dma_get_sstat
__STATIC_INLINE uint32_t ll_dma_get_sstat(dma_regs_t *DMAx, uint32_t channel)
Get source status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:914
ll_dma_is_active_flag_err2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3671
ll_dma_is_active_flag_tfr7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
Indicate the status of Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:3170
_ll_dma_init::block_size
uint32_t block_size
Definition: gr55xx_ll_dma.h:119
ll_dma_get_source_address
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: gr55xx_ll_dma.h:1891
ll_dma_select_handshaking
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: gr55xx_ll_dma.h:2412
ll_dma_is_active_flag_blk7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
Indicate the status of Channel 7 block complete flag.
Definition: gr55xx_ll_dma.h:3314
_ll_dma_init::src_peripheral
uint32_t src_peripheral
Definition: gr55xx_ll_dma.h:125
LL_DMA_DST_STAT_UPDATE_ENABLE
#define LL_DMA_DST_STAT_UPDATE_ENABLE
Definition: gr55xx_ll_dma.h:212
ll_dma_is_active_flag_blk4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: gr55xx_ll_dma.h:3269
ll_dma_clear_flag_tfr5
__STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
Clear Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:3860
ll_dma_set_destination_peripheral
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2359
ll_dma_get_destination_width
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: gr55xx_ll_dma.h:1550
ll_dma_enable_src_stat_update
__STATIC_INLINE void ll_dma_enable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
Enable Source Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2044
_ll_dma_init::dst_data_width
uint32_t dst_data_width
Definition: gr55xx_ll_dma.h:114
ll_dma_is_active_flag_gerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: gr55xx_ll_dma.h:2906
ll_dma_set_source_increment_mode
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: gr55xx_ll_dma.h:1358
ll_dma_is_active_flag_gtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: gr55xx_ll_dma.h:2846
ll_dma_set_destination_address
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: gr55xx_ll_dma.h:1867
ll_dma_req_src_last_single_transaction
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:2693
ll_dma_is_active_flag_err7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
Indicate the status of Channel 7 error flag.
Definition: gr55xx_ll_dma.h:3746
ll_dma_is_active_flag_blk6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
Indicate the status of Channel 6 block complete flag.
Definition: gr55xx_ll_dma.h:3299
ll_dma_clear_flag_err5
__STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
Clear Channel 5 error flag.
Definition: gr55xx_ll_dma.h:4436
ll_dma_resume_channel
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: gr55xx_ll_dma.h:605
ll_dma_clear_flag_dstt0
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: gr55xx_ll_dma.h:4217
_ll_dma_init::src_data_width
uint32_t src_data_width
Definition: gr55xx_ll_dma.h:109
ll_dma_clear_flag_err2
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: gr55xx_ll_dma.h:4391
ll_dma_set_mode
__STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
Set DMA mode Single block or Multi block.
Definition: gr55xx_ll_dma.h:781
ll_dma_set_m2m_src_address
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1941
ll_dma_is_active_flag_srct6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
Indicate the status of Channel 6 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3443
ll_dma_enable_it_blk
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4520
_ll_dma_init::direction
uint32_t direction
Definition: gr55xx_ll_dma.h:86
ll_dma_clear_flag_tfr6
__STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
Clear Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:3875
ll_dma_clear_flag_dstt
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4202
ll_dma_enable
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: gr55xx_ll_dma.h:444
ll_dma_clear_flag_blk0
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: gr55xx_ll_dma.h:3929
ll_dma_clear_flag_dstt2
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4247
_ll_dma_init::dst_peripheral
uint32_t dst_peripheral
Definition: gr55xx_ll_dma.h:130
ll_dma_set_dst_scatter_en
__STATIC_INLINE void ll_dma_set_dst_scatter_en(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_en)
Set destination scatter enable.
Definition: gr55xx_ll_dma.h:1251
ll_dma_disable_it_blk
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4640
ll_dma_src_stat_update_is_enable
__STATIC_INLINE uint32_t ll_dma_src_stat_update_is_enable(dma_regs_t *DMAx, uint32_t channel)
Check if Source Status Update Enable.
Definition: gr55xx_ll_dma.h:2092
_ll_dma_init::priority
uint32_t priority
Definition: gr55xx_ll_dma.h:135
ll_dma_is_active_flag_err4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: gr55xx_ll_dma.h:3701
ll_dma_is_active_flag_gdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2891
ll_dma_req_dst_single_transaction
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: gr55xx_ll_dma.h:2746
ll_dma_get_data_transfer_direction
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:750
ll_dma_enable_it_err
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: gr55xx_ll_dma.h:4592
ll_dma_req_dst_last_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2824
ll_dma_set_src_gather_sgc
__STATIC_INLINE void ll_dma_set_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgc)
Set source gather count.
Definition: gr55xx_ll_dma.h:2490
ll_dma_set_src_gather_sgi
__STATIC_INLINE void ll_dma_set_src_gather_sgi(dma_regs_t *DMAx, uint32_t channel, uint32_t src_gather_sgi)
Set source gather interval.
Definition: gr55xx_ll_dma.h:2439
ll_dma_clear_flag_dstt7
__STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
Clear Channel 7 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4322
ll_dma_get_src_gather_en
__STATIC_INLINE uint32_t ll_dma_get_src_gather_en(dma_regs_t *DMAx, uint32_t channel)
Get source gather enable.
Definition: gr55xx_ll_dma.h:1330
ll_dma_is_active_flag_err6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
Indicate the status of Channel 6 error flag.
Definition: gr55xx_ll_dma.h:3731
ll_dma_clear_flag_tfr7
__STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
Clear Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:3890
ll_dma_is_active_flag_rerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: gr55xx_ll_dma.h:3026
_ll_dma_init::dst_increment_mode
uint32_t dst_increment_mode
Definition: gr55xx_ll_dma.h:104
ll_dma_clear_flag_tfr4
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:3845
ll_dma_clear_flag_srct2
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4103
LL_DMA_SRC_STAT_UPDATE_ENABLE
#define LL_DMA_SRC_STAT_UPDATE_ENABLE
Definition: gr55xx_ll_dma.h:205
ll_dma_is_enable_it_srct
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4784
_ll_dma_init::dst_address
uint32_t dst_address
Definition: gr55xx_ll_dma.h:82
ll_dma_clear_flag_srct6
__STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
Clear Channel 6 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4163
ll_dma_get_dst_scatter_dsc
__STATIC_INLINE uint32_t ll_dma_get_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel)
Get destination scatter count..
Definition: gr55xx_ll_dma.h:2617
ll_dma_clear_flag_err6
__STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
Clear Channel 6 error flag.
Definition: gr55xx_ll_dma.h:4451
ll_dma_clear_flag_srct5
__STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
Clear Channel 5 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4148
ll_dma_enable_dst_stat_update
__STATIC_INLINE void ll_dma_enable_dst_stat_update(dma_regs_t *DMAx, uint32_t channel)
Enable Destination Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2116
ll_dma_is_active_flag_tfr2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:3095
ll_dma_is_active_flag_tfr6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
Indicate the status of Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:3155
ll_dma_is_enable
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: gr55xx_ll_dma.h:478
ll_dma_get_destination_peripheral
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2382
LL_DMA_SRC_STAT_UPDATE_DISABLE
#define LL_DMA_SRC_STAT_UPDATE_DISABLE
Definition: gr55xx_ll_dma.h:206
ll_dma_clear_flag_blk2
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: gr55xx_ll_dma.h:3959
ll_dma_set_destination_burst_length
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1633
ll_dma_req_src_last_burst_transaction
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2720
ll_dma_get_llp_dst_en
__STATIC_INLINE uint32_t ll_dma_get_llp_dst_en(dma_regs_t *DMAx, uint32_t channel)
Get destination LLP enable.
Definition: gr55xx_ll_dma.h:1171
ll_dma_enable_it_dstt
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4568
_ll_dma_init::src_increment_mode
uint32_t src_increment_mode
Definition: gr55xx_ll_dma.h:99
ll_dma_set_data_transfer_direction
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:722
ll_dma_set_dst_scatter_dsc
__STATIC_INLINE void ll_dma_set_dst_scatter_dsc(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_scatter_dsc)
Set destination scatter count.
Definition: gr55xx_ll_dma.h:2592
ll_dma_is_active_flag_tfr0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:3065
ll_dma_clear_flag_srct7
__STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
Clear Channel 7 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:4178
ll_dma_get_llp_loc
__STATIC_INLINE uint32_t ll_dma_get_llp_loc(dma_regs_t *DMAx, uint32_t channel)
Get LLP loc.
Definition: gr55xx_ll_dma.h:1118
ll_dma_is_active_flag_tfr3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:3110
ll_dma_set_dstat
__STATIC_INLINE void ll_dma_set_dstat(dma_regs_t *DMAx, uint32_t channel, uint32_t dstat)
Set deatination status after each block tranfer completed.
Definition: gr55xx_ll_dma.h:940
ll_dma_is_suspended
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: gr55xx_ll_dma.h:629
ll_dma_init_t
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
ll_dma_clear_flag_blk5
__STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
Clear Channel 5 Block Complete flag.
Definition: gr55xx_ll_dma.h:4004
ll_dma_set_source_width
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: gr55xx_ll_dma.h:1468
ll_dma_is_active_flag_rsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: gr55xx_ll_dma.h:2978
ll_dma_clear_flag_blk4
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: gr55xx_ll_dma.h:3989
ll_dma_is_active_flag_blk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:3194
ll_dma_is_active_flag_rtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: gr55xx_ll_dma.h:2930
ll_dma_is_active_flag_dstt6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
Indicate the status of Channel 6 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:3587
ll_dma_suspend_channel
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: gr55xx_ll_dma.h:580
ll_dma_get_src_gather_sgc
__STATIC_INLINE uint32_t ll_dma_get_src_gather_sgc(dma_regs_t *DMAx, uint32_t channel)
Get source gather count.
Definition: gr55xx_ll_dma.h:2515
ll_dma_clear_flag_dstt1
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:4232
ll_dma_clear_flag_blk
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:3914
ll_dma_is_active_flag_blk5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
Indicate the status of Channel 5 block complete flag.
Definition: gr55xx_ll_dma.h:3284
ll_dma_enable_it
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4856
ll_dma_is_active_flag_blk3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: gr55xx_ll_dma.h:3254
ll_dma_hs_choice
error_status_t ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral)
Initialize the DMA HS choice according to the specified parameters.
ll_dma_is_active_flag_rblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: gr55xx_ll_dma.h:2954
ll_dma_set_channel_priority_level
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: gr55xx_ll_dma.h:1693
ll_dma_get_block_size
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: gr55xx_ll_dma.h:1777
ll_dma_is_active_flag_gblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: gr55xx_ll_dma.h:2861
ll_dma_enable_it_srct
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4544
ll_dma_is_enable_it_err
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4832
ll_dma_clear_flag_err1
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: gr55xx_ll_dma.h:4376
ll_dma_disable_src_stat_update
__STATIC_INLINE void ll_dma_disable_src_stat_update(dma_regs_t *DMAx, uint32_t channel)
Disable Source Status Update Enable for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:2068
ll_dma_is_enable_it
__STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
Check if DMA interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4904
ll_dma_is_active_flag_srct3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: gr55xx_ll_dma.h:3398