gr55xx_ll_cgc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_cgc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CGC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_CGC CGC
47 * @brief CGC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(MCU_SUB) || defined(MCU_RET)
63 /**
64 * @defgroup CGC_LL_MACRO Defines
65 * @{
66 */
67
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup CGC_LL_Exported_Constants CGC Exported Constants
70 * @{
71 */
72
73 /** @defgroup CGC_LL_EC_WFI_CLK0 Block0 Clock During WFI
74 * @{
75 */
76 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK /**< Hclk for all security blocks */
77 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK /**< Hclk for hopping table */
78 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK /**< Hclk for ROM */
79 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK /**< Hclk for sense ADC */
80 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK /**< Hclk for GPIOs */
81 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
82 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK /**< Hclk for APB subsystem */
83 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK /**< Hclk for serial blocks */
84
85 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x000007FFU) /**< All clock group 0 */
86
87 /** @} */
88
89 /** @defgroup CGC_LL_EC_WFI_CLK1 Block1 Clock During WFI
90 * @{
91 */
92 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
93 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK /**< Hclk for cache top */
94 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK /**< Hclk for SRAMs */
95
96 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U) /**< All clock group 1 */
97 /** @} */
98
99 /** @defgroup CGC_LL_EC_WFI_CLK2 Block2 Clock During WFI
100 * @{
101 */
102 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK /**< Div4 clk for security blocks */
103 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
104
105 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U) /**< All clock group 2 */
106 /** @} */
107
108
109 /** @defgroup CGC_LL_EC_FRC_CLK0 Force Clock OFF
110 * @{
111 */
112 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK /**< Hclk for all security blocks */
113 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK /**< Hclk for hopping table */
114 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK /**< Hclk for ROM */
115 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK /**< Hclk for sense ADC */
116 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK /**< Hclk for GPIOs */
117 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
118 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK /**< Hclk for APB subsystem */
119 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK /**< Hclk for serial blocks */
120
121 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000777U) /**< All clock group 0 */
122 /** @} */
123
124 /** @defgroup CGC_LL_EC_FRC_CLK1 Force Clock OFF
125 * @{
126 */
127 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
128 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK /**< Hclk for cache top */
129 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK /**< Hclk for SRAMs */
130
131 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U) /**< All clock group 1 */
132 /** @} */
133
134 /** @defgroup CGC_LL_EC_FRC_CLK2 Force Clock OFF
135 * @{
136 */
137 #define LL_CGC_FRC_UART0_PCLK MCU_SUB_FORCE_UART0_PCLK /**< Pclk for uart0 */
138 #define LL_CGC_FRC_UART1_PCLK MCU_SUB_FORCE_UART1_PCLK /**< Pclk for uart1 */
139 #define LL_CGC_FRC_UART2_PCLK MCU_SUB_FORCE_UART2_PCLK /**< Pclk for uart2 */
140 #define LL_CGC_FRC_UART3_PCLK MCU_SUB_FORCE_UART3_PCLK /**< Pclk for uart3 */
141 #define LL_CGC_FRC_I2C0_PCLK MCU_SUB_FORCE_I2C0_PCLK /**< Hclk for i2c0 */
142 #define LL_CGC_FRC_I2C1_PCLK MCU_SUB_FORCE_I2C1_PCLK /**< Hclk for i2c1 */
143 #define LL_CGC_FRC_I2C2_PCLK MCU_SUB_FORCE_I2C2_PCLK /**< Hclk for i2c2 */
144 #define LL_CGC_FRC_I2C3_PCLK MCU_SUB_FORCE_I2C3_PCLK /**< Hclk for i2c3 */
145 #define LL_CGC_FRC_QSPI0_PCLK MCU_SUB_FORCE_QSPI0_PCLK /**< Hclk for qspi0 */
146 #define LL_CGC_FRC_QSPI1_PCLK MCU_SUB_FORCE_QSPI1_PCLK /**< Hclk for qspi1 */
147 #define LL_CGC_FRC_QSPI2_PCLK MCU_SUB_FORCE_QSPI2_PCLK /**< Hclk for qspi2 */
148 #define LL_CGC_FRC_SPI_M_PCLK MCU_SUB_FORCE_SPI_M_PCLK /**< Hclk for spim */
149 #define LL_CGC_FRC_SPI_S_PCLK MCU_SUB_FORCE_SPI_S_PCLK /**< Hclk for spis */
150 #define LL_CGC_FRC_I2S_PCLK MCU_SUB_FORCE_I2S_PCLK /**< Hclk for i2s */
151 #define LL_CGC_FRC_I2S_S_PCLK MCU_SUB_FORCE_I2S_S_PCLK /**< Hclk for i2ss */
152 #define LL_CGC_FRC_DSPI_PCLK MCU_SUB_FORCE_DSPI_PCLK /**< Hclk for dspi */
153 #define LL_CGC_FRC_PDM_PCLK MCU_SUB_FORCE_PDM_PCLK /**< Hclk for pdm */
154 #define LL_CGC_FRC_PWM_0_PCLK MCU_SUB_FORCE_PWM_0_PCLK /**< Pclk for PWM0 */
155 #define LL_CGC_FRC_PWM_1_PCLK MCU_SUB_FORCE_PWM_1_PCLK /**< Pclk for PWM1 */
156 #define LL_CGC_FRC_VTTBL_PCLK MCU_SUB_FORCE_VTTBL_PCLK /**< Pclk for VTTBL */
157 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK /**< Div4 clk for security blocksi */
158 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
159
160 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x705E03CFUL) /**< Hclk for serial blocks */
161 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x7A7FC3CFUL) /**< All clock group 2 */
162 /** @} */
163
164 /** @defgroup CGC_LL_PERIPH_CG_LP_EN Low Power Feature
165 * @{
166 */
167 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN /**< Enable AHB2APB ASYNC low-power feature */
168 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN /**< Enable AHB2APB SYNC low-power feature */
169 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_EN MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN /**< Enable qspim low-power feature */
170 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN /**< Enable AHB bus low-power feature */
171 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN /**< Enable i2c sclk low-power feature */
172 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN /**< Enable spis sclk low-power feature */
173 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN /**< Enable spim sclk low-power feature */
174 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN /**< Enable i2s master low-power feature */
175 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN /**< Enable uart pclk low-power feature */
176 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN /**< Enable uart sclk low-power feature */
177
178 #define LL_CGC_MCU_PERIPH_CG_LP ((uint32_t)0x00000F3FUL) /**< All Low Power Feature */
179 /** @} */
180
181
182 /** @defgroup CGC_LL_SUBSYS_PERI_CLK_SLP_OFF Turn the peripherals off during WFI/WFE
183 * @{
184 */
185 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 /**< Turn the uart0 off during WFI/WFE */
186 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 /**< Turn the uart1 off during WFI/WFE */
187 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 /**< Turn the uart2 off during WFI/WFE */
188 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 /**< Turn the uart3 off during WFI/WFE */
189 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM /**< Turn the i2s_m off during WFI/WFE */
190 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS /**< Turn the i2s_s off during WFI/WFE */
191 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM /**< Turn the spi_m off during WFI/WFE */
192 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS /**< Turn the spi_s off during WFI/WFE */
193 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 /**< Turn the pwm0 off during WFI/WFE */
194 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 /**< Turn the pwm1 off during WFI/WFE */
195 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 /**< Turn the qspim0 off during WFI/WFE */
196 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 /**< Turn the qspim1 off during WFI/WFE */
197 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 /**< Turn the qspim2 off during WFI/WFE */
198 #define LL_CGC_MCU_PERIPH_CG_LP_EN_DSPI_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI /**< Turn the dspi off during WFI/WFE */
199 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PDM_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PDM /**< Turn the pdm off during WFI/WFE */
200 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 /**< Turn the i2c0 off during WFI/WFE */
201 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 /**< Turn the i2c1 off during WFI/WFE */
202 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 /**< Turn the i2c0 off during WFI/WFE */
203 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 /**< Turn the i2c1 off during WFI/WFE */
204
205 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_OFF ((uint32_t)0x007C3F0FUL) /**< Serial blocks */
206 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL ((uint32_t)0x007FFF0FUL) /**< Serial blocks */
207
208 /** @} */
209
210 /** @defgroup CGC_LL_SUBSYS_SECU_CLK_CTRL Individual block's clock control inside security system
211 * @{
212 */
213 #define LL_CGC_MCU_FRC_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF /**< Force individual aes's clock control */
214 #define LL_CGC_MCU_SLP_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF /**< Individual aes's clock control */
215 #define LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF /**< Force individual hmac's clock control */
216 #define LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF /**< Individual hmac's clock control */
217 #define LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF /**< Force individual pkc's clock control */
218 #define LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF /**< Individual pkc's clock control */
219 #define LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF /**< Force individual present's clock control */
220 #define LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF /**< Individual present's clock control */
221 #define LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF /**< Force individual ramkey's clock control */
222 #define LL_CGC_MCU_SLP_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF /**< Individual ramkey's clock control */
223 #define LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF /**< Force individual rng's clock control */
224 #define LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF /**< Individual rng's clock control */
225 #define LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF /**< Force individual efuse's clock control */
226 #define LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF /**< Individual efuse's clock control */
227
228 #define LL_CGC_MCU_SECU_FRC_OFF_HCLK ((uint32_t)0x00001555U) /**< Hclk for security clock */
229 #define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK ((uint32_t)0x00002AAAU) /**< Hclk for security clock WFI/WFE */
230
231 #define LL_CGC_MCU_SECU_FRC_OFF_ALL (LL_CGC_MCU_SECU_FRC_OFF_HCLK |\
232 LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK) /**< Hclk for security clock */
233 /** @} */
234
235 #define LL_CGC_MCU_MISC_CLK_DEFAULT ((uint32_t)0x00000038U) /**< Hclk for msic default clock */
236
237 #define LL_CGC_MCU_MISC_CLK ((uint32_t)0x0000003CU) /**< Hclk for msic all clock */
238
239 #define LL_CGC_MCU_MISC_DMA_CLK ((uint32_t)0x00000038U) /**< Hclk for msic dma clock */
240
241
242
243 /** @defgroup CGC_LL_SUBSYS_DEFAULT_CLK Specify the default system clock when the system is initialized
244 * @{
245 */
246 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0 (LL_CGC_WFI_SECU_HCLK |\
247 LL_CGC_WFI_SNSADC_HCLK |\
248 LL_CGC_WFI_GPIO_HCLK |\
249 LL_CGC_WFI_BLE_BRG_HCLK |\
250 LL_CGC_WFI_SERIAL_HCLK) /**< Hclk0 for the system default clock WFI/WFE */
251
252 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1 (LL_CGC_WFI_AON_MCUSUB_HCLK |\
253 LL_CGC_WFI_XF_XQSPI_HCLK |\
254 LL_CGC_WFI_SRAM_HCLK) /**< Hclk1 for the system default clock WFI/WFE */
255
256
257 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK0 (LL_CGC_FRC_SECU_HCLK |\
258 LL_CGC_FRC_SNSADC_HCLK |\
259 LL_CGC_FRC_SERIAL_HCLK) /**< Hclk for the system default clock */
260
261
262 #define LL_CGC_MCU_PERIPH_CG_DEFAULT (LL_CGC_FRC_UART0_PCLK |\
263 LL_CGC_FRC_UART1_PCLK |\
264 LL_CGC_FRC_UART2_PCLK |\
265 LL_CGC_FRC_UART3_PCLK |\
266 LL_CGC_FRC_I2C0_PCLK |\
267 LL_CGC_FRC_I2C1_PCLK |\
268 LL_CGC_FRC_I2C2_PCLK |\
269 LL_CGC_FRC_I2C3_PCLK |\
270 LL_CGC_FRC_QSPI0_PCLK |\
271 LL_CGC_FRC_QSPI1_PCLK |\
272 LL_CGC_FRC_QSPI2_PCLK |\
273 LL_CGC_FRC_SPI_M_PCLK |\
274 LL_CGC_FRC_SPI_S_PCLK |\
275 LL_CGC_FRC_I2S_PCLK |\
276 LL_CGC_FRC_I2S_S_PCLK |\
277 LL_CGC_FRC_DSPI_PCLK |\
278 LL_CGC_FRC_PDM_PCLK |\
279 LL_CGC_FRC_PWM_0_PCLK |\
280 LL_CGC_FRC_PWM_1_PCLK) /**< pclk for the system default periph clock */
281
282 #define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT (MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
283 MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
284 MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 |\
285 MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 |\
286 MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM |\
287 MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS |\
288 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
289 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
290 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
291 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
292 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 |\
293 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 |\
294 MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 |\
295 MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI |\
296 MCU_SUB_PERIPH_CLK_SLP_OFF_PDM |\
297 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
298 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 |\
299 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 |\
300 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 ) /**< pclk for the system default periph wfi clock */
301
302 #define CGC_CLOCK_ENABLE (1) /**< Bit segment address enable */
303 #define CGC_CLOCK_DISABLE (0) /**< Bit segment address disable */
304
305 #if defined(BIT_BAND_SUPPORT)
306
307 #define BIT_SEGMENT_VALUE BIT_ADDR /**< Bit segment address value manipulation */
308
309 #else
310
311 #define BIT_BAND(addr, bitnum) (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2)) /**< Bit segment address calculation */
312 #define MEMORY_ADDR(addr) (*((volatile uint32_t *)(addr))) /**< Bit segment address type conversion */
313 #define BIT_SEGMENT_VALUE(addr, bitnum) MEMORY_ADDR(BIT_BAND(addr, bitnum)) /**< Bit segment address value manipulation */
314
315 #endif
316
317 /** @} */
318
319 /** @} */
320
321 /** @} */
322
323 /* Private types -------------------------------------------------------------*/
324 /* Private variables ---------------------------------------------------------*/
325 /* Private constants ---------------------------------------------------------*/
326 /* Private macros ------------------------------------------------------------*/
327 /* Exported functions --------------------------------------------------------*/
328 /** @defgroup CGC_LL_DRIVER_FUNCTIONS Functions
329 * @{
330 */
331
332 /**
333 * @brief Some peripherals automatic turn off clock during WFI. (Include: Security/HTB/PWM/
334 * ROM/SNSADC/GPIO/BLE_BRG/APB_SUB/SERIAL)
335 *
336 * Register | BitsName
337 * ----------|--------
338 * CG_CTRL_0 | SECU_HCLK
339 * CG_CTRL_0 | HTB_HCLK
340 * CG_CTRL_0 | PWM_HCLK
341 * CG_CTRL_0 | ROM_HCLK
342 * CG_CTRL_0 | SNSADC_HCLK
343 * CG_CTRL_0 | GPIO_HCLK
344 * CG_CTRL_0 | BLE_BRG_HCLK
345 * CG_CTRL_0 | APB_SUB_HCLK
346 * CG_CTRL_0 | SERIAL_HCLK
347 *
348 * @param clk_mask This parameter can be a combination of the following values:
349 * @arg @ref LL_CGC_WFI_SECU_HCLK
350 * @arg @ref LL_CGC_WFI_HTB_HCLK
351 * @arg @ref LL_CGC_WFI_ROM_HCLK
352 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
353 * @arg @ref LL_CGC_WFI_GPIO_HCLK
354 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
355 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
356 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
357 * @retval None
358 */
359 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
360 {
361 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0], LL_CGC_WFI_ALL_HCLK0, clk_mask);
362 }
363
364 /**
365 * @brief Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/
366 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
367 *
368 * Register | BitsName
369 * ----------|--------
370 * CG_CTRL_0 | SECU_HCLK
371 * CG_CTRL_0 | SIM_HCLK
372 * CG_CTRL_0 | HTB_HCLK
373 * CG_CTRL_0 | PWM_HCLK
374 * CG_CTRL_0 | ROM_HCLK
375 * CG_CTRL_0 | SNSADC_HCLK
376 * CG_CTRL_0 | GPIO_HCLK
377 * CG_CTRL_0 | DMA_HCLK
378 * CG_CTRL_0 | BLE_BRG_HCLK
379 * CG_CTRL_0 | APB_SUB_HCLK
380 * CG_CTRL_0 | SERIAL_HCLK
381 *
382 * @retval Returned value can be a combination of the following values:
383 * @arg @ref LL_CGC_WFI_SECU_HCLK
384 * @arg @ref LL_CGC_WFI_HTB_HCLK
385 * @arg @ref LL_CGC_WFI_ROM_HCLK
386 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
387 * @arg @ref LL_CGC_WFI_GPIO_HCLK
388 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
389 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
390 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
391 */
392 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
393 {
394 return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0]);
395 }
396
397 /**
398 * @brief Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
399 *
400 * Register | BitsName
401 * ----------|--------
402 * CG_CTRL_2 | AON_MCUSUB_HCLK
403 * CG_CTRL_2 | XF_XQSPI_HCLK
404 * CG_CTRL_2 | SRAM_HCLK
405 *
406 * @param clk_mask This parameter can be a combination of the following values:
407 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
408 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
409 * @arg @ref LL_CGC_WFI_SRAM_HCLK
410 * @retval None
411 */
412 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
413 {
414 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1, clk_mask);
415 }
416
417 /**
418 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
419 *
420 * Register | BitsName
421 * ----------|--------
422 * CG_CTRL_2 | AON_MCUSUB_HCLK
423 * CG_CTRL_2 | XF_XQSPI_HCLK
424 * CG_CTRL_2 | SRAM_HCLK
425 *
426 * @retval Returned value can be a combination of the following values:
427 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
428 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
429 * @arg @ref LL_CGC_WFI_SRAM_HCLK
430 */
431 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
432 {
433 return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1);
434 }
435
436 /**
437 * @brief Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
438 *
439 * Register | BitsName
440 * ----------|--------
441 * PERIPH_GC | SECU_DIV4_PCLK
442 * PERIPH_GC | XQSPI_DIV4_PCLK
443 *
444 * @param clk_mask This parameter can be a combination of the following values:
445 * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
446 * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
447 * @retval None
448 */
449 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
450 {
451 MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2, clk_mask);
452 }
453
454 /**
455 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
456 *
457 * Register | BitsName
458 * ----------|--------
459 * PERIPH_GC | SECU_DIV4_PCLK
460 * PERIPH_GC | XQSPI_DIV4_PCLK
461 *
462 * @retval Returned value can be a combination of the following values:
463 * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
464 * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
465 */
466 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
467 {
468 return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2);
469 }
470
471 /**
472 * @brief Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI.etc)
473 *
474 * Register | BitsName
475 * ----------|--------
476 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
477 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
478 *
479 * @param clk_mask This parameter can be a combination of the following values:
480 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
481 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
482 * .....
483 * @retval None
484 */
485 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
486 {
487 MODIFY_REG(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL, clk_mask);
488 }
489
490 /**
491 * @brief Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI.etc)
492 *
493 * Register | BitsName
494 * ----------|--------
495 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
496 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
497 *
498 * @retval Returned value can be a combination of the following values:
499 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
500 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
501 * .....
502 */
503 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
504 {
505 return READ_BITS(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL);
506 }
507
508 /**
509 * @brief Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
510 *
511 * Register | BitsName
512 * ----------|--------
513 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
514 *
515 * @param clk_mask This parameter can be a combination of the following values:
516 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
517 * .....
518 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
519 * @retval None
520 */
521 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
522 {
523 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
524 }
525
526 /**
527 * @brief Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
528 *
529 * Register | BitsName
530 * ----------|--------
531 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
532 *
533 * @retval Returned value can be a combination of the following values:
534 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
535 * .....
536 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
537 */
538 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
539 {
540 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
541 }
542
543 /**
544 * @brief Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/
545 * DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
546 *
547 * Register | BitsName
548 * ----------|--------
549 * CG_CTRL_1 | SECU_HCLK
550 * CG_CTRL_1 | SIM_HCLK
551 * CG_CTRL_1 | HTB_HCLK
552 * CG_CTRL_1 | ROM_HCLK
553 * CG_CTRL_1 | SNSADC_HCLK
554 * CG_CTRL_1 | GPIO_HCLK
555 * CG_CTRL_1 | DMA_HCLK
556 * CG_CTRL_1 | BLE_BRG_HCLK
557 * CG_CTRL_1 | APB_SUB_HCLK
558 * CG_CTRL_1 | SERIAL_HCLK
559 *
560 * @param clk_mask This parameter can be a combination of the following values:
561 * @arg @ref LL_CGC_FRC_SECU_HCLK
562 * @arg @ref LL_CGC_FRC_HTB_HCLK
563 * @arg @ref LL_CGC_FRC_ROM_HCLK
564 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
565 * @arg @ref LL_CGC_FRC_GPIO_HCLK
566 * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
567 * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
568 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
569 * @retval None
570 */
571 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
572 {
573 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1], LL_CGC_FRC_ALL_HCLK0, clk_mask);
574 }
575
576 /**
577 * @brief Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/
578 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
579 *
580 * Register | BitsName
581 * ----------|--------
582 * CG_CTRL_1 | SECU_HCLK
583 * CG_CTRL_1 | SIM_HCLK
584 * CG_CTRL_1 | HTB_HCLK
585 * CG_CTRL_1 | ROM_HCLK
586 * CG_CTRL_1 | SNSADC_HCLK
587 * CG_CTRL_1 | GPIO_HCLK
588 * CG_CTRL_1 | DMA_HCLK
589 * CG_CTRL_1 | BLE_BRG_HCLK
590 * CG_CTRL_1 | APB_SUB_HCLK
591 * CG_CTRL_1 | SERIAL_HCLK
592 *
593 * @retval Returned value can be a combination of the following values:
594 * @arg @ref LL_CGC_FRC_SECU_HCLK
595 * @arg @ref LL_CGC_FRC_HTB_HCLK
596 * @arg @ref LL_CGC_FRC_ROM_HCLK
597 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
598 * @arg @ref LL_CGC_FRC_GPIO_HCLK
599 * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
600 * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
601 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
602 */
603 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
604 {
605 return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1]);
606 }
607
608 /**
609 * @brief Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
610 *
611 * Register | BitsName
612 * ----------|--------
613 * CG_CTRL_2 | AON_MCUSUB_HCLK
614 * CG_CTRL_2 | XF_XQSPI_HCLK
615 * CG_CTRL_2 | SRAM_HCLK
616 *
617 * @param clk_mask This parameter can be a combination of the following values:
618 * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
619 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
620 * @arg @ref LL_CGC_FRC_SRAM_HCLK
621 * @retval None
622 */
623 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
624 {
625 MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1, clk_mask);
626 }
627
628 /**
629 * @brief Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
630 *
631 * Register | BitsName
632 * ----------|--------
633 * CG_CTRL_2 | AON_MCUSUB_HCLK
634 * CG_CTRL_2 | XF_XQSPI_HCLK
635 * CG_CTRL_2 | SRAM_HCLK
636 *
637 * @retval Returned value can be a combination of the following values:
638 * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
639 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
640 * @arg @ref LL_CGC_FRC_SRAM_HCLK
641 */
642 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
643 {
644 return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1);
645 }
646
647 /**
648 * @brief Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
649 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
650 *
651 * Register | BitsName
652 * ----------|--------
653 * PERIPH_GC | UART0_HCLK
654 * PERIPH_GC | UART1_HCLK
655 * PERIPH_GC | UART2_HCLK
656 * PERIPH_GC | UART3_HCLK
657 * PERIPH_GC | I2C0_HCLK
658 * PERIPH_GC | I2C1_HCLK
659 * PERIPH_GC | SPIM_HCLK
660 * PERIPH_GC | SPIS_HCLK
661 * PERIPH_GC | QSPI0_HCLK
662 * PERIPH_GC | QSPI1_HCLK
663 * PERIPH_GC | I2S_HCLK
664 * PERIPH_GC | SECU_DIV4_PCLK
665 * PERIPH_GC | XQSPI_DIV4_PCLK
666 * PERIPH_GC | PWM0_HCLK
667 * PERIPH_GC | PWM1_HCLK
668 *
669 * @param clk_mask This parameter can be a combination of the following values:
670 * @arg @ref LL_CGC_FRC_UART0_PCLK
671 * @arg @ref LL_CGC_FRC_UART1_PCLK
672 * @arg @ref LL_CGC_FRC_UART2_PCLK
673 * @arg @ref LL_CGC_FRC_UART3_PCLK
674 * @arg @ref LL_CGC_FRC_I2C0_PCLK
675 * @arg @ref LL_CGC_FRC_I2C1_PCLK
676 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
677 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
678 * @arg @ref LL_CGC_FRC_QSPI0_PCLK
679 * @arg @ref LL_CGC_FRC_QSPI1_PCLK
680 * @arg @ref LL_CGC_FRC_I2S_PCLK
681 * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
682 * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
683 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
684 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
685 * @retval None
686 */
687 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
688 {
689 MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2, clk_mask);
690 }
691
692
693 /**
694 * @brief Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
695 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
696 *
697 * Register | BitsName
698 * ----------|--------
699 * PERIPH_GC | UART0_HCLK
700 * PERIPH_GC | UART1_HCLK
701 * PERIPH_GC | UART2_HCLK
702 * PERIPH_GC | UART3_HCLK
703 * PERIPH_GC | UART4_HCLK
704 * PERIPH_GC | UART5_HCLK
705 * PERIPH_GC | I2C0_HCLK
706 * PERIPH_GC | I2C1_HCLK
707 * PERIPH_GC | SPIM_HCLK
708 * PERIPH_GC | SPIS_HCLK
709 * PERIPH_GC | QSPI0_HCLK
710 * PERIPH_GC | QSPI1_HCLK
711 * PERIPH_GC | I2S_HCLK
712 * PERIPH_GC | SECU_DIV4_PCLK
713 * PERIPH_GC | XQSPI_DIV4_PCLK
714 * PERIPH_GC | PWM0_HCLK
715 * PERIPH_GC | PWM1_HCLK
716 *
717 * @retval Returned value can be a combination of the following values:
718 * @arg @ref LL_CGC_FRC_UART0_PCLK
719 * @arg @ref LL_CGC_FRC_UART1_PCLK
720 * @arg @ref LL_CGC_FRC_UART2_PCLK
721 * @arg @ref LL_CGC_FRC_UART3_PCLK
722 * @arg @ref LL_CGC_FRC_I2C0_PCLK
723 * @arg @ref LL_CGC_FRC_I2C1_PCLK
724 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
725 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
726 * @arg @ref LL_CGC_FRC_QSPI0_PCLK
727 * @arg @ref LL_CGC_FRC_QSPI1_PCLK
728 * @arg @ref LL_CGC_FRC_I2S_PCLK
729 * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
730 * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
731 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
732 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
733 */
734 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
735 {
736 return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2);
737 }
738
739 /**
740 * @brief Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
741 *
742 * Register | BitsName
743 * ----------|--------
744 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
745 *
746 * @param clk_mask This parameter can be a combination of the following values:
747 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
748 * .....
749 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
750 * @retval None
751 */
752 __STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
753 {
754 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
755 }
756
757 /**
758 * @brief Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
759 *
760 * Register | BitsName
761 * ----------|--------
762 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
763 *
764 * @retval Returned value can be a combination of the following values:
765 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
766 * .....
767 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
768 */
769 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
770 {
771 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
772 }
773
774
775 /**
776 * @brief Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
777 *
778 * Register | BitsName
779 * ----------|--------
780 * CG_CTRL_0 | SECU_HCLK
781 *
782 * @retval None
783 */
784 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
785 {
786 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
787 }
788
789 /**
790 * @brief Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
791 *
792 * Register | BitsName
793 * ----------|--------
794 * CG_CTRL_0 | SECU_HCLK
795 *
796 * @retval None
797 */
798 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
799 {
800 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
801 }
802
803 /**
804 * @brief Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is enabled.
805 *
806 * Register | BitsName
807 * ----------|--------
808 * CG_CTRL_0 | SECU_HCLK
809 *
810 * @retval State of bit (1 or 0).
811 */
812 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
813 {
814 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
815 }
816
817 /**
818 * @brief Enable Hopping Table automatic turn off clock during WFI
819 *
820 * Register | BitsName
821 * ----------|--------
822 * CG_CTRL_0 | HTB_HCLK
823 *
824 * @retval None
825 */
826 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
827 {
828 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
829 }
830
831 /**
832 * @brief Disable Hopping Table automatic turn off clock during WFI
833 *
834 * Register | BitsName
835 * ----------|--------
836 * CG_CTRL_0 | HTB_HCLK
837 *
838 * @retval None
839 */
840 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
841 {
842 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
843 }
844
845 /**
846 * @brief Indicate whether the Hopping Table automatic turn off clock is enabled.
847 *
848 * Register | BitsName
849 * ----------|--------
850 * CG_CTRL_0 | HTB_HCLK
851 *
852 * @retval State of bit (1 or 0).
853 */
854 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
855 {
856 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
857 }
858
859 /**
860 * @brief Enable ROM automatic turn off clock during WFI
861 *
862 * Register | BitsName
863 * ----------|--------
864 * CG_CTRL_0 | ROM_HCLK
865 *
866 * @retval None
867 */
868 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
869 {
870 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
871 }
872
873 /**
874 * @brief Disable ROM automatic turn off clock during WFI
875 *
876 * Register | BitsName
877 * ----------|--------
878 * CG_CTRL_0 | ROM_HCLK
879 *
880 * @retval None
881 */
882 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
883 {
884 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
885 }
886
887 /**
888 * @brief Indicate whether the ROM automatic turn off clock is enabled.
889 *
890 * Register | BitsName
891 * ----------|--------
892 * CG_CTRL_0 | ROM_HCLK
893 *
894 * @retval State of bit (1 or 0).
895 */
896 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
897 {
898 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
899 }
900
901 /**
902 * @brief Enable SNSADC automatic turn off clock during WFI
903 *
904 * Register | BitsName
905 * ----------|--------
906 * CG_CTRL_0 | SNSADC_HCLK
907 *
908 * @retval None
909 */
910 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
911 {
912 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
913 }
914
915 /**
916 * @brief Disable SNSADC automatic turn off clock during WFI
917 *
918 * Register | BitsName
919 * ----------|--------
920 * CG_CTRL_0 | SNSADC_HCLK
921 *
922 * @retval None
923 */
924 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
925 {
926 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
927 }
928
929 /**
930 * @brief Indicate whether the SNSADC automatic turn off clock is enabled.
931 *
932 * Register | BitsName
933 * ----------|--------
934 * CG_CTRL_0 | SNSADC_HCLK
935 *
936 * @retval State of bit (1 or 0).
937 */
938 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
939 {
940 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
941 }
942
943 /**
944 * @brief Enable GPIO automatic turn off clock during WFI
945 *
946 * Register | BitsName
947 * ----------|--------
948 * CG_CTRL_0 | GPIO_HCLK
949 *
950 * @retval None
951 */
952 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
953 {
954 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
955 }
956
957 /**
958 * @brief Disable GPIO automatic turn off clock during WFI
959 *
960 * Register | BitsName
961 * ----------|--------
962 * CG_CTRL_0 | GPIO_HCLK
963 *
964 * @retval None
965 */
966 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
967 {
968 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
969 }
970
971 /**
972 * @brief Indicate whether the GPIO automatic turn off clock is enabled.
973 *
974 * Register | BitsName
975 * ----------|--------
976 * CG_CTRL_0 | GPIO_HCLK
977 *
978 * @retval State of bit (1 or 0).
979 */
980 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
981 {
982 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
983 }
984
985 /**
986 * @brief Enable DMA automatic turn off clock during WFI
987 *
988 * Register | BitsName
989 * ----------|--------
990 * CG_CTRL_0 | DMA_HCLK
991 *
992 * @retval None
993 */
994 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
995 {
996 // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_ENABLE;
997 }
998
999 /**
1000 * @brief Disable DMA automatic turn off clock during WFI
1001 *
1002 * Register | BitsName
1003 * ----------|--------
1004 * CG_CTRL_0 | DMA_HCLK
1005 *
1006 * @retval None
1007 */
1008 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
1009 {
1010 // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_DISABLE;
1011 }
1012
1013 /**
1014 * @brief Indicate whether the DMA automatic turn off clock is enabled.
1015 *
1016 * Register | BitsName
1017 * ----------|--------
1018 * CG_CTRL_0 | DMA_HCLK
1019 *
1020 * @retval State of bit (1 or 0).
1021 */
1022 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
1023 {
1024 // return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1025 return 0;
1026 }
1027
1028 /**
1029 * @brief Enable BLE Bridge automatic turn off clock during WFI
1030 *
1031 * Register | BitsName
1032 * ----------|--------
1033 * CG_CTRL_0 | BLE_BRG_HCLK
1034 *
1035 * @retval None
1036 */
1037 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
1038 {
1039 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1040 }
1041
1042 /**
1043 * @brief Disable BLE Bridge automatic turn off clock during WFI
1044 *
1045 * Register | BitsName
1046 * ----------|--------
1047 * CG_CTRL_0 | BLE_BRG_HCLK
1048 *
1049 * @retval None
1050 */
1051 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1052 {
1053 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1054 }
1055
1056 /**
1057 * @brief Indicate whether the BLE Bridge automatic turn off clock is enabled.
1058 *
1059 * Register | BitsName
1060 * ----------|--------
1061 * CG_CTRL_0 | BLE_BRG_HCLK
1062 *
1063 * @retval State of bit (1 or 0).
1064 */
1065 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1066 {
1067 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1068 }
1069
1070 /**
1071 * @brief Enable APB Subsystem automatic turn off clock during WFI
1072 *
1073 * Register | BitsName
1074 * ----------|--------
1075 * CG_CTRL_0 | APB_SUB_HCLK
1076 *
1077 * @retval None
1078 */
1079 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1080 {
1081 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1082 }
1083
1084 /**
1085 * @brief Disable APB Subsystem automatic turn off clock during WFI
1086 *
1087 * Register | BitsName
1088 * ----------|--------
1089 * CG_CTRL_0 | APB_SUB_HCLK
1090 *
1091 * @retval None
1092 */
1093 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1094 {
1095 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1096 }
1097
1098 /**
1099 * @brief Indicate whether the APB Subsystem automatic turn off clock is enabled.
1100 *
1101 * Register | BitsName
1102 * ----------|--------
1103 * CG_CTRL_0 | APB_SUB_HCLK
1104 *
1105 * @retval State of bit (1 or 0).
1106 */
1107 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1108 {
1109 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1110 }
1111
1112 /**
1113 * @brief Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1114 *
1115 * Register | BitsName
1116 * ----------|--------
1117 * CG_CTRL_0 | SERIAL_HCLK
1118 *
1119 * @retval None
1120 */
1121 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1122 {
1123 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1124 }
1125
1126 /**
1127 * @brief Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1128 *
1129 * Register | BitsName
1130 * ----------|--------
1131 * CG_CTRL_0 | SERIAL_HCLK
1132 *
1133 * @retval None
1134 */
1135 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1136 {
1137 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1138 }
1139
1140 /**
1141 * @brief Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off
1142 * clock is enabled.
1143 *
1144 * Register | BitsName
1145 * ----------|--------
1146 * CG_CTRL_0 | SERIAL_HCLK
1147 *
1148 * @retval State of bit (1 or 0).
1149 */
1150 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1151 {
1152 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1153 }
1154
1155 /**
1156 * @brief Enable AON_MUCSUB automatic turn off clock during WFI
1157 *
1158 * Register | BitsName
1159 * ----------|--------
1160 * CG_CTRL_2 | AON_MCUSUB_HCLK
1161 *
1162 * @retval None
1163 */
1164 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1165 {
1166 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1167 }
1168
1169 /**
1170 * @brief Disable AON_MUCSUB automatic turn off clock during WFI
1171 *
1172 * Register | BitsName
1173 * ----------|--------
1174 * CG_CTRL_2 | AON_MCUSUB_HCLK
1175 *
1176 * @retval None
1177 */
1178 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1179 {
1180 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1181 }
1182
1183 /**
1184 * @brief Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
1185 *
1186 * Register | BitsName
1187 * ----------|--------
1188 * CG_CTRL_2 | AON_MCUSUB_HCLK
1189 *
1190 * @retval State of bit (1 or 0).
1191 */
1192 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1193 {
1194 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1195 }
1196
1197 /**
1198 * @brief Enable XQSPI automatic turn off clock during WFI
1199 *
1200 * Register | BitsName
1201 * ----------|--------
1202 * CG_CTRL_2 | XF_XQSPI_HCLK
1203 *
1204 * @retval None
1205 */
1206 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1207 {
1208 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1209 }
1210
1211 /**
1212 * @brief Disable XQSPI automatic turn off clock during WFI
1213 *
1214 * Register | BitsName
1215 * ----------|--------
1216 * CG_CTRL_2 | XF_XQSPI_HCLK
1217 *
1218 * @retval None
1219 */
1220 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1221 {
1222 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1223 }
1224
1225 /**
1226 * @brief Indicate whether the XQSPI automatic turn off clock is enabled.
1227 *
1228 * Register | BitsName
1229 * ----------|--------
1230 * CG_CTRL_2 | XF_XQSPI_HCLK
1231 *
1232 * @retval State of bit (1 or 0).
1233 */
1234 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1235 {
1236 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1237 }
1238
1239 /**
1240 * @brief Enable SRAM automatic turn off clock during WFI
1241 *
1242 * Register | BitsName
1243 * ----------|--------
1244 * CG_CTRL_2 | SRAM_HCLK
1245 *
1246 * @retval None
1247 */
1248 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1249 {
1250 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1251 }
1252
1253 /**
1254 * @brief Disable SRAM automatic turn off clock during WFI
1255 *
1256 * Register | BitsName
1257 * ----------|--------
1258 * CG_CTRL_2 | SRAM_HCLK
1259 *
1260 * @retval None
1261 */
1262 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1263 {
1264 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1265 }
1266
1267 /**
1268 * @brief Indicate whether the SRAM automatic turn off clock is enabled.
1269 *
1270 * Register | BitsName
1271 * ----------|--------
1272 * CG_CTRL_2 | SRAM_HCLK
1273 *
1274 * @retval State of bit (1 or 0).
1275 */
1276 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1277 {
1278 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1279 }
1280
1281 /**
1282 * @brief Enable security blocks automatic turn off div4 clock during WFI
1283 *
1284 * Register | BitsName
1285 * ----------|--------
1286 * PERIPH_GC | SECU_DIV4_PCLK
1287 *
1288 * @retval None
1289 */
1290 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1291 {
1292 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1293 }
1294
1295 /**
1296 * @brief Disable security blocks automatic turn off div4 clock during WFI
1297 *
1298 * Register | BitsName
1299 * ----------|--------
1300 * PERIPH_GC | SECU_DIV4_PCLK
1301 *
1302 * @retval None
1303 */
1304 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1305 {
1306 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1307 }
1308
1309 /**
1310 * @brief Indicate whether the security blocks automatic turn off div4
1311 * clock is enabled.
1312 *
1313 * Register | BitsName
1314 * ----------|--------
1315 * PERIPH_GC | SECU_DIV4_PCLK
1316 *
1317 * @retval State of bit (1 or 0).
1318 */
1319 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1320 {
1321 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1322 }
1323
1324 /**
1325 * @brief Enable XQSPI automatic turn off div4 clock during WFI
1326 *
1327 * Register | BitsName
1328 * ----------|--------
1329 * PERIPH_GC | XQSPI_DIV4_PCLK
1330 *
1331 * @retval None
1332 */
1333 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1334 {
1335 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1336 }
1337
1338 /**
1339 * @brief Disable XQSPI automatic turn off div4 clock during WFI
1340 *
1341 * Register | BitsName
1342 * ----------|--------
1343 * PERIPH_GC | XQSPI_DIV4_PCLK
1344 *
1345 * @retval None
1346 */
1347 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1348 {
1349 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1350 }
1351
1352 /**
1353 * @brief Indicate whether the XQSPI automatic turn off div4 clock is enabled.
1354 *
1355 * Register | BitsName
1356 * ----------|--------
1357 * PERIPH_GC | XQSPI_DIV4_PCLK
1358 *
1359 * @retval State of bit (1 or 0).
1360 */
1361 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1362 {
1363 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1364 }
1365
1366 /**
1367 * @brief Enabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1368 *
1369 * Register | BitsName
1370 * ----------|--------
1371 * CG_CTRL_1 | SECU_HCLK
1372 *
1373 * @retval None
1374 */
1375 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1376 {
1377 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
1378 }
1379
1380 /**
1381 * @brief Disabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1382 *
1383 * Register | BitsName
1384 * ----------|--------
1385 * CG_CTRL_1 | SECU_HCLK
1386 *
1387 * @retval None
1388 */
1389 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1390 {
1391 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
1392 }
1393
1394 /**
1395 * @brief Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
1396 *
1397 * Register | BitsName
1398 * ----------|--------
1399 * CG_CTRL_1 | SECU_HCLK
1400 *
1401 * @retval State of bit (1 or 0).
1402 */
1403 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1404 {
1405 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1406 }
1407
1408 /**
1409 * @brief Enabling force to turn off the clock for Hopping Table.
1410 *
1411 * Register | BitsName
1412 * ----------|--------
1413 * CG_CTRL_1 | HTB_HCLK
1414 *
1415 * @retval None
1416 */
1417 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1418 {
1419 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1420 }
1421
1422 /**
1423 * @brief Disabling force to turn off the clock for Hopping Table.
1424 *
1425 * Register | BitsName
1426 * ----------|--------
1427 * CG_CTRL_1 | HTB_HCLK
1428 *
1429 * @retval None
1430 */
1431 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1432 {
1433 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1434 }
1435
1436 /**
1437 * @brief Indicate whether the clock for Hopping Table is forced to close.
1438 *
1439 * Register | BitsName
1440 * ----------|--------
1441 * CG_CTRL_1 | HTB_HCLK
1442 *
1443 * @retval State of bit (1 or 0).
1444 */
1445 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1446 {
1447 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1448 }
1449
1450 /**
1451 * @brief Enabling force to turn off the clock for ROM.
1452 *
1453 * Register | BitsName
1454 * ----------|--------
1455 * CG_CTRL_1 | ROM_HCLK
1456 *
1457 * @retval None
1458 */
1459 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1460 {
1461 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1462 }
1463
1464 /**
1465 * @brief Disabling force to turn off the clock for ROM.
1466 *
1467 * Register | BitsName
1468 * ----------|--------
1469 * CG_CTRL_1 | ROM_HCLK
1470 *
1471 * @retval None
1472 */
1473 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1474 {
1475 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1476 }
1477
1478 /**
1479 * @brief Indicate whether the clock for ROM is forced to close.
1480 *
1481 * Register | BitsName
1482 * ----------|--------
1483 * CG_CTRL_1 | ROM_HCLK
1484 *
1485 * @retval State of bit (1 or 0).
1486 */
1487 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1488 {
1489 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1490 }
1491
1492 /**
1493 * @brief Enabling force to turn off the clock for SNSADC.
1494 *
1495 * Register | BitsName
1496 * ----------|--------
1497 * CG_CTRL_1 | SNSADC_HCLK
1498 *
1499 * @retval None
1500 */
1501 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1502 {
1503 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1504 }
1505
1506 /**
1507 * @brief Disabling force to turn off the clock for SNSADC.
1508 *
1509 * Register | BitsName
1510 * ----------|--------
1511 * CG_CTRL_1 | SNSADC_HCLK
1512 *
1513 * @retval None
1514 */
1515 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1516 {
1517 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1518 }
1519
1520 /**
1521 * @brief Indicate whether the clock for SNSADC is forced to close.
1522 *
1523 * Register | BitsName
1524 * ----------|--------
1525 * CG_CTRL_1 | SNSADC_HCLK
1526 *
1527 * @retval State of bit (1 or 0).
1528 */
1529 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1530 {
1531 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1532 }
1533
1534 /**
1535 * @brief Enabling force to turn off the clock for GPIO.
1536 *
1537 * Register | BitsName
1538 * ----------|--------
1539 * CG_CTRL_1 | GPIO_HCLK
1540 *
1541 * @retval None
1542 */
1543 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1544 {
1545 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1546 }
1547
1548 /**
1549 * @brief Disabling force to turn off the clock for GPIO.
1550 *
1551 * Register | BitsName
1552 * ----------|--------
1553 * CG_CTRL_1 | GPIO_HCLK
1554 *
1555 * @retval None
1556 */
1557 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1558 {
1559 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1560 }
1561
1562 /**
1563 * @brief Indicate whether the clock for GPIO is forced to close.
1564 *
1565 * Register | BitsName
1566 * ----------|--------
1567 * CG_CTRL_1 | GPIO_HCLK
1568 *
1569 * @retval State of bit (1 or 0).
1570 */
1571 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1572 {
1573 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1574 }
1575
1576 /**
1577 * @brief Enabling force to turn off the clock for BLE Bridge.
1578 *
1579 * Register | BitsName
1580 * ----------|--------
1581 * CG_CTRL_1 | BLE_BRG_HCLK
1582 *
1583 * @retval None
1584 */
1585 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1586 {
1587 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1588 }
1589
1590 /**
1591 * @brief Disabling force to turn off the clock for BLE Bridge.
1592 *
1593 * Register | BitsName
1594 * ----------|--------
1595 * CG_CTRL_1 | BLE_BRG_HCLK
1596 *
1597 * @retval None
1598 */
1599 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1600 {
1601 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1602 }
1603
1604 /**
1605 * @brief Indicate whether the clock for BLE Bridge is forced to close.
1606 *
1607 * Register | BitsName
1608 * ----------|--------
1609 * CG_CTRL_1 | BLE_BRG_HCLK
1610 *
1611 * @retval State of bit (1 or 0).
1612 */
1613 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1614 {
1615 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1616 }
1617
1618 /**
1619 * @brief Enabling force to turn off the clock for APB Subsystem.
1620 *
1621 * Register | BitsName
1622 * ----------|--------
1623 * CG_CTRL_1 | APB_SUB_HCLK
1624 *
1625 * @retval None
1626 */
1627 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1628 {
1629 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1630 }
1631
1632 /**
1633 * @brief Disabling force to turn off the clock for APB Subsystem.
1634 *
1635 * Register | BitsName
1636 * ----------|--------
1637 * CG_CTRL_1 | APB_SUB_HCLK
1638 *
1639 * @retval None
1640 */
1641 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1642 {
1643 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1644 }
1645
1646 /**
1647 * @brief Indicate whether the clock for APB Subsystem is forced to close.
1648 *
1649 * Register | BitsName
1650 * ----------|--------
1651 * CG_CTRL_1 | APB_SUB_HCLK
1652 *
1653 * @retval State of bit (1 or 0).
1654 */
1655 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1656 {
1657 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1658 }
1659
1660 /**
1661 * @brief Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1662 *
1663 * Register | BitsName
1664 * ----------|--------
1665 * CG_CTRL_1 | SERIAL_HCLK
1666 *
1667 * @retval None
1668 */
1669 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1670 {
1671 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1672 }
1673
1674 /**
1675 * @brief Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1676 *
1677 * Register | BitsName
1678 * ----------|--------
1679 * CG_CTRL_1 | SERIAL_HCLK
1680 *
1681 * @retval None
1682 */
1683 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1684 {
1685 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1686 }
1687
1688 /**
1689 * @brief Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
1690 *
1691 * Register | BitsName
1692 * ----------|--------
1693 * CG_CTRL_1 | SERIAL_HCLK
1694 *
1695 * @retval State of bit (1 or 0).
1696 */
1697 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1698 {
1699 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1700 }
1701
1702 /**
1703 * @brief Enabling force to turn off the clock for AON_MUCSUB.
1704 *
1705 * Register | BitsName
1706 * ----------|--------
1707 * CG_CTRL_2 | AON_MCUSUB_HCLK
1708 *
1709 * @retval None
1710 */
1711 __STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
1712 {
1713 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1714 }
1715
1716 /**
1717 * @brief Disabling force to turn off the clock for AON_MUCSUB.
1718 *
1719 * Register | BitsName
1720 * ----------|--------
1721 * CG_CTRL_2 | AON_MCUSUB_HCLK
1722 *
1723 * @retval None
1724 */
1725 __STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
1726 {
1727 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1728 }
1729
1730 /**
1731 * @brief Indicate whether the clock for AON_MUCSUB is forced to close.
1732 *
1733 * Register | BitsName
1734 * ----------|--------
1735 * CG_CTRL_2 | AON_MCUSUB_HCLK
1736 *
1737 * @retval State of bit (1 or 0).
1738 */
1739 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
1740 {
1741 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1742 }
1743
1744 /**
1745 * @brief Enabling force to turn off the clock for XQSPI.
1746 *
1747 * Register | BitsName
1748 * ----------|--------
1749 * CG_CTRL_2 | XF_XQSPI_HCLK
1750 *
1751 * @retval None
1752 */
1753 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
1754 {
1755 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1756 }
1757
1758 /**
1759 * @brief Disabling force to turn off the clock for XQSPI.
1760 *
1761 * Register | BitsName
1762 * ----------|--------
1763 * CG_CTRL_2 | XF_XQSPI_HCLK
1764 *
1765 * @retval None
1766 */
1767 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
1768 {
1769 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1770 }
1771
1772 /**
1773 * @brief Indicate whether the clock for XQSPI is forced to close.
1774 *
1775 * Register | BitsName
1776 * ----------|--------
1777 * CG_CTRL_2 | XF_XQSPI_HCLK
1778 *
1779 * @retval State of bit (1 or 0).
1780 */
1781 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
1782 {
1783 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1784 }
1785
1786 /**
1787 * @brief Enabling force to turn off the clock for SRAM.
1788 *
1789 * Register | BitsName
1790 * ----------|--------
1791 * CG_CTRL_2 | SRAM_HCLK
1792 *
1793 * @retval None
1794 */
1795 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
1796 {
1797 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1798 }
1799
1800 /**
1801 * @brief Disabling force to turn off the clock for SRAM.
1802 *
1803 * Register | BitsName
1804 * ----------|--------
1805 * CG_CTRL_2 | SRAM_HCLK
1806 *
1807 * @retval None
1808 */
1809 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
1810 {
1811 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1812 }
1813
1814 /**
1815 * @brief Indicate whether the clock for SRAM is forced to close.
1816 *
1817 * Register | BitsName
1818 * ----------|--------
1819 * CG_CTRL_2 | SRAM_HCLK
1820 *
1821 * @retval State of bit (1 or 0).
1822 */
1823 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
1824 {
1825 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1826 }
1827
1828 /**
1829 * @brief Enabling force to turn off the clock for UART0.
1830 *
1831 * Register | BitsName
1832 * ----------|--------
1833 * PERIPH_GC | UART0_HCLK
1834 *
1835 * @retval None
1836 */
1837 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
1838 {
1839 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_ENABLE;
1840 }
1841
1842 /**
1843 * @brief Disabling force to turn off the clock for UART0.
1844 *
1845 * Register | BitsName
1846 * ----------|--------
1847 * PERIPH_GC | UART0_HCLK
1848 *
1849 * @retval None
1850 */
1851 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
1852 {
1853 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_DISABLE;
1854 }
1855
1856 /**
1857 * @brief Indicate whether the clock for UART0 is forced to close.
1858 *
1859 * Register | BitsName
1860 * ----------|--------
1861 * PERIPH_GC | UART0_HCLK
1862 *
1863 * @retval State of bit (1 or 0).
1864 */
1865 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
1866 {
1867 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1868 }
1869
1870 /**
1871 * @brief Enabling force to turn off the clock for UART1.
1872 *
1873 * Register | BitsName
1874 * ----------|--------
1875 * PERIPH_GC | UART1_HCLK
1876 *
1877 * @retval None
1878 */
1879 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
1880 {
1881 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_ENABLE;
1882 }
1883
1884 /**
1885 * @brief Disabling force to turn off the clock for UART1.
1886 *
1887 * Register | BitsName
1888 * ----------|--------
1889 * PERIPH_GC | UART1_HCLK
1890 *
1891 * @retval None
1892 */
1893 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
1894 {
1895 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_DISABLE;
1896 }
1897
1898 /**
1899 * @brief Indicate whether the clock for UART1 is forced to close.
1900 *
1901 * Register | BitsName
1902 * ----------|--------
1903 * PERIPH_GC | UART1_HCLK
1904 *
1905 * @retval State of bit (1 or 0).
1906 */
1907 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
1908 {
1909 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1910 }
1911
1912 /**
1913 * @brief Enabling force to turn off the clock for UART2.
1914 *
1915 * Register | BitsName
1916 * ----------|--------
1917 * PERIPH_GC | UART2_HCLK
1918 *
1919 * @retval None
1920 */
1921 __STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
1922 {
1923 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_ENABLE;
1924 }
1925
1926 /**
1927 * @brief Disabling force to turn off the clock for UART2.
1928 *
1929 * Register | BitsName
1930 * ----------|--------
1931 * PERIPH_GC | UART2_HCLK
1932 *
1933 * @retval None
1934 */
1935 __STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
1936 {
1937 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_DISABLE;
1938 }
1939
1940 /**
1941 * @brief Indicate whether the clock for UART2 is forced to close.
1942 *
1943 * Register | BitsName
1944 * ----------|--------
1945 * PERIPH_GC | UART2_HCLK
1946 *
1947 * @retval State of bit (1 or 0).
1948 */
1949 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
1950 {
1951 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1952 }
1953
1954 /**
1955 * @brief Enabling force to turn off the clock for UART3.
1956 *
1957 * Register | BitsName
1958 * ----------|--------
1959 * PERIPH_GC | UART3_HCLK
1960 *
1961 * @retval None
1962 */
1963 __STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
1964 {
1965 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_ENABLE;
1966 }
1967
1968 /**
1969 * @brief Disabling force to turn off the clock for UART3.
1970 *
1971 * Register | BitsName
1972 * ----------|--------
1973 * PERIPH_GC | UART3_HCLK
1974 *
1975 * @retval None
1976 */
1977 __STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
1978 {
1979 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_DISABLE;
1980 }
1981
1982 /**
1983 * @brief Indicate whether the clock for UART3 is forced to close.
1984 *
1985 * Register | BitsName
1986 * ----------|--------
1987 * PERIPH_GC | UART3_HCLK
1988 *
1989 * @retval State of bit (1 or 0).
1990 */
1991 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
1992 {
1993 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1994 }
1995
1996 /**
1997 * @brief Enabling force to turn off the clock for I2C0.
1998 *
1999 * Register | BitsName
2000 * ----------|--------
2001 * PERIPH_GC | I2C0_HCLK
2002 *
2003 * @retval None
2004 */
2005 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2006 {
2007 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2008 }
2009
2010 /**
2011 * @brief Disabling force to turn off the clock for I2C0.
2012 *
2013 * Register | BitsName
2014 * ----------|--------
2015 * PERIPH_GC | I2C0_HCLK
2016 *
2017 * @retval None
2018 */
2019 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2020 {
2021 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2022 }
2023
2024 /**
2025 * @brief Indicate whether the clock for I2C0 is forced to close.
2026 *
2027 * Register | BitsName
2028 * ----------|--------
2029 * PERIPH_GC | I2C0_HCLK
2030 *
2031 * @retval State of bit (1 or 0).
2032 */
2033 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2034 {
2035 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2036 }
2037
2038 /**
2039 * @brief Enabling force to turn off the clock for I2C1.
2040 *
2041 * Register | BitsName
2042 * ----------|--------
2043 * PERIPH_GC | I2C1_HCLK
2044 *
2045 * @retval None
2046 */
2047 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2048 {
2049 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2050 }
2051
2052 /**
2053 * @brief Disabling force to turn off the clock for I2C1.
2054 *
2055 * Register | BitsName
2056 * ----------|--------
2057 * PERIPH_GC | I2C1_HCLK
2058 *
2059 * @retval None
2060 */
2061 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2062 {
2063 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2064 }
2065
2066 /**
2067 * @brief Indicate whether the clock for I2C1 is forced to close.
2068 *
2069 * Register | BitsName
2070 * ----------|--------
2071 * PERIPH_GC | I2C1_HCLK
2072 *
2073 * @retval State of bit (1 or 0).
2074 */
2075 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2076 {
2077 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2078 }
2079
2080 /**
2081 * @brief Enabling force to turn off the clock for I2C2.
2082 *
2083 * Register | BitsName
2084 * ----------|--------
2085 * PERIPH_GC | I2C2_HCLK
2086 *
2087 * @retval None
2088 */
2089 __STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
2090 {
2091 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2092 }
2093
2094 /**
2095 * @brief Disabling force to turn off the clock for I2C2.
2096 *
2097 * Register | BitsName
2098 * ----------|--------
2099 * PERIPH_GC | I2C2_HCLK
2100 *
2101 * @retval None
2102 */
2103 __STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
2104 {
2105 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2106 }
2107
2108 /**
2109 * @brief Indicate whether the clock for I2C2 is forced to close.
2110 *
2111 * Register | BitsName
2112 * ----------|--------
2113 * PERIPH_GC | I2C2_HCLK
2114 *
2115 * @retval State of bit (1 or 0).
2116 */
2117 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
2118 {
2119 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2120 }
2121
2122 /**
2123 * @brief Enabling force to turn off the clock for I2C3.
2124 *
2125 * Register | BitsName
2126 * ----------|--------
2127 * PERIPH_GC | I2C3_HCLK
2128 *
2129 * @retval None
2130 */
2131 __STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
2132 {
2133 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_ENABLE;
2134 }
2135
2136 /**
2137 * @brief Disabling force to turn off the clock for I2C3.
2138 *
2139 * Register | BitsName
2140 * ----------|--------
2141 * PERIPH_GC | I2C3_HCLK
2142 *
2143 * @retval None
2144 */
2145 __STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
2146 {
2147 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_DISABLE;
2148 }
2149
2150 /**
2151 * @brief Indicate whether the clock for I2C3 is forced to close.
2152 *
2153 * Register | BitsName
2154 * ----------|--------
2155 * PERIPH_GC | I2C3_HCLK
2156 *
2157 * @retval State of bit (1 or 0).
2158 */
2159 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
2160 {
2161 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2162 }
2163
2164 /**
2165 * @brief Enabling force to turn off the clock for SPIM.
2166 *
2167 * Register | BitsName
2168 * ----------|--------
2169 * PERIPH_GC | SPIM_HCLK
2170 *
2171 * @retval None
2172 */
2173 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2174 {
2175 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_ENABLE;
2176 }
2177
2178 /**
2179 * @brief Disabling force to turn off the clock for SPIM.
2180 *
2181 * Register | BitsName
2182 * ----------|--------
2183 * PERIPH_GC | SPIM_HCLK
2184 *
2185 * @retval None
2186 */
2187 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2188 {
2189 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_DISABLE;
2190 }
2191
2192 /**
2193 * @brief Indicate whether the clock for SPIM is forced to close.
2194 *
2195 * Register | BitsName
2196 * ----------|--------
2197 * PERIPH_GC | SPIM_HCLK
2198 *
2199 * @retval State of bit (1 or 0).
2200 */
2201 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2202 {
2203 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2204 }
2205
2206 /**
2207 * @brief Enabling force to turn off the clock for SPIS.
2208 *
2209 * Register | BitsName
2210 * ----------|--------
2211 * PERIPH_GC | SPIS_HCLK
2212 *
2213 * @retval None
2214 */
2215 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2216 {
2217 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2218 }
2219
2220 /**
2221 * @brief Disabling force to turn off the clock for SPIS.
2222 *
2223 * Register | BitsName
2224 * ----------|--------
2225 * PERIPH_GC | SPIS_HCLK
2226 *
2227 * @retval None
2228 */
2229 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2230 {
2231 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2232 }
2233
2234 /**
2235 * @brief Indicate whether the clock for SPIS is forced to close.
2236 *
2237 * Register | BitsName
2238 * ----------|--------
2239 * PERIPH_GC | SPIS_HCLK
2240 *
2241 * @retval State of bit (1 or 0).
2242 */
2243 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2244 {
2245 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2246 }
2247
2248 /**
2249 * @brief Enabling force to turn off the clock for QSPI0.
2250 *
2251 * Register | BitsName
2252 * ----------|--------
2253 * PERIPH_GC | QSPI0_HCLK
2254 *
2255 * @retval None
2256 */
2257 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2258 {
2259 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2260 }
2261
2262 /**
2263 * @brief Disabling force to turn off the clock for QSPI0.
2264 *
2265 * Register | BitsName
2266 * ----------|--------
2267 * PERIPH_GC | QSPI0_HCLK
2268 *
2269 * @retval None
2270 */
2271 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2272 {
2273 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2274 }
2275
2276 /**
2277 * @brief Indicate whether the clock for QSPI0 is forced to close.
2278 *
2279 * Register | BitsName
2280 * ----------|--------
2281 * PERIPH_GC | QSPI0_HCLK
2282 *
2283 * @retval State of bit (1 or 0).
2284 */
2285 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2286 {
2287 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2288 }
2289
2290 /**
2291 * @brief Enabling force to turn off the clock for QSPI1.
2292 *
2293 * Register | BitsName
2294 * ----------|--------
2295 * PERIPH_GC | QSPI1_HCLK
2296 *
2297 * @retval None
2298 */
2299 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2300 {
2301 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2302 }
2303
2304 /**
2305 * @brief Disabling force to turn off the clock for QSPI1.
2306 *
2307 * Register | BitsName
2308 * ----------|--------
2309 * PERIPH_GC | QSPI1_HCLK
2310 *
2311 * @retval None
2312 */
2313 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2314 {
2315 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2316 }
2317
2318 /**
2319 * @brief Indicate whether the clock for QSPI1 is forced to close.
2320 *
2321 * Register | BitsName
2322 * ----------|--------
2323 * PERIPH_GC | QSPI1_HCLK
2324 *
2325 * @retval State of bit (1 or 0).
2326 */
2327 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2328 {
2329 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2330 }
2331
2332 /**
2333 * @brief Enabling force to turn off the clock for QSPI2.
2334 *
2335 * Register | BitsName
2336 * ----------|--------
2337 * PERIPH_GC | QSPI2_HCLK
2338 *
2339 * @retval None
2340 */
2341 __STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
2342 {
2343 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2344 }
2345
2346 /**
2347 * @brief Disabling force to turn off the clock for QSPI2.
2348 *
2349 * Register | BitsName
2350 * ----------|--------
2351 * PERIPH_GC | QSPI2_HCLK
2352 *
2353 * @retval None
2354 */
2355 __STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
2356 {
2357 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2358 }
2359
2360 /**
2361 * @brief Indicate whether the clock for QSPI2 is forced to close.
2362 *
2363 * Register | BitsName
2364 * ----------|--------
2365 * PERIPH_GC | QSPI2_HCLK
2366 *
2367 * @retval State of bit (1 or 0).
2368 */
2369 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
2370 {
2371 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2372 }
2373
2374
2375 /**
2376 * @brief Enabling force to turn off the clock for I2S master.
2377 *
2378 * Register | BitsName
2379 * ----------|--------
2380 * PERIPH_GC | I2S_HCLK
2381 *
2382 * @retval None
2383 */
2384 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2385 {
2386 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2387 }
2388
2389 /**
2390 * @brief Disabling force to turn off the clock for I2S master.
2391 *
2392 * Register | BitsName
2393 * ----------|--------
2394 * PERIPH_GC | I2S_HCLK
2395 *
2396 * @retval None
2397 */
2398 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2399 {
2400 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2401 }
2402
2403 /**
2404 * @brief Indicate whether the clock for I2S master is forced to close.
2405 *
2406 * Register | BitsName
2407 * ----------|--------
2408 * PERIPH_GC | I2S_HCLK
2409 *
2410 * @retval State of bit (1 or 0).
2411 */
2412 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2413 {
2414 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2415 }
2416
2417 /**
2418 * @brief Enabling force to turn off the clock for I2S slave.
2419 *
2420 * Register | BitsName
2421 * ----------|--------
2422 * PERIPH_GC | I2S_S_PCLK
2423 *
2424 * @retval None
2425 */
2426 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
2427 {
2428 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2429 }
2430
2431 /**
2432 * @brief Disabling force to turn off the clock for I2S slave.
2433 *
2434 * Register | BitsName
2435 * ----------|--------
2436 * PERIPH_GC | I2S_S_PCLK
2437 *
2438 * @retval None
2439 */
2440 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
2441 {
2442 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2443 }
2444
2445 /**
2446 * @brief Indicate whether the clock for I2S slave is forced to close.
2447 *
2448 * Register | BitsName
2449 * ----------|--------
2450 * PERIPH_GC | I2S_S_PCLK
2451 *
2452 * @retval State of bit (1 or 0).
2453 */
2454 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
2455 {
2456 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2457 }
2458
2459 /**
2460 * @brief Enabling force to turn off the clock for DSPI slave.
2461 *
2462 * Register | BitsName
2463 * ----------|--------
2464 * PERIPH_GC | DSPI_PCLK
2465 *
2466 * @retval None
2467 */
2468 __STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
2469 {
2470 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_ENABLE;
2471 }
2472
2473 /**
2474 * @brief Disabling force to turn off the clock for DSPI slave.
2475 *
2476 * Register | BitsName
2477 * ----------|--------
2478 * PERIPH_GC | DSPI_PCLK
2479 *
2480 * @retval None
2481 */
2482 __STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
2483 {
2484 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_DISABLE;
2485 }
2486
2487 /**
2488 * @brief Indicate whether the clock for DSPI is forced to close.
2489 *
2490 * Register | BitsName
2491 * ----------|--------
2492 * PERIPH_GC | DSPI_PCLK
2493 *
2494 * @retval State of bit (1 or 0).
2495 */
2496 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
2497 {
2498 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2499 }
2500
2501 /**
2502 * @brief Enabling force to turn off the clock for PDM slave.
2503 *
2504 * Register | BitsName
2505 * ----------|--------
2506 * PERIPH_GC | PDM_PCLK
2507 *
2508 * @retval None
2509 */
2510 __STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
2511 {
2512 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_ENABLE;
2513 }
2514
2515 /**
2516 * @brief Disabling force to turn off the clock for PDM slave.
2517 *
2518 * Register | BitsName
2519 * ----------|--------
2520 * PERIPH_GC | PDM_PCLK
2521 *
2522 * @retval None
2523 */
2524 __STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
2525 {
2526 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_DISABLE;
2527 }
2528
2529 /**
2530 * @brief Indicate whether the clock for PDM is forced to close.
2531 *
2532 * Register | BitsName
2533 * ----------|--------
2534 * PERIPH_GC | PDM_PCLK
2535 *
2536 * @retval State of bit (1 or 0).
2537 */
2538 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
2539 {
2540 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2541 }
2542
2543 /**
2544 * @brief Enabling force to turn off the div4 clock for security blocks.
2545 *
2546 * Register | BitsName
2547 * ----------|--------
2548 * PERIPH_GC | I2S_HCLK
2549 *
2550 * @retval None
2551 */
2552 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
2553 {
2554 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2555 }
2556
2557 /**
2558 * @brief Disabling force to turn off the div4 clock for security blocks.
2559 *
2560 * Register | BitsName
2561 * ----------|--------
2562 * PERIPH_GC | I2S_HCLK
2563 *
2564 * @retval None
2565 */
2566 __STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
2567 {
2568 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2569 }
2570
2571 /**
2572 * @brief Indicate whether the div4 clock for security blocks is forced to close.
2573 *
2574 * Register | BitsName
2575 * ----------|--------
2576 * PERIPH_GC | I2S_HCLK
2577 *
2578 * @retval State of bit (1 or 0).
2579 */
2580 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
2581 {
2582 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2583 }
2584 /**
2585 * @brief Enabling force to turn off the div4 clock for xf qspi blocks.
2586 *
2587 * Register | BitsName
2588 * ----------|--------
2589 * PERIPH_GC | XQSPI_HCLK
2590 *
2591 * @retval None
2592 */
2593 __STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
2594 {
2595 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2596 }
2597
2598 /**
2599 * @brief Disabling force to turn off the div4 clock for xf qspi blocks.
2600 *
2601 * Register | BitsName
2602 * ----------|--------
2603 * PERIPH_GC | XQSPI_HCLK
2604 *
2605 * @retval None
2606 */
2607 __STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
2608 {
2609 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2610 }
2611
2612 /**
2613 * @brief Indicate whether the div4 clock for xf qspi blocks is forced to close.
2614 *
2615 * Register | BitsName
2616 * ----------|--------
2617 * PERIPH_GC | XQSPI_HCLK
2618 *
2619 * @retval State of bit (1 or 0).
2620 */
2621 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
2622 {
2623 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2624 }
2625
2626 /**
2627 * @brief Enabling force to turn off the clock for PWM0.
2628 *
2629 * Register | BitsName
2630 * ----------|--------
2631 * PERIPH_GC | PWM0_PCLK
2632 *
2633 * @retval None
2634 */
2635 __STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
2636 {
2637 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2638 }
2639
2640 /**
2641 * @brief Disabling force to turn off the clock for PWM0.
2642 *
2643 * Register | BitsName
2644 * ----------|--------
2645 * PERIPH_GC | PWM0_PCLK
2646 *
2647 * @retval None
2648 */
2649 __STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
2650 {
2651 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2652 }
2653
2654 /**
2655 * @brief Indicate whether the clock for PWM0 is forced to close.
2656 *
2657 * Register | BitsName
2658 * ----------|--------
2659 * PERIPH_GC | PWM0_PCLK
2660 *
2661 * @retval State of bit (1 or 0).
2662 */
2663 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
2664 {
2665 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2666 }
2667
2668 /**
2669 * @brief Enabling force to turn off the clock for PWM1.
2670 *
2671 * Register | BitsName
2672 * ----------|--------
2673 * PERIPH_GC | PWM1_PCLK
2674 *
2675 * @retval None
2676 */
2677 __STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
2678 {
2679 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2680 }
2681
2682 /**
2683 * @brief Disabling force to turn off the clock for PWM1.
2684 *
2685 * Register | BitsName
2686 * ----------|--------
2687 * PERIPH_GC | PWM1_PCLK
2688 *
2689 * @retval None
2690 */
2691 __STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
2692 {
2693 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2694 }
2695
2696 /**
2697 * @brief Indicate whether the clock for PWM1 is forced to close.
2698 *
2699 * Register | BitsName
2700 * ----------|--------
2701 * PERIPH_GC | PWM1_PCLK
2702 *
2703 * @retval State of bit (1 or 0).
2704 */
2705 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
2706 {
2707 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2708 }
2709
2710 /**
2711 * @brief Enabling force to turn off the clock for VTTBL.
2712 *
2713 * Register | BitsName
2714 * ----------|--------
2715 * PERIPH_GC | VTTBL_PCLK
2716 *
2717 * @retval None
2718 */
2719 __STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
2720 {
2721 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_ENABLE;
2722 }
2723
2724 /**
2725 * @brief Disabling force to turn off the clock for VTTBL.
2726 *
2727 * Register | BitsName
2728 * ----------|--------
2729 * PERIPH_GC | VTTBL_PCLK
2730 *
2731 * @retval None
2732 */
2733 __STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
2734 {
2735 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_DISABLE;
2736 }
2737
2738 /**
2739 * @brief Indicate whether the clock for VTTBL is forced to close.
2740 *
2741 * Register | BitsName
2742 * ----------|--------
2743 * PERIPH_GC | VTTBL_PCLK
2744 *
2745 * @retval State of bit (1 or 0).
2746 */
2747 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
2748 {
2749 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2750 }
2751
2752 /**
2753 * @brief Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
2754 *
2755 * Register | BitsName
2756 * ---------|--------
2757 * CG_LP_EN | UART_LP_SCLK
2758 * CG_LP_EN | UART_LP_PCLK
2759 * CG_LP_EN | I2S_LP
2760 * CG_LP_EN | SPIM_LP_SCLK
2761 * CG_LP_EN | SPIS_LP_SCLK
2762 * CG_LP_EN | I2C_LP_SCLK
2763 * CG_LP_EN | AHB_BUS_LP
2764 *
2765 * @param clk_mask This parameter can be a combination of the following values:
2766 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
2767 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
2768 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
2769 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
2770 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
2771 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
2772 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
2773 * @retval None
2774 */
2775 __STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
2776 {
2777 WRITE_REG(MCU_RET->MCU_PERIPH_CG_LP_EN, clk_mask);
2778 }
2779
2780 /**
2781 * @brief Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
2782 *
2783 * Register | BitsName
2784 * ---------|--------
2785 * CG_LP_EN | UART_LP_SCLK
2786 * CG_LP_EN | UART_LP_PCLK
2787 * CG_LP_EN | I2S_LP
2788 * CG_LP_EN | SPIM_LP_SCLK
2789 * CG_LP_EN | SPIS_LP_SCLK
2790 * CG_LP_EN | I2C_LP_SCLK
2791 * CG_LP_EN | AHB_BUS_LP
2792 *
2793 * @retval Returned value can be a combination of the following values:
2794 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
2795 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
2796 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
2797 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
2798 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
2799 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
2800 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
2801 */
2802 __STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
2803 {
2804 return READ_REG(MCU_RET->MCU_PERIPH_CG_LP_EN);
2805 }
2806
2807 /**
2808 * @brief Enable uart sclk low-power feature
2809 *
2810 * Register | BitsName
2811 * ---------|--------
2812 * CG_LP_EN | UART_LP_SCLK
2813 *
2814 * @retval None
2815 */
2816 __STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
2817 {
2818 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2819 }
2820
2821 /**
2822 * @brief Disable uart sclk low-power feature
2823 *
2824 * Register | BitsName
2825 * ---------|--------
2826 * CG_LP_EN | UART_LP_SCLK
2827 *
2828 * @retval None
2829 */
2830 __STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
2831 {
2832 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
2833 }
2834
2835 /**
2836 * @brief Indicate whether the uart sclk low-power is enabled.
2837 *
2838 * Register | BitsName
2839 * ---------|--------
2840 * CG_LP_EN | UART_LP_SCLK
2841 *
2842 * @retval State of bit (1 or 0).
2843 */
2844 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
2845 {
2846 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
2847 }
2848
2849 /**
2850 * @brief Enable uart pclk low-power feature
2851 *
2852 * Register | BitsName
2853 * ---------|--------
2854 * CG_LP_EN | UART_LP_PCLK
2855 *
2856 * @retval None
2857 */
2858 __STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
2859 {
2860 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2861 }
2862
2863 /**
2864 * @brief Disable uart pclk low-power feature
2865 *
2866 * Register | BitsName
2867 * ---------|--------
2868 * CG_LP_EN | UART_LP_PCLK
2869 *
2870 * @retval None
2871 */
2872 __STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
2873 {
2874 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_DISABLE;
2875 }
2876
2877 /**
2878 * @brief Indicate whether the uart pclk low-power is enabled.
2879 *
2880 * Register | BitsName
2881 * ---------|--------
2882 * CG_LP_EN | UART_LP_PCLK
2883 *
2884 * @retval State of bit (1 or 0).
2885 */
2886 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
2887 {
2888 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
2889 }
2890
2891 /**
2892 * @brief Enable i2s low-power feature
2893 *
2894 * Register | BitsName
2895 * ---------|--------
2896 * CG_LP_EN | I2S_LP
2897 *
2898 * @retval None
2899 */
2900 __STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
2901 {
2902 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_ENABLE;
2903 }
2904
2905 /**
2906 * @brief Disable i2s low-power feature
2907 *
2908 * Register | BitsName
2909 * ---------|--------
2910 * CG_LP_EN | I2S_LP
2911 *
2912 * @retval None
2913 */
2914 __STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
2915 {
2916 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_DISABLE;
2917 }
2918
2919 /**
2920 * @brief Indicate whether the i2s low-power is enabled.
2921 *
2922 * Register | BitsName
2923 * ---------|--------
2924 * CG_LP_EN | I2S_LP
2925 *
2926 * @retval State of bit (1 or 0).
2927 */
2928 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
2929 {
2930 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
2931 }
2932
2933 /**
2934 * @brief Enable spim sclk low-power feature
2935 *
2936 * Register | BitsName
2937 * ---------|--------
2938 * CG_LP_EN | SPIM_LP_SCLK
2939 *
2940 * @retval None
2941 */
2942 __STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
2943 {
2944 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2945 }
2946
2947 /**
2948 * @brief Disable spim sclk low-power feature
2949 *
2950 * Register | BitsName
2951 * ---------|--------
2952 * CG_LP_EN | SPIM_LP_SCLK
2953 *
2954 * @retval None
2955 */
2956 __STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
2957 {
2958 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
2959 }
2960
2961 /**
2962 * @brief Indicate whether the spim sclk low-power is enabled.
2963 *
2964 * Register | BitsName
2965 * ---------|--------
2966 * CG_LP_EN | SPIM_LP_SCLK
2967 *
2968 * @retval State of bit (1 or 0).
2969 */
2970 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
2971 {
2972 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
2973 }
2974
2975 /**
2976 * @brief Enable spis sclk low-power feature
2977 *
2978 * Register | BitsName
2979 * ---------|--------
2980 * CG_LP_EN | SPIS_LP_SCLK
2981 *
2982 * @retval None
2983 */
2984 __STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
2985 {
2986 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2987 }
2988
2989 /**
2990 * @brief Disable spis sclk low-power feature
2991 *
2992 * Register | BitsName
2993 * ---------|--------
2994 * CG_LP_EN | SPIS_LP_SCLK
2995 *
2996 * @retval None
2997 */
2998 __STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
2999 {
3000 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3001 }
3002
3003 /**
3004 * @brief Indicate whether the spis sclk low-power is enabled.
3005 *
3006 * Register | BitsName
3007 * ---------|--------
3008 * CG_LP_EN | SPIS_LP_SCLK
3009 *
3010 * @retval State of bit (1 or 0).
3011 */
3012 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
3013 {
3014 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3015 }
3016
3017 /**
3018 * @brief Enable i2c sclk low-power feature
3019 *
3020 * Register | BitsName
3021 * ---------|--------
3022 * CG_LP_EN | I2C_LP_SCLK
3023 *
3024 * @retval None
3025 */
3026 __STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
3027 {
3028 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3029 }
3030
3031 /**
3032 * @brief Disable i2c sclk low-power feature
3033 *
3034 * Register | BitsName
3035 * ---------|--------
3036 * CG_LP_EN | I2C_LP_SCLK
3037 *
3038 * @retval None
3039 */
3040 __STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
3041 {
3042 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3043 }
3044
3045 /**
3046 * @brief Indicate whether the i2c sclk low-power is enabled.
3047 *
3048 * Register | BitsName
3049 * ---------|--------
3050 * CG_LP_EN | I2C_LP_SCLK
3051 *
3052 * @retval State of bit (1 or 0).
3053 */
3054 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
3055 {
3056 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3057 }
3058
3059 /**
3060 * @brief Enable ahb bus low-power feature
3061 *
3062 * Register | BitsName
3063 * ---------|--------
3064 * CG_LP_EN | AHB_BUS_LP
3065 *
3066 * @retval None
3067 */
3068 __STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
3069 {
3070 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3071 }
3072
3073 /**
3074 * @brief Disable ahb bus low-power feature
3075 *
3076 * Register | BitsName
3077 * ---------|--------
3078 * CG_LP_EN | AHB_BUS_LP
3079 *
3080 * @retval None
3081 */
3082 __STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
3083 {
3084 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3085 }
3086
3087 /**
3088 * @brief Indicate whether the ahb bus low-power is enabled.
3089 *
3090 * Register | BitsName
3091 * ---------|--------
3092 * CG_LP_EN | AHB_BUS_LP
3093 *
3094 * @retval State of bit (1 or 0).
3095 */
3096 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
3097 {
3098 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3099 }
3100
3101 /**
3102 * @brief Enable QSPIM low-power feature
3103 *
3104 * Register | BitsName
3105 * ---------|--------
3106 * CG_LP_EN | QSPIM_LP
3107 *
3108 * @retval None
3109 */
3110 __STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
3111 {
3112 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_ENABLE;
3113 }
3114
3115 /**
3116 * @brief Disable QSPIM low-power feature
3117 *
3118 * Register | BitsName
3119 * ---------|--------
3120 * CG_LP_EN | QSPIM_LP
3121 *
3122 * @retval None
3123 */
3124 __STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
3125 {
3126 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_DISABLE;
3127 }
3128
3129 /**
3130 * @brief Indicate whether the QSPIM low-power is enabled.
3131 *
3132 * Register | BitsName
3133 * ---------|--------
3134 * CG_LP_EN | QSPIM_LP
3135 *
3136 * @retval State of bit (1 or 0).
3137 */
3138 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
3139 {
3140 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) == (CGC_CLOCK_ENABLE));
3141 }
3142
3143 /**
3144 * @brief Enable AHB2APB bus low-power feature
3145 *
3146 * Register | BitsName
3147 * ---------|--------
3148 * CG_LP_EN | AHB2APB_BUS_LP
3149 *
3150 * @retval None
3151 */
3152 __STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
3153 {
3154 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3155 }
3156
3157 /**
3158 * @brief Disable AHB2APB bus low-power feature
3159 *
3160 * Register | BitsName
3161 * ---------|--------
3162 * CG_LP_EN | AHB2APB_BUS_LP
3163 *
3164 * @retval None
3165 */
3166 __STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
3167 {
3168 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3169 }
3170
3171 /**
3172 * @brief Indicate whether the AHB2APB bus low-power is enabled.
3173 *
3174 * Register | BitsName
3175 * ---------|--------
3176 * CG_LP_EN | AHB2APB_BUS_LP
3177 *
3178 * @retval State of bit (1 or 0).
3179 */
3180 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
3181 {
3182 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3183 }
3184
3185 /**
3186 * @brief Enable ahb bus low-power feature
3187 *
3188 * Register | BitsName
3189 * ---------|--------
3190 * CG_LP_EN | AHB_BUS_LP
3191 *
3192 * @retval None
3193 */
3194 __STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
3195 {
3196 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3197 }
3198
3199 /**
3200 * @brief Disable ahb bus low-power feature
3201 *
3202 * Register | BitsName
3203 * ---------|--------
3204 * CG_LP_EN | AHB_BUS_LP
3205 *
3206 * @retval None
3207 */
3208 __STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
3209 {
3210 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3211 }
3212
3213 /**
3214 * @brief Indicate whether the ahb bus low-power is enabled.
3215 *
3216 * Register | BitsName
3217 * ---------|--------
3218 * CG_LP_EN | AHB_BUS_LP
3219 *
3220 * @retval State of bit (1 or 0).
3221 */
3222 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
3223 {
3224 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3225 }
3226
3227 /**
3228 * @brief Enable turn UART0 off during WFI/WFE
3229 *
3230 * Register | BitsName
3231 * ---------|--------
3232 * CLK_SLP_OFF | UART0_SLP
3233 *
3234 * @retval None
3235 */
3236 __STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
3237 {
3238 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_ENABLE;
3239 }
3240
3241 /**
3242 * @brief Disable turn UART0 off during WFI/WFE
3243 *
3244 * Register | BitsName
3245 * ---------|--------
3246 * CLK_SLP_OFF | UART0_SLP
3247 *
3248 * @retval None
3249 */
3250 __STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
3251 {
3252 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_DISABLE;
3253 }
3254
3255 /**
3256 * @brief Indicate whether turn UART0 off during WFI/WFE is enabled.
3257 *
3258 * Register | BitsName
3259 * ---------|--------
3260 * CLK_SLP_OFF | UART0_SLP
3261 *
3262 * @retval State of bit (1 or 0).
3263 */
3264 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
3265 {
3266 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) == (CGC_CLOCK_ENABLE));
3267 }
3268
3269 /**
3270 * @brief Enable turn UART1 off during WFI/WFE
3271 *
3272 * Register | BitsName
3273 * ---------|--------
3274 * CLK_SLP_OFF | UART1_SLP
3275 *
3276 * @retval None
3277 */
3278 __STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
3279 {
3280 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_ENABLE;
3281 }
3282
3283 /**
3284 * @brief Disable turn UART1 off during WFI/WFE
3285 *
3286 * Register | BitsName
3287 * ---------|--------
3288 * CLK_SLP_OFF | UART1_SLP
3289 *
3290 * @retval None
3291 */
3292 __STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
3293 {
3294 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_DISABLE;
3295 }
3296
3297 /**
3298 * @brief Indicate whether turn UART1 off during WFI/WFE is enabled.
3299 *
3300 * Register | BitsName
3301 * ---------|--------
3302 * CLK_SLP_OFF | UART1_SLP
3303 *
3304 * @retval State of bit (1 or 0).
3305 */
3306 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
3307 {
3308 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) == (CGC_CLOCK_ENABLE));
3309 }
3310
3311 /**
3312 * @brief Enable turn UART2 off during WFI/WFE
3313 *
3314 * Register | BitsName
3315 * ---------|--------
3316 * CLK_SLP_OFF | UART2_SLP
3317 *
3318 * @retval None
3319 */
3320 __STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
3321 {
3322 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_ENABLE;
3323 }
3324
3325 /**
3326 * @brief Disable turn UART2 off during WFI/WFE
3327 *
3328 * Register | BitsName
3329 * ---------|--------
3330 * CLK_SLP_OFF | UART2_SLP
3331 *
3332 * @retval None
3333 */
3334 __STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
3335 {
3336 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_DISABLE;
3337 }
3338
3339 /**
3340 * @brief Indicate whether turn UART2 off during WFI/WFE is enabled.
3341 *
3342 * Register | BitsName
3343 * ---------|--------
3344 * CLK_SLP_OFF | UART2_SLP
3345 *
3346 * @retval State of bit (1 or 0).
3347 */
3348 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
3349 {
3350 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) == (CGC_CLOCK_ENABLE));
3351 }
3352
3353 /**
3354 * @brief Enable turn UART3 off during WFI/WFE
3355 *
3356 * Register | BitsName
3357 * ---------|--------
3358 * CLK_SLP_OFF | UART3_SLP
3359 *
3360 * @retval None
3361 */
3362 __STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
3363 {
3364 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_ENABLE;
3365 }
3366
3367 /**
3368 * @brief Disable turn UART3 off during WFI/WFE
3369 *
3370 * Register | BitsName
3371 * ---------|--------
3372 * CLK_SLP_OFF | UART3_SLP
3373 *
3374 * @retval None
3375 */
3376 __STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
3377 {
3378 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_DISABLE;
3379 }
3380
3381 /**
3382 * @brief Indicate whether turn UART3 off during WFI/WFE is enabled.
3383 *
3384 * Register | BitsName
3385 * ---------|--------
3386 * CLK_SLP_OFF | UART3_SLP
3387 *
3388 * @retval State of bit (1 or 0).
3389 */
3390 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
3391 {
3392 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) == (CGC_CLOCK_ENABLE));
3393 }
3394
3395 /**
3396 * @brief Enable turn I2C0 off during WFI/WFE
3397 *
3398 * Register | BitsName
3399 * ---------|--------
3400 * CLK_SLP_OFF | I2C0_SLP
3401 *
3402 * @retval None
3403 */
3404 __STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
3405 {
3406 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_ENABLE;
3407 }
3408
3409 /**
3410 * @brief Disable turn I2C0 off during WFI/WFE
3411 *
3412 * Register | BitsName
3413 * ---------|--------
3414 * CLK_SLP_OFF | I2C0_SLP
3415 *
3416 * @retval None
3417 */
3418 __STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
3419 {
3420 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_DISABLE;
3421 }
3422
3423 /**
3424 * @brief Indicate whether turn I2C0 off during WFI/WFE is enabled.
3425 *
3426 * Register | BitsName
3427 * ---------|--------
3428 * CLK_SLP_OFF | I2C0_SLP
3429 *
3430 * @retval State of bit (1 or 0).
3431 */
3432 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
3433 {
3434 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) == (CGC_CLOCK_ENABLE));
3435 }
3436
3437 /**
3438 * @brief Enable turn I2C1 off during WFI/WFE
3439 *
3440 * Register | BitsName
3441 * ---------|--------
3442 * CLK_SLP_OFF | I2C1_SLP
3443 *
3444 * @retval None
3445 */
3446 __STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
3447 {
3448 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_ENABLE;
3449 }
3450
3451 /**
3452 * @brief Disable turn I2C1 off during WFI/WFE
3453 *
3454 * Register | BitsName
3455 * ---------|--------
3456 * CLK_SLP_OFF | I2C1_SLP
3457 *
3458 * @retval None
3459 */
3460 __STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
3461 {
3462 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_DISABLE;
3463 }
3464
3465 /**
3466 * @brief Indicate whether turn I2C1 off during WFI/WFE is enabled.
3467 *
3468 * Register | BitsName
3469 * ---------|--------
3470 * CLK_SLP_OFF | I2C1_SLP
3471 *
3472 * @retval State of bit (1 or 0).
3473 */
3474 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
3475 {
3476 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) == (CGC_CLOCK_ENABLE));
3477 }
3478
3479 /**
3480 * @brief Enable turn I2C2 off during WFI/WFE
3481 *
3482 * Register | BitsName
3483 * ---------|--------
3484 * CLK_SLP_OFF | I2C2_SLP
3485 *
3486 * @retval None
3487 */
3488 __STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
3489 {
3490 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_ENABLE;
3491 }
3492
3493 /**
3494 * @brief Disable turn I2C2 off during WFI/WFE
3495 *
3496 * Register | BitsName
3497 * ---------|--------
3498 * CLK_SLP_OFF | I2C2_SLP
3499 *
3500 * @retval None
3501 */
3502 __STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
3503 {
3504 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_DISABLE;
3505 }
3506
3507 /**
3508 * @brief Indicate whether turn I2C2 off during WFI/WFE is enabled.
3509 *
3510 * Register | BitsName
3511 * ---------|--------
3512 * CLK_SLP_OFF | I2C2_SLP
3513 *
3514 * @retval State of bit (1 or 0).
3515 */
3516 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
3517 {
3518 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) == (CGC_CLOCK_ENABLE));
3519 }
3520
3521 /**
3522 * @brief Enable turn I2C3 off during WFI/WFE
3523 *
3524 * Register | BitsName
3525 * ---------|--------
3526 * CLK_SLP_OFF | I2C3_SLP
3527 *
3528 * @retval None
3529 */
3530 __STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
3531 {
3532 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_ENABLE;
3533 }
3534
3535 /**
3536 * @brief Disable turn I2C3 off during WFI/WFE
3537 *
3538 * Register | BitsName
3539 * ---------|--------
3540 * CLK_SLP_OFF | I2C3_SLP
3541 *
3542 * @retval None
3543 */
3544 __STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
3545 {
3546 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_DISABLE;
3547 }
3548
3549 /**
3550 * @brief Indicate whether turn I2C3 off during WFI/WFE is enabled.
3551 *
3552 * Register | BitsName
3553 * ---------|--------
3554 * CLK_SLP_OFF | I2C3_SLP
3555 *
3556 * @retval State of bit (1 or 0).
3557 */
3558 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
3559 {
3560 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) == (CGC_CLOCK_ENABLE));
3561 }
3562
3563 /**
3564 * @brief Enable turn I2S_M off during WFI/WFE
3565 *
3566 * Register | BitsName
3567 * ---------|--------
3568 * CLK_SLP_OFF | I2SM_SLP
3569 *
3570 * @retval None
3571 */
3572 __STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
3573 {
3574 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_ENABLE;
3575 }
3576
3577 /**
3578 * @brief Disable turn I2S_M off during WFI/WFE
3579 *
3580 * Register | BitsName
3581 * ---------|--------
3582 * CLK_SLP_OFF | I2SM_SLP
3583 *
3584 * @retval None
3585 */
3586 __STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
3587 {
3588 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_DISABLE;
3589 }
3590
3591 /**
3592 * @brief Indicate whether turn I2S_M off during WFI/WFE is enabled.
3593 *
3594 * Register | BitsName
3595 * ---------|--------
3596 * CLK_SLP_OFF | I2SM_SLP
3597 *
3598 * @retval State of bit (1 or 0).
3599 */
3600 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
3601 {
3602 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) == (CGC_CLOCK_ENABLE));
3603 }
3604
3605 /**
3606 * @brief Enable turn I2S_S off during WFI/WFE
3607 *
3608 * Register | BitsName
3609 * ---------|--------
3610 * CLK_SLP_OFF | I2SS_SLP
3611 *
3612 * @retval None
3613 */
3614 __STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
3615 {
3616 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_ENABLE;
3617 }
3618
3619 /**
3620 * @brief Disable turn I2S_S off during WFI/WFE
3621 *
3622 * Register | BitsName
3623 * ---------|--------
3624 * CLK_SLP_OFF | I2SS_SLP
3625 *
3626 * @retval None
3627 */
3628 __STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
3629 {
3630 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_DISABLE;
3631 }
3632
3633 /**
3634 * @brief Indicate whether turn I2S_S off during WFI/WFE is enabled.
3635 *
3636 * Register | BitsName
3637 * ---------|--------
3638 * CLK_SLP_OFF | I2SS_SLP
3639 *
3640 * @retval State of bit (1 or 0).
3641 */
3642 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
3643 {
3644 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) == (CGC_CLOCK_ENABLE));
3645 }
3646
3647 /**
3648 * @brief Enable turn SPI_M off during WFI/WFE
3649 *
3650 * Register | BitsName
3651 * ---------|--------
3652 * CLK_SLP_OFF | SPIM_SLP
3653 *
3654 * @retval None
3655 */
3656 __STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
3657 {
3658 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_ENABLE;
3659 }
3660
3661 /**
3662 * @brief Disable turn SPI_M off during WFI/WFE
3663 *
3664 * Register | BitsName
3665 * ---------|--------
3666 * CLK_SLP_OFF | SPIM_SLP
3667 *
3668 * @retval None
3669 */
3670 __STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
3671 {
3672 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_DISABLE;
3673 }
3674
3675 /**
3676 * @brief Indicate whether turn SPI_M off during WFI/WFE is enabled.
3677 *
3678 * Register | BitsName
3679 * ---------|--------
3680 * CLK_SLP_OFF | SPIM_SLP
3681 *
3682 * @retval State of bit (1 or 0).
3683 */
3684 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
3685 {
3686 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) == (CGC_CLOCK_ENABLE));
3687 }
3688
3689 /**
3690 * @brief Enable turn SPI_S off during WFI/WFE
3691 *
3692 * Register | BitsName
3693 * ---------|--------
3694 * CLK_SLP_OFF | SPIS_SLP
3695 *
3696 * @retval None
3697 */
3698 __STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
3699 {
3700 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_ENABLE;
3701 }
3702
3703 /**
3704 * @brief Disable turn SPI_S off during WFI/WFE
3705 *
3706 * Register | BitsName
3707 * ---------|--------
3708 * CLK_SLP_OFF | SPIS_SLP
3709 *
3710 * @retval None
3711 */
3712 __STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
3713 {
3714 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_DISABLE;
3715 }
3716
3717 /**
3718 * @brief Indicate whether turn SPI_S off during WFI/WFE is enabled.
3719 *
3720 * Register | BitsName
3721 * ---------|--------
3722 * CLK_SLP_OFF | SPIS_SLP
3723 *
3724 * @retval State of bit (1 or 0).
3725 */
3726 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
3727 {
3728 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) == (CGC_CLOCK_ENABLE));
3729 }
3730
3731 /**
3732 * @brief Enable turn pwm0 off during WFI/WFE
3733 *
3734 * Register | BitsName
3735 * ---------|--------
3736 * CLK_SLP_OFF | PWM0_SLP
3737 *
3738 * @retval None
3739 */
3740 __STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
3741 {
3742 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_ENABLE;
3743 }
3744
3745 /**
3746 * @brief Disable turn pwm0 off during WFI/WFE
3747 *
3748 * Register | BitsName
3749 * ---------|--------
3750 * CLK_SLP_OFF | PWM0_SLP
3751 *
3752 * @retval None
3753 */
3754 __STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
3755 {
3756 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_DISABLE;
3757 }
3758
3759 /**
3760 * @brief Indicate whether turn pwm0 off during WFI/WFE is enabled.
3761 *
3762 * Register | BitsName
3763 * ---------|--------
3764 * CLK_SLP_OFF | PWM0_SLP
3765 *
3766 * @retval State of bit (1 or 0).
3767 */
3768 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
3769 {
3770 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) == (CGC_CLOCK_ENABLE));
3771 }
3772
3773 /**
3774 * @brief Enable turn pwm1 off during WFI/WFE
3775 *
3776 * Register | BitsName
3777 * ---------|--------
3778 * CLK_SLP_OFF | PWM1_SLP
3779 *
3780 * @retval None
3781 */
3782 __STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
3783 {
3784 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_ENABLE;
3785 }
3786
3787 /**
3788 * @brief Disable turn pwm1 off during WFI/WFE
3789 *
3790 * Register | BitsName
3791 * ---------|--------
3792 * CLK_SLP_OFF | PWM1_SLP
3793 *
3794 * @retval None
3795 */
3796 __STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
3797 {
3798 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_DISABLE;
3799 }
3800
3801 /**
3802 * @brief Indicate whether turn pwm1 off during WFI/WFE is enabled.
3803 *
3804 * Register | BitsName
3805 * ---------|--------
3806 * CLK_SLP_OFF | PWM1_SLP
3807 *
3808 * @retval State of bit (1 or 0).
3809 */
3810 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
3811 {
3812 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) == (CGC_CLOCK_ENABLE));
3813 }
3814
3815 /**
3816 * @brief Enable turn QSPIM0 off during WFI/WFE
3817 *
3818 * Register | BitsName
3819 * ---------|--------
3820 * CLK_SLP_OFF | QSPIM0_SLP
3821 *
3822 * @retval None
3823 */
3824 __STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
3825 {
3826 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_ENABLE;
3827 }
3828
3829 /**
3830 * @brief Disable turn QSPIM0 off during WFI/WFE
3831 *
3832 * Register | BitsName
3833 * ---------|--------
3834 * CLK_SLP_OFF | QSPIM0_SLP
3835 *
3836 * @retval None
3837 */
3838 __STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
3839 {
3840 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_DISABLE;
3841 }
3842
3843 /**
3844 * @brief Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
3845 *
3846 * Register | BitsName
3847 * ---------|--------
3848 * CLK_SLP_OFF | QSPIM0_SLP
3849 *
3850 * @retval State of bit (1 or 0).
3851 */
3852 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
3853 {
3854 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) == (CGC_CLOCK_ENABLE));
3855 }
3856
3857 /**
3858 * @brief Enable turn QSPIM1 off during WFI/WFE
3859 *
3860 * Register | BitsName
3861 * ---------|--------
3862 * CLK_SLP_OFF | QSPIM1_SLP
3863 *
3864 * @retval None
3865 */
3866 __STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
3867 {
3868 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_ENABLE;
3869 }
3870
3871 /**
3872 * @brief Disable turn QSPIM1 off during WFI/WFE
3873 *
3874 * Register | BitsName
3875 * ---------|--------
3876 * CLK_SLP_OFF | QSPIM1_SLP
3877 *
3878 * @retval None
3879 */
3880 __STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
3881 {
3882 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_DISABLE;
3883 }
3884
3885 /**
3886 * @brief Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
3887 *
3888 * Register | BitsName
3889 * ---------|--------
3890 * CLK_SLP_OFF | QSPIM1_SLP
3891 *
3892 * @retval State of bit (1 or 0).
3893 */
3894 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
3895 {
3896 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) == (CGC_CLOCK_ENABLE));
3897 }
3898
3899 /**
3900 * @brief Enable turn QSPIM2 off during WFI/WFE
3901 *
3902 * Register | BitsName
3903 * ---------|--------
3904 * CLK_SLP_OFF | QSPIM2_SLP
3905 *
3906 * @retval None
3907 */
3908 __STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
3909 {
3910 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_ENABLE;
3911 }
3912
3913 /**
3914 * @brief Disable turn QSPIM2 off during WFI/WFE
3915 *
3916 * Register | BitsName
3917 * ---------|--------
3918 * CLK_SLP_OFF | QSPIM2_SLP
3919 *
3920 * @retval None
3921 */
3922 __STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
3923 {
3924 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_DISABLE;
3925 }
3926
3927 /**
3928 * @brief Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
3929 *
3930 * Register | BitsName
3931 * ---------|--------
3932 * CLK_SLP_OFF | QSPIM2_SLP
3933 *
3934 * @retval State of bit (1 or 0).
3935 */
3936 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
3937 {
3938 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) == (CGC_CLOCK_ENABLE));
3939 }
3940
3941 /**
3942 * @brief Enable turn DSPI off during WFI/WFE
3943 *
3944 * Register | BitsName
3945 * ---------|--------
3946 * CLK_SLP_OFF | DSPI_SLP
3947 *
3948 * @retval None
3949 */
3950 __STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
3951 {
3952 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_ENABLE;
3953 }
3954
3955 /**
3956 * @brief Disable turn DSPI off during WFI/WFE
3957 *
3958 * Register | BitsName
3959 * ---------|--------
3960 * CLK_SLP_OFF | DSPI_SLP
3961 *
3962 * @retval None
3963 */
3964 __STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
3965 {
3966 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_DISABLE;
3967 }
3968
3969 /**
3970 * @brief Indicate whether turn DSPI off during WFI/WFE is enabled.
3971 *
3972 * Register | BitsName
3973 * ---------|--------
3974 * CLK_SLP_OFF | DSPI_SLP
3975 *
3976 * @retval State of bit (1 or 0).
3977 */
3978 __STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
3979 {
3980 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) == (CGC_CLOCK_ENABLE));
3981 }
3982
3983 /**
3984 * @brief Enable turn PDM off during WFI/WFE
3985 *
3986 * Register | BitsName
3987 * ---------|--------
3988 * CLK_SLP_OFF | PDM_SLP
3989 *
3990 * @retval None
3991 */
3992 __STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
3993 {
3994 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_ENABLE;
3995 }
3996
3997 /**
3998 * @brief Disable turn PDM off during WFI/WFE
3999 *
4000 * Register | BitsName
4001 * ---------|--------
4002 * CLK_SLP_OFF | PDM_SLP
4003 *
4004 * @retval None
4005 */
4006 __STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
4007 {
4008 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_DISABLE;
4009 }
4010
4011 /**
4012 * @brief Indicate whether turn PDM off during WFI/WFE is enabled.
4013 *
4014 * Register | BitsName
4015 * ---------|--------
4016 * CLK_SLP_OFF | PDM_SLP
4017 *
4018 * @retval State of bit (1 or 0).
4019 */
4020 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
4021 {
4022 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) == (CGC_CLOCK_ENABLE));
4023 }
4024
4025 /**
4026 * @brief Individual block's clock control inside security system which was forced to turn off (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4027 *
4028 * Register | BitsName
4029 * ----------|--------
4030 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4031 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4032 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4033 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4034 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4035 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4036 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4037 *
4038 * @param clk_mask This parameter can be a combination of the following values:
4039 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4040 * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4041 * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4042 * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4043 * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4044 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4045 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4046 * @retval None
4047 */
4048 __STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
4049 {
4050 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
4051 }
4052
4053 /**
4054 * @brief Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4055 *
4056 * Register | BitsName
4057 * ----------|--------
4058 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4059 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4060 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4061 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4062 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4063 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4064 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4065 *
4066 * @retval Returned value can be a combination of the following values:
4067 * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4068 * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4069 * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4070 * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4071 * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4072 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4073 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4074 */
4075 __STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
4076 {
4077 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
4078 }
4079
4080 /**
4081 * @brief Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4082 *
4083 * Register | BitsName
4084 * ----------|--------
4085 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4086 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4087 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4088 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4089 *
4090 * @param clk_mask This parameter can be a combination of the following values:
4091 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4092 * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4093 * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4094 * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4095 * @retval None
4096 */
4097 __STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
4098 {
4099 MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
4100 }
4101
4102 /**
4103 * @brief Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4104 *
4105 * Register | BitsName
4106 * ----------|--------
4107 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4108 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4109 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4110 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4111 *
4112 * @retval Returned value can be a combination of the following values:
4113 * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4114 * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4115 * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4116 * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4117 */
4118 __STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
4119 {
4120 return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
4121 }
4122
4123 /**
4124 * @brief Enabling force to turn off the clock for AES.
4125 *
4126 * Register | BitsName
4127 * ----------|--------
4128 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4129 *
4130 * @retval None
4131 */
4132 __STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
4133 {
4134 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4135 }
4136
4137 /**
4138 * @brief Disabling force to turn off the clock for AES.
4139 *
4140 * Register | BitsName
4141 * ----------|--------
4142 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4143 *
4144 * @retval None
4145 */
4146 __STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
4147 {
4148 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4149 }
4150
4151 /**
4152 * @brief Indicate whether the clock for AES is forced to close.
4153 *
4154 * Register | BitsName
4155 * ----------|--------
4156 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4157 *
4158 * @retval State of bit (1 or 0).
4159 */
4160 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
4161 {
4162 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4163 }
4164
4165 /**
4166 * @brief Enabling force to turn off the clock for HMAC.
4167 *
4168 * Register | BitsName
4169 * ----------|--------
4170 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4171 *
4172 * @retval None
4173 */
4174 __STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
4175 {
4176 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4177 }
4178
4179 /**
4180 * @brief Disabling force to turn off the clock for HMAC.
4181 *
4182 * Register | BitsName
4183 * ----------|--------
4184 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4185 *
4186 * @retval None
4187 */
4188 __STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
4189 {
4190 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4191 }
4192
4193 /**
4194 * @brief Indicate whether the clock for HMAC is forced to close.
4195 *
4196 * Register | BitsName
4197 * ----------|--------
4198 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4199 *
4200 * @retval State of bit (1 or 0).
4201 */
4202 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
4203 {
4204 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4205 }
4206
4207 /**
4208 * @brief Enabling force to turn off the clock for PKC.
4209 *
4210 * Register | BitsName
4211 * ----------|--------
4212 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4213 *
4214 * @retval None
4215 */
4216 __STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
4217 {
4218 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4219 }
4220
4221 /**
4222 * @brief Disabling force to turn off the clock for PKC.
4223 *
4224 * Register | BitsName
4225 * ----------|--------
4226 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4227 *
4228 * @retval None
4229 */
4230 __STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
4231 {
4232 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4233 }
4234
4235 /**
4236 * @brief Indicate whether the clock for PKC is forced to close.
4237 *
4238 * Register | BitsName
4239 * ----------|--------
4240 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4241 *
4242 * @retval State of bit (1 or 0).
4243 */
4244 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
4245 {
4246 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4247 }
4248
4249 /**
4250 * @brief Enabling force to turn off the clock for PRESENT.
4251 *
4252 * Register | BitsName
4253 * ----------|--------
4254 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4255 *
4256 * @retval None
4257 */
4258 __STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
4259 {
4260 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4261 }
4262
4263 /**
4264 * @brief Disabling force to turn off the clock for PRESENT.
4265 *
4266 * Register | BitsName
4267 * ----------|--------
4268 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4269 *
4270 * @retval None
4271 */
4272 __STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
4273 {
4274 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4275 }
4276
4277 /**
4278 * @brief Indicate whether the clock for PRESENT is forced to close.
4279 *
4280 * Register | BitsName
4281 * ----------|--------
4282 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4283 *
4284 * @retval State of bit (1 or 0).
4285 */
4286 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
4287 {
4288 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4289 }
4290
4291 /**
4292 * @brief Enabling force to turn off the clock for RAMKEY.
4293 *
4294 * Register | BitsName
4295 * ----------|--------
4296 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4297 *
4298 * @retval None
4299 */
4300 __STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
4301 {
4302 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4303 }
4304
4305 /**
4306 * @brief Disabling force to turn off the clock for RAMKEY.
4307 *
4308 * Register | BitsName
4309 * ----------|--------
4310 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4311 *
4312 * @retval None
4313 */
4314 __STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
4315 {
4316 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4317 }
4318
4319 /**
4320 * @brief Indicate whether the clock for RAMKEY is forced to close.
4321 *
4322 * Register | BitsName
4323 * ----------|--------
4324 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4325 *
4326 * @retval State of bit (1 or 0).
4327 */
4328 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
4329 {
4330 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4331 }
4332
4333
4334 /**
4335 * @brief Enabling force to turn off the clock for RNG.
4336 *
4337 * Register | BitsName
4338 * ----------|--------
4339 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4340 *
4341 * @retval None
4342 */
4343 __STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
4344 {
4345 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4346 }
4347
4348 /**
4349 * @brief Disabling force to turn off the clock for RNG.
4350 *
4351 * Register | BitsName
4352 * ----------|--------
4353 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4354 *
4355 * @retval None
4356 */
4357 __STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
4358 {
4359 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4360 }
4361
4362 /**
4363 * @brief Indicate whether the clock for RNG is forced to close.
4364 *
4365 * Register | BitsName
4366 * ----------|--------
4367 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4368 *
4369 * @retval State of bit (1 or 0).
4370 */
4371 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
4372 {
4373 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4374 }
4375
4376 /**
4377 * @brief Enabling force to turn off the clock for EFUSE.
4378 *
4379 * Register | BitsName
4380 * ----------|--------
4381 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4382 *
4383 * @retval None
4384 */
4385 __STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
4386 {
4387 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4388 }
4389
4390 /**
4391 * @brief Disabling force to turn off the clock for EFUSE.
4392 *
4393 * Register | BitsName
4394 * ----------|--------
4395 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4396 *
4397 * @retval None
4398 */
4399 __STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
4400 {
4401 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4402 }
4403
4404 /**
4405 * @brief Indicate whether the clock for EFUSE is forced to close.
4406 *
4407 * Register | BitsName
4408 * ----------|--------
4409 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4410 *
4411 * @retval State of bit (1 or 0).
4412 */
4413 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
4414 {
4415 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4416 }
4417
4418 /**
4419 * @brief Enable AES automatic turn off clock during WFI/WFE
4420 *
4421 * Register | BitsName
4422 * ----------|--------
4423 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4424 *
4425 * @retval None
4426 */
4427 __STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
4428 {
4429 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4430 }
4431
4432 /**
4433 * @brief Disable AES automatic turn off clock during WFI/WFE
4434 *
4435 * Register | BitsName
4436 * ----------|--------
4437 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4438 *
4439 * @retval None
4440 */
4441 __STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
4442 {
4443 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4444 }
4445
4446 /**
4447 * @brief Indicate whether the AES automatic turn off clock is enabled.
4448 *
4449 * Register | BitsName
4450 * ----------|--------
4451 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4452 *
4453 * @retval State of bit (1 or 0).
4454 */
4455 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
4456 {
4457 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4458 }
4459
4460 /**
4461 * @brief Enable HMAC automatic turn off clock during WFI/WFE
4462 *
4463 * Register | BitsName
4464 * ----------|--------
4465 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4466 *
4467 * @retval None
4468 */
4469 __STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
4470 {
4471 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4472 }
4473
4474 /**
4475 * @brief Disable HMAC automatic turn off clock during WFI/WFE
4476 *
4477 * Register | BitsName
4478 * ----------|--------
4479 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4480 *
4481 * @retval None
4482 */
4483 __STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
4484 {
4485 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4486 }
4487
4488 /**
4489 * @brief Indicate whether the HMAC automatic turn off clock is enabled.
4490 *
4491 * Register | BitsName
4492 * ----------|--------
4493 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4494 *
4495 * @retval State of bit (1 or 0).
4496 */
4497 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
4498 {
4499 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4500 }
4501
4502 /**
4503 * @brief Enable PKC automatic turn off clock during WFI/WFE
4504 *
4505 * Register | BitsName
4506 * ----------|--------
4507 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4508 *
4509 * @retval None
4510 */
4511 __STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
4512 {
4513 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4514 }
4515
4516 /**
4517 * @brief Disable PKC automatic turn off clock during WFI/WFE
4518 *
4519 * Register | BitsName
4520 * ----------|--------
4521 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4522 *
4523 * @retval None
4524 */
4525 __STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
4526 {
4527 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4528 }
4529
4530 /**
4531 * @brief Indicate whether the PKC automatic turn off clock is enabled.
4532 *
4533 * Register | BitsName
4534 * ----------|--------
4535 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4536 *
4537 * @retval State of bit (1 or 0).
4538 */
4539 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
4540 {
4541 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4542 }
4543
4544 /**
4545 * @brief Enable PRESENT automatic turn off clock during WFI/WFE
4546 *
4547 * Register | BitsName
4548 * ----------|--------
4549 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4550 *
4551 * @retval None
4552 */
4553 __STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
4554 {
4555 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4556 }
4557
4558 /**
4559 * @brief Disable PRESENT automatic turn off clock during WFI/WFE
4560 *
4561 * Register | BitsName
4562 * ----------|--------
4563 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4564 *
4565 * @retval None
4566 */
4567 __STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
4568 {
4569 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4570 }
4571
4572 /**
4573 * @brief Indicate whether the PRESENT automatic turn off clock is enabled.
4574 *
4575 * Register | BitsName
4576 * ----------|--------
4577 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4578 *
4579 * @retval State of bit (1 or 0).
4580 */
4581 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
4582 {
4583 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4584 }
4585
4586 /**
4587 * @brief Enable RAMKEY automatic turn off clock during WFI/WFE
4588 *
4589 * Register | BitsName
4590 * ----------|--------
4591 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4592 *
4593 * @retval None
4594 */
4595 __STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
4596 {
4597 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4598 }
4599
4600 /**
4601 * @brief Disable RAMKEY automatic turn off clock during WFI/WFE
4602 *
4603 * Register | BitsName
4604 * ----------|--------
4605 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4606 *
4607 * @retval None
4608 */
4609 __STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
4610 {
4611 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4612 }
4613
4614 /**
4615 * @brief Indicate whether the RAMKEY automatic turn off clock is enabled.
4616 *
4617 * Register | BitsName
4618 * ----------|--------
4619 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4620 *
4621 * @retval State of bit (1 or 0).
4622 */
4623 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
4624 {
4625 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4626 }
4627
4628 /**
4629 * @brief Enable RNG automatic turn off clock during WFI/WFE
4630 *
4631 * Register | BitsName
4632 * ----------|--------
4633 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4634 *
4635 * @retval None
4636 */
4637 __STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
4638 {
4639 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4640 }
4641
4642 /**
4643 * @brief Disable RNG automatic turn off clock during WFI/WFE
4644 *
4645 * Register | BitsName
4646 * ----------|--------
4647 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4648 *
4649 * @retval None
4650 */
4651 __STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
4652 {
4653 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4654 }
4655
4656 /**
4657 * @brief Indicate whether the RNG automatic turn off clock is enabled.
4658 *
4659 * Register | BitsName
4660 * ----------|--------
4661 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4662 *
4663 * @retval State of bit (1 or 0).
4664 */
4665 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
4666 {
4667 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4668 }
4669
4670 /**
4671 * @brief Enable EFUSE automatic turn off clock during WFI/WFE
4672 *
4673 * Register | BitsName
4674 * ----------|--------
4675 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4676 *
4677 * @retval None
4678 */
4679 __STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
4680 {
4681 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4682 }
4683
4684 /**
4685 * @brief Disable EFUSE automatic turn off clock during WFI/WFE
4686 *
4687 * Register | BitsName
4688 * ----------|--------
4689 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4690 *
4691 * @retval None
4692 */
4693 __STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
4694 {
4695 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4696 }
4697
4698 /**
4699 * @brief Indicate whether the EFUSE automatic turn off clock is enabled.
4700 *
4701 * Register | BitsName
4702 * ----------|--------
4703 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4704 *
4705 * @retval State of bit (1 or 0).
4706 */
4707 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
4708 {
4709 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4710 }
4711
4712 /**
4713 * @brief Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
4714 *
4715 * Register | BitsName
4716 * ----------|--------
4717 * MCU_MISC_CLK | XQSPI/DMA0/DMA1/DMA2
4718 *
4719 * @retval None
4720 */
4721 __STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
4722 {
4723 MODIFY_REG(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK, clk_mask);
4724 }
4725
4726 /**
4727 * @brief Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
4728 *
4729 * Register | BitsName
4730 * ----------|--------
4731 * MCU_MISC_CLK | XQSPI/DMA0/DMA1/DMA2
4732 */
4733 __STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
4734 {
4735 return READ_BITS(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK);
4736 }
4737
4738 /**
4739 * @brief Enable XQSPI SCK CLK turn off
4740 *
4741 * Register | BitsName
4742 * ----------|--------
4743 * MCU_MISC_CLK |XQSPI SCK CLK_OFF
4744 *
4745 * @retval None
4746 */
4747 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
4748 {
4749 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_ENABLE;
4750 }
4751
4752 /**
4753 * @brief Disable XQSPI SCK CLK turn off
4754 *
4755 * Register | BitsName
4756 * ----------|--------
4757 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
4758 *
4759 * @retval None
4760 */
4761 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
4762 {
4763 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_DISABLE;
4764 }
4765
4766 /**
4767 * @brief Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
4768 *
4769 * Register | BitsName
4770 * ----------|--------
4771 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
4772 *
4773 * @retval State of bit (1 or 0).
4774 */
4775 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
4776 {
4777 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) == (CGC_CLOCK_ENABLE));
4778 }
4779
4780 /**
4781 * @brief Enable DMA0 turn off
4782 *
4783 * Register | BitsName
4784 * ----------|--------
4785 * MCU_MISC_CLK |DMA0_OFF
4786 *
4787 * @retval None
4788 */
4789 __STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
4790 {
4791 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
4792 }
4793
4794 /**
4795 * @brief Disable DMA0 turn off
4796 *
4797 * Register | BitsName
4798 * ----------|--------
4799 * MCU_MISC_CLK | DMA0_OFF
4800 *
4801 * @retval None
4802 */
4803 __STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
4804 {
4805 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
4806 }
4807
4808 /**
4809 * @brief Indicate whether the DMA0 automatic turn off clock is enabled.
4810 *
4811 * Register | BitsName
4812 * ----------|--------
4813 * MCU_MISC_CLK | DMA0_OFF
4814 *
4815 * @retval State of bit (1 or 0).
4816 */
4817 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
4818 {
4819 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
4820 }
4821
4822 /**
4823 * @brief Enable DMA1 turn off
4824 *
4825 * Register | BitsName
4826 * ----------|--------
4827 * MCU_MISC_CLK |DMA1_OFF
4828 *
4829 * @retval None
4830 */
4831 __STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
4832 {
4833 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
4834 }
4835
4836 /**
4837 * @brief Disable DMA1 turn off
4838 *
4839 * Register | BitsName
4840 * ----------|--------
4841 * MCU_MISC_CLK | DMA1_OFF
4842 *
4843 * @retval None
4844 */
4845 __STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
4846 {
4847 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
4848 }
4849
4850 /**
4851 * @brief Indicate whether the DMA1 automatic turn off clock is enabled.
4852 *
4853 * Register | BitsName
4854 * ----------|--------
4855 * MCU_MISC_CLK | DMA1_OFF
4856 *
4857 * @retval State of bit (1 or 0).
4858 */
4859 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
4860 {
4861 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
4862 }
4863
4864 /**
4865 * @brief Enable DMA2 turn off
4866 *
4867 * Register | BitsName
4868 * ----------|--------
4869 * MCU_MISC_CLK |DMA2_OFF
4870 *
4871 * @retval None
4872 */
4873 __STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
4874 {
4875 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
4876 }
4877
4878 /**
4879 * @brief Disable DMA2 turn off
4880 *
4881 * Register | BitsName
4882 * ----------|--------
4883 * MCU_MISC_CLK | DMA2_OFF
4884 *
4885 * @retval None
4886 */
4887 __STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
4888 {
4889 BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
4890 }
4891
4892 /**
4893 * @brief Indicate whether the DMA2 automatic turn off clock is enabled.
4894 *
4895 * Register | BitsName
4896 * ----------|--------
4897 * MCU_MISC_CLK | DMA2_OFF
4898 *
4899 * @retval State of bit (1 or 0).
4900 */
4901 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
4902 {
4903 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
4904 }
4905
4906 /** @} */
4907
4908 #endif /* CGC */
4909
4910 #ifdef __cplusplus
4911 }
4912 #endif
4913
4914 #endif /* __GR55XX_LL_CGC_H__ */
4915
4916 /** @} */
4917
4918 /** @} */
4919
4920 /** @} */
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2215
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1220
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:431
ll_cgc_is_enabled_spi_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
Indicate whether turn SPI_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3726
LL_CGC_MCU_SECU_FRC_OFF_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_HCLK
Definition: gr55xx_ll_cgc.h:228
ll_cgc_disable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
Disabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:2691
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:938
ll_cgc_disable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
Disabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:1977
ll_cgc_is_enabled_ahb_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3096
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2271
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2019
ll_cgc_disable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
Disable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3628
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1669
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:868
ll_cgc_get_wfi_off_hclk_4
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:538
ll_cgc_disable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
Disable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3796
ll_cgc_get_mcu_periph_low_power
__STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr55xx_ll_cgc.h:2802
ll_cgc_is_enabled_force_off_i2s_s_p_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2454
ll_cgc_set_wfi_off_hclk_4
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:521
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:910
ll_cgc_is_enabled_force_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
Indicate whether the clock for PRESENT is forced to close.
Definition: gr55xx_ll_cgc.h:4286
ll_cgc_enable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
Enabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:1921
ll_cgc_disable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
Disable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:2872
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:966
ll_cgc_disable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
Disabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:1935
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2173
ll_cgc_enable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
Enable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3278
ll_cgc_is_enabled_uart1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
Indicate whether turn UART1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3306
ll_cgc_disable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
Disable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3544
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2552
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr55xx_ll_cgc.h:571
ll_cgc_enable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
Enabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4258
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1178
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:1753
BIT_SEGMENT_VALUE
#define BIT_SEGMENT_VALUE(addr, bitnum)
Definition: gr55xx_ll_cgc.h:313
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:1907
ll_cgc_disable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
Disabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4188
ll_cgc_disable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
Disable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3460
ll_cgc_disable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
Disabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:2733
ll_cgc_disable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
Disable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3292
ll_cgc_enable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
Enable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3782
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1599
ll_cgc_enable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
Enabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2131
ll_cgc_enable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
Enable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3404
ll_cgc_is_enabled_force_off_dspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
Indicate whether the clock for DSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2496
ll_cgc_enable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
Enabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2089
ll_cgc_is_enabled_force_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
Indicate whether the clock for AES is forced to close.
Definition: gr55xx_ll_cgc.h:4160
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1206
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1276
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1417
ll_cgc_is_enabled_force_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
Indicate whether the clock for PKC is forced to close.
Definition: gr55xx_ll_cgc.h:4244
ll_cgc_is_enabled_spi_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
Indicate whether turn SPI_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3684
ll_cgc_enable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
Enable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4679
ll_cgc_is_enabled_force_off_xqspi_sck
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4775
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:812
ll_cgc_disable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
Disable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3754
ll_cgc_disable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
Disable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3964
ll_cgc_is_enabled_i2c1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
Indicate whether turn I2C1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3474
CGC_CLOCK_DISABLE
#define CGC_CLOCK_DISABLE
Definition: gr55xx_ll_cgc.h:303
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1375
ll_cgc_enable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
Enable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2942
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2075
ll_cgc_is_enabled_wfi_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
Indicate whether the EFUSE automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4707
ll_cgc_is_enabled_wfi_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
Indicate whether the RNG automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4665
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:466
ll_cgc_is_enabled_i2c2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
Indicate whether turn I2C2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3516
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1051
ll_cgc_enable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
Enabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2341
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2384
ll_cgc_get_force_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT...
Definition: gr55xx_ll_cgc.h:4075
ll_cgc_is_enabled_uart_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
Indicate whether the uart sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:2844
ll_cgc_enable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
Enable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3614
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1248
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2257
ll_cgc_is_enabled_ahb2apb_async_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3222
ll_cgc_enable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
Enable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:2858
ll_cgc_is_enabled_pwm1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
Indicate whether turn pwm1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3810
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:642
ll_cgc_enable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
Enable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:4747
ll_cgc_is_enabled_ahb2apb_sync_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
Indicate whether the AHB2APB bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3180
ll_cgc_is_enabled_force_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
Indicate whether the clock for RAMKEY is forced to close.
Definition: gr55xx_ll_cgc.h:4328
ll_cgc_set_force_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
Individual block's clock control inside security system which was forced to turn off (Include: AES/HM...
Definition: gr55xx_ll_cgc.h:4048
ll_cgc_enable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2426
ll_cgc_enable_qspim_low_power
__STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
Enable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3110
ll_cgc_disable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
Disable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3586
ll_cgc_is_enabled_i2s_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
Indicate whether the i2s low-power is enabled.
Definition: gr55xx_ll_cgc.h:2928
ll_cgc_enable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
Enable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3866
ll_cgc_is_enabled_dspi_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
Indicate whether turn DSPI off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3978
ll_cgc_disable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
Disable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3670
LL_CGC_WFI_ALL_HCLK0
#define LL_CGC_WFI_ALL_HCLK0
Definition: gr55xx_ll_cgc.h:85
LL_CGC_WFI_ALL_HCLK1
#define LL_CGC_WFI_ALL_HCLK1
Definition: gr55xx_ll_cgc.h:96
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1192
ll_cgc_enable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
Enable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3362
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1121
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1613
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1389
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1557
ll_cgc_disable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
Disabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4314
ll_cgc_get_slp_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMK...
Definition: gr55xx_ll_cgc.h:4118
ll_cgc_is_enabled_qspim2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3936
ll_cgc_is_enabled_force_off_uart2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
Indicate whether the clock for UART2 is forced to close.
Definition: gr55xx_ll_cgc.h:1949
ll_cgc_enable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
Enable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4469
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1022
ll_cgc_disable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
Disable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4525
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:412
ll_cgc_is_enabled_pwm0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
Indicate whether turn pwm0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3768
ll_cgc_is_enabled_force_off_i2c2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
Indicate whether the clock for I2C2 is forced to close.
Definition: gr55xx_ll_cgc.h:2117
ll_cgc_disable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
Disabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2145
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1627
ll_cgc_is_enabled_force_off_dma2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
Indicate whether the DMA2 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4901
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:798
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2061
ll_cgc_disable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
Disabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4272
ll_cgc_is_enabled_force_off_dma1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
Indicate whether the DMA1 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4859
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2187
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1290
ll_cgc_get_force_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:769
ll_cgc_disable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
Disabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:2649
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:1879
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:784
ll_cgc_enable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
Enable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3698
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1473
ll_cgc_is_enabled_spim_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
Indicate whether the spim sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:2970
LL_CGC_FRC_ALL_HCLK0
#define LL_CGC_FRC_ALL_HCLK0
Definition: gr55xx_ll_cgc.h:121
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1403
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1093
ll_cgc_enable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
Enabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:2593
ll_cgc_is_enabled_force_off_pdm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
Indicate whether the clock for PDM is forced to close.
Definition: gr55xx_ll_cgc.h:2538
ll_cgc_enable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
Enabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2510
ll_cgc_enable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
Enable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2984
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK...
Definition: gr55xx_ll_cgc.h:734
ll_cgc_disable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
Disable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3418
ll_cgc_disable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
Disable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3334
ll_cgc_disable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
Disable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4441
ll_cgc_disable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
Disable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:4845
ll_cgc_disable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
Disabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:4399
ll_cgc_enable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
Enabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:4343
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:1739
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:840
LL_CGC_FRC_ALL_HCLK1
#define LL_CGC_FRC_ALL_HCLK1
Definition: gr55xx_ll_cgc.h:131
ll_cgc_disable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3208
ll_cgc_disable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
Disable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3838
ll_cgc_is_enabled_force_off_dma0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
Indicate whether the DMA0 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4817
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:980
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1065
ll_cgc_set_wfi_off_hclk_3
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI....
Definition: gr55xx_ll_cgc.h:485
ll_cgc_is_enabled_force_off_pwm1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
Indicate whether the clock for PWM1 is forced to close.
Definition: gr55xx_ll_cgc.h:2705
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1529
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:896
ll_cgc_enable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
Enabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:2719
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:1795
ll_cgc_disable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
Disabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2355
ll_cgc_disable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
Disabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:2607
ll_cgc_enable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
Enable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4511
LL_CGC_FRC_ALL_HCLK2
#define LL_CGC_FRC_ALL_HCLK2
Definition: gr55xx_ll_cgc.h:161
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:1767
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1135
ll_cgc_disable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
Disable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2998
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1501
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1585
ll_cgc_is_enabled_uart3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
Indicate whether turn UART3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3390
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr55xx_ll_cgc.h:449
ll_cgc_enable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
Enable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4553
CGC_CLOCK_ENABLE
#define CGC_CLOCK_ENABLE
Definition: gr55xx_ll_cgc.h:302
ll_cgc_enable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3194
ll_cgc_enable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
Enable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3992
LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
Definition: gr55xx_ll_cgc.h:229
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2243
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:1711
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2005
ll_cgc_enable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
Enable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3488
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2327
ll_cgc_enable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
Enable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4427
ll_cgc_is_enabled_force_off_uart3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
Indicate whether the clock for UART3 is forced to close.
Definition: gr55xx_ll_cgc.h:1991
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2285
ll_cgc_is_enabled_uart2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
Indicate whether turn UART2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3348
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2201
ll_cgc_disable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3082
ll_cgc_disable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
Disabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4146
ll_cgc_disable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
Disable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4567
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2566
ll_cgc_is_enabled_uart0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
Indicate whether turn UART0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3264
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:2580
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:1837
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1515
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:826
ll_cgc_is_enabled_force_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
Indicate whether the clock for EFUSE is forced to close.
Definition: gr55xx_ll_cgc.h:4413
ll_cgc_disable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
Disable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3376
ll_cgc_enable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
Enable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3152
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1683
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1655
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:854
ll_cgc_is_enabled_force_off_i2c3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
Indicate whether the clock for I2C3 is forced to close.
Definition: gr55xx_ll_cgc.h:2159
ll_cgc_disable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
Disable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3922
ll_cgc_is_enabled_wfi_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
Indicate whether the PKC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4539
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:1725
ll_cgc_is_enabled_i2s_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
Indicate whether turn I2S_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3600
ll_cgc_is_enabled_force_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
Indicate whether the clock for HMAC is forced to close.
Definition: gr55xx_ll_cgc.h:4202
ll_cgc_enable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3068
ll_cgc_disable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
Disable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:4803
ll_cgc_disable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
Disabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2482
ll_cgc_is_enabled_wfi_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
Indicate whether the HMAC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4497
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:1851
ll_cgc_disable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
Disable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3502
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:924
ll_cgc_enable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
Enabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4174
ll_cgc_is_enabled_qspim_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
Indicate whether the QSPIM low-power is enabled.
Definition: gr55xx_ll_cgc.h:3138
ll_cgc_is_enabled_qspim0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3852
ll_cgc_enable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
Enable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4595
ll_cgc_enable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
Enable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3320
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:882
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1037
ll_cgc_is_enabled_i2s_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
Indicate whether turn I2S_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3642
ll_cgc_set_misc_clk
__STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
Definition: gr55xx_ll_cgc.h:4721
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1431
ll_cgc_enable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
Enabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4132
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1543
ll_cgc_disable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
Disable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4693
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/ ROM/SNSADC/GPIO/DMA/BLE_B...
Definition: gr55xx_ll_cgc.h:603
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:1823
ll_cgc_disable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
Disable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4483
ll_cgc_enable_i2s_low_power
__STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
Enable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:2900
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:994
ll_cgc_enable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
Enable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:4831
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/HTB/PWM/ ROM/SNSADC/GPIO/BLE...
Definition: gr55xx_ll_cgc.h:359
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr55xx_ll_cgc.h:392
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1234
ll_cgc_disable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
Disable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2956
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HC...
Definition: gr55xx_ll_cgc.h:687
ll_cgc_is_enabled_wfi_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
Indicate whether the AES automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4455
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1333
ll_cgc_is_enabled_i2c0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
Indicate whether turn I2C0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3432
ll_cgc_disable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
Disable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3250
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1304
ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
Indicate whether the div4 clock for xf qspi blocks is forced to close.
Definition: gr55xx_ll_cgc.h:2621
ll_cgc_disable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
Disable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:4761
ll_cgc_enable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
Enable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3950
ll_cgc_is_enabled_force_off_pwm0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
Indicate whether the clock for PWM0 is forced to close.
Definition: gr55xx_ll_cgc.h:2663
LL_CGC_MCU_MISC_CLK
#define LL_CGC_MCU_MISC_CLK
Definition: gr55xx_ll_cgc.h:237
ll_cgc_is_enabled_qspim1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3894
ll_cgc_enable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
Enable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3740
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1319
ll_cgc_enable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
Enable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3824
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:623
ll_cgc_is_enabled_i2c3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
Indicate whether turn I2C3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3558
ll_cgc_disable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
Disabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:4357
ll_cgc_disable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2440
ll_cgc_enable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
Enable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3236
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1262
ll_cgc_enable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
Enable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3530
ll_cgc_disable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
Disable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2830
ll_cgc_enable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
Enable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:4789
ll_cgc_enable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
Enable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4637
ll_cgc_disable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
Disable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3880
ll_cgc_enable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
Enable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3446
ll_cgc_enable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
Enable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3026
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:1893
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2412
ll_cgc_enable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
Enable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3572
ll_cgc_disable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
Disable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4006
ll_cgc_is_enabled_uart_pclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
Indicate whether the uart pclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:2886
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:1809
ll_cgc_enable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
Enabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4300
ll_cgc_disable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
Disabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2524
ll_cgc_set_slp_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/R...
Definition: gr55xx_ll_cgc.h:4097
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2047
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1459
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1347
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1107
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:952
ll_cgc_is_enabled_i2c_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
Indicate whether the i2c sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3054
ll_cgc_is_enabled_force_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
Indicate whether the clock for RNG is forced to close.
Definition: gr55xx_ll_cgc.h:4371
ll_cgc_is_enabled_wfi_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
Indicate whether the RAMKEY automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4623
ll_cgc_set_force_off_hclk_3
__STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:752
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1641
ll_cgc_disable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
Disable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3166
ll_cgc_enable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
Enable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3908
ll_cgc_disable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
Disabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4230
ll_cgc_disable_qspim_low_power
__STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
Disable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3124
ll_cgc_disable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
Disabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2103
ll_cgc_disable_i2s_low_power
__STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
Disable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:2914
ll_cgc_get_wfi_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI....
Definition: gr55xx_ll_cgc.h:503
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2313
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:1865
ll_cgc_enable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
Enabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4216
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1150
ll_cgc_disable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
Disable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3040
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2229
ll_cgc_enable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
Enable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:2816
ll_cgc_enable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
Enable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3656
ll_cgc_disable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
Disable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4609
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2299
ll_cgc_disable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
Disable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3712
ll_cgc_is_enabled_spis_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
Indicate whether the spis sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3012
ll_cgc_get_misc_clk
__STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
Definition: gr55xx_ll_cgc.h:4733
ll_cgc_is_enabled_force_off_qspi2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
Indicate whether the clock for QSPI2 is forced to close.
Definition: gr55xx_ll_cgc.h:2369
ll_cgc_set_mcu_periph_low_power
__STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr55xx_ll_cgc.h:2775
ll_cgc_is_enabled_wfi_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
Indicate whether the PRESENT automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:4581
ll_cgc_enable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
Enabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:4385
LL_CGC_WFI_ALL_HCLK2
#define LL_CGC_WFI_ALL_HCLK2
Definition: gr55xx_ll_cgc.h:105
ll_cgc_enable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
Enabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:1963
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1571
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2033
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1079
ll_cgc_is_enabled_pdm_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
Indicate whether turn PDM off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4020
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1487
ll_cgc_enable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
Enabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:2677
LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
#define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
Definition: gr55xx_ll_cgc.h:206
ll_cgc_enable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
Enabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:2635
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:1781
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1361
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1164
ll_cgc_disable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
Disable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:4887
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1697
ll_cgc_enable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
Enabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2468
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2398
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1445
ll_cgc_is_enabled_force_off_vttbl_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
Indicate whether the clock for VTTBL is forced to close.
Definition: gr55xx_ll_cgc.h:2747
ll_cgc_disable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
Disable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4651
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1008
ll_cgc_enable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
Enable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:4873