gr55xx_ll_dspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DSPI DSPI
47 * @brief DSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_DSPI_H__
53 #define __GR55XX_LL_DSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(DSPI)
63
64 /** @defgroup DSPI_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup DSPI_LL_ES_INIT DSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief DSPI init structures definition
75 */
76 typedef struct _ll_dspi_init_t
77 {
78 uint32_t data_size; /**< Specifies the DSPI data width.
79 This parameter can be a value of @ref DSPI_LL_EC_DATASIZE.
80
81 This feature can be modified afterwards using unitary function ll_dspi_set_data_size().*/
82
83 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
84 This parameter can be one even value between 0 and 7 @ref DSPI_LL_EC_CLK
85
86 This feature can be modified afterwards using unitary function ll_dspi_set_baud_rate_prescaler().*/
87
88 uint32_t transmit_format; /**< Specifies the DSPI transmission format.
89 This parameter can be a value of @ref DSPI_LL_EC_TRANSFER_FORMATE.
90
91 This feature can be modified afterwards using unitary function ll_dspi_set_transfer_format().*/
92
93 uint32_t dspi_mode; /**< Specifies the DSPI protocol mode.
94 This parameter can be a value of @ref DSPI_LL_EC_PROTOCOL_MODE.
95
96 This feature can be modified afterwards using unitary function ll_dspi_set_protocol_mode().*/
97 } ll_dspi_init_t;
98
99 /** @} */
100
101 /** @} */
102
103 /**
104 * @defgroup DSPI_LL_MACRO Defines
105 * @{
106 */
107
108 /* Exported constants --------------------------------------------------------*/
109 /** @defgroup DSPI_LL_Exported_Constants DSPI Exported Constants
110 * @{
111 */
112
113 /** @defgroup DSPI_LL_EC_GET_FLAG Get Flags Defines
114 * @brief Flags definitions which can be used with LL_DSPI_StatReg function
115 * @{
116 */
117 #define LL_DSPI_SR_FFE DSPI_STAT_FRE /**< Frame format error flag */
118 #define LL_DSPI_SR_BUSY DSPI_STAT_BUSY /**< Busy flag */
119 #define LL_DSPI_SR_OVR DSPI_STAT_OVR /**< Overrun flag */
120 #define LL_DSPI_SR_MODF DSPI_STAT_MODF /**< Mode fault */
121 #define LL_DSPI_SR_TFE DSPI_STAT_TXE /**< Tx FIFO empty flag */
122 #define LL_DSPI_SR_RFNE DSPI_STAT_RXNE /**< Rx FIFO not empty flag */
123 #define LL_DSPI_SR_ALL (LL_DSPI_SR_FFE | \
124 LL_DSPI_SR_BUSY | \
125 LL_DSPI_SR_OVR | \
126 LL_DSPI_SR_MODF | \
127 LL_DSPI_SR_TFE | \
128 LL_DSPI_SR_RFNE ) /**< All flag */
129 /** @} */
130
131 /** @defgroup DSPI_LL_EC_IT IT Defines
132 * @brief Interrupt definitions which can be used with LL_DSPI_Ctrl2Reg
133 * @{
134 */
135 #define LL_DSPI_IM_TXE DSPI_CR2_TXEIE /**< Transmit FIFO Empty Interrupt enable */
136 #define LL_DSPI_IM_RXNE DSPI_CR2_RXNEIE /**< Receive FIFO not empty Interrupt enable */
137 #define LL_DSPI_IM_ER DSPI_CR2_ERRIE /**< Error interrupt enable, OVR, MODF */
138 /** @} */
139
140 /** @defgroup DSPI_LL_EC_PROTOCOL_MODE DSPI Protocol mode
141 * @{
142 */
143 #define LL_DSPI_PROT_MODE_SPI (0UL << DSPI_MODE_SPIMODE_Pos) /**< DSPI Normal SPI Interface */
144 #define LL_DSPI_PROT_MODE_3W1L (1UL << DSPI_MODE_SPIMODE_Pos) /**< DSPI 3-Wire 1-Lane Interface */
145 #define LL_DSPI_PROT_MODE_4W1L (2UL << DSPI_MODE_SPIMODE_Pos) /**< DSPI 4-Wire 1-Lane Interface */
146 #define LL_DSPI_PROT_MODE_4W2L (3UL << DSPI_MODE_SPIMODE_Pos) /**< DSPI 4-Wire 2-Lane Interface */
147 /** @} */
148
149 /** @defgroup DSPI_LL_EC_TRANSFER_FORMATE DSPI Transmission Format
150 * @{
151 */
152 #define LL_DSPI_TF_MSB_FIRST (0x0) /**< DSPI Frame format MSB first */
153 #define LL_DSPI_TF_LSB_FIRST DSPI_CR1_LSBFIRST /**< DSPI Frame format LSB first */
154 /** @} */
155
156 /** @defgroup DSPI_LL_EC_DATASIZE Datawidth
157 * @{
158 */
159 #define LL_DSPI_DATASIZE_4BIT (3UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 4 bits */
160 #define LL_DSPI_DATASIZE_5BIT (4UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 5 bits */
161 #define LL_DSPI_DATASIZE_6BIT (5UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 6 bits */
162 #define LL_DSPI_DATASIZE_7BIT (6UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 7 bits */
163 #define LL_DSPI_DATASIZE_8BIT (7UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 8 bits */
164 #define LL_DSPI_DATASIZE_9BIT (8UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 9 bits */
165 #define LL_DSPI_DATASIZE_10BIT (9UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 10 bits */
166 #define LL_DSPI_DATASIZE_11BIT (10UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 11 bits */
167 #define LL_DSPI_DATASIZE_12BIT (11UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 12 bits */
168 #define LL_DSPI_DATASIZE_13BIT (12UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 13 bits */
169 #define LL_DSPI_DATASIZE_14BIT (13UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 14 bits */
170 #define LL_DSPI_DATASIZE_15BIT (14UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 15 bits */
171 #define LL_DSPI_DATASIZE_16BIT (15UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 16 bits */
172 #define LL_DSPI_DATASIZE_17BIT (16UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 17 bits */
173 #define LL_DSPI_DATASIZE_18BIT (17UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 18 bits */
174 #define LL_DSPI_DATASIZE_19BIT (18UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 19 bits */
175 #define LL_DSPI_DATASIZE_20BIT (19UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 20 bits */
176 #define LL_DSPI_DATASIZE_21BIT (20UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 21 bits */
177 #define LL_DSPI_DATASIZE_22BIT (21UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 22 bits */
178 #define LL_DSPI_DATASIZE_23BIT (22UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 23 bits */
179 #define LL_DSPI_DATASIZE_24BIT (23UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 24 bits */
180 #define LL_DSPI_DATASIZE_25BIT (24UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 25 bits */
181 #define LL_DSPI_DATASIZE_26BIT (25UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 26 bits */
182 #define LL_DSPI_DATASIZE_27BIT (26UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 27 bits */
183 #define LL_DSPI_DATASIZE_28BIT (27UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 28 bits */
184 #define LL_DSPI_DATASIZE_29BIT (28UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 29 bits */
185 #define LL_DSPI_DATASIZE_30BIT (29UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 30 bits */
186 #define LL_DSPI_DATASIZE_31BIT (30UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 31 bits */
187 #define LL_DSPI_DATASIZE_32BIT (31UL << DSPI_CR2_DS_Pos) /**< Data length for DSPI transfer: 32 bits */
188 /** @} */
189
190 /** @defgroup DSPI_LL_EC_BIDIMODE Bidirectional data mode enable
191 * @{
192 */
193 #define LL_DSPI_BIDIMODE_2L_UNBID 0x00000000UL /**< 2-line unidirectional data mode selected */
194 #define LL_DSPI_BIDIMODE_1L_BID DSPI_CR1_BIDIDE /**< 1-line bidirectional data mode selected */
195 /** @} */
196
197 /** @defgroup DSPI_LL_EC_TRANSFER_MODE Transfer Mode in 2-Line Unidirectional Data Mode
198 * @{
199 */
200 #define LL_DSPI_2L_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer */
201 #define LL_DSPI_2L_SIMPLEX_RX DSPI_CR1_RXONLY /**< Simplex Rx mode. Rx transfer only */
202 /** @} */
203
204 /** @defgroup DSPI_LL_EC_1L_TRANSFER_MODE Transfer Mode in 1-Line idirectional Data Mode
205 * @{
206 */
207 #define LL_DSPI_1L_SIMPLEX_RX 0x00000000UL /**< Simplex Rx mode. Rx receive only */
208 #define LL_DSPI_1L_SIMPLEX_TX DSPI_CR1_BIDIOE /**< Simplex Tx mode. Rx transfer only */
209 /** @} */
210
211 /** @defgroup DSPI_LL_EC_CLK DSPI Baud rate control
212 * @{
213 */
214 #define LL_DSPI_BAUD_RATE_2P1PCLK (0x0 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 2 */
215 #define LL_DSPI_BAUD_RATE_4P1PCLK (0x1 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 4 */
216 #define LL_DSPI_BAUD_RATE_8P1PCLK (0x2 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 8 */
217 #define LL_DSPI_BAUD_RATE_16P1PCLK (0x3 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 16 */
218 #define LL_DSPI_BAUD_RATE_32P1PCLK (0x4 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 32 */
219 #define LL_DSPI_BAUD_RATE_64P1PCLK (0x5 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 64 */
220 #define LL_DSPI_BAUD_RATE_128P1PCLK (0x6 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 128 */
221 #define LL_DSPI_BAUD_RATE_256PCLK (0x7 << DSPI_CR1_BAUD_Pos) /**< DSPI Baud rate fPCLK / 256 */
222 /** @} */
223
224 /** @defgroup DSPI_LL_EC_PHASE Clock Phase
225 * @{
226 */
227 #define LL_DSPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
228 #define LL_DSPI_SCPHA_2EDGE (DSPI_CR1_CPHA) /**< Second clock transition is the first data capture edge */
229 /** @} */
230
231 /** @defgroup DSPI_LL_EC_POLARITY Clock Polarity
232 * @{
233 */
234 #define LL_DSPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
235 #define LL_DSPI_SCPOL_HIGH (DSPI_CR1_CPOL) /**< Clock to 1 when idle */
236 /** @} */
237
238 /** @defgroup DSPI_LL_EC_DMA DMA Defines
239 * @{
240 */
241 #define LL_DSPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
242 #define LL_DSPI_DMA_TX_EN DSPI_CR2_TXDMAEN /**< Enable the transmit FIFO DMA channel */
243
244 #define LL_DSPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
245 #define LL_DSPI_DMA_RX_EN DSPI_CR2_RXDMAEN /**< Enable the receive FIFO DMA channel */
246 /** @} */
247
248 /** @defgroup DSPI_LL_EC_LAST_DMA_TF Last DMA transfer or receive
249 * @{
250 */
251 #define LL_DSPI_DMA_LTX_EVEN 0x00000000UL /**< Number of data to transfer is even */
252 #define LL_DSPI_DMA_LTX_ODD DSPI_CR2_LDMA_TX /**< Number of data to transfer is odd */
253
254 #define LL_DSPI_DMA_LRX_EVEN 0x00000000UL /**< Number of data to transfer is even */
255 #define LL_DSPI_DMA_LRX_ODD DSPI_CR2_LDMA_RX /**< Number of data to transfer is odd */
256 /** @} */
257
258 /** @defgroup DSPI_LL_EC_DMA DMA Defines
259 * @{
260 */
261 #define LL_DSPI_FRXTH_1P2 DSPI_CR1_FIFOTH_8 /**< FIFO level is 1/2 (8 bytes) */
262 #define LL_DSPI_FRXTH_1P4 DSPI_CR1_FIFOTH_4 /**< FIFO level is 1/4 (4 bytes) */
263 #define LL_DSPI_FRXTH_1P8 DSPI_CR1_FIFOTH_2 /**< FIFO level is 1/8 (2 bytes) */
264 #define LL_DSPI_FRXTH_1P16 DSPI_CR1_FIFOTH_1 /**< FIFO level is 1/16 (1 bytes) */
265 /** @} */
266
267 /** @defgroup DSPI_LL_EC_DCX Value of Data-Versus-Command information used in Display SPI Protocol Modes.
268 * @{
269 */
270 #define LL_DSPI_DCX_CMD 0x00000000UL /**< Data-Versus-Command value to 0(CMD) */
271 #define LL_DSPI_DCX_DATA (DSPI_MODE_DCX) /**< Data-Versus-Command value to 1(DATA) */
272 /** @} */
273
274 /** @defgroup DSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
275 * @{
276 */
277
278 /**
279 * @brief LL DSPI InitStrcut default configuartion
280 */
281 #define LL_DSPI_DEFAULT_CONFIG \
282 { \
283 .transmit_format = LL_DSPI_TF_MSB_FIRST, \
284 .data_size = LL_DSPI_DATASIZE_8BIT, \
285 .dspi_mode = LL_DSPI_PROT_MODE_4W1L, \
286 .baud_rate = LL_DSPI_BAUD_RATE_8P1PCLK, \
287 }
288
289 /** @} */
290
291 /** @} */
292
293 /* Exported macro ------------------------------------------------------------*/
294 /** @defgroup DSPI_LL_Exported_Macros DSPI Exported Macros
295 * @{
296 */
297
298 /** @defgroup DSPI_LL_EM_WRITE_READ Common Write and read registers Macros
299 * @{
300 */
301
302 /**
303 * @brief Write a value in DSPI register
304 * @param __instance__ DSPI instance
305 * @param __REG__ Register to be written
306 * @param __VALUE__ Value to be written in the register
307 * @retval None
308 */
309 #define LL_DSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
310
311 /**
312 * @brief Read a value in DSPI register
313 * @param __instance__ DSPI instance
314 * @param __REG__ Register to be read
315 * @retval Register value
316 */
317 #define LL_DSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
318
319 /** @} */
320
321 /** @} */
322
323 /** @} */
324
325 /* Exported functions --------------------------------------------------------*/
326 /** @defgroup DSPI_LL_DRIVER_FUNCTIONS Functions
327 * @{
328 */
329
330 /** @defgroup DSPI_LL_EF_Configuration Configuration functions
331 * @{
332 */
333
334 /**
335 * @brief Enable DSPI peripheral
336 *
337 * Register|BitsName
338 * --------|--------
339 * CTRL1 | EN
340 *
341 * @param DSPIx instance
342 * @retval None
343 */
344 __STATIC_INLINE void ll_dspi_enable(dspi_regs_t *DSPIx)
345 {
346 SET_BITS(DSPIx->CTRL1, DSPI_CR1_EN);
347 }
348
349 /**
350 * @brief Disable DSPI peripheral
351 *
352 * Register|BitsName
353 * --------|--------
354 * CTRL1 | EN
355 *
356 * @param DSPIx instance
357 * @retval None
358 */
359
360 __STATIC_INLINE void ll_dspi_disable(dspi_regs_t *DSPIx)
361 {
362 CLEAR_BITS(DSPIx->CTRL1, DSPI_CR1_EN);
363 }
364
365 /**
366 * @brief Check if DSPI peripheral is enabled
367 *
368 * Register|BitsName
369 * --------|--------
370 * CTRL1 | EN
371 *
372 * @param DSPIx instance
373 * @retval State of bit (1 or 0).
374 */
375 __STATIC_INLINE uint32_t ll_dspi_is_enabled(dspi_regs_t *DSPIx)
376 {
377 return (READ_BITS(DSPIx->CTRL1, DSPI_CR1_EN) == (DSPI_CR1_EN));
378 }
379
380 /**
381 * @brief Set clock polarity
382 * @note This bit should not be changed when communication is ongoing.
383 * This bit is not used in DSPI TI mode.
384 *
385 * Register|BitsName
386 * --------|--------
387 * CTRL1 | SCPOL
388 *
389 * @param DSPIx instance
390 * @param clock_polarity This parameter can be one of the following values:
391 * @arg @ref LL_DSPI_SCPOL_LOW
392 * @arg @ref LL_DSPI_SCPOL_HIGH
393 * @retval None
394 */
395 __STATIC_INLINE void ll_dspi_set_clock_polarity(dspi_regs_t *DSPIx, uint32_t clock_polarity)
396 {
397 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_CPOL, clock_polarity);
398 }
399
400 /**
401 * @brief Get clock polarity
402 *
403 * Register|BitsName
404 * --------|--------
405 * CTRL1 | SCPOL
406 *
407 * @param DSPIx instance
408 * @retval Returned value can be one of the following values:
409 * @arg @ref LL_DSPI_SCPOL_LOW
410 * @arg @ref LL_DSPI_SCPOL_HIGH
411 */
412 __STATIC_INLINE uint32_t ll_dspi_get_clock_polarity(dspi_regs_t *DSPIx)
413 {
414 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_CPOL));
415 }
416
417 /**
418 * @brief Set clock phase
419 * @note This bit should not be changed when communication is ongoing.
420 *
421 * Register|BitsName
422 * --------|--------
423 * CTRL1 | SCPHA
424 *
425 * @param DSPIx instance
426 * @param clock_phase This parameter can be one of the following values:
427 * @arg @ref LL_DSPI_SCPHA_1EDGE
428 * @arg @ref LL_DSPI_SCPHA_2EDGE
429 * @retval None
430 */
431 __STATIC_INLINE void ll_dspi_set_clock_phase(dspi_regs_t *DSPIx, uint32_t clock_phase)
432 {
433 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_CPHA, clock_phase);
434 }
435
436 /**
437 * @brief Get clock phase
438 *
439 * Register|BitsName
440 * --------|--------
441 * CTRL1 | SCPHA
442 *
443 * @param DSPIx instance
444 * @retval Returned value can be one of the following values:
445 * @arg @ref LL_DSPI_SCPHA_1EDGE
446 * @arg @ref LL_DSPI_SCPHA_2EDGE
447 */
448 __STATIC_INLINE uint32_t ll_dspi_get_clock_phase(dspi_regs_t *DSPIx)
449 {
450 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_CPHA));
451 }
452
453 /**
454 * @brief Set data frame format for transmitting/receiving the data
455 * @note This bit should be written only when DSPI is disabled (EN = 0) for correct operation.
456 *
457 * Register|BitsName
458 * --------|--------
459 * CTRL1 | LSBFIRST
460 *
461 * @param DSPIx instance
462 * @param frf This parameter can be one of the following values:
463 * @arg @ref LL_DSPI_TF_MSB_FIRST
464 * @arg @ref LL_DSPI_TF_LSB_FIRST
465 * @retval None
466 */
467 __STATIC_INLINE void ll_dspi_set_frame_format(dspi_regs_t *DSPIx, uint32_t frf)
468 {
469 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_LSBFIRST, frf);
470 }
471
472 /**
473 * @brief Get data frame format for transmitting/receiving the data
474 * @note This bit should be written only when DSPI is disabled (SSI_EN = 0) for correct operation.
475 *
476 * Register|BitsName
477 * --------|--------
478 * CTRL1 | LSBFIRST
479 *
480 * @param DSPIx instance
481 * @retval Returned value can be one of the following values:
482 * @arg @ref LL_DSPI_TF_MSB_FIRST
483 * @arg @ref LL_DSPI_TF_LSB_FIRST
484 */
485 __STATIC_INLINE uint32_t ll_dspi_get_frame_format(dspi_regs_t *DSPIx)
486 {
487 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_LSBFIRST));
488 }
489
490 /**
491 * @brief Set frame data size
492 *
493 * Register|BitsName
494 * --------|--------
495 * CTRL2 | DS
496 *
497 * @param DSPIx instance
498 * @param size This parameter can be one of the following values:
499 * @arg @ref LL_DSPI_DATASIZE_4BIT
500 * @arg @ref LL_DSPI_DATASIZE_5BIT
501 * @arg @ref LL_DSPI_DATASIZE_6BIT
502 * @arg @ref LL_DSPI_DATASIZE_7BIT
503 * @arg @ref LL_DSPI_DATASIZE_8BIT
504 * @arg @ref LL_DSPI_DATASIZE_9BIT
505 * @arg @ref LL_DSPI_DATASIZE_10BIT
506 * @arg @ref LL_DSPI_DATASIZE_11BIT
507 * @arg @ref LL_DSPI_DATASIZE_12BIT
508 * @arg @ref LL_DSPI_DATASIZE_13BIT
509 * @arg @ref LL_DSPI_DATASIZE_14BIT
510 * @arg @ref LL_DSPI_DATASIZE_15BIT
511 * @arg @ref LL_DSPI_DATASIZE_16BIT
512 * @arg @ref LL_DSPI_DATASIZE_17BIT
513 * @arg @ref LL_DSPI_DATASIZE_18BIT
514 * @arg @ref LL_DSPI_DATASIZE_19BIT
515 * @arg @ref LL_DSPI_DATASIZE_20BIT
516 * @arg @ref LL_DSPI_DATASIZE_21BIT
517 * @arg @ref LL_DSPI_DATASIZE_22BIT
518 * @arg @ref LL_DSPI_DATASIZE_23BIT
519 * @arg @ref LL_DSPI_DATASIZE_24BIT
520 * @arg @ref LL_DSPI_DATASIZE_25BIT
521 * @arg @ref LL_DSPI_DATASIZE_26BIT
522 * @arg @ref LL_DSPI_DATASIZE_27BIT
523 * @arg @ref LL_DSPI_DATASIZE_28BIT
524 * @arg @ref LL_DSPI_DATASIZE_29BIT
525 * @arg @ref LL_DSPI_DATASIZE_30BIT
526 * @arg @ref LL_DSPI_DATASIZE_31BIT
527 * @arg @ref LL_DSPI_DATASIZE_32BIT
528 * @retval None
529 */
530 __STATIC_INLINE void ll_dspi_set_data_size(dspi_regs_t *DSPIx, uint32_t size)
531 {
532 MODIFY_REG(DSPIx->CTRL2, DSPI_CR2_DS, size);
533 }
534
535 /**
536 * @brief Get frame data size
537 *
538 * Register|BitsName
539 * --------|--------
540 * CTRL2 | DS
541 *
542 * @param DSPIx instance
543 * @retval Returned value can be one of the following values:
544 * @arg @ref LL_DSPI_DATASIZE_4BIT
545 * @arg @ref LL_DSPI_DATASIZE_5BIT
546 * @arg @ref LL_DSPI_DATASIZE_6BIT
547 * @arg @ref LL_DSPI_DATASIZE_7BIT
548 * @arg @ref LL_DSPI_DATASIZE_8BIT
549 * @arg @ref LL_DSPI_DATASIZE_9BIT
550 * @arg @ref LL_DSPI_DATASIZE_10BIT
551 * @arg @ref LL_DSPI_DATASIZE_11BIT
552 * @arg @ref LL_DSPI_DATASIZE_12BIT
553 * @arg @ref LL_DSPI_DATASIZE_13BIT
554 * @arg @ref LL_DSPI_DATASIZE_14BIT
555 * @arg @ref LL_DSPI_DATASIZE_15BIT
556 * @arg @ref LL_DSPI_DATASIZE_16BIT
557 * @arg @ref LL_DSPI_DATASIZE_17BIT
558 * @arg @ref LL_DSPI_DATASIZE_18BIT
559 * @arg @ref LL_DSPI_DATASIZE_19BIT
560 * @arg @ref LL_DSPI_DATASIZE_20BIT
561 * @arg @ref LL_DSPI_DATASIZE_21BIT
562 * @arg @ref LL_DSPI_DATASIZE_22BIT
563 * @arg @ref LL_DSPI_DATASIZE_23BIT
564 * @arg @ref LL_DSPI_DATASIZE_24BIT
565 * @arg @ref LL_DSPI_DATASIZE_25BIT
566 * @arg @ref LL_DSPI_DATASIZE_26BIT
567 * @arg @ref LL_DSPI_DATASIZE_27BIT
568 * @arg @ref LL_DSPI_DATASIZE_28BIT
569 * @arg @ref LL_DSPI_DATASIZE_29BIT
570 * @arg @ref LL_DSPI_DATASIZE_30BIT
571 * @arg @ref LL_DSPI_DATASIZE_31BIT
572 * @arg @ref LL_DSPI_DATASIZE_32BIT
573 */
574 __STATIC_INLINE uint32_t ll_dspi_get_data_size(dspi_regs_t *DSPIx)
575 {
576 return (uint32_t)(READ_BITS(DSPIx->CTRL2, DSPI_CR2_DS));
577 }
578
579 /**
580 * @brief Set baud rate
581 * @note These bits should not be changed when communication is ongoing.
582 *
583 * Register|BitsName
584 * --------|--------
585 * CTRL1 | BR
586 *
587 * @param DSPIx SPI instance
588 * @param baud_rate This parameter can be one of the following values:
589 * @arg @ref LL_DSPI_BAUD_RATE_2P1PCLK
590 * @arg @ref LL_DSPI_BAUD_RATE_4P1PCLK
591 * @arg @ref LL_DSPI_BAUD_RATE_8P1PCLK
592 * @arg @ref LL_DSPI_BAUD_RATE_16P1PCLK
593 * @arg @ref LL_DSPI_BAUD_RATE_32P1PCLK
594 * @arg @ref LL_DSPI_BAUD_RATE_64P1PCLK
595 * @arg @ref LL_DSPI_BAUD_RATE_128P1PCLK
596 * @arg @ref LL_DSPI_BAUD_RATE_256PCLK
597 * @retval None
598 */
599 __STATIC_INLINE void ll_dspi_set_baud_rate(dspi_regs_t *DSPIx, uint32_t baud_rate)
600 {
601 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_BAUD, baud_rate);
602 }
603
604 /**
605 * @brief Get baud rate
606 *
607 * Register|BitsName
608 * --------|--------
609 * CTRL1 | BR
610 *
611 * @param DSPIx instance
612 * @retval Returned value can be one of the following values:
613 * @arg @ref LL_DSPI_BAUD_RATE_2P1PCLK
614 * @arg @ref LL_DSPI_BAUD_RATE_4P1PCLK
615 * @arg @ref LL_DSPI_BAUD_RATE_8P1PCLK
616 * @arg @ref LL_DSPI_BAUD_RATE_16P1PCLK
617 * @arg @ref LL_DSPI_BAUD_RATE_32P1PCLK
618 * @arg @ref LL_DSPI_BAUD_RATE_64P1PCLK
619 * @arg @ref LL_DSPI_BAUD_RATE_128P1PCLK
620 * @arg @ref LL_DSPI_BAUD_RATE_256PCLK
621 */
622 __STATIC_INLINE uint32_t ll_dspi_get_baud_rate(dspi_regs_t *DSPIx)
623 {
624 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_BAUD));
625 }
626
627 /**
628 * @brief Set bidirectional data mode enable
629 *
630 * Register|BitsName
631 * --------|--------
632 * CTRL1 | BIDIMODE
633 *
634 * @param DSPIx instance
635 * @param bid_mode This parameter can be one of the following values:
636 * @arg @ref LL_DSPI_BIDIMODE_2L_UNBID
637 * @arg @ref LL_DSPI_BIDIMODE_1L_BID
638 * @retval None
639 */
640 __STATIC_INLINE void ll_dspi_set_bidirectional_mode(dspi_regs_t *DSPIx, uint32_t bid_mode)
641 {
642 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_BIDIDE, bid_mode);
643 }
644
645 /**
646 * @brief Get baud rate
647 *
648 * Register|BitsName
649 * --------|--------
650 * CTRL1 | BIDIMODE
651 *
652 * @param DSPIx instance
653 * @retval Returned value can be one of the following values:
654 * @arg @ref LL_DSPI_BIDIMODE_2L_UNBID
655 * @arg @ref LL_DSPI_BIDIMODE_1L_BID
656 */
657 __STATIC_INLINE uint32_t ll_dspi_get_bidirectional_mode(dspi_regs_t *DSPIx)
658 {
659 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_BIDIDE));
660 }
661
662 /**
663 * @brief Set transfer direction mode in bidirectional mode.
664 *
665 * Register|BitsName
666 * --------|--------
667 * CTRL1 | BIDIOE
668 *
669 * @param DSPIx instance
670 * @param transfer_direction This parameter can be one of the following values:
671 * @arg @ref LL_DSPI_1L_SIMPLEX_RX
672 * @arg @ref LL_DSPI_1L_SIMPLEX_TX
673 * @retval None
674 */
675 __STATIC_INLINE void ll_dspi_set_transfer_direction_bidirectional(dspi_regs_t *DSPIx, uint32_t transfer_direction)
676 {
677 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_BIDIOE, transfer_direction);
678 }
679
680 /**
681 * @brief Get transfer direction mode in bidirectional mode.
682 *
683 * Register|BitsName
684 * --------|--------
685 * CTRL1 | BIDIOE
686 *
687 * @param DSPIx instance
688 * @retval Returned value can be one of the following values:
689 * @arg @ref LL_DSPI_1L_SIMPLEX_RX
690 * @arg @ref LL_DSPI_1L_SIMPLEX_TX
691 */
692 __STATIC_INLINE uint32_t ll_dspi_get_transfer_direction_bidirectional(dspi_regs_t *DSPIx)
693 {
694 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_BIDIOE));
695 }
696
697 /**
698 * @brief Set transfer direction mode in unbidirectional mode.
699 *
700 * Register|BitsName
701 * --------|--------
702 * CTRL1 | RXONLY
703 *
704 * @param DSPIx instance
705 * @param transfer_direction This parameter can be one of the following values:
706 * @arg @ref LL_DSPI_2L_FULL_DUPLEX
707 * @arg @ref LL_DSPI_2L_SIMPLEX_RX
708 * @retval None
709 */
710 __STATIC_INLINE void ll_dspi_set_transfer_direction_unbidirectional(dspi_regs_t *DSPIx, uint32_t transfer_direction)
711 {
712 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_RXONLY, transfer_direction);
713 }
714
715 /**
716 * @brief Get transfer direction mode in bidirectional mode.
717 *
718 * Register|BitsName
719 * --------|--------
720 * CTRL1 | RXONLY
721 *
722 * @param DSPIx instance
723 * @retval Returned value can be one of the following values:
724 * @arg @ref LL_DSPI_2L_FULL_DUPLEX
725 * @arg @ref LL_DSPI_2L_SIMPLEX_RX
726 */
727 __STATIC_INLINE uint32_t ll_dspi_get_transfer_direction_unbidirectional(dspi_regs_t *DSPIx)
728 {
729 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_RXONLY));
730 }
731
732 /**
733 * @brief Set threshold of TXFIFO that triggers an TXE event
734 *
735 * Register|BitsName
736 * --------|--------
737 * CTRL1 | FRXTH
738 *
739 * @param DSPIx instance
740 * @param threshold This parameter can be one of the following values:
741 * @arg @ref LL_DSPI_FRXTH_1P2
742 * @arg @ref LL_DSPI_FRXTH_1P4
743 * @arg @ref LL_DSPI_FRXTH_1P8
744 * @arg @ref LL_DSPI_FRXTH_1P16
745 * @retval None
746 */
747 __STATIC_INLINE void ll_dspi_set_rx_fifo_threshold(dspi_regs_t *DSPIx, uint32_t threshold)
748 {
749 MODIFY_REG(DSPIx->CTRL1, DSPI_CR1_FIFOTH, threshold);
750 }
751
752 /**
753 * @brief Get threshold of TXFIFO that triggers an TXE event
754 *
755 * Register|BitsName
756 * --------|--------
757 * CTRL1 | FRXTH
758 *
759 * @param DSPIx instance
760 * @retval Returned value can be one of the following values:
761 * @arg @ref LL_DSPI_FRXTH_1P2
762 * @arg @ref LL_DSPI_FRXTH_1P4
763 * @arg @ref LL_DSPI_FRXTH_1P8
764 * @arg @ref LL_DSPI_FRXTH_1P16
765 */
766 __STATIC_INLINE uint32_t ll_dspi_get_rx_fifo_threshold(dspi_regs_t *DSPIx)
767 {
768 return (uint32_t)(READ_BITS(DSPIx->CTRL1, DSPI_CR1_FIFOTH));
769 }
770
771 /**
772 * @brief FIFO Pointer Reset
773 *
774 * Register|BitsName
775 * --------|--------
776 * DSPI | FPRST
777 *
778 * @param DSPIx instance
779 */
780 __STATIC_INLINE void ll_dspi_flush_fifo(dspi_regs_t *DSPIx)
781 {
782 SET_BITS(DSPIx->CTRL1, DSPI_CR1_REFIFO);
783 CLEAR_BITS(DSPIx->CTRL1, DSPI_CR1_REFIFO);
784 }
785
786 /**
787 * @brief Master selection
788 *
789 * Register|BitsName
790 * --------|--------
791 * DSPI | MSTR
792 *
793 * @param DSPIx instance
794 */
795 __STATIC_INLINE void ll_dspi_master_select(dspi_regs_t *DSPIx)
796 {
797 SET_BITS(DSPIx->CTRL1, DSPI_CR1_MSTR);
798 }
799
800 /**
801 * @brief Last DMA transfer for transmission
802 * @note This bit is used in data packing mode, to define if the total number of data to transmit by
803 * DMA is odd or even. It has significance only if the TXDMAEN bit in the CTRL2 register is set and
804 * if packing mode is used (data length =< 8-bit and write access to DATA is 16-bit wide)
805 *
806 * Register|BitsName
807 * --------|--------
808 * CTRL2 | LDMA_TX
809 *
810 * @param DSPIx instance
811 * @param bid_mode This parameter can be one of the following values:
812 * @arg @ref LL_DSPI_DMA_LTX_EVEN
813 * @arg @ref LL_DSPI_DMA_LTX_ODD
814 * @retval None
815 */
816 __STATIC_INLINE void ll_dspi_set_last_dma_tx_packing(dspi_regs_t *DSPIx, uint32_t bid_mode)
817 {
818 MODIFY_REG(DSPIx->CTRL1, DSPI_CR2_LDMA_TX, bid_mode);
819 }
820
821 /**
822 * @brief Last DMA transfer for reception
823 * @note This bit is used in data packing mode, to define if the total number of data to receive
824 * by DMA is odd or even. It has significance only if the RXDMAEN bit in the CTRL2 register
825 * is set and if packing mode is used (data length =< 8-bit and write access to DATA is 16-bit wide)
826 *
827 * Register|BitsName
828 * --------|--------
829 * CTRL2 | LDMA_RX
830 *
831 * @param DSPIx instance
832 * @param bid_mode This parameter can be one of the following values:
833 * @arg @ref LL_DSPI_DMA_LRX_EVEN
834 * @arg @ref LL_DSPI_DMA_LRX_ODD
835 * @retval None
836 */
837 __STATIC_INLINE void ll_dspi_set_last_dma_rx_packing(dspi_regs_t *DSPIx, uint32_t bid_mode)
838 {
839 MODIFY_REG(DSPIx->CTRL2, DSPI_CR2_LDMA_RX, bid_mode);
840 }
841
842 /**
843 * @brief Enable DMA Tx
844 *
845 * Register|BitsName
846 * --------|--------
847 * CTRL2 | TXDMAEN
848 *
849 * @param DSPIx instance
850 * @retval None
851 */
852 __STATIC_INLINE void ll_dspi_enable_dma_tx(dspi_regs_t *DSPIx)
853 {
854 SET_BITS(DSPIx->CTRL2, DSPI_CR2_TXDMAEN);
855 }
856
857 /**
858 * @brief Disable DMA Tx
859 *
860 * Register|BitsName
861 * --------|--------
862 * CTRL2 | TXDMAEN
863 *
864 * @param DSPIx instance
865 * @retval None
866 */
867 __STATIC_INLINE void ll_dspi_disable_dma_tx(dspi_regs_t *DSPIx)
868 {
869 CLEAR_BITS(DSPIx->CTRL2, DSPI_CR2_TXDMAEN);
870 }
871
872 /**
873 * @brief Check if DMA Tx is enabled
874 *
875 * Register|BitsName
876 * --------|--------
877 * CTRL2 | TXDMAEN
878 *
879 * @param DSPIx instance
880 * @retval State of bit (1 or 0).
881 */
882 __STATIC_INLINE uint32_t ll_dspi_is_enabled_dma_tx(dspi_regs_t *DSPIx)
883 {
884 return (READ_BITS(DSPIx->CTRL2, DSPI_CR2_TXDMAEN) == (DSPI_CR2_TXDMAEN));
885 }
886
887 /**
888 * @brief Enable DMA Rx
889 *
890 * Register|BitsName
891 * --------|--------
892 * CTRL2 | RXDMAEN
893 *
894 * @param DSPIx instance
895 * @retval None
896 */
897 __STATIC_INLINE void ll_dspi_enable_dma_rx(dspi_regs_t *DSPIx)
898 {
899 SET_BITS(DSPIx->CTRL2, DSPI_CR2_RXDMAEN);
900 }
901
902 /**
903 * @brief Disable DMA Rx
904 *
905 * Register|BitsName
906 * --------|--------
907 * CTRL2 | RXDMAEN
908 *
909 * @param DSPIx instance
910 * @retval None
911 */
912 __STATIC_INLINE void ll_dspi_disable_dma_rx(dspi_regs_t *DSPIx)
913 {
914 CLEAR_BITS(DSPIx->CTRL2, DSPI_CR2_RXDMAEN);
915 }
916
917 /**
918 * @brief Check if DMA Rx is enabled
919 *
920 * Register|BitsName
921 * --------|--------
922 * CTRL2 | RXDMAEN
923 *
924 * @param DSPIx instance
925 * @retval State of bit (1 or 0).
926 */
927 __STATIC_INLINE uint32_t ll_dspi_is_enabled_dma_rx(dspi_regs_t *DSPIx)
928 {
929 return (READ_BITS(DSPIx->CTRL2, DSPI_CR2_RXDMAEN) == (DSPI_CR2_RXDMAEN));
930 }
931
932 /**
933 * @brief Value of Data-Versus-Command information
934 *
935 * Register|BitsName
936 * --------|--------
937 * MODE | DCX
938 *
939 * @param DSPIx instance
940 * @param dcx This parameter can be one of the following values:
941 * @arg @ref LL_DSPI_DCX_CMD
942 * @arg @ref LL_DSPI_DCX_DATA
943 * @retval None
944 */
945 __STATIC_INLINE void ll_dspi_set_dcx(dspi_regs_t *DSPIx, uint32_t dcx)
946 {
947 MODIFY_REG(DSPIx->MODE, DSPI_MODE_DCX, dcx);
948 }
949
950 /**
951 * @brief DSPI Protocol Mode
952 *
953 * Register|BitsName
954 * --------|--------
955 * MODE | SPIMODE
956 *
957 * @param DSPIx instance
958 * @param mode This parameter can be one of the following values:
959 * @arg @ref LL_DSPI_PROT_MODE_SPI
960 * @arg @ref LL_DSPI_PROT_MODE_3W1L
961 * @arg @ref LL_DSPI_PROT_MODE_4W1L
962 * @arg @ref LL_DSPI_PROT_MODE_4W2L
963 * @retval None
964 */
965 __STATIC_INLINE void ll_dspi_set_mode(dspi_regs_t *DSPIx, uint32_t mode)
966 {
967 MODIFY_REG(DSPIx->MODE, DSPI_MODE_SPIMODE, mode);
968 }
969
970 /**
971 * @brief Get DSPI Protocol Mode
972 *
973 * Register|BitsName
974 * --------|--------
975 * MODE | SPIMODE
976 *
977 * @param DSPIx instance
978 * @retval Returned value can be one of the following values:
979 * @arg @ref LL_DSPI_PROT_MODE_SPI
980 * @arg @ref LL_DSPI_PROT_MODE_3W1L
981 * @arg @ref LL_DSPI_PROT_MODE_4W1L
982 * @arg @ref LL_DSPI_PROT_MODE_4W2L
983 */
984 __STATIC_INLINE uint32_t ll_dspi_get_mode(dspi_regs_t *DSPIx)
985 {
986 return (READ_BITS(DSPIx->CTRL2, DSPI_MODE_SPIMODE));
987 }
988
989 /**
990 * @brief SS output enable
991 *
992 * Register|BitsName
993 * --------|--------
994 * CTRL2 | SSOE
995 *
996 * @param DSPIx instance
997 * @retval None
998 */
999 __STATIC_INLINE void ll_dspi_ss_out_enable(dspi_regs_t *DSPIx)
1000 {
1001 SET_BITS(DSPIx->CTRL2, DSPI_CR2_SSOE);
1002 }
1003
1004 /**
1005 * @brief Enable interrupt
1006 * @note This bit controls the generation of an interrupt when an event occurs.
1007 *
1008 * Register|BitsName
1009 * --------|--------
1010 * CTRL2 | INTMASK
1011 *
1012 * @param DSPIx instance
1013 * @param mask This parameter can be one of the following values:
1014 * @arg @ref LL_DSPI_IM_TXE
1015 * @arg @ref LL_DSPI_IM_RXNE
1016 * @arg @ref LL_DSPI_IM_ER
1017 * @retval None
1018 */
1019 __STATIC_INLINE void ll_dspi_enable_it(dspi_regs_t *DSPIx, uint32_t mask)
1020 {
1021 SET_BITS(DSPIx->CTRL2, mask);
1022 }
1023
1024 /**
1025 * @brief Disable interrupt
1026 * @note This bit controls the generation of an interrupt when an event occurs.
1027 *
1028 * Register|BitsName
1029 * --------|--------
1030 * CTRL2 | INTMASK
1031 *
1032 * @param DSPIx instance
1033 * @param mask This parameter can be one of the following values:
1034 * @arg @ref LL_DSPI_IM_TXE
1035 * @arg @ref LL_DSPI_IM_RXNE
1036 * @arg @ref LL_DSPI_IM_ER
1037 * @retval None
1038 */
1039 __STATIC_INLINE void ll_dspi_disable_it(dspi_regs_t *DSPIx, uint32_t mask)
1040 {
1041 CLEAR_BITS(DSPIx->CTRL2, mask);
1042 }
1043
1044 /**
1045 * @brief Check if interrupt is enabled
1046 *
1047 * Register|BitsName
1048 * --------|--------
1049 * CTRL2 | INTMASK
1050 *
1051 * @param DSPIx instance
1052 * @param mask This parameter can be one of the following values:
1053 * @arg @ref LL_DSPI_IM_TXE
1054 * @arg @ref LL_DSPI_IM_RXNE
1055 * @arg @ref LL_DSPI_IM_ER
1056 * @retval State of bit (1 or 0).
1057 */
1058 __STATIC_INLINE uint32_t ll_dspi_is_enabled_it(dspi_regs_t *DSPIx, uint32_t mask)
1059 {
1060 return (READ_BITS(DSPIx->CTRL2, mask) == mask);
1061 }
1062
1063 /**
1064 * @brief Get DSPI status
1065 *
1066 * Register|BitsName
1067 * --------|--------
1068 * STAT | STAT
1069 *
1070 * @param DSPIx instance
1071 * @retval Returned value can be one or combination of the following values:
1072 * @arg @ref LL_DSPI_SR_FFE
1073 * @arg @ref LL_DSPI_SR_BUSY
1074 * @arg @ref LL_DSPI_SR_OVR
1075 * @arg @ref LL_DSPI_SR_MODF
1076 * @arg @ref LL_DSPI_SR_TFE
1077 * @arg @ref LL_DSPI_SR_RFNE
1078 */
1079 __STATIC_INLINE uint32_t ll_dspi_get_status(dspi_regs_t *DSPIx)
1080 {
1081 return (uint32_t)(READ_REG(DSPIx->STAT) & LL_DSPI_SR_ALL);
1082 }
1083
1084 /**
1085 * @brief Check active flag
1086 *
1087 * Register|BitsName
1088 * --------|--------
1089 * STAT | FFE
1090 * STAT | BUSY
1091 * STAT | OVR
1092 * STAT | MODF
1093 * STAT | TFE
1094 * STAT | TFNF
1095 *
1096 * @param DSPIx instance
1097 * @param flag This parameter can be one of the following values:
1098 * @arg @ref LL_DSPI_SR_FFE
1099 * @arg @ref LL_DSPI_SR_BUSY
1100 * @arg @ref LL_DSPI_SR_OVR
1101 * @arg @ref LL_DSPI_SR_MODF
1102 * @arg @ref LL_DSPI_SR_TFE
1103 * @arg @ref LL_DSPI_SR_RFNE
1104 * @retval State of bit (1 or 0).
1105 */
1106 __STATIC_INLINE uint32_t ll_dspi_is_active_flag(dspi_regs_t *DSPIx, uint32_t flag)
1107 {
1108 return (READ_BITS(DSPIx->STAT, flag) == (flag));
1109 }
1110
1111 /**
1112 * @brief Get DSPI interrupt flags
1113 *
1114 * Register|BitsName
1115 * --------|--------
1116 * INTSTAT | INTSTAT
1117 *
1118 * @param DSPIx instance
1119 * @retval Returned value can be one or combination of the following values:
1120 * @arg @ref LL_DSPI_SR_FFE
1121 * @arg @ref LL_DSPI_SR_BUSY
1122 * @arg @ref LL_DSPI_SR_OVR
1123 * @arg @ref LL_DSPI_SR_MODF
1124 * @arg @ref LL_DSPI_SR_TFE
1125 * @arg @ref LL_DSPI_SR_RFNE
1126 */
1127 __STATIC_INLINE uint32_t ll_dspi_get_it_flag(dspi_regs_t *DSPIx)
1128 {
1129 return (uint32_t)(READ_REG(DSPIx->STAT) & LL_DSPI_SR_ALL);
1130 }
1131
1132 /**
1133 * @brief Check interrupt flag
1134 *
1135 * Register|BitsName
1136 * --------|--------
1137 * INTSTAT | FFE
1138 * INTSTAT | BUSY
1139 * INTSTAT | OVR
1140 * INTSTAT | MODF
1141 * INTSTAT | TFE
1142 * INTSTAT | RFNE
1143 *
1144 * @param DSPIx instance
1145 * @param flag This parameter can be one of the following values:
1146 * @arg @ref LL_DSPI_SR_FFE
1147 * @arg @ref LL_DSPI_SR_BUSY
1148 * @arg @ref LL_DSPI_SR_OVR
1149 * @arg @ref LL_DSPI_SR_MODF
1150 * @arg @ref LL_DSPI_SR_TFE
1151 * @arg @ref LL_DSPI_SR_RFNE
1152 * @retval State of bit (1 or 0).
1153 */
1154 __STATIC_INLINE uint32_t ll_dspi_is_it_flag(dspi_regs_t *DSPIx, uint32_t flag)
1155 {
1156 return (READ_BITS(DSPIx->STAT, flag) == flag);
1157 }
1158 /** @} */
1159
1160 /** @defgroup DSPI_LL_EF_Init DSPI Initialization and de-initialization functions
1161 * @{
1162 */
1163
1164 /**
1165 * @brief De-initialize DSPI registers (Registers restored to their default values).
1166 * @param DSPIx instance
1167 * @retval An error_status_t enumeration value:
1168 * - SUCCESS: DSPIx registers are de-initialized
1169 * - ERROR: DSPIx registers are not de-initialized
1170 */
1171 error_status_t ll_dspi_deinit(dspi_regs_t *DSPIx);
1172
1173 /**
1174 * @brief Initialize DSPI registers according to the specified
1175 * parameters in p_dspi_init.
1176 * @param DSPIx instance
1177 * @param p_dspi_init Pointer to a ll_dspi_init_t structure that contains the configuration
1178 * information for the specified DSPI peripheral.
1179 * @retval An error_status_t enumeration value:
1180 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1181 * - ERROR: Problem occurred during SSI Registers initialization
1182 */
1183 error_status_t ll_dspi_init(dspi_regs_t *DSPIx, ll_dspi_init_t *p_dspi_init);
1184
1185 /**
1186 * @brief Set each field of a @ref ll_dspi_init_t type structure to default value.
1187 * @param p_dspi_init Pointer to a @ref ll_dspi_init_t structure
1188 * whose fields will be set to default values.
1189 * @retval None
1190 */
1191 void ll_dspi_struct_init(ll_dspi_init_t *p_dspi_init);
1192
1193 /** @} */
1194
1195 /** @} */
1196
1197 #endif /* DSPI */
1198
1199 #ifdef __cplusplus
1200 }
1201 #endif
1202
1203 #endif /* __GR55XX_LL_DSPI_H__ */
1204
1205 /** @} */
1206
1207 /** @} */
1208
1209 /** @} */
1210