gr55xx_ll_rtc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_rtc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CALENDAR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_RTC RTC
47 * @brief RTC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_RTC_H__
53 #define __GR55XX_LL_RTC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 /**
63 * @defgroup RTC_LL_MACRO Defines
64 * @{
65 */
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
68 * @{
69 */
70 /** @defgroup RTC_LL_EC_CLOCK_DIV Clock divider
71 * @{
72 */
73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U) /**< Select SLP_CLK */
74 #define LL_RTC_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
75 #define LL_RTC_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
76 #define LL_RTC_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
77 #define LL_RTC_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
78 #define LL_RTC_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos) /**< Select 1/64 divider */
79 #define LL_RTC_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos) /**< Select 1/128 divider */
80 #define LL_RTC_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos) /**< Select 1/256 divider */
81 /** @} */
82
83 /** @defgroup AON_CTL_RTC_TIMER_CLK_SEL RTC Timer clock select defines
84 * @{
85 */
86 #define LL_RTC_TIMER_CLK_SEL_RNG (0x0U << RTC_CLK_SEL_Pos) /**< Select RNG clcok source */
87 #define LL_RTC_TIMER_CLK_SEL_XO (0x1U << RTC_CLK_SEL_Pos) /**< Select XO clcok source */
88 #define LL_RTC_TIMER_CLK_SEL_RNG2 (0x2U << RTC_CLK_SEL_Pos) /**< Select RNG2 clcok source */
89 #define LL_RTC_TIMER_CLK_SEL_RTC (0x3U << RTC_CLK_SEL_Pos) /**< Select RTC clcok source */
90 /** @} */
91
92 /** @defgroup AON_CTL_RTC_TIMER_PERIODIC_SEL RTC Periodic timer select defines
93 * @{
94 */
95 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U) /**< Select periodic alarm one-time */
96 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U) /**< Select periodic alarm auto-reload */
97 /** @} */
98
99 /** @defgroup RTC_READ_CONFIG RTC CFG0 register read defines
100 * @{
101 */
102 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
103 RTC_CFG0_ALARM_EN | \
104 RTC_CFG0_TICK_EN | \
105 RTC_CFG0_TICK_MDOE))
106 /** @} */
107
108 /** @} */
109
110 /** @} */
111
112 /* Exported functions --------------------------------------------------------*/
113 /** @defgroup RTC_LL_DRIVER_FUNCTIONS Functions
114 * @{
115 */
116
117 /** @defgroup RTC_LL_EF_Configuration Configuration functions
118 * @{
119 */
120 /**
121 * @brief Set the RTC Timer clock
122 *
123 * Register|BitsName
124 * --------|--------
125 * RTC_CLK | RTC_timer_clk_sel
126 *
127 * @param RTCx instance
128 * @param value This parameter can be a one of the following values:
129 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG
130 * @arg @ref LL_RTC_TIMER_CLK_SEL_XO
131 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG2
132 * @arg @ref LL_RTC_TIMER_CLK_SEL_RTC
133 * @retval None
134 */
135 __STATIC_INLINE void ll_rtc_timer_set_clk(rtc_regs_t* RTCx,uint32_t value)
136 {
137 MODIFY_REG(RTCx->CLK, RTC_CLK_SEL, value);
138 }
139
140 /**
141 * @brief Get the RTC Timer clock
142 *
143 * Register|BitsName
144 * --------|--------
145 * RTC_CLK | RTC_timer_clk_sel
146 *
147 * @param RTCx instance
148 * @retval RTC Timer clock source,the value can be the one of the following:
149 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG
150 * @arg @ref LL_RTC_TIMER_CLK_SEL_XO
151 * @arg @ref LL_RTC_TIMER_CLK_SEL_RNG2
152 * @arg @ref LL_RTC_TIMER_CLK_SEL_RTC
153 */
154 __STATIC_INLINE uint32_t ll_rtc1_timer_get_clk(rtc_regs_t* RTCx)
155 {
156 return (READ_BITS(RTCx->CLK, RTC_CLK_SEL));
157 }
158
159 /**
160 * @brief Enable RTC counter.
161 *
162 * Register|BitsName
163 * --------|--------
164 * RTC_CFG0 | EN
165 *
166 * @param RTCx instance
167 * @retval None
168 */
169 __STATIC_INLINE void ll_rtc_enable(rtc_regs_t* RTCx)
170 {
171 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
172 }
173
174 /**
175 * @brief Disable RTC counter.
176 *
177 * Register|BitsName
178 * --------|--------
179 * RTC_CFG0 | EN
180 *
181 * @param RTCx instance
182 * @retval None
183 */
184 __STATIC_INLINE void ll_rtc_disable(rtc_regs_t* RTCx)
185 {
186 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
187 }
188
189 /**
190 * @brief Check if the RTC peripheral is enabled or disabled.
191 *
192 * Register|BitsName
193 * --------|--------
194 * RTC_CFG0 | EN
195 *
196 * @param RTCx instance
197 * @retval State of bit (1 or 0).
198 */
199 __STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t* RTCx)
200 {
201 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
202 }
203
204 /**
205 * @brief Reloads RTC counter.
206 *
207 * Register|BitsName
208 * --------|--------
209 * RTC_TIMER_W | TIMER_VALUE
210 *
211 * @param RTCx instance
212 * @param counter RTC counter
213 * @retval None
214 */
215 __STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t* RTCx, uint32_t counter)
216 {
217 WRITE_REG(RTCx->TIMER_W, counter);
218 }
219
220 /**
221 * @brief Reloads RTC counter and request.
222 *
223 * Register|BitsName
224 * --------|--------
225 * RTC_TIMER_W | TIMER_VALUE
226 * RTC_CFG0 | VAL_LOAD
227 *
228 * @param RTCx instance
229 * @param start_value RTC counter
230 * @retval None
231 */
232 __STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t* RTCx, uint32_t start_value)
233 {
234 WRITE_REG(RTCx->TIMER_W, start_value);
235 SET_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
236 }
237
238 /**
239 * @brief Clear RTC counter
240 *
241 * Register|BitsName
242 * --------|--------
243 * RTC_CFG0 | VAL_LOAD
244 *
245 * @param RTCx instance
246 * @retval None
247 */
248 __STATIC_INLINE void ll_rtc_clear_counter_set(rtc_regs_t* RTCx)
249 {
250 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
251 }
252
253 // /**
254 // * @brief Reloads RTC alarm.
255 // *
256 // * Register|BitsName
257 // * --------|--------
258 // * RTC_TIMER_W | ALARM_VAL_LOAD
259 // *
260 // * @retval None
261 // */
262 //__STATIC_INLINE void ll_rtc_set_alarm_value(rtc_regs_t* RTCx, uint32_t value)
263 //{
264 // WRITE_REG(RTCx->ALARM_W, value);
265 // CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
266 // SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET);
267 //}
268
269 /**
270 * @brief Reloads RTC alarm and request.
271 *
272 * Register|BitsName
273 * --------|--------
274 * RTC_ALARM_W | ALARM_VAL_LOAD
275 * RTC_CFG0 | ALARM_VALUE
276 *
277 * @param RTCx instance
278 * @param alarm_value RTC alarm
279 * @retval None
280 */
281 __STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t* RTCx, uint32_t alarm_value)
282 {
283 WRITE_REG(RTCx->ALARM_W, alarm_value);
284 SET_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
285 }
286
287 /**
288 * @brief Reloads RTC perd_alarm.
289 *
290 * Register|BitsName
291 * --------|--------
292 * RTC_TIMER_W | ALARM_VAL_LOAD
293 *
294 * @param RTCx instance
295 * @param tick RTC perd_alarm
296 * @retval None
297 */
298 __STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t* RTCx, uint32_t tick)
299 {
300 WRITE_REG(RTCx->TICK_W, tick);
301 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
302 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET);
303 }
304
305 /**
306 * @brief Read the RTC counter config value.
307 *
308 * Register|BitsName
309 * --------|--------
310 * RTC_TIMER_W | TIMER_VAL_READ
311 *
312 * @param RTCx instance
313 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
314 */
315 __STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t* RTCx)
316 {
317 return (uint32_t)READ_REG(RTCx->TIMER_W);
318 }
319
320 /**
321 * @brief Read the RTC counter current value.
322 *
323 * Register|BitsName
324 * --------|--------
325 * RTC_TIMER_R | TIMER_VAL_READ
326 *
327 * @param RTCx instance
328 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
329 */
330 __STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t* RTCx)
331 {
332 return (uint32_t)READ_REG(RTCx->TIMER_R);
333 }
334
335 /**
336 * @brief Read the RTC counter config alarm value.
337 *
338 * Register|BitsName
339 * --------|--------
340 * RTC_ALARM_W | CAL_ALARM
341 *
342 * @param RTCx instance
343 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
344 */
345 __STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t* RTCx)
346 {
347 return (uint32_t)READ_REG(RTCx->ALARM_W);
348 }
349
350 /**
351 * @brief Read the RTC counter current alarm value.
352 *
353 * Register|BitsName
354 * --------|--------
355 * RTC_ALARM_R | CAL_ALARM
356 *
357 * @param RTCx instance
358 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
359 */
360 __STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t* RTCx)
361 {
362 return (uint32_t)READ_REG(RTCx->ALARM_R);
363 }
364
365 /**
366 * @brief Get RTC write tick.
367 *
368 * Register|BitsName
369 * --------|--------
370 * RTCx_TIMER_W | TIMER_VALUE
371 *
372 * @param RTCx instance
373 * @retval Value for current write tick
374 */
375 __STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t* RTCx)
376 {
377 return (uint32_t)READ_REG(RTCx->TICK_W);
378 }
379
380 /**
381 * @brief Get RTC read tick.
382 *
383 * Register|BitsName
384 * --------|--------
385 * RTCx_TIMER_W | TIMER_VALUE
386 *
387 * @param RTCx instance
388 * @retval Value for current read tick
389 */
390 __STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t* RTCx)
391 {
392 return (uint32_t)READ_REG(RTCx->TICK_R);
393 }
394
395 /**
396 * @brief Get the RTC wrap-around value.
397 * @note The value should be read multiple times until get the same value in at least two reads.
398 *
399 * Register|BitsName
400 * --------|--------
401 * RTC_STAT | WRAP_CNT
402 *
403 * @param RTCx instance
404 * @retval Value between Min_Data=0 and Max_Data=0xF
405 */
406 __STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t* RTCx)
407 {
408 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
409 }
410
411 /**
412 * @brief The RTC is busy.
413 *
414 * Register|BitsName
415 * --------|--------
416 * RTC_STAT | BUSY
417 *
418 * @param RTCx instance
419 * @retval Value between Min_Data=0 and Max_Data=0xF
420 */
421 __STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t* RTCx)
422 {
423 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
424 }
425
426 /**
427 * @brief The RTC is running.
428 *
429 * Register|BitsName
430 * --------|--------
431 * RTC_STAT | RUNNING
432 *
433 * @param RTCx instance
434 * @retval Value between Min_Data=0 and Max_Data=0xF
435 */
436 __STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t* RTCx)
437 {
438 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
439 }
440
441 /**
442 * @brief CLear RTC wrap.
443 *
444 * Register|BitsName
445 * --------|--------
446 * RTC_CFG0 | Wrap counter clear
447 *
448 * @param RTCx instance
449 * @retval None
450 */
451
452 __STATIC_INLINE void ll_rtc_clear_wrap(rtc_regs_t* RTCx)
453 {
454 SET_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
455 }
456
457 __STATIC_INLINE void ll_rtc_clear_wrap_set(rtc_regs_t* RTCx)
458 {
459 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
460 }
461
462 /**
463 * @brief Select the RTC clock divider.
464 *
465 * Register|BitsName
466 * --------|--------
467 * RTC_CFG1 | CLK_SEL
468 *
469 * @param RTCx instance
470 * @param div This parameter can be one of the following values:
471 * @arg @ref LL_RTC_DIV_NONE
472 * @arg @ref LL_RTC_DIV_2
473 * @arg @ref LL_RTC_DIV_4
474 * @arg @ref LL_RTC_DIV_8
475 * @arg @ref LL_RTC_DIV_16
476 * @arg @ref LL_RTC_DIV_32
477 * @arg @ref LL_RTC_DIV_64
478 * @arg @ref LL_RTC_DIV_128
479 * @retval None
480 */
481 __STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t* RTCx, uint32_t div)
482 {
483 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
484 }
485
486 /**
487 * @brief Set RTC alarm.
488 *
489 * Register|BitsName
490 * --------|--------
491 * RTC_TIMER_CTL | ALARM_EN
492 *
493 * @param RTCx instance
494 * @param value RTC alarm
495 * @retval None
496 */
497 __STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t* RTCx,uint32_t value)
498 {
499 WRITE_REG(RTCx->ALARM_W, value);
500 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET);
501 }
502
503 __STATIC_INLINE void ll_rtc_clear_alarm_set(rtc_regs_t* RTCx)
504 {
505 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
506 }
507
508 /**
509 * @brief Enable RTC alarm interrupt.
510 *
511 * Register|BitsName
512 * --------|--------
513 * RTC_TIMER_CTL | ALARM_INT_EN
514 *
515 * @param RTCx instance
516 * @retval None
517 */
518 __STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t* RTCx)
519 {
520 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
521 }
522
523 /**
524 * @brief Disable RTC alarm.
525 *
526 * Register|BitsName
527 * --------|--------
528 * RTC_TIMER_CTL | ALARM_DISBALE
529 *
530 * @param RTCx instance
531 * @retval None
532 */
533 __STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t* RTCx)
534 {
535 CLEAR_BITS(RTCx->CFG0,RTC_CFG0_ALARM_SET | RTC_CFG0_ALARM_EN);
536 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
537 }
538
539 /**
540 * @brief Disable RTC alarm interrupt.
541 *
542 * Register|BitsName
543 * --------|--------
544 * RTC_INT_EN | ALARM_INT_EN
545 *
546 * @param RTCx instance
547 * @retval None
548 */
549 __STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t* RTCx)
550 {
551 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
552 }
553
554 /**
555 * @brief Check if the RTC alarm interrupt is enabled or disabled.
556 *
557 * Register|BitsName
558 * --------|--------
559 * RTC_TIMER_CTL | ALARM_INT_EN
560 *
561 * @param RTCx instance
562 * @retval State of bit (1 or 0).
563 */
564 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t* RTCx)
565 {
566 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
567 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
568 }
569
570 /**
571 * @brief Set RTCx tick mode.
572 *
573 * Register|BitsName
574 * --------|--------
575 * RTCx_TIMER_CTL | TICK_EN
576 *
577 * @param RTCx instance
578 * @retval None
579 */
580 __STATIC_INLINE void ll_rtc_enable_tick(rtc_regs_t* RTCx)
581 {
582 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
583 SET_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
584 }
585
586 /**
587 * @brief Set RTCx alarm_mode.
588 *
589 * Register|BitsName
590 * --------|--------
591 * RTCx_TIMER_CTL | TICK_EN
592 *
593 * @param RTCx instance
594 * @param tick_mode This parameter can be a one of the following values:
595 * LL_RTCx_TIMER_TICK_TYPE_SINGLE
596 * LL_RTCx_TIMER_TICK_TYPE_AUTO
597 * @retval None
598 */
599 __STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t* RTCx, uint8_t tick_mode)
600 {
601 if(0 == tick_mode)
602 {
603 CLEAR_BITS(RTCx->CFG0,((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
604 }
605 else
606 {
607 SET_BITS(RTCx->CFG0,(tick_mode << RTC_CFG0_TICK_MDOE_Pos));
608 }
609 }
610
611 /**
612 * @brief Enable RTC tick interrupt.
613 *
614 * Register|BitsName
615 * --------|--------
616 * RTC_INT_EN | TICK_INT_EN
617 *
618 * @param RTCx instance
619 * @retval None
620 */
621 __STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t* RTCx)
622 {
623 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
624 }
625
626 /**
627 * @brief Disable RTCx tick.
628 *
629 * Register|BitsName
630 * --------|--------
631 * RTCx_TIMER_CTL | TICK_EN
632 *
633 * @param RTCx instance
634 * @retval None
635 */
636 __STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t* RTCx)
637 {
638 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
639 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
640 }
641
642 /**
643 * @brief Disable RTC tick interrupt.
644 *
645 * Register|BitsName
646 * --------|--------
647 * RTC_INT_EN | TICK0_INT_EN
648 *
649 * @param RTCx instance
650 * @retval None
651 */
652 __STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t* RTCx)
653 {
654 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
655 }
656
657 /**
658 * @brief Check if the RTC alarm interrupt is enabled or disabled.
659 *
660 * Register|BitsName
661 * --------|--------
662 * RTC_TIMER_CTL | TICK_EN
663 * RTC_INT_EN | TICK_INT_EN
664 *
665 * @param RTCx instance
666 * @retval State of bit (1 or 0).
667 */
668 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t* RTCx)
669 {
670 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
671 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
672 }
673
674 /**
675 * @brief Reloads RTCx tick counter and request.
676 *
677 * Register|BitsName
678 * --------|--------
679 * RTCx_TIMER_W | TIMER_VALUE
680 * RTCx_CFG0 | VAL_LOAD
681 *
682 * @param RTCx instance
683 * @param tick_reload RTC tick counter
684 * @retval None
685 */
686 __STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t* RTCx, uint32_t tick_reload)
687 {
688 WRITE_REG(RTCx->TICK_W, tick_reload);
689 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET);
690 }
691
692 /**
693 * @brief Restart RTCx tick counter and request.
694 *
695 * Register|BitsName
696 * --------|--------
697 * RTCx_CFG0 | RTC_CFG0_TICK_EN
698 *
699 * @param RTCx instance
700 * @retval None
701 */
702 __STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t* RTCx)
703 {
704 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET); /* clear alarm setting bit to avoid alarm value setting*/
705 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN);
706 }
707
708 /**
709 * @brief Disable RTCx tick value setting.
710 *
711 * Register|BitsName
712 * --------|--------
713 * RTCx_CFG0 | RTC_CFG0_TICK_EN
714 *
715 * @param RTCx instance
716 * @retval None
717 */
718 __STATIC_INLINE void ll_rtc_clear_tick_set(rtc_regs_t* RTCx)
719 {
720 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
721 }
722
723 /**
724 * @brief Enable RTC wrap interrupt.
725 *
726 * Register|BitsName
727 * --------|--------
728 * RTC_TIMER_CTL | WRAP_INT_EN
729 *
730 * @param RTCx instance
731 * @retval None
732 */
733 __STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t* RTCx)
734 {
735 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
736 }
737
738 /**
739 * @brief Disable RTC wrap interrupt.
740 *
741 * Register|BitsName
742 * --------|--------
743 * RTC_TIMER_CTL | WRAP_INT_EN
744 *
745 * @param RTCx instance
746 * @retval None
747 */
748 __STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t* RTCx)
749 {
750 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
751 }
752
753 /**
754 * @brief Check if the RTC wrap interrupt is enabled or disabled.
755 *
756 * Register|BitsName
757 * --------|--------
758 * RTC_TIMER_CTL | WRAP_INT_EN
759 *
760 * @param RTCx instance
761 * @retval State of bit (1 or 0).
762 */
763 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t* RTCx)
764 {
765 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
766 }
767
768 /** @} */
769
770 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
771 * @{
772 */
773
774 /**
775 * @brief Indicate if the RTC alarm event flag is set or not.
776 * @note This bit is set by hardware when the counter has reached alarm value.
777 * It can be cleared by writing 0 to this bit.
778 *
779 * Register|BitsName
780 * --------|--------
781 * SLP_EVENT | RTC_TIMER_ALARM
782 *
783 * @param RTCx instance
784 * @retval State of bit (1 or 0).
785 */
786 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t* RTCx)
787 {
788 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
789 }
790
791 /**
792 * @brief Indicate if the RTC wrap event flag is set or not.
793 * @note This bit is set by hardware when the counter has overflow.
794 * It can be cleared by writing 0 to this bit.
795 *
796 * Register|BitsName
797 * --------|--------
798 * SLP_EVENT | CALENDAR_TIMER_WRAP
799 *
800 * @param RTCx instance
801 * @retval State of bit (1 or 0).
802 */
803 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t* RTCx)
804 {
805 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
806 }
807
808 /**
809 * @brief Indicate if the RTC tick event flag is set or not.
810 * @note This bit is set by hardware when the counter has reached to 0.
811 * It can be cleared by writing 1 to this bit.
812 *
813 * Register|BitsName
814 * --------|--------
815 * RTC_INT_STAT | TICK_INT_STAT
816 *
817 * @param RTCx instance
818 * @retval State of bit (1 or 0).
819 */
820 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t* RTCx)
821 {
822 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
823 }
824
825 /**
826 * @brief Clear RTC alarm interrupt flag.
827 *
828 * Register|BitsName
829 * --------|--------
830 * SLP_EVENT| RTC_TIMER_ALARM
831 *
832 * @param RTCx instance
833 * @retval None
834 */
835 __STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t* RTCx)
836 {
837 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
838 }
839
840 /**
841 * @brief Clear RTC wrap interrupt flag.
842 *
843 * Register|BitsName
844 * --------|--------
845 * RTC_INT_STAT| RTC_TICK
846 *
847 * @param RTCx instance
848 * @retval None
849 */
850 __STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t* RTCx)
851 {
852 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
853 }
854
855
856 /**
857 * @brief Clear RTC tick interrupt flag.
858 *
859 * Register|BitsName
860 * --------|--------
861 * SLP_EVENT| RTC_TIMER_WRAP
862 *
863 * @param RTCx instance
864 * @retval None
865 */
866 __STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t* RTCx)
867 {
868 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
869 }
870
871 __STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t* RTCx)
872 {
873 if(RTCx == CALENDAR)
874 {
875 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
876 }
877 else if(RTCx == RTC1)
878 {
879 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
880 }
881 }
882
883 __STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t* RTCx)
884 {
885 if(RTCx == CALENDAR)
886 {
887 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
888 }
889 else if(RTCx == RTC1)
890 {
891 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
892 }
893 }
894
895 /**
896 * @brief Enable RTC alarm wakeup interrupt.
897 *
898 * Register|BitsName
899 * --------|--------
900 * AON_MISC | MCU_WAKEUP_CTRL
901 *
902 * @param RTCx instance
903 * @retval None
904 */
905 __STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t* RTCx)
906 {
907 if(RTCx == CALENDAR)
908 {
909 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
910 }
911 else if(RTCx == RTC1)
912 {
913 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
914 }
915 }
916
917 /**
918 * @brief Disable RTC alarm wakeup interrupt.
919 *
920 * Register|BitsName
921 * --------|--------
922 * AON_MISC | MCU_WAKEUP_CTRL
923 *
924 * @param RTCx instance
925 * @retval None
926 */
927 __STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t* RTCx)
928 {
929 if(RTCx == CALENDAR)
930 {
931 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
932 }
933 else if(RTCx == RTC1)
934 {
935 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
936 }
937 }
938
939 /** @} */
940
941 /** @} */
942
943
944 #ifdef __cplusplus
945 }
946 #endif
947
948 #endif /* __GR55XX_LL_RTC_H__ */
949
950 /** @} */
951
952 /** @} */
953
954 /** @} */
ll_rtc_it_is_enabled_tick
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:668
ll_rtc_is_running
__STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t *RTCx)
The RTC is running.
Definition: gr55xx_ll_rtc.h:436
ll_rtc_disable_tick
__STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t *RTCx)
Disable RTCx tick.
Definition: gr55xx_ll_rtc.h:636
ll_rtc_reload_counter
__STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t *RTCx, uint32_t counter)
Reloads RTC counter.
Definition: gr55xx_ll_rtc.h:215
ll_rtc_get_wrapcnt
__STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t *RTCx)
Get the RTC wrap-around value.
Definition: gr55xx_ll_rtc.h:406
ll_rtc_enable_tick
__STATIC_INLINE void ll_rtc_enable_tick(rtc_regs_t *RTCx)
Set RTCx tick mode.
Definition: gr55xx_ll_rtc.h:580
ll_rtc_is_active_flag_alarm
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t *RTCx)
Indicate if the RTC alarm event flag is set or not.
Definition: gr55xx_ll_rtc.h:786
ll_rtc_get_write_alarm
__STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t *RTCx)
Read the RTC counter config alarm value.
Definition: gr55xx_ll_rtc.h:345
ll_rtc_get_read_counter
__STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t *RTCx)
Read the RTC counter current value.
Definition: gr55xx_ll_rtc.h:330
ll_rtc_is_busy
__STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t *RTCx)
The RTC is busy.
Definition: gr55xx_ll_rtc.h:421
ll_rtc_clear_counter_set
__STATIC_INLINE void ll_rtc_clear_counter_set(rtc_regs_t *RTCx)
Clear RTC counter.
Definition: gr55xx_ll_rtc.h:248
ll_rtc_clear_alarm_set
__STATIC_INLINE void ll_rtc_clear_alarm_set(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:503
ll_rtc_clear_tick_it_event
__STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:883
ll_rtc1_timer_get_clk
__STATIC_INLINE uint32_t ll_rtc1_timer_get_clk(rtc_regs_t *RTCx)
Get the RTC Timer clock.
Definition: gr55xx_ll_rtc.h:154
ll_rtc_it_is_enabled_alarm
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:564
ll_rtc_it_disable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t *RTCx)
Disable RTC alarm wakeup interrupt.
Definition: gr55xx_ll_rtc.h:927
ll_rtc_clear_tick_set
__STATIC_INLINE void ll_rtc_clear_tick_set(rtc_regs_t *RTCx)
Disable RTCx tick value setting.
Definition: gr55xx_ll_rtc.h:718
ll_rtc_enable
__STATIC_INLINE void ll_rtc_enable(rtc_regs_t *RTCx)
Enable RTC counter.
Definition: gr55xx_ll_rtc.h:169
ll_rtc_it_enable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t *RTCx)
Enable RTC alarm wakeup interrupt.
Definition: gr55xx_ll_rtc.h:905
ll_rtc_clear_flag_tick
__STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t *RTCx)
Clear RTC tick interrupt flag.
Definition: gr55xx_ll_rtc.h:866
ll_rtc_clear_it_event
__STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:871
ll_rtc_it_enable_tick
__STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t *RTCx)
Enable RTC tick interrupt.
Definition: gr55xx_ll_rtc.h:621
ll_rtc_it_is_enabled_wrap
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t *RTCx)
Check if the RTC wrap interrupt is enabled or disabled.
Definition: gr55xx_ll_rtc.h:763
ll_rtc_it_enable_wrap
__STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t *RTCx)
Enable RTC wrap interrupt.
Definition: gr55xx_ll_rtc.h:733
ll_rtc_clear_flag_wrap
__STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t *RTCx)
Clear RTC wrap interrupt flag.
Definition: gr55xx_ll_rtc.h:850
ll_rtc_is_enabled
__STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t *RTCx)
Check if the RTC peripheral is enabled or disabled.
Definition: gr55xx_ll_rtc.h:199
ll_rtc_get_write_counter
__STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t *RTCx)
Read the RTC counter config value.
Definition: gr55xx_ll_rtc.h:315
ll_rtc_it_disable_wrap
__STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t *RTCx)
Disable RTC wrap interrupt.
Definition: gr55xx_ll_rtc.h:748
ll_rtc_is_active_flag_wrap
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t *RTCx)
Indicate if the RTC wrap event flag is set or not.
Definition: gr55xx_ll_rtc.h:803
ll_rtc_set_alarm
__STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t *RTCx, uint32_t value)
Set RTC alarm.
Definition: gr55xx_ll_rtc.h:497
ll_rtc_it_disable_alarm
__STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm interrupt.
Definition: gr55xx_ll_rtc.h:549
ll_rtc_alarm_value_set_and_request
__STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t *RTCx, uint32_t alarm_value)
Reloads RTC alarm and request.
Definition: gr55xx_ll_rtc.h:281
ll_rtc_it_enable_alarm
__STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t *RTCx)
Enable RTC alarm interrupt.
Definition: gr55xx_ll_rtc.h:518
ll_rtc_get_read_alarm
__STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t *RTCx)
Read the RTC counter current alarm value.
Definition: gr55xx_ll_rtc.h:360
ll_rtc_get_read_tick
__STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t *RTCx)
Get RTC read tick.
Definition: gr55xx_ll_rtc.h:390
ll_rtc_set_tick_mode
__STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t *RTCx, uint8_t tick_mode)
Set RTCx alarm_mode.
Definition: gr55xx_ll_rtc.h:599
ll_rtc_get_write_tick
__STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t *RTCx)
Get RTC write tick.
Definition: gr55xx_ll_rtc.h:375
ll_rtc_is_active_flag_tick
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t *RTCx)
Indicate if the RTC tick event flag is set or not.
Definition: gr55xx_ll_rtc.h:820
ll_rtc_set_clock_div
__STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t *RTCx, uint32_t div)
Select the RTC clock divider.
Definition: gr55xx_ll_rtc.h:481
ll_rtc_restart_tick
__STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t *RTCx)
Restart RTCx tick counter and request.
Definition: gr55xx_ll_rtc.h:702
ll_rtc_disable_alarm
__STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm.
Definition: gr55xx_ll_rtc.h:533
ll_rtc_reload_tick
__STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t *RTCx, uint32_t tick)
Reloads RTC perd_alarm.
Definition: gr55xx_ll_rtc.h:298
ll_rtc_start_value_set_and_request
__STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t *RTCx, uint32_t start_value)
Reloads RTC counter and request.
Definition: gr55xx_ll_rtc.h:232
ll_rtc_timer_set_clk
__STATIC_INLINE void ll_rtc_timer_set_clk(rtc_regs_t *RTCx, uint32_t value)
Set the RTC Timer clock.
Definition: gr55xx_ll_rtc.h:135
ll_rtc_clear_flag_alarm
__STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t *RTCx)
Clear RTC alarm interrupt flag.
Definition: gr55xx_ll_rtc.h:835
ll_rtc_clear_wrap
__STATIC_INLINE void ll_rtc_clear_wrap(rtc_regs_t *RTCx)
CLear RTC wrap.
Definition: gr55xx_ll_rtc.h:452
ll_rtc_it_disable_tick
__STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t *RTCx)
Disable RTC tick interrupt.
Definition: gr55xx_ll_rtc.h:652
ll_rtc_reload_tick_and_request
__STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t *RTCx, uint32_t tick_reload)
Reloads RTCx tick counter and request.
Definition: gr55xx_ll_rtc.h:686
ll_rtc_clear_wrap_set
__STATIC_INLINE void ll_rtc_clear_wrap_set(rtc_regs_t *RTCx)
Definition: gr55xx_ll_rtc.h:457
ll_rtc_disable
__STATIC_INLINE void ll_rtc_disable(rtc_regs_t *RTCx)
Disable RTC counter.
Definition: gr55xx_ll_rtc.h:184