gr55xx_ll_qspi.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_QSPI QSPI
47 * @brief QSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_QSPI_H__
53 #define __GR55xx_LL_QSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (QSPI0) || defined (QSPI1) || defined (QSPI2)
63
64 /** @defgroup LL_QSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup QSPI_LL_ES_INIT QSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief QSPI init structures definition
75 */
76 typedef struct _ll_qspi_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the QSPI transfer or receive mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_qspi_set_transfer_direction().*/
82
83 uint32_t instruction_size; /**< Specifies the QSPI instruction width.
84 This parameter can be a value of @ref SPI_LL_EC_INSTRUCTIONSIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_qspi_set_instruction_size().*/
87
88 uint32_t address_size; /**< Specifies the QSPI address width.
89 This parameter can be a value of @ref SPI_LL_EC_ADDRESSSIZE.
90
91 This feature can be modified afterwards using unitary function @ref ll_qspi_set_address_size().*/
92
93 uint32_t inst_addr_transfer_format; /**< Specifies the QSPI instruction and address transfer format.
94 This parameter can be a value of @ref SPI_LL_EC_ADDRINSTTRNASFERFORMAT.
95
96 This feature can be modified afterwards using unitary function @ref ll_qspi_set_add_inst_transfer_format().*/
97
98 uint32_t wait_cycles; /**< Specifies the QSPI dummy clock.
99 This parameter can be one of the following values: 0 ~ 31.
100
101 This feature can be modified afterwards using unitary function @ref ll_qspi_set_wait_cycles().*/
102
103 uint32_t data_size; /**< Specifies the QSPI data width.
104 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
105
106 This feature can be modified afterwards using unitary function @ref ll_qspi_set_data_size().*/
107
108 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
109 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
110 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_polarity().*/
111
112 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
113 This parameter can be a value of @ref SPI_LL_EC_PHASE.
114
115 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_phase().*/
116
117 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
118 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
119 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
120
121 This feature can be modified afterwards using unitary function @ref ll_qspi_set_baud_rate_prescaler().*/
122
123 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
124 This parameter can be a number between 0 and 0x7 */
125
126 } ll_qspi_init_t;
127
128 typedef enum {
129 LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY = 0, /* Specifies mmap mode to read only */
130 LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE = 1, /* Specifies mmap mode to read and write */
131 } ll_qspi_memorymapped_mode_e;
132
133 typedef struct _ll_qspi_memorymapped_read_init_t
134 {
135 /*
136 * memorymapped read setting parameters
137 */
138
139 uint32_t x_dfs; /**< Specifies the QSPI data frame size in xip mode.
140 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_DFS. */
141
142 uint32_t x_dfs_hardcode_en; /**< Specifies whether to enable the HSIZE hardcoded to DFS feature in memorymapped(xip) mode.
143 @ref LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE
144 @ref LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
145 */
146
147 uint32_t x_instruction_en; /**< Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
148 @ref LL_QSPI_CONCURRENT_XIP_INST_ENABLE
149 @ref LL_QSPI_CONCURRENT_XIP_INST_DISABLE
150 */
151
152 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
153 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE.
154 */
155
156 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
157
158 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
159 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE.
160 */
161
162 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
163 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT.
164 */
165
166 uint32_t x_mode_bits_en; /**< Specifies whether to enable mode bits phase in memorymapped(xip) mode.
167 @ref LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE
168 @ref LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
169 */
170
171 uint32_t x_mode_bits_length; /**< Specifies mode bits length
172 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_MBL.
173 */
174
175 uint32_t x_mode_bits_data; /**< Specifies value of mode bits phase */
176
177 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
178 value range [0 ~ 31]
179 */
180
181 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
182 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_FRF
183 */
184
185 uint32_t x_prefetch_en; /**< Specifies whether to enable the prefetch feature.
186 @ref LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE
187 @ref LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
188 */
189
190 uint32_t x_continous_xfer_en; /**< Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
191 @ref LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE
192 @ref LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
193 */
194
195 uint32_t x_continous_xfer_toc; /**< Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
196 unit in terms of hclk, range [0, 255]
197 */
198
199 uint32_t x_endian_mode; /**< Specifies endian mode in memorymapped(xip) mode.
200 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE
201 */
202 } ll_qspi_memorymapped_read_init_t;
203
204
205
206 typedef struct _ll_qspi_memorymapped_write_init_t
207 {
208 /*
209 * memorymapped write setting parameters
210 */
211
212 uint32_t x_wr_instruction_size; /**< Specifies instruction size in memorymapped(xip) write mode.
213 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE.
214 */
215
216 uint32_t x_wr_instruction; /**< Specifies instruction in memorymapped(xip) write mode. */
217
218 uint32_t x_wr_address_size; /**< Specifies instruction size in memorymapped(xip) write mode.
219 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE.
220 */
221
222 uint32_t x_wr_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) write mode.
223 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT.
224 */
225
226 uint32_t x_wr_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) write mode.
227 value range [0 ~ 31]
228 */
229
230 uint32_t x_wr_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) write mode.
231 This parameter can be a value of @ref LL_QSPI_CONCURRENT_XIP_FRF
232 */
233 } ll_qspi_memorymapped_write_init_t;
234
235
236 typedef struct _ll_qspi_memorymapped_init_t
237 {
238 /*
239 * basical setting parameters
240 */
241
242 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
243 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
244 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_polarity().*/
245
246 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
247 This parameter can be a value of @ref SPI_LL_EC_PHASE.
248 This feature can be modified afterwards using unitary function @ref ll_qspi_set_clock_phase().*/
249
250 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
251 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
252 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
253 This feature can be modified afterwards using unitary function @ref ll_qspi_set_baud_rate_prescaler().*/
254
255 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
256 This parameter can be a number between 0 and 0x7 */
257
258 ll_qspi_memorymapped_mode_e rw_mode; /**< Specifies the access mode for memorymapped: readonly or read&write */
259
260 ll_qspi_memorymapped_read_init_t rd; /**< Specifies the initized params for read, must set */
261
262 ll_qspi_memorymapped_write_init_t wr; /**< Specifies the initized params for write, if rw_mode is readonly, leave un-set */
263
264 } ll_qspi_memorymapped_init_t;
265
266 /** uint32_t clock_polarity; @} */
267
268 /** @} */
269
270 /**
271 * uint32_t clock_phase; @defgroup SPI_LL_MACRO Defines
272 * @{
273 */
274
275 /* Exported constants --------------------------------------------------------*/
276 /** uint32_t baud_rate; @defgroup SPI_LL_Exported_Constants SPI Exported Constants
277 * @{
278 */
279
280 /** @defgroup LL_QSPI_FIFO_DEPTH Defines
281 * @{
282 */
283 #define LL_QSPI_MAX_FIFO_DEPTH (32u) /**< FIFO Depth for QSPI Master */
284
285 #define LL_QSPI0_REG_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of Register Mode for QSPI0 Master */
286 #define LL_QSPI0_REG_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of Register Mode for QSPI0 Master */
287 #define LL_QSPI0_XIP_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of XIP Mode for QSPI0 Master */
288 #define LL_QSPI0_XIP_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of XIP Mode for QSPI0 Master */
289
290 #define LL_QSPI1_REG_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of Register Mode for QSPI1 Master */
291 #define LL_QSPI1_REG_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of Register Mode for QSPI1 Master */
292 #define LL_QSPI1_XIP_RX_FIFO_DEPTH (32u) /**< Receive FIFO Depth Of XIP Mode for QSPI1 Master */
293 #define LL_QSPI1_XIP_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of XIP Mode for QSPI1 Master */
294
295 #define LL_QSPI2_REG_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of Register Mode for QSPI2 Master */
296 #define LL_QSPI2_REG_TX_FIFO_DEPTH (32u) /**< Transmit FIFO Depth Of Register Mode for QSPI2 Master */
297 #define LL_QSPI2_XIP_RX_FIFO_DEPTH (16u) /**< Receive FIFO Depth Of XIP Mode for QSPI2 Master */
298 #define LL_QSPI2_XIP_TX_FIFO_DEPTH (16u) /**< Transmit FIFO Depth Of XIP Mode for QSPI2 Master */
299 /** @} */
300
301 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
302 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
303 * @{
304 */
305 #define LL_QSPI_SR_DCOL QSPI_STAT_DCOL /**< Data collision error flag */
306 #define LL_QSPI_SR_TXE QSPI_STAT_TXE /**< Transmission error flag */
307 #define LL_QSPI_SR_RFF QSPI_STAT_RFF /**< Rx FIFO full flag */
308 #define LL_QSPI_SR_RFNE QSPI_STAT_RFNE /**< Rx FIFO not empty flag */
309 #define LL_QSPI_SR_TFE QSPI_STAT_TFE /**< Tx FIFO empty flag */
310 #define LL_QSPI_SR_TFNF QSPI_STAT_TFNF /**< Tx FIFO not full flag */
311 #define LL_QSPI_SR_BUSY QSPI_STAT_BUSY /**< Busy flag */
312 /** @} */
313
314 /** @defgroup SPI_LL_EC_IT IT Defines
315 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
316 * @{
317 */
318 #define LL_QSPI_IM_SPITE QSPI_INTMASK_SPITEIM /**< SPI Transmit Error Interrupt enable */
319 #define LL_QSPI_IM_TXU QSPI_INTMASK_TXUIM /**< Transmit FIFO Underflow Interrupt enable */
320 #define LL_QSPI_IM_XRXO QSPI_INTMASK_XRXOIM /**< XIP Receive FIFO Overflow Interrupt enable */
321 #define LL_QSPI_IM_MST QSPI_INTMASK_MSTIM /**< Multi-Master Contention Interrupt enable */
322 #define LL_QSPI_IM_RXF QSPI_INTMASK_RXFIM /**< Receive FIFO Full Interrupt enable */
323 #define LL_QSPI_IM_RXO QSPI_INTMASK_RXOIM /**< Receive FIFO Overflow Interrupt enable */
324 #define LL_QSPI_IM_RXU QSPI_INTMASK_RXUIM /**< Receive FIFO Underflow Interrupt enable */
325 #define LL_QSPI_IM_TXO QSPI_INTMASK_TXOIM /**< Transmit FIFO Overflow Interrupt enable */
326 #define LL_QSPI_IM_TXE QSPI_INTMASK_TXEIM /**< Transmit FIFO Empty Interrupt enable */
327 #define LL_QSPI_IM_ALL (LL_QSPI_IM_SPITE| \
328 LL_QSPI_IM_TXU | \
329 LL_QSPI_IM_XRXO | \
330 LL_QSPI_IM_MST | \
331 LL_QSPI_IM_RXF | \
332 LL_QSPI_IM_RXO | \
333 LL_QSPI_IM_RXU | \
334 LL_QSPI_IM_TXO | \
335 LL_QSPI_IM_TXE)
336
337 #define LL_QSPI_IS_SPITE QSPI_INTMASK_SPITEIS /**< SPI Transmit Error Interrupt flag */
338 #define LL_QSPI_IS_TXU QSPI_INTMASK_TXUIS /**< Transmit FIFO Underflow Interrupt flag */
339 #define LL_QSPI_IS_XRXO QSPI_INTSTAT_XRXOIS /**< XIP Receive FIFO Overflow Interrupt flag */
340 #define LL_QSPI_IS_MST QSPI_INTSTAT_MSTIS /**< Multi-Master Contention Interrupt flag */
341 #define LL_QSPI_IS_RXF QSPI_INTSTAT_RXFIS /**< Receive FIFO Full Interrupt flag */
342 #define LL_QSPI_IS_RXO QSPI_INTSTAT_RXOIS /**< Receive FIFO Overflow Interrupt flag */
343 #define LL_QSPI_IS_RXU QSPI_INTSTAT_RXUIS /**< Receive FIFO Underflow Interrupt flag */
344 #define LL_QSPI_IS_TXO QSPI_INTSTAT_TXOIS /**< Transmit FIFO Overflow Interrupt flag */
345 #define LL_QSPI_IS_TXE QSPI_INTSTAT_TXEIS /**< Transmit FIFO Empty Interrupt flag */
346 #define LL_QSPI_IS_ALL (LL_QSPI_IS_SPITE| \
347 LL_QSPI_IS_TXU | \
348 LL_QSPI_IS_XRXO | \
349 LL_QSPI_IS_MST | \
350 LL_QSPI_IS_RXF | \
351 LL_QSPI_IS_RXO | \
352 LL_QSPI_IS_RXU | \
353 LL_QSPI_IS_TXO | \
354 LL_QSPI_IS_TXE)
355
356 #define LL_QSPI_RIS_SPITE QSPI_RAW_INTMASK_SPITEIR /**< SPI Transmit Error RAW Interrupt flag */
357 #define LL_QSPI_RIS_TXU QSPI_RAW_INTMASK_TXUIIR /**< Transmit FIFO Underflow RAW Interrupt flag */
358 #define LL_QSPI_RIS_XRXO QSPI_RAW_INTSTAT_XRXOIR /**< XIP Receive FIFO Overflow RAW Interrupt flag */
359 #define LL_QSPI_RIS_MST QSPI_RAW_INTSTAT_MSTIR /**< Multi-Master Contention RAW Interrupt flag */
360 #define LL_QSPI_RIS_RXF QSPI_RAW_INTSTAT_RXFIR /**< Receive FIFO Full RAW Interrupt flag */
361 #define LL_QSPI_RIS_RXO QSPI_RAW_INTSTAT_RXOIR /**< Receive FIFO Overflow RAW Interrupt flag */
362 #define LL_QSPI_RIS_RXU QSPI_RAW_INTSTAT_RXUIR /**< Receive FIFO Underflow RAW Interrupt flag */
363 #define LL_QSPI_RIS_TXO QSPI_RAW_INTSTAT_TXOIR /**< Transmit FIFO Overflow RAW Interrupt flag */
364 #define LL_QSPI_RIS_TXE QSPI_RAW_INTSTAT_TXEIR /**< Transmit FIFO Empty RAW Interrupt flag */
365 #define LL_QSPI_RIS_ALL (LL_QSPI_RIS_SPITE| \
366 LL_QSPI_RIS_TXU | \
367 LL_QSPI_RIS_XRXO | \
368 LL_QSPI_RIS_MST | \
369 LL_QSPI_RIS_RXF | \
370 LL_QSPI_RIS_RXO | \
371 LL_QSPI_RIS_RXU | \
372 LL_QSPI_RIS_TXO | \
373 LL_QSPI_RIS_TXE)
374
375 /** @} */
376
377 /** @defgroup SPI_LL_EC_SPIFRAMEFORMAT SPI Frame Format
378 * @{
379 */
380 #define LL_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
381 #define LL_QSPI_FRF_DUALSPI (1UL << QSPI_CTRL0_SPIFRF_Pos) /**< Dual-SPI frame format for transfer */
382 #define LL_QSPI_FRF_QUADSPI (2UL << QSPI_CTRL0_SPIFRF_Pos) /**< Quad-SPI frame format for transfer */
383 /** @} */
384
385 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
386 * @{
387 */
388 #define LL_QSPI_DATASIZE_4BIT (3UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 4 bits */
389 #define LL_QSPI_DATASIZE_5BIT (4UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 5 bits */
390 #define LL_QSPI_DATASIZE_6BIT (5UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 6 bits */
391 #define LL_QSPI_DATASIZE_7BIT (6UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 7 bits */
392 #define LL_QSPI_DATASIZE_8BIT (7UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 8 bits */
393 #define LL_QSPI_DATASIZE_9BIT (8UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 9 bits */
394 #define LL_QSPI_DATASIZE_10BIT (9UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 10 bits */
395 #define LL_QSPI_DATASIZE_11BIT (10UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 11 bits */
396 #define LL_QSPI_DATASIZE_12BIT (11UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 12 bits */
397 #define LL_QSPI_DATASIZE_13BIT (12UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 13 bits */
398 #define LL_QSPI_DATASIZE_14BIT (13UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 14 bits */
399 #define LL_QSPI_DATASIZE_15BIT (14UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 15 bits */
400 #define LL_QSPI_DATASIZE_16BIT (15UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 16 bits */
401 #define LL_QSPI_DATASIZE_17BIT (16UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 17 bits */
402 #define LL_QSPI_DATASIZE_18BIT (17UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 18 bits */
403 #define LL_QSPI_DATASIZE_19BIT (18UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 19 bits */
404 #define LL_QSPI_DATASIZE_20BIT (19UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 20 bits */
405 #define LL_QSPI_DATASIZE_21BIT (20UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 21 bits */
406 #define LL_QSPI_DATASIZE_22BIT (21UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 22 bits */
407 #define LL_QSPI_DATASIZE_23BIT (22UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 23 bits */
408 #define LL_QSPI_DATASIZE_24BIT (23UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 24 bits */
409 #define LL_QSPI_DATASIZE_25BIT (24UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 25 bits */
410 #define LL_QSPI_DATASIZE_26BIT (25UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 26 bits */
411 #define LL_QSPI_DATASIZE_27BIT (26UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 27 bits */
412 #define LL_QSPI_DATASIZE_28BIT (27UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 28 bits */
413 #define LL_QSPI_DATASIZE_29BIT (28UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 29 bits */
414 #define LL_QSPI_DATASIZE_30BIT (29UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 30 bits */
415 #define LL_QSPI_DATASIZE_31BIT (30UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 31 bits */
416 #define LL_QSPI_DATASIZE_32BIT (31UL << QSPI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 32 bits */
417 /** @} */
418
419 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
420 * @{
421 */
422 #define LL_QSPI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
423 #define LL_QSPI_MW_CMDSIZE_2BIT (1UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 2 bits */
424 #define LL_QSPI_MW_CMDSIZE_3BIT (2UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 3 bits */
425 #define LL_QSPI_MW_CMDSIZE_4BIT (3UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 4 bits */
426 #define LL_QSPI_MW_CMDSIZE_5BIT (4UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 5 bits */
427 #define LL_QSPI_MW_CMDSIZE_6BIT (5UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 6 bits */
428 #define LL_QSPI_MW_CMDSIZE_7BIT (6UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 7 bits */
429 #define LL_QSPI_MW_CMDSIZE_8BIT (7UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 8 bits */
430 #define LL_QSPI_MW_CMDSIZE_9BIT (8UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 9 bits */
431 #define LL_QSPI_MW_CMDSIZE_10BIT (9UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 10 bits */
432 #define LL_QSPI_MW_CMDSIZE_11BIT (10UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 11 bits */
433 #define LL_QSPI_MW_CMDSIZE_12BIT (11UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 12 bits */
434 #define LL_QSPI_MW_CMDSIZE_13BIT (12UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 13 bits */
435 #define LL_QSPI_MW_CMDSIZE_14BIT (13UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 14 bits */
436 #define LL_QSPI_MW_CMDSIZE_15BIT (14UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 15 bits */
437 #define LL_QSPI_MW_CMDSIZE_16BIT (15UL << QSPI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 16 bits */
438 /** @} */
439
440 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
441 * @{
442 */
443 #define LL_QSPI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
444 #define LL_QSPI_TEST_MODE (1UL << QSPI_CTRL0_SRL_Pos) /**< Test mode for SPI transfer: Rx and Tx connected inside */
445 /** @} */
446
447 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
448 * @{
449 */
450 #define LL_QSPI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
451 #define LL_QSPI_SLAVE_OUTEN (1UL << QSPI_CTRL0_SLVOE_Pos) /**< Output disable for SPI transfer as slave */
452 /** @} */
453
454 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
455 * @{
456 */
457 #define LL_QSPI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
458 #define LL_QSPI_SIMPLEX_TX (1UL << QSPI_CTRL0_TMOD_Pos) /**< Simplex Tx mode. Tx transfer only on 1 line */
459 #define LL_QSPI_SIMPLEX_RX (2UL << QSPI_CTRL0_TMOD_Pos) /**< Simplex Rx mode. Rx transfer only on 1 line */
460 #define LL_QSPI_READ_EEPROM (3UL << QSPI_CTRL0_TMOD_Pos) /**< Read EEPROM mode. Rx transfer only on 1 line */
461 /** @} */
462
463 /** @defgroup SPI_LL_EC_PHASE Clock Phase
464 * @{
465 */
466 #define LL_QSPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
467 #define LL_QSPI_SCPHA_2EDGE (1UL << QSPI_CTRL0_SCPHA_Pos) /**< Second clock transition is the first data capture edge */
468 /** @} */
469
470 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
471 * @{
472 */
473 #define LL_QSPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
474 #define LL_QSPI_SCPOL_HIGH (1UL << QSPI_CTRL0_SCPOL_Pos) /**< Clock to 1 when idle */
475 /** @} */
476
477 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
478 * @{
479 */
480 #define LL_QSPI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
481 #define LL_QSPI_PROTOCOL_TI (1UL << QSPI_CTRL0_FRF_Pos) /**< TI mode */
482 #define LL_QSPI_PROTOCOL_MICROWIRE (2UL << QSPI_CTRL0_FRF_Pos) /**< Microwire mode */
483 /** @} */
484
485 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
486 * @{
487 */
488 #define LL_QSPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
489 #define LL_QSPI_MICROWIRE_HANDSHAKE_EN (1UL << QSPI_MWC_MHS_Pos) /**< Disable Handshake for Microwire transfer */
490
491 #define LL_QSPI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
492 #define LL_QSPI_MICROWIRE_TX (1UL << QSPI_MWC_MDD_Pos) /**< Tx mode. Tx transfer at Microwire mode */
493
494 #define LL_QSPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
495 #define LL_QSPI_MICROWIRE_SEQUENTIAL (1UL << QSPI_MWC_MWMOD_Pos) /**< Sequential for Microwire transfer */
496 /** @} */
497
498 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
499 * @{
500 */
501 #define LL_QSPI_SLAVE1 QSPI_SE_SLAVE1 /**< Enable slave1 select pin for SPI transfer */
502 #define LL_QSPI_SLAVE0 QSPI_SE_SLAVE0 /**< Enable slave0 select pin for SPI transfer */
503 /** @} */
504
505 /** @defgroup SPI_LL_EC_DMA DMA Defines
506 * @{
507 */
508 #define LL_QSPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
509 #define LL_QSPI_DMA_TX_EN QSPI_DMAC_TDMAE /**< Enable the transmit FIFO DMA channel */
510
511 #define LL_QSPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
512 #define LL_QSPI_DMA_RX_EN QSPI_DMAC_RDMAE /**< Enable the receive FIFO DMA channel */
513 /** @} */
514
515 /** @defgroup SPI_LL_EC_INSTRUCTIONSIZE QSPI Instruction Size
516 * @{
517 */
518 #define LL_QSPI_INSTSIZE_0BIT 0x00000000UL /**< Instruction length for QSPI transfer: 0 bits */
519 #define LL_QSPI_INSTSIZE_4BIT (1UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 4 bits */
520 #define LL_QSPI_INSTSIZE_8BIT (2UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 8 bits */
521 #define LL_QSPI_INSTSIZE_16BIT (3UL << QSPI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 16 bits */
522 /** @} */
523
524 /** @defgroup SPI_LL_EC_ADDRESSSIZE QSPI Address Size
525 * @{
526 */
527 #define LL_QSPI_ADDRSIZE_0BIT 0x00000000UL /**< Address length for QSPI transfer: 0 bits */
528 #define LL_QSPI_ADDRSIZE_4BIT (1UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 4 bits */
529 #define LL_QSPI_ADDRSIZE_8BIT (2UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 8 bits */
530 #define LL_QSPI_ADDRSIZE_12BIT (3UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 12 bits */
531 #define LL_QSPI_ADDRSIZE_16BIT (4UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 16 bits */
532 #define LL_QSPI_ADDRSIZE_20BIT (5UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 20 bits */
533 #define LL_QSPI_ADDRSIZE_24BIT (6UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 24 bits */
534 #define LL_QSPI_ADDRSIZE_28BIT (7UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 28 bits */
535 #define LL_QSPI_ADDRSIZE_32BIT (8UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 32 bits */
536 #define LL_QSPI_ADDRSIZE_36BIT (9UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 36 bits */
537 #define LL_QSPI_ADDRSIZE_40BIT (10UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 40 bits */
538 #define LL_QSPI_ADDRSIZE_44BIT (11UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 44 bits */
539 #define LL_QSPI_ADDRSIZE_48BIT (12UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 48 bits */
540 #define LL_QSPI_ADDRSIZE_52BIT (13UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 52 bits */
541 #define LL_QSPI_ADDRSIZE_56BIT (14UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 56 bits */
542 #define LL_QSPI_ADDRSIZE_60BIT (15UL << QSPI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 60 bits */
543 /** @} */
544
545 /** @defgroup LL_QSPI_RX_SAMPLE_EDGE QSPI RX SAMPLE EDGE
546 * @{
547 */
548 #define LL_QSPI_RX_SAMPLE_POSITIVE_EDGE (0U)
549 #define LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE (1U)
550 /** @} */
551
552 /** @defgroup SPI_LL_EC_ADDRINSTTRNASFERFORMAT QSPI Address and Instruction Transfer Format
553 * @{
554 */
555 #define LL_QSPI_INST_ADDR_ALL_IN_SPI 0x00000000UL /**< Instruction and address are sent in SPI mode */
556 #define LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << QSPI_SCTRL0_TRANSTYPE_Pos) /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
557 #define LL_QSPI_INST_ADDR_ALL_IN_SPIFRF (2UL << QSPI_SCTRL0_TRANSTYPE_Pos) /**< Instruction and address are sent in Daul/Quad SPI mode */
558 /** @} */
559
560
561 /** @defgroup LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE : endian mode for qspi xip
562 * @{
563 */
564 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 0u /* Default endian order from AHB */
565 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 1u /* Re-order the read data as [23:16], [31:24], [7:0], [15:8] */
566 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 2u /* Re-order the read data as [7:0], [15:8], [23:16], [31:24] */
567 /** @} */
568
569 /** @defgroup LL_QSPI_CONCURRENT_XIP_SLAVE : Which Slave to Enable in XIP
570 * @{
571 */
572 #define LL_QSPI_CONCURRENT_XIP_SLAVE0 QSPI_XIP_SLAVE0_EN
573 /** @} */
574
575 /** @defgroup LL_QSPI_CONCURRENT_XIP_DFS : data frame size in xip, take effect when enable DFS_HC
576 * @{
577 */
578 #define LL_QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_DATASIZE_8BIT
579 #define LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_DATASIZE_16BIT
580 #define LL_QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_DATASIZE_32BIT
581 /** @} */
582
583 /** @defgroup LL_QSPI_CONCURRENT_XIP_MBL : mode bits length for xip mode
584 * @{
585 */
586 #define LL_QSPI_CONCURRENT_XIP_MBL_2 0x0 /* mode bits length equals to 2 bit */
587 #define LL_QSPI_CONCURRENT_XIP_MBL_4 0x1 /* mode bits length equals to 4 bit */
588 #define LL_QSPI_CONCURRENT_XIP_MBL_8 0x2 /* mode bits length equals to 8 bit */
589 #define LL_QSPI_CONCURRENT_XIP_MBL_16 0x3 /* mode bits length equals to 16 bit */
590 /** @} */
591
592 /** @defgroup LL_QSPI_CONCURRENT_XIP_INSTSIZE : instruction size for concurrent xip mode
593 * @{
594 */
595 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT 0x0 /* no instruction */
596 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT 0x1 /* instruction size equals 4bits */
597 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT 0x2 /* instruction size equals 8bits */
598 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT 0x3 /* instruction size equals 16bits */
599 /** @} */
600
601 /** @defgroup LL_QSPI_CONCURRENT_XIP_ADDRSIZE : address size for concurrent xip mode
602 * @{
603 */
604 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT 0x0 /**< Address length for QSPI XIP transfer: 0 bits */
605 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT 0x1 /**< Address length for QSPI XIP transfer: 4 bits */
606 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT 0x2 /**< Address length for QSPI XIP transfer: 8 bits */
607 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT 0x3 /**< Address length for QSPI XIP transfer: 12 bits */
608 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT 0x4 /**< Address length for QSPI XIP transfer: 16 bits */
609 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT 0x5 /**< Address length for QSPI XIP transfer: 20 bits */
610 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT 0x6 /**< Address length for QSPI XIP transfer: 24 bits */
611 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT 0x7 /**< Address length for QSPI XIP transfer: 28 bits */
612 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT 0x8 /**< Address length for QSPI XIP transfer: 32 bits */
613 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT 0x9 /**< Address length for QSPI XIP transfer: 36 bits */
614 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT 0xA /**< Address length for QSPI XIP transfer: 40 bits */
615 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT 0xB /**< Address length for QSPI XIP transfer: 44 bits */
616 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT 0xC /**< Address length for QSPI XIP transfer: 48 bits */
617 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT 0xD /**< Address length for QSPI XIP transfer: 52 bits */
618 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT 0xE /**< Address length for QSPI XIP transfer: 56 bits */
619 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT 0xF /**< Address length for QSPI XIP transfer: 60 bits */
620 /** @} */
621
622 /** @defgroup LL_QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT : transfer of inst & address for concurrent xip mode
623 * @{
624 */
625 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI 0x0 /**< Instruction and address are sent in SPI mode */
626 #define LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF 0x1 /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
627 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF 0x2 /**< Instruction and address are sent in Daul/Quad SPI mode */
628 /** @} */
629
630 /** @defgroup LL_QSPI_CONCURRENT_XIP_FRF : frame format for concurrent xip mode
631 * @{
632 */
633 #define LL_QSPI_CONCURRENT_XIP_FRF_RSVD 0x0 /**< SPI Frame format : Reserved */
634 #define LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI 0x1 /**< SPI Frame format : DUAL */
635 #define LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI 0x2 /**< SPI Frame format : QUAD */
636 #define LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI 0x3 /**< SPI Frame format : OCTAL */
637 /** @} */
638
639 /** @defgroup LL_QSPI_XIP_CLK_STRETCH Mode Clock stretch mode
640 * @{
641 */
642 #define LL_QSPI_CLK_STRETCH_ENABLE 1u
643 #define LL_QSPI_CLK_STRETCH_DISABLE 0u
644 /** @} */
645
646 /** @defgroup QSPI_XIP_PREFETCH XQSPI Xip Prefetch
647 * @{
648 */
649 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE 1u
650 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE 0u
651 /** @} */
652
653 /** @defgroup QSPI_XIP_CONT_XFERR QSPI Xip Count Xferr
654 * @{
655 */
656 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE 1u
657 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE 0u
658 /** @} */
659
660 /** @defgroup QSPI_XIP_INST_PHASE QSPI Xip Inst Phase
661 * @{
662 */
663 #define LL_QSPI_CONCURRENT_XIP_INST_ENABLE 1u
664 #define LL_QSPI_CONCURRENT_XIP_INST_DISABLE 0u
665 /** @} */
666
667 /** @defgroup QSPI_XIP_MODE_BITS_PHASE QSPI Xip Mode Enable
668 * @{
669 */
670 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE 1u
671 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE 0u
672 /** @} */
673
674 /** @defgroup QSPI_XIP_DFS_HC QSPI Xip Dfs Hardcode Enable
675 * @{
676 */
677 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE 1u
678 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE 0u
679 /** @} */
680
681 /** @defgroup LL_QSPI_CONCURRENT_XIP_INST_SENT_MODE QSPI Concurrent Xip Inst Sent Mode
682 * @{
683 */
684 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS 0u /*!< Send instruction for every transaction */
685 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS 1u /*!< Send instruction only for first transaction */
686 /** @} */
687
688
689 /** @defgroup SPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
690 * @{
691 */
692
693 /**
694 * @brief LL QSPI InitStrcut default configuartion
695 */
696 #define LL_QSPI_DEFAULT_CONFIG \
697 { \
698 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
699 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
700 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
701 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
702 .wait_cycles = 0, \
703 .data_size = LL_QSPI_DATASIZE_8BIT, \
704 .clock_polarity = LL_QSPI_SCPOL_LOW, \
705 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
706 .baud_rate = SystemCoreClock / 1000000, \
707 .rx_sample_delay = 0, \
708 }
709
710
711
712 #define LL_CONC_QSPI_DEFAULT_CONFIG \
713 { \
714 .baud_rate = SystemCoreClock / 1000000, \
715 .clock_polarity = LL_QSPI_SCPOL_LOW, \
716 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
717 .data_size = LL_QSPI_DATASIZE_8BIT, \
718 .clock_stretch_en = LL_QSPI_CLK_STRETCH_DISABLE, \
719 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
720 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
721 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
722 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
723 .wait_cycles = 0, \
724 .rx_sample_delay = 0, \
725 .data_beats = 0, \
726 .tx_start_fifo_threshold = 0, \
727 .tx_fifo_threshold = 0, \
728 .rx_fifo_threshold = 0, \
729 .dma_tx_fifo_level = 0, \
730 .dma_rx_fifo_level = 0, \
731 \
732 .x_prefetch_en = LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE, \
733 .x_continous_xfer_en = LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE, \
734 .x_continous_xfer_toc = 0x00, \
735 .x_dfs_hardcode_en = LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE, \
736 .x_mode_bits_en = LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE, \
737 .x_mode_bits_length = LL_QSPI_CONCURRENT_XIP_MBL_8, \
738 .x_mode_bits_data = 0x00, \
739 .x_instruction_en = LL_QSPI_CONCURRENT_XIP_INST_DISABLE, \
740 .x_instruction_size = LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT, \
741 .x_instruction = 0x00, \
742 .x_address_size = LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT,\
743 .x_inst_addr_transfer_format = LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF, \
744 .x_dummy_cycles = 0x00, \
745 .x_data_frame_format = LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI, \
746 }
747
748 /** @} */
749
750 /** @} */
751
752 /* Exported macro ------------------------------------------------------------*/
753 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
754 * @{
755 */
756
757 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
758 * @{
759 */
760
761 /**
762 * @brief Write a value in SPI register
763 * @param __instance__ SPI instance
764 * @param __REG__ Register to be written
765 * @param __VALUE__ Value to be written in the register
766 * @retval None
767 */
768 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
769
770 /**
771 * @brief Read a value in SPI register
772 * @param __instance__ SPI instance
773 * @param __REG__ Register to be read
774 * @retval Register value
775 */
776 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
777
778 /** @} */
779
780 /** @} */
781
782 /** @} */
783
784 /* Exported functions --------------------------------------------------------*/
785 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
786 * @{
787 */
788
789 /** @defgroup SPI_LL_EF_Configuration Configuration functions
790 * @{
791 */
792
793 /**
794 * @brief Enable slave select toggle
795 * @note This bit should not be changed when communication is ongoing.
796 *
797 * Register|BitsName
798 * --------|--------
799 * CTRL0 | SSTEN
800 *
801 * @param QSPIx QSPI instance
802 * @retval None
803 */
804 __STATIC_INLINE void ll_qspi_enable_ss_toggle(qspi_regs_t *QSPIx)
805 {
806 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
807 }
808
809 /**
810 * @brief Disable slave select toggle
811 * @note This bit should not be changed when communication is ongoing.
812 *
813 * Register|BitsName
814 * --------|--------
815 * CTRL0 | SSTEN
816 *
817 * @param QSPIx QSPI instance
818 * @retval None
819 */
820 __STATIC_INLINE void ll_qspi_disable_ss_toggle(qspi_regs_t *QSPIx)
821 {
822 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
823 }
824
825 /**
826 * @brief Check if slave select toggle is enabled
827 * @note This bit should not be changed when communication is ongoing.
828 *
829 * Register|BitsName
830 * --------|--------
831 * CTRL0 | SSTEN
832 *
833 * @param QSPIx QSPI instance
834 * @retval State of bit (1 or 0).
835 */
836 __STATIC_INLINE uint32_t ll_qspi_is_enabled_ss_toggle(qspi_regs_t *QSPIx)
837 {
838 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN) == (QSPI_CTRL0_SSTEN));
839 }
840
841 /**
842 * @brief Set data frame format for transmitting/receiving the data
843 * @note This bit should be written only when QSPI is disabled (QSPI_SSI_EN = 0) for correct operation.
844 *
845 * Register|BitsName
846 * --------|--------
847 * CTRL0 | SPIFRF
848 *
849 * @param QSPIx QSPI instance
850 * @param frf This parameter can be one of the following values:
851 * @arg @ref LL_QSPI_FRF_SPI
852 * @arg @ref LL_QSPI_FRF_DUALSPI
853 * @arg @ref LL_QSPI_FRF_QUADSPI
854 * @retval None
855 */
856 __STATIC_INLINE void ll_qspi_set_frame_format(qspi_regs_t *QSPIx, uint32_t frf)
857 {
858 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF, frf);
859 }
860
861 /**
862 * @brief Get data frame format for transmitting/receiving the data
863 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
864 *
865 * Register|BitsName
866 * --------|--------
867 * CTRL0 | SPIFRF
868 *
869 * @param QSPIx QSPI instance
870 * @retval Returned value can be one of the following values:
871 * @arg @ref LL_QSPI_FRF_SPI
872 * @arg @ref LL_QSPI_FRF_DUALSPI
873 * @arg @ref LL_QSPI_FRF_QUADSPI
874 */
875 __STATIC_INLINE uint32_t ll_qspi_get_frame_format(qspi_regs_t *QSPIx)
876 {
877 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF));
878 }
879
880 /**
881 * @brief Set frame data size
882 *
883 * Register|BitsName
884 * --------|--------
885 * CTRL0 | DFS32
886 *
887 * @param QSPIx QSPI instance
888 * @param size This parameter can be one of the following values:
889 * @arg @ref LL_QSPI_DATASIZE_4BIT
890 * @arg @ref LL_QSPI_DATASIZE_5BIT
891 * @arg @ref LL_QSPI_DATASIZE_6BIT
892 * @arg @ref LL_QSPI_DATASIZE_7BIT
893 * @arg @ref LL_QSPI_DATASIZE_8BIT
894 * @arg @ref LL_QSPI_DATASIZE_9BIT
895 * @arg @ref LL_QSPI_DATASIZE_10BIT
896 * @arg @ref LL_QSPI_DATASIZE_11BIT
897 * @arg @ref LL_QSPI_DATASIZE_12BIT
898 * @arg @ref LL_QSPI_DATASIZE_13BIT
899 * @arg @ref LL_QSPI_DATASIZE_14BIT
900 * @arg @ref LL_QSPI_DATASIZE_15BIT
901 * @arg @ref LL_QSPI_DATASIZE_16BIT
902 * @arg @ref LL_QSPI_DATASIZE_17BIT
903 * @arg @ref LL_QSPI_DATASIZE_18BIT
904 * @arg @ref LL_QSPI_DATASIZE_19BIT
905 * @arg @ref LL_QSPI_DATASIZE_20BIT
906 * @arg @ref LL_QSPI_DATASIZE_21BIT
907 * @arg @ref LL_QSPI_DATASIZE_22BIT
908 * @arg @ref LL_QSPI_DATASIZE_23BIT
909 * @arg @ref LL_QSPI_DATASIZE_24BIT
910 * @arg @ref LL_QSPI_DATASIZE_25BIT
911 * @arg @ref LL_QSPI_DATASIZE_26BIT
912 * @arg @ref LL_QSPI_DATASIZE_27BIT
913 * @arg @ref LL_QSPI_DATASIZE_28BIT
914 * @arg @ref LL_QSPI_DATASIZE_29BIT
915 * @arg @ref LL_QSPI_DATASIZE_30BIT
916 * @arg @ref LL_QSPI_DATASIZE_31BIT
917 * @arg @ref LL_QSPI_DATASIZE_32BIT
918 * @retval None
919 */
920 __STATIC_INLINE void ll_qspi_set_data_size(qspi_regs_t *QSPIx, uint32_t size)
921 {
922 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_DFS32, size);
923 }
924
925 /**
926 * @brief Get frame data size
927 *
928 * Register|BitsName
929 * --------|--------
930 * CTRL0 | DFS32
931 *
932 * @param QSPIx QSPI instance
933 * @retval Returned value can be one of the following values:
934 * @arg @ref LL_QSPI_DATASIZE_4BIT
935 * @arg @ref LL_QSPI_DATASIZE_5BIT
936 * @arg @ref LL_QSPI_DATASIZE_6BIT
937 * @arg @ref LL_QSPI_DATASIZE_7BIT
938 * @arg @ref LL_QSPI_DATASIZE_8BIT
939 * @arg @ref LL_QSPI_DATASIZE_9BIT
940 * @arg @ref LL_QSPI_DATASIZE_10BIT
941 * @arg @ref LL_QSPI_DATASIZE_11BIT
942 * @arg @ref LL_QSPI_DATASIZE_12BIT
943 * @arg @ref LL_QSPI_DATASIZE_13BIT
944 * @arg @ref LL_QSPI_DATASIZE_14BIT
945 * @arg @ref LL_QSPI_DATASIZE_15BIT
946 * @arg @ref LL_QSPI_DATASIZE_16BIT
947 * @arg @ref LL_QSPI_DATASIZE_17BIT
948 * @arg @ref LL_QSPI_DATASIZE_18BIT
949 * @arg @ref LL_QSPI_DATASIZE_19BIT
950 * @arg @ref LL_QSPI_DATASIZE_20BIT
951 * @arg @ref LL_QSPI_DATASIZE_21BIT
952 * @arg @ref LL_QSPI_DATASIZE_22BIT
953 * @arg @ref LL_QSPI_DATASIZE_23BIT
954 * @arg @ref LL_QSPI_DATASIZE_24BIT
955 * @arg @ref LL_QSPI_DATASIZE_25BIT
956 * @arg @ref LL_QSPI_DATASIZE_26BIT
957 * @arg @ref LL_QSPI_DATASIZE_27BIT
958 * @arg @ref LL_QSPI_DATASIZE_28BIT
959 * @arg @ref LL_QSPI_DATASIZE_29BIT
960 * @arg @ref LL_QSPI_DATASIZE_30BIT
961 * @arg @ref LL_QSPI_DATASIZE_31BIT
962 * @arg @ref LL_QSPI_DATASIZE_32BIT
963 */
964 __STATIC_INLINE uint32_t ll_qspi_get_data_size(qspi_regs_t *QSPIx)
965 {
966 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DFS32));
967 }
968
969 /**
970 * @brief Set the length of the control word for the Microwire frame format
971 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
972 *
973 * Register|BitsName
974 * --------|--------
975 * CTRL0 | CFS
976 *
977 * @param QSPIx QSPI instance
978 * @param size This parameter can be one of the following values:
979 * @arg @ref LL_QSPI_MW_CMDSIZE_1BIT
980 * @arg @ref LL_QSPI_MW_CMDSIZE_2BIT
981 * @arg @ref LL_QSPI_MW_CMDSIZE_3BIT
982 * @arg @ref LL_QSPI_MW_CMDSIZE_4BIT
983 * @arg @ref LL_QSPI_MW_CMDSIZE_5BIT
984 * @arg @ref LL_QSPI_MW_CMDSIZE_6BIT
985 * @arg @ref LL_QSPI_MW_CMDSIZE_7BIT
986 * @arg @ref LL_QSPI_MW_CMDSIZE_8BIT
987 * @arg @ref LL_QSPI_MW_CMDSIZE_9BIT
988 * @arg @ref LL_QSPI_MW_CMDSIZE_10BIT
989 * @arg @ref LL_QSPI_MW_CMDSIZE_11BIT
990 * @arg @ref LL_QSPI_MW_CMDSIZE_12BIT
991 * @arg @ref LL_QSPI_MW_CMDSIZE_13BIT
992 * @arg @ref LL_QSPI_MW_CMDSIZE_14BIT
993 * @arg @ref LL_QSPI_MW_CMDSIZE_15BIT
994 * @arg @ref LL_QSPI_MW_CMDSIZE_16BIT
995 * @retval None
996 */
997 __STATIC_INLINE void ll_qspi_set_control_frame_size(qspi_regs_t *QSPIx, uint32_t size)
998 {
999 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_CFS, size);
1000 }
1001
1002 /**
1003 * @brief Get the length of the control word for the Microwire frame format
1004 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
1005 *
1006 * Register|BitsName
1007 * --------|--------
1008 * CTRL0 | CFS
1009 *
1010 * @param QSPIx QSPI instance
1011 * @retval Returned value can be one of the following values:
1012 * @arg @ref LL_QSPI_MW_CMDSIZE_1BIT
1013 * @arg @ref LL_QSPI_MW_CMDSIZE_2BIT
1014 * @arg @ref LL_QSPI_MW_CMDSIZE_3BIT
1015 * @arg @ref LL_QSPI_MW_CMDSIZE_4BIT
1016 * @arg @ref LL_QSPI_MW_CMDSIZE_5BIT
1017 * @arg @ref LL_QSPI_MW_CMDSIZE_6BIT
1018 * @arg @ref LL_QSPI_MW_CMDSIZE_7BIT
1019 * @arg @ref LL_QSPI_MW_CMDSIZE_8BIT
1020 * @arg @ref LL_QSPI_MW_CMDSIZE_9BIT
1021 * @arg @ref LL_QSPI_MW_CMDSIZE_10BIT
1022 * @arg @ref LL_QSPI_MW_CMDSIZE_11BIT
1023 * @arg @ref LL_QSPI_MW_CMDSIZE_12BIT
1024 * @arg @ref LL_QSPI_MW_CMDSIZE_13BIT
1025 * @arg @ref LL_QSPI_MW_CMDSIZE_14BIT
1026 * @arg @ref LL_QSPI_MW_CMDSIZE_15BIT
1027 * @arg @ref LL_QSPI_MW_CMDSIZE_16BIT
1028 */
1029 __STATIC_INLINE uint32_t ll_qspi_get_control_frame_size(qspi_regs_t *QSPIx)
1030 {
1031 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_CFS));
1032 }
1033
1034 /**
1035 * @brief Enable SPI test mode
1036 *
1037 * Register|BitsName
1038 * --------|--------
1039 * CTRL0 | SRL
1040 *
1041 * @param QSPIx QSPI instance
1042 * @retval None
1043 */
1044 __STATIC_INLINE void ll_qspi_enable_test_mode(qspi_regs_t *QSPIx)
1045 {
1046 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1047 }
1048
1049 /**
1050 * @brief Disable SPI test mode
1051 *
1052 * Register|BitsName
1053 * --------|--------
1054 * CTRL0 | SRL
1055 *
1056 * @param QSPIx QSPI instance
1057 * @retval None
1058 */
1059 __STATIC_INLINE void ll_qspi_disable_test_mode(qspi_regs_t *QSPIx)
1060 {
1061 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1062 }
1063
1064 /**
1065 * @brief Check if SPI test mode is enabled
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * CTRL0 | SRL
1070 *
1071 * @param QSPIx QSPI instance
1072 * @retval State of bit (1 or 0).
1073 */
1074 __STATIC_INLINE uint32_t ll_qspi_is_enabled_test_mode(qspi_regs_t *QSPIx)
1075 {
1076 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL) == (QSPI_CTRL0_SRL));
1077 }
1078
1079 /**
1080 * @brief Enable slave output
1081 *
1082 * Register|BitsName
1083 * --------|--------
1084 * CTRL0 | SLVOE
1085 *
1086 * @param QSPIx QSPI instance
1087 * @retval None
1088 */
1089 __STATIC_INLINE void ll_qspi_enable_slave_out(qspi_regs_t *QSPIx)
1090 {
1091 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1092 }
1093
1094 /**
1095 * @brief Disable slave output
1096 *
1097 * Register|BitsName
1098 * --------|--------
1099 * CTRL0 | SLVOE
1100 *
1101 * @param QSPIx QSPI instance
1102 * @retval None
1103 */
1104 __STATIC_INLINE void ll_qspi_disable_salve_out(qspi_regs_t *QSPIx)
1105 {
1106 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1107 }
1108
1109 /**
1110 * @brief Check if slave output is enabled
1111 *
1112 * Register|BitsName
1113 * --------|--------
1114 * CTRL0 | SLVOE
1115 *
1116 * @param QSPIx QSPI instance
1117 * @retval State of bit (1 or 0).
1118 */
1119 __STATIC_INLINE uint32_t ll_qspi_is_enabled_slave_out(qspi_regs_t *QSPIx)
1120 {
1121 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE) != (QSPI_CTRL0_SLVOE));
1122 }
1123
1124 /**
1125 * @brief Set transfer direction mode
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * CTRL0 | TMOD
1130 *
1131 * @param QSPIx QSPI instance
1132 * @param transfer_direction This parameter can be one of the following values:
1133 * @arg @ref LL_QSPI_FULL_DUPLEX
1134 * @arg @ref LL_QSPI_SIMPLEX_TX
1135 * @arg @ref LL_QSPI_SIMPLEX_RX
1136 * @arg @ref LL_QSPI_READ_EEPROM
1137 * @retval None
1138 */
1139 __STATIC_INLINE void ll_qspi_set_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
1140 {
1141 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_TMOD, transfer_direction);
1142 }
1143
1144 /**
1145 * @brief Get transfer direction mode
1146 *
1147 * Register|BitsName
1148 * --------|--------
1149 * CTRL0 | TMOD
1150 *
1151 * @param QSPIx QSPI instance
1152 * @retval Returned value can be one of the following values:
1153 * @arg @ref LL_QSPI_FULL_DUPLEX
1154 * @arg @ref LL_QSPI_SIMPLEX_TX
1155 * @arg @ref LL_QSPI_SIMPLEX_RX
1156 * @arg @ref LL_QSPI_READ_EEPROM
1157 */
1158 __STATIC_INLINE uint32_t ll_qspi_get_transfer_direction(qspi_regs_t *QSPIx)
1159 {
1160 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_TMOD));
1161 }
1162
1163 /**
1164 * @brief Set clock polarity
1165 * @note This bit should not be changed when communication is ongoing.
1166 * This bit is not used in SPI TI mode.
1167 *
1168 * Register|BitsName
1169 * --------|--------
1170 * CTRL0 | SCPOL
1171 *
1172 * @param QSPIx QSPI instance
1173 * @param clock_polarity This parameter can be one of the following values:
1174 * @arg @ref LL_QSPI_SCPOL_LOW
1175 * @arg @ref LL_QSPI_SCPOL_HIGH
1176 * @retval None
1177 */
1178 __STATIC_INLINE void ll_qspi_set_clock_polarity(qspi_regs_t *QSPIx, uint32_t clock_polarity)
1179 {
1180 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPOL, clock_polarity);
1181 }
1182
1183 /**
1184 * @brief Get clock polarity
1185 *
1186 * Register|BitsName
1187 * --------|--------
1188 * CTRL0 | SCPOL
1189 *
1190 * @param QSPIx QSPI instance
1191 * @retval Returned value can be one of the following values:
1192 * @arg @ref LL_QSPI_SCPOL_LOW
1193 * @arg @ref LL_QSPI_SCPOL_HIGH
1194 */
1195 __STATIC_INLINE uint32_t ll_qspi_get_clock_polarity(qspi_regs_t *QSPIx)
1196 {
1197 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPOL));
1198 }
1199
1200 /**
1201 * @brief Set clock phase
1202 * @note This bit should not be changed when communication is ongoing.
1203 * This bit is not used in SPI TI mode.
1204 *
1205 * Register|BitsName
1206 * --------|--------
1207 * CTRL0 | SCPHA
1208 *
1209 * @param QSPIx QSPI instance
1210 * @param clock_phase This parameter can be one of the following values:
1211 * @arg @ref LL_QSPI_SCPHA_1EDGE
1212 * @arg @ref LL_QSPI_SCPHA_2EDGE
1213 * @retval None
1214 */
1215 __STATIC_INLINE void ll_qspi_set_clock_phase(qspi_regs_t *QSPIx, uint32_t clock_phase)
1216 {
1217 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPHA, clock_phase);
1218 }
1219
1220 /**
1221 * @brief Get clock phase
1222 *
1223 * Register|BitsName
1224 * --------|--------
1225 * CTRL0 | SCPHA
1226 *
1227 * @param QSPIx QSPI instance
1228 * @retval Returned value can be one of the following values:
1229 * @arg @ref LL_QSPI_SCPHA_1EDGE
1230 * @arg @ref LL_QSPI_SCPHA_2EDGE
1231 */
1232 __STATIC_INLINE uint32_t ll_qspi_get_clock_phase(qspi_regs_t *QSPIx)
1233 {
1234 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPHA));
1235 }
1236
1237 /**
1238 * @brief Set serial protocol used
1239 * @note This bit should be written only when SPI is disabled (QSPI_EN = 0) for correct operation.
1240 *
1241 * Register|BitsName
1242 * --------|--------
1243 * CTRL0 | FRF
1244 *
1245 * @param QSPIx QSPI instance
1246 * @param standard This parameter can be one of the following values:
1247 * @arg @ref LL_QSPI_PROTOCOL_MOTOROLA
1248 * @arg @ref LL_QSPI_PROTOCOL_TI
1249 * @arg @ref LL_QSPI_PROTOCOL_MICROWIRE
1250 * @retval None
1251 */
1252 __STATIC_INLINE void ll_qspi_set_standard(qspi_regs_t *QSPIx, uint32_t standard)
1253 {
1254 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_FRF, standard);
1255 }
1256
1257 /**
1258 * @brief Get serial protocol used
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * CTRL0 | FRF
1263 *
1264 * @param QSPIx QSPI instance
1265 * @retval Returned value can be one of the following values:
1266 * @arg @ref LL_QSPI_PROTOCOL_MOTOROLA
1267 * @arg @ref LL_QSPI_PROTOCOL_TI
1268 * @arg @ref LL_QSPI_PROTOCOL_MICROWIRE
1269 */
1270 __STATIC_INLINE uint32_t ll_qspi_get_standard(qspi_regs_t *QSPIx)
1271 {
1272 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_FRF));
1273 }
1274
1275 /**
1276 * @brief Set the number of data frames to be continuously received
1277 * @note These bits should not be changed when communication is ongoing.
1278 This bits are effect when TMOD = 2b10 or 2b11.
1279 This bits are not effect in SPIS.
1280 *
1281 * Register|BitsName
1282 * --------|--------
1283 * CTRL1 | NDF
1284 *
1285 * @param QSPIx QSPI instance
1286 * @param size This parameter can be one of the following values: 0 ~ 65535
1287 * @retval None
1288 */
1289 __STATIC_INLINE void ll_qspi_set_receive_size(qspi_regs_t *QSPIx, uint32_t size)
1290 {
1291 MODIFY_REG(QSPIx->CTRL1, QSPI_CTRL1_NDF, size);
1292 }
1293
1294 #define ll_qspi_set_xfer_size ll_qspi_set_receive_size
1295
1296 /**
1297 * @brief Get the number of data frames to be continuously received
1298 * @note These bits should not be changed when communication is ongoing.
1299 This bits are effect when TMOD = 2b10 or 2b11.
1300 This bits are not effect in SPIS.
1301 *
1302 * Register|BitsName
1303 * --------|--------
1304 * CTRL1 | NDF
1305 *
1306 * @param QSPIx QSPI instance
1307 * @retval Returned value can be one of the following values: 0 ~ 65535
1308 */
1309 __STATIC_INLINE uint32_t ll_qspi_get_receive_size(qspi_regs_t *QSPIx)
1310 {
1311 return (uint32_t)(READ_BITS(QSPIx->CTRL1, QSPI_CTRL1_NDF));
1312 }
1313
1314 /**
1315 * @brief Enable SPI peripheral
1316 *
1317 * Register|BitsName
1318 * --------|--------
1319 * QSPI_EN | EN
1320 *
1321 * @param QSPIx QSPI instance
1322 * @retval None
1323 */
1324 __STATIC_INLINE void ll_qspi_enable(qspi_regs_t *QSPIx)
1325 {
1326 SET_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1327 }
1328
1329 /**
1330 * @brief Disable SPI peripheral
1331 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
1332 *
1333 * Register|BitsName
1334 * --------|--------
1335 * QSPI_EN | EN
1336 *
1337 * @param QSPIx QSPI instance
1338 * @retval None
1339 */
1340 __STATIC_INLINE void ll_qspi_disable(qspi_regs_t *QSPIx)
1341 {
1342 CLEAR_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1343 }
1344
1345 /**
1346 * @brief Check if SPI peripheral is enabled
1347 *
1348 * Register|BitsName
1349 * --------|--------
1350 * QSPI_EN | EN
1351 *
1352 * @param QSPIx QSPI instance
1353 * @retval State of bit (1 or 0).
1354 */
1355 __STATIC_INLINE uint32_t ll_qspi_is_enabled(qspi_regs_t *QSPIx)
1356 {
1357 return (READ_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN) == (QSPI_SSI_EN));
1358 }
1359
1360 /**
1361 * @brief Enable Handshake in Microwire mode
1362 *
1363 * Register|BitsName
1364 * --------|--------
1365 * MWC | MHS
1366 *
1367 * @param QSPIx QSPI instance
1368 * @retval None
1369 */
1370 __STATIC_INLINE void ll_qspi_enable_micro_handshake(qspi_regs_t *QSPIx)
1371 {
1372 SET_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1373 }
1374
1375 /**
1376 * @brief Disable Handshake in Microwire mode
1377 *
1378 * Register|BitsName
1379 * --------|--------
1380 * MWC | MHS
1381 *
1382 * @param QSPIx QSPI instance
1383 * @retval None
1384 */
1385 __STATIC_INLINE void ll_qspi_disable_micro_handshake(qspi_regs_t *QSPIx)
1386 {
1387 CLEAR_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1388 }
1389
1390 /**
1391 * @brief Check if Handshake in Microwire mode is enabled
1392 *
1393 * Register|BitsName
1394 * --------|--------
1395 * MWC | MHS
1396 *
1397 * @param QSPIx QSPI instance
1398 * @retval State of bit (1 or 0).
1399 */
1400 __STATIC_INLINE uint32_t ll_qspi_is_enabled_micro_handshake(qspi_regs_t *QSPIx)
1401 {
1402 return (READ_BITS(QSPIx->MWC, QSPI_MWC_MHS) == (QSPI_MWC_MHS));
1403 }
1404
1405 /**
1406 * @brief Set transfer direction mode in Microwire mode
1407 * @note This bit should not be changed when communication is ongoing.
1408 *
1409 * Register|BitsName
1410 * --------|--------
1411 * MWC | MDD
1412 *
1413 * @param QSPIx QSPI instance
1414 * @param transfer_direction This parameter can be one of the following values:
1415 * @arg @ref LL_QSPI_MICROWIRE_RX
1416 * @arg @ref LL_QSPI_MICROWIRE_TX
1417 * @retval None
1418 */
1419 __STATIC_INLINE void ll_qspi_set_micro_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
1420 {
1421 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MDD, transfer_direction);
1422 }
1423
1424 /**
1425 * @brief Get transfer direction mode in Microwire mode
1426 * @note This bit should not be changed when communication is ongoing.
1427 *
1428 * Register|BitsName
1429 * --------|--------
1430 * MWC | MDD
1431 *
1432 * @param QSPIx QSPI instance
1433 * @retval Returned value can be one of the following values:
1434 * @arg @ref LL_QSPI_MICROWIRE_RX
1435 * @arg @ref LL_QSPI_MICROWIRE_TX
1436 */
1437 __STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_direction(qspi_regs_t *QSPIx)
1438 {
1439 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MDD));
1440 }
1441
1442 /**
1443 * @brief Set transfer mode in Microwire mode
1444 * @note This bit should not be changed when communication is ongoing.
1445 *
1446 * Register|BitsName
1447 * --------|--------
1448 * MWC | MWMOD
1449 *
1450 * @param QSPIx QSPI instance
1451 * @param transfer_mode This parameter can be one of the following values:
1452 * @arg @ref LL_QSPI_MICROWIRE_NON_SEQUENTIAL
1453 * @arg @ref LL_QSPI_MICROWIRE_SEQUENTIAL
1454 * @retval None
1455 */
1456 __STATIC_INLINE void ll_qspi_set_micro_transfer_mode(qspi_regs_t *QSPIx, uint32_t transfer_mode)
1457 {
1458 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MWMOD, transfer_mode);
1459 }
1460
1461 /**
1462 * @brief Get transfer mode in Microwire mode
1463 * @note This bit should not be changed when communication is ongoing.
1464 *
1465 * Register|BitsName
1466 * --------|--------
1467 * MWC | MWMOD
1468 *
1469 * @param QSPIx QSPI instance
1470 * @retval Returned value can be one of the following values:
1471 * @arg @ref LL_QSPI_MICROWIRE_NON_SEQUENTIAL
1472 * @arg @ref LL_QSPI_MICROWIRE_SEQUENTIAL
1473 */
1474 __STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_mode(qspi_regs_t *QSPIx)
1475 {
1476 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MWMOD));
1477 }
1478
1479 /**
1480 * @brief Enable slave select
1481 *
1482 * Register|BitsName
1483 * --------|--------
1484 * SE | SLAVE1
1485 * SE | SLAVE0
1486 *
1487 * @param QSPIx QSPI instance
1488 * @param ss This parameter can be one of the following values:
1489 * @arg @ref LL_QSPI_SLAVE1
1490 * @arg @ref LL_QSPI_SLAVE0
1491 * @retval None
1492 */
1493 __STATIC_INLINE void ll_qspi_enable_ss(qspi_regs_t *QSPIx, uint32_t ss)
1494 {
1495 SET_BITS(QSPIx->SE, ss);
1496 }
1497
1498 /**
1499 * @brief Disable slave select
1500 *
1501 * Register|BitsName
1502 * --------|--------
1503 * SE | SLAVE1
1504 * SE | SLAVE0
1505 *
1506 * @param QSPIx QSPI instance
1507 * @param ss This parameter can be one of the following values:
1508 * @arg @ref LL_QSPI_SLAVE1
1509 * @arg @ref LL_QSPI_SLAVE0
1510 * @retval None
1511 */
1512 __STATIC_INLINE void ll_qspi_disable_ss(qspi_regs_t *QSPIx, uint32_t ss)
1513 {
1514 CLEAR_BITS(QSPIx->SE, ss);
1515 }
1516
1517 /**
1518 * @brief Check if slave select is enabled
1519 *
1520 * Register|BitsName
1521 * --------|--------
1522 * SE | SLAVE1
1523 * SE | SLAVE0
1524 *
1525 * @param QSPIx QSPI instance
1526 * @param ss This parameter can be one of the following values:
1527 * @arg @ref LL_QSPI_SLAVE1
1528 * @arg @ref LL_QSPI_SLAVE0
1529 * @retval State of bit (1 or 0).
1530 */
1531 __STATIC_INLINE uint32_t ll_qspi_is_enabled_ss(qspi_regs_t *QSPIx, uint32_t ss)
1532 {
1533 return (READ_BITS(QSPIx->SE, ss) == ss);
1534 }
1535
1536 /**
1537 * @brief Set baud rate prescaler
1538 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1539 *
1540 * Register|BitsName
1541 * --------|--------
1542 * BAUD | SCKDIV
1543 *
1544 * @param QSPIx QSPI instance
1545 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1546 * @retval None
1547 */
1548 __STATIC_INLINE void ll_qspi_set_baud_rate_prescaler(qspi_regs_t *QSPIx, uint32_t baud_rate)
1549 {
1550 WRITE_REG(QSPIx->BAUD, baud_rate & QSPI_BAUD_SCKDIV);
1551 }
1552
1553 /**
1554 * @brief Get baud rate prescaler
1555 *
1556 * Register|BitsName
1557 * --------|--------
1558 * BAUD | SCKDIV
1559 *
1560 * @param QSPIx QSPI instance
1561 * @retval Returned value can be one even value between 2 and 65534.
1562 */
1563 __STATIC_INLINE uint32_t ll_qspi_get_baud_rate_prescaler(qspi_regs_t *QSPIx)
1564 {
1565 return (uint32_t)(READ_BITS(QSPIx->BAUD, QSPI_BAUD_SCKDIV));
1566 }
1567
1568 /**
1569 * @brief Set threshold of TX transfer start
1570 *
1571 * Register|BitsName
1572 * --------|--------
1573 * TXFTL | TXFTHR
1574 *
1575 * @param QSPIx QSPI instance
1576 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1577 * @retval None
1578 */
1579 __STATIC_INLINE void ll_qspi_set_tx_start_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1580 {
1581 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTHR_TFT, threshold << QSPI_TXFTHR_TFT_Pos);
1582 }
1583
1584 /**
1585 * @brief Get threshold of TX transfer start
1586 *
1587 * Register|BitsName
1588 * --------|--------
1589 * TXFTL | TXFTHR
1590 *
1591 * @param QSPIx QSPI instance
1592 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1593 */
1594 __STATIC_INLINE uint32_t ll_qspi_get_tx_start_fifo_threshold(qspi_regs_t *QSPIx)
1595 {
1596 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTHR_TFT) >> QSPI_TXFTHR_TFT_Pos);
1597 }
1598
1599 /**
1600 * @brief Set threshold of TXFIFO that triggers an TXE event
1601 *
1602 * Register|BitsName
1603 * --------|--------
1604 * TXFTL | TFT
1605 *
1606 * @param QSPIx QSPI instance
1607 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1608 * @retval None
1609 */
1610 __STATIC_INLINE void ll_qspi_set_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1611 {
1612 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTL_TFT, threshold << QSPI_TXFTL_TFT_Pos);
1613 }
1614
1615 /**
1616 * @brief Get threshold of TXFIFO that triggers an TXE event
1617 *
1618 * Register|BitsName
1619 * --------|--------
1620 * TXFTL | TFT
1621 *
1622 * @param QSPIx QSPI instance
1623 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1624 */
1625 __STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_threshold(qspi_regs_t *QSPIx)
1626 {
1627 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTL_TFT) >> QSPI_TXFTL_TFT_Pos);
1628 }
1629
1630 /**
1631 * @brief Set threshold of RXFIFO that triggers an RXNE event
1632 *
1633 * Register|BitsName
1634 * --------|--------
1635 * RXFTL | RFT
1636 *
1637 * @param QSPIx QSPI instance
1638 * @param threshold This parameter can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1639 * @retval None
1640 */
1641 __STATIC_INLINE void ll_qspi_set_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
1642 {
1643 WRITE_REG(QSPIx->RX_FTL, threshold);
1644 }
1645
1646 /**
1647 * @brief Get threshold of RXFIFO that triggers an RXNE event
1648 *
1649 * Register|BitsName
1650 * --------|--------
1651 * RXFTL | RFT
1652 *
1653 * @param QSPIx QSPI instance
1654 * @retval Returned value can be one of the following values: 0 ~ (FIFO_DEPTH - 1)
1655 */
1656 __STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_threshold(qspi_regs_t *QSPIx)
1657 {
1658 return (uint32_t)(READ_BITS(QSPIx->RX_FTL, QSPI_RXFTL_RFT));
1659 }
1660
1661 /**
1662 * @brief Get FIFO Transmission Level
1663 *
1664 * Register|BitsName
1665 * --------|--------
1666 * TXFL | TXTFL
1667 *
1668 * @param QSPIx QSPI instance
1669 * @retval Returned value can be one of the following values: 0 ~ FIFO_DEPTH
1670 */
1671 __STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_level(qspi_regs_t *QSPIx)
1672 {
1673 return (uint32_t)(READ_BITS(QSPIx->TX_FL, QSPI_TXFL_TXTFL));
1674 }
1675
1676 /**
1677 * @brief Get FIFO reception Level
1678 *
1679 * Register|BitsName
1680 * --------|--------
1681 * RXFL | RXTFL
1682 *
1683 * @param QSPIx QSPI instance
1684 * @retval Returned value can be one of the following values: 0 ~ FIFO_DEPTH
1685 */
1686 __STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_level(qspi_regs_t *QSPIx)
1687 {
1688 return (uint32_t)(READ_BITS(QSPIx->RX_FL, QSPI_RXFL_RXTFL));
1689 }
1690
1691 /**
1692 * @brief Get ID code
1693 *
1694 * Register|BitsName
1695 * --------|--------
1696 * IDCODE | ID
1697 *
1698 * @param QSPIx QSPI instance
1699 * @retval Returned value is const.
1700 */
1701 __STATIC_INLINE uint32_t ll_qspi_get_id_code(qspi_regs_t *QSPIx)
1702 {
1703 return (uint32_t)(READ_BITS(QSPIx->ID, QSPI_IDCODE_ID));
1704 }
1705
1706 /**
1707 * @brief Get IP version
1708 *
1709 * Register|BitsName
1710 * --------|--------
1711 * COMP | VERSION
1712 *
1713 * @param QSPIx QSPI instance
1714 * @retval Returned value is const.
1715 */
1716 __STATIC_INLINE uint32_t ll_qspi_get_version(qspi_regs_t *QSPIx)
1717 {
1718 return (uint32_t)(READ_BITS(QSPIx->VERSION_ID, QSPI_COMP_VERSION));
1719 }
1720
1721 /** @} */
1722
1723 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1724 * @{
1725 */
1726
1727 /**
1728 * @brief Enable interrupt
1729 * @note This bit controls the generation of an interrupt when an event occurs.
1730 *
1731 * Register|BitsName
1732 * --------|--------
1733 * INTMASK | INTMASK
1734 *
1735 * @param QSPIx QSPI instance
1736 * @param mask This parameter can be one of the following values:
1737 * @arg @ref LL_QSPI_IM_SPITE
1738 * @arg @ref LL_QSPI_IM_TXU
1739 * @arg @ref LL_QSPI_IM_XRXO
1740 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1741 * @arg @ref LL_QSPI_IM_RXF
1742 * @arg @ref LL_QSPI_IM_RXO
1743 * @arg @ref LL_QSPI_IM_RXU
1744 * @arg @ref LL_QSPI_IM_TXO
1745 * @arg @ref LL_QSPI_IM_TXE
1746 * @retval None
1747 */
1748 __STATIC_INLINE void ll_qspi_enable_it(qspi_regs_t *QSPIx, uint32_t mask)
1749 {
1750 SET_BITS(QSPIx->INTMASK, mask);
1751 }
1752
1753 /**
1754 * @brief Disable interrupt
1755 * @note This bit controls the generation of an interrupt when an event occurs.
1756 *
1757 * Register|BitsName
1758 * --------|--------
1759 * INTMASK | INTMASK
1760 *
1761 * @param QSPIx QSPI instance
1762 * @param mask This parameter can be one of the following values:
1763 * @arg @ref LL_QSPI_IM_SPITE
1764 * @arg @ref LL_QSPI_IM_TXU
1765 * @arg @ref LL_QSPI_IM_XRXO
1766 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1767 * @arg @ref LL_QSPI_IM_RXF
1768 * @arg @ref LL_QSPI_IM_RXO
1769 * @arg @ref LL_QSPI_IM_RXU
1770 * @arg @ref LL_QSPI_IM_TXO
1771 * @arg @ref LL_QSPI_IM_TXE
1772 * @retval None
1773 */
1774 __STATIC_INLINE void ll_qspi_disable_it(qspi_regs_t *QSPIx, uint32_t mask)
1775 {
1776 CLEAR_BITS(QSPIx->INTMASK, mask);
1777 }
1778
1779 /**
1780 * @brief Check if interrupt is enabled
1781 *
1782 * Register|BitsName
1783 * --------|--------
1784 * INTMASK | INTMASK
1785 *
1786 * @param QSPIx QSPI instance
1787 * @param mask This parameter can be one of the following values:
1788 * @arg @ref LL_QSPI_IM_SPITE
1789 * @arg @ref LL_QSPI_IM_TXU
1790 * @arg @ref LL_QSPI_IM_XRXO
1791 * @arg @ref LL_QSPI_IM_MST(not effect in SPIS)
1792 * @arg @ref LL_QSPI_IM_RXF
1793 * @arg @ref LL_QSPI_IM_RXO
1794 * @arg @ref LL_QSPI_IM_RXU
1795 * @arg @ref LL_QSPI_IM_TXO
1796 * @arg @ref LL_QSPI_IM_TXE
1797 * @retval State of bit (1 or 0).
1798 */
1799 __STATIC_INLINE uint32_t ll_qspi_is_enabled_it(qspi_regs_t *QSPIx, uint32_t mask)
1800 {
1801 return (READ_BITS(QSPIx->INTMASK, mask) == mask);
1802 }
1803
1804 /** @} */
1805
1806 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1807 * @{
1808 */
1809
1810 /**
1811 * @brief Get SPI status
1812 *
1813 * Register|BitsName
1814 * --------|--------
1815 * STAT | STAT
1816 *
1817 * @param QSPIx QSPI instance
1818 * @retval Returned value can be one or combination of the following values:
1819 * @arg @ref LL_QSPI_SR_DCOL(no effect in SPIS)
1820 * @arg @ref LL_QSPI_SR_TXE
1821 * @arg @ref LL_QSPI_SR_RFF
1822 * @arg @ref LL_QSPI_SR_RFNE
1823 * @arg @ref LL_QSPI_SR_TFE
1824 * @arg @ref LL_QSPI_SR_TFNF
1825 * @arg @ref LL_QSPI_SR_BUSY
1826 */
1827 __STATIC_INLINE uint32_t ll_qspi_get_status(qspi_regs_t *QSPIx)
1828 {
1829 return (uint32_t)(READ_REG(QSPIx->STAT));
1830 }
1831
1832 /**
1833 * @brief Check active flag
1834 *
1835 * Register|BitsName
1836 * --------|--------
1837 * STAT | DCOL
1838 * STAT | TXE
1839 * STAT | RFF
1840 * STAT | RFNE
1841 * STAT | TFE
1842 * STAT | TFNF
1843 * STAT | BUSY
1844 *
1845 * @param QSPIx QSPI instance
1846 * @param flag This parameter can be one of the following values:
1847 * @arg @ref LL_QSPI_SR_DCOL(no effect in SPIS)
1848 * @arg @ref LL_QSPI_SR_TXE
1849 * @arg @ref LL_QSPI_SR_RFF
1850 * @arg @ref LL_QSPI_SR_RFNE
1851 * @arg @ref LL_QSPI_SR_TFE
1852 * @arg @ref LL_QSPI_SR_TFNF
1853 * @arg @ref LL_QSPI_SR_BUSY
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t ll_qspi_is_active_flag(qspi_regs_t *QSPIx, uint32_t flag)
1857 {
1858 return (READ_BITS(QSPIx->STAT, flag) == (flag));
1859 }
1860
1861 /**
1862 * @brief Get SPI interrupt flags
1863 *
1864 * Register|BitsName
1865 * --------|--------
1866 * INTSTAT | INTSTAT
1867 *
1868 * @param QSPIx QSPI instance
1869 * @retval Returned value can be one or combination of the following values:
1870 * @arg @ref LL_QSPI_IS_SPITE
1871 * @arg @ref LL_QSPI_IS_TXU
1872 * @arg @ref LL_QSPI_IS_XRXO
1873 * @arg @ref LL_QSPI_IS_MST(no effect in SPIS)
1874 * @arg @ref LL_QSPI_IS_RXF
1875 * @arg @ref LL_QSPI_IS_RXO
1876 * @arg @ref LL_QSPI_IS_RXU
1877 * @arg @ref LL_QSPI_IS_TXO
1878 * @arg @ref LL_QSPI_IS_TXE
1879 */
1880 __STATIC_INLINE uint32_t ll_qspi_get_it_flag(qspi_regs_t *QSPIx)
1881 {
1882 return (uint32_t)(READ_REG(QSPIx->INTSTAT));
1883 }
1884
1885 /**
1886 * @brief Check interrupt flag
1887 *
1888 * Register|BitsName
1889 * --------|--------
1890 * INTSTAT | MSTIS
1891 * INTSTAT | RXFIS
1892 * INTSTAT | RXOIS
1893 * INTSTAT | RXUIS
1894 * INTSTAT | TXOIS
1895 * INTSTAT | TXEIS
1896 *
1897 * @param QSPIx QSPI instance
1898 * @param flag This parameter can be one of the following values:
1899 * @arg @ref LL_QSPI_IS_SPITE
1900 * @arg @ref LL_QSPI_IS_TXU
1901 * @arg @ref LL_QSPI_IS_XRXO
1902 * @arg @ref LL_QSPI_IS_MST(no effect in SPIS)
1903 * @arg @ref LL_QSPI_IS_RXF
1904 * @arg @ref LL_QSPI_IS_RXO
1905 * @arg @ref LL_QSPI_IS_RXU
1906 * @arg @ref LL_QSPI_IS_TXO
1907 * @arg @ref LL_QSPI_IS_TXE
1908 * @retval State of bit (1 or 0).
1909 */
1910 __STATIC_INLINE uint32_t ll_qspi_is_it_flag(qspi_regs_t *QSPIx, uint32_t flag)
1911 {
1912 return (READ_BITS(QSPIx->INTSTAT, flag) == flag);
1913 }
1914
1915 /**
1916 * @brief Get SPI raw interrupt flags
1917 *
1918 * Register|BitsName
1919 * --------|--------
1920 * RAW_INTSTAT | RAW_INTSTAT
1921 *
1922 * @param QSPIx QSPI instance
1923 * @retval Returned value can be one or combination of the following values:
1924 * @arg @ref LL_QSPI_RIS_SPITE
1925 * @arg @ref LL_QSPI_RIS_TXU
1926 * @arg @ref LL_QSPI_RIS_XRXO
1927 * @arg @ref LL_QSPI_RIS_MST(no effect in SPIS)
1928 * @arg @ref LL_QSPI_RIS_RXF
1929 * @arg @ref LL_QSPI_RIS_RXO
1930 * @arg @ref LL_QSPI_RIS_RXU
1931 * @arg @ref LL_QSPI_RIS_TXO
1932 * @arg @ref LL_QSPI_RIS_TXE
1933 */
1934 __STATIC_INLINE uint32_t ll_qspi_get_raw_if_flag(qspi_regs_t *QSPIx)
1935 {
1936 return (uint32_t)(READ_REG(QSPIx->RAW_INTSTAT));
1937 }
1938
1939 /**
1940 * @brief Clear transmit FIFO overflow error flag
1941 * @note Clearing this flag is done by reading TXOIC register
1942 *
1943 * Register|BitsName
1944 * --------|--------
1945 * TXOIC | TXOIC
1946 *
1947 * @param QSPIx QSPI instance
1948 * @retval None
1949 */
1950 __STATIC_INLINE void ll_qspi_clear_flag_txo(qspi_regs_t *QSPIx)
1951 {
1952 __IOM uint32_t tmpreg;
1953 tmpreg = QSPIx->TXOIC;
1954 (void) tmpreg;
1955 }
1956
1957 /**
1958 * @brief Clear receive FIFO overflow error flag
1959 * @note Clearing this flag is done by reading RXOIC register
1960 *
1961 * Register|BitsName
1962 * --------|--------
1963 * RXOIC | RXOIC
1964 *
1965 * @param QSPIx QSPI instance
1966 * @retval None
1967 */
1968 __STATIC_INLINE void ll_qspi_clear_flag_rxo(qspi_regs_t *QSPIx)
1969 {
1970 __IOM uint32_t tmpreg;
1971 tmpreg = QSPIx->RXOIC;
1972 (void) tmpreg;
1973 }
1974
1975 /**
1976 * @brief Clear receive FIFO underflow error flag
1977 * @note Clearing this flag is done by reading RXUIC register
1978 *
1979 * Register|BitsName
1980 * --------|--------
1981 * RXUIC | RXUIC
1982 *
1983 * @param QSPIx QSPI instance
1984 * @retval None
1985 */
1986 __STATIC_INLINE void ll_qspi_clear_flag_rxu(qspi_regs_t *QSPIx)
1987 {
1988 __IOM uint32_t tmpreg;
1989 tmpreg = QSPIx->RXUIC;
1990 (void) tmpreg;
1991 }
1992
1993 /**
1994 * @brief Clear multi-master error flag
1995 * @note Clearing this flag is done by reading MSTIC register
1996 *
1997 * Register|BitsName
1998 * --------|--------
1999 * MSTIC | MSTIC
2000 *
2001 * @param QSPIx QSPI instance
2002 * @retval None
2003 */
2004 __STATIC_INLINE void ll_qspi_clear_flag_mst(qspi_regs_t *QSPIx)
2005 {
2006 __IOM uint32_t tmpreg;
2007 tmpreg = QSPIx->MSTIC;
2008 (void) tmpreg;
2009 }
2010
2011 /**
2012 * @brief Clear XIP receive FIFO overflow flag
2013 * @note Clearing this flag is done by reading XRXOIC register
2014 *
2015 * Register|BitsName
2016 * --------|--------
2017 * XRXOIC | XRXOIC
2018 *
2019 * @param QSPIx QSPI instance
2020 * @retval None
2021 */
2022 __STATIC_INLINE void ll_qspi_clear_flag_xrxo(qspi_regs_t *QSPIx)
2023 {
2024 __IOM uint32_t tmpreg;
2025 tmpreg = QSPIx->XIP_RXOICR;
2026 (void) tmpreg;
2027 }
2028
2029 /**
2030 * @brief Clear all error(txo,rxu,rxo,mst) flag
2031 * @note Clearing this flag is done by reading INTCLR register
2032 *
2033 * Register|BitsName
2034 * --------|--------
2035 * INTCLR | INTCLR
2036 *
2037 * @param QSPIx QSPI instance
2038 * @retval None
2039 */
2040 __STATIC_INLINE void ll_qspi_clear_flag_all(qspi_regs_t *QSPIx)
2041 {
2042 __IOM uint32_t tmpreg;
2043 tmpreg = QSPIx->INTCLR;
2044 (void) tmpreg;
2045 }
2046
2047 /** @} */
2048
2049 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
2050 * @{
2051 */
2052
2053 /**
2054 * @brief Enable DMA Tx
2055 *
2056 * Register|BitsName
2057 * --------|--------
2058 * DMAC | TDMAE
2059 *
2060 * @param QSPIx QSPI instance
2061 * @retval None
2062 */
2063 __STATIC_INLINE void ll_qspi_enable_dma_req_tx(qspi_regs_t *QSPIx)
2064 {
2065 SET_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2066 }
2067
2068 /**
2069 * @brief Disable DMA Tx
2070 *
2071 * Register|BitsName
2072 * --------|--------
2073 * DMAC | TDMAE
2074 *
2075 * @param QSPIx QSPI instance
2076 * @retval None
2077 */
2078 __STATIC_INLINE void ll_qspi_disable_dma_req_tx(qspi_regs_t *QSPIx)
2079 {
2080 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2081 }
2082
2083 /**
2084 * @brief Check if DMA Tx is enabled
2085 *
2086 * Register|BitsName
2087 * --------|--------
2088 * DMAC | TDMAE
2089 *
2090 * @param QSPIx QSPI instance
2091 * @retval State of bit (1 or 0).
2092 */
2093 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_tx(qspi_regs_t *QSPIx)
2094 {
2095 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE) == (QSPI_DMAC_TDMAE));
2096 }
2097
2098 /**
2099 * @brief Enable DMA Rx
2100 *
2101 * Register|BitsName
2102 * --------|--------
2103 * DMAC | RDMAE
2104 *
2105 * @param QSPIx QSPI instance
2106 * @retval None
2107 */
2108 __STATIC_INLINE void ll_qspi_enable_dma_req_rx(qspi_regs_t *QSPIx)
2109 {
2110 SET_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2111 }
2112
2113 /**
2114 * @brief Disable DMA Rx
2115 *
2116 * Register|BitsName
2117 * --------|--------
2118 * DMAC | RDMAE
2119 *
2120 * @param QSPIx QSPI instance
2121 * @retval None
2122 */
2123 __STATIC_INLINE void ll_qspi_disable_dma_req_rx(qspi_regs_t *QSPIx)
2124 {
2125 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2126 }
2127
2128 /**
2129 * @brief Check if DMA Rx is enabled
2130 *
2131 * Register|BitsName
2132 * --------|--------
2133 * DMAC | RDMAE
2134 *
2135 * @param QSPIx QSPI instance
2136 * @retval State of bit (1 or 0).
2137 */
2138 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_rx(qspi_regs_t *QSPIx)
2139 {
2140 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE) == (QSPI_DMAC_RDMAE));
2141 }
2142
2143 /**
2144 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
2145 *
2146 * Register|BitsName
2147 * --------|--------
2148 * DMATDL | DMATDL
2149 *
2150 * @param QSPIx QSPI instance
2151 * @param threshold This parameter can be one of the following values: 0 ~ 7
2152 * @retval None
2153 */
2154 __STATIC_INLINE void ll_qspi_set_dma_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
2155 {
2156 WRITE_REG(QSPIx->DMA_TDL, threshold);
2157 }
2158
2159 /**
2160 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
2161 *
2162 * Register|BitsName
2163 * --------|--------
2164 * DMATDL | DMATDL
2165 *
2166 * @param QSPIx QSPI instance
2167 * @retval Returned value can be one of the following values: 0 ~ 7
2168 */
2169 __STATIC_INLINE uint32_t ll_qspi_get_dma_tx_fifo_threshold(qspi_regs_t *QSPIx)
2170 {
2171 return (uint32_t)(READ_BITS(QSPIx->DMA_TDL, QSPI_DMATDL_DMATDL));
2172 }
2173
2174 /**
2175 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
2176 *
2177 * Register|BitsName
2178 * --------|--------
2179 * DMARDL | DMARDL
2180 *
2181 * @param QSPIx QSPI instance
2182 * @param threshold This parameter can be one of the following values: 0 ~ 7
2183 * @retval None
2184 */
2185 __STATIC_INLINE void ll_qspi_set_dma_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
2186 {
2187 WRITE_REG(QSPIx->DMA_RDL, threshold);
2188 }
2189
2190 /**
2191 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
2192 *
2193 * Register|BitsName
2194 * --------|--------
2195 * DMARDL | DMARDL
2196 *
2197 * @param QSPIx QSPI instance
2198 * @retval Returned value can be one of the following values: 0 ~ 7
2199 */
2200 __STATIC_INLINE uint32_t ll_qspi_get_dma_rx_fifo_threshold(qspi_regs_t *QSPIx)
2201 {
2202 return (uint32_t)(READ_BITS(QSPIx->DMA_RDL, QSPI_DMARDL_DMARDL));
2203 }
2204
2205 /** @} */
2206
2207 /** @defgroup SPI_LL_EF_Data_Management Data_Management
2208 * @{
2209 */
2210
2211 /**
2212 * @brief Write 8-Bits in the data register
2213 *
2214 * Register|BitsName
2215 * --------|--------
2216 * DATA | DATA
2217 *
2218 * @param QSPIx QSPI instance
2219 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
2220 * @retval None
2221 */
2222 __STATIC_INLINE void ll_qspi_transmit_data8(qspi_regs_t *QSPIx, uint8_t tx_data)
2223 {
2224 *((__IOM uint8_t *)&QSPIx->DATA) = tx_data;
2225 }
2226
2227 /**
2228 * @brief Write 16-Bits in the data register
2229 *
2230 * Register|BitsName
2231 * --------|--------
2232 * DATA | DATA
2233 *
2234 * @param QSPIx QSPI instance
2235 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
2236 * @retval None
2237 */
2238 __STATIC_INLINE void ll_qspi_transmit_data16(qspi_regs_t *QSPIx, uint16_t tx_data)
2239 {
2240 *((__IOM uint16_t *)&QSPIx->DATA) = tx_data;
2241 }
2242
2243 /**
2244 * @brief Write 32-Bits in the data register
2245 *
2246 * Register|BitsName
2247 * --------|--------
2248 * DATA | DATA
2249 *
2250 * @param QSPIx QSPI instance
2251 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2252 * @retval None
2253 */
2254 __STATIC_INLINE void ll_qspi_transmit_data32(qspi_regs_t *QSPIx, uint32_t tx_data)
2255 {
2256 *((__IOM uint32_t *)&QSPIx->DATA) = tx_data;
2257 }
2258
2259 /**
2260 * @brief Read 8-Bits in the data register
2261 *
2262 * Register|BitsName
2263 * --------|--------
2264 * DATA | DATA
2265 *
2266 * @param QSPIx QSPI instance
2267 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
2268 */
2269 __STATIC_INLINE uint8_t ll_qspi_receive_data8(qspi_regs_t *QSPIx)
2270 {
2271 return (uint8_t)(READ_REG(QSPIx->DATA));
2272 }
2273
2274 /**
2275 * @brief Read 16-Bits in the data register
2276 *
2277 * Register|BitsName
2278 * --------|--------
2279 * DATA | DATA
2280 *
2281 * @param QSPIx QSPI instance
2282 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
2283 */
2284 __STATIC_INLINE uint16_t ll_qspi_receive_data16(qspi_regs_t *QSPIx)
2285 {
2286 return (uint16_t)(READ_REG(QSPIx->DATA));
2287 }
2288
2289 /**
2290 * @brief Read 32-Bits in the data register
2291 *
2292 * Register|BitsName
2293 * --------|--------
2294 * DATA | DATA
2295 *
2296 * @param QSPIx QSPI instance
2297 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2298 */
2299 __STATIC_INLINE uint32_t ll_qspi_receive_data32(qspi_regs_t *QSPIx)
2300 {
2301 return (uint32_t)(READ_REG(QSPIx->DATA));
2302 }
2303
2304 /**
2305 * @brief Set the RX sample edge
2306 *
2307 * Register|BitsName
2308 * --------|--------
2309 * RX_SAMPLE_DELAY | SE
2310 *
2311 * @param QSPIx QSPI instance
2312 * @param edge - @ ref LL_QSPI_RX_SAMPLE_POSITIVE_EDGE
2313 * @ ref LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE
2314 * @retval none
2315 */
2316 __STATIC_INLINE void ll_qspi_set_rx_sample_edge(qspi_regs_t *QSPIx, uint32_t edge)
2317 {
2318 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE, edge << QSPI_RX_SAMPLE_EDGE_Pos);
2319 }
2320
2321 /**
2322 * @brief Get the RX sample edge
2323 *
2324 * Register|BitsName
2325 * --------|--------
2326 * RX_SAMPLE_DELAY | SE
2327 *
2328 * @param QSPIx QSPI instance
2329 * @retval edge - @ ref LL_QSPI_RX_SAMPLE_POSITIVE_EDGE
2330 * @ ref LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE
2331 */
2332 __STATIC_INLINE uint32_t ll_qspi_get_rx_sample_edge(qspi_regs_t *QSPIx)
2333 {
2334 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE) >> QSPI_RX_SAMPLE_EDGE_Pos);
2335 }
2336
2337 /**
2338 * @brief Set Rx sample delay
2339 * @note This bit should not be changed when communication is ongoing.
2340 *
2341 * Register|BitsName
2342 * --------|--------
2343 * RX_SAMPLEDLY | RX_SAMPLEDLY
2344 *
2345 * @param QSPIx QSPI instance
2346 * @param delay This parameter can be one of the following values: 0 ~ 256
2347 * @retval None
2348 */
2349 __STATIC_INLINE void ll_qspi_set_rx_sample_delay(qspi_regs_t *QSPIx, uint32_t delay)
2350 {
2351 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY, delay);
2352 }
2353
2354 /**
2355 * @brief Get Rx sample delay
2356 * @note This bit should not be changed when communication is ongoing.
2357 *
2358 * Register|BitsName
2359 * --------|--------
2360 * RX_SAMPLEDLY | RX_SAMPLEDLY
2361 *
2362 * @param QSPIx QSPI instance
2363 * @retval Returned value can be one of the following values: 0 ~ 256
2364 */
2365 __STATIC_INLINE uint32_t ll_qspi_get_rx_sample_delay(qspi_regs_t *QSPIx)
2366 {
2367 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY));
2368 }
2369
2370 /**
2371 * @brief Enable the clock stretch feature for Enhanced SPI
2372 * @note This bit should not be changed when communication is ongoing.
2373 *
2374 * Register|BitsName
2375 * --------|--------
2376 * SCTRL0 | CLK_STRETCH_EN
2377 *
2378 * @param QSPIx QSPI instance
2379 * @retval None
2380 */
2381 __STATIC_INLINE void ll_qspi_enable_clk_stretch(qspi_regs_t *QSPIx)
2382 {
2383 SET_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2384 }
2385
2386 /**
2387 * @brief Disable the clock stretch feature for Enhanced SPI
2388 * @note This bit should not be changed when communication is ongoing.
2389 *
2390 * Register|BitsName
2391 * --------|--------
2392 * SCTRL0 | CLK_STRETCH_EN
2393 *
2394 * @param QSPIx QSPI instance
2395 * @retval None
2396 */
2397 __STATIC_INLINE void ll_qspi_disable_clk_stretch(qspi_regs_t *QSPIx)
2398 {
2399 CLEAR_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2400 }
2401
2402 /**
2403 * @brief Check if the clock stretch feature is enabled or not for Enhanced SPI
2404 * @note This bit should not be changed when communication is ongoing.
2405 *
2406 * Register|BitsName
2407 * --------|--------
2408 * SCTRL0 | CLK_STRETCH_EN
2409 *
2410 * @param QSPIx QSPI instance
2411 * @retval None
2412 */
2413 __STATIC_INLINE uint32_t ll_qspi_is_enabled_clk_stretch(qspi_regs_t *QSPIx)
2414 {
2415 return (READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN) == (QSPI_SCTRL0_CLK_STRETCH_EN));
2416 }
2417
2418 /**
2419 * @brief Set number of wait cycles in Dual/Quad SPI mode
2420 * @note This bit should not be changed when communication is ongoing.
2421 *
2422 * Register|BitsName
2423 * --------|--------
2424 * SCTRL0 | WAITCYCLES
2425 *
2426 * @param QSPIx QSPI instance
2427 * @param wait_cycles This parameter can be one of the following values: 0 ~ 31
2428 * @retval None
2429 */
2430 __STATIC_INLINE void ll_qspi_set_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
2431 {
2432 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES, wait_cycles << QSPI_SCTRL0_WAITCYCLES_Pos);
2433 }
2434
2435 /**
2436 * @brief Get number of wait cycles in Dual/Quad SPI mode
2437 * @note This bit should not be changed when communication is ongoing.
2438 *
2439 * Register|BitsName
2440 * --------|--------
2441 * SCTRL0 | WAITCYCLES
2442 *
2443 * @param QSPIx QSPI instance
2444 * @retval Returned value can be one of the following values: 0 ~ 31
2445 */
2446 __STATIC_INLINE uint32_t ll_qspi_get_wait_cycles(qspi_regs_t *QSPIx)
2447 {
2448 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES) >> QSPI_SCTRL0_WAITCYCLES_Pos);
2449 }
2450
2451 /**
2452 * @brief Set Dual/Quad SPI mode instruction length in bits
2453 * @note This bit should not be changed when communication is ongoing.
2454 *
2455 * Register|BitsName
2456 * --------|--------
2457 * SCTRL0 | INSTL
2458 *
2459 * @param QSPIx QSPI instance
2460 * @param size This parameter can be one of the following values:
2461 * @arg @ref LL_QSPI_INSTSIZE_0BIT
2462 * @arg @ref LL_QSPI_INSTSIZE_4BIT
2463 * @arg @ref LL_QSPI_INSTSIZE_8BIT
2464 * @arg @ref LL_QSPI_INSTSIZE_16BIT
2465 * @retval None
2466 */
2467 __STATIC_INLINE void ll_qspi_set_instruction_size(qspi_regs_t *QSPIx, uint32_t size)
2468 {
2469 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL, size);
2470 }
2471
2472 /**
2473 * @brief Get Dual/Quad SPI mode instruction length in bits
2474 * @note This bit should not be changed when communication is ongoing.
2475 *
2476 * Register|BitsName
2477 * --------|--------
2478 * SCTRL0 | INSTL
2479 *
2480 * @param QSPIx QSPI instance
2481 * @retval Returned value can be one of the following values:
2482 * @arg @ref LL_QSPI_INSTSIZE_0BIT
2483 * @arg @ref LL_QSPI_INSTSIZE_4BIT
2484 * @arg @ref LL_QSPI_INSTSIZE_8BIT
2485 * @arg @ref LL_QSPI_INSTSIZE_16BIT
2486 */
2487 __STATIC_INLINE uint32_t ll_qspi_get_instruction_size(qspi_regs_t *QSPIx)
2488 {
2489 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL));
2490 }
2491
2492 /**
2493 * @brief Set Dual/Quad SPI mode address length in bits
2494 * @note This bit should not be changed when communication is ongoing.
2495 *
2496 * Register|BitsName
2497 * --------|--------
2498 * SCTRL0 | ADDRL
2499 *
2500 * @param QSPIx QSPI instance
2501 * @param size This parameter can be one of the following values:
2502 * @arg @ref LL_QSPI_ADDRSIZE_0BIT
2503 * @arg @ref LL_QSPI_ADDRSIZE_4BIT
2504 * @arg @ref LL_QSPI_ADDRSIZE_8BIT
2505 * @arg @ref LL_QSPI_ADDRSIZE_12BIT
2506 * @arg @ref LL_QSPI_ADDRSIZE_16BIT
2507 * @arg @ref LL_QSPI_ADDRSIZE_20BIT
2508 * @arg @ref LL_QSPI_ADDRSIZE_24BIT
2509 * @arg @ref LL_QSPI_ADDRSIZE_28BIT
2510 * @arg @ref LL_QSPI_ADDRSIZE_32BIT
2511 * @arg @ref LL_QSPI_ADDRSIZE_36BIT
2512 * @arg @ref LL_QSPI_ADDRSIZE_40BIT
2513 * @arg @ref LL_QSPI_ADDRSIZE_44BIT
2514 * @arg @ref LL_QSPI_ADDRSIZE_48BIT
2515 * @arg @ref LL_QSPI_ADDRSIZE_52BIT
2516 * @arg @ref LL_QSPI_ADDRSIZE_56BIT
2517 * @arg @ref LL_QSPI_ADDRSIZE_60BIT
2518 * @retval None
2519 */
2520 __STATIC_INLINE void ll_qspi_set_address_size(qspi_regs_t *QSPIx, uint32_t size)
2521 {
2522 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL, size);
2523 }
2524
2525 /**
2526 * @brief Get Dual/Quad SPI mode address length in bits
2527 * @note This bit should not be changed when communication is ongoing.
2528 *
2529 * Register|BitsName
2530 * --------|--------
2531 * SCTRL0 | ADDRL
2532 *
2533 * @param QSPIx QSPI instance
2534 * @retval Returned value can be one of the following values:
2535 * @arg @ref LL_QSPI_ADDRSIZE_0BIT
2536 * @arg @ref LL_QSPI_ADDRSIZE_4BIT
2537 * @arg @ref LL_QSPI_ADDRSIZE_8BIT
2538 * @arg @ref LL_QSPI_ADDRSIZE_12BIT
2539 * @arg @ref LL_QSPI_ADDRSIZE_16BIT
2540 * @arg @ref LL_QSPI_ADDRSIZE_20BIT
2541 * @arg @ref LL_QSPI_ADDRSIZE_24BIT
2542 * @arg @ref LL_QSPI_ADDRSIZE_28BIT
2543 * @arg @ref LL_QSPI_ADDRSIZE_32BIT
2544 * @arg @ref LL_QSPI_ADDRSIZE_36BIT
2545 * @arg @ref LL_QSPI_ADDRSIZE_40BIT
2546 * @arg @ref LL_QSPI_ADDRSIZE_44BIT
2547 * @arg @ref LL_QSPI_ADDRSIZE_48BIT
2548 * @arg @ref LL_QSPI_ADDRSIZE_52BIT
2549 * @arg @ref LL_QSPI_ADDRSIZE_56BIT
2550 * @arg @ref LL_QSPI_ADDRSIZE_60BIT
2551 */
2552 __STATIC_INLINE uint32_t ll_qspi_get_address_size(qspi_regs_t *QSPIx)
2553 {
2554 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL));
2555 }
2556
2557 /**
2558 * @brief Set Dual/Quad SPI mode address and instruction transfer format
2559 * @note This bit should not be changed when communication is ongoing.
2560 *
2561 * Register|BitsName
2562 * --------|--------
2563 * SCTRL0 | TRANSTYPE
2564 *
2565 * @param QSPIx QSPI instance
2566 * @param format This parameter can be one of the following values:
2567 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPI
2568 * @arg @ref LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
2569 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPIFRF
2570 * @retval None
2571 */
2572 __STATIC_INLINE void ll_qspi_set_add_inst_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
2573 {
2574 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE, format);
2575 }
2576
2577 /**
2578 * @brief Get Dual/Quad SPI mode address and instruction transfer format
2579 * @note This bit should not be changed when communication is ongoing.
2580 *
2581 * Register|BitsName
2582 * --------|--------
2583 * SCTRL0 | TRANSTYPE
2584 *
2585 * @param QSPIx QSPI instance
2586 * @retval Returned value can be one of the following values:
2587 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPI
2588 * @arg @ref LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
2589 * @arg @ref LL_QSPI_INST_ADDR_ALL_IN_SPIFRF
2590 */
2591 __STATIC_INLINE uint32_t ll_qspi_get_addr_inst_transfer_format(qspi_regs_t *QSPIx)
2592 {
2593 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE));
2594 }
2595
2596
2597
2598 /**
2599 * @brief Enable the mode bits phase for concurrent xip mode
2600 * @note This bit should not be changed when xip is ongoing.
2601 *
2602 * Register|BitsName
2603 * --------|--------
2604 * XIP_CTRL | MD_BITS_EN
2605 *
2606 * @param QSPIx - QSPI instance
2607 * @retval none
2608 */
2609 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_mode_bits(qspi_regs_t *QSPIx)
2610 {
2611 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2612 }
2613
2614 /**
2615 * @brief Disable the mode bits phase for concurrent xip mode
2616 * @note This bit should not be changed when xip is ongoing.
2617 *
2618 * Register|BitsName
2619 * --------|--------
2620 * XIP_CTRL | MD_BITS_EN
2621 *
2622 * @param QSPIx - QSPI instance
2623 * @retval none
2624 */
2625 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_mode_bits(qspi_regs_t *QSPIx)
2626 {
2627 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2628 }
2629
2630 /**
2631 * @brief Check if the mode bits phase is enabled or not for concurrent xip mode
2632 * @note This bit should not be changed when xip is ongoing.
2633 *
2634 * Register|BitsName
2635 * --------|--------
2636 * XIP_CTRL | MD_BITS_EN
2637 *
2638 * @param QSPIx - QSPI instance
2639 * @retval TRUE/FALSE
2640 */
2641 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_mode_bits(qspi_regs_t *QSPIx)
2642 {
2643 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN) == (QSPI_XCTRL_MD_BIT_EN));
2644 }
2645
2646 /**
2647 * @brief Set the length of mode bits phase for concurrent xip mode
2648 * @note This bit should not be changed when xip is ongoing.
2649 *
2650 * Register|BitsName
2651 * --------|--------
2652 * XIP_CTRL | XIP_MBL
2653 *
2654 * @param QSPIx - QSPI instance
2655 * @param mbl - @ref LL_QSPI_CONCURRENT_XIP_MBL_2
2656 * @ref LL_QSPI_CONCURRENT_XIP_MBL_4
2657 * @ref LL_QSPI_CONCURRENT_XIP_MBL_8
2658 * @ref LL_QSPI_CONCURRENT_XIP_MBL_16
2659 * @retval none
2660 */
2661 __STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_length(qspi_regs_t *QSPIx, uint32_t mbl)
2662 {
2663 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL, mbl << QSPI_XCTRL_XIP_MBL_Pos);
2664 }
2665
2666 /**
2667 * @brief Get the length of mode bits phase for concurrent xip mode
2668 * @note This bit should not be changed when xip is ongoing.
2669 *
2670 * Register|BitsName
2671 * --------|--------
2672 * XIP_CTRL | XIP_MBL
2673 *
2674 * @param QSPIx - QSPI instance
2675 * @retval mbl - @ref LL_QSPI_CONCURRENT_XIP_MBL_2
2676 * @ref LL_QSPI_CONCURRENT_XIP_MBL_4
2677 * @ref LL_QSPI_CONCURRENT_XIP_MBL_8
2678 * @ref LL_QSPI_CONCURRENT_XIP_MBL_16
2679 */
2680 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_length(qspi_regs_t *QSPIx)
2681 {
2682 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL) >> QSPI_XCTRL_XIP_MBL_Pos);
2683 }
2684
2685 /**
2686 * @brief set the mode phase (sent after address phase) value in xip mode
2687 * @note This bit should not be changed when xip is ongoing.
2688 *
2689 * Register|BitsName
2690 * --------|--------
2691 * XIP_MODE_BITS | XIP_MD_BITS
2692 *
2693 * @param QSPIx - QSPI instance
2694 * @param mode - mode value, [0 ~ 0xFFFF]
2695 * @retval None
2696 */
2697 __STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_data(qspi_regs_t *QSPIx, uint32_t mode)
2698 {
2699 MODIFY_REG(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS, mode << QSPI_XIP_MODE_BITS_Pos);
2700 }
2701
2702 /**
2703 * @brief get the mode phase (sent after address phase) value in xip mode
2704 * @note This bit should not be changed when xip is ongoing.
2705 *
2706 * Register|BitsName
2707 * --------|--------
2708 * XIP_MODE_BITS | XIP_MD_BITS
2709 *
2710 * @param QSPIx - QSPI instance
2711 * @retval mode value, [0 ~ 0xFFFF]
2712 */
2713 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_data(qspi_regs_t *QSPIx)
2714 {
2715 return (uint32_t)(READ_BITS(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS) >> QSPI_XIP_MODE_BITS_Pos);
2716 }
2717
2718 /**
2719 * @brief set the ahb-incr transfer instruction in xip mode
2720 * @note This bit should not be changed when xip is ongoing.
2721 *
2722 * Register|BitsName
2723 * --------|--------
2724 * XIP_INCR_INST | INCR_INST
2725 *
2726 * @param QSPIx - QSPI instance
2727 * @param inst - instruction op-code, [0 ~ 0xFFFF]
2728 * @retval None
2729 */
2730 __STATIC_INLINE void ll_qspi_concurrent_set_xip_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
2731 {
2732 MODIFY_REG(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST, inst << QSPI_XIP_INCR_INST_Pos);
2733 }
2734
2735 /**
2736 * @brief get the ahb-incr transfer instruction in xip mode
2737 * @note This bit should not be changed when xip is ongoing.
2738 *
2739 * Register|BitsName
2740 * --------|--------
2741 * XIP_INCR_INST | INCR_INST
2742 *
2743 * @param QSPIx - QSPI instance
2744 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
2745 */
2746 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_incr_inst(qspi_regs_t *QSPIx)
2747 {
2748 return (uint32_t)(READ_BITS(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST) >> QSPI_XIP_INCR_INST_Pos);
2749 }
2750
2751 /**
2752 * @brief set the ahb-wrap transfer instruction in xip mode
2753 * @note This bit should not be changed when xip is ongoing.
2754 *
2755 * Register|BitsName
2756 * --------|--------
2757 * XIP_WRAP_INST | WRAP_INST
2758 *
2759 * @param QSPIx - QSPI instance
2760 * @param inst - wrap instruction op-code, [0 ~ 0xFFFF]
2761 * @retval None
2762 */
2763 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
2764 {
2765 MODIFY_REG(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST, inst << QSPI_XIP_WRAP_INST_Pos);
2766 }
2767
2768 /**
2769 * @brief get the ahb-wrap transfer instruction in xip mode
2770 * @note This bit should not be changed when xip is ongoing.
2771 *
2772 * Register|BitsName
2773 * --------|--------
2774 * XIP_WRAP_INST | WRAP_INST
2775 *
2776 * @param QSPIx - QSPI instance
2777 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
2778 */
2779 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wrap_inst(qspi_regs_t *QSPIx)
2780 {
2781 return (uint32_t)(READ_BITS(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST) >> QSPI_XIP_WRAP_INST_Pos);
2782 }
2783
2784 /**
2785 * @brief Enable the slave in xip mode
2786 * @note This bit should not be changed when xip is ongoing.
2787 *
2788 * Register|BitsName
2789 * --------|--------
2790 * XIP_SER | SER
2791 *
2792 * @param QSPIx - QSPI instance
2793 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2794 * @retval None
2795 */
2796 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2797 {
2798 SET_BITS(QSPIx->XIP_SER, ss);
2799 }
2800
2801 /**
2802 * @brief Disable the slave in xip mode
2803 * @note This bit should not be changed when xip is ongoing.
2804 *
2805 * Register|BitsName
2806 * --------|--------
2807 * XIP_SER | SER
2808 *
2809 * @param QSPIx - QSPI instance
2810 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2811 * @retval None
2812 */
2813 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2814 {
2815 CLEAR_BITS(QSPIx->XIP_SER, ss);
2816 }
2817
2818 /**
2819 * @brief Check if the slave is enabled or not for concurrent xip mode
2820 * @note This bit should not be changed when xip is ongoing.
2821 *
2822 * Register|BitsName
2823 * --------|--------
2824 * XIP_SER | SER
2825 *
2826 * @param QSPIx - QSPI instance
2827 * @param ss - @ref LL_QSPI_CONCURRENT_XIP_SLAVE0
2828 * @retval None
2829 */
2830 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
2831 {
2832 return (READ_BITS(QSPIx->XIP_SER, ss) == ss);
2833 }
2834
2835 /**
2836 * @brief Set time out count for continuous transfer for xip mode
2837 * @note This bit should not be changed when xip is ongoing.
2838 *
2839 * Register|BitsName
2840 * --------|--------
2841 * XIP_CNT_TIME_OUT | XTOC
2842 *
2843 * @param QSPIx - QSPI instance
2844 * @param xtoc - time out counter value in terms of hclk [0 ~ 0xFF]
2845 * @retval None
2846 */
2847 __STATIC_INLINE void ll_qspi_concurrent_set_xip_toc(qspi_regs_t *QSPIx, uint32_t xtoc)
2848 {
2849 MODIFY_REG(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT, xtoc << QSPI_XIP_TOCNT_Pos);
2850 }
2851
2852 /**
2853 * @brief Get time out count for continuous transfer for xip mode
2854 * @note This bit should not be changed when xip is ongoing.
2855 *
2856 * Register|BitsName
2857 * --------|--------
2858 * XIP_CNT_TIME_OUT | XTOC
2859 *
2860 * @param QSPIx - QSPI instance
2861 * @retval xtoc - time out counter value in terms of hclk [0 ~ 0xFF]
2862 */
2863 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_toc(qspi_regs_t *QSPIx)
2864 {
2865 return (uint32_t)(READ_BITS(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT) >> QSPI_XIP_TOCNT_Pos);
2866 }
2867
2868 /**
2869 * @brief Enable the pre-fetch feature for concurrent xip mode
2870 * @note This bit should not be changed when xip is ongoing.
2871 *
2872 * Register|BitsName
2873 * --------|--------
2874 * XIP_CTRL | XIP_PREFETCH_EN
2875 *
2876 * @param QSPIx - QSPI instance
2877 * @retval none
2878 */
2879 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_prefetch(qspi_regs_t *QSPIx)
2880 {
2881 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2882 }
2883
2884 /**
2885 * @brief Disable the pre-fetch feature for concurrent xip mode
2886 * @note This bit should not be changed when xip is ongoing.
2887 *
2888 * Register|BitsName
2889 * --------|--------
2890 * XIP_CTRL | XIP_PREFETCH_EN
2891 *
2892 * @param QSPIx - QSPI instance
2893 * @retval none
2894 */
2895 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_prefetch(qspi_regs_t *QSPIx)
2896 {
2897 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2898 }
2899
2900 /**
2901 * @brief check if the pre-fetch feature is enabled or not for concurrent xip mode
2902 * @note This bit should not be changed when xip is ongoing.
2903 *
2904 * Register|BitsName
2905 * --------|--------
2906 * XIP_CTRL | XIP_PREFETCH_EN
2907 *
2908 * @param QSPIx - QSPI instance
2909 * @retval TRUE/FALSE
2910 */
2911 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_prefetch(qspi_regs_t *QSPIx)
2912 {
2913 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN) == (QSPI_XCTRL_XIP_PREFETCH_EN));
2914 }
2915
2916 /**
2917 * @brief Enable the continuous transfer feature for concurrent xip mode
2918 * @note This bit should not be changed when xip is ongoing.
2919 *
2920 * Register|BitsName
2921 * --------|--------
2922 * XIP_CTRL | CONT_XFER_EN
2923 *
2924 * @param QSPIx - QSPI instance
2925 * @retval none
2926 */
2927 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_continuous_xfer(qspi_regs_t *QSPIx)
2928 {
2929 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2930 }
2931
2932 /**
2933 * @brief Disable the continuous transfer feature for concurrent xip mode
2934 * @note This bit should not be changed when xip is ongoing.
2935 *
2936 * Register|BitsName
2937 * --------|--------
2938 * XIP_CTRL | CONT_XFER_EN
2939 *
2940 * @param QSPIx - QSPI instance
2941 * @retval none
2942 */
2943 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_continuous_xfer(qspi_regs_t *QSPIx)
2944 {
2945 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2946 }
2947
2948 /**
2949 * @brief Check if the continuous transfer feature is enabled or not for concurrent xip mode
2950 * @note This bit should not be changed when xip is ongoing.
2951 *
2952 * Register|BitsName
2953 * --------|--------
2954 * XIP_CTRL | CONT_XFER_EN
2955 *
2956 * @param QSPIx - QSPI instance
2957 * @retval TRUE/FALSE
2958 */
2959 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_continuous_xfer(qspi_regs_t *QSPIx)
2960 {
2961 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN) == (QSPI_XCTRL_CONT_XFER_EN));
2962 }
2963
2964 /**
2965 * @brief Enable the instruction phase for concurrent xip mode
2966 * @note This bit should not be changed when xip is ongoing.
2967 *
2968 * Register|BitsName
2969 * --------|--------
2970 * XIP_CTRL | INST_EN
2971 *
2972 * @param QSPIx - QSPI instance
2973 * @retval none
2974 */
2975 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_instruction(qspi_regs_t *QSPIx)
2976 {
2977 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
2978 }
2979
2980 /**
2981 * @brief Disable the instruction phase for concurrent xip mode
2982 * @note This bit should not be changed when xip is ongoing.
2983 *
2984 * Register|BitsName
2985 * --------|--------
2986 * XIP_CTRL | INST_EN
2987 *
2988 * @param QSPIx - QSPI instance
2989 * @retval none
2990 */
2991 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_instruction(qspi_regs_t *QSPIx)
2992 {
2993 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
2994 }
2995
2996 /**
2997 * @brief Check if the instruction phase is enabled or not for concurrent xip mode
2998 * @note This bit should not be changed when xip is ongoing.
2999 *
3000 * Register|BitsName
3001 * --------|--------
3002 * XIP_CTRL | INST_EN
3003 *
3004 * @param QSPIx - QSPI instance
3005 * @retval TRUE/FALSE
3006 */
3007 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_instruction(qspi_regs_t *QSPIx)
3008 {
3009 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN) == (QSPI_XCTRL_INST_EN));
3010 }
3011
3012 /**
3013 * @brief Set the instruction size for concurrent xip mode
3014 * @note This bit should not be changed when xip is ongoing.
3015 *
3016 * Register|BitsName
3017 * --------|--------
3018 * XIP_CTRL | INST_L
3019 *
3020 * @param QSPIx - QSPI instance
3021 * @param inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3022 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3023 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3024 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3025 * @retval none
3026 */
3027 __STATIC_INLINE void ll_qspi_concurrent_set_xip_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
3028 {
3029 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL, inst_size << QSPI_XCTRL_INSTL_Pos);
3030 }
3031
3032 /**
3033 * @brief Get the instruction size for concurrent xip mode
3034 * @note This bit should not be changed when xip is ongoing.
3035 *
3036 * Register|BitsName
3037 * --------|--------
3038 * XIP_CTRL | INST_L
3039 *
3040 * @param QSPIx - QSPI instance
3041 * @retval inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3042 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3043 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3044 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3045 */
3046 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_instruction_size(qspi_regs_t *QSPIx)
3047 {
3048 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL) >> QSPI_XCTRL_INSTL_Pos);
3049 }
3050
3051
3052 /**
3053 * @brief Enable the hardcoded DFS feature for concurrent xip mode
3054 * @note This bit should not be changed when xip is ongoing.
3055 *
3056 * Register|BitsName
3057 * --------|--------
3058 * XIP_CTRL | DFS_HC
3059 *
3060 * @param QSPIx - QSPI instance
3061 * @retval none
3062 */
3063 __STATIC_INLINE void ll_qspi_concurrent_enable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3064 {
3065 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3066 }
3067
3068 /**
3069 * @brief Disable the hardcoded DFS feature for concurrent xip mode
3070 * @note This bit should not be changed when xip is ongoing.
3071 *
3072 * Register|BitsName
3073 * --------|--------
3074 * XIP_CTRL | DFS_HC
3075 *
3076 * @param QSPIx - QSPI instance
3077 * @retval none
3078 */
3079 __STATIC_INLINE void ll_qspi_concurrent_disable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3080 {
3081 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3082 }
3083
3084 /**
3085 * @brief Check if the hardcoded DFS feature is enabled or not for concurrent xip mode
3086 * @note This bit should not be changed when xip is ongoing.
3087 *
3088 * Register|BitsName
3089 * --------|--------
3090 * XIP_CTRL | DFS_HC
3091 *
3092 * @param QSPIx - QSPI instance
3093 * @retval TRUE/FALSE
3094 */
3095 __STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_dfs_hardcode(qspi_regs_t *QSPIx)
3096 {
3097 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC) == (QSPI_XCTRL_DFS_HC));
3098 }
3099
3100 /**
3101 * @brief Set the wait(also called dummy) cycles for concurrent xip mode
3102 * @note This bit should not be changed when xip is ongoing.
3103 *
3104 * Register|BitsName
3105 * --------|--------
3106 * XIP_CTRL | WAIT_CYCLES
3107 *
3108 * @param QSPIx - QSPI instance
3109 * @param wait_cycles - 0 ~ 31
3110 * @retval none
3111 */
3112 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
3113 {
3114 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES, wait_cycles << QSPI_XCTRL_WAITCYCLES_Pos);
3115 }
3116
3117 /**
3118 * @brief Get the wait(also called dummy) cycles for concurrent xip mode
3119 * @note This bit should not be changed when xip is ongoing.
3120 *
3121 * Register|BitsName
3122 * --------|--------
3123 * XIP_CTRL | WAIT_CYCLES
3124 *
3125 * @param QSPIx - QSPI instance
3126 * @retval wait_cycles - 0 ~ 31
3127 */
3128 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wait_cycles(qspi_regs_t *QSPIx)
3129 {
3130 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES) >> QSPI_XCTRL_WAITCYCLES_Pos);
3131 }
3132
3133 /**
3134 * @brief Set the address size for concurrent xip mode
3135 * @note This bit should not be changed when xip is ongoing.
3136 *
3137 * Register|BitsName
3138 * --------|--------
3139 * XIP_CTRL | ADDR_L
3140 *
3141 * @param QSPIx - QSPI instance
3142 * @param addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3143 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3144 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3145 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3146 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3147 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3148 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3149 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3150 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3151 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
3152 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
3153 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
3154 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
3155 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
3156 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
3157 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
3158 *
3159 * @retval none
3160 */
3161 __STATIC_INLINE void ll_qspi_concurrent_set_xip_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
3162 {
3163 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL, addr_size << QSPI_XCTRL_ADDRL_Pos);
3164 }
3165
3166 /**
3167 * @brief Get the address size for concurrent xip mode
3168 * @note This bit should not be changed when xip is ongoing.
3169 *
3170 * Register|BitsName
3171 * --------|--------
3172 * XIP_CTRL | ADDR_L
3173 *
3174 * @param QSPIx - QSPI instance
3175 * @retval addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3176 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3177 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3178 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3179 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3180 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3181 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3182 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3183 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3184 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
3185 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
3186 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
3187 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
3188 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
3189 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
3190 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
3191 */
3192 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_address_size(qspi_regs_t *QSPIx)
3193 {
3194 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL) >> QSPI_XCTRL_ADDRL_Pos);
3195 }
3196
3197 /**
3198 * @brief Set the transfer format of inst & address for concurrent xip mode
3199 * @note This bit should not be changed when xip is ongoing.
3200 *
3201 * Register|BitsName
3202 * --------|--------
3203 * XIP_CTRL | TRANS_TYPE
3204 *
3205 * @param QSPIx - QSPI instance
3206 * @param format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3207 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3208 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3209 *
3210 * @retval none
3211 */
3212 __STATIC_INLINE void ll_qspi_concurrent_set_xip_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
3213 {
3214 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE, format << QSPI_XCTRL_TRANSTYPE_Pos);
3215 }
3216
3217 /**
3218 * @brief Get the transfer format of inst & address for concurrent xip mode
3219 * @note This bit should not be changed when xip is ongoing.
3220 *
3221 * Register|BitsName
3222 * --------|--------
3223 * XIP_CTRL | TRANS_TYPE
3224 *
3225 * @param QSPIx - QSPI instance
3226 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3227 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3228 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3229 */
3230 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_addr_inst_transfer_format(qspi_regs_t *QSPIx)
3231 {
3232 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE) >> QSPI_XCTRL_TRANSTYPE_Pos);
3233 }
3234
3235 /**
3236 * @brief Set the QSPI frame format for concurrent xip mode
3237 * @note This bit should not be changed when xip is ongoing.
3238 *
3239 * Register|BitsName
3240 * --------|--------
3241 * XIP_CTRL | FRF
3242 *
3243 * @param QSPIx - QSPI instance
3244 * @param format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3245 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3246 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3247 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3248 *
3249 * @retval none
3250 */
3251 __STATIC_INLINE void ll_qspi_concurrent_set_xip_frame_format(qspi_regs_t *QSPIx, uint32_t format)
3252 {
3253 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF, format << QSPI_XCTRL_FRF_Pos);
3254 }
3255
3256 /**
3257 * @brief Get the QSPI frame format for concurrent xip mode
3258 * @note This bit should not be changed when xip is ongoing.
3259 *
3260 * Register|BitsName
3261 * --------|--------
3262 * XIP_CTRL | FRF
3263 *
3264 * @param QSPIx - QSPI instance
3265 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3266 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3267 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3268 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3269 *
3270 */
3271 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_frame_format(qspi_regs_t *QSPIx)
3272 {
3273 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF) >> QSPI_XCTRL_FRF_Pos);
3274 }
3275
3276
3277 /**
3278 * @brief Enable qspi xip mode
3279 * @note This bit should not be changed when communication is ongoing.
3280 *
3281 * Register|BitsName
3282 * --------|--------
3283 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3284 *
3285 * @param QSPIx QSPI instance
3286 *
3287 * @retval None
3288 */
3289 void ll_qspi_enable_xip(qspi_regs_t * QSPIx);
3290
3291 /**
3292 * @brief Disable qspi xip mode
3293 * @note This bit should not be changed when communication is ongoing.
3294 *
3295 * Register|BitsName
3296 * --------|--------
3297 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3298 *
3299 * @param QSPIx QSPI instance
3300 *
3301 * @retval None
3302 */
3303 void ll_qspi_disable_xip(qspi_regs_t * QSPIx);
3304
3305 /**
3306 * @brief Check if qspi xip mode is enabled
3307 * @note This bit should not be changed when communication is ongoing.
3308 *
3309 * Register|BitsName
3310 * --------|--------
3311 * QSPI_M_XIP : M0_XIP_EN | M1_XIP_EN
3312 *
3313 * @param QSPIx QSPI instance
3314 *
3315 * @retval None
3316 */
3317 uint32_t ll_qspi_is_enabled_xip(qspi_regs_t * QSPIx);
3318
3319 /**
3320 * @brief Set xip's endian mode
3321 * @note This bit should not be changed when communication is ongoing.
3322 *
3323 * Register|BitsName
3324 * --------|--------
3325 * QSPI_M_XIP : QSPI_M_XIP_M0_ENDIAN | QSPI_M_XIP_M1_ENDIAN | QSPI_M_XIP_M2_ENDIAN
3326 *
3327 * @param QSPIx QSPI instance
3328 *
3329 * @param mode - This parameter can be one of the following values:
3330 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
3331 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
3332 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
3333 *
3334 * @retval None
3335 */
3336 __STATIC_INLINE void ll_qspi_set_xip_endian_mode(qspi_regs_t * QSPIx, uint32_t mode)
3337 {
3338 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3339
3340 MODIFY_REG(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which), mode << which);
3341 }
3342
3343
3344 /**
3345 * @brief Get xip's endian mode
3346 * @note This bit should not be changed when communication is ongoing.
3347 *
3348 * Register|BitsName
3349 * --------|--------
3350 * QSPI_M_XIP : QSPI_M_XIP_M0_ENDIAN | QSPI_M_XIP_M1_ENDIAN | QSPI_M_XIP_M2_ENDIAN
3351 *
3352 * @param QSPIx QSPI instance
3353 *
3354 * @retval Returned value can be one of the following values:
3355 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
3356 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
3357 * @arg @ref LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
3358 *
3359 */
3360 __STATIC_INLINE uint32_t ll_qspi_get_xip_endian_mode(qspi_regs_t * QSPIx)
3361 {
3362 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3363
3364 return (READ_BITS(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which)) >> which );
3365 }
3366
3367 /************************* Add Following APIs from GR553xx-b0 *************************************/
3368
3369
3370 /**
3371 * @brief Enable dynamic of wait states for QSPI peripheral
3372 *
3373 * Register|BitsName
3374 * --------|--------
3375 * CTRL0 | DWS_EN
3376 *
3377 * @param QSPIx QSPI instance
3378 * @retval None
3379 */
3380 __STATIC_INLINE void ll_qspi_enable_dws(qspi_regs_t *QSPIx)
3381 {
3382 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3383 }
3384
3385 /**
3386 * @brief Disable dynamic of wait states for QSPI peripheral
3387 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
3388 *
3389 * Register|BitsName
3390 * --------|--------
3391 * CTRL0 | DWS_EN
3392 *
3393 * @param QSPIx QSPI instance
3394 * @retval None
3395 */
3396 __STATIC_INLINE void ll_qspi_disable_dws(qspi_regs_t *QSPIx)
3397 {
3398 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3399 }
3400
3401 /**
3402 * @brief Check if dynamic of wait states for QSPI peripheral is enabled
3403 *
3404 * Register|BitsName
3405 * --------|--------
3406 * CTRL0 | DWS_EN
3407 *
3408 * @param QSPIx QSPI instance
3409 * @retval State of bit (1 or 0).
3410 */
3411 __STATIC_INLINE uint32_t ll_qspi_is_enabled_dws(qspi_regs_t *QSPIx)
3412 {
3413 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN) == (QSPI_CTRL0_DWS_EN));
3414 }
3415
3416 /**
3417 * @brief Clear QSPI Transmit Error interrupt
3418 * @note Clearing this flag is done by reading SPITEIC register
3419 *
3420 * Register|BitsName
3421 * --------|--------
3422 * SPI_TEIC | SPI_TEIC
3423 *
3424 * @param QSPIx QSPI instance
3425 * @retval None
3426 */
3427 __STATIC_INLINE void ll_qspi_clear_flag_spite(qspi_regs_t *QSPIx)
3428 {
3429 __IOM uint32_t tmpreg;
3430 tmpreg = QSPIx->SPI_TEIC;
3431 (void) tmpreg;
3432 }
3433
3434 /**
3435 * @brief set the max wait cycles per transaction for dynamic wait state
3436 * @note This bit should not be changed when QSPI is ongoing.
3437 *
3438 * Register|BitsName
3439 * --------|--------
3440 * SPI_CTRL1 | QSPI_SCTRL1_MAX_WS
3441 *
3442 * @param QSPIx - QSPI instance
3443 * @param max_ws - max wait cycles per transaction [0 ~ 15]
3444 * @retval None
3445 */
3446 __STATIC_INLINE void ll_qspi_set_max_wait_cycles(qspi_regs_t *QSPIx, uint32_t max_ws)
3447 {
3448 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS, max_ws << QSPI_SCTRL1_MAX_WS_Pos);
3449 }
3450
3451 /**
3452 * @brief get the max wait cycles per transaction for dynamic wait state
3453 * @note This bit should not be changed when QSPI is ongoing.
3454 *
3455 * Register|BitsName
3456 * --------|--------
3457 * SPI_CTRL1 | QSPI_SCTRL1_MAX_WS
3458 *
3459 * @param QSPIx - QSPI instance
3460 * @retval max wait cycles per transaction [0 ~ 15]
3461 */
3462 __STATIC_INLINE uint32_t ll_qspi_get_max_wait_cycles(qspi_regs_t *QSPIx)
3463 {
3464 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS) >> QSPI_SCTRL1_MAX_WS_Pos);
3465 }
3466
3467 /**
3468 * @brief set the value for dynamic wait state
3469 * @note This bit should not be changed when QSPI is ongoing.
3470 *
3471 * Register|BitsName
3472 * --------|--------
3473 * SPI_CTRL1 | QSPI_SCTRL1_DYN_WS
3474 *
3475 * @param QSPIx - QSPI instance
3476 * @param dyn_ws - dynamic wait state [0 ~ 7]
3477 * @retval None
3478 */
3479 __STATIC_INLINE void ll_qspi_set_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
3480 {
3481 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS, dyn_ws << QSPI_SCTRL1_DYN_WS_Pos);
3482 }
3483
3484 /**
3485 * @brief get the value for dynamic wait state
3486 * @note This bit should not be changed when QSPI is ongoing.
3487 *
3488 * Register|BitsName
3489 * --------|--------
3490 * SPI_CTRL1 | QSPI_SCTRL1_DYN_WS
3491 *
3492 * @param QSPIx - QSPI instance
3493 * @param dyn_ws - dynamic wait state [0 ~ 7]
3494 * @retval dynamic wait state [0 ~ 7]
3495 */
3496 __STATIC_INLINE uint32_t ll_qspi_get_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
3497 {
3498 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS) >> QSPI_SCTRL1_DYN_WS_Pos);
3499 }
3500
3501 /**
3502 * @brief set the ahb-incr transfer instruction for write in xip mode
3503 * @note This bit should not be changed when xip is ongoing.
3504 *
3505 * Register|BitsName
3506 * --------|--------
3507 * XIP_WR_INCR_INST | WR_INCR_INST
3508 *
3509 * @param QSPIx - QSPI instance
3510 * @param inst - instruction op-code, [0 ~ 0xFFFF]
3511 * @retval None
3512 */
3513 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
3514 {
3515 MODIFY_REG(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST, inst << QSPI_XIP_WR_INCR_INST_Pos);
3516 }
3517
3518 /**
3519 * @brief get the ahb-incr transfer instruction for write in xip mode
3520 * @note This bit should not be changed when xip is ongoing.
3521 *
3522 * Register|BitsName
3523 * --------|--------
3524 * XIP_WR_INCR_INST | WR_INCR_INST
3525 *
3526 * @param QSPIx - QSPI instance
3527 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
3528 */
3529 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_incr_inst(qspi_regs_t *QSPIx)
3530 {
3531 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST) >> QSPI_XIP_WR_INCR_INST_Pos);
3532 }
3533
3534 /**
3535 * @brief set the ahb-wrap transfer instruction for write in xip mode
3536 * @note This bit should not be changed when xip is ongoing.
3537 *
3538 * Register|BitsName
3539 * --------|--------
3540 * XIP_WR_WRAP_INST | WR_WRAP_INST
3541 *
3542 * @param QSPIx - QSPI instance
3543 * @param inst - wrap instruction op-code, [0 ~ 0xFFFF]
3544 * @retval None
3545 */
3546 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
3547 {
3548 MODIFY_REG(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST, inst << QSPI_XIP_WR_WRAP_INST_Pos);
3549 }
3550
3551 /**
3552 * @brief get the ahb-wrap transfer instruction for write in xip mode
3553 * @note This bit should not be changed when xip is ongoing.
3554 *
3555 * Register|BitsName
3556 * --------|--------
3557 * XIP_WR_WRAP_INST | WR_WRAP_INST
3558 *
3559 * @param QSPIx - QSPI instance
3560 * @retval inst - instruction op-code, [0 ~ 0xFFFF]
3561 */
3562 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wrap_inst(qspi_regs_t *QSPIx)
3563 {
3564 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST) >> QSPI_XIP_WR_WRAP_INST_Pos);
3565 }
3566
3567
3568 /**
3569 * @brief Set the wait(also called dummy) cycles for concurrent xip write mode
3570 * @note This bit should not be changed when xip is ongoing.
3571 *
3572 * Register|BitsName
3573 * --------|--------
3574 * XIP_WR_CTRL | WAITCYCLES
3575 *
3576 * @param QSPIx - QSPI instance
3577 * @param wait_cycles - 0 ~ 31
3578 * @retval none
3579 */
3580 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
3581 {
3582 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES, wait_cycles << QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3583 }
3584
3585 /**
3586 * @brief Get the wait(also called dummy) cycles for concurrent xip write mode
3587 * @note This bit should not be changed when xip is ongoing.
3588 *
3589 * Register|BitsName
3590 * --------|--------
3591 * XIP_WR_CTRL | WAITCYCLES
3592 *
3593 * @param QSPIx - QSPI instance
3594 * @retval wait_cycles - 0 ~ 31
3595 */
3596 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wait_cycles(qspi_regs_t *QSPIx)
3597 {
3598 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES) >> QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3599 }
3600
3601
3602 /**
3603 * @brief Set the instruction size for concurrent xip write mode
3604 * @note This bit should not be changed when xip is ongoing.
3605 *
3606 * Register|BitsName
3607 * --------|--------
3608 * XIP_WR_CTRL | INSTL
3609 *
3610 * @param QSPIx - QSPI instance
3611 * @param inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3612 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3613 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3614 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3615 * @retval none
3616 */
3617 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
3618 {
3619 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL, inst_size << QSPI_XIP_WR_CTRL_INSTL_Pos);
3620 }
3621
3622 /**
3623 * @brief Get the instruction size for concurrent xip write mode
3624 * @note This bit should not be changed when xip is ongoing.
3625 *
3626 * Register|BitsName
3627 * --------|--------
3628 * XIP_WR_CTRL | INSTL
3629 *
3630 * @param QSPIx - QSPI instance
3631 * @retval inst_size - @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
3632 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
3633 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
3634 * @ref LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
3635 */
3636 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_instruction_size(qspi_regs_t *QSPIx)
3637 {
3638 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL) >> QSPI_XIP_WR_CTRL_INSTL_Pos);
3639 }
3640
3641
3642 /**
3643 * @brief Set the address size for concurrent xip write mode
3644 * @note This bit should not be changed when xip is ongoing.
3645 *
3646 * Register|BitsName
3647 * --------|--------
3648 * XIP_WR_CTRL | ADDRL
3649 *
3650 * @param QSPIx - QSPI instance
3651 * @param addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3652 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3653 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3654 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3655 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3656 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3657 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3658 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3659 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3660 *
3661 * @retval none
3662 */
3663 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
3664 {
3665 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL, addr_size << QSPI_XIP_WR_CTRL_ADDRL_Pos);
3666 }
3667
3668 /**
3669 * @brief Get the address size for concurrent xip write mode
3670 * @note This bit should not be changed when xip is ongoing.
3671 *
3672 * Register|BitsName
3673 * --------|--------
3674 * XIP_WR_CTRL | ADDRL
3675 *
3676 * @param QSPIx - QSPI instance
3677 * @retval addr_size - @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
3678 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
3679 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
3680 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
3681 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
3682 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
3683 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
3684 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
3685 * @ref LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
3686 */
3687 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_address_size(qspi_regs_t *QSPIx)
3688 {
3689 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL) >> QSPI_XIP_WR_CTRL_ADDRL_Pos);
3690 }
3691
3692 /**
3693 * @brief Set the transfer format of inst & address for concurrent xip write mode
3694 * @note This bit should not be changed when xip is ongoing.
3695 *
3696 * Register|BitsName
3697 * --------|--------
3698 * XIP_WR_CTRL | TRANS_TYPE
3699 *
3700 * @param QSPIx - QSPI instance
3701 * @param format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3702 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3703 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3704 *
3705 * @retval none
3706 */
3707 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
3708 {
3709 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE, format << QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3710 }
3711
3712 /**
3713 * @brief Get the transfer format of inst & address for concurrent xip write mode
3714 * @note This bit should not be changed when xip is ongoing.
3715 *
3716 * Register|BitsName
3717 * --------|--------
3718 * XIP_WR_CTRL | TRANS_TYPE
3719 *
3720 * @param QSPIx - QSPI instance
3721 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
3722 * @ref LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
3723 * @ref LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
3724 */
3725 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format(qspi_regs_t *QSPIx)
3726 {
3727 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE) >> QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3728 }
3729
3730 /**
3731 * @brief Set the QSPI frame format for concurrent xip write mode
3732 * @note This bit should not be changed when xip is ongoing.
3733 *
3734 * Register|BitsName
3735 * --------|--------
3736 * XIP_WR_CTRL | FRF
3737 *
3738 * @param QSPIx - QSPI instance
3739 * @param format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3740 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3741 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3742 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3743 *
3744 * @retval none
3745 */
3746 __STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_frame_format(qspi_regs_t *QSPIx, uint32_t format)
3747 {
3748 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF, format << QSPI_XIP_WR_CTRL_FRF_Pos);
3749 }
3750
3751 /**
3752 * @brief Get the QSPI frame format for concurrent xip write mode
3753 * @note This bit should not be changed when xip is ongoing.
3754 *
3755 * Register|BitsName
3756 * --------|--------
3757 * XIP_WR_CTRL | FRF
3758 *
3759 * @param QSPIx - QSPI instance
3760 * @retval format - @ref LL_QSPI_CONCURRENT_XIP_FRF_RSVD
3761 * @ref LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
3762 * @ref LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
3763 * @ref LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
3764 *
3765 */
3766 __STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_frame_format(qspi_regs_t *QSPIx)
3767 {
3768 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF) >> QSPI_XIP_WR_CTRL_FRF_Pos);
3769 }
3770
3771 /**
3772 * @brief Enable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens
3773 * @note Just enable in debug mode, not enable in release code
3774 * Set 0 to get hardfault when generate hresp = 1
3775 * Set 1 to avoid hardfault and always mask the hresp to 0, 1 is default value after System Reset
3776 *
3777 * Register|BitsName
3778 * --------|--------
3779 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3780 *
3781 *
3782 * @retval none
3783 *
3784 */
3785 __STATIC_INLINE void ll_qspi_enable_hresp_err_debug_mode(void)
3786 {
3787 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 0);
3788 }
3789
3790 /**
3791 * @brief Disable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens
3792 * @note Just enable in debug mode, not enable in release code
3793 *
3794 * Register|BitsName
3795 * --------|--------
3796 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3797 *
3798 *
3799 * @retval none
3800 *
3801 */
3802 __STATIC_INLINE void ll_qspi_disable_hresp_err_debug_mode(void)
3803 {
3804 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 1);
3805 }
3806
3807 /**
3808 * @brief Check if the AHB Response Error Debug is enabled for all QSPI Modules.
3809 * @note
3810 *
3811 * Register|BitsName
3812 * --------|--------
3813 * QSPI_M_HRESP_DBG : QSPI_M_HRESP_ERR_MASK
3814 *
3815 *
3816 * @retval none
3817 *
3818 */
3819 __STATIC_INLINE uint32_t ll_qspi_is_hresp_err_debug_mode_enabled(void)
3820 {
3821 return (READ_BITS(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN) == (0));
3822 }
3823
3824 /**
3825 * @brief Set CS Setup Delay for QSPI
3826 * @note This bit should not be changed when communication is ongoing.
3827 *
3828 * Register|BitsName
3829 * --------|--------
3830 * QSPI_M_CS_SETUP_DLY : MCU_SUB_QSPI_M0_CS_SETUP_DLY | MCU_SUB_QSPI_M1_CS_SETUP_DLY | MCU_SUB_QSPI_M2_CS_SETUP_DLY
3831 *
3832 * @param QSPIx QSPI instance
3833 *
3834 * @param delay - the SLCK count to delay
3835 *
3836 * @retval None
3837 */
3838 __STATIC_INLINE void ll_qspi_set_cs_setup_delay(qspi_regs_t * QSPIx, uint32_t delay)
3839 {
3840 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3841 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3842
3843 MODIFY_REG(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which, (baudrate*delay) << which);
3844 }
3845
3846
3847 /**
3848 * @brief Get CS Setup Delay for QSPI
3849 * @note This bit should not be changed when communication is ongoing.
3850 *
3851 * Register|BitsName
3852 * --------|--------
3853 * QSPI_M_CS_SETUP_DLY : MCU_SUB_QSPI_M0_CS_SETUP_DLY | MCU_SUB_QSPI_M1_CS_SETUP_DLY | MCU_SUB_QSPI_M2_CS_SETUP_DLY
3854 *
3855 * @param QSPIx QSPI instance
3856 *
3857 * @retval the SLCK count to delay
3858 */
3859 __STATIC_INLINE uint32_t ll_qspi_get_cs_setup_delay(qspi_regs_t * QSPIx)
3860 {
3861 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3862 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3863
3864 if(0 == baudrate){
3865 return 0;
3866 }
3867
3868 return (READ_BITS(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which) >> which)/baudrate;
3869 }
3870
3871 /**
3872 * @brief Set CS Release Delay for QSPI
3873 * @note This bit should not be changed when communication is ongoing.
3874 *
3875 * Register|BitsName
3876 * --------|--------
3877 * QSPI_M_CS_RELEASE_DLY : MCU_SUB_QSPI_M0_CS_RELEASE_DLY | MCU_SUB_QSPI_M1_CS_RELEASE_DLY | MCU_SUB_QSPI_M2_CS_RELEASE_DLY
3878 *
3879 * @param QSPIx QSPI instance
3880 *
3881 * @param delay - the SLCK count to delay
3882 *
3883 * @retval None
3884 */
3885 __STATIC_INLINE void ll_qspi_set_cs_release_delay(qspi_regs_t * QSPIx, uint32_t delay)
3886 {
3887 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ((QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3888 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3889
3890 MODIFY_REG(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which, (baudrate*delay) << which);
3891 }
3892
3893
3894 /**
3895 * @brief Get CS Release Delay for QSPI
3896 * @note This bit should not be changed when communication is ongoing.
3897 *
3898 * Register|BitsName
3899 * --------|--------
3900 * QSPI_M_CS_RELEASE_DLY : MCU_SUB_QSPI_M0_CS_RELEASE_DLY | MCU_SUB_QSPI_M1_CS_RELEASE_DLY | MCU_SUB_QSPI_M2_CS_RELEASE_DLY
3901 *
3902 * @param QSPIx QSPI instance
3903 *
3904 * @retval the SLCK count to delay
3905 */
3906 __STATIC_INLINE uint32_t ll_qspi_get_cs_release_delay(qspi_regs_t * QSPIx)
3907 {
3908 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3909 uint32_t baudrate = ll_qspi_get_baud_rate_prescaler(QSPIx);
3910
3911 if(0 == baudrate){
3912 return 0;
3913 }
3914
3915 return (READ_BITS(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which) >> which)/baudrate;
3916 }
3917
3918 /**
3919 * @brief Enable qspi xip dynamic little-endian mode
3920 * @note This bit should not be changed when communication is ongoing.
3921 *
3922 * Register|BitsName
3923 * --------|--------
3924 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3925 *
3926 * @param QSPIx QSPI instance
3927 *
3928 * @retval None
3929 */
3930 __STATIC_INLINE void ll_qspi_enable_xip_dynamic_le(qspi_regs_t * QSPIx)
3931 {
3932 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3933 SET_BITS(MCU_SUB->QSPI_M_XIP, which);
3934 }
3935
3936 /**
3937 * @brief Disable qspi xip dynamic little-endian mode
3938 * @note This bit should not be changed when communication is ongoing.
3939 *
3940 * Register|BitsName
3941 * --------|--------
3942 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3943 *
3944 * @param QSPIx QSPI instance
3945 *
3946 * @retval None
3947 */
3948 __STATIC_INLINE void ll_qspi_disable_xip_dynamic_le(qspi_regs_t * QSPIx)
3949 {
3950 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3951 CLEAR_BITS(MCU_SUB->QSPI_M_XIP, which);
3952 }
3953
3954 /**
3955 * @brief Check if qspi xip dynamic little-endian mode is enabled
3956 * @note This bit should not be changed when communication is ongoing.
3957 *
3958 * Register|BitsName
3959 * --------|--------
3960 * QSPI_M_XIP : MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN | MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN
3961 *
3962 * @param QSPIx QSPI instance
3963 *
3964 * @retval None
3965 */
3966 __STATIC_INLINE uint32_t ll_qspi_is_enabled_xip_dynamic_le(qspi_regs_t * QSPIx)
3967 {
3968 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3969 return (READ_BITS(MCU_SUB->QSPI_M_XIP, which) == (which));
3970 }
3971
3972 /**
3973 * @brief Get Receive FIFO Depth Of Register Mode
3974 * @note
3975 * @param QSPIx QSPI instance
3976 * @retval Receive FIFO Depth corresponded to QSPI instance
3977 */
3978 __STATIC_INLINE uint32_t ll_qspi_get_reg_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
3979 {
3980 if(QSPI0 == QSPIx) {
3981 return LL_QSPI0_REG_RX_FIFO_DEPTH;
3982 } else if(QSPI1 == QSPIx) {
3983 return LL_QSPI1_REG_RX_FIFO_DEPTH;
3984 } else {
3985 return LL_QSPI2_REG_RX_FIFO_DEPTH;
3986 }
3987 }
3988
3989 /**
3990 * @brief Get Transmit FIFO Depth Of Register Mode
3991 * @note
3992 * @param QSPIx QSPI instance
3993 * @retval Transmit FIFO Depth corresponded to QSPI instance
3994 */
3995 __STATIC_INLINE uint32_t ll_qspi_get_reg_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
3996 {
3997 if(QSPI0 == QSPIx) {
3998 return LL_QSPI0_REG_TX_FIFO_DEPTH;
3999 } else if(QSPI1 == QSPIx) {
4000 return LL_QSPI1_REG_TX_FIFO_DEPTH;
4001 } else {
4002 return LL_QSPI2_REG_TX_FIFO_DEPTH;
4003 }
4004 }
4005
4006 /**
4007 * @brief Get Receive FIFO Depth Of XIP Mode
4008 * @note
4009 * @param QSPIx QSPI instance
4010 * @retval Receive FIFO Depth corresponded to QSPI instance
4011 */
4012 __STATIC_INLINE uint32_t ll_qspi_get_xip_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
4013 {
4014 if(QSPI0 == QSPIx) {
4015 return LL_QSPI0_XIP_RX_FIFO_DEPTH;
4016 } else if(QSPI1 == QSPIx) {
4017 return LL_QSPI1_XIP_RX_FIFO_DEPTH;
4018 } else {
4019 return LL_QSPI2_XIP_RX_FIFO_DEPTH;
4020 }
4021 }
4022
4023 /**
4024 * @brief Get Transmit FIFO Depth Of XIP Mode
4025 * @note
4026 * @param QSPIx QSPI instance
4027 * @retval Transmit FIFO Depth corresponded to QSPI instance
4028 */
4029 __STATIC_INLINE uint32_t ll_qspi_get_xip_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
4030 {
4031 if(QSPI0 == QSPIx) {
4032 return LL_QSPI0_XIP_TX_FIFO_DEPTH;
4033 } else if(QSPI1 == QSPIx) {
4034 return LL_QSPI1_XIP_TX_FIFO_DEPTH;
4035 } else {
4036 return LL_QSPI2_XIP_TX_FIFO_DEPTH;
4037 }
4038 }
4039
4040 /**
4041 * @brief Get Transmit FIFO Depth Of XIP Mode
4042 * @note
4043 * @param QSPIx QSPI instance
4044 * @retval Transmit FIFO Depth corresponded to QSPI instance
4045 */
4046 __STATIC_INLINE uint32_t ll_qspi_get_xip_base_address(qspi_regs_t *QSPIx)
4047 {
4048 if(QSPI0 == QSPIx) {
4049 return QSPI0_XIP_BASE;
4050 } else if(QSPI1 == QSPIx) {
4051 return QSPI1_XIP_BASE;
4052 } else {
4053 return QSPI2_XIP_BASE;
4054 }
4055 }
4056 /** @} */
4057 /** @defgroup QSPI_LL_Init QSPI Initialization and de-initialization functions
4058 * @{
4059 */
4060
4061 /**
4062 * @brief De-initialize SSI registers (Registers restored to their default values).
4063 * @param QSPIx SSI instance
4064 * @retval An error_status_t enumeration value:
4065 * - SUCCESS: SSI registers are de-initialized
4066 * - ERROR: SSI registers are not de-initialized
4067 */
4068 error_status_t ll_qspi_deinit(qspi_regs_t *QSPIx);
4069
4070 /**
4071 * @brief Initialize SSI registers according to the specified
4072 * parameters in SPI_InitStruct.
4073 * @param QSPIx SSI instance
4074 * @param p_spi_init Pointer to a ll_qspi_init_t structure that contains the configuration
4075 * information for the specified QSPI peripheral.
4076 * @retval An error_status_t enumeration value:
4077 * - SUCCESS: SPI registers are initialized according to p_spi_init content
4078 * - ERROR: Problem occurred during SPI Registers initialization
4079 */
4080 error_status_t ll_qspi_init(qspi_regs_t *QSPIx, ll_qspi_init_t *p_spi_init);
4081
4082 /**
4083 * @brief Configure the qspi to memorymapped.
4084 * @param QSPIx QSPI instance
4085 * @param p_qspi_mmap_init pointer to a @ref ll_qspi_memorymapped_init_t structure
4086 * @retval An ErrorStatus enumeration value:
4087 * - SUCCESS: spi registers are de-initialized
4088 * - ERROR: not applicable
4089 */
4090 error_status_t ll_qspi_memorymapped(qspi_regs_t *QSPIx, ll_qspi_memorymapped_init_t * p_qspi_mmap_init);
4091
4092
4093 /**
4094 * @brief Set each field of a @ref ll_qspi_init_t type structure to default value.
4095 * @param p_spi_init Pointer to a @ref ll_qspi_init_t structure
4096 * whose fields will be set to default values.
4097 * @retval None
4098 */
4099 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
4100
4101 /** @} */
4102
4103 /** @} */
4104
4105 #endif /* QSPI0 || QSPI1 || QSPI2 */
4106
4107 #ifdef __cplusplus
4108 }
4109 #endif
4110
4111 #endif /* __GR55xx_LL_SPI_H__ */
4112
4113 /** @} */
4114
4115 /** @} */
4116
4117 /** @} */
LL_QSPI0_XIP_RX_FIFO_DEPTH
#define LL_QSPI0_XIP_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:287
ll_qspi_clear_flag_rxu
__STATIC_INLINE void ll_qspi_clear_flag_rxu(qspi_regs_t *QSPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_qspi.h:1986
ll_qspi_transmit_data32
__STATIC_INLINE void ll_qspi_transmit_data32(qspi_regs_t *QSPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2254
ll_qspi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_dma_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_qspi.h:2185
ll_qspi_get_frame_format
__STATIC_INLINE uint32_t ll_qspi_get_frame_format(qspi_regs_t *QSPIx)
Get data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_qspi.h:875
ll_qspi_enable_ss_toggle
__STATIC_INLINE void ll_qspi_enable_ss_toggle(qspi_regs_t *QSPIx)
Enable slave select toggle.
Definition: gr55xx_ll_qspi.h:804
ll_qspi_concurrent_get_xip_wr_frame_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3766
ll_qspi_get_transfer_direction
__STATIC_INLINE uint32_t ll_qspi_get_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode.
Definition: gr55xx_ll_qspi.h:1158
ll_qspi_receive_data32
__STATIC_INLINE uint32_t ll_qspi_receive_data32(qspi_regs_t *QSPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2299
LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE
@ LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE
Definition: gr55xx_ll_qspi.h:130
ll_qspi_set_address_size
__STATIC_INLINE void ll_qspi_set_address_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_qspi.h:2520
ll_qspi_concurrent_disable_xip_ss
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable the slave in xip mode.
Definition: gr55xx_ll_qspi.h:2813
ll_qspi_concurrent_get_xip_wr_instruction_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3636
ll_qspi_get_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_get_wait_cycles(qspi_regs_t *QSPIx)
Get number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_qspi.h:2446
ll_qspi_disable_hresp_err_debug_mode
__STATIC_INLINE void ll_qspi_disable_hresp_err_debug_mode(void)
Disable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens.
Definition: gr55xx_ll_qspi.h:3802
ll_qspi_concurrent_is_enabled_xip_dfs_hardcode
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Check if the hardcoded DFS feature is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3095
LL_QSPI1_XIP_TX_FIFO_DEPTH
#define LL_QSPI1_XIP_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:293
ll_qspi_get_reg_mode_tx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of Register Mode.
Definition: gr55xx_ll_qspi.h:3995
ll_qspi_concurrent_get_xip_wrap_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2779
_ll_qspi_init_t::instruction_size
uint32_t instruction_size
Definition: gr55xx_ll_qspi.h:83
ll_qspi_set_rx_sample_edge
__STATIC_INLINE void ll_qspi_set_rx_sample_edge(qspi_regs_t *QSPIx, uint32_t edge)
Set the RX sample edge.
Definition: gr55xx_ll_qspi.h:2316
ll_qspi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_delay(qspi_regs_t *QSPIx)
Get Rx sample delay.
Definition: gr55xx_ll_qspi.h:2365
ll_qspi_set_tx_start_fifo_threshold
__STATIC_INLINE void ll_qspi_set_tx_start_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TX transfer start.
Definition: gr55xx_ll_qspi.h:1579
ll_qspi_concurrent_set_xip_mode_bits_data
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_data(qspi_regs_t *QSPIx, uint32_t mode)
set the mode phase (sent after address phase) value in xip mode
Definition: gr55xx_ll_qspi.h:2697
LL_QSPI0_REG_RX_FIFO_DEPTH
#define LL_QSPI0_REG_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:285
ll_qspi_concurrent_set_xip_inst_addr_transfer_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3212
ll_qspi_concurrent_set_xip_frame_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3251
ll_qspi_enable_hresp_err_debug_mode
__STATIC_INLINE void ll_qspi_enable_hresp_err_debug_mode(void)
Enable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens.
Definition: gr55xx_ll_qspi.h:3785
ll_qspi_clear_flag_rxo
__STATIC_INLINE void ll_qspi_clear_flag_rxo(qspi_regs_t *QSPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_qspi.h:1968
ll_qspi_get_max_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_get_max_wait_cycles(qspi_regs_t *QSPIx)
get the max wait cycles per transaction for dynamic wait state
Definition: gr55xx_ll_qspi.h:3462
ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3725
LL_QSPI2_REG_RX_FIFO_DEPTH
#define LL_QSPI2_REG_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:295
_ll_qspi_init_t::address_size
uint32_t address_size
Definition: gr55xx_ll_qspi.h:88
ll_qspi_is_enabled_dws
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dws(qspi_regs_t *QSPIx)
Check if dynamic of wait states for QSPI peripheral is enabled.
Definition: gr55xx_ll_qspi.h:3411
ll_qspi_concurrent_enable_xip_continuous_xfer
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Enable the continuous transfer feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2927
_ll_qspi_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_qspi.h:108
ll_qspi_memorymapped
error_status_t ll_qspi_memorymapped(qspi_regs_t *QSPIx, ll_qspi_memorymapped_init_t *p_qspi_mmap_init)
Configure the qspi to memorymapped.
_ll_qspi_init_t::inst_addr_transfer_format
uint32_t inst_addr_transfer_format
Definition: gr55xx_ll_qspi.h:93
ll_qspi_concurrent_get_xip_address_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3192
ll_qspi_concurrent_get_xip_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3128
ll_qspi_enable_xip
void ll_qspi_enable_xip(qspi_regs_t *QSPIx)
Enable qspi xip mode.
ll_qspi_set_cs_setup_delay
__STATIC_INLINE void ll_qspi_set_cs_setup_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Setup Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3838
ll_qspi_concurrent_get_xip_instruction_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3046
_ll_qspi_memorymapped_write_init_t::x_wr_dummy_cycles
uint32_t x_wr_dummy_cycles
Definition: gr55xx_ll_qspi.h:226
_ll_qspi_memorymapped_read_init_t::x_endian_mode
uint32_t x_endian_mode
Definition: gr55xx_ll_qspi.h:199
ll_qspi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_qspi_is_enabled_test_mode(qspi_regs_t *QSPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_qspi.h:1074
ll_qspi_set_add_inst_transfer_format
__STATIC_INLINE void ll_qspi_set_add_inst_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_qspi.h:2572
ll_qspi_concurrent_set_xip_wr_frame_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3746
ll_qspi_get_standard
__STATIC_INLINE uint32_t ll_qspi_get_standard(qspi_regs_t *QSPIx)
Get serial protocol used.
Definition: gr55xx_ll_qspi.h:1270
ll_qspi_enable_micro_handshake
__STATIC_INLINE void ll_qspi_enable_micro_handshake(qspi_regs_t *QSPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_qspi.h:1370
ll_qspi_set_micro_transfer_direction
__STATIC_INLINE void ll_qspi_set_micro_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1419
_ll_qspi_memorymapped_read_init_t::x_prefetch_en
uint32_t x_prefetch_en
Definition: gr55xx_ll_qspi.h:185
ll_qspi_concurrent_set_xip_instruction_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3027
ll_qspi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_qspi.h:1671
ll_qspi_is_enabled_ss
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_qspi.h:1531
ll_qspi_get_control_frame_size
__STATIC_INLINE uint32_t ll_qspi_get_control_frame_size(qspi_regs_t *QSPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_qspi.h:1029
ll_qspi_disable_dma_req_rx
__STATIC_INLINE void ll_qspi_disable_dma_req_rx(qspi_regs_t *QSPIx)
Disable DMA Rx.
Definition: gr55xx_ll_qspi.h:2123
ll_qspi_set_dynamic_wait_state
__STATIC_INLINE void ll_qspi_set_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
set the value for dynamic wait state
Definition: gr55xx_ll_qspi.h:3479
ll_qspi_concurrent_get_xip_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3230
ll_qspi_disable_xip
void ll_qspi_disable_xip(qspi_regs_t *QSPIx)
Disable qspi xip mode.
ll_qspi_get_xip_mode_tx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4029
_ll_qspi_memorymapped_read_init_t::x_dfs
uint32_t x_dfs
Definition: gr55xx_ll_qspi.h:139
ll_qspi_memorymapped_write_init_t
struct _ll_qspi_memorymapped_write_init_t ll_qspi_memorymapped_write_init_t
_ll_qspi_memorymapped_write_init_t::x_wr_address_size
uint32_t x_wr_address_size
Definition: gr55xx_ll_qspi.h:218
ll_qspi_set_control_frame_size
__STATIC_INLINE void ll_qspi_set_control_frame_size(qspi_regs_t *QSPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_qspi.h:997
ll_qspi_enable_dws
__STATIC_INLINE void ll_qspi_enable_dws(qspi_regs_t *QSPIx)
Enable dynamic of wait states for QSPI peripheral.
Definition: gr55xx_ll_qspi.h:3380
_ll_qspi_memorymapped_read_init_t::x_instruction
uint32_t x_instruction
Definition: gr55xx_ll_qspi.h:156
ll_qspi_concurrent_is_enabled_xip_continuous_xfer
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_continuous_xfer(qspi_regs_t *QSPIx)
Check if the continuous transfer feature is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2959
_ll_qspi_memorymapped_write_init_t
Definition: gr55xx_ll_qspi.h:207
ll_qspi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss_toggle(qspi_regs_t *QSPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_qspi.h:836
ll_qspi_get_status
__STATIC_INLINE uint32_t ll_qspi_get_status(qspi_regs_t *QSPIx)
Get SPI status.
Definition: gr55xx_ll_qspi.h:1827
_ll_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_ll_qspi.h:123
ll_qspi_set_wait_cycles
__STATIC_INLINE void ll_qspi_set_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_qspi.h:2430
ll_qspi_get_receive_size
__STATIC_INLINE uint32_t ll_qspi_get_receive_size(qspi_regs_t *QSPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_qspi.h:1309
ll_qspi_concurrent_disable_xip_instruction
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_instruction(qspi_regs_t *QSPIx)
Disable the instruction phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2991
ll_qspi_concurrent_set_xip_wr_wait_cycles
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3580
ll_qspi_get_reg_mode_rx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of Register Mode.
Definition: gr55xx_ll_qspi.h:3978
ll_qspi_disable_xip_dynamic_le
__STATIC_INLINE void ll_qspi_disable_xip_dynamic_le(qspi_regs_t *QSPIx)
Disable qspi xip dynamic little-endian mode.
Definition: gr55xx_ll_qspi.h:3948
_ll_qspi_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_qspi.h:112
_ll_qspi_memorymapped_read_init_t::x_dfs_hardcode_en
uint32_t x_dfs_hardcode_en
Definition: gr55xx_ll_qspi.h:142
ll_qspi_concurrent_set_xip_wr_incr_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3513
ll_qspi_get_cs_release_delay
__STATIC_INLINE uint32_t ll_qspi_get_cs_release_delay(qspi_regs_t *QSPIx)
Get CS Release Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3906
ll_qspi_is_enabled_clk_stretch
__STATIC_INLINE uint32_t ll_qspi_is_enabled_clk_stretch(qspi_regs_t *QSPIx)
Check if the clock stretch feature is enabled or not for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2413
ll_qspi_disable_dma_req_tx
__STATIC_INLINE void ll_qspi_disable_dma_req_tx(qspi_regs_t *QSPIx)
Disable DMA Tx.
Definition: gr55xx_ll_qspi.h:2078
ll_qspi_enable_it
__STATIC_INLINE void ll_qspi_enable_it(qspi_regs_t *QSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_qspi.h:1748
ll_qspi_concurrent_is_enabled_xip_instruction
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_instruction(qspi_regs_t *QSPIx)
Check if the instruction phase is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3007
ll_qspi_get_xip_base_address
__STATIC_INLINE uint32_t ll_qspi_get_xip_base_address(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4046
_ll_qspi_memorymapped_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_qspi.h:250
ll_qspi_is_enabled_it
__STATIC_INLINE uint32_t ll_qspi_is_enabled_it(qspi_regs_t *QSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_qspi.h:1799
_ll_qspi_init_t
QSPI init structures definition.
Definition: gr55xx_ll_qspi.h:77
LL_QSPI1_REG_RX_FIFO_DEPTH
#define LL_QSPI1_REG_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:290
ll_qspi_set_tx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_qspi.h:1610
ll_qspi_set_transfer_direction
__STATIC_INLINE void ll_qspi_set_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_qspi.h:1139
ll_qspi_disable_micro_handshake
__STATIC_INLINE void ll_qspi_disable_micro_handshake(qspi_regs_t *QSPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_qspi.h:1385
ll_qspi_clear_flag_xrxo
__STATIC_INLINE void ll_qspi_clear_flag_xrxo(qspi_regs_t *QSPIx)
Clear XIP receive FIFO overflow flag.
Definition: gr55xx_ll_qspi.h:2022
ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3707
ll_qspi_set_cs_release_delay
__STATIC_INLINE void ll_qspi_set_cs_release_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Release Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3885
ll_qspi_enable_dma_req_tx
__STATIC_INLINE void ll_qspi_enable_dma_req_tx(qspi_regs_t *QSPIx)
Enable DMA Tx.
Definition: gr55xx_ll_qspi.h:2063
ll_qspi_get_instruction_size
__STATIC_INLINE uint32_t ll_qspi_get_instruction_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_qspi.h:2487
ll_qspi_set_rx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_qspi.h:1641
ll_qspi_concurrent_set_xip_mode_bits_length
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_length(qspi_regs_t *QSPIx, uint32_t mbl)
Set the length of mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2661
ll_qspi_concurrent_set_xip_wrap_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2763
ll_qspi_disable_ss_toggle
__STATIC_INLINE void ll_qspi_disable_ss_toggle(qspi_regs_t *QSPIx)
Disable slave select toggle.
Definition: gr55xx_ll_qspi.h:820
ll_qspi_concurrent_get_xip_mode_bits_data
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_data(qspi_regs_t *QSPIx)
get the mode phase (sent after address phase) value in xip mode
Definition: gr55xx_ll_qspi.h:2713
ll_qspi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_qspi.h:1656
ll_qspi_get_id_code
__STATIC_INLINE uint32_t ll_qspi_get_id_code(qspi_regs_t *QSPIx)
Get ID code.
Definition: gr55xx_ll_qspi.h:1701
_ll_qspi_memorymapped_write_init_t::x_wr_data_frame_format
uint32_t x_wr_data_frame_format
Definition: gr55xx_ll_qspi.h:230
ll_qspi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1437
ll_qspi_get_xip_mode_rx_fifo_depth
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of XIP Mode.
Definition: gr55xx_ll_qspi.h:4012
ll_qspi_is_enabled_xip_dynamic_le
__STATIC_INLINE uint32_t ll_qspi_is_enabled_xip_dynamic_le(qspi_regs_t *QSPIx)
Check if qspi xip dynamic little-endian mode is enabled.
Definition: gr55xx_ll_qspi.h:3966
_ll_qspi_memorymapped_read_init_t::x_data_frame_format
uint32_t x_data_frame_format
Definition: gr55xx_ll_qspi.h:181
LL_QSPI2_REG_TX_FIFO_DEPTH
#define LL_QSPI2_REG_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:296
ll_qspi_enable_slave_out
__STATIC_INLINE void ll_qspi_enable_slave_out(qspi_regs_t *QSPIx)
Enable slave output.
Definition: gr55xx_ll_qspi.h:1089
ll_qspi_set_frame_format
__STATIC_INLINE void ll_qspi_set_frame_format(qspi_regs_t *QSPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_qspi.h:856
_ll_qspi_memorymapped_read_init_t
Definition: gr55xx_ll_qspi.h:134
ll_qspi_get_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_qspi_get_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_qspi.h:2591
ll_qspi_disable_it
__STATIC_INLINE void ll_qspi_disable_it(qspi_regs_t *QSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_qspi.h:1774
ll_qspi_concurrent_enable_xip_dfs_hardcode
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Enable the hardcoded DFS feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3063
ll_qspi_concurrent_enable_xip_instruction
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_instruction(qspi_regs_t *QSPIx)
Enable the instruction phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2975
ll_qspi_get_cs_setup_delay
__STATIC_INLINE uint32_t ll_qspi_get_cs_setup_delay(qspi_regs_t *QSPIx)
Get CS Setup Delay for QSPI.
Definition: gr55xx_ll_qspi.h:3859
ll_qspi_set_data_size
__STATIC_INLINE void ll_qspi_set_data_size(qspi_regs_t *QSPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_qspi.h:920
_ll_qspi_memorymapped_read_init_t::x_mode_bits_data
uint32_t x_mode_bits_data
Definition: gr55xx_ll_qspi.h:175
ll_qspi_disable
__STATIC_INLINE void ll_qspi_disable(qspi_regs_t *QSPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_qspi.h:1340
_ll_qspi_memorymapped_init_t
Definition: gr55xx_ll_qspi.h:237
ll_qspi_concurrent_enable_xip_mode_bits
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_mode_bits(qspi_regs_t *QSPIx)
Enable the mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2609
ll_qspi_is_hresp_err_debug_mode_enabled
__STATIC_INLINE uint32_t ll_qspi_is_hresp_err_debug_mode_enabled(void)
Check if the AHB Response Error Debug is enabled for all QSPI Modules.
Definition: gr55xx_ll_qspi.h:3819
_ll_qspi_memorymapped_read_init_t::x_continous_xfer_toc
uint32_t x_continous_xfer_toc
Definition: gr55xx_ll_qspi.h:195
ll_qspi_transmit_data16
__STATIC_INLINE void ll_qspi_transmit_data16(qspi_regs_t *QSPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2238
ll_qspi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_qspi_set_dma_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_qspi.h:2154
ll_qspi_concurrent_set_xip_wait_cycles
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3112
ll_qspi_get_it_flag
__STATIC_INLINE uint32_t ll_qspi_get_it_flag(qspi_regs_t *QSPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_qspi.h:1880
_ll_qspi_memorymapped_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_ll_qspi.h:255
ll_qspi_is_it_flag
__STATIC_INLINE uint32_t ll_qspi_is_it_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_qspi.h:1910
_ll_qspi_memorymapped_write_init_t::x_wr_instruction_size
uint32_t x_wr_instruction_size
Definition: gr55xx_ll_qspi.h:212
ll_qspi_clear_flag_all
__STATIC_INLINE void ll_qspi_clear_flag_all(qspi_regs_t *QSPIx)
Clear all error(txo,rxu,rxo,mst) flag.
Definition: gr55xx_ll_qspi.h:2040
_ll_qspi_memorymapped_read_init_t::x_address_size
uint32_t x_address_size
Definition: gr55xx_ll_qspi.h:158
LL_QSPI0_XIP_TX_FIFO_DEPTH
#define LL_QSPI0_XIP_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:288
_ll_qspi_memorymapped_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_qspi.h:242
ll_qspi_disable_salve_out
__STATIC_INLINE void ll_qspi_disable_salve_out(qspi_regs_t *QSPIx)
Disable slave output.
Definition: gr55xx_ll_qspi.h:1104
ll_qspi_receive_data8
__STATIC_INLINE uint8_t ll_qspi_receive_data8(qspi_regs_t *QSPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2269
ll_qspi_enable_test_mode
__STATIC_INLINE void ll_qspi_enable_test_mode(qspi_regs_t *QSPIx)
Enable SPI test mode.
Definition: gr55xx_ll_qspi.h:1044
ll_qspi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_dma_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_qspi.h:2200
ll_qspi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_qspi.h:1625
ll_qspi_enable_xip_dynamic_le
__STATIC_INLINE void ll_qspi_enable_xip_dynamic_le(qspi_regs_t *QSPIx)
Enable qspi xip dynamic little-endian mode.
Definition: gr55xx_ll_qspi.h:3930
ll_qspi_memorymapped_read_init_t
struct _ll_qspi_memorymapped_read_init_t ll_qspi_memorymapped_read_init_t
ll_qspi_disable_clk_stretch
__STATIC_INLINE void ll_qspi_disable_clk_stretch(qspi_regs_t *QSPIx)
Disable the clock stretch feature for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2397
ll_qspi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_qspi.h:1686
ll_qspi_concurrent_disable_xip_dfs_hardcode
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Disable the hardcoded DFS feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3079
ll_qspi_concurrent_get_xip_frame_format
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3271
ll_qspi_concurrent_disable_xip_continuous_xfer
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Disable the continuous transfer feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2943
ll_qspi_concurrent_set_xip_wr_instruction_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3617
ll_qspi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_qspi_is_enabled_slave_out(qspi_regs_t *QSPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_qspi.h:1119
_ll_qspi_memorymapped_read_init_t::x_instruction_size
uint32_t x_instruction_size
Definition: gr55xx_ll_qspi.h:152
ll_qspi_memorymapped_mode_e
ll_qspi_memorymapped_mode_e
Definition: gr55xx_ll_qspi.h:128
ll_qspi_get_rx_sample_edge
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_edge(qspi_regs_t *QSPIx)
Get the RX sample edge.
Definition: gr55xx_ll_qspi.h:2332
ll_qspi_concurrent_is_enabled_xip_prefetch
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_prefetch(qspi_regs_t *QSPIx)
check if the pre-fetch feature is enabled or not for concurrent xip mode
Definition: gr55xx_ll_qspi.h:2911
ll_qspi_enable
__STATIC_INLINE void ll_qspi_enable(qspi_regs_t *QSPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_qspi.h:1324
ll_qspi_transmit_data8
__STATIC_INLINE void ll_qspi_transmit_data8(qspi_regs_t *QSPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2222
ll_qspi_get_data_size
__STATIC_INLINE uint32_t ll_qspi_get_data_size(qspi_regs_t *QSPIx)
Get frame data size.
Definition: gr55xx_ll_qspi.h:964
ll_qspi_get_clock_phase
__STATIC_INLINE uint32_t ll_qspi_get_clock_phase(qspi_regs_t *QSPIx)
Get clock phase.
Definition: gr55xx_ll_qspi.h:1232
ll_qspi_init_t
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
ll_qspi_concurrent_enable_xip_ss
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable the slave in xip mode.
Definition: gr55xx_ll_qspi.h:2796
ll_qspi_get_address_size
__STATIC_INLINE uint32_t ll_qspi_get_address_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_qspi.h:2552
ll_qspi_concurrent_disable_xip_prefetch
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_prefetch(qspi_regs_t *QSPIx)
Disable the pre-fetch feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2895
_ll_qspi_memorymapped_read_init_t::x_dummy_cycles
uint32_t x_dummy_cycles
Definition: gr55xx_ll_qspi.h:177
ll_qspi_concurrent_disable_xip_mode_bits
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_mode_bits(qspi_regs_t *QSPIx)
Disable the mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2625
_ll_qspi_memorymapped_init_t::wr
ll_qspi_memorymapped_write_init_t wr
Definition: gr55xx_ll_qspi.h:262
ll_qspi_receive_data16
__STATIC_INLINE uint16_t ll_qspi_receive_data16(qspi_regs_t *QSPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_qspi.h:2284
ll_qspi_get_xip_endian_mode
__STATIC_INLINE uint32_t ll_qspi_get_xip_endian_mode(qspi_regs_t *QSPIx)
Get xip's endian mode.
Definition: gr55xx_ll_qspi.h:3360
_ll_qspi_init_t::transfer_direction
uint32_t transfer_direction
Definition: gr55xx_ll_qspi.h:78
ll_qspi_set_receive_size
__STATIC_INLINE void ll_qspi_set_receive_size(qspi_regs_t *QSPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_qspi.h:1289
ll_qspi_set_rx_sample_delay
__STATIC_INLINE void ll_qspi_set_rx_sample_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_qspi.h:2349
_ll_qspi_memorymapped_read_init_t::x_mode_bits_length
uint32_t x_mode_bits_length
Definition: gr55xx_ll_qspi.h:171
_ll_qspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_qspi.h:117
ll_qspi_concurrent_get_xip_wr_address_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3687
ll_qspi_concurrent_get_xip_toc
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_toc(qspi_regs_t *QSPIx)
Get time out count for continuous transfer for xip mode.
Definition: gr55xx_ll_qspi.h:2863
ll_qspi_set_xip_endian_mode
__STATIC_INLINE void ll_qspi_set_xip_endian_mode(qspi_regs_t *QSPIx, uint32_t mode)
Set xip's endian mode.
Definition: gr55xx_ll_qspi.h:3336
ll_qspi_concurrent_set_xip_toc
__STATIC_INLINE void ll_qspi_concurrent_set_xip_toc(qspi_regs_t *QSPIx, uint32_t xtoc)
Set time out count for continuous transfer for xip mode.
Definition: gr55xx_ll_qspi.h:2847
ll_qspi_concurrent_set_xip_address_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:3161
ll_qspi_is_active_flag
__STATIC_INLINE uint32_t ll_qspi_is_active_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_qspi.h:1856
ll_qspi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_rx(qspi_regs_t *QSPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_qspi.h:2138
ll_qspi_get_version
__STATIC_INLINE uint32_t ll_qspi_get_version(qspi_regs_t *QSPIx)
Get IP version.
Definition: gr55xx_ll_qspi.h:1716
_ll_qspi_memorymapped_read_init_t::x_instruction_en
uint32_t x_instruction_en
Definition: gr55xx_ll_qspi.h:147
ll_qspi_disable_dws
__STATIC_INLINE void ll_qspi_disable_dws(qspi_regs_t *QSPIx)
Disable dynamic of wait states for QSPI peripheral.
Definition: gr55xx_ll_qspi.h:3396
LL_QSPI2_XIP_TX_FIFO_DEPTH
#define LL_QSPI2_XIP_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:298
ll_qspi_enable_ss
__STATIC_INLINE void ll_qspi_enable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_qspi.h:1493
_ll_qspi_memorymapped_write_init_t::x_wr_inst_addr_transfer_format
uint32_t x_wr_inst_addr_transfer_format
Definition: gr55xx_ll_qspi.h:222
_ll_qspi_memorymapped_read_init_t::x_mode_bits_en
uint32_t x_mode_bits_en
Definition: gr55xx_ll_qspi.h:166
ll_qspi_clear_flag_txo
__STATIC_INLINE void ll_qspi_clear_flag_txo(qspi_regs_t *QSPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_qspi.h:1950
ll_qspi_set_clock_phase
__STATIC_INLINE void ll_qspi_set_clock_phase(qspi_regs_t *QSPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_qspi.h:1215
ll_qspi_concurrent_is_enabled_xip_ss
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if the slave is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2830
ll_qspi_set_max_wait_cycles
__STATIC_INLINE void ll_qspi_set_max_wait_cycles(qspi_regs_t *QSPIx, uint32_t max_ws)
set the max wait cycles per transaction for dynamic wait state
Definition: gr55xx_ll_qspi.h:3446
ll_qspi_enable_clk_stretch
__STATIC_INLINE void ll_qspi_enable_clk_stretch(qspi_regs_t *QSPIx)
Enable the clock stretch feature for Enhanced SPI.
Definition: gr55xx_ll_qspi.h:2381
ll_qspi_concurrent_is_enabled_xip_mode_bits
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_mode_bits(qspi_regs_t *QSPIx)
Check if the mode bits phase is enabled or not for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2641
LL_QSPI1_REG_TX_FIFO_DEPTH
#define LL_QSPI1_REG_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:291
_ll_qspi_memorymapped_read_init_t::x_continous_xfer_en
uint32_t x_continous_xfer_en
Definition: gr55xx_ll_qspi.h:190
_ll_qspi_memorymapped_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_qspi.h:246
LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY
@ LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY
Definition: gr55xx_ll_qspi.h:129
_ll_qspi_init_t::wait_cycles
uint32_t wait_cycles
Definition: gr55xx_ll_qspi.h:98
ll_qspi_disable_test_mode
__STATIC_INLINE void ll_qspi_disable_test_mode(qspi_regs_t *QSPIx)
Disable SPI test mode.
Definition: gr55xx_ll_qspi.h:1059
ll_qspi_enable_dma_req_rx
__STATIC_INLINE void ll_qspi_enable_dma_req_rx(qspi_regs_t *QSPIx)
Enable DMA Rx.
Definition: gr55xx_ll_qspi.h:2108
ll_qspi_struct_init
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
_ll_qspi_memorymapped_read_init_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Definition: gr55xx_ll_qspi.h:162
ll_qspi_get_tx_start_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_tx_start_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TX transfer start.
Definition: gr55xx_ll_qspi.h:1594
ll_qspi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_tx(qspi_regs_t *QSPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_qspi.h:2093
ll_qspi_concurrent_get_xip_wr_incr_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3529
ll_qspi_get_clock_polarity
__STATIC_INLINE uint32_t ll_qspi_get_clock_polarity(qspi_regs_t *QSPIx)
Get clock polarity.
Definition: gr55xx_ll_qspi.h:1195
_ll_qspi_memorymapped_init_t::rw_mode
ll_qspi_memorymapped_mode_e rw_mode
Definition: gr55xx_ll_qspi.h:258
ll_qspi_clear_flag_spite
__STATIC_INLINE void ll_qspi_clear_flag_spite(qspi_regs_t *QSPIx)
Clear QSPI Transmit Error interrupt.
Definition: gr55xx_ll_qspi.h:3427
ll_qspi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_qspi_get_dma_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_qspi.h:2169
ll_qspi_deinit
error_status_t ll_qspi_deinit(qspi_regs_t *QSPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_qspi_disable_ss
__STATIC_INLINE void ll_qspi_disable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_qspi.h:1512
_ll_qspi_memorymapped_init_t::rd
ll_qspi_memorymapped_read_init_t rd
Definition: gr55xx_ll_qspi.h:260
ll_qspi_set_baud_rate_prescaler
__STATIC_INLINE void ll_qspi_set_baud_rate_prescaler(qspi_regs_t *QSPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_qspi.h:1548
ll_qspi_concurrent_enable_xip_prefetch
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_prefetch(qspi_regs_t *QSPIx)
Enable the pre-fetch feature for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2879
ll_qspi_is_enabled
__STATIC_INLINE uint32_t ll_qspi_is_enabled(qspi_regs_t *QSPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_qspi.h:1355
ll_qspi_get_dynamic_wait_state
__STATIC_INLINE uint32_t ll_qspi_get_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
get the value for dynamic wait state
Definition: gr55xx_ll_qspi.h:3496
ll_qspi_memorymapped_init_t
struct _ll_qspi_memorymapped_init_t ll_qspi_memorymapped_init_t
ll_qspi_concurrent_get_xip_incr_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2746
ll_qspi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_mode(qspi_regs_t *QSPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1474
ll_qspi_concurrent_get_xip_wr_wait_cycles
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3596
_ll_qspi_memorymapped_write_init_t::x_wr_instruction
uint32_t x_wr_instruction
Definition: gr55xx_ll_qspi.h:216
ll_qspi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_qspi_get_baud_rate_prescaler(qspi_regs_t *QSPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_qspi.h:1563
LL_QSPI1_XIP_RX_FIFO_DEPTH
#define LL_QSPI1_XIP_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:292
LL_QSPI0_REG_TX_FIFO_DEPTH
#define LL_QSPI0_REG_TX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:286
ll_qspi_concurrent_set_xip_incr_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction in xip mode
Definition: gr55xx_ll_qspi.h:2730
_ll_qspi_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_qspi.h:103
ll_qspi_set_instruction_size
__STATIC_INLINE void ll_qspi_set_instruction_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_qspi.h:2467
ll_qspi_is_enabled_xip
uint32_t ll_qspi_is_enabled_xip(qspi_regs_t *QSPIx)
Check if qspi xip mode is enabled.
ll_qspi_clear_flag_mst
__STATIC_INLINE void ll_qspi_clear_flag_mst(qspi_regs_t *QSPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_qspi.h:2004
ll_qspi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_qspi_is_enabled_micro_handshake(qspi_regs_t *QSPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_qspi.h:1400
ll_qspi_set_standard
__STATIC_INLINE void ll_qspi_set_standard(qspi_regs_t *QSPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_qspi.h:1252
ll_qspi_concurrent_set_xip_wr_wrap_inst
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3546
ll_qspi_init
error_status_t ll_qspi_init(qspi_regs_t *QSPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
ll_qspi_set_micro_transfer_mode
__STATIC_INLINE void ll_qspi_set_micro_transfer_mode(qspi_regs_t *QSPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_qspi.h:1456
ll_qspi_concurrent_get_xip_mode_bits_length
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_length(qspi_regs_t *QSPIx)
Get the length of mode bits phase for concurrent xip mode.
Definition: gr55xx_ll_qspi.h:2680
LL_QSPI2_XIP_RX_FIFO_DEPTH
#define LL_QSPI2_XIP_RX_FIFO_DEPTH
Definition: gr55xx_ll_qspi.h:297
ll_qspi_concurrent_get_xip_wr_wrap_inst
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction for write in xip mode
Definition: gr55xx_ll_qspi.h:3562
ll_qspi_concurrent_set_xip_wr_address_size
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip write mode.
Definition: gr55xx_ll_qspi.h:3663
ll_qspi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_qspi_get_raw_if_flag(qspi_regs_t *QSPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_qspi.h:1934
ll_qspi_set_clock_polarity
__STATIC_INLINE void ll_qspi_set_clock_polarity(qspi_regs_t *QSPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_qspi.h:1178