gr55xx_ll_aon_pmu.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_pmu.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PMU LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PMU PMU LL Module Driver
47 * @brief PMU LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_PMU_H_
53 #define __GR55XX_LL_PMU_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61
62 /** @defgroup AON_PMU_LL_DRIVER_FUNCTIONS Functions
63 * @{
64 */
65 /**
66 * @brief Enable the RTC
67 *
68 * Register|BitsName
69 * --------|--------
70 * RF_REG_0 | RTC_EN
71 *
72 * @retval None
73 *
74 */
75 __STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
76 {
77 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
78 }
79
80 /**
81 * @brief Enable the RTC and bypass GM
82 *
83 * Register|BitsName
84 * --------|--------
85 * RF_REG_0 | RTC_EN
86 * | CGM_MODE
87 *
88 * @retval None
89 *
90 */
91 __STATIC_INLINE void ll_aon_pmu_enable_rtc_cgm(void)
92 {
93 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN_GM);
94 }
95
96 /**
97 * @brief Disable the RTC
98 *
99 * Register|BitsName
100 * --------|--------
101 * RF_REG_0 | RTC_EN
102 *
103 */
104 __STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
105 {
106 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
107 }
108
109 /**
110 * @brief Set RTC GM
111 *
112 * Register|BitsName
113 * --------|--------
114 * RF_REG_0 | EN
115 *
116 * @param value: The rtc gm value.
117 *
118 */
119 __STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
120 {
121 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_GM, (value << AON_PMU_RF_REG_0_RTC_GM_Pos));
122 }
123
124 /**
125 * @brief Set lv,default is set to 1.8V,LSB = 8.5mv
126 *
127 * Register|BitsName
128 * --------|--------
129 * RF_REG_0 | EN
130 *
131 * @param value: The io ldo vout value.
132 *
133 */
134 __STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
135 {
136 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1, (value << AON_PMU_RF_REG_0_IO_LDO_REG1_Pos));
137 }
138
139 /**
140 * @brief Get the io ldo vout
141 *
142 * Register|BitsName
143 * --------|--------
144 * RF_REG_0 | vref_sel_lv_6_0
145 *
146 * @retval The io ldo vout value..
147 *
148 */
149 __STATIC_INLINE uint32_t ll_aon_pmu_get_io_ldo_vout(void)
150 {
151 return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1) >> AON_PMU_RF_REG_0_IO_LDO_REG1_Pos);
152 }
153
154 /**
155 * @brief Set stb io ldo
156 *
157 * Register|BitsName
158 * --------|--------
159 * RF_REG_3 | EN
160 *
161 * @param value: The io ldo vout value.
162 *
163 */
164 __STATIC_INLINE void ll_aon_pmu_set_stb_io_ldo_vout(uint32_t value)
165 {
166 MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_IO_LDO_REG2, ((value | 0x03) << AON_PMU_RF_REG_3_IO_LDO_REG2_Pos));
167 }
168
169 /**
170 * @brief Set retention level
171 *
172 * Register|BitsName
173 * --------|--------
174 * RF_REG_0 | ctrl_ret
175 *
176 * @param value: The retention level value.
177 *
178 */
179 __STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
180 {
181 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET, (value << AON_PMU_RF_REG_0_CTRL_RET_Pos));
182 }
183
184
185 /**
186 * @brief Get retention level
187 *
188 * Register|BitsName
189 * --------|--------
190 * RF_REG_0 | ctrl_ret
191 *
192 * @retval The current retention level.
193 *
194 */
195 __STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
196 {
197 return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET) >> AON_PMU_RF_REG_0_CTRL_RET_Pos);
198 }
199
200 /**
201 * @brief Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
202 *
203 * Register|BitsName
204 * --------|--------
205 * PMU_DCDC_VREF | DCDC_VREF_REG_VAL
206 *
207 * @param value: the dcdc vreg value.
208 *
209 */
210 __STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
211 {
212 MODIFY_REG(AON_PMU->PMU_DCDC_VREF, AON_PMU_DCDC_VREF_REG_VAL, (value << AON_PMU_DCDC_VREF_REG_VAL_Pos));
213 }
214
215 /**
216 * @brief Get dcdc vreg
217 *
218 * Register|BitsName
219 * --------|--------
220 * PMU_DCDC_VREF | DCDC_VREF_REG_VAL
221 *
222 * @retval The dcdc vreg value.
223 *
224 */
225 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
226 {
227 return (READ_BITS(AON_PMU->PMU_DCDC_VREF, AON_PMU_DCDC_VREF_REG_VAL) >> AON_PMU_DCDC_VREF_REG_VAL_Pos);
228 }
229
230 /**
231 * @brief Enable the io ldo bypass
232 *
233 * Register|BitsName
234 * --------|--------
235 * RF_REG_3 | BYPASS_EN
236 *
237 */
238 __STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
239 {
240 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
241 }
242
243 /**
244 * @brief Disable the io ldo bypass
245 *
246 * Register|BitsName
247 * --------|--------
248 * RF_REG_3 | BYPASS_EN
249 *
250 */
251 __STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
252 {
253 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
254 }
255
256 /**
257 * @brief Set dig ldo coarse and fine code
258 *
259 * Register|BitsName
260 * --------|--------
261 * RF_REG_4 | DIG_LDO_EN
262 *
263 * @param coarse_code: The dig ldo coarse.
264 * @param fine_code: The fine code value.
265 *
266 */
267 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_coarse_fine_code(uint32_t coarse_code, uint32_t fine_code)
268 {
269 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CORE_VO_SEL, ((coarse_code & 0x03) << AON_PMU_RF_REG_4_CORE_VO_SEL_Pos));
270 MODIFY_REG(AON_PMU->PMU_CORE_LDO_VREF, AON_PMU_CORE_LDO_VREF, ((fine_code & 0xF) << 9U));
271 }
272
273 /**
274 * @brief Get dig ldo coarse code
275 *
276 * Register|BitsName
277 * --------|--------
278 * RF_REG_4 | core_vo_sel
279 *
280 */
281 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_coarse_code(void)
282 {
283 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CORE_VO_SEL) >> AON_PMU_RF_REG_4_CORE_VO_SEL_Pos);
284 }
285
286 /**
287 * @brief Get dig ldo fine code
288 *
289 * Register|BitsName
290 * --------|--------
291 * PMU_CORE_LDO_VREF | reg_aon_pmu_core_ldo_vref
292 *
293 */
294 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_fine_code(void)
295 {
296 return (READ_BITS(AON_PMU->PMU_CORE_LDO_VREF, AON_PMU_CORE_LDO_VREF) >> 9U);
297 }
298
299
300
301 /**
302 * @brief Set dig ldo out
303 *
304 * Register|BitsName
305 * --------|--------
306 * RF_REG_4 | DIG_LDO_EN
307 *
308 * @param value: The dig ldo out value.
309 *
310 */
311 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
312 {
313 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CORE_VO_SEL, (((value >> 6) & 0x03) << AON_PMU_RF_REG_4_CORE_VO_SEL_Pos));
314 MODIFY_REG(AON_PMU->PMU_CORE_LDO_VREF, AON_PMU_CORE_LDO_VREF_REG_SEL, (((value >> 0)& 0x01) << AON_PMU_CORE_LDO_VREF_REG_SEL_Pos));
315 MODIFY_REG(AON_PMU->PMU_CORE_LDO_VREF, AON_PMU_CORE_LDO_VREF, (((value >> 1)& 0x1F) << AON_PMU_CORE_LDO_VREF_Pos));
316 }
317
318 /**
319 * @brief Get dig ldo out
320 *
321 * Register|BitsName
322 * --------|--------
323 * RF_REG_4 | DIG_LDO_EN
324 *
325 */
326 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
327 {
328 return (READ_BITS(AON_PMU->PMU_CORE_LDO_VREF, AON_PMU_CORE_LDO_VREF) >> AON_PMU_CORE_LDO_VREF_Pos);
329 }
330
331
332 /**
333 * @brief Enable the dig ldo bypass
334 *
335 * Register|BitsName
336 * --------|--------
337 * RF_REG_4 | BYPASS_EN
338 *
339 */
340 __STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
341 {
342 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
343 }
344
345 /**
346 * @brief Disable the dig ldo bypass
347 *
348 * Register|BitsName
349 * --------|--------
350 * RF_REG_4 | BYPASS_EN
351 *
352 */
353 __STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
354 {
355 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
356 }
357
358 /**
359 * @brief Set the dig ldo bypass
360 *
361 * Register|BitsName
362 * --------|--------
363 * RF_REG_4 | BYPASS_EN
364 *
365 * @param enable: Aon pmu set dig ldo bypass enable.
366 *
367 */
368 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
369 {
370 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN, (enable << AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos));
371 }
372
373 /**
374 * @brief Get the dig ldo bypass
375 *
376 * Register|BitsName
377 * --------|--------
378 * RF_REG_4 | BYPASS_EN
379 *
380 * @retval The dig ldo bypass enable value.
381 *
382 */
383 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
384 {
385 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN) >> AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos);
386 }
387
388
389 /**
390 * @brief Get dig ldo out
391 *
392 * Register|BitsName
393 * --------|--------
394 * RF_REG_4 | DIG_LDO_EN
395 *
396 */
397 __STATIC_INLINE void ll_aon_pmu_disable_sysldo(void)
398 {
399 MODIFY_REG(AON_PMU->FS_REG_0, AON_PMU_FS_REG_0_DCDC_EN, (0 << AON_PMU_FS_REG_0_DCDC_EN_Pos));
400 MODIFY_REG(AON_PMU->FS_REG_0, AON_PMU_FS_REG_0_SYSLDO_EN, (0 << AON_PMU_FS_REG_0_SYSLDO_EN_Pos));
401 }
402
403 /**
404 * @brief Set clk period
405 *
406 * Register|BitsName
407 * --------|--------
408 * RF_REG_4 | CLK_PERIOD
409 *
410 * @param value: The clock period value.
411 * @retval None
412 *
413 */
414 __STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
415 {
416 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CLK_PERIOD, (value << AON_PMU_RF_REG_4_CLK_PERIOD_Pos));
417 }
418
419 /**
420 * @brief Enables clock injection from XO to ring oscillator.
421 *
422 * Register|BitsName
423 * --------|--------
424 * RF_REG_1 | EN_INJ_ON
425 *
426 * @param value: The clock period value.
427 * @retval None
428 *
429 */
430 __STATIC_FORCEINLINE void ll_aon_pmu_set_clk_inject(uint32_t value)
431 {
432 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_EN_INJ, (value << AON_PMU_RF_REG_1_EN_INJ_Pos));
433 }
434
435 /**
436 * @brief Enable the dcdc ton startup
437 *
438 * Register|BitsName
439 * --------|--------
440 * DCDC_LDO_REG_0 | TON_STARTUP
441 *
442 */
443 __STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
444 {
445 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_TON_STARTUP);
446 }
447
448
449 /**
450 * @brief Set the dcdc power source.
451 *
452 * Register|BitsName
453 * --------|--------
454 * RF_REG_1 | vddint_sel
455 *
456 * @param value: Dcdc power source.
457 * @retval None
458 *
459 */
460 __STATIC_INLINE void ll_aon_pmu_set_dcdc_pwr_src(uint32_t value)
461 {
462 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_PWR_SRC_Msk, (value << AON_PMU_RF_REG_1_DCDC_PWR_SRC_Pos));
463 }
464
465
466 /**
467 * @brief Set the rtc cur cap
468 *
469 * Register|BitsName
470 * --------|--------
471 * RC_RTC_REG_0 | RTC_CAP
472 *
473 * @param value: The rtc current cap value.
474 *
475 */
476 __STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
477 {
478 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CS, (value << AON_PMU_RC_RTC_REG0_RTC_CS_Pos));
479 }
480
481 /**
482 * @brief Set the rtc cur cap
483 *
484 * Register|BitsName
485 * --------|--------
486 * RC_RTC_REG_0 | RTC_CAP
487 *
488 * @param value: The rtc current cap value.
489 *
490 */
491 __STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
492 {
493 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP, (value << AON_PMU_RC_RTC_REG0_RTC_CAP_Pos));
494 }
495
496 /**
497 * @brief Get the rtc cur cap
498 *
499 * Register|BitsName
500 * --------|--------
501 * RC_RTC_REG_0 | RTC_CAP
502 *
503 * @retval The rtc current cap value.
504 *
505 */
506 __STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
507 {
508 return (READ_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP) >> AON_PMU_RC_RTC_REG0_RTC_CAP_Pos);
509 }
510
511 /**
512 * @brief Enable the RCOSC
513 *
514 * Register|BitsName
515 * --------|--------
516 * RC_RTC_REG_0 | RCOSC
517 *
518 */
519 __STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
520 {
521 SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
522 }
523
524 /**
525 * @brief Disable the RCOSC
526 *
527 * Register|BitsName
528 * --------|--------
529 * RC_RTC_REG_0 | RCOSC
530 *
531 */
532 __STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
533 {
534 CLEAR_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
535 }
536
537 /**
538 * @brief modify lpd active
539 *
540 * Register|BitsName
541 * --------|--------
542 * PMU_LPD_CFG | LPD_VAON_ACTIVE
543 *
544 * @param value: Lpd active.
545 *
546 */
547 __STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
548 {
549 MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_CFG_VAON_ACTIVE, (value << AON_PMU_LPD_CFG_VAON_ACTIVE_Pos));
550 }
551 /**
552 * @brief modify lpd sleep
553 *
554 * Register|BitsName
555 * --------|--------
556 * PMU_LPD_CFG | LPD_VAON_SLEEP
557 *
558 * @param value: Lpd sleep.
559 *
560 */
561 __STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
562 {
563 MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_CFG_VAON_SLEEP, (value << AON_PMU_LPD_CFG_VAON_SLEEP_Pos));
564 }
565 /**
566 * @brief modify ton on
567 *
568 * Register|BitsName
569 * --------|--------
570 * PMU_TON_CFG | AON_PMU_TON_CTRL_ON
571 *
572 * @param value: Ton on.
573 *
574 */
575 __STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
576 {
577 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CFG_CTL_ON_VAL, (value << AON_PMU_TON_CFG_CTL_ON_VAL_Pos));
578 }
579
580 /**
581 * @brief Get tx ton value
582 *
583 * Register|BitsName
584 * --------|--------
585 * PMU_TON_CFG | AON_PMU_TON_CTRL_ON
586 *
587 * @retval The current tx ton value.
588 *
589 */
590 __STATIC_INLINE uint32_t ll_aon_pmu_get_tx_ton_val(void)
591 {
592 return (READ_BITS(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CFG_CTL_ON_VAL) >> AON_PMU_TON_CFG_CTL_ON_VAL_Pos);
593 }
594
595 /**
596 * @brief modify ton off
597 *
598 * Register|BitsName
599 * --------|--------
600 * PMU_TON_CFG | AON_PMU_TON_CTRL_OFF
601 *
602 * @param value: Ton off.
603 *
604 */
605 __STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
606 {
607 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CFG_CTL_OFF_VAL, (value << AON_PMU_TON_CFG_CTL_OFF_VAL_Pos));
608 }
609 /**
610 * @brief modify rng bump
611 *
612 * Register|BitsName
613 * --------|--------
614 * RF_REG_0 | AON_PMU_RF_REG_0_RNG_CLK_BUMP
615 *
616 * @param value: Rng bump.
617 *
618 */
619 __STATIC_INLINE void ll_aon_pmu_set_rng_clk_bump_val(uint32_t value)
620 {
621 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_CLK_BUMP, (value << AON_PMU_RF_REG_0_RNG_CLK_BUMP_Pos));
622 }
623 /**
624 * @brief modify rng cont
625 *
626 * Register|BitsName
627 * --------|--------
628 * RF_REG_0 | AON_PMU_RF_REG_0_RNG_FREQ_CONT
629 *
630 * @param value: Rng cont.
631 *
632 */
633 __STATIC_INLINE void ll_aon_pmu_set_rng_freq_cont(uint32_t value)
634 {
635 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_FREQ_CONT, (value << AON_PMU_RF_REG_0_RNG_FREQ_CONT_Pos));
636 }
637 /**
638 * @brief modify bg en
639 *
640 * Register|BitsName
641 * --------|--------
642 * RF_REG_4 | AON_PMU_RF_REG_4_BG_EN
643 *
644 * @param value: Bg en.
645 *
646 */
647 __STATIC_INLINE void ll_aon_pmu_set_bg_en(uint32_t value)
648 {
649 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_BG_EN, (value << AON_PMU_RF_REG_4_BG_EN_Pos));
650 }
651 /** @} */
652
653
654 /**
655 * @brief Enable short aon digcore
656 *
657 * Register|BitsName
658 * --------|--------
659 * RF_REG4 | rg_core2aon_sw_en
660 *
661 * @retval None
662 *
663 */
664 __STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
665 {
666 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_SHORT_AON_DIGCORE);
667 }
668
669 /**
670 * @brief Disable short aon digcore
671 *
672 * Register|BitsName
673 * --------|--------
674 * RF_REG4 | rg_core2aon_sw_en
675 *
676 * @retval None
677 *
678 */
679 __STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
680 {
681 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_SHORT_AON_DIGCORE);
682 }
683
684 #ifdef __cplusplus
685 }
686 #endif
687
688 #endif
689
690 /** @} */
691
692 /** @} */
693
694 /** @} */
ll_aon_pmu_get_io_ldo_vout
__STATIC_INLINE uint32_t ll_aon_pmu_get_io_ldo_vout(void)
Get the io ldo vout.
Definition: gr55xx_ll_aon_pmu.h:149
ll_aon_pmu_set_dig_ldo_out
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
Set dig ldo out.
Definition: gr55xx_ll_aon_pmu.h:311
ll_aon_pmu_set_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
Set the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:368
ll_aon_pmu_set_rng_freq_cont
__STATIC_INLINE void ll_aon_pmu_set_rng_freq_cont(uint32_t value)
modify rng cont
Definition: gr55xx_ll_aon_pmu.h:633
ll_aon_pmu_set_lpd_active
__STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
modify lpd active
Definition: gr55xx_ll_aon_pmu.h:547
ll_aon_pmu_enable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
Enable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:340
ll_aon_pmu_set_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
modify ton on
Definition: gr55xx_ll_aon_pmu.h:575
ll_aon_pmu_get_dig_ldo_bypass
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
Get the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:383
ll_aon_pmu_set_clk_period
__STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
Set clk period.
Definition: gr55xx_ll_aon_pmu.h:414
ll_aon_pmu_disable_sysldo
__STATIC_INLINE void ll_aon_pmu_disable_sysldo(void)
Get dig ldo out.
Definition: gr55xx_ll_aon_pmu.h:397
ll_aon_pmu_enable_ton_startup_overide
__STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
Enable the dcdc ton startup.
Definition: gr55xx_ll_aon_pmu.h:443
ll_aon_pmu_get_dig_ldo_coarse_code
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_coarse_code(void)
Get dig ldo coarse code.
Definition: gr55xx_ll_aon_pmu.h:281
ll_aon_pmu_set_rtc_cs
__STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:476
ll_aon_pmu_set_non_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
modify ton off
Definition: gr55xx_ll_aon_pmu.h:605
ll_aon_pmu_set_bg_en
__STATIC_INLINE void ll_aon_pmu_set_bg_en(uint32_t value)
modify bg en
Definition: gr55xx_ll_aon_pmu.h:647
ll_aon_pmu_set_dig_ldo_coarse_fine_code
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_coarse_fine_code(uint32_t coarse_code, uint32_t fine_code)
Set dig ldo coarse and fine code.
Definition: gr55xx_ll_aon_pmu.h:267
ll_aon_pmu_disable_rtc
__STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
Disable the RTC.
Definition: gr55xx_ll_aon_pmu.h:104
ll_aon_pmu_set_rtc_gm
__STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
Set RTC GM.
Definition: gr55xx_ll_aon_pmu.h:119
ll_aon_pmu_set_retention_level
__STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
Set retention level.
Definition: gr55xx_ll_aon_pmu.h:179
ll_aon_pmu_set_rng_clk_bump_val
__STATIC_INLINE void ll_aon_pmu_set_rng_clk_bump_val(uint32_t value)
modify rng bump
Definition: gr55xx_ll_aon_pmu.h:619
ll_aon_pmu_enable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
Enable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:664
ll_aon_pmu_set_lpd_sleep
__STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
modify lpd sleep
Definition: gr55xx_ll_aon_pmu.h:561
ll_aon_pmu_get_retention_level
__STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
Get retention level.
Definition: gr55xx_ll_aon_pmu.h:195
ll_aon_pmu_enable_rtc_cgm
__STATIC_INLINE void ll_aon_pmu_enable_rtc_cgm(void)
Enable the RTC and bypass GM.
Definition: gr55xx_ll_aon_pmu.h:91
ll_aon_pmu_disable_rcosc
__STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
Disable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:532
ll_aon_pmu_enable_rtc
__STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
Enable the RTC.
Definition: gr55xx_ll_aon_pmu.h:75
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_aon_pmu_enable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
Enable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:238
ll_aon_pmu_set_dcdc_pwr_src
__STATIC_INLINE void ll_aon_pmu_set_dcdc_pwr_src(uint32_t value)
Set the dcdc power source.
Definition: gr55xx_ll_aon_pmu.h:460
ll_aon_pmu_set_rtc_cap
__STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:491
ll_aon_pmu_set_dcdc_vreg
__STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
Definition: gr55xx_ll_aon_pmu.h:210
ll_aon_pmu_set_clk_inject
__STATIC_FORCEINLINE void ll_aon_pmu_set_clk_inject(uint32_t value)
Enables clock injection from XO to ring oscillator.
Definition: gr55xx_ll_aon_pmu.h:430
ll_aon_pmu_disable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
Disable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:679
ll_aon_pmu_get_tx_ton_val
__STATIC_INLINE uint32_t ll_aon_pmu_get_tx_ton_val(void)
Get tx ton value.
Definition: gr55xx_ll_aon_pmu.h:590
ll_aon_pmu_enable_rcosc
__STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
Enable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:519
ll_aon_pmu_set_stb_io_ldo_vout
__STATIC_INLINE void ll_aon_pmu_set_stb_io_ldo_vout(uint32_t value)
Set stb io ldo.
Definition: gr55xx_ll_aon_pmu.h:164
ll_aon_pmu_disable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
Disable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:353
ll_aon_pmu_get_dcdc_vreg
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
Get dcdc vreg.
Definition: gr55xx_ll_aon_pmu.h:225
ll_aon_pmu_get_dig_ldo_fine_code
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_fine_code(void)
Get dig ldo fine code.
Definition: gr55xx_ll_aon_pmu.h:294
ll_aon_pmu_get_dig_ldo_out
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
Get dig ldo out.
Definition: gr55xx_ll_aon_pmu.h:326
ll_aon_pmu_set_io_ldo_vout
__STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
Set lv,default is set to 1.8V,LSB = 8.5mv.
Definition: gr55xx_ll_aon_pmu.h:134
ll_aon_pmu_disable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
Disable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:251
ll_aon_pmu_get_rtc_cap
__STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
Get the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:506