gr55xx_hal_qspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_QSPI QSPI
47 * @brief QSPI HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_QSPI_H__
53 #define __GR55xx_HAL_QSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60
61 #include "gr55xx_ll_qspi.h"
62 #include "gr55xx_hal_def.h"
63
64 /* Exported types ------------------------------------------------------------*/
65 /** @addtogroup HAL_QSPI_ENUMERATIONS Enumerations
66 * @{
67 */
68
69 /** @defgroup HAL_QSPI_state HAL QSPI state
70 * @{
71 */
72
73 /**
74 * @brief HAL QSPI State Enumerations definition
75 */
76 typedef enum
77 {
78 HAL_QSPI_STATE_RESET = 0x00, /**< Peripheral not initialized */
79 HAL_QSPI_STATE_READY = 0x01, /**< Peripheral initialized and ready for use */
80 HAL_QSPI_STATE_BUSY = 0x02, /**< Peripheral in indirect mode and busy */
81 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /**< Peripheral in indirect mode with transmission ongoing */
82 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /**< Peripheral in indirect mode with reception ongoing */
83 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
84 HAL_QSPI_STATE_ABORT = 0x08, /**< Peripheral with abort request ongoing */
85 HAL_QSPI_STATE_ERROR = 0x04 /**< Peripheral in error */
86
87 } hal_qspi_state_t;
88
89 /**
90 *@brief HAL Status structures Of memorymapped definition
91 */
92 typedef enum
93 {
94 HAL_MMAPPED_STATE_DEACTIVED = 0x00U, /**< Deactived. */
95 HAL_MMAPPED_STATE_ACTIVED = 0x01U, /**< Actived. */
96 HAL_MMAPPED_STATE_ERROR = 0xFFU, /**< Actived. */
97 } hal_memorymapped_status_t;
98
99 /**
100 *@brief KEY index enum for memorymapped mode, use to modify any parameter quickly
101 */
102 typedef enum _qspi_memorymapped_idx_e {
103 QSPI_MMAPED_IDX_DFS_HARDCCODE_EN = 0x00, /**< paired value: QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE/QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE */
104 QSPI_MMAPED_IDX_DFS = 0x01, /**< paired value: @ref QSPI_CONCURRENT_XIP_DFS*/
105 QSPI_MMAPED_IDX_INST_EN = 0x02, /**< paired value: QSPI_CONCURRENT_XIP_INST_ENABLE/QSPI_CONCURRENT_XIP_INST_DISABLE */
106 QSPI_MMAPED_IDX_INST_SIZE = 0x03, /**< paired value: @ref QSPI_CONCURRENT_XIP_INSTSIZE */
107 QSPI_MMAPED_IDX_INST_VAL = 0x04, /**< paired value: instruction data */
108 QSPI_MMAPED_IDX_ADDR_SIZE = 0x05, /**< paired value: @ref QSPI_CONCURRENT_XIP_ADDRSIZE */
109 QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT = 0x06, /**< paired value: @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT */
110 QSPI_MMAPED_IDX_MODE_BITS_EN = 0x07, /**< paired value: QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE / QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE */
111 QSPI_MMAPED_IDX_MODE_BITS_SIZE = 0x08, /**< paired value: @ref QSPI_CONCURRENT_XIP_MBL */
112 QSPI_MMAPED_IDX_MODE_BITS_VAL = 0x09, /**< paired value: mode bits data */
113 QSPI_MMAPED_IDX_WAIT_CYCLES = 0x0A, /**< paired value: wait cycles, 0 ~ 31 */
114 QSPI_MMAPED_IDX_DATA_FRF = 0x0B, /**< paired value: @ref QSPI_CONCURRENT_XIP_FRF */
115 QSPI_MMAPED_IDX_PREFETCH_EN = 0x0C, /**< paired value: QSPI_CONCURRENT_XIP_PREFETCH_ENABLE / QSPI_CONCURRENT_XIP_PREFETCH_DISABLE */
116 QSPI_MMAPED_IDX_CONT_XFER_EN = 0x0D, /**< paired value: QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE / QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE*/
117 QSPI_MMAPED_IDX_CONT_XFER_TOC = 0x0E, /**< paired value: timeout count for the continuous transfer, 0 ~ 255 */
118 QSPI_MMAPED_IDX_EDIAN_MODE = 0x0F, /**< paired value: @ref QSPI_CONCURRENT_XIP_ENDIAN_MODE */
119 } qspi_memorymapped_idx_e;
120
121 /** @} */
122
123 /** @} */
124
125 /** @addtogroup HAL_QSPI_STRUCTURES Structures
126 * @{
127 */
128
129 /** @defgroup QSPI_Configuration QSPI Configuration
130 * @{
131 */
132
133 /**
134 * @brief QSPI init Structure definition.
135 */
136 typedef struct _qspi_init_t
137 {
138 uint32_t clock_prescaler; /**< Specifies the prescaler factor for generating clock based on the AHB clock.
139 This parameter can be a number between 0 and 0xFFFF. */
140
141 uint32_t clock_mode; /**< Specifies the Clock Mode. It indicates the level that clock takes between commands.
142 This parameter can be a value of @ref QSPI_Clock_Mode. */
143
144 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
145 This parameter can be a number between 0 and 0x7. */
146 } qspi_init_t;
147 /** @} */
148
149 /** @defgroup QSPI_handle QSPI handle
150 * @{
151 */
152
153 /**
154 * @brief QSPI handle Structure definition
155 */
156 typedef struct _qspi_handle
157 {
158 qspi_regs_t *p_instance; /**< QSPI registers base address. */
159
160 qspi_init_t init; /**< QSPI communication parameters. */
161
162 uint8_t *p_tx_buffer; /**< Pointer to QSPI Tx transfer Buffer. */
163
164 __IO uint32_t tx_xfer_size; /**< QSPI Tx Transfer size. */
165
166 __IO uint32_t tx_xfer_count; /**< QSPI Tx Transfer Counter */
167
168 uint8_t *p_rx_buffer; /**< Pointer to QSPI Rx transfer Buffer */
169
170 __IO uint32_t rx_xfer_size; /**< QSPI Rx Transfer size */
171
172 __IO uint32_t rx_xfer_count; /**< QSPI Rx Transfer Counter */
173
174 void (*write_fifo)(struct _qspi_handle *p_qspi); /**< Pointer to QSPI Tx transfer FIFO write function */
175
176 void (*read_fifo)(struct _qspi_handle *p_qspi); /**< Pointer to QSPI Rx transfer FIFO read function */
177
178 dma_handle_t *p_dma; /**< QSPI Rx/Tx DMA Handle parameters */
179
180 __IO hal_lock_t lock; /**< Locking object */
181
182 __IO hal_qspi_state_t state; /**< QSPI communication state */
183
184 __IO uint32_t error_code; /**< QSPI Error code */
185
186 uint32_t timeout; /**< Timeout for the QSPI memory access */
187
188 uint32_t retention[22]; /**< Save important register information. */
189 } qspi_handle_t;
190 /** @} */
191
192 /** @defgroup QSPI_Command QSPI command
193 * @{
194 */
195
196 /**
197 * @brief QSPI command Structure definition
198 */
199 typedef struct _qspi_command_t
200 {
201 uint32_t instruction; /**< Specifies the Instruction to be sent.
202 This parameter can be a value (8-bit) between 0x00 and 0xFF. */
203
204 uint32_t address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
205 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
206
207 uint32_t instruction_size; /**< Specifies the Instruction Size.
208 This parameter can be a value of @ref QSPI_Instruction_Size. */
209
210 uint32_t address_size; /**< Specifies the Address Size.
211 This parameter can be a value of @ref QSPI_Address_Size. */
212
213 uint32_t dummy_cycles; /**< Specifies the Number of Dummy Cycles.
214 This parameter can be a number between 0 and 31. */
215
216 uint32_t data_size; /**< Specifies the QSPI address width.
217 This parameter can be a value of @ref QSPI_Data_Size. */
218
219 uint32_t instruction_address_mode; /**< Specifies the Instruction and Address Mode.
220 This parameter can be a value of @ref QSPI_Inst_Addr_Mode. */
221
222 uint32_t data_mode; /**< Specifies the Data Mode (used for dummy cycles and data phases).
223 This parameter can be a value of @ref QSPI_Data_Mode. */
224
225 uint32_t length; /**< Specifies the number of data to transfer. (This is the number of bytes).
226 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
227 until end of memory).
228 when using in DMA LLP xfer, length means total length of all linkedlist block in bytes */
229
230 uint32_t clock_stretch_en; /**< Specifies whether to enable the clock stretch feature
231 This parameter can be LL_QSPI_CLK_STRETCH_ENABLE or LL_QSPI_CLK_STRETCH_DISABLE */
232 } qspi_command_t;
233 /** @} */
234
235 /**
236 * @brief QSPI memory map Structure definition
237 */
238 typedef struct _qspi_memorymapped_t
239 {
240
241 uint32_t x_sioo_mode; /**< Specifies instruction sent mode in memorymapped(xip) mode.
242 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_SENT_MODE. */
243
244 uint32_t x_instruction_en; /**< Specifies whether to enable the instruction phase feature in memorymapped(xip) mode.
245 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_PHASE. */
246
247 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
248 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INSTSIZE.*/
249
250 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
251
252
253 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
254 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ADDRSIZE. */
255
256 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
257 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT. */
258
259 uint32_t x_mode_bits_en; /**< Specifies whether to enable mode bits phase in memorymapped(xip) mode.
260 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_MODE_BITS_PHASE. */
261
262 uint32_t x_mode_bits_length; /**< Specifies mode bits length.
263 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_MBL. */
264
265 uint32_t x_mode_bits_data; /**< Specifies value of mode bits phase */
266
267
268 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
269 value range [0 ~ 31]. */
270
271 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
272 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_FRF. */
273
274 uint32_t x_prefetch_en; /**< Specifies whether to enable the prefetch feature.
275 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_PREFETCH. */
276
277 uint32_t x_continous_xfer_en; /**< Specifies whether to enable the continuous transfer feature in memorymapped(xip) mode.
278 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_CONT_XFER. */
279
280 uint32_t x_continous_xfer_toc; /**< Specifies timeout count for the continuous transfer feature in memorymapped(xip) mode.
281 unit in terms of hclk, range [0, 255]. */
282
283 uint32_t x_endian_mode; /**< Specifies endian mode in memorymapped(xip) mode.
284 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ENDIAN_MODE. */
285
286 } qspi_memorymapped_t;
287
288 /**
289 * @brief QSPI memory map write Structure definition
290 */
291 typedef struct _qspi_memorymapped_write_t
292 {
293
294 uint32_t x_instruction_size; /**< Specifies instruction size in memorymapped(xip) mode.
295 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INSTSIZE. */
296
297 uint32_t x_instruction; /**< Specifies instruction in memorymapped(xip) mode. */
298
299
300 uint32_t x_address_size; /**< Specifies instruction size in memorymapped(xip) mode.
301 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_ADDRSIZE. */
302
303 uint32_t x_inst_addr_transfer_format; /**< Specifies xfer format of inst & addr in memorymapped(xip) mode.
304 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT. */
305
306 uint32_t x_dummy_cycles; /**< Specifies wait(dummy) cycles in memorymapped(xip) mode.
307 value range [0 ~ 31]. */
308
309 uint32_t x_data_frame_format; /**< Specifies enhanced spi's frame format in memorymapped(xip) mode.
310 This parameter can be a value of @ref QSPI_CONCURRENT_XIP_FRF. */
311 } qspi_memorymapped_write_t;
312
313 /**
314 *@brief KEY:Value pair to set memorymapped parameter.
315 */
316 typedef struct _qspi_memorymapped_set_t {
317 qspi_memorymapped_idx_e mmap_key; /**< Memorymapped key. */
318 uint32_t mmap_val; /**< Memorymapped value. */
319 } qspi_memorymapped_set_t;
320
321
322 /**
323 * @brief QSPI command for psram-write Structure definition.
324 */
325 typedef struct {
326
327 uint32_t data_size; /**< Specifies the QSPI data width.
328 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 : data_size support 8/16/32 bits;
329 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 : data_size support 8/16 bits.
330 This parameter can be a value of @ref QSPI_Data_Size. */
331
332 uint32_t data_block_length; /**< Specifies the number of data in each block, This is the number of bytes.
333 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 : the length equals each block's length(including the inst & addr length);
334 if llp_data_mode is QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 : the length equals the result of one inst&addr block plus one data block.
335 This parameter can be any value between 0 and 4095. */
336
337 uint32_t llp_data_mode; /**< Specifies Linked list data mode. @ref QSPI_PSRAM_DATA_IN_LLP_MODE. */
338
339 uint32_t llp_data_shape; /**< Specifies Linked list data shape.
340 Just support @ref QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_RECTANGLE now. */
341
342 } qspi_psram_command_t;
343
344
345 /** @} */
346
347
348 /** @addtogroup HAL_QSPI_CALLBACK_STRUCTURES Callback Structures
349 * @{
350 */
351
352 /** @defgroup HAL_QSPI_Callback Callback
353 * @{
354 */
355
356 /**
357 * @brief HAL_QSPI Callback function definition
358 */
359
360 typedef struct _hal_qspi_callback
361 {
362 void (*qspi_msp_init)(qspi_handle_t *p_qspi); /**< QSPI init MSP callback */
363 void (*qspi_msp_deinit)(qspi_handle_t *p_qspi); /**< QSPI de-init MSP callback */
364 void (*qspi_error_callback)(qspi_handle_t *p_qspi); /**< QSPI error callback */
365 void (*qspi_abort_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI abort complete callback */
366 void (*qspi_rx_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI rx transfer completed callback */
367 void (*qspi_tx_cplt_callback)(qspi_handle_t *p_qspi); /**< QSPI tx transfer completed callback */
368 } hal_qspi_callback_t;
369
370 /** @} */
371
372 /** @} */
373
374 /**
375 * @defgroup HAL_QSPI_MACRO Defines
376 * @{
377 */
378
379 /* Exported constants --------------------------------------------------------*/
380 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
381 * @{
382 */
383
384 /** @defgroup QSPI_DMA_CTRL_REGISTER_CFG Set DMA Control Register
385 * @{
386 */
387 /**@brief Set DMA Control Register.
388 *@param src_direction : DMA_SRC_INCREMENT, DMA_SRC_DECREMENT, DMA_SRC_NO_CHANGE
389 *@param src_tr_width : DMA_SDATAALIGN_BYTE, DMA_SDATAALIGN_HALFWORD, DMA_SDATAALIGN_WORD
390 *@param dst_tr_width : DMA_DDATAALIGN_BYTE, DMA_DDATAALIGN_HALFWORD, DMA_DDATAALIGN_WORD
391 *@param src_msize : DMA_CTLL_SRC_MSIZE_1/DMA_CTLL_SRC_MSIZE_4/DMA_CTLL_SRC_MSIZE_8/DMA_CTLL_SRC_MSIZE_16
392 *@param dst_msize : DMA_CTLL_DST_MSIZE_1/DMA_CTLL_DST_MSIZE_4/DMA_CTLL_DST_MSIZE_8/DMA_CTLL_DST_MSIZE_16
393 *@param en_gather : DMA_SRC_GATHER_ENABLE / DMA_SRC_GATHER_DISABLE
394 */
395 #define QSPI_DMA_CRTL_LOW_REGISTER_CFG(src_direction, src_tr_width, dst_tr_width, src_msize, dst_msize, en_gather) \
396 ( \
397 DMA_CTLL_INI_EN | DMA_MEMORY_TO_PERIPH | DMA_LLP_SRC_ENABLE | DMA_LLP_DST_DISABLE | \
398 en_gather | DMA_DST_SCATTER_DISABLE | DMA_DST_NO_CHANGE | \
399 src_direction | src_tr_width | dst_tr_width | src_msize | dst_msize \
400 )
401 /** @} */
402
403
404 /** @defgroup HAL_QSPI_FIFO_DEPTH Fifo Depth
405 * @{
406 */
407 #define QSPI_MAX_FIFO_DEPTH LL_QSPI_MAX_FIFO_DEPTH /**< Max FIFO Depth for QSPI Master. */
408 /** @} */
409
410 /** @defgroup QSPI_Error_Code QSPI Error Code
411 * @{
412 */
413 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /**< No error. */
414 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /**< Timeout error */
415 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /**< Transfer error */
416 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /**< DMA transfer error */
417 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /**< Invalid parameter error */
418 /** @} */
419
420 /** @defgroup QSPI_Clock_Mode QSPI Clock Mode
421 * @{
422 */
423
424 #define QSPI_CLOCK_MODE_0 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_1EDGE) /**< Inactive state of CLK is low; CLK toggles at the start of the first data bit */
425 #define QSPI_CLOCK_MODE_1 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_2EDGE) /**< Inactive state of CLK is low; CLK toggles in the middle of the first data bit */
426 #define QSPI_CLOCK_MODE_2 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_1EDGE) /**< Inactive state of CLK is high; CLK toggles at the start of the first data bit */
427 #define QSPI_CLOCK_MODE_3 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_2EDGE) /**< Inactive state of CLK is high; CLK toggles in the middle of the first data bit */
428
429 /** @} */
430
431 /** @defgroup QSPI_Data_Mode QSPI Data Mode
432 * @{
433 */
434
435 #define QSPI_DATA_MODE_SPI LL_QSPI_FRF_SPI /**< Standard SPI Frame Format */
436 #define QSPI_DATA_MODE_DUALSPI LL_QSPI_FRF_DUALSPI /**< Dual SPI Frame Format */
437 #define QSPI_DATA_MODE_QUADSPI LL_QSPI_FRF_QUADSPI /**< Quad SPI Frame Format */
438
439 /** @} */
440
441 /** @defgroup QSPI_Instruction_Size QSPI Instruction Size
442 * @{
443 */
444
445 #define QSPI_INSTSIZE_00_BITS LL_QSPI_INSTSIZE_0BIT /**< 0-bit (No Instruction) */
446 #define QSPI_INSTSIZE_04_BITS LL_QSPI_INSTSIZE_4BIT /**< 4-bit Instruction */
447 #define QSPI_INSTSIZE_08_BITS LL_QSPI_INSTSIZE_8BIT /**< 8-bit Instruction */
448 #define QSPI_INSTSIZE_16_BITS LL_QSPI_INSTSIZE_16BIT /**< 16-bit Instruction */
449
450 /** @} */
451
452 /** @defgroup QSPI_Address_Size QSPI Address Size
453 * @{
454 */
455
456 #define QSPI_ADDRSIZE_00_BITS LL_QSPI_ADDRSIZE_0BIT /**< 0-bit address */
457 #define QSPI_ADDRSIZE_04_BITS LL_QSPI_ADDRSIZE_4BIT /**< 4-bit address */
458 #define QSPI_ADDRSIZE_08_BITS LL_QSPI_ADDRSIZE_8BIT /**< 8-bit address */
459 #define QSPI_ADDRSIZE_12_BITS LL_QSPI_ADDRSIZE_12BIT /**< 12-bit address */
460 #define QSPI_ADDRSIZE_16_BITS LL_QSPI_ADDRSIZE_16BIT /**< 16-bit address */
461 #define QSPI_ADDRSIZE_20_BITS LL_QSPI_ADDRSIZE_20BIT /**< 20-bit address */
462 #define QSPI_ADDRSIZE_24_BITS LL_QSPI_ADDRSIZE_24BIT /**< 24-bit address */
463 #define QSPI_ADDRSIZE_28_BITS LL_QSPI_ADDRSIZE_28BIT /**< 28-bit address */
464 #define QSPI_ADDRSIZE_32_BITS LL_QSPI_ADDRSIZE_32BIT /**< 32-bit address */
465
466 /** @} */
467
468 /** @defgroup QSPI_Data_Size Data Width
469 * @{
470 */
471
472 #define QSPI_DATASIZE_04_BITS LL_QSPI_DATASIZE_4BIT /**< Data length for SPI transfer: 4 bits */
473 #define QSPI_DATASIZE_05_BITS LL_QSPI_DATASIZE_5BIT /**< Data length for SPI transfer: 5 bits */
474 #define QSPI_DATASIZE_06_BITS LL_QSPI_DATASIZE_6BIT /**< Data length for SPI transfer: 6 bits */
475 #define QSPI_DATASIZE_07_BITS LL_QSPI_DATASIZE_7BIT /**< Data length for SPI transfer: 7 bits */
476 #define QSPI_DATASIZE_08_BITS LL_QSPI_DATASIZE_8BIT /**< Data length for SPI transfer: 8 bits */
477 #define QSPI_DATASIZE_09_BITS LL_QSPI_DATASIZE_9BIT /**< Data length for SPI transfer: 9 bits */
478 #define QSPI_DATASIZE_10_BITS LL_QSPI_DATASIZE_10BIT /**< Data length for SPI transfer: 10 bits */
479 #define QSPI_DATASIZE_11_BITS LL_QSPI_DATASIZE_11BIT /**< Data length for SPI transfer: 11 bits */
480 #define QSPI_DATASIZE_12_BITS LL_QSPI_DATASIZE_12BIT /**< Data length for SPI transfer: 12 bits */
481 #define QSPI_DATASIZE_13_BITS LL_QSPI_DATASIZE_13BIT /**< Data length for SPI transfer: 13 bits */
482 #define QSPI_DATASIZE_14_BITS LL_QSPI_DATASIZE_14BIT /**< Data length for SPI transfer: 14 bits */
483 #define QSPI_DATASIZE_15_BITS LL_QSPI_DATASIZE_15BIT /**< Data length for SPI transfer: 15 bits */
484 #define QSPI_DATASIZE_16_BITS LL_QSPI_DATASIZE_16BIT /**< Data length for SPI transfer: 16 bits */
485 #define QSPI_DATASIZE_17_BITS LL_QSPI_DATASIZE_17BIT /**< Data length for SPI transfer: 17 bits */
486 #define QSPI_DATASIZE_18_BITS LL_QSPI_DATASIZE_18BIT /**< Data length for SPI transfer: 18 bits */
487 #define QSPI_DATASIZE_19_BITS LL_QSPI_DATASIZE_19BIT /**< Data length for SPI transfer: 19 bits */
488 #define QSPI_DATASIZE_20_BITS LL_QSPI_DATASIZE_20BIT /**< Data length for SPI transfer: 20 bits */
489 #define QSPI_DATASIZE_21_BITS LL_QSPI_DATASIZE_21BIT /**< Data length for SPI transfer: 21 bits */
490 #define QSPI_DATASIZE_22_BITS LL_QSPI_DATASIZE_22BIT /**< Data length for SPI transfer: 22 bits */
491 #define QSPI_DATASIZE_23_BITS LL_QSPI_DATASIZE_23BIT /**< Data length for SPI transfer: 23 bits */
492 #define QSPI_DATASIZE_24_BITS LL_QSPI_DATASIZE_24BIT /**< Data length for SPI transfer: 24 bits */
493 #define QSPI_DATASIZE_25_BITS LL_QSPI_DATASIZE_25BIT /**< Data length for SPI transfer: 25 bits */
494 #define QSPI_DATASIZE_26_BITS LL_QSPI_DATASIZE_26BIT /**< Data length for SPI transfer: 26 bits */
495 #define QSPI_DATASIZE_27_BITS LL_QSPI_DATASIZE_27BIT /**< Data length for SPI transfer: 27 bits */
496 #define QSPI_DATASIZE_28_BITS LL_QSPI_DATASIZE_28BIT /**< Data length for SPI transfer: 28 bits */
497 #define QSPI_DATASIZE_29_BITS LL_QSPI_DATASIZE_29BIT /**< Data length for SPI transfer: 29 bits */
498 #define QSPI_DATASIZE_30_BITS LL_QSPI_DATASIZE_30BIT /**< Data length for SPI transfer: 30 bits */
499 #define QSPI_DATASIZE_31_BITS LL_QSPI_DATASIZE_31BIT /**< Data length for SPI transfer: 31 bits */
500 #define QSPI_DATASIZE_32_BITS LL_QSPI_DATASIZE_32BIT /**< Data length for SPI transfer: 32 bits */
501
502
503 /** @} */
504
505
506 /** @defgroup QSPI_Inst_Addr_Mode QSPI Instruction and Address Mode
507 * @{
508 */
509
510 #define QSPI_INST_ADDR_ALL_IN_SPI LL_QSPI_INST_ADDR_ALL_IN_SPI /**< Instruction and address are sent in SPI mode */
511 #define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF /**< Instruction is sent in SPI mode, and address is sent in Daul/Quad SPI mode */
512 #define QSPI_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_INST_ADDR_ALL_IN_SPIFRF /**< Instruction and address are sent in Daul/Quad SPI mode */
513
514 /** @} */
515
516 /** @defgroup QSPI_Flags QSPI Flags
517 * @{
518 */
519
520 #define QSPI_FLAG_DCOL LL_QSPI_SR_DCOL /**< Data collision error flag */
521 #define QSPI_FLAG_TXE LL_QSPI_SR_TXE /**< Transmission error flag */
522 #define QSPI_FLAG_RFF LL_QSPI_SR_RFF /**< Rx FIFO full flag */
523 #define QSPI_FLAG_RFNE LL_QSPI_SR_RFNE /**< Rx FIFO not empty flag */
524 #define QSPI_FLAG_TFE LL_QSPI_SR_TFE /**< Tx FIFO empty flag */
525 #define QSPI_FLAG_TFNF LL_QSPI_SR_TFNF /**< Tx FIFO not full flag */
526 #define QSPI_FLAG_BUSY LL_QSPI_SR_BUSY /**< Busy flag */
527
528 /** @} */
529
530 /** @defgroup QSPI_Interrupts QSPI Interrupts
531 * @{
532 */
533
534 #define QSPI_IT_TXU LL_QSPI_IS_TXU /**< Transmit FIFO Underflow Interrupt flag */
535 #define QSPI_IT_XRXO LL_QSPI_IS_XRXO /**< XIP Receive FIFO Overflow Interrupt flag. */
536 #define QSPI_IT_MST LL_QSPI_IS_MST /**< Multi-Master Contention Interrupt flag. */
537 #define QSPI_IT_RXF LL_QSPI_IS_RXF /**< Receive FIFO Full Interrupt flag. */
538 #define QSPI_IT_RXO LL_QSPI_IS_RXO /**< Receive FIFO Overflow Interrupt flag. */
539 #define QSPI_IT_RXU LL_QSPI_IS_RXU /**< Receive FIFO Underflow Interrupt flag. */
540 #define QSPI_IT_TXO LL_QSPI_IS_TXO /**< Transmit FIFO Overflow Interrupt flag. */
541 #define QSPI_IT_TXE LL_QSPI_IS_TXE /**< Transmit FIFO Empty Interrupt flag. */
542 #define QSPI_IT_ALL LL_QSPI_IS_ALL /**< ALL QSPI Interrupts flag. */
543
544 /** @} */
545
546 /** @defgroup QSPI_Timeout_definition QSPI Timeout_definition
547 * @{
548 */
549 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000) /**< 5s. */
550 /** @} */
551
552 /** @defgroup QSPI_CONCURRENT_XIP_ENDIAN_MODE endian mode for qspi xip
553 * @{
554 */
555 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 /**< Default endian order from AHB. */
556 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 /**< Re-order the read data as [23:16], [31:24], [7:0], [15:8]. */
557 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 /**< Re-order the read data as [7:0], [15:8], [23:16], [31:24]. */
558 /** @} */
559
560 /** @defgroup QSPI_CONCURRENT_XIP_SLAVE Which Slave to Enable in XIP
561 * @{
562 */
563 #define QSPI_CONCURRENT_XIP_SLAVE0 LL_QSPI_CONCURRENT_XIP_SLAVE0 /**< Enable Slave0 in XIP. */
564 /** @} */
565
566 /** @defgroup QSPI_CONCURRENT_XIP_DFS data frame size in xip, take effect when enable DFS_HC
567 * @{
568 */
569 #define QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_CONCURRENT_XIP_DFS_BYTE /**< Set data frame size as byte. */
570 #define QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD /**< Set data frame size as halfword. */
571 #define QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_CONCURRENT_XIP_DFS_WORD /**< Set data frame size as word. */
572 /** @} */
573
574 /** @defgroup QSPI_CONCURRENT_XIP_MBL mode bits length for xip mode
575 * @{
576 */
577 #define QSPI_CONCURRENT_XIP_MBL_2 LL_QSPI_CONCURRENT_XIP_MBL_2 /**< mode bits length equals to 2 bit. */
578 #define QSPI_CONCURRENT_XIP_MBL_4 LL_QSPI_CONCURRENT_XIP_MBL_4 /**< mode bits length equals to 4 bit. */
579 #define QSPI_CONCURRENT_XIP_MBL_8 LL_QSPI_CONCURRENT_XIP_MBL_8 /**< mode bits length equals to 8 bit. */
580 #define QSPI_CONCURRENT_XIP_MBL_16 LL_QSPI_CONCURRENT_XIP_MBL_16 /**< mode bits length equals to 16 bit. */
581 /** @} */
582
583 /** @defgroup QSPI_CONCURRENT_XIP_INSTSIZE instruction size for concurrent xip mode
584 * @{
585 */
586 #define QSPI_CONCURRENT_XIP_INSTSIZE_0BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT /**< no instruction */
587 #define QSPI_CONCURRENT_XIP_INSTSIZE_4BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT /**< instruction size equals 4bits */
588 #define QSPI_CONCURRENT_XIP_INSTSIZE_8BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT /**< instruction size equals 8bits */
589 #define QSPI_CONCURRENT_XIP_INSTSIZE_16BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT /**< instruction size equals 16bits */
590 /** @} */
591
592 /** @defgroup QSPI_CONCURRENT_XIP_ADDRSIZE address size for concurrent xip mode
593 * @{
594 */
595 #define QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT /**< Address length for QSPI XIP transfer: 0 bits */
596 #define QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT /**< Address length for QSPI XIP transfer: 4 bits */
597 #define QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT /**< Address length for QSPI XIP transfer: 8 bits */
598 #define QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT /**< Address length for QSPI XIP transfer: 12 bits */
599 #define QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT /**< Address length for QSPI XIP transfer: 16 bits */
600 #define QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT /**< Address length for QSPI XIP transfer: 20 bits */
601 #define QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT /**< Address length for QSPI XIP transfer: 24 bits */
602 #define QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT /**< Address length for QSPI XIP transfer: 28 bits */
603 #define QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT /**< Address length for QSPI XIP transfer: 32 bits */
604 #define QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT /**< Address length for QSPI XIP transfer: 36 bits */
605 #define QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT /**< Address length for QSPI XIP transfer: 40 bits */
606 #define QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT /**< Address length for QSPI XIP transfer: 44 bits */
607 #define QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT /**< Address length for QSPI XIP transfer: 48 bits */
608 #define QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT /**< Address length for QSPI XIP transfer: 52 bits */
609 #define QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT /**< Address length for QSPI XIP transfer: 56 bits */
610 #define QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT /**< Address length for QSPI XIP transfer: 60 bits */
611 /** @} */
612
613 /** @defgroup QSPI_CONCURRENT_XIP_INST_ADDR_TRANSFER_FORMAT transfer of inst & address for concurrent xip mode
614 * @{
615 */
616 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI /**< Instruction and address are sent in SPI mode */
617 #define QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
618 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF /**< Instruction and address are sent in Daul/Quad SPI mode */
619 /** @} */
620
621 /** @defgroup QSPI_CONCURRENT_XIP_FRF frame format for concurrent xip mode
622 * @{
623 */
624 #define QSPI_CONCURRENT_XIP_FRF_RSVD LL_QSPI_CONCURRENT_XIP_FRF_RSVD /**< SPI Frame format : Reserved. */
625 #define QSPI_CONCURRENT_XIP_FRF_DUAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI /**< SPI Frame format : DUAL. */
626 #define QSPI_CONCURRENT_XIP_FRF_QUAD_SPI LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI /**< SPI Frame format : QUAD. */
627 #define QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI /**< SPI Frame format : OCTAL. */
628 /** @} */
629
630 /** @defgroup QSPI_XIP_CLK_STRETCH Mode Clock stretch mode
631 * @{
632 */
633 #define QSPI_CLK_STRETCH_ENABLE LL_QSPI_CLK_STRETCH_ENABLE /**< Enable Clock stretch. */
634 #define QSPI_CLK_STRETCH_DISABLE LL_QSPI_CLK_STRETCH_DISABLE /**< Disable Clock stretch. */
635 /** @} */
636
637 /** @defgroup QSPI_CONCURRENT_XIP_PREFETCH Prefetch for concurrent xip mode
638 * @{
639 */
640 #define QSPI_CONCURRENT_XIP_PREFETCH_ENABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE /**< Enable Prefetch. */
641 #define QSPI_CONCURRENT_XIP_PREFETCH_DISABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE /**< Disable Prefetch. */
642 /** @} */
643
644 /** @defgroup QSPI_CONCURRENT_XIP_CONT_XFER Cont transfer for concurrent xip mode
645 * @{
646 */
647 #define QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE /**< Enable Cont trasfer. */
648 #define QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE /**< Disable Cont trasfer. */
649 /** @} */
650
651 /** @defgroup QSPI_CONCURRENT_XIP_INST_PHASE Instruction phase for concurrent xip mode
652 * @{
653 */
654 #define QSPI_CONCURRENT_XIP_INST_ENABLE LL_QSPI_CONCURRENT_XIP_INST_ENABLE /**< Enable Instruction phase. */
655 #define QSPI_CONCURRENT_XIP_INST_DISABLE LL_QSPI_CONCURRENT_XIP_INST_DISABLE /**< Disable Instruction phase. */
656 /** @} */
657
658 /** @defgroup QSPI_CONCURRENT_XIP_MODE_BITS_PHASE Bits phase for concurrent xip mode
659 * @{
660 */
661 #define QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE /**< Enable Bits phase. */
662 #define QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE /**< Disable Bits phase. */
663 /** @} */
664
665 /** @defgroup QSPI_CONCURRENT_XIP_DFS_HARDCORE DFS hardcore for concurrent xip mode
666 * @{
667 */
668 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE /**< Enable DFS Hardcore. */
669 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE /**< Disable DFS Hardcore. */
670 /** @} */
671
672 /** @defgroup QSPI_CONCURRENT_XIP_INST_SENT_MODE Instruction sent mode for concurrent xip mode
673 * @{
674 */
675 #define QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS /*!< Send instruction for every transaction */
676 #define QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS /*!< Send instruction only for first transaction */
677 /** @} */
678
679
680 /** @defgroup QSPI_PSRAM_DATA_IN_LLP_MODE BLOCK Mode for LLP
681 * @{
682 */
683 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 0u /**< This is Loop Block Mode, inst & addr in the head of each block,
684 data are following insta & addr in the same block. */
685 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 1u /**< This is Crossed Block Mode, inst & addr in the first block,
686 data in the second block, then inst & addr block, then data block again,
687 and repeat till the end. */
688 /** @} */
689
690
691 /** @defgroup QSPI_PSRAM_DATA_BLOCK_SHAPE BLOCK SHAPE for DMA LLP
692 * @{
693 */
694 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_RECTANGLE 0u /**< Data length in every Block are the same */
695
696 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_NON_RECTANGLE 1u /**< Data length in every Block are the different */
697 /** @} */
698
699 /** @} */
700
701 /* Exported macro ------------------------------------------------------------*/
702 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
703 * @{
704 */
705
706 /** @brief Reset QSPI handle states.
707 * @param __HANDLE__ QSPI handle.
708 * @retval None
709 */
710 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_QSPI_STATE_RESET)
711
712 /** @brief Enable the specified QSPI peripheral.
713 * @param __HANDLE__ Specifies the QSPI Handle.
714 * @retval None
715 */
716
717 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
718
719 /** @brief Disable the specified QSPI peripheral.
720 * @param __HANDLE__ Specifies the QSPI Handle.
721 * @retval None
722 */
723
724 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
725
726 /** @brief Enable the QSPI DMA TX Request.
727 * @param __HANDLE__ Specifies the QSPI Handle.
728 * @retval None
729 */
730
731 #define __HAL_QSPI_ENABLE_DMATX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
732
733 /** @brief Enable the QSPI DMA RX Request.
734 * @param __HANDLE__ Specifies the QSPI Handle.
735 * @retval None
736 */
737 #define __HAL_QSPI_ENABLE_DMARX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
738
739
740 /** @brief Disable the QSPI DMA TX Request.
741 * @param __HANDLE__ Specifies the QSPI Handle.
742 * @retval None
743 */
744 #define __HAL_QSPI_DISABLE_DMATX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
745
746
747 /** @brief Disable the QSPI DMA RX Request.
748 * @param __HANDLE__ Specifies the QSPI Handle.
749 * @retval None
750 */
751 #define __HAL_QSPI_DISABLE_DMARX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
752
753
754 /** @brief Enable the specified QSPI interrupts.
755 * @param __HANDLE__ Specifies the QSPI Handle.
756 * @param __INTERRUPT__ Specifies the interrupt source to enable.
757 * This parameter can be one of the following values:
758 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
759 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
760 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
761 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
762 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
763 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
764 * @retval None
765 */
766 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
767
768
769 /** @brief Disable the specified QSPI interrupts.
770 * @param __HANDLE__ Specifies the QSPI handle.
771 * @param __INTERRUPT__ Specifies the interrupt source to disable.
772 * This parameter can be one of the following values:
773 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
774 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
775 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
776 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
777 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
778 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
779 * @retval None
780 */
781 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
782
783
784 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
785 * @param __HANDLE__ Specifies the QSPI Handle.
786 * @param __INTERRUPT__ Specifies the interrupt source to check.
787 * This parameter can be one of the following values:
788 * @arg @ref QSPI_IT_MST Multi-Master Contention Interrupt enable
789 * @arg @ref QSPI_IT_RXF Receive FIFO Full Interrupt enable
790 * @arg @ref QSPI_IT_RXO Receive FIFO Overflow Interrupt enable
791 * @arg @ref QSPI_IT_RXU Receive FIFO Underflow Interrupt enable
792 * @arg @ref QSPI_IT_TXO Transmit FIFO Overflow Interrupt enable
793 * @arg @ref QSPI_IT_TXE Transmit FIFO Empty Interrupt enable
794 * @retval The new state of __IT__ (TRUE or FALSE).
795 */
796 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BITS((__HANDLE__)->p_instance->INTSTAT, (__INTERRUPT__)) == (__INTERRUPT__))
797
798
799 /** @brief Check whether the specified QSPI flag is set or not.
800 * @param __HANDLE__ Specifies the QSPI Handle.
801 * @param __FLAG__ Specifies the flag to check.
802 * This parameter can be one of the following values:
803 * @arg @ref QSPI_FLAG_DCOL Data collision error flag
804 * @arg @ref QSPI_FLAG_TXE Transmission error flag
805 * @arg @ref QSPI_FLAG_RFF Rx FIFO full flag
806 * @arg @ref QSPI_FLAG_RFNE Rx FIFO not empty flag
807 * @arg @ref QSPI_FLAG_TFE Tx FIFO empty flag
808 * @arg @ref QSPI_FLAG_TFNF Tx FIFO not full flag
809 * @arg @ref QSPI_FLAG_BUSY Busy flag
810 * @retval The new state of __FLAG__ (TRUE or FALSE).
811 */
812 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__)) != 0) ? SET : RESET)
813
814
815 /** @brief Clear the specified QSPI flag.
816 * @param __HANDLE__ Specifies the QSPI Handle.
817 * @param __FLAG__ Specifies the flag to clear.
818 * This parameter can be one of the following values:
819 * @arg @ref QSPI_FLAG_DCOL Data collision error flag
820 * @arg @ref QSPI_FLAG_TXE Transmission error flag
821 * @arg @ref QSPI_FLAG_RFF Rx FIFO full flag
822 * @arg @ref QSPI_FLAG_RFNE Rx FIFO not empty flag
823 * @arg @ref QSPI_FLAG_TFE Tx FIFO empty flag
824 * @arg @ref QSPI_FLAG_TFNF Tx FIFO not full flag
825 * @arg @ref QSPI_FLAG_BUSY Busy flag
826 * @retval None
827 */
828 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__))
829
830 /** @} */
831
832 /* Private macros ------------------------------------------------------------*/
833 /** @defgroup QSPI_Private_Macro QSPI Private Macros
834 * @{
835 */
836
837 /** @brief Check if QSPI Clock Prescaler is valid.
838 * @param __PRESCALER__ QSPI Clock Prescaler.
839 * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
840 */
841 #define IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
842
843
844 /** @brief Check if QSPI FIFO Threshold is valid.
845 * @param __THR__ QSPI FIFO Threshold.
846 * @retval SET (__THR__ is valid) or RESET (__THR__ is invalid)
847 */
848 #define IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= (QSPI_MAX_FIFO_DEPTH - 1)))
849
850 /** @brief Check if QSPI Clock Mode is valid.
851 * @param __CLKMODE__ QSPI Clock Mode.
852 * @retval SET (__CLKMODE__ is valid) or RESET (__CLKMODE__ is invalid)
853 */
854 #define IS_QSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
855 ((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
856 ((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
857 ((__CLKMODE__) == QSPI_CLOCK_MODE_3))
858
859 /** @brief Check if QSPI RX Sample Delay Value is valid.
860 * @param __DLY__ QSPI RX Sample Delay value
861 * @retval SET (__DLY__ is valid) or RESET (__DLY__ is invalid)
862 */
863 #define IS_QSPI_RX_SAMPLE_DLY(__DLY__) (((__DLY__) >= 0) && ((__DLY__) <= 7))
864
865
866 /** @brief Check if QSPI Instruction Size is valid.
867 * @param __INST_SIZE__ QSPI Instruction Size.
868 * @retval SET (__INST_SIZE__ is valid) or RESET (__INST_SIZE__ is invalid)
869 */
870 #define IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
871 ((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
872 ((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
873 ((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))
874
875 /** @brief Check if QSPI Address Size is valid.
876 * @param __ADDR_SIZE__ QSPI Address Size .
877 * @retval SET (__ADDR_SIZE__ is valid) or RESET (__ADDR_SIZE__ is invalid)
878 */
879 #define IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
880 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
881 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
882 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
883 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
884 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
885 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
886 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
887 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))
888
889 /** @brief Check if QSPI Dummy Cycle is valid.
890 * @param __DCY__ QSPI Dummy Cycle.
891 * @retval SET (__DCY__ is valid) or RESET (__DCY__ is invalid)
892 */
893 #define IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
894
895 /** @brief Check if QSPI Instruction and Address Mode is valid.
896 * @param __MODE__ QSPI Instruction and Address Mode.
897 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
898 */
899 #define IS_QSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
900 ((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
901 ((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))
902
903 /** @brief Check if QSPI Data Mode is valid.
904 * @param __MODE__ QSPI Data Mode.
905 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
906 */
907 #define IS_QSPI_DATA_MODE(__MODE__) (((__MODE__) == QSPI_DATA_MODE_SPI) || \
908 ((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
909 ((__MODE__) == QSPI_DATA_MODE_QUADSPI))
910
911
912 /** @brief Check if QSPI Data Size is supported currently.
913 * @param __SIZE__ QSPI Data Size.
914 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
915 */
916 #define IS_QSPI_SUPPORTED_DATA_SIZE(__SIZE__) (((__SIZE__) == QSPI_DATASIZE_08_BITS) || \
917 ((__SIZE__) == QSPI_DATASIZE_16_BITS) || \
918 ((__SIZE__) == QSPI_DATASIZE_32_BITS))
919
920 /** @} */
921
922
923
924 /** @defgroup QSPI_XIP_Private_Macro QSPI-XIP Private Macros
925 * @{
926 */
927
928 /** @brief Check if QSPI.XIP SIOO Mode is valid.
929 * @param _SIOO_ QSPI.XIP Data Mode.
930 * @retval SET (_SIOO_ is valid) or RESET (_SIOO_ is invalid)
931 */
932 #define IS_QSPI_CONC_XIP_SIOO_MODE(_SIOO_) ( (QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS == (_SIOO_)) || \
933 (QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS == (_SIOO_)) )
934
935 /** @brief Check if QSPI.XIP DFS Value is valid.
936 * @param _DFS_ QSPI.XIP DFS Value
937 * @retval SET (_DFS_ is valid) or RESET (_DFS_ is invalid)
938 */
939 #define IS_QSPI_CONC_XIP_DFS(_DFS_) ( (QSPI_CONCURRENT_XIP_DFS_BYTE == (_DFS_)) || \
940 (QSPI_CONCURRENT_XIP_DFS_HALFWORD == (_DFS_)) || \
941 (QSPI_CONCURRENT_XIP_DFS_WORD == (_DFS_)) )
942
943 /** @brief Check if QSPI.XIP DFS_HC Switch Value is valid.
944 * @param _HC_EN_ QSPI.XIP DFS Hardcode Switch.
945 * @retval SET (_HC_EN_ is valid) or RESET (_HC_EN_ is invalid)
946 */
947 #define IS_QSPI_CONC_XIP_DFS_HC_EN(_HC_EN_) ( (QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE == (_HC_EN_)) || \
948 (QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE == (_HC_EN_)) )
949
950 /** @brief Check if QSPI.XIP inst Switch is valid.
951 * @param _INST_EN_ QSPI.XIP inst en/dis.
952 * @retval SET (_INST_EN_ is valid) or RESET (_INST_EN_ is invalid)
953 */
954 #define IS_QSPI_CONC_XIP_INST_EN(_INST_EN_) ( (QSPI_CONCURRENT_XIP_INST_ENABLE == (_INST_EN_)) || \
955 (QSPI_CONCURRENT_XIP_INST_DISABLE == (_INST_EN_)) )
956
957 /** @brief Check if QSPI.XIP inst size is valid.
958 * @param _INST_SIZE_ QSPI.XIP inst size.
959 * @retval SET (_INST_SIZE_ is valid) or RESET (_INST_SIZE_ is invalid)
960 */
961 #define IS_QSPI_CONC_XIP_INST_SIZE(_INST_SIZE_) ( (QSPI_CONCURRENT_XIP_INSTSIZE_0BIT == (_INST_SIZE_) ) || \
962 (QSPI_CONCURRENT_XIP_INSTSIZE_4BIT == (_INST_SIZE_) ) || \
963 (QSPI_CONCURRENT_XIP_INSTSIZE_8BIT == (_INST_SIZE_) ) || \
964 (QSPI_CONCURRENT_XIP_INSTSIZE_16BIT == (_INST_SIZE_) ) )
965
966 /** @brief Check if QSPI.XIP inst is valid.
967 * @param _INST_ QSPI.XIP inst.
968 * @retval SET (_INST_ is valid) or RESET (_INST_ is invalid)
969 */
970 #define IS_QSPI_CONC_XIP_INST(_INST_) ((_INST_) <= 0xFFFF )
971
972 /** @brief Check if QSPI.XIP Address Size is valid.
973 * @param _ADDR_SIZE_ QSPI.XIP Address Size.
974 * @retval SET (_ADDR_SIZE_ is valid) or RESET (_ADDR_SIZE_ is invalid)
975 */
976 #define IS_QSPI_CONC_XIP_ADDR_SIZE(_ADDR_SIZE_) ( (QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT == (_ADDR_SIZE_) ) || \
977 (QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT == (_ADDR_SIZE_) ) || \
978 (QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT == (_ADDR_SIZE_) ) || \
979 (QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT == (_ADDR_SIZE_) ) || \
980 (QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT == (_ADDR_SIZE_) ) || \
981 (QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT == (_ADDR_SIZE_) ) || \
982 (QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT == (_ADDR_SIZE_) ) || \
983 (QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT == (_ADDR_SIZE_) ) || \
984 (QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT == (_ADDR_SIZE_) ) || \
985 (QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT == (_ADDR_SIZE_) ) || \
986 (QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT == (_ADDR_SIZE_) ) || \
987 (QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT == (_ADDR_SIZE_) ) || \
988 (QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT == (_ADDR_SIZE_) ) || \
989 (QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT == (_ADDR_SIZE_) ) || \
990 (QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT == (_ADDR_SIZE_) ) || \
991 (QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT == (_ADDR_SIZE_) ) )
992
993 /** @brief Check if QSPI.XIP Addr Xfer format is valid.
994 * @param _FORMAT_ QSPI.XIP Addr Xfer format.
995 * @retval SET (_FORMAT_ is valid) or RESET (_FORMAT_ is invalid)
996 */
997 #define IS_QSPI_CONC_INST_ADDR_XFER_FORMAT(_FORMAT_) ( (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI == (_FORMAT_)) || \
998 (QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF == (_FORMAT_)) || \
999 (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF == (_FORMAT_)) )
1000
1001 /** @brief Check if QSPI.XIP Mode bits Switch is valid.
1002 * @param _MD_EN_ QSPI.XIP Mode bits Switch.
1003 * @retval SET (_MD_EN_ is valid) or RESET (_MD_EN_ is invalid)
1004 */
1005 #define IS_QSPI_CONC_XIP_MODE_BITS_EN(_MD_EN_) ( (QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE == (_MD_EN_) ) || \
1006 (QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE == (_MD_EN_) ))
1007
1008 /** @brief Check if QSPI.XIP Mode Bits size is valid.
1009 * @param _MD_SIZE_ QSPI.XIP Mode Bits size.
1010 * @retval SET (_MD_SIZE_ is valid) or RESET (_MD_SIZE_ is invalid)
1011 */
1012 #define IS_QSPI_CONC_XIP_MODE_BITS_SIZE(_MD_SIZE_) ( (QSPI_CONCURRENT_XIP_MBL_2 == (_MD_SIZE_)) || \
1013 (QSPI_CONCURRENT_XIP_MBL_4 == (_MD_SIZE_)) || \
1014 (QSPI_CONCURRENT_XIP_MBL_8 == (_MD_SIZE_)) || \
1015 (QSPI_CONCURRENT_XIP_MBL_16 == (_MD_SIZE_)) )
1016
1017 /** @brief Check if QSPI.XIP Mode Bits is valid.
1018 * @param _MD_BITS_ QSPI.XIP Mode Bits.
1019 * @retval SET (_MD_BITS_ is valid) or RESET (_MD_BITS_ is invalid)
1020 */
1021 #define IS_QSPI_CONC_XIP_MODE_BITS(_MD_BITS_) ( (_MD_BITS_) <= 0xFFFF)
1022
1023 /** @brief Check if QSPI.XIP dummy cycles is valid.
1024 * @param __DCY__ QSPI.XIPdummy cycles.
1025 * @retval SET (__DCY__ is valid) or RESET (__DCY__ is invalid)
1026 */
1027 #define IS_QSPI_CONC_XIP_DUMMY_CYCLES(__DCY__) ( (__DCY__) <= 31)
1028
1029 /** @brief Check if QSPI.XIP frame format is valid.
1030 * @param _XIP_FRF_ QSPI.XIP frame format.
1031 * @retval SET (_XIP_FRF_ is valid) or RESET (_XIP_FRF_ is invalid)
1032 */
1033 #define IS_QSPI_CONC_XIP_DATA_FRF(_XIP_FRF_) ( (QSPI_CONCURRENT_XIP_FRF_DUAL_SPI == (_XIP_FRF_)) || \
1034 (QSPI_CONCURRENT_XIP_FRF_QUAD_SPI == (_XIP_FRF_)) )
1035
1036 /** @brief Check if QSPI.XIP prefetch switch is valid.
1037 * @param _PREFETCH_EN_ QSPI.XIP prefetch switch.
1038 * @retval SET (_PREFETCH_EN_ is valid) or RESET (_PREFETCH_EN_ is invalid)
1039 */
1040 #define IS_QSPI_CONC_XIP_PREFETCH_EN(_PREFETCH_EN_) ( (QSPI_CONCURRENT_XIP_PREFETCH_ENABLE == (_PREFETCH_EN_)) || \
1041 (QSPI_CONCURRENT_XIP_PREFETCH_DISABLE == (_PREFETCH_EN_)) )
1042
1043 /** @brief Check if QSPI.XIP cont xfer switch is valid.
1044 * @param _CONT_XFER_EN_ QSPI.XIP cont xfer switch.
1045 * @retval SET (_CONT_XFER_EN_ is valid) or RESET (_CONT_XFER_EN_ is invalid)
1046 */
1047 #define IS_QSPI_CONC_XIP_CONT_XFER_EN(_CONT_XFER_EN_) ( (QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE == (_CONT_XFER_EN_)) || \
1048 (QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE == (_CONT_XFER_EN_)) )
1049
1050 /** @brief Check if QSPI.XIP timeout count of cont xfer is valid.
1051 * @param _TOC_ QSPI.XIP timeout count of cont xfer.
1052 * @retval SET (_TOC_ is valid) or RESET (_TOC_ is invalid)
1053 */
1054 #define IS_QSPI_CONC_XIP_CONT_XFER_TOC(_TOC_) ( (_TOC_) <= 0xFF)
1055
1056 /** @brief Check if QSPI.XIP Data endian Mode is valid.
1057 * @param _MODE_ QSPI.XIP Data endian Mode.
1058 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
1059 */
1060 #define IS_QSPI_CONC_XIP_ENDIAN_MODE(_MODE_) ( (QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 == (_MODE_)) || \
1061 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 == (_MODE_)) || \
1062 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 == (_MODE_)) )
1063 /** @} */
1064
1065 /** @} */
1066
1067 /* Exported functions --------------------------------------------------------*/
1068 /** @addtogroup HAL_QSPI_DRIVER_FUNCTIONS Functions
1069 * @{
1070 */
1071
1072 /** @defgroup QSPI_Exported_Functions_Group1 Initialization and de-initialization functions
1073 * @brief Initialization and de-initialization functions
1074 *
1075 @verbatim
1076 ===============================================================================
1077 ##### Initialization and de-initialization functions #####
1078 ===============================================================================
1079 [..] This subsection provides a set of functions allowing to initialize and
1080 de-initialize the QSPIx peripheral:
1081
1082 (+) User must implement hal_qspi_msp_init() function in which he configures
1083 all related peripherals resources (GPIO, DMA, IT and NVIC ).
1084
1085 (+) Call the function hal_qspi_init() to configure the selected device with
1086 the selected configuration:
1087 (++) Clock Prescaler
1088 (++) Clock Mode
1089
1090 (+) Call the function hal_qspi_deinit() to restore the default configuration
1091 of the selected QSPIx peripheral.
1092
1093 @endverbatim
1094 * @{
1095 */
1096
1097 /**
1098 ****************************************************************************************
1099 * @brief Initialize the QSPI according to the specified parameters
1100 * in the qspi_init_t and initialize the associated handle.
1101 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1102 * @retval ::HAL_OK: Operation is OK.
1103 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1104 * @retval ::HAL_BUSY: Driver is busy.
1105 * @retval ::HAL_TIMEOUT: Timeout occurred.
1106 ****************************************************************************************
1107 */
1108 hal_status_t hal_qspi_init(qspi_handle_t *p_qspi);
1109
1110 /**
1111 ****************************************************************************************
1112 * @brief De-initialize the QSPI peripheral.
1113 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1114 * @retval ::HAL_OK: Operation is OK.
1115 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1116 * @retval ::HAL_BUSY: Driver is busy.
1117 * @retval ::HAL_TIMEOUT: Timeout occurred.
1118 ****************************************************************************************
1119 */
1120 hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi);
1121
1122 /**
1123 ****************************************************************************************
1124 * @brief Initialize the QSPI MSP.
1125 * @note This function should not be modified. When the callback is needed,
1126 * the hal_qspi_msp_deinit can be implemented in the user file.
1127 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1128 ****************************************************************************************
1129 */
1130 void hal_qspi_msp_init(qspi_handle_t *p_qspi);
1131
1132 /**
1133 ****************************************************************************************
1134 * @brief De-initialize the QSPI MSP.
1135 * @note This function should not be modified. When the callback is needed,
1136 * the hal_qspi_msp_deinit can be implemented in the user file.
1137 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1138 ****************************************************************************************
1139 */
1140 void hal_qspi_msp_deinit(qspi_handle_t *p_qspi);
1141
1142 /** @} */
1143
1144 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
1145 * @brief Data transfers functions
1146 *
1147 @verbatim
1148 ==============================================================================
1149 ##### IO operation functions #####
1150 ===============================================================================
1151 [..]
1152 This subsection provides a set of functions allowing to manage the QSPI
1153 data transfers.
1154
1155 [..] The QSPI supports master and slave mode:
1156
1157 (#) There are two modes of transfer:
1158 (++) Blocking mode: The communication is performed in polling mode.
1159 The HAL status of all data processing is returned by the same function
1160 after finishing transfer.
1161 (++) No-Blocking mode: The communication is performed using Interrupts.
1162 or DMA, These APIs return the HAL status.
1163 The end of the data processing will be indicated through the
1164 dedicated QSPI IRQ when using Interrupt mode or the DMA IRQ when
1165 using DMA mode.
1166 The hal_qspi_tx_cplt_callback(), hal_qspi_rx_cplt_callback() and hal_qspi_txrx_cplt_callback() user callbacks
1167 will be executed respectively at the end of the transmit or Receive process.
1168 The hal_qspi_error_callback() user callback will be executed when a communication error is detected
1169
1170 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
1171 exist for 1 Line (simplex) and 2 Lines (full duplex) modes.
1172
1173 @endverbatim
1174 * @{
1175 */
1176 /**
1177 ****************************************************************************************
1178 * @brief Configure the Memory Mapped mode. Called after hal_qspi_init(...)
1179 * @note This function is used only in Memory mapped Mode
1180 * @param[in] p_qspi: Pointer to a QSPI handle
1181 * @param[in] mmap_cmd: Structure that contains the memorymapped read command configuration information.
1182 * @param[in] mmap_wr_cmd: Structure that contains the memorymapped write command configuration information.
1183 * @retval hal status
1184 ****************************************************************************************
1185 */
1186 hal_status_t hal_qspi_memorymapped(qspi_handle_t *p_qspi, qspi_memorymapped_t * mmap_cmd, qspi_memorymapped_write_t * mmap_wr_cmd);
1187
1188 /**
1189 * @brief Active the memory mapped mode from Ready state. users must make sure parameters of mmaped mode hava been set correctly
1190 * @param p_qspi: QSPI handle
1191 * @param is_sioo_mode (TRUE/FALSE)- specifies SIOO Mode, must match to Slave device's inst
1192 * @note 1) This function is used only in Memory mapped Mode
1193 * 2) User must config the registers correcly firstly
1194 * 3) It requires that slave device's inst supports the SIOO Mode
1195 * @retval hal status
1196 */
1197 hal_status_t hal_qspi_memorymapped_active(qspi_handle_t *p_qspi, uint32_t is_sioo_mode);
1198
1199 /**
1200 * @brief Deactive the memory mapped mode to Ready state
1201 * it's recommended to use with hal_qspi_memorymapped_active to switch mode quickly
1202 * @param p_qspi: QSPI handle
1203 * @note This function is used only in Memory mapped Mode
1204 * @retval hal status
1205 */
1206 hal_status_t hal_qspi_memorymapped_deactive(qspi_handle_t *p_qspi);
1207
1208 /**
1209 * @brief Check whether the memory mapped mode is Actived
1210 * @param p_qspi: QSPI handle
1211 * @note This function is used only in Memory mapped Mode
1212 * @retval 1 - actived; 0 - not actived
1213 */
1214 hal_memorymapped_status_t hal_qspi_memorymapped_is_actived(qspi_handle_t *p_qspi);
1215
1216
1217 /**
1218 * @brief Used to update memorymapped any parameter quickly
1219 * @param p_qspi: QSPI handle
1220 * @param mmap_set: Pointer to k:v pair of qspi_memorymapped_set_t
1221 * @param count: Amount of mmap_set's element
1222 * @note This function is used only in Memory mapped Mode
1223 * @retval hal status
1224 */
1225 hal_status_t hal_qspi_memorymapped_update(qspi_handle_t *p_qspi, qspi_memorymapped_set_t * mmap_set, uint32_t count);
1226 /**
1227 ****************************************************************************************
1228 * @brief Transmit an amount of data with the specified instruction and address in blocking mode.
1229 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1230 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1231 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1232 * @param[in] p_data: Pointer to data buffer
1233 * @param[in] timeout: Timeout duration
1234 * @retval ::HAL_OK: Operation is OK.
1235 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1236 * @retval ::HAL_BUSY: Driver is busy.
1237 * @retval ::HAL_TIMEOUT: Timeout occurred.
1238 ****************************************************************************************
1239 */
1240 hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
1241
1242 /**
1243 ****************************************************************************************
1244 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
1245 * @note This function is used only in Indirect Read Mode.
1246 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1247 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1248 * @param[out] p_data: Pointer to data buffer
1249 * @param[in] timeout: Timeout duration
1250 * @retval ::HAL_OK: Operation is OK.
1251 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1252 * @retval ::HAL_BUSY: Driver is busy.
1253 * @retval ::HAL_TIMEOUT: Timeout occurred.
1254 ****************************************************************************************
1255 */
1256 hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
1257
1258 /**
1259 ****************************************************************************************
1260 * @brief Transmit only instruction in blocking mode.
1261 * @note This function is used only in Indirect Write Mode.
1262 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1263 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1264 * @param[in] timeout: Timeout duration
1265 * @retval ::HAL_OK: Operation is OK.
1266 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1267 * @retval ::HAL_BUSY: Driver is busy.
1268 * @retval ::HAL_TIMEOUT: Timeout occurred.
1269 ****************************************************************************************
1270 */
1271 hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout);
1272
1273 /**
1274 ****************************************************************************************
1275 * @brief Transmit an amount of data in blocking mode with standard SPI.
1276 * @note This function is used only in Indirect Write Mode.
1277 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1278 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1279 * QSPI_DATA_MODE_DUALSPI
1280 * QSPI_DATA_MODE_QUADSPI
1281 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1282 * QSPI_DATASIZE_16_BITS
1283 * QSPI_DATASIZE_32_BITS
1284 * @param[in] p_data: Pointer to data buffer
1285 * @param[in] data_length: Amount of data to be sent in bytes
1286 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1287 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1288 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1289 * @param[in] timeout: Timeout duration
1290 * @retval ::HAL_OK: Operation is OK.
1291 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1292 * @retval ::HAL_BUSY: Driver is busy.
1293 * @retval ::HAL_TIMEOUT: Timeout occurred.
1294 ****************************************************************************************
1295 */
1296 hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length, uint32_t timeout);
1297
1298 /**
1299 ****************************************************************************************
1300 * @brief Receive an amount of data in blocking mode with standard SPI.
1301 * @note This function is used only in Indirect Read Mode.
1302 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1303 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1304 * QSPI_DATA_MODE_DUALSPI
1305 * QSPI_DATA_MODE_QUADSPI
1306 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1307 * QSPI_DATASIZE_16_BITS
1308 * QSPI_DATASIZE_32_BITS
1309 * @param[in] p_data: Pointer to data buffer
1310 * @param[in] length: Amount of data to be sent in bytes
1311 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1312 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1313 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1314 * @param[in] timeout: Timeout duration
1315 * @retval ::HAL_OK: Operation is OK.
1316 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1317 * @retval ::HAL_BUSY: Driver is busy.
1318 * @retval ::HAL_TIMEOUT: Timeout occurred.
1319 ****************************************************************************************
1320 */
1321 hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length, uint32_t timeout);
1322
1323 /**
1324 ****************************************************************************************
1325 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with Interrupt.
1326 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1327 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1328 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1329 * @param[in] p_data: Pointer to data buffer
1330 * @retval ::HAL_OK: Operation is OK.
1331 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1332 * @retval ::HAL_BUSY: Driver is busy.
1333 * @retval ::HAL_TIMEOUT: Timeout occurred.
1334 ****************************************************************************************
1335 */
1336 hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1337
1338 /**
1339 ****************************************************************************************
1340 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
1341 * @note This function is used only in Indirect Read Mode.
1342 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1343 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1344 * @param[out] p_data: Pointer to data buffer
1345 * @retval ::HAL_OK: Operation is OK.
1346 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1347 * @retval ::HAL_BUSY: Driver is busy.
1348 * @retval ::HAL_TIMEOUT: Timeout occurred.
1349 ****************************************************************************************
1350 */
1351 hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1352
1353 /**
1354 ****************************************************************************************
1355 * @brief Transmit instruction in non-blocking mode with Interrupt.
1356 * @note This function is used only in Indirect Write Mode.
1357 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1358 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1359 * @retval ::HAL_OK: Operation is OK.
1360 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1361 * @retval ::HAL_BUSY: Driver is busy.
1362 * @retval ::HAL_TIMEOUT: Timeout occurred.
1363 ****************************************************************************************
1364 */
1365 hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
1366
1367 /**
1368 ****************************************************************************************
1369 * @brief Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
1370 * @note This function is used only in Indirect Write Mode.
1371 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1372 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1373 * QSPI_DATA_MODE_DUALSPI
1374 * QSPI_DATA_MODE_QUADSPI
1375 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1376 * QSPI_DATASIZE_16_BITS
1377 * QSPI_DATASIZE_32_BITS
1378 * @param[in] p_data: Pointer to data buffer
1379 * @param[in] data_length: Amount of data to be sent in bytes
1380 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1381 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1382 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1383 * @retval ::HAL_OK: Operation is OK.
1384 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1385 * @retval ::HAL_BUSY: Driver is busy.
1386 * @retval ::HAL_TIMEOUT: Timeout occurred.
1387 ****************************************************************************************
1388 */
1389 hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length);
1390
1391 /**
1392 ****************************************************************************************
1393 * @brief Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
1394 * @note This function is used only in Indirect Read Mode.
1395 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1396 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1397 * QSPI_DATA_MODE_DUALSPI
1398 * QSPI_DATA_MODE_QUADSPI
1399 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1400 * QSPI_DATASIZE_16_BITS
1401 * QSPI_DATASIZE_32_BITS
1402 * @param[in] p_data: Pointer to data buffer
1403 * @param[in] length: Amount of data to be sent in bytes
1404 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1405 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1406 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1407 * @retval ::HAL_OK: Operation is OK.
1408 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1409 * @retval ::HAL_BUSY: Driver is busy.
1410 * @retval ::HAL_TIMEOUT: Timeout occurred.
1411 ****************************************************************************************
1412 */
1413 hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1414
1415 /**
1416 ****************************************************************************************
1417 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
1418 * @note This function is used only in Indirect Write Mode. Dummy cycles in command will be ignored.
1419 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1420 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1421 * @param[in] p_data: Pointer to data buffer
1422 * @retval ::HAL_OK: Operation is OK.
1423 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1424 * @retval ::HAL_BUSY: Driver is busy.
1425 * @retval ::HAL_TIMEOUT: Timeout occurred.
1426 ****************************************************************************************
1427 */
1428 hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1429
1430 /**
1431 ****************************************************************************************
1432 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with DMA .
1433 * @note This function is used only in Indirect Read Mode.
1434 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1435 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1436 * @param[out] p_data: Pointer to data buffer
1437 * @retval ::HAL_OK: Operation is OK.
1438 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1439 * @retval ::HAL_BUSY: Driver is busy.
1440 * @retval ::HAL_TIMEOUT: Timeout occurred.
1441 ****************************************************************************************
1442 */
1443 hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
1444
1445 /**
1446 ****************************************************************************************
1447 * @brief Transmit instruction in non-blocking mode with DMA.
1448 * @note This function is used only in Indirect Write Mode.
1449 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1450 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1451 * @retval ::HAL_OK: Operation is OK.
1452 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1453 * @retval ::HAL_BUSY: Driver is busy.
1454 * @retval ::HAL_TIMEOUT: Timeout occurred.
1455 ****************************************************************************************
1456 */
1457 hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
1458
1459 /**
1460 ****************************************************************************************
1461 * @brief Transmit an amount of data in non-blocking mode at standard SPI with DMA.
1462 * @note This function is used only in Indirect Write Mode.
1463 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1464 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1465 * QSPI_DATA_MODE_DUALSPI
1466 * QSPI_DATA_MODE_QUADSPI
1467 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1468 * QSPI_DATASIZE_16_BITS
1469 * QSPI_DATASIZE_32_BITS
1470 * @param[in] p_data: Pointer to data buffer
1471 * @param[in] length: Amount of data to be sent in bytes
1472 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1473 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1474 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1475 * @retval ::HAL_OK: Operation is OK.
1476 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1477 * @retval ::HAL_BUSY: Driver is busy.
1478 * @retval ::HAL_TIMEOUT: Timeout occurred.
1479 ****************************************************************************************
1480 */
1481 hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1482
1483 /**
1484 ****************************************************************************************
1485 * @brief Receive an amount of data in non-blocking mode at standard SPI with DMA.
1486 * @note This function is used only in Indirect Read Mode.
1487 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1488 * @param[in] data_mode : @ref QSPI_DATA_MODE_SPI
1489 * QSPI_DATA_MODE_DUALSPI
1490 * QSPI_DATA_MODE_QUADSPI
1491 * @param[in] data_size : @ref QSPI_DATASIZE_08_BITS
1492 * QSPI_DATASIZE_16_BITS
1493 * QSPI_DATASIZE_32_BITS
1494 * @param[in] p_data: Pointer to data buffer
1495 * @param[in] length: Amount of data to be sent in bytes
1496 * 1. if data_mode equals QSPI_DATA_MODE_SPI : length must >= 2 bytes
1497 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : length must >= 4 bytes and be multiple of HALFWORD
1498 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : length must >= 8 bytes and be multiple of WORD
1499 * @retval ::HAL_OK: Operation is OK.
1500 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1501 * @retval ::HAL_BUSY: Driver is busy.
1502 * @retval ::HAL_TIMEOUT: Timeout occurred.
1503 ****************************************************************************************
1504 */
1505 hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length);
1506
1507
1508 /**
1509 ****************************************************************************************
1510 * @brief Transmit Multi-Block of data with the specified instruction and address in non-blocking mode with DMA Linked List Block.
1511 * @note This function is used only in Indirect Write Mode.
1512 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1513 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1514 * @param[in] p_llp_config: Pointer to Linked List Block
1515 * @retval ::HAL_OK: Operation is OK.
1516 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1517 * @retval ::HAL_BUSY: Driver is busy.
1518 * @retval ::HAL_TIMEOUT: Timeout occurred.
1519 ****************************************************************************************
1520 */
1521 hal_status_t hal_qspi_command_transmit_dma_llp(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_llp_config_t * p_llp_config);
1522
1523 /**
1524 ****************************************************************************************
1525 * @brief Transmit Multi-Block of data without instruction and address in non-blocking mode with DMA Linked List Block.
1526 * @note This function is used only in Indirect Write Mode.
1527 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1528 * @param[in] p_llp_config: Pointer to Linked List Block
1529 * @param[in] data_mode : @ref QSPI_Data_Mode
1530 * @param[in] data_length: Total data length of all blocks, in terms of bytes.
1531 * 1. if data_mode equals QSPI_DATA_MODE_SPI : data_length must >= 2 bytes
1532 * 2. if data_mode equals QSPI_DATA_MODE_DUALSPI : data_length must >= 4 bytes and be multiple of HALFWORD
1533 * 3. if data_mode equals QSPI_DATA_MODE_QUADSPI : data_length must >= 8 bytes and be multiple of WORD
1534 * @param[in] clock_stretch_enable: Whether enable the clock stretch feature
1535 * @retval ::HAL_OK: Operation is OK.
1536 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1537 * @retval ::HAL_BUSY: Driver is busy.
1538 * @retval ::HAL_TIMEOUT: Timeout occurred.
1539 ****************************************************************************************
1540 */
1541 hal_status_t hal_qspi_transmit_dma_llp(qspi_handle_t *p_qspi, dma_llp_config_t * p_llp_config, uint32_t data_mode, uint32_t data_length, uint32_t clock_stretch_enable);
1542
1543 /**
1544 ****************************************************************************************
1545 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA Gather.
1546 * @note This function is used only in Indirect Write Mode.
1547 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1548 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1549 * @param[in] p_gather_config: Pointer to DMA Gather Configure
1550 * @param[in] p_data: Pointer to data buffer to be sent
1551 * @retval ::HAL_OK: Operation is OK.
1552 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1553 * @retval ::HAL_BUSY: Driver is busy.
1554 * @retval ::HAL_TIMEOUT: Timeout occurred.
1555 ****************************************************************************************
1556 */
1557 hal_status_t hal_qspi_command_transmit_dma_gather(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_gather_config_t * p_gather_config, uint8_t *p_data);
1558
1559
1560 /**
1561 ****************************************************************************************
1562 * @brief Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA LLP.
1563 * And In Each Block, xfered specified by gather, every data block has the same gather configuration
1564 * @note This function is used only in Indirect Write Mode.
1565 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1566 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1567 * @param[in] p_llp_config: Pointer to DMA LLP Configure
1568 * @param[in] p_gather_config: Pointer to DMA Gather Configure
1569 *
1570 * @retval ::HAL_OK: Operation is OK.
1571 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1572 * @retval ::HAL_BUSY: Driver is busy.
1573 * @retval ::HAL_TIMEOUT: Timeout occurred.
1574 ****************************************************************************************
1575 */
1576 hal_status_t hal_qspi_command_transmit_dma_llp_gather(qspi_handle_t *p_qspi, qspi_command_t * p_cmd, dma_llp_config_t * p_llp_config, dma_gather_config_t * p_gather_config);
1577
1578
1579 /**
1580 ****************************************************************************************
1581 * @brief Receive an amount of data with the specified instruction and address in non-blocking mode with DMA Scatter.
1582 * @note This function is used only in Indirect Write Mode.
1583 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1584 * @param[in] p_cmd: Pointer to a qspi_command_t structure that contains the instruction and address for data transfer.
1585 * @param[in] p_data: Pointer to data buffer to be sent
1586 * @param[in] sct_interval: Specifies the destination address increment/decrement in multiples of data_size in qspi_command_t on a scatter boundary
1587 * @param[in] sct_count: Specifies the number of contiguous destination transfers of data_size in qspi_command_t between successive scatter intervals
1588 * @retval ::HAL_OK: Operation is OK.
1589 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1590 * @retval ::HAL_BUSY: Driver is busy.
1591 * @retval ::HAL_TIMEOUT: Timeout occurred.
1592 ****************************************************************************************
1593 */
1594 hal_status_t hal_qspi_command_receive_dma_scatter(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t sct_interval, uint32_t sct_count);
1595
1596
1597 /**
1598 ****************************************************************************************
1599 * @brief : Used to write PSRAM in high speed mode with dma LLP
1600 *
1601 * @note : THIS IS A RESTRICTED OR LIMITED USED FUNCTION !
1602 *
1603 * It requires the following usage Conditions :
1604 *
1605 * 1. Just USED to WRITE PSRAM, And The Length Of Block MUST be under the control of tCEM of PSRAM
1606 * 2. This Function can be USED Just When QSPI Clock Frequency is half Of System Frequency. And MUST config the prescaler firstly before calling this
1607 * 3. This Function Just Supports QUAD WRITE Command Of PSRAM in Quad Mode, such as the 0x02/0x38 QPI WRITE CMD in IPUS or AP-MEMORY
1608 * 4. Following the third point, The instruction size must be 8-bits, The address size must be 24-bits
1609 * 5. This Function Just Supports Rectangular data block, Data length in each data block are the same
1610 * 6. This Function Supports TWO DATA Block Mode : QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 (Loop Mode); QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 (Crossed Mode)
1611 * 7. When in QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 Mode, it supports the DATA_SIZE as 8/16/32bits;
1612 * When in QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 Mode, it just supports the DATA_SIZE as 8/16bits, not Support 32bits
1613 * 8. It Just support Single BURST for SRC&DST when configuring the DMA xfer
1614 * 9. Attention The Data Order.
1615 * When Data_Size is 8 Bits : INST -> ADDR-High -> ADDR-Middle -> ADDR-Low -> Byte 0 -> Byte 1 -> Byte 2 -> ...
1616 * When Data_Size is 16 Bits : ADDR-High -> INST -> ADDR-Low -> ADDR-Middle -> Short0.1 -> Short0.0 -> Short1.1 -> Short1.0 -> ...
1617 * When Data_Size is 32 Bits : ADDR-Low -> ADDR-Middle -> ADDR-High -> INST -> Word 0.3 -> Word 0.2 -> Word 0.1 -> Word 0.0 -> ...
1618 *
1619 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1620 * @param[in] p_cmd : Pointer to a psram command configuration.
1621 * @param[in] p_llp_config: Pointer to Linked List Block
1622 * @retval ::HAL_OK: Operation is OK.
1623 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1624 * @retval ::HAL_BUSY: Driver is busy.
1625 * @retval ::HAL_TIMEOUT: Timeout occurred.
1626 ****************************************************************************************
1627 */
1628 hal_status_t hal_qspi_psram_transmit_dma_llp_limited(qspi_handle_t *p_qspi, qspi_psram_command_t * p_cmd, dma_llp_config_t * p_llp_config);
1629
1630
1631 /**
1632 ****************************************************************************************
1633 * @brief Abort the current transmission.
1634 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1635 * @retval ::HAL_OK: Operation is OK.
1636 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1637 * @retval ::HAL_BUSY: Driver is busy.
1638 * @retval ::HAL_TIMEOUT: Timeout occurred.
1639 ****************************************************************************************
1640 */
1641 hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi);
1642
1643 /**
1644 ****************************************************************************************
1645 * @brief Abort the current transmission (non-blocking function)
1646 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1647 * @retval ::HAL_OK: Operation is OK.
1648 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1649 * @retval ::HAL_BUSY: Driver is busy.
1650 * @retval ::HAL_TIMEOUT: Timeout occurred.
1651 ****************************************************************************************
1652 */
1653 hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi);
1654
1655 /** @} */
1656
1657 /** @addtogroup QSPI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
1658 * @brief IRQ Handler and Callbacks functions
1659 * @{
1660 */
1661
1662 /**
1663 ****************************************************************************************
1664 * @brief Handle QSPI interrupt request.
1665 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1666 ****************************************************************************************
1667 */
1668 void hal_qspi_irq_handler(qspi_handle_t *p_qspi);
1669
1670 /**
1671 ****************************************************************************************
1672 * @brief Tx Transfer completed callback.
1673 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1674 ****************************************************************************************
1675 */
1676 void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi);
1677
1678 /**
1679 ****************************************************************************************
1680 * @brief Rx Transfer completed callback.
1681 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1682 ****************************************************************************************
1683 */
1684 void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi);
1685
1686 /**
1687 ****************************************************************************************
1688 * @brief QSPI error callback.
1689 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1690 ****************************************************************************************
1691 */
1692 void hal_qspi_error_callback(qspi_handle_t *p_qspi);
1693
1694 /**
1695 ****************************************************************************************
1696 * @brief QSPI Abort Complete callback.
1697 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1698 ****************************************************************************************
1699 */
1700 void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi);
1701
1702 /** @} */
1703
1704 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral State and Errors functions
1705 * @brief QSPI control functions
1706 *
1707 @verbatim
1708 ===============================================================================
1709 ##### Peripheral State and Errors functions #####
1710 ===============================================================================
1711 [..]
1712 This subsection provides a set of functions allowing to control the QSPI.
1713 (+) hal_qspi_get_state() API can be helpful to check in run-time the state of the QSPI peripheral.
1714 (+) hal_qspi_get_error() check in run-time Errors occurring during communication.
1715 (+) hal_qspi_set_timeout() set the timeout during internal process.
1716 @endverbatim
1717 * @{
1718 */
1719
1720 /**
1721 ****************************************************************************************
1722 * @brief Return the QSPI handle state.
1723 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1724 * @retval ::HAL_QSPI_STATE_RESET: Peripheral not initialized.
1725 * @retval ::HAL_QSPI_STATE_READY: Peripheral initialized and ready for use.
1726 * @retval ::HAL_QSPI_STATE_BUSY: Peripheral in indirect mode and busy.
1727 * @retval ::HAL_QSPI_STATE_BUSY_INDIRECT_TX: Peripheral in indirect mode with transmission ongoing.
1728 * @retval ::HAL_QSPI_STATE_BUSY_INDIRECT_RX: Peripheral in indirect mode with reception ongoing.
1729 * @retval ::HAL_QSPI_STATE_ABORT: Peripheral with abort request ongoing.
1730 * @retval ::HAL_QSPI_STATE_ERROR: Peripheral in error.
1731 ****************************************************************************************
1732 */
1733 hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi);
1734
1735 /**
1736 ****************************************************************************************
1737 * @brief Return the QSPI error code.
1738 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1739 * @return QSPI error code in bitmap format
1740 ****************************************************************************************
1741 */
1742 uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi);
1743
1744 /**
1745 ****************************************************************************************
1746 * @brief Set the QSPI cs setup & release time value.
1747 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1748 * @param[in] delay: delay clocks for cs setup & release, [0, 0x7]
1749 * @retval :: None.
1750 ****************************************************************************************
1751 */
1752 void hal_qspi_set_tcsu(qspi_handle_t *p_qspi, uint32_t delay);
1753
1754 /**
1755 ****************************************************************************************
1756 * @brief Set the QSPI internal process timeout value.
1757 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration information for the specified QSPI module.
1758 * @param[in] timeout: Internal process timeout value.
1759 * @retval :: None.
1760 ****************************************************************************************
1761 */
1762 void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout);
1763
1764 /**
1765 ****************************************************************************************
1766 * @brief Suspend some registers related to QSPI configuration before sleep.
1767 * @param[in] p_qspi: Pointer to a QSPIhandle which contains the configuration
1768 * information for the specified QSPI module.
1769 * @retval ::HAL_OK: Operation is OK.
1770 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1771 * @retval ::HAL_BUSY: Driver is busy.
1772 * @retval ::HAL_TIMEOUT: Timeout occurred.
1773 ****************************************************************************************
1774 */
1775 hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi);
1776
1777 /**
1778 ****************************************************************************************
1779 * @brief Restore some registers related to QSPI configuration after sleep.
1780 * This function must be used in conjunction with the hal_qspi_suspend_reg().
1781 * @param[in] p_qspi: Pointer to a QSPI handle which contains the configuration
1782 * information for the specified QSPI module.
1783 * @retval ::HAL_OK: Operation is OK.
1784 * @retval ::HAL_ERROR: Parameter error or operation not supported.
1785 * @retval ::HAL_BUSY: Driver is busy.
1786 * @retval ::HAL_TIMEOUT: Timeout occurred.
1787 ****************************************************************************************
1788 */
1789 hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi);
1790
1791 /** @} */
1792
1793 /** @} */
1794
1795 #ifdef __cplusplus
1796 }
1797 #endif
1798
1799 #endif /* __GR55xx_HAL_QSPI_H__ */
1800
1801 /** @} */
1802
1803 /** @} */
1804
1805 /** @} */
_qspi_memorymapped_t::x_endian_mode
uint32_t x_endian_mode
Definition: gr55xx_hal_qspi.h:283
_hal_qspi_callback::qspi_msp_deinit
void(* qspi_msp_deinit)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:363
_qspi_handle::tx_xfer_size
__IO uint32_t tx_xfer_size
Definition: gr55xx_hal_qspi.h:164
_qspi_command_t::instruction_size
uint32_t instruction_size
Definition: gr55xx_hal_qspi.h:207
_qspi_handle::timeout
uint32_t timeout
Definition: gr55xx_hal_qspi.h:186
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
qspi_memorymapped_idx_e
enum _qspi_memorymapped_idx_e qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
_qspi_memorymapped_t::x_instruction
uint32_t x_instruction
Definition: gr55xx_hal_qspi.h:250
_hal_qspi_callback::qspi_rx_cplt_callback
void(* qspi_rx_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:366
_qspi_memorymapped_t::x_dummy_cycles
uint32_t x_dummy_cycles
Definition: gr55xx_hal_qspi.h:268
_qspi_memorymapped_t::x_instruction_size
uint32_t x_instruction_size
Definition: gr55xx_hal_qspi.h:247
HAL_MMAPPED_STATE_ACTIVED
@ HAL_MMAPPED_STATE_ACTIVED
Definition: gr55xx_hal_qspi.h:95
hal_qspi_memorymapped_update
hal_status_t hal_qspi_memorymapped_update(qspi_handle_t *p_qspi, qspi_memorymapped_set_t *mmap_set, uint32_t count)
Used to update memorymapped any parameter quickly.
_qspi_command_t::data_size
uint32_t data_size
Definition: gr55xx_hal_qspi.h:216
_qspi_handle::p_instance
qspi_regs_t * p_instance
Definition: gr55xx_hal_qspi.h:158
_qspi_memorymapped_t::x_sioo_mode
uint32_t x_sioo_mode
Definition: gr55xx_hal_qspi.h:241
QSPI_MMAPED_IDX_CONT_XFER_TOC
@ QSPI_MMAPED_IDX_CONT_XFER_TOC
Definition: gr55xx_hal_qspi.h:117
HAL_QSPI_STATE_BUSY_MEM_MAPPED
@ HAL_QSPI_STATE_BUSY_MEM_MAPPED
Definition: gr55xx_hal_qspi.h:83
_qspi_memorymapped_set_t::mmap_key
qspi_memorymapped_idx_e mmap_key
Definition: gr55xx_hal_qspi.h:317
qspi_memorymapped_t
struct _qspi_memorymapped_t qspi_memorymapped_t
QSPI memory map Structure definition.
hal_qspi_receive
hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
_qspi_memorymapped_write_t::x_address_size
uint32_t x_address_size
Definition: gr55xx_hal_qspi.h:300
hal_qspi_command_receive
hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
_qspi_command_t::instruction_address_mode
uint32_t instruction_address_mode
Definition: gr55xx_hal_qspi.h:219
_qspi_memorymapped_write_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Definition: gr55xx_hal_qspi.h:303
HAL_QSPI_STATE_ABORT
@ HAL_QSPI_STATE_ABORT
Definition: gr55xx_hal_qspi.h:84
_qspi_command_t::length
uint32_t length
Definition: gr55xx_hal_qspi.h:225
QSPI_MMAPED_IDX_EDIAN_MODE
@ QSPI_MMAPED_IDX_EDIAN_MODE
Definition: gr55xx_hal_qspi.h:118
_qspi_handle::rx_xfer_size
__IO uint32_t rx_xfer_size
Definition: gr55xx_hal_qspi.h:170
_qspi_memorymapped_t::x_continous_xfer_en
uint32_t x_continous_xfer_en
Definition: gr55xx_hal_qspi.h:277
gr55xx_ll_qspi.h
Header file containing functions prototypes of QSPI LL library.
qspi_memorymapped_set_t
struct _qspi_memorymapped_set_t qspi_memorymapped_set_t
KEY:Value pair to set memorymapped parameter.
_qspi_handle::state
__IO hal_qspi_state_t state
Definition: gr55xx_hal_qspi.h:182
_hal_qspi_callback::qspi_error_callback
void(* qspi_error_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:364
_qspi_handle::rx_xfer_count
__IO uint32_t rx_xfer_count
Definition: gr55xx_hal_qspi.h:172
QSPI_MMAPED_IDX_ADDR_SIZE
@ QSPI_MMAPED_IDX_ADDR_SIZE
Definition: gr55xx_hal_qspi.h:108
hal_qspi_deinit
hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI peripheral.
hal_qspi_command_transmit_dma_llp_gather
hal_status_t hal_qspi_command_transmit_dma_llp_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config, dma_gather_config_t *p_gather_config)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA L...
_qspi_handle::p_tx_buffer
uint8_t * p_tx_buffer
Definition: gr55xx_hal_qspi.h:162
_qspi_init_t
QSPI init Structure definition.
Definition: gr55xx_hal_qspi.h:137
hal_qspi_msp_init
void hal_qspi_msp_init(qspi_handle_t *p_qspi)
Initialize the QSPI MSP.
_qspi_memorymapped_t::x_instruction_en
uint32_t x_instruction_en
Definition: gr55xx_hal_qspi.h:244
HAL_QSPI_STATE_RESET
@ HAL_QSPI_STATE_RESET
Definition: gr55xx_hal_qspi.h:78
QSPI_MMAPED_IDX_MODE_BITS_SIZE
@ QSPI_MMAPED_IDX_MODE_BITS_SIZE
Definition: gr55xx_hal_qspi.h:111
qspi_psram_command_t::data_block_length
uint32_t data_block_length
Definition: gr55xx_hal_qspi.h:332
hal_qspi_set_tcsu
void hal_qspi_set_tcsu(qspi_handle_t *p_qspi, uint32_t delay)
Set the QSPI cs setup & release time value.
_qspi_command_t
QSPI command Structure definition.
Definition: gr55xx_hal_qspi.h:200
_qspi_memorymapped_t::x_prefetch_en
uint32_t x_prefetch_en
Definition: gr55xx_hal_qspi.h:274
HAL_QSPI_STATE_READY
@ HAL_QSPI_STATE_READY
Definition: gr55xx_hal_qspi.h:79
hal_qspi_receive_dma
hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with DMA.
_qspi_memorymapped_write_t::x_dummy_cycles
uint32_t x_dummy_cycles
Definition: gr55xx_hal_qspi.h:306
_qspi_handle::write_fifo
void(* write_fifo)(struct _qspi_handle *p_qspi)
Definition: gr55xx_hal_qspi.h:174
hal_qspi_init
hal_status_t hal_qspi_init(qspi_handle_t *p_qspi)
Initialize the QSPI according to the specified parameters in the qspi_init_t and initialize the assoc...
QSPI_MMAPED_IDX_MODE_BITS_EN
@ QSPI_MMAPED_IDX_MODE_BITS_EN
Definition: gr55xx_hal_qspi.h:110
_qspi_command_t::address_size
uint32_t address_size
Definition: gr55xx_hal_qspi.h:210
_qspi_memorymapped_t::x_address_size
uint32_t x_address_size
Definition: gr55xx_hal_qspi.h:253
hal_qspi_msp_deinit
void hal_qspi_msp_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI MSP.
QSPI_MMAPED_IDX_DFS
@ QSPI_MMAPED_IDX_DFS
Definition: gr55xx_hal_qspi.h:104
hal_qspi_command_transmit_it
hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with Inter...
hal_qspi_transmit_dma
hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with DMA.
_qspi_handle::retention
uint32_t retention[22]
Definition: gr55xx_hal_qspi.h:188
_qspi_memorymapped_write_t::x_data_frame_format
uint32_t x_data_frame_format
Definition: gr55xx_hal_qspi.h:309
hal_qspi_suspend_reg
hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi)
Suspend some registers related to QSPI configuration before sleep.
hal_qspi_transmit_it
hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
hal_qspi_tx_cplt_callback
void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi)
Tx Transfer completed callback.
hal_qspi_transmit
hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
hal_qspi_command_receive_dma
hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
QSPI_MMAPED_IDX_PREFETCH_EN
@ QSPI_MMAPED_IDX_PREFETCH_EN
Definition: gr55xx_hal_qspi.h:115
hal_qspi_abort_cplt_callback
void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi)
QSPI Abort Complete callback.
hal_qspi_command_transmit
hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Transmit an amount of data with the specified instruction and address in blocking mode.
hal_qspi_memorymapped_active
hal_status_t hal_qspi_memorymapped_active(qspi_handle_t *p_qspi, uint32_t is_sioo_mode)
Active the memory mapped mode from Ready state. users must make sure parameters of mmaped mode hava b...
_qspi_memorymapped_t::x_inst_addr_transfer_format
uint32_t x_inst_addr_transfer_format
Definition: gr55xx_hal_qspi.h:256
_hal_qspi_callback::qspi_tx_cplt_callback
void(* qspi_tx_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:367
_qspi_handle::p_dma
dma_handle_t * p_dma
Definition: gr55xx_hal_qspi.h:178
HAL_QSPI_STATE_ERROR
@ HAL_QSPI_STATE_ERROR
Definition: gr55xx_hal_qspi.h:85
hal_qspi_memorymapped_deactive
hal_status_t hal_qspi_memorymapped_deactive(qspi_handle_t *p_qspi)
Deactive the memory mapped mode to Ready state it's recommended to use with hal_qspi_memorymapped_act...
_qspi_command_t::dummy_cycles
uint32_t dummy_cycles
Definition: gr55xx_hal_qspi.h:213
hal_qspi_irq_handler
void hal_qspi_irq_handler(qspi_handle_t *p_qspi)
Handle QSPI interrupt request.
hal_qspi_abort
hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi)
Abort the current transmission.
hal_memorymapped_status_t
hal_memorymapped_status_t
HAL Status structures Of memorymapped definition.
Definition: gr55xx_hal_qspi.h:93
_qspi_memorymapped_write_t::x_instruction_size
uint32_t x_instruction_size
Definition: gr55xx_hal_qspi.h:294
_qspi_memorymapped_set_t
KEY:Value pair to set memorymapped parameter.
Definition: gr55xx_hal_qspi.h:316
qspi_psram_command_t::llp_data_mode
uint32_t llp_data_mode
Definition: gr55xx_hal_qspi.h:337
_hal_qspi_callback
HAL_QSPI Callback function definition.
Definition: gr55xx_hal_qspi.h:361
hal_qspi_rx_cplt_callback
void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi)
Rx Transfer completed callback.
QSPI_MMAPED_IDX_INST_SIZE
@ QSPI_MMAPED_IDX_INST_SIZE
Definition: gr55xx_hal_qspi.h:106
hal_qspi_transmit_dma_llp
hal_status_t hal_qspi_transmit_dma_llp(qspi_handle_t *p_qspi, dma_llp_config_t *p_llp_config, uint32_t data_mode, uint32_t data_length, uint32_t clock_stretch_enable)
Transmit Multi-Block of data without instruction and address in non-blocking mode with DMA Linked Lis...
qspi_memorymapped_write_t
struct _qspi_memorymapped_write_t qspi_memorymapped_write_t
QSPI memory map write Structure definition.
QSPI_MMAPED_IDX_DATA_FRF
@ QSPI_MMAPED_IDX_DATA_FRF
Definition: gr55xx_hal_qspi.h:114
QSPI_MMAPED_IDX_INST_VAL
@ QSPI_MMAPED_IDX_INST_VAL
Definition: gr55xx_hal_qspi.h:107
_qspi_memorymapped_t
QSPI memory map Structure definition.
Definition: gr55xx_hal_qspi.h:239
_qspi_memorymapped_write_t
QSPI memory map write Structure definition.
Definition: gr55xx_hal_qspi.h:292
hal_qspi_abort_it
hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi)
Abort the current transmission (non-blocking function)
QSPI_MMAPED_IDX_WAIT_CYCLES
@ QSPI_MMAPED_IDX_WAIT_CYCLES
Definition: gr55xx_hal_qspi.h:113
qspi_command_t
struct _qspi_command_t qspi_command_t
QSPI command Structure definition.
HAL_QSPI_STATE_BUSY_INDIRECT_RX
@ HAL_QSPI_STATE_BUSY_INDIRECT_RX
Definition: gr55xx_hal_qspi.h:82
_qspi_memorymapped_write_t::x_instruction
uint32_t x_instruction
Definition: gr55xx_hal_qspi.h:297
_hal_qspi_callback::qspi_abort_cplt_callback
void(* qspi_abort_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:365
QSPI_MMAPED_IDX_CONT_XFER_EN
@ QSPI_MMAPED_IDX_CONT_XFER_EN
Definition: gr55xx_hal_qspi.h:116
hal_qspi_psram_transmit_dma_llp_limited
hal_status_t hal_qspi_psram_transmit_dma_llp_limited(qspi_handle_t *p_qspi, qspi_psram_command_t *p_cmd, dma_llp_config_t *p_llp_config)
: Used to write PSRAM in high speed mode with dma LLP
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
hal_qspi_command
hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
_qspi_memorymapped_t::x_continous_xfer_toc
uint32_t x_continous_xfer_toc
Definition: gr55xx_hal_qspi.h:280
_qspi_init_t::clock_prescaler
uint32_t clock_prescaler
Definition: gr55xx_hal_qspi.h:138
_qspi_handle::read_fifo
void(* read_fifo)(struct _qspi_handle *p_qspi)
Definition: gr55xx_hal_qspi.h:176
hal_qspi_command_transmit_dma_llp
hal_status_t hal_qspi_command_transmit_dma_llp(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config)
Transmit Multi-Block of data with the specified instruction and address in non-blocking mode with DMA...
qspi_psram_command_t::data_size
uint32_t data_size
Definition: gr55xx_hal_qspi.h:327
HAL_MMAPPED_STATE_DEACTIVED
@ HAL_MMAPPED_STATE_DEACTIVED
Definition: gr55xx_hal_qspi.h:94
_qspi_memorymapped_t::x_data_frame_format
uint32_t x_data_frame_format
Definition: gr55xx_hal_qspi.h:271
QSPI_MMAPED_IDX_DFS_HARDCCODE_EN
@ QSPI_MMAPED_IDX_DFS_HARDCCODE_EN
Definition: gr55xx_hal_qspi.h:103
_qspi_handle::error_code
__IO uint32_t error_code
Definition: gr55xx_hal_qspi.h:184
hal_qspi_resume_reg
hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi)
Restore some registers related to QSPI configuration after sleep. This function must be used in conju...
dma_llp_config
LL DMA llp config definition.
Definition: gr55xx_hal_dma.h:197
hal_qspi_command_receive_it
hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
_qspi_handle::init
qspi_init_t init
Definition: gr55xx_hal_qspi.h:160
qspi_psram_command_t::llp_data_shape
uint32_t llp_data_shape
Definition: gr55xx_hal_qspi.h:339
_qspi_memorymapped_idx_e
_qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
Definition: gr55xx_hal_qspi.h:102
_qspi_handle::lock
__IO hal_lock_t lock
Definition: gr55xx_hal_qspi.h:180
_qspi_command_t::instruction
uint32_t instruction
Definition: gr55xx_hal_qspi.h:201
_qspi_memorymapped_t::x_mode_bits_en
uint32_t x_mode_bits_en
Definition: gr55xx_hal_qspi.h:259
_qspi_handle::tx_xfer_count
__IO uint32_t tx_xfer_count
Definition: gr55xx_hal_qspi.h:166
HAL_QSPI_STATE_BUSY_INDIRECT_TX
@ HAL_QSPI_STATE_BUSY_INDIRECT_TX
Definition: gr55xx_hal_qspi.h:81
hal_qspi_command_transmit_dma
hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
hal_qspi_set_timeout
void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout)
Set the QSPI internal process timeout value.
hal_qspi_memorymapped
hal_status_t hal_qspi_memorymapped(qspi_handle_t *p_qspi, qspi_memorymapped_t *mmap_cmd, qspi_memorymapped_write_t *mmap_wr_cmd)
Configure the Memory Mapped mode. Called after hal_qspi_init(...)
dma_gather_config
LL DMA gather config definition.
Definition: gr55xx_hal_dma.h:181
qspi_handle_t
struct _qspi_handle qspi_handle_t
QSPI handle Structure definition.
hal_qspi_receive_it
hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
_qspi_memorymapped_set_t::mmap_val
uint32_t mmap_val
Definition: gr55xx_hal_qspi.h:318
hal_qspi_command_it
hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
_qspi_command_t::data_mode
uint32_t data_mode
Definition: gr55xx_hal_qspi.h:222
HAL_QSPI_STATE_BUSY
@ HAL_QSPI_STATE_BUSY
Definition: gr55xx_hal_qspi.h:80
qspi_init_t
struct _qspi_init_t qspi_init_t
QSPI init Structure definition.
hal_qspi_callback_t
struct _hal_qspi_callback hal_qspi_callback_t
HAL_QSPI Callback function definition.
hal_qspi_command_receive_dma_scatter
hal_status_t hal_qspi_command_receive_dma_scatter(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t sct_interval, uint32_t sct_count)
Receive an amount of data with the specified instruction and address in non-blocking mode with DMA Sc...
hal_qspi_state_t
hal_qspi_state_t
HAL QSPI State Enumerations definition.
Definition: gr55xx_hal_qspi.h:77
qspi_psram_command_t
QSPI command for psram-write Structure definition.
Definition: gr55xx_hal_qspi.h:325
hal_qspi_get_state
hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi)
Return the QSPI handle state.
_hal_qspi_callback::qspi_msp_init
void(* qspi_msp_init)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:362
hal_qspi_command_dma
hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with DMA.
_qspi_handle::p_rx_buffer
uint8_t * p_rx_buffer
Definition: gr55xx_hal_qspi.h:168
_qspi_handle
QSPI handle Structure definition.
Definition: gr55xx_hal_qspi.h:157
_qspi_command_t::address
uint32_t address
Definition: gr55xx_hal_qspi.h:204
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:277
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
QSPI_MMAPED_IDX_MODE_BITS_VAL
@ QSPI_MMAPED_IDX_MODE_BITS_VAL
Definition: gr55xx_hal_qspi.h:112
hal_qspi_get_error
uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi)
Return the QSPI error code.
_qspi_command_t::clock_stretch_en
uint32_t clock_stretch_en
Definition: gr55xx_hal_qspi.h:230
HAL_MMAPPED_STATE_ERROR
@ HAL_MMAPPED_STATE_ERROR
Definition: gr55xx_hal_qspi.h:96
_qspi_init_t::clock_mode
uint32_t clock_mode
Definition: gr55xx_hal_qspi.h:141
hal_qspi_error_callback
void hal_qspi_error_callback(qspi_handle_t *p_qspi)
QSPI error callback.
QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT
@ QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT
Definition: gr55xx_hal_qspi.h:109
_qspi_memorymapped_t::x_mode_bits_data
uint32_t x_mode_bits_data
Definition: gr55xx_hal_qspi.h:265
_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_hal_qspi.h:144
hal_qspi_memorymapped_is_actived
hal_memorymapped_status_t hal_qspi_memorymapped_is_actived(qspi_handle_t *p_qspi)
Check whether the memory mapped mode is Actived.
_qspi_memorymapped_t::x_mode_bits_length
uint32_t x_mode_bits_length
Definition: gr55xx_hal_qspi.h:262
QSPI_MMAPED_IDX_INST_EN
@ QSPI_MMAPED_IDX_INST_EN
Definition: gr55xx_hal_qspi.h:105
hal_qspi_command_transmit_dma_gather
hal_status_t hal_qspi_command_transmit_dma_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_gather_config_t *p_gather_config, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA G...