gr55xx_ll_advs.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_advs.h
5 * @author BLE RD
6 * @brief Header file containing functions prototypes of advs LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AVDS AVDS
47 * @brief AVDS LL module driver.
48 * @{
49 */
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR55XX_LL_ADVS_H_
52 #define __GR55XX_LL_ADVS_H_
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "gr55xx_hal.h"
60
61 /**
62 * @defgroup ADVS_LL_MACRO Defines
63 * @{
64 */
65 /** @defgroup LL_ADVS_ENABLE Analog Voltage Scaling enable state defines
66 * @{
67 */
68 #define LL_ADVS_DIS (0U) /**< Analog Voltage Scaling Disable(default) */
69 #define LL_ADVS_EN (1U) /**< Analog Voltage Scaling Enable */
70 /** @} */
71
72 /** @defgroup LL_ADVS_TYPE Analog Voltage Scaling slop control type defines
73 * @{
74 */
75 #define LL_ADVS_LOWER_TYPE (0U) /**< Analog Voltage Scaling Lower Type(default) */
76 #define LL_ADVS_HIGHER_TYPE (1U) /**< Analog Voltage Scaling Higher Type */
77 /** @} */
78
79 /** @defgroup LL_ADVS_LIMIT_ENABLE Analog Voltage Scaling limiter enable defines
80 * @{
81 */
82 #define LL_ADVS_LIMIT_DIS (0U) /**< Analog Voltage Scaling Limit Disable(default) */
83 #define LL_ADVS_LIMIT_EN (1U) /**< Analog Voltage Scaling Limit Enable */
84 /** @} */
85
86 /** @} */
87
88 /** @defgroup ADVS_LL_DRIVER_FUNCTIONS Functions
89 * @{
90 */
91 /**
92 * @brief The ADVS_DCDC block enable set
93 *
94 * Register|BitsName
95 * --------|--------
96 * ADVS_DCDC | EN_VTBIAS
97 */
98 __STATIC_INLINE void ll_advs_dcdc_enable_set(uint8_t enable)
99 {
100 MODIFY_REG(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_EN_VTBIAS, (enable << AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos));
101 }
102
103 /**
104 * @brief The ADVS_DCDC block enable get
105 *
106 * Register|BitsName
107 * --------|--------
108 * ADVS_DCDC | EN_VTBIAS
109 */
110 __STATIC_INLINE uint8_t ll_advs_dcdc_enable_get(void)
111 {
112 return ((READ_BITS(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_EN_VTBIAS)) >> AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos);
113 }
114
115 /**
116 * @brief The ADVS_DCDC's Slop Control type set
117 *
118 * Register|BitsName
119 * --------|--------
120 * ADVS_DCDC | VTBIAS_SLOPE_CTRL
121 */
122 __STATIC_INLINE void ll_advs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
123 {
124 MODIFY_REG(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos));
125 }
126
127 /**
128 * @brief The ADVS_DCDC's Slop Control type get
129 *
130 * Register|BitsName
131 * --------|--------
132 * ADVS_DCDC | VTBIAS_SLOPE_CTRL
133 */
134 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_slop_ctrl_get(void)
135 {
136 return ((READ_BITS(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos);
137 }
138
139 /**
140 * @brief The ADVS_DCDC's Lower Limit Control enable set
141 *
142 * Register|BitsName
143 * --------|--------
144 * ADVS_DCDC | EN_LIMITER
145 */
146 __STATIC_INLINE void ll_advs_dcdc_limiter_enable_set(uint8_t enable)
147 {
148 MODIFY_REG(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_EN_LIMITER, (enable << AON_PMU_ADVS_DCDC_EN_LIMITER_Pos));
149 }
150
151 /**
152 * @brief The ADVS_DCDC's Lower Limit Control enable get
153 *
154 * Register|BitsName
155 * --------|--------
156 * ADVS_DCDC | EN_LIMITER
157 */
158 __STATIC_INLINE uint8_t ll_advs_dcdc_limiter_enable_get(void)
159 {
160 return ((READ_BITS(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_EN_LIMITER)) >> AON_PMU_ADVS_DCDC_EN_LIMITER_Pos);
161 }
162
163 /**
164 * @brief The ADVS_DCDC's default level value of the VT bias set
165 *
166 * Register|BitsName
167 * --------|--------
168 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
169 */
170 __STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
171 {
172 MODIFY_REG(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos));
173 }
174
175 /**
176 * @brief The ADVS_DCDC's default level value of the VT bias get
177 *
178 * Register|BitsName
179 * --------|--------
180 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
181 */
182 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_vt_get(void)
183 {
184 return ((READ_BITS(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos);
185 }
186
187 /**
188 * @brief The ADVS_DCDC's lower limit for the output voltage set
189 *
190 * Register|BitsName
191 * --------|--------
192 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
193 */
194 __STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
195 {
196 MODIFY_REG(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos));
197 }
198
199 /**
200 * @brief The ADVS_DCDC's lower limit for the output voltage get
201 *
202 * Register|BitsName
203 * --------|--------
204 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
205 */
206 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_lower_limit_get(void)
207 {
208 return ((READ_BITS(AON_PMU->ADVS_DCDC, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos);
209 }
210
211 /**
212 * @brief The ADVS_DIGCORE block enable set
213 *
214 * Register|BitsName
215 * --------|--------
216 * ADVS_DIGCORE | EN_VTBIAS
217 */
218 __STATIC_INLINE void ll_advs_digcore_enable_set(uint8_t enable)
219 {
220 MODIFY_REG(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_EN_VTBIAS, (enable << AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos));
221 }
222
223 /**
224 * @brief The ADVS_DIGCORE block enable get
225 *
226 * Register|BitsName
227 * --------|--------
228 * ADVS_DIGCORE | EN_VTBIAS
229 */
230 __STATIC_INLINE uint8_t ll_advs_digcore_enable_get(void)
231 {
232 return ((READ_BITS(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_EN_VTBIAS)) >> AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos);
233 }
234
235 /**
236 * @brief The ADVS_DIGCORE's Slop Control type set
237 *
238 * Register|BitsName
239 * --------|--------
240 * ADVS_DIGCORE | VTBIAS_SLOPE_CTRL
241 */
242 __STATIC_INLINE void ll_advs_digcore_vtbias_slop_ctrl_set(uint8_t type)
243 {
244 MODIFY_REG(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos));
245 }
246
247 /**
248 * @brief The ADVS_DIGCORE's Slop Control type get
249 *
250 * Register|BitsName
251 * --------|--------
252 * ADVS_DIGCORE | VTBIAS_SLOPE_CTRL
253 */
254 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_slop_ctrl_get(void)
255 {
256 return ((READ_BITS(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos);
257 }
258
259 /**
260 * @brief The ADVS_DIGCORE's Lower Limit Control enable set
261 *
262 * Register|BitsName
263 * --------|--------
264 * ADVS_DIGCORE | EN_LIMITER
265 */
266 __STATIC_INLINE void ll_advs_digcore_limiter_enable_set(uint8_t enable)
267 {
268 MODIFY_REG(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_EN_LIMITER, (enable << AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos));
269 }
270
271 /**
272 * @brief The ADVS_DIGCORE's Lower Limit Control enable get
273 *
274 * Register|BitsName
275 * --------|--------
276 * ADVS_DIGCORE | EN_LIMITER
277 */
278 __STATIC_INLINE uint8_t ll_advs_digcore_limiter_enable_get(void)
279 {
280 return ((READ_BITS(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_EN_LIMITER)) >> AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos);
281 }
282
283 /**
284 * @brief The ADVS_DIGCORE's default level value of the VT bias set
285 *
286 * Register|BitsName
287 * --------|--------
288 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
289 */
290 __STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
291 {
292 MODIFY_REG(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos));
293 }
294
295 /**
296 * @brief The ADVS_DIGCORE's default level value of the VT bias get
297 *
298 * Register|BitsName
299 * --------|--------
300 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
301 */
302 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_vt_get(void)
303 {
304 return ((READ_BITS(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos);
305 }
306
307 /**
308 * @brief The ADVS_DIGCORE's lower limit for the output voltage set
309 *
310 * Register|BitsName
311 * --------|--------
312 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
313 */
314 __STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
315 {
316 MODIFY_REG(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos));
317 }
318
319 /**
320 * @brief The ADVS_DIGCORE's lower limit for the output voltage get
321 *
322 * Register|BitsName
323 * --------|--------
324 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
325 */
326 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_lower_limit_get(void)
327 {
328 return ((READ_BITS(AON_PMU->ADVS_DIGCORE, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos);
329 }
330
331 /** @} */
332
333 #ifdef __cplusplus
334 }
335 #endif
336
337 #endif
338 /** @} */
339
340 /** @} */
341
342 /** @} */
ll_advs_digcore_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
The ADVS_DIGCORE's default level value of the VT bias set.
Definition: gr55xx_ll_advs.h:290
ll_advs_dcdc_enable_set
__STATIC_INLINE void ll_advs_dcdc_enable_set(uint8_t enable)
The ADVS_DCDC block enable set.
Definition: gr55xx_ll_advs.h:98
ll_advs_dcdc_limiter_enable_get
__STATIC_INLINE uint8_t ll_advs_dcdc_limiter_enable_get(void)
The ADVS_DCDC's Lower Limit Control enable get.
Definition: gr55xx_ll_advs.h:158
ll_advs_dcdc_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_slop_ctrl_get(void)
The ADVS_DCDC's Slop Control type get.
Definition: gr55xx_ll_advs.h:134
ll_advs_dcdc_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_lower_limit_get(void)
The ADVS_DCDC's lower limit for the output voltage get.
Definition: gr55xx_ll_advs.h:206
ll_advs_dcdc_enable_get
__STATIC_INLINE uint8_t ll_advs_dcdc_enable_get(void)
The ADVS_DCDC block enable get.
Definition: gr55xx_ll_advs.h:110
ll_advs_dcdc_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
The ADVS_DCDC's Slop Control type set.
Definition: gr55xx_ll_advs.h:122
ll_advs_digcore_enable_set
__STATIC_INLINE void ll_advs_digcore_enable_set(uint8_t enable)
The ADVS_DIGCORE block enable set.
Definition: gr55xx_ll_advs.h:218
ll_advs_digcore_enable_get
__STATIC_INLINE uint8_t ll_advs_digcore_enable_get(void)
The ADVS_DIGCORE block enable get.
Definition: gr55xx_ll_advs.h:230
ll_advs_digcore_limiter_enable_set
__STATIC_INLINE void ll_advs_digcore_limiter_enable_set(uint8_t enable)
The ADVS_DIGCORE's Lower Limit Control enable set.
Definition: gr55xx_ll_advs.h:266
ll_advs_digcore_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_slop_ctrl_get(void)
The ADVS_DIGCORE's Slop Control type get.
Definition: gr55xx_ll_advs.h:254
ll_advs_dcdc_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
The ADVS_DCDC's lower limit for the output voltage set.
Definition: gr55xx_ll_advs.h:194
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_advs_dcdc_limiter_enable_set
__STATIC_INLINE void ll_advs_dcdc_limiter_enable_set(uint8_t enable)
The ADVS_DCDC's Lower Limit Control enable set.
Definition: gr55xx_ll_advs.h:146
ll_advs_digcore_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_vt_get(void)
The ADVS_DIGCORE's default level value of the VT bias get.
Definition: gr55xx_ll_advs.h:302
ll_advs_dcdc_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
The ADVS_DCDC's default level value of the VT bias set.
Definition: gr55xx_ll_advs.h:170
ll_advs_digcore_limiter_enable_get
__STATIC_INLINE uint8_t ll_advs_digcore_limiter_enable_get(void)
The ADVS_DIGCORE's Lower Limit Control enable get.
Definition: gr55xx_ll_advs.h:278
ll_advs_dcdc_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_vt_get(void)
The ADVS_DCDC's default level value of the VT bias get.
Definition: gr55xx_ll_advs.h:182
ll_advs_digcore_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_lower_limit_get(void)
The ADVS_DIGCORE's lower limit for the output voltage get.
Definition: gr55xx_ll_advs.h:326
ll_advs_digcore_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_advs_digcore_vtbias_slop_ctrl_set(uint8_t type)
The ADVS_DIGCORE's Slop Control type set.
Definition: gr55xx_ll_advs.h:242
ll_advs_digcore_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
The ADVS_DIGCORE's lower limit for the output voltage set.
Definition: gr55xx_ll_advs.h:314