gr55xx_efuse_layout.h
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1 #ifndef __GR55XX_EFUSE_LAYOUT_H__
2 #define __GR55XX_EFUSE_LAYOUT_H__
3
4 #include<stdio.h>
5 #include<stdint.h>
6
7 #define EFUSE_BT_ADDR_SIZE (6)
8 #define EFUSE_CHIP_UID_SIZE (16)
9 #define EFUSE_CHIP_ID_SIZE (6)
10 #define EFUSE_PRODUCT_ID_SIZE (2)
11 #define FW_PUBLIC_KEY_HASH_SIZE (16)
12 #define ROOT_PUBLIC_KEY_HASH_SIZE (16)
13
14 #define ECC_KEY_SIZE (32)
15 #define FW_KEY_SIZE (32)
16 #define HMAC_KEY_SIZE (32)
17 #define DATA_KEY_SIZE (32)
18
19 #define EFUSE_TRIM_PATTERN (0x4744)
20
21 #define EFUSE_IO_LDO_SEL_MASK (0x01)
22 #define EFUSE_IO_LDO_BYPASS_MASK (0x02)
23
24 /* Make sure it is same with the one in \boot_security\BL0\inc\efuse.h. */
25 typedef struct _efuse_trim0_t
26 {
27 uint8_t chip_uid[EFUSE_CHIP_UID_SIZE]; /* chip unique id, include wafer, lot etc. */
28 uint8_t ate_version;
29 uint8_t reserved0[2];
30 uint8_t io_ldo_sel; /* 0bit: IO_LDO selector (0: 1.8v, 1:3.3v); 1bit: IO_LDO_Bypass (0: no, 1: bypass) */
31 uint8_t bt_addr[EFUSE_BT_ADDR_SIZE];
32 uint16_t xo_offset;
33 uint16_t pattern; /* fixed 0x4744. Indicates whether trim is valid*/
34 uint16_t trim_sum;
35 uint16_t hw_version; /* A0: 0x4130, A1: 0x4131, B0: 0x4230 */
36 uint16_t chip_id; /* GR5515: 0x5515, GR5526: 0x5526, GR5332: 0x5332 */
37 uint16_t package;
38 uint16_t flash_size; /* 2048KB: 0x0800,1024KB: 0x0400, 512KB: 0x0200 */
39 uint16_t ram_size; /* 512KB: 0x0200, 256KB: 0x0100, 192KB: 0x00C0, 128KB: 0x0080 */
40 uint8_t reserved1[2];
41 uint8_t dcdc_vout1p05;
42 uint8_t dcdc_vout1p15;
43 uint8_t dig_ldo_0p9;
44 uint8_t dig_ldo_1p05;
45 uint8_t io_ldo_1p8; /* used for active */
46 uint8_t io_ldo_3p0;
47 uint8_t stb_io_ldo_1p8; /* used for sleep */
48 uint8_t stb_io_ldo_3p0;
49 uint8_t reserved2[4];
50 uint8_t tx_power;
51 uint8_t rssi_cali;
52 uint8_t lp_gain_offset_2m;
53 uint8_t reserved3;
54 } __attribute__ ((packed)) efuse_trim0_t;
55
56
57 typedef struct _efuse_exflash_timing_t
58 {
59 uint8_t flash_tVSL; /* tVSL: VCC(min.) to device operation. min 10us, unit: 10us */
60 uint8_t flash_tESL; /* tESL: Erase suspend latency. max 30us, unit: 5us */
61 uint8_t flash_tPSL; /* tPSL: Program suspend latency. max 30us, unit: 5us */
62 uint8_t flash_tPRS; /* tPRS: Latency between program resume and next suspend. max 30us, unit: 5us */
63 uint8_t flash_tERS; /* tERS: Latency between erase resume and next suspend. max 30us, unit: 5us */
64 uint8_t flash_tDP; /* tDP: CS# High to Deep Power-down Mode. unit: 5us */
65 uint8_t flash_tRES2; /* tRES2: CS# High To Standby Mode With Electronic Signature Read max 8us, unit: 5us */
66 uint8_t flash_tRDINT; /* tRDINT: Read status register interval after write opertion. Uint: 5us */
67 } __attribute__ ((packed)) efuse_exflash_timing_t;
68
69 typedef struct _efuse_sadc_trim_t
70 {
71 uint16_t offset_int_0p8;
72 uint16_t slope_int_0p8;
73 uint16_t offset_int_1p2;
74 uint16_t slope_int_1p2;
75 uint16_t offset_int_1p6;
76 uint16_t slope_int_1p6;
77 uint16_t offset_ext_1p0;
78 uint16_t slope_ext_1p0;
79 uint16_t temp;
80 uint16_t temp_ref;
81 } __attribute__ ((packed)) efuse_sadc_trim_t;
82
83 typedef struct _efuse_comp_trim_t
84 {
85 uint16_t slope_int_no1;
86 uint16_t slope_int_no2;
87 } __attribute__ ((packed)) efuse_comp_trim_t;
88
89 typedef struct _efuse_trim1_t
90 {
91 efuse_sadc_trim_t sadc_trim;
92 efuse_exflash_timing_t flash_timing;
93 efuse_comp_trim_t comp_trim;
94 uint8_t reserved[28];
95 } __attribute__ ((packed)) efuse_trim1_t;
96
97 typedef struct {
98 /* Configurations 4Byte */
99 uint32_t isp_uart_bypass : 1; /* 1: Not Support UART ISP Process, 0: Support UART ISP Process */
100 uint32_t isp_usb_bypass : 1; /* 1: Not Support USB ISP Process, 0: Support USB ISP Process */
101 uint32_t isp_jlink_bypass : 1; /* 1: Not Support JLINK ISP Process, 0: Support JLINK ISP Process */
102 uint32_t enc_boot_system_clk : 3; /* 0: XO-16M, 1: PLL-64M, 2: PLL-96M, 3: PLL-48M, 4: PLL-24M, 5: PLL-16M, 6: PLL-32M */
103 uint32_t enc_boot_flash_clk : 3; /* 0: 16MHz, 1: 48MHz, 2: 32MHz, 3: 24MHz, 4:64MHz */
104 uint32_t enc_boot_xip_read_cmd : 8; /* 0x03, 0x0B, 0x3B, 0xBB, 0x6B, 0xEB */
105 uint32_t memory_power_size : 2; /* 0: 256KB, 1: 192KB, 2: 128KB */
106 uint32_t reserved : 13;
107
108 uint16_t swd_disable; /* 0：not disable，1：disable */
109 uint16_t enc_mode; /* 0：unencrypted，1：encrypted */
110 uint32_t crc32; /* Key CRC32 */
111
112 uint8_t chip_id[EFUSE_CHIP_ID_SIZE]; /* user define */
113 uint8_t product_id[EFUSE_PRODUCT_ID_SIZE]; /* user define */
114 uint8_t fw_public_key_hash[FW_PUBLIC_KEY_HASH_SIZE];
115 uint8_t root_public_key_hash[ROOT_PUBLIC_KEY_HASH_SIZE];
116 } __attribute__ ((packed)) efuse_ctrl_section_t;
117
118 typedef struct {
119 uint8_t ecc_key[ECC_KEY_SIZE];
120 uint8_t fw_key[FW_KEY_SIZE];
121 uint8_t hmac_key[HMAC_KEY_SIZE];
122 uint8_t data_key[DATA_KEY_SIZE];
123 } __attribute__ ((packed)) efuse_key_section_t;
124
125 typedef struct {
126 uint8_t user_section[32];
127 efuse_trim1_t efuse_trim1;
128 efuse_ctrl_section_t backup_ctrl_section;
129 efuse_key_section_t backup_key_section;
130 efuse_trim0_t efuse_trim0;
131 efuse_ctrl_section_t main_ctrl_section;
132 efuse_key_section_t main_key_section;
133 } __attribute__ ((packed)) efuse_all_t;
134
135 #endif /* __GR55XX_EFUSE_LAYOUT_H__ */
_efuse_trim0_t::chip_id
uint16_t chip_id
Definition: gr55xx_efuse_layout.h:36
__attribute__
typedef __attribute__
Electronic Shelf Label Key Material.
Definition: esls.h:318
_efuse_trim0_t::stb_io_ldo_3p0
uint8_t stb_io_ldo_3p0
Definition: gr55xx_efuse_layout.h:48
_efuse_trim0_t::dig_ldo_0p9
uint8_t dig_ldo_0p9
Definition: gr55xx_efuse_layout.h:43
__attribute__::backup_ctrl_section
efuse_ctrl_section_t backup_ctrl_section
Definition: gr55xx_efuse_layout.h:128
EFUSE_CHIP_UID_SIZE
#define EFUSE_CHIP_UID_SIZE
Definition: gr55xx_efuse_layout.h:8
__attribute__::enc_boot_system_clk
uint32_t enc_boot_system_clk
Definition: gr55xx_efuse_layout.h:102
_efuse_trim0_t::chip_uid
uint8_t chip_uid[EFUSE_CHIP_UID_SIZE]
Definition: gr55xx_efuse_layout.h:27
EFUSE_PRODUCT_ID_SIZE
#define EFUSE_PRODUCT_ID_SIZE
Definition: gr55xx_efuse_layout.h:10
__attribute__::swd_disable
uint16_t swd_disable
Definition: gr55xx_efuse_layout.h:108
_efuse_sadc_trim_t::offset_int_0p8
uint16_t offset_int_0p8
Definition: gr55xx_efuse_layout.h:71
_efuse_trim0_t::tx_power
uint8_t tx_power
Definition: gr55xx_efuse_layout.h:50
_efuse_trim0_t::flash_size
uint16_t flash_size
Definition: gr55xx_efuse_layout.h:38
_efuse_sadc_trim_t::temp_ref
uint16_t temp_ref
Definition: gr55xx_efuse_layout.h:80
_efuse_trim0_t::dig_ldo_1p05
uint8_t dig_ldo_1p05
Definition: gr55xx_efuse_layout.h:44
_efuse_exflash_timing_t::flash_tRES2
uint8_t flash_tRES2
Definition: gr55xx_efuse_layout.h:65
_efuse_sadc_trim_t::slope_int_1p2
uint16_t slope_int_1p2
Definition: gr55xx_efuse_layout.h:74
_efuse_exflash_timing_t::flash_tERS
uint8_t flash_tERS
Definition: gr55xx_efuse_layout.h:63
chip_id
uint16_t chip_id
Definition: gr55xx_efuse_layout.h:9
_efuse_trim0_t::io_ldo_sel
uint8_t io_ldo_sel
Definition: gr55xx_efuse_layout.h:30
__attribute__::reserved
uint32_t reserved
Definition: gr55xx_efuse_layout.h:106
_efuse_trim0_t::dcdc_vout1p05
uint8_t dcdc_vout1p05
Definition: gr55xx_efuse_layout.h:41
__attribute__::main_ctrl_section
efuse_ctrl_section_t main_ctrl_section
Definition: gr55xx_efuse_layout.h:131
EFUSE_CHIP_ID_SIZE
#define EFUSE_CHIP_ID_SIZE
Definition: gr55xx_efuse_layout.h:9
_efuse_sadc_trim_t::temp
uint16_t temp
Definition: gr55xx_efuse_layout.h:79
_efuse_trim0_t::io_ldo_1p8
uint8_t io_ldo_1p8
Definition: gr55xx_efuse_layout.h:45
DATA_KEY_SIZE
#define DATA_KEY_SIZE
Definition: gr55xx_efuse_layout.h:17
_efuse_trim0_t::rssi_cali
uint8_t rssi_cali
Definition: gr55xx_efuse_layout.h:51
FW_PUBLIC_KEY_HASH_SIZE
#define FW_PUBLIC_KEY_HASH_SIZE
Definition: gr55xx_efuse_layout.h:11
_efuse_trim0_t::hw_version
uint16_t hw_version
Definition: gr55xx_efuse_layout.h:35
__attribute__::main_key_section
efuse_key_section_t main_key_section
Definition: gr55xx_efuse_layout.h:132
__attribute__::memory_power_size
uint32_t memory_power_size
Definition: gr55xx_efuse_layout.h:105
_efuse_trim1_t::sadc_trim
efuse_sadc_trim_t sadc_trim
Definition: gr55xx_efuse_layout.h:91
_efuse_sadc_trim_t
Definition: gr55xx_efuse_layout.h:70
_efuse_trim0_t::xo_offset
uint16_t xo_offset
Definition: gr55xx_efuse_layout.h:32
HMAC_KEY_SIZE
#define HMAC_KEY_SIZE
Definition: gr55xx_efuse_layout.h:16
_efuse_exflash_timing_t
Definition: gr55xx_efuse_layout.h:58
__attribute__::isp_usb_bypass
uint32_t isp_usb_bypass
Definition: gr55xx_efuse_layout.h:100
_efuse_sadc_trim_t::offset_int_1p6
uint16_t offset_int_1p6
Definition: gr55xx_efuse_layout.h:75
_efuse_trim0_t::bt_addr
uint8_t bt_addr[EFUSE_BT_ADDR_SIZE]
Definition: gr55xx_efuse_layout.h:31
_efuse_exflash_timing_t::flash_tPRS
uint8_t flash_tPRS
Definition: gr55xx_efuse_layout.h:62
_efuse_trim0_t::package
uint16_t package
Definition: gr55xx_efuse_layout.h:37
_efuse_trim0_t::ram_size
uint16_t ram_size
Definition: gr55xx_efuse_layout.h:39
_efuse_trim1_t::reserved
uint8_t reserved[28]
Definition: gr55xx_efuse_layout.h:94
_efuse_sadc_trim_t::slope_int_1p6
uint16_t slope_int_1p6
Definition: gr55xx_efuse_layout.h:76
_efuse_trim0_t::ate_version
uint8_t ate_version
Definition: gr55xx_efuse_layout.h:28
__attribute__::efuse_trim1
efuse_trim1_t efuse_trim1
Definition: gr55xx_efuse_layout.h:127
_efuse_trim1_t
Definition: gr55xx_efuse_layout.h:90
_efuse_trim0_t
Definition: gr55xx_efuse_layout.h:26
EFUSE_BT_ADDR_SIZE
#define EFUSE_BT_ADDR_SIZE
Definition: gr55xx_efuse_layout.h:7
_efuse_comp_trim_t::slope_int_no1
uint16_t slope_int_no1
Definition: gr55xx_efuse_layout.h:85
ROOT_PUBLIC_KEY_HASH_SIZE
#define ROOT_PUBLIC_KEY_HASH_SIZE
Definition: gr55xx_efuse_layout.h:12
_efuse_trim0_t::io_ldo_3p0
uint8_t io_ldo_3p0
Definition: gr55xx_efuse_layout.h:46
ECC_KEY_SIZE
#define ECC_KEY_SIZE
Definition: gr55xx_efuse_layout.h:14
_efuse_exflash_timing_t::flash_tRDINT
uint8_t flash_tRDINT
Definition: gr55xx_efuse_layout.h:66
_efuse_comp_trim_t
Definition: gr55xx_efuse_layout.h:84
_efuse_trim0_t::pattern
uint16_t pattern
Definition: gr55xx_efuse_layout.h:33
_efuse_sadc_trim_t::offset_ext_1p0
uint16_t offset_ext_1p0
Definition: gr55xx_efuse_layout.h:77
_efuse_trim0_t::reserved1
uint8_t reserved1[2]
Definition: gr55xx_efuse_layout.h:40
_efuse_trim0_t::stb_io_ldo_1p8
uint8_t stb_io_ldo_1p8
Definition: gr55xx_efuse_layout.h:47
_efuse_sadc_trim_t::offset_int_1p2
uint16_t offset_int_1p2
Definition: gr55xx_efuse_layout.h:73
__attribute__::efuse_trim0
efuse_trim0_t efuse_trim0
Definition: gr55xx_efuse_layout.h:130
_efuse_trim0_t::trim_sum
uint16_t trim_sum
Definition: gr55xx_efuse_layout.h:34
__attribute__::enc_mode
uint16_t enc_mode
Definition: gr55xx_efuse_layout.h:109
_efuse_trim0_t::dcdc_vout1p15
uint8_t dcdc_vout1p15
Definition: gr55xx_efuse_layout.h:42
_efuse_sadc_trim_t::slope_int_0p8
uint16_t slope_int_0p8
Definition: gr55xx_efuse_layout.h:72
_efuse_exflash_timing_t::flash_tESL
uint8_t flash_tESL
Definition: gr55xx_efuse_layout.h:60
__attribute__::isp_uart_bypass
uint32_t isp_uart_bypass
Definition: gr55xx_efuse_layout.h:99
__attribute__::enc_boot_xip_read_cmd
uint32_t enc_boot_xip_read_cmd
Definition: gr55xx_efuse_layout.h:104
_efuse_trim0_t::reserved0
uint8_t reserved0[2]
Definition: gr55xx_efuse_layout.h:29
_efuse_exflash_timing_t::flash_tVSL
uint8_t flash_tVSL
Definition: gr55xx_efuse_layout.h:59
__attribute__::crc32
uint32_t crc32
Definition: gr55xx_efuse_layout.h:110
_efuse_comp_trim_t::slope_int_no2
uint16_t slope_int_no2
Definition: gr55xx_efuse_layout.h:86
_efuse_sadc_trim_t::slope_ext_1p0
uint16_t slope_ext_1p0
Definition: gr55xx_efuse_layout.h:78
_efuse_trim0_t::lp_gain_offset_2m
uint8_t lp_gain_offset_2m
Definition: gr55xx_efuse_layout.h:52
FW_KEY_SIZE
#define FW_KEY_SIZE
Definition: gr55xx_efuse_layout.h:15
_efuse_trim0_t::reserved3
uint8_t reserved3
Definition: gr55xx_efuse_layout.h:53
__attribute__::enc_boot_flash_clk
uint32_t enc_boot_flash_clk
Definition: gr55xx_efuse_layout.h:103
_efuse_trim1_t::comp_trim
efuse_comp_trim_t comp_trim
Definition: gr55xx_efuse_layout.h:93
__attribute__::backup_key_section
efuse_key_section_t backup_key_section
Definition: gr55xx_efuse_layout.h:129
_efuse_exflash_timing_t::flash_tDP
uint8_t flash_tDP
Definition: gr55xx_efuse_layout.h:64
_efuse_exflash_timing_t::flash_tPSL
uint8_t flash_tPSL
Definition: gr55xx_efuse_layout.h:61
_efuse_trim0_t::reserved2
uint8_t reserved2[4]
Definition: gr55xx_efuse_layout.h:49
__attribute__::isp_jlink_bypass
uint32_t isp_jlink_bypass
Definition: gr55xx_efuse_layout.h:101
_efuse_trim1_t::flash_timing
efuse_exflash_timing_t flash_timing
Definition: gr55xx_efuse_layout.h:92