gr55xx_ll_gpadc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_gpadc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPADC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_ADC ADC
47 * @brief ADC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPADC_H__
53 #define __GR55XX_LL_GPADC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_CTL)
63
64 /** @defgroup ADC_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup ADC_LL_ES_INIT ADC Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL ADC init Structure definition
75 */
76 typedef struct _ll_gpadc_init
77 {
78 uint32_t channel_p; /**< Specifies the input source to GPADC channel P.
79 This parameter can be any value of @ref ADC_LL_EC_P_INPUT_SRC.*/
80
81 uint32_t channel_n; /**< Specifies the input source to GPADC channel N.
82 This parameter can be any value of @ref ADC_LL_EC_N_INPUT_SRC.*/
83
84 uint32_t input_mode; /**< Specifies the operation mode for the GPADC sample.
85 This parameter can be a value of @ref GPADC_LL_EC_INPUT_MODE.*/
86
87 uint32_t vdd_value; /**< Specifies the power supply value of the GPADC,which is also the max input of GPADC.
88 This parameter can be a value of @ref GPADC_LL_EC_VDD_VALUE.*/
89
90 uint32_t sp_rate; /**< Specifies the sample rate of GPADC.
91 This parameter can be a value of @ref GPADC_LL_EC_SP_RATE.*/
92
93 uint32_t pga_mode; /**< Specifies whether using PGA to gain the input or not.
94 This parameter can be a value of @ref GPADC_LL_EC_PGA_MODE.*/
95
96 uint32_t pga_gain; /**< Specifies whether using PGA to gain the input or not, and the gain value if using PGA.
97 This parameter can be a value of @ref GPADC_LL_EC_PGA_GAIN.*/
98 } ll_gpadc_init_t;
99 /** @} */
100
101 /** @} */
102
103 /**
104 * @defgroup GPADC_LL_MACRO Defines
105 * @{
106 */
107
108 /* Exported constants --------------------------------------------------------*/
109 /** @defgroup GPADC_LL_Exported_Constants GPADC Exported Constants
110 * @{
111 */
112
113 /** @defgroup the first set value of gpadc regs
114 * @{
115 */
116 #define LL_GPADC_CTRL0_DEFAULT_VALUE (0x882004ae)//M = 4'he(m+n=32), P = 2'h2(fixed), N = 6'h12(fixed), conv_num = 4'h0, td_t = 8'h20, ts_div = 3'h0, test_mode=1'd1(continu output); clk_inv=1'd0, cali_cap =1'h0, adc_en = 1'h0, conv_sel = 1'h1.
117 #define LL_GPADC_CTRL1_DEFAULT_VALUE (0x0000097b)
118 #define LL_GPADC_CONST_DEFAULT_VALUE (0x10e910e0)
119 #define LL_GPADC_ANA_CTRL_DEFAULT_VALUE (0x00022072)//Vref_pd=0,bypass pga,chp=2,chn=2.
120 /** @} */
121
122 /** @defgroup ADC_LL_EC_P_INPUT_SRC GPADC Input Source
123 * @{
124 */
125 #define LL_GPADC_P_INPUT_SRC_VCM (0UL) /**< Select vcm(=vdd/2) as input */
126 #define LL_GPADC_P_INPUT_SRC_IO1 (1UL) /**< Select MSIOB1 as input */
127 #define LL_GPADC_P_INPUT_SRC_IO2 (2UL) /**< Select MSIOB2 as input */
128 #define LL_GPADC_P_INPUT_SRC_IO3 (3UL) /**< Select MSIOB3 as input */
129 #define LL_GPADC_P_INPUT_SRC_IO4 (4UL) /**< Select MSIOB4 as input */
130 #define LL_GPADC_P_INPUT_SRC_IO5 (5UL) /**< Select MSIOB5 as input */
131 #define LL_GPADC_P_INPUT_SRC_IO6 (6UL) /**< Select MSIOB6 as input */
132 #define LL_GPADC_P_INPUT_SRC_IO7 (7UL) /**< Select MSIOB7 as input */
133 /** @} */
134
135 /** @defgroup ADC_LL_EC_N_INPUT_SRC GPADC Input Source
136 * @{
137 */
138 #define LL_GPADC_N_INPUT_SRC_VCM (0UL) /**< Select vcm(=vdd/2) as input */
139 #define LL_GPADC_N_INPUT_SRC_IO0 (1UL) /**< Select MSIOB0 as input */
140 #define LL_GPADC_N_INPUT_SRC_IO1 (2UL) /**< Select MSIOB1 as input */
141 #define LL_GPADC_N_INPUT_SRC_IO2 (3UL) /**< Select MSIOB2 as input */
142 #define LL_GPADC_N_INPUT_SRC_IO3 (4UL) /**< Select MSIOB3 as input */
143 #define LL_GPADC_N_INPUT_SRC_IO4 (5UL) /**< Select MSIOB4 as input */
144 #define LL_GPADC_N_INPUT_SRC_IO5 (6UL) /**< Select MSIOB5 as input */
145 #define LL_GPADC_N_INPUT_SRC_IO6 (7UL) /**< Select MSIOB6 as input */
146 /** @} */
147
148 /** @defgroup GPADC_LL_EC_INPUT_MODE GPADC Input Mode
149 * @{
150 */
151 #define LL_GPADC_INPUT_DIFFERENTIAL (0UL) /**< Differential mode */
152 #define LL_GPADC_INPUT_SINGLE (1UL ) /**< Single ended mode */
153 /** @} */
154
155 /** @defgroup GPADC_LL_EC_VDD_VALUE GPADC Vdd Value
156 * @{
157 */
158 #define LL_GPADC_VDD_VALUE_1P8 (0UL) /**< Vdd = 1.8 V */
159 #define LL_GPADC_VDD_VALUE_2P3 (5UL) /**< Vdd = 2.3 V */
160 /** @} */
161
162 /** @defgroup GPADC_LL_EC_SP_RATE GPADC Sample Rate
163 * @{
164 */
165 #define LL_GPADC_SPR_1M (0UL) /**<sample rate = 1Msps */
166 #define LL_GPADC_SPR_500K (1UL) /**<sample rate = 500Ksps */
167 #define LL_GPADC_SPR_250K (2UL) /**<sample rate = 250Ksps */
168 #define LL_GPADC_SPR_125K (3UL) /**<sample rate = 125Ksps */
169 /** @} */
170
171 /** @defgroup GPADC_LL_EC_PGA_MODE GPADC Pga Mode
172 * @{
173 */
174 #define LL_GPADC_PGA_MODE_BYPASS (0UL) /**<bypass mode, means not use pga*/
175 #define LL_GPADC_PGA_MODE_NORMAL (1UL) /**<use pga*/
176 /** @} */
177
178 /** @defgroup GPADC_LL_EC_PGA_GAIN GPADC Pga Gain
179 * @{
180 */
181 #define LL_GPADC_PGA_GAIN_0DB (0UL) /**<pga gain = 0db*/
182 #define LL_GPADC_PGA_GAIN_5DB (5UL) /**<pga gain = 5db*/
183 #define LL_GPADC_PGA_GAIN_10DB (10UL) /**<pga gain = 10db*/
184 #define LL_GPADC_PGA_GAIN_20DB (20UL) /**<pga gain = 20db*/
185
186 /** @} */
187
188 /** @} */
189
190 /* Exported macro ------------------------------------------------------------*/
191 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
192 * @{
193 */
194
195 /** @defgroup ADC_LL_EM_WRITE_READ Common Write and read registers Macros
196 * @{
197 */
198
199 /**
200 * @brief Write a value in ADC register
201 * @param __instance__ ADC instance
202 * @param __REG__ Register to be written
203 * @param __VALUE__ Value to be written in the register
204 * @retval None
205 */
206 #define LL_GPADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
207
208 /**
209 * @brief Read a value in ADC register
210 * @param __instance__ ADC instance
211 * @param __REG__ Register to be read
212 * @retval Register value
213 */
214 #define LL_GPADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
215
216 /** @} */
217
218 /** @} */
219
220 /* Private types -------------------------------------------------------------*/
221 /* Private variables ---------------------------------------------------------*/
222 /* Private constants ---------------------------------------------------------*/
223 /* Private macros ------------------------------------------------------------*/
224 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
225 * @{
226 */
227
228 /** @} */
229
230 /** @} */
231
232 /* Exported functions --------------------------------------------------------*/
233 /** @defgroup GPADC_LL_DRIVER_FUNCTIONS Functions
234 * @{
235 */
236
237 /** @defgroup GPADC_LL_EF_Configuration Basic Configuration
238 * @{
239 */
240
241 /**
242 * @brief Enable GPADC module.
243 *
244 * Register|BitsName
245 * --------|--------
246 * GPADC_CTRL0 | GPADC_CTRL0_ADC_EN_Msk
247 *
248 * @retval None
249 */
250 __STATIC_INLINE void ll_gpadc_enable(void)
251 {
252 SET_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk);
253 }
254
255 /**
256 * @brief Disable ADC module.
257 *
258 * Register|BitsName
259 * --------|--------
260 * GPADC_CTRL0 | GPADC_CTRL0_ADC_EN_Msk
261 *
262 * @retval None
263 */
264 __STATIC_INLINE void ll_gpadc_disable(void)
265 {
266 CLEAR_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk);
267 }
268
269 /**
270 * @brief Check if GPADC module is enabled.
271 *
272 * Register|BitsName
273 * --------|--------
274 * GPADC_CTRL0 | GPADC_CTRL0_ADC_EN_Msk
275 *
276 * @retval State of bit (1 or 0).
277 */
278 __STATIC_INLINE uint32_t ll_gpadc_is_enabled(void)
279 {
280 return (READ_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk) == (GPADC_CTRL0_ADC_EN_Msk));
281 }
282
283 /**
284 * @brief Set GPADC Vref.
285 *
286 * Register|BitsName
287 * --------|--------
288 * ANA_CTRL | GPADC_ANA_CTRL_VREF_SEL
289 *
290 * @param vref_sel value
291 * @retval None
292 */
293 __STATIC_INLINE void ll_gpadc_set_vref_sel(uint32_t vref_sel)
294 {
295 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_VREF_SEL_Msk, vref_sel << GPADC_ANA_CTRL_VREF_SEL_POS);
296 }
297
298 /**
299 * @brief Set GPADC input para.
300 *
301 * Register|BitsName
302 * --------|--------
303 * ANA_CTRL | GPADC_ANA_CTRL_ADC_INPUT GPADC_ANA_CTRL_ADC_INPUT_SEL
304 *
305 * @param input input value
306 * @param input_sel input sel value
307 * @retval None
308 */
309 __STATIC_INLINE void ll_gpadc_set_input_para(uint32_t input,uint32_t input_sel)
310 {
311 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_ADC_INPUT_Msk, input << GPADC_ANA_CTRL_ADC_INPUT_POS);
312 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_ADC_INPUT_SEL_Msk, input_sel << GPADC_ANA_CTRL_ADC_INPUT_SEL_POS);
313 }
314
315 /**
316 * @brief Set GPADC cali sel.
317 *
318 * Register|BitsName
319 * --------|--------
320 * ANA_CTRL | GPADC_ANA_CTRL_CALI_SEL
321 *
322 * @param cali_sel value
323 * @retval None
324 */
325 __STATIC_INLINE void ll_gpadc_set_cali_sel(uint32_t cali_sel)
326 {
327 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CALI_SEL_Msk , cali_sel << GPADC_ANA_CTRL_CALI_SEL_POS);
328 }
329
330 /**
331 * @brief Set GPADC chanel p sel.
332 *
333 * Register|BitsName
334 * --------|--------
335 * ANA_CTRL | GPADC_ANA_CTRL_CH_SEL_P
336 *
337 * @param chp_sel value
338 * @retval None
339 */
340 __STATIC_INLINE void ll_gpadc_set_chp_sel(uint32_t chp_sel)
341 {
342 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CH_SEL_P_Msk , chp_sel << GPADC_ANA_CTRL_CH_SEL_P_POS);
343 }
344
345 /**
346 * @brief Set GPADC chanel n sel.
347 *
348 * Register|BitsName
349 * --------|--------
350 * ANA_CTRL | GPADC_ANA_CTRL_CH_SEL_N
351 *
352 * @param chn_sel value
353 * @retval None
354 */
355 __STATIC_INLINE void ll_gpadc_set_chn_sel(uint32_t chn_sel)
356 {
357 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CH_SEL_N_Msk , chn_sel << GPADC_ANA_CTRL_CH_SEL_N_POS);
358 }
359
360 /**
361 * @brief Set GPADC clock division.
362 *
363 * Register|BitsName
364 * --------|--------
365 * CTRL0 | GPADC_CTRL0_TS_DIV
366 *
367 * @param div division value
368 * @retval None
369 */
370 __STATIC_INLINE void ll_gpadc_set_clk_div(uint32_t div)
371 {
372 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_TS_DIV_Msk, div << GPADC_CTRL0_TS_DIV_POS);
373 }
374
375 /**
376 * @brief Set GPADC data out mode
377 *
378 * Register|BitsName
379 * --------|--------
380 * CTRL0 | GPADC_CTRL0_SAMPLE_MODE
381 *
382 * @param mode 0:output data only once mode 1:output data continually
383 * @retval None
384 */
385 __STATIC_INLINE void ll_gpadc_set_data_out_mode(uint32_t mode)
386 {
387 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_SAMPLE_MODE_Msk, mode << GPADC_CTRL0_SAMPLE_MODE_POS);
388 }
389
390 /**
391 * @brief Set GPADC output data mode,raw data or converted data
392 *
393 * Register|BitsName
394 * --------|--------
395 * CTRL0 | GPADC_CTRL0_CONV_SEL
396 *
397 * @param conv_sel 0:output raw data; sel 1:output converted data
398 * @retval None
399 */
400 __STATIC_INLINE void ll_gpadc_set_conv_sel(uint32_t conv_sel)
401 {
402 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_CONV_SEL_Msk, conv_sel << GPADC_CTRL0_CONV_SEL_POS);
403 }
404
405 /**
406 * @brief Set GPADC vref power down to save power
407 *
408 * Register|BitsName
409 * --------|--------
410 * ANA_CTRL| GPADC_ANA_CTRL_VREF_PD
411 *
412 * @param pd 0:normal work; sel 1:vref power down
413 * @retval None
414 */
415 __STATIC_INLINE void ll_gpadc_set_vref_pd(uint32_t pd)
416 {
417 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_VREF_PD_Msk, pd << GPADC_ANA_CTRL_VREF_PD_POS);
418 }
419
420 /**
421 * @brief Set GPADC whether enter calibration mode or not
422 *
423 * Register|BitsName
424 * --------|--------
425 * CTRL0 | GPADC_CTRL0_CALI_CAP
426 *
427 * @param mode 0:normal mode; mode 1:calibration mode
428 * @retval None
429 */
430 __STATIC_INLINE void ll_gpadc_set_operation_mode(uint32_t mode)
431 {
432 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_CALI_CAP_Msk, mode << GPADC_CTRL0_CALI_CAP_POS);
433 }
434
435 /**
436 * @brief Enable GPADC offset function.
437 *
438 * Register|BitsName
439 * --------|--------
440 * GPADC_OFFSET | GPADC_OFFSET_OFFSET_EN
441 *
442 * @retval None
443 */
444 __STATIC_INLINE void ll_gpadc_offset_enable(void)
445 {
446 SET_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_EN_Msk);
447 }
448
449 /**
450 * @brief Disable GPADC offset function.
451 *
452 * Register|BitsName
453 * --------|--------
454 * GPADC_OFFSET | GPADC_OFFSET_OFFSET_EN
455 *
456 * @retval None
457 */
458 __STATIC_INLINE void ll_gpadc_offset_disable(void)
459 {
460 CLEAR_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_EN_Msk);
461 }
462
463 /**
464 * @brief Enable GPADC offset auto load function.
465 *
466 * Register|BitsName
467 * --------|--------
468 * GPADC_OFFSET | GPADC_OFFSET_OFFSET_AUTO_LOAD
469 *
470 * @retval None
471 */
472 __STATIC_INLINE void ll_gpadc_offset_auto_load_enable(void)
473 {
474 SET_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_AUTO_LOAD_Msk );
475 }
476
477 /**
478 * @brief Disable GPADC offset auto load function.
479 *
480 * Register|BitsName
481 * --------|--------
482 * GPADC_OFFSET | GPADC_OFFSET_OFFSET_AUTO_LOAD
483 *
484 * @retval None
485 */
486 __STATIC_INLINE void ll_gpadc_offset_auto_load_disable(void)
487 {
488 CLEAR_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_AUTO_LOAD_Msk );
489 }
490
491 /**
492 * @brief Return offset value of ADC FIFO.
493 *
494 * Register|BitsName
495 * --------|--------
496 * GPADC_OFFSET | GPADC_OFFSET_OFFSET_VALUE
497 *
498 * @retval Returned offset value can be a value between: 0 ~ ffff
499 */
500 __STATIC_INLINE uint32_t ll_gpadc_get_offset_value(void)
501 {
502 return (uint32_t)(READ_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_VALUE_Msk) >> GPADC_OFFSET_OFFSET_VALUE_POS);
503 }
504
505 /**
506 * @brief Return GPADC value P.
507 *
508 * Register|BitsName
509 * --------|--------
510 * GPADC_DATA | GPADC_DATA_DATA_P
511 *
512 * @retval Returned GPADC value P
513 */
514 __STATIC_INLINE uint32_t ll_gpadc_get_data_p(void)
515 {
516 return (uint32_t)(READ_BITS(GPADC->DATA, GPADC_DATA_DATA_P_Msk) >> GPADC_DATA_DATA_P_POS);
517 }
518
519 /**
520 * @brief Return GPADC value N.
521 *
522 * Register|BitsName
523 * --------|--------
524 * GPADC_DATA | GPADC_DATA_DATA_N
525 *
526 * @retval Return GPADC value N.
527 */
528 __STATIC_INLINE uint32_t ll_gpadc_get_data_n(void)
529 {
530 return (uint32_t)(READ_BITS(GPADC->DATA, GPADC_DATA_DATA_N_Msk) >> GPADC_DATA_DATA_N_POS);
531 }
532
533 /**
534 * @brief Set the value of coefx,x=coef_num,value=coef_value.
535 *
536 * Register|BitsName
537 * --------|--------
538 * GPADC_COEF|
539 *
540 * @param coef_num The numble of coefx
541 * @param coef_value The value of coefx
542 * @retval None
543 */
544 __STATIC_INLINE void ll_gpadc_set_coefx(uint8_t coef_num,uint32_t coef_value)
545 {
546 MODIFY_REG(*(&(GPADC->COEF0)+4*coef_num), GPADC_COEF0_COE0_Msk, coef_value << GPADC_COEF0_COE0_POS);
547 }
548
549 /**
550 * @brief Return the value of coefx,x=coef_num.
551 *
552 * Register|BitsName
553 * --------|--------
554 * GPADC_COEF |
555 *
556 * @param coef_num The numble of coefx
557 * @retval Return the value of coefx,x=coef_num
558 */
559 __STATIC_INLINE uint32_t ll_gpadc_get_coefx(uint8_t coef_num)
560 {
561 return (uint32_t)(READ_BITS(GPADC->COEF0+4*coef_num, GPADC_COEF0_COE0_Msk) >> GPADC_COEF0_COE0_POS);
562 }
563
564 /**
565 * @brief Return samples value of GPADC by reading FIFO.
566 * @note There are two value in the register, both of them is 16bits.
567 *
568 * Register|BitsName
569 * --------|--------
570 *
571 * @retval Smaples value of input
572 */
573 __STATIC_INLINE uint32_t ll_gpadc_read_fifo(void)
574 {
575 return (uint32_t)(READ_REG(GPADC->FIFO_RD));
576 }
577
578 /**
579 * @brief Set threshold of GPADC FIFO.
580 *
581 * Register|BitsName
582 * --------|--------
583 *
584 * @param thresh This parameter can be a value between: 0 ~ 63
585 * @retval None
586 */
587 __STATIC_INLINE void ll_gpadc_set_thresh(uint32_t thresh)
588 {
589 MODIFY_REG(GPADC->FIFO_THD, GPADC_FIFO_THD_Msk, (thresh & 0x3F) << GPADC_FIFO_THD_POS);
590 }
591
592 /**
593 * @brief Check if GPADC FIFO is not empty.
594 *
595 * Register|BitsName
596 * --------|--------
597 *
598 * @retval State of bit (1 or 0).
599 */
600 __STATIC_INLINE uint32_t ll_gpadc_is_fifo_notempty(void)
601 {
602 return (uint32_t)(READ_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_VALID) == GPADC_FIFO_STAT_VALID);
603 }
604
605 /**
606 * @brief Return count of GPADC FIFO.
607 *
608 * Register|BitsName
609 * --------|--------
610 *
611 * @retval Returned value can be a value between: 0 ~ 64
612 */
613 __STATIC_INLINE uint32_t ll_gpadc_get_fifo_count(void)
614 {
615 return (uint32_t)(READ_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_COUNT) >> GPADC_FIFO_STAT_COUNT_POS);
616 }
617
618 /**
619 * @brief Flush GPADC FIFO.
620 *
621 * Register|BitsName
622 * --------|--------
623 *
624 * @retval void
625 */
626 __STATIC_INLINE void ll_gpadc_flush_fifo(void)
627 {
628 SET_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_FLUSH_Msk);
629 CLEAR_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_FLUSH_Msk);
630 }
631
632 /**
633 * @brief Set the value of ldo23
634 *
635 * Register|BitsName
636 * --------|--------
637 *
638 * @param value The value of ldo23
639 */
640 __STATIC_INLINE void ll_gpadc_set_ldo23(uint32_t value)
641 {
642 MODIFY_REG(GPADC->ANA_MBG, GPADC_ANA_MBG_LDO23_SEL_Msk, value << GPADC_ANA_MBG_LDO23_SEL_POS);
643 }
644
645 /**
646 * @brief Enable PGA.
647 *
648 * Register|BitsName
649 * --------|--------
650 *
651 * @retval None
652 */
653 __STATIC_INLINE void ll_gpadc_pga_enable(void)
654 {
655 CLEAR_BITS(GPADC->ANA_PGA, GPADC_ANA_PGA_PD_Msk);
656 }
657
658 /**
659 * @brief Disable PGA.
660 *
661 * Register|BitsName
662 * --------|--------
663 *
664 * @retval None
665 */
666 __STATIC_INLINE void ll_gpadc_pga_disable(void)
667 {
668 SET_BITS(GPADC->ANA_PGA, GPADC_ANA_PGA_PD_Msk);
669 }
670 /**
671 * @brief Set the value of PGA Gain
672 *
673 * Register|BitsName
674 * --------|--------
675 *
676 *
677 * @param value The value of PGA Gain
678 */
679 __STATIC_INLINE void ll_gpadc_set_gain(uint32_t value)
680 {
681 MODIFY_REG(GPADC->ANA_PGA, GPADC_ANA_PGA_GAIN_CTRL_Msk, value << GPADC_ANA_PGA_GAIN_CTRL_POS);
682 }
683
684 /*
685 **
686 * @brief De-initialize GPADC registers (Registers restored to their default values).
687 * @retval An error_status_t enumeration value:
688 * - SUCCESS: GPADC registers are de-initialized
689 * - ERROR: GPADC registers are not de-initialized
690 */
691 error_status_t ll_gpadc_deinit(void);
692
693 /**
694 * @brief Initialize GPADC registers according to the specified.
695 * parameters in p_gpadc_init.
696 * @param p_gpadc_init Pointer to a ll_gpadc_init_t structure that contains the configuration
697 * information for the specified GPADC peripheral.
698 * @retval An error_status_t enumeration value:
699 * - SUCCESS: GPADC registers are initialized according to p_gpadc_init content
700 * - ERROR: Problem occurred during GPADC Registers initialization
701 */
702 error_status_t ll_gpadc_init(ll_gpadc_init_t *p_gpadc_init);
703
704 /**
705 * @brief Set each field of a @ref ll_gpadc_init_t type structure to default value.
706 * @param p_gpadc_init Pointer to a @ref ll_gpadc_init_t structure
707 * whose fields will be set to default values.
708 * @retval None
709 */
710 void ll_gpadc_struct_init(ll_gpadc_init_t *p_gpadc_init);
711
712 /** @} */
713
714 /** @} */
715
716 #endif /* AON */
717
718 #ifdef __cplusplus
719 }
720 #endif
721
722 #endif /* __GR55XX_LL_ADC_H__ */
723
724 /** @} */
725
726 /** @} */
727
728 /** @} */