gr55xx_ll_spi.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (SPIM) || defined (SPIS)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
87
88 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
89 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
90
91 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
92
93 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
94 This parameter can be a value of @ref SPI_LL_EC_PHASE.
95
96 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
97
98 uint32_t slave_select; /**< Specifies the SPI slave select.
99 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
100
101 This feature can be modified afterwards using unitary function @ref ll_spi_enable_ss().*/
102
103 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
104 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
105 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
108 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
109 This parameter can be a number between 0 and 0x7 */
110 } ll_spim_init_t;
111
112 /**
113 * @brief SPIS init structures definition
114 */
115 typedef struct _ll_spis_init_t
116 {
117 uint32_t data_size; /**< Specifies the SPI data width.
118 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
119
120 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
121
122 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
123 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
124
125 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
126
127 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
128 This parameter can be a value of @ref SPI_LL_EC_PHASE.
129
130 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
131
132 } ll_spis_init_t;
133
134 /** @} */
135
136 /** @} */
137
138 /**
139 * @defgroup SPI_LL_MACRO Defines
140 * @{
141 */
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
145 * @{
146 */
147
148 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
149 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
150 * @{
151 */
152 #define LL_SPI_SR_DCOL SPI_STAT_DATA_COLN_ERR /**< Data collision error flag */
153 #define LL_SPI_SR_TXE SPI_STAT_TX_ERR /**< Transmission error flag */
154 #define LL_SPI_SR_RFF SPI_STAT_RX_FIFO_FULL /**< Rx FIFO full flag */
155 #define LL_SPI_SR_RFNE SPI_STAT_RX_FIFO_NE /**< Rx FIFO not empty flag */
156 #define LL_SPI_SR_TFE SPI_STAT_TX_FIFO_EMPTY /**< Tx FIFO empty flag */
157 #define LL_SPI_SR_TFNF SPI_STAT_TX_FIFO_NF /**< Tx FIFO not full flag */
158 #define LL_SPI_SR_BUSY SPI_STAT_SSI_BUSY /**< Busy flag */
159 /** @} */
160
161 /** @defgroup SPI_LL_EC_IT IT Defines
162 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
163 * @{
164 */
165 #define LL_SPI_IM_MST SPI_INT_MASK_MULTI_M_CIM /**< Multi-Master Contention Interrupt enable */
166 #define LL_SPI_IM_RXF SPI_INT_MASK_RX_FIFO_FIM /**< Receive FIFO Full Interrupt enable */
167 #define LL_SPI_IM_RXO SPI_INT_MASK_RX_FIFO_OIM /**< Receive FIFO Overflow Interrupt enable */
168 #define LL_SPI_IM_RXU SPI_INT_MASK_RX_FIFO_UIM /**< Receive FIFO Underflow Interrupt enable */
169 #define LL_SPI_IM_TXO SPI_INT_MASK_TX_FIFO_OIM /**< Transmit FIFO Overflow Interrupt enable */
170 #define LL_SPI_IM_TXE SPI_INT_MASK_TX_FIFO_EIM /**< Transmit FIFO Empty Interrupt enable */
171
172 #define LL_SPI_IS_MST SPI_INT_STAT_MULTI_M_CIS /**< Multi-Master Contention Interrupt flag */
173 #define LL_SPI_IS_RXF SPI_INT_STAT_RX_FIFO_FIS /**< Receive FIFO Full Interrupt flag */
174 #define LL_SPI_IS_RXO SPI_INT_STAT_RX_FIFO_OIS /**< Receive FIFO Overflow Interrupt flag */
175 #define LL_SPI_IS_RXU SPI_INT_STAT_RX_FIFO_UIS /**< Receive FIFO Underflow Interrupt flag */
176 #define LL_SPI_IS_TXO SPI_INT_STAT_TX_FIFO_OIS /**< Transmit FIFO Overflow Interrupt flag */
177 #define LL_SPI_IS_TXE SPI_INT_STAT_TX_FIFO_EIS /**< Transmit FIFO Empty Interrupt flag */
178
179 #define LL_SPI_RIS_MST SPI_RAW_INT_STAT_MULTI_M_CRIS /**< Multi-Master Contention RAW Interrupt flag */
180 #define LL_SPI_RIS_RXF SPI_RAW_INT_STAT_RX_FIFO_FRIS /**< Receive FIFO Full RAW Interrupt flag */
181 #define LL_SPI_RIS_RXO SPI_RAW_INT_STAT_RX_FIFO_ORIS /**< Receive FIFO Overflow RAW Interrupt flag */
182 #define LL_SPI_RIS_RXU SPI_RAW_INT_STAT_RX_FIFO_URIS /**< Receive FIFO Underflow RAW Interrupt flag */
183 #define LL_SPI_RIS_TXO SPI_RAW_INT_STAT_TX_FIFO_ORIS /**< Transmit FIFO Overflow RAW Interrupt flag */
184 #define LL_SPI_RIS_TXE SPI_RAW_INT_STAT_TX_FIFO_ERIS /**< Transmit FIFO Empty RAW Interrupt flag */
185 /** @} */
186
187 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
188 * @{
189 */
190 #define LL_SPI_DATASIZE_4BIT (3UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 4 bits */
191 #define LL_SPI_DATASIZE_5BIT (4UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 5 bits */
192 #define LL_SPI_DATASIZE_6BIT (5UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 6 bits */
193 #define LL_SPI_DATASIZE_7BIT (6UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 7 bits */
194 #define LL_SPI_DATASIZE_8BIT (7UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 8 bits */
195 #define LL_SPI_DATASIZE_9BIT (8UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 9 bits */
196 #define LL_SPI_DATASIZE_10BIT (9UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 10 bits */
197 #define LL_SPI_DATASIZE_11BIT (10UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 11 bits */
198 #define LL_SPI_DATASIZE_12BIT (11UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 12 bits */
199 #define LL_SPI_DATASIZE_13BIT (12UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 13 bits */
200 #define LL_SPI_DATASIZE_14BIT (13UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 14 bits */
201 #define LL_SPI_DATASIZE_15BIT (14UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 15 bits */
202 #define LL_SPI_DATASIZE_16BIT (15UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 16 bits */
203 #define LL_SPI_DATASIZE_17BIT (16UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 17 bits */
204 #define LL_SPI_DATASIZE_18BIT (17UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 18 bits */
205 #define LL_SPI_DATASIZE_19BIT (18UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 19 bits */
206 #define LL_SPI_DATASIZE_20BIT (19UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 20 bits */
207 #define LL_SPI_DATASIZE_21BIT (20UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 21 bits */
208 #define LL_SPI_DATASIZE_22BIT (21UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 22 bits */
209 #define LL_SPI_DATASIZE_23BIT (22UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 23 bits */
210 #define LL_SPI_DATASIZE_24BIT (23UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 24 bits */
211 #define LL_SPI_DATASIZE_25BIT (24UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 25 bits */
212 #define LL_SPI_DATASIZE_26BIT (25UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 26 bits */
213 #define LL_SPI_DATASIZE_27BIT (26UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 27 bits */
214 #define LL_SPI_DATASIZE_28BIT (27UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 28 bits */
215 #define LL_SPI_DATASIZE_29BIT (28UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 29 bits */
216 #define LL_SPI_DATASIZE_30BIT (29UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 30 bits */
217 #define LL_SPI_DATASIZE_31BIT (30UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 31 bits */
218 #define LL_SPI_DATASIZE_32BIT (31UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 32 bits */
219 /** @} */
220
221 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
222 * @{
223 */
224 #define LL_SPI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
225 #define LL_SPI_MW_CMDSIZE_2BIT (1UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 2 bits */
226 #define LL_SPI_MW_CMDSIZE_3BIT (2UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 3 bits */
227 #define LL_SPI_MW_CMDSIZE_4BIT (3UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 4 bits */
228 #define LL_SPI_MW_CMDSIZE_5BIT (4UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 5 bits */
229 #define LL_SPI_MW_CMDSIZE_6BIT (5UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 6 bits */
230 #define LL_SPI_MW_CMDSIZE_7BIT (6UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 7 bits */
231 #define LL_SPI_MW_CMDSIZE_8BIT (7UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 8 bits */
232 #define LL_SPI_MW_CMDSIZE_9BIT (8UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 9 bits */
233 #define LL_SPI_MW_CMDSIZE_10BIT (9UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 10 bits */
234 #define LL_SPI_MW_CMDSIZE_11BIT (10UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 11 bits */
235 #define LL_SPI_MW_CMDSIZE_12BIT (11UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 12 bits */
236 #define LL_SPI_MW_CMDSIZE_13BIT (12UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 13 bits */
237 #define LL_SPI_MW_CMDSIZE_14BIT (13UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 14 bits */
238 #define LL_SPI_MW_CMDSIZE_15BIT (14UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 15 bits */
239 #define LL_SPI_MW_CMDSIZE_16BIT (15UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 16 bits */
240 /** @} */
241
242 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
243 * @{
244 */
245 #define LL_SPI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
246 #define LL_SPI_TEST_MODE (1UL << SPI_CTRL0_SHIFT_REG_LOOP_POS) /**< Test mode for SPI transfer: Rx and Tx connected inside */
247 /** @} */
248
249 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
250 * @{
251 */
252 #define LL_SPI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
253 #define LL_SPI_SLAVE_OUTEN (1UL << SPI_CTRL0_S_OUT_EN_POS) /**< Output disable for SPI transfer as slave */
254 /** @} */
255
256 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
257 * @{
258 */
259 #define LL_SPI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
260 #define LL_SPI_SIMPLEX_TX (1UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Tx mode. Tx transfer only on 1 line */
261 #define LL_SPI_SIMPLEX_RX (2UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Rx mode. Rx transfer only on 1 line */
262 #define LL_SPI_READ_EEPROM (3UL << SPI_CTRL0_XFE_MODE_POS) /**< Read EEPROM mode. Rx transfer only on 1 line */
263 /** @} */
264
265 /** @defgroup SPI_LL_EC_PHASE Clock Phase
266 * @{
267 */
268 #define LL_SPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
269 #define LL_SPI_SCPHA_2EDGE (1UL << SPI_CTRL0_SERIAL_CLK_PHASE_POS) /**< Second clock transition is the first data capture edge */
270 /** @} */
271
272 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
273 * @{
274 */
275 #define LL_SPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
276 #define LL_SPI_SCPOL_HIGH (1UL << SPI_CTRL0_SERIAL_CLK_POL_POS) /**< Clock to 1 when idle */
277 /** @} */
278
279 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
280 * @{
281 */
282 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
283 #define LL_SPI_PROTOCOL_TI (1UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< TI mode */
284 #define LL_SPI_PROTOCOL_MICROWIRE (2UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< Microwire mode */
285 /** @} */
286
287 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
288 * @{
289 */
290 #define LL_SPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
291 #define LL_SPI_MICROWIRE_HANDSHAKE_EN (1UL << SPI_MW_CTRL_MW_HSG_POS) /**< Disable Handshake for Microwire transfer */
292
293 #define LL_SPI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
294 #define LL_SPI_MICROWIRE_TX (1UL << SPI_MW_CTRL_MW_DIR_DW_POS) /**< Tx mode. Tx transfer at Microwire mode */
295
296 #define LL_SPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
297 #define LL_SPI_MICROWIRE_SEQUENTIAL (1UL << SPI_MW_CTRL_MW_XFE_MODE_POS) /**< Sequential for Microwire transfer */
298 /** @} */
299
300 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
301 * @{
302 */
303 #define LL_SPI_SLAVE1 SPI_SLA_S1_SEL_EN /**< Enable slave1 select pin for SPI transfer */
304 #define LL_SPI_SLAVE0 SPI_SLA_S0_SEL_EN /**< Enable slave0 select pin for SPI transfer */
305 /** @} */
306
307 /** @defgroup SPI_LL_EC_DMA DMA Defines
308 * @{
309 */
310 #define LL_SPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
311 #define LL_SPI_DMA_TX_EN SPI_DMA_CTRL_TX_DMA_EN /**< Enable the transmit FIFO DMA channel */
312
313 #define LL_SPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
314 #define LL_SPI_DMA_RX_EN SPI_DMA_CTRL_RX_DMA_EN /**< Enable the receive FIFO DMA channel */
315 /** @} */
316
317 /** @defgroup LL_SPI_x_FIFO_DEPTH Defines
318 * @{
319 */
320 #define LL_SPI_M_FIFO_DEPTH (16u) /**< FIFO Depth for SPI Master */
321 #define LL_SPI_S_FIFO_DEPTH (16u) /**< FIFO Depth for SPI Slave */
322 /** @} */
323
324 /**
325 * @brief LL SPIM InitStrcut default configuartion
326 */
327 #define LL_SPIM_DEFAULT_CONFIG \
328 { \
329 .transfer_direction = LL_SPI_FULL_DUPLEX, \
330 .data_size = LL_SPI_DATASIZE_8BIT, \
331 .clock_polarity = LL_SPI_SCPOL_LOW, \
332 .clock_phase = LL_SPI_SCPHA_1EDGE, \
333 .slave_select = LL_SPI_SLAVE0, \
334 .baud_rate = SystemCoreClock / 2000000, \
335 .rx_sample_delay = 0, \
336 }
337
338 /**
339 * @brief LL SPIS InitStrcut default configuartion
340 */
341 #define LL_SPIS_DEFAULT_CONFIG \
342 { \
343 .data_size = LL_SPI_DATASIZE_8BIT, \
344 .clock_polarity = LL_SPI_SCPOL_LOW, \
345 .clock_phase = LL_SPI_SCPHA_1EDGE, \
346 }
347 /** @} */
348
349 /* Exported macro ------------------------------------------------------------*/
350 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
351 * @{
352 */
353
354 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
355 * @{
356 */
357
358 /**
359 * @brief Write a value in SPI register
360 * @param __instance__ SPI instance
361 * @param __REG__ Register to be written
362 * @param __VALUE__ Value to be written in the register
363 * @retval None
364 */
365 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
366
367 /**
368 * @brief Read a value in SPI register
369 * @param __instance__ SPI instance
370 * @param __REG__ Register to be read
371 * @retval Register value
372 */
373 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
374
375 /** @} */
376
377 /** @} */
378
379 /** @} */
380
381 /* Exported functions --------------------------------------------------------*/
382 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
383 * @{
384 */
385
386 /** @defgroup SPI_LL_EF_Configuration Configuration functions
387 * @{
388 */
389
390 /**
391 * @brief Enable slave select toggle
392 * @note This bit should not be changed when communication is ongoing.
393 *
394 * Register|BitsName
395 * --------|--------
396 * CTRL0 | SSTEN
397 *
398 * @param SPIx SPI instance
399 * @retval None
400 */
401 __STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
402 {
403 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
404 }
405
406 /**
407 * @brief Disable slave select toggle
408 * @note This bit should not be changed when communication is ongoing.
409 *
410 * Register|BitsName
411 * --------|--------
412 * CTRL0 | SSTEN
413 *
414 * @param SPIx SPI instance
415 * @retval None
416 */
417 __STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
418 {
419 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
420 }
421
422 /**
423 * @brief Check if slave select toggle is enabled
424 * @note This bit should not be changed when communication is ongoing.
425 *
426 * Register|BitsName
427 * --------|--------
428 * CTRL0 | SSTEN
429 *
430 * @param SPIx SPI instance
431 * @retval State of bit (1 or 0).
432 */
433 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
434 {
435 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN) == (SPI_CTRL0_S_ST_EN));
436 }
437
438 /**
439 * @brief Set frame data size
440 *
441 * Register|BitsName
442 * --------|--------
443 * CTRL0 | DFS32
444 *
445 * @param SPIx SPI instance
446 * @param size This parameter can be one of the following values:
447 * @arg @ref LL_SPI_DATASIZE_4BIT
448 * @arg @ref LL_SPI_DATASIZE_5BIT
449 * @arg @ref LL_SPI_DATASIZE_6BIT
450 * @arg @ref LL_SPI_DATASIZE_7BIT
451 * @arg @ref LL_SPI_DATASIZE_8BIT
452 * @arg @ref LL_SPI_DATASIZE_9BIT
453 * @arg @ref LL_SPI_DATASIZE_10BIT
454 * @arg @ref LL_SPI_DATASIZE_11BIT
455 * @arg @ref LL_SPI_DATASIZE_12BIT
456 * @arg @ref LL_SPI_DATASIZE_13BIT
457 * @arg @ref LL_SPI_DATASIZE_14BIT
458 * @arg @ref LL_SPI_DATASIZE_15BIT
459 * @arg @ref LL_SPI_DATASIZE_16BIT
460 * @arg @ref LL_SPI_DATASIZE_17BIT
461 * @arg @ref LL_SPI_DATASIZE_18BIT
462 * @arg @ref LL_SPI_DATASIZE_19BIT
463 * @arg @ref LL_SPI_DATASIZE_20BIT
464 * @arg @ref LL_SPI_DATASIZE_21BIT
465 * @arg @ref LL_SPI_DATASIZE_22BIT
466 * @arg @ref LL_SPI_DATASIZE_23BIT
467 * @arg @ref LL_SPI_DATASIZE_24BIT
468 * @arg @ref LL_SPI_DATASIZE_25BIT
469 * @arg @ref LL_SPI_DATASIZE_26BIT
470 * @arg @ref LL_SPI_DATASIZE_27BIT
471 * @arg @ref LL_SPI_DATASIZE_28BIT
472 * @arg @ref LL_SPI_DATASIZE_29BIT
473 * @arg @ref LL_SPI_DATASIZE_30BIT
474 * @arg @ref LL_SPI_DATASIZE_31BIT
475 * @arg @ref LL_SPI_DATASIZE_32BIT
476 * @retval None
477 */
478 __STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
479 {
480 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE, size);
481 }
482
483 /**
484 * @brief Get frame data size
485 *
486 * Register|BitsName
487 * --------|--------
488 * CTRL0 | DFS32
489 *
490 * @param SPIx SPI instance
491 * @retval Returned value can be one of the following values:
492 * @arg @ref LL_SPI_DATASIZE_4BIT
493 * @arg @ref LL_SPI_DATASIZE_5BIT
494 * @arg @ref LL_SPI_DATASIZE_6BIT
495 * @arg @ref LL_SPI_DATASIZE_7BIT
496 * @arg @ref LL_SPI_DATASIZE_8BIT
497 * @arg @ref LL_SPI_DATASIZE_9BIT
498 * @arg @ref LL_SPI_DATASIZE_10BIT
499 * @arg @ref LL_SPI_DATASIZE_11BIT
500 * @arg @ref LL_SPI_DATASIZE_12BIT
501 * @arg @ref LL_SPI_DATASIZE_13BIT
502 * @arg @ref LL_SPI_DATASIZE_14BIT
503 * @arg @ref LL_SPI_DATASIZE_15BIT
504 * @arg @ref LL_SPI_DATASIZE_16BIT
505 * @arg @ref LL_SPI_DATASIZE_17BIT
506 * @arg @ref LL_SPI_DATASIZE_18BIT
507 * @arg @ref LL_SPI_DATASIZE_19BIT
508 * @arg @ref LL_SPI_DATASIZE_20BIT
509 * @arg @ref LL_SPI_DATASIZE_21BIT
510 * @arg @ref LL_SPI_DATASIZE_22BIT
511 * @arg @ref LL_SPI_DATASIZE_23BIT
512 * @arg @ref LL_SPI_DATASIZE_24BIT
513 * @arg @ref LL_SPI_DATASIZE_25BIT
514 * @arg @ref LL_SPI_DATASIZE_26BIT
515 * @arg @ref LL_SPI_DATASIZE_27BIT
516 * @arg @ref LL_SPI_DATASIZE_28BIT
517 * @arg @ref LL_SPI_DATASIZE_29BIT
518 * @arg @ref LL_SPI_DATASIZE_30BIT
519 * @arg @ref LL_SPI_DATASIZE_31BIT
520 * @arg @ref LL_SPI_DATASIZE_32BIT
521 */
522 __STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
523 {
524 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE));
525 }
526
527 /**
528 * @brief Set the length of the control word for the Microwire frame format
529 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
530 *
531 * Register|BitsName
532 * --------|--------
533 * CTRL0 | CFS
534 *
535 * @param SPIx SPI instance
536 * @param size This parameter can be one of the following values:
537 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
538 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
539 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
540 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
541 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
542 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
543 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
544 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
545 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
546 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
547 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
548 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
549 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
550 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
551 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
552 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
553 * @retval None
554 */
555 __STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
556 {
557 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE, size);
558 }
559
560 /**
561 * @brief Get the length of the control word for the Microwire frame format
562 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
563 *
564 * Register|BitsName
565 * --------|--------
566 * CTRL0 | CFS
567 *
568 * @param SPIx SPI instance
569 * @retval Returned value can be one of the following values:
570 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
571 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
572 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
573 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
574 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
575 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
576 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
577 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
578 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
579 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
580 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
581 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
582 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
583 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
584 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
585 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
586 */
587 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
588 {
589 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE));
590 }
591
592 /**
593 * @brief Enable SPI test mode
594 *
595 * Register|BitsName
596 * --------|--------
597 * CTRL0 | SRL
598 *
599 * @param SPIx SPI instance
600 * @retval None
601 */
602 __STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
603 {
604 SET_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
605 }
606
607 /**
608 * @brief Disable SPI test mode
609 *
610 * Register|BitsName
611 * --------|--------
612 * CTRL0 | SRL
613 *
614 * @param SPIx SPI instance
615 * @retval None
616 */
617 __STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
618 {
619 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
620 }
621
622 /**
623 * @brief Check if SPI test mode is enabled
624 *
625 * Register|BitsName
626 * --------|--------
627 * CTRL0 | SRL
628 *
629 * @param SPIx SPI instance
630 * @retval State of bit (1 or 0).
631 */
632 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
633 {
634 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP) == (SPI_CTRL0_SHIFT_REG_LOOP));
635 }
636
637 /**
638 * @brief Enable slave output
639 *
640 * Register|BitsName
641 * --------|--------
642 * CTRL0 | SLVOE
643 *
644 * @param SPIx SPI instance
645 * @retval None
646 */
647 __STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
648 {
649 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
650 }
651
652 /**
653 * @brief Disable slave output
654 *
655 * Register|BitsName
656 * --------|--------
657 * CTRL0 | SLVOE
658 *
659 * @param SPIx SPI instance
660 * @retval None
661 */
662 __STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
663 {
664 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
665 }
666
667 /**
668 * @brief Check if slave output is enabled
669 *
670 * Register|BitsName
671 * --------|--------
672 * CTRL0 | SLVOE
673 *
674 * @param SPIx SPI instance
675 * @retval State of bit (1 or 0).
676 */
677 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
678 {
679 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN) != (SPI_CTRL0_S_OUT_EN));
680 }
681
682 /**
683 * @brief Set transfer direction mode
684 *
685 * Register|BitsName
686 * --------|--------
687 * CTRL0 | TMOD
688 *
689 * @param SPIx SPI instance
690 * @param transfer_direction This parameter can be one of the following values:
691 * @arg @ref LL_SPI_FULL_DUPLEX
692 * @arg @ref LL_SPI_SIMPLEX_TX
693 * @arg @ref LL_SPI_SIMPLEX_RX
694 * @arg @ref LL_SPI_READ_EEPROM
695 * @retval None
696 */
697 __STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
698 {
699 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_XFE_MODE, transfer_direction);
700 }
701
702 /**
703 * @brief Get transfer direction mode
704 *
705 * Register|BitsName
706 * --------|--------
707 * CTRL0 | TMOD
708 *
709 * @param SPIx SPI instance
710 * @retval Returned value can be one of the following values:
711 * @arg @ref LL_SPI_FULL_DUPLEX
712 * @arg @ref LL_SPI_SIMPLEX_TX
713 * @arg @ref LL_SPI_SIMPLEX_RX
714 * @arg @ref LL_SPI_READ_EEPROM
715 */
716 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
717 {
718 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_XFE_MODE));
719 }
720
721 /**
722 * @brief Set clock polarity
723 * @note This bit should not be changed when communication is ongoing.
724 * This bit is not used in SPI TI mode.
725 *
726 * Register|BitsName
727 * --------|--------
728 * CTRL0 | SCPOL
729 *
730 * @param SPIx SPI instance
731 * @param clock_polarity This parameter can be one of the following values:
732 * @arg @ref LL_SPI_SCPOL_LOW
733 * @arg @ref LL_SPI_SCPOL_HIGH
734 * @retval None
735 */
736 __STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
737 {
738 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL, clock_polarity);
739 }
740
741 /**
742 * @brief Get clock polarity
743 *
744 * Register|BitsName
745 * --------|--------
746 * CTRL0 | SCPOL
747 *
748 * @param SPIx SPI instance
749 * @retval Returned value can be one of the following values:
750 * @arg @ref LL_SPI_SCPOL_LOW
751 * @arg @ref LL_SPI_SCPOL_HIGH
752 */
753 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
754 {
755 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL));
756 }
757
758 /**
759 * @brief Set clock phase
760 * @note This bit should not be changed when communication is ongoing.
761 * This bit is not used in SPI TI mode.
762 *
763 * Register|BitsName
764 * --------|--------
765 * CTRL0 | SCPHA
766 *
767 * @param SPIx SPI instance
768 * @param clock_phase This parameter can be one of the following values:
769 * @arg @ref LL_SPI_SCPHA_1EDGE
770 * @arg @ref LL_SPI_SCPHA_2EDGE
771 * @retval None
772 */
773 __STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
774 {
775 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE, clock_phase);
776 }
777
778 /**
779 * @brief Get clock phase
780 *
781 * Register|BitsName
782 * --------|--------
783 * CTRL0 | SCPHA
784 *
785 * @param SPIx SPI instance
786 * @retval Returned value can be one of the following values:
787 * @arg @ref LL_SPI_SCPHA_1EDGE
788 * @arg @ref LL_SPI_SCPHA_2EDGE
789 */
790 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
791 {
792 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE));
793 }
794
795 /**
796 * @brief Set serial protocol used
797 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
798 *
799 * Register|BitsName
800 * --------|--------
801 * CTRL0 | FRF
802 *
803 * @param SPIx SPI instance
804 * @param standard This parameter can be one of the following values:
805 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
806 * @arg @ref LL_SPI_PROTOCOL_TI
807 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
808 * @retval None
809 */
810 __STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
811 {
812 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT, standard);
813 }
814
815 /**
816 * @brief Get serial protocol used
817 *
818 * Register|BitsName
819 * --------|--------
820 * CTRL0 | FRF
821 *
822 * @param SPIx SPI instance
823 * @retval Returned value can be one of the following values:
824 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
825 * @arg @ref LL_SPI_PROTOCOL_TI
826 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
827 */
828 __STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
829 {
830 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT));
831 }
832
833 /**
834 * @brief Set the number of data frames to be continuously received
835 * @note These bits should not be changed when communication is ongoing.
836 This bits are effect when TMOD = 2b10 or 2b11.
837 This bits are not effect in SPIS.
838 *
839 * Register|BitsName
840 * --------|--------
841 * CTRL1 | NDF
842 *
843 * @param SPIx SPI instance
844 * @param size This parameter can be one of the following values: 0 ~ 65535
845 * @retval None
846 */
847 __STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
848 {
849 MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME, size);
850 }
851
852 /**
853 * @brief Get the number of data frames to be continuously received
854 * @note These bits should not be changed when communication is ongoing.
855 This bits are effect when TMOD = 2b10 or 2b11.
856 This bits are not effect in SPIS.
857 *
858 * Register|BitsName
859 * --------|--------
860 * CTRL1 | NDF
861 *
862 * @param SPIx SPI instance
863 * @retval Returned value can be one of the following values: 0 ~ 65535
864 */
865 __STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
866 {
867 return (uint32_t)(READ_BITS(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME));
868 }
869
870 /**
871 * @brief Enable SPI peripheral
872 *
873 * Register|BitsName
874 * --------|--------
875 * SSI_EN | EN
876 *
877 * @param SPIx SPI instance
878 * @retval None
879 */
880 __STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
881 {
882 SET_BITS(SPIx->SSI_EN, SPI_SSI_EN);
883 }
884
885 /**
886 * @brief Disable SPI peripheral
887 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
888 *
889 * Register|BitsName
890 * --------|--------
891 * SSI_EN | EN
892 *
893 * @param SPIx SPI instance
894 * @retval None
895 */
896 __STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
897 {
898 CLEAR_BITS(SPIx->SSI_EN, SPI_SSI_EN);
899 }
900
901 /**
902 * @brief Check if SPI peripheral is enabled
903 *
904 * Register|BitsName
905 * --------|--------
906 * SSI_EN | EN
907 *
908 * @param SPIx SPI instance
909 * @retval State of bit (1 or 0).
910 */
911 __STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
912 {
913 return (READ_BITS(SPIx->SSI_EN, SPI_SSI_EN) == (SPI_SSI_EN));
914 }
915
916 /**
917 * @brief Enable Handshake in Microwire mode
918 *
919 * Register|BitsName
920 * --------|--------
921 * MWC | MHS
922 *
923 * @param SPIx SPI instance
924 * @retval None
925 */
926 __STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
927 {
928 SET_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
929 }
930
931 /**
932 * @brief Disable Handshake in Microwire mode
933 *
934 * Register|BitsName
935 * --------|--------
936 * MWC | MHS
937 *
938 * @param SPIx SPI instance
939 * @retval None
940 */
941 __STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
942 {
943 CLEAR_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
944 }
945
946 /**
947 * @brief Check if Handshake in Microwire mode is enabled
948 *
949 * Register|BitsName
950 * --------|--------
951 * MWC | MHS
952 *
953 * @param SPIx SPI instance
954 * @retval State of bit (1 or 0).
955 */
956 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
957 {
958 return (READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG) == (SPI_MW_CTRL_MW_HSG));
959 }
960
961 /**
962 * @brief Set transfer direction mode in Microwire mode
963 * @note This bit should not be changed when communication is ongoing.
964 *
965 * Register|BitsName
966 * --------|--------
967 * MWC | MDD
968 *
969 * @param SPIx SPI instance
970 * @param transfer_direction This parameter can be one of the following values:
971 * @arg @ref LL_SPI_MICROWIRE_RX
972 * @arg @ref LL_SPI_MICROWIRE_TX
973 * @retval None
974 */
975 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
976 {
977 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW, transfer_direction);
978 }
979
980 /**
981 * @brief Get transfer direction mode in Microwire mode
982 * @note This bit should not be changed when communication is ongoing.
983 *
984 * Register|BitsName
985 * --------|--------
986 * MWC | MDD
987 *
988 * @param SPIx SPI instance
989 * @retval Returned value can be one of the following values:
990 * @arg @ref LL_SPI_MICROWIRE_RX
991 * @arg @ref LL_SPI_MICROWIRE_TX
992 */
993 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
994 {
995 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW));
996 }
997
998 /**
999 * @brief Set transfer mode in Microwire mode
1000 * @note This bit should not be changed when communication is ongoing.
1001 *
1002 * Register|BitsName
1003 * --------|--------
1004 * MWC | MWMOD
1005 *
1006 * @param SPIx SPI instance
1007 * @param transfer_mode This parameter can be one of the following values:
1008 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1009 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1010 * @retval None
1011 */
1012 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
1013 {
1014 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE, transfer_mode);
1015 }
1016
1017 /**
1018 * @brief Get transfer mode in Microwire mode
1019 * @note This bit should not be changed when communication is ongoing.
1020 *
1021 * Register|BitsName
1022 * --------|--------
1023 * MWC | MWMOD
1024 *
1025 * @param SPIx SPI instance
1026 * @retval Returned value can be one of the following values:
1027 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1028 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1029 */
1030 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
1031 {
1032 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE));
1033 }
1034
1035 /**
1036 * @brief Enable slave select
1037 *
1038 * Register|BitsName
1039 * --------|--------
1040 * SE | SLAVE1
1041 * SE | SLAVE0
1042 *
1043 * @param SPIx SPI instance
1044 * @param ss This parameter can be one of the following values:
1045 * @arg @ref LL_SPI_SLAVE1
1046 * @arg @ref LL_SPI_SLAVE0
1047 * @retval None
1048 */
1049 __STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
1050 {
1051 SET_BITS(SPIx->S_EN, ss);
1052 }
1053
1054 /**
1055 * @brief Disable slave select
1056 *
1057 * Register|BitsName
1058 * --------|--------
1059 * SE | SLAVE1
1060 * SE | SLAVE0
1061 *
1062 * @param SPIx SPI instance
1063 * @param ss This parameter can be one of the following values:
1064 * @arg @ref LL_SPI_SLAVE1
1065 * @arg @ref LL_SPI_SLAVE0
1066 * @retval None
1067 */
1068 __STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
1069 {
1070 CLEAR_BITS(SPIx->S_EN, ss);
1071 }
1072
1073 /**
1074 * @brief Check if slave select is enabled
1075 *
1076 * Register|BitsName
1077 * --------|--------
1078 * SE | SLAVE1
1079 * SE | SLAVE0
1080 *
1081 * @param SPIx SPI instance
1082 * @param ss This parameter can be one of the following values:
1083 * @arg @ref LL_SPI_SLAVE1
1084 * @arg @ref LL_SPI_SLAVE0
1085 * @retval State of bit (1 or 0).
1086 */
1087 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
1088 {
1089 return (READ_BITS(SPIx->S_EN, ss) == ss);
1090 }
1091
1092 /**
1093 * @brief Set baud rate prescaler
1094 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1095 *
1096 * Register|BitsName
1097 * --------|--------
1098 * BAUD | SCKDIV
1099 *
1100 * @param SPIx SPI instance
1101 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1102 * @retval None
1103 */
1104 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
1105 {
1106 WRITE_REG(SPIx->BAUD, baud_rate);
1107 }
1108
1109 /**
1110 * @brief Get baud rate prescaler
1111 *
1112 * Register|BitsName
1113 * --------|--------
1114 * BAUD | SCKDIV
1115 *
1116 * @param SPIx SPI instance
1117 * @retval Returned value can be one even value between 2 and 65534.
1118 */
1119 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
1120 {
1121 return (uint32_t)(READ_BITS(SPIx->BAUD, SPI_BAUD_CLK_DIV));
1122 }
1123
1124 /**
1125 * @brief Set threshold of TXFIFO that triggers an TXE event
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * TXFTL | TFT
1130 *
1131 * @param SPIx SPI instance
1132 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1133 * @retval None
1134 */
1135 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1136 {
1137 WRITE_REG(SPIx->TX_FIFO_TL, threshold);
1138 }
1139
1140 /**
1141 * @brief Get threshold of TXFIFO that triggers an TXE event
1142 *
1143 * Register|BitsName
1144 * --------|--------
1145 * TXFTL | TFT
1146 *
1147 * @param SPIx SPI instance
1148 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1149 */
1150 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
1151 {
1152 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_TL, SPI_TX_FIFO_TL_TX_FIFO_THD));
1153 }
1154
1155 /**
1156 * @brief Set threshold of RXFIFO that triggers an RXNE event
1157 *
1158 * Register|BitsName
1159 * --------|--------
1160 * RXFTL | RFT
1161 *
1162 * @param SPIx SPI instance
1163 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1164 * @retval None
1165 */
1166 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1167 {
1168 WRITE_REG(SPIx->RX_FIFO_TL, threshold);
1169 }
1170
1171 /**
1172 * @brief Get threshold of RXFIFO that triggers an RXNE event
1173 *
1174 * Register|BitsName
1175 * --------|--------
1176 * RXFTL | RFT
1177 *
1178 * @param SPIx SPI instance
1179 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1180 */
1181 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
1182 {
1183 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_TL, SPI_RX_FIFO_TL_RX_FIFO_THD));
1184 }
1185
1186 /**
1187 * @brief Get FIFO Transmission Level
1188 *
1189 * Register|BitsName
1190 * --------|--------
1191 * TXFL | TXTFL
1192 *
1193 * @param SPIx SPI instance
1194 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1195 */
1196 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
1197 {
1198 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_LEVEL, SPI_TX_FIFO_LEVEL_TX_FIFO_LEVEL));
1199 }
1200
1201 /**
1202 * @brief Get FIFO reception Level
1203 *
1204 * Register|BitsName
1205 * --------|--------
1206 * RXFL | RXTFL
1207 *
1208 * @param SPIx SPI instance
1209 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1210 */
1211 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
1212 {
1213 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_LEVEL, SPI_RX_FIFO_LEVEL_RX_FIFO_LEVEL));
1214 }
1215
1216 /** @} */
1217
1218 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1219 * @{
1220 */
1221
1222 /**
1223 * @brief Enable interrupt
1224 * @note This bit controls the generation of an interrupt when an event occurs.
1225 *
1226 * Register|BitsName
1227 * --------|--------
1228 * INTMASK | INTMASK
1229 *
1230 * @param SPIx SPI instance
1231 * @param mask This parameter can be one of the following values:
1232 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1233 * @arg @ref LL_SPI_IM_RXF
1234 * @arg @ref LL_SPI_IM_RXO
1235 * @arg @ref LL_SPI_IM_RXU
1236 * @arg @ref LL_SPI_IM_TXO
1237 * @arg @ref LL_SPI_IM_TXE
1238 * @retval None
1239 */
1240 __STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
1241 {
1242 SET_BITS(SPIx->INT_MASK, mask);
1243 }
1244
1245 /**
1246 * @brief Disable interrupt
1247 * @note This bit controls the generation of an interrupt when an event occurs.
1248 *
1249 * Register|BitsName
1250 * --------|--------
1251 * INTMASK | INTMASK
1252 *
1253 * @param SPIx SPI instance
1254 * @param mask This parameter can be one of the following values:
1255 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1256 * @arg @ref LL_SPI_IM_RXF
1257 * @arg @ref LL_SPI_IM_RXO
1258 * @arg @ref LL_SPI_IM_RXU
1259 * @arg @ref LL_SPI_IM_TXO
1260 * @arg @ref LL_SPI_IM_TXE
1261 * @retval None
1262 */
1263 __STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
1264 {
1265 CLEAR_BITS(SPIx->INT_MASK, mask);
1266 }
1267
1268 /**
1269 * @brief Check if interrupt is enabled
1270 *
1271 * Register|BitsName
1272 * --------|--------
1273 * INTMASK | INTMASK
1274 *
1275 * @param SPIx SPI instance
1276 * @param mask This parameter can be one of the following values:
1277 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1278 * @arg @ref LL_SPI_IM_RXF
1279 * @arg @ref LL_SPI_IM_RXO
1280 * @arg @ref LL_SPI_IM_RXU
1281 * @arg @ref LL_SPI_IM_TXO
1282 * @arg @ref LL_SPI_IM_TXE
1283 * @retval State of bit (1 or 0).
1284 */
1285 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
1286 {
1287 return (READ_BITS(SPIx->INT_MASK, mask) == mask);
1288 }
1289
1290 /** @} */
1291
1292 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1293 * @{
1294 */
1295
1296 /**
1297 * @brief Get SPI status
1298 *
1299 * Register|BitsName
1300 * --------|--------
1301 * STAT | STAT
1302 *
1303 * @param SPIx SPI instance
1304 * @retval Returned value can be one or combination of the following values:
1305 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1306 * @arg @ref LL_SPI_SR_TXE
1307 * @arg @ref LL_SPI_SR_RFF
1308 * @arg @ref LL_SPI_SR_RFNE
1309 * @arg @ref LL_SPI_SR_TFE
1310 * @arg @ref LL_SPI_SR_TFNF
1311 * @arg @ref LL_SPI_SR_BUSY
1312 */
1313 __STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
1314 {
1315 return (uint32_t)(READ_REG(SPIx->STAT));
1316 }
1317
1318 /**
1319 * @brief Check active flag
1320 *
1321 * Register|BitsName
1322 * --------|--------
1323 * STAT | DCOL
1324 * STAT | TXE
1325 * STAT | RFF
1326 * STAT | RFNE
1327 * STAT | TFE
1328 * STAT | TFNF
1329 * STAT | BUSY
1330 *
1331 * @param SPIx SPI instance
1332 * @param flag This parameter can be one of the following values:
1333 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1334 * @arg @ref LL_SPI_SR_TXE
1335 * @arg @ref LL_SPI_SR_RFF
1336 * @arg @ref LL_SPI_SR_RFNE
1337 * @arg @ref LL_SPI_SR_TFE
1338 * @arg @ref LL_SPI_SR_TFNF
1339 * @arg @ref LL_SPI_SR_BUSY
1340 * @retval State of bit (1 or 0).
1341 */
1342 __STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
1343 {
1344 return (READ_BITS(SPIx->STAT, flag) == (flag));
1345 }
1346
1347 /**
1348 * @brief Get SPI interrupt flags
1349 *
1350 * Register|BitsName
1351 * --------|--------
1352 * INTSTAT | INTSTAT
1353 *
1354 * @param SPIx SPI instance
1355 * @retval Returned value can be one or combination of the following values:
1356 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1357 * @arg @ref LL_SPI_IM_RXF
1358 * @arg @ref LL_SPI_IM_RXO
1359 * @arg @ref LL_SPI_IM_RXU
1360 * @arg @ref LL_SPI_IM_TXO
1361 * @arg @ref LL_SPI_IM_TXE
1362 */
1363 __STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
1364 {
1365 return (uint32_t)(READ_REG(SPIx->INT_STAT));
1366 }
1367
1368 /**
1369 * @brief Check interrupt flag
1370 *
1371 * Register|BitsName
1372 * --------|--------
1373 * INTSTAT | MSTIS
1374 * INTSTAT | RXFIS
1375 * INTSTAT | RXOIS
1376 * INTSTAT | RXUIS
1377 * INTSTAT | TXOIS
1378 * INTSTAT | TXEIS
1379 *
1380 * @param SPIx SPI instance
1381 * @param flag This parameter can be one of the following values:
1382 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1383 * @arg @ref LL_SPI_IM_RXF
1384 * @arg @ref LL_SPI_IM_RXO
1385 * @arg @ref LL_SPI_IM_RXU
1386 * @arg @ref LL_SPI_IM_TXO
1387 * @arg @ref LL_SPI_IM_TXE
1388 * @retval State of bit (1 or 0).
1389 */
1390 __STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
1391 {
1392 return (READ_BITS(SPIx->INT_STAT, flag) == flag);
1393 }
1394
1395 /**
1396 * @brief Get SPI raw interrupt flags
1397 *
1398 * Register|BitsName
1399 * --------|--------
1400 * RAW_INTSTAT | RAW_INTSTAT
1401 *
1402 * @param SPIx SPI instance
1403 * @retval Returned value can be one or combination of the following values:
1404 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1405 * @arg @ref LL_SPI_IM_RXF
1406 * @arg @ref LL_SPI_IM_RXO
1407 * @arg @ref LL_SPI_IM_RXU
1408 * @arg @ref LL_SPI_IM_TXO
1409 * @arg @ref LL_SPI_IM_TXE
1410 */
1411 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
1412 {
1413 return (uint32_t)(READ_REG(SPIx->RAW_INT_STAT));
1414 }
1415
1416 /**
1417 * @brief Clear transmit FIFO overflow error flag
1418 * @note Clearing this flag is done by reading TXOIC register
1419 *
1420 * Register|BitsName
1421 * --------|--------
1422 * TXOIC | TXOIC
1423 *
1424 * @param SPIx SPI instance
1425 * @retval None
1426 */
1427 __STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
1428 {
1429 __IOM uint32_t tmpreg;
1430 tmpreg = SPIx->TX_FIFO_OIC;
1431 (void) tmpreg;
1432 }
1433
1434 /**
1435 * @brief Clear receive FIFO overflow error flag
1436 * @note Clearing this flag is done by reading RXOIC register
1437 *
1438 * Register|BitsName
1439 * --------|--------
1440 * RXOIC | RXOIC
1441 *
1442 * @param SPIx SPI instance
1443 * @retval None
1444 */
1445 __STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
1446 {
1447 __IOM uint32_t tmpreg;
1448 tmpreg = SPIx->RX_FIFO_OIC;
1449 (void) tmpreg;
1450 }
1451
1452 /**
1453 * @brief Clear receive FIFO underflow error flag
1454 * @note Clearing this flag is done by reading RXUIC register
1455 *
1456 * Register|BitsName
1457 * --------|--------
1458 * RXUIC | RXUIC
1459 *
1460 * @param SPIx SPI instance
1461 * @retval None
1462 */
1463 __STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
1464 {
1465 __IOM uint32_t tmpreg;
1466 tmpreg = SPIx->RX_FIFO_UIC;
1467 (void) tmpreg;
1468 }
1469
1470 /**
1471 * @brief Clear multi-master error flag
1472 * @note Clearing this flag is done by reading MSTIC register
1473 *
1474 * Register|BitsName
1475 * --------|--------
1476 * MSTIC | MSTIC
1477 *
1478 * @param SPIx SPI instance
1479 * @retval None
1480 */
1481 __STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
1482 {
1483 __IOM uint32_t tmpreg;
1484 tmpreg = SPIx->MULTI_M_IC;
1485 (void) tmpreg;
1486 }
1487
1488 /**
1489 * @brief Clear all error flag
1490 * @note Clearing this flag is done by reading INTCLR register
1491 *
1492 * Register|BitsName
1493 * --------|--------
1494 * INTCLR | INTCLR
1495 *
1496 * @param SPIx SPI instance
1497 * @retval None
1498 */
1499 __STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
1500 {
1501 __IOM uint32_t tmpreg;
1502 tmpreg = SPIx->INT_CLR;
1503 (void) tmpreg;
1504 }
1505
1506 /** @} */
1507
1508 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1509 * @{
1510 */
1511
1512 /**
1513 * @brief Enable DMA Tx
1514 *
1515 * Register|BitsName
1516 * --------|--------
1517 * DMAC | TDMAE
1518 *
1519 * @param SPIx SPI instance
1520 * @retval None
1521 */
1522 __STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
1523 {
1524 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1525 }
1526
1527 /**
1528 * @brief Disable DMA Tx
1529 *
1530 * Register|BitsName
1531 * --------|--------
1532 * DMAC | TDMAE
1533 *
1534 * @param SPIx SPI instance
1535 * @retval None
1536 */
1537 __STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
1538 {
1539 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1540 }
1541
1542 /**
1543 * @brief Check if DMA Tx is enabled
1544 *
1545 * Register|BitsName
1546 * --------|--------
1547 * DMAC | TDMAE
1548 *
1549 * @param SPIx SPI instance
1550 * @retval State of bit (1 or 0).
1551 */
1552 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
1553 {
1554 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN) == (SPI_DMA_CTRL_TX_DMA_EN));
1555 }
1556
1557 /**
1558 * @brief Enable DMA Rx
1559 *
1560 * Register|BitsName
1561 * --------|--------
1562 * DMAC | RDMAE
1563 *
1564 * @param SPIx SPI instance
1565 * @retval None
1566 */
1567 __STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
1568 {
1569 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1570 }
1571
1572 /**
1573 * @brief Disable DMA Rx
1574 *
1575 * Register|BitsName
1576 * --------|--------
1577 * DMAC | RDMAE
1578 *
1579 * @param SPIx SPI instance
1580 * @retval None
1581 */
1582 __STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
1583 {
1584 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1585 }
1586
1587 /**
1588 * @brief Check if DMA Rx is enabled
1589 *
1590 * Register|BitsName
1591 * --------|--------
1592 * DMAC | RDMAE
1593 *
1594 * @param SPIx SPI instance
1595 * @retval State of bit (1 or 0).
1596 */
1597 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
1598 {
1599 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN) == (SPI_DMA_CTRL_RX_DMA_EN));
1600 }
1601
1602 /**
1603 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
1604 *
1605 * Register|BitsName
1606 * --------|--------
1607 * DMATDL | DMATDL
1608 *
1609 * @param SPIx SPI instance
1610 * @param threshold This parameter can be one of the following values: 0 ~ 7
1611 * @retval None
1612 */
1613 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1614 {
1615 WRITE_REG(SPIx->DMA_TX_DL, threshold);
1616 }
1617
1618 /**
1619 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
1620 *
1621 * Register|BitsName
1622 * --------|--------
1623 * DMATDL | DMATDL
1624 *
1625 * @param SPIx SPI instance
1626 * @retval Returned value can be one of the following values: 0 ~ 7
1627 */
1628 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
1629 {
1630 return (uint32_t)(READ_BITS(SPIx->DMA_TX_DL, SPI_DMA_TX_DL_DMA_TX_DL));
1631 }
1632
1633 /**
1634 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
1635 *
1636 * Register|BitsName
1637 * --------|--------
1638 * DMARDL | DMARDL
1639 *
1640 * @param SPIx SPI instance
1641 * @param threshold This parameter can be one of the following values: 0 ~ 7
1642 * @retval None
1643 */
1644 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1645 {
1646 WRITE_REG(SPIx->DMA_RX_DL, threshold);
1647 }
1648
1649 /**
1650 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
1651 *
1652 * Register|BitsName
1653 * --------|--------
1654 * DMARDL | DMARDL
1655 *
1656 * @param SPIx SPI instance
1657 * @retval Returned value can be one of the following values: 0 ~ 7
1658 */
1659 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
1660 {
1661 return (uint32_t)(READ_BITS(SPIx->DMA_RX_DL, SPI_DMA_RX_DL_DMA_RX_DL));
1662 }
1663
1664 /** @} */
1665
1666 /** @defgroup SPI_LL_EF_Data_Management Data_Management
1667 * @{
1668 */
1669
1670 /**
1671 * @brief Write 8-Bits in the data register
1672 *
1673 * Register|BitsName
1674 * --------|--------
1675 * DATA | DATA
1676 *
1677 * @param SPIx SPI instance
1678 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
1679 * @retval None
1680 */
1681 __STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
1682 {
1683 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1684 }
1685
1686 /**
1687 * @brief Write 16-Bits in the data register
1688 *
1689 * Register|BitsName
1690 * --------|--------
1691 * DATA | DATA
1692 *
1693 * @param SPIx SPI instance
1694 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
1695 * @retval None
1696 */
1697 __STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
1698 {
1699 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1700 }
1701
1702 /**
1703 * @brief Write 32-Bits in the data register
1704 *
1705 * Register|BitsName
1706 * --------|--------
1707 * DATA | DATA
1708 *
1709 * @param SPIx SPI instance
1710 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1711 * @retval None
1712 */
1713 __STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
1714 {
1715 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1716 }
1717
1718 /**
1719 * @brief Read 8-Bits in the data register
1720 *
1721 * Register|BitsName
1722 * --------|--------
1723 * DATA | DATA
1724 *
1725 * @param SPIx SPI instance
1726 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
1727 */
1728 __STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
1729 {
1730 return (uint8_t)(READ_REG(SPIx->DATA));
1731 }
1732
1733 /**
1734 * @brief Read 16-Bits in the data register
1735 *
1736 * Register|BitsName
1737 * --------|--------
1738 * DATA | DATA
1739 *
1740 * @param SPIx SPI instance
1741 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
1742 */
1743 __STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
1744 {
1745 return (uint16_t)(READ_REG(SPIx->DATA));
1746 }
1747
1748 /**
1749 * @brief Read 32-Bits in the data register
1750 *
1751 * Register|BitsName
1752 * --------|--------
1753 * DATA | DATA
1754 *
1755 * @param SPIx SPI instance
1756 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1757 */
1758 __STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
1759 {
1760 return (uint32_t)(READ_REG(SPIx->DATA));
1761 }
1762
1763 /**
1764 * @brief Set Rx sample delay
1765 * @note This bit should not be changed when communication is ongoing.
1766 *
1767 * Register|BitsName
1768 * --------|--------
1769 * RX_SAMPLEDLY | RX_SAMPLEDLY
1770 *
1771 * @param SPIx SPI instance
1772 * @param delay This parameter can be one of the following values: 0 ~ 7
1773 * @retval None
1774 */
1775 __STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
1776 {
1777 MODIFY_REG(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY, delay);
1778 }
1779
1780 /**
1781 * @brief Get Rx sample delay
1782 * @note This bit should not be changed when communication is ongoing.
1783 *
1784 * Register|BitsName
1785 * --------|--------
1786 * RX_SAMPLEDLY | RX_SAMPLEDLY
1787 *
1788 * @param SPIx SPI instance
1789 * @retval Returned value can be one of the following values: 0 ~ 7
1790 */
1791 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
1792 {
1793 return (uint32_t)(READ_BITS(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY));
1794 }
1795
1796 /** @} */
1797
1798 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
1799 * @{
1800 */
1801
1802 /**
1803 * @brief De-initialize SSI registers (Registers restored to their default values).
1804 * @param SPIx SSI instance
1805 * @retval An error_status_t enumeration value:
1806 * - SUCCESS: SSI registers are de-initialized
1807 * - ERROR: SSI registers are not de-initialized
1808 */
1809 error_status_t ll_spim_deinit(spi_regs_t *SPIx);
1810
1811 /**
1812 * @brief Initialize SPIM registers according to the specified
1813 * parameters in p_spi_init.
1814 * @param SPIx SSI instance
1815 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
1816 * information for the specified SPIM peripheral.
1817 * @retval An error_status_t enumeration value:
1818 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1819 * - ERROR: Problem occurred during SSI Registers initialization
1820 */
1821 error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
1822
1823 /**
1824 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
1825 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
1826 * whose fields will be set to default values.
1827 * @retval None
1828 */
1829 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
1830
1831 /** @} */
1832
1833 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
1834 * @{
1835 */
1836
1837 /**
1838 * @brief De-initialize SSI registers (Registers restored to their default values).
1839 * @param SPIx SSI instance
1840 * @retval An error_status_t enumeration value:
1841 * - SUCCESS: SSI registers are de-initialized
1842 * - ERROR: SSI registers are not de-initialized
1843 */
1844 error_status_t ll_spis_deinit(spi_regs_t *SPIx);
1845
1846 /**
1847 * @brief Initialize SSI registers according to the specified
1848 * parameters in p_spi_init.
1849 * @param SPIx SSI instance
1850 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
1851 * information for the specified SPIS peripheral.
1852 * @retval An error_status_t enumeration value:
1853 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1854 * - ERROR: Problem occurred during SPI Registers initialization
1855 */
1856 error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
1857
1858 /**
1859 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
1860 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
1861 * whose fields will be set to default values.
1862 * @retval None
1863 */
1864 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
1865 /** @} */
1866
1867 /** @} */
1868
1869 #endif /* SPIM || SPIS */
1870
1871 #ifdef __cplusplus
1872 }
1873 #endif
1874
1875 #endif /* __GR55xx_LL_SPI_H__ */
1876
1877 /** @} */
1878
1879 /** @} */
1880
1881 /** @} */
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr55xx_ll_spi.h:1567
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_spi.h:632
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1135
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1681
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr55xx_ll_spi.h:1791
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr55xx_ll_spi.h:1582
_ll_spis_init_t
SPIS init structures definition.
Definition: gr55xx_ll_spi.h:116
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1150
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1659
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_spi.h:117
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_spi.h:1049
ll_spis_init
error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr55xx_ll_spi.h:401
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_spi.h:1240
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr55xx_ll_spi.h:602
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1613
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr55xx_ll_spi.h:77
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
Enable slave output.
Definition: gr55xx_ll_spi.h:647
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:847
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_spi.h:1775
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_spi.h:1342
ll_spim_init
error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_spi.h:880
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
Clear all error flag.
Definition: gr55xx_ll_spi.h:1499
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1181
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:926
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr55xx_ll_spi.h:417
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_spi.h:88
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_spi.h:1411
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
Disable slave output.
Definition: gr55xx_ll_spi.h:662
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_spi.h:122
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_spi.h:1363
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1644
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_spi.h:896
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1758
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_spi.h:1104
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1628
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:993
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_spi.h:103
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_spi.h:956
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:587
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Definition: gr55xx_ll_spi.h:78
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1697
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_spi.h:810
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_spi.h:83
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
Get SPI status.
Definition: gr55xx_ll_spi.h:1313
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
Get frame data size.
Definition: gr55xx_ll_spi.h:522
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1030
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_spi.h:736
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:975
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_spi.h:1196
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_spi.h:1552
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_spi.h:911
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_spi.h:478
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr55xx_ll_spi.h:1522
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_spi.h:1068
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1166
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:941
_ll_spim_init_t::slave_select
uint32_t slave_select
Definition: gr55xx_ll_spi.h:98
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:865
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
Get clock phase.
Definition: gr55xx_ll_spi.h:790
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_spi.h:1211
ll_spim_deinit
error_status_t ll_spim_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr55xx_ll_spi.h:1537
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_spi.h:1119
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1743
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_spi.h:677
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_spi.h:433
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
Get serial protocol used.
Definition: gr55xx_ll_spi.h:828
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1445
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1427
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1713
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr55xx_ll_spi.h:716
_ll_spim_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_ll_spi.h:108
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_spi.h:1390
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_spi.h:127
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_spi.h:93
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:555
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1728
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_spi.h:1597
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_spi.h:773
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_spi.h:1263
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1012
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_spi.h:1087
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_spi.h:1285
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_spi.h:697
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr55xx_ll_spi.h:617
ll_spis_deinit
error_status_t ll_spis_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_spi.h:1481
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
Get clock polarity.
Definition: gr55xx_ll_spi.h:753
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_spi.h:1463