var group___s_p_i___l_l___exported___constants =
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    [ "SPI Frame Format", "d5/db9/group___s_p_i___l_l___e_c___s_p_i_f_r_a_m_e_f_o_r_m_a_t.html", "d5/db9/group___s_p_i___l_l___e_c___s_p_i_f_r_a_m_e_f_o_r_m_a_t" ],
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    [ "Test Mode", "d3/d09/group___s_p_i___l_l___e_c___t_e_s_t___m_o_d_e.html", "d3/d09/group___s_p_i___l_l___e_c___t_e_s_t___m_o_d_e" ],
    [ "Slave Out Enable", "dc/d9c/group___s_p_i___l_l___e_c___s_l_a_v_e_o_u_t___e_n_a_b_l_e.html", "dc/d9c/group___s_p_i___l_l___e_c___s_l_a_v_e_o_u_t___e_n_a_b_l_e" ],
    [ "Transfer Mode", "da/d52/group___s_p_i___l_l___e_c___t_r_a_n_s_f_e_r___m_o_d_e.html", "da/d52/group___s_p_i___l_l___e_c___t_r_a_n_s_f_e_r___m_o_d_e" ],
    [ "Clock Phase", "da/dd5/group___s_p_i___l_l___e_c___p_h_a_s_e.html", "da/dd5/group___s_p_i___l_l___e_c___p_h_a_s_e" ],
    [ "Clock Polarity", "dc/dfc/group___s_p_i___l_l___e_c___p_o_l_a_r_i_t_y.html", "dc/dfc/group___s_p_i___l_l___e_c___p_o_l_a_r_i_t_y" ],
    [ "Serial Protocol", "db/dbc/group___s_p_i___l_l___e_c___p_r_o_t_o_c_o_l.html", "db/dbc/group___s_p_i___l_l___e_c___p_r_o_t_o_c_o_l" ],
    [ "MicroWire Control", "df/d77/group___s_p_i___l_l___e_c___m_i_c_r_o_w_i_r_e_c_o_n_t_r_o_l.html", "df/d77/group___s_p_i___l_l___e_c___m_i_c_r_o_w_i_r_e_c_o_n_t_r_o_l" ],
    [ "Slave Select", "d4/dfe/group___s_p_i___l_l___e_c___s_l_a_v_e_s_e_l_e_c_t.html", "d4/dfe/group___s_p_i___l_l___e_c___s_l_a_v_e_s_e_l_e_c_t" ],
    [ "DMA Defines", "d5/dd7/group___s_p_i___l_l___e_c___d_m_a.html", "d5/dd7/group___s_p_i___l_l___e_c___d_m_a" ],
    [ "QSPI Instruction Size", "de/dee/group___s_p_i___l_l___e_c___i_n_s_t_r_u_c_t_i_o_n_s_i_z_e.html", "de/dee/group___s_p_i___l_l___e_c___i_n_s_t_r_u_c_t_i_o_n_s_i_z_e" ],
    [ "QSPI Address Size", "d2/d30/group___s_p_i___l_l___e_c___a_d_d_r_e_s_s_s_i_z_e.html", "d2/d30/group___s_p_i___l_l___e_c___a_d_d_r_e_s_s_s_i_z_e" ],
    [ "QSPI RX SAMPLE EDGE", "d1/ded/group___l_l___q_s_p_i___r_x___s_a_m_p_l_e___e_d_g_e.html", "d1/ded/group___l_l___q_s_p_i___r_x___s_a_m_p_l_e___e_d_g_e" ],
    [ "QSPI Address and Instruction Transfer Format", "dc/d99/group___s_p_i___l_l___e_c___a_d_d_r_i_n_s_t_t_r_n_a_s_f_e_r_f_o_r_m_a_t.html", "dc/d99/group___s_p_i___l_l___e_c___a_d_d_r_i_n_s_t_t_r_n_a_s_f_e_r_f_o_r_m_a_t" ],
    [ ": endian mode for qspi xip", "d3/dad/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___e_n_d_i_a_n___m_o_d_e.html", "d3/dad/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___e_n_d_i_a_n___m_o_d_e" ],
    [ ": Which Slave to Enable in XIP", "d1/dc7/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___s_l_a_v_e.html", "d1/dc7/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___s_l_a_v_e" ],
    [ ": data frame size in xip, take effect when enable DFS_HC", "d9/d3a/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s.html", "d9/d3a/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___d_f_s" ],
    [ ": mode bits length for xip mode", "db/da9/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_b_l.html", "db/da9/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___m_b_l" ],
    [ ": instruction size for concurrent xip mode", "d5/d9b/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t_s_i_z_e.html", "d5/d9b/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t_s_i_z_e" ],
    [ ": address size for concurrent xip mode", "de/dba/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___a_d_d_r_s_i_z_e.html", "de/dba/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___a_d_d_r_s_i_z_e" ],
    [ ": transfer of inst & address for concurrent xip mode", "dc/dfb/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___a_d_d_r___t_r_a_n_s_f_e_r___f_o_r_m_a_t.html", "dc/dfb/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___a_d_d_r___t_r_a_n_s_f_e_r___f_o_r_m_a_t" ],
    [ ": frame format for concurrent xip mode", "df/dfe/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___f_r_f.html", "df/dfe/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___f_r_f" ],
    [ "Mode Clock stretch mode", "d4/d07/group___l_l___q_s_p_i___x_i_p___c_l_k___s_t_r_e_t_c_h.html", "d4/d07/group___l_l___q_s_p_i___x_i_p___c_l_k___s_t_r_e_t_c_h" ],
    [ "XQSPI Xip Prefetch", "d5/def/group___q_s_p_i___x_i_p___p_r_e_f_e_t_c_h.html", "d5/def/group___q_s_p_i___x_i_p___p_r_e_f_e_t_c_h" ],
    [ "QSPI Xip Count Xferr", "df/d76/group___q_s_p_i___x_i_p___c_o_n_t___x_f_e_r_r.html", "df/d76/group___q_s_p_i___x_i_p___c_o_n_t___x_f_e_r_r" ],
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    [ "QSPI Xip Mode Enable", "d1/d1f/group___q_s_p_i___x_i_p___m_o_d_e___b_i_t_s___p_h_a_s_e.html", "d1/d1f/group___q_s_p_i___x_i_p___m_o_d_e___b_i_t_s___p_h_a_s_e" ],
    [ "QSPI Xip Dfs Hardcode Enable", "da/d89/group___q_s_p_i___x_i_p___d_f_s___h_c.html", "da/d89/group___q_s_p_i___x_i_p___d_f_s___h_c" ],
    [ "QSPI Concurrent Xip Inst Sent Mode", "d4/d29/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___s_e_n_t___m_o_d_e.html", "d4/d29/group___l_l___q_s_p_i___c_o_n_c_u_r_r_e_n_t___x_i_p___i_n_s_t___s_e_n_t___m_o_d_e" ],
    [ "InitStrcut default configuartion", "d4/dc7/group___s_p_i___l_l___e_c___d_e_f_a_u_l_t___c_o_n_f_i_g.html", "d4/dc7/group___s_p_i___l_l___e_c___d_e_f_a_u_l_t___c_o_n_f_i_g" ],
    [ "Defines", "d2/d6c/group___l_l___s_p_i__x___f_i_f_o___d_e_p_t_h.html", "d2/d6c/group___l_l___s_p_i__x___f_i_f_o___d_e_p_t_h" ],
    [ "LL_SPIM_DEFAULT_CONFIG", "d1/db5/group___s_p_i___l_l___exported___constants.html#gad4fa8f165315dcbc5e79e8173504b205", null ],
    [ "LL_SPIS_DEFAULT_CONFIG", "d1/db5/group___s_p_i___l_l___exported___constants.html#gaa6dd7d25e68a0e91b5758a22fac6dc8e", null ]
];