gr55xx_ll_dvs.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dvs.h
5 * @author BLE RD
6 * @brief Header file containing functions prototypes of dvs LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DVS DVS
47 * @brief DVS LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_dvs_H_
53 #define __GR55XX_LL_dvs_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61
62 /**
63 * @defgroup DVS_LL_MACRO Defines
64 * @{
65 */
66 /** @defgroup Analog_Voltage_Scale_enable Analog Voltage Scaling enable state defines
67 * @{
68 */
69 #define LL_ANALOG_VOLTAGE_SCALE_DIS (0U) /**< Analog Voltage Scaling Disable(default) */
70 #define LL_ANALOG_VOLTAGE_SCALE_EN (1U) /**< Analog Voltage Scaling Enable */
71 /** @} */
72
73 /** @defgroup Analog_Voltage_Scale_type Analog Voltage Scaling slop control type defines
74 * @{
75 */
76 #define LL_ANALOG_VOLTAGE_SCALE_LOWER_TYPE (0U) /**< Analog Voltage Scaling Lower Type(default) */
77 #define LL_ANALOG_VOLTAGE_SCALE_HIGHER_TYPE (1U) /**< Analog Voltage Scaling Higher Type */
78 /** @} */
79
80 /** @defgroup Analog Voltage Scaling limiter enable defines
81 * @{
82 */
83 #define LL_ANALOG_VOLTAGE_SCALE_LIMIT_DIS (0U) /**< Analog Voltage Scaling Limit Disable(default) */
84 #define LL_ANALOG_VOLTAGE_SCALE_LIMIT_EN (1U) /**< Analog Voltage Scaling Limit Enable */
85 /** @} */
86
87 /** @} */
88
89 /** @defgroup DVS_LL_DRIVER_FUNCTIONS Functions
90 * @{
91 */
92 /**
93 * @brief The DVS_DCDC block enable set
94 *
95 * Register|BitsName
96 * --------|--------
97 * DVS_DCDC | EN_VTBIAS
98 */
99 __STATIC_INLINE void ll_dvs_dcdc_enable_set(uint8_t enable)
100 {
101 MODIFY_REG(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_EN_VTBIAS, (enable << AON_PMU_DVS_DCDC_EN_VTBIAS_Pos));
102 }
103
104 /**
105 * @brief The DVS_DCDC block enable get
106 *
107 * Register|BitsName
108 * --------|--------
109 * DVS_DCDC | EN_VTBIAS
110 */
111 __STATIC_INLINE uint8_t ll_dvs_dcdc_enable_get(void)
112 {
113 return ((READ_BITS(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_EN_VTBIAS)) >> AON_PMU_DVS_DCDC_EN_VTBIAS_Pos);
114 }
115
116 /**
117 * @brief The DVS_DCDC's Slop Control type set
118 *
119 * Register|BitsName
120 * --------|--------
121 * DVS_DCDC | VTBIAS_SLOPE_CTRL
122 */
123 __STATIC_INLINE void ll_dvs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
124 {
125 MODIFY_REG(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_SLOPE_CTRL, (type << AON_PMU_DVS_DCDC_VTBIAS_SLOPE_CTRL_Pos));
126 }
127
128 /**
129 * @brief The DVS_DCDC's Slop Control type get
130 *
131 * Register|BitsName
132 * --------|--------
133 * DVS_DCDC | VTBIAS_SLOPE_CTRL
134 */
135 __STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_slop_ctrl_get(void)
136 {
137 return ((READ_BITS(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_SLOPE_CTRL)) >> AON_PMU_DVS_DCDC_VTBIAS_SLOPE_CTRL_Pos);
138 }
139
140 /**
141 * @brief The DVS_DCDC's Lower Limit Control enable set
142 *
143 * Register|BitsName
144 * --------|--------
145 * DVS_DCDC | EN_LIMITER
146 */
147 __STATIC_INLINE void ll_dvs_dcdc_limiter_enable_set(uint8_t enable)
148 {
149 MODIFY_REG(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_EN_LIMITER, (enable << AON_PMU_DVS_DCDC_EN_LIMITER_Pos));
150 }
151
152 /**
153 * @brief The DVS_DCDC's Lower Limit Control enable get
154 *
155 * Register|BitsName
156 * --------|--------
157 * DVS_DCDC | EN_LIMITER
158 */
159 __STATIC_INLINE uint8_t ll_dvs_dcdc_limiter_enable_get(void)
160 {
161 return ((READ_BITS(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_EN_LIMITER)) >> AON_PMU_DVS_DCDC_EN_LIMITER_Pos);
162 }
163
164 /**
165 * @brief The DVS_DCDC's default level value of the VT bias set
166 *
167 * Register|BitsName
168 * --------|--------
169 * DVS_DCDC | VTBIAS_CTRL_VT_2_0
170 */
171 __STATIC_INLINE void ll_dvs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
172 {
173 MODIFY_REG(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_DVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos));
174 }
175
176 /**
177 * @brief The DVS_DCDC's default level value of the VT bias get
178 *
179 * Register|BitsName
180 * --------|--------
181 * DVS_DCDC | VTBIAS_CTRL_VT_2_0
182 */
183 __STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_ctrl_vt_get(void)
184 {
185 return ((READ_BITS(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_DVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos);
186 }
187
188 /**
189 * @brief The DVS_DCDC's lower limit for the output voltage set
190 *
191 * Register|BitsName
192 * --------|--------
193 * DVS_DCDC | VTBIAS_CTRL_VT_2_0
194 */
195 __STATIC_INLINE void ll_dvs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
196 {
197 MODIFY_REG(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_DVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos));
198 }
199
200 /**
201 * @brief The DVS_DCDC's lower limit for the output voltage get
202 *
203 * Register|BitsName
204 * --------|--------
205 * DVS_DCDC | VTBIAS_CTRL_VT_2_0
206 */
207 __STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_ctrl_lower_limit_get(void)
208 {
209 return ((READ_BITS(AON_PMU->DVS_DCDC, AON_PMU_DVS_DCDC_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_DVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos);
210 }
211
212 /**
213 * @brief The DVS_DIGCORE block enable set
214 *
215 * Register|BitsName
216 * --------|--------
217 * DVS_DIGCORE | EN_VTBIAS
218 */
219 __STATIC_INLINE void ll_dvs_digcore_enable_set(uint8_t enable)
220 {
221 MODIFY_REG(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_EN_VTBIAS, (enable << AON_PMU_DVS_DIGCORE_EN_VTBIAS_Pos));
222 }
223
224 /**
225 * @brief The DVS_DIGCORE block enable get
226 *
227 * Register|BitsName
228 * --------|--------
229 * DVS_DIGCORE | EN_VTBIAS
230 */
231 __STATIC_INLINE uint8_t ll_dvs_digcore_enable_get(void)
232 {
233 return ((READ_BITS(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_EN_VTBIAS)) >> AON_PMU_DVS_DIGCORE_EN_VTBIAS_Pos);
234 }
235
236 /**
237 * @brief The DVS_DIGCORE's Slop Control type set
238 *
239 * Register|BitsName
240 * --------|--------
241 * DVS_DIGCORE | VTBIAS_SLOPE_CTRL
242 */
243 __STATIC_INLINE void ll_dvs_digcore_vtbias_slop_ctrl_set(uint8_t type)
244 {
245 MODIFY_REG(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_SLOPE_CTRL, (type << AON_PMU_DVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos));
246 }
247
248 /**
249 * @brief The DVS_DIGCORE's Slop Control type get
250 *
251 * Register|BitsName
252 * --------|--------
253 * DVS_DIGCORE | VTBIAS_SLOPE_CTRL
254 */
255 __STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_slop_ctrl_get(void)
256 {
257 return ((READ_BITS(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_SLOPE_CTRL)) >> AON_PMU_DVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos);
258 }
259
260 /**
261 * @brief The DVS_DIGCORE's Lower Limit Control enable set
262 *
263 * Register|BitsName
264 * --------|--------
265 * DVS_DIGCORE | EN_LIMITER
266 */
267 __STATIC_INLINE void ll_dvs_digcore_limiter_enable_set(uint8_t enable)
268 {
269 MODIFY_REG(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_EN_LIMITER, (enable << AON_PMU_DVS_DIGCORE_EN_LIMITER_Pos));
270 }
271
272 /**
273 * @brief The DVS_DIGCORE's Lower Limit Control enable get
274 *
275 * Register|BitsName
276 * --------|--------
277 * DVS_DIGCORE | EN_LIMITER
278 */
279 __STATIC_INLINE uint8_t ll_dvs_digcore_limiter_enable_get(void)
280 {
281 return ((READ_BITS(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_EN_LIMITER)) >> AON_PMU_DVS_DIGCORE_EN_LIMITER_Pos);
282 }
283
284 /**
285 * @brief The DVS_DIGCORE's default level value of the VT bias set
286 *
287 * Register|BitsName
288 * --------|--------
289 * DVS_DIGCORE | VTBIAS_CTRL_VT_2_0
290 */
291 __STATIC_INLINE void ll_dvs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
292 {
293 MODIFY_REG(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos));
294 }
295
296 /**
297 * @brief The DVS_DIGCORE's default level value of the VT bias get
298 *
299 * Register|BitsName
300 * --------|--------
301 * DVS_DIGCORE | VTBIAS_CTRL_VT_2_0
302 */
303 __STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_ctrl_vt_get(void)
304 {
305 return ((READ_BITS(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos);
306 }
307
308 /**
309 * @brief The DVS_DIGCORE's lower limit for the output voltage set
310 *
311 * Register|BitsName
312 * --------|--------
313 * DVS_DIGCORE | VTBIAS_CTRL_VT_2_0
314 */
315 __STATIC_INLINE void ll_dvs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
316 {
317 MODIFY_REG(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos));
318 }
319
320 /**
321 * @brief The DVS_DIGCORE's lower limit for the output voltage get
322 *
323 * Register|BitsName
324 * --------|--------
325 * DVS_DIGCORE | VTBIAS_CTRL_VT_2_0
326 */
327 __STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_ctrl_lower_limit_get(void)
328 {
329 return ((READ_BITS(AON_PMU->DVS_DIGCORE, AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_DVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos);
330 }
331
332 /** @} */
333
334 #endif
335 /** @} */
336
337 /** @} */
338
339 /** @} */
ll_dvs_dcdc_limiter_enable_get
__STATIC_INLINE uint8_t ll_dvs_dcdc_limiter_enable_get(void)
The DVS_DCDC's Lower Limit Control enable get.
Definition: gr55xx_ll_dvs.h:159
ll_dvs_digcore_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_ctrl_lower_limit_get(void)
The DVS_DIGCORE's lower limit for the output voltage get.
Definition: gr55xx_ll_dvs.h:327
ll_dvs_dcdc_enable_get
__STATIC_INLINE uint8_t ll_dvs_dcdc_enable_get(void)
The DVS_DCDC block enable get.
Definition: gr55xx_ll_dvs.h:111
ll_dvs_digcore_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_dvs_digcore_vtbias_slop_ctrl_set(uint8_t type)
The DVS_DIGCORE's Slop Control type set.
Definition: gr55xx_ll_dvs.h:243
ll_dvs_digcore_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_dvs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
The DVS_DIGCORE's lower limit for the output voltage set.
Definition: gr55xx_ll_dvs.h:315
ll_dvs_digcore_enable_get
__STATIC_INLINE uint8_t ll_dvs_digcore_enable_get(void)
The DVS_DIGCORE block enable get.
Definition: gr55xx_ll_dvs.h:231
ll_dvs_dcdc_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_dvs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
The DVS_DCDC's default level value of the VT bias set.
Definition: gr55xx_ll_dvs.h:171
ll_dvs_digcore_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_ctrl_vt_get(void)
The DVS_DIGCORE's default level value of the VT bias get.
Definition: gr55xx_ll_dvs.h:303
ll_dvs_dcdc_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_dvs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
The DVS_DCDC's Slop Control type set.
Definition: gr55xx_ll_dvs.h:123
ll_dvs_dcdc_enable_set
__STATIC_INLINE void ll_dvs_dcdc_enable_set(uint8_t enable)
The DVS_DCDC block enable set.
Definition: gr55xx_ll_dvs.h:99
ll_dvs_dcdc_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_ctrl_lower_limit_get(void)
The DVS_DCDC's lower limit for the output voltage get.
Definition: gr55xx_ll_dvs.h:207
ll_dvs_digcore_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_dvs_digcore_vtbias_slop_ctrl_get(void)
The DVS_DIGCORE's Slop Control type get.
Definition: gr55xx_ll_dvs.h:255
ll_dvs_dcdc_limiter_enable_set
__STATIC_INLINE void ll_dvs_dcdc_limiter_enable_set(uint8_t enable)
The DVS_DCDC's Lower Limit Control enable set.
Definition: gr55xx_ll_dvs.h:147
ll_dvs_digcore_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_dvs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
The DVS_DIGCORE's default level value of the VT bias set.
Definition: gr55xx_ll_dvs.h:291
ll_dvs_digcore_enable_set
__STATIC_INLINE void ll_dvs_digcore_enable_set(uint8_t enable)
The DVS_DIGCORE block enable set.
Definition: gr55xx_ll_dvs.h:219
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_dvs_dcdc_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_slop_ctrl_get(void)
The DVS_DCDC's Slop Control type get.
Definition: gr55xx_ll_dvs.h:135
ll_dvs_digcore_limiter_enable_set
__STATIC_INLINE void ll_dvs_digcore_limiter_enable_set(uint8_t enable)
The DVS_DIGCORE's Lower Limit Control enable set.
Definition: gr55xx_ll_dvs.h:267
ll_dvs_digcore_limiter_enable_get
__STATIC_INLINE uint8_t ll_dvs_digcore_limiter_enable_get(void)
The DVS_DIGCORE's Lower Limit Control enable get.
Definition: gr55xx_ll_dvs.h:279
ll_dvs_dcdc_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_dvs_dcdc_vtbias_ctrl_vt_get(void)
The DVS_DCDC's default level value of the VT bias get.
Definition: gr55xx_ll_dvs.h:183
ll_dvs_dcdc_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_dvs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
The DVS_DCDC's lower limit for the output voltage set.
Definition: gr55xx_ll_dvs.h:195