gr55xx_hal_gpio_ex.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_gpio_ex.h
5 * @author BLE Driver Team
6 * @brief Header file containing extended macro of GPIO HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_GPIOEx GPIOEx
47 * @brief GPIOEx HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_GPIO_EX_H__
53 #define __GR55xx_HAL_GPIO_EX_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal_def.h"
61 #include "gr55xx_ll_gpio.h"
62
63 /* Exported types ------------------------------------------------------------*/
64
65 /**
66 * @defgroup HAL_GPIOEX_MACRO Defines
67 * @{
68 */
69
70 /* Exported constants --------------------------------------------------------*/
71 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
72 * @{
73 */
74
75 /** @defgroup GPIOEx_Mux_Mode GPIOEx Mux Mode definition
76 * @{
77 */
78 #define GPIO_MUX_0 LL_GPIO_MUX_0 /**< GPIO Mux mode 0 */
79 #define GPIO_MUX_1 LL_GPIO_MUX_1 /**< GPIO Mux mode 1 */
80 #define GPIO_MUX_2 LL_GPIO_MUX_2 /**< GPIO Mux mode 2 */
81 #define GPIO_MUX_3 LL_GPIO_MUX_3 /**< GPIO Mux mode 3 */
82 #define GPIO_MUX_4 LL_GPIO_MUX_4 /**< GPIO Mux mode 4 */
83 #define GPIO_MUX_5 LL_GPIO_MUX_5 /**< GPIO Mux mode 5 */
84 #define GPIO_MUX_6 LL_GPIO_MUX_6 /**< GPIO Mux mode 6 */
85 #define GPIO_MUX_7 LL_GPIO_MUX_7 /**< GPIO Mux mode 7 */
86 #define GPIO_MUX_8 LL_GPIO_MUX_8 /**< GPIO Mux mode 8 */
87 /** @} */
88
89 /** @defgroup GPIOEx_Mux_Function_Selection GPIOEx Mux function selection
90 * @{
91 */
92
93
94 #if defined (GR5X25)
95 /*---------------------------------- GR5X25 ------------------------------*/
96
97 /** @defgroup GPIOEx_Common_Selection GPIO PIN common MUX selection(Available for all GPIO pins)
98 * @{
99 */
100 #define GPIO_PIN_MUX_TESTBUS GPIO_MUX_8 /**< GPIO PIN x Mux Select TESTBUS */
101
102 #define GPIO_PIN_MUX_GPIO GPIO_MUX_8 /**< GPIO PIN x Mux Select GPIO */
103
104 /** @} */
105
106 /** @defgroup GPIOEx_GPIO0_PIN0_Mux_Selection GPIO0_PIN0 MUX selection
107 * @{
108 */
109 #define GPIO0_PIN0_MUX_SWD_CLK GPIO_MUX_0 /**< GPIO0_PIN0 Mux Select SWD_CLK */
110 #define GPIO0_PIN0_MUX_I2C0_SCL GPIO_MUX_1 /**< GPIO0_PIN0 Mux Select I2C0_SCL */
111 #define GPIO0_PIN0_MUX_I2C1_SCL GPIO_MUX_2 /**< GPIO0_PIN0 Mux Select I2C1_SCL */
112 #define GPIO0_PIN0_MUX_UART1_CTS GPIO_MUX_3 /**< GPIO0_PIN0 Mux Select UART1_CTS */
113 #define GPIO0_PIN0_MUX_UART0_TX GPIO_MUX_4 /**< GPIO0_PIN0 Mux Select UART0_TX */
114 #define GPIO0_PIN0_MUX_UART1_TX GPIO_MUX_5 /**< GPIO0_PIN0 Mux Select UART1_TX */
115 #define GPIO0_PIN0_MUX_UART0_CTS GPIO_MUX_6 /**< GPIO0_PIN0 Mux Select UART0_CTS */
116 /** @} */
117
118 /** @defgroup GPIOEx_GPIO0_PIN1_Mux_Selection GPIO0_PIN1 MUX selection
119 * @{
120 */
121 #define GPIO0_PIN1_MUX_SWD_IO GPIO_MUX_0 /**< GPIO0_PIN1 Mux Select SWD_IO */
122 #define GPIO0_PIN1_MUX_I2C0_SDA GPIO_MUX_1 /**< GPIO0_PIN1 Mux Select I2C0_SDA */
123 #define GPIO0_PIN1_MUX_I2C1_SDA GPIO_MUX_2 /**< GPIO0_PIN1 Mux Select I2C1_SDA */
124 #define GPIO0_PIN1_MUX_UART1_RTS GPIO_MUX_3 /**< GPIO0_PIN1 Mux Select UART1_RTS */
125 #define GPIO0_PIN1_MUX_UART0_RX GPIO_MUX_4 /**< GPIO0_PIN1 Mux Select UART0_RX */
126 #define GPIO0_PIN1_MUX_UART1_RX GPIO_MUX_5 /**< GPIO0_PIN1 Mux Select UART1_RX */
127 #define GPIO0_PIN1_MUX_UART0_RTS GPIO_MUX_6 /**< GPIO0_PIN1 Mux Select UART0_RTS */
128 /** @} */
129
130 /** @defgroup GPIOEx_GPIO0_PIN2_Mux_Selection GPIO0_PIN2 MUX selection
131 * @{
132 */
133 #define GPIO0_PIN2_MUX_UART0_CTS GPIO_MUX_0 /**< GPIO0_PIN2 Mux Select UART0_CTS */
134 #define GPIO0_PIN2_MUX_PDM_CLKO GPIO_MUX_1 /**< GPIO0_PIN2 Mux Select PDM_CLKO */
135 #define GPIO0_PIN2_MUX_SIM_PRESENCE GPIO_MUX_2 /**< GPIO0_PIN2 Mux Select SIM_PRESENCE */
136 #define GPIO0_PIN2_MUX_I2C0_SCL GPIO_MUX_3 /**< GPIO0_PIN2 Mux Select I2C0_SCL */
137 #define GPIO0_PIN2_MUX_FERP_TRIG GPIO_MUX_4 /**< GPIO0_PIN2 Mux Select FERP_TRIG */
138 #define GPIO0_PIN2_MUX_SWV GPIO_MUX_5 /**< GPIO0_PIN2 Mux Select SWV */
139 /** @} */
140
141 /** @defgroup GPIOEx_GPIO0_PIN3_Mux_Selection GPIO0_PIN3 MUX selection
142 * @{
143 */
144 #define GPIO0_PIN3_MUX_UART0_RTS GPIO_MUX_0 /**< GPIO0_PIN3 Mux Select UART0_RTS */
145 #define GPIO0_PIN3_MUX_PDM_DI GPIO_MUX_1 /**< GPIO0_PIN3 Mux Select PDM_DI */
146 #define GPIO0_PIN2_MUX_I2C0_SDA GPIO_MUX_2 /**< GPIO0_PIN3 Mux Select I2C0_SDA */
147 #define GPIO0_PIN3_MUX_SIM_RST_N GPIO_MUX_3 /**< GPIO0_PIN3 Mux Select SIM_RST_N */
148 #define GPIO0_PIN3_MUX_PWM1_C GPIO_MUX_4 /**< GPIO0_PIN3 Mux Select PWM1_C */
149 #define GPIO0_PIN3_MUX_PWM0_B GPIO_MUX_5 /**< GPIO0_PIN3 Mux Select PWM0_B */
150 /** @} */
151
152 /** @defgroup GPIOEx_GPIO0_PIN4_Mux_Selection GPIO0_PIN4 MUX selection
153 * @{
154 */
155 #define GPIO0_PIN4_MUX_UART0_RX GPIO_MUX_0 /**< GPIO0_PIN4 Mux Select UART0_RX */
156 #define GPIO0_PIN4_MUX_I2C1_SCL GPIO_MUX_1 /**< GPIO0_PIN4 Mux Select I2C1_SCL */
157 #define GPIO0_PIN4_MUX_SIM_IO GPIO_MUX_2 /**< GPIO0_PIN4 Mux Select SIM_IO */
158 #define GPIO0_PIN4_MUX_PDM_CLKO GPIO_MUX_3 /**< GPIO0_PIN4 Mux Select PDM_CLKO */
159 #define GPIO0_PIN4_MUX_PWM1_A GPIO_MUX_4 /**< GPIO0_PIN4 Mux Select PWM1_A */
160 #define GPIO0_PIN4_MUX_PWM0_B GPIO_MUX_5 /**< GPIO0_PIN4 Mux Select PWM0_B */
161 /** @} */
162
163 /** @defgroup GPIOEx_GPIO0_PIN5_Mux_Selection GPIO0_PIN5 MUX selection
164 * @{
165 */
166 #define GPIO0_PIN5_MUX_UART0_RX GPIO_MUX_0 /**< GPIO0_PIN5 Mux Select UART0_RX */
167 #define GPIO0_PIN5_MUX_I2C1_SDA GPIO_MUX_1 /**< GPIO0_PIN5 Mux Select I2C1_SDA */
168 #define GPIO0_PIN5_MUX_SIM_CLK GPIO_MUX_2 /**< GPIO0_PIN5 Mux Select SIM_CLK */
169 #define GPIO0_PIN5_MUX_PDM_DI GPIO_MUX_3 /**< GPIO0_PIN5 Mux Select PDM_DI */
170 #define GPIO0_PIN5_MUX_PWM1_A GPIO_MUX_4 /**< GPIO0_PIN5 Mux Select PWM1_A */
171 #define GPIO0_PIN5_MUX_PWM0_A GPIO_MUX_5 /**< GPIO0_PIN5 Mux Select PWM0_A */
172 /** @} */
173
174 /** @defgroup GPIOEx_GPIO0_PIN6_Mux_Selection GPIO0_PIN6 MUX selection
175 * @{
176 */
177 #define GPIO0_PIN5_MUX_SPIS_MOSI GPIO_MUX_0 /**< GPIO0_PIN6 Mux Select SPIS_MOSI */
178 #define GPIO0_PIN6_MUX_I2SM_WS GPIO_MUX_1 /**< GPIO0_PIN6 Mux Select I2S_WS */
179 #define GPIO0_PIN6_MUX_I2SS_WS GPIO_MUX_2 /**< GPIO0_PIN6 Mux Select I2S_S_WS */
180 #define GPIO0_PIN6_MUX_I2C1_SCL GPIO_MUX_3 /**< GPIO0_PIN6 Mux Select I2C1_SCL */
181 #define GPIO0_PIN6_MUX_UART1_CTS GPIO_MUX_4 /**< GPIO0_PIN6 Mux Select UART1_CTS */
182 #define GPIO0_PIN6_MUX_I2C0_SCL GPIO_MUX_5 /**< GPIO0_PIN6 Mux Select I2C0_SCL */
183 /** @} */
184
185 /** @defgroup GPIOEx_GPIO0_PIN7_Mux_Selection GPIO0_PIN7 MUX selection
186 * @{
187 */
188 #define GPIO0_PIN7_MUX_SPI_S_CLK GPIO_MUX_0 /**< GPIO0_PIN7 Mux Select SPI_S_CLK */
189 #define GPIO0_PIN7_MUX_I2S_TX_SDO GPIO_MUX_1 /**< GPIO0_PIN7 Mux Select I2S_TX_SDO */
190 #define GPIO0_PIN7_MUX_I2S_S_TX_SDO GPIO_MUX_2 /**< GPIO0_PIN7 Mux Select I2S_S_TX_SDO */
191 #define GPIO0_PIN7_MUX_I2C1_SDA GPIO_MUX_3 /**< GPIO0_PIN7 Mux Select I2C1_SDA */
192 #define GPIO0_PIN7_MUX_UART1_RTS GPIO_MUX_4 /**< GPIO0_PIN7 Mux Select UART1_RTS */
193 #define GPIO0_PIN7_MUX_I2C0_SDA GPIO_MUX_5 /**< GPIO0_PIN7 Mux Select I2C0_SDA */
194 /** @} */
195
196 /** @defgroup GPIOEx_GPIO0_PIN8_Mux_Selection GPIO0_PIN8 MUX selection
197 * @{
198 */
199 #define GPIO0_PIN8_MUX_SPI_S_MISO GPIO_MUX_0 /**< GPIO0_PIN8 Mux Select SPI_S_MISO */
200 #define GPIO0_PIN8_MUX_I2S_RX_SDI GPIO_MUX_1 /**< GPIO0_PIN8 Mux Select I2S_RX_SDI */
201 #define GPIO0_PIN8_MUX_I2S_S_RX_SDI GPIO_MUX_2 /**< GPIO0_PIN8 Mux Select I2S_S_RX_SDI */
202 #define GPIO0_PIN8_MUX_PDM_CLKO GPIO_MUX_3 /**< GPIO0_PIN8 Mux Select PDM_CLKO */
203 #define GPIO0_PIN8_MUX_UART1_TX GPIO_MUX_4 /**< GPIO0_PIN8 Mux Select UART1_TX */
204 #define GPIO0_PIN8_MUX_PWM0_A GPIO_MUX_5 /**< GPIO0_PIN8 Mux Select PWM0_A */
205 /** @} */
206
207 /** @defgroup GPIOEx_GPIO0_PIN9_Mux_Selection GPIO0_PIN9 MUX selection
208 * @{
209 */
210 #define GPIO0_PIN9_MUX_SPI_S_CS_N GPIO_MUX_0 /**< GPIO0_PIN9 Mux Select SPI_S_CS_N */
211 #define GPIO0_PIN9_MUX_I2S_SCLK GPIO_MUX_1 /**< GPIO0_PIN9 Mux Select I2S_SCLK */
212 #define GPIO0_PIN9_MUX_I2S_S_SCLK GPIO_MUX_2 /**< GPIO0_PIN9 Mux Select I2S_S_SCLK */
213 #define GPIO0_PIN9_MUX_PDM_DI GPIO_MUX_3 /**< GPIO0_PIN9 Mux Select PDM_DI */
214 #define GPIO0_PIN9_MUX_UART1_RX GPIO_MUX_4 /**< GPIO0_PIN9 Mux Select UART1_RX */
215 #define GPIO0_PIN9_MUX_PWM0_A GPIO_MUX_5 /**< GPIO0_PIN9 Mux Select PWM0_A */
216 /** @} */
217
218 /** @defgroup GPIOEx_GPIO0_PIN10_Mux_Selection GPIO0_PIN10 MUX selection
219 * @{
220 */
221 #define GPIO0_PIN10_MUX_QSPI_M0_IO_3 GPIO_MUX_0 /**< GPIO0_PIN10 Mux Select QSPI_M0_IO_3 */
222 #define GPIO0_PIN10_MUX_SWV GPIO_MUX_1 /**< GPIO0_PIN10 Mux Select SWV */
223 #define GPIO0_PIN10_MUX_UART0_RX GPIO_MUX_2 /**< GPIO0_PIN10 Mux Select UART0_RX */
224 #define GPIO0_PIN10_MUX_UART1_TX GPIO_MUX_3 /**< GPIO0_PIN10 Mux Select UART1_TX */
225 #define GPIO0_PIN10_MUX_I2C0_SCL GPIO_MUX_4 /**< GPIO0_PIN10 Mux Select I2C0_SCL */
226 #define GPIO0_PIN10_MUX_I2C1_SCL GPIO_MUX_5 /**< GPIO0_PIN10 Mux Select I2C1_SCL */
227 /** @} */
228
229 /** @defgroup GPIOEx_GPIO0_PIN11_Mux_Selection GPIO0_PIN11 MUX selection
230 * @{
231 */
232 #define GPIO0_PIN11_MUX_QSPI_M0_IO_2 GPIO_MUX_0 /**< GPIO0_PIN10 Mux Select QSPI_M0_IO_2 */
233 #define GPIO0_PIN11_MUX_SPI_M_CS1_N GPIO_MUX_1 /**< GPIO0_PIN10 Mux Select SPI_M_CS1_N */
234 #define GPIO0_PIN11_MUX_UART0_TX GPIO_MUX_2 /**< GPIO0_PIN10 Mux Select UART0_TX */
235 #define GPIO0_PIN11_MUX_UART1_RX GPIO_MUX_3 /**< GPIO0_PIN10 Mux Select UART1_RX */
236 #define GPIO0_PIN11_MUX_I2C0_SDA GPIO_MUX_4 /**< GPIO0_PIN10 Mux Select I2C0_SDA */
237 #define GPIO0_PIN11_MUX_I2C1_SDA GPIO_MUX_5 /**< GPIO0_PIN10 Mux Select I2C1_SDA */
238 /** @} */
239
240 /** @defgroup GPIOEx_GPIO0_PIN12_Mux_Selection GPIO0_PIN12 MUX selection
241 * @{
242 */
243 #define GPIO0_PIN12_MUX_QSPI_M0_CS_N GPIO_MUX_0 /**< GPIO0_PIN12 Mux Select QSPI_M0_CS_N */
244 #define GPIO0_PIN12_MUX_SPI_M_CS0_N GPIO_MUX_1 /**< GPIO0_PIN12 Mux Select SPI_M_CS0_N */
245 #define GPIO0_PIN12_MUX_SIM_PRESENCE GPIO_MUX_2 /**< GPIO0_PIN12 Mux Select SIM_PRESENCE */
246 #define GPIO0_PIN12_MUX_I2S_WS GPIO_MUX_3 /**< GPIO0_PIN12 Mux Select I2S_WS */
247 #define GPIO0_PIN12_MUX_I2S_S_WS GPIO_MUX_4 /**< GPIO0_PIN12 Mux Select I2S_S_WS */
248 #define GPIO0_PIN12_MUX_SPI_S_CS_N GPIO_MUX_5 /**< GPIO0_PIN12 Mux Select SPI_S_CS_N */
249 /** @} */
250
251 /** @defgroup GPIOEx_GPIO0_PIN13_Mux_Selection GPIO0_PIN13 MUX selection
252 * @{
253 */
254 #define GPIO0_PIN13_MUX_QSPI_M0_IO_1 GPIO_MUX_0 /**< GPIO0_PIN13 Mux Select QSPI_M0_IO_1 */
255 #define GPIO0_PIN13_MUX_SPI_M_MISO GPIO_MUX_1 /**< GPIO0_PIN13 Mux Select SPI_M_MISO */
256 #define GPIO0_PIN13_MUX_SIM_RST_N GPIO_MUX_2 /**< GPIO0_PIN13 Mux Select SIM_RST_N */
257 #define GPIO0_PIN13_MUX_I2S_TX_SDO GPIO_MUX_3 /**< GPIO0_PIN13 Mux Select I2S_TX_SDO */
258 #define GPIO0_PIN13_MUX_I2S_S_TX_SDO GPIO_MUX_4 /**< GPIO0_PIN13 Mux Select I2S_S_TX_SDO */
259 #define GPIO0_PIN13_MUX_SPI_S_MOSI GPIO_MUX_5 /**< GPIO0_PIN13 Mux Select SPI_S_MOSI */
260 /** @} */
261
262 /** @defgroup GPIOEx_GPIO0_PIN14_Mux_Selection GPIO0_PIN14 MUX selection
263 * @{
264 */
265 #define GPIO0_PIN14_MUX_QSPI_M0_IO_0 GPIO_MUX_0 /**< GPIO0_PIN14 Mux Select QSPI_M0_IO_0 */
266 #define GPIO0_PIN14_MUX_SPI_M_MOSI GPIO_MUX_1 /**< GPIO0_PIN14 Mux Select SPI_M_MOSI */
267 #define GPIO0_PIN14_MUX_SIM_IO GPIO_MUX_2 /**< GPIO0_PIN14 Mux Select SIM_IO */
268 #define GPIO0_PIN14_MUX_I2S_RX_SDI GPIO_MUX_3 /**< GPIO0_PIN14 Mux Select I2S_RX_SDI */
269 #define GPIO0_PIN14_MUX_I2S_S_RX_SDI GPIO_MUX_4 /**< GPIO0_PIN14 Mux Select I2S_S_RX_SDI */
270 #define GPIO0_PIN14_MUX_SPI_S_MISO GPIO_MUX_5 /**< GPIO0_PIN14 Mux Select SPI_S_MISO */
271 /** @} */
272
273 /** @defgroup GPIOEx_GPIO0_PIN15_Mux_Selection GPIO0_PIN15 MUX selection
274 * @{
275 */
276 #define GPIO0_PIN15_MUX_QSPI_M0_CLK GPIO_MUX_0 /**< GPIO0_PIN15 Mux Select QSPI_M0_CLK */
277 #define GPIO0_PIN15_MUX_SPI_M_CLK GPIO_MUX_1 /**< GPIO0_PIN15 Mux Select SPI_M_CLK */
278 #define GPIO0_PIN15_MUX_SIM_CLK GPIO_MUX_2 /**< GPIO0_PIN15 Mux Select SIM_CLK */
279 #define GPIO0_PIN15_MUX_I2S_SCLK GPIO_MUX_3 /**< GPIO0_PIN15 Mux Select I2S_SCLK */
280 #define GPIO0_PIN15_MUX_I2S_S_SCLK GPIO_MUX_4 /**< GPIO0_PIN15 Mux Select I2S_S_SCLK */
281 #define GPIO0_PIN15_MUX_SPI_S_CLK GPIO_MUX_5 /**< GPIO0_PIN15 Mux Select SPI_S_CLK */
282 /** @} */
283
284 /** @defgroup GPIOEx_GPIO1_PIN0_Mux_Selection GPIO1_PIN0 MUX selection
285 * @{
286 */
287 #define GPIO1_PIN0_MUX_XQSPI_M_CS_N GPIO_MUX_0 /**< GPIO1_PIN0 Mux Select XQSPI_M_CS_N */
288 /** @} */
289
290 /** @defgroup GPIOEx_GPIO1_PIN1_Mux_Selection GPIO1_PIN1 MUX selection
291 * @{
292 */
293 #define GPIO1_PIN1_MUX_XQSPI_M_IO_3 GPIO_MUX_0 /**< GPIO1_PIN1 Mux Select XQSPI_M_IO_3 */
294 /** @} */
295
296 /** @defgroup GPIOEx_GPIO1_PIN2_Mux_Selection GPIO1_PIN2 MUX selection
297 * @{
298 */
299 #define GPIO1_PIN2_MUX_XQSPI_M_CLK GPIO_MUX_0 /**< GPIO1_PIN2 Mux Select XQSPI_M_CLK */
300 /** @} */
301
302 /** @defgroup GPIOEx_GPIO1_PIN3_Mux_Selection GPIO1_PIN3 MUX selection
303 * @{
304 */
305 #define GPIO1_PIN3_MUX_XQSPI_M_IO_2 GPIO_MUX_0 /**< GPIO1_PIN3 Mux Select XQSPI_M_IO_2 */
306 /** @} */
307
308 /** @defgroup GPIOEx_GPIO1_PIN4_Mux_Selection GPIO1_PIN4 MUX selection
309 * @{
310 */
311 #define GPIO1_PIN4_MUX_XQSPI_M_IO_1 GPIO_MUX_0 /**< GPIO1_PIN4 Mux Select XQSPI_M_IO_1 */
312 /** @} */
313
314 /** @defgroup GPIOEx_GPIO1_PIN5_Mux_Selection GPIO1_PIN5 MUX selection
315 * @{
316 */
317 #define GPIO1_PIN5_MUX_XQSPI_M_IO_0 GPIO_MUX_0 /**< GPIO1_PIN5 Mux Select XQSPI_M_IO_0 */
318 /** @} */
319
320 /** @defgroup GPIOEx_GPIO1_PIN6_Mux_Selection GPIO1_PIN6 MUX selection
321 * @{
322 */
323 #define GPIO1_PIN6_MUX_QSPI_M1_CLK GPIO_MUX_0 /**< GPIO1_PIN6 Mux Select QSPI_M1_CLK */
324 /** @} */
325
326 /** @defgroup GPIOEx_GPIO1_PIN7_Mux_Selection GPIO1_PIN7 MUX selection
327 * @{
328 */
329 #define GPIO1_PIN7_MUX_QSPI_M1_IO_0 GPIO_MUX_0 /**< GPIO1_PIN7 Mux Select QSPI_M1_IO_0 */
330 /** @} */
331
332 /** @defgroup GPIOEx_GPIO1_PIN8_Mux_Selection GPIO1_PIN8 MUX selection
333 * @{
334 */
335 #define GPIO1_PIN8_MUX_QSPI_M1_IO_1 GPIO_MUX_0 /**< GPIO1_PIN8 Mux Select SPIM_CLK */
336 /** @} */
337
338 /** @defgroup GPIOEx_GPIO1_PIN9_Mux_Selection GPIO1_PIN9 MUX selection
339 * @{
340 */
341 #define GPIO1_PIN9_MUX_QSPI_M1_CS_N GPIO_MUX_0 /**< GPIO1_PIN9 Mux Select QSPI_M1_CS_N */
342 #define GPIO1_PIN9_MUX_DSPI_NSS GPIO_MUX_1 /**< GPIO1_PIN9 Mux Select DSPI_NSS */
343 #define GPIO1_PIN9_MUX_SPI_M_CS1_N GPIO_MUX_2 /**< GPIO1_PIN9 Mux Select SPI_M_CS1_N */
344 /** @} */
345
346 /** @defgroup GPIOEx_GPIO1_PIN10_Mux_Selection GPIO1_PIN10 MUX selection
347 * @{
348 */
349 #define GPIO1_PIN10_MUX_QSPI_M1_IO_2 GPIO_MUX_0 /**< GPIO1_PIN10 Mux Select QSPI_M1_IO_2 */
350 /** @} */
351
352 /** @defgroup GPIOEx_GPIO1_PIN11_Mux_Selection GPIO1_PIN11 MUX selection
353 * @{
354 */
355 #define GPIO1_PIN11_MUX_QSPI_M1_IO_3 GPIO_MUX_0 /**< GPIO1_PIN11 Mux Select QSPI_M1_IO_3 */
356 /** @} */
357
358 /** @defgroup GPIOEx_GPIO1_PIN12_Mux_Selection GPIO1_PIN12 MUX selection
359 * @{
360 */
361 #define GPIO1_PIN12_MUX_DSPI_DCX GPIO_MUX_0 /**< GPIO1_PIN12 Mux Select DSPI_DCX */
362 #define GPIO1_PIN12_MUX_SPI_M_CS0_N GPIO_MUX_1 /**< GPIO1_PIN12 Mux Select SPI_M_CS0_N */
363 #define GPIO1_PIN12_MUX_I2C1_SCL GPIO_MUX_2 /**< GPIO1_PIN12 Mux Select I2C1_SCL */
364 #define GPIO1_PIN12_MUX_PWM0_B GPIO_MUX_3 /**< GPIO1_PIN12 Mux Select PWM0_B */
365 #define GPIO1_PIN12_MUX_I2C0_SCL GPIO_MUX_4 /**< GPIO1_PIN12 Mux Select I2C0_SCL */
366 #define GPIO1_PIN12_MUX_PDM_CLKO GPIO_MUX_5 /**< GPIO1_PIN12 Mux Select PDM_CLKO */
367 /** @} */
368
369 /** @defgroup GPIOEx_GPIO1_PIN13_Mux_Selection GPIO1_PIN13 MUX selection
370 * @{
371 */
372 #define GPIO1_PIN12_MUX_DSPI_MOSI GPIO_MUX_0 /**< GPIO1_PIN13 Mux Select DSPI_MOSI */
373 #define GPIO1_PIN12_MUX_SPI_M_MOSI GPIO_MUX_1 /**< GPIO1_PIN13 Mux Select SPI_M_MOSI */
374 #define GPIO1_PIN12_MUX_I2C1_SDA GPIO_MUX_2 /**< GPIO1_PIN13 Mux Select I2C1_SDA */
375 #define GPIO1_PIN12_MUX_PWM0_A GPIO_MUX_3 /**< GPIO1_PIN13 Mux Select PWM0_A */
376 #define GPIO1_PIN12_MUX_I2C0_SDA GPIO_MUX_4 /**< GPIO1_PIN13 Mux Select I2C0_SDA */
377 #define GPIO1_PIN12_MUX_PDM_DI GPIO_MUX_5 /**< GPIO1_PIN13 Mux Select PDM_DI */
378 /** @} */
379
380 /** @defgroup GPIOEx_GPIO1_PIN14_Mux_Selection GPIO1_PIN14 MUX selection
381 * @{
382 */
383 #define GPIO1_PIN14_MUX_DSPI_MISO GPIO_MUX_0 /**< GPIO1_PIN14 Mux Select DSPI_MISO */
384 #define GPIO1_PIN14_MUX_SPI_M_MISO GPIO_MUX_1 /**< GPIO1_PIN14 Mux Select SPI_M_MISO */
385 /** @} */
386
387 /** @defgroup GPIOEx_GPIO1_PIN15_Mux_Selection GPIO1_PIN15 MUX selection
388 * @{
389 */
390 #define GPIO1_PIN15_MUX_DSPI_SCK GPIO_MUX_0 /**< GPIO1_PIN15 Mux Select DSPI_SCK */
391 #define GPIO1_PIN15_MUX_SPI_M_CLK GPIO_MUX_1 /**< GPIO1_PIN15 Mux Select SPI_M_CLK */
392 /** @} */
393
394 /**
395 * @brief Check if GPIO Mux mode is valid.
396 * @param __MUX__ GPIO mux mode.
397 * @retval SET (__ACTION__ is valid) or RESET (__ACTION__ is invalid)
398 */
399 #define IS_GPIO_MUX(__MUX__) (((__MUX__) <= GPIO_MUX_8))
400
401 /*------------------------------------------------------------------------------------------*/
402 #endif /* GR5X25 */
403
404 /** @} */
405
406 /** @} */
407
408 /** @} */
409
410 #ifdef __cplusplus
411 }
412 #endif
413
414 #endif /* __GR55xx_HAL_GPIO_EX_H__ */
415
416 /** @} */
417
418 /** @} */
419
420 /** @} */
gr55xx_ll_gpio.h
Header file containing functions prototypes of GPIO LL library.
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.