gr55xx_ll_aon_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_IO) || defined(MCU_RET)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
79 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
80
81 uint32_t mode; /**< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
83
84 AON_GPIO HW configuration can be modified afterwards using unitary function
85 @ref ll_aon_gpio_set_pin_mode(). */
86
87 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
88 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
89
90 AON_GPIO HW configuration can be modified afterwards using unitary function
91 @ref ll_aon_gpio_set_pin_pull(). */
92
93 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
94 This parameter can be a value of @ref AON_GPIO_LL_EC_MUX.
95
96 AON_GPIO HW configuration can be modified afterwards using unitary function
97 @ref ll_aon_gpio_set_pin_mux(). */
98
99 uint32_t speed; /**< Specifies the Speed for the selected pins.
100 This parameter can be a value of @ref AON_GPIO_LL_EC_SPEED.
101
102 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_speed().*/
103
104 uint32_t strength; /**< Specifies the Speed for the selected pins.
105 This parameter can be a value of @ref AON_GPIO_LL_EC_STRENGTH.
106
107 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_strength().*/
108
109 uint32_t input_type; /**< Specifies the input type for the selected pins.
110 This parameter can be a value of @ref AON_GPIO_LL_EC_INPUT_TYPE.
111
112 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_input_type().*/
113
114 uint32_t trigger; /**< Specifies the trigger signal active edge.
115 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
116 } ll_aon_gpio_init_t;
117
118 /** @} */
119
120 /** @} */
121
122 /**
123 * @defgroup AON_GPIO_LL_MACRO Defines
124 * @{
125 */
126
127 /* Exported constants --------------------------------------------------------*/
128 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
129 * @{
130 */
131 /** @defgroup AON_GPIO_LL_PRIVATE_MACRO AON_GPIO Mode
132 * @{
133 */
134 #define LL_AON_GPIO_MODE_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position AON_GPIO_LL_EC_MODE */
135 #define LL_AON_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position AON_GPIO_LL_EC_MODE */
136 #define LL_AON_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in AON_GPIO_LL_EC_STRENGTH */
137 #define LL_AON_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in AON_GPIO_LL_EC_STRENGTH */
138 #define LL_AON_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in AON_GPIO_LL_EC_STRENGTH */
139 #define LL_AON_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in AON_GPIO_LL_EC_STRENGTH */
140 /** @} */
141
142 /** @defgroup AON_GPIO_LL_EC_PIN PIN
143 * @{
144 */
145 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
146 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
147 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
148 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
149 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
150 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
151 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
152 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
153 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
154 /** @} */
155
156 /** @defgroup AON_GPIO_LL_EC_MODE Mode
157 * @{
158 */
159 #define LL_AON_GPIO_MODE_NONE ((uint32_t)0x0U) /**< No input or output */
160 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x1U) /**< Select input mode */
161 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x2U) /**< Select output mode */
162 #define LL_AON_GPIO_MODE_INOUT ((uint32_t)0x3U) /**< Select input and output mode */
163
164 /** @} */
165
166 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
167 * @{
168 */
169 #define LL_AON_GPIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
170 #define LL_AON_GPIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
171 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
172 /** @} */
173
174
175 /** @defgroup AON_GPIO_LL_EC_MUX Alternate Function
176 * @{
177 */
178 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
179 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
180 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
181 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
182 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
183 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
184 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
185 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
186 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
187 /** @} */
188
189
190 /** @defgroup AON_GPIO_LL_EC_SPEED IO speed
191 * @{
192 */
193 #define LL_AON_GPIO_SPEED_MEDIUM ((uint32_t)0x1U) /*!< Select medium speed */
194 #define LL_AON_GPIO_SPEED_HIGH ((uint32_t)0x0U) /*!< Select high speed */
195 /** @} */
196
197 /** @defgroup AON_GPIO_LL_EC_STRENGTH IO strength
198 * @{
199 */
200 #define LL_AON_GPIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
201 #define LL_AON_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
202 #define LL_AON_GPIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
203 #define LL_AON_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
204 /** @} */
205
206 /** @defgroup AON_GPIO_LL_EC_INPUT_TYPE Input type
207 * @{
208 */
209 #define LL_AON_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
210 #define LL_AON_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
211 /** @} */
212
213 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
214 * @{
215 */
216 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
217 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
218 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
219 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
220 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
221 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /**< Trigger both edge */
222 /** @} */
223
224
225 /** @defgroup AON_GPIO_LL_CLOCK_OUT Select clock output via AON_GPIO_4
226 * @{
227 */
228 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U) /**< RNG_OSC_32K */
229 #define LL_CLK_RNG_OSC_2MHZ ((uint32_t)0x01U) /**< RNG_OSC_2MHz */
230 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U) /**< RC_OSC_CLK */
231 #define LL_CLK_RTC_CLK ((uint32_t)0x03U) /**< RTC_CLK */
232 /** @} */
233
234
235 /** @} */
236
237 /* Exported macro ------------------------------------------------------------*/
238 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
239 * @{
240 */
241
242 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
243 * @{
244 */
245
246 /**
247 * @brief Write a value in AON_GPIO register
248 * @param __instance__ AON_GPIO instance
249 * @param __REG__ Register to be written
250 * @param __VALUE__ Value to be written in the register
251 * @retval None
252 */
253 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
254
255 /**
256 * @brief Read a value in AON_GPIO register
257 * @param __instance__ AON_GPIO instance
258 * @param __REG__ Register to be read
259 * @retval Register value
260 */
261 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262
263 /** @} */
264
265 /** @} */
266
267 /* Private types -------------------------------------------------------------*/
268 /* Private variables ---------------------------------------------------------*/
269 /* Private constants ---------------------------------------------------------*/
270 /* Private macros ------------------------------------------------------------*/
271 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
272 * @{
273 */
274 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
275 * @{
276 */
277
278 /**
279 * @brief LL AON_GPIO InitStrcut default configuartion
280 */
281 #define LL_AON_GPIO_DEFAULT_CONFIG \
282 { \
283 .pin = LL_AON_GPIO_PIN_ALL, \
284 .mode = LL_AON_GPIO_MODE_INPUT, \
285 .pull = LL_AON_GPIO_PULL_DOWN, \
286 .mux = LL_AON_GPIO_MUX_8, \
287 .speed = LL_AON_GPIO_SPEED_MEDIUM, \
288 .strength = LL_AON_GPIO_STRENGTH_MEDIUM, \
289 .input_type = LL_AON_GPIO_INPUT_TYPE_CMOS, \
290 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
291 }
292 /** @} */
293
294 /** @} */
295
296 /** @} */
297
298 /* Exported functions --------------------------------------------------------*/
299 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
300 * @{
301 */
302
303 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
304 * @{
305 */
306
307 /**
308 * @brief Set several AON_GPIO pins to input/output mode.
309 *
310 * Register|BitsName
311 * --------|--------
312 * AON_PAD_CTL1 | AON_GPO_OE_N
313 *
314 * @param pin_mask This parameter can be a combination of the following values:
315 * @arg @ref LL_AON_GPIO_PIN_0
316 * @arg @ref LL_AON_GPIO_PIN_1
317 * @arg @ref LL_AON_GPIO_PIN_2
318 * @arg @ref LL_AON_GPIO_PIN_3
319 * @arg @ref LL_AON_GPIO_PIN_4
320 * @arg @ref LL_AON_GPIO_PIN_5
321 * @arg @ref LL_AON_GPIO_PIN_6
322 * @arg @ref LL_AON_GPIO_PIN_7
323 * @arg @ref LL_AON_GPIO_PIN_ALL
324 * @param mode This parameter can be one of the following values:
325 * @arg @ref LL_AON_GPIO_MODE_NONE
326 * @arg @ref LL_AON_GPIO_MODE_INPUT
327 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
328 * @arg @ref LL_AON_GPIO_MODE_INOUT
329 * @retval None
330 */
331 __STATIC_FORCEINLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
332 {
333 uint32_t ie_mask = (pin_mask << AON_IO_AON_PAD_IE_POS) & AON_IO_AON_PAD_IE;
334 uint32_t oe_mask = (pin_mask << AON_IO_AON_PAD_OE_POS) & AON_IO_AON_PAD_OE;
335 uint32_t ie = ((mode == LL_AON_GPIO_MODE_INPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
336 uint32_t oe = ((mode == LL_AON_GPIO_MODE_OUTPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
337 MODIFY_REG(AON_IO->AON_PAD_CTRL0, ie_mask, ie);
338 MODIFY_REG(AON_IO->AON_PAD_CTRL0, oe_mask, oe);
339 }
340
341 /**
342 * @brief Return gpio mode for a AON_GPIO pin.
343 * @note I/O mode can be Input mode. General purpose output.
344 * @note Warning: only one pin can be passed as parameter.
345 *
346 * Register|BitsName
347 * --------|--------
348 * AON_PAD_CTL0 | IE
349 * AON_PAD_CTL1 | OE
350 *
351 * @param pin This parameter can be one of the following values:
352 * @arg @ref LL_AON_GPIO_PIN_0
353 * @arg @ref LL_AON_GPIO_PIN_1
354 * @arg @ref LL_AON_GPIO_PIN_2
355 * @arg @ref LL_AON_GPIO_PIN_3
356 * @arg @ref LL_AON_GPIO_PIN_4
357 * @arg @ref LL_AON_GPIO_PIN_5
358 * @arg @ref LL_AON_GPIO_PIN_6
359 * @arg @ref LL_AON_GPIO_PIN_7
360 * @retval Returned value can be one of the following values:
361 * @arg @ref LL_AON_GPIO_MODE_NONE
362 * @arg @ref LL_AON_GPIO_MODE_INPUT
363 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
364 * @arg @ref LL_AON_GPIO_MODE_INOUT
365 */
366 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
367 {
368 uint32_t ie_mask = (pin << AON_IO_AON_PAD_IE_POS) & AON_IO_AON_PAD_IE;
369 uint32_t oe_mask = (pin << AON_IO_AON_PAD_OE_POS) & AON_IO_AON_PAD_OE;
370 uint32_t ie = READ_BITS(AON_IO->AON_PAD_CTRL0, ie_mask) >> (POSITION_VAL(pin));
371 uint32_t oe = READ_BITS(AON_IO->AON_PAD_CTRL0, oe_mask) >> (POSITION_VAL(pin));
372 return (((ie >> AON_IO_AON_PAD_IE_POS) << LL_AON_GPIO_MODE_INPUT_POS)
373 | ((oe >> AON_IO_AON_PAD_OE_POS) << LL_AON_GPIO_MODE_OUTPUT_POS));
374 }
375
376 /**
377 * @brief Set several AON_GPIO pins to input type.
378 *
379 * Register|BitsName
380 * --------|--------
381 * AON_PAD_CTL2 | IS
382 *
383 * @param pin_mask This parameter can be a combination of the following values:
384 * @arg @ref LL_AON_GPIO_PIN_0
385 * @arg @ref LL_AON_GPIO_PIN_1
386 * @arg @ref LL_AON_GPIO_PIN_2
387 * @arg @ref LL_AON_GPIO_PIN_3
388 * @arg @ref LL_AON_GPIO_PIN_4
389 * @arg @ref LL_AON_GPIO_PIN_5
390 * @arg @ref LL_AON_GPIO_PIN_6
391 * @arg @ref LL_AON_GPIO_PIN_7
392 * @arg @ref LL_AON_GPIO_PIN_ALL
393 * @param type This parameter can be one of the following values:
394 * @arg @ref LL_AON_GPIO_INPUT_TYPE_CMOS
395 * @arg @ref LL_AON_GPIO_INPUT_TYPE_SCHMITT
396 * @retval None
397 */
398 __STATIC_INLINE void ll_aon_gpio_set_pin_input_type(uint32_t pin_mask, uint32_t type)
399 {
400 pin_mask = (pin_mask << AON_IO_AON_PAD_IS_POS) & AON_IO_AON_PAD_IS;
401 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask, (type == LL_AON_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
402 }
403
404 /**
405 * @brief Return input type for a AON_GPIO pin.
406 * @note I/O mode can be Input mode. General purpose output.
407 * @note Warning: only one pin can be passed as parameter.
408 *
409 * Register|BitsName
410 * --------|--------
411 * AON_PAD_CTL2 | IS
412 *
413 * @param pin This parameter can be one of the following values:
414 * @arg @ref LL_AON_GPIO_PIN_0
415 * @arg @ref LL_AON_GPIO_PIN_1
416 * @arg @ref LL_AON_GPIO_PIN_2
417 * @arg @ref LL_AON_GPIO_PIN_3
418 * @arg @ref LL_AON_GPIO_PIN_4
419 * @arg @ref LL_AON_GPIO_PIN_5
420 * @arg @ref LL_AON_GPIO_PIN_6
421 * @arg @ref LL_AON_GPIO_PIN_7
422 * @retval Returned value can be one of the following values:
423 * @arg @ref LL_AON_GPIO_INPUT_TYPE_CMOS
424 * @arg @ref LL_AON_GPIO_INPUT_TYPE_SCHMITT
425 */
426 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_input_type(uint32_t pin)
427 {
428 pin = (pin << AON_IO_AON_PAD_IS_POS) & AON_IO_AON_PAD_IS;
429 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL2, pin) == pin) ?
430 LL_AON_GPIO_INPUT_TYPE_SCHMITT : LL_AON_GPIO_INPUT_TYPE_CMOS);
431 }
432
433 /**
434 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
435 * @note Warning: only one pin can be passed as parameter.
436 *
437 * Register|BitsName
438 * --------|--------
439 * AON_PAD_CTL0 | PE
440 * AON_PAD_CTL0 | PS
441 *
442 * @param pin_mask This parameter can be a combination of the following values:
443 * @arg @ref LL_AON_GPIO_PIN_0
444 * @arg @ref LL_AON_GPIO_PIN_1
445 * @arg @ref LL_AON_GPIO_PIN_2
446 * @arg @ref LL_AON_GPIO_PIN_3
447 * @arg @ref LL_AON_GPIO_PIN_4
448 * @arg @ref LL_AON_GPIO_PIN_5
449 * @arg @ref LL_AON_GPIO_PIN_6
450 * @arg @ref LL_AON_GPIO_PIN_7
451 * @arg @ref LL_AON_GPIO_PIN_ALL
452 * @param pull This parameter can be one of the following values:
453 * @arg @ref LL_AON_GPIO_PULL_NO
454 * @arg @ref LL_AON_GPIO_PULL_UP
455 * @arg @ref LL_AON_GPIO_PULL_DOWN
456 * @retval None
457 */
458 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
459 {
460 uint32_t ps_mask = (pin_mask << AON_IO_AON_PAD_PS_POS) & AON_IO_AON_PAD_PS;
461 uint32_t pe_mask = (pin_mask << AON_IO_AON_PAD_PE_POS) & AON_IO_AON_PAD_PE;
462 uint32_t ps = (pull == LL_AON_GPIO_PULL_UP) ? ps_mask : 0x0000U;
463 uint32_t pe = (pull == LL_AON_GPIO_PULL_NO) ? 0x0000U : pe_mask;
464 MODIFY_REG(AON_IO->AON_PAD_CTRL1, pe_mask | ps_mask, pe | ps);
465 }
466
467 /**
468 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
469 * @note Warning: only one pin can be passed as parameter.
470 *
471 * Register|BitsName
472 * --------|--------
473 * AON_PAD_CTL0 | PE
474 * AON_PAD_CTL0 | PS
475 *
476 * @param pin This parameter can be one of the following values:
477 * @arg @ref LL_AON_GPIO_PIN_0
478 * @arg @ref LL_AON_GPIO_PIN_1
479 * @arg @ref LL_AON_GPIO_PIN_2
480 * @arg @ref LL_AON_GPIO_PIN_3
481 * @arg @ref LL_AON_GPIO_PIN_4
482 * @arg @ref LL_AON_GPIO_PIN_5
483 * @arg @ref LL_AON_GPIO_PIN_6
484 * @arg @ref LL_AON_GPIO_PIN_7
485 * @retval Returned value can be one of the following values:
486 * @arg @ref LL_AON_GPIO_PULL_NO
487 * @arg @ref LL_AON_GPIO_PULL_UP
488 * @arg @ref LL_AON_GPIO_PULL_DOWN
489 */
490 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
491 {
492 uint32_t ps_mask = (pin << AON_IO_AON_PAD_PS_POS) & AON_IO_AON_PAD_PS;
493 uint32_t pe_mask = (pin << AON_IO_AON_PAD_PE_POS) & AON_IO_AON_PAD_PE;
494 return ((READ_BITS(AON_IO->AON_PAD_CTRL1, pe_mask) == RESET) ? LL_AON_GPIO_PULL_NO :
495 ((READ_BITS(AON_IO->AON_PAD_CTRL1, ps_mask) == RESET) ? LL_AON_GPIO_PULL_DOWN : LL_AON_GPIO_PULL_UP));
496 }
497
498 /**
499 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
500 * @note Possible values are from AF0 to AF15 depending on target.
501 * @note Warning: only one pin can be passed as parameter.
502 *
503 * Register|BitsName
504 * --------|--------
505 * AON_PAD_MUX_CTRL | CTRL0_7
506 * AON_PAD_CTL_0 | MCU_OVR
507 *
508 * @param pin This parameter can be one of the following values:
509 * @arg @ref LL_AON_GPIO_PIN_0
510 * @arg @ref LL_AON_GPIO_PIN_1
511 * @arg @ref LL_AON_GPIO_PIN_2
512 * @arg @ref LL_AON_GPIO_PIN_3
513 * @arg @ref LL_AON_GPIO_PIN_4
514 * @arg @ref LL_AON_GPIO_PIN_5
515 * @arg @ref LL_AON_GPIO_PIN_6
516 * @arg @ref LL_AON_GPIO_PIN_7
517 * @param mux This parameter can be one of the following values:
518 * @arg @ref LL_AON_GPIO_MUX_0
519 * @arg @ref LL_AON_GPIO_MUX_1
520 * @arg @ref LL_AON_GPIO_MUX_2
521 * @arg @ref LL_AON_GPIO_MUX_3
522 * @arg @ref LL_AON_GPIO_MUX_4
523 * @arg @ref LL_AON_GPIO_MUX_5
524 * @arg @ref LL_AON_GPIO_MUX_6
525 * @arg @ref LL_AON_GPIO_MUX_7
526 * @arg @ref LL_AON_GPIO_MUX_8
527 * @retval None
528 */
529 __STATIC_INLINE void ll_aon_gpio_set_pin_mux(uint32_t pin, uint32_t mux)
530 {
531 uint32_t pos = POSITION_VAL(pin) << 2;
532 MODIFY_REG(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
533 if(LL_AON_GPIO_MUX_8 == mux)
534 {
535 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
536 }
537 else
538 {
539 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
540 }
541 }
542
543 /**
544 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
545 *
546 * Register|BitsName
547 * --------|--------
548 * AON_PAD_MUX_CTRL | CTRL0_7
549 * AON_PAD_CTL_0 | MCU_OVR
550 *
551 * @param pin This parameter can be one of the following values:
552 * @arg @ref LL_AON_GPIO_PIN_0
553 * @arg @ref LL_AON_GPIO_PIN_1
554 * @arg @ref LL_AON_GPIO_PIN_2
555 * @arg @ref LL_AON_GPIO_PIN_3
556 * @arg @ref LL_AON_GPIO_PIN_4
557 * @arg @ref LL_AON_GPIO_PIN_5
558 * @arg @ref LL_AON_GPIO_PIN_6
559 * @arg @ref LL_AON_GPIO_PIN_7
560 * @retval Returned value can be one of the following values:
561 * @arg @ref LL_AON_GPIO_MUX_0
562 * @arg @ref LL_AON_GPIO_MUX_1
563 * @arg @ref LL_AON_GPIO_MUX_2
564 * @arg @ref LL_AON_GPIO_MUX_3
565 * @arg @ref LL_AON_GPIO_MUX_4
566 * @arg @ref LL_AON_GPIO_MUX_5
567 * @arg @ref LL_AON_GPIO_MUX_6
568 * @arg @ref LL_AON_GPIO_MUX_7
569 * @arg @ref LL_AON_GPIO_MUX_8
570 */
571 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mux(uint32_t pin)
572 {
573 if(READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
574 {
575 uint32_t pos = POSITION_VAL(pin) << 2;
576 return (READ_BITS(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
577 }
578 else
579 {
580 return LL_AON_GPIO_MUX_8;
581 }
582 }
583
584 /**
585 * @brief Configure slew rate for a dedicated AON_GPIO pin.
586 * @note Warning: only one pin can be passed as parameter.
587 *
588 * Register|BitsName
589 * --------|--------
590 * AON_PAD_CTRL2 | SR
591 *
592 * @param pin_mask This parameter can be a combination of the following values:
593 * @arg @ref LL_AON_GPIO_PIN_0
594 * @arg @ref LL_AON_GPIO_PIN_1
595 * @arg @ref LL_AON_GPIO_PIN_2
596 * @arg @ref LL_AON_GPIO_PIN_3
597 * @arg @ref LL_AON_GPIO_PIN_4
598 * @arg @ref LL_AON_GPIO_PIN_5
599 * @arg @ref LL_AON_GPIO_PIN_6
600 * @arg @ref LL_AON_GPIO_PIN_7
601 * @arg @ref LL_AON_GPIO_PIN_ALL
602 * @param speed This parameter can be one of the following values:
603 * @arg @ref LL_AON_GPIO_SPEED_MEDIUM
604 * @arg @ref LL_AON_GPIO_SPEED_HIGH
605 * @retval None
606 */
607 __STATIC_INLINE void ll_aon_gpio_set_pin_speed(uint32_t pin_mask, uint32_t speed)
608 {
609 uint32_t pos;
610 pos = POSITION_VAL(pin_mask);
611 MODIFY_REG(AON_IO->AON_PAD_CTRL1, pin_mask << AON_IO_AON_PAD_SR_POS, speed << pos << AON_IO_AON_PAD_SR_POS);
612 }
613
614 /**
615 * @brief Return slew rate for a dedicated AON_GPIO pin.
616 * @note Warning: only one pin can be passed as parameter.
617 *
618 * Register|BitsName
619 * --------|--------
620 * AON_PAD_CTRL2 | SR
621 *
622 * @param pin This parameter can be one of the following values:
623 * @arg @ref LL_AON_GPIO_PIN_0
624 * @arg @ref LL_AON_GPIO_PIN_1
625 * @arg @ref LL_AON_GPIO_PIN_2
626 * @arg @ref LL_AON_GPIO_PIN_3
627 * @arg @ref LL_AON_GPIO_PIN_4
628 * @arg @ref LL_AON_GPIO_PIN_5
629 * @arg @ref LL_AON_GPIO_PIN_6
630 * @arg @ref LL_AON_GPIO_PIN_7
631 * @retval Returned value can be one of the following values:
632 * @arg @ref LL_AON_GPIO_SPEED_MEDIUM
633 * @arg @ref LL_AON_GPIO_SPEED_HIGH
634 */
635 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_speed(uint32_t pin)
636 {
637 uint32_t pos;
638 pos = POSITION_VAL(pin);
639 return (READ_BITS(AON_IO->AON_PAD_CTRL1, pin << AON_IO_AON_PAD_SR_POS) >> AON_IO_AON_PAD_SR_POS >> pos);
640 }
641
642
643 /**
644 * @brief Configure output drive strength for a dedicated AON_GPIO pin.
645 * @note Warning: only one pin can be passed as parameter.
646 *
647 * Register|BitsName
648 * --------|--------
649 * AON_PAD_CTL3 | DS0
650 * AON_PAD_CTL3 | DS1
651 *
652 * @param pin_mask This parameter can be a combination of the following values:
653 * @arg @ref LL_AON_GPIO_PIN_0
654 * @arg @ref LL_AON_GPIO_PIN_1
655 * @arg @ref LL_AON_GPIO_PIN_2
656 * @arg @ref LL_AON_GPIO_PIN_3
657 * @arg @ref LL_AON_GPIO_PIN_4
658 * @arg @ref LL_AON_GPIO_PIN_5
659 * @arg @ref LL_AON_GPIO_PIN_6
660 * @arg @ref LL_AON_GPIO_PIN_7
661 * @arg @ref LL_AON_GPIO_PIN_ALL
662 * @param strength This parameter can be one of the following values:
663 * @arg @ref LL_AON_GPIO_STRENGTH_LOW
664 * @arg @ref LL_AON_GPIO_STRENGTH_MEDIUM
665 * @arg @ref LL_AON_GPIO_STRENGTH_HIGH
666 * @arg @ref LL_AON_GPIO_STRENGTH_ULTRA
667 * @retval None
668 */
669 __STATIC_INLINE void ll_aon_gpio_set_pin_strength(uint32_t pin_mask, uint32_t strength)
670 {
671 uint32_t pos;
672 pos = POSITION_VAL(pin_mask);
673 uint8_t ds0 = (strength & LL_AON_GPIO_STRENGTH_DS0_MASK) >> LL_AON_GPIO_STRENGTH_DS0_POS;
674 uint8_t ds1 = (strength & LL_AON_GPIO_STRENGTH_DS1_MASK) >> LL_AON_GPIO_STRENGTH_DS1_POS;
675 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS0_POS , ds0 << pos << AON_IO_AON_PAD_DS0_POS);
676 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS1_POS , ds1 << pos << AON_IO_AON_PAD_DS1_POS);
677 }
678
679 /**
680 * @brief Return output strength for a dedicated AON_GPIO pin.
681 * @note Warning: only one pin can be passed as parameter.
682 *
683 * Register|BitsName
684 * --------|--------
685 * AON_PAD_CTL3 | DS0
686 * AON_PAD_CTL3 | DS1
687 *
688 * @param pin_mask This parameter can be one of the following values:
689 * @arg @ref LL_AON_GPIO_PIN_0
690 * @arg @ref LL_AON_GPIO_PIN_1
691 * @arg @ref LL_AON_GPIO_PIN_2
692 * @arg @ref LL_AON_GPIO_PIN_3
693 * @arg @ref LL_AON_GPIO_PIN_4
694 * @arg @ref LL_AON_GPIO_PIN_5
695 * @arg @ref LL_AON_GPIO_PIN_6
696 * @arg @ref LL_AON_GPIO_PIN_7
697 * @retval Returned value can be one of the following values:
698 * @arg @ref LL_AON_GPIO_STRENGTH_LOW
699 * @arg @ref LL_AON_GPIO_STRENGTH_MEDIUM
700 * @arg @ref LL_AON_GPIO_STRENGTH_HIGH
701 * @arg @ref LL_AON_GPIO_STRENGTH_ULTRA
702 */
703 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_strength(uint32_t pin_mask)
704 {
705 uint32_t pos;
706 pos = POSITION_VAL(pin_mask);
707 uint8_t ds0 = READ_BITS(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS0_POS ) >> AON_IO_AON_PAD_DS0_POS >> pos;
708 uint8_t ds1 = READ_BITS(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS1_POS ) >> AON_IO_AON_PAD_DS1_POS >> pos;
709 return ((ds0 << LL_AON_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_AON_GPIO_STRENGTH_DS1_POS));
710 }
711 /**
712 * @brief Enable clock output on AON_GPIO_PIN4.
713 *
714 * Register|BitsName
715 * --------|--------
716 * AON_PAD_CLK | AON_PAD_CLK
717 *
718 * @param clk_sel This parameter can be the following values:
719 * @arg @ref LL_CLK_RNG_OSC_32K
720 * @arg @ref LL_CLK_RNG_OSC_2MHZ
721 * @arg @ref LL_CLK_RC_OSC_CLK
722 * @arg @ref LL_CLK_RTC_CLK
723 * @retval None
724 */
725 __STATIC_INLINE void ll_aon_gpio4_enable_clk_output(uint32_t clk_sel)
726 {
727 MODIFY_REG(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
728 AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
729 }
730
731 /**
732 * @brief Disable clock output on AON_GPIO_PIN4.
733 *
734 * Register|BitsName
735 * --------|--------
736 * AON_PAD_CLK | AON_PAD_CLK
737 *
738 * @retval None
739 */
740 __STATIC_INLINE void ll_aon_gpio4_disable_clk_output(void)
741 {
742 CLEAR_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
743 }
744
745 /**
746 * @brief Check if clock output on AON_GPIO_PIN4 is enabled or disabled.
747 *
748 * Register|BitsName
749 * --------|--------
750 * AON_PAD_CLK | AON_PAD_CLK
751 *
752 * @retval State of bit (1 or 0).
753 */
754 __STATIC_INLINE uint32_t ll_aon_gpio4_is_enabled_clk_output(void)
755 {
756 return (READ_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
757 }
758
759 /**
760 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
761 *
762 * Register|BitsName
763 * --------|--------
764 * PWR_RET01 | XO_2MHZ_ENA
765 *
766 * @retval None
767 */
768 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
769 {
770 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
771 }
772
773 /**
774 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
775 *
776 * Register|BitsName
777 * --------|--------
778 * PWR_RET01 | XO_2MHZ_ENA
779 *
780 * @retval None
781 */
782 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
783 {
784 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
785 }
786
787 /**
788 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
789 *
790 * Register|BitsName
791 * --------|--------
792 * PWR_RET01 | XO_2MHZ_ENA
793 *
794 * @retval None
795 */
796 __STATIC_FORCEINLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
797 {
798 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
799 }
800
801 /** @} */
802
803 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
804 * @{
805 */
806
807 /**
808 * @brief Return full input data register value of AON_GPIO.
809 *
810 * Register|BitsName
811 * --------|--------
812 * AON_PAD_CTL1 | O_AON_GPI
813 *
814 * @retval Input data register value of port
815 */
816 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
817 {
818 uint32_t pin_mask = (LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_IN_VAL_POS) & AON_IO_AON_PAD_IN_VAL;
819 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) >> AON_IO_AON_PAD_IN_VAL_POS);
820 }
821
822 /**
823 * @brief Return if input data level of several AON_GPIO pins is high or low.
824 *
825 * Register|BitsName
826 * --------|--------
827 * AON_PAD_CTL1 | O_AON_GPI
828 *
829 * @param pin_mask This parameter can be a combination of the following values:
830 * @arg @ref LL_AON_GPIO_PIN_0
831 * @arg @ref LL_AON_GPIO_PIN_1
832 * @arg @ref LL_AON_GPIO_PIN_2
833 * @arg @ref LL_AON_GPIO_PIN_3
834 * @arg @ref LL_AON_GPIO_PIN_4
835 * @arg @ref LL_AON_GPIO_PIN_5
836 * @arg @ref LL_AON_GPIO_PIN_6
837 * @arg @ref LL_AON_GPIO_PIN_7
838 * @arg @ref LL_AON_GPIO_PIN_ALL
839 * @retval State of bit (1 or 0).
840 */
841 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_pin(uint32_t pin_mask)
842 {
843 pin_mask = (pin_mask << AON_IO_AON_PAD_IN_VAL_POS) & AON_IO_AON_PAD_IN_VAL;
844 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
845 }
846
847 /**
848 * @brief Return if output data level of several AON_GPIO pins is high or low.
849 *
850 * Register|BitsName
851 * --------|--------
852 * AON_PAD_CTL1 | AON_GPIO
853 *
854 * @param pin_mask This parameter can be a combination of the following values:
855 * @arg @ref LL_AON_GPIO_PIN_0
856 * @arg @ref LL_AON_GPIO_PIN_1
857 * @arg @ref LL_AON_GPIO_PIN_2
858 * @arg @ref LL_AON_GPIO_PIN_3
859 * @arg @ref LL_AON_GPIO_PIN_4
860 * @arg @ref LL_AON_GPIO_PIN_5
861 * @arg @ref LL_AON_GPIO_PIN_6
862 * @arg @ref LL_AON_GPIO_PIN_7
863 * @arg @ref LL_AON_GPIO_PIN_ALL
864 * @retval State of bit (1 or 0).
865 */
866 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_pin(uint32_t pin_mask)
867 {
868 pin_mask = (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL;
869 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
870 }
871 /**
872 * @brief Write output data register of AON_GPIO.
873 *
874 * Register|BitsName
875 * --------|--------
876 * AON_PAD_CTL1 | AON_GPO
877 *
878 * @param port_value Level value for each pin of the port
879 * @retval None
880 */
881 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
882 {
883 MODIFY_REG(AON_IO->AON_PAD_CTRL0, AON_IO_AON_PAD_OUT_VAL, (port_value << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
884 }
885
886 /**
887 * @brief Return full output data register value of AON_GPIO.
888 *
889 * Register|BitsName
890 * --------|--------
891 * AON_PAD_CTL1 | AON_GPO
892 *
893 * @retval Output data register value of port
894 */
895 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
896 {
897 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, AON_IO_AON_PAD_OUT_VAL) >> AON_IO_AON_PAD_OUT_VAL_POS);
898 }
899
900 /**
901 * @brief Return if input data level of several AON_GPIO pins is high or low.
902 *
903 * Register|BitsName
904 * --------|--------
905 * AON_PAD_CTL1 | AON_GPO
906 *
907 * @param pin_mask This parameter can be a combination of the following values:
908 * @arg @ref LL_AON_GPIO_PIN_0
909 * @arg @ref LL_AON_GPIO_PIN_1
910 * @arg @ref LL_AON_GPIO_PIN_2
911 * @arg @ref LL_AON_GPIO_PIN_3
912 * @arg @ref LL_AON_GPIO_PIN_4
913 * @arg @ref LL_AON_GPIO_PIN_5
914 * @arg @ref LL_AON_GPIO_PIN_6
915 * @arg @ref LL_AON_GPIO_PIN_7
916 * @arg @ref LL_AON_GPIO_PIN_ALL
917 * @retval State of bit (1 or 0).
918 */
919 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
920 {
921 pin_mask = (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL;
922 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
923 }
924
925 /**
926 * @brief Set specified AON_GPIO pins to high level
927 *
928 * Register|BitsName
929 * --------|--------
930 * AON_PAD_CTL1 | AON_GPO
931 *
932 * @param pin_mask This parameter can be a combination of the following values:
933 * @arg @ref LL_AON_GPIO_PIN_0
934 * @arg @ref LL_AON_GPIO_PIN_1
935 * @arg @ref LL_AON_GPIO_PIN_2
936 * @arg @ref LL_AON_GPIO_PIN_3
937 * @arg @ref LL_AON_GPIO_PIN_4
938 * @arg @ref LL_AON_GPIO_PIN_5
939 * @arg @ref LL_AON_GPIO_PIN_6
940 * @arg @ref LL_AON_GPIO_PIN_7
941 * @arg @ref LL_AON_GPIO_PIN_ALL
942 * @retval None
943 */
944 __STATIC_FORCEINLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
945 {
946 SET_BITS(AON_IO->AON_PAD_CTRL0, (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
947 }
948
949 /**
950 * @brief Set specified AON_GPIO pins to low level.
951 *
952 * Register|BitsName
953 * --------|--------
954 * AON_PAD_CTL1 | AON_GPO
955 *
956 * @param pin_mask This parameter can be a combination of the following values:
957 * @arg @ref LL_AON_GPIO_PIN_0
958 * @arg @ref LL_AON_GPIO_PIN_1
959 * @arg @ref LL_AON_GPIO_PIN_2
960 * @arg @ref LL_AON_GPIO_PIN_3
961 * @arg @ref LL_AON_GPIO_PIN_4
962 * @arg @ref LL_AON_GPIO_PIN_5
963 * @arg @ref LL_AON_GPIO_PIN_6
964 * @arg @ref LL_AON_GPIO_PIN_7
965 * @arg @ref LL_AON_GPIO_PIN_ALL
966 * @retval None
967 */
968 __STATIC_FORCEINLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
969 {
970 CLEAR_BITS(AON_IO->AON_PAD_CTRL0, (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
971 }
972
973 /**
974 * @brief Toggle data value of specified AON_GPIO pins.
975 *
976 * Register|BitsName
977 * --------|--------
978 * AON_PAD_CTL1 | AON_GPO
979 *
980 * @param pin_mask This parameter can be a combination of the following values:
981 * @arg @ref LL_AON_GPIO_PIN_0
982 * @arg @ref LL_AON_GPIO_PIN_1
983 * @arg @ref LL_AON_GPIO_PIN_2
984 * @arg @ref LL_AON_GPIO_PIN_3
985 * @arg @ref LL_AON_GPIO_PIN_4
986 * @arg @ref LL_AON_GPIO_PIN_5
987 * @arg @ref LL_AON_GPIO_PIN_6
988 * @arg @ref LL_AON_GPIO_PIN_7
989 * @arg @ref LL_AON_GPIO_PIN_ALL
990 * @retval None
991 */
992 __STATIC_FORCEINLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
993 {
994 WRITE_REG(AON_IO->AON_PAD_CTRL0, (READ_REG(AON_IO->AON_PAD_CTRL0)
995 ^ ((pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL)));
996 }
997
998 /** @} */
999
1000 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
1001 * @{
1002 */
1003
1004 /**
1005 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
1006 *
1007 * Register|BitsName
1008 * --------|--------
1009 * INTPOLCLR | INTPOLCLR
1010 * INTTYPESET | INTTYPESET
1011 *
1012 * @param pin_mask This parameter can be a combination of the following values:
1013 * @arg @ref LL_AON_GPIO_PIN_0
1014 * @arg @ref LL_AON_GPIO_PIN_1
1015 * @arg @ref LL_AON_GPIO_PIN_2
1016 * @arg @ref LL_AON_GPIO_PIN_3
1017 * @arg @ref LL_AON_GPIO_PIN_4
1018 * @arg @ref LL_AON_GPIO_PIN_5
1019 * @arg @ref LL_AON_GPIO_PIN_6
1020 * @arg @ref LL_AON_GPIO_PIN_7
1021 * @arg @ref LL_AON_GPIO_PIN_ALL
1022 * @retval None
1023 */
1024 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
1025 {
1026 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1027 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1028 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1029 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1030 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1031 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
1032 }
1033
1034 /**
1035 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
1036 *
1037 * Register|BitsName
1038 * --------|--------
1039 * INTPOLCLR | INTPOLCLR
1040 * INTTYPESET | INTTYPESET
1041 *
1042 * @param pin_mask This parameter can be a combination of the following values:
1043 * @arg @ref LL_AON_GPIO_PIN_0
1044 * @arg @ref LL_AON_GPIO_PIN_1
1045 * @arg @ref LL_AON_GPIO_PIN_2
1046 * @arg @ref LL_AON_GPIO_PIN_3
1047 * @arg @ref LL_AON_GPIO_PIN_4
1048 * @arg @ref LL_AON_GPIO_PIN_5
1049 * @arg @ref LL_AON_GPIO_PIN_6
1050 * @arg @ref LL_AON_GPIO_PIN_7
1051 * @arg @ref LL_AON_GPIO_PIN_ALL
1052 * @retval State of bit (1 or 0)
1053 */
1054 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
1055 {
1056 uint32_t invert = ((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1057 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1058 uint32_t edge_type = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1059 return (invert && edge_en && edge_type);
1060 }
1061
1062 /**
1063 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
1064 *
1065 * Register|BitsName
1066 * --------|--------
1067 * INTPOLSET | INTPOLSET
1068 * INTTYPESET | INTTYPESET
1069 *
1070 * @param pin_mask This parameter can be a combination of the following values:
1071 * @arg @ref LL_AON_GPIO_PIN_0
1072 * @arg @ref LL_AON_GPIO_PIN_1
1073 * @arg @ref LL_AON_GPIO_PIN_2
1074 * @arg @ref LL_AON_GPIO_PIN_3
1075 * @arg @ref LL_AON_GPIO_PIN_4
1076 * @arg @ref LL_AON_GPIO_PIN_5
1077 * @arg @ref LL_AON_GPIO_PIN_6
1078 * @arg @ref LL_AON_GPIO_PIN_7
1079 * @arg @ref LL_AON_GPIO_PIN_ALL
1080 * @retval None
1081 */
1082 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
1083 {
1084 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1085 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1086 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1087 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1088 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1089 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
1090 }
1091
1092 /**
1093 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
1094 * @note Please check each device line mapping for AON_GPIO Line availability
1095 *
1096 * Register|BitsName
1097 * --------|--------
1098 * INTPOLSET | INTPOLSET
1099 * INTTYPESET | INTTYPESET
1100 *
1101 * @param pin_mask This parameter can be a combination of the following values:
1102 * @arg @ref LL_AON_GPIO_PIN_0
1103 * @arg @ref LL_AON_GPIO_PIN_1
1104 * @arg @ref LL_AON_GPIO_PIN_2
1105 * @arg @ref LL_AON_GPIO_PIN_3
1106 * @arg @ref LL_AON_GPIO_PIN_4
1107 * @arg @ref LL_AON_GPIO_PIN_5
1108 * @arg @ref LL_AON_GPIO_PIN_6
1109 * @arg @ref LL_AON_GPIO_PIN_7
1110 * @arg @ref LL_AON_GPIO_PIN_ALL
1111 * @retval State of bit (1 or 0).
1112 */
1113 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
1114 {
1115 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1116 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1117 uint32_t edge_type = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1118 return (invert && edge_en && edge_type);
1119 }
1120
1121 /**
1122 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
1123 *
1124 * Register|BitsName
1125 * --------|--------
1126 * INTPOLSET | INTPOLSET
1127 * INTTYPECLR | INTTYPECLR
1128 *
1129 * @param pin_mask This parameter can be a combination of the following values:
1130 * @arg @ref LL_AON_GPIO_PIN_0
1131 * @arg @ref LL_AON_GPIO_PIN_1
1132 * @arg @ref LL_AON_GPIO_PIN_2
1133 * @arg @ref LL_AON_GPIO_PIN_3
1134 * @arg @ref LL_AON_GPIO_PIN_4
1135 * @arg @ref LL_AON_GPIO_PIN_5
1136 * @arg @ref LL_AON_GPIO_PIN_6
1137 * @arg @ref LL_AON_GPIO_PIN_7
1138 * @arg @ref LL_AON_GPIO_PIN_ALL
1139 * @retval None
1140 */
1141 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
1142 {
1143 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1144 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1145 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1146 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
1147 }
1148
1149 /**
1150 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
1151 *
1152 * Register|BitsName
1153 * --------|--------
1154 * INTPOLSET | INTPOLSET
1155 * INTTYPECLR | INTTYPECLR
1156 *
1157 * @param pin_mask This parameter can be a combination of the following values:
1158 * @arg @ref LL_AON_GPIO_PIN_0
1159 * @arg @ref LL_AON_GPIO_PIN_1
1160 * @arg @ref LL_AON_GPIO_PIN_2
1161 * @arg @ref LL_AON_GPIO_PIN_3
1162 * @arg @ref LL_AON_GPIO_PIN_4
1163 * @arg @ref LL_AON_GPIO_PIN_5
1164 * @arg @ref LL_AON_GPIO_PIN_6
1165 * @arg @ref LL_AON_GPIO_PIN_7
1166 * @arg @ref LL_AON_GPIO_PIN_ALL
1167 * @retval State of bit (1 or 0).
1168 */
1169 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
1170 {
1171 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1172 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1173 return (invert && edge_en );
1174 }
1175
1176 /**
1177 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
1178 *
1179 * Register|BitsName
1180 * --------|--------
1181 * INTPOLCLR | INTPOLCLR
1182 * INTTYPECLR | INTTYPECLR
1183 *
1184 * @param pin_mask This parameter can be a combination of the following values:
1185 * @arg @ref LL_AON_GPIO_PIN_0
1186 * @arg @ref LL_AON_GPIO_PIN_1
1187 * @arg @ref LL_AON_GPIO_PIN_2
1188 * @arg @ref LL_AON_GPIO_PIN_3
1189 * @arg @ref LL_AON_GPIO_PIN_4
1190 * @arg @ref LL_AON_GPIO_PIN_5
1191 * @arg @ref LL_AON_GPIO_PIN_6
1192 * @arg @ref LL_AON_GPIO_PIN_7
1193 * @arg @ref LL_AON_GPIO_PIN_ALL
1194 * @retval None
1195 */
1196 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
1197 {
1198 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1199 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1200 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1201 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
1202 }
1203
1204 /**
1205 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
1206 *
1207 * Register|BitsName
1208 * --------|--------
1209 * INTPOLCLR | INTPOLCLR
1210 * INTTYPECLR | INTTYPECLR
1211 *
1212 * @param pin_mask This parameter can be a combination of the following values:
1213 * @arg @ref LL_AON_GPIO_PIN_0
1214 * @arg @ref LL_AON_GPIO_PIN_1
1215 * @arg @ref LL_AON_GPIO_PIN_2
1216 * @arg @ref LL_AON_GPIO_PIN_3
1217 * @arg @ref LL_AON_GPIO_PIN_4
1218 * @arg @ref LL_AON_GPIO_PIN_5
1219 * @arg @ref LL_AON_GPIO_PIN_6
1220 * @arg @ref LL_AON_GPIO_PIN_7
1221 * @arg @ref LL_AON_GPIO_PIN_ALL
1222 * @retval State of bit (1 or 0).
1223 */
1224 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
1225 {
1226 uint32_t invert = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1227 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1228 return (invert && edge_en);
1229 }
1230
1231 /**
1232 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
1233 *
1234 * Register|BitsName
1235 * --------|--------
1236 * INTPOLCLR | INTPOLCLR
1237 * INTTYPECLR | INTTYPECLR
1238 *
1239 * @param pin_mask This parameter can be a combination of the following values:
1240 * @arg @ref LL_AON_GPIO_PIN_0
1241 * @arg @ref LL_AON_GPIO_PIN_1
1242 * @arg @ref LL_AON_GPIO_PIN_2
1243 * @arg @ref LL_AON_GPIO_PIN_3
1244 * @arg @ref LL_AON_GPIO_PIN_4
1245 * @arg @ref LL_AON_GPIO_PIN_5
1246 * @arg @ref LL_AON_GPIO_PIN_6
1247 * @arg @ref LL_AON_GPIO_PIN_7
1248 * @arg @ref LL_AON_GPIO_PIN_ALL
1249 * @retval None
1250 */
1251 __STATIC_INLINE void ll_aon_gpio_enable_both_trigger(uint32_t pin_mask)
1252 {
1253 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1254 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1255 SET_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en | both);
1256 }
1257
1258 /**
1259 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
1260 *
1261 * Register|BitsName
1262 * --------|--------
1263 * INTPOLCLR | INTPOLCLR
1264 * INTTYPECLR | INTTYPECLR
1265 *
1266 * @param pin_mask This parameter can be a combination of the following values:
1267 * @arg @ref LL_AON_GPIO_PIN_0
1268 * @arg @ref LL_AON_GPIO_PIN_1
1269 * @arg @ref LL_AON_GPIO_PIN_2
1270 * @arg @ref LL_AON_GPIO_PIN_3
1271 * @arg @ref LL_AON_GPIO_PIN_4
1272 * @arg @ref LL_AON_GPIO_PIN_5
1273 * @arg @ref LL_AON_GPIO_PIN_6
1274 * @arg @ref LL_AON_GPIO_PIN_7
1275 * @arg @ref LL_AON_GPIO_PIN_ALL
1276 * @retval State of bit (1 or 0)
1277 */
1278 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_both_trigger(uint32_t pin_mask)
1279 {
1280 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1281 uint32_t edge_both = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1282 return ( edge_en && edge_both);
1283 }
1284
1285 /**
1286 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
1287 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1288 *
1289 * Register|BitsName
1290 * --------|--------
1291 * INTENSET | INTENSET
1292 *
1293 * @param pin_mask This parameter can be a combination of the following values:
1294 * @arg @ref LL_AON_GPIO_PIN_0
1295 * @arg @ref LL_AON_GPIO_PIN_1
1296 * @arg @ref LL_AON_GPIO_PIN_2
1297 * @arg @ref LL_AON_GPIO_PIN_3
1298 * @arg @ref LL_AON_GPIO_PIN_4
1299 * @arg @ref LL_AON_GPIO_PIN_5
1300 * @arg @ref LL_AON_GPIO_PIN_6
1301 * @arg @ref LL_AON_GPIO_PIN_7
1302 * @arg @ref LL_AON_GPIO_PIN_ALL
1303 * @retval None
1304 */
1305 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
1306 {
1307 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1308 }
1309
1310 /**
1311 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
1312 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1313 *
1314 * Register|BitsName
1315 * --------|--------
1316 * INTENCLR | INTENCLR
1317 *
1318 * @param pin_mask This parameter can be a combination of the following values:
1319 * @arg @ref LL_AON_GPIO_PIN_0
1320 * @arg @ref LL_AON_GPIO_PIN_1
1321 * @arg @ref LL_AON_GPIO_PIN_2
1322 * @arg @ref LL_AON_GPIO_PIN_3
1323 * @arg @ref LL_AON_GPIO_PIN_4
1324 * @arg @ref LL_AON_GPIO_PIN_5
1325 * @arg @ref LL_AON_GPIO_PIN_6
1326 * @arg @ref LL_AON_GPIO_PIN_7
1327 * @arg @ref LL_AON_GPIO_PIN_ALL
1328 * @retval None
1329 */
1330 __STATIC_FORCEINLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
1331 {
1332 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1333 }
1334
1335 /**
1336 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1337 *
1338 * Register|BitsName
1339 * --------|--------
1340 * INTENSET | INTENSET
1341 *
1342 * @param pin_mask This parameter can be a combination of the following values:
1343 * @arg @ref LL_AON_GPIO_PIN_0
1344 * @arg @ref LL_AON_GPIO_PIN_1
1345 * @arg @ref LL_AON_GPIO_PIN_2
1346 * @arg @ref LL_AON_GPIO_PIN_3
1347 * @arg @ref LL_AON_GPIO_PIN_4
1348 * @arg @ref LL_AON_GPIO_PIN_5
1349 * @arg @ref LL_AON_GPIO_PIN_6
1350 * @arg @ref LL_AON_GPIO_PIN_7
1351 * @arg @ref LL_AON_GPIO_PIN_ALL
1352 * @retval State of bit (1 or 0).
1353 */
1354 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1355 {
1356 return ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1357 }
1358
1359 /**
1360 * @brief Get aon gpio enable pins.
1361 *
1362 * Register|BitsName
1363 * --------|--------
1364 * INTENSET | INTENSET
1365 * @retval Returned value can be one of the following values:
1366 * @arg @ref LL_AON_GPIO_PIN_0
1367 * @arg @ref LL_AON_GPIO_PIN_1
1368 * @arg @ref LL_AON_GPIO_PIN_2
1369 * @arg @ref LL_AON_GPIO_PIN_3
1370 * @arg @ref LL_AON_GPIO_PIN_4
1371 * @arg @ref LL_AON_GPIO_PIN_5
1372 * @arg @ref LL_AON_GPIO_PIN_6
1373 * @arg @ref LL_AON_GPIO_PIN_7
1374 * @arg @ref LL_AON_GPIO_PIN_ALL
1375 */
1376 __STATIC_INLINE uint32_t ll_aon_gpio_get_enabled_pin(void)
1377 {
1378 return (READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1379 }
1380
1381 /**
1382 * @brief Check if the AON_GPIO master interrupt is enabled or disabled.
1383 *
1384 * Register|BitsName
1385 * --------|--------
1386 * AON_MISC | MCU_WAKEUP_CTRL
1387 * @retval State of bit (1 or 0).
1388 */
1389 __STATIC_INLINE uint32_t ll_aon_gpio_is_enable_wakeup_it(void)
1390 {
1391 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_EXT) == (AON_CTL_MCU_WAKEUP_CTRL_EXT));
1392 }
1393 /** @} */
1394
1395 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
1396 * @{
1397 */
1398
1399 /**
1400 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
1401 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1402 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1403 *
1404 * Register|BitsName
1405 * --------|--------
1406 * INTSTATUS | INTSTATUS
1407 *
1408 * @param pin_mask This parameter can be a combination of the following values:
1409 * @arg @ref LL_AON_GPIO_PIN_0
1410 * @arg @ref LL_AON_GPIO_PIN_1
1411 * @arg @ref LL_AON_GPIO_PIN_2
1412 * @arg @ref LL_AON_GPIO_PIN_3
1413 * @arg @ref LL_AON_GPIO_PIN_4
1414 * @arg @ref LL_AON_GPIO_PIN_5
1415 * @arg @ref LL_AON_GPIO_PIN_6
1416 * @arg @ref LL_AON_GPIO_PIN_7
1417 * @arg @ref LL_AON_GPIO_PIN_ALL
1418 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1419 */
1420 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1421 {
1422 return (READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1423 }
1424
1425 /**
1426 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1427 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1428 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1429 *
1430 * Register|BitsName
1431 * --------|--------
1432 * INTSTATUS | INTSTATUS
1433 *
1434 * @param pin_mask This parameter can be a combination of the following values:
1435 * @arg @ref LL_AON_GPIO_PIN_0
1436 * @arg @ref LL_AON_GPIO_PIN_1
1437 * @arg @ref LL_AON_GPIO_PIN_2
1438 * @arg @ref LL_AON_GPIO_PIN_3
1439 * @arg @ref LL_AON_GPIO_PIN_4
1440 * @arg @ref LL_AON_GPIO_PIN_5
1441 * @arg @ref LL_AON_GPIO_PIN_6
1442 * @arg @ref LL_AON_GPIO_PIN_7
1443 * @arg @ref LL_AON_GPIO_PIN_ALL
1444 * @retval State of bit (1 or 0).
1445 */
1446 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1447 {
1448 return ((READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1449 }
1450
1451 /**
1452 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1453 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1454 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1455 *
1456 * Register|BitsName
1457 * --------|--------
1458 * INTSTATUS | INTSTATUS
1459 *
1460 * @param pin_mask This parameter can be a combination of the following values:
1461 * @arg @ref LL_AON_GPIO_PIN_0
1462 * @arg @ref LL_AON_GPIO_PIN_1
1463 * @arg @ref LL_AON_GPIO_PIN_2
1464 * @arg @ref LL_AON_GPIO_PIN_3
1465 * @arg @ref LL_AON_GPIO_PIN_4
1466 * @arg @ref LL_AON_GPIO_PIN_5
1467 * @arg @ref LL_AON_GPIO_PIN_6
1468 * @arg @ref LL_AON_GPIO_PIN_7
1469 * @arg @ref LL_AON_GPIO_PIN_ALL
1470 * @retval None
1471 */
1472 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1473 {
1474 CLEAR_BITS(AON_IO->EXT_WAKEUP_STAT, pin_mask);
1475 }
1476
1477 /**
1478 * @brief Indicate if the AON GPIO event flag is set or not.
1479 * @note This bit is set by hardware when system wakeup by AON GPIO.
1480 * It can be cleared by writing 0 to this bit.
1481 *
1482 * Register|BitsName
1483 * --------|--------
1484 * SLP_EVENT | AON GPIO
1485 *
1486 * @retval State of bit (1 or 0).
1487 */
1488 __STATIC_INLINE uint32_t ll_aon_gpio_read_event_flag_it(void)
1489 {
1490 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1491 }
1492
1493 /**
1494 * @brief Clear AON GPIO event interrupt flag.
1495 *
1496 * Register|BitsName
1497 * --------|--------
1498 * SLP_EVENT| AON GPIO
1499 *
1500 * @retval None
1501 */
1502 __STATIC_INLINE void ll_aon_gpio_clear_event_flag_it(void)
1503 {
1504 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);
1505 }
1506
1507 /** @} */
1508
1509 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1510 * @{
1511 */
1512 /**
1513 * @brief Initialize AON_GPIO registers according to the specified.
1514 * parameters in p_aon_gpio_init.
1515 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1516 * information for the specified AON_GPIO peripheral.
1517 * @retval An error_status_t enumeration value:
1518 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1519 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1520 */
1521 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1522
1523 /** @} */
1524
1525 /** @} */
1526
1527 #endif /* AON */
1528
1529 #ifdef __cplusplus
1530 }
1531 #endif
1532
1533 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1534
1535 /** @} */
1536
1537 /** @} */
1538
1539 /** @} */