gr55xx_ll_adc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_adc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of ADC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_ADC ADC
47 * @brief ADC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_ADC_H__
53 #define __GR55XX_LL_ADC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_CTL)
63
64 /** @defgroup ADC_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup ADC_LL_ES_INIT ADC Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL ADC init Structure definition
75 */
76 typedef struct _ll_adc_init
77 {
78 uint32_t channel_p; /**< Specifies the input source to ADC channel P.
79 This parameter can be any value of @ref ADC_LL_EC_INPUT_SRC.
80
81 This parament can be modified afterwards using unitary function @ref ll_adc_set_channelp(). */
82
83 uint32_t channel_n; /**< Specifies the input source to ADC channel N.
84 This parameter can be any value of @ref ADC_LL_EC_INPUT_SRC.
85
86 This parament can be modified afterwards using unitary function @ref ll_adc_set_channeln(). */
87
88 uint32_t input_mode; /**< Specifies the operation mode for the ADC sample.
89 This parameter can be a value of @ref ADC_LL_EC_INPUT_MODE.
90
91 This parament can be modified afterwards using unitary function @ref ll_adc_set_input_mode(). */
92
93 uint32_t ref_source; /**< Specifies the source of the ADC reference.
94 This parameter can be a value of @ref ADC_LL_EC_REFERENCE_SRC.
95
96 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref().*/
97
98 uint32_t ref_value; /*!< Specifies the value of the ADC buffered reference.
99 This parameter can be a value of @ref ADC_LL_EC_REFERENCE.
100
101 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref_value().*/
102
103 uint32_t clock; /**< Specifies the clock of ADC.
104 This parameter can be a value of @ref ADC_LL_EC_CLK.
105
106 This parament can be modified afterwards using unitary function @ref ll_adc_set_clock().*/
107
108 } ll_adc_init_t;
109
110 /** @} */
111
112 /** @} */
113
114 /**
115 * @defgroup ADC_LL_MACRO Defines
116 * @{
117 */
118
119 /* Exported constants --------------------------------------------------------*/
120 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
121 * @{
122 */
123
124 /** @defgroup ADC_LL_EC_CLK ADC CLOCK
125 * @{
126 */
127 #if defined(GR5X25)
128 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16 MHz */
129 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8 MHz */
130 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4 MHz */
131 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 1 MHz */
132 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16KHz */
133 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8KHz */
134 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4KHz */
135 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< Close Clock*/
136 #endif
137 /** @} */
138
139 /** @defgroup ADC_LL_EC_REFERENCE ADC Buffered Internal Reference Value
140 * @{
141 */
142 #define LL_ADC_REF_VALUE_0P8 (0x4UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 0.85 V */
143 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.28 V */
144 #define LL_ADC_REF_VALUE_1P6 (0xBUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.60 V */
145 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 2.00 V */
146 /** @} */
147
148 /** @defgroup ADC_LL_EC_INPUT_MODE ADC Input Mode
149 * @{
150 */
151 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos) /**< Single ended mode */
152 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL) /**< Differential mode */
153 /** @} */
154
155 /** @defgroup ADC_LL_EC_INPUT_SRC ADC Input Source
156 * @{
157 */
158 #define LL_ADC_INPUT_SRC_IO0 (0UL) /**< Select MSIO0 as input */
159 #define LL_ADC_INPUT_SRC_IO1 (1UL) /**< Select MSIO1 as input */
160 #define LL_ADC_INPUT_SRC_IO2 (2UL) /**< Select MSIO2 as input */
161 #define LL_ADC_INPUT_SRC_IO3 (3UL) /**< Select MSIO3 as input */
162 #define LL_ADC_INPUT_SRC_IO4 (4UL) /**< Select MSIO4 as input */
163 #define LL_ADC_INPUT_SRC_IO5 (5UL) /**< Select MSIO5 as input */
164 #define LL_ADC_INPUT_SRC_IO6 (6UL) /**< Select MSIO6 as input */
165 #define LL_ADC_INPUT_SRC_IO7 (7UL) /**< Select MSIO7 as input */
166 #define LL_ADC_INPUT_SRC_TMP (13UL) /**< Select temperature as input */
167 #define LL_ADC_INPUT_SRC_BAT (14UL) /**< Select Vbattery as input */
168 #define LL_ADC_INPUT_SRC_REF (15UL) /**< Select reference as input */
169
170 /** @} */
171
172 /** @defgroup ADC_LL_EC_REFERENCE_SRC ADC Reference Source
173 * @{
174 */
175 #if defined(GR5X25)
176 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL) /**< Select buffered internal reference as reference */
177 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO0 as reference */
178 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO1 as reference */
179 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO2 as reference */
180 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO3 as reference */
181 #endif
182 /** @} */
183
184 /** @defgroup ADC_LL_CFG_REG_DEFAULT ADC Config Register Default Value
185 * @{
186 */
187 #define LL_ADC_CFG_REG_DEFAULT (0x0710070AU) /**< The default value of the SNSADC_CFG register in AON_PMU */
188 /** @} */
189
190 /** @} */
191
192 /* Exported macro ------------------------------------------------------------*/
193 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
194 * @{
195 */
196
197 /** @defgroup ADC_LL_EM_WRITE_READ Common Write and read registers Macros
198 * @{
199 */
200
201 /**
202 * @brief Write a value in ADC register
203 * @param __instance__ ADC instance
204 * @param __REG__ Register to be written
205 * @param __VALUE__ Value to be written in the register
206 * @retval None
207 */
208 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
209
210 /**
211 * @brief Read a value in ADC register
212 * @param __instance__ ADC instance
213 * @param __REG__ Register to be read
214 * @retval Register value
215 */
216 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
217
218 /** @} */
219
220 /** @} */
221
222 /* Private types -------------------------------------------------------------*/
223 /* Private variables ---------------------------------------------------------*/
224 /* Private constants ---------------------------------------------------------*/
225 /* Private macros ------------------------------------------------------------*/
226 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
227 * @{
228 */
229
230 /** @defgroup ADC_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
231 * @{
232 */
233
234 /**
235 * @brief LL ADC InitStrcut default configuartion
236 */
237 #if defined(GR5X25)
238 #define LL_ADC_DEFAULT_CONFIG \
239 { \
240 .channel_p = LL_ADC_INPUT_SRC_IO0, \
241 .channel_n = LL_ADC_INPUT_SRC_IO1, \
242 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
243 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
244 .ref_value = LL_ADC_REF_VALUE_1P2, \
245 .clock = LL_ADC_CLK_16M \
246 }
247 #else
248 #define LL_ADC_DEFAULT_CONFIG \
249 { \
250 .channel_p = LL_ADC_INPUT_SRC_IO0, \
251 .channel_n = LL_ADC_INPUT_SRC_IO1, \
252 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
253 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
254 .ref_value = LL_ADC_REF_VALUE_1P2, \
255 .clock = LL_ADC_CLK_16 \
256 }
257 #endif
258 /** @} */
259
260 /** @} */
261
262 /** @} */
263
264 /* Exported functions --------------------------------------------------------*/
265 /** @defgroup ADC_LL_DRIVER_FUNCTIONS Functions
266 * @{
267 */
268
269 /** @defgroup ADC_LL_EF_Configuration Basic Configuration
270 * @{
271 */
272
273 /**
274 * @brief Enable ADC module.
275 *
276 * Register|BitsName
277 * --------|--------
278 * SNSADC_CFG | REG4
279 *
280 * @retval None
281 */
282 __STATIC_INLINE void ll_adc_enable(void)
283 {
284 #if defined(GR5X25)
285 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
286 #endif
287 }
288
289 /**
290 * @brief Disable ADC module.
291 *
292 * Register|BitsName
293 * --------|--------
294 * SNSADC_CFG | REG4
295 *
296 * @retval None
297 */
298 __STATIC_INLINE void ll_adc_disable(void)
299 {
300 #if defined(GR5X25)
301 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
302 #endif
303 }
304
305 /**
306 * @brief Check if ADC module is enabled.
307 *
308 * Register|BitsName
309 * --------|--------
310 * SNSADC_CFG | REG4
311 *
312 * @retval State of bit (1 or 0).
313 */
314 __STATIC_INLINE uint32_t ll_adc_is_enabled(void)
315 {
316 #if defined(GR5X25)
317 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
318 #endif
319 }
320
321 /**
322 * @brief Disable ADC clock.
323 *
324 * Register|BitsName
325 * --------|--------
326 * MSIO_PAD_CFG_1 | ADC_CLK_EN
327 *
328 * @retval None
329 */
330 __STATIC_INLINE void ll_adc_disable_clock(void)
331 {
332 #if defined(GR5X25)
333 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
334 #endif
335 }
336
337 /**
338 * @brief Check if ADC clock is enabled.
339 *
340 * Register|BitsName
341 * --------|--------
342 * MSIO_PAD_CFG_1 | ADC_CLK_EN
343 *
344 * @retval State of bit (1 or 0).
345 */
346 __STATIC_INLINE uint32_t ll_adc_is_enabled_clock(void)
347 {
348 #if defined(GR5X25)
349 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
350 #endif
351 }
352
353 /**
354 * @brief Set ADC clock source.
355 *
356 * Register|BitsName
357 * --------|--------
358 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
359 *
360 * @param clk This parameter can be one of the following values:
361 * @arg @ref LL_ADC_CLK_16M
362 * @arg @ref LL_ADC_CLK_8M
363 * @arg @ref LL_ADC_CLK_4M
364 * @arg @ref LL_ADC_CLK_1M
365 * @arg @ref LL_ADC_CLK_16K
366 * @arg @ref LL_ADC_CLK_8K
367 * @arg @ref LL_ADC_CLK_4K
368 * @retval None
369 */
370 __STATIC_INLINE void ll_adc_set_clock(uint32_t clk)
371 {
372 #if defined(GR5X25)
373 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
374 #endif
375 }
376
377 /**
378 * @brief Return source for ADC clock.
379 *
380 * Register|BitsName
381 * --------|--------
382 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
383 *
384 * @retval Returned value can be one of the following values:
385 * @arg @ref LL_ADC_CLK_16M
386 * @arg @ref LL_ADC_CLK_8M
387 * @arg @ref LL_ADC_CLK_4M
388 * @arg @ref LL_ADC_CLK_1M
389 * @arg @ref LL_ADC_CLK_16K
390 * @arg @ref LL_ADC_CLK_8K
391 * @arg @ref LL_ADC_CLK_4K
392 */
393 __STATIC_INLINE uint32_t ll_adc_get_clock(void)
394 {
395 #if defined(GR5X25)
396 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
397 #endif
398 }
399
400 /**
401 * @brief Set ADC bias reference.
402 *
403 * Register|BitsName
404 * --------|--------
405 * SNSADC_CFG | REG1
406 *
407 * @param value This parameter can be one of the following values:
408 * @arg @ref LL_ADC_REF_VALUE_0P8
409 * @arg @ref LL_ADC_REF_VALUE_1P2
410 * @arg @ref LL_ADC_REF_VALUE_1P6
411 * @arg @ref LL_ADC_REF_VALUE_2P0
412 * @retval None
413 */
414 __STATIC_INLINE void ll_adc_set_ref_value(uint32_t value)
415 {
416 #if defined(GR5X25)
417 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
418 #endif
419 }
420
421 /**
422 * @brief Return ADC bias reference.
423 *
424 * Register|BitsName
425 * --------|--------
426 * SNSADC_CFG | REG1
427 *
428 * @retval Returned value can be one of the following values:
429 * @arg @ref LL_ADC_REF_VALUE_0P8
430 * @arg @ref LL_ADC_REF_VALUE_1P2
431 * @arg @ref LL_ADC_REF_VALUE_1P6
432 * @arg @ref LL_ADC_REF_VALUE_2P0
433 */
434 __STATIC_INLINE uint32_t ll_adc_get_ref_value(void)
435 {
436 #if defined(GR5X25)
437 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
438 #endif
439 }
440
441 /**
442 * @brief Enable temperature sensor.
443 *
444 * Register|BitsName
445 * --------|--------
446 * SNSADC_CFG | REG2
447 *
448 * @retval None
449 */
450 __STATIC_INLINE void ll_adc_enable_temp(void)
451 {
452 #if defined(GR5X25)
453 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
454 #endif
455 }
456
457 /**
458 * @brief Disable temperature sensor.
459 *
460 * Register|BitsName
461 * --------|--------
462 * SNSADC_CFG | REG2
463 *
464 * @retval None
465 */
466 __STATIC_INLINE void ll_adc_disable_temp(void)
467 {
468 #if defined(GR5X25)
469 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
470 #endif
471 }
472
473 /**
474 * @brief Check if temperature sensor is enabled.
475 *
476 * Register|BitsName
477 * --------|--------
478 * SNSADC_CFG | REG2
479 *
480 * @retval State of bit (1 or 0).
481 */
482 __STATIC_INLINE uint32_t ll_adc_is_enabled_temp(void)
483 {
484 #if defined(GR5X25)
485 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
486 #endif
487 }
488
489 /**
490 * @brief Enable Vbattery sensor.
491 *
492 * Register|BitsName
493 * --------|--------
494 * SNSADC_CFG | REG2
495 *
496 * @retval None
497 */
498 __STATIC_INLINE void ll_adc_enable_vbat(void)
499 {
500 #if defined(GR5X25)
501 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
502 #endif
503 }
504
505 /**
506 * @brief Disable Vbattery sensor.
507 *
508 * Register|BitsName
509 * --------|--------
510 * SNSADC_CFG | REG2
511 *
512 * @retval None
513 */
514 __STATIC_INLINE void ll_adc_disable_vbat(void)
515 {
516 #if defined(GR5X25)
517 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
518 #endif
519 }
520
521 /**
522 * @brief Check if Vbattery sensor is enabled.
523 *
524 * Register|BitsName
525 * --------|--------
526 * SNSADC_CFG | REG2
527 *
528 * @retval State of bit (1 or 0).
529 */
530 __STATIC_INLINE uint32_t ll_adc_is_enabled_vbat(void)
531 {
532 #if defined(GR5X25)
533 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
534 #endif
535 }
536
537 /**
538 * @brief Set ADC input mode.
539 *
540 * Register|BitsName
541 * --------|--------
542 * SNSADC_CFG | REG2
543 *
544 * @param mode This parameter can be one of the following values:
545 * @arg @ref LL_ADC_INPUT_SINGLE
546 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
547 * @retval None
548 */
549 __STATIC_INLINE void ll_adc_set_input_mode(uint32_t mode)
550 {
551 #if defined(GR5X25)
552 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
553 #endif
554 }
555
556 /**
557 * @brief Return ADC input mode.
558 *
559 * Register|BitsName
560 * --------|--------
561 * SNSADC_CFG | REG2
562 *
563 * @retval Returned value can be one of the following values:
564 * @arg @ref LL_ADC_INPUT_SINGLE
565 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
566 */
567 __STATIC_INLINE uint32_t ll_adc_get_input_mode(void)
568 {
569 #if defined(GR5X25)
570 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk) >> AON_PMU_SNSADC_CFG_SINGLE_EN_Pos);
571 #endif
572 }
573
574 /**
575 * @brief Enable offset calibration.
576 * @note Enable offset calibration, used to swap inputs of comparator for offset
577 * calibration.
578 *
579 * Register|BitsName
580 * --------|--------
581 * SNSADC_CFG | REG2
582 *
583 * @retval None
584 */
585 __STATIC_INLINE void ll_adc_enable_ofs_cal(void)
586 {
587 #if defined(GR5X25)
588 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
589 #endif
590 }
591
592 /**
593 * @brief Disable offset calibration.
594 *
595 * Register|BitsName
596 * --------|--------
597 * SNSADC_CFG | REG2
598 *
599 * @retval None
600 */
601 __STATIC_INLINE void ll_adc_disable_ofs_cal(void)
602 {
603 #if defined(GR5X25)
604 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
605 #endif
606 }
607
608 /**
609 * @brief Check if offset calibration is enabled.
610 *
611 * Register|BitsName
612 * --------|--------
613 * SNSADC_CFG | REG2
614 *
615 * @retval State of bit (1 or 0).
616 */
617 __STATIC_INLINE uint32_t ll_adc_is_enabled_ofs_cal(void)
618 {
619 #if defined(GR5X25)
620 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
621 #endif
622 }
623
624 /**
625 * @brief Set dynamic rang of ADC.
626 * @note When higher input signal frequencies close to Nyquist rate, you should set 1.
627 *
628 * Register|BitsName
629 * --------|--------
630 * SNSADC_CFG | REG2
631 *
632 * @param rang This parameter can be a value between: 1 ~ 7
633 * @retval None
634 */
635 __STATIC_INLINE void ll_adc_set_dynamic_rang(uint32_t rang)
636 {
637 #if defined(GR5X25)
638 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
639 #endif
640 }
641
642 /**
643 * @brief Return ADC dynamic rang.
644 *
645 * Register|BitsName
646 * --------|--------
647 * SNSADC_CFG | REG2
648 *
649 * @retval Returned value can be a value between: 1 ~ 7
650 */
651 __STATIC_INLINE uint32_t ll_adc_get_dynamic_rang(void)
652 {
653 #if defined(GR5X25)
654 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
655 #endif
656 }
657
658 /**
659 * @brief Set source of ADC input channelP.
660 *
661 * Register|BitsName
662 * --------|--------
663 * SNSADC_CFG | REG3
664 *
665 * @param source This parameter can be one of the following values:
666 * @arg @ref LL_ADC_INPUT_SRC_IO0
667 * @arg @ref LL_ADC_INPUT_SRC_IO1
668 * @arg @ref LL_ADC_INPUT_SRC_IO2
669 * @arg @ref LL_ADC_INPUT_SRC_IO3
670 * @arg @ref LL_ADC_INPUT_SRC_IO4
671 * @arg @ref LL_ADC_INPUT_SRC_TMP
672 * @arg @ref LL_ADC_INPUT_SRC_BAT
673 * @retval None
674 */
675 __STATIC_INLINE void ll_adc_set_channelp(uint32_t source)
676 {
677 #if defined(GR5X25)
678 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
679 #endif
680 }
681
682 /**
683 * @brief Return source of ADC input channelP.
684 *
685 * Register|BitsName
686 * --------|--------
687 * SNSADC_CFG | REG3
688 *
689 * @retval Returned value can be one of the following values:
690 * @arg @ref LL_ADC_INPUT_SRC_IO0
691 * @arg @ref LL_ADC_INPUT_SRC_IO1
692 * @arg @ref LL_ADC_INPUT_SRC_IO2
693 * @arg @ref LL_ADC_INPUT_SRC_IO3
694 * @arg @ref LL_ADC_INPUT_SRC_IO4
695 * @arg @ref LL_ADC_INPUT_SRC_TMP
696 * @arg @ref LL_ADC_INPUT_SRC_BAT
697 */
698 __STATIC_INLINE uint32_t ll_adc_get_channelp(void)
699 {
700 #if defined(GR5X25)
701 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
702 #endif
703 }
704
705 /**
706 * @brief Set source of ADC input channelN.
707 *
708 * Register|BitsName
709 * --------|--------
710 * SNSADC_CFG | REG3
711 *
712 * @param source This parameter can be one of the following values:
713 * @arg @ref LL_ADC_INPUT_SRC_IO0
714 * @arg @ref LL_ADC_INPUT_SRC_IO1
715 * @arg @ref LL_ADC_INPUT_SRC_IO2
716 * @arg @ref LL_ADC_INPUT_SRC_IO3
717 * @arg @ref LL_ADC_INPUT_SRC_IO4
718 * @arg @ref LL_ADC_INPUT_SRC_TMP
719 * @arg @ref LL_ADC_INPUT_SRC_BAT
720 * @retval None
721 */
722 __STATIC_INLINE void ll_adc_set_channeln(uint32_t source)
723 {
724 #if defined(GR5X25)
725 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
726 #endif
727 }
728
729 /**
730 * @brief Return source of ADC input channelN.
731 *
732 * Register|BitsName
733 * --------|--------
734 * SNSADC_CFG | REG3
735 *
736 * @retval Returned value can be one of the following values:
737 * @arg @ref LL_ADC_INPUT_SRC_IO0
738 * @arg @ref LL_ADC_INPUT_SRC_IO1
739 * @arg @ref LL_ADC_INPUT_SRC_IO2
740 * @arg @ref LL_ADC_INPUT_SRC_IO3
741 * @arg @ref LL_ADC_INPUT_SRC_IO4
742 * @arg @ref LL_ADC_INPUT_SRC_TMP
743 * @arg @ref LL_ADC_INPUT_SRC_BAT
744 */
745 __STATIC_INLINE uint32_t ll_adc_get_channeln(void)
746 {
747 #if defined(GR5X25)
748 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
749 #endif
750 }
751
752 /**
753 * @brief Enable ADC MAS_RST.
754 *
755 * Register|BitsName
756 * --------|--------
757 * SNSADC_CFG | REG4
758 *
759 * @retval None
760 */
761 __STATIC_INLINE void ll_adc_enable_mas_rst(void)
762 {
763 #if defined(GR5X25)
764 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
765 #endif
766 }
767
768 /**
769 * @brief Disable ADC MAS_RST.
770 *
771 * Register|BitsName
772 * --------|--------
773 * SNSADC_CFG | REG4
774 *
775 * @retval None
776 */
777 __STATIC_INLINE void ll_adc_disable_mas_rst(void)
778 {
779 #if defined(GR5X25)
780 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
781 #endif
782 }
783
784 /**
785 * @brief Check if ADC MAS_RST is enabled.
786 *
787 * Register|BitsName
788 * --------|--------
789 * SNSADC_CFG | REG4
790 *
791 * @retval State of bit (1 or 0).
792 */
793 __STATIC_INLINE uint32_t ll_adc_is_enabled_mas_rst(void)
794 {
795 #if defined(GR5X25)
796 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
797 #endif
798 }
799
800 /**
801 * @brief Set source of ADC reference.
802 *
803 * Register|BitsName
804 * --------|--------
805 * SNSADC_CFG | REG4
806 *
807 * @param source This parameter can be one of the following values:
808 * @arg @ref LL_ADC_REF_SRC_BUF_INT
809 * @arg @ref LL_ADC_REF_SRC_IO0
810 * @arg @ref LL_ADC_REF_SRC_IO1
811 * @arg @ref LL_ADC_REF_SRC_IO2
812 * @arg @ref LL_ADC_REF_SRC_IO3
813 * @retval None
814 */
815 __STATIC_INLINE void ll_adc_set_ref(uint32_t source)
816 {
817 #if defined(GR5X25)
818 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
819 #endif
820 }
821
822 /**
823 * @brief Return source of ADC reference.
824 *
825 * Register|BitsName
826 * --------|--------
827 * SNSADC_CFG | REG4
828 *
829 * @retval Returned value can be one of the following values:
830 * @arg @ref LL_ADC_REF_SRC_BUF_INT
831 * @arg @ref LL_ADC_REF_SRC_IO0
832 * @arg @ref LL_ADC_REF_SRC_IO1
833 * @arg @ref LL_ADC_REF_SRC_IO2
834 * @arg @ref LL_ADC_REF_SRC_IO3
835 */
836 __STATIC_INLINE uint32_t ll_adc_get_ref(void)
837 {
838 #if defined(GR5X25)
839 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
840 #endif
841 }
842
843 /**
844 * @brief Set current of ADC reference circuit.
845 * @note When samples at 100kbps, you should set 0.
846 * When samples at 1mbps, you should set 7.
847 *
848 * Register|BitsName
849 * --------|--------
850 * SNSADC_CFG | REG4
851 *
852 * @param source This parameter can be a value between: 0 ~ 7
853 * @retval None
854 */
855 __STATIC_INLINE void ll_adc_set_ref_current(uint32_t source)
856 {
857 #if defined(GR5X25)
858 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
859 #endif
860 }
861
862 /**
863 * @brief Return current of ADC reference circuit.
864 *
865 * Register|BitsName
866 * --------|--------
867 * SNSADC_CFG | REG4
868 *
869 * @retval Returned value can be a value between: 0 ~ 7
870 */
871 __STATIC_INLINE uint32_t ll_adc_get_ref_current(void)
872 {
873 #if defined(GR5X25)
874 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
875 #endif
876 }
877
878 /** @} */
879
880 /** @defgroup ADC_LL_EF_FIFO_Access FIFO Access
881 * @{
882 */
883
884 /**
885 * @brief Return samples value of ADC by reading FIFO.
886 * @note There are two value in the register, both of them is 16bits.
887 *
888 * Register|BitsName
889 * --------|--------
890 * SENSE_ADC_FIFO | SENSE_ADC_FIFO
891 *
892 * @retval Smaples value of input
893 */
894 __STATIC_INLINE uint32_t ll_adc_read_fifo(void)
895 {
896 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
897 }
898
899 /**
900 * @brief Set threshold of ADC FIFO.
901 *
902 * Register|BitsName
903 * --------|--------
904 * SENSE_FF_THRESH | SENSE_FF_THRESH
905 *
906 * @param thresh This parameter can be a value between: 0 ~ 64
907 * @retval None
908 */
909 __STATIC_INLINE void ll_adc_set_thresh(uint32_t thresh)
910 {
911 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
912 }
913
914 /**
915 * @brief Return threshold of ADC FIFO.
916 *
917 * Register|BitsName
918 * --------|--------
919 * SENSE_FF_THRESH | SENSE_FF_THRESH
920 *
921 * @retval Returned value can be a value between: 0 ~ 64
922 */
923 __STATIC_INLINE uint32_t ll_adc_get_thresh(void)
924 {
925 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
926 }
927
928 /**
929 * @brief Enable ADC dma_req.
930 *
931 * Register|BitsName
932 * --------|--------
933 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
934 *
935 * @retval None
936 */
937 __STATIC_INLINE void ll_adc_enable_dma_req(void)
938 {
939 #if defined(GR5X25)
940 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
941 #endif
942 }
943
944 /**
945 * @brief Disable ADC dma_req.
946 *
947 * Register|BitsName
948 * --------|--------
949 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
950 *
951 * @retval None
952 */
953 __STATIC_INLINE void ll_adc_disable_dma_req(void)
954 {
955 #if defined(GR5X25)
956 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
957 #endif
958 }
959
960
961 /**
962 * @brief Check if dma_req is enabled.
963 *
964 * Register|BitsName
965 * --------|--------
966 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
967 *
968 * @retval State of bit (1 or 0).
969 */
970 __STATIC_INLINE uint32_t ll_adc_is_enabled_dma_req(void)
971 {
972 #if defined(GR5X25)
973 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
974 #endif
975 }
976
977 /**
978 * @brief Check if ADC FIFO is not empty.
979 *
980 * Register|BitsName
981 * --------|--------
982 * SENSE_ADC_STAT | VAL
983 *
984 * @retval State of bit (1 or 0).
985 */
986 __STATIC_INLINE uint32_t ll_adc_is_fifo_notempty(void)
987 {
988 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
989 }
990
991 /**
992 * @brief Return count of ADC FIFO.
993 *
994 * Register|BitsName
995 * --------|--------
996 * SENSE_ADC_STAT | FF_COUNT
997 *
998 * @retval Returned value can be a value between: 0 ~ 64
999 */
1000 __STATIC_INLINE uint32_t ll_adc_get_fifo_count(void)
1001 {
1002 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
1003 }
1004
1005 /**
1006 * @brief Flush ADC FIFO.
1007 *
1008 * Register|BitsName
1009 * --------|--------
1010 * SENSE_ADC_STAT | FF_FLUSH
1011 *
1012 * @retval void
1013 */
1014 __STATIC_INLINE void ll_adc_flush_fifo(void)
1015 {
1016 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
1017 }
1018
1019 /**
1020 * @brief Try to lock sw token.
1021 *
1022 * Register|BitsName
1023 * --------|--------
1024 * SENSE_ADC_GET_TKN_SW
1025 *
1026 * @retval Returned true if sw lock adc token success; return false if sw lock adc token fail
1027 */
1028 __STATIC_INLINE uint32_t ll_adc_try_lock_sw_token(void)
1029 {
1030 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
1031 }
1032
1033 /**
1034 * @brief Release sw token.
1035 *
1036 * Register|BitsName
1037 * --------|--------
1038 * SENSE_ADC_RET_TKN_SW | SW_RELEASE_Msk
1039 *
1040 * @retval none
1041 */
1042 __STATIC_INLINE void ll_adc_release_sw_token(void)
1043 {
1044 CLEAR_BITS(MCU_SUB->SENSE_ADC_RET_TKN_SW, MCU_SUB_SNSADC_RET_TKN_SW_RELEASE_Msk);
1045 }
1046
1047 /**
1048 * @brief get adc token state.
1049 *
1050 * Register|BitsName
1051 * --------|--------
1052 * SENSE_ADC_TKN_STS
1053 *
1054 * @retval Returned value from SENSE_ADC_TKN_STS reg
1055 */
1056 __STATIC_INLINE uint32_t ll_adc_get_token_state(void)
1057 {
1058 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);
1059 }
1060
1061 /** @} */
1062
1063 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
1064 * @{
1065 */
1066
1067 /**
1068 * @brief De-initialize ADC registers (Registers restored to their default values).
1069 * @retval An error_status_t enumeration value:
1070 * - SUCCESS: ADC registers are de-initialized
1071 * - ERROR: ADC registers are not de-initialized
1072 */
1073 error_status_t ll_adc_deinit(void);
1074
1075 /**
1076 * @brief Initialize ADC registers according to the specified.
1077 * parameters in p_adc_init.
1078 * @param p_adc_init Pointer to a ll_adc_init_t structure that contains the configuration
1079 * information for the specified ADC peripheral.
1080 * @retval An error_status_t enumeration value:
1081 * - SUCCESS: ADC registers are initialized according to p_adc_init content
1082 * - ERROR: Problem occurred during ADC Registers initialization
1083 */
1084 error_status_t ll_adc_init(ll_adc_init_t *p_adc_init);
1085
1086 /**
1087 * @brief Set each field of a @ref ll_adc_init_t type structure to default value.
1088 * @param p_adc_init Pointer to a @ref ll_adc_init_t structure
1089 * whose fields will be set to default values.
1090 * @retval None
1091 */
1092 void ll_adc_struct_init(ll_adc_init_t *p_adc_init);
1093
1094 /** @} */
1095
1096 /** @} */
1097
1098 #endif /* AON */
1099
1100 #ifdef __cplusplus
1101 }
1102 #endif
1103
1104 #endif /* __GR55XX_LL_ADC_H__ */
1105
1106 /** @} */
1107
1108 /** @} */
1109
1110 /** @} */