app_graphics_dc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file app_graphics_dc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DC app library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2021 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38
39 /** @addtogroup PERIPHERAL Peripheral Driver
40 * @{
41 */
42
43 /** @addtogroup APP_DRIVER APP DRIVER
44 * @{
45 */
46
47 /** @defgroup APP_GRAPHICS_DC DC
48 * @brief GRAPHICS_DC APP module driver.
49 * @{
50 */
51
52 #ifndef __APP_GRAPHICS_GRAPHICS_DC_H__
53 #define __APP_GRAPHICS_GRAPHICS_DC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 #include "gr55xx.h"
60 #include "app_io.h"
61 #include "hal_gdc.h"
62 #include "hal_gdc_regs.h"
63 #include "hal_gdc_mipi.h"
64
65 /** @addtogroup APP_GRAPHICS_DC_ENUM Enumerations
66 * @{
67 */
68
69 /**
70 * @brief Define SPI work Mode for DC
71 */
72 typedef enum {
73 GDC_MODE_SPI = 0, /**< By 1-wire SPI */
74 GDC_MODE_DSPI, /**< 1bit cmd + 8bit data, and DCX signal */
75 GDC_MODE_QSPI, /**< By Quad SPI */
76 } graphics_dc_mspi_e;
77
78
79 /**
80 * @brief Define Clock Frequency for DC
81 */
82 typedef enum {
83 GDC_CLOCK_FREQ_48MHz = 0x00, /**< DC clock, 48MHz */
84 GDC_CLOCK_FREQ_24MHz = 0x03, /**< DC clock, 24MHz */
85 GDC_CLOCK_FREQ_12MHz = 0x05, /**< DC clock, 12MHz */
86 GDC_CLOCK_FREQ_6MHz = 0x09, /**< DC clock, 6MHz */
87 GDC_CLOCK_FREQ_3MHz = 0x11, /**< DC clock, 3MHz */
88 } graphics_dc_clock_freq_e;
89
90
91 /**
92 * @brief Define Clock Mode for DC
93 */
94 typedef enum {
95 GDC_CLOCK_MODE_0 = 0x00, /**< DC clock mode 0 */
96 GDC_CLOCK_MODE_1 = 0x01, /**< DC clock mode 1 */
97 GDC_CLOCK_MODE_2 = 0x02, /**< DC clock mode 2 */
98 GDC_CLOCK_MODE_3 = 0x03, /**< DC clock mode 3 */
99 } graphics_dc_clock_mode_e;
100
101
102 /**
103 * @brief Define Delay Clock for DC Tcsu
104 */
105 typedef enum {
106 GDC_TCSU_CYCLE_0 = 0x00, /**< delay 0 clock cycle */
107 GDC_TCSU_CYCLE_1 = 0x01, /**< delay 1 clock cycle */
108 GDC_TCSU_CYCLE_2 = 0x02, /**< delay 2 clock cycle */
109 GDC_TCSU_CYCLE_3 = 0x03, /**< delay 3 clock cycle */
110 GDC_TCSU_CYCLE_4 = 0x04, /**< delay 4 clock cycle */
111 } graphics_dc_tcsu_cycle_e;
112
113 /**
114 * @brief Display Controller Power Mode Enumerations definition
115 */
116 typedef enum {
117 GDC_POWER_STATE_SLEEP = 0, /* sleep state */
118 GDC_POWER_STATE_ACTIVE = 1, /* active state */
119 } graphics_dc_power_state_e;
120
121 /** @} */
122
123
124 /** @addtogroup APP_GRAPHICS_DC_STRUCTURES Structures
125 * @{
126 */
127
128 /** @defgroup GRAPHICS_DC_Configuration GRAPHICS DC Configuration
129 * @{
130 */
131 /**
132 * @brief QSPI IO configuration Structures
133 */
134 typedef struct
135 {
136 app_io_pull_t pull; /**< Specifies the Pull-up or Pull-Down activation for the selected pins. */
137 uint8_t enable; /**< Enable or disable the pin. */
138 } app_graphics_dc_pin_t;
139
140
141 /**
142 * @brief define DC pins
143 */
144 typedef struct
145 {
146 app_graphics_dc_pin_t csn; /**< Set the configuration of QSPI CS pin. */
147 app_graphics_dc_pin_t clk; /**< Set the configuration of QSPI CLK pin. */
148 app_graphics_dc_pin_t io0; /**< Set the configuration of QSPI IO0 pin. */
149 app_graphics_dc_pin_t io1; /**< Set the configuration of QSPI IO1 pin. */
150 app_graphics_dc_pin_t io2; /**< Set the configuration of QSPI IO2 pin. */
151 app_graphics_dc_pin_t io3; /**< Set the configuration of QSPI IO3 pin. */
152 app_graphics_dc_pin_t dcx; /**< Set the configuration of QSPI IO3 pin. */
153 } app_graphics_dc_pins_t;
154 /** @} */
155
156 /** @} */
157
158
159 /** @addtogroup APP_GRAPHICS_DC_ENUM Enumerations
160 * @{
161 */
162 /**
163 * @brief Define work layers for DC
164 */
165 typedef enum {
166 GDC_ONE_LAYER_MODE = 0x00, /**< 1 layer mode */
167 GDC_TWO_LAYER_MODE = 0x01, /**< 2 layer mode */
168 } graphics_dc_layer_mode_e;
169
170
171 /**
172 * @brief Define the data format for frame buffer of DC
173 */
174 typedef enum {
175 GDC_DATA_FORMAT_RGB565 = HAL_GDC_RGB565, /**< FrameBuffer is RGA565, 16bit, no Alpha */
176 GDC_DATA_FORMAT_RGB24 = HAL_GDC_RGB24, /**< FrameBuffer is RGA24, 24bit, no Alpha */
177 GDC_DATA_FORMAT_RGBA8888 = HAL_GDC_RGBA8888, /**< FrameBuffer is RGBA8888, 32bit with Alpha */
178 GDC_DATA_FORMAT_ABGR8888 = HAL_GDC_ABGR8888, /**< FrameBuffer is ABGR8888, 32bit with Alpha */
179 GDC_DATA_FORMAT_ARGB8888 = HAL_GDC_ARGB8888, /**< FrameBuffer is ARGB8888, 32bit with Alpha */
180 GDC_DATA_FORMAT_BGRA8888 = HAL_GDC_BGRA8888, /**< FrameBuffer is BGRA8888, 32bit with Alpha */
181 GDC_DATA_FORMAT_TSC4 = HAL_GDC_TSC4, /**< FrameBuffer is RGB565 compressed by TSC4 */
182 GDC_DATA_FORMAT_TSC6 = HAL_GDC_TSC6, /**< FrameBuffer is *888 compressed by TSC6 */
183 GDC_DATA_FORMAT_TSC6A = HAL_GDC_TSC6A, /**< FrameBuffer is *8888 compressed by TSC6A */
184 } graphics_dc_data_format_e;
185
186
187 /**
188 * @brief Define the Output MIPI Timing for DATA Phase of DC
189 * Timing of MIPICFG_2RGB888_OPT1 is True MIPICFG_2RGB888_OPT0, and
190 * Timing of MIPICFG_2RGB888_OPT0 is True MIPICFG_2RGB888_OPT1, They need to exchange !!!
191 */
192 typedef enum {
193 GDC_MIPICFG_SPI_RGB565_OPT0 = MIPICFG_1RGB565_OPT0, /**< Sent in SPI Mode, Output format is RGB565 with option.0 */
194 GDC_MIPICFG_SPI_RGB888_OPT0 = MIPICFG_1RGB888_OPT0, /**< Sent in SPI Mode, Output format is RGB565 with option.0 */
195 GDC_MIPICFG_DSPI_RGB565_OPT0 = MIPICFG_2RGB565_OPT0, /**< Sent in DSPI Mode, Output format is RGB565 with option.0 */
196 GDC_MIPICFG_DSPI_RGB888_OPT0 = MIPICFG_2RGB888_OPT1, /**< Sent in DSPI Mode, Output format is RGB888 with option.0 */
197 GDC_MIPICFG_DSPI_RGB888_OPT1 = MIPICFG_2RGB888_OPT0, /**< Sent in DSPI Mode, Output format is RGB888 with option.1 */
198 GDC_MIPICFG_QSPI_RGB565_OPT0 = MIPICFG_4RGB565_OPT0, /**< Sent in QSPI Mode, Output format is RGB565 with option.0 */
199 GDC_MIPICFG_QSPI_RGB888_OPT0 = MIPICFG_4RGB888_OPT0, /**< Sent in QSPI Mode, Output format is RGB888 with option.0 */
200 } graphics_dc_mipi_format_e;
201
202
203 /**
204 * @brief Define the Output pixel bits for DC
205 */
206 typedef enum {
207 GDC_OUT_PIXEL_BITS_16 = 16, /**< Output pixel 16 bits */
208 GDC_OUT_PIXEL_BITS_24 = 24, /**< Output pixel 24 bits */
209 GDC_OUT_PIXEL_BITS_NOT_SUPPORT = 0xFF, /**< Not support */
210 } graphics_dc_out_pixel_bits_e;
211
212 /**
213 * @brief Define the Output Frame Timing for DC
214 */
215 typedef enum {
216 GDC_SPI_FRAME_TIMING_0 = 0x00, /**< 8Bit CMD::24Bit ADDR::Ndata, All Sent in SPI */
217 GDC_DSPI_FRAME_TIMING_0, /**< 8Bit CMD Sent in SPI::NO ADDR::Ndata Sent in DSPI, with DCX */
218 GDC_QSPI_FRAME_TIMING_0, /**< 8Bit CMD::24Bit ADDR Sent in SPI, All Data Sent in QSPI */
219 GDC_QSPI_FRAME_TIMING_1, /**< 8Bit CMD Sent in SPI, 24Bit ADDR and All data Sent in QSPI */
220 } app_graphics_dc_frame_timing_e;
221
222
223 /**
224 * @brief Define the bits of address phase for DC Frame
225 */
226 typedef enum {
227 GDC_FRAME_ADDRESS_WIDTH_NONE = 0xFF, /**< Not support */
228 GDC_FRAME_ADDRESS_WIDTH_08BIT = MIPI_CMD08, /**< Frame address width 8bits */
229 GDC_FRAME_ADDRESS_WIDTH_16BIT = MIPI_CMD16, /**< Frame address width 16bits */
230 GDC_FRAME_ADDRESS_WIDTH_24BIT = MIPI_CMD24, /**< Frame address width 24bits */
231 } app_graphics_dc_frame_address_width_e;
232
233 /**
234 * @brief Define access type for DC
235 */
236 typedef enum {
237 GDC_ACCESS_TYPE_SYNC = 0, /**< SYNC access type */
238 GDC_ACCESS_TYPE_ASYNC, /**< ASYNC access type */
239 } app_graphics_dc_access_type_e;
240
241
242 /**
243 * @brief Define frame output result for DC
244 */
245 typedef enum {
246 GDC_FRAME_RES_SUCCESS = 0x00, /**< frame sent success */
247 GDC_FRAME_RES_ASYNC_WAIT, /**< frame sent, but need to get the result in async callback */
248 GDC_FRAME_RES_FAIL, /**< frame sent fail */
249 GDC_FRAME_RES_UNSUPPORT, /**< frame format/command not support,please check config params */
250 } app_graphics_dc_frame_result_e;
251
252 /** @} */
253
254 /** @addtogroup APP_GRAPHICS_DC_STRUCTURES Structures
255 * @{
256 */
257
258 /**
259 * @brief Define init params for DC
260 */
261 typedef struct {
262 graphics_dc_mspi_e mspi_mode; /**< Specify spi mode, Ref Optional values of graphics_dc_mspi_e */
263 graphics_dc_clock_freq_e clock_freq; /**< Specify dc clock freq, Ref Optional values of graphics_dc_clock_freq_e */
264 graphics_dc_clock_mode_e clock_mode; /**< Specify dc clock mode, Ref Optional values of graphics_dc_clock_mode_e */
265 graphics_dc_tcsu_cycle_e tcsu_cycle; /**< Specify cs setup delay, Ref Optional values of graphics_dc_tcsu_cycle_e */
266 graphics_dc_layer_mode_e layer_mode; /**< Specify which layer to flush, Ref Optional values of graphics_dc_layer_mode_e */
267 graphics_dc_mipi_format_e mipicfg_format; /**< Specify mipi timing format, Ref Optional values of graphics_dc_mipi_format_e */
268 uint16_t resolution_x; /**< Specify the x resolution in pixels */
269 uint16_t resolution_y; /**< Specify the y resolution in pixels */
270 app_graphics_dc_pins_t pins_cfg; /**< Specify pins state */
271 } app_graphics_dc_params_t;
272
273 /**
274 * @brief Define DC Frame Layer configuration
275 */
276 typedef struct {
277 void * frame_baseaddr ; /**< Frame Address */
278 uint32_t resolution_x; /**< Resolution X */
279 uint32_t resolution_y; /**< Resolution Y */
280 int32_t row_stride; /**< Stride */
281 int32_t start_x; /**< Start Rendering X Coordinator */
282 int32_t start_y; /**< Start Rendering Y Coordinator */
283 uint32_t size_x; /**< Rendering Size X */
284 uint32_t size_y; /**< Rendering Size Y */
285 uint8_t alpha; /**< Alpha */
286 uint8_t blendmode; /**< Blending Mode */
287 graphics_dc_data_format_e data_format; /**< Format */
288 } app_graphics_dc_framelayer_t;
289
290
291 /**
292 * @brief Define Control Command for DC Frame
293 */
294 typedef struct {
295 uint8_t command; /**< Command phase for display timing */
296 uint32_t address; /**< Address phase for display timing,if no address phase, ignore this */
297 app_graphics_dc_frame_address_width_e address_width; /**< Optional values: @ref GDC_FRAME_ADDRESS_WIDTH_NONE
298 @ref GDC_FRAME_ADDRESS_WIDTH_08BIT
299 @ref GDC_FRAME_ADDRESS_WIDTH_16BIT
300 @ref GDC_FRAME_ADDRESS_WIDTH_24BIT */
301 app_graphics_dc_frame_timing_e frame_timing; /**< Specify the supported frame timing */
302 } app_graphics_dc_cmd_t;
303
304 /** @} */
305
306
307 /**
308 * @defgroup APP_GRAPHICS_DC_MACRO Defines
309 * @{
310 */
311
312 /* Exported constants --------------------------------------------------------*/
313 /** @defgroup GRAPHICS_DC_Exported_Constants DC Exported Constants
314 * @{
315 */
316
317 /** @defgroup GRAPHICS_DC_PIN DC Pins Define
318 * @{
319 */
320 #define GRAPHICS_DC_CSN_PORT APP_IO_TYPE_GPIOB /**< Define DC CSN PORT */
321 #define GRAPHICS_DC_CSN_PIN APP_IO_PIN_11 /**< Define DC CSN PIN */
322 #define GRAPHICS_DC_CSN_PIN_MUX APP_IO_MUX_1 /**< Define DC CSN PIN.MUX */
323
324 #define GRAPHICS_DC_CLK_PORT APP_IO_TYPE_GPIOB /**< Define DC CLK PORT */
325 #define GRAPHICS_DC_CLK_PIN APP_IO_PIN_0 /**< Define DC CLK PIN */
326 #define GRAPHICS_DC_CLK_PIN_MUX APP_IO_MUX_1 /**< Define DC CLK PIN.MUX */
327
328 #define GRAPHICS_DC_IO0_PORT APP_IO_TYPE_GPIOB /**< Define DC IO0 PORT */
329 #define GRAPHICS_DC_IO0_PIN APP_IO_PIN_1 /**< Define DC IO0 PIN */
330 #define GRAPHICS_DC_IO0_PIN_MUX APP_IO_MUX_1 /**< Define DC IO0 PIN.MUX */
331
332 #define GRAPHICS_DC_IO1_PORT APP_IO_TYPE_GPIOB /**< Define DC IO1 PORT */
333 #define GRAPHICS_DC_IO1_PIN APP_IO_PIN_2 /**< Define DC IO1 PIN */
334 #define GRAPHICS_DC_IO1_PIN_MUX APP_IO_MUX_1 /**< Define DC IO1 PIN.MUX */
335
336 #define GRAPHICS_DC_IO2_PORT APP_IO_TYPE_GPIOB /**< Define DC IO2 PORT */
337 #define GRAPHICS_DC_IO2_PIN APP_IO_PIN_3 /**< Define DC IO2 PIN */
338 #define GRAPHICS_DC_IO2_PIN_MUX APP_IO_MUX_1 /**< Define DC IO2 PIN.MUX */
339
340 #define GRAPHICS_DC_IO3_PORT APP_IO_TYPE_GPIOB /**< Define DC IO3 PORT */
341 #define GRAPHICS_DC_IO3_PIN APP_IO_PIN_4 /**< Define DC IO3 PIN */
342 #define GRAPHICS_DC_IO3_PIN_MUX APP_IO_MUX_1 /**< Define DC IO3 PIN.MUX */
343
344 #define GRAPHICS_DC_DCX_PORT APP_IO_TYPE_GPIOB /**< Define DC DCX PORT */
345 #define GRAPHICS_DC_DCX_PIN APP_IO_PIN_13 /**< Define DC DCX PIN */
346 #define GRAPHICS_DC_DCX_PIN_MUX APP_IO_MUX_5 /**< Define DC DCX PIN.MUX */
347 /** @} */
348
349 /** @defgroup GRAPHICS_DC_LAYER DC Layers Define
350 * @{
351 */
352 #define GRAPHICS_DC_LAYER_0 0u /**< Define DC Layer 0 */
353 #define GRAPHICS_DC_LAYER_1 1u /**< Define DC Layer 1 */
354 /** @} */
355
356 /** @defgroup GRAPHICS_DC_EVT IRQ callback events Define
357 * @{
358 */
359 #define GDC_IRQ_EVT_FRAME_TRANSMITION_END 0x01 /**< Define Frame Xfer End event */
360 #define GDC_IRQ_EVT_CMD_TRANSMITION_END 0x02 /**< Define CMD Xfer End event */
361 /** @} */
362
363 /** @defgroup GRAPHICS_DC_BASEADDR DC registers memory base address Define
364 * @{
365 */
366 #define GRAPHICS_DC_BASEADDR 0xA3FF4000 /**< Define DC registers memory base address */
367 /** @} */
368
369 /** @} */
370
371 /** @} */
372
373
374 /** @addtogroup APP_GRAPHICS_DC_TYPEDEFS Type definitions
375 * @{
376 */
377 /**
378 * @brief DC IRQ callback definition
379 */
380 typedef void (* graphics_dc_irq_event_notify_cb )(uint32_t evt);
381
382 /**
383 * @brief DC Refresh callback definition
384 */
385 typedef void (* graphics_dc_set_refresh_area_cb )(uint32_t mark, uint32_t x_start, uint32_t x_end, uint32_t y_start, uint32_t y_end);
386
387 /** @} */
388
389
390 /** @addtogroup APP_GRAPHICS_DC_DRIVER_FUNCTIONS Functions
391 * @{
392 */
393
394 /**
395 ****************************************************************************************
396 * @brief init Graphics DC dev
397 *
398 * @param[in] dc_params: pointer to dc init params
399 * @param[in] evt_cb: event callback
400 * Note: GDC_IRQ_EVT_FRAME_TRANSMITION_END & GDC_IRQ_EVT_CMD_TRANSMITION_END
401 * @retval ::APP_DRV_SUCCESS
402 * @retval ::APP_DRV_ERR_HAL
403 * @retval ::APP_DRV_ERR_POINTER_NULL
404 ****************************************************************************************
405 */
406 uint16_t graphics_dc_init(app_graphics_dc_params_t * dc_params, graphics_dc_irq_event_notify_cb evt_cb);
407
408 /**
409 ****************************************************************************************
410 * @brief de-init Graphics DC dev, just called when needed to reboot/reset
411 *
412 ****************************************************************************************
413 */
414 void graphics_dc_deinit(void);
415
416 /**
417 ****************************************************************************************
418 * @brief re-init i/o for Graphics DC dev with pre-init i/o setting
419 *
420 ****************************************************************************************
421 */
422 void graphics_dc_pins_reinit(void);
423
424 /**
425 *****************************************************************************************
426 * @brief Switch power state for DC module
427 *
428 * @param[in] state: power state to switch
429 *
430 * @return none
431 *****************************************************************************************
432 */
433 void app_graphics_dc_set_power_state(graphics_dc_power_state_e state);
434
435 /**
436 *****************************************************************************************
437 * @brief DC clock frequency set
438 *
439 * @param[in] clock_freq: DC clock frequency
440 *
441 * @return none
442 *****************************************************************************************
443 */
444 void app_graphics_dc_freq_set(graphics_dc_clock_freq_e clock_freq);
445
446 /**
447 ****************************************************************************************
448 * @brief Send 1 Byte CMD,3 Byte ADDR And N Byte Data in 1-wire SPI Mode
449 * @note Timing Diagram :
450 * CSN: |_________________________________________________|
451 * CLK: __|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|___
452 * IO0: __[ -1Byte CMD- ][ -3Byte CMD- ][ -NByte Data- ]__
453 * @param[in] cmd_8bit: 8bits command
454 * @param[in] address_24bit: 24bits address
455 * @param[in] data: Pointer to data buffer
456 * @param[in] length: Data length
457 ****************************************************************************************
458 */
459 void app_graphics_dc_spi_send(uint8_t cmd_8bit, uint32_t address_24bit, uint8_t * data, uint32_t length);
460
461
462 /**
463 ****************************************************************************************
464 * @brief Send single cmd in 3-wire mode for DSPI (no DCX and 1 more MSB Bit for cmd indicator)
465 * @note Timing Diagram :
466 * CSN: |______________________________________|
467 * CLK: __|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|__
468 * SD0: __[0][ ---------8Bit CMD----------- ]__ (9-Bit in All)
469 * DCX: _______________________________________ (Always Low)
470 * @param[in] cmd: 8bits command
471 ****************************************************************************************
472 */
473 void app_graphics_dc_dspi_send_cmd_in_3wire_1lane(uint8_t cmd);
474
475
476 /**
477 ****************************************************************************************
478 * @brief Send single cmd &data in 3-wire mode for DSPI (no DCX and 1 more MSB Bit for cmd/data indicator)
479 * @note Timing Diagram :
480 * CSN: |_________________________________________________________________________|
481 * CLK: __|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|__
482 * SD0: __[0][ ---------8Bit CMD------------][1][ ---------8Bit DATA----------- ]__ (18-Bit in All)
483 * DCX: ___________________________________________________________________________ (Always Low)
484 * @param[in] cmd: 8bits command
485 * @param[in] data: 8bits data
486 ****************************************************************************************
487 */
488 void app_graphics_dc_dspi_send_cmd_data_in_3wire_1lane(uint8_t cmd, uint8_t data) ;
489
490
491 /**
492 ****************************************************************************************
493 * @brief Send cmd &data in 4-wire mode for DSPI (DCX as SD1, and 1 more MSB Bit for cmd/data indicator)
494 * @note Timing Diagram :
495 * CSN: |___________________________________________|
496 * CLK: __|-|_|-|_|...|-|_|-|_|-|_|-|_|....|-|_|-|___
497 * SD0: __[0][ ---H8Bit CMD--][1][ --H8Bit DATA-- ]__ (18Bit in All )
498 * DCX: __[0][ ---L8Bit CMD--][1][ --L8Bit DATA-- ]__ (use DCX as SD1)
499 * @param[in] cmd: 16bits command
500 * @param[in] data: 16bits data
501 ****************************************************************************************
502 */
503 void app_graphics_dc_dspi_send_cmd_data_in_4wire_2lane(uint16_t cmd, uint16_t data);
504
505
506 /**
507 ****************************************************************************************
508 * @brief Send cmd &data in 4-wire mode for DSPI (DCX as SD1, and 1 more MSB Bit for cmd/data indicator)
509 * @note Timing Diagram :
510 * CSN: |___________________________________________________________________________|
511 * CLK: __|-|_|-|_|...|-|_|-|_|-|_|-|_|....|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|...-|__
512 * SD0: __[0][ ---H8Bit CMD--][1][ --H8Bit DATA-- ][1][ --H8Bit DATA-- ][1][......]__ (Nx9Bit in All )
513 * DCX: __[0][ ---L8Bit CMD--][1][ --L8Bit DATA-- ][1][ --L8Bit DATA-- ][1][......]__ (use DCX as SD1)
514 * @param[in] cmd: 16bits command
515 * @param[in] data: Pointer to data buffer
516 * @param[in] length: Data length
517 ****************************************************************************************
518 */
519 void app_graphics_dc_dspi_send_cmd_datas_in_4wire_2lane(uint16_t cmd, uint16_t * data , int length);
520
521
522 /**
523 ****************************************************************************************
524 * @brief Send one whole frame by DC
525 *
526 * @param[in] which_layer:
527 * @arg @ref GRAPHICS_DC_LAYER_0
528 * @arg @ref GRAPHICS_DC_LAYER_1
529 * @param[in] frame_layer: pointer to dc layer setting
530 * @param[in] dc_cmd: pointer to DC control command
531 * @param[in] access_type:
532 * @arg @ref GDC_ACCESS_TYPE_SYNC, send frame sync
533 * @arg @ref GDC_ACCESS_TYPE_ASYNC, send frame async, must handle the frame result in callback
534 ****************************************************************************************
535 */
536 app_graphics_dc_frame_result_e app_graphics_dc_send_single_frame(uint32_t which_layer, app_graphics_dc_framelayer_t * frame_layer, app_graphics_dc_cmd_t * dc_cmd, app_graphics_dc_access_type_e access_type);
537
538 /** @} */
539
540 #ifdef __cplusplus
541 }
542 #endif
543
544 #endif /* __APP_GRAPHICS_GRAPHICS_DC_H__ */
545
546 /** @} */
547 /** @} */
548 /** @} */
app_graphics_dc_dspi_send_cmd_data_in_4wire_2lane
void app_graphics_dc_dspi_send_cmd_data_in_4wire_2lane(uint16_t cmd, uint16_t data)
Send cmd &data in 4-wire mode for DSPI (DCX as SD1, and 1 more MSB Bit for cmd/data indicator)
GDC_SPI_FRAME_TIMING_0
@ GDC_SPI_FRAME_TIMING_0
Definition: app_graphics_dc.h:216
GDC_FRAME_RES_UNSUPPORT
@ GDC_FRAME_RES_UNSUPPORT
Definition: app_graphics_dc.h:249
app_graphics_dc_framelayer_t::size_x
uint32_t size_x
Definition: app_graphics_dc.h:283
GDC_POWER_STATE_SLEEP
@ GDC_POWER_STATE_SLEEP
Definition: app_graphics_dc.h:117
GDC_CLOCK_FREQ_6MHz
@ GDC_CLOCK_FREQ_6MHz
Definition: app_graphics_dc.h:86
GDC_CLOCK_MODE_2
@ GDC_CLOCK_MODE_2
Definition: app_graphics_dc.h:97
app_graphics_dc_pin_t
QSPI IO configuration Structures.
Definition: app_graphics_dc.h:135
graphics_dc_pins_reinit
void graphics_dc_pins_reinit(void)
re-init i/o for Graphics DC dev with pre-init i/o setting
app_graphics_dc_params_t::tcsu_cycle
graphics_dc_tcsu_cycle_e tcsu_cycle
Definition: app_graphics_dc.h:265
app_graphics_dc_pins_t::io2
app_graphics_dc_pin_t io2
Definition: app_graphics_dc.h:150
GDC_ACCESS_TYPE_SYNC
@ GDC_ACCESS_TYPE_SYNC
Definition: app_graphics_dc.h:237
GDC_FRAME_RES_FAIL
@ GDC_FRAME_RES_FAIL
Definition: app_graphics_dc.h:248
GDC_TCSU_CYCLE_3
@ GDC_TCSU_CYCLE_3
Definition: app_graphics_dc.h:109
app_graphics_dc_dspi_send_cmd_in_3wire_1lane
void app_graphics_dc_dspi_send_cmd_in_3wire_1lane(uint8_t cmd)
Send single cmd in 3-wire mode for DSPI (no DCX and 1 more MSB Bit for cmd indicator)
GDC_MODE_SPI
@ GDC_MODE_SPI
Definition: app_graphics_dc.h:73
app_graphics_dc_pin_t::enable
uint8_t enable
Definition: app_graphics_dc.h:137
GDC_CLOCK_FREQ_48MHz
@ GDC_CLOCK_FREQ_48MHz
Definition: app_graphics_dc.h:83
graphics_dc_deinit
void graphics_dc_deinit(void)
de-init Graphics DC dev, just called when needed to reboot/reset
graphics_dc_clock_mode_e
graphics_dc_clock_mode_e
Define Clock Mode for DC.
Definition: app_graphics_dc.h:94
GDC_ACCESS_TYPE_ASYNC
@ GDC_ACCESS_TYPE_ASYNC
Definition: app_graphics_dc.h:238
GDC_TCSU_CYCLE_1
@ GDC_TCSU_CYCLE_1
Definition: app_graphics_dc.h:107
graphics_dc_clock_freq_e
graphics_dc_clock_freq_e
Define Clock Frequency for DC.
Definition: app_graphics_dc.h:82
app_graphics_dc_cmd_t::frame_timing
app_graphics_dc_frame_timing_e frame_timing
Definition: app_graphics_dc.h:301
app_graphics_dc_cmd_t::address
uint32_t address
Definition: app_graphics_dc.h:296
GDC_DATA_FORMAT_RGBA8888
@ GDC_DATA_FORMAT_RGBA8888
Definition: app_graphics_dc.h:177
graphics_dc_set_refresh_area_cb
void(* graphics_dc_set_refresh_area_cb)(uint32_t mark, uint32_t x_start, uint32_t x_end, uint32_t y_start, uint32_t y_end)
DC Refresh callback definition.
Definition: app_graphics_dc.h:385
GDC_CLOCK_MODE_3
@ GDC_CLOCK_MODE_3
Definition: app_graphics_dc.h:98
GDC_CLOCK_MODE_1
@ GDC_CLOCK_MODE_1
Definition: app_graphics_dc.h:96
graphics_dc_power_state_e
graphics_dc_power_state_e
Display Controller Power Mode Enumerations definition.
Definition: app_graphics_dc.h:116
GDC_MIPICFG_DSPI_RGB565_OPT0
@ GDC_MIPICFG_DSPI_RGB565_OPT0
Definition: app_graphics_dc.h:195
GDC_CLOCK_FREQ_3MHz
@ GDC_CLOCK_FREQ_3MHz
Definition: app_graphics_dc.h:87
GDC_DATA_FORMAT_TSC6
@ GDC_DATA_FORMAT_TSC6
Definition: app_graphics_dc.h:182
GDC_CLOCK_FREQ_24MHz
@ GDC_CLOCK_FREQ_24MHz
Definition: app_graphics_dc.h:84
app_graphics_dc_params_t::resolution_x
uint16_t resolution_x
Definition: app_graphics_dc.h:268
app_io_pull_t
app_io_pull_t
GPIO pull Enumerations definition.
Definition: app_io.h:183
app_graphics_dc_pins_t::io0
app_graphics_dc_pin_t io0
Definition: app_graphics_dc.h:148
app_graphics_dc_spi_send
void app_graphics_dc_spi_send(uint8_t cmd_8bit, uint32_t address_24bit, uint8_t *data, uint32_t length)
Send 1 Byte CMD,3 Byte ADDR And N Byte Data in 1-wire SPI Mode.
GDC_DATA_FORMAT_RGB565
@ GDC_DATA_FORMAT_RGB565
Definition: app_graphics_dc.h:175
GDC_DATA_FORMAT_BGRA8888
@ GDC_DATA_FORMAT_BGRA8888
Definition: app_graphics_dc.h:180
app_graphics_dc_frame_result_e
app_graphics_dc_frame_result_e
Define frame output result for DC.
Definition: app_graphics_dc.h:245
GDC_FRAME_ADDRESS_WIDTH_NONE
@ GDC_FRAME_ADDRESS_WIDTH_NONE
Definition: app_graphics_dc.h:227
app_graphics_dc_pins_t::dcx
app_graphics_dc_pin_t dcx
Definition: app_graphics_dc.h:152
app_graphics_dc_send_single_frame
app_graphics_dc_frame_result_e app_graphics_dc_send_single_frame(uint32_t which_layer, app_graphics_dc_framelayer_t *frame_layer, app_graphics_dc_cmd_t *dc_cmd, app_graphics_dc_access_type_e access_type)
Send one whole frame by DC.
app_graphics_dc_params_t
Define init params for DC.
Definition: app_graphics_dc.h:261
GDC_MIPICFG_DSPI_RGB888_OPT1
@ GDC_MIPICFG_DSPI_RGB888_OPT1
Definition: app_graphics_dc.h:197
app_graphics_dc_framelayer_t::data_format
graphics_dc_data_format_e data_format
Definition: app_graphics_dc.h:287
GDC_MIPICFG_DSPI_RGB888_OPT0
@ GDC_MIPICFG_DSPI_RGB888_OPT0
Definition: app_graphics_dc.h:196
GDC_QSPI_FRAME_TIMING_1
@ GDC_QSPI_FRAME_TIMING_1
Definition: app_graphics_dc.h:219
app_graphics_dc_framelayer_t
Define DC Frame Layer configuration.
Definition: app_graphics_dc.h:276
GDC_OUT_PIXEL_BITS_16
@ GDC_OUT_PIXEL_BITS_16
Definition: app_graphics_dc.h:207
app_graphics_dc_params_t::clock_freq
graphics_dc_clock_freq_e clock_freq
Definition: app_graphics_dc.h:263
GDC_CLOCK_FREQ_12MHz
@ GDC_CLOCK_FREQ_12MHz
Definition: app_graphics_dc.h:85
graphics_dc_layer_mode_e
graphics_dc_layer_mode_e
Define work layers for DC.
Definition: app_graphics_dc.h:165
app_graphics_dc_framelayer_t::row_stride
int32_t row_stride
Definition: app_graphics_dc.h:280
app_io.h
Header file containing functions prototypes of GPIO app library.
app_graphics_dc_params_t::pins_cfg
app_graphics_dc_pins_t pins_cfg
Definition: app_graphics_dc.h:270
app_graphics_dc_pins_t::clk
app_graphics_dc_pin_t clk
Definition: app_graphics_dc.h:147
app_graphics_dc_params_t::resolution_y
uint16_t resolution_y
Definition: app_graphics_dc.h:269
GDC_DATA_FORMAT_TSC6A
@ GDC_DATA_FORMAT_TSC6A
Definition: app_graphics_dc.h:183
app_graphics_dc_cmd_t
Define Control Command for DC Frame.
Definition: app_graphics_dc.h:294
app_graphics_dc_frame_timing_e
app_graphics_dc_frame_timing_e
Define the Output Frame Timing for DC.
Definition: app_graphics_dc.h:215
GDC_OUT_PIXEL_BITS_NOT_SUPPORT
@ GDC_OUT_PIXEL_BITS_NOT_SUPPORT
Definition: app_graphics_dc.h:209
app_graphics_dc_params_t::mipicfg_format
graphics_dc_mipi_format_e mipicfg_format
Definition: app_graphics_dc.h:267
app_graphics_dc_framelayer_t::resolution_x
uint32_t resolution_x
Definition: app_graphics_dc.h:278
GDC_TCSU_CYCLE_0
@ GDC_TCSU_CYCLE_0
Definition: app_graphics_dc.h:106
GDC_TCSU_CYCLE_4
@ GDC_TCSU_CYCLE_4
Definition: app_graphics_dc.h:110
GDC_TWO_LAYER_MODE
@ GDC_TWO_LAYER_MODE
Definition: app_graphics_dc.h:167
app_graphics_dc_dspi_send_cmd_data_in_3wire_1lane
void app_graphics_dc_dspi_send_cmd_data_in_3wire_1lane(uint8_t cmd, uint8_t data)
Send single cmd &data in 3-wire mode for DSPI (no DCX and 1 more MSB Bit for cmd/data indicator)
GDC_POWER_STATE_ACTIVE
@ GDC_POWER_STATE_ACTIVE
Definition: app_graphics_dc.h:118
graphics_dc_irq_event_notify_cb
void(* graphics_dc_irq_event_notify_cb)(uint32_t evt)
DC IRQ callback definition.
Definition: app_graphics_dc.h:380
app_graphics_dc_framelayer_t::resolution_y
uint32_t resolution_y
Definition: app_graphics_dc.h:279
GDC_FRAME_ADDRESS_WIDTH_08BIT
@ GDC_FRAME_ADDRESS_WIDTH_08BIT
Definition: app_graphics_dc.h:228
app_graphics_dc_pins_t
define DC pins
Definition: app_graphics_dc.h:145
graphics_dc_mspi_e
graphics_dc_mspi_e
Define SPI work Mode for DC.
Definition: app_graphics_dc.h:72
app_graphics_dc_framelayer_t::alpha
uint8_t alpha
Definition: app_graphics_dc.h:285
GDC_FRAME_ADDRESS_WIDTH_24BIT
@ GDC_FRAME_ADDRESS_WIDTH_24BIT
Definition: app_graphics_dc.h:230
app_graphics_dc_frame_address_width_e
app_graphics_dc_frame_address_width_e
Define the bits of address phase for DC Frame.
Definition: app_graphics_dc.h:226
GDC_MIPICFG_SPI_RGB565_OPT0
@ GDC_MIPICFG_SPI_RGB565_OPT0
Definition: app_graphics_dc.h:193
graphics_dc_data_format_e
graphics_dc_data_format_e
Define the data format for frame buffer of DC.
Definition: app_graphics_dc.h:174
app_graphics_dc_cmd_t::command
uint8_t command
Definition: app_graphics_dc.h:295
app_graphics_dc_framelayer_t::size_y
uint32_t size_y
Definition: app_graphics_dc.h:284
app_graphics_dc_pins_t::io3
app_graphics_dc_pin_t io3
Definition: app_graphics_dc.h:151
app_graphics_dc_framelayer_t::start_y
int32_t start_y
Definition: app_graphics_dc.h:282
GDC_MIPICFG_QSPI_RGB888_OPT0
@ GDC_MIPICFG_QSPI_RGB888_OPT0
Definition: app_graphics_dc.h:199
app_graphics_dc_framelayer_t::frame_baseaddr
void * frame_baseaddr
Definition: app_graphics_dc.h:277
app_graphics_dc_params_t::clock_mode
graphics_dc_clock_mode_e clock_mode
Definition: app_graphics_dc.h:264
GDC_MIPICFG_SPI_RGB888_OPT0
@ GDC_MIPICFG_SPI_RGB888_OPT0
Definition: app_graphics_dc.h:194
GDC_ONE_LAYER_MODE
@ GDC_ONE_LAYER_MODE
Definition: app_graphics_dc.h:166
app_graphics_dc_freq_set
void app_graphics_dc_freq_set(graphics_dc_clock_freq_e clock_freq)
DC clock frequency set.
app_graphics_dc_pins_t::csn
app_graphics_dc_pin_t csn
Definition: app_graphics_dc.h:146
GDC_DATA_FORMAT_ARGB8888
@ GDC_DATA_FORMAT_ARGB8888
Definition: app_graphics_dc.h:179
graphics_dc_tcsu_cycle_e
graphics_dc_tcsu_cycle_e
Define Delay Clock for DC Tcsu.
Definition: app_graphics_dc.h:105
app_graphics_dc_pins_t::io1
app_graphics_dc_pin_t io1
Definition: app_graphics_dc.h:149
graphics_dc_mipi_format_e
graphics_dc_mipi_format_e
Define the Output MIPI Timing for DATA Phase of DC Timing of MIPICFG_2RGB888_OPT1 is True MIPICFG_2RG...
Definition: app_graphics_dc.h:192
app_graphics_dc_set_power_state
void app_graphics_dc_set_power_state(graphics_dc_power_state_e state)
Switch power state for DC module.
GDC_TCSU_CYCLE_2
@ GDC_TCSU_CYCLE_2
Definition: app_graphics_dc.h:108
GDC_FRAME_RES_SUCCESS
@ GDC_FRAME_RES_SUCCESS
Definition: app_graphics_dc.h:246
GDC_MIPICFG_QSPI_RGB565_OPT0
@ GDC_MIPICFG_QSPI_RGB565_OPT0
Definition: app_graphics_dc.h:198
app_graphics_dc_pin_t::pull
app_io_pull_t pull
Definition: app_graphics_dc.h:136
GDC_MODE_DSPI
@ GDC_MODE_DSPI
Definition: app_graphics_dc.h:74
app_graphics_dc_dspi_send_cmd_datas_in_4wire_2lane
void app_graphics_dc_dspi_send_cmd_datas_in_4wire_2lane(uint16_t cmd, uint16_t *data, int length)
Send cmd &data in 4-wire mode for DSPI (DCX as SD1, and 1 more MSB Bit for cmd/data indicator)
GDC_DSPI_FRAME_TIMING_0
@ GDC_DSPI_FRAME_TIMING_0
Definition: app_graphics_dc.h:217
app_graphics_dc_framelayer_t::blendmode
uint8_t blendmode
Definition: app_graphics_dc.h:286
GDC_FRAME_ADDRESS_WIDTH_16BIT
@ GDC_FRAME_ADDRESS_WIDTH_16BIT
Definition: app_graphics_dc.h:229
GDC_MODE_QSPI
@ GDC_MODE_QSPI
Definition: app_graphics_dc.h:75
graphics_dc_out_pixel_bits_e
graphics_dc_out_pixel_bits_e
Define the Output pixel bits for DC.
Definition: app_graphics_dc.h:206
GDC_OUT_PIXEL_BITS_24
@ GDC_OUT_PIXEL_BITS_24
Definition: app_graphics_dc.h:208
app_graphics_dc_access_type_e
app_graphics_dc_access_type_e
Define access type for DC.
Definition: app_graphics_dc.h:236
GDC_CLOCK_MODE_0
@ GDC_CLOCK_MODE_0
Definition: app_graphics_dc.h:95
GDC_FRAME_RES_ASYNC_WAIT
@ GDC_FRAME_RES_ASYNC_WAIT
Definition: app_graphics_dc.h:247
graphics_dc_init
uint16_t graphics_dc_init(app_graphics_dc_params_t *dc_params, graphics_dc_irq_event_notify_cb evt_cb)
init Graphics DC dev
app_graphics_dc_framelayer_t::start_x
int32_t start_x
Definition: app_graphics_dc.h:281
GDC_DATA_FORMAT_ABGR8888
@ GDC_DATA_FORMAT_ABGR8888
Definition: app_graphics_dc.h:178
GDC_DATA_FORMAT_TSC4
@ GDC_DATA_FORMAT_TSC4
Definition: app_graphics_dc.h:181
GDC_QSPI_FRAME_TIMING_0
@ GDC_QSPI_FRAME_TIMING_0
Definition: app_graphics_dc.h:218
GDC_DATA_FORMAT_RGB24
@ GDC_DATA_FORMAT_RGB24
Definition: app_graphics_dc.h:176
app_graphics_dc_params_t::layer_mode
graphics_dc_layer_mode_e layer_mode
Definition: app_graphics_dc.h:266
app_graphics_dc_params_t::mspi_mode
graphics_dc_mspi_e mspi_mode
Definition: app_graphics_dc.h:262
app_graphics_dc_cmd_t::address_width
app_graphics_dc_frame_address_width_e address_width
Definition: app_graphics_dc.h:297