gr55xx_ll_uart.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (UART0) || defined (UART1) || \
63 defined (UART2) || defined (UART3)
64
65 /** @defgroup UART_LL_STRUCTURES Structures
66 * @{
67 */
68
69 /* Exported types ------------------------------------------------------------*/
70 /** @defgroup UART_LL_ES_INIT UART Exported init structures
71 * @{
72 */
73
74 /**
75 * @brief LL UART init Structure definition
76 */
77 typedef struct _ll_uart_init_t
78 {
79 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
80
81 This feature can be modified afterwards using unitary function @ref ll_uart_set_baud_rate().*/
82
83 uint32_t data_bits; /**< Specifies the number of data bits transmitted or received in a frame.
84 This parameter can be a value of @ref UART_LL_EC_DATABITS.
85
86 This feature can be modified afterwards using unitary function @ref ll_uart_set_data_bits_length().*/
87
88 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
89 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
90
91 This feature can be modified afterwards using unitary function @ref ll_uart_set_stop_bits_length().*/
92
93 uint32_t parity; /**< Specifies the parity mode.
94 This parameter can be a value of @ref UART_LL_EC_PARITY.
95
96 This feature can be modified afterwards using unitary function @ref ll_uart_set_parity().*/
97
98 uint32_t hw_flow_ctrl; /**< Specifies whether the hardware flow control mode is enabled or disabled.
99 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
100
101 This feature can be modified afterwards using unitary function @ref ll_uart_set_hw_flow_ctrl().*/
102 } ll_uart_init_t;
103
104 /** @} */
105
106 /** @} */
107
108 /**
109 * @defgroup UART_LL_MACRO Defines
110 * @{
111 */
112
113 /* Exported constants --------------------------------------------------------*/
114 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
115 * @{
116 */
117
118 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
119 * @brief Flags definitions which can be used with LL_UART_ReadReg function
120 * @{
121 */
122 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
123 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
124 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
125 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
126 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register empty flag */
127 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
128 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
129
130 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
131 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
132 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
133 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
134 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
135 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
136
137 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
138 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
139 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
140 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
141 /** @} */
142
143 /** @defgroup UART_LL_EC_IT IT Defines
144 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
145 * @{
146 */
147 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status Interrupt */
148 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line Status Interrupt */
149 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding Register Empty Interrupt */
150 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available Interrupt and Character Timeout Interrupt */
151 /** @} */
152
153 /** @defgroup UART_LL_EC_PARITY Parity Control
154 * @{
155 */
156 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
157 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and Odd Parity is selected */
158 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and Even Parity is selected */
159 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and Stick Parity 0 is selected */
160 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and Stick Parity 1 is selected */
161 /** @} */
162
163 /** @defgroup UART_LL_EC_DATABITS Data Bits
164 * @{
165 */
166 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit, 5 data bits, n stop bits */
167 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit, 6 data bits, n stop bits */
168 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit, 7 data bits, n stop bits */
169 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit, 8 data bits, n stop bits */
170 /** @} */
171
172 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
173 * @{
174 */
175 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
176 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
177 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
178 /** @} */
179
180 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
181 * @{
182 */
183 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow control disabled */
184 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow control enabled */
185 /** @} */
186
187 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
188 * @{
189 */
190 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
191 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
192 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
193 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
194 /** @} */
195
196 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
197 * @{
198 */
199 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
200 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
201 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
202 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
203 /** @} */
204
205 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
206 * @{
207 */
208 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
209 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
210 /** @} */
211
212 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
213 * @{
214 */
215 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
216 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
217 /** @} */
218
219 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
220 * @{
221 */
222
223 /**
224 * @brief LL UART InitStrcut default configuartion
225 */
226 #define LL_UART_DEFAULT_CONFIG \
227 { \
228 .baud_rate = 9600U, \
229 .data_bits = LL_UART_DATABITS_8B, \
230 .stop_bits = LL_UART_STOPBITS_1, \
231 .parity = LL_UART_PARITY_NONE, \
232 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
233 }
234 /** @} */
235
236 /** @} */
237
238 /* Exported macro ------------------------------------------------------------*/
239 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
240 * @{
241 */
242
243 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
244 * @{
245 */
246
247 /**
248 * @brief Write a value in UART register
249 * @param __instance__ UART instance
250 * @param __REG__ Register to be written
251 * @param __VALUE__ Value to be written in the register
252 * @retval None
253 */
254 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
255
256 /**
257 * @brief Read a value in UART register
258 * @param __instance__ UART instance
259 * @param __REG__ Register to be read
260 * @retval Register value
261 */
262 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
263
264 /** @} */
265
266 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
267 * @{
268 */
269
270 /**
271 * @brief Compute UARTDIV value according to Peripheral Clock and
272 * expected Baud Rate (32 bits value of UARTDIV is returned)
273 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
274 * @param __BAUDRATE__ Baud rate value to achieve
275 * @retval UARTDIV value to be used for DLL,DLH registers
276 */
277 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
278
279 /**
280 * @brief Compute UARTDLF value according to Peripheral Clock and
281 * expected Baud Rate (32 bits value of UARTDLF is returned)
282 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
283 * @param __BAUDRATE__ Baud rate value to achieve
284 * @retval UARTDLF value to be used for DLL,DLH registers
285 */
286 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
287
288 /** @} */
289
290 /** @} */
291
292 /** @} */
293
294 /* Exported functions --------------------------------------------------------*/
295 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
296 * @{
297 */
298
299 /** @defgroup UART_LL_EF_Configuration Configuration functions
300 * @{
301 */
302
303 /**
304 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
305 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
306 * (Baud rate value != 0)
307 *
308 * Register|BitsName
309 * --------|--------
310 * DLL | DLL
311 * DLH | DLH
312 *
313 * @param UARTx UART instance
314 * @param peripheral_clock Peripheral Clock
315 * @param baud_rate Baud Rate
316 * @retval None
317 */
318 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
319 {
320 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
321
322 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
323 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
324 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
325 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
326 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
327 }
328
329 /**
330 * @brief Return current Baud Rate value
331 * @note In case of non-initialized or invalid value stored in DLL,DLH and DLF register, the value 0 will be returned..
332 *
333 * Register|BitsName
334 * --------|--------
335 * DLL | DLL
336 * DLH | DLH
337 *
338 * @param UARTx UART instance
339 * @param peripheral_clock Peripheral Clock
340 * @retval Baud Rate
341 */
342 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
343 {
344 register uint32_t uartdiv = 0x0U;
345 register uint32_t baud = 0x0U;
346
347 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
348 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
349 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
350
351 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
352 {
353 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
354 }
355
356 return baud;
357 }
358
359 /**
360 * @brief Set the length of the data bits
361 *
362 * Register|BitsName
363 * --------|--------
364 * LCR | DLS
365 *
366 * @param UARTx UART instance
367 * @param data_bits This parameter can be one of the following values:
368 * @arg @ref LL_UART_DATABITS_5B
369 * @arg @ref LL_UART_DATABITS_6B
370 * @arg @ref LL_UART_DATABITS_7B
371 * @arg @ref LL_UART_DATABITS_8B
372 *
373 * @retval None
374 */
375 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
376 {
377 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
378 }
379
380 /**
381 * @brief Return the length of the data bits
382 *
383 * Register|BitsName
384 * --------|--------
385 * LCR | DLS
386 *
387 * @param UARTx UART instance
388 * @retval Returned value can be one of the following values:
389 * @arg @ref LL_UART_DATABITS_5B
390 * @arg @ref LL_UART_DATABITS_6B
391 * @arg @ref LL_UART_DATABITS_7B
392 * @arg @ref LL_UART_DATABITS_8B
393 */
394 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
395 {
396 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
397 }
398
399 /**
400 * @brief Set the length of the stop bits
401 *
402 * Register|BitsName
403 * --------|--------
404 * LCR | STOP
405 *
406 * @param UARTx UART instance
407 * @param stop_bits This parameter can be one of the following values:
408 * @arg @ref LL_UART_STOPBITS_1
409 * @arg @ref LL_UART_STOPBITS_1_5 (*)
410 * @arg @ref LL_UART_STOPBITS_2 (*)
411 *
412 * (*) STOPBITS_1_5 only valid when DataBits = 5
413 * (*) STOPBITS_2 is invalid when DataBits = 5
414 * @retval None
415 */
416 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
417 {
418 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
419 }
420
421 /**
422 * @brief Retrieve the length of the stop bits
423 *
424 * Register|BitsName
425 * --------|--------
426 * LCR | STOP
427 *
428 * @param UARTx UART instance
429 * @retval Returned value can be one of the following values:
430 * @arg @ref LL_UART_STOPBITS_1
431 * @arg @ref LL_UART_STOPBITS_1_5
432 * @arg @ref LL_UART_STOPBITS_2
433 */
434 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
435 {
436 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
437 }
438
439 /**
440 * @brief Configure Parity.
441 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
442 * When the parity control is enabled (Odd,Even,0,1), computed parity bit is inserted at the MSB position
443 * and parity is checked on the received data.
444 *
445 * Register|BitsName
446 * --------|--------
447 * LCR | SP
448 * LCR | EPS
449 * LCR | PEN
450 *
451 * @param UARTx UART instance
452 * @param parity This parameter can be one of the following values:
453 * @arg @ref LL_UART_PARITY_NONE
454 * @arg @ref LL_UART_PARITY_EVEN
455 * @arg @ref LL_UART_PARITY_ODD
456 * @arg @ref LL_UART_PARITY_SP0
457 * @arg @ref LL_UART_PARITY_SP1
458 * @retval None
459 */
460 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
461 {
462 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
463 }
464
465 /**
466 * @brief Return Parity configuration
467 *
468 * Register|BitsName
469 * --------|--------
470 * LCR | SP
471 * LCR | EPS
472 * LCR | PEN
473 *
474 * @param UARTx UART instance
475 * @retval Returned value can be one of the following values:
476 * @arg @ref LL_UART_PARITY_NONE
477 * @arg @ref LL_UART_PARITY_EVEN
478 * @arg @ref LL_UART_PARITY_ODD
479 * @arg @ref LL_UART_PARITY_SP0
480 * @arg @ref LL_UART_PARITY_SP1
481 */
482 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
483 {
484 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
485 }
486
487 /**
488 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
489 * @note This function call is equivalent to the following function call sequence :
490 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
491 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
492 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
493 *
494 * Register|BitsName
495 * --------|--------
496 * LCR | PS
497 * LCR | EPS
498 * LCR | PEN
499 * LCR | STOP
500 * LCR | DLS
501 *
502 * @param UARTx UART instance
503 * @param data_bits This parameter can be one of the following values:
504 * @arg @ref LL_UART_DATABITS_5B
505 * @arg @ref LL_UART_DATABITS_6B
506 * @arg @ref LL_UART_DATABITS_7B
507 * @arg @ref LL_UART_DATABITS_8B
508 * @param parity This parameter can be one of the following values:
509 * @arg @ref LL_UART_PARITY_NONE
510 * @arg @ref LL_UART_PARITY_EVEN
511 * @arg @ref LL_UART_PARITY_ODD
512 * @arg @ref LL_UART_PARITY_SP0
513 * @arg @ref LL_UART_PARITY_SP1
514 * @param stop_bits This parameter can be one of the following values:
515 * @arg @ref LL_UART_STOPBITS_1
516 * @arg @ref LL_UART_STOPBITS_1_5 (*)
517 * @arg @ref LL_UART_STOPBITS_2 (*)
518 *
519 * (*) STOPBITS_1_5 only valid when DataBits = 5
520 * (*) STOPBITS_2 is invalid when DataBits = 5
521 * @retval None
522 */
523 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
524 uint32_t data_bits,
525 uint32_t parity,
526 uint32_t stop_bits)
527 {
528 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
529 }
530
531 /**
532 * @brief Set UART RTS pin state to Active/Inactive
533 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
534 *
535 * Register|BitsName
536 * --------|--------
537 * SRTS | SRTS
538 * MCR | RTS
539 *
540 * @param UARTx UART instance
541 * @param pin_state This parameter can be one of the following values:
542 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
543 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
544 * @retval None
545 */
546 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
547 {
548 WRITE_REG(UARTx->SRTS, pin_state);
549 }
550
551 /**
552 * @brief Get UART RTS pin state
553 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
554 *
555 * Register|BitsName
556 * --------|--------
557 * SRTS | SRTS
558 * MCR | RTS
559 *
560 * @param UARTx UART instance
561 * @retval Returned value can be one of the following values:
562 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
563 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
564 */
565 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
566 {
567 return (uint32_t)(READ_REG(UARTx->SRTS));
568 }
569
570 /**
571 * @brief Get UART CTS pin state
572 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
573 *
574 * Register|BitsName
575 * --------|--------
576 * MSR | CTS
577 *
578 * @param UARTx UART instance
579 * @retval Returned value can be one of the following values:
580 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
581 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
582 */
583 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
584 {
585 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
586 }
587
588 /**
589 * @brief Indicate if CTS is changed since the last time the MSR was read
590 *
591 * Register|BitsName
592 * --------|--------
593 * MSR | DCTS
594 *
595 * @param UARTx UART instance
596 * @retval State of bit (1 or 0).
597 */
598 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
599 {
600 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
601 }
602
603 /**
604 * @brief Configure SIR mode enable
605 * @note This function is used to Enable UART SIR mode.
606 *
607 * Register|BitsName
608 * --------|--------
609 * MCR | SIRE
610 *
611 * @param UARTx UART instance
612 * @retval None
613 */
614 __STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
615 {
616 SET_BITS(UARTx->MCR, UART_MCR_SIRE);
617 }
618
619 /**
620 * @brief Configure SIR mode disable
621 * @note This function is used to Disable UART SIR mode.
622 *
623 * Register|BitsName
624 * --------|--------
625 * MCR | SIRE
626 *
627 * @param UARTx UART instance
628 * @retval None
629 */
630 __STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
631 {
632 CLEAR_BITS(UARTx->MCR, UART_MCR_SIRE);
633 }
634
635 /**
636 * @brief Return SIR mode state
637 * @note This function is used to return UART SIR mode state.
638 *
639 * Register|BitsName
640 * --------|--------
641 * MCR | SIRE
642 *
643 * @param UARTx UART instance
644 * @retval State of bit (1 or 0).
645 */
646 __STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
647 {
648 return (READ_BITS(UARTx->MCR, UART_MCR_SIRE) == UART_MCR_SIRE);
649 }
650
651 /**
652 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
653 * @note This function is used to Enable/Disable UART Auto Flow Control.
654 *
655 * Register|BitsName
656 * --------|--------
657 * MCR | AFCE
658 * MCR | RTS
659 *
660 * @param UARTx UART instance
661 * @param hw_flow_ctrl This parameter can be one of the following values:
662 * @arg @ref LL_UART_HWCONTROL_NONE
663 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
664 * @retval None
665 */
666 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
667 {
668 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
669 }
670
671 /**
672 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
673 *
674 * Register|BitsName
675 * --------|--------
676 * MCR | AFCE
677 * MCR | RTS
678 *
679 * @param UARTx UART instance
680 * @retval Returned value can be one of the following values:
681 * @arg @ref LL_UART_HWCONTROL_NONE
682 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
683 */
684 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
685 {
686 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
687 }
688
689 /**
690 * @brief Enable Break sending
691 *
692 * Register|BitsName
693 * --------|--------
694 * LCR | BC
695 *
696 * @param UARTx UART instance
697 * @retval None
698 */
699 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
700 {
701 WRITE_REG(UARTx->SBCR, 0x1U);
702 }
703
704 /**
705 * @brief Disable Break sending
706 *
707 * Register|BitsName
708 * --------|--------
709 * LCR | BC
710 *
711 * @param UARTx UART instance
712 * @retval None
713 */
714 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
715 {
716 WRITE_REG(UARTx->SBCR, 0x0U);
717 }
718
719 /**
720 * @brief Indicate if Break sending is enabled
721 *
722 * Register|BitsName
723 * --------|--------
724 * LCR | BC
725 *
726 * @param UARTx UART instance
727 * @retval State of bit (1 or 0).
728 */
729 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
730 {
731 return READ_REG(UARTx->SBCR);
732 }
733
734 /**
735 * @brief Enable TX FIFO and RX FIFO
736 *
737 * Register|BitsName
738 * --------|--------
739 * SFE | SFE
740 *
741 * @param UARTx UART instance
742 * @retval None
743 */
744 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
745 {
746 WRITE_REG(UARTx->SFE, 0x1U);
747 }
748
749 /**
750 * @brief Disable TX FIFO and RX FIFO
751 *
752 * Register|BitsName
753 * --------|--------
754 * SFE | SFE
755 *
756 * @param UARTx UART instance
757 * @retval None
758 */
759 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
760 {
761 WRITE_REG(UARTx->SFE, 0x0U);
762 }
763
764 /**
765 * @brief Indicate if TX FIFO and RX FIFO is enabled
766 *
767 * Register|BitsName
768 * --------|--------
769 * SFE | SFE
770 *
771 * @param UARTx UART instance
772 * @retval State of bit (1 or 0).
773 */
774 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
775 {
776 return READ_REG(UARTx->SFE);
777 }
778
779 /**
780 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
781 *
782 * Register|BitsName
783 * --------|--------
784 * STET | STET
785 *
786 * @param UARTx UART instance
787 * @param threshold This parameter can be one of the following values:
788 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
789 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
790 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
791 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
792 * @retval None
793 */
794 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
795 {
796 WRITE_REG(UARTx->STET, threshold);
797 }
798
799 /**
800 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
801 *
802 * Register|BitsName
803 * --------|--------
804 * STET | STET
805 *
806 * @param UARTx UART instance
807 * @retval Returned value can be one of the following values:
808 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
809 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
810 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
811 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
812 */
813 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
814 {
815 return (uint32_t)(READ_REG(UARTx->STET));
816 }
817
818 /**
819 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
820 *
821 * Register|BitsName
822 * --------|--------
823 * SRT | SRT
824 *
825 * @param UARTx UART instance
826 * @param threshold This parameter can be one of the following values:
827 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
828 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
829 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
830 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
831 * @retval None
832 */
833 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
834 {
835 WRITE_REG(UARTx->SRT, threshold);
836 }
837
838 /**
839 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
840 *
841 * Register|BitsName
842 * --------|--------
843 * SRT | SRT
844 *
845 * @param UARTx UART instance
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
848 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
849 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
850 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
851 */
852 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
853 {
854 return (uint32_t)(READ_REG(UARTx->SRT));
855 }
856
857 /**
858 * @brief Get FIFO Transmission Level
859 *
860 * Register|BitsName
861 * --------|--------
862 * TFL | TFL
863 *
864 * @param UARTx UART instance
865 * @retval Returned value can be one of the following values:
866 */
867 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
868 {
869 return (uint32_t)(READ_REG(UARTx->TFL));
870 }
871
872 /**
873 * @brief Get FIFO reception Level
874 *
875 * Register|BitsName
876 * --------|--------
877 * RFL | RFL
878 *
879 * @param UARTx UART instance
880 * @retval Returned value can be one of the following values:
881 */
882 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
883 {
884 return (uint32_t)(READ_REG(UARTx->RFL));
885 }
886
887 /**
888 * @brief Flush Receive FIFO
889 *
890 * Register|BitsName
891 * --------|--------
892 * SRR | RFR
893 *
894 * @param UARTx UART instance
895 * @retval None
896 */
897 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
898 {
899 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
900 }
901
902 /**
903 * @brief Flush Transmit FIFO
904 *
905 * Register|BitsName
906 * --------|--------
907 * SRR | XFR
908 *
909 * @param UARTx UART instance
910 * @retval None
911 */
912 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
913 {
914 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
915 }
916
917 /**
918 * @brief Reset UART
919 * @note This function asynchronously resets the DW_apb_uart and synchronously
920 * removes the reset assertion. For a two clock implementation, both pclk
921 * and sclk domains will be reset.
922 *
923 * Register|BitsName
924 * --------|--------
925 * SRR | UR
926 *
927 * @param UARTx UART instance
928 * @retval None
929 */
930 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
931 {
932 WRITE_REG(UARTx->SRR, UART_SRR_UR);
933 }
934
935 /** @} */
936
937 /** @defgroup UART_LL_EF_IT_Management IT_Management
938 * @{
939 */
940
941 /**
942 * @brief Enable Modem Status Interrupt
943 *
944 * Register|BitsName
945 * --------|--------
946 * IER | EDSSI
947 *
948 * @param UARTx UART instance
949 * @retval None
950 */
951 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
952 {
953 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
954 }
955
956 /**
957 * @brief Enable Receiver Line Status Interrupt
958 *
959 * Register|BitsName
960 * --------|--------
961 * IER | RLS
962 *
963 * @param UARTx UART instance
964 * @retval None
965 */
966 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
967 {
968 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
969 }
970
971 /**
972 * @brief Enable Transmit Holding Register Empty Interrupt
973 *
974 * Register|BitsName
975 * --------|--------
976 * IER | PTIME
977 * IER | ETBEI
978 *
979 * @param UARTx UART instance
980 * @retval None
981 */
982 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
983 {
984 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
985 }
986
987 /**
988 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
989 *
990 * Register|BitsName
991 * --------|--------
992 * IER | ERBFI
993 *
994 * @param UARTx UART instance
995 * @retval None
996 */
997 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
998 {
999 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1000 }
1001
1002 /**
1003 * @brief Disable Modem Status Interrupt
1004 *
1005 * Register|BitsName
1006 * --------|--------
1007 * IER | EDSSI
1008 *
1009 * @param UARTx UART instance
1010 * @retval None
1011 */
1012 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
1013 {
1014 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1015 }
1016
1017 /**
1018 * @brief Disable Receiver Line Status Interrupt
1019 *
1020 * Register|BitsName
1021 * --------|--------
1022 * IER | RLS
1023 *
1024 * @param UARTx UART instance
1025 * @retval None
1026 */
1027 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
1028 {
1029 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1030 }
1031
1032 /**
1033 * @brief Disable Transmit Holding Register Empty Interrupt
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * IER | PTIME
1038 * IER | ETBEI
1039 *
1040 * @param UARTx UART instance
1041 * @retval None
1042 */
1043 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
1044 {
1045 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1046 }
1047
1048 /**
1049 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1050 *
1051 * Register|BitsName
1052 * --------|--------
1053 * IER | ERBFI
1054 *
1055 * @param UARTx UART instance
1056 * @retval None
1057 */
1058 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1059 {
1060 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1061 }
1062
1063 /**
1064 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1065 *
1066 * Register|BitsName
1067 * --------|--------
1068 * IER | EDSSI
1069 *
1070 * @param UARTx UART instance
1071 * @retval State of bit (1 or 0).
1072 */
1073 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1074 {
1075 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1076 }
1077
1078 /**
1079 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1080 *
1081 * Register|BitsName
1082 * --------|--------
1083 * IER | RLS
1084 *
1085 * @param UARTx UART instance
1086 * @retval State of bit (1 or 0).
1087 */
1088 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1089 {
1090 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1091 }
1092
1093 /**
1094 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1095 *
1096 * Register|BitsName
1097 * --------|--------
1098 * IER | PTIME
1099 * IER | ETBEI
1100 *
1101 * @param UARTx UART instance
1102 * @retval State of bit (1 or 0).
1103 */
1104 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1105 {
1106 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1107 }
1108
1109 /**
1110 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1111 * is enabled or disabled.
1112 *
1113 * Register|BitsName
1114 * --------|--------
1115 * IER | ERBFI
1116 *
1117 * @param UARTx UART instance
1118 * @retval State of bit (1 or 0).
1119 */
1120 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1121 {
1122 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1123 }
1124
1125 /**
1126 * @brief Enable the specified UART Interrupt.
1127 *
1128 * Register|BitsName
1129 * --------|--------
1130 * IER | EDSSI
1131 * IER | ERLS
1132 * IER | PTIME
1133 * IER | ETBEI
1134 * IER | ERBFI
1135 *
1136 * @param UARTx UART instance
1137 * @param mask This parameter can be a combination of the following values:
1138 * @arg @ref LL_UART_IER_MS
1139 * @arg @ref LL_UART_IER_RLS
1140 * @arg @ref LL_UART_IER_THRE
1141 * @arg @ref LL_UART_IER_RDA
1142 * @retval None
1143 */
1144 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1145 {
1146 SET_BITS(UARTx->DLH_IER.IER, mask);
1147 }
1148
1149 /**
1150 * @brief Disable the specified UART Interrupt.
1151 *
1152 * Register|BitsName
1153 * --------|--------
1154 * IER | EDSSI
1155 * IER | ERLS
1156 * IER | PTIME
1157 * IER | ETBEI
1158 * IER | ERBFI
1159 *
1160 * @param UARTx UART instance
1161 * @param mask This parameter can be a combination of the following values:
1162 * @arg @ref LL_UART_IER_MS
1163 * @arg @ref LL_UART_IER_RLS
1164 * @arg @ref LL_UART_IER_THRE
1165 * @arg @ref LL_UART_IER_RDA
1166 * @retval None
1167 */
1168 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1169 {
1170 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1171 }
1172
1173 /**
1174 * @brief Check if the specified UART Interrupt is enabled or disabled.
1175 *
1176 * Register|BitsName
1177 * --------|--------
1178 * IER | EDSSI
1179 * IER | ERLS
1180 * IER | PTIME
1181 * IER | ETBEI
1182 * IER | ERBFI
1183 *
1184 * @param UARTx UART instance
1185 * @param mask This parameter can be a combination of the following values:
1186 * @arg @ref LL_UART_IER_MS
1187 * @arg @ref LL_UART_IER_RLS
1188 * @arg @ref LL_UART_IER_THRE
1189 * @arg @ref LL_UART_IER_RDA
1190 * @retval State of bit (1 or 0).
1191 */
1192 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1193 {
1194 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1195 }
1196
1197 /** @} */
1198
1199 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1200 * @{
1201 */
1202
1203 /**
1204 * @brief Get UART Receive Line Status Flag
1205 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1206 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1207 *
1208 * Register|BitsName
1209 * --------|--------
1210 * LSR | OE
1211 * LSR | PE
1212 * LSR | FE
1213 * LSR | BI
1214 * LSR | THRE
1215 * LSR | TEMT
1216 * LSR | RFE
1217 *
1218 * @param UARTx UART instance
1219 * @retval Returned value can be a combination of the following values:
1220 * @arg @ref LL_UART_LSR_OE
1221 * @arg @ref LL_UART_LSR_PE
1222 * @arg @ref LL_UART_LSR_FE
1223 * @arg @ref LL_UART_LSR_BI
1224 * @arg @ref LL_UART_LSR_THRE
1225 * @arg @ref LL_UART_LSR_TEMT
1226 * @arg @ref LL_UART_LSR_RFE
1227 */
1228 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1229 {
1230 return ((uint32_t)READ_REG(UARTx->LSR));
1231 }
1232
1233 /**
1234 * @brief Clear UART Receive Line Status Flag
1235 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1236 *
1237 * Register|BitsName
1238 * --------|--------
1239 * LSR | OE
1240 * LSR | PE
1241 * LSR | FE
1242 * LSR | BI
1243 * LSR | RFE
1244 *
1245 * @param UARTx UART instance
1246 * @retval None
1247 */
1248 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1249 {
1250 __IO uint32_t tmpreg;
1251 tmpreg = READ_REG(UARTx->LSR);
1252 (void) tmpreg;
1253 }
1254
1255 /**
1256 * @brief Check if the UART Receive FIFO Full Flag is set or not
1257 *
1258 * Register|BitsName
1259 * --------|--------
1260 * USR | RFF
1261 *
1262 * @param UARTx UART instance
1263 * @retval State of bit (1 or 0).
1264 */
1265 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1266 {
1267 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1268 }
1269
1270 /**
1271 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1272 *
1273 * Register|BitsName
1274 * --------|--------
1275 * USR | RFNE
1276 *
1277 * @param UARTx UART instance
1278 * @retval State of bit (1 or 0).
1279 */
1280 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1281 {
1282 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1283 }
1284
1285 /**
1286 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1287 *
1288 * Register|BitsName
1289 * --------|--------
1290 * USR | TFE
1291 *
1292 * @param UARTx UART instance
1293 * @retval State of bit (1 or 0).
1294 */
1295 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1296 {
1297 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1298 }
1299
1300 /**
1301 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1302 *
1303 * Register|BitsName
1304 * --------|--------
1305 * USR | TFNF
1306 *
1307 * @param UARTx UART instance
1308 * @retval State of bit (1 or 0).
1309 */
1310 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1311 {
1312 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1313 }
1314
1315 /**
1316 * @brief Get UART interrupt flags
1317 * @note The interrupt flags will be cleared after reading IIR.
1318 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1319 * and No Interrupt Pending Flag will be RESET, read IIR again can get the pended interrupt
1320 *
1321 * Register|BitsName
1322 * --------|--------
1323 * IIR | IID
1324 *
1325 * @param UARTx UART instance
1326 * @retval Returned value can be one or combination of the following values:
1327 * @arg @ref LL_UART_IIR_MS
1328 * @arg @ref LL_UART_IIR_NIP
1329 * @arg @ref LL_UART_IIR_THRE
1330 * @arg @ref LL_UART_IIR_RDA
1331 * @arg @ref LL_UART_IIR_RLS
1332 * @arg @ref LL_UART_IIR_CTO
1333 */
1334 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1335 {
1336 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1337 }
1338
1339 /** @} */
1340
1341 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1342 * @{
1343 */
1344
1345 /**
1346 * @brief Get the data register address used for DMA transfer
1347 * @note The address of data register RBR is the same as the address of THR.
1348 *
1349 * Register|BitsName
1350 * --------|--------
1351 * RBR | RBR
1352 * THR | THR
1353 *
1354 * @param UARTx UART instance
1355 * @retval Address of data register
1356 */
1357 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1358 {
1359 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1360 }
1361
1362 /** @} */
1363
1364 /** @defgroup UART_LL_EF_Data_Management Data_Management
1365 * @{
1366 */
1367
1368 /**
1369 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1370 *
1371 * Register|BitsName
1372 * --------|--------
1373 * RBR | RBR
1374 *
1375 * @param UARTx UART instance
1376 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1377 */
1378 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1379 {
1380 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1381 }
1382
1383 /**
1384 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1385 *
1386 * Register|BitsName
1387 * --------|--------
1388 * THR | THR
1389 *
1390 * @param UARTx UART instance
1391 * @param value between Min_Data=0x00 and Max_Data=0xFF
1392 * @retval None
1393 */
1394 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1395 {
1396 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1397 }
1398
1399 /** @} */
1400
1401 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1402 * @{
1403 */
1404
1405 /**
1406 * @brief De-initialize UART registers (Registers restored to their default values).
1407 * @param UARTx UART instance
1408 * @retval An error_status_t enumeration value:
1409 * - SUCCESS: UART registers are de-initialized
1410 * - ERROR: UART registers are not de-initialized
1411 */
1412 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1413
1414 /**
1415 * @brief Initialize UART registers according to the specified
1416 * parameters in p_uart_init.
1417 * @param UARTx UART instance
1418 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1419 * information for the specified UART peripheral.
1420 * @retval An error_status_t enumeration value:
1421 * - SUCCESS: UART registers are initialized according to p_uart_init content
1422 * - ERROR: Problem occurred during UART Registers initialization
1423 */
1424 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1425
1426 /**
1427 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1428 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1429 * whose fields will be set to default values.
1430 * @retval None
1431 */
1432 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1433
1434 /** @} */
1435
1436 /** @} */
1437
1438 #endif /* UART0 || UART1 || UART2 || UART3 || UART4 || UART5*/
1439
1440 #ifdef __cplusplus
1441 }
1442 #endif
1443
1444 #endif /* __GR55xx_LL_UART_H__ */
1445
1446 /** @} */
1447
1448 /** @} */
1449
1450 /** @} */
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1280
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1073
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: gr55xx_ll_uart.h:546
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: gr55xx_ll_uart.h:729
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:1043
ll_uart_enable_sir
__STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
Configure SIR mode enable.
Definition: gr55xx_ll_uart.h:614
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: gr55xx_ll_uart.h:416
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: gr55xx_ll_uart.h:318
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: gr55xx_ll_uart.h:774
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:982
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_uart.h:1357
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:951
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: gr55xx_ll_uart.h:460
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1058
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: gr55xx_ll_uart.h:286
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_uart.h:867
_ll_uart_init_t
LL UART init Structure definition.
Definition: gr55xx_ll_uart.h:78
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:852
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: gr55xx_ll_uart.h:565
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:966
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: gr55xx_ll_uart.h:714
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1104
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1265
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1144
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1228
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: gr55xx_ll_uart.h:699
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:759
ll_uart_init
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: gr55xx_ll_uart.h:394
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: gr55xx_ll_uart.h:583
_ll_uart_init_t::data_bits
uint32_t data_bits
Definition: gr55xx_ll_uart.h:83
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1088
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1248
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:997
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: gr55xx_ll_uart.h:342
_ll_uart_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_uart.h:79
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: gr55xx_ll_uart.h:1120
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1394
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1168
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:684
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:666
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:813
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:1012
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:833
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: gr55xx_ll_uart.h:912
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1378
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: gr55xx_ll_uart.h:482
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: gr55xx_ll_uart.h:930
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:1027
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Definition: gr55xx_ll_uart.h:88
_ll_uart_init_t::parity
uint32_t parity
Definition: gr55xx_ll_uart.h:93
ll_uart_disable_sir
__STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
Configure SIR mode disable.
Definition: gr55xx_ll_uart.h:630
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: gr55xx_ll_uart.h:882
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Definition: gr55xx_ll_uart.h:98
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1295
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: gr55xx_ll_uart.h:523
ll_uart_deinit
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:744
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:794
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: gr55xx_ll_uart.h:434
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: gr55xx_ll_uart.h:598
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1192
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1310
ll_uart_is_enabled_sir
__STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
Return SIR mode state.
Definition: gr55xx_ll_uart.h:646
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: gr55xx_ll_uart.h:897
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: gr55xx_ll_uart.h:277
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: gr55xx_ll_uart.h:375
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: gr55xx_ll_uart.h:1334