gr55xx_ll_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_GPIO GPIO
47 * @brief GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPIO_H__
53 #define __GR55XX_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (GPIO0) || defined (GPIO1) || defined(MCU_RET)
63
64 /** @defgroup GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup GPIO_LL_ES_INIT GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL GPIO init configuration definition
75 */
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin; /*!< Specifies the GPIO pins to be GPIO_InitStructured.
79 This parameter can be any value of @ref GPIO_LL_EC_PIN */
80
81 uint32_t mode; /*!< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref GPIO_LL_EC_MODE.
83
84 GPIO HW GPIO_Init Struct can be modified afterwards using unitary function @ref ll_gpio_set_pin_mode(). */
85
86 uint32_t pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref GPIO_LL_EC_PULL.
88
89 GPIO HW configuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref GPIO_LL_EC_MUX.
93
94 GPIO HW GPIO_Init Struct can be modified afterwards using unitary function
95 @ref ll_gpio_set_pin_mux(). */
96
97 uint32_t speed; /*!< Specifies the slew rate for the selected pins.
98 This parameter can be a value of @ref GPIO_LL_EC_SPEED.
99
100 GPIO HW GPIO_Init Struct can be modified afterwards using unitary function
101 @ref ll_gpio_set_pin_speed(). */
102
103 uint32_t strength; /*!< Specifies the output drive strength for the selected pins.
104 This parameter can be a value of @ref GPIO_LL_EC_STRENGTH.
105
106 GPIO HW GPIO_Init Struct can be modified afterwards using unitary function
107 @ref ll_gpio_set_pin_strength(). */
108
109 uint32_t input_type; /*!< Specifies the input type for the selected pins.
110 This parameter can be a value of @ref GPIO_LL_EC_INPUT_TYPE.
111
112 GPIO HW GPIO_Init Struct can be modified afterwards using unitary function
113 @ref ll_gpio_set_pin_input_type(). */
114
115 uint32_t trigger; /*!< Specifies the trigger signal active edge.
116 This parameter can be a value of @ref GPIO_LL_EC_TRIGGER. */
117
118 } ll_gpio_init_t;
119
120 /** @} */
121
122 /** @} */
123
124 /**
125 * @defgroup GPIO_LL_MACRO Defines
126 * @{
127 */
128
129 /* Exported constants --------------------------------------------------------*/
130 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
131 * @{
132 */
133 /** @defgroup GPIO_LL_PRIVATE_MACRO GPIO Mode
134 * @{
135 */
136 #define LL_GPIO_MODE_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position GPIO_LL_EC_MODE */
137 #define LL_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position GPIO_LL_EC_MODE */
138 #define LL_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in GPIO_LL_EC_STRENGTH */
139 #define LL_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in GPIO_LL_EC_STRENGTH */
140 #define LL_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in GPIO_LL_EC_STRENGTH */
141 #define LL_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in GPIO_LL_EC_STRENGTH */
142 /** @} */
143
144 /** @defgroup GPIO_LL_EC_PIN PIN
145 * @{
146 */
147 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U) /*!< Select pin 0 */
148 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U) /*!< Select pin 1 */
149 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U) /*!< Select pin 2 */
150 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U) /*!< Select pin 3 */
151 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U) /*!< Select pin 4 */
152 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U) /*!< Select pin 5 */
153 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U) /*!< Select pin 6 */
154 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U) /*!< Select pin 7 */
155 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U) /*!< Select pin 8 */
156 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U) /*!< Select pin 9 */
157 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U) /*!< Select pin 10 */
158 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U) /*!< Select pin 11 */
159 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U) /*!< Select pin 12 */
160 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U) /*!< Select pin 13 */
161 #define LL_GPIO_PIN_14 ((uint32_t)0x4000U) /*!< Select pin 14 */
162 #define LL_GPIO_PIN_15 ((uint32_t)0x8000U) /*!< Select pin 15 */
163 #define LL_GPIO_PIN_ALL ((uint32_t)0xFFFFU) /*!< Select all pins */
164 /** @} */
165
166 /** @defgroup GPIO_LL_EC_MODE Mode
167 * @{
168 */
169 #define LL_GPIO_MODE_NONE ((uint32_t)0x0U) /**< No input or output */
170 #define LL_GPIO_MODE_INPUT ((uint32_t)0x1U) /**< Select input mode */
171 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x2U) /**< Select output mode */
172 #define LL_GPIO_MODE_INOUT ((uint32_t)0x3U) /**< Select input and output mode */
173 /** @} */
174
175 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
176 * @{
177 */
178 #define LL_GPIO_PULL_NO ((uint32_t)0x0U) /*!< Select I/O no pull */
179 #define LL_GPIO_PULL_UP ((uint32_t)0x1U) /*!< Select I/O pull up */
180 #define LL_GPIO_PULL_DOWN ((uint32_t)0x2U) /*!< Select I/O pull down */
181 /** @} */
182
183 /** @defgroup GPIO_LL_EC_MUX Alternate Function
184 * @{
185 */
186 #define LL_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
187 #define LL_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
188 #define LL_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
189 #define LL_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
190 #define LL_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
191 #define LL_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
192 #define LL_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
193 #define LL_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
194 #define LL_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
195 /** @} */
196
197 /** @defgroup GPIO_LL_EC_SPEED IO Speed
198 * @{
199 */
200 #define LL_GPIO_SPEED_MEDIUM ((uint32_t)0x0U) /*!< Select medium speed slew rate */
201 #define LL_GPIO_SPEED_HIGH ((uint32_t)0x1U) /*!< Select high speed slew rate */
202 /** @} */
203
204 /** @defgroup GPIO_LL_EC_STRENGTH IO Strength
205 * @{
206 */
207 #define LL_GPIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
208 #define LL_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
209 #define LL_GPIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
210 #define LL_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
211 /** @} */
212
213 /** @defgroup GPIO_LL_EC_INPUT_TYPE Input type
214 * @{
215 */
216 #define LL_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
217 #define LL_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
218 /** @} */
219
220 /** @defgroup GPIO_LL_EC_TRIGGER Interrupt Trigger
221 * @{
222 */
223 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /*!< No Trigger Mode */
224 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /*!< Trigger Rising Mode */
225 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /*!< Trigger Falling Mode */
226 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /*!< Trigger High Mode */
227 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /*!< Trigger Low Mode */
228 #define LL_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /*!< Trigger Both Rising and Falling Mode */
229
230 /** @} */
231
232 /** @defgroup GPIO_LL_REG_ADDR Address of GPIOx Registers
233 * @attention x=0/1/2
234 * @{
235 */
236 #define GPIO_DATA_ADDR(x) (GPIO##x##_BASE+0x00) /*!< GPIOx_DATA_ADDR */
237 #define GPIO_DATAOUT_ADDR(x) (GPIO##x##_BASE+0x04) /*!< GPIOx_DATAOUT_ADDR */
238 #define GPIO_OUTENSET_ADDR(x) (GPIO##x##_BASE+0x10) /*!< GPIOx_OUTENSET_ADDR */
239 #define GPIO_OUTENCLR_ADDR(x) (GPIO##x##_BASE+0x14) /*!< GPIOx_OUTENCLR_ADDR */
240 #define GPIO_ALTFUNCSET_ADDR(x) (GPIO##x##_BASE+0x18) /*!< GPIOx_ALTFUNCSET_ADDR */
241 #define GPIO_ALTFUNCCLR_ADDR(x) (GPIO##x##_BASE+0x1c) /*!< GPIOx_ALTFUNCCLR_ADDR */
242 #define GPIO_INTENSET_ADDR(x) (GPIO##x##_BASE+0x20) /*!< GPIOx_INTENSET_ADDR */
243 #define GPIO_INTENCLR_ADDR(x) (GPIO##x##_BASE+0x24) /*!< GPIOx_INTENCLR_ADDR */
244 #define GPIO_INTTYPESET_ADDR(x) (GPIO##x##_BASE+0x28) /*!< GPIOx_INTTYPESET_ADDR */
245 #define GPIO_INTTYPECLR_ADDR(x) (GPIO##x##_BASE+0x2c) /*!< GPIOx_INTTYPECLR_ADDR */
246 #define GPIO_INTPOLSET_ADDR(x) (GPIO##x##_BASE+0x30) /*!< GPIOx_INTPOLSET_ADDR */
247 #define GPIO_INTPOLCLR_ADDR(x) (GPIO##x##_BASE+0x34) /*!< GPIOx_INTPOLCLR_ADDR */
248 #define GPIO_INTSTAT_ADDR(x) (GPIO##x##_BASE+0x38) /*!< GPIOx_INTSTAT_ADDR */
249 #define GPIO_INTDBESET_ADDR(x) (GPIO##x##_BASE+0x40) /*!< GPIOx_INTDBESET_ADDR */
250 #define GPIO_INTDBECLR_ADDR(x) (GPIO##x##_BASE+0x44) /*!< GPIOx_INTDBECLR_ADDR */
251 /** @} */
252
253 /** @defgroup GPIO_LL_BITBAND_SET Set nth bit for GPIOx register 0 or 1
254 * @attention x=0/1/2,0<=n<=31
255 * @{
256 */
257 #define SET_GPIO_DATA(x,n) BIT_ADDR(GPIO_DATA_ADDR(x),n) /*!< BITBAND GPIOx_DATA_ADDR */
258 #define SET_GPIO_DATAOUT(x,n) BIT_ADDR(GPIO_DATAOUT_ADDR(x),n) /*!< BITBAND GPIOx_DATAOUT_ADDR */
259 #define SET_GPIO_OUTENSET(x,n) BIT_ADDR(GPIO_OUTENSET_ADDR(x),n) /*!< BITBAND GPIOx_OUTENSET_ADDR */
260 #define SET_GPIO_OUTENCLR(x,n) BIT_ADDR(GPIO_OUTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_OUTENCLR_ADDR */
261 #define SET_GPIO_ALTFUNCSET(x,n) BIT_ADDR(GPIO_ALTFUNCSET_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCSET_ADDR */
262 #define SET_GPIO_ALTFUNCCLR(x,n) BIT_ADDR(GPIO_ALTFUNCCLR_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCCLR_ADDR */
263 #define SET_GPIO_INTENSET(x,n) BIT_ADDR(GPIO_INTENSET_ADDR(x),n) /*!< BITBAND GPIOx_INTENSET_ADDR */
264 #define SET_GPIO_INTENCLR(x,n) BIT_ADDR(GPIO_INTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTENCLR_ADDR */
265 #define SET_GPIO_INTTYPESET(x,n) BIT_ADDR(GPIO_INTTYPESET_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPESET_ADDR */
266 #define SET_GPIO_INTTYPECLR(x,n) BIT_ADDR(GPIO_INTTYPECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPECLR_ADDR */
267 #define SET_GPIO_INTPOLSET(x,n) BIT_ADDR(GPIO_INTPOLSET_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLSET_ADDR */
268 #define SET_GPIO_INTPOLCLR(x,n) BIT_ADDR(GPIO_INTPOLCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLCLR_ADDR */
269 #define SET_GPIO_INTSTAT(x,n) BIT_ADDR(GPIO_INTSTAT_ADDR(x),n) /*!< BITBAND GPIOx_INTSTAT_ADDR */
270 #define SET_GPIO_INTDBESET(x,n) BIT_ADDR(GPIO_INTDBESET_ADDR(x),n) /*!< BITBAND GPIOx_INTDBESET_ADDR */
271 #define SET_GPIO_INTDBECLR(x,n) BIT_ADDR(GPIO_INTDBECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTDBECLR_ADDR */
272 /** @} */
273
274 /** @defgroup GPIO_LL_EC_DEFAULT_CONFIG InitStrcut default configuration
275 * @{
276 */
277
278 /**
279 * @brief LL GPIO InitStrcut default configuration
280 */
281 #define LL_GPIO_DEFAULT_CONFIG \
282 { \
283 .pin = LL_GPIO_PIN_ALL, \
284 .mode = LL_GPIO_MODE_INPUT, \
285 .pull = LL_GPIO_PULL_DOWN, \
286 .mux = LL_GPIO_MUX_8, \
287 .speed = LL_GPIO_SPEED_MEDIUM, \
288 .strength = LL_GPIO_STRENGTH_MEDIUM, \
289 .input_type = LL_GPIO_INPUT_TYPE_CMOS, \
290 .trigger = LL_GPIO_TRIGGER_NONE, \
291 }
292 /** @} */
293
294 /** @} */
295
296 /* Exported macro ------------------------------------------------------------*/
297 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
298 * @{
299 */
300
301 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
302 * @{
303 */
304
305 /**
306 * @brief Write a value in GPIO register
307 * @param __instance__ GPIO instance
308 * @param __REG__ Register to be written
309 * @param __VALUE__ Value to be written in the register
310 * @retval None
311 */
312 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
313
314 /**
315 * @brief Read a value in GPIO register
316 * @param __instance__ GPIO instance
317 * @param __REG__ Register to be read
318 * @retval Register value
319 */
320 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
321
322 /** @} */
323
324 /** @} */
325
326 /* Private types -------------------------------------------------------------*/
327 /* Private variables ---------------------------------------------------------*/
328 /* Private constants ---------------------------------------------------------*/
329 /* Private macros ------------------------------------------------------------*/
330 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
331 * @{
332 */
333
334 /** @} */
335
336 /** @} */
337
338 /* Exported functions --------------------------------------------------------*/
339 /** @defgroup GPIO_LL_DRIVER_FUNCTIONS Functions
340 * @{
341 */
342
343 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
344 * @{
345 */
346
347 /**
348 * @brief Set several pins to input/output mode on dedicated port.
349 *
350 * Register|BitsName
351 * --------|--------
352 * OUTENSET | OUTENSET
353 * OUTENCLR | OUTENCLR
354 *
355 * @param GPIOx GPIO Port
356 * @param pin_mask This parameter can be a combination of the following values:
357 * @arg @ref LL_GPIO_PIN_0
358 * @arg @ref LL_GPIO_PIN_1
359 * @arg @ref LL_GPIO_PIN_2
360 * @arg @ref LL_GPIO_PIN_3
361 * @arg @ref LL_GPIO_PIN_4
362 * @arg @ref LL_GPIO_PIN_5
363 * @arg @ref LL_GPIO_PIN_6
364 * @arg @ref LL_GPIO_PIN_7
365 * @arg @ref LL_GPIO_PIN_8
366 * @arg @ref LL_GPIO_PIN_9
367 * @arg @ref LL_GPIO_PIN_10
368 * @arg @ref LL_GPIO_PIN_11
369 * @arg @ref LL_GPIO_PIN_12
370 * @arg @ref LL_GPIO_PIN_13
371 * @arg @ref LL_GPIO_PIN_14
372 * @arg @ref LL_GPIO_PIN_15
373 * @arg @ref LL_GPIO_PIN_ALL
374 * @param mode This parameter can be one of the following values:
375 * @arg @ref LL_GPIO_MODE_NONE
376 * @arg @ref LL_GPIO_MODE_INPUT
377 * @arg @ref LL_GPIO_MODE_OUTPUT
378 * @arg @ref LL_GPIO_MODE_INOUT
379 * @retval None
380 */
381 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
382 {
383 uint32_t oe_mask = (pin_mask << GPIO_OUTENSET_Pos) & GPIO_OUTENSET;
384 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
385 uint32_t ie_mask = (pin_mask << MCU_PAD_DPAD_IE_POS) & MCU_PAD_DPAD_IE;
386 uint32_t ie = ((mode == LL_GPIO_MODE_INPUT) || (mode == LL_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
387 uint32_t oe = ((mode == LL_GPIO_MODE_OUTPUT) || (mode == LL_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
388 WRITE_REG(GPIOx->OUTENCLR, oe_mask);
389 WRITE_REG(GPIOx->OUTENSET, oe);
390 if(GPIO2 == GPIOx)
391 {
392 MODIFY_REG(MCU_RET->DPAD_IE_BUS_1, ie_mask, ie);
393 }
394 else
395 {
396 MODIFY_REG(MCU_RET->DPAD_IE_BUS_0, ie_mask, ie);
397 }
398 }
399
400 /**
401 * @brief Return gpio mode for a dedicated pin on dedicated port.
402 * @note I/O mode can be Input mode, General purpose output.
403 * @note Warning: only one pin can be passed as parameter.
404 *
405 * Register|BitsName
406 * --------|--------
407 * OUTENSET | OUTENSET
408 *
409 * @param GPIOx GPIO Port
410 * @param pin This parameter can be one of the following values:
411 * @arg @ref LL_GPIO_PIN_0
412 * @arg @ref LL_GPIO_PIN_1
413 * @arg @ref LL_GPIO_PIN_2
414 * @arg @ref LL_GPIO_PIN_3
415 * @arg @ref LL_GPIO_PIN_4
416 * @arg @ref LL_GPIO_PIN_5
417 * @arg @ref LL_GPIO_PIN_6
418 * @arg @ref LL_GPIO_PIN_7
419 * @arg @ref LL_GPIO_PIN_8
420 * @arg @ref LL_GPIO_PIN_9
421 * @arg @ref LL_GPIO_PIN_10
422 * @arg @ref LL_GPIO_PIN_11
423 * @arg @ref LL_GPIO_PIN_12
424 * @arg @ref LL_GPIO_PIN_13
425 * @arg @ref LL_GPIO_PIN_14
426 * @arg @ref LL_GPIO_PIN_15
427 * @retval Returned value can be one of the following values:
428 * @arg @ref LL_GPIO_MODE_NONE
429 * @arg @ref LL_GPIO_MODE_INPUT
430 * @arg @ref LL_GPIO_MODE_OUTPUT
431 * @arg @ref LL_GPIO_MODE_INOUT
432 */
433 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
434 {
435 /* IE_SET OE_SET
436 LL_GPIO_MODE_NONE 0 0
437 LL_GPIO_MODE_INPUT 1 0
438 LL_GPIO_MODE_OUTPUT 0 1
439 LL_GPIO_MODE_INOUT 1 1
440 */
441 #define IE_SET ((uint32_t)0x1U) /**< GPIO INPUT ENABLE */
442 #define OE_SET ((uint32_t)0x2U) /**< GPIO OUTPUT ENABLE */
443
444 uint32_t pin_raw = pin;
445 pin <<= ((GPIOx == GPIO1) ? 16 : 0);
446 uint32_t ie_mask = (pin << MCU_PAD_DPAD_IE_POS) & MCU_PAD_DPAD_IE;
447 uint32_t oe_mask = (pin_raw << GPIO_OUTENSET_Pos) & GPIO_OUTENSET;
448 uint32_t ie, oe;
449 if(GPIO2 == GPIOx)
450 {
451 ie = READ_BITS(MCU_RET->DPAD_IE_BUS_1, ie_mask) >> (POSITION_VAL(pin));
452 oe = READ_BITS(GPIOx->OUTENSET, oe_mask) >> (POSITION_VAL(pin_raw));
453 }
454 else
455 {
456 ie = READ_BITS(MCU_RET->DPAD_IE_BUS_0, ie_mask) >> (POSITION_VAL(pin));
457 oe = READ_BITS(GPIOx->OUTENSET, oe_mask) >> (POSITION_VAL(pin_raw));
458 }
459
460 switch (ie | (oe << 1))
461 {
462 case IE_SET:
463 return LL_GPIO_MODE_INPUT;
464 case OE_SET:
465 return LL_GPIO_MODE_OUTPUT;
466 case IE_SET | OE_SET:
467 return LL_GPIO_MODE_INOUT;
468 default:
469 return LL_GPIO_MODE_NONE;
470 }
471 }
472
473 /**
474 * @brief Set several pins input type on dedicated port.
475 *
476 * Register|BitsName
477 * --------|--------
478 * OUTENSET | OUTENSET
479 * OUTENCLR | OUTENCLR
480 *
481 * @param GPIOx GPIO Port
482 * @param pin_mask This parameter can be a combination of the following values:
483 * @arg @ref LL_GPIO_PIN_0
484 * @arg @ref LL_GPIO_PIN_1
485 * @arg @ref LL_GPIO_PIN_2
486 * @arg @ref LL_GPIO_PIN_3
487 * @arg @ref LL_GPIO_PIN_4
488 * @arg @ref LL_GPIO_PIN_5
489 * @arg @ref LL_GPIO_PIN_6
490 * @arg @ref LL_GPIO_PIN_7
491 * @arg @ref LL_GPIO_PIN_8
492 * @arg @ref LL_GPIO_PIN_9
493 * @arg @ref LL_GPIO_PIN_10
494 * @arg @ref LL_GPIO_PIN_11
495 * @arg @ref LL_GPIO_PIN_12
496 * @arg @ref LL_GPIO_PIN_13
497 * @arg @ref LL_GPIO_PIN_14
498 * @arg @ref LL_GPIO_PIN_15
499 * @arg @ref LL_GPIO_PIN_ALL
500 * @param type This parameter can be one of the following values:
501 * @arg @ref LL_GPIO_INPUT_TYPE_CMOS
502 * @arg @ref LL_GPIO_INPUT_TYPE_SCHMITT
503 * @retval None
504 */
505 __STATIC_INLINE void ll_gpio_set_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t type)
506 {
507 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
508 if(GPIO2 == GPIOx)
509 {
510 MODIFY_REG(MCU_RET->DPAD_IS_BUS_1, pin_mask, (type == LL_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
511 }
512 else
513 {
514 MODIFY_REG(MCU_RET->DPAD_IS_BUS_0, pin_mask, (type == LL_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
515 }
516 }
517
518 /**
519 * @brief Return gpio input type for a dedicated pin on dedicated port.
520 * @note I/O mode can be Input mode, General purpose output.
521 * @note Warning: only one pin can be passed as parameter.
522 *
523 * Register|BitsName
524 * --------|--------
525 * OUTENSET | OUTENSET
526 *
527 * @param GPIOx GPIO Port
528 * @param pin This parameter can be one of the following values:
529 * @arg @ref LL_GPIO_PIN_0
530 * @arg @ref LL_GPIO_PIN_1
531 * @arg @ref LL_GPIO_PIN_2
532 * @arg @ref LL_GPIO_PIN_3
533 * @arg @ref LL_GPIO_PIN_4
534 * @arg @ref LL_GPIO_PIN_5
535 * @arg @ref LL_GPIO_PIN_6
536 * @arg @ref LL_GPIO_PIN_7
537 * @arg @ref LL_GPIO_PIN_8
538 * @arg @ref LL_GPIO_PIN_9
539 * @arg @ref LL_GPIO_PIN_10
540 * @arg @ref LL_GPIO_PIN_11
541 * @arg @ref LL_GPIO_PIN_12
542 * @arg @ref LL_GPIO_PIN_13
543 * @arg @ref LL_GPIO_PIN_14
544 * @arg @ref LL_GPIO_PIN_15
545 * @retval Returned value can be one of the following values:
546 * @arg @ref LL_GPIO_INPUT_TYPE_CMOS
547 * @arg @ref LL_GPIO_INPUT_TYPE_SCHMITT
548 */
549 __STATIC_INLINE uint32_t ll_gpio_get_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin)
550 {
551 pin <<= ((GPIOx == GPIO1) ? 16 : 0);
552
553 if(GPIO2 == GPIOx)
554 {
555 return ((uint32_t)(READ_BITS(MCU_RET->DPAD_IS_BUS_1, pin) == pin) ?
556 LL_GPIO_INPUT_TYPE_SCHMITT : LL_GPIO_INPUT_TYPE_CMOS);
557 }
558 else
559 {
560 return ((uint32_t)(READ_BITS(MCU_RET->DPAD_IS_BUS_0, pin) == pin) ?
561 LL_GPIO_INPUT_TYPE_SCHMITT : LL_GPIO_INPUT_TYPE_CMOS);
562 }
563 }
564
565 /**
566 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
567 *
568 * Register|BitsName
569 * --------|--------
570 * DPAD_PE_BUS | PE
571 * DPAD_PS_BUS | PS
572 *
573 * @param GPIOx GPIO Port
574 * @param pin_mask This parameter can be a combination of the following values:
575 * @arg @ref LL_GPIO_PIN_0
576 * @arg @ref LL_GPIO_PIN_1
577 * @arg @ref LL_GPIO_PIN_2
578 * @arg @ref LL_GPIO_PIN_3
579 * @arg @ref LL_GPIO_PIN_4
580 * @arg @ref LL_GPIO_PIN_5
581 * @arg @ref LL_GPIO_PIN_6
582 * @arg @ref LL_GPIO_PIN_7
583 * @arg @ref LL_GPIO_PIN_8
584 * @arg @ref LL_GPIO_PIN_9
585 * @arg @ref LL_GPIO_PIN_10
586 * @arg @ref LL_GPIO_PIN_11
587 * @arg @ref LL_GPIO_PIN_12
588 * @arg @ref LL_GPIO_PIN_13
589 * @arg @ref LL_GPIO_PIN_14
590 * @arg @ref LL_GPIO_PIN_15
591 * @param pull This parameter can be one of the following values:
592 * @arg @ref LL_GPIO_PULL_NO
593 * @arg @ref LL_GPIO_PULL_UP
594 * @arg @ref LL_GPIO_PULL_DOWN
595 * @retval None
596 */
597 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
598 {
599 /* Get pin mask in resistor related registers, GPIO0:0~15, GPIO1:16~31 */
600 if(GPIO2 == GPIOx)
601 {
602 MODIFY_REG(MCU_RET->DPAD_PS_BUS_1, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
603 MODIFY_REG(MCU_RET->DPAD_PE_BUS_1, pin_mask, (pull == LL_GPIO_PULL_NO) ? 0x0000U : pin_mask);
604 }
605 else
606 {
607 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
608 MODIFY_REG(MCU_RET->DPAD_PS_BUS_0, pin_mask, ((pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U));
609 MODIFY_REG(MCU_RET->DPAD_PE_BUS_0, pin_mask, ((pull == LL_GPIO_PULL_NO) ? 0x0000U : pin_mask));
610 }
611 }
612
613 /**
614 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
615 * @note Warning: only one pin can be passed as parameter.
616 *
617 * Register|BitsName
618 * --------|--------
619 * DPAD_PE_BUS | PE
620 * DPAD_PS_BUS | PS
621 *
622 * @param GPIOx GPIO Port
623 * @param pin This parameter can be one of the following values:
624 * @arg @ref LL_GPIO_PIN_0
625 * @arg @ref LL_GPIO_PIN_1
626 * @arg @ref LL_GPIO_PIN_2
627 * @arg @ref LL_GPIO_PIN_3
628 * @arg @ref LL_GPIO_PIN_4
629 * @arg @ref LL_GPIO_PIN_5
630 * @arg @ref LL_GPIO_PIN_6
631 * @arg @ref LL_GPIO_PIN_7
632 * @arg @ref LL_GPIO_PIN_8
633 * @arg @ref LL_GPIO_PIN_9
634 * @arg @ref LL_GPIO_PIN_10
635 * @arg @ref LL_GPIO_PIN_11
636 * @arg @ref LL_GPIO_PIN_12
637 * @arg @ref LL_GPIO_PIN_13
638 * @arg @ref LL_GPIO_PIN_14
639 * @arg @ref LL_GPIO_PIN_15
640 * @retval Returned value can be one of the following values:
641 * @arg @ref LL_GPIO_PULL_NO
642 * @arg @ref LL_GPIO_PULL_UP
643 * @arg @ref LL_GPIO_PULL_DOWN
644 */
645 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
646 {
647 /* Get pin position in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
648 if(GPIO2 == GPIOx)
649 {
650 return ((READ_BITS(MCU_RET->DPAD_PE_BUS_1, pin) == RESET) ? LL_GPIO_PULL_NO :
651 ((READ_BITS(MCU_RET->DPAD_PS_BUS_1, pin) == RESET) ? LL_GPIO_PULL_DOWN : LL_GPIO_PULL_UP));
652 }
653 else
654 {
655 pin <<= ((GPIOx == GPIO1) ? 16 : 0);
656 return ((READ_BITS(MCU_RET->DPAD_PE_BUS_0, pin) == RESET) ? LL_GPIO_PULL_NO :
657 ((READ_BITS(MCU_RET->DPAD_PS_BUS_0, pin) == RESET) ? LL_GPIO_PULL_DOWN : LL_GPIO_PULL_UP));
658 }
659 }
660
661 /**
662 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
663 * @note Possible values are from AF0 to AF15 depending on target.
664 * @note Warning: only one pin can be passed as parameter.
665 *
666 * Register|BitsName
667 * --------|--------
668 * DPAD_MUX_CTRL0_7 | CTRL0_7
669 * DPAD_MUX_CTRL16_23 | CTRL16_23
670 *
671 * @param GPIOx GPIO Port
672 * @param pin This parameter can be one of the following values:
673 * @arg @ref LL_GPIO_PIN_0
674 * @arg @ref LL_GPIO_PIN_1
675 * @arg @ref LL_GPIO_PIN_2
676 * @arg @ref LL_GPIO_PIN_3
677 * @arg @ref LL_GPIO_PIN_4
678 * @arg @ref LL_GPIO_PIN_5
679 * @arg @ref LL_GPIO_PIN_6
680 * @arg @ref LL_GPIO_PIN_7
681 * @arg @ref LL_GPIO_PIN_8
682 * @arg @ref LL_GPIO_PIN_9
683 * @arg @ref LL_GPIO_PIN_10
684 * @arg @ref LL_GPIO_PIN_11
685 * @arg @ref LL_GPIO_PIN_12
686 * @arg @ref LL_GPIO_PIN_13
687 * @arg @ref LL_GPIO_PIN_14
688 * @arg @ref LL_GPIO_PIN_15
689 * @param mux This parameter can be one of the following values:
690 * @arg @ref LL_GPIO_MUX_0
691 * @arg @ref LL_GPIO_MUX_1
692 * @arg @ref LL_GPIO_MUX_2
693 * @arg @ref LL_GPIO_MUX_3
694 * @arg @ref LL_GPIO_MUX_4
695 * @arg @ref LL_GPIO_MUX_5
696 * @arg @ref LL_GPIO_MUX_6
697 * @arg @ref LL_GPIO_MUX_7
698 * @arg @ref LL_GPIO_MUX_8
699 * @retval None
700 */
701 __STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
702 {
703 volatile uint32_t* GPIO_MUX_REG_BASE = &(MCU_RET->DPAD_MUX_CTL_00_07);
704 uint8_t offset;
705 uint32_t pos;
706
707 pin = POSITION_VAL(pin);
708 pos = (pin & 7) << 2; /* pos = (pin % 8) * 4 */
709
710 if(GPIO0 == GPIOx)
711 {
712 offset = pin >> 3; /* offset = pin / 8 */
713 }
714 else if(GPIO1 == GPIOx)
715 {
716 offset = (pin >> 3) + 2; /* offset = pin / 8 + 2*/
717 }
718 else //GPIO2
719 {
720 offset = 4; /* DPAD_MUX_CTL_32_39 - DPAD_MUX_CTL_00_07 */
721 }
722
723 MODIFY_REG(*(GPIO_MUX_REG_BASE + offset), 0xF << pos, mux << pos);
724 }
725
726 /**
727 * @brief Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
728 * @note Possible values are from AF0 to AF15 depending on target.
729 *
730 * Register|BitsName
731 * --------|--------
732 * DPAD_MUX_CTRL8_15 | CTRL8_15
733 * DPAD_MUX_CTRL24_31 | CTRL24_31
734 *
735 * @param GPIOx GPIO Port
736 * @param pin This parameter can be one of the following values:
737 * @arg @ref LL_GPIO_PIN_0
738 * @arg @ref LL_GPIO_PIN_1
739 * @arg @ref LL_GPIO_PIN_2
740 * @arg @ref LL_GPIO_PIN_3
741 * @arg @ref LL_GPIO_PIN_4
742 * @arg @ref LL_GPIO_PIN_5
743 * @arg @ref LL_GPIO_PIN_6
744 * @arg @ref LL_GPIO_PIN_7
745 * @arg @ref LL_GPIO_PIN_8
746 * @arg @ref LL_GPIO_PIN_9
747 * @arg @ref LL_GPIO_PIN_10
748 * @arg @ref LL_GPIO_PIN_11
749 * @arg @ref LL_GPIO_PIN_12
750 * @arg @ref LL_GPIO_PIN_13
751 * @arg @ref LL_GPIO_PIN_14
752 * @arg @ref LL_GPIO_PIN_15
753 * @retval Returned value can be one of the following values:
754 * @arg @ref LL_GPIO_MUX_0
755 * @arg @ref LL_GPIO_MUX_1
756 * @arg @ref LL_GPIO_MUX_2
757 * @arg @ref LL_GPIO_MUX_3
758 * @arg @ref LL_GPIO_MUX_4
759 * @arg @ref LL_GPIO_MUX_5
760 * @arg @ref LL_GPIO_MUX_6
761 * @arg @ref LL_GPIO_MUX_7
762 * @arg @ref LL_GPIO_MUX_8
763 */
764 __STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
765 {
766 uint32_t pos = POSITION_VAL(pin) << 2;
767 if(GPIO0 == GPIOx)
768 {
769 if(pin < LL_GPIO_PIN_8)
770 {
771 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_00_07, 0xF << pos) >> pos);
772 }
773 else
774 {
775 pos = POSITION_VAL(pin >> 8) << 2;
776 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_08_15, 0xF << pos) >> pos);
777 }
778 }
779 else if(GPIO1 == GPIOx)
780 {
781 if(pin < LL_GPIO_PIN_8)
782 {
783 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_16_23, 0xF << pos) >> pos);
784 }
785 else
786 {
787 pos = POSITION_VAL(pin >> 8) << 2;
788 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_24_31, 0xF << pos) >> pos);
789 }
790 }
791 else
792 {
793 if(pin < LL_GPIO_PIN_8)
794 {
795 return (READ_BITS(MCU_RET->DPAD_MUX_CTL_32_39, 0xF << pos) >> pos);
796 }
797 }
798 return 0;
799 }
800
801 /**
802 * @brief Configure gpio speed for a dedicated pin on a dedicated port.
803 *
804 * Register|BitsName
805 * --------|--------
806 * MCU_RET | DPAD_SR_BUS
807 * MCU_RET | DPAD_SR_BUS
808 *
809 * @param GPIOx GPIO Port
810 * @param pin_mask This parameter can be a combination of the following values:
811 * @arg @ref LL_GPIO_PIN_0
812 * @arg @ref LL_GPIO_PIN_1
813 * @arg @ref LL_GPIO_PIN_2
814 * @arg @ref LL_GPIO_PIN_3
815 * @arg @ref LL_GPIO_PIN_4
816 * @arg @ref LL_GPIO_PIN_5
817 * @arg @ref LL_GPIO_PIN_6
818 * @arg @ref LL_GPIO_PIN_7
819 * @arg @ref LL_GPIO_PIN_8
820 * @arg @ref LL_GPIO_PIN_9
821 * @arg @ref LL_GPIO_PIN_10
822 * @arg @ref LL_GPIO_PIN_11
823 * @arg @ref LL_GPIO_PIN_12
824 * @arg @ref LL_GPIO_PIN_13
825 * @arg @ref LL_GPIO_PIN_14
826 * @arg @ref LL_GPIO_PIN_15
827 * @param speed This parameter can be one of the following values:
828 * @arg @ref LL_GPIO_SPEED_MEDIUM
829 * @arg @ref LL_GPIO_SPEED_HIGH
830 * @retval None
831 */
832 __STATIC_INLINE void ll_gpio_set_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t speed)
833 {
834 uint32_t pos;
835 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
836 pos = POSITION_VAL(pin_mask);
837 if(GPIO2 == GPIOx)
838 {
839 MODIFY_REG(MCU_RET->DPAD_SR_BUS_1, pin_mask << MCU_PAD_DPAD_SR_POS, speed << pos << MCU_PAD_DPAD_SR_POS);
840 }
841 else
842 {
843 MODIFY_REG(MCU_RET->DPAD_SR_BUS_0, pin_mask << MCU_PAD_DPAD_SR_POS, speed << pos << MCU_PAD_DPAD_SR_POS);
844 }
845 }
846
847 /**
848 * @brief Return gpio speed for a dedicated pin on a dedicated port
849 * @note Warning: only one pin can be passed as parameter.
850 *
851 * Register|BitsName
852 * --------|--------
853 * MCU_RET | DPAD_SR_BUS
854 * MCU_RET | DPAD_SR_BUS
855 *
856 * @param GPIOx GPIO Port
857 * @param pin_mask This parameter can be one of the following values:
858 * @arg @ref LL_GPIO_PIN_0
859 * @arg @ref LL_GPIO_PIN_1
860 * @arg @ref LL_GPIO_PIN_2
861 * @arg @ref LL_GPIO_PIN_3
862 * @arg @ref LL_GPIO_PIN_4
863 * @arg @ref LL_GPIO_PIN_5
864 * @arg @ref LL_GPIO_PIN_6
865 * @arg @ref LL_GPIO_PIN_7
866 * @arg @ref LL_GPIO_PIN_8
867 * @arg @ref LL_GPIO_PIN_9
868 * @arg @ref LL_GPIO_PIN_10
869 * @arg @ref LL_GPIO_PIN_11
870 * @arg @ref LL_GPIO_PIN_12
871 * @arg @ref LL_GPIO_PIN_13
872 * @arg @ref LL_GPIO_PIN_14
873 * @arg @ref LL_GPIO_PIN_15
874 * @retval Returned value can be one of the following values:
875 * @arg @ref LL_GPIO_SPEED_MEDIUM
876 * @arg @ref LL_GPIO_SPEED_HIGH
877 */
878 __STATIC_INLINE uint32_t ll_gpio_get_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask)
879 {
880 uint32_t pos;
881 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
882 pos = POSITION_VAL(pin_mask);
883 if(GPIO2 == GPIOx)
884 {
885 return (READ_BITS(MCU_RET->DPAD_SR_BUS_1, pin_mask << MCU_PAD_DPAD_SR_POS ) >> pos >> MCU_PAD_DPAD_SR_POS);
886 }
887 else
888 {
889 return (READ_BITS(MCU_RET->DPAD_SR_BUS_0, pin_mask << MCU_PAD_DPAD_SR_POS ) >> pos >> MCU_PAD_DPAD_SR_POS);
890 }
891 }
892
893 /**
894 * @brief Configure gpio output drive strength for a dedicated pin on a dedicated port.
895 *
896 * Register|BitsName
897 * --------|--------
898 * MCU_RET | DPAD_DS0_BUS
899 * MCU_RET | DPAD_DS1_BUS
900 *
901 * @param GPIOx GPIO Port
902 * @param pin_mask This parameter can be a combination of the following values:
903 * @arg @ref LL_GPIO_PIN_0
904 * @arg @ref LL_GPIO_PIN_1
905 * @arg @ref LL_GPIO_PIN_2
906 * @arg @ref LL_GPIO_PIN_3
907 * @arg @ref LL_GPIO_PIN_4
908 * @arg @ref LL_GPIO_PIN_5
909 * @arg @ref LL_GPIO_PIN_6
910 * @arg @ref LL_GPIO_PIN_7
911 * @arg @ref LL_GPIO_PIN_8
912 * @arg @ref LL_GPIO_PIN_9
913 * @arg @ref LL_GPIO_PIN_10
914 * @arg @ref LL_GPIO_PIN_11
915 * @arg @ref LL_GPIO_PIN_12
916 * @arg @ref LL_GPIO_PIN_13
917 * @arg @ref LL_GPIO_PIN_14
918 * @arg @ref LL_GPIO_PIN_15
919 * @param strength This parameter can be one of the following values:
920 * @arg @ref LL_GPIO_STRENGTH_LOW
921 * @arg @ref LL_GPIO_STRENGTH_MEDIUM
922 * @arg @ref LL_GPIO_STRENGTH_HIGH
923 * @arg @ref LL_GPIO_STRENGTH_ULTRA
924 * @retval None
925 */
926 __STATIC_INLINE void ll_gpio_set_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t strength)
927 {
928 uint32_t pos;
929 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
930 pos = POSITION_VAL(pin_mask);
931 uint8_t ds0 = (strength & LL_GPIO_STRENGTH_DS0_MASK) >> LL_GPIO_STRENGTH_DS0_POS;
932 uint8_t ds1 = (strength & LL_GPIO_STRENGTH_DS1_MASK) >> LL_GPIO_STRENGTH_DS1_POS;
933
934 if(GPIO2 == GPIOx)
935 {
936 MODIFY_REG(MCU_RET->DPAD_DS0_BUS_1, pin_mask << MCU_PAD_DPAD_DS0_POS , ds0 << pos << MCU_PAD_DPAD_DS0_POS);
937 MODIFY_REG(MCU_RET->DPAD_DS1_BUS_1, pin_mask << MCU_PAD_DPAD_DS1_POS , ds1 << pos << MCU_PAD_DPAD_DS1_POS);
938 }
939 else
940 {
941 MODIFY_REG(MCU_RET->DPAD_DS0_BUS_0, pin_mask << MCU_PAD_DPAD_DS0_POS , ds0 << pos << MCU_PAD_DPAD_DS0_POS);
942 MODIFY_REG(MCU_RET->DPAD_DS1_BUS_0, pin_mask << MCU_PAD_DPAD_DS1_POS , ds1 << pos << MCU_PAD_DPAD_DS1_POS);
943 }
944 }
945
946 /**
947 * @brief Return gpio output drive strength for a dedicated pin on a dedicated port
948 * @note Warning: only one pin can be passed as parameter.
949 *
950 * Register|BitsName
951 * --------|--------
952 * MCU_RET | DPAD_DS0_BUS
953 * MCU_RET | DPAD_DS1_BUS
954 *
955 * @param GPIOx GPIO Port
956 * @param pin_mask This parameter can be one of the following values:
957 * @arg @ref LL_GPIO_PIN_0
958 * @arg @ref LL_GPIO_PIN_1
959 * @arg @ref LL_GPIO_PIN_2
960 * @arg @ref LL_GPIO_PIN_3
961 * @arg @ref LL_GPIO_PIN_4
962 * @arg @ref LL_GPIO_PIN_5
963 * @arg @ref LL_GPIO_PIN_6
964 * @arg @ref LL_GPIO_PIN_7
965 * @arg @ref LL_GPIO_PIN_8
966 * @arg @ref LL_GPIO_PIN_9
967 * @arg @ref LL_GPIO_PIN_10
968 * @arg @ref LL_GPIO_PIN_11
969 * @arg @ref LL_GPIO_PIN_12
970 * @arg @ref LL_GPIO_PIN_13
971 * @arg @ref LL_GPIO_PIN_14
972 * @arg @ref LL_GPIO_PIN_15
973 * @retval Returned value can be one of the following values:
974 * @arg @ref LL_GPIO_STRENGTH_LOW
975 * @arg @ref LL_GPIO_STRENGTH_MEDIUM
976 * @arg @ref LL_GPIO_STRENGTH_HIGH
977 * @arg @ref LL_GPIO_STRENGTH_ULTRA
978 */
979 __STATIC_INLINE uint32_t ll_gpio_get_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask)
980 {
981 uint32_t pos;
982 pin_mask <<= ((GPIOx == GPIO1) ? 16 : 0);
983 pos = POSITION_VAL(pin_mask);
984 uint8_t ds0, ds1;
985 if(GPIO2 == GPIOx)
986 {
987 ds0 = READ_BITS(MCU_RET->DPAD_DS0_BUS_1, pin_mask << MCU_PAD_DPAD_DS0_POS ) >> MCU_PAD_DPAD_DS0_POS >> pos;
988 ds1 = READ_BITS(MCU_RET->DPAD_DS1_BUS_1, pin_mask << MCU_PAD_DPAD_DS1_POS ) >> MCU_PAD_DPAD_DS1_POS>> pos;
989 }
990 else
991 {
992 ds0 = READ_BITS(MCU_RET->DPAD_DS0_BUS_0, pin_mask << MCU_PAD_DPAD_DS0_POS ) >> MCU_PAD_DPAD_DS0_POS >> pos;
993 ds1 = READ_BITS(MCU_RET->DPAD_DS1_BUS_0, pin_mask << MCU_PAD_DPAD_DS1_POS ) >> MCU_PAD_DPAD_DS1_POS>> pos;
994 }
995 return ((ds0 << LL_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_GPIO_STRENGTH_DS1_POS));
996 }
997 /** @} */
998
999 /** @defgroup GPIO_LL_EF_Data_Access Data Access
1000 * @{
1001 */
1002
1003 /**
1004 * @brief Return full input data register value for a dedicated port.
1005 *
1006 * Register|BitsName
1007 * --------|--------
1008 * DATA | DATA
1009 *
1010 * @param GPIOx GPIO Port
1011 * @retval Input data register value of port
1012 */
1013 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
1014 {
1015 return (uint32_t)(READ_REG(GPIOx->DATA));
1016 }
1017
1018 /**
1019 * @brief Return if input data level for several pins of dedicated port is high or low.
1020 *
1021 * Register|BitsName
1022 * --------|--------
1023 * DATA | DATA
1024 *
1025 * @param GPIOx GPIO Port
1026 * @param pin_mask This parameter can be a combination of the following values:
1027 * @arg @ref LL_GPIO_PIN_0
1028 * @arg @ref LL_GPIO_PIN_1
1029 * @arg @ref LL_GPIO_PIN_2
1030 * @arg @ref LL_GPIO_PIN_3
1031 * @arg @ref LL_GPIO_PIN_4
1032 * @arg @ref LL_GPIO_PIN_5
1033 * @arg @ref LL_GPIO_PIN_6
1034 * @arg @ref LL_GPIO_PIN_7
1035 * @arg @ref LL_GPIO_PIN_8
1036 * @arg @ref LL_GPIO_PIN_9
1037 * @arg @ref LL_GPIO_PIN_10
1038 * @arg @ref LL_GPIO_PIN_11
1039 * @arg @ref LL_GPIO_PIN_12
1040 * @arg @ref LL_GPIO_PIN_13
1041 * @arg @ref LL_GPIO_PIN_14
1042 * @arg @ref LL_GPIO_PIN_15
1043 * @arg @ref LL_GPIO_PIN_ALL
1044 * @retval State of bit (1 or 0).
1045 */
1046 __STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1047 {
1048 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
1049 }
1050
1051 /**
1052 * @brief Write output data register for the port.
1053 *
1054 * Register|BitsName
1055 * --------|--------
1056 * DATAOUT | DATAOUT
1057 *
1058 * @param GPIOx GPIO Port
1059 * @param port_value Level value for each pin of the port
1060 * @retval None
1061 */
1062 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
1063 {
1064 WRITE_REG(GPIOx->DATAOUT, port_value);
1065 }
1066
1067 /**
1068 * @brief Return full output data register value for a dedicated port.
1069 *
1070 * Register|BitsName
1071 * --------|--------
1072 * DATAOUT | DATAOUT
1073 *
1074 * @param GPIOx GPIO Port
1075 * @retval Output data register value of port
1076 */
1077 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
1078 {
1079 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
1080 }
1081
1082 /**
1083 * @brief Return if output data level for several pins of dedicated port is high or low.
1084 *
1085 * Register|BitsName
1086 * --------|--------
1087 * DATA | DATAOUT
1088 *
1089 * @param GPIOx GPIO Port
1090 * @param pin_mask This parameter can be a combination of the following values:
1091 * @arg @ref LL_GPIO_PIN_0
1092 * @arg @ref LL_GPIO_PIN_1
1093 * @arg @ref LL_GPIO_PIN_2
1094 * @arg @ref LL_GPIO_PIN_3
1095 * @arg @ref LL_GPIO_PIN_4
1096 * @arg @ref LL_GPIO_PIN_5
1097 * @arg @ref LL_GPIO_PIN_6
1098 * @arg @ref LL_GPIO_PIN_7
1099 * @arg @ref LL_GPIO_PIN_8
1100 * @arg @ref LL_GPIO_PIN_9
1101 * @arg @ref LL_GPIO_PIN_10
1102 * @arg @ref LL_GPIO_PIN_11
1103 * @arg @ref LL_GPIO_PIN_12
1104 * @arg @ref LL_GPIO_PIN_13
1105 * @arg @ref LL_GPIO_PIN_14
1106 * @arg @ref LL_GPIO_PIN_15
1107 * @arg @ref LL_GPIO_PIN_ALL
1108 * @retval State of bit (1 or 0).
1109 */
1110 __STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1111 {
1112 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
1113 }
1114
1115 /**
1116 * @brief Set several pins to high level on dedicated gpio port.
1117 *
1118 * Register|BitsName
1119 * --------|--------
1120 * DATAOUT | DATAOUT
1121 *
1122 * @param GPIOx GPIO Port
1123 * @param pin_mask This parameter can be a combination of the following values:
1124 * @arg @ref LL_GPIO_PIN_0
1125 * @arg @ref LL_GPIO_PIN_1
1126 * @arg @ref LL_GPIO_PIN_2
1127 * @arg @ref LL_GPIO_PIN_3
1128 * @arg @ref LL_GPIO_PIN_4
1129 * @arg @ref LL_GPIO_PIN_5
1130 * @arg @ref LL_GPIO_PIN_6
1131 * @arg @ref LL_GPIO_PIN_7
1132 * @arg @ref LL_GPIO_PIN_8
1133 * @arg @ref LL_GPIO_PIN_9
1134 * @arg @ref LL_GPIO_PIN_10
1135 * @arg @ref LL_GPIO_PIN_11
1136 * @arg @ref LL_GPIO_PIN_12
1137 * @arg @ref LL_GPIO_PIN_13
1138 * @arg @ref LL_GPIO_PIN_14
1139 * @arg @ref LL_GPIO_PIN_15
1140 * @arg @ref LL_GPIO_PIN_ALL
1141 * @retval None
1142 */
1143 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1144 {
1145 #ifdef USE_GPIO_MASK_REGISTER
1146 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
1147 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
1148 pin_mask & GPIO_MASKHIGHBYTE_DATA);
1149 #else
1150 SET_BITS(GPIOx->DATAOUT, pin_mask);
1151 #endif
1152 }
1153
1154 /**
1155 * @brief Set several pins to low level on dedicated gpio port.
1156 *
1157 * Register|BitsName
1158 * --------|--------
1159 * DATAOUT | DATAOUT
1160 *
1161 * @param GPIOx GPIO Port
1162 * @param pin_mask This parameter can be a combination of the following values:
1163 * @arg @ref LL_GPIO_PIN_0
1164 * @arg @ref LL_GPIO_PIN_1
1165 * @arg @ref LL_GPIO_PIN_2
1166 * @arg @ref LL_GPIO_PIN_3
1167 * @arg @ref LL_GPIO_PIN_4
1168 * @arg @ref LL_GPIO_PIN_5
1169 * @arg @ref LL_GPIO_PIN_6
1170 * @arg @ref LL_GPIO_PIN_7
1171 * @arg @ref LL_GPIO_PIN_8
1172 * @arg @ref LL_GPIO_PIN_9
1173 * @arg @ref LL_GPIO_PIN_10
1174 * @arg @ref LL_GPIO_PIN_11
1175 * @arg @ref LL_GPIO_PIN_12
1176 * @arg @ref LL_GPIO_PIN_13
1177 * @arg @ref LL_GPIO_PIN_14
1178 * @arg @ref LL_GPIO_PIN_15
1179 * @arg @ref LL_GPIO_PIN_ALL
1180 * @retval None
1181 */
1182 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1183 {
1184 #ifdef USE_GPIO_MASK_REGISTER
1185 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
1186 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
1187 #else
1188 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
1189 #endif
1190 }
1191
1192 /**
1193 * @brief Toggle data value for several pin of dedicated port.
1194 *
1195 * Register|BitsName
1196 * --------|--------
1197 * DATAOUT | DATAOUT
1198 *
1199 * @param GPIOx GPIO Port
1200 * @param pin_mask This parameter can be a combination of the following values:
1201 * @arg @ref LL_GPIO_PIN_0
1202 * @arg @ref LL_GPIO_PIN_1
1203 * @arg @ref LL_GPIO_PIN_2
1204 * @arg @ref LL_GPIO_PIN_3
1205 * @arg @ref LL_GPIO_PIN_4
1206 * @arg @ref LL_GPIO_PIN_5
1207 * @arg @ref LL_GPIO_PIN_6
1208 * @arg @ref LL_GPIO_PIN_7
1209 * @arg @ref LL_GPIO_PIN_8
1210 * @arg @ref LL_GPIO_PIN_9
1211 * @arg @ref LL_GPIO_PIN_10
1212 * @arg @ref LL_GPIO_PIN_11
1213 * @arg @ref LL_GPIO_PIN_12
1214 * @arg @ref LL_GPIO_PIN_13
1215 * @arg @ref LL_GPIO_PIN_14
1216 * @arg @ref LL_GPIO_PIN_15
1217 * @arg @ref LL_GPIO_PIN_ALL
1218 * @retval None
1219 */
1220 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1221 {
1222 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
1223 }
1224
1225 /** @} */
1226
1227 /** @defgroup GPIO_LL_EF_IT_Management IT_Management
1228 * @{
1229 */
1230
1231 /**
1232 * @brief Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
1233 * @note
1234 *
1235 * Register|BitsName
1236 * --------|--------
1237 * INTPOLCLR | INTPOLCLR
1238 * INTTYPESET | INTTYPESET
1239 *
1240 * @param GPIOx GPIO instance.
1241 * @param pin_mask This parameter can be a combination of the following values:
1242 * @arg @ref LL_GPIO_PIN_0
1243 * @arg @ref LL_GPIO_PIN_1
1244 * @arg @ref LL_GPIO_PIN_2
1245 * @arg @ref LL_GPIO_PIN_3
1246 * @arg @ref LL_GPIO_PIN_4
1247 * @arg @ref LL_GPIO_PIN_5
1248 * @arg @ref LL_GPIO_PIN_6
1249 * @arg @ref LL_GPIO_PIN_7
1250 * @arg @ref LL_GPIO_PIN_8
1251 * @arg @ref LL_GPIO_PIN_9
1252 * @arg @ref LL_GPIO_PIN_10
1253 * @arg @ref LL_GPIO_PIN_11
1254 * @arg @ref LL_GPIO_PIN_12
1255 * @arg @ref LL_GPIO_PIN_13
1256 * @arg @ref LL_GPIO_PIN_14
1257 * @arg @ref LL_GPIO_PIN_15
1258 * @arg @ref LL_GPIO_PIN_ALL
1259 * @retval None
1260 */
1261 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1262 {
1263 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1264 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1265 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
1266 }
1267
1268 /**
1269 * @brief Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
1270 * @note
1271 *
1272 * Register|BitsName
1273 * --------|--------
1274 * INTPOLSET | INTPOLSET
1275 * INTTYPESET | INTTYPESET
1276 *
1277 * @param GPIOx GPIO instance.
1278 * @param pin_mask This parameter can be a combination of the following values:
1279 * @arg @ref LL_GPIO_PIN_0
1280 * @arg @ref LL_GPIO_PIN_1
1281 * @arg @ref LL_GPIO_PIN_2
1282 * @arg @ref LL_GPIO_PIN_3
1283 * @arg @ref LL_GPIO_PIN_4
1284 * @arg @ref LL_GPIO_PIN_5
1285 * @arg @ref LL_GPIO_PIN_6
1286 * @arg @ref LL_GPIO_PIN_7
1287 * @arg @ref LL_GPIO_PIN_8
1288 * @arg @ref LL_GPIO_PIN_9
1289 * @arg @ref LL_GPIO_PIN_10
1290 * @arg @ref LL_GPIO_PIN_11
1291 * @arg @ref LL_GPIO_PIN_12
1292 * @arg @ref LL_GPIO_PIN_13
1293 * @arg @ref LL_GPIO_PIN_14
1294 * @arg @ref LL_GPIO_PIN_15
1295 * @arg @ref LL_GPIO_PIN_ALL
1296 * @retval None
1297 */
1298 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1299 {
1300 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1301 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1302 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
1303 }
1304
1305 /**
1306 * @brief Enable GPIO High Level Trigger for pins in the range of 0 to 15.
1307 * @note
1308 *
1309 * Register|BitsName
1310 * --------|--------
1311 * INTPOLSET | INTPOLSET
1312 * INTTYPECLR | INTTYPECLR
1313 *
1314 * @param GPIOx GPIO instance.
1315 * @param pin_mask This parameter can be a combination of the following values:
1316 * @arg @ref LL_GPIO_PIN_0
1317 * @arg @ref LL_GPIO_PIN_1
1318 * @arg @ref LL_GPIO_PIN_2
1319 * @arg @ref LL_GPIO_PIN_3
1320 * @arg @ref LL_GPIO_PIN_4
1321 * @arg @ref LL_GPIO_PIN_5
1322 * @arg @ref LL_GPIO_PIN_6
1323 * @arg @ref LL_GPIO_PIN_7
1324 * @arg @ref LL_GPIO_PIN_8
1325 * @arg @ref LL_GPIO_PIN_9
1326 * @arg @ref LL_GPIO_PIN_10
1327 * @arg @ref LL_GPIO_PIN_11
1328 * @arg @ref LL_GPIO_PIN_12
1329 * @arg @ref LL_GPIO_PIN_13
1330 * @arg @ref LL_GPIO_PIN_14
1331 * @arg @ref LL_GPIO_PIN_15
1332 * @arg @ref LL_GPIO_PIN_ALL
1333 * @retval None
1334 */
1335 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1336 {
1337 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1338 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1339 }
1340
1341 /**
1342 * @brief Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
1343 * @note
1344 *
1345 * Register|BitsName
1346 * --------|--------
1347 * INTPOLCLR | INTPOLCLR
1348 * INTTYPECLR | INTTYPECLR
1349 *
1350 * @param GPIOx GPIO instance.
1351 * @param pin_mask This parameter can be a combination of the following values:
1352 * @arg @ref LL_GPIO_PIN_0
1353 * @arg @ref LL_GPIO_PIN_1
1354 * @arg @ref LL_GPIO_PIN_2
1355 * @arg @ref LL_GPIO_PIN_3
1356 * @arg @ref LL_GPIO_PIN_4
1357 * @arg @ref LL_GPIO_PIN_5
1358 * @arg @ref LL_GPIO_PIN_6
1359 * @arg @ref LL_GPIO_PIN_7
1360 * @arg @ref LL_GPIO_PIN_8
1361 * @arg @ref LL_GPIO_PIN_9
1362 * @arg @ref LL_GPIO_PIN_10
1363 * @arg @ref LL_GPIO_PIN_11
1364 * @arg @ref LL_GPIO_PIN_12
1365 * @arg @ref LL_GPIO_PIN_13
1366 * @arg @ref LL_GPIO_PIN_14
1367 * @arg @ref LL_GPIO_PIN_15
1368 * @arg @ref LL_GPIO_PIN_ALL
1369 * @retval None
1370 */
1371 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1372 {
1373 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1374 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1375 }
1376
1377 /**
1378 * @brief Enable GPIO both edge Trigger for pins in the range of 0 to 15.
1379 * @note
1380 *
1381 * Register|BitsName
1382 * --------|--------
1383 * INTPOLCLR | INTPOLCLR
1384 * INTTYPESET | INTTYPESET
1385 * INTTYPESET | INTTYPESET
1386 *
1387 * @param GPIOx GPIO instance.
1388 * @param pin_mask This parameter can be a combination of the following values:
1389 * @arg @ref LL_GPIO_PIN_0
1390 * @arg @ref LL_GPIO_PIN_1
1391 * @arg @ref LL_GPIO_PIN_2
1392 * @arg @ref LL_GPIO_PIN_3
1393 * @arg @ref LL_GPIO_PIN_4
1394 * @arg @ref LL_GPIO_PIN_5
1395 * @arg @ref LL_GPIO_PIN_6
1396 * @arg @ref LL_GPIO_PIN_7
1397 * @arg @ref LL_GPIO_PIN_8
1398 * @arg @ref LL_GPIO_PIN_9
1399 * @arg @ref LL_GPIO_PIN_10
1400 * @arg @ref LL_GPIO_PIN_11
1401 * @arg @ref LL_GPIO_PIN_12
1402 * @arg @ref LL_GPIO_PIN_13
1403 * @arg @ref LL_GPIO_PIN_14
1404 * @arg @ref LL_GPIO_PIN_15
1405 * @arg @ref LL_GPIO_PIN_ALL
1406 * @retval None
1407 */
1408 __STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1409 {
1410 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1411 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1412 WRITE_REG(GPIOx->INTDBESET, pin_mask);
1413 }
1414
1415 /**
1416 * @brief Get trigger type for pins in the range of 0 to 15
1417 * @note
1418 *
1419 * Register|BitsName
1420 * --------|--------
1421 * INTPOLCLR | INTPOLCLR
1422 * INTTYPECLR | INTTYPECLR
1423 * INTTYPESET | INTTYPESET
1424 *
1425 * @param GPIOx GPIO instance.
1426 * @param pin_mask This parameter can be a combination of the following values:
1427 * @arg @ref LL_GPIO_PIN_0
1428 * @arg @ref LL_GPIO_PIN_1
1429 * @arg @ref LL_GPIO_PIN_2
1430 * @arg @ref LL_GPIO_PIN_3
1431 * @arg @ref LL_GPIO_PIN_4
1432 * @arg @ref LL_GPIO_PIN_5
1433 * @arg @ref LL_GPIO_PIN_6
1434 * @arg @ref LL_GPIO_PIN_7
1435 * @arg @ref LL_GPIO_PIN_8
1436 * @arg @ref LL_GPIO_PIN_9
1437 * @arg @ref LL_GPIO_PIN_10
1438 * @arg @ref LL_GPIO_PIN_11
1439 * @arg @ref LL_GPIO_PIN_12
1440 * @arg @ref LL_GPIO_PIN_13
1441 * @arg @ref LL_GPIO_PIN_14
1442 * @arg @ref LL_GPIO_PIN_15
1443 * @retval Returned value can be one of the following values:
1444 * @arg @ref LL_GPIO_TRIGGER_FALLING
1445 * @arg @ref LL_GPIO_TRIGGER_RISING
1446 * @arg @ref LL_GPIO_TRIGGER_BOTH_EDGE
1447 * @arg @ref LL_GPIO_TRIGGER_HIGH
1448 * @arg @ref LL_GPIO_TRIGGER_LOW
1449 */
1450 __STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
1451 {
1452 /* INTTYPESET INTPOLSET INTDBESET
1453 TRIGGER_FALLING 1 0 0
1454 TRIGGER_RISING 1 1 0
1455 TRIGGER_BOTH_EDGE 1 X 1
1456 TRIGGER_HIGH 0 1 X
1457 TRIGGER_LOW 0 0 X
1458 */
1459 #define TYPE_SET ((uint32_t)0x4U) /**< GPIO INTTYPESET is set */
1460 #define POL_SET ((uint32_t)0x2U) /**< GPIO INTPOLSET is set */
1461 #define DBE_SET ((uint32_t)0x1U) /**< GPIO INTDBESET is set */
1462
1463 uint32_t pos = POSITION_VAL(pin_mask);
1464 uint32_t type = (READ_BITS(GPIOx->INTTYPESET, pin_mask) >> pos ) << 2;
1465 uint32_t pol = (READ_BITS(GPIOx->INTPOLSET, pin_mask) >> pos) << 1;
1466 uint32_t both_edge = (READ_BITS(GPIOx->INTDBESET, pin_mask) >> pos);
1467
1468 switch (type | pol | both_edge)
1469 {
1470 case TYPE_SET:
1471 return LL_GPIO_TRIGGER_FALLING;
1472 case TYPE_SET | POL_SET:
1473 return LL_GPIO_TRIGGER_RISING;
1474 case TYPE_SET | DBE_SET:
1475 return LL_GPIO_TRIGGER_BOTH_EDGE;
1476 case TYPE_SET | POL_SET | DBE_SET:
1477 return LL_GPIO_TRIGGER_BOTH_EDGE;
1478 case POL_SET:
1479 return LL_GPIO_TRIGGER_HIGH;
1480 default:
1481 return LL_GPIO_TRIGGER_LOW;
1482 }
1483 }
1484
1485 /**
1486 * @brief Enable GPIO interrupts for pins in the range of 0 to 15.
1487 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1488 *
1489 * Register|BitsName
1490 * --------|--------
1491 * INTENSET | INTENSET
1492 *
1493 * @param GPIOx GPIO instance.
1494 * @param pin_mask This parameter can be a combination of the following values:
1495 * @arg @ref LL_GPIO_PIN_0
1496 * @arg @ref LL_GPIO_PIN_1
1497 * @arg @ref LL_GPIO_PIN_2
1498 * @arg @ref LL_GPIO_PIN_3
1499 * @arg @ref LL_GPIO_PIN_4
1500 * @arg @ref LL_GPIO_PIN_5
1501 * @arg @ref LL_GPIO_PIN_6
1502 * @arg @ref LL_GPIO_PIN_7
1503 * @arg @ref LL_GPIO_PIN_8
1504 * @arg @ref LL_GPIO_PIN_9
1505 * @arg @ref LL_GPIO_PIN_10
1506 * @arg @ref LL_GPIO_PIN_11
1507 * @arg @ref LL_GPIO_PIN_12
1508 * @arg @ref LL_GPIO_PIN_13
1509 * @arg @ref LL_GPIO_PIN_14
1510 * @arg @ref LL_GPIO_PIN_15
1511 * @arg @ref LL_GPIO_PIN_ALL
1512 * @retval None
1513 */
1514 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1515 {
1516 WRITE_REG(GPIOx->INTENSET, pin_mask);
1517 }
1518
1519 /**
1520 * @brief Disable GPIO interrupts for pins in the range of 0 to 15.
1521 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1522 *
1523 * Register|BitsName
1524 * --------|--------
1525 * INTENCLR | INTENCLR
1526 *
1527 * @param GPIOx GPIO instance.
1528 * @param pin_mask This parameter can be a combination of the following values:
1529 * @arg @ref LL_GPIO_PIN_0
1530 * @arg @ref LL_GPIO_PIN_1
1531 * @arg @ref LL_GPIO_PIN_2
1532 * @arg @ref LL_GPIO_PIN_3
1533 * @arg @ref LL_GPIO_PIN_4
1534 * @arg @ref LL_GPIO_PIN_5
1535 * @arg @ref LL_GPIO_PIN_6
1536 * @arg @ref LL_GPIO_PIN_7
1537 * @arg @ref LL_GPIO_PIN_8
1538 * @arg @ref LL_GPIO_PIN_9
1539 * @arg @ref LL_GPIO_PIN_10
1540 * @arg @ref LL_GPIO_PIN_11
1541 * @arg @ref LL_GPIO_PIN_12
1542 * @arg @ref LL_GPIO_PIN_13
1543 * @arg @ref LL_GPIO_PIN_14
1544 * @arg @ref LL_GPIO_PIN_15
1545 * @arg @ref LL_GPIO_PIN_ALL
1546 * @retval None
1547 */
1548 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1549 {
1550 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1551 }
1552
1553 /**
1554 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1555 *
1556 * Register|BitsName
1557 * --------|--------
1558 * INTENSET | INTENSET
1559 *
1560 * @param GPIOx GPIO instance.
1561 * @param pin_mask This parameter can be a combination of the following values:
1562 * @arg @ref LL_GPIO_PIN_0
1563 * @arg @ref LL_GPIO_PIN_1
1564 * @arg @ref LL_GPIO_PIN_2
1565 * @arg @ref LL_GPIO_PIN_3
1566 * @arg @ref LL_GPIO_PIN_4
1567 * @arg @ref LL_GPIO_PIN_5
1568 * @arg @ref LL_GPIO_PIN_6
1569 * @arg @ref LL_GPIO_PIN_7
1570 * @arg @ref LL_GPIO_PIN_8
1571 * @arg @ref LL_GPIO_PIN_9
1572 * @arg @ref LL_GPIO_PIN_10
1573 * @arg @ref LL_GPIO_PIN_11
1574 * @arg @ref LL_GPIO_PIN_12
1575 * @arg @ref LL_GPIO_PIN_13
1576 * @arg @ref LL_GPIO_PIN_14
1577 * @arg @ref LL_GPIO_PIN_15
1578 * @arg @ref LL_GPIO_PIN_ALL
1579 * @retval State of bit (1 or 0).
1580 */
1581 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1582 {
1583 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1584 }
1585
1586 /** @} */
1587
1588 /** @defgroup GPIO_LL_EF_Flag_Management Flag_Management
1589 * @{
1590 */
1591
1592 /**
1593 * @brief Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15
1594 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1595 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1596 *
1597 * Register|BitsName
1598 * --------|--------
1599 * INTSTATUS | INTSTATUS
1600 *
1601 * @param GPIOx GPIO instance.
1602 * @param pin_mask This parameter can be a combination of the following values:
1603 * @arg @ref LL_GPIO_PIN_0
1604 * @arg @ref LL_GPIO_PIN_1
1605 * @arg @ref LL_GPIO_PIN_2
1606 * @arg @ref LL_GPIO_PIN_3
1607 * @arg @ref LL_GPIO_PIN_4
1608 * @arg @ref LL_GPIO_PIN_5
1609 * @arg @ref LL_GPIO_PIN_6
1610 * @arg @ref LL_GPIO_PIN_7
1611 * @arg @ref LL_GPIO_PIN_8
1612 * @arg @ref LL_GPIO_PIN_9
1613 * @arg @ref LL_GPIO_PIN_10
1614 * @arg @ref LL_GPIO_PIN_11
1615 * @arg @ref LL_GPIO_PIN_12
1616 * @arg @ref LL_GPIO_PIN_13
1617 * @arg @ref LL_GPIO_PIN_14
1618 * @arg @ref LL_GPIO_PIN_15
1619 * @arg @ref LL_GPIO_PIN_ALL
1620 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1621 */
1622 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1623 {
1624 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1625 }
1626
1627 /**
1628 * @brief Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
1629 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1630 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1631 *
1632 * Register|BitsName
1633 * --------|--------
1634 * INTSTATUS | INTSTATUS
1635 *
1636 * @param GPIOx GPIO instance.
1637 * @param pin_mask This parameter can be a combination of the following values:
1638 * @arg @ref LL_GPIO_PIN_0
1639 * @arg @ref LL_GPIO_PIN_1
1640 * @arg @ref LL_GPIO_PIN_2
1641 * @arg @ref LL_GPIO_PIN_3
1642 * @arg @ref LL_GPIO_PIN_4
1643 * @arg @ref LL_GPIO_PIN_5
1644 * @arg @ref LL_GPIO_PIN_6
1645 * @arg @ref LL_GPIO_PIN_7
1646 * @arg @ref LL_GPIO_PIN_8
1647 * @arg @ref LL_GPIO_PIN_9
1648 * @arg @ref LL_GPIO_PIN_10
1649 * @arg @ref LL_GPIO_PIN_11
1650 * @arg @ref LL_GPIO_PIN_12
1651 * @arg @ref LL_GPIO_PIN_13
1652 * @arg @ref LL_GPIO_PIN_14
1653 * @arg @ref LL_GPIO_PIN_15
1654 * @arg @ref LL_GPIO_PIN_ALL
1655 * @retval State of bit (1 or 0).
1656 */
1657 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1658 {
1659 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1660 }
1661
1662 /**
1663 * @brief Clear Interrupt Status flag for pins in the range of 0 to 15.
1664 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1665 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1666 *
1667 * Register|BitsName
1668 * --------|--------
1669 * INTSTATUS | INTSTATUS
1670 *
1671 * @param GPIOx GPIO instance.
1672 * @param pin_mask This parameter can be a combination of the following values:
1673 * @arg @ref LL_GPIO_PIN_0
1674 * @arg @ref LL_GPIO_PIN_1
1675 * @arg @ref LL_GPIO_PIN_2
1676 * @arg @ref LL_GPIO_PIN_3
1677 * @arg @ref LL_GPIO_PIN_4
1678 * @arg @ref LL_GPIO_PIN_5
1679 * @arg @ref LL_GPIO_PIN_6
1680 * @arg @ref LL_GPIO_PIN_7
1681 * @arg @ref LL_GPIO_PIN_8
1682 * @arg @ref LL_GPIO_PIN_9
1683 * @arg @ref LL_GPIO_PIN_10
1684 * @arg @ref LL_GPIO_PIN_11
1685 * @arg @ref LL_GPIO_PIN_12
1686 * @arg @ref LL_GPIO_PIN_13
1687 * @arg @ref LL_GPIO_PIN_14
1688 * @arg @ref LL_GPIO_PIN_15
1689 * @arg @ref LL_GPIO_PIN_ALL
1690 * @retval None
1691 */
1692 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1693 {
1694 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1695 }
1696
1697 /** @} */
1698
1699 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
1700 * @{
1701 */
1702 /**
1703 * @brief Initialize GPIO registers according to the specified
1704 * parameters in p_gpio_init.
1705 * @param GPIOx GPIO instance.
1706 * @param p_gpio_init Pointer to a ll_gpio_init_t structure that contains the configuration
1707 * information for the specified GPIO peripheral.
1708 * @retval An error_status_t enumeration value:
1709 * - SUCCESS: GPIO registers are initialized according to p_gpio_init content
1710 * - ERROR: Problem occurred during GPIO Registers initialization
1711 */
1712 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1713 /** @} */
1714
1715 /** @} */
1716
1717 #endif /* defined (GPIO0) || defined (GPIO1) */
1718
1719 #ifdef __cplusplus
1720 }
1721 #endif
1722
1723 #endif /* __GR55xx_LL_GPIO_H__ */
1724
1725 /** @} */
1726
1727 /** @} */
1728
1729 /** @} */
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:1013
_ll_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_gpio.h:78
LL_GPIO_STRENGTH_DS1_POS
#define LL_GPIO_STRENGTH_DS1_POS
Definition: gr55xx_ll_gpio.h:141
ll_gpio_get_pin_strength
__STATIC_INLINE uint32_t ll_gpio_get_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return gpio output drive strength for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:979
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr55xx_ll_gpio.h:178
LL_GPIO_TRIGGER_RISING
#define LL_GPIO_TRIGGER_RISING
Definition: gr55xx_ll_gpio.h:224
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1335
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_gpio.h:1581
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr55xx_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
_ll_gpio_init::strength
uint32_t strength
Definition: gr55xx_ll_gpio.h:103
ll_gpio_get_pin_speed
__STATIC_INLINE uint32_t ll_gpio_get_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return gpio speed for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:878
LL_GPIO_INPUT_TYPE_SCHMITT
#define LL_GPIO_INPUT_TYPE_SCHMITT
Definition: gr55xx_ll_gpio.h:217
ll_gpio_get_pin_input_type
__STATIC_INLINE uint32_t ll_gpio_get_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio input type for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:549
LL_GPIO_STRENGTH_DS1_MASK
#define LL_GPIO_STRENGTH_DS1_MASK
Definition: gr55xx_ll_gpio.h:139
ll_gpio_read_input_pin
__STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:1046
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr55xx_ll_gpio.h:179
_ll_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_gpio.h:91
LL_GPIO_MODE_INOUT
#define LL_GPIO_MODE_INOUT
Definition: gr55xx_ll_gpio.h:172
ll_gpio_read_output_pin
__STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if output data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:1110
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_gpio.h:115
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:1077
OE_SET
#define OE_SET
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:1143
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1298
ll_gpio_enable_both_edge_trigger
__STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO both edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1408
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1657
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1514
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:433
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:645
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:1182
_ll_gpio_init::speed
uint32_t speed
Definition: gr55xx_ll_gpio.h:97
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr55xx_ll_gpio.h:180
LL_GPIO_TRIGGER_LOW
#define LL_GPIO_TRIGGER_LOW
Definition: gr55xx_ll_gpio.h:227
LL_GPIO_TRIGGER_HIGH
#define LL_GPIO_TRIGGER_HIGH
Definition: gr55xx_ll_gpio.h:226
LL_GPIO_TRIGGER_FALLING
#define LL_GPIO_TRIGGER_FALLING
Definition: gr55xx_ll_gpio.h:225
LL_GPIO_PIN_8
#define LL_GPIO_PIN_8
Definition: gr55xx_ll_gpio.h:155
TYPE_SET
#define TYPE_SET
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr55xx_ll_gpio.h:1220
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr55xx_ll_gpio.h:1062
ll_gpio_set_pin_speed
__STATIC_INLINE void ll_gpio_set_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t speed)
Configure gpio speed for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:832
LL_GPIO_TRIGGER_BOTH_EDGE
#define LL_GPIO_TRIGGER_BOTH_EDGE
Definition: gr55xx_ll_gpio.h:228
ll_gpio_get_trigger_type
__STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
Get trigger type for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1450
_ll_gpio_init::input_type
uint32_t input_type
Definition: gr55xx_ll_gpio.h:109
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr55xx_ll_gpio.h:170
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1371
_ll_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_gpio.h:81
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_gpio.h:171
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr55xx_ll_gpio.h:381
LL_GPIO_INPUT_TYPE_CMOS
#define LL_GPIO_INPUT_TYPE_CMOS
Definition: gr55xx_ll_gpio.h:216
LL_GPIO_MODE_NONE
#define LL_GPIO_MODE_NONE
Definition: gr55xx_ll_gpio.h:169
LL_GPIO_STRENGTH_DS0_MASK
#define LL_GPIO_STRENGTH_DS0_MASK
Definition: gr55xx_ll_gpio.h:138
IE_SET
#define IE_SET
_ll_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_gpio.h:86
POL_SET
#define POL_SET
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1622
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1261
ll_gpio_set_pin_strength
__STATIC_INLINE void ll_gpio_set_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t strength)
Configure gpio output drive strength for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:926
DBE_SET
#define DBE_SET
ll_gpio_set_pin_input_type
__STATIC_INLINE void ll_gpio_set_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t type)
Set several pins input type on dedicated port.
Definition: gr55xx_ll_gpio.h:505
LL_GPIO_STRENGTH_DS0_POS
#define LL_GPIO_STRENGTH_DS0_POS
Definition: gr55xx_ll_gpio.h:140
ll_gpio_set_pin_mux
__STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:701
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1548
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:597
ll_gpio_get_pin_mux
__STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:764
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1692