Macros
Specify the default system clock when the system is initialized
Peripheral Driver » LL Driver » CGC » Defines » CGC Exported Constants

## Macros
#define | LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0
#define | LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1
#define | LL_CGC_MCU_SUBSYS_DEFAULT_CLK0
#define | LL_CGC_MCU_PERIPH_CG_DEFAULT
#define | LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT
#define | CGC_CLOCK_ENABLE (1)
#define | CGC_CLOCK_DISABLE (0)
#define | BIT_BAND(addr, bitnum) (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2))
#define | MEMORY_ADDR(addr) (*((volatile uint32_t *)(addr)))
#define | BIT_SEGMENT_VALUE(addr, bitnum) MEMORY_ADDR(BIT_BAND(addr, bitnum))

## Detailed Description

## Macro Definition Documentation

## ◆ BIT_BAND

#define BIT_BAND | ( |  | addr,
|  |  | bitnum
| ) |  | (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2))

Bit segment address calculation

Definition at line 311 of file gr55xx_ll_cgc.h.

## ◆ BIT_SEGMENT_VALUE

#define BIT_SEGMENT_VALUE | ( |  | addr,
|  |  | bitnum
| ) |  | MEMORY_ADDR(BIT_BAND(addr, bitnum))

Bit segment address value manipulation

Definition at line 313 of file gr55xx_ll_cgc.h.

## ◆ CGC_CLOCK_DISABLE

#define CGC_CLOCK_DISABLE (0)

Bit segment address disable

Definition at line 303 of file gr55xx_ll_cgc.h.

## ◆ CGC_CLOCK_ENABLE

#define CGC_CLOCK_ENABLE (1)

Bit segment address enable

Definition at line 302 of file gr55xx_ll_cgc.h.

## ◆ LL_CGC_MCU_PERIPH_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_CG_DEFAULT

Value:
(LL_CGC_FRC_UART0_PCLK |\
LL_CGC_FRC_UART1_PCLK |\
LL_CGC_FRC_UART2_PCLK |\
LL_CGC_FRC_UART3_PCLK |\
LL_CGC_FRC_I2C0_PCLK |\
LL_CGC_FRC_I2C1_PCLK |\
LL_CGC_FRC_I2C2_PCLK |\
LL_CGC_FRC_I2C3_PCLK |\
LL_CGC_FRC_QSPI0_PCLK |\
LL_CGC_FRC_QSPI1_PCLK |\
LL_CGC_FRC_QSPI2_PCLK |\
LL_CGC_FRC_SPI_M_PCLK |\
LL_CGC_FRC_SPI_S_PCLK |\
LL_CGC_FRC_I2S_PCLK |\
LL_CGC_FRC_I2S_S_PCLK |\
LL_CGC_FRC_DSPI_PCLK |\
LL_CGC_FRC_PDM_PCLK |\
LL_CGC_FRC_PWM_0_PCLK |\
LL_CGC_FRC_PWM_1_PCLK)

pclk for the system default periph clock

Definition at line 280 of file gr55xx_ll_cgc.h.

## ◆ LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT

Value:
(MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PDM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 )

pclk for the system default periph wfi clock

Definition at line 300 of file gr55xx_ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_CLK0

#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK0

Value:
(LL_CGC_FRC_SECU_HCLK |\
LL_CGC_FRC_SNSADC_HCLK |\
LL_CGC_FRC_SERIAL_HCLK)

Hclk for the system default clock

Definition at line 259 of file gr55xx_ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0

Value:
(LL_CGC_WFI_SECU_HCLK |\
LL_CGC_WFI_SNSADC_HCLK |\
LL_CGC_WFI_GPIO_HCLK |\
LL_CGC_WFI_BLE_BRG_HCLK |\
LL_CGC_WFI_SERIAL_HCLK)

Hclk0 for the system default clock WFI/WFE

Definition at line 250 of file gr55xx_ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1

Value:
(LL_CGC_WFI_AON_MCUSUB_HCLK |\
LL_CGC_WFI_XF_XQSPI_HCLK |\
LL_CGC_WFI_SRAM_HCLK)

Hclk1 for the system default clock WFI/WFE

Definition at line 254 of file gr55xx_ll_cgc.h.

## ◆ MEMORY_ADDR

#define MEMORY_ADDR | ( |  | addr | ) | (*((volatile uint32_t *)(addr)))

Bit segment address type conversion

Definition at line 312 of file gr55xx_ll_cgc.h.

LL_CGC_WFI_SECU_HCLK
#define LL_CGC_WFI_SECU_HCLK
Definition: gr55xx_ll_cgc.h:76
LL_CGC_WFI_AON_MCUSUB_HCLK
#define LL_CGC_WFI_AON_MCUSUB_HCLK
Definition: gr55xx_ll_cgc.h:92
LL_CGC_FRC_SECU_HCLK
#define LL_CGC_FRC_SECU_HCLK
Definition: gr55xx_ll_cgc.h:112
LL_CGC_FRC_UART0_PCLK
#define LL_CGC_FRC_UART0_PCLK
Definition: gr55xx_ll_cgc.h:137