gr55xx_ll_msio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON_MSIO) || defined(MCU_RET)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief MSIO pad Enumerations definition
75 */
76 typedef enum
77 {
78 MSIOA = 0x00, /**< MSIO_A_PAD */
79 } msio_pad_t;
80
81
82 /**
83 * @brief LL MSIO init Structure definition
84 */
85 typedef struct _ll_msio_init
86 {
87 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
88 This parameter can be any value of @ref MSIO_LL_EC_PIN */
89
90 uint32_t direction; /**< Specifies the direction for the selected pins.
91 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
92
93 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_direction(). */
94
95 uint32_t mode; /**< Specifies the operating mode for the selected pins.
96 This parameter can be a value of @ref MSIO_LL_EC_MODE.
97
98 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_mode(). */
99
100 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
101 This parameter can be a value of @ref MSIO_LL_EC_PULL.
102
103 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_pull().*/
104
105 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
106 This parameter can be a value of @ref MSIO_LL_EC_MUX.
107
108 GPIO HW MSIO_InitStructuration can be modified afterwards using unitary function
109 @ref ll_msio_set_pin_mux(). */
110
111 uint32_t speed; /**< Specifies the IO speed for the selected pins.
112 This parameter can be a value of @ref MSIO_LL_EC_SPEED.
113 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_speed().*/
114
115 uint32_t strength; /**< Specifies the IO output drive strength for the selected pins.
116 This parameter can be a value of @ref MSIO_LL_EC_STRENGTH.
117 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_strength().*/
118
119 uint32_t input_type; /**< Specifies the IO input type for the selected pins.
120 This parameter can be a value of @ref MSIO_LL_EC_INPUT_TYPE.
121 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_input_type().*/
122 } ll_msio_init_t;
123
124 /** @} */
125
126 /** @} */
127
128 /**
129 * @defgroup MSIO_LL_MACRO Defines
130 * @{
131 */
132
133 /* Exported constants --------------------------------------------------------*/
134 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
135 * @{
136 */
137 /** @defgroup MSIO_LL_PRIVATE_MACRO MSIO Mode
138 * @{
139 */
140 #define LL_MSIO_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position MSIO_LL_EC_DIRECTION */
141 #define LL_MSIO_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position MSIO_LL_EC_DIRECTION */
142 #define LL_MSIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in MSIO_LL_EC_STRENGTH */
143 #define LL_MSIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in MSIO_LL_EC_STRENGTH */
144 #define LL_MSIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in MSIO_LL_EC_STRENGTH */
145 #define LL_MSIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in MSIO_LL_EC_STRENGTH */
146 /** @} */
147
148 /** @defgroup MSIO_LL_EC_PIN PIN
149 * @{
150 */
151 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
152 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
153 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
154 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
155 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
156 #define LL_MSIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
157 #define LL_MSIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
158 #define LL_MSIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
159 #define LL_MSIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
160
161 /** @} */
162
163 /** @defgroup MSIO_LL_EC_DIRECTION Direction
164 * @{
165 */
166 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
167 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
168 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
169 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
170 /** @} */
171
172 /** @defgroup MSIO_LL_EC_MODE Mode
173 * @{
174 */
175 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x1U) /**< Select analog mode */
176 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x0U) /**< Enable digital mode */
177 /** @} */
178
179 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
180 * @{
181 */
182 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
183 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
184 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
185 /** @} */
186
187 /** @defgroup MSIO_LL_EC_MUX Alternate Function
188 * @{
189 */
190 #define LL_MSIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
191 #define LL_MSIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
192 #define LL_MSIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
193 #define LL_MSIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
194 #define LL_MSIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
195 #define LL_MSIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
196 #define LL_MSIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
197 #define LL_MSIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
198 #define LL_MSIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
199 /** @} */
200
201 /** @defgroup MSIO_LL_EC_SPEED IO Speed
202 * @{
203 */
204 #define LL_MSIO_SPEED_MEDIUM ((uint32_t)0x0U) /*!< Select medium speed */
205 #define LL_MSIO_SPEED_HIGH ((uint32_t)0x1U) /*!< Select high speed */
206 /** @} */
207
208 /** @defgroup MSIO_LL_EC_STRENGTH IO Strength
209 * @{
210 */
211 #define LL_MSIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
212 #define LL_MSIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
213 #define LL_MSIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
214 #define LL_MSIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
215 /** @} */
216
217 /** @defgroup MSIO_LL_EC_INPUT_TYPE Input type
218 * @{
219 */
220 #define LL_MSIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
221 #define LL_MSIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
222 /** @} */
223
224 /** @} */
225
226 /* Exported macro ------------------------------------------------------------*/
227 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
228 * @{
229 */
230
231 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
232 * @{
233 */
234
235 /**
236 * @brief Write a value in MSIO register
237 * @param __instance__ MSIO instance
238 * @param __REG__ Register to be written
239 * @param __VALUE__ Value to be written in the register
240 * @retval None
241 */
242 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
243
244 /**
245 * @brief Read a value in MSIO register
246 * @param __instance__ MSIO instance
247 * @param __REG__ Register to be read
248 * @retval Register value
249 */
250 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
251
252 /** @} */
253
254 /** @} */
255
256 /* Private types -------------------------------------------------------------*/
257 /* Private variables ---------------------------------------------------------*/
258 /* Private constants ---------------------------------------------------------*/
259 /* Private macros ------------------------------------------------------------*/
260 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
261 * @{
262 */
263
264 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuration
265 * @{
266 */
267
268 /**
269 * @brief LL MSIO InitStrcut default configuration
270 */
271 #define LL_MSIO_DEFAULT_CONFIG \
272 { \
273 .pin = LL_MSIO_PIN_ALL, \
274 .direction = LL_MSIO_DIRECTION_INPUT, \
275 .mode = LL_MSIO_MODE_DIGITAL, \
276 .pull = LL_MSIO_PULL_DOWN, \
277 .mux = LL_MSIO_MUX_8, \
278 .speed = LL_MSIO_SPEED_MEDIUM, \
279 .strength = LL_MSIO_STRENGTH_MEDIUM, \
280 .input_type = LL_MSIO_INPUT_TYPE_CMOS, \
281 }
282 /** @} */
283
284 /** @} */
285
286 /** @} */
287
288 /* Exported functions --------------------------------------------------------*/
289 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
290 * @{
291 */
292
293 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
294 * @{
295 */
296
297 /**
298 * @brief Set several MSIO pins to input/output direction.
299 *
300 * Register|BitsName
301 * --------|--------
302 * MSIO_PAD_CFG_0 | OE
303 * MSIO_PAD_CFG_0 | IE
304 *
305 * @param pin_mask This parameter can be a combination of the following values:
306 * @arg @ref LL_MSIO_PIN_0
307 * @arg @ref LL_MSIO_PIN_1
308 * @arg @ref LL_MSIO_PIN_2
309 * @arg @ref LL_MSIO_PIN_3
310 * @arg @ref LL_MSIO_PIN_4
311 * @arg @ref LL_MSIO_PIN_5
312 * @arg @ref LL_MSIO_PIN_6
313 * @arg @ref LL_MSIO_PIN_7
314 * @arg @ref LL_MSIO_PIN_ALL
315 * @param MSIOx MSIO instance.
316 * @param direction This parameter can be one of the following values:
317 * @arg @ref LL_MSIO_DIRECTION_NONE
318 * @arg @ref LL_MSIO_DIRECTION_INPUT
319 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
320 * @arg @ref LL_MSIO_DIRECTION_INOUT
321 * @retval None
322 */
323 __STATIC_INLINE void ll_msio_set_pin_direction(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t direction)
324 {
325 uint32_t ie_mask = (pin_mask << AON_MSIO_A_PAD_IE_POS) & AON_MSIO_A_PAD_IE;
326 uint32_t oe_mask = (pin_mask << AON_MSIO_A_PAD_OE_POS) & AON_MSIO_A_PAD_OE;
327 uint32_t ie = ((direction == LL_MSIO_DIRECTION_INPUT) || (direction == LL_MSIO_DIRECTION_INOUT)) ? ie_mask : 0x0000U;
328 uint32_t oe = ((direction == LL_MSIO_DIRECTION_OUTPUT) || (direction == LL_MSIO_DIRECTION_INOUT)) ? oe_mask : 0x0000U;
329 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, ie_mask, ie);
330 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask, oe);
331
332 }
333
334 /**
335 * @brief Return gpio direction for a MSIO pin.
336 * @note I/O direction can be Input direction, General purpose output.
337 * @note Warning: only one pin can be passed as parameter.
338 *
339 * Register|BitsName
340 * --------|--------
341 * MSIO_PAD_CFG_0 | OE
342 * MSIO_PAD_CFG_1 | IE
343 *
344 * @param MSIOx MSIO instance.
345 * @param pin This parameter can be one of the following values:
346 * @arg @ref LL_MSIO_PIN_0
347 * @arg @ref LL_MSIO_PIN_1
348 * @arg @ref LL_MSIO_PIN_2
349 * @arg @ref LL_MSIO_PIN_3
350 * @arg @ref LL_MSIO_PIN_4
351 * @arg @ref LL_MSIO_PIN_5
352 * @arg @ref LL_MSIO_PIN_6
353 * @arg @ref LL_MSIO_PIN_7
354 * @retval Returned value can be one of the following values:
355 * @arg @ref LL_MSIO_DIRECTION_NONE
356 * @arg @ref LL_MSIO_DIRECTION_INPUT
357 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
358 * @arg @ref LL_MSIO_DIRECTION_INOUT
359 */
360 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(msio_pad_t MSIOx, uint32_t pin)
361 {
362 uint32_t ie_mask = (pin << AON_MSIO_A_PAD_IE_POS) & AON_MSIO_A_PAD_IE;
363 uint32_t oe_mask = (pin << AON_MSIO_A_PAD_OE_POS) & AON_MSIO_A_PAD_OE;
364 uint32_t ie = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, ie_mask) >> (POSITION_VAL(pin));
365 uint32_t oe = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask) >> (POSITION_VAL(pin));
366 return (((ie >> AON_MSIO_A_PAD_IE_POS) << LL_MSIO_INPUT_POS)
367 | ((oe >> AON_MSIO_A_PAD_OE_POS) << LL_MSIO_OUTPUT_POS));
368 }
369
370 /**
371 * @brief Set several MSIO pins to analog/digital mode.
372 *
373 * Register|BitsName
374 * --------|--------
375 * MSIO_PAD_CFG_3 | AE
376 *
377 * @param MSIOx MSIO instance.
378 * @param pin_mask This parameter can be a combination of the following values:
379 * @arg @ref LL_MSIO_PIN_0
380 * @arg @ref LL_MSIO_PIN_1
381 * @arg @ref LL_MSIO_PIN_2
382 * @arg @ref LL_MSIO_PIN_3
383 * @arg @ref LL_MSIO_PIN_4
384 * @arg @ref LL_MSIO_PIN_5
385 * @arg @ref LL_MSIO_PIN_6
386 * @arg @ref LL_MSIO_PIN_7
387 * @arg @ref LL_MSIO_PIN_ALL
388 * @param mode This parameter can be one of the following values:
389 * @arg @ref LL_MSIO_MODE_ANALOG
390 * @arg @ref LL_MSIO_MODE_DIGITAL
391 * @retval None
392 */
393 __STATIC_INLINE void ll_msio_set_pin_mode(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t mode)
394 {
395 uint32_t mask = (pin_mask << AON_MSIO_A_PAD_AE_POS) & AON_MSIO_A_PAD_AE;
396 if(mode == LL_MSIO_MODE_ANALOG)
397 {
398 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG2, mask);
399 }
400 else
401 {
402 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG2, mask);
403 }
404 }
405
406 /**
407 * @brief Return gpio mode for a MSIO pin.
408 * @note I/O mode can be analog or digital.
409 * @note Warning: only one pin can be passed as parameter.
410 *
411 * Register|BitsName
412 * --------|--------
413 * MSIO_PAD_CFG_3 | AE
414 *
415 * @param MSIOx MSIO instance.
416 * @param pin This parameter can be one of the following values:
417 * @arg @ref LL_MSIO_PIN_0
418 * @arg @ref LL_MSIO_PIN_1
419 * @arg @ref LL_MSIO_PIN_2
420 * @arg @ref LL_MSIO_PIN_3
421 * @arg @ref LL_MSIO_PIN_4
422 * @arg @ref LL_MSIO_PIN_5
423 * @arg @ref LL_MSIO_PIN_6
424 * @arg @ref LL_MSIO_PIN_7
425 * @retval Returned value can be one of the following values:
426 * @arg @ref LL_MSIO_MODE_ANALOG
427 * @arg @ref LL_MSIO_MODE_DIGITAL
428 */
429 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(msio_pad_t MSIOx, uint32_t pin)
430 {
431 uint32_t mask = (pin << AON_MSIO_A_PAD_AE_POS) & AON_MSIO_A_PAD_AE;
432 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG2, mask) == mask) ? LL_MSIO_MODE_ANALOG : LL_MSIO_MODE_DIGITAL);
433 }
434
435 /**
436 * @brief Set several MSIO pins input type.
437 *
438 * Register|BitsName
439 * --------|--------
440 * MSIO_A_PAD_CFG2 | IS
441 *
442 * @param MSIOx MSIO instance
443 * @param pin_mask This parameter can be a combination of the following values:
444 * @arg @ref LL_MSIO_PIN_0
445 * @arg @ref LL_MSIO_PIN_1
446 * @arg @ref LL_MSIO_PIN_2
447 * @arg @ref LL_MSIO_PIN_3
448 * @arg @ref LL_MSIO_PIN_4
449 * @arg @ref LL_MSIO_PIN_5
450 * @arg @ref LL_MSIO_PIN_6
451 * @arg @ref LL_MSIO_PIN_7
452 * @arg @ref LL_MSIO_PIN_ALL
453 * @param type This parameter can be one of the following values:
454 * @arg @ref LL_MSIO_INPUT_TYPE_CMOS
455 * @arg @ref LL_MSIO_INPUT_TYPE_SCHMITT
456 * @retval None
457 */
458 __STATIC_INLINE void ll_msio_set_pin_input_type(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t type)
459 {
460 pin_mask = (pin_mask << AON_MSIO_A_PAD_IS_POS) & AON_MSIO_A_PAD_IS;
461 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, pin_mask, (type == LL_MSIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
462 }
463
464 /**
465 * @brief Return input type for a MSIO pin.
466 * @note I/O mode can be analog or digital.
467 * @note Warning: only one pin can be passed as parameter.
468 *
469 * Register|BitsName
470 * --------|--------
471 * MSIO_A_PAD_CFG2 | IS
472 *
473 * @param MSIOx MSIO instance
474 * @param pin This parameter can be one of the following values:
475 * @arg @ref LL_MSIO_PIN_0
476 * @arg @ref LL_MSIO_PIN_1
477 * @arg @ref LL_MSIO_PIN_2
478 * @arg @ref LL_MSIO_PIN_3
479 * @arg @ref LL_MSIO_PIN_4
480 * @arg @ref LL_MSIO_PIN_5
481 * @arg @ref LL_MSIO_PIN_6
482 * @arg @ref LL_MSIO_PIN_7
483 * @arg @ref LL_MSIO_PIN_ALL
484 * @retval Returned value can be one of the following values:
485 * @arg @ref LL_MSIO_INPUT_TYPE_CMOS
486 * @arg @ref LL_MSIO_INPUT_TYPE_SCHMITT
487 */
488 __STATIC_INLINE uint32_t ll_msio_get_pin_input_type(msio_pad_t MSIOx, uint32_t pin)
489 {
490 pin = (pin << AON_MSIO_A_PAD_IS_POS) & AON_MSIO_A_PAD_IS;
491 return ((uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, pin) == pin) ?
492 LL_MSIO_INPUT_TYPE_SCHMITT : LL_MSIO_INPUT_TYPE_CMOS);
493 }
494 /**
495 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
496 *
497 * Register|BitsName
498 * --------|--------
499 * MSIO_PAD_CFG_1 | PE
500 * MSIO_PAD_CFG_1 | PS
501 *
502 * @param MSIOx MSIO instance.
503 * @param pin_mask This parameter can be a combination of the following values:
504 * @arg @ref LL_MSIO_PIN_0
505 * @arg @ref LL_MSIO_PIN_1
506 * @arg @ref LL_MSIO_PIN_2
507 * @arg @ref LL_MSIO_PIN_3
508 * @arg @ref LL_MSIO_PIN_4
509 * @arg @ref LL_MSIO_PIN_5
510 * @arg @ref LL_MSIO_PIN_6
511 * @arg @ref LL_MSIO_PIN_7
512 * @arg @ref LL_MSIO_PIN_ALL
513 * @param pull This parameter can be one of the following values:
514 * @arg @ref LL_MSIO_PULL_NO
515 * @arg @ref LL_MSIO_PULL_UP
516 * @arg @ref LL_MSIO_PULL_DOWN
517 * @retval None
518 */
519 __STATIC_INLINE void ll_msio_set_pin_pull(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t pull)
520 {
521 uint32_t ps_mask = (pin_mask << AON_MSIO_A_PAD_PS_POS) & AON_MSIO_A_PAD_PS;
522 uint32_t pe_mask = (pin_mask << AON_MSIO_A_PAD_PE_POS) & AON_MSIO_A_PAD_PE;
523 uint32_t ps = (pull == LL_MSIO_PULL_UP) ? ps_mask : 0x0000U;
524 uint32_t pe = (pull == LL_MSIO_PULL_NO) ? 0x0000U : pe_mask;
525 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, pe_mask | ps_mask, pe | ps);
526 }
527
528 /**
529 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
530 * @note Warning: only one pin can be passed as parameter.
531 *
532 * Register|BitsName
533 * --------|--------
534 * MSIO_PAD_CFG_1 | PE
535 * MSIO_PAD_CFG_1 | PS
536 *
537 * @param MSIOx MSIO instance.
538 * @param pin This parameter can be one of the following values:
539 * @arg @ref LL_MSIO_PIN_0
540 * @arg @ref LL_MSIO_PIN_1
541 * @arg @ref LL_MSIO_PIN_2
542 * @arg @ref LL_MSIO_PIN_3
543 * @arg @ref LL_MSIO_PIN_4
544 * @arg @ref LL_MSIO_PIN_5
545 * @arg @ref LL_MSIO_PIN_6
546 * @arg @ref LL_MSIO_PIN_7
547 * @retval Returned value can be one of the following values:
548 * @arg @ref LL_MSIO_PULL_NO
549 * @arg @ref LL_MSIO_PULL_UP
550 * @arg @ref LL_MSIO_PULL_DOWN
551 */
552 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(msio_pad_t MSIOx, uint32_t pin)
553 {
554 uint32_t ps_mask = (pin << AON_MSIO_A_PAD_PS_POS) & AON_MSIO_A_PAD_PS;
555 uint32_t pe_mask = (pin << AON_MSIO_A_PAD_PE_POS) & AON_MSIO_A_PAD_PE;
556 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, pe_mask) == RESET) ? LL_MSIO_PULL_NO :
557 ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ps_mask) == RESET) ? LL_MSIO_PULL_DOWN : LL_MSIO_PULL_UP));
558 }
559
560 /**
561 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
562 * @note Possible values are from AF0 to AF7 depending on target.
563 * @note Warning: only one pin can be passed as parameter.
564 *
565 * Register|BitsName
566 * --------|--------
567 * MSIO_PAD_MUX_CTL | CTL_00_04
568 * MSIO_PAD_CFG_1 | MCU_OVR
569 *
570 * @param MSIOx MSIO instance.
571 * @param pin This parameter can be one of the following values:
572 * @arg @ref LL_MSIO_PIN_0
573 * @arg @ref LL_MSIO_PIN_1
574 * @arg @ref LL_MSIO_PIN_2
575 * @arg @ref LL_MSIO_PIN_3
576 * @arg @ref LL_MSIO_PIN_4
577 * @arg @ref LL_MSIO_PIN_5
578 * @arg @ref LL_MSIO_PIN_6
579 * @arg @ref LL_MSIO_PIN_7
580 * @param mux This parameter can be one of the following values:
581 * @arg @ref LL_MSIO_MUX_0
582 * @arg @ref LL_MSIO_MUX_1
583 * @arg @ref LL_MSIO_MUX_2
584 * @arg @ref LL_MSIO_MUX_3
585 * @arg @ref LL_MSIO_MUX_4
586 * @arg @ref LL_MSIO_MUX_5
587 * @arg @ref LL_MSIO_MUX_6
588 * @arg @ref LL_MSIO_MUX_7
589 * @arg @ref LL_MSIO_MUX_8
590 * @retval None
591 */
592 __STATIC_INLINE void ll_msio_set_pin_mux(msio_pad_t MSIOx, uint32_t pin, uint32_t mux)
593 {
594 uint32_t pos = POSITION_VAL(pin) << 2;
595 MODIFY_REG(MCU_RET->MSIO_A_PAD_MUX_CTL, 0xF << pos, mux << pos);
596 if (LL_MSIO_MUX_8 == mux)
597 {
598 CLEAR_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS);
599 }
600 else
601 {
602 SET_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS);
603 }
604 }
605
606 /**
607 * @brief Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
608 *
609 * Register|BitsName
610 * --------|--------
611 * MSIO_PAD_MUX_CTL | CTL_00_04
612 * MSIO_PAD_CFG_1 | MCU_OVR
613 *
614 * @param MSIOx MSIO instance.
615 * @param pin This parameter can be one of the following values:
616 * @arg @ref LL_MSIO_PIN_0
617 * @arg @ref LL_MSIO_PIN_1
618 * @arg @ref LL_MSIO_PIN_2
619 * @arg @ref LL_MSIO_PIN_3
620 * @arg @ref LL_MSIO_PIN_4
621 * @arg @ref LL_MSIO_PIN_5
622 * @arg @ref LL_MSIO_PIN_6
623 * @arg @ref LL_MSIO_PIN_7
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_MSIO_MUX_0
626 * @arg @ref LL_MSIO_MUX_1
627 * @arg @ref LL_MSIO_MUX_2
628 * @arg @ref LL_MSIO_MUX_3
629 * @arg @ref LL_MSIO_MUX_4
630 * @arg @ref LL_MSIO_MUX_5
631 * @arg @ref LL_MSIO_MUX_6
632 * @arg @ref LL_MSIO_MUX_7
633 * @arg @ref LL_MSIO_MUX_8
634 */
635 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(msio_pad_t MSIOx, uint32_t pin)
636 {
637 if (READ_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS))
638 {
639 uint32_t pos = POSITION_VAL(pin) << 2;
640 return (READ_BITS(MCU_RET->MSIO_A_PAD_MUX_CTL, 0xF << pos) >> pos);
641 }
642 else
643 {
644 return LL_MSIO_MUX_8;
645 }
646 }
647
648 /**
649 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 9 for a dedicated port.
650 * @note Possible values are from AF0 to AF7 depending on target.
651 * @note Warning: only one pin can be passed as parameter.
652 *
653 * Register|BitsName
654 * --------|--------
655 * MSIO_A_PAD_CFG2 | SR
656 *
657 * @param MSIOx MSIO instance
658 * @param pin_mask This parameter can be one of the following values:
659 * @arg @ref LL_MSIO_PIN_0
660 * @arg @ref LL_MSIO_PIN_1
661 * @arg @ref LL_MSIO_PIN_2
662 * @arg @ref LL_MSIO_PIN_3
663 * @arg @ref LL_MSIO_PIN_4
664 * @arg @ref LL_MSIO_PIN_5
665 * @arg @ref LL_MSIO_PIN_6
666 * @arg @ref LL_MSIO_PIN_7
667 * @param speed This parameter can be one of the following values:
668 * @arg @ref LL_MSIO_SPEED_MEDIUM
669 * @arg @ref LL_MSIO_SPEED_HIGH
670 * @retval None
671 */
672 __STATIC_INLINE void ll_msio_set_pin_speed(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t speed)
673 {
674 uint32_t pos;
675 pos = POSITION_VAL(pin_mask);
676 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, pin_mask << AON_MSIO_A_PAD_SR_POS, speed << pos << AON_MSIO_A_PAD_SR_POS);
677 }
678
679 /**
680 * @brief Return gpio alternate function of a dedicated pin from 0 to 9 for a dedicated port.
681 *
682 * Register|BitsName
683 * --------|--------
684 * MSIO_A_PAD_CFG2 | SR
685 *
686 * @param MSIOx MSIO instance
687 * @param pin This parameter can be one of the following values:
688 * @arg @ref LL_MSIO_PIN_0
689 * @arg @ref LL_MSIO_PIN_1
690 * @arg @ref LL_MSIO_PIN_2
691 * @arg @ref LL_MSIO_PIN_3
692 * @arg @ref LL_MSIO_PIN_4
693 * @arg @ref LL_MSIO_PIN_5
694 * @arg @ref LL_MSIO_PIN_6
695 * @arg @ref LL_MSIO_PIN_7
696 * @retval Returned value can be one of the following values:
697 * @arg @ref LL_MSIO_SPEED_MEDIUM
698 * @arg @ref LL_MSIO_SPEED_HIGH
699 */
700 __STATIC_INLINE uint32_t ll_msio_get_pin_speed(msio_pad_t MSIOx, uint32_t pin)
701 {
702 uint32_t pos;
703 pos = POSITION_VAL(pin);
704 return (READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, pin << AON_MSIO_A_PAD_SR_POS) >> AON_MSIO_A_PAD_SR_POS >> pos);
705 }
706
707 /**
708 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 9 for a dedicated port.
709 * @note Possible values are from AF0 to AF7 depending on target.
710 * @note Warning: only one pin can be passed as parameter.
711 *
712 * Register|BitsName
713 * --------|--------
714 * MSIO_A_PAD_CFG3 | DS0
715 * MSIO_A_PAD_CFG3 | DS1
716 *
717 * @param MSIOx MSIO instance
718 * @param pin_mask This parameter can be one of the following values:
719 * @arg @ref LL_MSIO_PIN_0
720 * @arg @ref LL_MSIO_PIN_1
721 * @arg @ref LL_MSIO_PIN_2
722 * @arg @ref LL_MSIO_PIN_3
723 * @arg @ref LL_MSIO_PIN_4
724 * @arg @ref LL_MSIO_PIN_5
725 * @arg @ref LL_MSIO_PIN_6
726 * @arg @ref LL_MSIO_PIN_7
727 * @param strength This parameter can be one of the following values:
728 * @arg @ref LL_MSIO_STRENGTH_LOW
729 * @arg @ref LL_MSIO_STRENGTH_MEDIUM
730 * @arg @ref LL_MSIO_STRENGTH_HIGH
731 * @arg @ref LL_MSIO_STRENGTH_ULTRA
732 *
733 * @retval None
734 */
735 __STATIC_INLINE void ll_msio_set_pin_strength(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t strength)
736 {
737 uint32_t pos;
738 pos = POSITION_VAL(pin_mask);
739 uint8_t ds0 = (strength & LL_MSIO_STRENGTH_DS0_MASK) >> LL_MSIO_STRENGTH_DS0_POS;
740 uint8_t ds1 = (strength & LL_MSIO_STRENGTH_DS1_MASK) >> LL_MSIO_STRENGTH_DS1_POS;
741 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_DS0_POS , ds0 << pos << AON_MSIO_A_PAD_DS0_POS);
742 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_DS1_POS , ds1 << pos << AON_MSIO_A_PAD_DS1_POS);
743 }
744
745 /**
746 * @brief Return gpio alternate function of a dedicated pin from 0 to 9 for a dedicated port.
747 *
748 * Register|BitsName
749 * --------|--------
750 * MSIO_A_PAD_CFG3 | DS0
751 * MSIO_A_PAD_CFG3 | DS1
752 *
753 * @param MSIOx MSIO instance
754 * @param pin_mask This parameter can be one of the following values:
755 * @arg @ref LL_MSIO_PIN_0
756 * @arg @ref LL_MSIO_PIN_1
757 * @arg @ref LL_MSIO_PIN_2
758 * @arg @ref LL_MSIO_PIN_3
759 * @arg @ref LL_MSIO_PIN_4
760 * @arg @ref LL_MSIO_PIN_5
761 * @arg @ref LL_MSIO_PIN_6
762 * @arg @ref LL_MSIO_PIN_7
763
764 * @retval Returned value can be one of the following values:
765 * @arg @ref LL_MSIO_STRENGTH_LOW
766 * @arg @ref LL_MSIO_STRENGTH_MEDIUM
767 * @arg @ref LL_MSIO_STRENGTH_HIGH
768 * @arg @ref LL_MSIO_STRENGTH_ULTRA
769 */
770 __STATIC_INLINE uint32_t ll_msio_get_pin_strength(msio_pad_t MSIOx, uint32_t pin_mask)
771 {
772 uint32_t pos;
773 pos = POSITION_VAL(pin_mask);
774 uint8_t ds0 = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_DS0_POS ) >> AON_MSIO_A_PAD_DS0_POS >> pos;
775 uint8_t ds1 = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_DS1_POS ) >> AON_MSIO_A_PAD_DS1_POS >> pos;
776 return ((ds0 << LL_MSIO_STRENGTH_DS0_POS) | (ds1 << LL_MSIO_STRENGTH_DS1_POS));
777 }
778 /** @} */
779
780 /** @defgroup MSIO_LL_EF_Data_Access Data Access
781 * @{
782 */
783
784 /**
785 * @brief Return full input data register value of MSIO.
786 *
787 * Register|BitsName
788 * --------|--------
789 * MSIO_A_PAD_CFG0 | AON_MSIO_A_PAD_IN
790 *
791 * @param MSIOx MSIO instance.
792 * @retval Input data register value of port
793 */
794 __STATIC_INLINE uint32_t ll_msio_read_input_port(msio_pad_t MSIOx)
795 {
796 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_IN_VAL) >> AON_MSIO_A_PAD_IN_VAL_POS);
797 }
798
799 /**
800 * @brief Return if input data level of several MSIO pins is high or low.
801 *
802 * Register|BitsName
803 * --------|--------
804 * MSIO_A_PAD_CFG0 | IN_VAL
805 *
806 * @param MSIOx MSIO instance.
807 * @param pin_mask This parameter can be a combination of the following values:
808 * @arg @ref LL_MSIO_PIN_0
809 * @arg @ref LL_MSIO_PIN_1
810 * @arg @ref LL_MSIO_PIN_2
811 * @arg @ref LL_MSIO_PIN_3
812 * @arg @ref LL_MSIO_PIN_4
813 * @arg @ref LL_MSIO_PIN_5
814 * @arg @ref LL_MSIO_PIN_6
815 * @arg @ref LL_MSIO_PIN_7
816 * @arg @ref LL_MSIO_PIN_ALL
817 * @retval State of bit (1 or 0).
818 */
819 __STATIC_INLINE uint32_t ll_msio_read_input_pin(msio_pad_t MSIOx, uint32_t pin_mask)
820 {
821 pin_mask = (pin_mask << AON_MSIO_A_PAD_IN_VAL_POS) & AON_MSIO_A_PAD_IN_VAL;
822 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
823 }
824
825 /**
826 * @brief Return if input data level of several MSIO pins is high or low.
827 *
828 * Register|BitsName
829 * --------|--------
830 * MSIO_PAD_CFG_0 | OUT_VAL
831 *
832 * @param MSIOx MSIO instance.
833 * @param pin_mask This parameter can be a combination of the following values:
834 * @arg @ref LL_MSIO_PIN_0
835 * @arg @ref LL_MSIO_PIN_1
836 * @arg @ref LL_MSIO_PIN_2
837 * @arg @ref LL_MSIO_PIN_3
838 * @arg @ref LL_MSIO_PIN_4
839 * @arg @ref LL_MSIO_PIN_5
840 * @arg @ref LL_MSIO_PIN_6
841 * @arg @ref LL_MSIO_PIN_7
842 * @arg @ref LL_MSIO_PIN_ALL
843 * @retval State of bit (1 or 0).
844 */
845 __STATIC_INLINE uint32_t ll_msio_read_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
846 {
847 pin_mask = (pin_mask << AON_MSIO_A_PAD_OUT_VAL_POS) & AON_MSIO_A_PAD_OUT_VAL;
848 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
849 }
850
851 /**
852 * @brief Write output data register of MSIO.
853 *
854 * Register|BitsName
855 * --------|--------
856 * MSIO_PAD_CFG_0 | OUT_VAL
857 *
858 * @param MSIOx MSIO instance.
859 * @param port_value Level value for each pin of the port
860 * @retval None
861 */
862 __STATIC_INLINE void ll_msio_write_output_port(msio_pad_t MSIOx, uint32_t port_value)
863 {
864 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_OUT_VAL, (port_value << AON_MSIO_A_PAD_OUT_VAL_POS) & AON_MSIO_A_PAD_OUT_VAL);
865 }
866 /**
867 * @brief Return full output data register value of MSIO.
868 *
869 * Register|BitsName
870 * --------|--------
871 * MSIO_PAD_CFG_0 | IN
872 *
873 * @param MSIOx MSIO instance.
874 * @retval Output data register value of port
875 */
876 __STATIC_INLINE uint32_t ll_msio_read_output_port(msio_pad_t MSIOx)
877 {
878 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_OUT_VAL) >> AON_MSIO_A_PAD_OUT_VAL_POS);
879 }
880
881 /**
882 * @brief Set specified MSIO pins to high level
883 *
884 * Register|BitsName
885 * --------|--------
886 * MSIO_PAD_CFG_0 | OUT_VAL
887 *
888 * @param MSIOx MSIO instance.
889 * @param pin_mask This parameter can be a combination of the following values:
890 * @arg @ref LL_MSIO_PIN_0
891 * @arg @ref LL_MSIO_PIN_1
892 * @arg @ref LL_MSIO_PIN_2
893 * @arg @ref LL_MSIO_PIN_3
894 * @arg @ref LL_MSIO_PIN_4
895 * @arg @ref LL_MSIO_PIN_5
896 * @arg @ref LL_MSIO_PIN_6
897 * @arg @ref LL_MSIO_PIN_7
898 * @arg @ref LL_MSIO_PIN_ALL
899 * @retval None
900 */
901 __STATIC_INLINE void ll_msio_set_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
902 {
903 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_A_PAD_OUT_VAL_POS) & AON_MSIO_A_PAD_OUT_VAL);
904 }
905
906 /**
907 * @brief Set specified MSIO pins to low level.
908 *
909 * Register|BitsName
910 * --------|--------
911 * MSIO_PAD_CFG_0 | OUT_VAL
912 *
913 * @param MSIOx MSIO instance.
914 * @param pin_mask This parameter can be a combination of the following values:
915 * @arg @ref LL_MSIO_PIN_0
916 * @arg @ref LL_MSIO_PIN_1
917 * @arg @ref LL_MSIO_PIN_2
918 * @arg @ref LL_MSIO_PIN_3
919 * @arg @ref LL_MSIO_PIN_4
920 * @arg @ref LL_MSIO_PIN_5
921 * @arg @ref LL_MSIO_PIN_6
922 * @arg @ref LL_MSIO_PIN_7
923 * @arg @ref LL_MSIO_PIN_ALL
924 * @retval None
925 */
926 __STATIC_INLINE void ll_msio_reset_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
927 {
928 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_A_PAD_OUT_VAL_POS) & AON_MSIO_A_PAD_OUT_VAL);
929 }
930
931 /**
932 * @brief Toggle data value of specified MSIO pins.
933 *
934 * Register|BitsName
935 * --------|--------
936 * MSIO_PAD_CFG_0 | OUT_VAL
937 *
938 * @param MSIOx MSIO instance.
939 * @param pin_mask This parameter can be a combination of the following values:
940 * @arg @ref LL_MSIO_PIN_0
941 * @arg @ref LL_MSIO_PIN_1
942 * @arg @ref LL_MSIO_PIN_2
943 * @arg @ref LL_MSIO_PIN_3
944 * @arg @ref LL_MSIO_PIN_4
945 * @arg @ref LL_MSIO_PIN_5
946 * @arg @ref LL_MSIO_PIN_6
947 * @arg @ref LL_MSIO_PIN_7
948 * @arg @ref LL_MSIO_PIN_ALL
949 * @retval None
950 */
951 __STATIC_INLINE void ll_msio_toggle_pin(msio_pad_t MSIOx, uint32_t pin_mask)
952 {
953 WRITE_REG(AON_MSIO->MSIO_A_PAD_CFG0, (READ_REG(AON_MSIO->MSIO_A_PAD_CFG0) ^ ((pin_mask << AON_MSIO_A_PAD_OUT_VAL_POS) & AON_MSIO_A_PAD_OUT_VAL)));
954 }
955
956 /** @} */
957
958 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
959 * @{
960 */
961 /**
962 * @brief Initialize MSIO registers according to the specified.
963 * parameters in p_msio_init.
964 *
965 * @param MSIOx MSIO instance.
966 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
967 * information for the specified MSIO peripheral.
968 * @retval An error_status_t enumeration value:
969 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
970 * - ERROR: Problem occurred during MSIO Registers initialization
971 */
972 error_status_t ll_msio_init(msio_pad_t MSIOx,ll_msio_init_t *p_msio_init);
973
974 /** @} */
975
976 /** @} */
977
978 #endif /* defined(AON_MSIO) || defined(MCU_RET) */
979
980 #ifdef __cplusplus
981 }
982 #endif
983
984 #endif /* __GR55XX_LL_MSIO_H__ */
985
986 /** @} */
987
988 /** @} */
989
990 /** @} */