gr533x_ll_rtc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_rtc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of RTC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_RTC RTC
47 * @brief RTC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_RTC_H__
53 #define __GR533X_LL_RTC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 /**
63 * @defgroup RTC_LL_MACRO Defines
64 * @{
65 */
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
68 * @{
69 */
70 /** @defgroup RTC_LL_EC_CLOCK_DIV Clock divider
71 * @{
72 */
73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U) /**< Select SLP_CLK */
74 #define LL_RTC_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
75 #define LL_RTC_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
76 #define LL_RTC_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
77 #define LL_RTC_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos) /**< Select 1/32 divider */
78 #define LL_RTC_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos) /**< Select 1/64 divider */
79 #define LL_RTC_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos) /**< Select 1/128 divider */
80 #define LL_RTC_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos) /**< Select 1/256 divider */
81 /** @} */
82
83 /** @defgroup AON_CTL_RTC_TIMER_PERIODIC_SEL RTC Periodic timer select defines
84 * @{
85 */
86 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U) /**< Select periodic alarm one-time */
87 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U) /**< Select periodic alarm auto-reload */
88 /** @} */
89
90 /** @defgroup RTC_READ_CONFIG RTC CFG0 register read defines
91 * @{
92 */
93 /**
94 * @brief LL RTC Read CFG
95 */
96 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
97 RTC_CFG0_ALARM_EN | \
98 RTC_CFG0_TICK_EN | \
99 RTC_CFG0_TICK_MDOE))
100 /** @} */
101
102 /** @} */
103
104 /** @} */
105
106 /* Exported functions --------------------------------------------------------*/
107 /** @defgroup RTC_LL_DRIVER_FUNCTIONS Functions
108 * @{
109 */
110
111 /** @defgroup RTC_LL_EF_Configuration Configuration functions
112 * @{
113 */
114
115 /**
116 * @brief Enable RTC counter.
117 *
118 * Register|BitsName
119 * --------|--------
120 * RTC_CFG0 | EN
121 *
122 * @param RTCx RTC instance
123 * @retval None
124 */
125 __STATIC_INLINE void ll_rtc_enable(rtc_regs_t* RTCx)
126 {
127 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
128 }
129
130 /**
131 * @brief Disable RTC counter.
132 *
133 * Register|BitsName
134 * --------|--------
135 * RTC_CFG0 | EN
136 *
137 * @param RTCx RTC instance
138 * @retval None
139 */
140 __STATIC_INLINE void ll_rtc_disable(rtc_regs_t* RTCx)
141 {
142 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
143 }
144
145 /**
146 * @brief Check if the RTC peripheral is enabled or disabled.
147 *
148 * Register|BitsName
149 * --------|--------
150 * RTC_CFG0 | EN
151 *
152 * @param RTCx RTC instance
153 * @retval State of bit (1 or 0).
154 */
155 __STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t* RTCx)
156 {
157 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
158 }
159
160 /**
161 * @brief Reloads RTC counter.
162 *
163 * Register|BitsName
164 * --------|--------
165 * RTC_TIMER_W | TIMER_VALUE
166 *
167 * @param RTCx RTC instance
168 * @param counter RTC counter
169 * @retval None
170 */
171 __STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t* RTCx, uint32_t counter)
172 {
173 WRITE_REG(RTCx->TIMER_W, counter);
174 }
175
176 /**
177 * @brief Reloads RTC counter and request.
178 *
179 * Register|BitsName
180 * --------|--------
181 * RTC_TIMER_W | TIMER_VALUE
182 * RTC_CFG0 | VAL_LOAD
183 *
184 * @param RTCx RTC instance
185 * @param start_value RTC counter
186 * @retval None
187 */
188 __STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t* RTCx, uint32_t start_value)
189 {
190 WRITE_REG(RTCx->TIMER_W, start_value);
191 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TIMER_SET | (READ_CFG0_CFG(RTCx)));
192 }
193
194 /**
195 * @brief Reloads RTC alarm.
196 *
197 * Register|BitsName
198 * --------|--------
199 * RTC_TIMER_W | ALARM_VAL_LOAD
200 *
201 * @param RTCx RTC instance
202 * @param value RTC alarm value
203 * @retval None
204 */
205 __STATIC_INLINE void ll_rtc_reload_alarm(rtc_regs_t* RTCx, uint32_t value)
206 {
207 WRITE_REG(RTCx->ALARM_W, value);
208 }
209
210 /**
211 * @brief Reloads RTC alarm and request.
212 *
213 * Register|BitsName
214 * --------|--------
215 * RTC_ALARM_W | ALARM_VAL_LOAD
216 * RTC_CFG0 | ALARM_VALUE
217 *
218 * @param RTCx RTC instance
219 * @param alarm_value RTC alarm value
220 * @retval None
221 */
222 __STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t* RTCx, uint32_t alarm_value)
223 {
224 WRITE_REG(RTCx->ALARM_W, alarm_value);
225 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET | (READ_CFG0_CFG(RTCx)));
226 }
227
228 /**
229 * @brief Reloads RTC perd_alarm.
230 *
231 * Register|BitsName
232 * --------|--------
233 * RTC_TIMER_W | ALARM_VAL_LOAD
234 *
235 * @param RTCx RTC instance
236 * @param tick RTC tick value
237 * @retval None
238 */
239 __STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t* RTCx, uint32_t tick)
240 {
241 WRITE_REG(RTCx->TICK_W, tick);
242 }
243
244 /**
245 * @brief Reloads RTC tick and request.
246 *
247 * Register|BitsName
248 * --------|--------
249 * RTC_TICK_W | TICK_VAL_LOAD
250 * RTC_CFG0 | TICK_VALUE
251 *
252 * @param RTCx RTC instance
253 * @param alarm_value RTC tick value
254 * @retval None
255 */
256 __STATIC_INLINE void ll_rtc_tick_value_set_and_request(rtc_regs_t* RTCx, uint32_t alarm_value)
257 {
258 WRITE_REG(RTCx->ALARM_W, alarm_value);
259 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET | (READ_CFG0_CFG(RTCx)));
260 }
261
262 /**
263 * @brief Read the RTC counter config value.
264 *
265 * Register|BitsName
266 * --------|--------
267 * RTC_TIMER_W | TIMER_VAL_READ
268 *
269 * @param RTCx RTC instance
270 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
271 */
272 __STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t* RTCx)
273 {
274 return (uint32_t)READ_REG(RTCx->TIMER_W);
275 }
276
277 /**
278 * @brief Read the RTC counter current value.
279 *
280 * Register|BitsName
281 * --------|--------
282 * RTC_TIMER_R | TIMER_VAL_READ
283 *
284 * @param RTCx RTC instance
285 * @retval Value for current counter which should ranging between 0 ~ 0xFFFF_FFFF
286 */
287 __STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t* RTCx)
288 {
289 return (uint32_t)READ_REG(RTCx->TIMER_R);
290 }
291
292 /**
293 * @brief Read the RTC counter config alarm value.
294 *
295 * Register|BitsName
296 * --------|--------
297 * RTC_ALARM_W | CAL_ALARM
298 *
299 * @param RTCx RTC instance
300 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
301 */
302 __STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t* RTCx)
303 {
304 return (uint32_t)READ_REG(RTCx->ALARM_W);
305 }
306
307 /**
308 * @brief Read the RTC counter current alarm value.
309 *
310 * Register|BitsName
311 * --------|--------
312 * RTC_ALARM_R | CAL_ALARM
313 *
314 * @param RTCx RTC instance
315 * @retval Value for current alarm which should ranging between 0 ~ 0xFFFF_FFFF
316 */
317 __STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t* RTCx)
318 {
319 return (uint32_t)READ_REG(RTCx->ALARM_R);
320 }
321
322 /**
323 * @brief Read the RTC counter config tick value.
324 *
325 * Register|BitsName
326 * --------|--------
327 * RTC_TICK_W | TICK_SET
328 *
329 * @param RTCx RTC instance
330 * @retval Value for current tick which should ranging between 0 ~ 0xFFFF_FFFF
331 */
332 __STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t* RTCx)
333 {
334 return (uint32_t)READ_REG(RTCx->TICK_W);
335 }
336
337 /**
338 * @brief Read the RTC counter current tick value.
339 *
340 * Register|BitsName
341 * --------|--------
342 * RTC_TICK_R | TICK_RD
343 *
344 * @param RTCx RTC instance
345 * @retval Value for current tick which should ranging between 0 ~ 0xFFFF_FFFF
346 */
347 __STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t* RTCx)
348 {
349 return (uint32_t)READ_REG(RTCx->TICK_R);
350 }
351
352 /**
353 * @brief Get the RTC wrap-around value.
354 * @note The value should be read multiple times until get the same value in at least two reads.
355 *
356 * Register|BitsName
357 * --------|--------
358 * RTC_STAT | WRAP_CNT
359 *
360 * @param RTCx RTC instance
361 * @retval Value between Min_Data=0 and Max_Data=0xF
362 */
363 __STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t* RTCx)
364 {
365 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
366 }
367
368 /**
369 * @brief The RTC is busy.
370 *
371 * Register|BitsName
372 * --------|--------
373 * RTC_STAT | BUSY
374 *
375 * @param RTCx RTC instance
376 * @retval Value between Min_Data=0 and Max_Data=0xF
377 */
378 __STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t* RTCx)
379 {
380 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
381 }
382
383 /**
384 * @brief The RTC is running.
385 *
386 * Register|BitsName
387 * --------|--------
388 * RTC_STAT | RUNNING
389 *
390 * @param RTCx RTC instance
391 * @retval Value between Min_Data=0 and Max_Data=0xF
392 */
393 __STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t* RTCx)
394 {
395 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
396 }
397
398 /**
399 * @brief CLear RTC wrap.
400 *
401 * Register|BitsName
402 * --------|--------
403 * RTC_CFG0 | Wrap counter clear
404 *
405 * @param RTCx RTC instance
406 * @retval None
407 */
408
409 __STATIC_INLINE void ll_rtc_clear_wrap_and_request(rtc_regs_t* RTCx)
410 {
411 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_WRAP_CLR | (READ_CFG0_CFG(RTCx)));
412 }
413
414 /**
415 * @brief Select the RTC clock divider.
416 *
417 * Register|BitsName
418 * --------|--------
419 * RTC_CFG1 | CLK_SEL
420 *
421 * @param RTCx RTC instance
422 * @param div This parameter can be one of the following values:
423 * @arg @ref LL_RTC_DIV_NONE
424 * @arg @ref LL_RTC_DIV_2
425 * @arg @ref LL_RTC_DIV_4
426 * @arg @ref LL_RTC_DIV_8
427 * @arg @ref LL_RTC_DIV_16
428 * @arg @ref LL_RTC_DIV_32
429 * @arg @ref LL_RTC_DIV_64
430 * @arg @ref LL_RTC_DIV_128
431 * @retval None
432 */
433 __STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t* RTCx, uint32_t div)
434 {
435 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
436 }
437
438 /**
439 * @brief Set RTC alarm.
440 *
441 * Register|BitsName
442 * --------|--------
443 * RTC_TIMER_CTL | ALARM_EN
444 *
445 * @param RTCx RTC instance
446 * @param value RTC alarm value
447 * @retval None
448 */
449 __STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t* RTCx, uint32_t value)
450 {
451 WRITE_REG(RTCx->ALARM_W, value);
452 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET | (READ_CFG0_CFG(RTCx)));
453 }
454
455 /**
456 * @brief Enable RTC alarm interrupt.
457 *
458 * Register|BitsName
459 * --------|--------
460 * RTC_TIMER_CTL | ALARM_INT_EN
461 *
462 * @param RTCx RTC instance
463 * @retval None
464 */
465 __STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t* RTCx)
466 {
467 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
468 }
469
470 /**
471 * @brief Disable RTC alarm.
472 *
473 * Register|BitsName
474 * --------|--------
475 * RTC_TIMER_CTL | ALARM_DISBALE
476 *
477 * @param RTCx RTC instance
478 * @retval None
479 */
480 __STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t* RTCx)
481 {
482 WRITE_REG(RTCx->CFG0, ((READ_CFG0_CFG(RTCx)) & (~RTC_CFG0_ALARM_EN) & (~RTC_CFG0_ALARM_SET)) | RTC_CFG0_CFG);
483 }
484
485 /**
486 * @brief Disable RTC alarm interrupt.
487 *
488 * Register|BitsName
489 * --------|--------
490 * RTC_INT_EN | ALARM_INT_EN
491 *
492 * @param RTCx RTC instance
493 * @retval None
494 */
495 __STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t* RTCx)
496 {
497 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
498 }
499
500 /**
501 * @brief Check if the RTC alarm interrupt is enabled or disabled.
502 *
503 * Register|BitsName
504 * --------|--------
505 * RTC_TIMER_CTL | ALARM_INT_EN
506 *
507 * @param RTCx RTC instance
508 * @retval State of bit (1 or 0).
509 */
510 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t* RTCx)
511 {
512 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
513 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
514 }
515
516 /**
517 * @brief Set RTCx alarm_mode.
518 *
519 * Register|BitsName
520 * --------|--------
521 * RTCx_TIMER_CTL | TICK_EN
522 *
523 * @param RTCx RTC instance
524 * @param tick_mode This parameter can be a one of the following values:
525 * @arg @ref LL_RTC_TIMER_TICK_TYPE_SINGLE
526 * @arg @ref LL_RTC_TIMER_TICK_TYPE_AUTO
527 * @retval None
528 */
529 __STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t* RTCx, uint8_t tick_mode)
530 {
531 if(0 == tick_mode)
532 {
533 CLEAR_BITS(RTCx->CFG0, ((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
534 }
535 else
536 {
537 SET_BITS(RTCx->CFG0, (tick_mode << RTC_CFG0_TICK_MDOE_Pos));
538 }
539 }
540
541 /**
542 * @brief Enable RTC tick interrupt.
543 *
544 * Register|BitsName
545 * --------|--------
546 * RTC_INT_EN | TICK_INT_EN
547 *
548 * @param RTCx RTC instance
549 * @retval None
550 */
551 __STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t* RTCx)
552 {
553 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
554 }
555
556 /**
557 * @brief Disable RTCx tick.
558 *
559 * Register|BitsName
560 * --------|--------
561 * RTCx_TIMER_CTL | TICK_EN
562 *
563 * @param RTCx RTC instance
564 * @retval None
565 */
566 __STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t* RTCx)
567 {
568 WRITE_REG(RTCx->CFG0, ((READ_CFG0_CFG(RTCx)) & (~RTC_CFG0_TICK_EN) & (~RTC_CFG0_TICK_SET)) | RTC_CFG0_CFG);
569 }
570
571 /**
572 * @brief Disable RTC tick interrupt.
573 *
574 * Register|BitsName
575 * --------|--------
576 * RTC_INT_EN | TICK0_INT_EN
577 *
578 * @param RTCx RTC instance
579 * @retval None
580 */
581 __STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t* RTCx)
582 {
583 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
584 }
585
586 /**
587 * @brief Check if the RTC alarm interrupt is enabled or disabled.
588 *
589 * Register|BitsName
590 * --------|--------
591 * RTC_TIMER_CTL | TICK_EN
592 * RTC_INT_EN | TICK_INT_EN
593 *
594 * @param RTCx RTC instance
595 * @retval State of bit (1 or 0).
596 */
597 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t* RTCx)
598 {
599 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
600 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
601 }
602
603 /**
604 * @brief Reloads RTCx tick counter and request.
605 *
606 * Register|BitsName
607 * --------|--------
608 * RTCx_TIMER_W | TIMER_VALUE
609 * RTCx_CFG0 | VAL_LOAD
610 *
611 * @param RTCx RTC instance
612 * @param tick_reload RTC tick counter
613 * @retval None
614 */
615 __STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t* RTCx, uint32_t tick_reload)
616 {
617 WRITE_REG(RTCx->TICK_W, tick_reload);
618 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET | (READ_CFG0_CFG(RTCx)));
619 }
620
621 /**
622 * @brief Restart RTCx tick counter and request.
623 *
624 * Register|BitsName
625 * --------|--------
626 * RTCx_CFG0 | RTC_CFG0_TICK_EN
627 *
628 * @param RTCx RTC instance
629 * @retval None
630 */
631 __STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t* RTCx)
632 {
633 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN | (READ_CFG0_CFG(RTCx)));
634 }
635
636 /**
637 * @brief Enable RTC wrap interrupt.
638 *
639 * Register|BitsName
640 * --------|--------
641 * RTC_TIMER_CTL | WRAP_INT_EN
642 *
643 * @param RTCx RTC instance
644 * @retval None
645 */
646 __STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t* RTCx)
647 {
648 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
649 }
650
651 /**
652 * @brief Disable RTC wrap interrupt.
653 *
654 * Register|BitsName
655 * --------|--------
656 * RTC_TIMER_CTL | WRAP_INT_EN
657 *
658 * @param RTCx RTC instance
659 * @retval None
660 */
661 __STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t* RTCx)
662 {
663 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
664 }
665
666 /**
667 * @brief Check if the RTC wrap interrupt is enabled or disabled.
668 *
669 * Register|BitsName
670 * --------|--------
671 * RTC_TIMER_CTL | WRAP_INT_EN
672 *
673 * @param RTCx RTC instance
674 * @retval State of bit (1 or 0).
675 */
676 __STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t* RTCx)
677 {
678 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
679 }
680
681 /** @} */
682
683 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
684 * @{
685 */
686
687 /**
688 * @brief Indicate if the RTC alarm event flag is set or not.
689 * @note This bit is set by hardware when the counter has reached alarm value.
690 * It can be cleared by writing 0 to this bit.
691 *
692 * Register|BitsName
693 * --------|--------
694 * SLP_EVENT | RTC_TIMER_ALARM
695 *
696 * @param RTCx RTC instance
697 * @retval State of bit (1 or 0).
698 */
699 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t* RTCx)
700 {
701 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
702 }
703
704 /**
705 * @brief Indicate if the RTC wrap event flag is set or not.
706 * @note This bit is set by hardware when the counter has overflow.
707 * It can be cleared by writing 0 to this bit.
708 *
709 * Register|BitsName
710 * --------|--------
711 * SLP_EVENT | CALENDAR_TIMER_WRAP
712 *
713 * @param RTCx RTC instance
714 * @retval State of bit (1 or 0).
715 */
716 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t* RTCx)
717 {
718 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
719 }
720
721 /**
722 * @brief Indicate if the RTC tick event flag is set or not.
723 * @note This bit is set by hardware when the counter has reached to 0.
724 * It can be cleared by writing 1 to this bit.
725 *
726 * Register|BitsName
727 * --------|--------
728 * RTC_INT_STAT | TICK_INT_STAT
729 *
730 * @param RTCx RTC instance
731 * @retval State of bit (1 or 0).
732 */
733 __STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t* RTCx)
734 {
735 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
736 }
737
738 /**
739 * @brief Clear RTC alarm interrupt flag.
740 *
741 * Register|BitsName
742 * --------|--------
743 * SLP_EVENT| RTC_TIMER_ALARM
744 *
745 * @param RTCx RTC instance
746 * @retval None
747 */
748 __STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t* RTCx)
749 {
750 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
751 }
752
753 /**
754 * @brief Clear RTC wrap interrupt flag.
755 *
756 * Register|BitsName
757 * --------|--------
758 * RTC_INT_STAT| RTC_TICK
759 *
760 * @param RTCx RTC instance
761 * @retval None
762 */
763 __STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t* RTCx)
764 {
765 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
766 }
767
768 /**
769 * @brief Clear RTC tick interrupt flag.
770 *
771 * Register|BitsName
772 * --------|--------
773 * SLP_EVENT| RTC_TIMER_WRAP
774 *
775 * @param RTCx RTC instance
776 * @retval None
777 */
778 __STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t* RTCx)
779 {
780 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
781 }
782
783 /**
784 * @brief Clear RTC interrupt event.
785 *
786 * Register|BitsName
787 * --------|--------
788 * AON_MISC | AON_SLP_EVENT
789 *
790 * @param RTCx RTC instance
791 * @retval None
792 */
793 __STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t* RTCx)
794 {
795 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
796 }
797
798 /**
799 * @brief Clear RTC tick interrupt event.
800 *
801 * Register|BitsName
802 * --------|--------
803 * AON_MISC | AON_SLP_EVENT
804 *
805 * @param RTCx RTC instance
806 * @retval None
807 */
808 __STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t* RTCx)
809 {
810 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
811 }
812
813 /**
814 * @brief Enable RTC alarm wakeup interrupt.
815 *
816 * Register|BitsName
817 * --------|--------
818 * AON_MISC | MCU_WAKEUP_CTRL
819 *
820 * @param RTCx RTC instance
821 * @retval None
822 */
823 __STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t* RTCx)
824 {
825 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
826 }
827
828 /**
829 * @brief Disable RTC alarm wakeup interrupt.
830 *
831 * Register|BitsName
832 * --------|--------
833 * AON_MISC | MCU_WAKEUP_CTRL
834 *
835 * @param RTCx RTC instance
836 * @retval None
837 */
838 __STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t* RTCx)
839 {
840 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
841 }
842
843 /** @} */
844
845 /** @} */
846
847
848 #ifdef __cplusplus
849 }
850 #endif
851
852 #endif /* __GR55XX_LL_RTC_H__ */
853
854 /** @} */
855
856 /** @} */
857
858 /** @} */
ll_rtc_tick_value_set_and_request
__STATIC_INLINE void ll_rtc_tick_value_set_and_request(rtc_regs_t *RTCx, uint32_t alarm_value)
Reloads RTC tick and request.
Definition: gr533x_ll_rtc.h:256
ll_rtc_it_is_enabled_tick
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_tick(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr533x_ll_rtc.h:597
ll_rtc_is_running
__STATIC_INLINE uint32_t ll_rtc_is_running(rtc_regs_t *RTCx)
The RTC is running.
Definition: gr533x_ll_rtc.h:393
ll_rtc_disable_tick
__STATIC_INLINE void ll_rtc_disable_tick(rtc_regs_t *RTCx)
Disable RTCx tick.
Definition: gr533x_ll_rtc.h:566
ll_rtc_reload_counter
__STATIC_INLINE void ll_rtc_reload_counter(rtc_regs_t *RTCx, uint32_t counter)
Reloads RTC counter.
Definition: gr533x_ll_rtc.h:171
ll_rtc_get_wrapcnt
__STATIC_INLINE uint32_t ll_rtc_get_wrapcnt(rtc_regs_t *RTCx)
Get the RTC wrap-around value.
Definition: gr533x_ll_rtc.h:363
ll_rtc_is_active_flag_alarm
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_alarm(rtc_regs_t *RTCx)
Indicate if the RTC alarm event flag is set or not.
Definition: gr533x_ll_rtc.h:699
ll_rtc_get_write_alarm
__STATIC_INLINE uint32_t ll_rtc_get_write_alarm(rtc_regs_t *RTCx)
Read the RTC counter config alarm value.
Definition: gr533x_ll_rtc.h:302
ll_rtc_get_read_counter
__STATIC_INLINE uint32_t ll_rtc_get_read_counter(rtc_regs_t *RTCx)
Read the RTC counter current value.
Definition: gr533x_ll_rtc.h:287
ll_rtc_is_busy
__STATIC_INLINE uint32_t ll_rtc_is_busy(rtc_regs_t *RTCx)
The RTC is busy.
Definition: gr533x_ll_rtc.h:378
ll_rtc_clear_tick_it_event
__STATIC_INLINE void ll_rtc_clear_tick_it_event(rtc_regs_t *RTCx)
Clear RTC tick interrupt event.
Definition: gr533x_ll_rtc.h:808
ll_rtc_reload_alarm
__STATIC_INLINE void ll_rtc_reload_alarm(rtc_regs_t *RTCx, uint32_t value)
Reloads RTC alarm.
Definition: gr533x_ll_rtc.h:205
ll_rtc_it_is_enabled_alarm
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_alarm(rtc_regs_t *RTCx)
Check if the RTC alarm interrupt is enabled or disabled.
Definition: gr533x_ll_rtc.h:510
ll_rtc_it_disable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_disable_wakeup_by_rtc(rtc_regs_t *RTCx)
Disable RTC alarm wakeup interrupt.
Definition: gr533x_ll_rtc.h:838
ll_rtc_enable
__STATIC_INLINE void ll_rtc_enable(rtc_regs_t *RTCx)
Enable RTC counter.
Definition: gr533x_ll_rtc.h:125
ll_rtc_clear_wrap_and_request
__STATIC_INLINE void ll_rtc_clear_wrap_and_request(rtc_regs_t *RTCx)
CLear RTC wrap.
Definition: gr533x_ll_rtc.h:409
ll_rtc_it_enable_wakeup_by_rtc
__STATIC_INLINE void ll_rtc_it_enable_wakeup_by_rtc(rtc_regs_t *RTCx)
Enable RTC alarm wakeup interrupt.
Definition: gr533x_ll_rtc.h:823
ll_rtc_clear_flag_tick
__STATIC_INLINE void ll_rtc_clear_flag_tick(rtc_regs_t *RTCx)
Clear RTC tick interrupt flag.
Definition: gr533x_ll_rtc.h:778
ll_rtc_clear_it_event
__STATIC_INLINE void ll_rtc_clear_it_event(rtc_regs_t *RTCx)
Clear RTC interrupt event.
Definition: gr533x_ll_rtc.h:793
ll_rtc_it_enable_tick
__STATIC_INLINE void ll_rtc_it_enable_tick(rtc_regs_t *RTCx)
Enable RTC tick interrupt.
Definition: gr533x_ll_rtc.h:551
ll_rtc_it_is_enabled_wrap
__STATIC_INLINE uint32_t ll_rtc_it_is_enabled_wrap(rtc_regs_t *RTCx)
Check if the RTC wrap interrupt is enabled or disabled.
Definition: gr533x_ll_rtc.h:676
ll_rtc_it_enable_wrap
__STATIC_INLINE void ll_rtc_it_enable_wrap(rtc_regs_t *RTCx)
Enable RTC wrap interrupt.
Definition: gr533x_ll_rtc.h:646
ll_rtc_clear_flag_wrap
__STATIC_INLINE void ll_rtc_clear_flag_wrap(rtc_regs_t *RTCx)
Clear RTC wrap interrupt flag.
Definition: gr533x_ll_rtc.h:763
ll_rtc_is_enabled
__STATIC_INLINE uint32_t ll_rtc_is_enabled(rtc_regs_t *RTCx)
Check if the RTC peripheral is enabled or disabled.
Definition: gr533x_ll_rtc.h:155
ll_rtc_get_write_counter
__STATIC_INLINE uint32_t ll_rtc_get_write_counter(rtc_regs_t *RTCx)
Read the RTC counter config value.
Definition: gr533x_ll_rtc.h:272
ll_rtc_it_disable_wrap
__STATIC_INLINE void ll_rtc_it_disable_wrap(rtc_regs_t *RTCx)
Disable RTC wrap interrupt.
Definition: gr533x_ll_rtc.h:661
ll_rtc_is_active_flag_wrap
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_wrap(rtc_regs_t *RTCx)
Indicate if the RTC wrap event flag is set or not.
Definition: gr533x_ll_rtc.h:716
ll_rtc_set_alarm
__STATIC_INLINE void ll_rtc_set_alarm(rtc_regs_t *RTCx, uint32_t value)
Set RTC alarm.
Definition: gr533x_ll_rtc.h:449
ll_rtc_it_disable_alarm
__STATIC_INLINE void ll_rtc_it_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm interrupt.
Definition: gr533x_ll_rtc.h:495
READ_CFG0_CFG
#define READ_CFG0_CFG(RTCx)
LL RTC Read CFG.
Definition: gr533x_ll_rtc.h:96
ll_rtc_alarm_value_set_and_request
__STATIC_INLINE void ll_rtc_alarm_value_set_and_request(rtc_regs_t *RTCx, uint32_t alarm_value)
Reloads RTC alarm and request.
Definition: gr533x_ll_rtc.h:222
ll_rtc_it_enable_alarm
__STATIC_INLINE void ll_rtc_it_enable_alarm(rtc_regs_t *RTCx)
Enable RTC alarm interrupt.
Definition: gr533x_ll_rtc.h:465
ll_rtc_get_read_alarm
__STATIC_INLINE uint32_t ll_rtc_get_read_alarm(rtc_regs_t *RTCx)
Read the RTC counter current alarm value.
Definition: gr533x_ll_rtc.h:317
ll_rtc_get_read_tick
__STATIC_INLINE uint32_t ll_rtc_get_read_tick(rtc_regs_t *RTCx)
Read the RTC counter current tick value.
Definition: gr533x_ll_rtc.h:347
ll_rtc_set_tick_mode
__STATIC_INLINE void ll_rtc_set_tick_mode(rtc_regs_t *RTCx, uint8_t tick_mode)
Set RTCx alarm_mode.
Definition: gr533x_ll_rtc.h:529
ll_rtc_get_write_tick
__STATIC_INLINE uint32_t ll_rtc_get_write_tick(rtc_regs_t *RTCx)
Read the RTC counter config tick value.
Definition: gr533x_ll_rtc.h:332
ll_rtc_is_active_flag_tick
__STATIC_INLINE uint32_t ll_rtc_is_active_flag_tick(rtc_regs_t *RTCx)
Indicate if the RTC tick event flag is set or not.
Definition: gr533x_ll_rtc.h:733
ll_rtc_set_clock_div
__STATIC_INLINE void ll_rtc_set_clock_div(rtc_regs_t *RTCx, uint32_t div)
Select the RTC clock divider.
Definition: gr533x_ll_rtc.h:433
ll_rtc_restart_tick
__STATIC_INLINE void ll_rtc_restart_tick(rtc_regs_t *RTCx)
Restart RTCx tick counter and request.
Definition: gr533x_ll_rtc.h:631
ll_rtc_disable_alarm
__STATIC_INLINE void ll_rtc_disable_alarm(rtc_regs_t *RTCx)
Disable RTC alarm.
Definition: gr533x_ll_rtc.h:480
ll_rtc_reload_tick
__STATIC_INLINE void ll_rtc_reload_tick(rtc_regs_t *RTCx, uint32_t tick)
Reloads RTC perd_alarm.
Definition: gr533x_ll_rtc.h:239
ll_rtc_start_value_set_and_request
__STATIC_INLINE void ll_rtc_start_value_set_and_request(rtc_regs_t *RTCx, uint32_t start_value)
Reloads RTC counter and request.
Definition: gr533x_ll_rtc.h:188
ll_rtc_clear_flag_alarm
__STATIC_INLINE void ll_rtc_clear_flag_alarm(rtc_regs_t *RTCx)
Clear RTC alarm interrupt flag.
Definition: gr533x_ll_rtc.h:748
ll_rtc_it_disable_tick
__STATIC_INLINE void ll_rtc_it_disable_tick(rtc_regs_t *RTCx)
Disable RTC tick interrupt.
Definition: gr533x_ll_rtc.h:581
ll_rtc_reload_tick_and_request
__STATIC_INLINE void ll_rtc_reload_tick_and_request(rtc_regs_t *RTCx, uint32_t tick_reload)
Reloads RTCx tick counter and request.
Definition: gr533x_ll_rtc.h:615
ll_rtc_disable
__STATIC_INLINE void ll_rtc_disable(rtc_regs_t *RTCx)
Disable RTC counter.
Definition: gr533x_ll_rtc.h:140