gr533x_ll_cgc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_cgc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CGC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_CGC CGC
47 * @brief CGC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_CGC_H__
53 #define __GR533X_LL_CGC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined(MCU_SUB)
63
64 /**
65 * @defgroup CGC_LL_MACRO Defines
66 * @{
67 */
68
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup CGC_LL_Exported_Constants CGC Exported Constants
71 * @{
72 */
73
74 /** @defgroup CGC_LL_EC_WFI_CLK0 Block0 Clock During WFI
75 * @{
76 */
77 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK /**< Hclk for all security blocks */
78 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK /**< Hclk for hopping table */
79 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK /**< Hclk for ROM */
80 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK /**< Hclk for sense ADC */
81 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK /**< Hclk for GPIOs */
82 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
83 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK /**< Hclk for APB subsystem */
84 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK /**< Hclk for serial blocks */
85 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x000007FFU) /**< All clock group 0 */
86
87 /** @} */
88
89 /** @defgroup CGC_LL_EC_WFI_CLK1 Block1 Clock During WFI
90 * @{
91 */
92 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
93 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK /**< Hclk for cache top */
94 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK /**< Hclk for SRAMs */
95
96 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U) /**< All clock group 1 */
97 /** @} */
98
99
100 /** @defgroup CGC_LL_EC_FRC_CLK0 Force Clock OFF
101 * @{
102 */
103 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK /**< Hclk for all security blocks */
104 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK /**< Hclk for hopping table */
105 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK /**< Hclk for ROM */
106 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK /**< Hclk for sense ADC */
107 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK /**< Hclk for GPIOs */
108 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
109 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK /**< Hclk for APB subsystem */
110 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK /**< Hclk for serial blocks */
111 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000775U) /**< All clock group 0 */
112 /** @} */
113
114 /** @defgroup CGC_LL_EC_FRC_CLK1 Force Clock OFF
115 * @{
116 */
117 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK /**< Hclk for cache top */
118 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK /**< Hclk for SRAMs */
119
120 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00060000U) /**< All clock group 1 */
121 /** @} */
122
123 /** @defgroup CGC_LL_EC_FRC_CLK2 Force Clock OFF
124 * @{
125 */
126 #define LL_CGC_FRC_UART0_PCLK MCU_SUB_FORCE_UART0_PCLK /**< Pclk for uart0 */
127 #define LL_CGC_FRC_UART1_PCLK MCU_SUB_FORCE_UART1_PCLK /**< Pclk for uart1 */
128 #define LL_CGC_FRC_I2C0_PCLK MCU_SUB_FORCE_I2C0_PCLK /**< Hclk for i2c0 */
129 #define LL_CGC_FRC_I2C1_PCLK MCU_SUB_FORCE_I2C1_PCLK /**< Hclk for i2c1 */
130 #define LL_CGC_FRC_SPI_M_PCLK MCU_SUB_FORCE_SPI_M_PCLK /**< Hclk for spim */
131 #define LL_CGC_FRC_SPI_S_PCLK MCU_SUB_FORCE_SPI_S_PCLK /**< Hclk for spis */
132 #define LL_CGC_FRC_PWM_0_PCLK MCU_SUB_FORCE_PWM_0_PCLK /**< Pclk for PWM0 */
133 #define LL_CGC_FRC_PWM_1_PCLK MCU_SUB_FORCE_PWM_1_PCLK /**< Pclk for PWM1 */
134 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x30063005UL) /**< Hclk for serial blocks */
135 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x30063005UL) /**< All clock group 2 */
136 /** @} */
137
138 /** @defgroup CGC_LL_PERIPH_CG_LP_EN Low Power Feature
139 * @{
140 */
141 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN /**< Enable AHB2APB ASYNC low-power feature */
142 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN /**< Enable AHB2APB SYNC low-power feature */
143 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN /**< Enable AHB bus low-power feature */
144 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN /**< Enable i2c sclk low-power feature */
145 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN /**< Enable spis sclk low-power feature */
146 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN /**< Enable spim sclk low-power feature */
147 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN /**< Enable uart pclk low-power feature */
148 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN /**< Enable uart sclk low-power feature */
149 /** @} */
150
151 #define LL_CGC_MCU_PERIPH_CG_LP ((uint32_t)0x00000D3BUL) /**< All Low Power Feature */
152
153 /** @defgroup CGC_LL_SUBSYS_PERI_CLK_SLP_OFF Turn the peripherals off during WFI/WFE
154 * @{
155 */
156 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 /**< Turn the uart0 off during WFI/WFE */
157 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 /**< Turn the uart1 off during WFI/WFE */
158 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM /**< Turn the spi_m off during WFI/WFE */
159 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS /**< Turn the spi_s off during WFI/WFE */
160 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 /**< Turn the pwm0 off during WFI/WFE */
161 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 /**< Turn the pwm1 off during WFI/WFE */
162 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 /**< Turn the i2c0 off during WFI/WFE */
163 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 /**< Turn the i2c1 off during WFI/WFE */
164
165 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_OFF ((uint32_t)0x00003CC3UL) /**< Serial blocks */
166 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL ((uint32_t)0x00003CC3UL) /**< Serial blocks */
167 /** @} */
168
169 /** @defgroup CGC_LL_SUBSYS_SECU_CLK_CTRL Individual block's clock control inside security system
170 * @{
171 */
172 #define LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF /**< Force individual rng's clock control */
173 #define LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF /**< Individual rng's clock control */
174 #define LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF /**< Force individual efuse's clock control */
175 #define LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF /**< Individual efuse's clock control */
176
177 #define LL_CGC_MCU_SECU_FRC_OFF_HCLK ((uint32_t)0x00001400U) /**< Hclk for security clock */
178 #define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK ((uint32_t)0x00002800U) /**< Hclk for security clock WFI/WFE */
179
180 #define LL_CGC_MCU_SECU_FRC_OFF_ALL (LL_CGC_MCU_SECU_FRC_OFF_HCLK |\
181 LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK) /**< Hclk for security clock */
182 /** @} */
183
184 #define LL_CGC_MCU_MISC_CLK_DEFAULT ((uint32_t)0x00000008U) /**< Hclk for msic default clock */
185
186 #define LL_CGC_MCU_MISC_CLK ((uint32_t)0x0000000CU) /**< Hclk for msic all clock */
187
188 #define LL_CGC_MCU_MISC_DMA_CLK ((uint32_t)0x00000008U) /**< Hclk for msic dma clock */
189
190 /** @defgroup CGC_LL_SUBSYS_DEFAULT_CLK Specify the default system clock when the system is initialized
191 * @{
192 */
193
194
195 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0 (LL_CGC_WFI_SECU_HCLK |\
196 LL_CGC_WFI_SNSADC_HCLK |\
197 LL_CGC_WFI_GPIO_HCLK |\
198 LL_CGC_WFI_BLE_BRG_HCLK |\
199 LL_CGC_WFI_SERIAL_HCLK) /**< Hclk0 for the system default clock WFI/WFE */
200
201 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1 (LL_CGC_WFI_AON_MCUSUB_HCLK |\
202 LL_CGC_WFI_XF_XQSPI_HCLK) /**< Hclk1 for the system default clock WFI/WFE */
203
204
205 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK (LL_CGC_FRC_SECU_HCLK |\
206 LL_CGC_FRC_SNSADC_HCLK |\
207 LL_CGC_FRC_SERIAL_HCLK) /**< Hclk for the system default clock */
208
209
210
211 #define LL_CGC_MCU_PERIPH_CG_DEFAULT (LL_CGC_FRC_UART0_PCLK |\
212 LL_CGC_FRC_UART1_PCLK |\
213 LL_CGC_FRC_I2C0_PCLK |\
214 LL_CGC_FRC_I2C1_PCLK |\
215 LL_CGC_FRC_SPI_M_PCLK |\
216 LL_CGC_FRC_SPI_S_PCLK |\
217 LL_CGC_FRC_PWM_0_PCLK |\
218 LL_CGC_FRC_PWM_1_PCLK) /**< pclk for the system default periph clock */
219
220 #define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT (MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
221 MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
222 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
223 MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
224 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
225 MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
226 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
227 MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1) /**< pclk for the system default periph wfi clock */
228
229
230
231 #define CGC_CLOCK_ENABLE (1) /**< Bit segment address enable */
232 #define CGC_CLOCK_DISABLE (0) /**< Bit segment address disable */
233
234 #define BIT_SEGMENT_VALUE BIT_ADDR /**< Bit segment address value manipulation */
235
236 /** @} */
237
238 /** @} */
239
240 /** @} */
241
242 /* Private types -------------------------------------------------------------*/
243 /* Private variables ---------------------------------------------------------*/
244 /* Private constants ---------------------------------------------------------*/
245 /* Private macros ------------------------------------------------------------*/
246 /* Exported functions --------------------------------------------------------*/
247 /** @defgroup CGC_LL_DRIVER_FUNCTIONS Functions
248 * @{
249 */
250
251 /**
252 * @brief Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/
253 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
254 *
255 * Register | BitsName
256 * ----------|--------
257 * CG_CTRL_0 | SECU_HCLK
258 * CG_CTRL_0 | SIM_HCLK
259 * CG_CTRL_0 | HTB_HCLK
260 * CG_CTRL_0 | PWM_HCLK
261 * CG_CTRL_0 | ROM_HCLK
262 * CG_CTRL_0 | SNSADC_HCLK
263 * CG_CTRL_0 | GPIO_HCLK
264 * CG_CTRL_0 | DMA_HCLK
265 * CG_CTRL_0 | BLE_BRG_HCLK
266 * CG_CTRL_0 | APB_SUB_HCLK
267 * CG_CTRL_0 | SERIAL_HCLK
268 *
269 * @param clk_mask This parameter can be a combination of the following values:
270 * @arg @ref LL_CGC_WFI_SECU_HCLK
271 * @arg @ref LL_CGC_WFI_HTB_HCLK
272 * @arg @ref LL_CGC_WFI_ROM_HCLK
273 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
274 * @arg @ref LL_CGC_WFI_GPIO_HCLK
275 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
276 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
277 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
278 * @retval None
279 */
280 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
281 {
282 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], LL_CGC_WFI_ALL_HCLK0, clk_mask);
283 }
284
285 /**
286 * @brief Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/
287 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
288 *
289 * Register | BitsName
290 * ----------|--------
291 * CG_CTRL_0 | SECU_HCLK
292 * CG_CTRL_0 | SIM_HCLK
293 * CG_CTRL_0 | HTB_HCLK
294 * CG_CTRL_0 | PWM_HCLK
295 * CG_CTRL_0 | ROM_HCLK
296 * CG_CTRL_0 | SNSADC_HCLK
297 * CG_CTRL_0 | GPIO_HCLK
298 * CG_CTRL_0 | DMA_HCLK
299 * CG_CTRL_0 | BLE_BRG_HCLK
300 * CG_CTRL_0 | APB_SUB_HCLK
301 * CG_CTRL_0 | SERIAL_HCLK
302 *
303 * @retval Returned value can be a combination of the following values:
304 * @arg @ref LL_CGC_WFI_SECU_HCLK
305 * @arg @ref LL_CGC_WFI_HTB_HCLK
306 * @arg @ref LL_CGC_WFI_ROM_HCLK
307 * @arg @ref LL_CGC_WFI_SNSADC_HCLK
308 * @arg @ref LL_CGC_WFI_GPIO_HCLK
309 * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
310 * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
311 * @arg @ref LL_CGC_WFI_SERIAL_HCLK
312 */
313 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
314 {
315 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0]);
316 }
317
318 /**
319 * @brief Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
320 *
321 * Register | BitsName
322 * ----------|--------
323 * CG_CTRL_2 | AON_MCUSUB_HCLK
324 * CG_CTRL_2 | XF_XQSPI_HCLK
325 * CG_CTRL_2 | SRAM_HCLK
326 *
327 * @param clk_mask This parameter can be a combination of the following values:
328 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
329 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
330 * @arg @ref LL_CGC_WFI_SRAM_HCLK
331 * @retval None
332 */
333 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
334 {
335 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1, clk_mask);
336 }
337
338 /**
339 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
340 *
341 * Register | BitsName
342 * ----------|--------
343 * CG_CTRL_2 | AON_MCUSUB_HCLK
344 * CG_CTRL_2 | XF_XQSPI_HCLK
345 * CG_CTRL_2 | SRAM_HCLK
346 *
347 * @retval Returned value can be a combination of the following values:
348 * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
349 * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
350 * @arg @ref LL_CGC_WFI_SRAM_HCLK
351 */
352 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
353 {
354 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1);
355 }
356
357 /**
358 * @brief Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
359 *
360 * Register | BitsName
361 * ----------|--------
362 * PERIPH_GC | SECU_DIV4_PCLK
363 * PERIPH_GC | XQSPI_DIV4_PCLK
364 *
365 * @param clk_mask This parameter can be a combination of the following values:
366 * @retval None
367 */
368 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
369 {
370 }
371
372 /**
373 * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
374 *
375 * Register | BitsName
376 * ----------|--------
377 * PERIPH_GC | SECU_DIV4_PCLK
378 * PERIPH_GC | XQSPI_DIV4_PCLK
379 *
380 * @retval Returned value can be a combination of the following values:
381 */
382 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
383 {
384 return 0;
385 }
386
387 /**
388 * @brief Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI.etc)
389 *
390 * Register | BitsName
391 * ----------|--------
392 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
393 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
394 *
395 * @param clk_mask This parameter can be a combination of the following values:
396 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
397 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
398 * .....
399 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF
400 * @retval None
401 */
402 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
403 {
404 MODIFY_REG(MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL, clk_mask);
405 }
406
407 /**
408 * @brief Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI.etc)
409 *
410 * Register | BitsName
411 * ----------|--------
412 * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
413 * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
414 *
415 * @retval Returned value can be a combination of the following values:
416 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
417 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
418 * .....
419 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF
420 */
421 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
422 {
423 return READ_BITS(MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL);
424 }
425
426 /**
427 * @brief Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
428 *
429 * Register | BitsName
430 * ----------|--------
431 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
432 *
433 * @param clk_mask This parameter can be a combination of the following values:
434 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
435 * .....
436 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
437 * @retval None
438 */
439 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
440 {
441 MODIFY_REG(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
442 }
443
444 /**
445 * @brief Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
446 *
447 * Register | BitsName
448 * ----------|--------
449 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
450 *
451 * @retval Returned value can be a combination of the following values:
452 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
453 * .....
454 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
455 */
456 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
457 {
458 return READ_BITS(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
459 }
460
461 /**
462 * @brief Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/
463 * DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
464 *
465 * Register | BitsName
466 * ----------|--------
467 * CG_CTRL_1 | SECU_HCLK
468 * CG_CTRL_1 | SIM_HCLK
469 * CG_CTRL_1 | HTB_HCLK
470 * CG_CTRL_1 | ROM_HCLK
471 * CG_CTRL_1 | SNSADC_HCLK
472 * CG_CTRL_1 | GPIO_HCLK
473 * CG_CTRL_1 | DMA_HCLK
474 * CG_CTRL_1 | BLE_BRG_HCLK
475 * CG_CTRL_1 | APB_SUB_HCLK
476 * CG_CTRL_1 | SERIAL_HCLK
477 *
478 * @param clk_mask This parameter can be a combination of the following values:
479 * @arg @ref LL_CGC_FRC_SECU_HCLK
480 * @arg @ref LL_CGC_FRC_HTB_HCLK
481 * @arg @ref LL_CGC_FRC_ROM_HCLK
482 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
483 * @arg @ref LL_CGC_FRC_GPIO_HCLK
484 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
485 * @retval None
486 */
487 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
488 {
489 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], LL_CGC_FRC_ALL_HCLK0, clk_mask);
490 }
491
492 /**
493 * @brief Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/
494 * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
495 *
496 * Register | BitsName
497 * ----------|--------
498 * CG_CTRL_1 | SECU_HCLK
499 * CG_CTRL_1 | SIM_HCLK
500 * CG_CTRL_1 | HTB_HCLK
501 * CG_CTRL_1 | ROM_HCLK
502 * CG_CTRL_1 | SNSADC_HCLK
503 * CG_CTRL_1 | GPIO_HCLK
504 * CG_CTRL_1 | DMA_HCLK
505 * CG_CTRL_1 | BLE_BRG_HCLK
506 * CG_CTRL_1 | APB_SUB_HCLK
507 * CG_CTRL_1 | SERIAL_HCLK
508 *
509 * @retval Returned value can be a combination of the following values:
510 * @arg @ref LL_CGC_FRC_SECU_HCLK
511 * @arg @ref LL_CGC_FRC_HTB_HCLK
512 * @arg @ref LL_CGC_FRC_ROM_HCLK
513 * @arg @ref LL_CGC_FRC_SNSADC_HCLK
514 * @arg @ref LL_CGC_FRC_GPIO_HCLK
515 * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
516 * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
517 * @arg @ref LL_CGC_FRC_SERIAL_HCLK
518 */
519 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
520 {
521 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1]);
522 }
523
524 /**
525 * @brief Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
526 *
527 * Register | BitsName
528 * ----------|--------
529 * CG_CTRL_2 | AON_MCUSUB_HCLK
530 * CG_CTRL_2 | XF_XQSPI_HCLK
531 * CG_CTRL_2 | SRAM_HCLK
532 *
533 * @param clk_mask This parameter can be a combination of the following values:
534 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
535 * @arg @ref LL_CGC_FRC_SRAM_HCLK
536 * @retval None
537 */
538 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
539 {
540 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1, clk_mask);
541 }
542
543 /**
544 * @brief Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
545 *
546 * Register | BitsName
547 * ----------|--------
548 * CG_CTRL_2 | AON_MCUSUB_HCLK
549 * CG_CTRL_2 | XF_XQSPI_HCLK
550 * CG_CTRL_2 | SRAM_HCLK
551 *
552 * @retval Returned value can be a combination of the following values:
553 * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
554 * @arg @ref LL_CGC_FRC_SRAM_HCLK
555 */
556 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
557 {
558 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1);
559 }
560
561 /**
562 * @brief Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
563 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
564 *
565 * Register | BitsName
566 * ----------|--------
567 * PERIPH_GC | UART0_HCLK
568 * PERIPH_GC | UART1_HCLK
569 * PERIPH_GC | I2C0_HCLK
570 * PERIPH_GC | I2C1_HCLK
571 * PERIPH_GC | SPIM_HCLK
572 * PERIPH_GC | SPIS_HCLK
573 * PERIPH_GC | XQSPI_DIV4_PCLK
574 * PERIPH_GC | PWM0_HCLK
575 * PERIPH_GC | PWM1_HCLK
576 *
577 * @param clk_mask This parameter can be a combination of the following values:
578 * @arg @ref LL_CGC_FRC_UART0_PCLK
579 * @arg @ref LL_CGC_FRC_UART1_PCLK
580 * @arg @ref LL_CGC_FRC_I2C0_PCLK
581 * @arg @ref LL_CGC_FRC_I2C1_PCLK
582 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
583 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
584 * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
585 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
586 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
587 * @retval None
588 */
589 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
590 {
591 MODIFY_REG(MCU_SUB->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2, clk_mask);
592 }
593
594
595 /**
596 * @brief Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
597 * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
598 *
599 * Register | BitsName
600 * ----------|--------
601 * PERIPH_GC | UART0_HCLK
602 * PERIPH_GC | UART1_HCLK
603 * PERIPH_GC | I2C0_HCLK
604 * PERIPH_GC | I2C1_HCLK
605 * PERIPH_GC | SPIM_HCLK
606 * PERIPH_GC | SPIS_HCLK
607 * PERIPH_GC | XQSPI_DIV4_PCLK
608 * PERIPH_GC | PWM0_HCLK
609 * PERIPH_GC | PWM1_HCLK
610 *
611 * @retval Returned value can be a combination of the following values:
612 * @arg @ref LL_CGC_FRC_UART0_PCLK
613 * @arg @ref LL_CGC_FRC_UART1_PCLK
614 * @arg @ref LL_CGC_FRC_I2C0_PCLK
615 * @arg @ref LL_CGC_FRC_I2C1_PCLK
616 * @arg @ref LL_CGC_FRC_SPI_M_PCLK
617 * @arg @ref LL_CGC_FRC_SPI_S_PCLK
618 * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
619 * @arg @ref LL_CGC_FRC_PWM_0_PCLK
620 * @arg @ref LL_CGC_FRC_PWM_1_PCLK
621 */
622 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
623 {
624 return READ_BITS(MCU_SUB->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2);
625 }
626
627 /**
628 * @brief Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
629 *
630 * Register | BitsName
631 * ----------|--------
632 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
633 *
634 * @param clk_mask This parameter can be a combination of the following values:
635 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
636 * .....
637 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
638 * @retval None
639 */
640 __STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
641 {
642 MODIFY_REG(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
643 }
644
645 /**
646 * @brief Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
647 *
648 * Register | BitsName
649 * ----------|--------
650 * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
651 *
652 * @retval Returned value can be a combination of the following values:
653 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
654 * .....
655 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
656 */
657 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
658 {
659 return READ_BITS(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
660 }
661
662 /**
663 * @brief Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
664 *
665 * Register | BitsName
666 * ----------|--------
667 * CG_CTRL_0 | SECU_HCLK
668 *
669 * @retval None
670 */
671 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
672 {
673 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
674 }
675
676 /**
677 * @brief Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
678 *
679 * Register | BitsName
680 * ----------|--------
681 * CG_CTRL_0 | SECU_HCLK
682 *
683 * @retval None
684 */
685 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
686 {
687 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
688 }
689
690 /**
691 * @brief Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is enabled.
692 *
693 * Register | BitsName
694 * ----------|--------
695 * CG_CTRL_0 | SECU_HCLK
696 *
697 * @retval State of bit (1 or 0).
698 */
699 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
700 {
701 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
702 }
703
704 /**
705 * @brief Enable SIM automatic turn off clock during WFI
706 *
707 * Register | BitsName
708 * ----------|--------
709 * CG_CTRL_0 | SIM_HCLK
710 *
711 * @retval None
712 */
713 __STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
714 {
715 }
716
717 /**
718 * @brief Disable SIM automatic turn off clock during WFI
719 *
720 * Register | BitsName
721 * ----------|--------
722 * CG_CTRL_0 | SIM_HCLK
723 *
724 * @retval None
725 */
726 __STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
727 {
728 }
729
730 /**
731 * @brief Indicate whether the SIM automatic turn off clock is enabled.
732 *
733 * Register | BitsName
734 * ----------|--------
735 * CG_CTRL_0 | SIM_HCLK
736 *
737 * @retval State of bit (1 or 0).
738 */
739 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
740 {
741 return 0;
742 }
743
744 /**
745 * @brief Enable Hopping Table automatic turn off clock during WFI
746 *
747 * Register | BitsName
748 * ----------|--------
749 * CG_CTRL_0 | HTB_HCLK
750 *
751 * @retval None
752 */
753 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
754 {
755 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
756 }
757
758 /**
759 * @brief Disable Hopping Table automatic turn off clock during WFI
760 *
761 * Register | BitsName
762 * ----------|--------
763 * CG_CTRL_0 | HTB_HCLK
764 *
765 * @retval None
766 */
767 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
768 {
769 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
770 }
771
772 /**
773 * @brief Indicate whether the Hopping Table automatic turn off clock is enabled.
774 *
775 * Register | BitsName
776 * ----------|--------
777 * CG_CTRL_0 | HTB_HCLK
778 *
779 * @retval State of bit (1 or 0).
780 */
781 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
782 {
783 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
784 }
785
786 /**
787 * @brief Enable PWM automatic turn off clock during WFI
788 *
789 * Register | BitsName
790 * ----------|--------
791 * CG_CTRL_0 | PWM_HCLK
792 *
793 * @retval None
794 */
795 __STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
796 {
797 }
798
799 /**
800 * @brief Disable PWM automatic turn off clock during WFI
801 *
802 * Register | BitsName
803 * ----------|--------
804 * CG_CTRL_0 | PWM_HCLK
805 *
806 * @retval None
807 */
808 __STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
809 {
810 }
811
812 /**
813 * @brief Indicate whether the PWM automatic turn off clock is enabled.
814 *
815 * Register | BitsName
816 * ----------|--------
817 * CG_CTRL_0 | PWM_HCLK
818 *
819 * @retval State of bit (1 or 0).
820 */
821 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
822 {
823 return 0;
824 }
825
826 /**
827 * @brief Enable ROM automatic turn off clock during WFI
828 *
829 * Register | BitsName
830 * ----------|--------
831 * CG_CTRL_0 | ROM_HCLK
832 *
833 * @retval None
834 */
835 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
836 {
837 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
838 }
839
840 /**
841 * @brief Disable ROM automatic turn off clock during WFI
842 *
843 * Register | BitsName
844 * ----------|--------
845 * CG_CTRL_0 | ROM_HCLK
846 *
847 * @retval None
848 */
849 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
850 {
851 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
852 }
853
854 /**
855 * @brief Indicate whether the ROM automatic turn off clock is enabled.
856 *
857 * Register | BitsName
858 * ----------|--------
859 * CG_CTRL_0 | ROM_HCLK
860 *
861 * @retval State of bit (1 or 0).
862 */
863 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
864 {
865 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
866 }
867
868 /**
869 * @brief Enable SNSADC automatic turn off clock during WFI
870 *
871 * Register | BitsName
872 * ----------|--------
873 * CG_CTRL_0 | SNSADC_HCLK
874 *
875 * @retval None
876 */
877 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
878 {
879 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
880 }
881
882 /**
883 * @brief Disable SNSADC automatic turn off clock during WFI
884 *
885 * Register | BitsName
886 * ----------|--------
887 * CG_CTRL_0 | SNSADC_HCLK
888 *
889 * @retval None
890 */
891 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
892 {
893 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
894 }
895
896 /**
897 * @brief Indicate whether the SNSADC automatic turn off clock is enabled.
898 *
899 * Register | BitsName
900 * ----------|--------
901 * CG_CTRL_0 | SNSADC_HCLK
902 *
903 * @retval State of bit (1 or 0).
904 */
905 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
906 {
907 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
908 }
909
910 /**
911 * @brief Enable GPIO automatic turn off clock during WFI
912 *
913 * Register | BitsName
914 * ----------|--------
915 * CG_CTRL_0 | GPIO_HCLK
916 *
917 * @retval None
918 */
919 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
920 {
921 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
922 }
923
924 /**
925 * @brief Disable GPIO automatic turn off clock during WFI
926 *
927 * Register | BitsName
928 * ----------|--------
929 * CG_CTRL_0 | GPIO_HCLK
930 *
931 * @retval None
932 */
933 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
934 {
935 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
936 }
937
938 /**
939 * @brief Indicate whether the GPIO automatic turn off clock is enabled.
940 *
941 * Register | BitsName
942 * ----------|--------
943 * CG_CTRL_0 | GPIO_HCLK
944 *
945 * @retval State of bit (1 or 0).
946 */
947 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
948 {
949 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
950 }
951
952 /**
953 * @brief Enable DMA automatic turn off clock during WFI
954 *
955 * Register | BitsName
956 * ----------|--------
957 * CG_CTRL_0 | DMA_HCLK
958 *
959 * @retval None
960 */
961 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
962 {
963 }
964
965 /**
966 * @brief Disable DMA automatic turn off clock during WFI
967 *
968 * Register | BitsName
969 * ----------|--------
970 * CG_CTRL_0 | DMA_HCLK
971 *
972 * @retval None
973 */
974 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
975 {
976 }
977
978 /**
979 * @brief Indicate whether the DMA automatic turn off clock is enabled.
980 *
981 * Register | BitsName
982 * ----------|--------
983 * CG_CTRL_0 | DMA_HCLK
984 *
985 * @retval State of bit (1 or 0).
986 */
987 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
988 {
989 return 0;
990 }
991
992 /**
993 * @brief Enable BLE Bridge automatic turn off clock during WFI
994 *
995 * Register | BitsName
996 * ----------|--------
997 * CG_CTRL_0 | BLE_BRG_HCLK
998 *
999 * @retval None
1000 */
1001 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
1002 {
1003 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1004 }
1005
1006 /**
1007 * @brief Disable BLE Bridge automatic turn off clock during WFI
1008 *
1009 * Register | BitsName
1010 * ----------|--------
1011 * CG_CTRL_0 | BLE_BRG_HCLK
1012 *
1013 * @retval None
1014 */
1015 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1016 {
1017 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1018 }
1019
1020 /**
1021 * @brief Indicate whether the BLE Bridge automatic turn off clock is enabled.
1022 *
1023 * Register | BitsName
1024 * ----------|--------
1025 * CG_CTRL_0 | BLE_BRG_HCLK
1026 *
1027 * @retval State of bit (1 or 0).
1028 */
1029 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1030 {
1031 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1032 }
1033
1034 /**
1035 * @brief Enable APB Subsystem automatic turn off clock during WFI
1036 *
1037 * Register | BitsName
1038 * ----------|--------
1039 * CG_CTRL_0 | APB_SUB_HCLK
1040 *
1041 * @retval None
1042 */
1043 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1044 {
1045 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1046 }
1047
1048 /**
1049 * @brief Disable APB Subsystem automatic turn off clock during WFI
1050 *
1051 * Register | BitsName
1052 * ----------|--------
1053 * CG_CTRL_0 | APB_SUB_HCLK
1054 *
1055 * @retval None
1056 */
1057 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1058 {
1059 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1060 }
1061
1062 /**
1063 * @brief Indicate whether the APB Subsystem automatic turn off clock is enabled.
1064 *
1065 * Register | BitsName
1066 * ----------|--------
1067 * CG_CTRL_0 | APB_SUB_HCLK
1068 *
1069 * @retval State of bit (1 or 0).
1070 */
1071 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1072 {
1073 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1074 }
1075
1076 /**
1077 * @brief Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1078 *
1079 * Register | BitsName
1080 * ----------|--------
1081 * CG_CTRL_0 | SERIAL_HCLK
1082 *
1083 * @retval None
1084 */
1085 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1086 {
1087 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1088 }
1089
1090 /**
1091 * @brief Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1092 *
1093 * Register | BitsName
1094 * ----------|--------
1095 * CG_CTRL_0 | SERIAL_HCLK
1096 *
1097 * @retval None
1098 */
1099 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1100 {
1101 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1102 }
1103
1104 /**
1105 * @brief Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off
1106 * clock is enabled.
1107 *
1108 * Register | BitsName
1109 * ----------|--------
1110 * CG_CTRL_0 | SERIAL_HCLK
1111 *
1112 * @retval State of bit (1 or 0).
1113 */
1114 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1115 {
1116 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1117 }
1118
1119 /**
1120 * @brief Enable AON_MUCSUB automatic turn off clock during WFI
1121 *
1122 * Register | BitsName
1123 * ----------|--------
1124 * CG_CTRL_2 | AON_MCUSUB_HCLK
1125 *
1126 * @retval None
1127 */
1128 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1129 {
1130 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1131 }
1132
1133 /**
1134 * @brief Disable AON_MUCSUB automatic turn off clock during WFI
1135 *
1136 * Register | BitsName
1137 * ----------|--------
1138 * CG_CTRL_2 | AON_MCUSUB_HCLK
1139 *
1140 * @retval None
1141 */
1142 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1143 {
1144 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1145 }
1146
1147 /**
1148 * @brief Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
1149 *
1150 * Register | BitsName
1151 * ----------|--------
1152 * CG_CTRL_2 | AON_MCUSUB_HCLK
1153 *
1154 * @retval State of bit (1 or 0).
1155 */
1156 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1157 {
1158 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1159 }
1160
1161 /**
1162 * @brief Enable XQSPI automatic turn off clock during WFI
1163 *
1164 * Register | BitsName
1165 * ----------|--------
1166 * CG_CTRL_2 | XF_XQSPI_HCLK
1167 *
1168 * @retval None
1169 */
1170 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1171 {
1172 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1173 }
1174
1175 /**
1176 * @brief Disable XQSPI automatic turn off clock during WFI
1177 *
1178 * Register | BitsName
1179 * ----------|--------
1180 * CG_CTRL_2 | XF_XQSPI_HCLK
1181 *
1182 * @retval None
1183 */
1184 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1185 {
1186 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1187 }
1188
1189 /**
1190 * @brief Indicate whether the XQSPI automatic turn off clock is enabled.
1191 *
1192 * Register | BitsName
1193 * ----------|--------
1194 * CG_CTRL_2 | XF_XQSPI_HCLK
1195 *
1196 * @retval State of bit (1 or 0).
1197 */
1198 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1199 {
1200 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1201 }
1202
1203 /**
1204 * @brief Enable SRAM automatic turn off clock during WFI
1205 *
1206 * Register | BitsName
1207 * ----------|--------
1208 * CG_CTRL_2 | SRAM_HCLK
1209 *
1210 * @retval None
1211 */
1212 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1213 {
1214 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1215 }
1216
1217 /**
1218 * @brief Disable SRAM automatic turn off clock during WFI
1219 *
1220 * Register | BitsName
1221 * ----------|--------
1222 * CG_CTRL_2 | SRAM_HCLK
1223 *
1224 * @retval None
1225 */
1226 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1227 {
1228 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1229 }
1230
1231 /**
1232 * @brief Indicate whether the SRAM automatic turn off clock is enabled.
1233 *
1234 * Register | BitsName
1235 * ----------|--------
1236 * CG_CTRL_2 | SRAM_HCLK
1237 *
1238 * @retval State of bit (1 or 0).
1239 */
1240 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1241 {
1242 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1243 }
1244
1245 /**
1246 * @brief Enable security blocks automatic turn off div4 clock during WFI
1247 *
1248 * Register | BitsName
1249 * ----------|--------
1250 * PERIPH_GC | SECU_DIV4_PCLK
1251 *
1252 * @retval None
1253 */
1254 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1255 {
1256 }
1257
1258 /**
1259 * @brief Disable security blocks automatic turn off div4 clock during WFI
1260 *
1261 * Register | BitsName
1262 * ----------|--------
1263 * PERIPH_GC | SECU_DIV4_PCLK
1264 *
1265 * @retval None
1266 */
1267 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1268 {
1269 }
1270
1271 /**
1272 * @brief Indicate whether the security blocks automatic turn off div4
1273 * clock is enabled.
1274 *
1275 * Register | BitsName
1276 * ----------|--------
1277 * PERIPH_GC | SECU_DIV4_PCLK
1278 *
1279 * @retval State of bit (1 or 0).
1280 */
1281 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1282 {
1283 return 0;
1284 }
1285
1286 /**
1287 * @brief Enable XQSPI automatic turn off div4 clock during WFI
1288 *
1289 * Register | BitsName
1290 * ----------|--------
1291 * PERIPH_GC | XQSPI_DIV4_PCLK
1292 *
1293 * @retval None
1294 */
1295 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1296 {
1297 }
1298
1299 /**
1300 * @brief Disable XQSPI automatic turn off div4 clock during WFI
1301 *
1302 * Register | BitsName
1303 * ----------|--------
1304 * PERIPH_GC | XQSPI_DIV4_PCLK
1305 *
1306 * @retval None
1307 */
1308 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1309 {
1310 }
1311
1312 /**
1313 * @brief Indicate whether the XQSPI automatic turn off div4 clock is enabled.
1314 *
1315 * Register | BitsName
1316 * ----------|--------
1317 * PERIPH_GC | XQSPI_DIV4_PCLK
1318 *
1319 * @retval State of bit (1 or 0).
1320 */
1321 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1322 {
1323 return 0;
1324 }
1325
1326 /**
1327 * @brief Enabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1328 *
1329 * Register | BitsName
1330 * ----------|--------
1331 * CG_CTRL_1 | SECU_HCLK
1332 *
1333 * @retval None
1334 */
1335 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1336 {
1337 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
1338 }
1339
1340 /**
1341 * @brief Disabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1342 *
1343 * Register | BitsName
1344 * ----------|--------
1345 * CG_CTRL_1 | SECU_HCLK
1346 *
1347 * @retval None
1348 */
1349 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1350 {
1351 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
1352 }
1353
1354 /**
1355 * @brief Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
1356 *
1357 * Register | BitsName
1358 * ----------|--------
1359 * CG_CTRL_1 | SECU_HCLK
1360 *
1361 * @retval State of bit (1 or 0).
1362 */
1363 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1364 {
1365 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1366 }
1367
1368 /**
1369 * @brief Enabling force to turn off the clock for Hopping Table.
1370 *
1371 * Register | BitsName
1372 * ----------|--------
1373 * CG_CTRL_1 | HTB_HCLK
1374 *
1375 * @retval None
1376 */
1377 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1378 {
1379 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1380 }
1381
1382 /**
1383 * @brief Disabling force to turn off the clock for Hopping Table.
1384 *
1385 * Register | BitsName
1386 * ----------|--------
1387 * CG_CTRL_1 | HTB_HCLK
1388 *
1389 * @retval None
1390 */
1391 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1392 {
1393 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1394 }
1395
1396 /**
1397 * @brief Indicate whether the clock for Hopping Table is forced to close.
1398 *
1399 * Register | BitsName
1400 * ----------|--------
1401 * CG_CTRL_1 | HTB_HCLK
1402 *
1403 * @retval State of bit (1 or 0).
1404 */
1405 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1406 {
1407 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1408 }
1409
1410 /**
1411 * @brief Enabling force to turn off the clock for ROM.
1412 *
1413 * Register | BitsName
1414 * ----------|--------
1415 * CG_CTRL_1 | ROM_HCLK
1416 *
1417 * @retval None
1418 */
1419 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1420 {
1421 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1422 }
1423
1424 /**
1425 * @brief Disabling force to turn off the clock for ROM.
1426 *
1427 * Register | BitsName
1428 * ----------|--------
1429 * CG_CTRL_1 | ROM_HCLK
1430 *
1431 * @retval None
1432 */
1433 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1434 {
1435 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1436 }
1437
1438 /**
1439 * @brief Indicate whether the clock for ROM is forced to close.
1440 *
1441 * Register | BitsName
1442 * ----------|--------
1443 * CG_CTRL_1 | ROM_HCLK
1444 *
1445 * @retval State of bit (1 or 0).
1446 */
1447 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1448 {
1449 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1450 }
1451
1452 /**
1453 * @brief Enabling force to turn off the clock for SNSADC.
1454 *
1455 * Register | BitsName
1456 * ----------|--------
1457 * CG_CTRL_1 | SNSADC_HCLK
1458 *
1459 * @retval None
1460 */
1461 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1462 {
1463 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1464 }
1465
1466 /**
1467 * @brief Disabling force to turn off the clock for SNSADC.
1468 *
1469 * Register | BitsName
1470 * ----------|--------
1471 * CG_CTRL_1 | SNSADC_HCLK
1472 *
1473 * @retval None
1474 */
1475 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1476 {
1477 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1478 }
1479
1480 /**
1481 * @brief Indicate whether the clock for SNSADC is forced to close.
1482 *
1483 * Register | BitsName
1484 * ----------|--------
1485 * CG_CTRL_1 | SNSADC_HCLK
1486 *
1487 * @retval State of bit (1 or 0).
1488 */
1489 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1490 {
1491 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1492 }
1493
1494 /**
1495 * @brief Enabling force to turn off the clock for GPIO.
1496 *
1497 * Register | BitsName
1498 * ----------|--------
1499 * CG_CTRL_1 | GPIO_HCLK
1500 *
1501 * @retval None
1502 */
1503 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1504 {
1505 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1506 }
1507
1508 /**
1509 * @brief Disabling force to turn off the clock for GPIO.
1510 *
1511 * Register | BitsName
1512 * ----------|--------
1513 * CG_CTRL_1 | GPIO_HCLK
1514 *
1515 * @retval None
1516 */
1517 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1518 {
1519 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1520 }
1521
1522 /**
1523 * @brief Indicate whether the clock for GPIO is forced to close.
1524 *
1525 * Register | BitsName
1526 * ----------|--------
1527 * CG_CTRL_1 | GPIO_HCLK
1528 *
1529 * @retval State of bit (1 or 0).
1530 */
1531 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1532 {
1533 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1534 }
1535
1536 /**
1537 * @brief Enabling force to turn off the clock for BLE Bridge.
1538 *
1539 * Register | BitsName
1540 * ----------|--------
1541 * CG_CTRL_1 | BLE_BRG_HCLK
1542 *
1543 * @retval None
1544 */
1545 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1546 {
1547 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1548 }
1549
1550 /**
1551 * @brief Disabling force to turn off the clock for BLE Bridge.
1552 *
1553 * Register | BitsName
1554 * ----------|--------
1555 * CG_CTRL_1 | BLE_BRG_HCLK
1556 *
1557 * @retval None
1558 */
1559 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1560 {
1561 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1562 }
1563
1564 /**
1565 * @brief Indicate whether the clock for BLE Bridge is forced to close.
1566 *
1567 * Register | BitsName
1568 * ----------|--------
1569 * CG_CTRL_1 | BLE_BRG_HCLK
1570 *
1571 * @retval State of bit (1 or 0).
1572 */
1573 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1574 {
1575 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1576 }
1577
1578 /**
1579 * @brief Enabling force to turn off the clock for APB Subsystem.
1580 *
1581 * Register | BitsName
1582 * ----------|--------
1583 * CG_CTRL_1 | APB_SUB_HCLK
1584 *
1585 * @retval None
1586 */
1587 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1588 {
1589 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1590 }
1591
1592 /**
1593 * @brief Disabling force to turn off the clock for APB Subsystem.
1594 *
1595 * Register | BitsName
1596 * ----------|--------
1597 * CG_CTRL_1 | APB_SUB_HCLK
1598 *
1599 * @retval None
1600 */
1601 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1602 {
1603 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1604 }
1605
1606 /**
1607 * @brief Indicate whether the clock for APB Subsystem is forced to close.
1608 *
1609 * Register | BitsName
1610 * ----------|--------
1611 * CG_CTRL_1 | APB_SUB_HCLK
1612 *
1613 * @retval State of bit (1 or 0).
1614 */
1615 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1616 {
1617 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1618 }
1619
1620 /**
1621 * @brief Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1622 *
1623 * Register | BitsName
1624 * ----------|--------
1625 * CG_CTRL_1 | SERIAL_HCLK
1626 *
1627 * @retval None
1628 */
1629 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1630 {
1631 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1632 }
1633
1634 /**
1635 * @brief Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1636 *
1637 * Register | BitsName
1638 * ----------|--------
1639 * CG_CTRL_1 | SERIAL_HCLK
1640 *
1641 * @retval None
1642 */
1643 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1644 {
1645 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1646 }
1647
1648 /**
1649 * @brief Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
1650 *
1651 * Register | BitsName
1652 * ----------|--------
1653 * CG_CTRL_1 | SERIAL_HCLK
1654 *
1655 * @retval State of bit (1 or 0).
1656 */
1657 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1658 {
1659 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1660 }
1661
1662 /**
1663 * @brief Enabling force to turn off the clock for AON_MUCSUB.
1664 *
1665 * Register | BitsName
1666 * ----------|--------
1667 * CG_CTRL_2 | AON_MCUSUB_HCLK
1668 *
1669 * @retval None
1670 */
1671 __STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
1672 {
1673 }
1674
1675 /**
1676 * @brief Disabling force to turn off the clock for AON_MUCSUB.
1677 *
1678 * Register | BitsName
1679 * ----------|--------
1680 * CG_CTRL_2 | AON_MCUSUB_HCLK
1681 *
1682 * @retval None
1683 */
1684 __STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
1685 {
1686 }
1687
1688 /**
1689 * @brief Indicate whether the clock for AON_MUCSUB is forced to close.
1690 *
1691 * Register | BitsName
1692 * ----------|--------
1693 * CG_CTRL_2 | AON_MCUSUB_HCLK
1694 *
1695 * @retval State of bit (1 or 0).
1696 */
1697 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
1698 {
1699 return 0;
1700 }
1701
1702 /**
1703 * @brief Enabling force to turn off the clock for XQSPI.
1704 *
1705 * Register | BitsName
1706 * ----------|--------
1707 * CG_CTRL_2 | XF_XQSPI_HCLK
1708 *
1709 * @retval None
1710 */
1711 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
1712 {
1713 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1714 }
1715
1716 /**
1717 * @brief Disabling force to turn off the clock for XQSPI.
1718 *
1719 * Register | BitsName
1720 * ----------|--------
1721 * CG_CTRL_2 | XF_XQSPI_HCLK
1722 *
1723 * @retval None
1724 */
1725 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
1726 {
1727 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1728 }
1729
1730 /**
1731 * @brief Indicate whether the clock for XQSPI is forced to close.
1732 *
1733 * Register | BitsName
1734 * ----------|--------
1735 * CG_CTRL_2 | XF_XQSPI_HCLK
1736 *
1737 * @retval State of bit (1 or 0).
1738 */
1739 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
1740 {
1741 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1742 }
1743
1744 /**
1745 * @brief Enabling force to turn off the clock for SRAM.
1746 *
1747 * Register | BitsName
1748 * ----------|--------
1749 * CG_CTRL_2 | SRAM_HCLK
1750 *
1751 * @retval None
1752 */
1753 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
1754 {
1755 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1756 }
1757
1758 /**
1759 * @brief Disabling force to turn off the clock for SRAM.
1760 *
1761 * Register | BitsName
1762 * ----------|--------
1763 * CG_CTRL_2 | SRAM_HCLK
1764 *
1765 * @retval None
1766 */
1767 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
1768 {
1769 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1770 }
1771
1772 /**
1773 * @brief Indicate whether the clock for SRAM is forced to close.
1774 *
1775 * Register | BitsName
1776 * ----------|--------
1777 * CG_CTRL_2 | SRAM_HCLK
1778 *
1779 * @retval State of bit (1 or 0).
1780 */
1781 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
1782 {
1783 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1784 }
1785
1786 /**
1787 * @brief Enabling force to turn off the clock for UART0.
1788 *
1789 * Register | BitsName
1790 * ----------|--------
1791 * PERIPH_GC | UART0_HCLK
1792 *
1793 * @retval None
1794 */
1795 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
1796 {
1797 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_ENABLE;
1798 }
1799
1800 /**
1801 * @brief Disabling force to turn off the clock for UART0.
1802 *
1803 * Register | BitsName
1804 * ----------|--------
1805 * PERIPH_GC | UART0_HCLK
1806 *
1807 * @retval None
1808 */
1809 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
1810 {
1811 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_DISABLE;
1812 }
1813
1814 /**
1815 * @brief Indicate whether the clock for UART0 is forced to close.
1816 *
1817 * Register | BitsName
1818 * ----------|--------
1819 * PERIPH_GC | UART0_HCLK
1820 *
1821 * @retval State of bit (1 or 0).
1822 */
1823 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
1824 {
1825 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1826 }
1827
1828 /**
1829 * @brief Enabling force to turn off the clock for UART1.
1830 *
1831 * Register | BitsName
1832 * ----------|--------
1833 * PERIPH_GC | UART1_HCLK
1834 *
1835 * @retval None
1836 */
1837 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
1838 {
1839 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_ENABLE;
1840 }
1841
1842 /**
1843 * @brief Disabling force to turn off the clock for UART1.
1844 *
1845 * Register | BitsName
1846 * ----------|--------
1847 * PERIPH_GC | UART1_HCLK
1848 *
1849 * @retval None
1850 */
1851 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
1852 {
1853 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_DISABLE;
1854 }
1855
1856 /**
1857 * @brief Indicate whether the clock for UART1 is forced to close.
1858 *
1859 * Register | BitsName
1860 * ----------|--------
1861 * PERIPH_GC | UART1_HCLK
1862 *
1863 * @retval State of bit (1 or 0).
1864 */
1865 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
1866 {
1867 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1868 }
1869
1870 /**
1871 * @brief Enabling force to turn off the clock for UART2.
1872 *
1873 * Register | BitsName
1874 * ----------|--------
1875 * PERIPH_GC | UART2_HCLK
1876 *
1877 * @retval None
1878 */
1879 __STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
1880 {
1881 }
1882
1883 /**
1884 * @brief Disabling force to turn off the clock for UART2.
1885 *
1886 * Register | BitsName
1887 * ----------|--------
1888 * PERIPH_GC | UART2_HCLK
1889 *
1890 * @retval None
1891 */
1892 __STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
1893 {
1894 }
1895
1896 /**
1897 * @brief Indicate whether the clock for UART2 is forced to close.
1898 *
1899 * Register | BitsName
1900 * ----------|--------
1901 * PERIPH_GC | UART2_HCLK
1902 *
1903 * @retval State of bit (1 or 0).
1904 */
1905 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
1906 {
1907 return 0;
1908 }
1909
1910 /**
1911 * @brief Enabling force to turn off the clock for UART3.
1912 *
1913 * Register | BitsName
1914 * ----------|--------
1915 * PERIPH_GC | UART3_HCLK
1916 *
1917 * @retval None
1918 */
1919 __STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
1920 {
1921 }
1922
1923 /**
1924 * @brief Disabling force to turn off the clock for UART3.
1925 *
1926 * Register | BitsName
1927 * ----------|--------
1928 * PERIPH_GC | UART3_HCLK
1929 *
1930 * @retval None
1931 */
1932 __STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
1933 {
1934 }
1935
1936 /**
1937 * @brief Indicate whether the clock for UART3 is forced to close.
1938 *
1939 * Register | BitsName
1940 * ----------|--------
1941 * PERIPH_GC | UART3_HCLK
1942 *
1943 * @retval State of bit (1 or 0).
1944 */
1945 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
1946 {
1947 return 0;
1948 }
1949
1950 /**
1951 * @brief Enabling force to turn off the clock for UART4.
1952 *
1953 * Register | BitsName
1954 * ----------|--------
1955 * PERIPH_GC | UART4_HCLK
1956 *
1957 * @retval None
1958 */
1959 __STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
1960 {
1961 }
1962
1963 /**
1964 * @brief Disabling force to turn off the clock for UART4.
1965 *
1966 * Register | BitsName
1967 * ----------|--------
1968 * PERIPH_GC | UART4_HCLK
1969 *
1970 * @retval None
1971 */
1972 __STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
1973 {
1974 }
1975
1976 /**
1977 * @brief Indicate whether the clock for UART4 is forced to close.
1978 *
1979 * Register | BitsName
1980 * ----------|--------
1981 * PERIPH_GC | UART4_HCLK
1982 *
1983 * @retval State of bit (1 or 0).
1984 */
1985 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
1986 {
1987 return 0;
1988 }
1989
1990 /**
1991 * @brief Enabling force to turn off the clock for UART5.
1992 *
1993 * Register | BitsName
1994 * ----------|--------
1995 * PERIPH_GC | UART5_HCLK
1996 *
1997 * @retval None
1998 */
1999 __STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
2000 {
2001 }
2002
2003 /**
2004 * @brief Disabling force to turn off the clock for UART5.
2005 *
2006 * Register | BitsName
2007 * ----------|--------
2008 * PERIPH_GC | UART5_HCLK
2009 *
2010 * @retval None
2011 */
2012 __STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
2013 {
2014 }
2015
2016 /**
2017 * @brief Indicate whether the clock for UART5 is forced to close.
2018 *
2019 * Register | BitsName
2020 * ----------|--------
2021 * PERIPH_GC | UART5_HCLK
2022 *
2023 * @retval State of bit (1 or 0).
2024 */
2025 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
2026 {
2027 return 0;
2028 }
2029
2030 /**
2031 * @brief Enabling force to turn off the clock for I2C0.
2032 *
2033 * Register | BitsName
2034 * ----------|--------
2035 * PERIPH_GC | I2C0_HCLK
2036 *
2037 * @retval None
2038 */
2039 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2040 {
2041 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2042 }
2043
2044 /**
2045 * @brief Disabling force to turn off the clock for I2C0.
2046 *
2047 * Register | BitsName
2048 * ----------|--------
2049 * PERIPH_GC | I2C0_HCLK
2050 *
2051 * @retval None
2052 */
2053 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2054 {
2055 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2056 }
2057
2058 /**
2059 * @brief Indicate whether the clock for I2C0 is forced to close.
2060 *
2061 * Register | BitsName
2062 * ----------|--------
2063 * PERIPH_GC | I2C0_HCLK
2064 *
2065 * @retval State of bit (1 or 0).
2066 */
2067 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2068 {
2069 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2070 }
2071
2072 /**
2073 * @brief Enabling force to turn off the clock for I2C1.
2074 *
2075 * Register | BitsName
2076 * ----------|--------
2077 * PERIPH_GC | I2C1_HCLK
2078 *
2079 * @retval None
2080 */
2081 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2082 {
2083 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2084 }
2085
2086 /**
2087 * @brief Disabling force to turn off the clock for I2C1.
2088 *
2089 * Register | BitsName
2090 * ----------|--------
2091 * PERIPH_GC | I2C1_HCLK
2092 *
2093 * @retval None
2094 */
2095 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2096 {
2097 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2098 }
2099
2100 /**
2101 * @brief Indicate whether the clock for I2C1 is forced to close.
2102 *
2103 * Register | BitsName
2104 * ----------|--------
2105 * PERIPH_GC | I2C1_HCLK
2106 *
2107 * @retval State of bit (1 or 0).
2108 */
2109 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2110 {
2111 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2112 }
2113
2114 /**
2115 * @brief Enabling force to turn off the clock for I2C2.
2116 *
2117 * Register | BitsName
2118 * ----------|--------
2119 * PERIPH_GC | I2C2_HCLK
2120 *
2121 * @retval None
2122 */
2123 __STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
2124 {
2125 }
2126
2127 /**
2128 * @brief Disabling force to turn off the clock for I2C2.
2129 *
2130 * Register | BitsName
2131 * ----------|--------
2132 * PERIPH_GC | I2C2_HCLK
2133 *
2134 * @retval None
2135 */
2136 __STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
2137 {
2138 }
2139
2140 /**
2141 * @brief Indicate whether the clock for I2C2 is forced to close.
2142 *
2143 * Register | BitsName
2144 * ----------|--------
2145 * PERIPH_GC | I2C2_HCLK
2146 *
2147 * @retval State of bit (1 or 0).
2148 */
2149 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
2150 {
2151 return 0;
2152 }
2153
2154 /**
2155 * @brief Enabling force to turn off the clock for I2C3.
2156 *
2157 * Register | BitsName
2158 * ----------|--------
2159 * PERIPH_GC | I2C3_HCLK
2160 *
2161 * @retval None
2162 */
2163 __STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
2164 {
2165 }
2166
2167 /**
2168 * @brief Disabling force to turn off the clock for I2C3.
2169 *
2170 * Register | BitsName
2171 * ----------|--------
2172 * PERIPH_GC | I2C3_HCLK
2173 *
2174 * @retval None
2175 */
2176 __STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
2177 {
2178 }
2179
2180 /**
2181 * @brief Indicate whether the clock for I2C3 is forced to close.
2182 *
2183 * Register | BitsName
2184 * ----------|--------
2185 * PERIPH_GC | I2C3_HCLK
2186 *
2187 * @retval State of bit (1 or 0).
2188 */
2189 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
2190 {
2191 return 0;
2192 }
2193
2194 /**
2195 * @brief Enabling force to turn off the clock for I2C4.
2196 *
2197 * Register | BitsName
2198 * ----------|--------
2199 * PERIPH_GC | I2C4_HCLK
2200 *
2201 * @retval None
2202 */
2203 __STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
2204 {
2205 }
2206
2207 /**
2208 * @brief Disabling force to turn off the clock for I2C4.
2209 *
2210 * Register | BitsName
2211 * ----------|--------
2212 * PERIPH_GC | I2C4_HCLK
2213 *
2214 * @retval None
2215 */
2216 __STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
2217 {
2218 }
2219
2220 /**
2221 * @brief Indicate whether the clock for I2C4 is forced to close.
2222 *
2223 * Register | BitsName
2224 * ----------|--------
2225 * PERIPH_GC | I2C4_HCLK
2226 *
2227 * @retval State of bit (1 or 0).
2228 */
2229 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
2230 {
2231 return 0;
2232 }
2233
2234 /**
2235 * @brief Enabling force to turn off the clock for I2C5.
2236 *
2237 * Register | BitsName
2238 * ----------|--------
2239 * PERIPH_GC | I2C5_HCLK
2240 *
2241 * @retval None
2242 */
2243 __STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
2244 {
2245 }
2246
2247 /**
2248 * @brief Disabling force to turn off the clock for I2C5.
2249 *
2250 * Register | BitsName
2251 * ----------|--------
2252 * PERIPH_GC | I2C5_HCLK
2253 *
2254 * @retval None
2255 */
2256 __STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
2257 {
2258 }
2259
2260 /**
2261 * @brief Indicate whether the clock for I2C5 is forced to close.
2262 *
2263 * Register | BitsName
2264 * ----------|--------
2265 * PERIPH_GC | I2C5_HCLK
2266 *
2267 * @retval State of bit (1 or 0).
2268 */
2269 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
2270 {
2271 return 0;
2272 }
2273
2274 /**
2275 * @brief Enabling force to turn off the clock for SPIM.
2276 *
2277 * Register | BitsName
2278 * ----------|--------
2279 * PERIPH_GC | SPIM_HCLK
2280 *
2281 * @retval None
2282 */
2283 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2284 {
2285 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_ENABLE;
2286 }
2287
2288 /**
2289 * @brief Disabling force to turn off the clock for SPIM.
2290 *
2291 * Register | BitsName
2292 * ----------|--------
2293 * PERIPH_GC | SPIM_HCLK
2294 *
2295 * @retval None
2296 */
2297 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2298 {
2299 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_DISABLE;
2300 }
2301
2302 /**
2303 * @brief Indicate whether the clock for SPIM is forced to close.
2304 *
2305 * Register | BitsName
2306 * ----------|--------
2307 * PERIPH_GC | SPIM_HCLK
2308 *
2309 * @retval State of bit (1 or 0).
2310 */
2311 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2312 {
2313 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2314 }
2315
2316 /**
2317 * @brief Enabling force to turn off the clock for SPIS.
2318 *
2319 * Register | BitsName
2320 * ----------|--------
2321 * PERIPH_GC | SPIS_HCLK
2322 *
2323 * @retval None
2324 */
2325 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2326 {
2327 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2328 }
2329
2330 /**
2331 * @brief Disabling force to turn off the clock for SPIS.
2332 *
2333 * Register | BitsName
2334 * ----------|--------
2335 * PERIPH_GC | SPIS_HCLK
2336 *
2337 * @retval None
2338 */
2339 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2340 {
2341 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2342 }
2343
2344 /**
2345 * @brief Indicate whether the clock for SPIS is forced to close.
2346 *
2347 * Register | BitsName
2348 * ----------|--------
2349 * PERIPH_GC | SPIS_HCLK
2350 *
2351 * @retval State of bit (1 or 0).
2352 */
2353 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2354 {
2355 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2356 }
2357
2358 /**
2359 * @brief Enabling force to turn off the clock for QSPI0.
2360 *
2361 * Register | BitsName
2362 * ----------|--------
2363 * PERIPH_GC | QSPI0_HCLK
2364 *
2365 * @retval None
2366 */
2367 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2368 {
2369 }
2370
2371 /**
2372 * @brief Disabling force to turn off the clock for QSPI0.
2373 *
2374 * Register | BitsName
2375 * ----------|--------
2376 * PERIPH_GC | QSPI0_HCLK
2377 *
2378 * @retval None
2379 */
2380 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2381 {
2382 }
2383
2384 /**
2385 * @brief Indicate whether the clock for QSPI0 is forced to close.
2386 *
2387 * Register | BitsName
2388 * ----------|--------
2389 * PERIPH_GC | QSPI0_HCLK
2390 *
2391 * @retval State of bit (1 or 0).
2392 */
2393 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2394 {
2395 return 0;
2396 }
2397
2398 /**
2399 * @brief Enabling force to turn off the clock for QSPI1.
2400 *
2401 * Register | BitsName
2402 * ----------|--------
2403 * PERIPH_GC | QSPI1_HCLK
2404 *
2405 * @retval None
2406 */
2407 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2408 {
2409 }
2410
2411 /**
2412 * @brief Disabling force to turn off the clock for QSPI1.
2413 *
2414 * Register | BitsName
2415 * ----------|--------
2416 * PERIPH_GC | QSPI1_HCLK
2417 *
2418 * @retval None
2419 */
2420 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2421 {
2422 }
2423
2424 /**
2425 * @brief Indicate whether the clock for QSPI1 is forced to close.
2426 *
2427 * Register | BitsName
2428 * ----------|--------
2429 * PERIPH_GC | QSPI1_HCLK
2430 *
2431 * @retval State of bit (1 or 0).
2432 */
2433 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2434 {
2435 return 0;
2436 }
2437
2438 /**
2439 * @brief Enabling force to turn off the clock for QSPI2.
2440 *
2441 * Register | BitsName
2442 * ----------|--------
2443 * PERIPH_GC | QSPI2_HCLK
2444 *
2445 * @retval None
2446 */
2447 __STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
2448 {
2449 }
2450
2451 /**
2452 * @brief Disabling force to turn off the clock for QSPI2.
2453 *
2454 * Register | BitsName
2455 * ----------|--------
2456 * PERIPH_GC | QSPI2_HCLK
2457 *
2458 * @retval None
2459 */
2460 __STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
2461 {
2462 }
2463
2464 /**
2465 * @brief Indicate whether the clock for QSPI2 is forced to close.
2466 *
2467 * Register | BitsName
2468 * ----------|--------
2469 * PERIPH_GC | QSPI2_HCLK
2470 *
2471 * @retval State of bit (1 or 0).
2472 */
2473 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
2474 {
2475 return 0;
2476 }
2477
2478
2479 /**
2480 * @brief Enabling force to turn off the clock for I2S master.
2481 *
2482 * Register | BitsName
2483 * ----------|--------
2484 * PERIPH_GC | I2S_HCLK
2485 *
2486 * @retval None
2487 */
2488 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2489 {
2490 }
2491
2492 /**
2493 * @brief Disabling force to turn off the clock for I2S master.
2494 *
2495 * Register | BitsName
2496 * ----------|--------
2497 * PERIPH_GC | I2S_HCLK
2498 *
2499 * @retval None
2500 */
2501 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2502 {
2503 }
2504
2505 /**
2506 * @brief Indicate whether the clock for I2S master is forced to close.
2507 *
2508 * Register | BitsName
2509 * ----------|--------
2510 * PERIPH_GC | I2S_HCLK
2511 *
2512 * @retval State of bit (1 or 0).
2513 */
2514 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2515 {
2516 return 0;
2517 }
2518
2519 /**
2520 * @brief Enabling force to turn off the clock for I2S slave.
2521 *
2522 * Register | BitsName
2523 * ----------|--------
2524 * PERIPH_GC | I2S_S_PCLK
2525 *
2526 * @retval None
2527 */
2528 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
2529 {
2530 }
2531
2532 /**
2533 * @brief Disabling force to turn off the clock for I2S slave.
2534 *
2535 * Register | BitsName
2536 * ----------|--------
2537 * PERIPH_GC | I2S_S_PCLK
2538 *
2539 * @retval None
2540 */
2541 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
2542 {
2543 }
2544
2545 /**
2546 * @brief Indicate whether the clock for I2S slave is forced to close.
2547 *
2548 * Register | BitsName
2549 * ----------|--------
2550 * PERIPH_GC | I2S_S_PCLK
2551 *
2552 * @retval State of bit (1 or 0).
2553 */
2554 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
2555 {
2556 return 0;
2557 }
2558
2559 /**
2560 * @brief Enabling force to turn off the clock for DSPI slave.
2561 *
2562 * Register | BitsName
2563 * ----------|--------
2564 * PERIPH_GC | DSPI_PCLK
2565 *
2566 * @retval None
2567 */
2568 __STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
2569 {
2570 }
2571
2572 /**
2573 * @brief Disabling force to turn off the clock for DSPI slave.
2574 *
2575 * Register | BitsName
2576 * ----------|--------
2577 * PERIPH_GC | DSPI_PCLK
2578 *
2579 * @retval None
2580 */
2581 __STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
2582 {
2583 }
2584
2585 /**
2586 * @brief Indicate whether the clock for DSPI is forced to close.
2587 *
2588 * Register | BitsName
2589 * ----------|--------
2590 * PERIPH_GC | DSPI_PCLK
2591 *
2592 * @retval State of bit (1 or 0).
2593 */
2594 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
2595 {
2596 return 0;
2597 }
2598
2599 /**
2600 * @brief Enabling force to turn off the clock for PDM slave.
2601 *
2602 * Register | BitsName
2603 * ----------|--------
2604 * PERIPH_GC | PDM_PCLK
2605 *
2606 * @retval None
2607 */
2608 __STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
2609 {
2610 }
2611
2612 /**
2613 * @brief Disabling force to turn off the clock for PDM slave.
2614 *
2615 * Register | BitsName
2616 * ----------|--------
2617 * PERIPH_GC | PDM_PCLK
2618 *
2619 * @retval None
2620 */
2621 __STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
2622 {
2623 }
2624
2625 /**
2626 * @brief Indicate whether the clock for PDM is forced to close.
2627 *
2628 * Register | BitsName
2629 * ----------|--------
2630 * PERIPH_GC | PDM_PCLK
2631 *
2632 * @retval State of bit (1 or 0).
2633 */
2634 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
2635 {
2636 return 0;
2637 }
2638
2639 /**
2640 * @brief Enabling force to turn off the div4 clock for security blocks.
2641 *
2642 * Register | BitsName
2643 * ----------|--------
2644 * PERIPH_GC | I2S_HCLK
2645 *
2646 * @retval None
2647 */
2648 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
2649 {
2650 }
2651
2652 /**
2653 * @brief Disabling force to turn off the div4 clock for security blocks.
2654 *
2655 * Register | BitsName
2656 * ----------|--------
2657 * PERIPH_GC | I2S_HCLK
2658 *
2659 * @retval None
2660 */
2661 __STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
2662 {
2663 }
2664
2665 /**
2666 * @brief Indicate whether the div4 clock for security blocks is forced to close.
2667 *
2668 * Register | BitsName
2669 * ----------|--------
2670 * PERIPH_GC | I2S_HCLK
2671 *
2672 * @retval State of bit (1 or 0).
2673 */
2674 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
2675 {
2676 return 0;
2677 }
2678 /**
2679 * @brief Enabling force to turn off the div4 clock for xf qspi blocks.
2680 *
2681 * Register | BitsName
2682 * ----------|--------
2683 * PERIPH_GC | XQSPI_HCLK
2684 *
2685 * @retval None
2686 */
2687 __STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
2688 {
2689 }
2690
2691 /**
2692 * @brief Disabling force to turn off the div4 clock for xf qspi blocks.
2693 *
2694 * Register | BitsName
2695 * ----------|--------
2696 * PERIPH_GC | XQSPI_HCLK
2697 *
2698 * @retval None
2699 */
2700 __STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
2701 {
2702 }
2703
2704 /**
2705 * @brief Indicate whether the div4 clock for xf qspi blocks is forced to close.
2706 *
2707 * Register | BitsName
2708 * ----------|--------
2709 * PERIPH_GC | XQSPI_HCLK
2710 *
2711 * @retval State of bit (1 or 0).
2712 */
2713 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
2714 {
2715 return 0;
2716 }
2717
2718 /**
2719 * @brief Enabling force to turn off the clock for PWM0.
2720 *
2721 * Register | BitsName
2722 * ----------|--------
2723 * PERIPH_GC | PWM0_PCLK
2724 *
2725 * @retval None
2726 */
2727 __STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
2728 {
2729 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2730 }
2731
2732 /**
2733 * @brief Disabling force to turn off the clock for PWM0.
2734 *
2735 * Register | BitsName
2736 * ----------|--------
2737 * PERIPH_GC | PWM0_PCLK
2738 *
2739 * @retval None
2740 */
2741 __STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
2742 {
2743 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2744 }
2745
2746 /**
2747 * @brief Indicate whether the clock for PWM0 is forced to close.
2748 *
2749 * Register | BitsName
2750 * ----------|--------
2751 * PERIPH_GC | PWM0_PCLK
2752 *
2753 * @retval State of bit (1 or 0).
2754 */
2755 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
2756 {
2757 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2758 }
2759
2760 /**
2761 * @brief Enabling force to turn off the clock for PWM1.
2762 *
2763 * Register | BitsName
2764 * ----------|--------
2765 * PERIPH_GC | PWM1_PCLK
2766 *
2767 * @retval None
2768 */
2769 __STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
2770 {
2771 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2772 }
2773
2774 /**
2775 * @brief Disabling force to turn off the clock for PWM1.
2776 *
2777 * Register | BitsName
2778 * ----------|--------
2779 * PERIPH_GC | PWM1_PCLK
2780 *
2781 * @retval None
2782 */
2783 __STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
2784 {
2785 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2786 }
2787
2788 /**
2789 * @brief Indicate whether the clock for PWM1 is forced to close.
2790 *
2791 * Register | BitsName
2792 * ----------|--------
2793 * PERIPH_GC | PWM1_PCLK
2794 *
2795 * @retval State of bit (1 or 0).
2796 */
2797 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
2798 {
2799 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2800 }
2801
2802 /**
2803 * @brief Enabling force to turn off the clock for VTTBL.
2804 *
2805 * Register | BitsName
2806 * ----------|--------
2807 * PERIPH_GC | VTTBL_PCLK
2808 *
2809 * @retval None
2810 */
2811 __STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
2812 {
2813 }
2814
2815 /**
2816 * @brief Disabling force to turn off the clock for VTTBL.
2817 *
2818 * Register | BitsName
2819 * ----------|--------
2820 * PERIPH_GC | VTTBL_PCLK
2821 *
2822 * @retval None
2823 */
2824 __STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
2825 {
2826 }
2827
2828 /**
2829 * @brief Indicate whether the clock for VTTBL is forced to close.
2830 *
2831 * Register | BitsName
2832 * ----------|--------
2833 * PERIPH_GC | VTTBL_PCLK
2834 *
2835 * @retval State of bit (1 or 0).
2836 */
2837 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
2838 {
2839 return 0;
2840 }
2841
2842 /**
2843 * @brief Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
2844 *
2845 * Register | BitsName
2846 * ---------|--------
2847 * CG_LP_EN | UART_LP_SCLK
2848 * CG_LP_EN | UART_LP_PCLK
2849 * CG_LP_EN | I2S_LP
2850 * CG_LP_EN | SPIM_LP_SCLK
2851 * CG_LP_EN | SPIS_LP_SCLK
2852 * CG_LP_EN | I2C_LP_SCLK
2853 * CG_LP_EN | AHB_BUS_LP
2854 *
2855 * @param clk_mask This parameter can be a combination of the following values:
2856 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN
2857 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN
2858 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
2859 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
2860 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
2861 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
2862 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
2863 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
2864 * @retval None
2865 */
2866 __STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
2867 {
2868 WRITE_REG(MCU_SUB->MCU_PERIPH_CG_LP_EN, clk_mask);
2869 }
2870
2871 /**
2872 * @brief Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
2873 *
2874 * Register | BitsName
2875 * ---------|--------
2876 * CG_LP_EN | UART_LP_SCLK
2877 * CG_LP_EN | UART_LP_PCLK
2878 * CG_LP_EN | I2S_LP
2879 * CG_LP_EN | SPIM_LP_SCLK
2880 * CG_LP_EN | SPIS_LP_SCLK
2881 * CG_LP_EN | I2C_LP_SCLK
2882 * CG_LP_EN | AHB_BUS_LP
2883 *
2884 * @retval Returned value can be a combination of the following values:
2885 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN
2886 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN
2887 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
2888 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
2889 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
2890 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
2891 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
2892 * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
2893 */
2894 __STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
2895 {
2896 return READ_REG(MCU_SUB->MCU_PERIPH_CG_LP_EN);
2897 }
2898
2899 /**
2900 * @brief Enable uart sclk low-power feature
2901 *
2902 * Register | BitsName
2903 * ---------|--------
2904 * CG_LP_EN | UART_LP_SCLK
2905 *
2906 * @retval None
2907 */
2908 __STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
2909 {
2910 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2911 }
2912
2913 /**
2914 * @brief Disable uart sclk low-power feature
2915 *
2916 * Register | BitsName
2917 * ---------|--------
2918 * CG_LP_EN | UART_LP_SCLK
2919 *
2920 * @retval None
2921 */
2922 __STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
2923 {
2924 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
2925 }
2926
2927 /**
2928 * @brief Indicate whether the uart sclk low-power is enabled.
2929 *
2930 * Register | BitsName
2931 * ---------|--------
2932 * CG_LP_EN | UART_LP_SCLK
2933 *
2934 * @retval State of bit (1 or 0).
2935 */
2936 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
2937 {
2938 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
2939 }
2940
2941 /**
2942 * @brief Enable uart pclk low-power feature
2943 *
2944 * Register | BitsName
2945 * ---------|--------
2946 * CG_LP_EN | UART_LP_PCLK
2947 *
2948 * @retval None
2949 */
2950 __STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
2951 {
2952 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_ENABLE;
2953 }
2954
2955 /**
2956 * @brief Disable uart pclk low-power feature
2957 *
2958 * Register | BitsName
2959 * ---------|--------
2960 * CG_LP_EN | UART_LP_PCLK
2961 *
2962 * @retval None
2963 */
2964 __STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
2965 {
2966 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_DISABLE;
2967 }
2968
2969 /**
2970 * @brief Indicate whether the uart pclk low-power is enabled.
2971 *
2972 * Register | BitsName
2973 * ---------|--------
2974 * CG_LP_EN | UART_LP_PCLK
2975 *
2976 * @retval State of bit (1 or 0).
2977 */
2978 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
2979 {
2980 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
2981 }
2982
2983 /**
2984 * @brief Enable i2s low-power feature
2985 *
2986 * Register | BitsName
2987 * ---------|--------
2988 * CG_LP_EN | I2S_LP
2989 *
2990 * @retval None
2991 */
2992 __STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
2993 {
2994 }
2995
2996 /**
2997 * @brief Disable i2s low-power feature
2998 *
2999 * Register | BitsName
3000 * ---------|--------
3001 * CG_LP_EN | I2S_LP
3002 *
3003 * @retval None
3004 */
3005 __STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
3006 {
3007 }
3008
3009 /**
3010 * @brief Indicate whether the i2s low-power is enabled.
3011 *
3012 * Register | BitsName
3013 * ---------|--------
3014 * CG_LP_EN | I2S_LP
3015 *
3016 * @retval State of bit (1 or 0).
3017 */
3018 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
3019 {
3020 return 0;
3021 }
3022
3023 /**
3024 * @brief Enable spim sclk low-power feature
3025 *
3026 * Register | BitsName
3027 * ---------|--------
3028 * CG_LP_EN | SPIM_LP_SCLK
3029 *
3030 * @retval None
3031 */
3032 __STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
3033 {
3034 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3035 }
3036
3037 /**
3038 * @brief Disable spim sclk low-power feature
3039 *
3040 * Register | BitsName
3041 * ---------|--------
3042 * CG_LP_EN | SPIM_LP_SCLK
3043 *
3044 * @retval None
3045 */
3046 __STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
3047 {
3048 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3049 }
3050
3051 /**
3052 * @brief Indicate whether the spim sclk low-power is enabled.
3053 *
3054 * Register | BitsName
3055 * ---------|--------
3056 * CG_LP_EN | SPIM_LP_SCLK
3057 *
3058 * @retval State of bit (1 or 0).
3059 */
3060 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
3061 {
3062 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3063 }
3064
3065 /**
3066 * @brief Enable spis sclk low-power feature
3067 *
3068 * Register | BitsName
3069 * ---------|--------
3070 * CG_LP_EN | SPIS_LP_SCLK
3071 *
3072 * @retval None
3073 */
3074 __STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
3075 {
3076 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3077 }
3078
3079 /**
3080 * @brief Disable spis sclk low-power feature
3081 *
3082 * Register | BitsName
3083 * ---------|--------
3084 * CG_LP_EN | SPIS_LP_SCLK
3085 *
3086 * @retval None
3087 */
3088 __STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
3089 {
3090 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3091 }
3092
3093 /**
3094 * @brief Indicate whether the spis sclk low-power is enabled.
3095 *
3096 * Register | BitsName
3097 * ---------|--------
3098 * CG_LP_EN | SPIS_LP_SCLK
3099 *
3100 * @retval State of bit (1 or 0).
3101 */
3102 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
3103 {
3104 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3105 }
3106
3107 /**
3108 * @brief Enable i2c sclk low-power feature
3109 *
3110 * Register | BitsName
3111 * ---------|--------
3112 * CG_LP_EN | I2C_LP_SCLK
3113 *
3114 * @retval None
3115 */
3116 __STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
3117 {
3118 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3119 }
3120
3121 /**
3122 * @brief Disable i2c sclk low-power feature
3123 *
3124 * Register | BitsName
3125 * ---------|--------
3126 * CG_LP_EN | I2C_LP_SCLK
3127 *
3128 * @retval None
3129 */
3130 __STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
3131 {
3132 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3133 }
3134
3135 /**
3136 * @brief Indicate whether the i2c sclk low-power is enabled.
3137 *
3138 * Register | BitsName
3139 * ---------|--------
3140 * CG_LP_EN | I2C_LP_SCLK
3141 *
3142 * @retval State of bit (1 or 0).
3143 */
3144 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
3145 {
3146 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3147 }
3148
3149 /**
3150 * @brief Enable ahb bus low-power feature
3151 *
3152 * Register | BitsName
3153 * ---------|--------
3154 * CG_LP_EN | AHB_BUS_LP
3155 *
3156 * @retval None
3157 */
3158 __STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
3159 {
3160 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3161 }
3162
3163 /**
3164 * @brief Disable ahb bus low-power feature
3165 *
3166 * Register | BitsName
3167 * ---------|--------
3168 * CG_LP_EN | AHB_BUS_LP
3169 *
3170 * @retval None
3171 */
3172 __STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
3173 {
3174 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3175 }
3176
3177 /**
3178 * @brief Indicate whether the ahb bus low-power is enabled.
3179 *
3180 * Register | BitsName
3181 * ---------|--------
3182 * CG_LP_EN | AHB_BUS_LP
3183 *
3184 * @retval State of bit (1 or 0).
3185 */
3186 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
3187 {
3188 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3189 }
3190
3191 /**
3192 * @brief Enable QSPIM low-power feature
3193 *
3194 * Register | BitsName
3195 * ---------|--------
3196 * CG_LP_EN | QSPIM_LP
3197 *
3198 * @retval None
3199 */
3200 __STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
3201 {
3202 }
3203
3204 /**
3205 * @brief Disable QSPIM low-power feature
3206 *
3207 * Register | BitsName
3208 * ---------|--------
3209 * CG_LP_EN | QSPIM_LP
3210 *
3211 * @retval None
3212 */
3213 __STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
3214 {
3215 }
3216
3217 /**
3218 * @brief Indicate whether the QSPIM low-power is enabled.
3219 *
3220 * Register | BitsName
3221 * ---------|--------
3222 * CG_LP_EN | QSPIM_LP
3223 *
3224 * @retval State of bit (1 or 0).
3225 */
3226 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
3227 {
3228 return 0;
3229 }
3230
3231 /**
3232 * @brief Enable AHB2APB bus low-power feature
3233 *
3234 * Register | BitsName
3235 * ---------|--------
3236 * CG_LP_EN | AHB2APB_BUS_LP
3237 *
3238 * @retval None
3239 */
3240 __STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
3241 {
3242 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3243 }
3244
3245 /**
3246 * @brief Disable AHB2APB bus low-power feature
3247 *
3248 * Register | BitsName
3249 * ---------|--------
3250 * CG_LP_EN | AHB2APB_BUS_LP
3251 *
3252 * @retval None
3253 */
3254 __STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
3255 {
3256 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3257 }
3258
3259 /**
3260 * @brief Indicate whether the AHB2APB bus low-power is enabled.
3261 *
3262 * Register | BitsName
3263 * ---------|--------
3264 * CG_LP_EN | AHB2APB_BUS_LP
3265 *
3266 * @retval State of bit (1 or 0).
3267 */
3268 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
3269 {
3270 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3271 }
3272
3273 /**
3274 * @brief Enable ahb bus low-power feature
3275 *
3276 * Register | BitsName
3277 * ---------|--------
3278 * CG_LP_EN | AHB_BUS_LP
3279 *
3280 * @retval None
3281 */
3282 __STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
3283 {
3284 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3285 }
3286
3287 /**
3288 * @brief Disable ahb bus low-power feature
3289 *
3290 * Register | BitsName
3291 * ---------|--------
3292 * CG_LP_EN | AHB_BUS_LP
3293 *
3294 * @retval None
3295 */
3296 __STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
3297 {
3298 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3299 }
3300
3301 /**
3302 * @brief Indicate whether the ahb bus low-power is enabled.
3303 *
3304 * Register | BitsName
3305 * ---------|--------
3306 * CG_LP_EN | AHB_BUS_LP
3307 *
3308 * @retval State of bit (1 or 0).
3309 */
3310 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
3311 {
3312 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3313 }
3314
3315 /**
3316 * @brief Enable turn UART0 off during WFI/WFE
3317 *
3318 * Register | BitsName
3319 * ---------|--------
3320 * CLK_SLP_OFF | UART0_SLP
3321 *
3322 * @retval None
3323 */
3324 __STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
3325 {
3326 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_ENABLE;
3327 }
3328
3329 /**
3330 * @brief Disable turn UART0 off during WFI/WFE
3331 *
3332 * Register | BitsName
3333 * ---------|--------
3334 * CLK_SLP_OFF | UART0_SLP
3335 *
3336 * @retval None
3337 */
3338 __STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
3339 {
3340 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_DISABLE;
3341 }
3342
3343 /**
3344 * @brief Indicate whether turn UART0 off during WFI/WFE is enabled.
3345 *
3346 * Register | BitsName
3347 * ---------|--------
3348 * CLK_SLP_OFF | UART0_SLP
3349 *
3350 * @retval State of bit (1 or 0).
3351 */
3352 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
3353 {
3354 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) == (CGC_CLOCK_ENABLE));
3355 }
3356
3357 /**
3358 * @brief Enable turn UART1 off during WFI/WFE
3359 *
3360 * Register | BitsName
3361 * ---------|--------
3362 * CLK_SLP_OFF | UART1_SLP
3363 *
3364 * @retval None
3365 */
3366 __STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
3367 {
3368 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_ENABLE;
3369 }
3370
3371 /**
3372 * @brief Disable turn UART1 off during WFI/WFE
3373 *
3374 * Register | BitsName
3375 * ---------|--------
3376 * CLK_SLP_OFF | UART1_SLP
3377 *
3378 * @retval None
3379 */
3380 __STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
3381 {
3382 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_DISABLE;
3383 }
3384
3385 /**
3386 * @brief Indicate whether turn UART1 off during WFI/WFE is enabled.
3387 *
3388 * Register | BitsName
3389 * ---------|--------
3390 * CLK_SLP_OFF | UART1_SLP
3391 *
3392 * @retval State of bit (1 or 0).
3393 */
3394 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
3395 {
3396 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) == (CGC_CLOCK_ENABLE));
3397 }
3398
3399 /**
3400 * @brief Enable turn UART2 off during WFI/WFE
3401 *
3402 * Register | BitsName
3403 * ---------|--------
3404 * CLK_SLP_OFF | UART2_SLP
3405 *
3406 * @retval None
3407 */
3408 __STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
3409 {
3410 }
3411
3412 /**
3413 * @brief Disable turn UART2 off during WFI/WFE
3414 *
3415 * Register | BitsName
3416 * ---------|--------
3417 * CLK_SLP_OFF | UART2_SLP
3418 *
3419 * @retval None
3420 */
3421 __STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
3422 {
3423 }
3424
3425 /**
3426 * @brief Indicate whether turn UART2 off during WFI/WFE is enabled.
3427 *
3428 * Register | BitsName
3429 * ---------|--------
3430 * CLK_SLP_OFF | UART2_SLP
3431 *
3432 * @retval State of bit (1 or 0).
3433 */
3434 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
3435 {
3436 return 0;
3437 }
3438
3439 /**
3440 * @brief Enable turn UART3 off during WFI/WFE
3441 *
3442 * Register | BitsName
3443 * ---------|--------
3444 * CLK_SLP_OFF | UART3_SLP
3445 *
3446 * @retval None
3447 */
3448 __STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
3449 {
3450 }
3451
3452 /**
3453 * @brief Disable turn UART3 off during WFI/WFE
3454 *
3455 * Register | BitsName
3456 * ---------|--------
3457 * CLK_SLP_OFF | UART3_SLP
3458 *
3459 * @retval None
3460 */
3461 __STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
3462 {
3463 }
3464
3465 /**
3466 * @brief Indicate whether turn UART3 off during WFI/WFE is enabled.
3467 *
3468 * Register | BitsName
3469 * ---------|--------
3470 * CLK_SLP_OFF | UART3_SLP
3471 *
3472 * @retval State of bit (1 or 0).
3473 */
3474 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
3475 {
3476 return 0;
3477 }
3478
3479 /**
3480 * @brief Enable turn UART4 off during WFI/WFE
3481 *
3482 * Register | BitsName
3483 * ---------|--------
3484 * CLK_SLP_OFF | UART4_SLP
3485 *
3486 * @retval None
3487 */
3488 __STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
3489 {
3490 }
3491
3492 /**
3493 * @brief Disable turn UART4 off during WFI/WFE
3494 *
3495 * Register | BitsName
3496 * ---------|--------
3497 * CLK_SLP_OFF | UART4_SLP
3498 *
3499 * @retval None
3500 */
3501 __STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
3502 {
3503 }
3504
3505 /**
3506 * @brief Indicate whether turn UART4 off during WFI/WFE is enabled.
3507 *
3508 * Register | BitsName
3509 * ---------|--------
3510 * CLK_SLP_OFF | UART4_SLP
3511 *
3512 * @retval State of bit (1 or 0).
3513 */
3514 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
3515 {
3516 return 0;
3517 }
3518
3519 /**
3520 * @brief Enable turn UART5 off during WFI/WFE
3521 *
3522 * Register | BitsName
3523 * ---------|--------
3524 * CLK_SLP_OFF | UART5_SLP
3525 *
3526 * @retval None
3527 */
3528 __STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
3529 {
3530 }
3531
3532 /**
3533 * @brief Disable turn UART5 off during WFI/WFE
3534 *
3535 * Register | BitsName
3536 * ---------|--------
3537 * CLK_SLP_OFF | UART5_SLP
3538 *
3539 * @retval None
3540 */
3541 __STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
3542 {
3543 }
3544
3545 /**
3546 * @brief Indicate whether turn UART5 off during WFI/WFE is enabled.
3547 *
3548 * Register | BitsName
3549 * ---------|--------
3550 * CLK_SLP_OFF | UART5_SLP
3551 *
3552 * @retval State of bit (1 or 0).
3553 */
3554 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
3555 {
3556 return 0;
3557 }
3558
3559 /**
3560 * @brief Enable turn I2C0 off during WFI/WFE
3561 *
3562 * Register | BitsName
3563 * ---------|--------
3564 * CLK_SLP_OFF | I2C0_SLP
3565 *
3566 * @retval None
3567 */
3568 __STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
3569 {
3570 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_ENABLE;
3571 }
3572
3573 /**
3574 * @brief Disable turn I2C0 off during WFI/WFE
3575 *
3576 * Register | BitsName
3577 * ---------|--------
3578 * CLK_SLP_OFF | I2C0_SLP
3579 *
3580 * @retval None
3581 */
3582 __STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
3583 {
3584 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_DISABLE;
3585 }
3586
3587 /**
3588 * @brief Indicate whether turn I2C0 off during WFI/WFE is enabled.
3589 *
3590 * Register | BitsName
3591 * ---------|--------
3592 * CLK_SLP_OFF | I2C0_SLP
3593 *
3594 * @retval State of bit (1 or 0).
3595 */
3596 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
3597 {
3598 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) == (CGC_CLOCK_ENABLE));
3599 }
3600
3601 /**
3602 * @brief Enable turn I2C1 off during WFI/WFE
3603 *
3604 * Register | BitsName
3605 * ---------|--------
3606 * CLK_SLP_OFF | I2C1_SLP
3607 *
3608 * @retval None
3609 */
3610 __STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
3611 {
3612 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_ENABLE;
3613 }
3614
3615 /**
3616 * @brief Disable turn I2C1 off during WFI/WFE
3617 *
3618 * Register | BitsName
3619 * ---------|--------
3620 * CLK_SLP_OFF | I2C1_SLP
3621 *
3622 * @retval None
3623 */
3624 __STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
3625 {
3626 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_DISABLE;
3627 }
3628
3629 /**
3630 * @brief Indicate whether turn I2C1 off during WFI/WFE is enabled.
3631 *
3632 * Register | BitsName
3633 * ---------|--------
3634 * CLK_SLP_OFF | I2C1_SLP
3635 *
3636 * @retval State of bit (1 or 0).
3637 */
3638 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
3639 {
3640 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) == (CGC_CLOCK_ENABLE));
3641 }
3642
3643 /**
3644 * @brief Enable turn I2C2 off during WFI/WFE
3645 *
3646 * Register | BitsName
3647 * ---------|--------
3648 * CLK_SLP_OFF | I2C2_SLP
3649 *
3650 * @retval None
3651 */
3652 __STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
3653 {
3654 }
3655
3656 /**
3657 * @brief Disable turn I2C2 off during WFI/WFE
3658 *
3659 * Register | BitsName
3660 * ---------|--------
3661 * CLK_SLP_OFF | I2C2_SLP
3662 *
3663 * @retval None
3664 */
3665 __STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
3666 {
3667 }
3668
3669 /**
3670 * @brief Indicate whether turn I2C2 off during WFI/WFE is enabled.
3671 *
3672 * Register | BitsName
3673 * ---------|--------
3674 * CLK_SLP_OFF | I2C2_SLP
3675 *
3676 * @retval State of bit (1 or 0).
3677 */
3678 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
3679 {
3680 return 0;
3681 }
3682
3683 /**
3684 * @brief Enable turn I2C3 off during WFI/WFE
3685 *
3686 * Register | BitsName
3687 * ---------|--------
3688 * CLK_SLP_OFF | I2C3_SLP
3689 *
3690 * @retval None
3691 */
3692 __STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
3693 {
3694 }
3695
3696 /**
3697 * @brief Disable turn I2C3 off during WFI/WFE
3698 *
3699 * Register | BitsName
3700 * ---------|--------
3701 * CLK_SLP_OFF | I2C3_SLP
3702 *
3703 * @retval None
3704 */
3705 __STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
3706 {
3707 }
3708
3709 /**
3710 * @brief Indicate whether turn I2C3 off during WFI/WFE is enabled.
3711 *
3712 * Register | BitsName
3713 * ---------|--------
3714 * CLK_SLP_OFF | I2C3_SLP
3715 *
3716 * @retval State of bit (1 or 0).
3717 */
3718 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
3719 {
3720 return 0;
3721 }
3722
3723 /**
3724 * @brief Enable turn I2C4 off during WFI/WFE
3725 *
3726 * Register | BitsName
3727 * ---------|--------
3728 * CLK_SLP_OFF | I2C4_SLP
3729 *
3730 * @retval None
3731 */
3732 __STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
3733 {
3734 }
3735
3736 /**
3737 * @brief Disable turn I2C4 off during WFI/WFE
3738 *
3739 * Register | BitsName
3740 * ---------|--------
3741 * CLK_SLP_OFF | I2C4_SLP
3742 *
3743 * @retval None
3744 */
3745 __STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
3746 {
3747 }
3748
3749 /**
3750 * @brief Indicate whether turn I2C4 off during WFI/WFE is enabled.
3751 *
3752 * Register | BitsName
3753 * ---------|--------
3754 * CLK_SLP_OFF | I2C4_SLP
3755 *
3756 * @retval State of bit (1 or 0).
3757 */
3758 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
3759 {
3760 return 0;
3761 }
3762
3763 /**
3764 * @brief Enable turn I2C5 off during WFI/WFE
3765 *
3766 * Register | BitsName
3767 * ---------|--------
3768 * CLK_SLP_OFF | I2C5_SLP
3769 *
3770 * @retval None
3771 */
3772 __STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
3773 {
3774 }
3775
3776 /**
3777 * @brief Disable turn I2C5 off during WFI/WFE
3778 *
3779 * Register | BitsName
3780 * ---------|--------
3781 * CLK_SLP_OFF | I2C5_SLP
3782 *
3783 * @retval None
3784 */
3785 __STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
3786 {
3787 }
3788
3789 /**
3790 * @brief Indicate whether turn I2C5 off during WFI/WFE is enabled.
3791 *
3792 * Register | BitsName
3793 * ---------|--------
3794 * CLK_SLP_OFF | I2C5_SLP
3795 *
3796 * @retval State of bit (1 or 0).
3797 */
3798 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
3799 {
3800 return 0;
3801 }
3802
3803 /**
3804 * @brief Enable turn I2S_M off during WFI/WFE
3805 *
3806 * Register | BitsName
3807 * ---------|--------
3808 * CLK_SLP_OFF | I2SM_SLP
3809 *
3810 * @retval None
3811 */
3812 __STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
3813 {
3814 }
3815
3816 /**
3817 * @brief Disable turn I2S_M off during WFI/WFE
3818 *
3819 * Register | BitsName
3820 * ---------|--------
3821 * CLK_SLP_OFF | I2SM_SLP
3822 *
3823 * @retval None
3824 */
3825 __STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
3826 {
3827 }
3828
3829 /**
3830 * @brief Indicate whether turn I2S_M off during WFI/WFE is enabled.
3831 *
3832 * Register | BitsName
3833 * ---------|--------
3834 * CLK_SLP_OFF | I2SM_SLP
3835 *
3836 * @retval State of bit (1 or 0).
3837 */
3838 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
3839 {
3840 return 0;
3841 }
3842
3843 /**
3844 * @brief Enable turn I2S_S off during WFI/WFE
3845 *
3846 * Register | BitsName
3847 * ---------|--------
3848 * CLK_SLP_OFF | I2SS_SLP
3849 *
3850 * @retval None
3851 */
3852 __STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
3853 {
3854 }
3855
3856 /**
3857 * @brief Disable turn I2S_S off during WFI/WFE
3858 *
3859 * Register | BitsName
3860 * ---------|--------
3861 * CLK_SLP_OFF | I2SS_SLP
3862 *
3863 * @retval None
3864 */
3865 __STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
3866 {
3867 }
3868
3869 /**
3870 * @brief Indicate whether turn I2S_S off during WFI/WFE is enabled.
3871 *
3872 * Register | BitsName
3873 * ---------|--------
3874 * CLK_SLP_OFF | I2SS_SLP
3875 *
3876 * @retval State of bit (1 or 0).
3877 */
3878 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
3879 {
3880 return 0;
3881 }
3882
3883 /**
3884 * @brief Enable turn SPI_M off during WFI/WFE
3885 *
3886 * Register | BitsName
3887 * ---------|--------
3888 * CLK_SLP_OFF | SPIM_SLP
3889 *
3890 * @retval None
3891 */
3892 __STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
3893 {
3894 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_ENABLE;
3895 }
3896
3897 /**
3898 * @brief Disable turn SPI_M off during WFI/WFE
3899 *
3900 * Register | BitsName
3901 * ---------|--------
3902 * CLK_SLP_OFF | SPIM_SLP
3903 *
3904 * @retval None
3905 */
3906 __STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
3907 {
3908 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_DISABLE;
3909 }
3910
3911 /**
3912 * @brief Indicate whether turn SPI_M off during WFI/WFE is enabled.
3913 *
3914 * Register | BitsName
3915 * ---------|--------
3916 * CLK_SLP_OFF | SPIM_SLP
3917 *
3918 * @retval State of bit (1 or 0).
3919 */
3920 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
3921 {
3922 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) == (CGC_CLOCK_ENABLE));
3923 }
3924
3925 /**
3926 * @brief Enable turn SPI_S off during WFI/WFE
3927 *
3928 * Register | BitsName
3929 * ---------|--------
3930 * CLK_SLP_OFF | SPIS_SLP
3931 *
3932 * @retval None
3933 */
3934 __STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
3935 {
3936 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_ENABLE;
3937 }
3938
3939 /**
3940 * @brief Disable turn SPI_S off during WFI/WFE
3941 *
3942 * Register | BitsName
3943 * ---------|--------
3944 * CLK_SLP_OFF | SPIS_SLP
3945 *
3946 * @retval None
3947 */
3948 __STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
3949 {
3950 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_DISABLE;
3951 }
3952
3953 /**
3954 * @brief Indicate whether turn SPI_S off during WFI/WFE is enabled.
3955 *
3956 * Register | BitsName
3957 * ---------|--------
3958 * CLK_SLP_OFF | SPIS_SLP
3959 *
3960 * @retval State of bit (1 or 0).
3961 */
3962 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
3963 {
3964 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) == (CGC_CLOCK_ENABLE));
3965 }
3966
3967 /**
3968 * @brief Enable turn pwm0 off during WFI/WFE
3969 *
3970 * Register | BitsName
3971 * ---------|--------
3972 * CLK_SLP_OFF | PWM0_SLP
3973 *
3974 * @retval None
3975 */
3976 __STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
3977 {
3978 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_ENABLE;
3979 }
3980
3981 /**
3982 * @brief Disable turn pwm0 off during WFI/WFE
3983 *
3984 * Register | BitsName
3985 * ---------|--------
3986 * CLK_SLP_OFF | PWM0_SLP
3987 *
3988 * @retval None
3989 */
3990 __STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
3991 {
3992 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_DISABLE;
3993 }
3994
3995 /**
3996 * @brief Indicate whether turn pwm0 off during WFI/WFE is enabled.
3997 *
3998 * Register | BitsName
3999 * ---------|--------
4000 * CLK_SLP_OFF | PWM0_SLP
4001 *
4002 * @retval State of bit (1 or 0).
4003 */
4004 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
4005 {
4006 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) == (CGC_CLOCK_ENABLE));
4007 }
4008
4009 /**
4010 * @brief Enable turn pwm1 off during WFI/WFE
4011 *
4012 * Register | BitsName
4013 * ---------|--------
4014 * CLK_SLP_OFF | PWM1_SLP
4015 *
4016 * @retval None
4017 */
4018 __STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
4019 {
4020 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_ENABLE;
4021 }
4022
4023 /**
4024 * @brief Disable turn pwm1 off during WFI/WFE
4025 *
4026 * Register | BitsName
4027 * ---------|--------
4028 * CLK_SLP_OFF | PWM1_SLP
4029 *
4030 * @retval None
4031 */
4032 __STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
4033 {
4034 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_DISABLE;
4035 }
4036
4037 /**
4038 * @brief Indicate whether turn pwm1 off during WFI/WFE is enabled.
4039 *
4040 * Register | BitsName
4041 * ---------|--------
4042 * CLK_SLP_OFF | PWM1_SLP
4043 *
4044 * @retval State of bit (1 or 0).
4045 */
4046 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
4047 {
4048 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) == (CGC_CLOCK_ENABLE));
4049 }
4050
4051 /**
4052 * @brief Enable turn QSPIM0 off during WFI/WFE
4053 *
4054 * Register | BitsName
4055 * ---------|--------
4056 * CLK_SLP_OFF | QSPIM0_SLP
4057 *
4058 * @retval None
4059 */
4060 __STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
4061 {
4062 }
4063
4064 /**
4065 * @brief Disable turn QSPIM0 off during WFI/WFE
4066 *
4067 * Register | BitsName
4068 * ---------|--------
4069 * CLK_SLP_OFF | QSPIM0_SLP
4070 *
4071 * @retval None
4072 */
4073 __STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
4074 {
4075 }
4076
4077 /**
4078 * @brief Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
4079 *
4080 * Register | BitsName
4081 * ---------|--------
4082 * CLK_SLP_OFF | QSPIM0_SLP
4083 *
4084 * @retval State of bit (1 or 0).
4085 */
4086 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
4087 {
4088 return 0;
4089 }
4090
4091 /**
4092 * @brief Enable turn QSPIM1 off during WFI/WFE
4093 *
4094 * Register | BitsName
4095 * ---------|--------
4096 * CLK_SLP_OFF | QSPIM1_SLP
4097 *
4098 * @retval None
4099 */
4100 __STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
4101 {
4102 }
4103
4104 /**
4105 * @brief Disable turn QSPIM1 off during WFI/WFE
4106 *
4107 * Register | BitsName
4108 * ---------|--------
4109 * CLK_SLP_OFF | QSPIM1_SLP
4110 *
4111 * @retval None
4112 */
4113 __STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
4114 {
4115 }
4116
4117 /**
4118 * @brief Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
4119 *
4120 * Register | BitsName
4121 * ---------|--------
4122 * CLK_SLP_OFF | QSPIM1_SLP
4123 *
4124 * @retval State of bit (1 or 0).
4125 */
4126 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
4127 {
4128 return 0;
4129 }
4130
4131 /**
4132 * @brief Enable turn QSPIM2 off during WFI/WFE
4133 *
4134 * Register | BitsName
4135 * ---------|--------
4136 * CLK_SLP_OFF | QSPIM2_SLP
4137 *
4138 * @retval None
4139 */
4140 __STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
4141 {
4142 }
4143
4144 /**
4145 * @brief Disable turn QSPIM2 off during WFI/WFE
4146 *
4147 * Register | BitsName
4148 * ---------|--------
4149 * CLK_SLP_OFF | QSPIM2_SLP
4150 *
4151 * @retval None
4152 */
4153 __STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
4154 {
4155 }
4156
4157 /**
4158 * @brief Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
4159 *
4160 * Register | BitsName
4161 * ---------|--------
4162 * CLK_SLP_OFF | QSPIM2_SLP
4163 *
4164 * @retval State of bit (1 or 0).
4165 */
4166 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
4167 {
4168 return 0;
4169 }
4170
4171 /**
4172 * @brief Enable turn DSPI off during WFI/WFE
4173 *
4174 * Register | BitsName
4175 * ---------|--------
4176 * CLK_SLP_OFF | DSPI_SLP
4177 *
4178 * @retval None
4179 */
4180 __STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
4181 {
4182 }
4183
4184 /**
4185 * @brief Disable turn DSPI off during WFI/WFE
4186 *
4187 * Register | BitsName
4188 * ---------|--------
4189 * CLK_SLP_OFF | DSPI_SLP
4190 *
4191 * @retval None
4192 */
4193 __STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
4194 {
4195 }
4196
4197 /**
4198 * @brief Indicate whether turn DSPI off during WFI/WFE is enabled.
4199 *
4200 * Register | BitsName
4201 * ---------|--------
4202 * CLK_SLP_OFF | DSPI_SLP
4203 *
4204 * @retval State of bit (1 or 0).
4205 */
4206 __STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
4207 {
4208 return 0;
4209 }
4210
4211 /**
4212 * @brief Enable turn PDM off during WFI/WFE
4213 *
4214 * Register | BitsName
4215 * ---------|--------
4216 * CLK_SLP_OFF | PDM_SLP
4217 *
4218 * @retval None
4219 */
4220 __STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
4221 {
4222 }
4223
4224 /**
4225 * @brief Disable turn PDM off during WFI/WFE
4226 *
4227 * Register | BitsName
4228 * ---------|--------
4229 * CLK_SLP_OFF | PDM_SLP
4230 *
4231 * @retval None
4232 */
4233 __STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
4234 {
4235 }
4236
4237 /**
4238 * @brief Indicate whether turn PDM off during WFI/WFE is enabled.
4239 *
4240 * Register | BitsName
4241 * ---------|--------
4242 * CLK_SLP_OFF | PDM_SLP
4243 *
4244 * @retval State of bit (1 or 0).
4245 */
4246 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
4247 {
4248 return 0;
4249 }
4250
4251 /**
4252 * @brief Individual block's clock control inside security system which was forced to turn off (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4253 *
4254 * Register | BitsName
4255 * ----------|--------
4256 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4257 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4258 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4259 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4260 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4261 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4262 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4263 *
4264 * @param clk_mask This parameter can be a combination of the following values:
4265 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4266 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4267 * @retval None
4268 */
4269 __STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
4270 {
4271 MODIFY_REG(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
4272 }
4273
4274 /**
4275 * @brief Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4276 *
4277 * Register | BitsName
4278 * ----------|--------
4279 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4280 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4281 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4282 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4283 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4284 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4285 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4286 *
4287 * @retval Returned value can be a combination of the following values:
4288 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4289 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4290 */
4291 __STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
4292 {
4293 return READ_BITS(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
4294 }
4295
4296 /**
4297 * @brief Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4298 *
4299 * Register | BitsName
4300 * ----------|--------
4301 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4302 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4303 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4304 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4305 *
4306 * @param clk_mask This parameter can be a combination of the following values:
4307 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4308 * @arg @ref LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN
4309 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4310 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
4311 * @retval None
4312 */
4313 __STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
4314 {
4315 MODIFY_REG(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
4316 }
4317
4318 /**
4319 * @brief Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4320 *
4321 * Register | BitsName
4322 * ----------|--------
4323 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4324 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4325 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4326 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4327 *
4328 * @retval Returned value can be a combination of the following values:
4329 * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4330 * @arg @ref LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN
4331 * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4332 * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
4333 */
4334 __STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
4335 {
4336 return READ_BITS(MCU_SUB->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
4337 }
4338
4339 /**
4340 * @brief Enabling force to turn off the clock for AES.
4341 *
4342 * Register | BitsName
4343 * ----------|--------
4344 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4345 *
4346 * @retval None
4347 */
4348 __STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
4349 {
4350 }
4351
4352 /**
4353 * @brief Disabling force to turn off the clock for AES.
4354 *
4355 * Register | BitsName
4356 * ----------|--------
4357 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4358 *
4359 * @retval None
4360 */
4361 __STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
4362 {
4363 }
4364
4365 /**
4366 * @brief Indicate whether the clock for AES is forced to close.
4367 *
4368 * Register | BitsName
4369 * ----------|--------
4370 * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4371 *
4372 * @retval State of bit (1 or 0).
4373 */
4374 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
4375 {
4376 return 0;
4377 }
4378
4379 /**
4380 * @brief Enabling force to turn off the clock for HMAC.
4381 *
4382 * Register | BitsName
4383 * ----------|--------
4384 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4385 *
4386 * @retval None
4387 */
4388 __STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
4389 {
4390 }
4391
4392 /**
4393 * @brief Disabling force to turn off the clock for HMAC.
4394 *
4395 * Register | BitsName
4396 * ----------|--------
4397 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4398 *
4399 * @retval None
4400 */
4401 __STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
4402 {
4403 }
4404
4405 /**
4406 * @brief Indicate whether the clock for HMAC is forced to close.
4407 *
4408 * Register | BitsName
4409 * ----------|--------
4410 * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4411 *
4412 * @retval State of bit (1 or 0).
4413 */
4414 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
4415 {
4416 return 0;
4417 }
4418
4419 /**
4420 * @brief Enabling force to turn off the clock for PKC.
4421 *
4422 * Register | BitsName
4423 * ----------|--------
4424 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4425 *
4426 * @retval None
4427 */
4428 __STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
4429 {
4430 }
4431
4432 /**
4433 * @brief Disabling force to turn off the clock for PKC.
4434 *
4435 * Register | BitsName
4436 * ----------|--------
4437 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4438 *
4439 * @retval None
4440 */
4441 __STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
4442 {
4443 }
4444
4445 /**
4446 * @brief Indicate whether the clock for PKC is forced to close.
4447 *
4448 * Register | BitsName
4449 * ----------|--------
4450 * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4451 *
4452 * @retval State of bit (1 or 0).
4453 */
4454 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
4455 {
4456 return 0;
4457 }
4458
4459 /**
4460 * @brief Enabling force to turn off the clock for PRESENT.
4461 *
4462 * Register | BitsName
4463 * ----------|--------
4464 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4465 *
4466 * @retval None
4467 */
4468 __STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
4469 {
4470 }
4471
4472 /**
4473 * @brief Disabling force to turn off the clock for PRESENT.
4474 *
4475 * Register | BitsName
4476 * ----------|--------
4477 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4478 *
4479 * @retval None
4480 */
4481 __STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
4482 {
4483 }
4484
4485 /**
4486 * @brief Indicate whether the clock for PRESENT is forced to close.
4487 *
4488 * Register | BitsName
4489 * ----------|--------
4490 * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4491 *
4492 * @retval State of bit (1 or 0).
4493 */
4494 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
4495 {
4496 return 0;
4497 }
4498
4499 /**
4500 * @brief Enabling force to turn off the clock for RAMKEY.
4501 *
4502 * Register | BitsName
4503 * ----------|--------
4504 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4505 *
4506 * @retval None
4507 */
4508 __STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
4509 {
4510 }
4511
4512 /**
4513 * @brief Disabling force to turn off the clock for RAMKEY.
4514 *
4515 * Register | BitsName
4516 * ----------|--------
4517 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4518 *
4519 * @retval None
4520 */
4521 __STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
4522 {
4523 }
4524
4525 /**
4526 * @brief Indicate whether the clock for RAMKEY is forced to close.
4527 *
4528 * Register | BitsName
4529 * ----------|--------
4530 * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4531 *
4532 * @retval State of bit (1 or 0).
4533 */
4534 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
4535 {
4536 return 0;
4537 }
4538
4539
4540 /**
4541 * @brief Enabling force to turn off the clock for RNG.
4542 *
4543 * Register | BitsName
4544 * ----------|--------
4545 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4546 *
4547 * @retval None
4548 */
4549 __STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
4550 {
4551 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4552 }
4553
4554 /**
4555 * @brief Disabling force to turn off the clock for RNG.
4556 *
4557 * Register | BitsName
4558 * ----------|--------
4559 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4560 *
4561 * @retval None
4562 */
4563 __STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
4564 {
4565 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4566 }
4567
4568 /**
4569 * @brief Indicate whether the clock for RNG is forced to close.
4570 *
4571 * Register | BitsName
4572 * ----------|--------
4573 * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4574 *
4575 * @retval State of bit (1 or 0).
4576 */
4577 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
4578 {
4579 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4580 }
4581
4582 /**
4583 * @brief Enabling force to turn off the clock for EFUSE.
4584 *
4585 * Register | BitsName
4586 * ----------|--------
4587 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4588 *
4589 * @retval None
4590 */
4591 __STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
4592 {
4593 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4594 }
4595
4596 /**
4597 * @brief Disabling force to turn off the clock for EFUSE.
4598 *
4599 * Register | BitsName
4600 * ----------|--------
4601 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4602 *
4603 * @retval None
4604 */
4605 __STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
4606 {
4607 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4608 }
4609
4610 /**
4611 * @brief Indicate whether the clock for EFUSE is forced to close.
4612 *
4613 * Register | BitsName
4614 * ----------|--------
4615 * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4616 *
4617 * @retval State of bit (1 or 0).
4618 */
4619 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
4620 {
4621 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4622 }
4623
4624 /**
4625 * @brief Enable AES automatic turn off clock during WFI/WFE
4626 *
4627 * Register | BitsName
4628 * ----------|--------
4629 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4630 *
4631 * @retval None
4632 */
4633 __STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
4634 {
4635 }
4636
4637 /**
4638 * @brief Disable AES automatic turn off clock during WFI/WFE
4639 *
4640 * Register | BitsName
4641 * ----------|--------
4642 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4643 *
4644 * @retval None
4645 */
4646 __STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
4647 {
4648 }
4649
4650 /**
4651 * @brief Indicate whether the AES automatic turn off clock is enabled.
4652 *
4653 * Register | BitsName
4654 * ----------|--------
4655 * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4656 *
4657 * @retval State of bit (1 or 0).
4658 */
4659 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
4660 {
4661 return 0;
4662 }
4663
4664 /**
4665 * @brief Enable HMAC automatic turn off clock during WFI/WFE
4666 *
4667 * Register | BitsName
4668 * ----------|--------
4669 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4670 *
4671 * @retval None
4672 */
4673 __STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
4674 {
4675 }
4676
4677 /**
4678 * @brief Disable HMAC automatic turn off clock during WFI/WFE
4679 *
4680 * Register | BitsName
4681 * ----------|--------
4682 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4683 *
4684 * @retval None
4685 */
4686 __STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
4687 {
4688 }
4689
4690 /**
4691 * @brief Indicate whether the HMAC automatic turn off clock is enabled.
4692 *
4693 * Register | BitsName
4694 * ----------|--------
4695 * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4696 *
4697 * @retval State of bit (1 or 0).
4698 */
4699 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
4700 {
4701 return 0;
4702 }
4703
4704 /**
4705 * @brief Enable PKC automatic turn off clock during WFI/WFE
4706 *
4707 * Register | BitsName
4708 * ----------|--------
4709 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4710 *
4711 * @retval None
4712 */
4713 __STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
4714 {
4715 }
4716
4717 /**
4718 * @brief Disable PKC automatic turn off clock during WFI/WFE
4719 *
4720 * Register | BitsName
4721 * ----------|--------
4722 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4723 *
4724 * @retval None
4725 */
4726 __STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
4727 {
4728 }
4729
4730 /**
4731 * @brief Indicate whether the PKC automatic turn off clock is enabled.
4732 *
4733 * Register | BitsName
4734 * ----------|--------
4735 * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4736 *
4737 * @retval State of bit (1 or 0).
4738 */
4739 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
4740 {
4741 return 0;
4742 }
4743
4744 /**
4745 * @brief Enable PRESENT automatic turn off clock during WFI/WFE
4746 *
4747 * Register | BitsName
4748 * ----------|--------
4749 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4750 *
4751 * @retval None
4752 */
4753 __STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
4754 {
4755 }
4756
4757 /**
4758 * @brief Disable PRESENT automatic turn off clock during WFI/WFE
4759 *
4760 * Register | BitsName
4761 * ----------|--------
4762 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4763 *
4764 * @retval None
4765 */
4766 __STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
4767 {
4768 }
4769
4770 /**
4771 * @brief Indicate whether the PRESENT automatic turn off clock is enabled.
4772 *
4773 * Register | BitsName
4774 * ----------|--------
4775 * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4776 *
4777 * @retval State of bit (1 or 0).
4778 */
4779 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
4780 {
4781 return 0;
4782 }
4783
4784 /**
4785 * @brief Enable RAMKEY automatic turn off clock during WFI/WFE
4786 *
4787 * Register | BitsName
4788 * ----------|--------
4789 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4790 *
4791 * @retval None
4792 */
4793 __STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
4794 {
4795 }
4796
4797 /**
4798 * @brief Disable RAMKEY automatic turn off clock during WFI/WFE
4799 *
4800 * Register | BitsName
4801 * ----------|--------
4802 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4803 *
4804 * @retval None
4805 */
4806 __STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
4807 {
4808 }
4809
4810 /**
4811 * @brief Indicate whether the RAMKEY automatic turn off clock is enabled.
4812 *
4813 * Register | BitsName
4814 * ----------|--------
4815 * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
4816 *
4817 * @retval State of bit (1 or 0).
4818 */
4819 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
4820 {
4821 return 0;
4822 }
4823
4824 /**
4825 * @brief Enable RNG automatic turn off clock during WFI/WFE
4826 *
4827 * Register | BitsName
4828 * ----------|--------
4829 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4830 *
4831 * @retval None
4832 */
4833 __STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
4834 {
4835 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4836 }
4837
4838 /**
4839 * @brief Disable RNG automatic turn off clock during WFI/WFE
4840 *
4841 * Register | BitsName
4842 * ----------|--------
4843 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4844 *
4845 * @retval None
4846 */
4847 __STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
4848 {
4849 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4850 }
4851
4852 /**
4853 * @brief Indicate whether the RNG automatic turn off clock is enabled.
4854 *
4855 * Register | BitsName
4856 * ----------|--------
4857 * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
4858 *
4859 * @retval State of bit (1 or 0).
4860 */
4861 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
4862 {
4863 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4864 }
4865
4866 /**
4867 * @brief Enable EFUSE automatic turn off clock during WFI/WFE
4868 *
4869 * Register | BitsName
4870 * ----------|--------
4871 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4872 *
4873 * @retval None
4874 */
4875 __STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
4876 {
4877 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
4878 }
4879
4880 /**
4881 * @brief Disable EFUSE automatic turn off clock during WFI/WFE
4882 *
4883 * Register | BitsName
4884 * ----------|--------
4885 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4886 *
4887 * @retval None
4888 */
4889 __STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
4890 {
4891 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
4892 }
4893
4894 /**
4895 * @brief Indicate whether the EFUSE automatic turn off clock is enabled.
4896 *
4897 * Register | BitsName
4898 * ----------|--------
4899 * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
4900 *
4901 * @retval State of bit (1 or 0).
4902 */
4903 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
4904 {
4905 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
4906 }
4907
4908 /**
4909 * @brief Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0)
4910 *
4911 * Register | BitsName
4912 * ----------|--------
4913 * MCU_MISC_CLK | GPADC/XQSPI/DMA0
4914 *
4915 * @retval None
4916 */
4917 __STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
4918 {
4919 MODIFY_REG(MCU_SUB->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK, clk_mask);
4920 }
4921
4922 /**
4923 * @brief Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0)
4924 *
4925 * Register | BitsName
4926 * ----------|--------
4927 * MCU_MISC_CLK | GPADC/XQSPI/DMA0
4928 */
4929 __STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
4930 {
4931 return READ_BITS(MCU_SUB->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK);
4932 }
4933
4934 /**
4935 * @brief Enabling force to turn off the clock for GPADC.
4936 *
4937 * Register | BitsName
4938 * ----------|--------
4939 * MCU_MISC_CLK | GPADC_HCLK_FRC_OFF
4940 *
4941 * @retval None
4942 */
4943 __STATIC_INLINE void ll_cgc_enable_force_off_gpadc_hclk(void)
4944 {
4945 }
4946
4947 /**
4948 * @brief Disabling force to turn off the clock for GPADC.
4949 *
4950 * Register | BitsName
4951 * ----------|--------
4952 * MCU_MISC_CLK | GPADC_HCLK_FRC_OFF
4953 *
4954 * @retval None
4955 */
4956 __STATIC_INLINE void ll_cgc_disable_force_off_gpadc_hclk(void)
4957 {
4958 }
4959
4960 /**
4961 * @brief Indicate whether the clock for GPADC is forced to close.
4962 *
4963 * Register | BitsName
4964 * ----------|--------
4965 * MCU_MISC_CLK | GPADC_HCLK_FRC_OFF
4966 *
4967 * @retval State of bit (1 or 0).
4968 */
4969 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpadc_hclk(void)
4970 {
4971 return 0;
4972 }
4973
4974 /**
4975 * @brief Enable GPADC automatic turn off clock during WFI/WFE
4976 *
4977 * Register | BitsName
4978 * ----------|--------
4979 * MCU_MISC_CLK |GPADC_HCLK_SLP_OFF
4980 *
4981 * @retval None
4982 */
4983 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpadc_hclk(void)
4984 {
4985 }
4986
4987 /**
4988 * @brief Disable GPADC automatic turn off clock during WFI/WFE
4989 *
4990 * Register | BitsName
4991 * ----------|--------
4992 * MCU_MISC_CLK | GPADC_HCLK_SLP_OFF
4993 *
4994 * @retval None
4995 */
4996 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpadc_hclk(void)
4997 {
4998 }
4999
5000 /**
5001 * @brief Indicate whether the GPADC automatic turn off clock is enabled.
5002 *
5003 * Register | BitsName
5004 * ----------|--------
5005 * MCU_MISC_CLK | GPADC_HCLK_SLP_OFF
5006 *
5007 * @retval State of bit (1 or 0).
5008 */
5009 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpadc_hclk(void)
5010 {
5011 return 0;
5012 }
5013
5014 /**
5015 * @brief Enable XQSPI SCK CLK turn off
5016 *
5017 * Register | BitsName
5018 * ----------|--------
5019 * MCU_MISC_CLK |XQSPI SCK CLK_OFF
5020 *
5021 * @retval None
5022 */
5023 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
5024 {
5025 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_ENABLE;
5026 }
5027
5028 /**
5029 * @brief Disable XQSPI SCK CLK turn off
5030 *
5031 * Register | BitsName
5032 * ----------|--------
5033 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5034 *
5035 * @retval None
5036 */
5037 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
5038 {
5039 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_DISABLE;
5040 }
5041
5042 /**
5043 * @brief Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
5044 *
5045 * Register | BitsName
5046 * ----------|--------
5047 * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5048 *
5049 * @retval State of bit (1 or 0).
5050 */
5051 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
5052 {
5053 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5054 }
5055
5056 /**
5057 * @brief Enable DMA0 turn off
5058 *
5059 * Register | BitsName
5060 * ----------|--------
5061 * MCU_MISC_CLK |DMA0_OFF
5062 *
5063 * @retval None
5064 */
5065 __STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
5066 {
5067 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5068 }
5069
5070 /**
5071 * @brief Disable DMA0 turn off
5072 *
5073 * Register | BitsName
5074 * ----------|--------
5075 * MCU_MISC_CLK | DMA0_OFF
5076 *
5077 * @retval None
5078 */
5079 __STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
5080 {
5081 BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5082 }
5083
5084 /**
5085 * @brief Indicate whether the DMA0 automatic turn off clock is enabled.
5086 *
5087 * Register | BitsName
5088 * ----------|--------
5089 * MCU_MISC_CLK | DMA0_OFF
5090 *
5091 * @retval State of bit (1 or 0).
5092 */
5093 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
5094 {
5095 return (BIT_SEGMENT_VALUE((uint32_t)&MCU_SUB->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5096 }
5097
5098 /** @} */
5099
5100 #endif /* CGC */
5101
5102 #ifdef __cplusplus
5103 }
5104 #endif
5105
5106 #endif /* __GR533X_LL_CGC_H__ */
5107
5108 /** @} */
5109
5110 /** @} */
5111
5112 /** @} */
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr533x_ll_cgc.h:2325
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1184
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr533x_ll_cgc.h:352
ll_cgc_is_enabled_spi_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
Indicate whether turn SPI_S off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3962
LL_CGC_MCU_SECU_FRC_OFF_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_HCLK
Definition: gr533x_ll_cgc.h:177
ll_cgc_disable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
Disabling force to turn off the clock for PWM1.
Definition: gr533x_ll_cgc.h:2783
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:905
ll_cgc_disable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
Disabling force to turn off the clock for UART3.
Definition: gr533x_ll_cgc.h:1932
ll_cgc_is_enabled_i2c5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
Indicate whether turn I2C5 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3798
ll_cgc_is_enabled_ahb_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr533x_ll_cgc.h:3186
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr533x_ll_cgc.h:2380
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr533x_ll_cgc.h:2053
ll_cgc_disable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
Disable turn I2S_S off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3865
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr533x_ll_cgc.h:1629
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:835
ll_cgc_get_wfi_off_hclk_4
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr533x_ll_cgc.h:456
ll_cgc_disable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
Disable turn pwm1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4032
ll_cgc_get_mcu_periph_low_power
__STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr533x_ll_cgc.h:2894
ll_cgc_is_enabled_force_off_i2s_s_p_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr533x_ll_cgc.h:2554
ll_cgc_set_wfi_off_hclk_4
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr533x_ll_cgc.h:439
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:877
ll_cgc_is_enabled_force_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
Indicate whether the clock for PRESENT is forced to close.
Definition: gr533x_ll_cgc.h:4494
ll_cgc_enable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
Enabling force to turn off the clock for UART2.
Definition: gr533x_ll_cgc.h:1879
ll_cgc_disable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
Disable uart pclk low-power feature.
Definition: gr533x_ll_cgc.h:2964
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:933
ll_cgc_disable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
Disabling force to turn off the clock for UART2.
Definition: gr533x_ll_cgc.h:1892
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr533x_ll_cgc.h:2283
ll_cgc_enable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
Enable turn UART1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3366
ll_cgc_is_enabled_uart1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
Indicate whether turn UART1 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3394
ll_cgc_disable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
Disable turn I2C3 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3705
ll_cgc_disable_wfi_off_gpadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpadc_hclk(void)
Disable GPADC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4996
ll_cgc_disable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
Disable turn I2C4 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3745
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr533x_ll_cgc.h:2648
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr533x_ll_cgc.h:487
ll_cgc_enable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
Enabling force to turn off the clock for PRESENT.
Definition: gr533x_ll_cgc.h:4468
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1142
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr533x_ll_cgc.h:1711
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr533x_ll_cgc.h:1865
ll_cgc_disable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
Disabling force to turn off the clock for HMAC.
Definition: gr533x_ll_cgc.h:4401
ll_cgc_disable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
Disable turn I2C1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3624
ll_cgc_is_enabled_wfi_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:739
ll_cgc_disable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
Disable turn I2C5 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3785
ll_cgc_disable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
Disabling force to turn off the clock for VTTBL.
Definition: gr533x_ll_cgc.h:2824
ll_cgc_disable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
Disable turn UART1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3380
ll_cgc_enable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
Enabling force to turn off the clock for UART5.
Definition: gr533x_ll_cgc.h:1999
ll_cgc_enable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
Enable turn pwm1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4018
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr533x_ll_cgc.h:1559
ll_cgc_enable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
Enabling force to turn off the clock for I2C3.
Definition: gr533x_ll_cgc.h:2163
ll_cgc_enable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
Enable turn I2C0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3568
ll_cgc_disable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:726
ll_cgc_is_enabled_force_off_dspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
Indicate whether the clock for DSPI is forced to close.
Definition: gr533x_ll_cgc.h:2594
ll_cgc_enable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
Enabling force to turn off the clock for I2C2.
Definition: gr533x_ll_cgc.h:2123
ll_cgc_is_enabled_force_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
Indicate whether the clock for AES is forced to close.
Definition: gr533x_ll_cgc.h:4374
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1170
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:1240
ll_cgc_enable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
Enabling force to turn off the clock for I2C5.
Definition: gr533x_ll_cgc.h:2243
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr533x_ll_cgc.h:1377
ll_cgc_is_enabled_force_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
Indicate whether the clock for PKC is forced to close.
Definition: gr533x_ll_cgc.h:4454
ll_cgc_is_enabled_spi_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
Indicate whether turn SPI_M off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3920
ll_cgc_enable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
Enable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4875
ll_cgc_is_enabled_force_off_xqspi_sck
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:5051
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr533x_ll_cgc.h:699
ll_cgc_disable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
Disable turn pwm0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3990
ll_cgc_disable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
Disable turn DSPI off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4193
ll_cgc_is_enabled_i2c1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
Indicate whether turn I2C1 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3638
CGC_CLOCK_DISABLE
#define CGC_CLOCK_DISABLE
Definition: gr533x_ll_cgc.h:232
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr533x_ll_cgc.h:1335
ll_cgc_enable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
Enable spim sclk low-power feature.
Definition: gr533x_ll_cgc.h:3032
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr533x_ll_cgc.h:2109
ll_cgc_is_enabled_wfi_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
Indicate whether the EFUSE automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4903
ll_cgc_disable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
Disable turn UART4 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3501
ll_cgc_is_enabled_wfi_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
Indicate whether the RNG automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4861
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr533x_ll_cgc.h:382
ll_cgc_is_enabled_i2c2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
Indicate whether turn I2C2 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3678
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1015
ll_cgc_enable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
Enabling force to turn off the clock for QSPI2.
Definition: gr533x_ll_cgc.h:2447
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr533x_ll_cgc.h:2488
ll_cgc_get_force_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT...
Definition: gr533x_ll_cgc.h:4291
ll_cgc_is_enabled_uart_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
Indicate whether the uart sclk low-power is enabled.
Definition: gr533x_ll_cgc.h:2936
ll_cgc_enable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
Enable turn I2S_S off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3852
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1212
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr533x_ll_cgc.h:2367
ll_cgc_is_enabled_ahb2apb_async_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr533x_ll_cgc.h:3310
ll_cgc_enable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
Enable uart pclk low-power feature.
Definition: gr533x_ll_cgc.h:2950
ll_cgc_is_enabled_pwm1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
Indicate whether turn pwm1 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4046
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr533x_ll_cgc.h:556
ll_cgc_enable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
Enable XQSPI SCK CLK turn off.
Definition: gr533x_ll_cgc.h:5023
ll_cgc_is_enabled_ahb2apb_sync_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
Indicate whether the AHB2APB bus low-power is enabled.
Definition: gr533x_ll_cgc.h:3268
ll_cgc_is_enabled_force_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
Indicate whether the clock for RAMKEY is forced to close.
Definition: gr533x_ll_cgc.h:4534
ll_cgc_set_force_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
Individual block's clock control inside security system which was forced to turn off (Include: AES/HM...
Definition: gr533x_ll_cgc.h:4269
ll_cgc_enable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr533x_ll_cgc.h:2528
ll_cgc_enable_qspim_low_power
__STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
Enable QSPIM low-power feature.
Definition: gr533x_ll_cgc.h:3200
ll_cgc_disable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
Disable turn I2S_M off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3825
ll_cgc_is_enabled_i2s_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
Indicate whether the i2s low-power is enabled.
Definition: gr533x_ll_cgc.h:3018
ll_cgc_enable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
Enable turn QSPIM1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4100
ll_cgc_is_enabled_dspi_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
Indicate whether turn DSPI off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4206
ll_cgc_disable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
Disable turn SPI_M off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3906
LL_CGC_WFI_ALL_HCLK0
#define LL_CGC_WFI_ALL_HCLK0
Definition: gr533x_ll_cgc.h:85
LL_CGC_WFI_ALL_HCLK1
#define LL_CGC_WFI_ALL_HCLK1
Definition: gr533x_ll_cgc.h:96
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:1156
ll_cgc_enable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
Enable turn UART3 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3448
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1085
ll_cgc_enable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:713
ll_cgc_enable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
Enable turn I2C4 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3732
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr533x_ll_cgc.h:1573
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr533x_ll_cgc.h:1349
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr533x_ll_cgc.h:1517
ll_cgc_disable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
Disabling force to turn off the clock for RAMKEY.
Definition: gr533x_ll_cgc.h:4521
ll_cgc_get_slp_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMK...
Definition: gr533x_ll_cgc.h:4334
ll_cgc_is_enabled_qspim2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4166
ll_cgc_is_enabled_force_off_uart2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
Indicate whether the clock for UART2 is forced to close.
Definition: gr533x_ll_cgc.h:1905
ll_cgc_enable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
Enable HMAC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4673
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:987
ll_cgc_disable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
Disable PKC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4726
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr533x_ll_cgc.h:333
ll_cgc_is_enabled_pwm0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
Indicate whether turn pwm0 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4004
ll_cgc_is_enabled_force_off_i2c2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
Indicate whether the clock for I2C2 is forced to close.
Definition: gr533x_ll_cgc.h:2149
ll_cgc_disable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
Disabling force to turn off the clock for I2C3.
Definition: gr533x_ll_cgc.h:2176
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr533x_ll_cgc.h:1587
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:685
ll_cgc_enable_force_off_gpadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpadc_hclk(void)
Enabling force to turn off the clock for GPADC.
Definition: gr533x_ll_cgc.h:4943
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr533x_ll_cgc.h:2095
ll_cgc_disable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
Disabling force to turn off the clock for PRESENT.
Definition: gr533x_ll_cgc.h:4481
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr533x_ll_cgc.h:2297
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr533x_ll_cgc.h:1254
ll_cgc_get_force_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr533x_ll_cgc.h:657
ll_cgc_enable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
Enable turn UART4 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3488
ll_cgc_enable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
Enable turn I2C5 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3772
ll_cgc_is_enabled_wfi_off_gpadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpadc_hclk(void)
Indicate whether the GPADC automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:5009
ll_cgc_disable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
Disabling force to turn off the clock for PWM0.
Definition: gr533x_ll_cgc.h:2741
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr533x_ll_cgc.h:1837
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:671
ll_cgc_enable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
Enable turn SPI_S off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3934
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr533x_ll_cgc.h:1433
ll_cgc_is_enabled_force_off_i2c4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
Indicate whether the clock for I2C4 is forced to close.
Definition: gr533x_ll_cgc.h:2229
ll_cgc_is_enabled_spim_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
Indicate whether the spim sclk low-power is enabled.
Definition: gr533x_ll_cgc.h:3060
LL_CGC_FRC_ALL_HCLK0
#define LL_CGC_FRC_ALL_HCLK0
Definition: gr533x_ll_cgc.h:111
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr533x_ll_cgc.h:1363
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1057
ll_cgc_enable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
Enabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr533x_ll_cgc.h:2687
ll_cgc_is_enabled_force_off_pdm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
Indicate whether the clock for PDM is forced to close.
Definition: gr533x_ll_cgc.h:2634
ll_cgc_enable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
Enabling force to turn off the clock for PDM slave.
Definition: gr533x_ll_cgc.h:2608
ll_cgc_enable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
Enable spis sclk low-power feature.
Definition: gr533x_ll_cgc.h:3074
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK...
Definition: gr533x_ll_cgc.h:622
ll_cgc_disable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
Disable turn I2C0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3582
ll_cgc_disable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
Disable turn UART2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3421
ll_cgc_disable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
Disable AES automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4646
ll_cgc_disable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
Disabling force to turn off the clock for EFUSE.
Definition: gr533x_ll_cgc.h:4605
ll_cgc_enable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
Enabling force to turn off the clock for RNG.
Definition: gr533x_ll_cgc.h:4549
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr533x_ll_cgc.h:1697
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:767
LL_CGC_FRC_ALL_HCLK1
#define LL_CGC_FRC_ALL_HCLK1
Definition: gr533x_ll_cgc.h:120
ll_cgc_disable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr533x_ll_cgc.h:3296
ll_cgc_enable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
Enabling force to turn off the clock for UART4.
Definition: gr533x_ll_cgc.h:1959
ll_cgc_disable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
Disable turn QSPIM0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4073
ll_cgc_is_enabled_force_off_dma0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
Indicate whether the DMA0 automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:5093
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:947
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:1029
ll_cgc_disable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
Disable turn UART5 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3541
ll_cgc_set_wfi_off_hclk_3
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI....
Definition: gr533x_ll_cgc.h:402
ll_cgc_is_enabled_force_off_i2c5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
Indicate whether the clock for I2C5 is forced to close.
Definition: gr533x_ll_cgc.h:2269
ll_cgc_is_enabled_force_off_pwm1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
Indicate whether the clock for PWM1 is forced to close.
Definition: gr533x_ll_cgc.h:2797
ll_cgc_is_enabled_uart4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
Indicate whether turn UART4 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3514
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr533x_ll_cgc.h:1489
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:863
ll_cgc_enable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
Enabling force to turn off the clock for VTTBL.
Definition: gr533x_ll_cgc.h:2811
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr533x_ll_cgc.h:1753
ll_cgc_disable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
Disabling force to turn off the clock for QSPI2.
Definition: gr533x_ll_cgc.h:2460
ll_cgc_disable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
Disabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr533x_ll_cgc.h:2700
ll_cgc_enable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
Enable PKC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4713
LL_CGC_FRC_ALL_HCLK2
#define LL_CGC_FRC_ALL_HCLK2
Definition: gr533x_ll_cgc.h:135
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr533x_ll_cgc.h:1725
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1099
ll_cgc_disable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
Disable spis sclk low-power feature.
Definition: gr533x_ll_cgc.h:3088
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr533x_ll_cgc.h:1461
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr533x_ll_cgc.h:1545
ll_cgc_is_enabled_uart3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
Indicate whether turn UART3 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3474
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr533x_ll_cgc.h:368
ll_cgc_enable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
Enable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4753
CGC_CLOCK_ENABLE
#define CGC_CLOCK_ENABLE
Definition: gr533x_ll_cgc.h:231
ll_cgc_enable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr533x_ll_cgc.h:3282
ll_cgc_enable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
Enable turn PDM off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4220
LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
Definition: gr533x_ll_cgc.h:178
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr533x_ll_cgc.h:2353
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr533x_ll_cgc.h:1671
ll_cgc_is_enabled_force_off_gpadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpadc_hclk(void)
Indicate whether the clock for GPADC is forced to close.
Definition: gr533x_ll_cgc.h:4969
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr533x_ll_cgc.h:2039
ll_cgc_enable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
Enable turn I2C2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3652
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr533x_ll_cgc.h:2433
ll_cgc_enable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
Enable AES automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4633
ll_cgc_is_enabled_force_off_uart3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
Indicate whether the clock for UART3 is forced to close.
Definition: gr533x_ll_cgc.h:1945
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr533x_ll_cgc.h:2393
ll_cgc_is_enabled_uart5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
Indicate whether turn UART5 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3554
ll_cgc_is_enabled_uart2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
Indicate whether turn UART2 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3434
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr533x_ll_cgc.h:2311
ll_cgc_disable_force_off_gpadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpadc_hclk(void)
Disabling force to turn off the clock for GPADC.
Definition: gr533x_ll_cgc.h:4956
ll_cgc_disable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr533x_ll_cgc.h:3172
ll_cgc_disable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
Disabling force to turn off the clock for AES.
Definition: gr533x_ll_cgc.h:4361
ll_cgc_disable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
Disable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4766
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr533x_ll_cgc.h:2661
ll_cgc_is_enabled_uart0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
Indicate whether turn UART0 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3352
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr533x_ll_cgc.h:2674
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr533x_ll_cgc.h:1795
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr533x_ll_cgc.h:1475
ll_cgc_disable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
Disabling force to turn off the clock for I2C4.
Definition: gr533x_ll_cgc.h:2216
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:753
ll_cgc_is_enabled_force_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
Indicate whether the clock for EFUSE is forced to close.
Definition: gr533x_ll_cgc.h:4619
ll_cgc_disable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
Disable turn UART3 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3461
ll_cgc_enable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
Enable AHB2APB bus low-power feature.
Definition: gr533x_ll_cgc.h:3240
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr533x_ll_cgc.h:1643
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr533x_ll_cgc.h:1615
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:781
ll_cgc_is_enabled_force_off_i2c3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
Indicate whether the clock for I2C3 is forced to close.
Definition: gr533x_ll_cgc.h:2189
ll_cgc_disable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
Disable turn QSPIM2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4153
ll_cgc_is_enabled_wfi_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
Indicate whether the PKC automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4739
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr533x_ll_cgc.h:1684
ll_cgc_is_enabled_i2s_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
Indicate whether turn I2S_M off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3838
ll_cgc_is_enabled_force_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
Indicate whether the clock for HMAC is forced to close.
Definition: gr533x_ll_cgc.h:4414
ll_cgc_enable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr533x_ll_cgc.h:3158
ll_cgc_disable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
Disable DMA0 turn off.
Definition: gr533x_ll_cgc.h:5079
ll_cgc_disable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
Disabling force to turn off the clock for DSPI slave.
Definition: gr533x_ll_cgc.h:2581
ll_cgc_is_enabled_wfi_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
Indicate whether the HMAC automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4699
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr533x_ll_cgc.h:1809
ll_cgc_disable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:808
ll_cgc_disable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
Disable turn I2C2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3665
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:891
ll_cgc_enable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
Enabling force to turn off the clock for HMAC.
Definition: gr533x_ll_cgc.h:4388
ll_cgc_is_enabled_qspim_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
Indicate whether the QSPIM low-power is enabled.
Definition: gr533x_ll_cgc.h:3226
ll_cgc_is_enabled_qspim0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4086
ll_cgc_enable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
Enable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4793
ll_cgc_enable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
Enable turn UART2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3408
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:849
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1001
ll_cgc_is_enabled_force_off_uart4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
Indicate whether the clock for UART4 is forced to close.
Definition: gr533x_ll_cgc.h:1985
ll_cgc_is_enabled_i2s_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
Indicate whether turn I2S_S off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3878
ll_cgc_set_misc_clk
__STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0)
Definition: gr533x_ll_cgc.h:4917
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr533x_ll_cgc.h:1391
ll_cgc_enable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
Enabling force to turn off the clock for AES.
Definition: gr533x_ll_cgc.h:4348
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr533x_ll_cgc.h:1503
ll_cgc_disable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
Disable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4889
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/ ROM/SNSADC/GPIO/DMA/BLE_B...
Definition: gr533x_ll_cgc.h:519
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr533x_ll_cgc.h:1781
ll_cgc_disable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
Disable HMAC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4686
ll_cgc_enable_i2s_low_power
__STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
Enable i2s low-power feature.
Definition: gr533x_ll_cgc.h:2992
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:961
ll_cgc_enable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
Enabling force to turn off the clock for I2C4.
Definition: gr533x_ll_cgc.h:2203
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO...
Definition: gr533x_ll_cgc.h:280
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr533x_ll_cgc.h:313
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:1198
ll_cgc_disable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
Disable spim sclk low-power feature.
Definition: gr533x_ll_cgc.h:3046
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HC...
Definition: gr533x_ll_cgc.h:589
ll_cgc_is_enabled_wfi_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
Indicate whether the AES automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4659
ll_cgc_disable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
Disabling force to turn off the clock for UART4.
Definition: gr533x_ll_cgc.h:1972
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr533x_ll_cgc.h:1295
ll_cgc_is_enabled_i2c0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
Indicate whether turn I2C0 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3596
ll_cgc_disable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
Disable turn UART0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3338
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr533x_ll_cgc.h:1267
ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
Indicate whether the div4 clock for xf qspi blocks is forced to close.
Definition: gr533x_ll_cgc.h:2713
ll_cgc_disable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
Disable XQSPI SCK CLK turn off.
Definition: gr533x_ll_cgc.h:5037
BIT_SEGMENT_VALUE
#define BIT_SEGMENT_VALUE
Definition: gr533x_ll_cgc.h:234
ll_cgc_enable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
Enable turn DSPI off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4180
ll_cgc_is_enabled_force_off_pwm0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
Indicate whether the clock for PWM0 is forced to close.
Definition: gr533x_ll_cgc.h:2755
LL_CGC_MCU_MISC_CLK
#define LL_CGC_MCU_MISC_CLK
Definition: gr533x_ll_cgc.h:186
ll_cgc_is_enabled_qspim1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4126
ll_cgc_is_enabled_i2c4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
Indicate whether turn I2C4 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3758
ll_cgc_enable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
Enable turn pwm0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3976
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr533x_ll_cgc.h:1281
ll_cgc_enable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
Enable turn QSPIM0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4060
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr533x_ll_cgc.h:538
ll_cgc_is_enabled_i2c3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
Indicate whether turn I2C3 off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:3718
ll_cgc_disable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
Disabling force to turn off the clock for RNG.
Definition: gr533x_ll_cgc.h:4563
ll_cgc_disable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr533x_ll_cgc.h:2541
ll_cgc_enable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
Enable turn UART0 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3324
ll_cgc_is_enabled_wfi_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:821
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1226
ll_cgc_enable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
Enable turn I2C3 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3692
ll_cgc_disable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
Disable uart sclk low-power feature.
Definition: gr533x_ll_cgc.h:2922
ll_cgc_enable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
Enable DMA0 turn off.
Definition: gr533x_ll_cgc.h:5065
ll_cgc_enable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
Enable turn UART5 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3528
ll_cgc_enable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
Enable RNG automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4833
ll_cgc_disable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
Disable turn QSPIM1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4113
ll_cgc_enable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
Enable turn I2C1 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3610
ll_cgc_enable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
Enable i2c sclk low-power feature.
Definition: gr533x_ll_cgc.h:3116
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr533x_ll_cgc.h:1851
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr533x_ll_cgc.h:2514
ll_cgc_enable_wfi_off_gpadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpadc_hclk(void)
Enable GPADC automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4983
ll_cgc_enable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
Enable turn I2S_M off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3812
ll_cgc_disable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
Disable turn PDM off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4233
ll_cgc_is_enabled_uart_pclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
Indicate whether the uart pclk low-power is enabled.
Definition: gr533x_ll_cgc.h:2978
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr533x_ll_cgc.h:1767
ll_cgc_enable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
Enabling force to turn off the clock for RAMKEY.
Definition: gr533x_ll_cgc.h:4508
ll_cgc_disable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
Disabling force to turn off the clock for PDM slave.
Definition: gr533x_ll_cgc.h:2621
ll_cgc_set_slp_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/R...
Definition: gr533x_ll_cgc.h:4313
ll_cgc_enable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:795
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr533x_ll_cgc.h:2081
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr533x_ll_cgc.h:1419
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr533x_ll_cgc.h:1308
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:1071
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:919
ll_cgc_is_enabled_i2c_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
Indicate whether the i2c sclk low-power is enabled.
Definition: gr533x_ll_cgc.h:3144
ll_cgc_is_enabled_force_off_uart5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
Indicate whether the clock for UART5 is forced to close.
Definition: gr533x_ll_cgc.h:2025
ll_cgc_is_enabled_force_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
Indicate whether the clock for RNG is forced to close.
Definition: gr533x_ll_cgc.h:4577
ll_cgc_is_enabled_wfi_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
Indicate whether the RAMKEY automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4819
ll_cgc_set_force_off_hclk_3
__STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr533x_ll_cgc.h:640
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr533x_ll_cgc.h:1601
ll_cgc_disable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
Disabling force to turn off the clock for I2C5.
Definition: gr533x_ll_cgc.h:2256
ll_cgc_disable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
Disable AHB2APB bus low-power feature.
Definition: gr533x_ll_cgc.h:3254
ll_cgc_enable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
Enable turn QSPIM2 off during WFI/WFE.
Definition: gr533x_ll_cgc.h:4140
ll_cgc_disable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
Disabling force to turn off the clock for PKC.
Definition: gr533x_ll_cgc.h:4441
ll_cgc_disable_qspim_low_power
__STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
Disable QSPIM low-power feature.
Definition: gr533x_ll_cgc.h:3213
ll_cgc_disable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
Disabling force to turn off the clock for I2C2.
Definition: gr533x_ll_cgc.h:2136
ll_cgc_disable_i2s_low_power
__STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
Disable i2s low-power feature.
Definition: gr533x_ll_cgc.h:3005
ll_cgc_get_wfi_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI....
Definition: gr533x_ll_cgc.h:421
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr533x_ll_cgc.h:2420
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr533x_ll_cgc.h:1823
ll_cgc_enable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
Enabling force to turn off the clock for PKC.
Definition: gr533x_ll_cgc.h:4428
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr533x_ll_cgc.h:1114
ll_cgc_disable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
Disable i2c sclk low-power feature.
Definition: gr533x_ll_cgc.h:3130
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr533x_ll_cgc.h:2339
ll_cgc_enable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
Enable uart sclk low-power feature.
Definition: gr533x_ll_cgc.h:2908
ll_cgc_enable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
Enable turn SPI_M off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3892
ll_cgc_disable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
Disable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4806
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr533x_ll_cgc.h:2407
ll_cgc_disable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
Disable turn SPI_S off during WFI/WFE.
Definition: gr533x_ll_cgc.h:3948
ll_cgc_is_enabled_spis_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
Indicate whether the spis sclk low-power is enabled.
Definition: gr533x_ll_cgc.h:3102
ll_cgc_disable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
Disabling force to turn off the clock for UART5.
Definition: gr533x_ll_cgc.h:2012
ll_cgc_get_misc_clk
__STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0)
Definition: gr533x_ll_cgc.h:4929
ll_cgc_is_enabled_force_off_qspi2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
Indicate whether the clock for QSPI2 is forced to close.
Definition: gr533x_ll_cgc.h:2473
ll_cgc_set_mcu_periph_low_power
__STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr533x_ll_cgc.h:2866
ll_cgc_is_enabled_wfi_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
Indicate whether the PRESENT automatic turn off clock is enabled.
Definition: gr533x_ll_cgc.h:4779
ll_cgc_enable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
Enabling force to turn off the clock for EFUSE.
Definition: gr533x_ll_cgc.h:4591
ll_cgc_enable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
Enabling force to turn off the clock for UART3.
Definition: gr533x_ll_cgc.h:1919
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr533x_ll_cgc.h:1531
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr533x_ll_cgc.h:2067
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1043
ll_cgc_is_enabled_pdm_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
Indicate whether turn PDM off during WFI/WFE is enabled.
Definition: gr533x_ll_cgc.h:4246
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr533x_ll_cgc.h:1447
ll_cgc_enable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
Enabling force to turn off the clock for PWM1.
Definition: gr533x_ll_cgc.h:2769
LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
#define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
Definition: gr533x_ll_cgc.h:166
ll_cgc_enable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
Enabling force to turn off the clock for PWM0.
Definition: gr533x_ll_cgc.h:2727
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr533x_ll_cgc.h:1739
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr533x_ll_cgc.h:1321
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:1128
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr533x_ll_cgc.h:1657
ll_cgc_enable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
Enabling force to turn off the clock for DSPI slave.
Definition: gr533x_ll_cgc.h:2568
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr533x_ll_cgc.h:2501
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr533x_ll_cgc.h:1405
ll_cgc_is_enabled_force_off_vttbl_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
Indicate whether the clock for VTTBL is forced to close.
Definition: gr533x_ll_cgc.h:2837
ll_cgc_disable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
Disable RNG automatic turn off clock during WFI/WFE.
Definition: gr533x_ll_cgc.h:4847
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr533x_ll_cgc.h:974