gr533x_ll_advs.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_advs.h
5 * @author BLE RD
6 * @brief Header file containing functions prototypes of advs LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_ADVS ADVS
47 * @brief ADVS LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_advs_H_
53 #define __GR533X_LL_advs_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_hal.h"
61
62 /**
63 * @defgroup ADVS_LL_MACRO Defines
64 * @{
65 */
66 /** @defgroup LL_ADVS_VTBIAS_ENABLE Scaling vtbias enable state defines
67 * @{
68 */
69 #define LL_ADVS_VTBIAS_DIS (0U) /**< VTBIAS Disable(default) */
70 #define LL_ADVS_VTBIAS_EN (1U) /**< VTBIAS Enable */
71 /** @} */
72
73 /** @defgroup LL_ADVS_BLK_ENABLE Scaling blk enable state defines
74 * @{
75 */
76 #define LL_ADVS_BLK_DIS (0U) /**< BLK Disable(default) */
77 #define LL_ADVS_BLK_EN (1U) /**< BLK Enable */
78 /** @} */
79
80 /** @defgroup LL_ADVS_TYPE Scaling slop control type defines
81 * @{
82 */
83 #define LL_ADVS_SLOP_LOWER_TYPE (0U) /**< Lower Slop Type(default) */
84 #define LL_ADVS_SLOP_HIGHER_TYPE (1U) /**< Higher Slop Type */
85 /** @} */
86
87 /** @defgroup LL_ADVS_LIMIT_ENABLE Scaling limiter enable defines
88 * @{
89 */
90 #define LL_ADVS_LIMIT_DIS (0U) /**< Scaling Limit Disable(default) */
91 #define LL_ADVS_LIMIT_EN (1U) /**< Scaling Limit Enable */
92 /** @} */
93
94 /** @} */
95
96 /** @defgroup ADVS_LL_DRIVER_FUNCTIONS Functions
97 * @{
98 */
99 /**
100 * @brief The ADVS_DCDC vtbias enable set
101 *
102 * Register|BitsName
103 * --------|--------
104 * ADVS_DCDC | EN_VTBIAS
105 */
106 __STATIC_INLINE void ll_advs_dcdc_vtbias_enable_set(uint8_t enable)
107 {
108 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_VTBIAS, (enable << AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos));
109 }
110
111 /**
112 * @brief The ADVS_DCDC vtbias enable get
113 *
114 * Register|BitsName
115 * --------|--------
116 * ADVS_DCDC | EN_VTBIAS
117 */
118 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_enable_get(void)
119 {
120 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_VTBIAS)) >> AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos);
121 }
122
123 /**
124 * @brief The ADVS_DCDC blk enable set
125 *
126 * Register|BitsName
127 * --------|--------
128 * ADVS_DCDC | EN_BLK
129 */
130 __STATIC_INLINE void ll_advs_dcdc_blk_enable_set(uint8_t enable)
131 {
132 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_BLK, (enable << AON_PMU_ADVS_DCDC_EN_BLK_Pos));
133 }
134
135 /**
136 * @brief The ADVS_DCDC blk enable get
137 *
138 * Register|BitsName
139 * --------|--------
140 * ADVS_DCDC | EN_BLK
141 */
142 __STATIC_INLINE uint8_t ll_advs_dcdc_blk_enable_get(void)
143 {
144 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_BLK)) >> AON_PMU_ADVS_DCDC_EN_BLK_Pos);
145 }
146
147 /**
148 * @brief The ADVS_DCDC's Slop Control type set
149 *
150 * Register|BitsName
151 * --------|--------
152 * ADVS_DCDC | VTBIAS_SLOPE_CTRL
153 */
154 __STATIC_INLINE void ll_advs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
155 {
156 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos));
157 }
158
159 /**
160 * @brief The ADVS_DCDC's Slop Control type get
161 *
162 * Register|BitsName
163 * --------|--------
164 * ADVS_DCDC | VTBIAS_SLOPE_CTRL
165 */
166 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_slop_ctrl_get(void)
167 {
168 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos);
169 }
170
171 /**
172 * @brief The ADVS_DCDC's Lower Limit Control enable set
173 *
174 * Register|BitsName
175 * --------|--------
176 * ADVS_DCDC | EN_LIMITER
177 */
178 __STATIC_INLINE void ll_advs_dcdc_limiter_enable_set(uint8_t enable)
179 {
180 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_LIMITER, (enable << AON_PMU_ADVS_DCDC_EN_LIMITER_Pos));
181 }
182
183 /**
184 * @brief The ADVS_DCDC's Lower Limit Control enable get
185 *
186 * Register|BitsName
187 * --------|--------
188 * ADVS_DCDC | EN_LIMITER
189 */
190 __STATIC_INLINE uint8_t ll_advs_dcdc_limiter_enable_get(void)
191 {
192 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_LIMITER)) >> AON_PMU_ADVS_DCDC_EN_LIMITER_Pos);
193 }
194
195 /**
196 * @brief The ADVS_DCDC's default level value of the VT bias set
197 *
198 * Register|BitsName
199 * --------|--------
200 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
201 */
202 __STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
203 {
204 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL, (vt << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos));
205 }
206
207 /**
208 * @brief The ADVS_DCDC's default level value of the VT bias get
209 *
210 * Register|BitsName
211 * --------|--------
212 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
213 */
214 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_vt_get(void)
215 {
216 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos);
217 }
218
219 /**
220 * @brief The ADVS_DCDC's lower limit for the output voltage set
221 *
222 * Register|BitsName
223 * --------|--------
224 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
225 */
226 __STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
227 {
228 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos));
229 }
230
231 /**
232 * @brief The ADVS_DCDC's lower limit for the output voltage get
233 *
234 * Register|BitsName
235 * --------|--------
236 * ADVS_DCDC | VTBIAS_CTRL_VT_2_0
237 */
238 __STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_lower_limit_get(void)
239 {
240 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos);
241 }
242
243 /**
244 * @brief The ADVS_LPD vtbias enable set
245 *
246 * Register|BitsName
247 * --------|--------
248 * ADVS_LPD | EN_VTBIAS
249 */
250 __STATIC_INLINE void ll_advs_lpd_vtbias_enable_set(uint8_t enable)
251 {
252 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_EN, (enable << AON_PMU_ADVS_LPD_VTBIAS_EN_Pos));
253 }
254
255 /**
256 * @brief The ADVS_LPD vtbias enable get
257 *
258 * Register|BitsName
259 * --------|--------
260 * ADVS_LPD | EN_VTBIAS
261 */
262 __STATIC_INLINE uint8_t ll_advs_lpd_vtbias_enable_get(void)
263 {
264 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_EN)) >> AON_PMU_ADVS_LPD_VTBIAS_EN_Pos);
265 }
266
267 /**
268 * @brief The ADVS_LPD's default level value of the VT bias set
269 *
270 * Register|BitsName
271 * --------|--------
272 * ADVS_LPD | VTBIAS_CTRL_VT
273 */
274 __STATIC_INLINE void ll_advs_lpd_vtbias_ctrl_vt_set(uint8_t vt)
275 {
276 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL, (vt << AON_PMU_ADVS_LPD_VTBIAS_CTRL_Pos));
277 }
278
279 /**
280 * @brief The ADVS_LPD's default level value of the VT bias get
281 *
282 * Register|BitsName
283 * --------|--------
284 * ADVS_LPD | VTBIAS_CTRL_VT
285 */
286 __STATIC_INLINE uint8_t ll_advs_lpd_vtbias_ctrl_vt_get(void)
287 {
288 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL)) >> AON_PMU_ADVS_LPD_VTBIAS_CTRL_Pos);
289 }
290
291 /**
292 * @brief The ADVS_DIGCORE vtbias enable set
293 *
294 * Register|BitsName
295 * --------|--------
296 * ADVS_DIGCORE | EN_VTBIAS
297 */
298 __STATIC_INLINE void ll_advs_digcore_vtbias_enable_set(uint8_t enable)
299 {
300 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_VTBIAS, (enable << AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos));
301 }
302
303 /**
304 * @brief The ADVS_DIGCORE vtbias enable get
305 *
306 * Register|BitsName
307 * --------|--------
308 * ADVS_DIGCORE | EN_VTBIAS
309 */
310 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_enable_get(void)
311 {
312 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_VTBIAS)) >> AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos);
313 }
314
315 /**
316 * @brief The ADVS_DIGCORE blk enable set
317 *
318 * Register|BitsName
319 * --------|--------
320 * ADVS_DIGCORE | EN_BLK
321 */
322 __STATIC_INLINE void ll_advs_digcore_blk_enable_set(uint8_t enable)
323 {
324 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_BLK, (enable << AON_PMU_ADVS_DIGCORE_EN_BLK_Pos));
325 }
326
327 /**
328 * @brief The ADVS_DIGCORE blk enable get
329 *
330 * Register|BitsName
331 * --------|--------
332 * ADVS_DIGCORE | EN_BLK
333 */
334 __STATIC_INLINE uint8_t ll_advs_digcore_blk_enable_get(void)
335 {
336 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_BLK)) >> AON_PMU_ADVS_DIGCORE_EN_BLK_Pos);
337 }
338
339 /**
340 * @brief The ADVS_DIGCORE's Slop Control type set
341 *
342 * Register|BitsName
343 * --------|--------
344 * ADVS_DIGCORE | VTBIAS_SLOPE_CTRL
345 */
346 __STATIC_INLINE void ll_advs_digcore_vtbias_slop_ctrl_set(uint8_t type)
347 {
348 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos));
349 }
350
351 /**
352 * @brief The ADVS_DIGCORE's Slop Control type get
353 *
354 * Register|BitsName
355 * --------|--------
356 * ADVS_DIGCORE | VTBIAS_SLOPE_CTRL
357 */
358 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_slop_ctrl_get(void)
359 {
360 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos);
361 }
362
363 /**
364 * @brief The ADVS_DIGCORE's Lower Limit Control enable set
365 *
366 * Register|BitsName
367 * --------|--------
368 * ADVS_DIGCORE | EN_LIMITER
369 */
370 __STATIC_INLINE void ll_advs_digcore_limiter_enable_set(uint8_t enable)
371 {
372 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_LIMITER, (enable << AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos));
373 }
374
375 /**
376 * @brief The ADVS_DIGCORE's Lower Limit Control enable get
377 *
378 * Register|BitsName
379 * --------|--------
380 * ADVS_DIGCORE | EN_LIMITER
381 */
382 __STATIC_INLINE uint8_t ll_advs_digcore_limiter_enable_get(void)
383 {
384 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_LIMITER)) >> AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos);
385 }
386
387 /**
388 * @brief The ADVS_DIGCORE's default level value of the VT bias set
389 *
390 * Register|BitsName
391 * --------|--------
392 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
393 */
394 __STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
395 {
396 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos));
397 }
398
399 /**
400 * @brief The ADVS_DIGCORE's default level value of the VT bias get
401 *
402 * Register|BitsName
403 * --------|--------
404 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
405 */
406 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_vt_get(void)
407 {
408 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos);
409 }
410
411 /**
412 * @brief The ADVS_DIGCORE's lower limit for the output voltage set
413 *
414 * Register|BitsName
415 * --------|--------
416 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
417 */
418 __STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
419 {
420 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos));
421 }
422
423 /**
424 * @brief The ADVS_DIGCORE's lower limit for the output voltage get
425 *
426 * Register|BitsName
427 * --------|--------
428 * ADVS_DIGCORE | VTBIAS_CTRL_VT_2_0
429 */
430 __STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_lower_limit_get(void)
431 {
432 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos);
433 }
434
435 /** @} */
436
437 #endif
438 /** @} */
439
440 /** @} */
441
442 /** @} */
ll_advs_digcore_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_vt_set(uint8_t vt)
The ADVS_DIGCORE's default level value of the VT bias set.
Definition: gr533x_ll_advs.h:394
ll_advs_dcdc_limiter_enable_get
__STATIC_INLINE uint8_t ll_advs_dcdc_limiter_enable_get(void)
The ADVS_DCDC's Lower Limit Control enable get.
Definition: gr533x_ll_advs.h:190
ll_advs_dcdc_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_slop_ctrl_get(void)
The ADVS_DCDC's Slop Control type get.
Definition: gr533x_ll_advs.h:166
ll_advs_lpd_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_advs_lpd_vtbias_ctrl_vt_get(void)
The ADVS_LPD's default level value of the VT bias get.
Definition: gr533x_ll_advs.h:286
ll_advs_dcdc_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_lower_limit_get(void)
The ADVS_DCDC's lower limit for the output voltage get.
Definition: gr533x_ll_advs.h:238
ll_advs_digcore_blk_enable_set
__STATIC_INLINE void ll_advs_digcore_blk_enable_set(uint8_t enable)
The ADVS_DIGCORE blk enable set.
Definition: gr533x_ll_advs.h:322
ll_advs_dcdc_blk_enable_get
__STATIC_INLINE uint8_t ll_advs_dcdc_blk_enable_get(void)
The ADVS_DCDC blk enable get.
Definition: gr533x_ll_advs.h:142
ll_advs_dcdc_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_slop_ctrl_set(uint8_t type)
The ADVS_DCDC's Slop Control type set.
Definition: gr533x_ll_advs.h:154
ll_advs_digcore_blk_enable_get
__STATIC_INLINE uint8_t ll_advs_digcore_blk_enable_get(void)
The ADVS_DIGCORE blk enable get.
Definition: gr533x_ll_advs.h:334
ll_advs_dcdc_blk_enable_set
__STATIC_INLINE void ll_advs_dcdc_blk_enable_set(uint8_t enable)
The ADVS_DCDC blk enable set.
Definition: gr533x_ll_advs.h:130
ll_advs_digcore_vtbias_enable_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_enable_get(void)
The ADVS_DIGCORE vtbias enable get.
Definition: gr533x_ll_advs.h:310
ll_advs_dcdc_vtbias_enable_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_enable_get(void)
The ADVS_DCDC vtbias enable get.
Definition: gr533x_ll_advs.h:118
ll_advs_lpd_vtbias_enable_get
__STATIC_INLINE uint8_t ll_advs_lpd_vtbias_enable_get(void)
The ADVS_LPD vtbias enable get.
Definition: gr533x_ll_advs.h:262
ll_advs_digcore_limiter_enable_set
__STATIC_INLINE void ll_advs_digcore_limiter_enable_set(uint8_t enable)
The ADVS_DIGCORE's Lower Limit Control enable set.
Definition: gr533x_ll_advs.h:370
ll_advs_digcore_vtbias_enable_set
__STATIC_INLINE void ll_advs_digcore_vtbias_enable_set(uint8_t enable)
The ADVS_DIGCORE vtbias enable set.
Definition: gr533x_ll_advs.h:298
ll_advs_digcore_vtbias_slop_ctrl_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_slop_ctrl_get(void)
The ADVS_DIGCORE's Slop Control type get.
Definition: gr533x_ll_advs.h:358
ll_advs_dcdc_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_lower_limit_set(uint8_t limit)
The ADVS_DCDC's lower limit for the output voltage set.
Definition: gr533x_ll_advs.h:226
ll_advs_dcdc_limiter_enable_set
__STATIC_INLINE void ll_advs_dcdc_limiter_enable_set(uint8_t enable)
The ADVS_DCDC's Lower Limit Control enable set.
Definition: gr533x_ll_advs.h:178
ll_advs_digcore_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_vt_get(void)
The ADVS_DIGCORE's default level value of the VT bias get.
Definition: gr533x_ll_advs.h:406
gr533x_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_advs_dcdc_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_ctrl_vt_set(uint8_t vt)
The ADVS_DCDC's default level value of the VT bias set.
Definition: gr533x_ll_advs.h:202
ll_advs_digcore_limiter_enable_get
__STATIC_INLINE uint8_t ll_advs_digcore_limiter_enable_get(void)
The ADVS_DIGCORE's Lower Limit Control enable get.
Definition: gr533x_ll_advs.h:382
ll_advs_dcdc_vtbias_ctrl_vt_get
__STATIC_INLINE uint8_t ll_advs_dcdc_vtbias_ctrl_vt_get(void)
The ADVS_DCDC's default level value of the VT bias get.
Definition: gr533x_ll_advs.h:214
ll_advs_digcore_vtbias_ctrl_lower_limit_get
__STATIC_INLINE uint8_t ll_advs_digcore_vtbias_ctrl_lower_limit_get(void)
The ADVS_DIGCORE's lower limit for the output voltage get.
Definition: gr533x_ll_advs.h:430
ll_advs_lpd_vtbias_enable_set
__STATIC_INLINE void ll_advs_lpd_vtbias_enable_set(uint8_t enable)
The ADVS_LPD vtbias enable set.
Definition: gr533x_ll_advs.h:250
ll_advs_digcore_vtbias_slop_ctrl_set
__STATIC_INLINE void ll_advs_digcore_vtbias_slop_ctrl_set(uint8_t type)
The ADVS_DIGCORE's Slop Control type set.
Definition: gr533x_ll_advs.h:346
ll_advs_digcore_vtbias_ctrl_lower_limit_set
__STATIC_INLINE void ll_advs_digcore_vtbias_ctrl_lower_limit_set(uint8_t limit)
The ADVS_DIGCORE's lower limit for the output voltage set.
Definition: gr533x_ll_advs.h:418
ll_advs_dcdc_vtbias_enable_set
__STATIC_INLINE void ll_advs_dcdc_vtbias_enable_set(uint8_t enable)
The ADVS_DCDC vtbias enable set.
Definition: gr533x_ll_advs.h:106
ll_advs_lpd_vtbias_ctrl_vt_set
__STATIC_INLINE void ll_advs_lpd_vtbias_ctrl_vt_set(uint8_t vt)
The ADVS_LPD's default level value of the VT bias set.
Definition: gr533x_ll_advs.h:274