gr533x_ll_msio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_MSIO_H__
53 #define __GR533X_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined(AON_MSIO)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief MSIO pad Enumerations definition
75 */
76 typedef enum
77 {
78 MSIOA = 0x00, /**< MSIO_A_PAD */
79 } msio_pad_t;
80
81
82 /**
83 * @brief LL MSIO init Structure definition
84 */
85 typedef struct _ll_msio_init
86 {
87 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
88 This parameter can be any value of @ref MSIO_LL_EC_PIN */
89
90 uint32_t direction; /**< Specifies the direction for the selected pins.
91 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
92
93 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_direction(). */
94
95 uint32_t mode; /**< Specifies the operating mode for the selected pins.
96 This parameter can be a value of @ref MSIO_LL_EC_MODE.
97
98 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_mode(). */
99
100 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
101 This parameter can be a value of @ref MSIO_LL_EC_PULL.
102
103 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_pull().*/
104
105 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
106 This parameter can be a value of MSIO_LL_EC_MUX.
107
108 GPIO HW MSIO_InitStructuration can be modified afterwards using unitary function
109 @ref ll_msio_set_pin_mux(). */
110
111 uint32_t speed; /**< Specifies the IO speed for the selected pins.
112 This parameter can be a value of @ref MSIO_LL_EC_SPEED.
113 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_speed().*/
114
115 uint32_t strength; /**< Specifies the IO output drive strength for the selected pins.
116 This parameter can be a value of @ref MSIO_LL_EC_STRENGTH.
117 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_strength().*/
118
119 uint32_t input_type; /**< Specifies the IO input type for the selected pins.
120 This parameter can be a value of @ref MSIO_LL_EC_INPUT_TYPE.
121 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_input_type().*/
122 } ll_msio_init_t;
123
124 /** @} */
125
126 /** @} */
127
128 /**
129 * @defgroup MSIO_LL_MACRO Defines
130 * @{
131 */
132
133 /* Exported constants --------------------------------------------------------*/
134 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
135 * @{
136 */
137 /** @defgroup MSIO_LL_PRIVATE_MACRO MSIO private macro
138 * @{
139 */
140 #define LL_MSIO_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position MSIO_LL_EC_DIRECTION */
141 #define LL_MSIO_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position MSIO_LL_EC_DIRECTION */
142 #define LL_MSIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in MSIO_LL_EC_STRENGTH */
143 #define LL_MSIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in MSIO_LL_EC_STRENGTH */
144 #define LL_MSIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in MSIO_LL_EC_STRENGTH */
145 #define LL_MSIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in MSIO_LL_EC_STRENGTH */
146 /** @} */
147
148 /** @defgroup MSIO_LL_EC_PIN PIN MSIO pin
149 * @{
150 */
151 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
152 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
153 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
154 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
155 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
156 #define LL_MSIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
157 #define LL_MSIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
158 #define LL_MSIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
159 #define LL_MSIO_PIN_8 ((uint32_t)0x100U) /**< Select pin 8 */
160 #define LL_MSIO_PIN_9 ((uint32_t)0x200U) /**< Select pin 9 */
161 #define LL_MSIO_PIN_ALL ((uint32_t)0x3FFU) /**< Select all pins */
162
163 /** @} */
164
165 /** @defgroup MSIO_LL_EC_DIRECTION Direction
166 * @{
167 */
168 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
169 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
170 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
171 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
172 /** @} */
173
174 /** @defgroup MSIO_LL_EC_MODE Mode
175 * @{
176 */
177 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x1U) /**< Select analog mode */
178 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x0U) /**< Enable digital mode */
179 /** @} */
180
181 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
182 * @{
183 */
184 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
185 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
186 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
187 /** @} */
188
189 /** @defgroup MSIO_LL_EC_SPEED IO Speed
190 * @{
191 */
192 #define LL_MSIO_SPEED_MEDIUM ((uint32_t)0x1U) /*!< Select medium speed */
193 #define LL_MSIO_SPEED_HIGH ((uint32_t)0x0U) /*!< Select high speed */
194 /** @} */
195
196 /** @defgroup MSIO_LL_EC_STRENGTH IO Strength
197 * @{
198 */
199 #define LL_MSIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
200 #define LL_MSIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
201 #define LL_MSIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
202 #define LL_MSIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
203 /** @} */
204
205 /** @defgroup MSIO_LL_EC_INPUT_TYPE Input type
206 * @{
207 */
208 #define LL_MSIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
209 #define LL_MSIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
210 /** @} */
211 /** @} */
212
213 /* Exported macro ------------------------------------------------------------*/
214 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
215 * @{
216 */
217
218 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
219 * @{
220 */
221
222 /**
223 * @brief Write a value in MSIO register
224 * @param __instance__ MSIO instance
225 * @param __REG__ Register to be written
226 * @param __VALUE__ Value to be written in the register
227 * @retval None
228 */
229 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
230
231 /**
232 * @brief Read a value in MSIO register
233 * @param __instance__ MSIO instance
234 * @param __REG__ Register to be read
235 * @retval Register value
236 */
237 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
238
239 /** @} */
240
241 /** @} */
242
243 /* Private types -------------------------------------------------------------*/
244 /* Private variables ---------------------------------------------------------*/
245 /* Private constants ---------------------------------------------------------*/
246 /* Private macros ------------------------------------------------------------*/
247 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
248 * @{
249 */
250
251 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuration
252 * @{
253 */
254
255 /**
256 * @brief LL MSIO InitStrcut default configuration
257 */
258 #define LL_MSIO_DEFAULT_CONFIG \
259 { \
260 .pin = LL_MSIO_PIN_ALL, \
261 .direction = LL_MSIO_DIRECTION_INPUT, \
262 .mode = LL_MSIO_MODE_DIGITAL, \
263 .pull = LL_MSIO_PULL_DOWN, \
264 .mux = IO_MUX_GPIO, \
265 .speed = LL_MSIO_SPEED_MEDIUM, \
266 .strength = LL_MSIO_STRENGTH_MEDIUM, \
267 .input_type = LL_MSIO_INPUT_TYPE_CMOS, \
268 }
269 /** @} */
270
271 /** @} */
272
273 /** @} */
274
275 /* Exported functions --------------------------------------------------------*/
276 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
277 * @{
278 */
279
280 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
281 * @{
282 */
283
284 /**
285 * @brief Set several MSIO pins to input/output direction.
286 *
287 * Register|BitsName
288 * --------|--------
289 * MSIO_PAD_CFG_0 | OE
290 * MSIO_PAD_CFG_1 | IE
291 *
292 * @param MSIOx MSIO instance
293 * @param pin_mask This parameter can be a combination of the following values:
294 * @arg @ref LL_MSIO_PIN_0
295 * @arg @ref LL_MSIO_PIN_1
296 * @arg @ref LL_MSIO_PIN_2
297 * @arg @ref LL_MSIO_PIN_3
298 * @arg @ref LL_MSIO_PIN_4
299 * @arg @ref LL_MSIO_PIN_5
300 * @arg @ref LL_MSIO_PIN_6
301 * @arg @ref LL_MSIO_PIN_7
302 * @arg @ref LL_MSIO_PIN_8
303 * @arg @ref LL_MSIO_PIN_9
304 * @arg @ref LL_MSIO_PIN_ALL
305 * @param direction This parameter can be one of the following values:
306 * @arg @ref LL_MSIO_DIRECTION_NONE
307 * @arg @ref LL_MSIO_DIRECTION_INPUT
308 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
309 * @arg @ref LL_MSIO_DIRECTION_INOUT
310 * @retval None
311 */
312 __STATIC_INLINE void ll_msio_set_pin_direction(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t direction)
313 {
314 uint32_t ie_mask = (pin_mask << AON_MSIO_A_PAD_CFG1_IE_POS) & AON_MSIO_A_PAD_CFG1_IE;
315 uint32_t oe_mask = (pin_mask << AON_MSIO_A_PAD_CFG0_OE_POS) & AON_MSIO_A_PAD_CFG0_OE;
316 uint32_t ie = ((direction == LL_MSIO_DIRECTION_INPUT) || (direction == LL_MSIO_DIRECTION_INOUT)) ? ie_mask : 0x0000U;
317 uint32_t oe = ((direction == LL_MSIO_DIRECTION_OUTPUT) || (direction == LL_MSIO_DIRECTION_INOUT)) ? oe_mask : 0x0000U;
318 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask, ie);
319 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask, oe);
320
321 }
322
323 /**
324 * @brief Return gpio direction for a MSIO pin.
325 * @note I/O direction can be Input direction, General purpose output.
326 * @note Warning: only one pin can be passed as parameter.
327 *
328 * Register|BitsName
329 * --------|--------
330 * MSIO_PAD_CFG_0 | OE
331 * MSIO_PAD_CFG_1 | IE
332 *
333 * @param MSIOx MSIO instance.
334 * @param pin This parameter can be one of the following values:
335 * @arg @ref LL_MSIO_PIN_0
336 * @arg @ref LL_MSIO_PIN_1
337 * @arg @ref LL_MSIO_PIN_2
338 * @arg @ref LL_MSIO_PIN_3
339 * @arg @ref LL_MSIO_PIN_4
340 * @arg @ref LL_MSIO_PIN_5
341 * @arg @ref LL_MSIO_PIN_6
342 * @arg @ref LL_MSIO_PIN_7
343 * @arg @ref LL_MSIO_PIN_8
344 * @arg @ref LL_MSIO_PIN_9
345 * @retval Returned value can be one of the following values:
346 * @arg @ref LL_MSIO_DIRECTION_NONE
347 * @arg @ref LL_MSIO_DIRECTION_INPUT
348 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
349 * @arg @ref LL_MSIO_DIRECTION_INOUT
350 */
351 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(msio_pad_t MSIOx, uint32_t pin)
352 {
353 uint32_t ie_mask = (pin << AON_MSIO_A_PAD_CFG1_IE_POS) & AON_MSIO_A_PAD_CFG1_IE;
354 uint32_t oe_mask = (pin << AON_MSIO_A_PAD_CFG0_OE_POS) & AON_MSIO_A_PAD_CFG0_OE;
355 uint32_t ie = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ie_mask) >> (POSITION_VAL(pin));
356 uint32_t oe = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, oe_mask) >> (POSITION_VAL(pin));
357 return (((ie >> AON_MSIO_A_PAD_CFG1_IE_POS) << LL_MSIO_INPUT_POS)
358 | ((oe >> AON_MSIO_A_PAD_CFG0_OE_POS) << LL_MSIO_OUTPUT_POS));
359 }
360
361 /**
362 * @brief Set several MSIO pins to analog/digital mode.
363 *
364 * Register|BitsName
365 * --------|--------
366 * MSIO_PAD_CFG_3 | AE
367 *
368 * @param MSIOx MSIO instance.
369 * @param pin_mask This parameter can be a combination of the following values:
370 * @arg @ref LL_MSIO_PIN_0
371 * @arg @ref LL_MSIO_PIN_1
372 * @arg @ref LL_MSIO_PIN_2
373 * @arg @ref LL_MSIO_PIN_3
374 * @arg @ref LL_MSIO_PIN_4
375 * @arg @ref LL_MSIO_PIN_5
376 * @arg @ref LL_MSIO_PIN_6
377 * @arg @ref LL_MSIO_PIN_7
378 * @arg @ref LL_MSIO_PIN_8
379 * @arg @ref LL_MSIO_PIN_9
380 * @arg @ref LL_MSIO_PIN_ALL
381 * @param mode This parameter can be one of the following values:
382 * @arg @ref LL_MSIO_MODE_ANALOG
383 * @arg @ref LL_MSIO_MODE_DIGITAL
384 * @retval None
385 */
386 __STATIC_INLINE void ll_msio_set_pin_mode(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t mode)
387 {
388 uint32_t mask = (pin_mask << AON_MSIO_A_PAD_CFG3_AE_POS) & AON_MSIO_A_PAD_CFG3_AE;
389 if(mode == LL_MSIO_MODE_ANALOG)
390 {
391 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG3, mask);
392 }
393 else
394 {
395 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG3, mask);
396 }
397 }
398
399 /**
400 * @brief Return gpio mode for a MSIO pin.
401 * @note I/O mode can be analog or digital.
402 * @note Warning: only one pin can be passed as parameter.
403 *
404 * Register|BitsName
405 * --------|--------
406 * MSIO_PAD_CFG_3 | AE
407 *
408 * @param MSIOx MSIO instance.
409 * @param pin This parameter can be one of the following values:
410 * @arg @ref LL_MSIO_PIN_0
411 * @arg @ref LL_MSIO_PIN_1
412 * @arg @ref LL_MSIO_PIN_2
413 * @arg @ref LL_MSIO_PIN_3
414 * @arg @ref LL_MSIO_PIN_4
415 * @arg @ref LL_MSIO_PIN_5
416 * @arg @ref LL_MSIO_PIN_6
417 * @arg @ref LL_MSIO_PIN_7
418 * @arg @ref LL_MSIO_PIN_8
419 * @arg @ref LL_MSIO_PIN_9
420 * @retval Returned value can be one of the following values:
421 * @arg @ref LL_MSIO_MODE_ANALOG
422 * @arg @ref LL_MSIO_MODE_DIGITAL
423 */
424 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(msio_pad_t MSIOx, uint32_t pin)
425 {
426 uint32_t mask = (pin << AON_MSIO_A_PAD_CFG3_AE_POS) & AON_MSIO_A_PAD_CFG3_AE;
427 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG3, mask) == mask) ? LL_MSIO_MODE_ANALOG : LL_MSIO_MODE_DIGITAL);
428 }
429
430
431 /**
432 * @brief Set several MSIO pins input type.
433 *
434 * Register|BitsName
435 * --------|--------
436 * MSIO_A_PAD_CFG2 | IS
437 *
438 * @param MSIOx MSIO instance.
439 * @param pin_mask This parameter can be a combination of the following values:
440 * @arg @ref LL_MSIO_PIN_0
441 * @arg @ref LL_MSIO_PIN_1
442 * @arg @ref LL_MSIO_PIN_2
443 * @arg @ref LL_MSIO_PIN_3
444 * @arg @ref LL_MSIO_PIN_4
445 * @arg @ref LL_MSIO_PIN_5
446 * @arg @ref LL_MSIO_PIN_6
447 * @arg @ref LL_MSIO_PIN_7
448 * @arg @ref LL_MSIO_PIN_8
449 * @arg @ref LL_MSIO_PIN_9
450 * @arg @ref LL_MSIO_PIN_ALL
451 * @param type This parameter can be one of the following values:
452 * @arg @ref LL_MSIO_INPUT_TYPE_CMOS
453 * @arg @ref LL_MSIO_INPUT_TYPE_SCHMITT
454 * @retval None
455 */
456 __STATIC_INLINE void ll_msio_set_pin_input_type(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t type)
457 {
458 pin_mask = (pin_mask << AON_MSIO_A_PAD_CFG2_IS_POS) & AON_MSIO_A_PAD_CFG2_IS;
459 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask, (type == LL_MSIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
460 }
461
462 /**
463 * @brief Return input type for a MSIO pin.
464 * @note I/O mode can be analog or digital.
465 * @note Warning: only one pin can be passed as parameter.
466 *
467 * Register|BitsName
468 * --------|--------
469 * MSIO_A_PAD_CFG2 | IS
470 *
471 * @param MSIOx MSIO instance.
472 * @param pin This parameter can be one of the following values:
473 * @arg @ref LL_MSIO_PIN_0
474 * @arg @ref LL_MSIO_PIN_1
475 * @arg @ref LL_MSIO_PIN_2
476 * @arg @ref LL_MSIO_PIN_3
477 * @arg @ref LL_MSIO_PIN_4
478 * @arg @ref LL_MSIO_PIN_5
479 * @arg @ref LL_MSIO_PIN_6
480 * @arg @ref LL_MSIO_PIN_7
481 * @arg @ref LL_MSIO_PIN_8
482 * @arg @ref LL_MSIO_PIN_9
483 * @retval Returned value can be one of the following values:
484 * @arg @ref LL_MSIO_INPUT_TYPE_CMOS
485 * @arg @ref LL_MSIO_INPUT_TYPE_SCHMITT
486 */
487 __STATIC_INLINE uint32_t ll_msio_get_pin_input_type(msio_pad_t MSIOx, uint32_t pin)
488 {
489 pin = (pin << AON_MSIO_A_PAD_CFG2_IS_POS) & AON_MSIO_A_PAD_CFG2_IS;
490 return ((uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG2, pin) == pin) ?
491 LL_MSIO_INPUT_TYPE_SCHMITT : LL_MSIO_INPUT_TYPE_CMOS);
492 }
493
494 /**
495 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
496 *
497 * Register|BitsName
498 * --------|--------
499 * MSIO_PAD_CFG_1 | PE
500 * MSIO_PAD_CFG_1 | PS
501 *
502 * @param MSIOx MSIO instance.
503 * @param pin_mask This parameter can be a combination of the following values:
504 * @arg @ref LL_MSIO_PIN_0
505 * @arg @ref LL_MSIO_PIN_1
506 * @arg @ref LL_MSIO_PIN_2
507 * @arg @ref LL_MSIO_PIN_3
508 * @arg @ref LL_MSIO_PIN_4
509 * @arg @ref LL_MSIO_PIN_5
510 * @arg @ref LL_MSIO_PIN_6
511 * @arg @ref LL_MSIO_PIN_7
512 * @arg @ref LL_MSIO_PIN_8
513 * @arg @ref LL_MSIO_PIN_9
514 * @arg @ref LL_MSIO_PIN_ALL
515 * @param pull This parameter can be one of the following values:
516 * @arg @ref LL_MSIO_PULL_NO
517 * @arg @ref LL_MSIO_PULL_UP
518 * @arg @ref LL_MSIO_PULL_DOWN
519 * @retval None
520 */
521 __STATIC_INLINE void ll_msio_set_pin_pull(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t pull)
522 {
523 uint32_t ps_mask = (pin_mask << AON_MSIO_A_PAD_CFG1_PS_POS) & AON_MSIO_A_PAD_CFG1_PS;
524 uint32_t pe_mask = (pin_mask << AON_MSIO_A_PAD_CFG1_PE_POS) & AON_MSIO_A_PAD_CFG1_PE;
525 uint32_t ps = (pull == LL_MSIO_PULL_UP) ? ps_mask : 0x0000U;
526 uint32_t pe = (pull == LL_MSIO_PULL_NO) ? 0x0000U : pe_mask;
527 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG1, pe_mask | ps_mask, pe | ps);
528 }
529
530 /**
531 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
532 * @note Warning: only one pin can be passed as parameter.
533 *
534 * Register|BitsName
535 * --------|--------
536 * MSIO_PAD_CFG_1 | PE
537 * MSIO_PAD_CFG_1 | PS
538 *
539 * @param MSIOx MSIO instance.
540 * @param pin This parameter can be one of the following values:
541 * @arg @ref LL_MSIO_PIN_0
542 * @arg @ref LL_MSIO_PIN_1
543 * @arg @ref LL_MSIO_PIN_2
544 * @arg @ref LL_MSIO_PIN_3
545 * @arg @ref LL_MSIO_PIN_4
546 * @arg @ref LL_MSIO_PIN_5
547 * @arg @ref LL_MSIO_PIN_6
548 * @arg @ref LL_MSIO_PIN_7
549 * @arg @ref LL_MSIO_PIN_8
550 * @arg @ref LL_MSIO_PIN_9
551 * @retval Returned value can be one of the following values:
552 * @arg @ref LL_MSIO_PULL_NO
553 * @arg @ref LL_MSIO_PULL_UP
554 * @arg @ref LL_MSIO_PULL_DOWN
555 */
556 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(msio_pad_t MSIOx, uint32_t pin)
557 {
558 uint32_t ps_mask = (pin << AON_MSIO_A_PAD_CFG1_PS_POS) & AON_MSIO_A_PAD_CFG1_PS;
559 uint32_t pe_mask = (pin << AON_MSIO_A_PAD_CFG1_PE_POS) & AON_MSIO_A_PAD_CFG1_PE;
560 return ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, pe_mask) == RESET) ? LL_MSIO_PULL_NO :
561 ((READ_BITS(AON_MSIO->MSIO_A_PAD_CFG1, ps_mask) == RESET) ? LL_MSIO_PULL_DOWN : LL_MSIO_PULL_UP));
562 }
563
564 /**
565 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 9 for a dedicated port.
566 * @note Possible values are from AF0 to AF7 depending on target.
567 * @note Warning: only one pin can be passed as parameter.
568 *
569 * Register|BitsName
570 * --------|--------
571 * MSIO_PAD_MUX | MSIO_PAD_MUX
572 * MSIO_PAD_CFG_1 | MCU_OVR
573 *
574 * @param MSIOx MSIO instance.
575 * @param pin This parameter can be one of the following values:
576 * @arg @ref LL_MSIO_PIN_0
577 * @arg @ref LL_MSIO_PIN_1
578 * @arg @ref LL_MSIO_PIN_2
579 * @arg @ref LL_MSIO_PIN_3
580 * @arg @ref LL_MSIO_PIN_4
581 * @arg @ref LL_MSIO_PIN_5
582 * @arg @ref LL_MSIO_PIN_6
583 * @arg @ref LL_MSIO_PIN_7
584 * @arg @ref LL_MSIO_PIN_8
585 * @arg @ref LL_MSIO_PIN_9
586 * @param mux This parameter can be one of the following values:
587 * IO_MUX_GPIO define
588 * @retval None
589 */
590 __STATIC_INLINE void ll_msio_set_pin_mux(msio_pad_t MSIOx, uint32_t pin, uint32_t mux)
591 {
592 if(IO_MUX_GPIO == mux)
593 {
594 CLEAR_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS);
595 }
596 else
597 {
598 SET_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS);
599 }
600
601 uint8_t id;
602 uint32_t pos;
603
604 pin = POSITION_VAL(pin);
605
606 id = pin >> 2;
607 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
608
609 MODIFY_REG(MCU_PAD->MSIO_PAD_MUX[id], IO_MUX_BIT_MASK << pos, mux << pos);
610 }
611
612 /**
613 * @brief Return gpio alternate function of a dedicated pin from 0 to 9 for a dedicated port.
614 *
615 * Register|BitsName
616 * --------|--------
617 * MSIO_PAD_MUX | MSIO_PAD_MUX
618 * MSIO_PAD_CFG_1 | MCU_OVR
619 *
620 * @param MSIOx MSIO instance.
621 * @param pin This parameter can be one of the following values:
622 * @arg @ref LL_MSIO_PIN_0
623 * @arg @ref LL_MSIO_PIN_1
624 * @arg @ref LL_MSIO_PIN_2
625 * @arg @ref LL_MSIO_PIN_3
626 * @arg @ref LL_MSIO_PIN_4
627 * @arg @ref LL_MSIO_PIN_5
628 * @arg @ref LL_MSIO_PIN_6
629 * @arg @ref LL_MSIO_PIN_7
630 * @arg @ref LL_MSIO_PIN_8
631 * @arg @ref LL_MSIO_PIN_9
632 * @retval Returned value can be one of the following values:
633 * IO_MUX_GPIO define
634 */
635 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(msio_pad_t MSIOx, uint32_t pin)
636 {
637 if (READ_BITS(AON_MSIO->MSIO_MCU_OVR, pin << AON_MSIO_MCU_OVR_MSIO_OVR_POS))
638 {
639 uint8_t id;
640 uint32_t pos;
641
642 pin = POSITION_VAL(pin);
643
644 id = pin >> 2;
645 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
646
647 return (READ_BITS(MCU_PAD->MSIO_PAD_MUX[id], IO_MUX_BIT_MASK << pos) >> pos);
648 }
649 else
650 {
651 return IO_MUX_GPIO;
652 }
653 }
654
655 /**
656 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 9 for a dedicated port.
657 * @note Possible values are from AF0 to AF7 depending on target.
658 * @note Warning: only one pin can be passed as parameter.
659 *
660 * Register|BitsName
661 * --------|--------
662 * MSIO_A_PAD_CFG2 | SR
663 *
664 * @param MSIOx MSIO instance.
665 * @param pin_mask This parameter can be one of the following values:
666 * @arg @ref LL_MSIO_PIN_0
667 * @arg @ref LL_MSIO_PIN_1
668 * @arg @ref LL_MSIO_PIN_2
669 * @arg @ref LL_MSIO_PIN_3
670 * @arg @ref LL_MSIO_PIN_4
671 * @arg @ref LL_MSIO_PIN_5
672 * @arg @ref LL_MSIO_PIN_6
673 * @arg @ref LL_MSIO_PIN_7
674 * @arg @ref LL_MSIO_PIN_8
675 * @arg @ref LL_MSIO_PIN_9
676 * @param speed This parameter can be one of the following values:
677 * @arg @ref LL_MSIO_SPEED_MEDIUM
678 * @arg @ref LL_MSIO_SPEED_HIGH
679 * @retval None
680 */
681 __STATIC_INLINE void ll_msio_set_pin_speed(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t speed)
682 {
683 if(speed)
684 {
685 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_CFG2_SR_POS, pin_mask << AON_MSIO_A_PAD_CFG2_SR_POS);
686 }
687 else
688 {
689 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG2, pin_mask << AON_MSIO_A_PAD_CFG2_SR_POS, 0);
690 }
691 }
692
693 /**
694 * @brief Return gpio alternate function of a dedicated pin from 0 to 9 for a dedicated port.
695 *
696 * Register|BitsName
697 * --------|--------
698 * MSIO_A_PAD_CFG2 | SR
699 *
700 * @param MSIOx MSIO instance.
701 * @param pin This parameter can be one of the following values:
702 * @arg @ref LL_MSIO_PIN_0
703 * @arg @ref LL_MSIO_PIN_1
704 * @arg @ref LL_MSIO_PIN_2
705 * @arg @ref LL_MSIO_PIN_3
706 * @arg @ref LL_MSIO_PIN_4
707 * @arg @ref LL_MSIO_PIN_5
708 * @arg @ref LL_MSIO_PIN_6
709 * @arg @ref LL_MSIO_PIN_7
710 * @arg @ref LL_MSIO_PIN_8
711 * @arg @ref LL_MSIO_PIN_9
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_MSIO_SPEED_MEDIUM
714 * @arg @ref LL_MSIO_SPEED_HIGH
715 */
716 __STATIC_INLINE uint32_t ll_msio_get_pin_speed(msio_pad_t MSIOx, uint32_t pin)
717 {
718 uint32_t pos;
719 pos = POSITION_VAL(pin);
720 return (READ_BITS(AON_MSIO->MSIO_A_PAD_CFG2, pin << AON_MSIO_A_PAD_CFG2_SR_POS) >> AON_MSIO_A_PAD_CFG2_SR_POS >> pos);
721 }
722
723 /**
724 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 9 for a dedicated port.
725 * @note Possible values are from AF0 to AF7 depending on target.
726 * @note Warning: only one pin can be passed as parameter.
727 *
728 * Register|BitsName
729 * --------|--------
730 * MSIO_A_PAD_CFG3 | DS0
731 * MSIO_A_PAD_CFG3 | DS1
732 *
733 * @param MSIOx MSIO instance.
734 * @param pin_mask This parameter can be one of the following values:
735 * @arg @ref LL_MSIO_PIN_0
736 * @arg @ref LL_MSIO_PIN_1
737 * @arg @ref LL_MSIO_PIN_2
738 * @arg @ref LL_MSIO_PIN_3
739 * @arg @ref LL_MSIO_PIN_4
740 * @arg @ref LL_MSIO_PIN_5
741 * @arg @ref LL_MSIO_PIN_6
742 * @arg @ref LL_MSIO_PIN_7
743 * @arg @ref LL_MSIO_PIN_8
744 * @arg @ref LL_MSIO_PIN_9
745 * @param strength This parameter can be one of the following values:
746 * @arg @ref LL_MSIO_STRENGTH_LOW
747 * @arg @ref LL_MSIO_STRENGTH_MEDIUM
748 * @arg @ref LL_MSIO_STRENGTH_HIGH
749 * @arg @ref LL_MSIO_STRENGTH_ULTRA
750 *
751 * @retval None
752 */
753 __STATIC_INLINE void ll_msio_set_pin_strength(msio_pad_t MSIOx, uint32_t pin_mask, uint32_t strength)
754 {
755 uint8_t ds0 = (strength & LL_MSIO_STRENGTH_DS0_MASK) >> LL_MSIO_STRENGTH_DS0_POS;
756 uint8_t ds1 = (strength & LL_MSIO_STRENGTH_DS1_MASK) >> LL_MSIO_STRENGTH_DS1_POS;
757 if(ds0)
758 {
759 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS0_POS , pin_mask << AON_MSIO_A_PAD_CFG3_DS0_POS);
760 }
761 else
762 {
763 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS0_POS , 0);
764 }
765 if(ds1)
766 {
767 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS1_POS , pin_mask << AON_MSIO_A_PAD_CFG3_DS1_POS);
768 }
769 else
770 {
771 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS1_POS , 0);
772 }
773 }
774
775 /**
776 * @brief Return gpio alternate function of a dedicated pin from 0 to 9 for a dedicated port.
777 *
778 * Register|BitsName
779 * --------|--------
780 * MSIO_A_PAD_CFG3 | DS0
781 * MSIO_A_PAD_CFG3 | DS1
782 *
783 * @param MSIOx MSIO instance.
784 * @param pin_mask This parameter can be one of the following values:
785 * @arg @ref LL_MSIO_PIN_0
786 * @arg @ref LL_MSIO_PIN_1
787 * @arg @ref LL_MSIO_PIN_2
788 * @arg @ref LL_MSIO_PIN_3
789 * @arg @ref LL_MSIO_PIN_4
790 * @arg @ref LL_MSIO_PIN_5
791 * @arg @ref LL_MSIO_PIN_6
792 * @arg @ref LL_MSIO_PIN_7
793 * @arg @ref LL_MSIO_PIN_8
794 * @arg @ref LL_MSIO_PIN_9
795 * @retval Returned value can be one of the following values:
796 * @arg @ref LL_MSIO_STRENGTH_LOW
797 * @arg @ref LL_MSIO_STRENGTH_MEDIUM
798 * @arg @ref LL_MSIO_STRENGTH_HIGH
799 * @arg @ref LL_MSIO_STRENGTH_ULTRA
800 */
801 __STATIC_INLINE uint32_t ll_msio_get_pin_strength(msio_pad_t MSIOx, uint32_t pin_mask)
802 {
803 uint32_t pos;
804 pos = POSITION_VAL(pin_mask);
805 uint8_t ds0 = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS0_POS ) >> AON_MSIO_A_PAD_CFG3_DS0_POS >> pos;
806 uint8_t ds1 = READ_BITS(AON_MSIO->MSIO_A_PAD_CFG3, pin_mask << AON_MSIO_A_PAD_CFG3_DS1_POS ) >> AON_MSIO_A_PAD_CFG3_DS1_POS >> pos;
807 return ((ds0 << LL_MSIO_STRENGTH_DS0_POS) | (ds1 << LL_MSIO_STRENGTH_DS1_POS));
808 }
809 /** @} */
810
811 /** @defgroup MSIO_LL_EF_Data_Access Data Access
812 * @{
813 */
814
815 /**
816 * @brief Return full input data register value of MSIO.
817 *
818 * Register|BitsName
819 * --------|--------
820 * MSIO_A_PAD_CFG0 | AON_MSIO_A_PAD_CFG0_IN
821 *
822 * @param MSIOx MSIO instance.
823 * @retval Input data register value of port
824 */
825 __STATIC_INLINE uint32_t ll_msio_read_input_port(msio_pad_t MSIOx)
826 {
827 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_CFG0_IN_VAL) >> AON_MSIO_A_PAD_CFG0_IN_VAL_POS);
828 }
829
830 /**
831 * @brief Return if input data level of several MSIO pins is high or low.
832 *
833 * Register|BitsName
834 * --------|--------
835 * MSIO_A_PAD_CFG0 | IN_VAL
836 *
837 * @param MSIOx MSIO instance.
838 * @param pin_mask This parameter can be a combination of the following values:
839 * @arg @ref LL_MSIO_PIN_0
840 * @arg @ref LL_MSIO_PIN_1
841 * @arg @ref LL_MSIO_PIN_2
842 * @arg @ref LL_MSIO_PIN_3
843 * @arg @ref LL_MSIO_PIN_4
844 * @arg @ref LL_MSIO_PIN_5
845 * @arg @ref LL_MSIO_PIN_6
846 * @arg @ref LL_MSIO_PIN_7
847 * @arg @ref LL_MSIO_PIN_8
848 * @arg @ref LL_MSIO_PIN_9
849 * @arg @ref LL_MSIO_PIN_ALL
850 * @retval State of bit (1 or 0).
851 */
852 __STATIC_INLINE uint32_t ll_msio_read_input_pin(msio_pad_t MSIOx, uint32_t pin_mask)
853 {
854 pin_mask = (pin_mask << AON_MSIO_A_PAD_CFG0_IN_VAL_POS) & AON_MSIO_A_PAD_CFG0_IN_VAL;
855 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
856 }
857
858 /**
859 * @brief Return if input data level of several MSIO pins is high or low.
860 *
861 * Register|BitsName
862 * --------|--------
863 * MSIO_PAD_CFG_0 | OUT_VAL
864 *
865 * @param MSIOx MSIO instance.
866 * @param pin_mask This parameter can be a combination of the following values:
867 * @arg @ref LL_MSIO_PIN_0
868 * @arg @ref LL_MSIO_PIN_1
869 * @arg @ref LL_MSIO_PIN_2
870 * @arg @ref LL_MSIO_PIN_3
871 * @arg @ref LL_MSIO_PIN_4
872 * @arg @ref LL_MSIO_PIN_5
873 * @arg @ref LL_MSIO_PIN_6
874 * @arg @ref LL_MSIO_PIN_7
875 * @arg @ref LL_MSIO_PIN_8
876 * @arg @ref LL_MSIO_PIN_9
877 * @arg @ref LL_MSIO_PIN_ALL
878 * @retval State of bit (1 or 0).
879 */
880 __STATIC_INLINE uint32_t ll_msio_read_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
881 {
882 pin_mask = (pin_mask << AON_MSIO_A_PAD_CFG0_OUT_VAL_POS) & AON_MSIO_A_PAD_CFG0_OUT_VAL;
883 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, pin_mask) == pin_mask);
884 }
885
886 /**
887 * @brief Write output data register of MSIO.
888 *
889 * Register|BitsName
890 * --------|--------
891 * MSIO_PAD_CFG_0 | OUT_VAL
892 *
893 * @param MSIOx MSIO instance.
894 * @param port_value Level value for each pin of the port
895 * @retval None
896 */
897 __STATIC_INLINE void ll_msio_write_output_port(msio_pad_t MSIOx, uint32_t port_value)
898 {
899 MODIFY_REG(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_CFG0_OUT_VAL, (port_value << AON_MSIO_A_PAD_CFG0_OUT_VAL_POS) & AON_MSIO_A_PAD_CFG0_OUT_VAL);
900 }
901 /**
902 * @brief Return full output data register value of MSIO.
903 *
904 * Register|BitsName
905 * --------|--------
906 * MSIO_PAD_CFG_0 | IN
907 *
908 * @param MSIOx MSIO instance.
909 * @retval Output data register value of port
910 */
911 __STATIC_INLINE uint32_t ll_msio_read_output_port(msio_pad_t MSIOx)
912 {
913 return (uint32_t)(READ_BITS(AON_MSIO->MSIO_A_PAD_CFG0, AON_MSIO_A_PAD_CFG0_OUT_VAL) >> AON_MSIO_A_PAD_CFG0_OUT_VAL_POS);
914 }
915
916 /**
917 * @brief Set specified MSIO pins to high level
918 *
919 * Register|BitsName
920 * --------|--------
921 * MSIO_PAD_CFG_0 | OUT_VAL
922 *
923 * @param MSIOx MSIO instance.
924 * @param pin_mask This parameter can be a combination of the following values:
925 * @arg @ref LL_MSIO_PIN_0
926 * @arg @ref LL_MSIO_PIN_1
927 * @arg @ref LL_MSIO_PIN_2
928 * @arg @ref LL_MSIO_PIN_3
929 * @arg @ref LL_MSIO_PIN_4
930 * @arg @ref LL_MSIO_PIN_5
931 * @arg @ref LL_MSIO_PIN_6
932 * @arg @ref LL_MSIO_PIN_7
933 * @arg @ref LL_MSIO_PIN_8
934 * @arg @ref LL_MSIO_PIN_9
935 * @arg @ref LL_MSIO_PIN_ALL
936 * @retval None
937 */
938 __STATIC_INLINE void ll_msio_set_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
939 {
940 SET_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_A_PAD_CFG0_OUT_VAL_POS) & AON_MSIO_A_PAD_CFG0_OUT_VAL);
941 }
942
943 /**
944 * @brief Set specified MSIO pins to low level.
945 *
946 * Register|BitsName
947 * --------|--------
948 * MSIO_PAD_CFG_0 | OUT_VAL
949 *
950 * @param MSIOx MSIO instance.
951 * @param pin_mask This parameter can be a combination of the following values:
952 * @arg @ref LL_MSIO_PIN_0
953 * @arg @ref LL_MSIO_PIN_1
954 * @arg @ref LL_MSIO_PIN_2
955 * @arg @ref LL_MSIO_PIN_3
956 * @arg @ref LL_MSIO_PIN_4
957 * @arg @ref LL_MSIO_PIN_5
958 * @arg @ref LL_MSIO_PIN_6
959 * @arg @ref LL_MSIO_PIN_7
960 * @arg @ref LL_MSIO_PIN_8
961 * @arg @ref LL_MSIO_PIN_9
962 * @arg @ref LL_MSIO_PIN_ALL
963 * @retval None
964 */
965 __STATIC_INLINE void ll_msio_reset_output_pin(msio_pad_t MSIOx, uint32_t pin_mask)
966 {
967 CLEAR_BITS(AON_MSIO->MSIO_A_PAD_CFG0, (pin_mask << AON_MSIO_A_PAD_CFG0_OUT_VAL_POS) & AON_MSIO_A_PAD_CFG0_OUT_VAL);
968 }
969
970 /**
971 * @brief Toggle data value of specified MSIO pins.
972 *
973 * Register|BitsName
974 * --------|--------
975 * MSIO_PAD_CFG_0 | OUT_VAL
976 *
977 * @param MSIOx MSIO instance.
978 * @param pin_mask This parameter can be a combination of the following values:
979 * @arg @ref LL_MSIO_PIN_0
980 * @arg @ref LL_MSIO_PIN_1
981 * @arg @ref LL_MSIO_PIN_2
982 * @arg @ref LL_MSIO_PIN_3
983 * @arg @ref LL_MSIO_PIN_4
984 * @arg @ref LL_MSIO_PIN_5
985 * @arg @ref LL_MSIO_PIN_6
986 * @arg @ref LL_MSIO_PIN_7
987 * @arg @ref LL_MSIO_PIN_8
988 * @arg @ref LL_MSIO_PIN_9
989 * @arg @ref LL_MSIO_PIN_ALL
990 * @retval None
991 */
992 __STATIC_INLINE void ll_msio_toggle_pin(msio_pad_t MSIOx, uint32_t pin_mask)
993 {
994 WRITE_REG(AON_MSIO->MSIO_A_PAD_CFG0, (READ_REG(AON_MSIO->MSIO_A_PAD_CFG0) ^ ((pin_mask << AON_MSIO_A_PAD_CFG0_OUT_VAL_POS) & AON_MSIO_A_PAD_CFG0_OUT_VAL)));
995 }
996
997 /** @} */
998
999
1000 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
1001 * @{
1002 */
1003 /**
1004 * @brief Initialize MSIO registers according to the specified.
1005 * parameters in p_msio_init.
1006 *
1007 * @param MSIOx MSIO instance.
1008 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
1009 * information for the specified MSIO peripheral.
1010 * @retval An error_status_t enumeration value:
1011 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
1012 * - ERROR: Problem occurred during MSIO Registers initialization
1013 */
1014 error_status_t ll_msio_init(msio_pad_t MSIOx,ll_msio_init_t *p_msio_init);
1015
1016 /** @} */
1017
1018 /** @} */
1019
1020 #endif /* AON_MSIO */
1021
1022 #ifdef __cplusplus
1023 }
1024 #endif
1025
1026 #endif /* __GR533X_LL_MSIO_H__ */
1027
1028 /** @} */
1029
1030 /** @} */
1031
1032 /** @} */