gr533x_hal_cgc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_hal_cgc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CGC HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_CGC CGC
47 * @brief CGC HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_HAL_CGC_H__
53 #define __GR533x_HAL_CGC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_ll_cgc.h"
61 #include "gr533x_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
64 /** @addtogroup HAL_CGC_ENUMERATIONS Enumerations
65 * @{
66 */
67
68 /**
69 * @brief CGC Bit Open and Bit Close Enumerations
70 */
71 typedef enum
72 {
73 CGC_CLK_ON = 0U, /**< Turn on the clock.*/
74 CGC_CLK_OFF = 1U, /**< Turn off the clock.*/
75 } cgc_clk_state_t;
76
77 /** @} */
78
79 /** @addtogroup HAL_CGC_STRUCTURES Structures
80 * @{
81 */
82
83 /**
84 * @brief CGC init structure definition
85 */
86 typedef struct _cgc_init
87 {
88 uint32_t wfi_clk; /**< Specifies the blocks that automatically closes the clock.
89 This parameter can be a combination of @ref CGC_LL_EC_WFI_CLK0 */
90
91 uint32_t force_clk; /**< Specifies the blocks to forcibly turn off the clock.
92 This parameter can be a combination of @ref CGC_LL_EC_FRC_CLK0 */
93 } cgc_init_t;
94
95 /** @} */
96
97
98 /**
99 * @defgroup HAL_CGC_MACRO Defines
100 * @{
101 */
102
103 /* Exported constants --------------------------------------------------------*/
104 /** @defgroup CGC_Exported_Constants CGC Exported Constants
105 * @{
106 */
107
108 /** @defgroup CGC_auto_clk Automatic Turn off clocks
109 * @{
110 */
111 #define CGC_WFI_SECU_HCLK ((uint32_t)0x00000001U) /**< Hclk for all security blocks */
112 #define CGC_WFI_SIM_HCLK ((uint32_t)0x00000002U) /**< Hclk for sim card interface */
113 #define CGC_WFI_HTB_HCLK ((uint32_t)0x00000004U) /**< Hclk for hopping table */
114 #define CGC_WFI_PWM_HCLK ((uint32_t)0x00000008U) /**< Hclk for PWM */
115 #define CGC_WFI_ROM_HCLK ((uint32_t)0x00000010U) /**< Hclk for ROM */
116 #define CGC_WFI_SNSADC_HCLK ((uint32_t)0x00000020U) /**< Hclk for sense ADC */
117 #define CGC_WFI_GPIO_HCLK ((uint32_t)0x00000040U) /**< Hclk for GPIOs */
118 #define CGC_WFI_DMA_HCLK ((uint32_t)0x00000080U) /**< Hclk for DMA engine */
119 #define CGC_WFI_BLE_BRG_HCLK ((uint32_t)0x00000100U) /**< Hclk for BLE MCU bridge */
120 #define CGC_WFI_APB_SUB_HCLK ((uint32_t)0x00000200U) /**< Hclk for APB subsystem */
121 #define CGC_WFI_SERIAL_HCLK ((uint32_t)0x00000400U) /**< Hclk for serial blocks */
122 #define CGC_WFI_I2S_S_HCLK ((uint32_t)0x00000800U) /**< Hclk for I2S slave */
123 #define CGC_WFI_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) /**< Hclk for Always-on register */
124 #define CGC_WFI_XF_XQSPI_HCLK ((uint32_t)0x00002000U) /**< Hclk for cache top */
125 #define CGC_WFI_SRAM_HCLK ((uint32_t)0x00004000U) /**< Hclk for SRAMs */
126 #define CGC_WFI_SECU_DIV4_PCLK ((uint32_t)0x00008000U) /**< Div4 clk for security blocks */
127 #define CGC_WFI_XQSPI_DIV4_PCLK ((uint32_t)0x00020000U) /**< Div4 clk for xf qspi */
128
129 #define CGC_WFI_ALL_CLK ((uint32_t)0x0002FFFFU) /**< All clocks */
130 /** @} */
131
132 /** @defgroup CGC_force_clk Force cloks off
133 * @{
134 */
135 #define CGC_FRC_SECU_HCLK ((uint32_t)0x00000001U) /**< Hclk for all security blocks */
136 #define CGC_FRC_SIM_HCLK ((uint32_t)0x00000002U) /**< Hclk for sim card interface */
137 #define CGC_FRC_HTB_HCLK ((uint32_t)0x00000004U) /**< Hclk for hopping table */
138 #define CGC_FRC_PWM_HCLK ((uint32_t)0x00000008U) /**< Hclk for PWM */
139 #define CGC_FRC_ROM_HCLK ((uint32_t)0x00000010U) /**< Hclk for ROM */
140 #define CGC_FRC_SNSADC_HCLK ((uint32_t)0x00000020U) /**< Hclk for sense ADC */
141 #define CGC_FRC_GPIO_HCLK ((uint32_t)0x00000040U) /**< Hclk for GPIOs */
142 #define CGC_FRC_DMA_HCLK ((uint32_t)0x00000080U) /**< Hclk for DMA engine */
143 #define CGC_FRC_BLE_BRG_HCLK ((uint32_t)0x00000100U) /**< Hclk for BLE MCU bridge */
144 #define CGC_FRC_APB_SUB_HCLK ((uint32_t)0x00000200U) /**< Hclk for APB subsystem */
145 #define CGC_FRC_SERIAL_HCLK ((uint32_t)0x00000400U) /**< Hclk for serial blocks */
146 #define CGC_FRC_I2S_S_HCLK ((uint32_t)0x00000800U) /**< Hclk for I2S slave */
147 #define CGC_FRC_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) /**< Hclk for Always-on register */
148 #define CGC_FRC_XF_XQSPI_HCLK ((uint32_t)0x00002000U) /**< Hclk for cache top */
149 #define CGC_FRC_SRAM_HCLK ((uint32_t)0x00004000U) /**< Hclk for SRAMs */
150 #define CGC_FRC_UART0_HCLK ((uint32_t)0x00008000U) /**< Hclk for uart0 */
151 #define CGC_FRC_UART1_HCLK ((uint32_t)0x00010000U) /**< Hclk for uart1 */
152 #define CGC_FRC_I2C0_HCLK ((uint32_t)0x00020000U) /**< Hclk for i2c0 */
153 #define CGC_FRC_I2C1_HCLK ((uint32_t)0x00040000U) /**< Hclk for i2c1 */
154 #define CGC_FRC_SPIM_HCLK ((uint32_t)0x00080000U) /**< Hclk for spim */
155 #define CGC_FRC_SPIS_HCLK ((uint32_t)0x00100000U) /**< Hclk for spis */
156 #define CGC_FRC_QSPI0_HCLK ((uint32_t)0x00200000U) /**< Hclk for qspi0 */
157 #define CGC_FRC_QSPI1_HCLK ((uint32_t)0x00400000U) /**< Hclk for qspi1 */
158 #define CGC_FRC_I2S_HCLK ((uint32_t)0x00800000U) /**< Hclk for i2s */
159 #define CGC_FRC_SECU_DIV4_PCLK ((uint32_t)0x01000000U) /**< Div4 clk for security blocks */
160 #define CGC_FRC_XQSPI_DIV4_PCLK ((uint32_t)0x04000000U) /**< Div4 clk for xf qspi */
161
162 #define CGC_FRC_ALL_CLK ((uint32_t)0x05FFFFFFU) /**< All clocks */
163 /** @} */
164
165
166
167 /**
168 * @brief CGC_default_config init Struct default configuartion
169 */
170 #define CGC_DEFAULT_CONFIG \
171 { \
172 .wfi_clk = ~CGC_WFI_ALL_CLK, \
173 .force_clk = ~CGC_FRC_ALL_CLK, \
174 }
175 /** @} */
176
177 /** @} */
178
179
180 /* Exported functions --------------------------------------------------------*/
181 /** @addtogroup HAL_CGC_DRIVER_FUNCTIONS Functions
182 * @{
183 */
184
185 /** @addtogroup CGC_Exported_Functions_Group1 Initialization and de-initialization functions
186 * @brief Initialization and Configuration functions
187 * @{
188 */
189
190 /**
191 ****************************************************************************************
192 * @brief Initialize the CGC registers according to the specified parameters in the @ref cgc_init_t.
193 * @param[in] p_cgc_init: Pointer to a @ref cgc_init_t structure that contains
194 * the configuration information for the specified CGC registers.
195 ****************************************************************************************
196 */
197 void hal_cgc_init(cgc_init_t *p_cgc_init);
198
199 /**
200 ****************************************************************************************
201 * @brief De-initialize the CGC registers to their default reset values.
202 ****************************************************************************************
203 */
204 void hal_cgc_deinit(void);
205
206 /** @} */
207
208 /** @addtogroup CGC_Exported_Functions_Group2 Peripheral Control functions.
209 * @brief Clock Gate Open and Closemanagement functions.
210 * @{
211 */
212
213 /**
214 ****************************************************************************************
215 * @brief Configure the clock state for a specified block during WFI.
216 * @param[in] blocks: Specifies the peripheral blocks.
217 * This parameter can be a combiantion of the following values:
218 * @arg @ref CGC_WFI_SECU_HCLK
219 * @arg @ref CGC_WFI_SIM_HCLK
220 * @arg @ref CGC_WFI_HTB_HCLK
221 * @arg @ref CGC_WFI_PWM_HCLK
222 * @arg @ref CGC_WFI_ROM_HCLK
223 * @arg @ref CGC_WFI_SNSADC_HCLK
224 * @arg @ref CGC_WFI_GPIO_HCLK
225 * @arg @ref CGC_WFI_DMA_HCLK
226 * @arg @ref CGC_WFI_BLE_BRG_HCLK
227 * @arg @ref CGC_WFI_APB_SUB_HCLK
228 * @arg @ref CGC_WFI_SERIAL_HCLK
229 * @arg @ref CGC_WFI_I2S_S_HCLK
230 * @arg @ref CGC_WFI_AON_MCUSUB_HCLK
231 * @arg @ref CGC_WFI_XF_XQSPI_HCLK
232 * @arg @ref CGC_WFI_SRAM_HCLK
233 * @arg @ref CGC_WFI_SECU_DIV4_PCLK
234 * @arg @ref CGC_WFI_XQSPI_DIV4_PCLK
235 * @param[in] clk_state: Specifies the clock state during WFI.
236 * This parameter can be one of the following values:
237 * @arg @ref CGC_CLK_ON
238 * @arg @ref CGC_CLK_OFF
239 ****************************************************************************************
240 */
241 void hal_cgc_config_wfi_clk(uint32_t blocks, cgc_clk_state_t clk_state);
242
243 /**
244 ****************************************************************************************
245 * @brief Get the clock state for a specified block during WFI.
246 * @param[in] block: Specifies the peripheral blocks.
247 * This parameter can be one of the following values:
248 * @arg @ref CGC_WFI_SECU_HCLK
249 * @arg @ref CGC_WFI_SIM_HCLK
250 * @arg @ref CGC_WFI_HTB_HCLK
251 * @arg @ref CGC_WFI_PWM_HCLK
252 * @arg @ref CGC_WFI_ROM_HCLK
253 * @arg @ref CGC_WFI_SNSADC_HCLK
254 * @arg @ref CGC_WFI_GPIO_HCLK
255 * @arg @ref CGC_WFI_DMA_HCLK
256 * @arg @ref CGC_WFI_BLE_BRG_HCLK
257 * @arg @ref CGC_WFI_APB_SUB_HCLK
258 * @arg @ref CGC_WFI_SERIAL_HCLK
259 * @arg @ref CGC_WFI_I2S_S_HCLK
260 * @arg @ref CGC_WFI_AON_MCUSUB_HCLK
261 * @arg @ref CGC_WFI_XF_XQSPI_HCLK
262 * @arg @ref CGC_WFI_SRAM_HCLK
263 * @arg @ref CGC_WFI_SECU_DIV4_PCLK
264 * @arg @ref CGC_WFI_XQSPI_DIV4_PCLK
265 * @retval ::CGC_CLK_ON: Clock On.
266 * @retval ::CGC_CLK_OFF: Clock Off.
267 ****************************************************************************************
268 */
269 cgc_clk_state_t hal_cgc_get_wfi_clk(uint32_t block);
270
271 /**
272 ****************************************************************************************
273 * @brief Forced to Configure the clock state for a specified block.
274 * @param[in] blocks: Specifies the peripheral blocks.
275 * This parameter can be a combiantion of the following values:
276 * @arg @ref CGC_FRC_SECU_HCLK
277 * @arg @ref CGC_FRC_SIM_HCLK
278 * @arg @ref CGC_FRC_HTB_HCLK
279 * @arg @ref CGC_FRC_PWM_HCLK
280 * @arg @ref CGC_FRC_ROM_HCLK
281 * @arg @ref CGC_FRC_SNSADC_HCLK
282 * @arg @ref CGC_FRC_GPIO_HCLK
283 * @arg @ref CGC_FRC_DMA_HCLK
284 * @arg @ref CGC_FRC_BLE_BRG_HCLK
285 * @arg @ref CGC_FRC_APB_SUB_HCLK
286 * @arg @ref CGC_FRC_SERIAL_HCLK
287 * @arg @ref CGC_FRC_I2S_S_HCLK
288 * @arg @ref CGC_FRC_AON_MCUSUB_HCLK
289 * @arg @ref CGC_FRC_XF_XQSPI_HCLK
290 * @arg @ref CGC_FRC_SRAM_HCLK
291 * @arg @ref CGC_FRC_UART0_HCLK
292 * @arg @ref CGC_FRC_UART1_HCLK
293 * @arg @ref CGC_FRC_I2C0_HCLK
294 * @arg @ref CGC_FRC_I2C1_HCLK
295 * @arg @ref CGC_FRC_SPIM_HCLK
296 * @arg @ref CGC_FRC_SPIS_HCLK
297 * @arg @ref CGC_FRC_QSPI0_HCLK
298 * @arg @ref CGC_FRC_QSPI1_HCLK
299 * @arg @ref CGC_FRC_I2S_HCLK
300 * @arg @ref CGC_FRC_SECU_DIV4_PCLK
301 * @arg @ref CGC_FRC_XQSPI_DIV4_PCLK
302 * @param[in] clk_state: Specifies the clock state.
303 * This parameter can be one of the following values:
304 * @arg @ref CGC_CLK_ON
305 * @arg @ref CGC_CLK_OFF
306 ****************************************************************************************
307 */
308 void hal_cgc_config_force_clk(uint32_t blocks, cgc_clk_state_t clk_state);
309
310 /**
311 ****************************************************************************************
312 * @brief Get the clock status of the currently specified block.
313 * @param[in] block: Specifies the peripheral blocks.
314 * This parameter can be one of the following values:
315 * @arg @ref CGC_FRC_SECU_HCLK
316 * @arg @ref CGC_FRC_SIM_HCLK
317 * @arg @ref CGC_FRC_HTB_HCLK
318 * @arg @ref CGC_FRC_PWM_HCLK
319 * @arg @ref CGC_FRC_ROM_HCLK
320 * @arg @ref CGC_FRC_SNSADC_HCLK
321 * @arg @ref CGC_FRC_GPIO_HCLK
322 * @arg @ref CGC_FRC_DMA_HCLK
323 * @arg @ref CGC_FRC_BLE_BRG_HCLK
324 * @arg @ref CGC_FRC_APB_SUB_HCLK
325 * @arg @ref CGC_FRC_SERIAL_HCLK
326 * @arg @ref CGC_FRC_I2S_S_HCLK
327 * @arg @ref CGC_FRC_AON_MCUSUB_HCLK
328 * @arg @ref CGC_FRC_XF_XQSPI_HCLK
329 * @arg @ref CGC_FRC_SRAM_HCLK
330 * @arg @ref CGC_FRC_UART0_HCLK
331 * @arg @ref CGC_FRC_UART1_HCLK
332 * @arg @ref CGC_FRC_I2C0_HCLK
333 * @arg @ref CGC_FRC_I2C1_HCLK
334 * @arg @ref CGC_FRC_SPIM_HCLK
335 * @arg @ref CGC_FRC_SPIS_HCLK
336 * @arg @ref CGC_FRC_QSPI0_HCLK
337 * @arg @ref CGC_FRC_QSPI1_HCLK
338 * @arg @ref CGC_FRC_I2S_HCLK
339 * @arg @ref CGC_FRC_SECU_DIV4_PCLK
340 * @arg @ref CGC_FRC_XQSPI_DIV4_PCLK
341 * @retval ::CGC_CLK_ON: Clock On.
342 * @retval ::CGC_CLK_OFF: Clock Off.
343 ****************************************************************************************
344 */
345 cgc_clk_state_t hal_cgc_get_force_clk(uint32_t block);
346
347
348 /** @} */
349
350 /** @} */
351
352 #ifdef __cplusplus
353 }
354 #endif
355
356 #endif /* __GR533x_HAL_CGC_H__ */
357
358 /** @} */
359
360 /** @} */
361
362 /** @} */
cgc_clk_state_t
cgc_clk_state_t
CGC Bit Open and Bit Close Enumerations.
Definition: gr533x_hal_cgc.h:72
CGC_CLK_ON
@ CGC_CLK_ON
Definition: gr533x_hal_cgc.h:73
_cgc_init::force_clk
uint32_t force_clk
Definition: gr533x_hal_cgc.h:91
hal_cgc_get_wfi_clk
cgc_clk_state_t hal_cgc_get_wfi_clk(uint32_t block)
Get the clock state for a specified block during WFI.
hal_cgc_get_force_clk
cgc_clk_state_t hal_cgc_get_force_clk(uint32_t block)
Get the clock status of the currently specified block.
gr533x_ll_cgc.h
Header file containing functions prototypes of CGC LL library.
cgc_init_t
struct _cgc_init cgc_init_t
CGC init structure definition.
CGC_CLK_OFF
@ CGC_CLK_OFF
Definition: gr533x_hal_cgc.h:74
_cgc_init::wfi_clk
uint32_t wfi_clk
Definition: gr533x_hal_cgc.h:88
hal_cgc_config_force_clk
void hal_cgc_config_force_clk(uint32_t blocks, cgc_clk_state_t clk_state)
Forced to Configure the clock state for a specified block.
_cgc_init
CGC init structure definition.
Definition: gr533x_hal_cgc.h:87
hal_cgc_config_wfi_clk
void hal_cgc_config_wfi_clk(uint32_t blocks, cgc_clk_state_t clk_state)
Configure the clock state for a specified block during WFI.
gr533x_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_cgc_init
void hal_cgc_init(cgc_init_t *p_cgc_init)
Initialize the CGC registers according to the specified parameters in the cgc_init_t.
hal_cgc_deinit
void hal_cgc_deinit(void)
De-initialize the CGC registers to their default reset values.