52 #ifndef __GR533X_LL_AON_GPIO_H__
53 #define __GR533X_LL_AON_GPIO_H__
76 typedef struct _ll_aon_gpio_init
114 } ll_aon_gpio_init_t;
132 #define LL_AON_GPIO_MODE_INPUT_POS ((uint32_t)0x0U)
133 #define LL_AON_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U)
134 #define LL_AON_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U)
135 #define LL_AON_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U)
136 #define LL_AON_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U)
137 #define LL_AON_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U)
143 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U)
144 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U)
145 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U)
146 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U)
147 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U)
148 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U)
149 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U)
150 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U)
151 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU)
157 #define LL_AON_GPIO_MODE_NONE ((uint32_t)0x0U)
158 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x1U)
159 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x2U)
160 #define LL_AON_GPIO_MODE_INOUT ((uint32_t)0x3U)
167 #define LL_AON_GPIO_PULL_NO ((uint32_t)0x0U)
168 #define LL_AON_GPIO_PULL_UP ((uint32_t)0x1U)
169 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x2U)
176 #define LL_AON_GPIO_SPEED_MEDIUM ((uint32_t)0x1U)
177 #define LL_AON_GPIO_SPEED_HIGH ((uint32_t)0x0U)
183 #define LL_AON_GPIO_STRENGTH_LOW ((uint32_t)0x00U)
184 #define LL_AON_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U)
185 #define LL_AON_GPIO_STRENGTH_HIGH ((uint32_t)0x10U)
186 #define LL_AON_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U)
192 #define LL_AON_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U)
193 #define LL_AON_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U)
199 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U)
200 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U)
201 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U)
202 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U)
203 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U)
204 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U)
210 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U)
211 #define LL_CLK_RNG_OSC_250K ((uint32_t)0x01U)
212 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U)
213 #define LL_CLK_RTC_CLK ((uint32_t)0x03U)
234 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
242 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262 #define LL_AON_GPIO_DEFAULT_CONFIG \
264 .pin = LL_AON_GPIO_PIN_ALL, \
265 .mode = LL_AON_GPIO_MODE_INPUT, \
266 .pull = LL_AON_GPIO_PULL_DOWN, \
267 .mux = IO_MUX_GPIO, \
268 .speed = LL_AON_GPIO_SPEED_MEDIUM, \
269 .strength = LL_AON_GPIO_STRENGTH_MEDIUM, \
270 .input_type = LL_AON_GPIO_INPUT_TYPE_CMOS, \
271 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
312 __STATIC_INLINE
void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
314 uint32_t ie_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_IE_POS) & AON_IO_AON_PAD_CTRL0_IE;
315 uint32_t oe_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OE_POS) & AON_IO_AON_PAD_CTRL1_OE;
316 uint32_t ie = ((mode == LL_AON_GPIO_MODE_INPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
317 uint32_t oe = ((mode == LL_AON_GPIO_MODE_OUTPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
318 MODIFY_REG(AON_IO->AON_PAD_CTRL0, ie_mask, ie);
319 MODIFY_REG(AON_IO->AON_PAD_CTRL1, oe_mask, oe);
347 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
349 uint32_t ie_mask = (pin << AON_IO_AON_PAD_CTRL0_IE_POS) & AON_IO_AON_PAD_CTRL0_IE;
350 uint32_t oe_mask = (pin << AON_IO_AON_PAD_CTRL1_OE_POS) & AON_IO_AON_PAD_CTRL1_OE;
351 uint32_t ie = READ_BITS(AON_IO->AON_PAD_CTRL0, ie_mask) >> (POSITION_VAL(pin));
352 uint32_t oe = READ_BITS(AON_IO->AON_PAD_CTRL1, oe_mask) >> (POSITION_VAL(pin));
353 return (((ie >> AON_IO_AON_PAD_CTRL0_IE_POS) << LL_AON_GPIO_MODE_INPUT_POS)
354 | ((oe >> AON_IO_AON_PAD_CTRL1_OE_POS) << LL_AON_GPIO_MODE_OUTPUT_POS));
379 __STATIC_INLINE
void ll_aon_gpio_set_pin_input_type(uint32_t pin_mask, uint32_t type)
381 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL2_IS_POS) & AON_IO_AON_PAD_CTRL2_IS;
382 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask, (type == LL_AON_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
407 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_input_type(uint32_t pin)
409 pin = (pin << AON_IO_AON_PAD_CTRL2_IS_POS) & AON_IO_AON_PAD_CTRL2_IS;
410 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL2, pin) == pin) ?
411 LL_AON_GPIO_INPUT_TYPE_SCHMITT : LL_AON_GPIO_INPUT_TYPE_CMOS);
439 __STATIC_INLINE
void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
441 uint32_t ps_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_PS_POS) & AON_IO_AON_PAD_CTRL0_PS;
442 uint32_t pe_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_PE_POS) & AON_IO_AON_PAD_CTRL0_PE;
443 uint32_t ps = (pull == LL_AON_GPIO_PULL_UP) ? ps_mask : 0x0000U;
444 uint32_t pe = (pull == LL_AON_GPIO_PULL_NO) ? 0x0000U : pe_mask;
445 MODIFY_REG(AON_IO->AON_PAD_CTRL0, pe_mask | ps_mask, pe | ps);
471 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
473 uint32_t ps_mask = (pin << AON_IO_AON_PAD_CTRL0_PS_POS) & AON_IO_AON_PAD_CTRL0_PS;
474 uint32_t pe_mask = (pin << AON_IO_AON_PAD_CTRL0_PE_POS) & AON_IO_AON_PAD_CTRL0_PE;
475 return ((READ_BITS(AON_IO->AON_PAD_CTRL0, pe_mask) == RESET) ? LL_AON_GPIO_PULL_NO :
476 ((READ_BITS(AON_IO->AON_PAD_CTRL0, ps_mask) == RESET) ? LL_AON_GPIO_PULL_DOWN : LL_AON_GPIO_PULL_UP));
502 __STATIC_INLINE
void ll_aon_gpio_set_pin_mux(uint32_t pin, uint32_t mux)
507 if(IO_MUX_GPIO == mux)
509 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
513 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
516 pin = POSITION_VAL(pin);
519 pos = (pin & 3) << 3;
521 MODIFY_REG(MCU_PAD->AON_PAD_MUX[
id], IO_MUX_BIT_MASK << pos, mux << pos);
544 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mux(uint32_t pin)
546 if (READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
551 pin = POSITION_VAL(pin);
554 pos = (pin & 3) << 3;
556 return (READ_BITS(MCU_PAD->AON_PAD_MUX[
id], IO_MUX_BIT_MASK << pos) >> pos);
587 __STATIC_INLINE
void ll_aon_gpio_set_pin_speed(uint32_t pin_mask, uint32_t speed)
591 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS);
595 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS, 0);
620 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_speed(uint32_t pin)
623 pos = POSITION_VAL(pin);
624 return (READ_BITS(AON_IO->AON_PAD_CTRL2, pin << AON_IO_AON_PAD_CTRL2_SR_POS) >> AON_IO_AON_PAD_CTRL2_SR_POS >> pos);
653 __STATIC_INLINE
void ll_aon_gpio_set_pin_strength(uint32_t pin_mask, uint32_t strength)
655 uint8_t ds0 = (strength & LL_AON_GPIO_STRENGTH_DS0_MASK) >> LL_AON_GPIO_STRENGTH_DS0_POS;
656 uint8_t ds1 = (strength & LL_AON_GPIO_STRENGTH_DS1_MASK) >> LL_AON_GPIO_STRENGTH_DS1_POS;
659 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS , pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS);
663 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS , 0);
667 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS , pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS);
671 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS , 0);
699 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_strength(uint32_t pin_mask)
702 pos = POSITION_VAL(pin_mask);
703 uint8_t ds0 = READ_BITS(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS ) >> AON_IO_AON_PAD_CTRL3_DS0_POS >> pos;
704 uint8_t ds1 = READ_BITS(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS ) >> AON_IO_AON_PAD_CTRL3_DS1_POS >> pos;
705 return ((ds0 << LL_AON_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_AON_GPIO_STRENGTH_DS1_POS));
722 __STATIC_INLINE
void ll_aon_gpio4_enable_clk_output(uint32_t clk_sel)
724 MODIFY_REG(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
725 AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
737 __STATIC_INLINE
void ll_aon_gpio4_disable_clk_output(
void)
739 CLEAR_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
751 __STATIC_INLINE uint32_t ll_aon_gpio4_is_enabled_clk_output(
void)
753 return (READ_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
765 __STATIC_INLINE
void ll_aon_gpio_enable_xo_2mhz_output(
void)
767 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
779 __STATIC_INLINE
void ll_aon_gpio_disable_xo_2mhz_output(
void)
781 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
793 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(
void)
795 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
813 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(
void)
815 uint32_t pin_mask = (LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
816 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) >> AON_IO_AON_PAD_CTRL1_IN_VAL_POS);
838 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_pin(uint32_t pin_mask)
840 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
841 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
863 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_pin(uint32_t pin_mask)
865 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
866 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
879 __STATIC_INLINE
void ll_aon_gpio_write_output_port(uint32_t port_value)
881 MODIFY_REG(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL, (port_value << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
893 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(
void)
895 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL) >> AON_IO_AON_PAD_CTRL1_OUT_VAL_POS);
917 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
919 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
920 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
942 __STATIC_INLINE
void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
944 SET_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
966 __STATIC_INLINE
void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
968 CLEAR_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
990 __STATIC_INLINE
void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
992 WRITE_REG(AON_IO->AON_PAD_CTRL1, (READ_REG(AON_IO->AON_PAD_CTRL1)
993 ^ ((pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL)));
1022 __STATIC_INLINE
void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
1024 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1025 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1026 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1027 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1028 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1029 MODIFY_REG(AON_CTL->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
1052 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
1054 uint32_t invert = ((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1055 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1056 uint32_t edge_type = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1057 return (invert && edge_en && edge_type);
1080 __STATIC_INLINE
void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
1082 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1083 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1084 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1085 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1086 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1087 MODIFY_REG(AON_CTL->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
1111 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
1113 uint32_t invert = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1114 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1115 uint32_t edge_type = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1116 return (invert && edge_en && edge_type);
1139 __STATIC_INLINE
void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
1141 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1142 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1143 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1144 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en);
1167 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
1169 uint32_t invert = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1170 uint32_t edge_en = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1171 return (invert && edge_en );
1194 __STATIC_INLINE
void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
1196 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1197 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1198 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1199 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en);
1222 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
1224 uint32_t invert = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1225 uint32_t edge_en = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1226 return (invert && edge_en);
1249 __STATIC_INLINE
void ll_aon_gpio_enable_both_trigger(uint32_t pin_mask)
1251 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1252 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1253 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en | both);
1276 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_both_trigger(uint32_t pin_mask)
1278 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1279 uint32_t edge_both = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1280 return ( edge_en && edge_both);
1303 __STATIC_INLINE
void ll_aon_gpio_enable_it(uint32_t pin_mask)
1305 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL0, pin_mask);
1328 __STATIC_INLINE
void ll_aon_gpio_disable_it(uint32_t pin_mask)
1330 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, pin_mask);
1352 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1354 return ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1374 __STATIC_INLINE uint32_t ll_aon_gpio_get_enabled_pin(
void)
1376 return (READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1387 __STATIC_INLINE uint32_t ll_aon_gpio_is_enable_wakeup_it(
void)
1389 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_EXT) == (AON_CTL_MCU_WAKEUP_CTRL_EXT));
1419 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1421 return (READ_BITS(AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1445 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1447 return ((READ_BITS(AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1471 __STATIC_INLINE
void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1473 CLEAR_BITS(AON_CTL->EXT_WAKEUP_STAT, pin_mask);
1487 __STATIC_INLINE uint32_t ll_aon_gpio_read_event_flag_it(
void)
1489 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1501 __STATIC_INLINE
void ll_aon_gpio_clear_event_flag_it(
void)
1503 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);
1520 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);