52 #ifndef __GR533X_LL_advs_H_
53 #define __GR533X_LL_advs_H_
69 #define LL_ADVS_VTBIAS_DIS (0U)
70 #define LL_ADVS_VTBIAS_EN (1U)
76 #define LL_ADVS_BLK_DIS (0U)
77 #define LL_ADVS_BLK_EN (1U)
83 #define LL_ADVS_SLOP_LOWER_TYPE (0U)
84 #define LL_ADVS_SLOP_HIGHER_TYPE (1U)
90 #define LL_ADVS_LIMIT_DIS (0U)
91 #define LL_ADVS_LIMIT_EN (1U)
108 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_VTBIAS, (enable << AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos));
120 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_VTBIAS)) >> AON_PMU_ADVS_DCDC_EN_VTBIAS_Pos);
132 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_BLK, (enable << AON_PMU_ADVS_DCDC_EN_BLK_Pos));
144 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_BLK)) >> AON_PMU_ADVS_DCDC_EN_BLK_Pos);
156 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos));
168 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DCDC_VTBIAS_SLOPE_CTRL_Pos);
180 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_LIMITER, (enable << AON_PMU_ADVS_DCDC_EN_LIMITER_Pos));
192 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_EN_LIMITER)) >> AON_PMU_ADVS_DCDC_EN_LIMITER_Pos);
204 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL, (vt << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos));
216 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_VT_2_0_Pos);
228 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos));
240 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DCDC_VTBIAS_CTRL_LIMIT_2_0_Pos);
252 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_EN, (enable << AON_PMU_ADVS_LPD_VTBIAS_EN_Pos));
264 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_EN)) >> AON_PMU_ADVS_LPD_VTBIAS_EN_Pos);
276 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL, (vt << AON_PMU_ADVS_LPD_VTBIAS_CTRL_Pos));
288 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_0, AON_PMU_ADVS_LPD_VTBIAS_CTRL)) >> AON_PMU_ADVS_LPD_VTBIAS_CTRL_Pos);
300 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_VTBIAS, (enable << AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos));
312 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_VTBIAS)) >> AON_PMU_ADVS_DIGCORE_EN_VTBIAS_Pos);
324 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_BLK, (enable << AON_PMU_ADVS_DIGCORE_EN_BLK_Pos));
336 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_BLK)) >> AON_PMU_ADVS_DIGCORE_EN_BLK_Pos);
348 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL, (type << AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos));
360 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_SLOPE_CTRL_Pos);
372 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_LIMITER, (enable << AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos));
384 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_EN_LIMITER)) >> AON_PMU_ADVS_DIGCORE_EN_LIMITER_Pos);
396 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0, (vt << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos));
408 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_VT_2_0_Pos);
420 MODIFY_REG(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0, (limit << AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos));
432 return ((READ_BITS(AON_PMU->PMU_ADVS_CFG_1, AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0)) >> AON_PMU_ADVS_DIGCORE_VTBIAS_CTRL_LIMIT_2_0_Pos);