gr533x_ll_gpio.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_GPIO GPIO
47 * @brief GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_GPIO_H__
53 #define __GR533X_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined (GPIO0)
63
64 /** @defgroup GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup GPIO_LL_ES_INIT GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL GPIO init configuration definition
75 */
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin; /*!< Specifies the GPIO pins to be GPIO_InitStructured.
79 This parameter can be any value of @ref GPIO_LL_EC_PIN */
80
81 uint32_t mode; /*!< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref GPIO_LL_EC_MODE.
83
84 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_mode(). */
85
86 uint32_t pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref GPIO_LL_EC_PULL.
88
89 GPIO HW configuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of GPIO_LL_EC_MUX.
93
94 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_gpio_set_pin_mux(). */
96
97 uint32_t speed; /*!< Specifies the slew rate for the selected pins.
98 This parameter can be a value of @ref GPIO_LL_EC_SPEED.
99
100 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
101 @ref ll_gpio_set_pin_speed(). */
102
103 uint32_t strength; /*!< Specifies the output drive strength for the selected pins.
104 This parameter can be a value of @ref GPIO_LL_EC_STRENGTH.
105
106 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
107 @ref ll_gpio_set_pin_strength(). */
108
109 uint32_t input_type; /*!< Specifies the input type for the selected pins.
110 This parameter can be a value of @ref GPIO_LL_EC_INPUT_TYPE.
111
112 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
113 @ref ll_gpio_set_pin_input_type(). */
114
115 uint32_t trigger; /*!< Specifies the trigger signal active edge.
116 This parameter can be a value of @ref GPIO_LL_EC_TRIGGER. */
117
118 } ll_gpio_init_t;
119
120 /** @} */
121
122 /** @} */
123
124 /**
125 * @defgroup GPIO_LL_MACRO Defines
126 * @{
127 */
128
129 /* Exported constants --------------------------------------------------------*/
130 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
131 * @{
132 */
133 /** @defgroup GPIO_LL_PRIVATE_MACRO GPIO private macro
134 * @{
135 */
136 #define LL_GPIO_MODE_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position GPIO_LL_EC_MODE */
137 #define LL_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position GPIO_LL_EC_MODE */
138 #define LL_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in GPIO_LL_EC_STRENGTH */
139 #define LL_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in GPIO_LL_EC_STRENGTH */
140 #define LL_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in GPIO_LL_EC_STRENGTH */
141 #define LL_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in GPIO_LL_EC_STRENGTH */
142 /** @} */
143
144 /** @defgroup GPIO_LL_EC_PIN PIN
145 * @{
146 */
147 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U) /*!< Select pin 0 */
148 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U) /*!< Select pin 1 */
149 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U) /*!< Select pin 2 */
150 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U) /*!< Select pin 3 */
151 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U) /*!< Select pin 4 */
152 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U) /*!< Select pin 5 */
153 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U) /*!< Select pin 6 */
154 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U) /*!< Select pin 7 */
155 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U) /*!< Select pin 8 */
156 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U) /*!< Select pin 9 */
157 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U) /*!< Select pin 10 */
158 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U) /*!< Select pin 11 */
159 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U) /*!< Select pin 12 */
160 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U) /*!< Select pin 13 */
161 #define LL_GPIO_PIN_ALL ((uint32_t)0x3FFFU) /*!< Select all pins */
162 /** @} */
163
164 /** @defgroup GPIO_LL_EC_MODE Mode
165 * @{
166 */
167 #define LL_GPIO_MODE_NONE ((uint32_t)0x0U) /**< No input or output */
168 #define LL_GPIO_MODE_INPUT ((uint32_t)0x1U) /**< Select input mode */
169 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x2U) /**< Select output mode */
170 #define LL_GPIO_MODE_INOUT ((uint32_t)0x3U) /**< Select input and output mode */
171 /** @} */
172
173 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
174 * @{
175 */
176 #define LL_GPIO_PULL_NO ((uint32_t)0x0U) /*!< Select I/O no pull */
177 #define LL_GPIO_PULL_UP ((uint32_t)0x1U) /*!< Select I/O pull up */
178 #define LL_GPIO_PULL_DOWN ((uint32_t)0x2U) /*!< Select I/O pull down */
179 /** @} */
180
181 /** @defgroup GPIO_LL_EC_SPEED IO Speed
182 * @{
183 */
184 #define LL_GPIO_SPEED_MEDIUM ((uint32_t)0x1U) /*!< Select medium speed slew rate */
185 #define LL_GPIO_SPEED_HIGH ((uint32_t)0x0U) /*!< Select high speed slew rate */
186 /** @} */
187
188 /** @defgroup GPIO_LL_EC_STRENGTH IO Strength
189 * @{
190 */
191 #define LL_GPIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
192 #define LL_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
193 #define LL_GPIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
194 #define LL_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
195 /** @} */
196
197 /** @defgroup GPIO_LL_EC_INPUT_TYPE Input type
198 * @{
199 */
200 #define LL_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
201 #define LL_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
202 /** @} */
203
204 /** @defgroup GPIO_LL_EC_TRIGGER Interrupt Trigger
205 * @{
206 */
207 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /*!< No Trigger Mode */
208 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /*!< Trigger Rising Mode */
209 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /*!< Trigger Falling Mode */
210 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /*!< Trigger High Mode */
211 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /*!< Trigger Low Mode */
212 #define LL_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /*!< Trigger Both Rising and Falling Mode */
213 /** @} */
214
215 /** @defgroup Address of GPIOx Registers
216 * @attention x=0/1/2
217 * @{
218 */
219 #define GPIO_DATA_ADDR(x) (GPIO##x##_BASE+0x00) /*!< GPIOx_DATA_ADDR */
220 #define GPIO_DATAOUT_ADDR(x) (GPIO##x##_BASE+0x04) /*!< GPIOx_DATAOUT_ADDR */
221 #define GPIO_OUTENSET_ADDR(x) (GPIO##x##_BASE+0x10) /*!< GPIOx_OUTENSET_ADDR */
222 #define GPIO_OUTENCLR_ADDR(x) (GPIO##x##_BASE+0x14) /*!< GPIOx_OUTENCLR_ADDR */
223 #define GPIO_ALTFUNCSET_ADDR(x) (GPIO##x##_BASE+0x18) /*!< GPIOx_ALTFUNCSET_ADDR */
224 #define GPIO_ALTFUNCCLR_ADDR(x) (GPIO##x##_BASE+0x1c) /*!< GPIOx_ALTFUNCCLR_ADDR */
225 #define GPIO_INTENSET_ADDR(x) (GPIO##x##_BASE+0x20) /*!< GPIOx_INTENSET_ADDR */
226 #define GPIO_INTENCLR_ADDR(x) (GPIO##x##_BASE+0x24) /*!< GPIOx_INTENCLR_ADDR */
227 #define GPIO_INTTYPESET_ADDR(x) (GPIO##x##_BASE+0x28) /*!< GPIOx_INTTYPESET_ADDR */
228 #define GPIO_INTTYPECLR_ADDR(x) (GPIO##x##_BASE+0x2c) /*!< GPIOx_INTTYPECLR_ADDR */
229 #define GPIO_INTPOLSET_ADDR(x) (GPIO##x##_BASE+0x30) /*!< GPIOx_INTPOLSET_ADDR */
230 #define GPIO_INTPOLCLR_ADDR(x) (GPIO##x##_BASE+0x34) /*!< GPIOx_INTPOLCLR_ADDR */
231 #define GPIO_INTSTAT_ADDR(x) (GPIO##x##_BASE+0x38) /*!< GPIOx_INTSTAT_ADDR */
232 #define GPIO_INTDBESET_ADDR(x) (GPIO##x##_BASE+0x40) /*!< GPIOx_INTDBESET_ADDR */
233 #define GPIO_INTDBECLR_ADDR(x) (GPIO##x##_BASE+0x44) /*!< GPIOx_INTDBECLR_ADDR */
234 /** @} */
235
236 /** @defgroup GPIO_LL_BITBAND_SET Set nth bit for GPIOx register 0 or 1
237 * @attention x=0/1/2,0<=n<=31
238 * @{
239 */
240 #define SET_GPIO_DATA(x,n) BIT_ADDR(GPIO_DATA_ADDR(x),n) /*!< BITBAND GPIOx_DATA_ADDR */
241 #define SET_GPIO_DATAOUT(x,n) BIT_ADDR(GPIO_DATAOUT_ADDR(x),n) /*!< BITBAND GPIOx_DATAOUT_ADDR */
242 #define SET_GPIO_OUTENSET(x,n) BIT_ADDR(GPIO_OUTENSET_ADDR(x),n) /*!< BITBAND GPIOx_OUTENSET_ADDR */
243 #define SET_GPIO_OUTENCLR(x,n) BIT_ADDR(GPIO_OUTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_OUTENCLR_ADDR */
244 #define SET_GPIO_ALTFUNCSET(x,n) BIT_ADDR(GPIO_ALTFUNCSET_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCSET_ADDR */
245 #define SET_GPIO_ALTFUNCCLR(x,n) BIT_ADDR(GPIO_ALTFUNCCLR_ADDR(x),n) /*!< BITBAND GPIOx_ALTFUNCCLR_ADDR */
246 #define SET_GPIO_INTENSET(x,n) BIT_ADDR(GPIO_INTENSET_ADDR(x),n) /*!< BITBAND GPIOx_INTENSET_ADDR */
247 #define SET_GPIO_INTENCLR(x,n) BIT_ADDR(GPIO_INTENCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTENCLR_ADDR */
248 #define SET_GPIO_INTTYPESET(x,n) BIT_ADDR(GPIO_INTTYPESET_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPESET_ADDR */
249 #define SET_GPIO_INTTYPECLR(x,n) BIT_ADDR(GPIO_INTTYPECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTTYPECLR_ADDR */
250 #define SET_GPIO_INTPOLSET(x,n) BIT_ADDR(GPIO_INTPOLSET_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLSET_ADDR */
251 #define SET_GPIO_INTPOLCLR(x,n) BIT_ADDR(GPIO_INTPOLCLR_ADDR(x),n) /*!< BITBAND GPIOx_INTPOLCLR_ADDR */
252 #define SET_GPIO_INTSTAT(x,n) BIT_ADDR(GPIO_INTSTAT_ADDR(x),n) /*!< BITBAND GPIOx_INTSTAT_ADDR */
253 #define SET_GPIO_INTDBESET(x,n) BIT_ADDR(GPIO_INTDBESET_ADDR(x),n) /*!< BITBAND GPIOx_INTDBESET_ADDR */
254 #define SET_GPIO_INTDBECLR(x,n) BIT_ADDR(GPIO_INTDBECLR_ADDR(x),n) /*!< BITBAND GPIOx_INTDBECLR_ADDR */
255 /** @} */
256
257 /** @defgroup GPIO_LL_EC_DEFAULT_CONFIG InitStrcut default configuration
258 * @{
259 */
260
261 /**
262 * @brief LL GPIO InitStrcut default configuration
263 */
264 #define LL_GPIO_DEFAULT_CONFIG \
265 { \
266 .pin = LL_GPIO_PIN_ALL, \
267 .mode = LL_GPIO_MODE_INPUT, \
268 .pull = LL_GPIO_PULL_DOWN, \
269 .mux = IO_MUX_GPIO, \
270 .speed = LL_GPIO_SPEED_MEDIUM, \
271 .strength = LL_GPIO_STRENGTH_MEDIUM, \
272 .input_type = LL_GPIO_INPUT_TYPE_CMOS, \
273 .trigger = LL_GPIO_TRIGGER_NONE, \
274 }
275 /** @} */
276
277 /** @} */
278
279 /* Exported macro ------------------------------------------------------------*/
280 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
281 * @{
282 */
283
284 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
285 * @{
286 */
287
288 /**
289 * @brief Write a value in GPIO register
290 * @param __instance__ GPIO instance
291 * @param __REG__ Register to be written
292 * @param __VALUE__ Value to be written in the register
293 * @retval None
294 */
295 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
296
297 /**
298 * @brief Read a value in GPIO register
299 * @param __instance__ GPIO instance
300 * @param __REG__ Register to be read
301 * @retval Register value
302 */
303 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
304
305 /** @} */
306
307 /** @} */
308
309 /* Private types -------------------------------------------------------------*/
310 /* Private variables ---------------------------------------------------------*/
311 /* Private constants ---------------------------------------------------------*/
312 /* Private macros ------------------------------------------------------------*/
313 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
314 * @{
315 */
316
317 /** @brief Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
318 * @param __GPIOx__ This parameter can be one of the following values:
319 * @arg GPIO0
320 * @arg GPIO1
321 * @retval none
322 */
323 #define LL_GPIO_GET_RESISTOR_POS(__GPIOx__) (((__GPIOx__) == GPIO0) ? 0 : 16)
324
325 /** @brief Get the starting position of the specified GPIO instance in related DPAD register.
326 * @param __GPIOx__ This parameter can be one of the following values:
327 * @arg GPIO0
328 * @arg GPIO1
329 * @retval none
330 */
331 #define LL_GPIO_GET_DPAD_POS(__GPIOx__) (((__GPIOx__) == GPIO0) ? 0 : 16)
332
333 /** @brief Get mux control register address of specified GPIO instance.
334 * @param __GPIOx__ This parameter can be one of the following values:
335 * @arg GPIO0
336 * @arg GPIO1
337 * @retval none
338 */
339 #define LL_GPIO_GET_REG_MUX_CTRL_0_7( __GPIOx__) \
340 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL_00_07) : &(MCU_SUB->DPAD_MUX_CTL_16_23))
341
342 /** @brief Get mux control register address of specified GPIO instance.
343 * @param __GPIOx__ This parameter can be one of the following values:
344 * @arg GPIO0
345 * @arg GPIO1
346 * @retval none
347 */
348 #define LL_GPIO_GET_REG_MUX_CTRL_8_15( __GPIOx__) \
349 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL_08_15) : &(MCU_SUB->DPAD_MUX_CTL_24_31))
350
351 /** @} */
352
353 /** @} */
354
355 /* Exported functions --------------------------------------------------------*/
356 /** @defgroup GPIO_LL_DRIVER_FUNCTIONS Functions
357 * @{
358 */
359
360 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
361 * @{
362 */
363
364 /**
365 * @brief Set several pins to input/output mode on dedicated port.
366 *
367 * Register|BitsName
368 * --------|--------
369 * OUTENSET | OUTENSET
370 * OUTENCLR | OUTENCLR
371 *
372 * @param GPIOx GPIO Port
373 * @param pin_mask This parameter can be a combination of the following values:
374 * @arg @ref LL_GPIO_PIN_0
375 * @arg @ref LL_GPIO_PIN_1
376 * @arg @ref LL_GPIO_PIN_2
377 * @arg @ref LL_GPIO_PIN_3
378 * @arg @ref LL_GPIO_PIN_4
379 * @arg @ref LL_GPIO_PIN_5
380 * @arg @ref LL_GPIO_PIN_6
381 * @arg @ref LL_GPIO_PIN_7
382 * @arg @ref LL_GPIO_PIN_8
383 * @arg @ref LL_GPIO_PIN_9
384 * @arg @ref LL_GPIO_PIN_10
385 * @arg @ref LL_GPIO_PIN_11
386 * @arg @ref LL_GPIO_PIN_12
387 * @arg @ref LL_GPIO_PIN_13
388 * @arg @ref LL_GPIO_PIN_ALL
389 * @param mode This parameter can be one of the following values:
390 * @arg @ref LL_GPIO_MODE_NONE
391 * @arg @ref LL_GPIO_MODE_INPUT
392 * @arg @ref LL_GPIO_MODE_OUTPUT
393 * @arg @ref LL_GPIO_MODE_INOUT
394 * @retval None
395 */
396 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
397 {
398 uint32_t ie_mask = (pin_mask << MCU_PAD_DPAD_IE_POS) & MCU_PAD_DPAD_IE;
399 uint32_t oe_mask = (pin_mask << GPIO_OUTENSET_Pos) & GPIO_OUTENSET;
400 uint32_t ie = ((mode == LL_GPIO_MODE_INPUT) || (mode == LL_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
401 uint32_t oe = ((mode == LL_GPIO_MODE_OUTPUT) || (mode == LL_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
402 MODIFY_REG(MCU_PAD->DPAD_IE_BUS, ie_mask, ie);
403 WRITE_REG(GPIOx->OUTENCLR, oe_mask);
404 WRITE_REG(GPIOx->OUTENSET, oe);
405 }
406
407 /**
408 * @brief Return gpio mode for a dedicated pin on dedicated port.
409 * @note I/O mode can be Input mode, General purpose output.
410 * @note Warning: only one pin can be passed as parameter.
411 *
412 * Register|BitsName
413 * --------|--------
414 * OUTENSET | OUTENSET
415 *
416 * @param GPIOx GPIO Port
417 * @param pin This parameter can be one of the following values:
418 * @arg @ref LL_GPIO_PIN_0
419 * @arg @ref LL_GPIO_PIN_1
420 * @arg @ref LL_GPIO_PIN_2
421 * @arg @ref LL_GPIO_PIN_3
422 * @arg @ref LL_GPIO_PIN_4
423 * @arg @ref LL_GPIO_PIN_5
424 * @arg @ref LL_GPIO_PIN_6
425 * @arg @ref LL_GPIO_PIN_7
426 * @arg @ref LL_GPIO_PIN_8
427 * @arg @ref LL_GPIO_PIN_9
428 * @arg @ref LL_GPIO_PIN_10
429 * @arg @ref LL_GPIO_PIN_11
430 * @arg @ref LL_GPIO_PIN_12
431 * @arg @ref LL_GPIO_PIN_13
432 * @retval Returned value can be one of the following values:
433 * @arg @ref LL_GPIO_MODE_NONE
434 * @arg @ref LL_GPIO_MODE_INPUT
435 * @arg @ref LL_GPIO_MODE_OUTPUT
436 * @arg @ref LL_GPIO_MODE_INOUT
437 */
438 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
439 {
440 uint32_t ie_mask = (pin << MCU_PAD_DPAD_IE_POS) & MCU_PAD_DPAD_IE;
441 uint32_t oe_mask = (pin << GPIO_OUTENSET_Pos) & GPIO_OUTENSET;
442 uint32_t ie = READ_BITS(MCU_PAD->DPAD_IE_BUS, ie_mask) >> (POSITION_VAL(pin));
443 uint32_t oe = READ_BITS(GPIOx->OUTENSET, oe_mask) >> (POSITION_VAL(pin));
444 return (((ie >> MCU_PAD_DPAD_IE_POS) << LL_GPIO_MODE_INPUT_POS)
445 | ((oe >> GPIO_OUTENSET_Pos) << LL_GPIO_MODE_OUTPUT_POS));
446 }
447
448 /**
449 * @brief Set several pins input type on dedicated port.
450 *
451 * Register|BitsName
452 * --------|--------
453 * OUTENSET | OUTENSET
454 * OUTENCLR | OUTENCLR
455 *
456 * @param GPIOx GPIO Port
457 * @param pin_mask This parameter can be a combination of the following values:
458 * @arg @ref LL_GPIO_PIN_0
459 * @arg @ref LL_GPIO_PIN_1
460 * @arg @ref LL_GPIO_PIN_2
461 * @arg @ref LL_GPIO_PIN_3
462 * @arg @ref LL_GPIO_PIN_4
463 * @arg @ref LL_GPIO_PIN_5
464 * @arg @ref LL_GPIO_PIN_6
465 * @arg @ref LL_GPIO_PIN_7
466 * @arg @ref LL_GPIO_PIN_8
467 * @arg @ref LL_GPIO_PIN_9
468 * @arg @ref LL_GPIO_PIN_10
469 * @arg @ref LL_GPIO_PIN_11
470 * @arg @ref LL_GPIO_PIN_12
471 * @arg @ref LL_GPIO_PIN_13
472 * @arg @ref LL_GPIO_PIN_ALL
473 * @param type This parameter can be one of the following values:
474 * @arg @ref LL_GPIO_INPUT_TYPE_CMOS
475 * @arg @ref LL_GPIO_INPUT_TYPE_SCHMITT
476 * @retval None
477 */
478 __STATIC_INLINE void ll_gpio_set_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t type)
479 {
480 pin_mask = (pin_mask << MCU_PAD_DPAD_IS_POS) & MCU_PAD_DPAD_IS;
481 MODIFY_REG(MCU_PAD->DPAD_IS_BUS, pin_mask, (type == LL_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
482 }
483
484 /**
485 * @brief Return gpio input type for a dedicated pin on dedicated port.
486 * @note I/O mode can be Input mode, General purpose output.
487 * @note Warning: only one pin can be passed as parameter.
488 *
489 * Register|BitsName
490 * --------|--------
491 * OUTENSET | OUTENSET
492 *
493 * @param GPIOx GPIO Port
494 * @param pin This parameter can be one of the following values:
495 * @arg @ref LL_GPIO_PIN_0
496 * @arg @ref LL_GPIO_PIN_1
497 * @arg @ref LL_GPIO_PIN_2
498 * @arg @ref LL_GPIO_PIN_3
499 * @arg @ref LL_GPIO_PIN_4
500 * @arg @ref LL_GPIO_PIN_5
501 * @arg @ref LL_GPIO_PIN_6
502 * @arg @ref LL_GPIO_PIN_7
503 * @arg @ref LL_GPIO_PIN_8
504 * @arg @ref LL_GPIO_PIN_9
505 * @arg @ref LL_GPIO_PIN_10
506 * @arg @ref LL_GPIO_PIN_11
507 * @arg @ref LL_GPIO_PIN_12
508 * @arg @ref LL_GPIO_PIN_13
509 * @retval Returned value can be one of the following values:
510 * @arg @ref LL_GPIO_INPUT_TYPE_CMOS
511 * @arg @ref LL_GPIO_INPUT_TYPE_SCHMITT
512 */
513 __STATIC_INLINE uint32_t ll_gpio_get_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin)
514 {
515 pin = (pin << MCU_PAD_DPAD_IS_POS) & MCU_PAD_DPAD_IS;
516 return ((uint32_t)(READ_BITS(MCU_PAD->DPAD_IS_BUS, pin) == pin) ?
517 LL_GPIO_INPUT_TYPE_SCHMITT : LL_GPIO_INPUT_TYPE_CMOS);
518 }
519
520 /**
521 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
522 *
523 * Register|BitsName
524 * --------|--------
525 * DPAD_PE_BUS | PE
526 * DPAD_PS_BUS | PS
527 *
528 * @param GPIOx GPIO Port
529 * @param pin_mask This parameter can be a combination of the following values:
530 * @arg @ref LL_GPIO_PIN_0
531 * @arg @ref LL_GPIO_PIN_1
532 * @arg @ref LL_GPIO_PIN_2
533 * @arg @ref LL_GPIO_PIN_3
534 * @arg @ref LL_GPIO_PIN_4
535 * @arg @ref LL_GPIO_PIN_5
536 * @arg @ref LL_GPIO_PIN_6
537 * @arg @ref LL_GPIO_PIN_7
538 * @arg @ref LL_GPIO_PIN_8
539 * @arg @ref LL_GPIO_PIN_9
540 * @arg @ref LL_GPIO_PIN_10
541 * @arg @ref LL_GPIO_PIN_11
542 * @arg @ref LL_GPIO_PIN_12
543 * @arg @ref LL_GPIO_PIN_13
544 * @param pull This parameter can be one of the following values:
545 * @arg @ref LL_GPIO_PULL_NO
546 * @arg @ref LL_GPIO_PULL_UP
547 * @arg @ref LL_GPIO_PULL_DOWN
548 * @retval None
549 */
550 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
551 {
552 MODIFY_REG(MCU_PAD->DPAD_PE_BUS, pin_mask, ((pull == LL_GPIO_PULL_NO) ? 0x0000U : pin_mask));
553 MODIFY_REG(MCU_PAD->DPAD_PS_BUS, pin_mask, ((pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U));
554 }
555
556 /**
557 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
558 * @note Warning: only one pin can be passed as parameter.
559 *
560 * Register|BitsName
561 * --------|--------
562 * DPAD_PE_BUS | PE
563 * DPAD_PS_BUS | PS
564 *
565 * @param GPIOx GPIO Port
566 * @param pin This parameter can be one of the following values:
567 * @arg @ref LL_GPIO_PIN_0
568 * @arg @ref LL_GPIO_PIN_1
569 * @arg @ref LL_GPIO_PIN_2
570 * @arg @ref LL_GPIO_PIN_3
571 * @arg @ref LL_GPIO_PIN_4
572 * @arg @ref LL_GPIO_PIN_5
573 * @arg @ref LL_GPIO_PIN_6
574 * @arg @ref LL_GPIO_PIN_7
575 * @arg @ref LL_GPIO_PIN_8
576 * @arg @ref LL_GPIO_PIN_9
577 * @arg @ref LL_GPIO_PIN_10
578 * @arg @ref LL_GPIO_PIN_11
579 * @arg @ref LL_GPIO_PIN_12
580 * @arg @ref LL_GPIO_PIN_13
581 * @retval Returned value can be one of the following values:
582 * @arg @ref LL_GPIO_PULL_NO
583 * @arg @ref LL_GPIO_PULL_UP
584 * @arg @ref LL_GPIO_PULL_DOWN
585 */
586 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
587 {
588 return ((READ_BITS(MCU_PAD->DPAD_PE_BUS, pin) == RESET) ? LL_GPIO_PULL_NO :
589 ((READ_BITS(MCU_PAD->DPAD_PS_BUS, pin) == RESET) ? LL_GPIO_PULL_DOWN : LL_GPIO_PULL_UP));
590 }
591
592 /**
593 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
594 * @note Possible values are from AF0 to AF15 depending on target.
595 * @note Warning: only one pin can be passed as parameter.
596 *
597 * Register|BitsName
598 * --------|--------
599 * DPAD_MUX | DPAD_MUX
600 *
601 * @param GPIOx GPIO Port
602 * @param pin This parameter can be one of the following values:
603 * @arg @ref LL_GPIO_PIN_0
604 * @arg @ref LL_GPIO_PIN_1
605 * @arg @ref LL_GPIO_PIN_2
606 * @arg @ref LL_GPIO_PIN_3
607 * @arg @ref LL_GPIO_PIN_4
608 * @arg @ref LL_GPIO_PIN_5
609 * @arg @ref LL_GPIO_PIN_6
610 * @arg @ref LL_GPIO_PIN_7
611 * @arg @ref LL_GPIO_PIN_8
612 * @arg @ref LL_GPIO_PIN_9
613 * @arg @ref LL_GPIO_PIN_10
614 * @arg @ref LL_GPIO_PIN_11
615 * @arg @ref LL_GPIO_PIN_12
616 * @arg @ref LL_GPIO_PIN_13
617 * @param mux This parameter can be one of the following values:
618 * IO_MUX_GPIO define
619 * @retval None
620 */
621 __STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
622 {
623 uint8_t id;
624 uint32_t pos;
625
626 pin = POSITION_VAL(pin);
627 if(GPIO0 == GPIOx)
628 {
629 id = pin >> 2;
630 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
631 }
632 else
633 {
634 id = 4;
635 pos = pin;
636 }
637
638 MODIFY_REG(MCU_PAD->DPAD_MUX[id], IO_MUX_BIT_MASK << pos, mux << pos);
639 }
640
641 /**
642 * @brief Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
643 * @note Possible values are from AF0 to AF15 depending on target.
644 *
645 * Register|BitsName
646 * --------|--------
647 * DPAD_MUX | DPAD_MUX
648 *
649 * @param GPIOx GPIO Port
650 * @param pin This parameter can be one of the following values:
651 * @arg @ref LL_GPIO_PIN_0
652 * @arg @ref LL_GPIO_PIN_1
653 * @arg @ref LL_GPIO_PIN_2
654 * @arg @ref LL_GPIO_PIN_3
655 * @arg @ref LL_GPIO_PIN_4
656 * @arg @ref LL_GPIO_PIN_5
657 * @arg @ref LL_GPIO_PIN_6
658 * @arg @ref LL_GPIO_PIN_7
659 * @arg @ref LL_GPIO_PIN_8
660 * @arg @ref LL_GPIO_PIN_9
661 * @arg @ref LL_GPIO_PIN_10
662 * @arg @ref LL_GPIO_PIN_11
663 * @arg @ref LL_GPIO_PIN_12
664 * @arg @ref LL_GPIO_PIN_13
665 * @retval Returned value can be one of the following values:
666 * IO_MUX_GPIO define
667 */
668 __STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
669 {
670 uint8_t id;
671 uint32_t pos;
672
673 pin = POSITION_VAL(pin);
674 if(GPIO0 == GPIOx)
675 {
676 id = pin >> 2;
677 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
678 }
679 else
680 {
681 id = 4;
682 pos = pin;
683 }
684
685 return (READ_BITS(MCU_PAD->DPAD_MUX[id], IO_MUX_BIT_MASK << pos) >> pos);
686 }
687
688 /**
689 * @brief Configure gpio speed for a dedicated pin on a dedicated port.
690 *
691 * Register|BitsName
692 * --------|--------
693 * MCU_PAD | DPAD_SR_BUS
694 * MCU_PAD | DPAD_SR_BUS
695 *
696 * @param GPIOx GPIO Port
697 * @param pin_mask This parameter can be a combination of the following values:
698 * @arg @ref LL_GPIO_PIN_0
699 * @arg @ref LL_GPIO_PIN_1
700 * @arg @ref LL_GPIO_PIN_2
701 * @arg @ref LL_GPIO_PIN_3
702 * @arg @ref LL_GPIO_PIN_4
703 * @arg @ref LL_GPIO_PIN_5
704 * @arg @ref LL_GPIO_PIN_6
705 * @arg @ref LL_GPIO_PIN_7
706 * @arg @ref LL_GPIO_PIN_8
707 * @arg @ref LL_GPIO_PIN_9
708 * @arg @ref LL_GPIO_PIN_10
709 * @arg @ref LL_GPIO_PIN_11
710 * @arg @ref LL_GPIO_PIN_12
711 * @arg @ref LL_GPIO_PIN_13
712 * @param speed This parameter can be one of the following values:
713 * @arg @ref LL_GPIO_SPEED_MEDIUM
714 * @arg @ref LL_GPIO_SPEED_HIGH
715 * @retval None
716 */
717 __STATIC_INLINE void ll_gpio_set_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t speed)
718 {
719 if(speed)
720 {
721 MODIFY_REG(MCU_PAD->DPAD_SR_BUS, pin_mask << MCU_PAD_DPAD_SR_POS, pin_mask << MCU_PAD_DPAD_SR_POS);
722 }
723 else
724 {
725 MODIFY_REG(MCU_PAD->DPAD_SR_BUS, pin_mask << MCU_PAD_DPAD_SR_POS, 0);
726 }
727 }
728
729 /**
730 * @brief Return gpio speed for a dedicated pin on a dedicated port
731 * @note Warning: only one pin can be passed as parameter.
732 *
733 * Register|BitsName
734 * --------|--------
735 * MCU_PAD | DPAD_SR_BUS
736 * MCU_PAD | DPAD_SR_BUS
737 *
738 * @param GPIOx GPIO Port
739 * @param pin_mask This parameter can be one of the following values:
740 * @arg @ref LL_GPIO_PIN_0
741 * @arg @ref LL_GPIO_PIN_1
742 * @arg @ref LL_GPIO_PIN_2
743 * @arg @ref LL_GPIO_PIN_3
744 * @arg @ref LL_GPIO_PIN_4
745 * @arg @ref LL_GPIO_PIN_5
746 * @arg @ref LL_GPIO_PIN_6
747 * @arg @ref LL_GPIO_PIN_7
748 * @arg @ref LL_GPIO_PIN_8
749 * @arg @ref LL_GPIO_PIN_9
750 * @arg @ref LL_GPIO_PIN_10
751 * @arg @ref LL_GPIO_PIN_11
752 * @arg @ref LL_GPIO_PIN_12
753 * @arg @ref LL_GPIO_PIN_13
754 * @retval Returned value can be one of the following values:
755 * @arg @ref LL_GPIO_SPEED_MEDIUM
756 * @arg @ref LL_GPIO_SPEED_HIGH
757 */
758 __STATIC_INLINE uint32_t ll_gpio_get_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask)
759 {
760 uint32_t pos;
761 pos = POSITION_VAL(pin_mask);
762 return (READ_BITS(MCU_PAD->DPAD_SR_BUS, pin_mask << MCU_PAD_DPAD_SR_POS ) >> pos >> MCU_PAD_DPAD_SR_POS);
763 }
764
765 /**
766 * @brief Configure gpio output drive strength for a dedicated pin on a dedicated port.
767 *
768 * Register|BitsName
769 * --------|--------
770 * MCU_PAD | DPAD_DS0_BUS
771 * MCU_PAD | DPAD_DS1_BUS
772 *
773 * @param GPIOx GPIO Port
774 * @param pin_mask This parameter can be a combination of the following values:
775 * @arg @ref LL_GPIO_PIN_0
776 * @arg @ref LL_GPIO_PIN_1
777 * @arg @ref LL_GPIO_PIN_2
778 * @arg @ref LL_GPIO_PIN_3
779 * @arg @ref LL_GPIO_PIN_4
780 * @arg @ref LL_GPIO_PIN_5
781 * @arg @ref LL_GPIO_PIN_6
782 * @arg @ref LL_GPIO_PIN_7
783 * @arg @ref LL_GPIO_PIN_8
784 * @arg @ref LL_GPIO_PIN_9
785 * @arg @ref LL_GPIO_PIN_10
786 * @arg @ref LL_GPIO_PIN_11
787 * @arg @ref LL_GPIO_PIN_12
788 * @arg @ref LL_GPIO_PIN_13
789 * @param strength This parameter can be one of the following values:
790 * @arg @ref LL_GPIO_STRENGTH_LOW
791 * @arg @ref LL_GPIO_STRENGTH_MEDIUM
792 * @arg @ref LL_GPIO_STRENGTH_HIGH
793 * @arg @ref LL_GPIO_STRENGTH_ULTRA
794 * @retval None
795 */
796 __STATIC_INLINE void ll_gpio_set_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t strength)
797 {
798 uint8_t ds0 = (strength & LL_GPIO_STRENGTH_DS0_MASK) >> LL_GPIO_STRENGTH_DS0_POS;
799 uint8_t ds1 = (strength & LL_GPIO_STRENGTH_DS1_MASK) >> LL_GPIO_STRENGTH_DS1_POS;
800 if(ds0)
801 {
802 MODIFY_REG(MCU_PAD->DPAD_DS0_BUS, pin_mask << MCU_PAD_DPAD_DS0_POS , pin_mask << MCU_PAD_DPAD_DS0_POS);
803 }
804 else
805 {
806 MODIFY_REG(MCU_PAD->DPAD_DS0_BUS, pin_mask << MCU_PAD_DPAD_DS0_POS , 0);
807 }
808 if(ds1)
809 {
810 MODIFY_REG(MCU_PAD->DPAD_DS1_BUS, pin_mask << MCU_PAD_DPAD_DS1_POS , pin_mask << MCU_PAD_DPAD_DS1_POS);
811 }
812 else
813 {
814 MODIFY_REG(MCU_PAD->DPAD_DS1_BUS, pin_mask << MCU_PAD_DPAD_DS1_POS , 0);
815 }
816 }
817
818 /**
819 * @brief Return gpio output drive strength for a dedicated pin on a dedicated port
820 * @note Warning: only one pin can be passed as parameter.
821 *
822 * Register|BitsName
823 * --------|--------
824 * MCU_PAD | DPAD_DS0_BUS
825 * MCU_PAD | DPAD_DS1_BUS
826 *
827 * @param GPIOx GPIO Port
828 * @param pin_mask This parameter can be one of the following values:
829 * @arg @ref LL_GPIO_PIN_0
830 * @arg @ref LL_GPIO_PIN_1
831 * @arg @ref LL_GPIO_PIN_2
832 * @arg @ref LL_GPIO_PIN_3
833 * @arg @ref LL_GPIO_PIN_4
834 * @arg @ref LL_GPIO_PIN_5
835 * @arg @ref LL_GPIO_PIN_6
836 * @arg @ref LL_GPIO_PIN_7
837 * @arg @ref LL_GPIO_PIN_8
838 * @arg @ref LL_GPIO_PIN_9
839 * @arg @ref LL_GPIO_PIN_10
840 * @arg @ref LL_GPIO_PIN_11
841 * @arg @ref LL_GPIO_PIN_12
842 * @arg @ref LL_GPIO_PIN_13
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_GPIO_STRENGTH_LOW
845 * @arg @ref LL_GPIO_STRENGTH_MEDIUM
846 * @arg @ref LL_GPIO_STRENGTH_HIGH
847 * @arg @ref LL_GPIO_STRENGTH_ULTRA
848 */
849 __STATIC_INLINE uint32_t ll_gpio_get_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask)
850 {
851 uint32_t pos;
852 pos = POSITION_VAL(pin_mask);
853 uint8_t ds0 = READ_BITS(MCU_PAD->DPAD_DS0_BUS, pin_mask << MCU_PAD_DPAD_DS0_POS ) >> MCU_PAD_DPAD_DS0_POS >> pos;
854 uint8_t ds1 = READ_BITS(MCU_PAD->DPAD_DS1_BUS, pin_mask << MCU_PAD_DPAD_DS1_POS ) >> MCU_PAD_DPAD_DS1_POS >> pos;
855 return ((ds0 << LL_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_GPIO_STRENGTH_DS1_POS));
856 }
857 /** @} */
858
859 /** @defgroup GPIO_LL_EF_Data_Access Data Access
860 * @{
861 */
862
863 /**
864 * @brief Return full input data register value for a dedicated port.
865 *
866 * Register|BitsName
867 * --------|--------
868 * DATA | DATA
869 *
870 * @param GPIOx GPIO Port
871 * @retval Input data register value of port
872 */
873 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
874 {
875 return (uint32_t)(READ_REG(GPIOx->DATA));
876 }
877
878 /**
879 * @brief Return if input data level for several pins of dedicated port is high or low.
880 *
881 * Register|BitsName
882 * --------|--------
883 * DATA | DATA
884 *
885 * @param GPIOx GPIO Port
886 * @param pin_mask This parameter can be a combination of the following values:
887 * @arg @ref LL_GPIO_PIN_0
888 * @arg @ref LL_GPIO_PIN_1
889 * @arg @ref LL_GPIO_PIN_2
890 * @arg @ref LL_GPIO_PIN_3
891 * @arg @ref LL_GPIO_PIN_4
892 * @arg @ref LL_GPIO_PIN_5
893 * @arg @ref LL_GPIO_PIN_6
894 * @arg @ref LL_GPIO_PIN_7
895 * @arg @ref LL_GPIO_PIN_8
896 * @arg @ref LL_GPIO_PIN_9
897 * @arg @ref LL_GPIO_PIN_10
898 * @arg @ref LL_GPIO_PIN_11
899 * @arg @ref LL_GPIO_PIN_12
900 * @arg @ref LL_GPIO_PIN_13
901 * @arg @ref LL_GPIO_PIN_ALL
902 * @retval State of bit (1 or 0).
903 */
904 __STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
905 {
906 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
907 }
908
909 /**
910 * @brief Write output data register for the port.
911 *
912 * Register|BitsName
913 * --------|--------
914 * DATAOUT | DATAOUT
915 *
916 * @param GPIOx GPIO Port
917 * @param port_value Level value for each pin of the port
918 * @retval None
919 */
920 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
921 {
922 WRITE_REG(GPIOx->DATAOUT, port_value);
923 }
924
925 /**
926 * @brief Return full output data register value for a dedicated port.
927 *
928 * Register|BitsName
929 * --------|--------
930 * DATAOUT | DATAOUT
931 *
932 * @param GPIOx GPIO Port
933 * @retval Output data register value of port
934 */
935 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
936 {
937 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
938 }
939
940 /**
941 * @brief Return if output data level for several pins of dedicated port is high or low.
942 *
943 * Register|BitsName
944 * --------|--------
945 * DATA | DATAOUT
946 *
947 * @param GPIOx GPIO Port
948 * @param pin_mask This parameter can be a combination of the following values:
949 * @arg @ref LL_GPIO_PIN_0
950 * @arg @ref LL_GPIO_PIN_1
951 * @arg @ref LL_GPIO_PIN_2
952 * @arg @ref LL_GPIO_PIN_3
953 * @arg @ref LL_GPIO_PIN_4
954 * @arg @ref LL_GPIO_PIN_5
955 * @arg @ref LL_GPIO_PIN_6
956 * @arg @ref LL_GPIO_PIN_7
957 * @arg @ref LL_GPIO_PIN_8
958 * @arg @ref LL_GPIO_PIN_9
959 * @arg @ref LL_GPIO_PIN_10
960 * @arg @ref LL_GPIO_PIN_11
961 * @arg @ref LL_GPIO_PIN_12
962 * @arg @ref LL_GPIO_PIN_13
963 * @arg @ref LL_GPIO_PIN_ALL
964 * @retval State of bit (1 or 0).
965 */
966 __STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
967 {
968 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
969 }
970
971 /**
972 * @brief Return if input data level for several pins of dedicated port is high or low.
973 *
974 * Register|BitsName
975 * --------|--------
976 * DATAOUT | DATAOUT
977 *
978 * @param GPIOx GPIO Port
979 * @param pin_mask This parameter can be a combination of the following values:
980 * @arg @ref LL_GPIO_PIN_0
981 * @arg @ref LL_GPIO_PIN_1
982 * @arg @ref LL_GPIO_PIN_2
983 * @arg @ref LL_GPIO_PIN_3
984 * @arg @ref LL_GPIO_PIN_4
985 * @arg @ref LL_GPIO_PIN_5
986 * @arg @ref LL_GPIO_PIN_6
987 * @arg @ref LL_GPIO_PIN_7
988 * @arg @ref LL_GPIO_PIN_8
989 * @arg @ref LL_GPIO_PIN_9
990 * @arg @ref LL_GPIO_PIN_10
991 * @arg @ref LL_GPIO_PIN_11
992 * @arg @ref LL_GPIO_PIN_12
993 * @arg @ref LL_GPIO_PIN_13
994 * @arg @ref LL_GPIO_PIN_ALL
995 * @retval State of bit (1 or 0).
996 */
997 __STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
998 {
999 return (READ_BITS(GPIOx->OUTENSET, pin_mask) == (pin_mask));
1000 }
1001
1002 /**
1003 * @brief Set several pins to high level on dedicated gpio port.
1004 *
1005 * Register|BitsName
1006 * --------|--------
1007 * DATAOUT | DATAOUT
1008 *
1009 * @param GPIOx GPIO Port
1010 * @param pin_mask This parameter can be a combination of the following values:
1011 * @arg @ref LL_GPIO_PIN_0
1012 * @arg @ref LL_GPIO_PIN_1
1013 * @arg @ref LL_GPIO_PIN_2
1014 * @arg @ref LL_GPIO_PIN_3
1015 * @arg @ref LL_GPIO_PIN_4
1016 * @arg @ref LL_GPIO_PIN_5
1017 * @arg @ref LL_GPIO_PIN_6
1018 * @arg @ref LL_GPIO_PIN_7
1019 * @arg @ref LL_GPIO_PIN_8
1020 * @arg @ref LL_GPIO_PIN_9
1021 * @arg @ref LL_GPIO_PIN_10
1022 * @arg @ref LL_GPIO_PIN_11
1023 * @arg @ref LL_GPIO_PIN_12
1024 * @arg @ref LL_GPIO_PIN_13
1025 * @arg @ref LL_GPIO_PIN_ALL
1026 * @retval None
1027 */
1028 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1029 {
1030 #ifdef USE_GPIO_MASK_REGISTER
1031 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
1032 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
1033 pin_mask & GPIO_MASKHIGHBYTE_DATA);
1034 #else
1035 SET_BITS(GPIOx->DATAOUT, pin_mask);
1036 #endif
1037 }
1038
1039 /**
1040 * @brief Set several pins to low level on dedicated gpio port.
1041 *
1042 * Register|BitsName
1043 * --------|--------
1044 * DATAOUT | DATAOUT
1045 *
1046 * @param GPIOx GPIO Port
1047 * @param pin_mask This parameter can be a combination of the following values:
1048 * @arg @ref LL_GPIO_PIN_0
1049 * @arg @ref LL_GPIO_PIN_1
1050 * @arg @ref LL_GPIO_PIN_2
1051 * @arg @ref LL_GPIO_PIN_3
1052 * @arg @ref LL_GPIO_PIN_4
1053 * @arg @ref LL_GPIO_PIN_5
1054 * @arg @ref LL_GPIO_PIN_6
1055 * @arg @ref LL_GPIO_PIN_7
1056 * @arg @ref LL_GPIO_PIN_8
1057 * @arg @ref LL_GPIO_PIN_9
1058 * @arg @ref LL_GPIO_PIN_10
1059 * @arg @ref LL_GPIO_PIN_11
1060 * @arg @ref LL_GPIO_PIN_12
1061 * @arg @ref LL_GPIO_PIN_13
1062 * @arg @ref LL_GPIO_PIN_ALL
1063 * @retval None
1064 */
1065 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1066 {
1067 #ifdef USE_GPIO_MASK_REGISTER
1068 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
1069 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
1070 #else
1071 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
1072 #endif
1073 }
1074
1075 /**
1076 * @brief Toggle data value for several pin of dedicated port.
1077 *
1078 * Register|BitsName
1079 * --------|--------
1080 * DATAOUT | DATAOUT
1081 *
1082 * @param GPIOx GPIO Port
1083 * @param pin_mask This parameter can be a combination of the following values:
1084 * @arg @ref LL_GPIO_PIN_0
1085 * @arg @ref LL_GPIO_PIN_1
1086 * @arg @ref LL_GPIO_PIN_2
1087 * @arg @ref LL_GPIO_PIN_3
1088 * @arg @ref LL_GPIO_PIN_4
1089 * @arg @ref LL_GPIO_PIN_5
1090 * @arg @ref LL_GPIO_PIN_6
1091 * @arg @ref LL_GPIO_PIN_7
1092 * @arg @ref LL_GPIO_PIN_8
1093 * @arg @ref LL_GPIO_PIN_9
1094 * @arg @ref LL_GPIO_PIN_10
1095 * @arg @ref LL_GPIO_PIN_11
1096 * @arg @ref LL_GPIO_PIN_12
1097 * @arg @ref LL_GPIO_PIN_13
1098 * @arg @ref LL_GPIO_PIN_ALL
1099 * @retval None
1100 */
1101 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
1102 {
1103 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
1104 }
1105
1106 /** @} */
1107
1108 /** @defgroup GPIO_LL_EF_IT_Management IT_Management
1109 * @{
1110 */
1111
1112 /**
1113 * @brief Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
1114 * @note
1115 *
1116 * Register|BitsName
1117 * --------|--------
1118 * INTPOLCLR | INTPOLCLR
1119 * INTTYPESET | INTTYPESET
1120 *
1121 * @param GPIOx GPIO instance.
1122 * @param pin_mask This parameter can be a combination of the following values:
1123 * @arg @ref LL_GPIO_PIN_0
1124 * @arg @ref LL_GPIO_PIN_1
1125 * @arg @ref LL_GPIO_PIN_2
1126 * @arg @ref LL_GPIO_PIN_3
1127 * @arg @ref LL_GPIO_PIN_4
1128 * @arg @ref LL_GPIO_PIN_5
1129 * @arg @ref LL_GPIO_PIN_6
1130 * @arg @ref LL_GPIO_PIN_7
1131 * @arg @ref LL_GPIO_PIN_8
1132 * @arg @ref LL_GPIO_PIN_9
1133 * @arg @ref LL_GPIO_PIN_10
1134 * @arg @ref LL_GPIO_PIN_11
1135 * @arg @ref LL_GPIO_PIN_12
1136 * @arg @ref LL_GPIO_PIN_13
1137 * @arg @ref LL_GPIO_PIN_ALL
1138 * @retval None
1139 */
1140 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1141 {
1142 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1143 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1144 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
1145 }
1146
1147 /**
1148 * @brief Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
1149 * @note
1150 *
1151 * Register|BitsName
1152 * --------|--------
1153 * INTPOLSET | INTPOLSET
1154 * INTTYPESET | INTTYPESET
1155 *
1156 * @param GPIOx GPIO instance.
1157 * @param pin_mask This parameter can be a combination of the following values:
1158 * @arg @ref LL_GPIO_PIN_0
1159 * @arg @ref LL_GPIO_PIN_1
1160 * @arg @ref LL_GPIO_PIN_2
1161 * @arg @ref LL_GPIO_PIN_3
1162 * @arg @ref LL_GPIO_PIN_4
1163 * @arg @ref LL_GPIO_PIN_5
1164 * @arg @ref LL_GPIO_PIN_6
1165 * @arg @ref LL_GPIO_PIN_7
1166 * @arg @ref LL_GPIO_PIN_8
1167 * @arg @ref LL_GPIO_PIN_9
1168 * @arg @ref LL_GPIO_PIN_10
1169 * @arg @ref LL_GPIO_PIN_11
1170 * @arg @ref LL_GPIO_PIN_12
1171 * @arg @ref LL_GPIO_PIN_13
1172 * @arg @ref LL_GPIO_PIN_ALL
1173 * @retval None
1174 */
1175 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1176 {
1177 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1178 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1179 WRITE_REG(GPIOx->INTDBECLR, pin_mask);
1180 }
1181
1182 /**
1183 * @brief Enable GPIO High Level Trigger for pins in the range of 0 to 15.
1184 * @note
1185 *
1186 * Register|BitsName
1187 * --------|--------
1188 * INTPOLSET | INTPOLSET
1189 * INTTYPECLR | INTTYPECLR
1190 *
1191 * @param GPIOx GPIO instance.
1192 * @param pin_mask This parameter can be a combination of the following values:
1193 * @arg @ref LL_GPIO_PIN_0
1194 * @arg @ref LL_GPIO_PIN_1
1195 * @arg @ref LL_GPIO_PIN_2
1196 * @arg @ref LL_GPIO_PIN_3
1197 * @arg @ref LL_GPIO_PIN_4
1198 * @arg @ref LL_GPIO_PIN_5
1199 * @arg @ref LL_GPIO_PIN_6
1200 * @arg @ref LL_GPIO_PIN_7
1201 * @arg @ref LL_GPIO_PIN_8
1202 * @arg @ref LL_GPIO_PIN_9
1203 * @arg @ref LL_GPIO_PIN_10
1204 * @arg @ref LL_GPIO_PIN_11
1205 * @arg @ref LL_GPIO_PIN_12
1206 * @arg @ref LL_GPIO_PIN_13
1207 * @arg @ref LL_GPIO_PIN_ALL
1208 * @retval None
1209 */
1210 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1211 {
1212 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1213 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1214 }
1215
1216 /**
1217 * @brief Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
1218 * @note
1219 *
1220 * Register|BitsName
1221 * --------|--------
1222 * INTPOLCLR | INTPOLCLR
1223 * INTTYPECLR | INTTYPECLR
1224 *
1225 * @param GPIOx GPIO instance.
1226 * @param pin_mask This parameter can be a combination of the following values:
1227 * @arg @ref LL_GPIO_PIN_0
1228 * @arg @ref LL_GPIO_PIN_1
1229 * @arg @ref LL_GPIO_PIN_2
1230 * @arg @ref LL_GPIO_PIN_3
1231 * @arg @ref LL_GPIO_PIN_4
1232 * @arg @ref LL_GPIO_PIN_5
1233 * @arg @ref LL_GPIO_PIN_6
1234 * @arg @ref LL_GPIO_PIN_7
1235 * @arg @ref LL_GPIO_PIN_8
1236 * @arg @ref LL_GPIO_PIN_9
1237 * @arg @ref LL_GPIO_PIN_10
1238 * @arg @ref LL_GPIO_PIN_11
1239 * @arg @ref LL_GPIO_PIN_12
1240 * @arg @ref LL_GPIO_PIN_13
1241 * @arg @ref LL_GPIO_PIN_ALL
1242 * @retval None
1243 */
1244 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1245 {
1246 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1247 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1248 }
1249
1250 /**
1251 * @brief Enable GPIO both edge Trigger for pins in the range of 0 to 15.
1252 * @note
1253 *
1254 * Register|BitsName
1255 * --------|--------
1256 * INTPOLCLR | INTPOLCLR
1257 * INTTYPESET | INTTYPESET
1258 * INTTYPESET | INTTYPESET
1259 *
1260 * @param GPIOx GPIO instance.
1261 * @param pin_mask This parameter can be a combination of the following values:
1262 * @arg @ref LL_GPIO_PIN_0
1263 * @arg @ref LL_GPIO_PIN_1
1264 * @arg @ref LL_GPIO_PIN_2
1265 * @arg @ref LL_GPIO_PIN_3
1266 * @arg @ref LL_GPIO_PIN_4
1267 * @arg @ref LL_GPIO_PIN_5
1268 * @arg @ref LL_GPIO_PIN_6
1269 * @arg @ref LL_GPIO_PIN_7
1270 * @arg @ref LL_GPIO_PIN_8
1271 * @arg @ref LL_GPIO_PIN_9
1272 * @arg @ref LL_GPIO_PIN_10
1273 * @arg @ref LL_GPIO_PIN_11
1274 * @arg @ref LL_GPIO_PIN_12
1275 * @arg @ref LL_GPIO_PIN_13
1276 * @arg @ref LL_GPIO_PIN_ALL
1277 * @retval None
1278 */
1279 __STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1280 {
1281 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1282 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1283 WRITE_REG(GPIOx->INTDBESET, pin_mask);
1284 }
1285
1286 /**
1287 * @brief Get trigger type for pins in the range of 0 to 15
1288 * @note
1289 *
1290 * Register|BitsName
1291 * --------|--------
1292 * INTPOLCLR | INTPOLCLR
1293 * INTTYPECLR | INTTYPECLR
1294 * INTTYPESET | INTTYPESET
1295 *
1296 * @param GPIOx GPIO instance.
1297 * @param pin_mask This parameter can be a combination of the following values:
1298 * @arg @ref LL_GPIO_PIN_0
1299 * @arg @ref LL_GPIO_PIN_1
1300 * @arg @ref LL_GPIO_PIN_2
1301 * @arg @ref LL_GPIO_PIN_3
1302 * @arg @ref LL_GPIO_PIN_4
1303 * @arg @ref LL_GPIO_PIN_5
1304 * @arg @ref LL_GPIO_PIN_6
1305 * @arg @ref LL_GPIO_PIN_7
1306 * @arg @ref LL_GPIO_PIN_8
1307 * @arg @ref LL_GPIO_PIN_9
1308 * @arg @ref LL_GPIO_PIN_10
1309 * @arg @ref LL_GPIO_PIN_11
1310 * @arg @ref LL_GPIO_PIN_12
1311 * @arg @ref LL_GPIO_PIN_13
1312 * @retval Returned value can be one of the following values:
1313 * @arg @ref LL_GPIO_PULL_NO
1314 * @arg @ref LL_GPIO_PULL_UP
1315 * @arg @ref LL_GPIO_PULL_DOWN
1316 */
1317 __STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
1318 {
1319 /* INTTYPESET INTPOLSET INTDBESET
1320 TRIGGER_FALLING 1 0 0
1321 TRIGGER_RISING 1 1 0
1322 TRIGGER_BOTH_EDGE 1 X 1
1323 TRIGGER_HIGH 0 1 X
1324 TRIGGER_LOW 0 0 X
1325 */
1326 #define TYPE_SET ((uint32_t)0x4U) // GPIO INTTYPESET is set
1327 #define POL_SET ((uint32_t)0x2U) // GPIO INTPOLSET is set
1328 #define DBE_SET ((uint32_t)0x1U) // GPIO INTDBESET is set
1329
1330 uint32_t pos = POSITION_VAL(pin_mask);
1331 uint32_t type = (READ_BITS(GPIOx->INTTYPESET, pin_mask) >> pos ) << 2;
1332 uint32_t pol = (READ_BITS(GPIOx->INTPOLSET, pin_mask) >> pos) << 1;
1333 uint32_t both_egde = (READ_BITS(GPIOx->INTDBESET, pin_mask) >> pos);
1334
1335 switch (type | pol | both_egde)
1336 {
1337 case TYPE_SET:
1338 return LL_GPIO_TRIGGER_FALLING;
1339 case TYPE_SET | POL_SET:
1340 return LL_GPIO_TRIGGER_RISING;
1341 case TYPE_SET | DBE_SET:
1342 return LL_GPIO_TRIGGER_BOTH_EDGE;
1343 case TYPE_SET | POL_SET | DBE_SET:
1344 return LL_GPIO_TRIGGER_BOTH_EDGE;
1345 case POL_SET:
1346 return LL_GPIO_TRIGGER_HIGH;
1347 default:
1348 return LL_GPIO_TRIGGER_LOW;
1349 }
1350
1351 #undef TYPE_SET
1352 #undef POL_SET
1353 #undef BOTH_SET
1354 }
1355
1356 /**
1357 * @brief Enable GPIO interrupts for pins in the range of 0 to 15.
1358 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1359 *
1360 * Register|BitsName
1361 * --------|--------
1362 * INTENSET | INTENSET
1363 *
1364 * @param GPIOx GPIO instance.
1365 * @param pin_mask This parameter can be a combination of the following values:
1366 * @arg @ref LL_GPIO_PIN_0
1367 * @arg @ref LL_GPIO_PIN_1
1368 * @arg @ref LL_GPIO_PIN_2
1369 * @arg @ref LL_GPIO_PIN_3
1370 * @arg @ref LL_GPIO_PIN_4
1371 * @arg @ref LL_GPIO_PIN_5
1372 * @arg @ref LL_GPIO_PIN_6
1373 * @arg @ref LL_GPIO_PIN_7
1374 * @arg @ref LL_GPIO_PIN_8
1375 * @arg @ref LL_GPIO_PIN_9
1376 * @arg @ref LL_GPIO_PIN_10
1377 * @arg @ref LL_GPIO_PIN_11
1378 * @arg @ref LL_GPIO_PIN_12
1379 * @arg @ref LL_GPIO_PIN_13
1380 * @arg @ref LL_GPIO_PIN_ALL
1381 * @retval None
1382 */
1383 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1384 {
1385 WRITE_REG(GPIOx->INTENSET, pin_mask);
1386 }
1387
1388 /**
1389 * @brief Disable GPIO interrupts for pins in the range of 0 to 15.
1390 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1391 *
1392 * Register|BitsName
1393 * --------|--------
1394 * INTENCLR | INTENCLR
1395 *
1396 * @param GPIOx GPIO instance.
1397 * @param pin_mask This parameter can be a combination of the following values:
1398 * @arg @ref LL_GPIO_PIN_0
1399 * @arg @ref LL_GPIO_PIN_1
1400 * @arg @ref LL_GPIO_PIN_2
1401 * @arg @ref LL_GPIO_PIN_3
1402 * @arg @ref LL_GPIO_PIN_4
1403 * @arg @ref LL_GPIO_PIN_5
1404 * @arg @ref LL_GPIO_PIN_6
1405 * @arg @ref LL_GPIO_PIN_7
1406 * @arg @ref LL_GPIO_PIN_8
1407 * @arg @ref LL_GPIO_PIN_9
1408 * @arg @ref LL_GPIO_PIN_10
1409 * @arg @ref LL_GPIO_PIN_11
1410 * @arg @ref LL_GPIO_PIN_12
1411 * @arg @ref LL_GPIO_PIN_13
1412 * @arg @ref LL_GPIO_PIN_ALL
1413 * @retval None
1414 */
1415 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1416 {
1417 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1418 }
1419
1420 /**
1421 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1422 *
1423 * Register|BitsName
1424 * --------|--------
1425 * INTENSET | INTENSET
1426 *
1427 * @param GPIOx GPIO instance.
1428 * @param pin_mask This parameter can be a combination of the following values:
1429 * @arg @ref LL_GPIO_PIN_0
1430 * @arg @ref LL_GPIO_PIN_1
1431 * @arg @ref LL_GPIO_PIN_2
1432 * @arg @ref LL_GPIO_PIN_3
1433 * @arg @ref LL_GPIO_PIN_4
1434 * @arg @ref LL_GPIO_PIN_5
1435 * @arg @ref LL_GPIO_PIN_6
1436 * @arg @ref LL_GPIO_PIN_7
1437 * @arg @ref LL_GPIO_PIN_8
1438 * @arg @ref LL_GPIO_PIN_9
1439 * @arg @ref LL_GPIO_PIN_10
1440 * @arg @ref LL_GPIO_PIN_11
1441 * @arg @ref LL_GPIO_PIN_12
1442 * @arg @ref LL_GPIO_PIN_13
1443 * @arg @ref LL_GPIO_PIN_ALL
1444 * @retval State of bit (1 or 0).
1445 */
1446 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1447 {
1448 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1449 }
1450
1451 /** @} */
1452
1453 /** @defgroup GPIO_LL_EF_Flag_Management Flag_Management
1454 * @{
1455 */
1456
1457 /**
1458 * @brief Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15
1459 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1460 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1461 *
1462 * Register|BitsName
1463 * --------|--------
1464 * INTSTATUS | INTSTATUS
1465 *
1466 * @param GPIOx GPIO instance.
1467 * @param pin_mask This parameter can be a combination of the following values:
1468 * @arg @ref LL_GPIO_PIN_0
1469 * @arg @ref LL_GPIO_PIN_1
1470 * @arg @ref LL_GPIO_PIN_2
1471 * @arg @ref LL_GPIO_PIN_3
1472 * @arg @ref LL_GPIO_PIN_4
1473 * @arg @ref LL_GPIO_PIN_5
1474 * @arg @ref LL_GPIO_PIN_6
1475 * @arg @ref LL_GPIO_PIN_7
1476 * @arg @ref LL_GPIO_PIN_8
1477 * @arg @ref LL_GPIO_PIN_9
1478 * @arg @ref LL_GPIO_PIN_10
1479 * @arg @ref LL_GPIO_PIN_11
1480 * @arg @ref LL_GPIO_PIN_12
1481 * @arg @ref LL_GPIO_PIN_13
1482 * @arg @ref LL_GPIO_PIN_ALL
1483 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1484 */
1485 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1486 {
1487 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1488 }
1489
1490 /**
1491 * @brief Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
1492 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1493 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1494 *
1495 * Register|BitsName
1496 * --------|--------
1497 * INTSTATUS | INTSTATUS
1498 *
1499 * @param GPIOx GPIO instance.
1500 * @param pin_mask This parameter can be a combination of the following values:
1501 * @arg @ref LL_GPIO_PIN_0
1502 * @arg @ref LL_GPIO_PIN_1
1503 * @arg @ref LL_GPIO_PIN_2
1504 * @arg @ref LL_GPIO_PIN_3
1505 * @arg @ref LL_GPIO_PIN_4
1506 * @arg @ref LL_GPIO_PIN_5
1507 * @arg @ref LL_GPIO_PIN_6
1508 * @arg @ref LL_GPIO_PIN_7
1509 * @arg @ref LL_GPIO_PIN_8
1510 * @arg @ref LL_GPIO_PIN_9
1511 * @arg @ref LL_GPIO_PIN_10
1512 * @arg @ref LL_GPIO_PIN_11
1513 * @arg @ref LL_GPIO_PIN_12
1514 * @arg @ref LL_GPIO_PIN_13
1515 * @arg @ref LL_GPIO_PIN_ALL
1516 * @retval State of bit (1 or 0).
1517 */
1518 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1519 {
1520 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1521 }
1522
1523 /**
1524 * @brief Clear Interrupt Status flag for pins in the range of 0 to 15.
1525 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1526 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1527 *
1528 * Register|BitsName
1529 * --------|--------
1530 * INTSTATUS | INTSTATUS
1531 *
1532 * @param GPIOx GPIO instance.
1533 * @param pin_mask This parameter can be a combination of the following values:
1534 * @arg @ref LL_GPIO_PIN_0
1535 * @arg @ref LL_GPIO_PIN_1
1536 * @arg @ref LL_GPIO_PIN_2
1537 * @arg @ref LL_GPIO_PIN_3
1538 * @arg @ref LL_GPIO_PIN_4
1539 * @arg @ref LL_GPIO_PIN_5
1540 * @arg @ref LL_GPIO_PIN_6
1541 * @arg @ref LL_GPIO_PIN_7
1542 * @arg @ref LL_GPIO_PIN_8
1543 * @arg @ref LL_GPIO_PIN_9
1544 * @arg @ref LL_GPIO_PIN_10
1545 * @arg @ref LL_GPIO_PIN_11
1546 * @arg @ref LL_GPIO_PIN_12
1547 * @arg @ref LL_GPIO_PIN_13
1548 * @arg @ref LL_GPIO_PIN_ALL
1549 * @retval None
1550 */
1551 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1552 {
1553 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1554 }
1555
1556 /** @} */
1557
1558 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
1559 * @{
1560 */
1561 /**
1562 * @brief Initialize GPIO registers according to the specified
1563 * parameters in p_gpio_init.
1564 * @param GPIOx GPIO instance.
1565 * @param p_gpio_init Pointer to a ll_gpio_init_t structure that contains the configuration
1566 * information for the specified GPIO peripheral.
1567 * @retval An error_status_t enumeration value:
1568 * - SUCCESS: GPIO registers are initialized according to p_gpio_init content
1569 * - ERROR: Problem occurred during GPIO Registers initialization
1570 */
1571 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1572 /** @} */
1573
1574 /** @} */
1575
1576 #endif /* defined (GPIO0) || defined (GPIO1) */
1577
1578 #ifdef __cplusplus
1579 }
1580 #endif
1581
1582 #endif /* __GR533x_LL_GPIO_H__ */
1583
1584 /** @} */
1585
1586 /** @} */
1587
1588 /** @} */
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr533x_ll_gpio.h:873
_ll_gpio_init::pin
uint32_t pin
Definition: gr533x_ll_gpio.h:78
LL_GPIO_STRENGTH_DS1_POS
#define LL_GPIO_STRENGTH_DS1_POS
Definition: gr533x_ll_gpio.h:141
ll_gpio_get_pin_strength
__STATIC_INLINE uint32_t ll_gpio_get_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return gpio output drive strength for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:849
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr533x_ll_gpio.h:176
LL_GPIO_TRIGGER_RISING
#define LL_GPIO_TRIGGER_RISING
Definition: gr533x_ll_gpio.h:208
ll_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr533x_ll_gpio.h:997
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1210
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr533x_ll_gpio.h:1446
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr533x_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
_ll_gpio_init::strength
uint32_t strength
Definition: gr533x_ll_gpio.h:103
ll_gpio_get_pin_speed
__STATIC_INLINE uint32_t ll_gpio_get_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return gpio speed for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:758
LL_GPIO_INPUT_TYPE_SCHMITT
#define LL_GPIO_INPUT_TYPE_SCHMITT
Definition: gr533x_ll_gpio.h:201
DBE_SET
#define DBE_SET
ll_gpio_get_pin_input_type
__STATIC_INLINE uint32_t ll_gpio_get_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio input type for a dedicated pin on dedicated port.
Definition: gr533x_ll_gpio.h:513
LL_GPIO_STRENGTH_DS1_MASK
#define LL_GPIO_STRENGTH_DS1_MASK
Definition: gr533x_ll_gpio.h:139
ll_gpio_read_input_pin
__STATIC_INLINE uint32_t ll_gpio_read_input_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr533x_ll_gpio.h:904
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr533x_ll_gpio.h:177
_ll_gpio_init::mux
uint32_t mux
Definition: gr533x_ll_gpio.h:91
LL_GPIO_MODE_INOUT
#define LL_GPIO_MODE_INOUT
Definition: gr533x_ll_gpio.h:170
TYPE_SET
#define TYPE_SET
ll_gpio_read_output_pin
__STATIC_INLINE uint32_t ll_gpio_read_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if output data level for several pins of dedicated port is high or low.
Definition: gr533x_ll_gpio.h:966
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr533x_ll_gpio.h:115
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr533x_ll_gpio.h:935
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr533x_ll_gpio.h:1028
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1175
ll_gpio_enable_both_edge_trigger
__STATIC_INLINE void ll_gpio_enable_both_edge_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO both edge Trigger for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1279
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1518
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1383
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr533x_ll_gpio.h:438
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:586
LL_GPIO_MODE_OUTPUT_POS
#define LL_GPIO_MODE_OUTPUT_POS
Definition: gr533x_ll_gpio.h:137
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr533x_ll_gpio.h:1065
_ll_gpio_init::speed
uint32_t speed
Definition: gr533x_ll_gpio.h:97
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr533x_ll_gpio.h:178
LL_GPIO_TRIGGER_LOW
#define LL_GPIO_TRIGGER_LOW
Definition: gr533x_ll_gpio.h:211
LL_GPIO_TRIGGER_HIGH
#define LL_GPIO_TRIGGER_HIGH
Definition: gr533x_ll_gpio.h:210
LL_GPIO_TRIGGER_FALLING
#define LL_GPIO_TRIGGER_FALLING
Definition: gr533x_ll_gpio.h:209
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr533x_ll_gpio.h:1101
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr533x_ll_gpio.h:920
ll_gpio_set_pin_speed
__STATIC_INLINE void ll_gpio_set_pin_speed(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t speed)
Configure gpio speed for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:717
LL_GPIO_TRIGGER_BOTH_EDGE
#define LL_GPIO_TRIGGER_BOTH_EDGE
Definition: gr533x_ll_gpio.h:212
ll_gpio_get_trigger_type
__STATIC_INLINE uint32_t ll_gpio_get_trigger_type(gpio_regs_t *GPIOx, uint32_t pin_mask)
Get trigger type for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1317
_ll_gpio_init::input_type
uint32_t input_type
Definition: gr533x_ll_gpio.h:109
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr533x_ll_gpio.h:168
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1244
_ll_gpio_init::mode
uint32_t mode
Definition: gr533x_ll_gpio.h:81
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr533x_ll_gpio.h:169
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr533x_ll_gpio.h:396
LL_GPIO_INPUT_TYPE_CMOS
#define LL_GPIO_INPUT_TYPE_CMOS
Definition: gr533x_ll_gpio.h:200
LL_GPIO_STRENGTH_DS0_MASK
#define LL_GPIO_STRENGTH_DS0_MASK
Definition: gr533x_ll_gpio.h:138
_ll_gpio_init::pull
uint32_t pull
Definition: gr533x_ll_gpio.h:86
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1485
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1140
ll_gpio_set_pin_strength
__STATIC_INLINE void ll_gpio_set_pin_strength(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t strength)
Configure gpio output drive strength for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:796
LL_GPIO_MODE_INPUT_POS
#define LL_GPIO_MODE_INPUT_POS
Definition: gr533x_ll_gpio.h:136
POL_SET
#define POL_SET
ll_gpio_set_pin_input_type
__STATIC_INLINE void ll_gpio_set_pin_input_type(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t type)
Set several pins input type on dedicated port.
Definition: gr533x_ll_gpio.h:478
LL_GPIO_STRENGTH_DS0_POS
#define LL_GPIO_STRENGTH_DS0_POS
Definition: gr533x_ll_gpio.h:140
ll_gpio_set_pin_mux
__STATIC_INLINE void ll_gpio_set_pin_mux(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr533x_ll_gpio.h:621
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1415
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr533x_ll_gpio.h:550
ll_gpio_get_pin_mux
__STATIC_INLINE uint32_t ll_gpio_get_pin_mux(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 15 for a dedicated port.
Definition: gr533x_ll_gpio.h:668
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr533x_ll_gpio.h:1551