gr533x_hal_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_hal_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_DMA DMA
47 * @brief DMA HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_HAL_DMA_H__
53 #define __GR533x_HAL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_ll_dma.h"
61 #include "gr533x_hal_def.h"
62 #include <stdbool.h>
63
64 /* Exported types ------------------------------------------------------------*/
65 /** @addtogroup HAL_DMA_ENUMERATIONS Enumerations
66 * @{
67 */
68
69 /** @defgroup HAL_DMA_state HAL DMA state
70 * @{
71 */
72
73 /**
74 * @brief HAL DMA State Enumerations definition
75 */
76 typedef enum
77 {
78 HAL_DMA_STATE_RESET = 0x00U, /**< DMA not yet initialized or disabled */
79 HAL_DMA_STATE_READY = 0x01U, /**< DMA process success and ready for use */
80 HAL_DMA_STATE_BUSY = 0x02U, /**< DMA process is ongoing */
81 HAL_DMA_STATE_TIMEOUT = 0x03U, /**< DMA timeout state */
82 HAL_DMA_STATE_ERROR = 0x04U, /**< DMA error state */
83 } hal_dma_state_t;
84 /** @} */
85
86 /** @defgroup HAL_DMA_channel HAL DMA channel
87 * @{
88 */
89
90 /**
91 * @brief HAL DMA Channel Enumerations definition
92 */
93 typedef enum
94 {
95 DMA_Channel0 = 0U, /**< Channel 0 */
96 DMA_Channel1 = 1U, /**< Channel 1 */
97 DMA_Channel2 = 2U, /**< Channel 2 */
98 DMA_Channel3 = 3U, /**< Channel 3 */
99 DMA_Channel4 = 4U, /**< Channel 4 */
100 DMA_Channel_NUM_MAX /**< Only for check parameter, not used as input parameters. */
101 } dma_channel_t;
102 /** @} */
103
104 /** @defgroup HAL_DMA_callback_ID HAL DMA callback ID
105 * @{
106 */
107
108 /**
109 * @brief HAL DMA Callback ID Enumerations definition
110 */
111 typedef enum
112 {
113 HAL_DMA_XFER_TFR_CB_ID = 0x00, /**< Full transfer */
114 HAL_DMA_XFER_BLK_CB_ID = 0x01, /**< Block transfer */
115 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /**< Error */
116 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /**< Abort */
117 HAL_DMA_XFER_ALL_CB_ID = 0x04 /**< All */
118 } hal_dma_callback_id_t;
119 /** @} */
120
121 /** @} */
122
123
124 /** @addtogroup HAL_DMA_STRUCTURES Structures
125 * @{
126 */
127
128 /**
129 * @brief DMA LOCK Structure definition
130 */
131 typedef struct _dma_lock_config
132 {
133 uint32_t channel_lock_en; /**< Specifies the dma channel lock enable.
134 This parameter can be a value of @ref DMA_CHANNEL_LOCK_EN */
135
136 uint32_t channel_lock_level; /**< Specifies the dma channel lock level.
137 This parameter can be a value of @ref DMA_CHANNEL_LOCK_LEVEL */
138
139 uint32_t bus_lock_en; /**< Specifies the dma bus lock enable.
140 This parameter can be a value of @ref DMA_BUS_LOCK_EN */
141
142 uint32_t bus_lock_level; /**< Specifies the dma bus lock level.
143 This parameter can be a value of @ref DMA_BUS_LOCK_LEVEL */
144 } dma_lock_config;
145
146 /** @} */
147
148
149 /** @addtogroup HAL_DMA_STRUCTURES Structures
150 * @{
151 */
152
153 /**
154 * @brief DMA Configuration Structure definition
155 */
156 typedef struct _dma_init
157 {
158 uint32_t src_request; /**< Specifies the source request selected for the specified channel.
159 This parameter can be a value of @ref DMA_request */
160
161 uint32_t dst_request; /**< Specifies the destination request selected for the specified channel.
162 This parameter can be a value of @ref DMA_request */
163
164 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
165 from memory to memory or from peripheral to memory.
166 This parameter can be a value of @ref DMA_Data_transfer_direction */
167
168 uint32_t src_increment; /**< Specifies whether the srouce address register should be incremented or decrement or not.
169 This parameter can be a value of @ref DMA_Source_incremented_mode */
170
171 uint32_t dst_increment; /**< Specifies whether the destination address register should be incremented or decrement or not.
172 This parameter can be a value of @ref DMA_Destination_incremented_mode */
173
174 uint32_t src_data_alignment; /**< Specifies the source data width.
175 This parameter can be a value of @ref DMA_Source_data_size */
176
177 uint32_t dst_data_alignment; /**< Specifies the destination data width.
178 This parameter can be a value of @ref DMA_Destination_data_size */
179
180 uint32_t priority; /**< Specifies the software priority for the DMA Channel.
181 This parameter can be a value of @ref DMA_Priority_level */
182 } dma_init_t;
183
184 /** @} */
185
186 /** @addtogroup DMA_handle DMA handle
187 * @{
188 */
189
190 /**
191 * @brief DMA handle Structure definition
192 */
193 typedef struct _dma_handle
194 {
195 dma_regs_t *p_instance; /**< DMA registers base address */
196
197 dma_channel_t channel; /**< DMA Channel Number */
198
199 dma_init_t init; /**< DMA communication parameters */
200
201 hal_lock_t lock; /**< DMA locking object */
202
203 __IO hal_dma_state_t state; /**< DMA transfer state */
204
205 void *p_parent; /**< Parent object state */
206
207 void (* xfer_tfr_callback)(struct _dma_handle *p_dma); /**< DMA transfer complete callback */
208
209 void (* xfer_blk_callback)(struct _dma_handle *p_dma); /**< DMA block complete callback */
210
211 void (* xfer_error_callback)(struct _dma_handle *p_dma); /**< DMA transfer error callback */
212
213 void (* xfer_abort_callback)(struct _dma_handle *p_dma); /**< DMA transfer abort callback */
214
215 __IO uint32_t error_code; /**< DMA Error code */
216
217 uint32_t retention[5]; /**< DMA important register information. */
218 } dma_handle_t;
219
220 /** @} */
221
222 /**
223 * @defgroup HAL_DMA_MACRO Defines
224 * @{
225 */
226
227 /* Exported constants --------------------------------------------------------*/
228 /** @defgroup DMA_Exported_Constants DMA Exported Constants
229 * @{
230 */
231
232 /** @defgroup DMA_Error_Code DMA Error Code
233 * @{
234 */
235 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /**< No error */
236 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /**< Transfer error */
237 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /**< no ongoing transfer */
238 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /**< Timeout error */
239 #define HAL_DMA_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /**< Invalid parameters error */
240 /** @} */
241
242 /** @defgroup DMA_request DMA request definitions
243 * @{
244 */
245 /********************************* definition for DMA0 HS **************************************/
246 #define DMA0_REQUEST_CTE LL_DMA0_PERIPH_CTE /**< DMA CTE transmit request */
247 #define DMA0_REQUEST_PWM0 LL_DMA0_PERIPH_PWM0 /**< DMA PWM0 transmit request */
248 #define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
249 #define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX /**< DMA SPIM RX transmit request */
250 #define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX /**< DMA SPIS TX transmit request */
251 #define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX /**< DMA SPIS RX transmit request */
252 #define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX /**< DMA UART0 TX transmit request */
253 #define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX /**< DMA UART0 RX transmit request */
254 #define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX /**< DMA UART1 TX transmit request */
255 #define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX /**< DMA UART1 RX transmit request */
256 #define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC /**< DMA SNSADC transmit request */
257 #define DMA0_REQUEST_I2C0_TX LL_DMA0_PERIPH_I2C0_TX /**< DMA peripheral type is I2C0 TX */
258 #define DMA0_REQUEST_I2C0_RX LL_DMA0_PERIPH_I2C0_RX /**< DMA peripheral type is I2C0 RX */
259 #define DMA0_REQUEST_I2C1_TX LL_DMA0_PERIPH_I2C1_TX /**< DMA peripheral type is I2C1 TX */
260 #define DMA0_REQUEST_I2C1_RX LL_DMA0_PERIPH_I2C1_RX /**< DMA peripheral type is I2C1 RX */
261 #define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM /**< DMA is Memory transmit request */
262
263 /** @} */
264
265 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
266 * @{
267 */
268 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /**< Memory to memory direction */
269 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /**< Memory to peripheral direction */
270 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /**< Peripheral to memory direction */
271 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH /**< Peripheral to Peripheral direction */
272 /** @} */
273
274 /** @defgroup DMA_Source_incremented_mode DMA Source Incremented Mode
275 * @{
276 */
277 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT /**< Source increment mode */
278 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT /**< Source decrement mode */
279 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE /**< Source no change mode */
280 /** @} */
281
282 /** @defgroup DMA_Destination_incremented_mode DMA Destination Incremented Mode
283 * @{
284 */
285 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT /**< Destination increment mode */
286 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT /**< Destination decrement mode */
287 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE /**< Destination no change mode */
288 /** @} */
289
290 /** @defgroup DMA_Source_data_size DMA Source Data Size Alignment
291 * @{
292 */
293 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE /**< Source data alignment : Byte */
294 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD /**< Source data alignment : HalfWord */
295 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD /**< Source data alignment : Word */
296 /** @} */
297
298 /** @defgroup DMA_Destination_data_size DMA Destination Data Size Alignment
299 * @{
300 */
301 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE /**< Destination data alignment : Byte */
302 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD /**< Destination data alignment : HalfWord */
303 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD /**< Destination data alignment : Word */
304 /** @} */
305
306 /** @} */
307
308 /** @defgroup DMA_Priority_level DMA Priority Level
309 * @{
310 */
311 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0 /**< Priority level : Low */
312 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_1 /**< Priority level : Medium */
313 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_2 /**< Priority level : High */
314 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_3 /**< Priority level : Very High */
315 /** @} */
316
317 /** @defgroup DMA_CHANNEL_LOCK_EN DMA Channel Lock Enable
318 * @{
319 */
320 #define DMA_HAL_CHANNEL_LOCK_ENABLE LL_DMA_LOCK_CH_ENABLE /**< DMA Channel Lock Enable */
321 #define DMA_HAL_CHANNEL_LOCK_DISABLE LL_DMA_LOCK_CH_DISABLE /**< DMA Channel Lock Disable */
322 /** @} */
323
324 /** @defgroup DMA_CHANNEL_LOCK_LEVEL DMA Channel Lock Level
325 * @{
326 */
327 #define DMA_HAL_CHANNEL_LOCK_TFR LL_DMA_LOCK_CH_LEVEL_TFR /**< DMA Channel Lock Over complete DMA transfer */
328 #define DMA_HAL_CHANNEL_LOCK_BLK LL_DMA_LOCK_CH_LEVEL_BLK /**< DMA Channel Lock Over complete DMA block transfer */
329 #define DMA_HAL_CHANNEL_LOCK_TRANS LL_DMA_LOCK_CH_LEVEL_TRANS /**< DMA Channel Lock Over complete DMA transaction */
330 /** @} */
331
332 /** @defgroup DMA_BUS_LOCK_EN DMA Channel Lock Enable
333 * @{
334 */
335 #define DMA_HAL_BUS_LOCK_ENABLE LL_DMA_LOCK_BUS_ENABLE /**< DMA Bus Lock Enable */
336 #define DMA_HAL_BUS_LOCK_DISABLE LL_DMA_LOCK_BUS_DISABLE /**< DMA Bus Lock Disable */
337 /** @} */
338
339 /** @defgroup DMA_BUS_LOCK_LEVEL DMA Bus Lock Level
340 * @{
341 */
342 #define DMA_HAL_BUS_LOCK_TFR LL_DMA_LOCK_BUS_LEVEL_TFR /**< DMA Bus Lock Over complete DMA transfer */
343 #define DMA_HAL_BUS_LOCK_BLK LL_DMA_LOCK_BUS_LEVEL_BLK /**< DMA Bus Lock Over complete DMA block transfer */
344 #define DMA_HAL_BUS_LOCK_TRANS LL_DMA_LOCK_BUS_LEVEL_TRANS /**< DMA Bus Lock Over complete DMA transaction */
345 /** @} */
346
347
348 /* Private macros ------------------------------------------------------------*/
349 /** @defgroup DMA_Private_Macro DMA Private Macros
350 * @{
351 */
352
353 /** @brief Check if DMA instance is valid.
354 * @param __p_instance__ DMA instance.
355 * @retval SET (__p_instance__ is valid) or RESET (__p_instance__ is invalid)
356 */
357 #define IS_DMA_ALL_P_INSTANCE(__p_instance__) (((__p_instance__) == DMA0))
358
359 /** @brief Check if DMA channel instance is valid.
360 * @param __instance__ DMA channel instance.
361 * @retval SET (__instance__ is valid) or RESET (__instance__ is invalid)
362 */
363
364 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
365 ((__instance__) == DMA_Channel1) || \
366 ((__instance__) == DMA_Channel2) || \
367 ((__instance__) == DMA_Channel3) || \
368 ((__instance__) == DMA_Channel4))
369
370
371
372 /** @brief Check if DMA request is valid.
373 * @param __REQUEST__ DMA request.
374 * @retval SET (__REQUEST__ is valid) or RESET (__REQUEST__ is invalid)
375 */
376
377 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA0_REQUEST_SPIM_TX) || \
378 ((__REQUEST__) == DMA0_REQUEST_SPIM_RX) || \
379 ((__REQUEST__) == DMA0_REQUEST_SPIS_TX) || \
380 ((__REQUEST__) == DMA0_REQUEST_SPIS_RX) || \
381 ((__REQUEST__) == DMA0_REQUEST_UART0_TX) || \
382 ((__REQUEST__) == DMA0_REQUEST_UART0_RX) || \
383 ((__REQUEST__) == DMA0_REQUEST_UART1_TX) || \
384 ((__REQUEST__) == DMA0_REQUEST_UART1_RX) || \
385 ((__REQUEST__) == DMA0_REQUEST_SNSADC) || \
386 ((__REQUEST__) == DMA0_REQUEST_MEM) || \
387 ((__REQUEST__) == DMA0_REQUEST_I2C0_TX) || \
388 ((__REQUEST__) == DMA0_REQUEST_I2C0_RX) || \
389 ((__REQUEST__) == DMA0_REQUEST_I2C1_TX) || \
390 ((__REQUEST__) == DMA0_REQUEST_I2C1_RX))
391
392 /** @brief Check if DMA direction is valid.
393 * @param __DIRECTION__ DMA direction.
394 * @retval SET (__DIRECTION__ is valid) or RESET (__DIRECTION__ is invalid)
395 */
396 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
397 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
398 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
399 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
400
401 /** @brief Check if DMA buffer size is valid.
402 * @param __SIZE__ DMA buffer size.
403 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
404 */
405 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) <= 0xFFF))
406
407 /** @brief Check if DMA source address increment state is valid.
408 * @param __STATE__ DMA source address increment state.
409 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
410 */
411 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
412 ((__STATE__) == DMA_SRC_DECREMENT) || \
413 ((__STATE__) == DMA_SRC_NO_CHANGE))
414
415 /** @brief Check if DMA destination address increment state is valid.
416 * @param __STATE__ DMA destination address increment state.
417 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
418 */
419 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
420 ((__STATE__) == DMA_DST_DECREMENT) || \
421 ((__STATE__) == DMA_DST_NO_CHANGE))
422
423 /** @brief Check if DMA source data size is valid.
424 * @param __SIZE__ DMA source data size.
425 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
426 */
427 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
428 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
429 ((__SIZE__) == DMA_SDATAALIGN_WORD))
430
431 /** @brief Check if DMA destination data size is valid.
432 * @param __SIZE__ DMA destination data size.
433 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
434 */
435 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
436 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
437 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
438
439 /** @brief Check if DMA priority is valid.
440 * @param __PRIORITY__ DMA priority.
441 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid)
442 */
443 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
444 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
445 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
446 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
447
448 /** @} */
449
450 /** @} */
451
452
453 /* Exported functions --------------------------------------------------------*/
454 /** @addtogroup HAL_DMA_DRIVER_FUNCTIONS Functions
455 * @{
456 */
457
458 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
459 * @brief Initialization and de-initialization functions
460 *
461 @verbatim
462 ===============================================================================
463 ##### Initialization and de-initialization functions #####
464 ===============================================================================
465 [..]
466 This section provides functions allowing to initialize the DMA Channel source
467 and destination addresses, incrementation and data sizes, transfer direction,
468 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
469 [..]
470 The hal_dma_init() function follows the DMA configuration procedures as described in
471 reference manual.
472
473 @endverbatim
474 * @{
475 */
476
477 /**
478 ****************************************************************************************
479 * @brief Initialize the DMA according to the specified
480 * parameters in the dma_init_t and initialize the associated handle.
481 *
482 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
483 *
484 * @retval ::HAL_OK: Operation is OK.
485 * @retval ::HAL_ERROR: Parameter error or operation not supported.
486 * @retval ::HAL_BUSY: Driver is busy.
487 * @retval ::HAL_TIMEOUT: Timeout occurred.
488 ****************************************************************************************
489 */
490 hal_status_t hal_dma_init(dma_handle_t *p_dma);
491
492 /**
493 ****************************************************************************************
494 * @brief De-initialize the DMA peripheral.
495 *
496 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
497 *
498 * @retval ::HAL_OK: Operation is OK.
499 * @retval ::HAL_ERROR: Parameter error or operation not supported.
500 * @retval ::HAL_BUSY: Driver is busy.
501 * @retval ::HAL_TIMEOUT: Timeout occurred.
502 ****************************************************************************************
503 */
504 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
505
506 /** @} */
507
508
509 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
510 * @brief Input and Output operation functions
511 *
512 @verbatim
513 ===============================================================================
514 ##### IO operation functions #####
515 ===============================================================================
516 [..] This section provides functions allowing to:
517 (+) Configure the source, destination address and data length and Start DMA transfer
518 (+) Configure the source, destination address and data length and
519 Start DMA transfer with interrupt
520 (+) Abort DMA transfer
521 (+) Poll for transfer complete
522 (+) Handle DMA interrupt request
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 ****************************************************************************************
530 * @brief Start the DMA Transfer.
531 *
532 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
533 * @param[in] src_address: The source memory Buffer address
534 * @param[in] dst_address: The destination memory Buffer address
535 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
536 *
537 * @retval ::HAL_OK: Operation is OK.
538 * @retval ::HAL_ERROR: Parameter error or operation not supported.
539 * @retval ::HAL_BUSY: Driver is busy.
540 * @retval ::HAL_TIMEOUT: Timeout occurred.
541 ****************************************************************************************
542 */
543 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
544
545 /**
546 ****************************************************************************************
547 * @brief Start the DMA Transfer whit channel lock and bus lock.
548 *
549 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
550 * @param[in] src_address: The source memory Buffer address
551 * @param[in] dst_address: The destination memory Buffer address
552 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
553 * @param[in] lock_config: The Config of DMA channel and bus lock.
554 *
555 * @retval ::HAL_OK: Operation is OK.
556 * @retval ::HAL_ERROR: Parameter error or operation not supported.
557 * @retval ::HAL_BUSY: Driver is busy.
558 * @retval ::HAL_TIMEOUT: Timeout occurred.
559 ****************************************************************************************
560 */
561 hal_status_t hal_dma_start_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config);
562
563 /**
564 ****************************************************************************************
565 * @brief Start the DMA Transfer with interrupt enabled & Channel Diabled.
566 *
567 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
568 * @param[in] src_address: The source memory Buffer address
569 * @param[in] dst_address: The destination memory Buffer address
570 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
571 *
572 * @retval ::HAL_OK: Operation is OK.
573 * @retval ::HAL_ERROR: Parameter error or operation not supported.
574 * @retval ::HAL_BUSY: Driver is busy.
575 * @retval ::HAL_TIMEOUT: Timeout occurred.
576 ****************************************************************************************
577 */
578 hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
579
580 /**
581 ****************************************************************************************
582 * @brief Start the DMA Transfer with interrupt enabled & Channel Enabled.
583 *
584 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
585 * @param[in] src_address: The source memory Buffer address
586 * @param[in] dst_address: The destination memory Buffer address
587 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
588 *
589 * @retval ::HAL_OK: Operation is OK.
590 * @retval ::HAL_ERROR: Parameter error or operation not supported.
591 * @retval ::HAL_BUSY: Driver is busy.
592 * @retval ::HAL_TIMEOUT: Timeout occurred.
593 ****************************************************************************************
594 */
595 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
596
597 /**
598 ****************************************************************************************
599 * @brief Start the DMA Transfer with interrupt enabled、channel lock and bus lock.
600 *
601 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
602 * @param[in] src_address: The source memory Buffer address
603 * @param[in] dst_address: The destination memory Buffer address
604 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
605 * @param[in] lock_config: The Config of DMA channel and bus lock.
606 *
607 * @retval ::HAL_OK: Operation is OK.
608 * @retval ::HAL_ERROR: Parameter error or operation not supported.
609 * @retval ::HAL_BUSY: Driver is busy.
610 * @retval ::HAL_TIMEOUT: Timeout occurred.
611 ****************************************************************************************
612 */
613 hal_status_t hal_dma_start_it_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config);
614
615 /**
616 ****************************************************************************************
617 * @brief Abort the DMA Transfer.
618 *
619 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
620 *
621 * @retval ::HAL_OK: Operation is OK.
622 * @retval ::HAL_ERROR: Parameter error or operation not supported.
623 * @retval ::HAL_BUSY: Driver is busy.
624 * @retval ::HAL_TIMEOUT: Timeout occurred.
625 ****************************************************************************************
626 */
627 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
628
629 /**
630 ****************************************************************************************
631 * @brief Aborts the DMA Transfer in Interrupt mode.
632 *
633 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
634 *
635 * @retval ::HAL_OK: Operation is OK.
636 * @retval ::HAL_ERROR: Parameter error or operation not supported.
637 * @retval ::HAL_BUSY: Driver is busy.
638 * @retval ::HAL_TIMEOUT: Timeout occurred.
639 ****************************************************************************************
640 */
641 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
642
643 /**
644 ****************************************************************************************
645 * @brief Polling for transfer complete.
646 *
647 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
648 * @param[in] timeout: Timeout duration.
649 *
650 * @retval ::HAL_OK: Operation is OK.
651 * @retval ::HAL_ERROR: Parameter error or operation not supported.
652 * @retval ::HAL_BUSY: Driver is busy.
653 * @retval ::HAL_TIMEOUT: Timeout occurred.
654 ****************************************************************************************
655 */
656 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
657
658 /** @} */
659
660 /** @addtogroup DMA_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
661 * @brief IRQ Handler and Callbacks functions
662 * @{
663 */
664
665 /**
666 ****************************************************************************************
667 * @brief Handle DMA interrupt request.
668 *
669 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
670 ****************************************************************************************
671 */
672 void hal_dma_irq_handler(dma_handle_t *p_dma);
673
674 /**
675 ****************************************************************************************
676 * @brief Register callbacks
677 *
678 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
679 * @param[in] id: User Callback identifer. This parameter can be one of the following values:
680 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
681 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
682 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
683 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
684 * @param[in] callback: Pointer to private callbacsk function which has pointer to a dma_handle_t structure as parameter.
685 *
686 * @retval ::HAL_OK: Operation is OK.
687 * @retval ::HAL_ERROR: Parameter error or operation not supported.
688 * @retval ::HAL_BUSY: Driver is busy.
689 * @retval ::HAL_TIMEOUT: Timeout occurred.
690 ****************************************************************************************
691 */
692 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void (* callback)( dma_handle_t * p_dma));
693
694 /**
695 ****************************************************************************************
696 * @brief UnRegister callbacks
697 *
698 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
699 * @param[in] id: User Callback identifer. This parameter can be a combiantion of the following values:
700 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
701 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
702 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
703 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
704 * @arg @ref HAL_DMA_XFER_ALL_CB_ID
705 *
706 * @retval ::HAL_OK: Operation is OK.
707 * @retval ::HAL_ERROR: Parameter error or operation not supported.
708 * @retval ::HAL_BUSY: Driver is busy.
709 * @retval ::HAL_TIMEOUT: Timeout occurred.
710 ****************************************************************************************
711 */
712 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
713
714 /** @} */
715
716 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
717 * @brief Peripheral State and Errors functions
718 *
719 @verbatim
720 ===============================================================================
721 ##### Peripheral State and Errors functions #####
722 ===============================================================================
723 [..]
724 This subsection provides functions allowing to
725 (+) Check the DMA state
726 (+) Get error code
727
728 @endverbatim
729 * @{
730 */
731
732 /**
733 ****************************************************************************************
734 * @brief Return the DMA hande state.
735 *
736 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
737 *
738 * @retval ::HAL_DMA_STATE_RESET: DMA not yet initialized or disabled.
739 * @retval ::HAL_DMA_STATE_READY: DMA process succeeded and ready for use.
740 * @retval ::HAL_DMA_STATE_BUSY: DMA process is ongoing.
741 * @retval ::HAL_DMA_STATE_TIMEOUT: DMA timeout state.
742 * @retval ::HAL_DMA_STATE_ERROR: DMA error state.
743 ****************************************************************************************
744 */
745 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
746
747 /**
748 ****************************************************************************************
749 * @brief Return the DMA error code.
750 *
751 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
752 *
753 * @return DMA Error Code
754 ****************************************************************************************
755 */
756 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
757
758 /**
759 ****************************************************************************************
760 * @brief Suspend some registers related to DMA configuration before sleep.
761 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
762 * information for the specified DMA module.
763 * @retval ::HAL_OK: Operation is OK.
764 * @retval ::HAL_ERROR: Parameter error or operation not supported.
765 * @retval ::HAL_BUSY: Driver is busy.
766 * @retval ::HAL_TIMEOUT: Timeout occurred.
767 ****************************************************************************************
768 */
769 hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma);
770
771 /**
772 ****************************************************************************************
773 * @brief Restore some registers related to DMA configuration after sleep.
774 * This function must be used in conjunction with the hal_dma_resume_reg().
775 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
776 * information for the specified DMA module.
777 * @retval ::HAL_OK: Operation is OK.
778 * @retval ::HAL_ERROR: Parameter error or operation not supported.
779 * @retval ::HAL_BUSY: Driver is busy.
780 * @retval ::HAL_TIMEOUT: Timeout occurred.
781 ****************************************************************************************
782 */
783 hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma);
784
785 /**
786 ****************************************************************************************
787 * @brief set the flag if DMAn has been used before sleep
788 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
789 * information for the specified DMA module.
790 * @retval ::None
791 ****************************************************************************************
792 */
793 void dma_set_renew_flag(dma_handle_t *p_dma);
794
795 /**
796 ****************************************************************************************
797 * @brief resume dma regs before using if just waked up from sleep /only need to clear sleep_flag
798 * if on initial or deinitial state.
799 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
800 * information for the specified DMA module.
801 * @param[in] init_flag: true: use in init function or deinit function
802 * fault: not use in init function or deinit function
803 * @retval ::None
804 ****************************************************************************************
805 */
806 void dma_resume_before_using(dma_handle_t *p_dma, bool init_flag);
807
808 /**
809 ****************************************************************************************
810 * @brief Suspend the register of the specified DMA channel.
811 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
812 * information for the specified DMA module.
813 * @param[in] channel: dma channel,can be one of the values of dma_channel_t.
814 * @retval ::None
815 ****************************************************************************************
816 */
817 void hal_dma_suspend_channel(dma_handle_t *p_dma, uint32_t channel);
818
819 /**
820 ****************************************************************************************
821 * @brief Resume the register of the specified DMA channel.
822 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
823 * information for the specified DMA module.
824 * @param[in] channel: dma channel,can be one of the values of dma_channel_t.
825 * @retval ::None
826 ****************************************************************************************
827 */
828 void hal_dma_resume_channel(dma_handle_t *p_dma, uint32_t channel);
829
830 /** @} */
831
832 /** @} */
833
834 #ifdef __cplusplus
835 }
836 #endif
837
838 #endif /* __GR533x_HAL_DMA_H__*/
839
840 /** @} */
841
842 /** @} */
843
844 /** @} */
DMA_Channel4
@ DMA_Channel4
Definition: gr533x_hal_dma.h:99
HAL_DMA_XFER_TFR_CB_ID
@ HAL_DMA_XFER_TFR_CB_ID
Definition: gr533x_hal_dma.h:113
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr533x_hal_def.h:81
_dma_handle::p_instance
dma_regs_t * p_instance
Definition: gr533x_hal_dma.h:195
hal_dma_get_error
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA_Channel1
@ DMA_Channel1
Definition: gr533x_hal_dma.h:96
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition: gr533x_hal_dma.h:81
_dma_init
DMA Configuration Structure definition.
Definition: gr533x_hal_dma.h:157
dma_init_t
struct _dma_init dma_init_t
DMA Configuration Structure definition.
_dma_handle::error_code
__IO uint32_t error_code
Definition: gr533x_hal_dma.h:215
DMA_Channel0
@ DMA_Channel0
Definition: gr533x_hal_dma.h:95
dma_handle_t
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
hal_dma_state_t
HAL DMA State Enumerations definition.
Definition: gr533x_hal_dma.h:77
hal_dma_start_it
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Enabled.
hal_dma_abort_it
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: gr533x_hal_dma.h:79
_dma_init::dst_increment
uint32_t dst_increment
Definition: gr533x_hal_dma.h:171
_dma_handle::init
dma_init_t init
Definition: gr533x_hal_dma.h:199
gr533x_ll_dma.h
Header file containing functions prototypes of DMA LL library.
hal_dma_start_lock
hal_status_t hal_dma_start_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer whit channel lock and bus lock.
_dma_lock_config::channel_lock_en
uint32_t channel_lock_en
Definition: gr533x_hal_dma.h:133
DMA_Channel2
@ DMA_Channel2
Definition: gr533x_hal_dma.h:97
hal_dma_irq_handler
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
_dma_handle::xfer_blk_callback
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
Definition: gr533x_hal_dma.h:209
hal_dma_suspend_channel
void hal_dma_suspend_channel(dma_handle_t *p_dma, uint32_t channel)
Suspend the register of the specified DMA channel.
hal_dma_suspend_reg
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
_dma_handle::retention
uint32_t retention[5]
Definition: gr533x_hal_dma.h:217
_dma_init::priority
uint32_t priority
Definition: gr533x_hal_dma.h:180
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: gr533x_hal_dma.h:116
hal_dma_register_callback
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: gr533x_hal_dma.h:117
_dma_init::dst_request
uint32_t dst_request
Definition: gr533x_hal_dma.h:161
hal_dma_poll_for_transfer
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_dma_start
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
hal_dma_resume_reg
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep. This function must be used in conjun...
_dma_handle::state
__IO hal_dma_state_t state
Definition: gr533x_hal_dma.h:203
_dma_lock_config::bus_lock_en
uint32_t bus_lock_en
Definition: gr533x_hal_dma.h:139
hal_dma_init
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
_dma_handle::xfer_error_callback
void(* xfer_error_callback)(struct _dma_handle *p_dma)
Definition: gr533x_hal_dma.h:211
HAL_DMA_XFER_BLK_CB_ID
@ HAL_DMA_XFER_BLK_CB_ID
Definition: gr533x_hal_dma.h:114
dma_set_renew_flag
void dma_set_renew_flag(dma_handle_t *p_dma)
set the flag if DMAn has been used before sleep
hal_dma_start_it_dc
hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Diabled.
hal_dma_callback_id_t
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
Definition: gr533x_hal_dma.h:112
DMA_Channel3
@ DMA_Channel3
Definition: gr533x_hal_dma.h:98
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: gr533x_hal_dma.h:82
_dma_handle::xfer_tfr_callback
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
Definition: gr533x_hal_dma.h:207
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: gr533x_hal_dma.h:80
_dma_handle::xfer_abort_callback
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
Definition: gr533x_hal_dma.h:213
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr533x_hal_def.h:70
_dma_init::direction
uint32_t direction
Definition: gr533x_hal_dma.h:164
_dma_lock_config::channel_lock_level
uint32_t channel_lock_level
Definition: gr533x_hal_dma.h:136
hal_dma_get_state
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
DMA_Channel_NUM_MAX
@ DMA_Channel_NUM_MAX
Definition: gr533x_hal_dma.h:100
hal_dma_unregister_callback
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
_dma_handle::channel
dma_channel_t channel
Definition: gr533x_hal_dma.h:197
_dma_init::dst_data_alignment
uint32_t dst_data_alignment
Definition: gr533x_hal_dma.h:177
_dma_handle::lock
hal_lock_t lock
Definition: gr533x_hal_dma.h:201
dma_lock_config
struct _dma_lock_config dma_lock_config
DMA LOCK Structure definition.
hal_dma_resume_channel
void hal_dma_resume_channel(dma_handle_t *p_dma, uint32_t channel)
Resume the register of the specified DMA channel.
_dma_lock_config
DMA LOCK Structure definition.
Definition: gr533x_hal_dma.h:132
_dma_handle::p_parent
void * p_parent
Definition: gr533x_hal_dma.h:205
hal_dma_abort
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: gr533x_hal_dma.h:115
dma_resume_before_using
void dma_resume_before_using(dma_handle_t *p_dma, bool init_flag)
resume dma regs before using if just waked up from sleep /only need to clear sleep_flag if on initial...
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: gr533x_hal_dma.h:78
_dma_init::src_request
uint32_t src_request
Definition: gr533x_hal_dma.h:158
gr533x_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
_dma_lock_config::bus_lock_level
uint32_t bus_lock_level
Definition: gr533x_hal_dma.h:142
_dma_init::src_data_alignment
uint32_t src_data_alignment
Definition: gr533x_hal_dma.h:174
_dma_handle
DMA handle Structure definition.
Definition: gr533x_hal_dma.h:194
hal_dma_deinit
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr533x_hal_dma.h:94
_dma_init::src_increment
uint32_t src_increment
Definition: gr533x_hal_dma.h:168
hal_dma_start_it_lock
hal_status_t hal_dma_start_it_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer with interrupt enabled、channel lock and bus lock.