gr533x_ll_adc.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_adc.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of ADC LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_ADC ADC
47 * @brief ADC LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_ADC_H__
53 #define __GR533X_LL_ADC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined(AON_CTL)
63
64 /** @defgroup ADC_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup ADC_LL_ES_INIT ADC Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL ADC init Structure definition
75 */
76 typedef struct _ll_adc_init
77 {
78 uint32_t channel_p; /**< Specifies the input source to ADC channel P.
79 This parameter can be any value of @ref ADC_LL_EC_INPUT_SRC.
80
81 This parament can be modified afterwards using unitary function @ref ll_adc_set_channelp(). */
82
83 uint32_t channel_n; /**< Specifies the input source to ADC channel N.
84 This parameter can be any value of @ref ADC_LL_EC_INPUT_SRC.
85
86 This parament can be modified afterwards using unitary function @ref ll_adc_set_channeln(). */
87
88 uint32_t input_mode; /**< Specifies the operation mode for the ADC sample.
89 This parameter can be a value of @ref ADC_LL_EC_INPUT_MODE.
90
91 This parament can be modified afterwards using unitary function @ref ll_adc_set_input_mode(). */
92
93 uint32_t ref_source; /**< Specifies the source of the ADC reference.
94 This parameter can be a value of @ref ADC_LL_EC_REFERENCE_SRC.
95
96 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref().*/
97
98 uint32_t ref_value; /*!< Specifies the value of the ADC buffered reference.
99 This parameter can be a value of @ref ADC_LL_EC_REFERENCE.
100
101 This parament can be modified afterwards using unitary function @ref ll_adc_set_ref_value().*/
102
103 uint32_t clock; /**< Specifies the clock of ADC.
104 This parameter can be a value of @ref ADC_LL_EC_CLK.
105
106 This parament can be modified afterwards using unitary function @ref ll_adc_set_clock().*/
107
108 } ll_adc_init_t;
109
110 /** @} */
111
112 /** @} */
113
114 /**
115 * @defgroup ADC_LL_MACRO Defines
116 * @{
117 */
118
119 /* Exported constants --------------------------------------------------------*/
120 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
121 * @{
122 */
123
124 /** @defgroup ADC_LL_EC_CLK ADC CLOCK
125 * @{
126 */
127 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16 MHz */
128 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8 MHz */
129 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4 MHz */
130 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 1 MHz */
131 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 16KHz */
132 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 8KHz */
133 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< ADC Clock = 4KHz */
134 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos) /**< No ADC Clock*/
135
136 /** @} */
137
138 /** @defgroup ADC_LL_EC_REFERENCE ADC Buffered Internal Reference Value
139 * @{
140 */
141 #define LL_ADC_REF_VALUE_0P8 (0x3UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 0.85 V */
142 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.28 V */
143 #define LL_ADC_REF_VALUE_1P6 (0xAUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 1.60 V */
144 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos) /**< Reference = 2.00 V */
145 /** @} */
146
147 /** @defgroup ADC_LL_EC_INPUT_MODE ADC Input Mode
148 * @{
149 */
150 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos) /**< Single ended mode */
151 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL) /**< Differential mode */
152 /** @} */
153
154 /** @defgroup ADC_LL_EC_INPUT_SRC ADC Input Source
155 * @{
156 */
157 #define LL_ADC_INPUT_SRC_IO0 (0UL) /**< Select MSIO0 as input */
158 #define LL_ADC_INPUT_SRC_IO1 (1UL) /**< Select MSIO1 as input */
159 #define LL_ADC_INPUT_SRC_IO2 (2UL) /**< Select MSIO2 as input */
160 #define LL_ADC_INPUT_SRC_IO3 (3UL) /**< Select MSIO3 as input */
161 #define LL_ADC_INPUT_SRC_IO4 (4UL) /**< Select MSIO4 as input */
162 #define LL_ADC_INPUT_SRC_IO5 (5UL) /**< Select MSIO5 as input */
163 #define LL_ADC_INPUT_SRC_IO6 (6UL) /**< Select MSIO6 as input */
164 #define LL_ADC_INPUT_SRC_IO7 (7UL) /**< Select MSIO7 as input */
165 #define LL_ADC_INPUT_SRC_TMP (13UL) /**< Select temperature as input */
166 #define LL_ADC_INPUT_SRC_BAT (14UL) /**< Select Vbattery as input */
167 #define LL_ADC_INPUT_SRC_REF (15UL) /**< Select reference as input */
168
169 /** @} */
170
171 /** @defgroup ADC_LL_EC_REFERENCE_SRC ADC Reference Source
172 * @{
173 */
174 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL) /**< Select buffered internal reference as reference */
175 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO0 as reference */
176 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO1 as reference */
177 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO2 as reference */
178 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos) /**< Select MSIO3 as reference */
179
180 /** @} */
181
182 /** @} */
183
184 /* Exported macro ------------------------------------------------------------*/
185 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
186 * @{
187 */
188
189 /** @defgroup ADC_LL_EM_WRITE_READ Common Write and read registers Macros
190 * @{
191 */
192
193 /**
194 * @brief Write a value in ADC register
195 * @param __instance__ ADC instance
196 * @param __REG__ Register to be written
197 * @param __VALUE__ Value to be written in the register
198 * @retval None
199 */
200 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
201
202 /**
203 * @brief Read a value in ADC register
204 * @param __instance__ ADC instance
205 * @param __REG__ Register to be read
206 * @retval Register value
207 */
208 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
209
210 /** @} */
211
212 /** @} */
213
214 /* Private types -------------------------------------------------------------*/
215 /* Private variables ---------------------------------------------------------*/
216 /* Private constants ---------------------------------------------------------*/
217 /* Private macros ------------------------------------------------------------*/
218 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
219 * @{
220 */
221
222 /** @defgroup ADC_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
223 * @{
224 */
225
226 /**
227 * @brief LL ADC InitStrcut default configuartion
228 */
229
230 #define LL_ADC_DEFAULT_CONFIG \
231 { \
232 .channel_p = LL_ADC_INPUT_SRC_IO0, \
233 .channel_n = LL_ADC_INPUT_SRC_IO1, \
234 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
235 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
236 .ref_value = LL_ADC_REF_VALUE_1P2, \
237 .clock = LL_ADC_CLK_16M \
238 }
239
240 /** @} */
241
242 /** @} */
243
244 /** @} */
245
246 /* Exported functions --------------------------------------------------------*/
247 /** @defgroup ADC_LL_DRIVER_FUNCTIONS Functions
248 * @{
249 */
250
251 /** @defgroup ADC_LL_EF_Configuration Basic Configuration
252 * @{
253 */
254
255 /**
256 * @brief Enable ADC module.
257 *
258 * Register|BitsName
259 * --------|--------
260 * SNSADC_CFG | REG4
261 *
262 * @retval None
263 */
264 __STATIC_INLINE void ll_adc_enable(void)
265 {
266 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
267 }
268
269 /**
270 * @brief Disable ADC module.
271 *
272 * Register|BitsName
273 * --------|--------
274 * SNSADC_CFG | REG4
275 *
276 * @retval None
277 */
278 __STATIC_INLINE void ll_adc_disable(void)
279 {
280 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
281 }
282
283 /**
284 * @brief Check if ADC module is enabled.
285 *
286 * Register|BitsName
287 * --------|--------
288 * SNSADC_CFG | REG4
289 *
290 * @retval State of bit (1 or 0).
291 */
292 __STATIC_INLINE uint32_t ll_adc_is_enabled(void)
293 {
294 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
295 }
296
297 /**
298 * @brief Disable ADC clock.
299 *
300 * Register|BitsName
301 * --------|--------
302 * MSIO_PAD_CFG_1 | ADC_CLK_EN
303 *
304 * @retval None
305 */
306 __STATIC_INLINE void ll_adc_disable_clock(void)
307 {
308 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
309 }
310
311 /**
312 * @brief Check if ADC clock is enabled.
313 *
314 * Register|BitsName
315 * --------|--------
316 * MSIO_PAD_CFG_1 | ADC_CLK_EN
317 *
318 * @retval State of bit (1 or 0).
319 */
320 __STATIC_INLINE uint32_t ll_adc_is_enabled_clock(void)
321 {
322 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
323 }
324
325 /**
326 * @brief Set ADC clock source.
327 *
328 * Register|BitsName
329 * --------|--------
330 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
331 *
332 * @param clk This parameter can be one of the following values:
333 * @arg @ref LL_ADC_CLK_16M
334 * @arg @ref LL_ADC_CLK_8M
335 * @arg @ref LL_ADC_CLK_4M
336 * @arg @ref LL_ADC_CLK_1M
337 * @arg @ref LL_ADC_CLK_16K
338 * @arg @ref LL_ADC_CLK_8K
339 * @arg @ref LL_ADC_CLK_4K
340 * @arg @ref LL_ADC_CLK_NONE
341 * @retval None
342 */
343 __STATIC_INLINE void ll_adc_set_clock(uint32_t clk)
344 {
345 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
346 }
347
348 /**
349 * @brief Return source for ADC clock.
350 *
351 * Register|BitsName
352 * --------|--------
353 * MSIO_PAD_CFG_1 | ADC_CLK_SEL
354 *
355 * @retval Returned value can be one of the following values:
356 * @arg @ref LL_ADC_CLK_16M
357 * @arg @ref LL_ADC_CLK_8M
358 * @arg @ref LL_ADC_CLK_4M
359 * @arg @ref LL_ADC_CLK_1M
360 * @arg @ref LL_ADC_CLK_16K
361 * @arg @ref LL_ADC_CLK_8K
362 * @arg @ref LL_ADC_CLK_4K
363 * @arg @ref LL_ADC_CLK_NONE
364 */
365 __STATIC_INLINE uint32_t ll_adc_get_clock(void)
366 {
367 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
368 }
369
370 /**
371 * @brief Set ADC bias reference.
372 *
373 * Register|BitsName
374 * --------|--------
375 * SNSADC_CFG | REG1
376 *
377 * @param value This parameter can be one of the following values:
378 * @arg @ref LL_ADC_REF_VALUE_0P8
379 * @arg @ref LL_ADC_REF_VALUE_1P2
380 * @arg @ref LL_ADC_REF_VALUE_1P6
381 * @arg @ref LL_ADC_REF_VALUE_2P0
382 * @retval None
383 */
384 __STATIC_INLINE void ll_adc_set_ref_value(uint32_t value)
385 {
386 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
387 }
388
389 /**
390 * @brief Return ADC bias reference.
391 *
392 * Register|BitsName
393 * --------|--------
394 * SNSADC_CFG | REG1
395 *
396 * @retval Returned value can be one of the following values:
397 * @arg @ref LL_ADC_REF_VALUE_0P8
398 * @arg @ref LL_ADC_REF_VALUE_1P2
399 * @arg @ref LL_ADC_REF_VALUE_1P6
400 * @arg @ref LL_ADC_REF_VALUE_2P0
401 */
402 __STATIC_INLINE uint32_t ll_adc_get_ref_value(void)
403 {
404 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
405 }
406
407 /**
408 * @brief Enable temperature sensor.
409 *
410 * Register|BitsName
411 * --------|--------
412 * SNSADC_CFG | REG2
413 *
414 * @retval None
415 */
416 __STATIC_INLINE void ll_adc_enable_temp(void)
417 {
418 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
419 }
420
421 /**
422 * @brief Disable temperature sensor.
423 *
424 * Register|BitsName
425 * --------|--------
426 * SNSADC_CFG | REG2
427 *
428 * @retval None
429 */
430 __STATIC_INLINE void ll_adc_disable_temp(void)
431 {
432 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
433 }
434
435 /**
436 * @brief Check if temperature sensor is enabled.
437 *
438 * Register|BitsName
439 * --------|--------
440 * SNSADC_CFG | REG2
441 *
442 * @retval State of bit (1 or 0).
443 */
444 __STATIC_INLINE uint32_t ll_adc_is_enabled_temp(void)
445 {
446 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
447 }
448
449 /**
450 * @brief Enable Vbattery sensor.
451 *
452 * Register|BitsName
453 * --------|--------
454 * SNSADC_CFG | REG2
455 *
456 * @retval None
457 */
458 __STATIC_INLINE void ll_adc_enable_vbat(void)
459 {
460 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
461 }
462
463 /**
464 * @brief Disable Vbattery sensor.
465 *
466 * Register|BitsName
467 * --------|--------
468 * SNSADC_CFG | REG2
469 *
470 * @retval None
471 */
472 __STATIC_INLINE void ll_adc_disable_vbat(void)
473 {
474 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
475 }
476
477 /**
478 * @brief Check if Vbattery sensor is enabled.
479 *
480 * Register|BitsName
481 * --------|--------
482 * SNSADC_CFG | REG2
483 *
484 * @retval State of bit (1 or 0).
485 */
486 __STATIC_INLINE uint32_t ll_adc_is_enabled_vbat(void)
487 {
488 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
489 }
490
491 /**
492 * @brief Set ADC input mode.
493 *
494 * Register|BitsName
495 * --------|--------
496 * SNSADC_CFG | REG2
497 *
498 * @param mode This parameter can be one of the following values:
499 * @arg @ref LL_ADC_INPUT_SINGLE
500 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
501 * @retval None
502 */
503 __STATIC_INLINE void ll_adc_set_input_mode(uint32_t mode)
504 {
505 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
506 }
507
508 /**
509 * @brief Return ADC input mode.
510 *
511 * Register|BitsName
512 * --------|--------
513 * SNSADC_CFG | REG2
514 *
515 * @retval Returned value can be one of the following values:
516 * @arg @ref LL_ADC_INPUT_SINGLE
517 * @arg @ref LL_ADC_INPUT_DIFFERENTIAL
518 */
519 __STATIC_INLINE uint32_t ll_adc_get_input_mode(void)
520 {
521 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk));
522 }
523
524 /**
525 * @brief Enable offset calibration.
526 * @note Enable offset calibration, used to swap inputs of comparator for offset
527 * calibration.
528 *
529 * Register|BitsName
530 * --------|--------
531 * SNSADC_CFG | REG2
532 *
533 * @retval None
534 */
535 __STATIC_INLINE void ll_adc_enable_ofs_cal(void)
536 {
537 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
538 }
539
540 /**
541 * @brief Disable offset calibration.
542 *
543 * Register|BitsName
544 * --------|--------
545 * SNSADC_CFG | REG2
546 *
547 * @retval None
548 */
549 __STATIC_INLINE void ll_adc_disable_ofs_cal(void)
550 {
551 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
552 }
553
554 /**
555 * @brief Check if offset calibration is enabled.
556 *
557 * Register|BitsName
558 * --------|--------
559 * SNSADC_CFG | REG2
560 *
561 * @retval State of bit (1 or 0).
562 */
563 __STATIC_INLINE uint32_t ll_adc_is_enabled_ofs_cal(void)
564 {
565 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
566 }
567
568 /**
569 * @brief Set dynamic rang of ADC.
570 * @note When higher input signal frequencies close to Nyquist rate, you should set 1.
571 *
572 * Register|BitsName
573 * --------|--------
574 * SNSADC_CFG | REG2
575 *
576 * @param rang This parameter can be a value between: 1 ~ 7
577 * @retval None
578 */
579 __STATIC_INLINE void ll_adc_set_dynamic_rang(uint32_t rang)
580 {
581 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
582 }
583
584 /**
585 * @brief Return ADC dynamic rang.
586 *
587 * Register|BitsName
588 * --------|--------
589 * SNSADC_CFG | REG2
590 *
591 * @retval Returned value can be a value between: 1 ~ 7
592 */
593 __STATIC_INLINE uint32_t ll_adc_get_dynamic_rang(void)
594 {
595 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
596 }
597
598 /**
599 * @brief Set source of ADC input channelP.
600 *
601 * Register|BitsName
602 * --------|--------
603 * SNSADC_CFG | REG3
604 *
605 * @param source This parameter can be one of the following values:
606 * @arg @ref LL_ADC_INPUT_SRC_IO0
607 * @arg @ref LL_ADC_INPUT_SRC_IO1
608 * @arg @ref LL_ADC_INPUT_SRC_IO2
609 * @arg @ref LL_ADC_INPUT_SRC_IO3
610 * @arg @ref LL_ADC_INPUT_SRC_IO4
611 * @arg @ref LL_ADC_INPUT_SRC_TMP
612 * @arg @ref LL_ADC_INPUT_SRC_BAT
613 * @retval None
614 */
615 __STATIC_INLINE void ll_adc_set_channelp(uint32_t source)
616 {
617 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
618 }
619
620 /**
621 * @brief Return source of ADC input channelP.
622 *
623 * Register|BitsName
624 * --------|--------
625 * SNSADC_CFG | REG3
626 *
627 * @retval Returned value can be one of the following values:
628 * @arg @ref LL_ADC_INPUT_SRC_IO0
629 * @arg @ref LL_ADC_INPUT_SRC_IO1
630 * @arg @ref LL_ADC_INPUT_SRC_IO2
631 * @arg @ref LL_ADC_INPUT_SRC_IO3
632 * @arg @ref LL_ADC_INPUT_SRC_IO4
633 * @arg @ref LL_ADC_INPUT_SRC_TMP
634 * @arg @ref LL_ADC_INPUT_SRC_BAT
635 */
636 __STATIC_INLINE uint32_t ll_adc_get_channelp(void)
637 {
638 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
639 }
640
641 /**
642 * @brief Set source of ADC input channelN.
643 *
644 * Register|BitsName
645 * --------|--------
646 * SNSADC_CFG | REG3
647 *
648 * @param source This parameter can be one of the following values:
649 * @arg @ref LL_ADC_INPUT_SRC_IO0
650 * @arg @ref LL_ADC_INPUT_SRC_IO1
651 * @arg @ref LL_ADC_INPUT_SRC_IO2
652 * @arg @ref LL_ADC_INPUT_SRC_IO3
653 * @arg @ref LL_ADC_INPUT_SRC_IO4
654 * @arg @ref LL_ADC_INPUT_SRC_TMP
655 * @arg @ref LL_ADC_INPUT_SRC_BAT
656 * @retval None
657 */
658 __STATIC_INLINE void ll_adc_set_channeln(uint32_t source)
659 {
660 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
661 }
662
663 /**
664 * @brief Return source of ADC input channelN.
665 *
666 * Register|BitsName
667 * --------|--------
668 * SNSADC_CFG | REG3
669 *
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_ADC_INPUT_SRC_IO0
672 * @arg @ref LL_ADC_INPUT_SRC_IO1
673 * @arg @ref LL_ADC_INPUT_SRC_IO2
674 * @arg @ref LL_ADC_INPUT_SRC_IO3
675 * @arg @ref LL_ADC_INPUT_SRC_IO4
676 * @arg @ref LL_ADC_INPUT_SRC_TMP
677 * @arg @ref LL_ADC_INPUT_SRC_BAT
678 */
679 __STATIC_INLINE uint32_t ll_adc_get_channeln(void)
680 {
681 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
682 }
683
684 /**
685 * @brief Enable ADC MAS_RST.
686 *
687 * Register|BitsName
688 * --------|--------
689 * SNSADC_CFG | REG4
690 *
691 * @retval None
692 */
693 __STATIC_INLINE void ll_adc_enable_mas_rst(void)
694 {
695 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
696 }
697
698 /**
699 * @brief Disable ADC MAS_RST.
700 *
701 * Register|BitsName
702 * --------|--------
703 * SNSADC_CFG | REG4
704 *
705 * @retval None
706 */
707 __STATIC_INLINE void ll_adc_disable_mas_rst(void)
708 {
709 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
710 }
711
712 /**
713 * @brief Check if ADC MAS_RST is enabled.
714 *
715 * Register|BitsName
716 * --------|--------
717 * SNSADC_CFG | REG4
718 *
719 * @retval State of bit (1 or 0).
720 */
721 __STATIC_INLINE uint32_t ll_adc_is_enabled_mas_rst(void)
722 {
723 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
724 }
725
726 /**
727 * @brief Set source of ADC reference.
728 *
729 * Register|BitsName
730 * --------|--------
731 * SNSADC_CFG | REG4
732 *
733 * @param source This parameter can be one of the following values:
734 * @arg @ref LL_ADC_REF_SRC_BUF_INT
735 * @arg @ref LL_ADC_REF_SRC_IO0
736 * @arg @ref LL_ADC_REF_SRC_IO1
737 * @arg @ref LL_ADC_REF_SRC_IO2
738 * @arg @ref LL_ADC_REF_SRC_IO3
739 * @retval None
740 */
741 __STATIC_INLINE void ll_adc_set_ref(uint32_t source)
742 {
743 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
744 }
745
746 /**
747 * @brief Return source of ADC reference.
748 *
749 * Register|BitsName
750 * --------|--------
751 * SNSADC_CFG | REG4
752 *
753 * @retval Returned value can be one of the following values:
754 * @arg @ref LL_ADC_REF_SRC_BUF_INT
755 * @arg @ref LL_ADC_REF_SRC_IO0
756 * @arg @ref LL_ADC_REF_SRC_IO1
757 * @arg @ref LL_ADC_REF_SRC_IO2
758 * @arg @ref LL_ADC_REF_SRC_IO3
759 */
760 __STATIC_INLINE uint32_t ll_adc_get_ref(void)
761 {
762 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
763 }
764
765 /**
766 * @brief Set current of ADC reference circuit.
767 * @note When samples at 100kbps, you should set 0.
768 * When samples at 1mbps, you should set 7.
769 *
770 * Register|BitsName
771 * --------|--------
772 * SNSADC_CFG | REG4
773 *
774 * @param source This parameter can be a value between: 0 ~ 7
775 * @retval None
776 */
777 __STATIC_INLINE void ll_adc_set_ref_current(uint32_t source)
778 {
779 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
780 }
781
782 /**
783 * @brief Return current of ADC reference circuit.
784 *
785 * Register|BitsName
786 * --------|--------
787 * SNSADC_CFG | REG4
788 *
789 * @retval Returned value can be a value between: 0 ~ 7
790 */
791 __STATIC_INLINE uint32_t ll_adc_get_ref_current(void)
792 {
793 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
794 }
795
796 /** @} */
797
798 /** @defgroup ADC_LL_EF_FIFO_Access FIFO Access
799 * @{
800 */
801
802 /**
803 * @brief Return samples value of ADC by reading FIFO.
804 * @note There are two value in the register, both of them is 16bits.
805 *
806 * Register|BitsName
807 * --------|--------
808 * SENSE_ADC_FIFO | SENSE_ADC_FIFO
809 *
810 * @retval Smaples value of input
811 */
812 __STATIC_INLINE uint32_t ll_adc_read_fifo(void)
813 {
814 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
815 }
816
817 /**
818 * @brief Set threshold of ADC FIFO.
819 *
820 * Register|BitsName
821 * --------|--------
822 * SENSE_FF_THRESH | SENSE_FF_THRESH
823 *
824 * @param thresh This parameter can be a value between: 0 ~ 64
825 * @retval None
826 */
827 __STATIC_INLINE void ll_adc_set_thresh(uint32_t thresh)
828 {
829 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
830 }
831
832 /**
833 * @brief Return threshold of ADC FIFO.
834 *
835 * Register|BitsName
836 * --------|--------
837 * SENSE_FF_THRESH | SENSE_FF_THRESH
838 *
839 * @retval Returned value can be a value between: 0 ~ 64
840 */
841 __STATIC_INLINE uint32_t ll_adc_get_thresh(void)
842 {
843 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
844 }
845
846 /**
847 * @brief Enable ADC dma_req.
848 *
849 * Register|BitsName
850 * --------|--------
851 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
852 *
853 * @retval None
854 */
855 __STATIC_INLINE void ll_adc_enable_dma_req(void)
856 {
857 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
858 }
859
860 /**
861 * @brief Disable ADC dma_req.
862 *
863 * Register|BitsName
864 * --------|--------
865 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
866 *
867 * @retval None
868 */
869 __STATIC_INLINE void ll_adc_disable_dma_req(void)
870 {
871 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
872 }
873
874 /**
875 * @brief Check if dma_req is enabled.
876 *
877 * Register|BitsName
878 * --------|--------
879 * SENSE_FF_THRESH | MCU_SUB_SNSADC_FF_DMA_EN
880 *
881 * @retval State of bit (1 or 0).
882 */
883 __STATIC_INLINE uint32_t ll_adc_is_enabled_dma_req(void)
884 {
885 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
886 }
887
888 /**
889 * @brief Check if ADC FIFO is not empty.
890 *
891 * Register|BitsName
892 * --------|--------
893 * SENSE_ADC_STAT | VAL
894 *
895 * @retval State of bit (1 or 0).
896 */
897 __STATIC_INLINE uint32_t ll_adc_is_fifo_notempty(void)
898 {
899 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
900 }
901
902 /**
903 * @brief Return count of ADC FIFO.
904 *
905 * Register|BitsName
906 * --------|--------
907 * SENSE_ADC_STAT | FF_COUNT
908 *
909 * @retval Returned value can be a value between: 0 ~ 64
910 */
911 __STATIC_INLINE uint32_t ll_adc_get_fifo_count(void)
912 {
913 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
914 }
915
916 /**
917 * @brief Flush ADC FIFO.
918 *
919 * Register|BitsName
920 * --------|--------
921 * SENSE_ADC_STAT | FF_FLUSH
922 *
923 * @retval void
924 */
925 __STATIC_INLINE void ll_adc_flush_fifo(void)
926 {
927 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
928 }
929
930 /**
931 * @brief Try to lock hw token.
932 *
933 * Register|BitsName
934 * --------|--------
935 * SENSE_ADC_GET_TKN_HW
936 *
937 * @retval Returned true if hw lock adc token success; return false if hw lock adc token fail
938 */
939 __STATIC_INLINE uint32_t ll_adc_try_lock_hw_token(void)
940 {
941 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_HW) == MCU_SUB_SNSADC_TKN_LOCKED_HW);
942 }
943
944 /**
945 * @brief Release hw token.
946 *
947 * Register|BitsName
948 * --------|--------
949 * SENSE_ADC_RET_TKN_HW | HW_RELEASE_Msk
950 *
951 * @retval none
952 */
953 __STATIC_INLINE void ll_adc_release_hw_token(void)
954 {
955 WRITE_REG(MCU_SUB->SENSE_ADC_RET_TKN_HW, 0x00);
956 }
957
958 /**
959 * @brief Try to lock sw token.
960 *
961 * Register|BitsName
962 * --------|--------
963 * SENSE_ADC_GET_TKN_SW
964 *
965 * @retval Returned true if sw lock adc token success; return false if sw lock adc token fail
966 */
967 __STATIC_INLINE uint32_t ll_adc_try_lock_sw_token(void)
968 {
969 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
970 }
971
972 /**
973 * @brief Release sw token.
974 *
975 * Register|BitsName
976 * --------|--------
977 * SENSE_ADC_RET_TKN_SW | SW_RELEASE_Msk
978 *
979 * @retval none
980 */
981 __STATIC_INLINE void ll_adc_release_sw_token(void)
982 {
983 WRITE_REG(MCU_SUB->SENSE_ADC_RET_TKN_SW, 0x00);
984 }
985
986 /**
987 * @brief get adc token state.
988 *
989 * Register|BitsName
990 * --------|--------
991 * SENSE_ADC_TKN_STS
992 *
993 * @retval Returned value from SENSE_ADC_TKN_STS reg
994 */
995 __STATIC_INLINE uint32_t ll_adc_get_token_state(void)
996 {
997 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);
998 }
999
1000 /** @} */
1001
1002 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
1003 * @{
1004 */
1005
1006 /**
1007 * @brief De-initialize ADC registers (Registers restored to their default values).
1008 * @retval An error_status_t enumeration value:
1009 * - SUCCESS: ADC registers are de-initialized
1010 * - ERROR: ADC registers are not de-initialized
1011 */
1012 error_status_t ll_adc_deinit(void);
1013
1014 /**
1015 * @brief Initialize ADC registers according to the specified.
1016 * parameters in p_adc_init.
1017 * @param p_adc_init Pointer to a ll_adc_init_t structure that contains the configuration
1018 * information for the specified ADC peripheral.
1019 * @retval An error_status_t enumeration value:
1020 * - SUCCESS: ADC registers are initialized according to p_adc_init content
1021 * - ERROR: Problem occurred during ADC Registers initialization
1022 */
1023 error_status_t ll_adc_init(ll_adc_init_t *p_adc_init);
1024
1025 /**
1026 * @brief Set each field of a @ref ll_adc_init_t type structure to default value.
1027 * @param p_adc_init Pointer to a @ref ll_adc_init_t structure
1028 * whose fields will be set to default values.
1029 * @retval None
1030 */
1031 void ll_adc_struct_init(ll_adc_init_t *p_adc_init);
1032
1033 /** @} */
1034
1035 /** @} */
1036
1037 #endif /* AON */
1038
1039 #ifdef __cplusplus
1040 }
1041 #endif
1042
1043 #endif /* __GR533X_LL_ADC_H__ */
1044
1045 /** @} */
1046
1047 /** @} */
1048
1049 /** @} */