gr533x_ll_bod.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_bod.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CALENDAR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_BOD BOD Module Driver
47 * @brief BOD LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_BOD_H_
53 #define __GR55XX_LL_BOD_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 /** @defgroup BOD_LL_STRUCTURES Structures
63 * @{
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup BOD_LL_ES_INIT BOD Exported init structures
68 * @{
69 */
70
71 /**
72 * @brief LL BOD init Structure definition
73 */
74 typedef struct _ll_bod_init
75 {
76 uint8_t bod_en; /**< Specifies the bod enable.
77 This parameter can be any value of @ref BOD_LL_ENABLE.
78 This parament can be modified afterwards using unitary function @ref ll_bod_bod_enable() and ll_bod_bod_disable(). */
79
80 uint8_t bod2_en; /**< Specifies the bod2 enable.
81 This parameter can be any value of @ref BOD2_LL_ENABLE.
82 This parament can be modified afterwards using unitary function @ref ll_bod_bod2_enable() and ll_bod_bod2_disable().. */
83
84 uint8_t bod2_lvl; /**< Specifies the bod2 level.
85 This parameter can be a value of @ref BOD2_LL_LEVEL.
86 This parament can be modified afterwards using unitary function @ref ll_bod_bod2_lvl_ctrl_lv_set(). */
87 uint8_t bod_static_en; /**< Specifies the bod static enbale.
88 This parameter can be a value of @ref BOD_LL_STATIC_ENABLE.
89 This parament can be modified afterwards using unitary function @ref ll_bod_static_enable() and ll_bod_static_disable(). */
90
91 uint8_t bod2_auto_power_bypass_en; /**< Specifies the bod bod2 auto power bypass.
92 This parameter can be a value of @ref BOD_LL_BOD2_AUTO_POWER_BYPASS.
93 This parament can be modified afterwards using unitary function @ref ll_bod_bod2_auto_power_bypass_enable()
94 and ll_bod_bod2_auto_power_bypass_disable(). */
95 } ll_bod_init_t;
96
97 /** @} */
98
99 /** @} */
100
101 /**
102 * @defgroup BOD_LL_MACRO Defines
103 * @{
104 */
105
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup BOD_LL_Exported_Constants BOD Exported Constants
108 * @{
109 */
110
111 /** @defgroup BOD_LL_ENABLE BOD ENABLE
112 * @{
113 */
114 #define LL_BOD_BOD_ENABLE (0x1) /**< BOD enable */
115 #define LL_BOD_BOD_DISABLE (0x0) /**< BOD disable */
116 /** @} */
117
118 /** @defgroup BOD2_LL_ENABLE BOD2 ENABLE
119 * @{
120 */
121 #define LL_BOD_BOD2_ENABLE (0x1) /**< BOD2 enable */
122 #define LL_BOD_BOD2_DISABLE (0x0) /**< BOD2 disable */
123 /** @} */
124
125 /** @defgroup BOD_LL_STATIC_ENABLE BOD STATIC ENABLE
126 * @{
127 */
128 #define LL_BOD_STATIC_ENABLE (0x1) /**< BOD STATIC enable */
129 #define LL_BOD_STATIC_DISABLE (0x0) /**< BOD STATIC disable */
130 /** @} */
131
132 /** @defgroup BOD_LL_BOD2_AUTO_POWER_BYPASS BOD2 AUTO POWER BYPASS
133 * @{
134 */
135 #define LL_BOD_BOD2_AUTO_POWER_BYPASS_ENABLE (0x1) /**< BOD STATIC enable */
136 #define LL_BOD_BOD2_AUTO_POWER_BYPASS_DISABLE (0x0) /**< BOD STATIC disable */
137 /** @} */
138
139 /** @defgroup BOD2_LL_LEVEL BOD2 LVEVL
140 * @{
141 */
142 #define LL_BOD_BOD2_LEVEL_0 (0x0) /**< BOD2 Level 0 */
143 #define LL_BOD_BOD2_LEVEL_1 (0x1) /**< BOD2 Level 1 */
144 #define LL_BOD_BOD2_LEVEL_2 (0x2) /**< BOD2 Level 2 */
145 #define LL_BOD_BOD2_LEVEL_3 (0x3) /**< BOD2 Level 3 */
146 #define LL_BOD_BOD2_LEVEL_4 (0x4) /**< BOD2 Level 4 */
147 #define LL_BOD_BOD2_LEVEL_5 (0x5) /**< BOD2 Level 5 */
148 #define LL_BOD_BOD2_LEVEL_6 (0x6) /**< BOD2 Level 6 */
149 #define LL_BOD_BOD2_LEVEL_7 (0x7) /**< BOD2 Level 7 */
150 /** @} */
151
152 /** @} */
153
154 /** @} */
155
156 /** @defgroup BOD_LL_DRIVER_FUNCTIONS Functions
157 * @{
158 */
159 /**
160 * @brief Enable the bod
161 *
162 * Register|BitsName
163 * --------|--------
164 * RF_REG_3 | bod_en_lv
165 *
166 */
167 __STATIC_INLINE void ll_bod_bod_enable(void)
168 {
169 #if defined(BIT_BAND_SUPPORT)
170 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 1;
171 #else
172 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
173 #endif
174 }
175
176 /**
177 * @brief Disable the bod
178 *
179 * Register|BitsName
180 * --------|--------
181 * RF_REG_3 | bod_en_lv
182 *
183 */
184 __STATIC_INLINE void ll_bod_bod_disable(void)
185 {
186 #if defined(BIT_BAND_SUPPORT)
187 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 0;
188 #else
189 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
190 #endif
191 }
192
193 /**
194 * @brief Enable the bod2
195 *
196 * Register|BitsName
197 * --------|--------
198 * RF_REG_3 | bod2_en_lv
199 *
200 */
201 __STATIC_INLINE void ll_bod_bod2_enable(void)
202 {
203 #if defined(BIT_BAND_SUPPORT)
204 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 1;
205 #else
206 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
207 #endif
208 }
209
210 /**
211 * @brief Disable the bod2
212 *
213 * Register|BitsName
214 * --------|--------
215 * RF_REG_3 | bod2_en_lv
216 *
217 */
218 __STATIC_INLINE void ll_bod_bod2_disable(void)
219 {
220 #if defined(BIT_BAND_SUPPORT)
221 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 0;
222 #else
223 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
224 #endif
225 }
226
227 /**
228 * @brief Set bod control level
229 *
230 * Register|BitsName
231 * --------|--------
232 * RF_REG_3 | bod_lvl_ctrl_lv_3_0
233 * @param lvl_ctrl_lv: 0x0 ~ 0xF
234 */
235 __STATIC_INLINE void ll_bod_bod2_lvl_ctrl_lv_set(uint8_t lvl_ctrl_lv)
236 {
237 #if defined(BIT_BAND_SUPPORT)
238 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos) = (lvl_ctrl_lv & 0x01);
239 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos+1) = ((lvl_ctrl_lv>>1) & 0x01);
240 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos+2) = ((lvl_ctrl_lv>>2) & 0x01);
241 #else
242 MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV, (lvl_ctrl_lv << AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos));
243 #endif
244 }
245
246 /**
247 * @brief enable bod static lv
248 *
249 * Register|BitsName
250 * --------|--------
251 * RF_REG_3 | bod_static_lv
252 */
253 __STATIC_INLINE void ll_bod_static_enable(void)
254 {
255 #if defined(BIT_BAND_SUPPORT)
256 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_Pos) = 1;
257 #else
258 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_EN);
259 #endif
260 }
261
262 /**
263 * @brief disable bod static lv
264 *
265 * Register|BitsName
266 * --------|--------
267 * RF_REG_3 | bod_static_lv
268 */
269 __STATIC_INLINE void ll_bod_static_disable(void)
270 {
271 #if defined(BIT_BAND_SUPPORT)
272 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_Pos) = 0;
273 #else
274 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_EN);
275 #endif
276 }
277
278 /**
279 * @brief Enable the bod2 auto power bypass
280 *
281 * Register|BitsName
282 * --------|--------
283 * RF_REG_3 | bod2_auto_power_bypass_enable
284 *
285 */
286 __STATIC_INLINE void ll_bod_bod2_auto_power_bypass_enable(void)
287 {
288 #if defined(BIT_BAND_SUPPORT)
289 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS_Pos) = 1;
290 #else
291 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
292 #endif
293 }
294
295 /**
296 * @brief Disable the bod2 auto power bypass
297 *
298 * Register|BitsName
299 * --------|--------
300 * RF_REG_3 | bod2_auto_power_bypass_enable
301 *
302 */
303 __STATIC_INLINE void ll_bod_bod2_auto_power_bypass_disable(void)
304 {
305 #if defined(BIT_BAND_SUPPORT)
306 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS_Pos) = 0;
307 #else
308 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
309 #endif
310 }
311
312 /**
313 * @brief Indicate if the BOD Power Flag is set or not.
314 *
315 * Register|BitsName
316 * --------|--------
317 * RF_REG_3 | pmu_bod_ok
318 *
319 * @retval State of bit (1 or 0).
320 */
321 __STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_bod_ok(void)
322 {
323 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_OK) == AON_PMU_RF_REG_3_BOD2_OK);
324 }
325
326 /**
327 * @brief Indicate if the BOD2 Power Flag is set or not.
328 *
329 * Register|BitsName
330 * --------|--------
331 * RF_REG_3 | bod2_pwr_ctrl_post
332 *
333 * @retval State of bit (1 or 0).
334 */
335 __STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_bod2_pwr_ctrl_post(void)
336 {
337 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_PWR_CTRL_POST) == AON_PMU_RF_REG_3_BOD2_PWR_CTRL_POST);
338 }
339
340 /**
341 * @brief Indicate if the BOD INTR Flag is set or not.
342 *
343 * Register|BitsName
344 * --------|--------
345 * RF_REG_3 | pmu_bod_intr
346 *
347 * @retval State of bit (1 or 0).
348 */
349 __STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_pmu_bod_intr(void)
350 {
351 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_INT) == AON_PMU_RF_REG_3_BOD2_INT);
352 }
353
354
355 /**
356 * @brief enable BOD FEDGE Event.
357 *
358 * Register|BitsName
359 * --------|--------
360 * AON_IRQ | AON_CTL_AON_IRQ_EN_PMU_BOD_FALL
361 *
362 * @retval State of bit (1 or 0).
363 */
364 __STATIC_INLINE void ll_bod_bod2_enable_fedge(void)
365 {
366 SET_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_FALL);
367 }
368
369 /**
370 * @brief disable BOD FEDGE Event.
371 *
372 * Register|BitsName
373 * --------|--------
374 * AON_IRQ | AON_CTL_AON_IRQ_EN_PMU_BOD_FALL
375 *
376 * @retval State of bit (1 or 0).
377 */
378 __STATIC_INLINE void ll_bod_bod2_disable_fedge(void)
379 {
380 CLEAR_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_FALL);
381 }
382
383 /**
384 * @brief enable BOD REDGE Event.
385 *
386 * Register|BitsName
387 * --------|--------
388 * AON_IRQ | AON_CTL_AON_IRQ_EN_PMU_BOD_RISE
389 *
390 * @retval State of bit (1 or 0).
391 */
392 __STATIC_INLINE void ll_bod_bod2_enable_redge(void)
393 {
394 SET_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_RISE);
395 }
396
397 /**
398 * @brief disable BOD REDGE Event.
399 *
400 * Register|BitsName
401 * --------|--------
402 * AON_IRQ | AON_CTL_AON_IRQ_EN_PMU_BOD_RISE
403 *
404 * @retval State of bit (1 or 0).
405 */
406 __STATIC_INLINE void ll_bod_bod2_disable_redge(void)
407 {
408 CLEAR_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_RISE);
409 }
410
411 /**
412 * @brief Indicate if the BOD FEDGE Event Flag is set or not.
413 *
414 * Register|BitsName
415 * --------|--------
416 * AON_IRQ | AON_CTL_AON_IRQ_PMU_BOD_FALL
417 *
418 * @retval State of bit (1 or 0).
419 */
420 __STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_fedge(void)
421 {
422 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD_FALL) == AON_CTL_AON_IRQ_PMU_BOD_FALL);
423 }
424
425 /**
426 * @brief Clear Interrupt Status flag.
427 *
428 * Register|BitsName
429 * --------|--------
430 * AON_IRQ| AON_CTL_AON_IRQ_PMU_BOD_FALL
431 *
432 * @retval None
433 */
434 __STATIC_INLINE void ll_bod_bod2_clear_flag_fedge(void)
435 {
436 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD_FALL);
437 }
438
439 /**
440 * @brief Indicate if the BOD REDGE Event Flag is set or not.
441 *
442 * Register|BitsName
443 * --------|--------
444 * AON_IRQ | AON_CTL_AON_IRQ_PMU_BOD_RISE
445 *
446 * @retval State of bit (1 or 0).
447 */
448 __STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_redge(void)
449 {
450 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD_RISE) == AON_CTL_AON_IRQ_PMU_BOD_RISE);
451 }
452
453 /**
454 * @brief Clear Interrupt Status flag.
455 *
456 * Register|BitsName
457 * --------|--------
458 * AON_IRQ| AON_CTL_AON_IRQ_PMU_BOD_RISE
459 *
460 * @retval None
461 */
462 __STATIC_INLINE void ll_bod_bod2_clear_flag_redge(void)
463 {
464 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD_RISE);
465 }
466
467 /**
468 * @brief De-initialize the BOD registers to their default reset values.
469 * @retval An error_status_t enumeration value:
470 * - SUCCESS: PDM registers are de-initialized
471 * - ERROR: PDM registers are not de-initialized
472 */
473 error_status_t ll_bod_deinit(void);
474
475 /**
476 * @brief Initialize the BOD registers according to the specified parameters in p_bod_init.
477 * @param p_bod_init pointer to a @ref ll_bod_init_t structure.
478 * @retval An error_status_t enumeration value:
479 * - SUCCESS: BOD registers are initialized
480 * - ERROR: Not applicable
481 */
482 error_status_t ll_bod_init(ll_bod_init_t *p_bod_init);
483
484 /**
485 * @brief Set each field of a p_bod_init type structure to default value.
486 * @param p_bod_init Pointer to a @ref ll_bod_init_t structure
487 * whose fields will be set to default values.
488 * @retval None
489 */
490 void ll_bod_struct_init(ll_bod_init_t *p_bod_init);
491 /** @} */
492 #endif
493 /** @} */
494
495 /** @} */
496
497 /** @} */
_ll_bod_init::bod_static_en
uint8_t bod_static_en
Definition: gr533x_ll_bod.h:87
ll_bod_bod2_is_active_flag_bod2_pwr_ctrl_post
__STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_bod2_pwr_ctrl_post(void)
Indicate if the BOD2 Power Flag is set or not.
Definition: gr533x_ll_bod.h:335
ll_bod_static_enable
__STATIC_INLINE void ll_bod_static_enable(void)
enable bod static lv
Definition: gr533x_ll_bod.h:253
ll_bod_bod2_disable_fedge
__STATIC_INLINE void ll_bod_bod2_disable_fedge(void)
disable BOD FEDGE Event.
Definition: gr533x_ll_bod.h:378
ll_bod_bod2_enable_redge
__STATIC_INLINE void ll_bod_bod2_enable_redge(void)
enable BOD REDGE Event.
Definition: gr533x_ll_bod.h:392
ll_bod_bod2_disable
__STATIC_INLINE void ll_bod_bod2_disable(void)
Disable the bod2.
Definition: gr533x_ll_bod.h:218
ll_bod_bod2_is_active_flag_pmu_bod_intr
__STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_pmu_bod_intr(void)
Indicate if the BOD INTR Flag is set or not.
Definition: gr533x_ll_bod.h:349
ll_bod_bod_enable
__STATIC_INLINE void ll_bod_bod_enable(void)
Enable the bod.
Definition: gr533x_ll_bod.h:167
ll_bod_bod2_is_active_flag_fedge
__STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_fedge(void)
Indicate if the BOD FEDGE Event Flag is set or not.
Definition: gr533x_ll_bod.h:420
_ll_bod_init
LL BOD init Structure definition.
Definition: gr533x_ll_bod.h:75
ll_bod_bod2_lvl_ctrl_lv_set
__STATIC_INLINE void ll_bod_bod2_lvl_ctrl_lv_set(uint8_t lvl_ctrl_lv)
Set bod control level.
Definition: gr533x_ll_bod.h:235
_ll_bod_init::bod2_en
uint8_t bod2_en
Definition: gr533x_ll_bod.h:80
ll_bod_init_t
struct _ll_bod_init ll_bod_init_t
LL BOD init Structure definition.
_ll_bod_init::bod_en
uint8_t bod_en
Definition: gr533x_ll_bod.h:76
ll_bod_bod2_clear_flag_redge
__STATIC_INLINE void ll_bod_bod2_clear_flag_redge(void)
Clear Interrupt Status flag.
Definition: gr533x_ll_bod.h:462
ll_bod_bod2_enable_fedge
__STATIC_INLINE void ll_bod_bod2_enable_fedge(void)
enable BOD FEDGE Event.
Definition: gr533x_ll_bod.h:364
ll_bod_bod2_auto_power_bypass_disable
__STATIC_INLINE void ll_bod_bod2_auto_power_bypass_disable(void)
Disable the bod2 auto power bypass.
Definition: gr533x_ll_bod.h:303
ll_bod_bod2_clear_flag_fedge
__STATIC_INLINE void ll_bod_bod2_clear_flag_fedge(void)
Clear Interrupt Status flag.
Definition: gr533x_ll_bod.h:434
ll_bod_static_disable
__STATIC_INLINE void ll_bod_static_disable(void)
disable bod static lv
Definition: gr533x_ll_bod.h:269
ll_bod_struct_init
void ll_bod_struct_init(ll_bod_init_t *p_bod_init)
Set each field of a p_bod_init type structure to default value.
ll_bod_bod2_is_active_flag_redge
__STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_redge(void)
Indicate if the BOD REDGE Event Flag is set or not.
Definition: gr533x_ll_bod.h:448
ll_bod_bod2_auto_power_bypass_enable
__STATIC_INLINE void ll_bod_bod2_auto_power_bypass_enable(void)
Enable the bod2 auto power bypass.
Definition: gr533x_ll_bod.h:286
ll_bod_bod2_enable
__STATIC_INLINE void ll_bod_bod2_enable(void)
Enable the bod2.
Definition: gr533x_ll_bod.h:201
ll_bod_bod_disable
__STATIC_INLINE void ll_bod_bod_disable(void)
Disable the bod.
Definition: gr533x_ll_bod.h:184
ll_bod_bod2_disable_redge
__STATIC_INLINE void ll_bod_bod2_disable_redge(void)
disable BOD REDGE Event.
Definition: gr533x_ll_bod.h:406
_ll_bod_init::bod2_auto_power_bypass_en
uint8_t bod2_auto_power_bypass_en
Definition: gr533x_ll_bod.h:91
ll_bod_init
error_status_t ll_bod_init(ll_bod_init_t *p_bod_init)
Initialize the BOD registers according to the specified parameters in p_bod_init.
ll_bod_deinit
error_status_t ll_bod_deinit(void)
De-initialize the BOD registers to their default reset values.
_ll_bod_init::bod2_lvl
uint8_t bod2_lvl
Definition: gr533x_ll_bod.h:84
ll_bod_bod2_is_active_flag_bod_ok
__STATIC_INLINE uint32_t ll_bod_bod2_is_active_flag_bod_ok(void)
Indicate if the BOD Power Flag is set or not.
Definition: gr533x_ll_bod.h:321