gr533x_ll_aon_gpio.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_AON_GPIO_H__
53 #define __GR533X_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined(AON_IO)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
79 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
80
81 uint32_t mode; /**< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
83
84 AON_GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_mode(). */
85
86 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
88
89 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of AON_GPIO_LL_EC_MUX.
93
94 GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_aon_gpio_set_pin_mux(). */
96
97 uint32_t speed; /**< Specifies the Speed for the selected pins.
98 This parameter can be a value of @ref AON_GPIO_LL_EC_SPEED.
99
100 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_speed().*/
101
102 uint32_t strength; /**< Specifies the Speed for the selected pins.
103 This parameter can be a value of @ref AON_GPIO_LL_EC_STRENGTH.
104
105 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_strength().*/
106
107 uint32_t input_type; /**< Specifies the input type for the selected pins.
108 This parameter can be a value of @ref AON_GPIO_LL_EC_INPUT_TYPE.
109
110 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_input_type().*/
111
112 uint32_t trigger; /**< Specifies the trigger signal active edge.
113 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
114 } ll_aon_gpio_init_t;
115
116 /** @} */
117
118 /** @} */
119
120 /**
121 * @defgroup AON_GPIO_LL_MACRO Defines
122 * @{
123 */
124
125 /* Exported constants --------------------------------------------------------*/
126 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
127 * @{
128 */
129 /** @defgroup AON_GPIO_LL_PRIVATE_MACRO Private Macro
130 * @{
131 */
132 #define LL_AON_GPIO_MODE_INPUT_POS ((uint32_t)0x0U) /*!< Input mode bit position AON_GPIO_LL_EC_MODE */
133 #define LL_AON_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U) /*!< Output mode bit position AON_GPIO_LL_EC_MODE */
134 #define LL_AON_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U) /*!< DS0 mask in AON_GPIO_LL_EC_STRENGTH */
135 #define LL_AON_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U) /*!< DS1 mask in AON_GPIO_LL_EC_STRENGTH */
136 #define LL_AON_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U) /*!< DS0 bit position in AON_GPIO_LL_EC_STRENGTH */
137 #define LL_AON_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U) /*!< DS1 bit position in AON_GPIO_LL_EC_STRENGTH */
138 /** @} */
139
140 /** @defgroup AON_GPIO_LL_EC_PIN PIN
141 * @{
142 */
143 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
144 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
145 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
146 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
147 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
148 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
149 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
150 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
151 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
152 /** @} */
153
154 /** @defgroup AON_GPIO_LL_EC_MODE Mode
155 * @{
156 */
157 #define LL_AON_GPIO_MODE_NONE ((uint32_t)0x0U) /**< No input or output */
158 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x1U) /**< Select input mode */
159 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x2U) /**< Select output mode */
160 #define LL_AON_GPIO_MODE_INOUT ((uint32_t)0x3U) /**< Select input and output mode */
161
162 /** @} */
163
164 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
165 * @{
166 */
167 #define LL_AON_GPIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
168 #define LL_AON_GPIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
169 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
170 /** @} */
171
172
173 /** @defgroup AON_GPIO_LL_EC_SPEED IO speed
174 * @{
175 */
176 #define LL_AON_GPIO_SPEED_MEDIUM ((uint32_t)0x1U) /*!< Select medium speed */
177 #define LL_AON_GPIO_SPEED_HIGH ((uint32_t)0x0U) /*!< Select high speed */
178 /** @} */
179
180 /** @defgroup AON_GPIO_LL_EC_STRENGTH IO strength
181 * @{
182 */
183 #define LL_AON_GPIO_STRENGTH_LOW ((uint32_t)0x00U) /*!< Select low output driver strength */
184 #define LL_AON_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U) /*!< Select medium output driver strength */
185 #define LL_AON_GPIO_STRENGTH_HIGH ((uint32_t)0x10U) /*!< Select high output driver strength */
186 #define LL_AON_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U) /*!< Select high output driver strength */
187 /** @} */
188
189 /** @defgroup AON_GPIO_LL_EC_INPUT_TYPE Input type
190 * @{
191 */
192 #define LL_AON_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U) /**< CMOS input */
193 #define LL_AON_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U) /**< Schmitt input */
194 /** @} */
195
196 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
197 * @{
198 */
199 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
200 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
201 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
202 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
203 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
204 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U) /**< Trigger both edge */
205 /** @} */
206
207 /** @defgroup AON_GPIO_LL_CLOCK_OUT Clock Out
208 * @{
209 */
210 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U) /**< RNG osc 32k */
211 #define LL_CLK_RNG_OSC_250K ((uint32_t)0x01U) /**< RNG osc 250k */
212 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U) /**< RC osc clk */
213 #define LL_CLK_RTC_CLK ((uint32_t)0x03U) /**< RTC clk */
214 /** @} */
215
216 /** @} */
217
218 /* Exported macro ------------------------------------------------------------*/
219 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
220 * @{
221 */
222
223 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
224 * @{
225 */
226
227 /**
228 * @brief Write a value in AON_GPIO register
229 * @param __instance__ AON_GPIO instance
230 * @param __REG__ Register to be written
231 * @param __VALUE__ Value to be written in the register
232 * @retval None
233 */
234 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
235
236 /**
237 * @brief Read a value in AON_GPIO register
238 * @param __instance__ AON_GPIO instance
239 * @param __REG__ Register to be read
240 * @retval Register value
241 */
242 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
243
244 /** @} */
245
246 /** @} */
247
248 /* Private types -------------------------------------------------------------*/
249 /* Private variables ---------------------------------------------------------*/
250 /* Private constants ---------------------------------------------------------*/
251 /* Private macros ------------------------------------------------------------*/
252 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
253 * @{
254 */
255 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
256 * @{
257 */
258
259 /**
260 * @brief LL AON_GPIO InitStrcut default configuartion
261 */
262 #define LL_AON_GPIO_DEFAULT_CONFIG \
263 { \
264 .pin = LL_AON_GPIO_PIN_ALL, \
265 .mode = LL_AON_GPIO_MODE_INPUT, \
266 .pull = LL_AON_GPIO_PULL_DOWN, \
267 .mux = IO_MUX_GPIO, \
268 .speed = LL_AON_GPIO_SPEED_MEDIUM, \
269 .strength = LL_AON_GPIO_STRENGTH_MEDIUM, \
270 .input_type = LL_AON_GPIO_INPUT_TYPE_CMOS, \
271 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
272 }
273 /** @} */
274
275 /** @} */
276
277 /** @} */
278
279 /* Exported functions --------------------------------------------------------*/
280 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
281 * @{
282 */
283
284 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
285 * @{
286 */
287
288 /**
289 * @brief Set several AON_GPIO pins to input/output mode.
290 *
291 * Register|BitsName
292 * --------|--------
293 * AON_PAD_CTL1 | AON_GPO_OE_N
294 *
295 * @param pin_mask This parameter can be a combination of the following values:
296 * @arg @ref LL_AON_GPIO_PIN_0
297 * @arg @ref LL_AON_GPIO_PIN_1
298 * @arg @ref LL_AON_GPIO_PIN_2
299 * @arg @ref LL_AON_GPIO_PIN_3
300 * @arg @ref LL_AON_GPIO_PIN_4
301 * @arg @ref LL_AON_GPIO_PIN_5
302 * @arg @ref LL_AON_GPIO_PIN_6
303 * @arg @ref LL_AON_GPIO_PIN_7
304 * @arg @ref LL_AON_GPIO_PIN_ALL
305 * @param mode This parameter can be one of the following values:
306 * @arg @ref LL_AON_GPIO_MODE_NONE
307 * @arg @ref LL_AON_GPIO_MODE_INPUT
308 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
309 * @arg @ref LL_AON_GPIO_MODE_INOUT
310 * @retval None
311 */
312 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
313 {
314 uint32_t ie_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_IE_POS) & AON_IO_AON_PAD_CTRL0_IE;
315 uint32_t oe_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OE_POS) & AON_IO_AON_PAD_CTRL1_OE;
316 uint32_t ie = ((mode == LL_AON_GPIO_MODE_INPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
317 uint32_t oe = ((mode == LL_AON_GPIO_MODE_OUTPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
318 MODIFY_REG(AON_IO->AON_PAD_CTRL0, ie_mask, ie);
319 MODIFY_REG(AON_IO->AON_PAD_CTRL1, oe_mask, oe);
320 }
321
322 /**
323 * @brief Return gpio mode for a AON_GPIO pin.
324 * @note I/O mode can be Input mode. General purpose output.
325 * @note Warning: only one pin can be passed as parameter.
326 *
327 * Register|BitsName
328 * --------|--------
329 * AON_PAD_CTL0 | IE
330 * AON_PAD_CTL1 | OE
331 *
332 * @param pin This parameter can be one of the following values:
333 * @arg @ref LL_AON_GPIO_PIN_0
334 * @arg @ref LL_AON_GPIO_PIN_1
335 * @arg @ref LL_AON_GPIO_PIN_2
336 * @arg @ref LL_AON_GPIO_PIN_3
337 * @arg @ref LL_AON_GPIO_PIN_4
338 * @arg @ref LL_AON_GPIO_PIN_5
339 * @arg @ref LL_AON_GPIO_PIN_6
340 * @arg @ref LL_AON_GPIO_PIN_7
341 * @retval Returned value can be one of the following values:
342 * @arg @ref LL_AON_GPIO_MODE_NONE
343 * @arg @ref LL_AON_GPIO_MODE_INPUT
344 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
345 * @arg @ref LL_AON_GPIO_MODE_INOUT
346 */
347 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
348 {
349 uint32_t ie_mask = (pin << AON_IO_AON_PAD_CTRL0_IE_POS) & AON_IO_AON_PAD_CTRL0_IE;
350 uint32_t oe_mask = (pin << AON_IO_AON_PAD_CTRL1_OE_POS) & AON_IO_AON_PAD_CTRL1_OE;
351 uint32_t ie = READ_BITS(AON_IO->AON_PAD_CTRL0, ie_mask) >> (POSITION_VAL(pin));
352 uint32_t oe = READ_BITS(AON_IO->AON_PAD_CTRL1, oe_mask) >> (POSITION_VAL(pin));
353 return (((ie >> AON_IO_AON_PAD_CTRL0_IE_POS) << LL_AON_GPIO_MODE_INPUT_POS)
354 | ((oe >> AON_IO_AON_PAD_CTRL1_OE_POS) << LL_AON_GPIO_MODE_OUTPUT_POS));
355 }
356
357 /**
358 * @brief Set several AON_GPIO pins to input type.
359 *
360 * Register|BitsName
361 * --------|--------
362 * AON_PAD_CTL2 | IS
363 *
364 * @param pin_mask This parameter can be a combination of the following values:
365 * @arg @ref LL_AON_GPIO_PIN_0
366 * @arg @ref LL_AON_GPIO_PIN_1
367 * @arg @ref LL_AON_GPIO_PIN_2
368 * @arg @ref LL_AON_GPIO_PIN_3
369 * @arg @ref LL_AON_GPIO_PIN_4
370 * @arg @ref LL_AON_GPIO_PIN_5
371 * @arg @ref LL_AON_GPIO_PIN_6
372 * @arg @ref LL_AON_GPIO_PIN_7
373 * @arg @ref LL_AON_GPIO_PIN_ALL
374 * @param type This parameter can be one of the following values:
375 * @arg @ref LL_AON_GPIO_INPUT_TYPE_CMOS
376 * @arg @ref LL_AON_GPIO_INPUT_TYPE_SCHMITT
377 * @retval None
378 */
379 __STATIC_INLINE void ll_aon_gpio_set_pin_input_type(uint32_t pin_mask, uint32_t type)
380 {
381 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL2_IS_POS) & AON_IO_AON_PAD_CTRL2_IS;
382 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask, (type == LL_AON_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
383 }
384
385 /**
386 * @brief Return input type for a AON_GPIO pin.
387 * @note I/O mode can be Input mode. General purpose output.
388 * @note Warning: only one pin can be passed as parameter.
389 *
390 * Register|BitsName
391 * --------|--------
392 * AON_PAD_CTL2 | IS
393 *
394 * @param pin This parameter can be one of the following values:
395 * @arg @ref LL_AON_GPIO_PIN_0
396 * @arg @ref LL_AON_GPIO_PIN_1
397 * @arg @ref LL_AON_GPIO_PIN_2
398 * @arg @ref LL_AON_GPIO_PIN_3
399 * @arg @ref LL_AON_GPIO_PIN_4
400 * @arg @ref LL_AON_GPIO_PIN_5
401 * @arg @ref LL_AON_GPIO_PIN_6
402 * @arg @ref LL_AON_GPIO_PIN_7
403 * @retval Returned value can be one of the following values:
404 * @arg @ref LL_AON_GPIO_INPUT_TYPE_CMOS
405 * @arg @ref LL_AON_GPIO_INPUT_TYPE_SCHMITT
406 */
407 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_input_type(uint32_t pin)
408 {
409 pin = (pin << AON_IO_AON_PAD_CTRL2_IS_POS) & AON_IO_AON_PAD_CTRL2_IS;
410 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL2, pin) == pin) ?
411 LL_AON_GPIO_INPUT_TYPE_SCHMITT : LL_AON_GPIO_INPUT_TYPE_CMOS);
412 }
413
414 /**
415 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
416 * @note Warning: only one pin can be passed as parameter.
417 *
418 * Register|BitsName
419 * --------|--------
420 * AON_PAD_CTL0 | PE
421 * AON_PAD_CTL0 | PS
422 *
423 * @param pin_mask This parameter can be a combination of the following values:
424 * @arg @ref LL_AON_GPIO_PIN_0
425 * @arg @ref LL_AON_GPIO_PIN_1
426 * @arg @ref LL_AON_GPIO_PIN_2
427 * @arg @ref LL_AON_GPIO_PIN_3
428 * @arg @ref LL_AON_GPIO_PIN_4
429 * @arg @ref LL_AON_GPIO_PIN_5
430 * @arg @ref LL_AON_GPIO_PIN_6
431 * @arg @ref LL_AON_GPIO_PIN_7
432 * @arg @ref LL_AON_GPIO_PIN_ALL
433 * @param pull This parameter can be one of the following values:
434 * @arg @ref LL_AON_GPIO_PULL_NO
435 * @arg @ref LL_AON_GPIO_PULL_UP
436 * @arg @ref LL_AON_GPIO_PULL_DOWN
437 * @retval None
438 */
439 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
440 {
441 uint32_t ps_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_PS_POS) & AON_IO_AON_PAD_CTRL0_PS;
442 uint32_t pe_mask = (pin_mask << AON_IO_AON_PAD_CTRL0_PE_POS) & AON_IO_AON_PAD_CTRL0_PE;
443 uint32_t ps = (pull == LL_AON_GPIO_PULL_UP) ? ps_mask : 0x0000U;
444 uint32_t pe = (pull == LL_AON_GPIO_PULL_NO) ? 0x0000U : pe_mask;
445 MODIFY_REG(AON_IO->AON_PAD_CTRL0, pe_mask | ps_mask, pe | ps);
446 }
447
448 /**
449 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
450 * @note Warning: only one pin can be passed as parameter.
451 *
452 * Register|BitsName
453 * --------|--------
454 * AON_PAD_CTL0 | PE
455 * AON_PAD_CTL0 | PS
456 *
457 * @param pin This parameter can be one of the following values:
458 * @arg @ref LL_AON_GPIO_PIN_0
459 * @arg @ref LL_AON_GPIO_PIN_1
460 * @arg @ref LL_AON_GPIO_PIN_2
461 * @arg @ref LL_AON_GPIO_PIN_3
462 * @arg @ref LL_AON_GPIO_PIN_4
463 * @arg @ref LL_AON_GPIO_PIN_5
464 * @arg @ref LL_AON_GPIO_PIN_6
465 * @arg @ref LL_AON_GPIO_PIN_7
466 * @retval Returned value can be one of the following values:
467 * @arg @ref LL_AON_GPIO_PULL_NO
468 * @arg @ref LL_AON_GPIO_PULL_UP
469 * @arg @ref LL_AON_GPIO_PULL_DOWN
470 */
471 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
472 {
473 uint32_t ps_mask = (pin << AON_IO_AON_PAD_CTRL0_PS_POS) & AON_IO_AON_PAD_CTRL0_PS;
474 uint32_t pe_mask = (pin << AON_IO_AON_PAD_CTRL0_PE_POS) & AON_IO_AON_PAD_CTRL0_PE;
475 return ((READ_BITS(AON_IO->AON_PAD_CTRL0, pe_mask) == RESET) ? LL_AON_GPIO_PULL_NO :
476 ((READ_BITS(AON_IO->AON_PAD_CTRL0, ps_mask) == RESET) ? LL_AON_GPIO_PULL_DOWN : LL_AON_GPIO_PULL_UP));
477 }
478
479 /**
480 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
481 * @note Possible values are from AF0 to AF15 depending on target.
482 * @note Warning: only one pin can be passed as parameter.
483 *
484 * Register|BitsName
485 * --------|--------
486 * AON_PAD_MUX | AON_PAD_MUX
487 * AON_MCU_OVR | AON_MCU_OVR
488 *
489 * @param pin This parameter can be one of the following values:
490 * @arg @ref LL_AON_GPIO_PIN_0
491 * @arg @ref LL_AON_GPIO_PIN_1
492 * @arg @ref LL_AON_GPIO_PIN_2
493 * @arg @ref LL_AON_GPIO_PIN_3
494 * @arg @ref LL_AON_GPIO_PIN_4
495 * @arg @ref LL_AON_GPIO_PIN_5
496 * @arg @ref LL_AON_GPIO_PIN_6
497 * @arg @ref LL_AON_GPIO_PIN_7
498 * @param mux This parameter can be one of the following values:
499 * IO_MUX_GPIO define
500 * @retval None
501 */
502 __STATIC_INLINE void ll_aon_gpio_set_pin_mux(uint32_t pin, uint32_t mux)
503 {
504 uint8_t id;
505 uint32_t pos;
506
507 if(IO_MUX_GPIO == mux)
508 {
509 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
510 }
511 else
512 {
513 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
514 }
515
516 pin = POSITION_VAL(pin);
517
518 id = pin >> 2;
519 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
520
521 MODIFY_REG(MCU_PAD->AON_PAD_MUX[id], IO_MUX_BIT_MASK << pos, mux << pos);
522 }
523
524 /**
525 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
526 *
527 * Register|BitsName
528 * --------|--------
529 * AON_PAD_MUX | AON_PAD_MUX
530 * AON_MCU_OVR | AON_MCU_OVR
531 *
532 * @param pin This parameter can be one of the following values:
533 * @arg @ref LL_AON_GPIO_PIN_0
534 * @arg @ref LL_AON_GPIO_PIN_1
535 * @arg @ref LL_AON_GPIO_PIN_2
536 * @arg @ref LL_AON_GPIO_PIN_3
537 * @arg @ref LL_AON_GPIO_PIN_4
538 * @arg @ref LL_AON_GPIO_PIN_5
539 * @arg @ref LL_AON_GPIO_PIN_6
540 * @arg @ref LL_AON_GPIO_PIN_7
541 * @retval Returned value can be one of the following values:
542 * IO_MUX_GPIO define
543 */
544 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mux(uint32_t pin)
545 {
546 if (READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
547 {
548 uint8_t id;
549 uint32_t pos;
550
551 pin = POSITION_VAL(pin);
552
553 id = pin >> 2;
554 pos = (pin & 3) << 3; /* pos = (pin % 4) * 8 */
555
556 return (READ_BITS(MCU_PAD->AON_PAD_MUX[id], IO_MUX_BIT_MASK << pos) >> pos);
557 }
558 else
559 {
560 return IO_MUX_GPIO;
561 }
562 }
563
564 /**
565 * @brief Configure slew rate for a dedicated AON_GPIO pin.
566 * @note Warning: only one pin can be passed as parameter.
567 *
568 * Register|BitsName
569 * --------|--------
570 * AON_PAD_CTRL2 | SR
571 *
572 * @param pin_mask This parameter can be a combination of the following values:
573 * @arg @ref LL_AON_GPIO_PIN_0
574 * @arg @ref LL_AON_GPIO_PIN_1
575 * @arg @ref LL_AON_GPIO_PIN_2
576 * @arg @ref LL_AON_GPIO_PIN_3
577 * @arg @ref LL_AON_GPIO_PIN_4
578 * @arg @ref LL_AON_GPIO_PIN_5
579 * @arg @ref LL_AON_GPIO_PIN_6
580 * @arg @ref LL_AON_GPIO_PIN_7
581 * @arg @ref LL_AON_GPIO_PIN_ALL
582 * @param speed This parameter can be one of the following values:
583 * @arg @ref LL_AON_GPIO_SPEED_MEDIUM
584 * @arg @ref LL_AON_GPIO_SPEED_HIGH
585 * @retval None
586 */
587 __STATIC_INLINE void ll_aon_gpio_set_pin_speed(uint32_t pin_mask, uint32_t speed)
588 {
589 if(speed)
590 {
591 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS);
592 }
593 else
594 {
595 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_CTRL2_SR_POS, 0);
596 }
597 }
598
599 /**
600 * @brief Return slew rate for a dedicated AON_GPIO pin.
601 * @note Warning: only one pin can be passed as parameter.
602 *
603 * Register|BitsName
604 * --------|--------
605 * AON_PAD_CTRL2 | SR
606 *
607 * @param pin This parameter can be one of the following values:
608 * @arg @ref LL_AON_GPIO_PIN_0
609 * @arg @ref LL_AON_GPIO_PIN_1
610 * @arg @ref LL_AON_GPIO_PIN_2
611 * @arg @ref LL_AON_GPIO_PIN_3
612 * @arg @ref LL_AON_GPIO_PIN_4
613 * @arg @ref LL_AON_GPIO_PIN_5
614 * @arg @ref LL_AON_GPIO_PIN_6
615 * @arg @ref LL_AON_GPIO_PIN_7
616 * @retval Returned value can be one of the following values:
617 * @arg @ref LL_AON_GPIO_SPEED_MEDIUM
618 * @arg @ref LL_AON_GPIO_SPEED_HIGH
619 */
620 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_speed(uint32_t pin)
621 {
622 uint32_t pos;
623 pos = POSITION_VAL(pin);
624 return (READ_BITS(AON_IO->AON_PAD_CTRL2, pin << AON_IO_AON_PAD_CTRL2_SR_POS) >> AON_IO_AON_PAD_CTRL2_SR_POS >> pos);
625 }
626
627 /**
628 * @brief Configure output drive strength for a dedicated AON_GPIO pin.
629 * @note Warning: only one pin can be passed as parameter.
630 *
631 * Register|BitsName
632 * --------|--------
633 * AON_PAD_CTL3 | DS0
634 * AON_PAD_CTL3 | DS1
635 *
636 * @param pin_mask This parameter can be a combination of the following values:
637 * @arg @ref LL_AON_GPIO_PIN_0
638 * @arg @ref LL_AON_GPIO_PIN_1
639 * @arg @ref LL_AON_GPIO_PIN_2
640 * @arg @ref LL_AON_GPIO_PIN_3
641 * @arg @ref LL_AON_GPIO_PIN_4
642 * @arg @ref LL_AON_GPIO_PIN_5
643 * @arg @ref LL_AON_GPIO_PIN_6
644 * @arg @ref LL_AON_GPIO_PIN_7
645 * @arg @ref LL_AON_GPIO_PIN_ALL
646 * @param strength This parameter can be one of the following values:
647 * @arg @ref LL_AON_GPIO_STRENGTH_LOW
648 * @arg @ref LL_AON_GPIO_STRENGTH_MEDIUM
649 * @arg @ref LL_AON_GPIO_STRENGTH_HIGH
650 * @arg @ref LL_AON_GPIO_STRENGTH_ULTRA
651 * @retval None
652 */
653 __STATIC_INLINE void ll_aon_gpio_set_pin_strength(uint32_t pin_mask, uint32_t strength)
654 {
655 uint8_t ds0 = (strength & LL_AON_GPIO_STRENGTH_DS0_MASK) >> LL_AON_GPIO_STRENGTH_DS0_POS;
656 uint8_t ds1 = (strength & LL_AON_GPIO_STRENGTH_DS1_MASK) >> LL_AON_GPIO_STRENGTH_DS1_POS;
657 if(ds0)
658 {
659 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS , pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS);
660 }
661 else
662 {
663 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS , 0);
664 }
665 if(ds1)
666 {
667 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS , pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS);
668 }
669 else
670 {
671 MODIFY_REG(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS , 0);
672 }
673 }
674
675 /**
676 * @brief Return output strength for a dedicated AON_GPIO pin.
677 * @note Warning: only one pin can be passed as parameter.
678 *
679 * Register|BitsName
680 * --------|--------
681 * AON_PAD_CTL3 | DS0
682 * AON_PAD_CTL3 | DS1
683 *
684 * @param pin_mask This parameter can be one of the following values:
685 * @arg @ref LL_AON_GPIO_PIN_0
686 * @arg @ref LL_AON_GPIO_PIN_1
687 * @arg @ref LL_AON_GPIO_PIN_2
688 * @arg @ref LL_AON_GPIO_PIN_3
689 * @arg @ref LL_AON_GPIO_PIN_4
690 * @arg @ref LL_AON_GPIO_PIN_5
691 * @arg @ref LL_AON_GPIO_PIN_6
692 * @arg @ref LL_AON_GPIO_PIN_7
693 * @retval Returned value can be one of the following values:
694 * @arg @ref LL_AON_GPIO_STRENGTH_LOW
695 * @arg @ref LL_AON_GPIO_STRENGTH_MEDIUM
696 * @arg @ref LL_AON_GPIO_STRENGTH_HIGH
697 * @arg @ref LL_AON_GPIO_STRENGTH_ULTRA
698 */
699 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_strength(uint32_t pin_mask)
700 {
701 uint32_t pos;
702 pos = POSITION_VAL(pin_mask);
703 uint8_t ds0 = READ_BITS(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS0_POS ) >> AON_IO_AON_PAD_CTRL3_DS0_POS >> pos;
704 uint8_t ds1 = READ_BITS(AON_IO->AON_PAD_CTRL3, pin_mask << AON_IO_AON_PAD_CTRL3_DS1_POS ) >> AON_IO_AON_PAD_CTRL3_DS1_POS >> pos;
705 return ((ds0 << LL_AON_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_AON_GPIO_STRENGTH_DS1_POS));
706 }
707
708 /**
709 * @brief Enable clock output on AON_GPIO_PIN4.
710 *
711 * Register|BitsName
712 * --------|--------
713 * AON_PAD_CLK | AON_PAD_CLK
714 *
715 * @param clk_sel This parameter can be the following values:
716 * @arg @ref LL_CLK_RNG_OSC_32K
717 * @arg @ref LL_CLK_RNG_OSC_250K
718 * @arg @ref LL_CLK_RC_OSC_CLK
719 * @arg @ref LL_CLK_RTC_CLK
720 * @retval None
721 */
722 __STATIC_INLINE void ll_aon_gpio4_enable_clk_output(uint32_t clk_sel)
723 {
724 MODIFY_REG(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
725 AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
726 }
727
728 /**
729 * @brief Disable clock output on AON_GPIO_PIN4.
730 *
731 * Register|BitsName
732 * --------|--------
733 * AON_PAD_CLK | AON_PAD_CLK
734 *
735 * @retval None
736 */
737 __STATIC_INLINE void ll_aon_gpio4_disable_clk_output(void)
738 {
739 CLEAR_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
740 }
741
742 /**
743 * @brief Check if clock output on AON_GPIO_PIN4 is enabled or disabled.
744 *
745 * Register|BitsName
746 * --------|--------
747 * AON_PAD_CLK | AON_PAD_CLK
748 *
749 * @retval State of bit (1 or 0).
750 */
751 __STATIC_INLINE uint32_t ll_aon_gpio4_is_enabled_clk_output(void)
752 {
753 return (READ_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
754 }
755
756 /**
757 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
758 *
759 * Register|BitsName
760 * --------|--------
761 * PWR_RET01 | XO_2MHZ_ENA
762 *
763 * @retval None
764 */
765 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
766 {
767 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
768 }
769
770 /**
771 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
772 *
773 * Register|BitsName
774 * --------|--------
775 * PWR_RET01 | XO_2MHZ_ENA
776 *
777 * @retval None
778 */
779 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
780 {
781 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
782 }
783
784 /**
785 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
786 *
787 * Register|BitsName
788 * --------|--------
789 * PWR_RET01 | XO_2MHZ_ENA
790 *
791 * @retval None
792 */
793 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
794 {
795 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
796 }
797
798 /** @} */
799
800 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
801 * @{
802 */
803
804 /**
805 * @brief Return full input data register value of AON_GPIO.
806 *
807 * Register|BitsName
808 * --------|--------
809 * AON_PAD_CTL1 | IN_VAL
810 *
811 * @retval Input data register value of port
812 */
813 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
814 {
815 uint32_t pin_mask = (LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
816 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) >> AON_IO_AON_PAD_CTRL1_IN_VAL_POS);
817 }
818
819 /**
820 * @brief Return if input data level of several AON_GPIO pins is high or low.
821 *
822 * Register|BitsName
823 * --------|--------
824 * AON_PAD_CTL1 | IN_VAL
825 *
826 * @param pin_mask This parameter can be a combination of the following values:
827 * @arg @ref LL_AON_GPIO_PIN_0
828 * @arg @ref LL_AON_GPIO_PIN_1
829 * @arg @ref LL_AON_GPIO_PIN_2
830 * @arg @ref LL_AON_GPIO_PIN_3
831 * @arg @ref LL_AON_GPIO_PIN_4
832 * @arg @ref LL_AON_GPIO_PIN_5
833 * @arg @ref LL_AON_GPIO_PIN_6
834 * @arg @ref LL_AON_GPIO_PIN_7
835 * @arg @ref LL_AON_GPIO_PIN_ALL
836 * @retval State of bit (1 or 0).
837 */
838 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_pin(uint32_t pin_mask)
839 {
840 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
841 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
842 }
843
844 /**
845 * @brief Return if output data level of several AON_GPIO pins is high or low.
846 *
847 * Register|BitsName
848 * --------|--------
849 * AON_PAD_CTL1 | AON_GPIO
850 *
851 * @param pin_mask This parameter can be a combination of the following values:
852 * @arg @ref LL_AON_GPIO_PIN_0
853 * @arg @ref LL_AON_GPIO_PIN_1
854 * @arg @ref LL_AON_GPIO_PIN_2
855 * @arg @ref LL_AON_GPIO_PIN_3
856 * @arg @ref LL_AON_GPIO_PIN_4
857 * @arg @ref LL_AON_GPIO_PIN_5
858 * @arg @ref LL_AON_GPIO_PIN_6
859 * @arg @ref LL_AON_GPIO_PIN_7
860 * @arg @ref LL_AON_GPIO_PIN_ALL
861 * @retval State of bit (1 or 0).
862 */
863 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_pin(uint32_t pin_mask)
864 {
865 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
866 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
867 }
868
869 /**
870 * @brief Write output data register of AON_GPIO.
871 *
872 * Register|BitsName
873 * --------|--------
874 * AON_PAD_CTL1 | AON_GPO
875 *
876 * @param port_value Level value for each pin of the port
877 * @retval None
878 */
879 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
880 {
881 MODIFY_REG(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL, (port_value << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
882 }
883
884 /**
885 * @brief Return full output data register value of AON_GPIO.
886 *
887 * Register|BitsName
888 * --------|--------
889 * AON_PAD_CTL1 | AON_GPO
890 *
891 * @retval Output data register value of port
892 */
893 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
894 {
895 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL) >> AON_IO_AON_PAD_CTRL1_OUT_VAL_POS);
896 }
897
898 /**
899 * @brief Return if input data level of several AON_GPIO pins is high or low.
900 *
901 * Register|BitsName
902 * --------|--------
903 * AON_PAD_CTL1 | AON_GPO
904 *
905 * @param pin_mask This parameter can be a combination of the following values:
906 * @arg @ref LL_AON_GPIO_PIN_0
907 * @arg @ref LL_AON_GPIO_PIN_1
908 * @arg @ref LL_AON_GPIO_PIN_2
909 * @arg @ref LL_AON_GPIO_PIN_3
910 * @arg @ref LL_AON_GPIO_PIN_4
911 * @arg @ref LL_AON_GPIO_PIN_5
912 * @arg @ref LL_AON_GPIO_PIN_6
913 * @arg @ref LL_AON_GPIO_PIN_7
914 * @arg @ref LL_AON_GPIO_PIN_ALL
915 * @retval State of bit (1 or 0).
916 */
917 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
918 {
919 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
920 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
921 }
922
923 /**
924 * @brief Set specified AON_GPIO pins to high level
925 *
926 * Register|BitsName
927 * --------|--------
928 * AON_PAD_CTL1 | AON_GPO
929 *
930 * @param pin_mask This parameter can be a combination of the following values:
931 * @arg @ref LL_AON_GPIO_PIN_0
932 * @arg @ref LL_AON_GPIO_PIN_1
933 * @arg @ref LL_AON_GPIO_PIN_2
934 * @arg @ref LL_AON_GPIO_PIN_3
935 * @arg @ref LL_AON_GPIO_PIN_4
936 * @arg @ref LL_AON_GPIO_PIN_5
937 * @arg @ref LL_AON_GPIO_PIN_6
938 * @arg @ref LL_AON_GPIO_PIN_7
939 * @arg @ref LL_AON_GPIO_PIN_ALL
940 * @retval None
941 */
942 __STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
943 {
944 SET_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
945 }
946
947 /**
948 * @brief Set specified AON_GPIO pins to low level.
949 *
950 * Register|BitsName
951 * --------|--------
952 * AON_PAD_CTL1 | AON_GPO
953 *
954 * @param pin_mask This parameter can be a combination of the following values:
955 * @arg @ref LL_AON_GPIO_PIN_0
956 * @arg @ref LL_AON_GPIO_PIN_1
957 * @arg @ref LL_AON_GPIO_PIN_2
958 * @arg @ref LL_AON_GPIO_PIN_3
959 * @arg @ref LL_AON_GPIO_PIN_4
960 * @arg @ref LL_AON_GPIO_PIN_5
961 * @arg @ref LL_AON_GPIO_PIN_6
962 * @arg @ref LL_AON_GPIO_PIN_7
963 * @arg @ref LL_AON_GPIO_PIN_ALL
964 * @retval None
965 */
966 __STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
967 {
968 CLEAR_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
969 }
970
971 /**
972 * @brief Toggle data value of specified AON_GPIO pins.
973 *
974 * Register|BitsName
975 * --------|--------
976 * AON_PAD_CTL1 | AON_GPO
977 *
978 * @param pin_mask This parameter can be a combination of the following values:
979 * @arg @ref LL_AON_GPIO_PIN_0
980 * @arg @ref LL_AON_GPIO_PIN_1
981 * @arg @ref LL_AON_GPIO_PIN_2
982 * @arg @ref LL_AON_GPIO_PIN_3
983 * @arg @ref LL_AON_GPIO_PIN_4
984 * @arg @ref LL_AON_GPIO_PIN_5
985 * @arg @ref LL_AON_GPIO_PIN_6
986 * @arg @ref LL_AON_GPIO_PIN_7
987 * @arg @ref LL_AON_GPIO_PIN_ALL
988 * @retval None
989 */
990 __STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
991 {
992 WRITE_REG(AON_IO->AON_PAD_CTRL1, (READ_REG(AON_IO->AON_PAD_CTRL1)
993 ^ ((pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL)));
994 }
995
996 /** @} */
997
998 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
1004 *
1005 * Register|BitsName
1006 * --------|--------
1007 * INTPOLCLR | INTPOLCLR
1008 * INTTYPESET | INTTYPESET
1009 *
1010 * @param pin_mask This parameter can be a combination of the following values:
1011 * @arg @ref LL_AON_GPIO_PIN_0
1012 * @arg @ref LL_AON_GPIO_PIN_1
1013 * @arg @ref LL_AON_GPIO_PIN_2
1014 * @arg @ref LL_AON_GPIO_PIN_3
1015 * @arg @ref LL_AON_GPIO_PIN_4
1016 * @arg @ref LL_AON_GPIO_PIN_5
1017 * @arg @ref LL_AON_GPIO_PIN_6
1018 * @arg @ref LL_AON_GPIO_PIN_7
1019 * @arg @ref LL_AON_GPIO_PIN_ALL
1020 * @retval None
1021 */
1022 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
1023 {
1024 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1025 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1026 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1027 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1028 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1029 MODIFY_REG(AON_CTL->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
1030 }
1031
1032 /**
1033 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * INTPOLCLR | INTPOLCLR
1038 * INTTYPESET | INTTYPESET
1039 *
1040 * @param pin_mask This parameter can be a combination of the following values:
1041 * @arg @ref LL_AON_GPIO_PIN_0
1042 * @arg @ref LL_AON_GPIO_PIN_1
1043 * @arg @ref LL_AON_GPIO_PIN_2
1044 * @arg @ref LL_AON_GPIO_PIN_3
1045 * @arg @ref LL_AON_GPIO_PIN_4
1046 * @arg @ref LL_AON_GPIO_PIN_5
1047 * @arg @ref LL_AON_GPIO_PIN_6
1048 * @arg @ref LL_AON_GPIO_PIN_7
1049 * @arg @ref LL_AON_GPIO_PIN_ALL
1050 * @retval State of bit (1 or 0)
1051 */
1052 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
1053 {
1054 uint32_t invert = ((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1055 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1056 uint32_t edge_type = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1057 return (invert && edge_en && edge_type);
1058 }
1059
1060 /**
1061 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
1062 *
1063 * Register|BitsName
1064 * --------|--------
1065 * INTPOLSET | INTPOLSET
1066 * INTTYPESET | INTTYPESET
1067 *
1068 * @param pin_mask This parameter can be a combination of the following values:
1069 * @arg @ref LL_AON_GPIO_PIN_0
1070 * @arg @ref LL_AON_GPIO_PIN_1
1071 * @arg @ref LL_AON_GPIO_PIN_2
1072 * @arg @ref LL_AON_GPIO_PIN_3
1073 * @arg @ref LL_AON_GPIO_PIN_4
1074 * @arg @ref LL_AON_GPIO_PIN_5
1075 * @arg @ref LL_AON_GPIO_PIN_6
1076 * @arg @ref LL_AON_GPIO_PIN_7
1077 * @arg @ref LL_AON_GPIO_PIN_ALL
1078 * @retval None
1079 */
1080 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
1081 {
1082 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1083 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1084 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1085 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1086 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1087 MODIFY_REG(AON_CTL->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
1088 }
1089
1090 /**
1091 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
1092 * @note Please check each device line mapping for AON_GPIO Line availability
1093 *
1094 * Register|BitsName
1095 * --------|--------
1096 * INTPOLSET | INTPOLSET
1097 * INTTYPESET | INTTYPESET
1098 *
1099 * @param pin_mask This parameter can be a combination of the following values:
1100 * @arg @ref LL_AON_GPIO_PIN_0
1101 * @arg @ref LL_AON_GPIO_PIN_1
1102 * @arg @ref LL_AON_GPIO_PIN_2
1103 * @arg @ref LL_AON_GPIO_PIN_3
1104 * @arg @ref LL_AON_GPIO_PIN_4
1105 * @arg @ref LL_AON_GPIO_PIN_5
1106 * @arg @ref LL_AON_GPIO_PIN_6
1107 * @arg @ref LL_AON_GPIO_PIN_7
1108 * @arg @ref LL_AON_GPIO_PIN_ALL
1109 * @retval State of bit (1 or 0).
1110 */
1111 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
1112 {
1113 uint32_t invert = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1114 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1115 uint32_t edge_type = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1116 return (invert && edge_en && edge_type);
1117 }
1118
1119 /**
1120 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
1121 *
1122 * Register|BitsName
1123 * --------|--------
1124 * INTPOLSET | INTPOLSET
1125 * INTTYPECLR | INTTYPECLR
1126 *
1127 * @param pin_mask This parameter can be a combination of the following values:
1128 * @arg @ref LL_AON_GPIO_PIN_0
1129 * @arg @ref LL_AON_GPIO_PIN_1
1130 * @arg @ref LL_AON_GPIO_PIN_2
1131 * @arg @ref LL_AON_GPIO_PIN_3
1132 * @arg @ref LL_AON_GPIO_PIN_4
1133 * @arg @ref LL_AON_GPIO_PIN_5
1134 * @arg @ref LL_AON_GPIO_PIN_6
1135 * @arg @ref LL_AON_GPIO_PIN_7
1136 * @arg @ref LL_AON_GPIO_PIN_ALL
1137 * @retval None
1138 */
1139 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
1140 {
1141 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1142 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1143 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1144 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en);
1145 }
1146
1147 /**
1148 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
1149 *
1150 * Register|BitsName
1151 * --------|--------
1152 * INTPOLSET | INTPOLSET
1153 * INTTYPECLR | INTTYPECLR
1154 *
1155 * @param pin_mask This parameter can be a combination of the following values:
1156 * @arg @ref LL_AON_GPIO_PIN_0
1157 * @arg @ref LL_AON_GPIO_PIN_1
1158 * @arg @ref LL_AON_GPIO_PIN_2
1159 * @arg @ref LL_AON_GPIO_PIN_3
1160 * @arg @ref LL_AON_GPIO_PIN_4
1161 * @arg @ref LL_AON_GPIO_PIN_5
1162 * @arg @ref LL_AON_GPIO_PIN_6
1163 * @arg @ref LL_AON_GPIO_PIN_7
1164 * @arg @ref LL_AON_GPIO_PIN_ALL
1165 * @retval State of bit (1 or 0).
1166 */
1167 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
1168 {
1169 uint32_t invert = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1170 uint32_t edge_en = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1171 return (invert && edge_en );
1172 }
1173
1174 /**
1175 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
1176 *
1177 * Register|BitsName
1178 * --------|--------
1179 * INTPOLCLR | INTPOLCLR
1180 * INTTYPECLR | INTTYPECLR
1181 *
1182 * @param pin_mask This parameter can be a combination of the following values:
1183 * @arg @ref LL_AON_GPIO_PIN_0
1184 * @arg @ref LL_AON_GPIO_PIN_1
1185 * @arg @ref LL_AON_GPIO_PIN_2
1186 * @arg @ref LL_AON_GPIO_PIN_3
1187 * @arg @ref LL_AON_GPIO_PIN_4
1188 * @arg @ref LL_AON_GPIO_PIN_5
1189 * @arg @ref LL_AON_GPIO_PIN_6
1190 * @arg @ref LL_AON_GPIO_PIN_7
1191 * @arg @ref LL_AON_GPIO_PIN_ALL
1192 * @retval None
1193 */
1194 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
1195 {
1196 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1197 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1198 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL0, invert);
1199 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en);
1200 }
1201
1202 /**
1203 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
1204 *
1205 * Register|BitsName
1206 * --------|--------
1207 * INTPOLCLR | INTPOLCLR
1208 * INTTYPECLR | INTTYPECLR
1209 *
1210 * @param pin_mask This parameter can be a combination of the following values:
1211 * @arg @ref LL_AON_GPIO_PIN_0
1212 * @arg @ref LL_AON_GPIO_PIN_1
1213 * @arg @ref LL_AON_GPIO_PIN_2
1214 * @arg @ref LL_AON_GPIO_PIN_3
1215 * @arg @ref LL_AON_GPIO_PIN_4
1216 * @arg @ref LL_AON_GPIO_PIN_5
1217 * @arg @ref LL_AON_GPIO_PIN_6
1218 * @arg @ref LL_AON_GPIO_PIN_7
1219 * @arg @ref LL_AON_GPIO_PIN_ALL
1220 * @retval State of bit (1 or 0).
1221 */
1222 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
1223 {
1224 uint32_t invert = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1225 uint32_t edge_en = (((~READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1226 return (invert && edge_en);
1227 }
1228
1229 /**
1230 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
1231 *
1232 * Register|BitsName
1233 * --------|--------
1234 * INTPOLCLR | INTPOLCLR
1235 * INTTYPECLR | INTTYPECLR
1236 *
1237 * @param pin_mask This parameter can be a combination of the following values:
1238 * @arg @ref LL_AON_GPIO_PIN_0
1239 * @arg @ref LL_AON_GPIO_PIN_1
1240 * @arg @ref LL_AON_GPIO_PIN_2
1241 * @arg @ref LL_AON_GPIO_PIN_3
1242 * @arg @ref LL_AON_GPIO_PIN_4
1243 * @arg @ref LL_AON_GPIO_PIN_5
1244 * @arg @ref LL_AON_GPIO_PIN_6
1245 * @arg @ref LL_AON_GPIO_PIN_7
1246 * @arg @ref LL_AON_GPIO_PIN_ALL
1247 * @retval None
1248 */
1249 __STATIC_INLINE void ll_aon_gpio_enable_both_trigger(uint32_t pin_mask)
1250 {
1251 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1252 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1253 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL1, edge_en | both);
1254 }
1255
1256 /**
1257 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
1258 *
1259 * Register|BitsName
1260 * --------|--------
1261 * INTPOLCLR | INTPOLCLR
1262 * INTTYPECLR | INTTYPECLR
1263 *
1264 * @param pin_mask This parameter can be a combination of the following values:
1265 * @arg @ref LL_AON_GPIO_PIN_0
1266 * @arg @ref LL_AON_GPIO_PIN_1
1267 * @arg @ref LL_AON_GPIO_PIN_2
1268 * @arg @ref LL_AON_GPIO_PIN_3
1269 * @arg @ref LL_AON_GPIO_PIN_4
1270 * @arg @ref LL_AON_GPIO_PIN_5
1271 * @arg @ref LL_AON_GPIO_PIN_6
1272 * @arg @ref LL_AON_GPIO_PIN_7
1273 * @arg @ref LL_AON_GPIO_PIN_ALL
1274 * @retval State of bit (1 or 0)
1275 */
1276 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_both_trigger(uint32_t pin_mask)
1277 {
1278 uint32_t edge_en = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1279 uint32_t edge_both = ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1280 return ( edge_en && edge_both);
1281 }
1282
1283 /**
1284 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
1285 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1286 *
1287 * Register|BitsName
1288 * --------|--------
1289 * INTENSET | INTENSET
1290 *
1291 * @param pin_mask This parameter can be a combination of the following values:
1292 * @arg @ref LL_AON_GPIO_PIN_0
1293 * @arg @ref LL_AON_GPIO_PIN_1
1294 * @arg @ref LL_AON_GPIO_PIN_2
1295 * @arg @ref LL_AON_GPIO_PIN_3
1296 * @arg @ref LL_AON_GPIO_PIN_4
1297 * @arg @ref LL_AON_GPIO_PIN_5
1298 * @arg @ref LL_AON_GPIO_PIN_6
1299 * @arg @ref LL_AON_GPIO_PIN_7
1300 * @arg @ref LL_AON_GPIO_PIN_ALL
1301 * @retval None
1302 */
1303 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
1304 {
1305 SET_BITS(AON_CTL->EXT_WAKEUP_CTRL0, pin_mask);
1306 }
1307
1308 /**
1309 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
1310 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1311 *
1312 * Register|BitsName
1313 * --------|--------
1314 * INTENCLR | INTENCLR
1315 *
1316 * @param pin_mask This parameter can be a combination of the following values:
1317 * @arg @ref LL_AON_GPIO_PIN_0
1318 * @arg @ref LL_AON_GPIO_PIN_1
1319 * @arg @ref LL_AON_GPIO_PIN_2
1320 * @arg @ref LL_AON_GPIO_PIN_3
1321 * @arg @ref LL_AON_GPIO_PIN_4
1322 * @arg @ref LL_AON_GPIO_PIN_5
1323 * @arg @ref LL_AON_GPIO_PIN_6
1324 * @arg @ref LL_AON_GPIO_PIN_7
1325 * @arg @ref LL_AON_GPIO_PIN_ALL
1326 * @retval None
1327 */
1328 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
1329 {
1330 CLEAR_BITS(AON_CTL->EXT_WAKEUP_CTRL0, pin_mask);
1331 }
1332
1333 /**
1334 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1335 *
1336 * Register|BitsName
1337 * --------|--------
1338 * INTENSET | INTENSET
1339 *
1340 * @param pin_mask This parameter can be a combination of the following values:
1341 * @arg @ref LL_AON_GPIO_PIN_0
1342 * @arg @ref LL_AON_GPIO_PIN_1
1343 * @arg @ref LL_AON_GPIO_PIN_2
1344 * @arg @ref LL_AON_GPIO_PIN_3
1345 * @arg @ref LL_AON_GPIO_PIN_4
1346 * @arg @ref LL_AON_GPIO_PIN_5
1347 * @arg @ref LL_AON_GPIO_PIN_6
1348 * @arg @ref LL_AON_GPIO_PIN_7
1349 * @arg @ref LL_AON_GPIO_PIN_ALL
1350 * @retval State of bit (1 or 0).
1351 */
1352 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1353 {
1354 return ((READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1355 }
1356
1357 /**
1358 * @brief Get aon gpio enable pins.
1359 *
1360 * Register|BitsName
1361 * --------|--------
1362 * INTENSET | INTENSET
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_AON_GPIO_PIN_0
1365 * @arg @ref LL_AON_GPIO_PIN_1
1366 * @arg @ref LL_AON_GPIO_PIN_2
1367 * @arg @ref LL_AON_GPIO_PIN_3
1368 * @arg @ref LL_AON_GPIO_PIN_4
1369 * @arg @ref LL_AON_GPIO_PIN_5
1370 * @arg @ref LL_AON_GPIO_PIN_6
1371 * @arg @ref LL_AON_GPIO_PIN_7
1372 * @arg @ref LL_AON_GPIO_PIN_ALL
1373 */
1374 __STATIC_INLINE uint32_t ll_aon_gpio_get_enabled_pin(void)
1375 {
1376 return (READ_BITS(AON_CTL->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1377 }
1378
1379 /**
1380 * @brief Check if the AON_GPIO master interrupt is enabled or disabled.
1381 *
1382 * Register|BitsName
1383 * --------|--------
1384 * AON_MISC | MCU_WAKEUP_CTRL
1385 * @retval State of bit (1 or 0).
1386 */
1387 __STATIC_INLINE uint32_t ll_aon_gpio_is_enable_wakeup_it(void)
1388 {
1389 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_EXT) == (AON_CTL_MCU_WAKEUP_CTRL_EXT));
1390 }
1391
1392 /** @} */
1393
1394 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
1395 * @{
1396 */
1397
1398 /**
1399 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
1400 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1401 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1402 *
1403 * Register|BitsName
1404 * --------|--------
1405 * INTSTATUS | INTSTATUS
1406 *
1407 * @param pin_mask This parameter can be a combination of the following values:
1408 * @arg @ref LL_AON_GPIO_PIN_0
1409 * @arg @ref LL_AON_GPIO_PIN_1
1410 * @arg @ref LL_AON_GPIO_PIN_2
1411 * @arg @ref LL_AON_GPIO_PIN_3
1412 * @arg @ref LL_AON_GPIO_PIN_4
1413 * @arg @ref LL_AON_GPIO_PIN_5
1414 * @arg @ref LL_AON_GPIO_PIN_6
1415 * @arg @ref LL_AON_GPIO_PIN_7
1416 * @arg @ref LL_AON_GPIO_PIN_ALL
1417 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1418 */
1419 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1420 {
1421 return (READ_BITS(AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1422 }
1423
1424 /**
1425 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1426 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1427 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1428 *
1429 * Register|BitsName
1430 * --------|--------
1431 * INTSTATUS | INTSTATUS
1432 *
1433 * @param pin_mask This parameter can be a combination of the following values:
1434 * @arg @ref LL_AON_GPIO_PIN_0
1435 * @arg @ref LL_AON_GPIO_PIN_1
1436 * @arg @ref LL_AON_GPIO_PIN_2
1437 * @arg @ref LL_AON_GPIO_PIN_3
1438 * @arg @ref LL_AON_GPIO_PIN_4
1439 * @arg @ref LL_AON_GPIO_PIN_5
1440 * @arg @ref LL_AON_GPIO_PIN_6
1441 * @arg @ref LL_AON_GPIO_PIN_7
1442 * @arg @ref LL_AON_GPIO_PIN_ALL
1443 * @retval State of bit (1 or 0).
1444 */
1445 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1446 {
1447 return ((READ_BITS(AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1448 }
1449
1450 /**
1451 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1452 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1453 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1454 *
1455 * Register|BitsName
1456 * --------|--------
1457 * INTSTATUS | INTSTATUS
1458 *
1459 * @param pin_mask This parameter can be a combination of the following values:
1460 * @arg @ref LL_AON_GPIO_PIN_0
1461 * @arg @ref LL_AON_GPIO_PIN_1
1462 * @arg @ref LL_AON_GPIO_PIN_2
1463 * @arg @ref LL_AON_GPIO_PIN_3
1464 * @arg @ref LL_AON_GPIO_PIN_4
1465 * @arg @ref LL_AON_GPIO_PIN_5
1466 * @arg @ref LL_AON_GPIO_PIN_6
1467 * @arg @ref LL_AON_GPIO_PIN_7
1468 * @arg @ref LL_AON_GPIO_PIN_ALL
1469 * @retval None
1470 */
1471 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1472 {
1473 CLEAR_BITS(AON_CTL->EXT_WAKEUP_STAT, pin_mask);
1474 }
1475
1476 /**
1477 * @brief Indicate if the AON GPIO event flag is set or not.
1478 * @note This bit is set by hardware when system wakeup by AON GPIO.
1479 * It can be cleared by writing 0 to this bit.
1480 *
1481 * Register|BitsName
1482 * --------|--------
1483 * SLP_EVENT | AON GPIO
1484 *
1485 * @retval State of bit (1 or 0).
1486 */
1487 __STATIC_INLINE uint32_t ll_aon_gpio_read_event_flag_it(void)
1488 {
1489 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1490 }
1491
1492 /**
1493 * @brief Clear AON GPIO event interrupt flag.
1494 *
1495 * Register|BitsName
1496 * --------|--------
1497 * SLP_EVENT| AON GPIO
1498 *
1499 * @retval None
1500 */
1501 __STATIC_INLINE void ll_aon_gpio_clear_event_flag_it(void)
1502 {
1503 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);
1504 }
1505
1506 /** @} */
1507
1508 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1509 * @{
1510 */
1511 /**
1512 * @brief Initialize AON_GPIO registers according to the specified.
1513 * parameters in p_aon_gpio_init.
1514 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1515 * information for the specified AON_GPIO peripheral.
1516 * @retval An error_status_t enumeration value:
1517 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1518 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1519 */
1520 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1521
1522 /** @} */
1523
1524 /** @} */
1525
1526 #endif /* AON */
1527
1528 #ifdef __cplusplus
1529 }
1530 #endif
1531
1532 #endif /* __GR533X_LL_AON_GPIO_H__ */
1533
1534 /** @} */
1535
1536 /** @} */
1537
1538 /** @} */