gr533x_ll_ddvs.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_ddvs.h
5 * @author BLE RD
6 * @brief Header file containing functions prototypes of DDVS LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DDVS LL Clock Calibration
47 * @brief CLOCK CALIBRATION LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_DDVS_H_
53 #define __GR533X_LL_DDVS_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_hal.h"
61
62 /**
63 * @defgroup DDVS_LL_MACRO Defines
64 * @{
65 */
66 /** @defgroup DDVS_ENABLE Mode defines
67 * @{
68 */
69 #define LL_DDVS_DIS (0U) /**< DDVS Disable(default) */
70 #define LL_DDVS_EN (1U) /**< DDVS Enable */
71 /** @} */
72
73 /** @defgroup DDVS_MODE Mode defines
74 * @{
75 */
76 #define LL_DDVS_AUTO_MODE (0U) /**< DDVS Auto Mode(default) */
77 #define LL_DDVS_MALNUAL_MODE (1U) /**< DDVS Manual Mode */
78 /** @} */
79
80 /** @defgroup DDVS_RINGO Mode defines
81 * @{
82 */
83 #define LL_DDVS_RINGO_0_EN (1<<0U) /**< DDVS Ringo_0 Enable */
84 #define LL_DDVS_RINGO_1_EN (1<<1U) /**< DDVS Ringo_1 Enable */
85 #define LL_DDVS_RINGO_2_EN (1<<2U) /**< DDVS Ringo_2 Enable */
86 #define LL_DDVS_RINGO_3_EN (1<<3U) /**< DDVS Ringo_3 Enable */
87 #define LL_DDVS_RINGO_ALL_EN (0xFU) /**< DDVS All Ringos Enable */
88 #define LL_DDVS_RINGO_ALL_DIS (0x0U) /**< DDVS All Ringos Disable */
89 /** @} */
90
91 /** @defgroup DDVS_DIVIDE_FACTOR Divide factor defines
92 * @{
93 */
94 #define LL_DDVS_DIVIDE_FACTOR_8K (0U) /**< DDVS div_factor 8k */
95 #define LL_DDVS_DIVIDE_FACTOR_4K (1U) /**< DDVS div_factor 4k */
96 #define LL_DDVS_DIVIDE_FACTOR_16K (2U) /**< DDVS div_factor 16k */
97 /** @} */
98
99 /** @defgroup DDVS_CLOCK_SEL Clock Selection defines
100 * @{
101 */
102 #define LL_DDVS_CLK_SEL_XO_32M (0U) /**< DDVS Clock Select XO_32M */
103 #define LL_DDVS_CLK_SEL_XO_16M (1U) /**< DDVS Clock Select XO_16M */
104 #define LL_DDVS_CLK_SEL_SYS_32M (2U) /**< DDVS Clock Select SYS_32M */
105 #define LL_DDVS_CLK_SEL_SYS_16M (3U) /**< DDVS Clock Select SYS_16M */
106 /** @} */
107
108 /** @defgroup DDVS_CLOCK_SWITCH Mode defines
109 * @{
110 */
111 #define LL_DDVS_CLK_DIS (0U) /**< DDVS Clock Disable(default) */
112 #define LL_DDVS_CLK_EN (1U) /**< DDVS Clock Enable */
113 /** @} */
114
115 /** @} */
116
117 /** @defgroup DDVS_LL_DRIVER_FUNCTIONS Functions
118 * @{
119 */
120 /**
121 * @brief Enable the DDVS block
122 *
123 * Register|BitsName
124 * --------|--------
125 * DDVS_EN | CONF_DDVS_EN
126 */
127 __STATIC_INLINE void ll_ddvs_enable_set(uint8_t enable)
128 {
129 MODIFY_REG(DDVS_CTRL->DDVS_EN, DDVS_CTRL_CONF_DDVS_EN, (enable << DDVS_CTRL_CONF_DDVS_EN_POS));
130 }
131
132 /**
133 * @brief DDVS block enable state get
134 *
135 * Register|BitsName
136 * --------|--------
137 * DDVS_EN | CONF_DDVS_EN
138 */
139 __STATIC_INLINE uint8_t ll_ddvs_enable_get(void)
140 {
141 return ((READ_BITS(DDVS_CTRL->DDVS_EN, DDVS_CTRL_CONF_DDVS_EN)) >> DDVS_CTRL_CONF_DDVS_EN_POS);
142 }
143
144 /**
145 * @brief DDVS mode set
146 * 0b - DDVS automatic mode (default)
147 * 1b - DDVS manual mode
148 * Register|BitsName
149 * --------|--------
150 * DDVS_CFG_1 | CONF_DDVS_MODE
151 */
152 __STATIC_INLINE void ll_ddvs_mode_set(uint8_t mode)
153 {
154 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE, (mode<<DDVS_CFG_1_CONF_DDVS_MODE_POS));
155 }
156
157 /**
158 * @brief DDVS mode get
159 * 0b - DDVS automatic mode (default)
160 * 1b - DDVS manual mode
161 * Register|BitsName
162 * --------|--------
163 * DDVS_CFG_1 | CONF_DDVS_MODE
164 */
165 __STATIC_INLINE uint8_t ll_ddvs_mode_get(void)
166 {
167 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE)) >> DDVS_CFG_1_CONF_DDVS_MODE_POS);
168 }
169
170 /**
171 * @brief DDVS Slow threshold(limit for ringo goes bigger) set
172 * This is the limitation of ringo being bigger than target_cnt
173 * Register|BitsName
174 * --------|--------
175 * DDVS_CFG_1 | CONF_THRESHOLD_SLOW
176 */
177 __STATIC_INLINE void ll_ddvs_slow_threshold_set(uint16_t threshold)
178 {
179 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_THRESHOLD_SLOW, (threshold<<DDVS_CFG_1_CONF_THRESHOLD_SLOW_POS));
180 }
181
182 /**
183 * @brief DDVS Slow threshold(limit for ringo goes bigger) get
184 * This is the limitation of ringo being bigger than target_cnt
185 * Register|BitsName
186 * --------|--------
187 * DDVS_CFG_1 | CONF_THRESHOLD_SLOW
188 */
189 __STATIC_INLINE uint16_t ll_ddvs_slow_threshold_get(void)
190 {
191 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_THRESHOLD_SLOW)) >> DDVS_CFG_1_CONF_THRESHOLD_SLOW_POS);
192 }
193
194 /**
195 * @brief DDVS Target count set
196 *
197 * Register|BitsName
198 * --------|--------
199 * DDVS_CFG_2 | CONF_TARGET_CNT
200 */
201 __STATIC_INLINE void ll_ddvs_target_cnt_set(uint16_t target_cnt)
202 {
203 MODIFY_REG(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_TARGET_CNT, (target_cnt<<DDVS_CFG_2_CONF_TARGET_CNT_POS));
204 }
205
206 /**
207 * @brief DDVS Target count get
208 *
209 * Register|BitsName
210 * --------|--------
211 * DDVS_CFG_2 | CONF_TARGET_CNT
212 */
213 __STATIC_INLINE uint16_t ll_ddvs_target_cnt_get(void)
214 {
215 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_TARGET_CNT)) >> DDVS_CFG_2_CONF_TARGET_CNT_POS);
216 }
217
218 /**
219 * @brief DDVS Fast threshold set
220 * This is the limitation of ringo being smaller than target_cnt
221 * Register|BitsName
222 * --------|--------
223 * DDVS_CFG_2 | CONF_THRESHOLD_FAST
224 */
225 __STATIC_INLINE void ll_ddvs_fast_threshold_set(uint16_t threshold)
226 {
227 MODIFY_REG(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_THRESHOLD_FAST, (threshold<<DDVS_CFG_2_CONF_THRESHOLD_FAST_POS));
228 }
229
230 /**
231 * @brief DDVS Fast threshold get
232 * This is the limitation of ringo being smaller than target_cnt
233 * Register|BitsName
234 * --------|--------
235 * DDVS_CFG_2 | CONF_THRESHOLD_FAST
236 */
237 __STATIC_INLINE uint16_t ll_ddvs_fast_threshold_get(void)
238 {
239 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_2, DDVS_CFG_2_CONF_THRESHOLD_FAST)) >> DDVS_CFG_2_CONF_THRESHOLD_FAST_POS);
240 }
241
242 /**
243 * @brief DDVS Error interrupt enable
244 *
245 * Register|BitsName
246 * --------|--------
247 * DDVS_CFG_1 | ERR_INT
248 */
249 __STATIC_INLINE void ll_ddvs_err_int_enable(void)
250 {
251 SET_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_INT_EN);
252 }
253
254 /**
255 * @brief DDVS Error interrupt disable
256 *
257 * Register|BitsName
258 * --------|--------
259 * DDVS_CFG_1 | ERR_INT
260 */
261 __STATIC_INLINE void ll_ddvs_err_int_disable(void)
262 {
263 CLEAR_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_INT_EN);
264 }
265
266 /**
267 * @brief DDVS Error interrupt clear
268 * From Spec, the ddvs mode shall set to manual mode before clear the interrupt
269 * When the error happens, it means the target_cnt shall be increased
270 * Register|BitsName
271 * --------|--------
272 * DDVS_CFG_1 | ERR_INT
273 */
274 __STATIC_INLINE void ll_ddvs_err_int_clear(void)
275 {
276 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DDVS_MODE, (LL_DDVS_MALNUAL_MODE<<DDVS_CFG_1_CONF_DDVS_MODE_POS));
277 CLEAR_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_ERR_INT);
278 }
279
280 /**
281 * @brief DDVS Manual vref set
282 *
283 * Register|BitsName
284 * --------|--------
285 * DDVS_CFG_1 | CONF_VREF_MANUAL
286 */
287 __STATIC_INLINE void ll_ddvs_manual_vref_set(uint8_t vref)
288 {
289 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_VREF_MANUAL, (vref<<DDVS_CFG_1_CONF_VREF_MANUAL_POS));
290 }
291
292 /**
293 * @brief DDVS Manual vref get
294 *
295 * Register|BitsName
296 * --------|--------
297 * DDVS_CFG_1 | CONF_VREF_MANUAL
298 */
299 __STATIC_INLINE uint8_t ll_ddvs_manual_vref_get(void)
300 {
301 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_VREF_MANUAL))>>DDVS_CFG_1_CONF_VREF_MANUAL_POS);
302 }
303
304 /**
305 * @brief DDVS Ringo enable set
306 * 0000b - disable all 4 ringos (default)
307 * 0001b~1111b - enable corresponding ringos
308 * Register|BitsName
309 * --------|--------
310 * DDVS_CFG_1 | CONF_RINGO_EN
311 */
312 __STATIC_INLINE void ll_ddvs_ringo_en_set(uint8_t ringo_bits)
313 {
314 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_RINGO_EN, (ringo_bits<<DDVS_CFG_1_CONF_RINGO_EN_POS));
315 }
316
317 /**
318 * @brief DDVS Ringo enable get
319 * 0000b - disable all 4 ringos (default)
320 * 0001b~1111b - enable corresponding ringos
321 * Register|BitsName
322 * --------|--------
323 * DDVS_CFG_1 | CONF_RINGO_EN
324 */
325 __STATIC_INLINE uint8_t ll_ddvs_ringo_en_get(void)
326 {
327 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_RINGO_EN)) >> DDVS_CFG_1_CONF_RINGO_EN_POS);
328 }
329
330 /**
331 * @brief DDVS Ringo frequency divide factor set
332 * 00b - 8K (default)
333 * 01b - 4K
334 * 10b - 16K
335 * 11b - Reserved
336 * Register|BitsName
337 * --------|--------
338 * DDVS_CFG_1 | CONF_DIV_FACTOR
339 */
340 __STATIC_INLINE void ll_ddvs_div_factor_set(uint8_t factor)
341 {
342 MODIFY_REG(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DIV_FACTOR, (factor<<DDVS_CFG_1_CONF_DIV_FACTOR_POS));
343 }
344
345 /**
346 * @brief DDVS Ringo frequency divide factor get
347 * 00b - 8K (default)
348 * 01b - 4K
349 * 10b - 16K
350 * 11b - Reserved
351 * Register|BitsName
352 * --------|--------
353 * DDVS_CFG_1 | CONF_DIV_FACTOR
354 */
355 __STATIC_INLINE uint8_t ll_ddvs_div_factor_get(void)
356 {
357 return ((READ_BITS(DDVS_CTRL->DDVS_CFG_1, DDVS_CFG_1_CONF_DIV_FACTOR)) >> DDVS_CFG_1_CONF_DIV_FACTOR_POS);
358 }
359
360 /**
361 * @brief DDVS Ringo_0 count get
362 * Register|BitsName
363 * --------|--------
364 * DDVS_RINGO_CNT_01 | RINGO_0_CNT
365 */
366 __STATIC_INLINE uint16_t ll_ddvs_ringo_0_cnt_get(void)
367 {
368 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_01, DDVS_RINGO_CNT_01_RINGO_0_CNT)) >> DDVS_RINGO_CNT_01_RINGO_0_CNT_POS);
369 }
370
371 /**
372 * @brief DDVS Ringo_1 count get
373 * Register|BitsName
374 * --------|--------
375 * DDVS_RINGO_CNT_01 | RINGO_1_CNT
376 */
377 __STATIC_INLINE uint16_t ll_ddvs_ringo_1_cnt_get(void)
378 {
379 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_01, DDVS_RINGO_CNT_01_RINGO_1_CNT)) >> DDVS_RINGO_CNT_01_RINGO_1_CNT_POS);
380 }
381
382 /**
383 * @brief DDVS Ringo_2 count get
384 * Register|BitsName
385 * --------|--------
386 * DDVS_RINGO_CNT_23 | RINGO_2_CNT
387 */
388 __STATIC_INLINE uint16_t ll_ddvs_ringo_2_cnt_get(void)
389 {
390 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_23, DDVS_RINGO_CNT_23_RINGO_2_CNT)) >> DDVS_RINGO_CNT_23_RINGO_2_CNT_POS);
391 }
392
393 /**
394 * @brief DDVS Ringo_3 count get
395 * Register|BitsName
396 * --------|--------
397 * DDVS_RINGO_CNT_23 | RINGO_3_CNT
398 */
399 __STATIC_INLINE uint16_t ll_ddvs_ringo_3_cnt_get(void)
400 {
401 return ((READ_BITS(DDVS_CTRL->DDVS_RINGO_CNT_23, DDVS_RINGO_CNT_23_RINGO_3_CNT)) >> DDVS_RINGO_CNT_23_RINGO_3_CNT_POS);
402 }
403
404 /**
405 * @brief DDVS FSM state get
406 * Register|BitsName
407 * --------|--------
408 * DDVS_FSM | STS_FSM_CURR
409 */
410 __STATIC_INLINE uint8_t ll_ddvs_fsm_state_get(void)
411 {
412 return ((READ_BITS(DDVS_CTRL->DDVS_FSM, DDVS_FSM_STS_FSM_CURR)) >> DDVS_FSM_STS_FSM_CURR_POS);
413 }
414
415 /**
416 * @brief DDVS Clock enable set
417 * Register|BitsName
418 * --------|--------
419 * DDVS_CLK_CTRL | DDVS_CLK_EN
420 */
421 __STATIC_INLINE void ll_ddvs_clk_enable_set(uint8_t enable)
422 {
423 MODIFY_REG(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_EN, (enable << DDVS_CLK_CTRL_DDVS_CLK_EN_POS));
424 }
425
426 /**
427 * @brief DDVS Clock enable get
428 * Register|BitsName
429 * --------|--------
430 * DDVS_CLK_CTRL | DDVS_CLK_EN
431 */
432 __STATIC_INLINE uint8_t ll_ddvs_clk_enable_get(void)
433 {
434 return ((READ_BITS(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_EN)) >> DDVS_CLK_CTRL_DDVS_CLK_EN_POS);
435 }
436
437 /**
438 * @brief DDVS Clock selection set
439 * 0: xo_32MHz(default), 1: xo_16MHz, 2: sys_32MHz, 3: sys_16MHz
440 * Register|BitsName
441 * --------|--------
442 * DDVS_CLK_CTRL | CONF_RINGO_EN
443 */
444 __STATIC_INLINE void ll_ddvs_clk_sel_set(uint8_t clk_sel)
445 {
446 MODIFY_REG(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_SEL, (clk_sel<<DDVS_CLK_CTRL_DDVS_CLK_SEL_POS));
447 }
448
449 /**
450 * @brief DDVS Clock selection get
451 * 0: xo_32MHz(default), 1: xo_16MHz, 2: sys_32MHz, 3: sys_16MHz
452 * Register|BitsName
453 * --------|--------
454 * DDVS_CLK_CTRL | CONF_RINGO_EN
455 */
456 __STATIC_INLINE uint8_t ll_ddvs_clk_sel_get(void)
457 {
458 return ((READ_BITS(DDVS_CTRL->DDVS_CLK_CTRL, DDVS_CLK_CTRL_DDVS_CLK_SEL)) >> DDVS_CLK_CTRL_DDVS_CLK_SEL_POS);
459 }
460
461 /** @} */
462
463 #endif
464 /** @} */
465
466 /** @} */
467
468 /** @} */
ll_ddvs_mode_set
__STATIC_INLINE void ll_ddvs_mode_set(uint8_t mode)
DDVS mode set 0b - DDVS automatic mode (default) 1b - DDVS manual mode Register|BitsName --------|---...
Definition: gr533x_ll_ddvs.h:152
ll_ddvs_slow_threshold_set
__STATIC_INLINE void ll_ddvs_slow_threshold_set(uint16_t threshold)
DDVS Slow threshold(limit for ringo goes bigger) set This is the limitation of ringo being bigger tha...
Definition: gr533x_ll_ddvs.h:177
ll_ddvs_ringo_0_cnt_get
__STATIC_INLINE uint16_t ll_ddvs_ringo_0_cnt_get(void)
DDVS Ringo_0 count get Register|BitsName --------|-------- DDVS_RINGO_CNT_01 | RINGO_0_CNT.
Definition: gr533x_ll_ddvs.h:366
ll_ddvs_div_factor_set
__STATIC_INLINE void ll_ddvs_div_factor_set(uint8_t factor)
DDVS Ringo frequency divide factor set 00b - 8K (default) 01b - 4K 10b - 16K 11b - Reserved Register|...
Definition: gr533x_ll_ddvs.h:340
ll_ddvs_manual_vref_get
__STATIC_INLINE uint8_t ll_ddvs_manual_vref_get(void)
DDVS Manual vref get.
Definition: gr533x_ll_ddvs.h:299
ll_ddvs_div_factor_get
__STATIC_INLINE uint8_t ll_ddvs_div_factor_get(void)
DDVS Ringo frequency divide factor get 00b - 8K (default) 01b - 4K 10b - 16K 11b - Reserved Register|...
Definition: gr533x_ll_ddvs.h:355
ll_ddvs_ringo_3_cnt_get
__STATIC_INLINE uint16_t ll_ddvs_ringo_3_cnt_get(void)
DDVS Ringo_3 count get Register|BitsName --------|-------- DDVS_RINGO_CNT_23 | RINGO_3_CNT.
Definition: gr533x_ll_ddvs.h:399
ll_ddvs_err_int_disable
__STATIC_INLINE void ll_ddvs_err_int_disable(void)
DDVS Error interrupt disable.
Definition: gr533x_ll_ddvs.h:261
ll_ddvs_enable_set
__STATIC_INLINE void ll_ddvs_enable_set(uint8_t enable)
Enable the DDVS block.
Definition: gr533x_ll_ddvs.h:127
LL_DDVS_MALNUAL_MODE
#define LL_DDVS_MALNUAL_MODE
Definition: gr533x_ll_ddvs.h:77
ll_ddvs_clk_enable_get
__STATIC_INLINE uint8_t ll_ddvs_clk_enable_get(void)
DDVS Clock enable get Register|BitsName --------|-------- DDVS_CLK_CTRL | DDVS_CLK_EN.
Definition: gr533x_ll_ddvs.h:432
ll_ddvs_manual_vref_set
__STATIC_INLINE void ll_ddvs_manual_vref_set(uint8_t vref)
DDVS Manual vref set.
Definition: gr533x_ll_ddvs.h:287
ll_ddvs_enable_get
__STATIC_INLINE uint8_t ll_ddvs_enable_get(void)
DDVS block enable state get.
Definition: gr533x_ll_ddvs.h:139
ll_ddvs_slow_threshold_get
__STATIC_INLINE uint16_t ll_ddvs_slow_threshold_get(void)
DDVS Slow threshold(limit for ringo goes bigger) get This is the limitation of ringo being bigger tha...
Definition: gr533x_ll_ddvs.h:189
ll_ddvs_clk_sel_set
__STATIC_INLINE void ll_ddvs_clk_sel_set(uint8_t clk_sel)
DDVS Clock selection set 0: xo_32MHz(default), 1: xo_16MHz, 2: sys_32MHz, 3: sys_16MHz Register|BitsN...
Definition: gr533x_ll_ddvs.h:444
ll_ddvs_fsm_state_get
__STATIC_INLINE uint8_t ll_ddvs_fsm_state_get(void)
DDVS FSM state get Register|BitsName --------|-------- DDVS_FSM | STS_FSM_CURR.
Definition: gr533x_ll_ddvs.h:410
ll_ddvs_ringo_en_set
__STATIC_INLINE void ll_ddvs_ringo_en_set(uint8_t ringo_bits)
DDVS Ringo enable set 0000b - disable all 4 ringos (default) 0001b~1111b - enable corresponding ringo...
Definition: gr533x_ll_ddvs.h:312
ll_ddvs_err_int_enable
__STATIC_INLINE void ll_ddvs_err_int_enable(void)
DDVS Error interrupt enable.
Definition: gr533x_ll_ddvs.h:249
ll_ddvs_fast_threshold_get
__STATIC_INLINE uint16_t ll_ddvs_fast_threshold_get(void)
DDVS Fast threshold get This is the limitation of ringo being smaller than target_cnt Register|BitsNa...
Definition: gr533x_ll_ddvs.h:237
ll_ddvs_fast_threshold_set
__STATIC_INLINE void ll_ddvs_fast_threshold_set(uint16_t threshold)
DDVS Fast threshold set This is the limitation of ringo being smaller than target_cnt Register|BitsNa...
Definition: gr533x_ll_ddvs.h:225
ll_ddvs_ringo_en_get
__STATIC_INLINE uint8_t ll_ddvs_ringo_en_get(void)
DDVS Ringo enable get 0000b - disable all 4 ringos (default) 0001b~1111b - enable corresponding ringo...
Definition: gr533x_ll_ddvs.h:325
ll_ddvs_ringo_2_cnt_get
__STATIC_INLINE uint16_t ll_ddvs_ringo_2_cnt_get(void)
DDVS Ringo_2 count get Register|BitsName --------|-------- DDVS_RINGO_CNT_23 | RINGO_2_CNT.
Definition: gr533x_ll_ddvs.h:388
ll_ddvs_target_cnt_get
__STATIC_INLINE uint16_t ll_ddvs_target_cnt_get(void)
DDVS Target count get.
Definition: gr533x_ll_ddvs.h:213
gr533x_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_ddvs_err_int_clear
__STATIC_INLINE void ll_ddvs_err_int_clear(void)
DDVS Error interrupt clear From Spec, the ddvs mode shall set to manual mode before clear the interru...
Definition: gr533x_ll_ddvs.h:274
ll_ddvs_mode_get
__STATIC_INLINE uint8_t ll_ddvs_mode_get(void)
DDVS mode get 0b - DDVS automatic mode (default) 1b - DDVS manual mode Register|BitsName --------|---...
Definition: gr533x_ll_ddvs.h:165
ll_ddvs_target_cnt_set
__STATIC_INLINE void ll_ddvs_target_cnt_set(uint16_t target_cnt)
DDVS Target count set.
Definition: gr533x_ll_ddvs.h:201
ll_ddvs_clk_enable_set
__STATIC_INLINE void ll_ddvs_clk_enable_set(uint8_t enable)
DDVS Clock enable set Register|BitsName --------|-------- DDVS_CLK_CTRL | DDVS_CLK_EN.
Definition: gr533x_ll_ddvs.h:421
ll_ddvs_ringo_1_cnt_get
__STATIC_INLINE uint16_t ll_ddvs_ringo_1_cnt_get(void)
DDVS Ringo_1 count get Register|BitsName --------|-------- DDVS_RINGO_CNT_01 | RINGO_1_CNT.
Definition: gr533x_ll_ddvs.h:377
ll_ddvs_clk_sel_get
__STATIC_INLINE uint8_t ll_ddvs_clk_sel_get(void)
DDVS Clock selection get 0: xo_32MHz(default), 1: xo_16MHz, 2: sys_32MHz, 3: sys_16MHz Register|BitsN...
Definition: gr533x_ll_ddvs.h:456