52 #ifndef __GR533x_LL_DMA_H__
53 #define __GR533x_LL_DMA_H__
76 typedef struct _ll_dma_init
92 uint32_t src_increment_mode;
97 uint32_t dst_increment_mode;
102 uint32_t src_data_width;
107 uint32_t dst_data_width;
118 uint32_t src_peripheral;
123 uint32_t dst_peripheral;
151 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
152 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
153 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
154 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
155 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
156 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
162 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
163 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
164 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
165 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
171 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
172 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
173 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
179 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
180 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
181 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
187 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
188 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
189 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
190 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
191 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
192 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
193 #define LL_DMA_SRC_BURST_LENGTH_128 DMA_CTLL_SRC_MSIZE_128
194 #define LL_DMA_SRC_BURST_LENGTH_256 DMA_CTLL_SRC_MSIZE_256
200 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
201 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
202 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
203 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
204 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
205 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
206 #define LL_DMA_DST_BURST_LENGTH_128 DMA_CTLL_DST_MSIZE_128
207 #define LL_DMA_DST_BURST_LENGTH_256 DMA_CTLL_DST_MSIZE_256
213 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
214 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
215 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
221 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
222 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
223 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
229 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
230 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
231 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
232 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
233 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
234 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
235 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
236 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
242 #define LL_DMA_LOCK_CH_ENABLE DMA_CFGL_LOCK_CH_ENABLE
243 #define LL_DMA_LOCK_CH_DSIBALE DMA_CFGL_LOCK_CH_DISABLE
249 #define LL_DMA_LOCK_CH_LEVEL_TFR DMA_CFGL_LOCK_CH_L_TFR
250 #define LL_DMA_LOCK_CH_LEVEL_BLK DMA_CFGL_LOCK_CH_L_BLK
251 #define LL_DMA_LOCK_CH_LEVEL_TRANS DMA_CFGL_LOCK_CH_L_TRANS
257 #define LL_DMA_LOCK_BUS_ENABLE DMA_CFGL_LOCK_B_ENABLE
258 #define LL_DMA_LOCK_BUS_DSIBALE DMA_CFGL_LOCK_B_DISABLE
264 #define LL_DMA_LOCK_BUS_LEVEL_TFR DMA_CFGL_LOCK_B_L_TFR
265 #define LL_DMA_LOCK_BUS_LEVEL_BLK DMA_CFGL_LOCK_B_L_BLK
266 #define LL_DMA_LOCK_BUS_LEVEL_TRANS DMA_CFGL_LOCK_B_L_TRANS
272 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
273 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
279 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
280 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
287 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU)
290 #define LL_DMA0_PERIPH_CTE ((uint32_t)0x00000000U)
291 #define LL_DMA0_PERIPH_PWM0 ((uint32_t)0x00000001U)
292 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U)
293 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U)
294 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U)
295 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U)
296 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U)
297 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U)
298 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U)
299 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U)
300 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU)
301 #define LL_DMA0_PERIPH_I2C0_TX ((uint32_t)0x0000000CU)
302 #define LL_DMA0_PERIPH_I2C0_RX ((uint32_t)0x0000000DU)
303 #define LL_DMA0_PERIPH_I2C1_TX ((uint32_t)0x0000000EU)
304 #define LL_DMA0_PERIPH_I2C1_RX ((uint32_t)0x0000000FU)
326 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
334 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
363 __STATIC_INLINE
void ll_dma_enable(dma_regs_t *DMAx)
365 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
382 __STATIC_INLINE
void ll_dma_disable(dma_regs_t *DMAx)
384 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
397 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
399 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
420 __STATIC_INLINE
void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
422 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
441 __STATIC_INLINE
void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
443 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
464 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
466 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
487 __STATIC_INLINE
void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
489 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
509 __STATIC_INLINE
void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
511 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
530 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
532 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
551 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
553 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
586 __STATIC_INLINE
void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
588 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
589 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
613 __STATIC_INLINE
void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
615 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
638 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
640 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
663 __STATIC_INLINE
void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
665 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
687 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
689 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
712 __STATIC_INLINE
void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
714 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
736 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
738 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
761 __STATIC_INLINE
void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
763 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
785 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
787 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
810 __STATIC_INLINE
void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
812 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
834 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
836 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
859 __STATIC_INLINE
void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
861 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
883 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
885 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
908 __STATIC_INLINE
void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
910 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
932 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
934 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
959 __STATIC_INLINE
void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
961 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
985 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
987 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1008 __STATIC_INLINE
void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1010 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1031 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1033 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1062 __STATIC_INLINE
void ll_dma_config_address(dma_regs_t *DMAx,
1064 uint32_t src_address,
1065 uint32_t dst_address,
1068 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1069 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1070 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1090 __STATIC_INLINE
void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1092 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1112 __STATIC_INLINE
void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1114 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1133 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1135 return READ_REG(DMAx->CHANNEL[channel].SAR);
1154 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1156 return READ_REG(DMAx->CHANNEL[channel].DAR);
1177 __STATIC_INLINE
void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1179 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1180 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1202 __STATIC_INLINE
void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1204 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1205 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1225 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1227 return READ_REG(DMAx->CHANNEL[channel].SAR);
1247 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
1249 return READ_REG(DMAx->CHANNEL[channel].DAR);
1285 __STATIC_INLINE
void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1287 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1321 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
1323 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1358 __STATIC_INLINE
void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1360 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1394 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
1396 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
1421 __STATIC_INLINE
void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
1423 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1424 src_handshaking | dst_handshaking);
1445 __STATIC_INLINE
void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
1447 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
1468 __STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
1470 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
1489 __STATIC_INLINE
void ll_dma_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1491 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1510 __STATIC_INLINE
void ll_dma_disable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1512 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1531 __STATIC_INLINE uint32_t ll_dma_is_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1533 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH) == DMA_CFGL_LOCK_CH);
1552 __STATIC_INLINE
void ll_dma_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1554 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1573 __STATIC_INLINE
void ll_dma_disable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1575 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1594 __STATIC_INLINE uint32_t ll_dma_is_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1596 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B) == DMA_CFGL_LOCK_B);
1619 __STATIC_INLINE
void ll_dma_set_channel_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
1621 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L, lock_level);
1643 __STATIC_INLINE uint32_t ll_dma_get_channel_lock_level(dma_regs_t *DMAx, uint32_t channel)
1645 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L);
1668 __STATIC_INLINE
void ll_dma_set_bus_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
1670 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L, lock_level);
1692 __STATIC_INLINE uint32_t ll_dma_get_bus_lock_level(dma_regs_t *DMAx, uint32_t channel)
1694 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L);
1714 __STATIC_INLINE
void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1716 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1717 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1736 __STATIC_INLINE
void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1738 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1759 __STATIC_INLINE
void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1761 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1762 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1763 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1783 __STATIC_INLINE
void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1785 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1786 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1806 __STATIC_INLINE
void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1808 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1809 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1828 __STATIC_INLINE
void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1830 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1851 __STATIC_INLINE
void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1853 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1854 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1855 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1875 __STATIC_INLINE
void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1877 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1878 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1897 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
1899 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1912 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
1914 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1927 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
1929 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1942 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
1944 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1957 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
1959 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1978 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
1980 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
1999 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
2001 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2020 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
2022 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2041 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
2043 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2062 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
2064 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2083 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2085 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2098 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
2100 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2113 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
2115 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2128 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
2130 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2143 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
2145 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2158 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
2160 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2180 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2182 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2195 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
2197 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2210 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
2212 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2225 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
2227 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2240 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
2242 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2255 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
2257 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2277 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2279 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2292 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
2294 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2307 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
2309 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2322 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
2324 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2337 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
2339 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2352 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
2354 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2373 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2375 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2388 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
2390 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2403 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
2405 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2418 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
2420 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2433 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
2435 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2448 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
2450 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2469 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
2471 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
2484 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
2486 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
2499 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
2501 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
2514 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
2516 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
2529 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
2531 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
2544 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
2546 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
2565 __STATIC_INLINE
void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2567 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2580 __STATIC_INLINE
void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
2582 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2595 __STATIC_INLINE
void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
2597 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2610 __STATIC_INLINE
void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
2612 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
2625 __STATIC_INLINE
void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
2627 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
2640 __STATIC_INLINE
void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
2642 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
2661 __STATIC_INLINE
void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2663 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
2676 __STATIC_INLINE
void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
2678 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
2691 __STATIC_INLINE
void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
2693 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
2706 __STATIC_INLINE
void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
2708 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
2721 __STATIC_INLINE
void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
2723 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
2736 __STATIC_INLINE
void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
2738 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
2757 __STATIC_INLINE
void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2759 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
2772 __STATIC_INLINE
void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
2774 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
2787 __STATIC_INLINE
void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
2789 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
2802 __STATIC_INLINE
void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
2804 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
2817 __STATIC_INLINE
void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
2819 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
2832 __STATIC_INLINE
void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
2834 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
2853 __STATIC_INLINE
void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2855 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
2868 __STATIC_INLINE
void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
2870 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
2883 __STATIC_INLINE
void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
2885 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
2898 __STATIC_INLINE
void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
2900 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
2913 __STATIC_INLINE
void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
2915 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
2928 __STATIC_INLINE
void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
2930 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
2949 __STATIC_INLINE
void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
2951 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
2964 __STATIC_INLINE
void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
2966 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
2979 __STATIC_INLINE
void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
2981 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
2994 __STATIC_INLINE
void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
2996 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3009 __STATIC_INLINE
void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
3011 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
3024 __STATIC_INLINE
void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
3026 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
3051 __STATIC_INLINE
void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3053 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3072 __STATIC_INLINE
void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3074 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3093 __STATIC_INLINE
void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3095 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3114 __STATIC_INLINE
void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3116 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3135 __STATIC_INLINE
void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3137 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3156 __STATIC_INLINE
void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3158 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3177 __STATIC_INLINE
void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3179 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3198 __STATIC_INLINE
void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3200 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3219 __STATIC_INLINE
void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3221 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3240 __STATIC_INLINE
void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
3242 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3261 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3263 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3282 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3284 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
3303 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3305 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
3324 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3326 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
3345 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3347 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
3366 __STATIC_INLINE
void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
3368 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3387 __STATIC_INLINE
void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
3389 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
3408 __STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
3410 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
3432 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
3448 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
3456 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);