gr533x_ll_pwm.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef __GR533X_LL_PWM_H__
52 #define __GR533X_LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr533x.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /* Exported types ------------------------------------------------------------*/
63 /** @addtogroup LL_PWM_ENUMERATIONS Enumerations
64 * @{
65 */
66
67 /**
68 * @brief LL PWM Mode definition
69 */
70 typedef enum
71 {
72 LL_PWM_FLICKER_MODE = 0x00, /**< Choose PWM Flicker Mode */
73 LL_PWM_BREATH_MODE, /**< Choose PWM Breath Mode */
74 LL_PWM_CODING_MODE, /**< Choose PWM Coding Mode */
75 } ll_pwm_mode_t;
76
77 /** @} */
78
79 /** @defgroup PWM_LL_STRUCTURES Structures
80 * @{
81 */
82
83 /* Exported types ------------------------------------------------------------*/
84 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
85 * @{
86 */
87
88 /**
89 * @brief LL PWM Output Channel init Structure definition.
90 */
91 typedef struct _ll_pwm_none_coding_channel_init_t
92 {
93 uint8_t duty; /**< Specifies the duty in PWM output mode.
94 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.*/
95
96 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
97 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
98
99 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
100 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
101
102 uint32_t flickerstop_lvl; /**< Specifies the IO level when channel flicker stop.
103 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
104 } ll_pwm_none_coding_channel_init_t;
105
106 /**
107 * @brief LL PWM Output Channel init Structure definition.
108 */
109 typedef struct _ll_pwm_coding_channel_init_t
110 {
111 uint32_t ll_comp0; /**< Specifies current channel first compare value
112 This parameter must be a number ranges between Min_Data=0 and Max_Data=period.*/
113
114 uint32_t ll_comp1; /**< Specifies current channel second compare value
115 This parameter must be a number ranges between Min_Data=0 and Max_Data=period.*/
116
117 uint8_t ll_drive_polarity; /**< Specifies the drive polarity in PWM output mode.
118 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
119 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
120 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
121
122 uint8_t ll_waiting_time_lvl; /**< Specifies the waiting time level in coding mode.
123 This parameter can be a value of @ref PWM_LL_WAITING_TIME_LVL.*/
124
125 } ll_pwm_coding_channel_init_t;
126
127 /**
128 * @brief LL PWM none coding mode Structure definition.
129 */
130 typedef struct _ll_pwm_none_coding_mode_init_t
131 {
132 uint32_t align; /**< Specifies the PWM alignment pulses.
133 This parameter can be a value of @ref PWM_LL_EC_ALIGN.*/
134
135 uint32_t prescaler; /**< Specifies the prescaler value which will be used configure PWM output frequency.
136 This parameter must be a number ranges between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
137 This parameter should be larger than 128.
138
139 This feature can be modified afterwards using unitary function @ref ll_pwm_set_prescaler().*/
140
141 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
142 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
143 This parameter is recommended to be larger than 128*prescaler to guarantee an ideal breath effect.
144
145 This feature can be modified afterwards using unitary function @ref ll_pwm_set_breath_prescaler().*/
146
147 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
148 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFF.
149
150 This feature can be modified afterwards using unitary function @ref ll_pwm_set_hold_prescaler().*/
151
152 uint32_t breathstop_lvl; /**< Specifies the IO level when breath stop.
153 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
154
155 ll_pwm_none_coding_channel_init_t channel_a; /**< Specifies the configuration of channelA.
156 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
157
158 ll_pwm_none_coding_channel_init_t channel_b; /**< Specifies the configuration of channelB.
159 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
160
161 ll_pwm_none_coding_channel_init_t channel_c; /**< Specifies the configuration of channelC.
162 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
163 } ll_pwm_none_coding_mode_init_t;
164
165 /**
166 * @brief LL PWM coding mode Structure definition.
167 */
168 typedef struct _ll_pwm_coding_mode_init_t
169 {
170 uint32_t ll_period; /**< Specifies the period value which will be used configure PWM output frequency in coding mode.
171 This parameter must be a number ranges between Min_Data = 0 and Max_Data = SysCoreCLK.*/
172
173 uint32_t ll_waiting_time; /**< Specifies the waiting time before PWM waveform generation in coding mode.
174 This parameter control PWM waiting time count in the coding mode.*/
175
176 uint8_t ll_data_width_valid; /**< Specifies the coding data valid width in Coding mode.
177 This parameter control coding data valid width = DATA_WIDTH_VALID + 1,
178 DATA_WIDTH_VALID value ranges between Min_Data = 0x0 and Max_Data = 0x1F.*/
179
180 uint8_t ll_coding_channel_select; /**< Specifies the coding channel select all 3 channels or only channel A.
181 This parameter can be a value of @ref PWM_LL_CODING_CHANNEL*/
182
183 ll_pwm_coding_channel_init_t ll_channel_a; /**< Specifies the configuration of channelA in coding mode.
184 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
185
186 ll_pwm_coding_channel_init_t ll_channel_b; /**< Specifies the configuration of channelB in coding mode.
187 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
188
189 ll_pwm_coding_channel_init_t ll_channel_c; /**< Specifies the configuration of channelC in coding mode.
190 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
191 } ll_pwm_coding_mode_init_t;
192
193 /**
194 * @brief LL PWM init Structure definition.
195 */
196 typedef struct _ll_pwm_init_t
197 {
198 ll_pwm_mode_t ll_mode; /**< Specifies the PWM output mode.
199 This parameter can be a value of PWM_LL_EC_MODE.
200
201 This feature can be modified afterwards using unitary function @ref ll_pwm_set_mode().*/
202
203 uint32_t ll_prd_cycles; /**< Specifies the number of period cycle in Flicker mode or Coding mode.
204 This parameter control the number of period cycles, when set to 0 will continuously generate waveform.*/
205
206 ll_pwm_none_coding_mode_init_t none_coding_mode_cfg; /**< Specifies the none coding mode config.
207 This parameter can be a value of @ref ll_pwm_none_coding_mode_init_t.*/
208
209 ll_pwm_coding_mode_init_t coding_mode_cfg; /**< Specifies the coding mode config.
210 This parameter can be a value of @ref ll_pwm_coding_mode_init_t.*/
211
212 } ll_pwm_init_t;
213
214 /** @} */
215
216 /** @} */
217
218 /**
219 * @defgroup PWM_LL_MACRO Defines
220 * @{
221 */
222
223 /* Exported constants --------------------------------------------------------*/
224 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
225 * @{
226 */
227
228 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
229 * @{
230 */
231 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
232 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
233 /** @} */
234
235 /** @defgroup PWM_LL_STOP_LVL PWM stop io level
236 * @{
237 */
238 #define LL_PWM_STOP_LVL_LOW (0x00000000U) /**< PWM stop in low io level */
239 #define LL_PWM_STOP_LVL_HIGH (0x00000001U) /**< PWM stop in high io level */
240 /** @} */
241
242 /** @defgroup PWM_LL_WAITING_TIME_LVL PWM waiting time io level
243 * @{
244 */
245 #define LL_PWM_WAITING_TIME_LVL_LOW (0x00000000U) /**< PWM waiting time io level low */
246 #define LL_PWM_WAITING_TIME_LVL_HIGH (0x00000001U) /**< PWM waiting time io level high */
247 /** @} */
248
249 /** @defgroup PWM_LL_CODING_CHANNEL PWM coding channel select in coding mode
250 * @{
251 */
252 #define LL_PWM_CODING_CHANNEL_ALL (0x00000000U) /**< Select all channels operation in coding mode */
253 #define LL_PWM_CODING_CHANNEL_A (0x00000001U) /**< Select channle A operation in coding mode */
254 /** @} */
255
256 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
257 * @{
258 */
259 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
260 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
261 /** @} */
262
263 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
264 * @{
265 */
266 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
267 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
268 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
269 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
270 /** @} */
271
272 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
273 * @{
274 */
275 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
276 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
277 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
278 /** @} */
279
280 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
281 * @{
282 */
283
284 /**
285 * @brief LL PWM None Coding Channel InitStrcut default configuartion
286 */
287 #define LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG \
288 { \
289 .duty = 50, \
290 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
291 .flickerstop_lvl = LL_PWM_STOP_LVL_LOW, \
292 }
293
294 /**
295 * @brief LL PWM Coding Channel InitStrcut default configuartion
296 */
297 #define LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG \
298 { \
299 .ll_comp0 = 0, \
300 .ll_comp1 = 640, \
301 .ll_drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
302 .ll_waiting_time_lvl = LL_PWM_WAITING_TIME_LVL_LOW, \
303 }
304
305 /**
306 * @brief LL PWM None Coding InitStrcut default configuartion
307 */
308 #define LL_PWM_NONE_CODING_DEFAULT_CONFIG \
309 { \
310 .align = LL_PWM_EDGE_ALIGNED, \
311 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
312 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
313 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
314 .breathstop_lvl = LL_PWM_STOP_LVL_LOW, \
315 .channel_a = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
316 .channel_b = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
317 .channel_c = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
318 }
319
320 /**
321 * @brief LL PWM Coding InitStrcut default configuartion
322 */
323 #define LL_PWM_CODING_DEFAULT_CONFIG \
324 { \
325 .ll_period = 640, \
326 .ll_waiting_time = 640, \
327 .ll_data_width_valid = 0x1F, \
328 .ll_coding_channel_select = LL_PWM_CODING_CHANNEL_ALL, \
329 .ll_channel_a = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
330 .ll_channel_b = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
331 .ll_channel_c = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
332 }
333
334 /**
335 * @brief LL PWM InitStrcut default configuartion
336 */
337 #define LL_PWM_DEFAULT_CONFIG \
338 { \
339 .ll_mode = LL_PWM_FLICKER_MODE, \
340 .ll_prd_cycles = 0x0, \
341 .none_coding_mode_cfg = LL_PWM_NONE_CODING_DEFAULT_CONFIG, \
342 .coding_mode_cfg = LL_PWM_CODING_DEFAULT_CONFIG, \
343 }
344
345 /** @} */
346
347 /** @} */
348
349 /* Exported macro ------------------------------------------------------------*/
350 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
351 * @{
352 */
353
354 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
355 * @{
356 */
357
358 /**
359 * @brief Write a value in PWM register
360 * @param __instance__ PWM instance
361 * @param __REG__ Register to be written
362 * @param __VALUE__ Value to be written in the register
363 * @retval None
364 */
365 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
366
367 /**
368 * @brief Read a value in PWM register
369 * @param __instance__ PWM instance
370 * @param __REG__ Register to be read
371 * @retval Register value
372 */
373 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
374
375 /** @} */
376
377 /** @} */
378
379 /** @} */
380
381 /* Exported functions --------------------------------------------------------*/
382 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
383 * @{
384 */
385
386 /** @defgroup PWM_LL_EF_Configuration Configuration functions
387 * @{
388 */
389
390 /**
391 * @brief Enable PWM.
392 *
393 * Register|BitsName
394 * --------|--------
395 * MODE | EN
396 *
397 * @param PWMx PWM instance
398 * @retval None
399 */
400 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
401 {
402 SET_BITS(PWMx->MODE, PWM_MODE_EN);
403 }
404
405 /**
406 * @brief Disable PWM.
407 *
408 * Register|BitsName
409 * --------|--------
410 * MODE | EN
411 *
412 * @param PWMx PWM instance
413 * @retval None
414 */
415 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
416 {
417 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
418 }
419
420 /**
421 * @brief Indicate whether the PWM is enabled.
422 *
423 * Register|BitsName
424 * --------|--------
425 * MODE | EN
426 *
427 * @param PWMx PWM instance
428 * @retval State of bit (1 or 0).
429 */
430 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
431 {
432 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
433 }
434
435 /**
436 * @brief Enable PWM pause.
437 *
438 * Register|BitsName
439 * --------|--------
440 * MODE | PAUSE
441 *
442 * @param PWMx PWM instance
443 * @retval None
444 */
445 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
446 {
447 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
448 }
449
450 /**
451 * @brief Disable PWM pause.
452 *
453 * Register|BitsName
454 * --------|--------
455 * MODE | PAUSE
456 *
457 * @param PWMx PWM instance
458 * @retval None
459 */
460 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
461 {
462 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
463 }
464
465 /**
466 * @brief Indicate whether the PWM pause is enabled.
467 *
468 * Register|BitsName
469 * --------|--------
470 * MODE | PAUSE
471 *
472 * @param PWMx PWM instance
473 * @retval State of bit (1 or 0).
474 */
475 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
476 {
477 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
478 }
479
480 /**
481 * @brief Set PWM mode.
482 *
483 * Register|BitsName
484 * --------|--------
485 * MODE | BREATHEN and CODINGEN
486 *
487 * @param PWMx PWM instance
488 * @param mode This parameter can be one of the following values:
489 * @arg @ref LL_PWM_FLICKER_MODE
490 * @arg @ref LL_PWM_BREATH_MODE
491 * @arg @ref LL_PWM_CODING_MODE
492 * @retval None
493 */
494 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, ll_pwm_mode_t mode)
495 {
496 if(mode == LL_PWM_CODING_MODE) {
497 if(PWMx == PWM0) {
498 MODIFY_REG(PWMx->MODE, PWM_MODE_CODINGEN, 0x1 << PWM_MODE_CODINGEN_Pos);
499 }
500 } else {
501 CLEAR_BITS(PWMx->MODE, PWM_MODE_CODINGEN);
502 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, (mode == LL_PWM_BREATH_MODE) ?
503 (0x1 << PWM_MODE_BREATHEN_Pos) : (0x0 << PWM_MODE_BREATHEN_Pos));
504 }
505 }
506
507 /**
508 * @brief Get PWM mode.
509 *
510 * Register|BitsName
511 * --------|--------
512 * MODE | BREATHEN and CODINGEN
513 *
514 * @param PWMx PWM instance
515 * @retval Return value can be one of the following values:
516 * @arg @ref LL_PWM_FLICKER_MODE
517 * @arg @ref LL_PWM_BREATH_MODE
518 * @arg @ref LL_PWM_CODING_MODE
519 */
520 __STATIC_INLINE ll_pwm_mode_t ll_pwm_get_mode(pwm_regs_t *PWMx)
521 {
522 if(READ_BITS(PWMx->MODE, PWM_MODE_CODINGEN) == PWM_MODE_CODINGEN) {
523 return LL_PWM_CODING_MODE;
524 } else {
525 return ((READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN) == PWM_MODE_BREATHEN) ? LL_PWM_BREATH_MODE : LL_PWM_FLICKER_MODE);
526 }
527 }
528
529 /**
530 * @brief Enable positive drive mode in channelA.
531 *
532 * Register|BitsName
533 * --------|--------
534 * MODE | DPENA
535 *
536 * @param PWMx PWM instance
537 * @retval None
538 */
539 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
540 {
541 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
542 }
543
544 /**
545 * @brief Disable positive drive mode in channelA.
546 *
547 * Register|BitsName
548 * --------|--------
549 * MODE | DPENA
550 *
551 * @param PWMx PWM instance
552 * @retval None
553 */
554 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
555 {
556 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
557 }
558
559 /**
560 * @brief Indicate whether the positive drive mode in channelA is enabled.
561 *
562 * Register|BitsName
563 * --------|--------
564 * MODE | DPENA
565 *
566 * @param PWMx PWM instance
567 * @retval State of bit (1 or 0).
568 */
569 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
570 {
571 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
572 }
573
574 /**
575 * @brief Enable positive drive mode in channelB.
576 *
577 * Register|BitsName
578 * --------|--------
579 * MODE | DPENB
580 *
581 * @param PWMx PWM instance
582 * @retval None
583 */
584 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
585 {
586 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
587 }
588
589 /**
590 * @brief Disable positive drive mode in channelB.
591 *
592 * Register|BitsName
593 * --------|--------
594 * MODE | DPENB
595 *
596 * @param PWMx PWM instance
597 * @retval None
598 */
599 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
600 {
601 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
602 }
603
604 /**
605 * @brief Indicate whether the positive drive mode in channelB is enabled.
606 *
607 * Register|BitsName
608 * --------|--------
609 * MODE | DPENB
610 *
611 * @param PWMx PWM instance
612 * @retval State of bit (1 or 0).
613 */
614 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
615 {
616 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
617 }
618
619 /**
620 * @brief Enable positive drive mode in channelC.
621 *
622 * Register|BitsName
623 * --------|--------
624 * MODE | DPENC
625 *
626 * @param PWMx PWM instance
627 * @retval None
628 */
629 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
630 {
631 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
632 }
633
634 /**
635 * @brief Disable positive drive mode in channelC.
636 *
637 * Register|BitsName
638 * --------|--------
639 * MODE | DPENC
640 *
641 * @param PWMx PWM instance
642 * @retval None
643 */
644 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
645 {
646 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
647 }
648
649 /**
650 * @brief Indicate whether the positive drive mode in channelC is enabled.
651 *
652 * Register|BitsName
653 * --------|--------
654 * MODE | DPENC
655 *
656 * @param PWMx PWM instance
657 * @retval State of bit (1 or 0).
658 */
659 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
660 {
661 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
662 }
663
664 /**
665 * @brief Set the channel_a stop level in flicker mode.
666 *
667 * Register|BitsName
668 * --------|--------
669 * MODE | FLICKER_PAUSE_LEVEL_A
670 *
671 * @param PWMx PWM flicker stop level
672 * @param flickerstop_lvl This parameter can be set with 0 or 1.
673 * @retval None
674 */
675 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
676 {
677 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_A_Pos);
678 }
679
680 /**
681 * @brief Get the channel_a stop level in flicker mode.
682 *
683 * Register|BitsName
684 * --------|--------
685 * MODE | FLICKER_PAUSE_LEVEL_A
686 *
687 * @param PWMx
688 * @retval Return value of 0 or 1.
689 */
690 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
691 {
692 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A));
693 }
694
695 /**
696 * @brief Set the channel_b stop level in flicker mode.
697 *
698 * Register|BitsName
699 * --------|--------
700 * MODE | FLICKER_PAUSE_LEVEL_B
701 *
702 * @param PWMx PWM flicker stop level
703 * @param flickerstop_lvl This parameter can be set with 0 or 1.
704 * @retval None
705 */
706 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
707 {
708 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_B_Pos);
709 }
710
711 /**
712 * @brief Get the channel_b stop level in flicker mode.
713 *
714 * Register|BitsName
715 * --------|--------
716 * MODE | FLICKER_PAUSE_LEVEL_B
717 *
718 * @param PWMx
719 * @retval Return value of 0 or 1.
720 */
721 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
722 {
723 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B));
724 }
725
726 /**
727 * @brief Set the channel_c stop level in flicker mode.
728 *
729 * Register|BitsName
730 * --------|--------
731 * MODE | FLICKER_PAUSE_LEVEL_C
732 *
733 * @param PWMx PWM flicker stop level
734 * @param flickerstop_lvl This parameter can be set with 0 or 1.
735 * @retval None
736 */
737 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
738 {
739 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_C_Pos);
740 }
741
742 /**
743 * @brief Get the channel_c stop level in flicker mode.
744 *
745 * Register|BitsName
746 * --------|--------
747 * MODE | FLICKER_PAUSE_LEVEL_C
748 *
749 * @param PWMx
750 * @retval Return value of 0 or 1.
751 */
752 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
753 {
754 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C));
755 }
756
757 /**
758 * @brief Set the channel_a waiting time level in coding mode.
759 *
760 * Register|BitsName
761 * --------|--------
762 * MODE | WAITING_TIME_LEVEL_A
763 *
764 * @param PWMx
765 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
766 * @retval None
767 */
768 __STATIC_INLINE void ll_pwm_set_waiting_time_level_a(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
769 {
770 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_A_Pos);
771 }
772
773 /**
774 * @brief Get the channel_a waiting time level in coding mode.
775 *
776 * Register|BitsName
777 * --------|--------
778 * MODE | WAITING_TIME_LEVEL_A
779 *
780 * @param PWMx
781 * @retval Return value of 0 or 1.
782 */
783 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_a(pwm_regs_t *PWMx)
784 {
785 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A) == (PWM_MODE_WAITING_TIME_LEVEL_A));
786 }
787
788 /**
789 * @brief Set the channel_b waiting time level in coding mode.
790 *
791 * Register|BitsName
792 * --------|--------
793 * MODE | WAITING_TIME_LEVEL_B
794 *
795 * @param PWMx
796 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
797 * @retval None
798 */
799 __STATIC_INLINE void ll_pwm_set_waiting_time_level_b(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
800 {
801 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_B_Pos);
802 }
803
804 /**
805 * @brief Get the channel_b waiting time level in coding mode.
806 *
807 * Register|BitsName
808 * --------|--------
809 * MODE | WAITING_TIME_LEVEL_B
810 *
811 * @param PWMx
812 * @retval Return value of 0 or 1.
813 */
814 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_b(pwm_regs_t *PWMx)
815 {
816 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B) == (PWM_MODE_WAITING_TIME_LEVEL_B));
817 }
818
819 /**
820 * @brief Set the channel_c waiting time level in coding mode.
821 *
822 * Register|BitsName
823 * --------|--------
824 * MODE | WAITING_TIME_LEVEL_C
825 *
826 * @param PWMx
827 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
828 * @retval None
829 */
830 __STATIC_INLINE void ll_pwm_set_waiting_time_level_c(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
831 {
832 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_C_Pos);
833 }
834
835 /**
836 * @brief Get the channel_c waiting time level in coding mode.
837 *
838 * Register|BitsName
839 * --------|--------
840 * MODE | WAITING_TIME_LEVEL_C
841 *
842 * @param PWMx
843 * @retval Return value of 0 or 1.
844 */
845 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_c(pwm_regs_t *PWMx)
846 {
847 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C) == (PWM_MODE_WAITING_TIME_LEVEL_C));
848 }
849
850 /**
851 * @brief Set DMA enable in coding mode.
852 *
853 * Register|BitsName
854 * --------|--------
855 * MODE | DMA_EN
856 *
857 * @param PWMx
858 * @retval None
859 */
860 __STATIC_INLINE void ll_pwm_set_dma_enable(pwm_regs_t *PWMx)
861 {
862 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x1 << PWM_MODE_DMA_EN_Pos);
863 }
864
865 /**
866 * @brief Set DMA disable in coding mode.
867 *
868 * Register|BitsName
869 * --------|--------
870 * MODE | DMA_EN
871 *
872 * @param PWMx
873 * @retval None
874 */
875 __STATIC_INLINE void ll_pwm_set_dma_disable(pwm_regs_t *PWMx)
876 {
877 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x0 << PWM_MODE_DMA_EN_Pos);
878 }
879
880 /**
881 * @brief Get DMA enable or disable.
882 *
883 * Register|BitsName
884 * --------|--------
885 * MODE | DMA_EN
886 *
887 * @param PWMx
888 * @retval Return value of 0 or 1.
889 */
890 __STATIC_INLINE uint8_t ll_pwm_get_dma_en(pwm_regs_t *PWMx)
891 {
892 return (READ_BITS(PWMx->MODE, PWM_MODE_DMA_EN) == (PWM_MODE_DMA_EN));
893 }
894
895 /**
896 * @brief Choose 3 channels operation in coding mode or only choose channel A operation in coding mode.
897 *
898 * Register|BitsName
899 * --------|--------
900 * MODE | CODING_CHANNEL_SELECT
901 *
902 * @param PWMx
903 * @param coding_channel This parameter can be set with LL_PWM_CODING_CHANNEL_ALL or LL_PWM_CODING_CHANNEL_A.
904 * @retval None
905 */
906 __STATIC_INLINE void ll_pwm_coding_channel_select(pwm_regs_t *PWMx, uint8_t coding_channel)
907 {
908 MODIFY_REG(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT, coding_channel << PWM_MODE_CODING_CHANNEL_SELECT_Pos);
909 }
910
911 /**
912 * @brief Get PWM coding channel.
913 *
914 * Register|BitsName
915 * --------|--------
916 * MODE | CODING_CHANNEL_SELECT
917 *
918 * @param PWMx
919 * @retval Return value of 0 or 1, 0 represents LL_PWM_CODING_CHANNEL_ALL, 1 represents LL_PWM_CODING_CHANNEL_A
920 */
921 __STATIC_INLINE uint8_t ll_pwm_get_coding_channel(pwm_regs_t *PWMx)
922 {
923 return (READ_BITS(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT) == (PWM_MODE_CODING_CHANNEL_SELECT));
924 }
925
926 /**
927 * @brief Check update active flag
928 *
929 * Register|BitsName
930 * --------|--------
931 * UPDATE | SAG
932 *
933 * @param PWMx PWM instance
934 * @retval State of bit (1 or 0).
935 */
936 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
937 {
938 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
939 }
940
941 /**
942 * @brief Enable update all parameters.
943 *
944 * Register|BitsName
945 * --------|--------
946 * UPDATE | SA
947 *
948 * @param PWMx PWM instance
949 * @retval None
950 */
951 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
952 {
953 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
954 }
955
956 /**
957 * @brief Disable update all parameters.
958 *
959 * Register|BitsName
960 * --------|--------
961 * UPDATE | SA
962 *
963 * @param PWMx PWM instance
964 * @retval None
965 */
966 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
967 {
968 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
969 }
970
971 /**
972 * @brief Indicate whether the update all parameters is enabled.
973 *
974 * Register|BitsName
975 * --------|--------
976 * UPDATE | SA
977 *
978 * @param PWMx PWM instance
979 * @retval State of bit (1 or 0).
980 */
981 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
982 {
983 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
984 }
985
986 /**
987 * @brief Enable update period.
988 *
989 * Register|BitsName
990 * --------|--------
991 * UPDATE | SSPRD
992 *
993 * @param PWMx PWM instance
994 * @retval None
995 */
996 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
997 {
998 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
999 }
1000
1001 /**
1002 * @brief Disable update period.
1003 *
1004 * Register|BitsName
1005 * --------|--------
1006 * UPDATE | SSPRD
1007 *
1008 * @param PWMx PWM instance
1009 * @retval None
1010 */
1011 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
1012 {
1013 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
1014 }
1015
1016 /**
1017 * @brief Indicate whether the update period is enabled.
1018 *
1019 * Register|BitsName
1020 * --------|--------
1021 * UPDATE | SSPRD
1022 *
1023 * @param PWMx PWM instance
1024 * @retval State of bit (1 or 0).
1025 */
1026 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
1027 {
1028 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
1029 }
1030
1031 /**
1032 * @brief Enable update compareA0.
1033 *
1034 * Register|BitsName
1035 * --------|--------
1036 * UPDATE | SSCMPA0
1037 *
1038 * @param PWMx PWM instance
1039 * @retval None
1040 */
1041 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
1042 {
1043 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1044 }
1045
1046 /**
1047 * @brief Disable update compareA0.
1048 *
1049 * Register|BitsName
1050 * --------|--------
1051 * UPDATE | SSCMPA0
1052 *
1053 * @param PWMx PWM instance
1054 * @retval None
1055 */
1056 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
1057 {
1058 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1059 }
1060
1061 /**
1062 * @brief Indicate whether the update compareA0 is enabled.
1063 *
1064 * Register|BitsName
1065 * --------|--------
1066 * UPDATE | SSCMPA0
1067 *
1068 * @param PWMx PWM instance
1069 * @retval State of bit (1 or 0).
1070 */
1071 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
1072 {
1073 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
1074 }
1075
1076 /**
1077 * @brief Enable update compareA1.
1078 *
1079 * Register|BitsName
1080 * --------|--------
1081 * UPDATE | SSCMPA1
1082 *
1083 * @param PWMx PWM instance
1084 * @retval None
1085 */
1086 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
1087 {
1088 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1089 }
1090
1091 /**
1092 * @brief Disable update compareA1.
1093 *
1094 * Register|BitsName
1095 * --------|--------
1096 * UPDATE | SSCMPA1
1097 *
1098 * @param PWMx PWM instance
1099 * @retval None
1100 */
1101 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
1102 {
1103 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1104 }
1105
1106 /**
1107 * @brief Indicate whether the update compareA1 is enabled.
1108 *
1109 * Register|BitsName
1110 * --------|--------
1111 * UPDATE | SSCMPA1
1112 *
1113 * @param PWMx PWM instance
1114 * @retval State of bit (1 or 0).
1115 */
1116 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
1117 {
1118 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
1119 }
1120
1121 /**
1122 * @brief Enable update compareB0.
1123 *
1124 * Register|BitsName
1125 * --------|--------
1126 * UPDATE | SSCMPB0
1127 *
1128 * @param PWMx PWM instance
1129 * @retval None
1130 */
1131 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
1132 {
1133 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1134 }
1135
1136 /**
1137 * @brief Disable update compareB0.
1138 *
1139 * Register|BitsName
1140 * --------|--------
1141 * UPDATE | SSCMPB0
1142 *
1143 * @param PWMx PWM instance
1144 * @retval None
1145 */
1146 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
1147 {
1148 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1149 }
1150
1151 /**
1152 * @brief Indicate whether the update compareB0 is enabled.
1153 *
1154 * Register|BitsName
1155 * --------|--------
1156 * UPDATE | SSCMPB0
1157 *
1158 * @param PWMx PWM instance
1159 * @retval State of bit (1 or 0).
1160 */
1161 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
1162 {
1163 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
1164 }
1165
1166 /**
1167 * @brief Enable update compareB1.
1168 *
1169 * Register|BitsName
1170 * --------|--------
1171 * UPDATE | SSCMPB1
1172 *
1173 * @param PWMx PWM instance
1174 * @retval None
1175 */
1176 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
1177 {
1178 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1179 }
1180
1181 /**
1182 * @brief Disable update compareB1.
1183 *
1184 * Register|BitsName
1185 * --------|--------
1186 * UPDATE | SSCMPB1
1187 *
1188 * @param PWMx PWM instance
1189 * @retval None
1190 */
1191 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
1192 {
1193 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1194 }
1195
1196 /**
1197 * @brief Indicate whether the update compareB1 is enabled.
1198 *
1199 * Register|BitsName
1200 * --------|--------
1201 * UPDATE | SSCMPB1
1202 *
1203 * @param PWMx PWM instance
1204 * @retval State of bit (1 or 0).
1205 */
1206 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
1207 {
1208 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
1209 }
1210
1211 /**
1212 * @brief Enable update compareC0.
1213 *
1214 * Register|BitsName
1215 * --------|--------
1216 * UPDATE | SSCMPC0
1217 *
1218 * @param PWMx PWM instance
1219 * @retval None
1220 */
1221 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
1222 {
1223 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1224 }
1225
1226 /**
1227 * @brief Disable update compareC0.
1228 *
1229 * Register|BitsName
1230 * --------|--------
1231 * UPDATE | SSCMPC0
1232 *
1233 * @param PWMx PWM instance
1234 * @retval None
1235 */
1236 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
1237 {
1238 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1239 }
1240
1241 /**
1242 * @brief Indicate whether the update compareC0 is enabled.
1243 *
1244 * Register|BitsName
1245 * --------|--------
1246 * UPDATE | SSCMPC0
1247 *
1248 * @param PWMx PWM instance
1249 * @retval State of bit (1 or 0).
1250 */
1251 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
1252 {
1253 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
1254 }
1255
1256 /**
1257 * @brief Enable update compareC1.
1258 *
1259 * Register|BitsName
1260 * --------|--------
1261 * UPDATE | SSCMPC1
1262 *
1263 * @param PWMx PWM instance
1264 * @retval None
1265 */
1266 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
1267 {
1268 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1269 }
1270
1271 /**
1272 * @brief Disable update compareC1.
1273 *
1274 * Register|BitsName
1275 * --------|--------
1276 * UPDATE | SSCMPC1
1277 *
1278 * @param PWMx PWM instance
1279 * @retval None
1280 */
1281 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
1282 {
1283 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1284 }
1285
1286 /**
1287 * @brief Indicate whether the update compareC1 is enabled.
1288 *
1289 * Register|BitsName
1290 * --------|--------
1291 * UPDATE | SSCMPC1
1292 *
1293 * @param PWMx PWM instance
1294 * @retval State of bit (1 or 0).
1295 */
1296 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
1297 {
1298 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
1299 }
1300
1301 /**
1302 * @brief Enable update breath period.
1303 *
1304 * Register|BitsName
1305 * --------|--------
1306 * UPDATE | SSBRPRD
1307 *
1308 * @param PWMx PWM instance
1309 * @retval None
1310 */
1311 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
1312 {
1313 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1314 }
1315
1316 /**
1317 * @brief Disable update breath period.
1318 *
1319 * Register|BitsName
1320 * --------|--------
1321 * UPDATE | SSBRPRD
1322 *
1323 * @param PWMx PWM instance
1324 * @retval None
1325 */
1326 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
1327 {
1328 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1329 }
1330
1331 /**
1332 * @brief Indicate whether the update breath period is enabled.
1333 *
1334 * Register|BitsName
1335 * --------|--------
1336 * UPDATE | SSBRPRD
1337 *
1338 * @param PWMx PWM instance
1339 * @retval State of bit (1 or 0).
1340 */
1341 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
1342 {
1343 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
1344 }
1345
1346 /**
1347 * @brief Enable update hold period.
1348 *
1349 * Register|BitsName
1350 * --------|--------
1351 * UPDATE | SSHOLD
1352 *
1353 * @param PWMx PWM instance
1354 * @retval None
1355 */
1356 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
1357 {
1358 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1359 }
1360
1361 /**
1362 * @brief Disable update hold period.
1363 *
1364 * Register|BitsName
1365 * --------|--------
1366 * UPDATE | SSHOLD
1367 *
1368 * @param PWMx PWM instance
1369 * @retval None
1370 */
1371 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1372 {
1373 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1374 }
1375
1376 /**
1377 * @brief Indicate whether the update hold period is enabled.
1378 *
1379 * Register|BitsName
1380 * --------|--------
1381 * UPDATE | SSHOLD
1382 *
1383 * @param PWMx PWM instance
1384 * @retval State of bit (1 or 0).
1385 */
1386 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1387 {
1388 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1389 }
1390
1391 /**
1392 * @brief Enable update active event.
1393 *
1394 * Register|BitsName
1395 * --------|--------
1396 * UPDATE | SSAQCTRL
1397 *
1398 * @param PWMx PWM instance
1399 * @retval None
1400 */
1401 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1402 {
1403 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1404 }
1405
1406 /**
1407 * @brief Disable update active event.
1408 *
1409 * Register|BitsName
1410 * --------|--------
1411 * UPDATE | SSAQCTRL
1412 *
1413 * @param PWMx PWM instance
1414 * @retval None
1415 */
1416 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1417 {
1418 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1419 }
1420
1421 /**
1422 * @brief Indicate whether the update active event is enabled.
1423 *
1424 * Register|BitsName
1425 * --------|--------
1426 * UPDATE | SSAQCTRL
1427 *
1428 * @param PWMx PWM instance
1429 * @retval State of bit (1 or 0).
1430 */
1431 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1432 {
1433 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1434 }
1435
1436 /**
1437 * @brief Set the PWM prescaler.
1438 *
1439 * Register|BitsName
1440 * --------|--------
1441 * PRD | PRD
1442 *
1443 * @param PWMx PWM instance
1444 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1445 * @retval None
1446 */
1447 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1448 {
1449 WRITE_REG(PWMx->PRD, prescaler);
1450 }
1451
1452 /**
1453 * @brief Get the PWM prescaler.
1454 *
1455 * Register|BitsName
1456 * --------|--------
1457 * PRD | PRD
1458 *
1459 * @param PWMx PWM instance
1460 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1461 */
1462 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1463 {
1464 return (READ_REG(PWMx->PRD));
1465 }
1466
1467 /**
1468 * @brief Set the PWM compare counter A0.
1469 *
1470 * Register|BitsName
1471 * --------|--------
1472 * CMPA0 | CMPA0
1473 *
1474 * @param PWMx PWM instance
1475 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1476 * @retval None
1477 */
1478 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1479 {
1480 WRITE_REG(PWMx->CMPA0, compare);
1481 }
1482
1483 /**
1484 * @brief Get the PWM compare counter A0.
1485 *
1486 * Register|BitsName
1487 * --------|--------
1488 * CMPA0 | CMPA0
1489 *
1490 * @param PWMx PWM instance
1491 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1492 */
1493 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1494 {
1495 return (READ_REG(PWMx->CMPA0));
1496 }
1497
1498 /**
1499 * @brief Set the PWM compare counter A1.
1500 *
1501 * Register|BitsName
1502 * --------|--------
1503 * CMPA1 | CMPA1
1504 *
1505 * @param PWMx PWM instance
1506 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1507 * @retval None
1508 */
1509 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1510 {
1511 WRITE_REG(PWMx->CMPA1, compare);
1512 }
1513
1514 /**
1515 * @brief Get the PWM compare counter A1.
1516 *
1517 * Register|BitsName
1518 * --------|--------
1519 * CMPA1 | CMPA1
1520 *
1521 * @param PWMx PWM instance
1522 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1523 */
1524 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1525 {
1526 return (READ_REG(PWMx->CMPA1));
1527 }
1528
1529 /**
1530 * @brief Set the PWM compare counter B0.
1531 *
1532 * Register|BitsName
1533 * --------|--------
1534 * CMPB0 | CMPB0
1535 *
1536 * @param PWMx PWM instance
1537 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1538 * @retval None
1539 */
1540 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1541 {
1542 WRITE_REG(PWMx->CMPB0, compare);
1543 }
1544
1545 /**
1546 * @brief Get the PWM compare counter B0.
1547 *
1548 * Register|BitsName
1549 * --------|--------
1550 * CMPB0 | CMPB0
1551 *
1552 * @param PWMx PWM instance
1553 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1554 */
1555 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1556 {
1557 return (READ_REG(PWMx->CMPB0));
1558 }
1559
1560 /**
1561 * @brief Set the PWM compare counter B1.
1562 *
1563 * Register|BitsName
1564 * --------|--------
1565 * CMPB1 | CMPB1
1566 *
1567 * @param PWMx PWM instance
1568 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1569 * @retval None
1570 */
1571 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1572 {
1573 WRITE_REG(PWMx->CMPB1, compare);
1574 }
1575
1576 /**
1577 * @brief Get the PWM compare counter B1.
1578 *
1579 * Register|BitsName
1580 * --------|--------
1581 * CMPB1 | CMPB1
1582 *
1583 * @param PWMx PWM instance
1584 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1585 */
1586 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1587 {
1588 return (READ_REG(PWMx->CMPB1));
1589 }
1590
1591 /**
1592 * @brief Set the PWM compare counter C0.
1593 *
1594 * Register|BitsName
1595 * --------|--------
1596 * CMPC0 | CMPC0
1597 *
1598 * @param PWMx PWM instance
1599 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1600 * @retval None
1601 */
1602 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1603 {
1604 WRITE_REG(PWMx->CMPC0, compare);
1605 }
1606
1607 /**
1608 * @brief Get the PWM compare counter C0.
1609 *
1610 * Register|BitsName
1611 * --------|--------
1612 * CMPC0 | CMPC0
1613 *
1614 * @param PWMx PWM instance
1615 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1616 */
1617 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1618 {
1619 return (READ_REG(PWMx->CMPC0));
1620 }
1621
1622 /**
1623 * @brief Set the PWM compare counter C1.
1624 *
1625 * Register|BitsName
1626 * --------|--------
1627 * CMPC1 | CMPC1
1628 *
1629 * @param PWMx PWM instance
1630 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1631 * @retval None
1632 */
1633 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1634 {
1635 WRITE_REG(PWMx->CMPC1, compare);
1636 }
1637
1638 /**
1639 * @brief Get the PWM compare counter C1.
1640 *
1641 * Register|BitsName
1642 * --------|--------
1643 * CMPC1 | CMPC1
1644 *
1645 * @param PWMx PWM instance
1646 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1647 */
1648 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1649 {
1650 return (READ_REG(PWMx->CMPC1));
1651 }
1652
1653 /**
1654 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1655 *
1656 * Register|BitsName
1657 * --------|--------
1658 * AQCTRL | A0
1659 *
1660 * @param PWMx PWM instance
1661 * @param action_event This parameter can be one of the following values:
1662 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1663 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1664 * @arg @ref LL_PWM_ACTIONEVENT_SET
1665 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1666 * @retval None
1667 */
1668 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1669 {
1670 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1671 }
1672
1673 /**
1674 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1675 *
1676 * Register|BitsName
1677 * --------|--------
1678 * AQCTRL | A0
1679 *
1680 * @param PWMx PWM instance
1681 * @retval Return value can be one of the following values:
1682 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1683 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1684 * @arg @ref LL_PWM_ACTIONEVENT_SET
1685 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1686 */
1687 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1688 {
1689 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1690 }
1691
1692 /**
1693 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1694 *
1695 * Register|BitsName
1696 * --------|--------
1697 * AQCTRL | A1
1698 *
1699 * @param PWMx PWM instance
1700 * @param action_event This parameter can be one of the following values:
1701 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1702 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1703 * @arg @ref LL_PWM_ACTIONEVENT_SET
1704 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1705 * @retval None
1706 */
1707 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1708 {
1709 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1710 }
1711
1712 /**
1713 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1714 *
1715 * Register|BitsName
1716 * --------|--------
1717 * AQCTRL | A1
1718 *
1719 * @param PWMx PWM instance
1720 * @retval Return value can be one of the following values:
1721 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1722 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1723 * @arg @ref LL_PWM_ACTIONEVENT_SET
1724 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1725 */
1726 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1727 {
1728 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1729 }
1730
1731 /**
1732 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1733 *
1734 * Register|BitsName
1735 * --------|--------
1736 * AQCTRL | B0
1737 *
1738 * @param PWMx PWM instance
1739 * @param action_event This parameter can be one of the following values:
1740 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1741 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1742 * @arg @ref LL_PWM_ACTIONEVENT_SET
1743 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1744 * @retval None
1745 */
1746 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1747 {
1748 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1749 }
1750
1751 /**
1752 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1753 *
1754 * Register|BitsName
1755 * --------|--------
1756 * AQCTRL | B0
1757 *
1758 * @param PWMx PWM instance
1759 * @retval Return value can be one of the following values:
1760 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1761 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1762 * @arg @ref LL_PWM_ACTIONEVENT_SET
1763 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1764 */
1765 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1766 {
1767 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1768 }
1769
1770 /**
1771 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1772 *
1773 * Register|BitsName
1774 * --------|--------
1775 * AQCTRL | B1
1776 *
1777 * @param PWMx PWM instance
1778 * @param action_event This parameter can be one of the following values:
1779 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1780 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1781 * @arg @ref LL_PWM_ACTIONEVENT_SET
1782 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1783 * @retval None
1784 */
1785 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1786 {
1787 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1788 }
1789
1790 /**
1791 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1792 *
1793 * Register|BitsName
1794 * --------|--------
1795 * AQCTRL | B1
1796 *
1797 * @param PWMx PWM instance
1798 * @retval Return value can be one of the following values:
1799 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1800 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1801 * @arg @ref LL_PWM_ACTIONEVENT_SET
1802 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1803 */
1804 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1805 {
1806 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1807 }
1808
1809 /**
1810 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1811 *
1812 * Register|BitsName
1813 * --------|--------
1814 * AQCTRL | C0
1815 *
1816 * @param PWMx PWM instance
1817 * @param action_event This parameter can be one of the following values:
1818 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1819 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1820 * @arg @ref LL_PWM_ACTIONEVENT_SET
1821 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1822 * @retval None
1823 */
1824 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1825 {
1826 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1827 }
1828
1829 /**
1830 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1831 *
1832 * Register|BitsName
1833 * --------|--------
1834 * AQCTRL | C0
1835 *
1836 * @param PWMx PWM instance
1837 * @retval Return value can be one of the following values:
1838 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1839 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1840 * @arg @ref LL_PWM_ACTIONEVENT_SET
1841 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1842 */
1843 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1844 {
1845 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1846 }
1847
1848 /**
1849 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1850 *
1851 * Register|BitsName
1852 * --------|--------
1853 * AQCTRL | C1
1854 *
1855 * @param PWMx PWM instance
1856 * @param action_event This parameter can be one of the following values:
1857 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1858 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1859 * @arg @ref LL_PWM_ACTIONEVENT_SET
1860 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1861 * @retval None
1862 */
1863 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1864 {
1865 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1866 }
1867
1868 /**
1869 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1870 *
1871 * Register|BitsName
1872 * --------|--------
1873 * AQCTRL | C1
1874 *
1875 * @param PWMx PWM instance
1876 * @retval Return value can be one of the following values:
1877 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1878 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1879 * @arg @ref LL_PWM_ACTIONEVENT_SET
1880 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1881 */
1882 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1883 {
1884 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1885 }
1886
1887 /**
1888 * @brief Set the breath prescaler in breath mode.
1889 *
1890 * Register|BitsName
1891 * --------|--------
1892 * BRPRD | BRPRD
1893 *
1894 * @param PWMx PWM instance
1895 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1896 * @retval None
1897 */
1898 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1899 {
1900 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1901 }
1902
1903 /**
1904 * @brief Get the breath prescaler in breath mode.
1905 *
1906 * Register|BitsName
1907 * --------|--------
1908 * BRPRD | BRPRD
1909 *
1910 * @param PWMx PWM instance
1911 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1912 */
1913 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1914 {
1915 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1916 }
1917
1918 /**
1919 * @brief Set the hold prescaler in breath mode.
1920 *
1921 * Register|BitsName
1922 * --------|--------
1923 * HOLD | HOLD
1924 *
1925 * @param PWMx PWM instance
1926 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1927 * @retval None
1928 */
1929 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1930 {
1931 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1932 }
1933
1934 /**
1935 * @brief Get the hold prescaler in breath mode.
1936 *
1937 * Register|BitsName
1938 * --------|--------
1939 * HOLD | HOLD
1940 *
1941 * @param PWMx PWM instance
1942 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1943 */
1944 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1945 {
1946 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1947 }
1948
1949 /**
1950 * @brief Set the stop level in breath mode.
1951 *
1952 * Register|BitsName
1953 * --------|--------
1954 * MODE | BREATH_PAUSE_LEVEL
1955 *
1956 * @param PWMx PWM breath stop level
1957 * @param breathstop_lvl This parameter can be set with 0 or 1.
1958 * @retval None
1959 */
1960 __STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
1961 {
1962 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL, breathstop_lvl << PWM_MODE_BREATH_PAUSE_LEVEL_Pos);
1963 }
1964
1965 /**
1966 * @brief Get the stop level in breath mode.
1967 *
1968 * Register|BitsName
1969 * --------|--------
1970 * MODE | BREATH_PAUSE_LEVEL
1971 *
1972 * @param PWMx PWM breath stop level
1973 * @retval Return value of 0 or 1.
1974 */
1975 __STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
1976 {
1977 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL));
1978 }
1979
1980 /**
1981 * @brief Set the number of PWM period cycle in flicker mode or coding mode.
1982 *
1983 * Register|BitsName
1984 * --------|--------
1985 * PRD_CYCLES | PRD_CYCLES
1986 *
1987 * @param PWMx
1988 * @param prd_cycles This parameter control the number of period cycles, when set to 0 will continuously generate waveform.
1989 * @retval None.
1990 */
1991 __STATIC_INLINE void ll_pwm_set_prd_cycles(pwm_regs_t *PWMx, uint32_t prd_cycles)
1992 {
1993 WRITE_REG(PWMx->PRD_CYCLES, prd_cycles);
1994 }
1995
1996 /**
1997 * @brief Get the number of PWM period cycle.
1998 *
1999 * Register|BitsName
2000 * --------|--------
2001 * PRD_CYCLES | PRD_CYCLES
2002 *
2003 * @param PWMx
2004 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
2005 */
2006 __STATIC_INLINE uint32_t ll_pwm_get_prd_cycles(pwm_regs_t *PWMx)
2007 {
2008 return (READ_REG(PWMx->PRD_CYCLES));
2009 }
2010
2011 /**
2012 * @brief Set the waiting time count in coding mode.
2013 *
2014 * Register|BitsName
2015 * --------|--------
2016 * WAIT_TIME | WAIT_TIME
2017 *
2018 * @param PWMx
2019 * @param waiting_time This parameter control PWM waiting time in the coding mode.
2020 * @retval None.
2021 */
2022 __STATIC_INLINE void ll_pwm_set_waiting_time(pwm_regs_t *PWMx, uint32_t waiting_time)
2023 {
2024 WRITE_REG(PWMx->WAIT_TIME, waiting_time);
2025 }
2026
2027 /**
2028 * @brief Get the waiting time count.
2029 *
2030 * Register|BitsName
2031 * --------|--------
2032 * WAIT_TIME | WAIT_TIME
2033 *
2034 * @param PWMx
2035 * @retval Return count value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
2036 */
2037 __STATIC_INLINE uint32_t ll_pwm_get_waiting_time(pwm_regs_t *PWMx)
2038 {
2039 return (READ_REG(PWMx->WAIT_TIME));
2040 }
2041
2042 /**
2043 * @brief Set the valid coding data width in coding mode.
2044 *
2045 * Register|BitsName
2046 * --------|--------
2047 * DATA_WIDTH_VALID | DATA_WIDTH_VALID
2048 *
2049 * @param PWMx
2050 * @param data_valid_width This parameter control coding data valid width = DATA_WIDTH_VALID + 1,
2051 * DATA_WIDTH_VALID value ranges between Min_Data = 0x0 and Max_Data = 0x1F.
2052 * @retval None.
2053 */
2054 __STATIC_INLINE void ll_pwm_set_data_width_valid(pwm_regs_t *PWMx, uint8_t data_valid_width)
2055 {
2056 MODIFY_REG(PWMx->DATA_WIDTH_VALID, PWM_DATA_WIDTH_VALID, data_valid_width << PWM_DATA_WIDTH_VALID_Pos);
2057 }
2058
2059 /**
2060 * @brief Get the valid coding data width.
2061 *
2062 * Register|BitsName
2063 * --------|--------
2064 * DATA_WIDTH_VALID | DATA_WIDTH_VALID
2065 *
2066 * @param PWMx
2067 * @retval Return the valid data width in coding mode
2068 */
2069 __STATIC_INLINE uint8_t ll_pwm_get_data_width_valid(pwm_regs_t *PWMx)
2070 {
2071 return (uint8_t)(READ_REG(PWMx->DATA_WIDTH_VALID) & PWM_DATA_WIDTH_VALID);
2072 }
2073
2074 /**
2075 * @brief Set the PWM coding data in coding mode.
2076 *
2077 * Register|BitsName
2078 * --------|--------
2079 * CODING_DATA | CODING_DATA
2080 *
2081 * @param PWMx
2082 * @param coding_data This parameter control PWM generate waveform by coding data.
2083 * @retval None.
2084 */
2085 __STATIC_INLINE void ll_pwm_set_coding_data(pwm_regs_t *PWMx, uint32_t coding_data)
2086 {
2087 WRITE_REG(PWMx->CODING_DATA, coding_data);
2088 }
2089
2090 /**
2091 * @brief Get the PWM coding data in coding mode.
2092 *
2093 * Register|BitsName
2094 * --------|--------
2095 * CODING_DATA | CODING_DATA
2096 *
2097 * @param PWMx
2098 * @retval Return the coding_data value in coding mode.
2099 */
2100 __STATIC_INLINE uint32_t ll_pwm_get_coding_data(pwm_regs_t *PWMx)
2101 {
2102 return (READ_REG(PWMx->CODING_DATA));
2103 }
2104
2105 /**
2106 * @brief Get pwm coding status
2107 *
2108 * Register|BitsName
2109 * --------|--------
2110 * CODING_STATUS | CODING_STATUS
2111 *
2112 * @param PWMx
2113 * @retval Return the pwm coding status
2114 */
2115 __STATIC_INLINE uint32_t ll_pwm_get_coding_status(pwm_regs_t *PWMx)
2116 {
2117 return (READ_REG(PWMx->CODING_STATUS));
2118 }
2119
2120 /**
2121 * @brief Clear pwma coding error status.
2122 *
2123 * Register|BitsName
2124 * --------|--------
2125 * CLR_CODING_STATUS | CODING_A_ERROR_CLR
2126 *
2127 * @param PWMx
2128 * @retval None.
2129 */
2130 __STATIC_INLINE void ll_pwm_clr_coding_a_error_status(pwm_regs_t *PWMx)
2131 {
2132 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CODING_STATUS_CODING_A_ERROR_CLR, 0x1 << PWM_CODING_STATUS_CODING_A_ERROR_CLR_Pos);
2133 }
2134
2135 /**
2136 * @brief Get pwma coding error status
2137 *
2138 * Register|BitsName
2139 * --------|--------
2140 * CODING_STATUS | CODING_A_ERROR
2141 *
2142 * @param PWMx
2143 * @retval Return the pwma coding error status
2144 */
2145 __STATIC_INLINE uint8_t ll_pwm_get_coding_a_error_status(pwm_regs_t *PWMx)
2146 {
2147 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_A_ERROR) == (PWM_CODING_STATUS_CODING_A_ERROR));
2148 }
2149
2150 /**
2151 * @brief Clear pwmb coding error status.
2152 *
2153 * Register|BitsName
2154 * --------|--------
2155 * CLR_CODING_STATUS | CODING_B_ERROR_CLR
2156 *
2157 * @param PWMx
2158 * @retval None.
2159 */
2160 __STATIC_INLINE void ll_pwm_clr_coding_b_error_status(pwm_regs_t *PWMx)
2161 {
2162 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CODING_STATUS_CODING_B_ERROR_CLR, 0x1 << PWM_CODING_STATUS_CODING_B_ERROR_CLR_Pos);
2163 }
2164
2165 /**
2166 * @brief Get pwmb coding error status
2167 *
2168 * Register|BitsName
2169 * --------|--------
2170 * CODING_STATUS | CODING_B_ERROR
2171 *
2172 * @param PWMx
2173 * @retval Return the pwmb coding error status
2174 */
2175 __STATIC_INLINE uint8_t ll_pwm_get_coding_b_error_status(pwm_regs_t *PWMx)
2176 {
2177 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_B_ERROR) == (PWM_CODING_STATUS_CODING_B_ERROR));
2178 }
2179
2180 /**
2181 * @brief Clear pwmc coding error status.
2182 *
2183 * Register|BitsName
2184 * --------|--------
2185 * CLR_CODING_STATUS | CODING_C_ERROR_CLR
2186 *
2187 * @param PWMx
2188 * @retval None.
2189 */
2190 __STATIC_INLINE void ll_pwm_clr_coding_c_error_status(pwm_regs_t *PWMx)
2191 {
2192 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CODING_STATUS_CODING_C_ERROR_CLR, 0x1 << PWM_CODING_STATUS_CODING_C_ERROR_CLR_Pos);
2193 }
2194
2195 /**
2196 * @brief Get pwmc coding error status
2197 *
2198 * Register|BitsName
2199 * --------|--------
2200 * CODING_STATUS | CODING_C_ERROR
2201 *
2202 * @param PWMx
2203 * @retval Return the pwmc coding error status
2204 */
2205 __STATIC_INLINE uint8_t ll_pwm_get_coding_c_error_status(pwm_regs_t *PWMx)
2206 {
2207 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_C_ERROR) == (PWM_CODING_STATUS_CODING_C_ERROR));
2208 }
2209
2210 /**
2211 * @brief Clear coding done status.
2212 *
2213 * Register|BitsName
2214 * --------|--------
2215 * CLR_CODING_STATUS | CODING_DONE_CLR
2216 *
2217 * @param PWMx
2218 * @retval None.
2219 */
2220 __STATIC_INLINE void ll_pwm_clr_coding_done_status(pwm_regs_t *PWMx)
2221 {
2222 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CODING_STATUS_CODING_DONE_CLR, 0x1 << PWM_CODING_STATUS_CODING_DONE_CLR_Pos);
2223 }
2224
2225 /**
2226 * @brief Get PWM conding done status
2227 *
2228 * Register|BitsName
2229 * --------|--------
2230 * CODING_STATUS | CODING_DONE
2231 *
2232 * @param PWMx
2233 * @retval Return the coding done interrupt status
2234 */
2235 __STATIC_INLINE uint8_t ll_pwm_get_coding_done_status(pwm_regs_t *PWMx)
2236 {
2237 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_DONE) == (PWM_CODING_STATUS_CODING_DONE));
2238 }
2239
2240 /**
2241 * @brief Clear coding load status.
2242 *
2243 * Register|BitsName
2244 * --------|--------
2245 * CLR_CODING_STATUS | CODING_LAOD_CLR
2246 *
2247 * @param PWMx
2248 * @retval None.
2249 */
2250 __STATIC_INLINE void ll_pwm_clr_coding_load_status(pwm_regs_t *PWMx)
2251 {
2252 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CODING_STATUS_CODING_LOAD_CLR, 0x1 << PWM_CODING_STATUS_CODING_LOAD_CLR_Pos);
2253 }
2254
2255 /**
2256 * @brief Get PWM conding load status
2257 *
2258 * Register|BitsName
2259 * --------|--------
2260 * CODING_STATUS | CODING_LOAD
2261 *
2262 * @param PWMx
2263 * @retval Return the coding load interrupt status
2264 */
2265 __STATIC_INLINE uint8_t ll_pwm_get_coding_load_status(pwm_regs_t *PWMx)
2266 {
2267 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_LOAD) == (PWM_CODING_STATUS_CODING_LOAD));
2268 }
2269
2270 /**
2271 * @brief Get the coding data register address used for DMA transfer
2272 *
2273 * Register|BitsName
2274 * --------|--------
2275 * MODE | CODING_DATA
2276 *
2277 * @param PWMx
2278 * @retval Address of coding data register
2279 */
2280 __STATIC_INLINE uint32_t ll_pwm_dma_get_register_address(pwm_regs_t *PWMx)
2281 {
2282 return ((uint32_t) &(PWMx->CODING_DATA));
2283 }
2284
2285 /** @} */
2286
2287 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
2288 * @{
2289 */
2290
2291 /**
2292 * @brief De-initialize PWM registers (Registers restored to their default values).
2293 * @param PWMx PWM instance
2294 * @retval An error_status_t enumeration value:
2295 * - SUCCESS: PWM registers are de-initialized
2296 * - ERROR: PWM registers are not de-initialized
2297 */
2298 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
2299
2300 /**
2301 * @brief Initialize PWM registers according to the specified
2302 * parameters in PWM_InitStruct.
2303 * @param PWMx PWM instance
2304 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
2305 * information for the specified PWM peripheral.
2306 * @retval An error_status_t enumeration value:
2307 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
2308 * - ERROR: Problem occurred during PWM Registers initialization
2309 */
2310 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
2311
2312 /**
2313 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
2314 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
2315 * whose fields will be set to default values.
2316 * @retval None
2317 */
2318 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
2319
2320 /** @} */
2321
2322 /** @} */
2323
2324 #endif /* PWM0 || PWM1 */
2325
2326 #ifdef __cplusplus
2327 }
2328 #endif
2329
2330 #endif /* __GR533X_LL_PWM_H__ */
2331
2332 /** @} */
2333
2334 /** @} */
2335
2336 /** @} */
_ll_pwm_none_coding_channel_init_t::drive_polarity
uint8_t drive_polarity
Definition: gr533x_ll_pwm.h:96
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: gr533x_ll_pwm.h:1281
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: gr533x_ll_pwm.h:614
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: gr533x_ll_pwm.h:1602
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr533x_ll_pwm.h:1746
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: gr533x_ll_pwm.h:1617
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, ll_pwm_mode_t mode)
Set PWM mode.
Definition: gr533x_ll_pwm.h:494
_ll_pwm_coding_channel_init_t::ll_comp1
uint32_t ll_comp1
Definition: gr533x_ll_pwm.h:114
ll_pwm_get_prd_cycles
__STATIC_INLINE uint32_t ll_pwm_get_prd_cycles(pwm_regs_t *PWMx)
Get the number of PWM period cycle.
Definition: gr533x_ll_pwm.h:2006
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: gr533x_ll_pwm.h:1633
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: gr533x_ll_pwm.h:1478
ll_pwm_get_flicker_stop_level_c
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
Get the channel_c stop level in flicker mode.
Definition: gr533x_ll_pwm.h:752
ll_pwm_get_dma_en
__STATIC_INLINE uint8_t ll_pwm_get_dma_en(pwm_regs_t *PWMx)
Get DMA enable or disable.
Definition: gr533x_ll_pwm.h:890
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr533x_ll_pwm.h:1882
ll_pwm_get_coding_status
__STATIC_INLINE uint32_t ll_pwm_get_coding_status(pwm_regs_t *PWMx)
Get pwm coding status.
Definition: gr533x_ll_pwm.h:2115
ll_pwm_dma_get_register_address
__STATIC_INLINE uint32_t ll_pwm_dma_get_register_address(pwm_regs_t *PWMx)
Get the coding data register address used for DMA transfer.
Definition: gr533x_ll_pwm.h:2280
ll_pwm_set_data_width_valid
__STATIC_INLINE void ll_pwm_set_data_width_valid(pwm_regs_t *PWMx, uint8_t data_valid_width)
Set the valid coding data width in coding mode.
Definition: gr533x_ll_pwm.h:2054
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: gr533x_ll_pwm.h:197
_ll_pwm_none_coding_mode_init_t::hprescaler
uint32_t hprescaler
Definition: gr533x_ll_pwm.h:147
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: gr533x_ll_pwm.h:1416
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: gr533x_ll_pwm.h:1146
ll_pwm_set_dma_disable
__STATIC_INLINE void ll_pwm_set_dma_disable(pwm_regs_t *PWMx)
Set DMA disable in coding mode.
Definition: gr533x_ll_pwm.h:875
ll_pwm_none_coding_mode_init_t
struct _ll_pwm_none_coding_mode_init_t ll_pwm_none_coding_mode_init_t
LL PWM none coding mode Structure definition.
ll_pwm_get_waiting_time
__STATIC_INLINE uint32_t ll_pwm_get_waiting_time(pwm_regs_t *PWMx)
Get the waiting time count.
Definition: gr533x_ll_pwm.h:2037
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: gr533x_ll_pwm.h:951
_ll_pwm_none_coding_mode_init_t::channel_c
ll_pwm_none_coding_channel_init_t channel_c
Definition: gr533x_ll_pwm.h:161
ll_pwm_get_coding_c_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_c_error_status(pwm_regs_t *PWMx)
Get pwmc coding error status.
Definition: gr533x_ll_pwm.h:2205
_ll_pwm_init_t::none_coding_mode_cfg
ll_pwm_none_coding_mode_init_t none_coding_mode_cfg
Definition: gr533x_ll_pwm.h:206
_ll_pwm_init_t::ll_prd_cycles
uint32_t ll_prd_cycles
Definition: gr533x_ll_pwm.h:203
_ll_pwm_coding_mode_init_t::ll_period
uint32_t ll_period
Definition: gr533x_ll_pwm.h:170
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: gr533x_ll_pwm.h:1462
ll_pwm_get_coding_done_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_done_status(pwm_regs_t *PWMx)
Get PWM conding done status.
Definition: gr533x_ll_pwm.h:2235
ll_pwm_init
error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
_ll_pwm_none_coding_channel_init_t::duty
uint8_t duty
Definition: gr533x_ll_pwm.h:93
ll_pwm_set_waiting_time_level_a
__STATIC_INLINE void ll_pwm_set_waiting_time_level_a(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_a waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:768
_ll_pwm_none_coding_mode_init_t::breathstop_lvl
uint32_t breathstop_lvl
Definition: gr533x_ll_pwm.h:152
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: gr533x_ll_pwm.h:1493
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: gr533x_ll_pwm.h:1913
_ll_pwm_init_t::ll_mode
ll_pwm_mode_t ll_mode
Definition: gr533x_ll_pwm.h:198
_ll_pwm_coding_channel_init_t::ll_drive_polarity
uint8_t ll_drive_polarity
Definition: gr533x_ll_pwm.h:117
LL_PWM_CODING_MODE
@ LL_PWM_CODING_MODE
Definition: gr533x_ll_pwm.h:74
ll_pwm_coding_channel_init_t
struct _ll_pwm_coding_channel_init_t ll_pwm_coding_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: gr533x_ll_pwm.h:1371
ll_pwm_clr_coding_b_error_status
__STATIC_INLINE void ll_pwm_clr_coding_b_error_status(pwm_regs_t *PWMx)
Clear pwmb coding error status.
Definition: gr533x_ll_pwm.h:2160
ll_pwm_deinit
error_status_t ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
ll_pwm_get_data_width_valid
__STATIC_INLINE uint8_t ll_pwm_get_data_width_valid(pwm_regs_t *PWMx)
Get the valid coding data width.
Definition: gr533x_ll_pwm.h:2069
_ll_pwm_none_coding_mode_init_t::bprescaler
uint32_t bprescaler
Definition: gr533x_ll_pwm.h:141
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: gr533x_ll_pwm.h:1206
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: gr533x_ll_pwm.h:1401
_ll_pwm_init_t::coding_mode_cfg
ll_pwm_coding_mode_init_t coding_mode_cfg
Definition: gr533x_ll_pwm.h:209
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr533x_ll_pwm.h:1668
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: gr533x_ll_pwm.h:1509
ll_pwm_get_mode
__STATIC_INLINE ll_pwm_mode_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: gr533x_ll_pwm.h:520
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: gr533x_ll_pwm.h:1586
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: gr533x_ll_pwm.h:981
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr533x_ll_pwm.h:1785
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: gr533x_ll_pwm.h:430
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: gr533x_ll_pwm.h:1236
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr533x_ll_pwm.h:1765
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: gr533x_ll_pwm.h:1101
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: gr533x_ll_pwm.h:445
ll_pwm_set_coding_data
__STATIC_INLINE void ll_pwm_set_coding_data(pwm_regs_t *PWMx, uint32_t coding_data)
Set the PWM coding data in coding mode.
Definition: gr533x_ll_pwm.h:2085
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: gr533x_ll_pwm.h:1431
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: gr533x_ll_pwm.h:1071
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: gr533x_ll_pwm.h:1161
_ll_pwm_none_coding_mode_init_t
LL PWM none coding mode Structure definition.
Definition: gr533x_ll_pwm.h:131
ll_pwm_mode_t
ll_pwm_mode_t
LL PWM Mode definition.
Definition: gr533x_ll_pwm.h:71
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: gr533x_ll_pwm.h:1555
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: gr533x_ll_pwm.h:996
_ll_pwm_coding_mode_init_t::ll_channel_a
ll_pwm_coding_channel_init_t ll_channel_a
Definition: gr533x_ll_pwm.h:183
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: gr533x_ll_pwm.h:1356
ll_pwm_set_breath_stop_level
__STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
Set the stop level in breath mode.
Definition: gr533x_ll_pwm.h:1960
ll_pwm_set_flicker_stop_level_b
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_b stop level in flicker mode.
Definition: gr533x_ll_pwm.h:706
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: gr533x_ll_pwm.h:1898
ll_pwm_get_breath_stop_level
__STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
Get the stop level in breath mode.
Definition: gr533x_ll_pwm.h:1975
ll_pwm_clr_coding_done_status
__STATIC_INLINE void ll_pwm_clr_coding_done_status(pwm_regs_t *PWMx)
Clear coding done status.
Definition: gr533x_ll_pwm.h:2220
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: gr533x_ll_pwm.h:475
_ll_pwm_coding_channel_init_t::ll_waiting_time_lvl
uint8_t ll_waiting_time_lvl
Definition: gr533x_ll_pwm.h:122
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: gr533x_ll_pwm.h:1266
_ll_pwm_coding_channel_init_t::ll_comp0
uint32_t ll_comp0
Definition: gr533x_ll_pwm.h:111
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: gr533x_ll_pwm.h:1191
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: gr533x_ll_pwm.h:460
ll_pwm_get_coding_a_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_a_error_status(pwm_regs_t *PWMx)
Get pwma coding error status.
Definition: gr533x_ll_pwm.h:2145
_ll_pwm_coding_mode_init_t::ll_coding_channel_select
uint8_t ll_coding_channel_select
Definition: gr533x_ll_pwm.h:180
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: gr533x_ll_pwm.h:569
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr533x_ll_pwm.h:1863
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: gr533x_ll_pwm.h:1524
ll_pwm_set_prd_cycles
__STATIC_INLINE void ll_pwm_set_prd_cycles(pwm_regs_t *PWMx, uint32_t prd_cycles)
Set the number of PWM period cycle in flicker mode or coding mode.
Definition: gr533x_ll_pwm.h:1991
ll_pwm_none_coding_channel_init_t
struct _ll_pwm_none_coding_channel_init_t ll_pwm_none_coding_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_get_coding_data
__STATIC_INLINE uint32_t ll_pwm_get_coding_data(pwm_regs_t *PWMx)
Get the PWM coding data in coding mode.
Definition: gr533x_ll_pwm.h:2100
_ll_pwm_coding_mode_init_t::ll_data_width_valid
uint8_t ll_data_width_valid
Definition: gr533x_ll_pwm.h:176
ll_pwm_get_coding_load_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_load_status(pwm_regs_t *PWMx)
Get PWM conding load status.
Definition: gr533x_ll_pwm.h:2265
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: gr533x_ll_pwm.h:1026
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: gr533x_ll_pwm.h:1341
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: gr533x_ll_pwm.h:1131
LL_PWM_BREATH_MODE
@ LL_PWM_BREATH_MODE
Definition: gr533x_ll_pwm.h:73
ll_pwm_set_waiting_time
__STATIC_INLINE void ll_pwm_set_waiting_time(pwm_regs_t *PWMx, uint32_t waiting_time)
Set the waiting time count in coding mode.
Definition: gr533x_ll_pwm.h:2022
_ll_pwm_coding_mode_init_t::ll_waiting_time
uint32_t ll_waiting_time
Definition: gr533x_ll_pwm.h:173
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: gr533x_ll_pwm.h:1176
ll_pwm_get_waiting_time_level_b
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_b(pwm_regs_t *PWMx)
Get the channel_b waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:814
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: gr533x_ll_pwm.h:1011
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: gr533x_ll_pwm.h:1944
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: gr533x_ll_pwm.h:1056
ll_pwm_set_flicker_stop_level_c
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_c stop level in flicker mode.
Definition: gr533x_ll_pwm.h:737
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: gr533x_ll_pwm.h:1311
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: gr533x_ll_pwm.h:1041
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: gr533x_ll_pwm.h:1386
ll_pwm_set_waiting_time_level_c
__STATIC_INLINE void ll_pwm_set_waiting_time_level_c(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_c waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:830
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr533x_ll_pwm.h:1726
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: gr533x_ll_pwm.h:966
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: gr533x_ll_pwm.h:936
ll_pwm_clr_coding_load_status
__STATIC_INLINE void ll_pwm_clr_coding_load_status(pwm_regs_t *PWMx)
Clear coding load status.
Definition: gr533x_ll_pwm.h:2250
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: gr533x_ll_pwm.h:1929
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: gr533x_ll_pwm.h:1251
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: gr533x_ll_pwm.h:644
_ll_pwm_coding_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr533x_ll_pwm.h:110
_ll_pwm_none_coding_mode_init_t::channel_a
ll_pwm_none_coding_channel_init_t channel_a
Definition: gr533x_ll_pwm.h:155
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: gr533x_ll_pwm.h:1571
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: gr533x_ll_pwm.h:1296
_ll_pwm_none_coding_mode_init_t::prescaler
uint32_t prescaler
Definition: gr533x_ll_pwm.h:135
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: gr533x_ll_pwm.h:584
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: gr533x_ll_pwm.h:400
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: gr533x_ll_pwm.h:599
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: gr533x_ll_pwm.h:415
ll_pwm_get_flicker_stop_level_a
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
Get the channel_a stop level in flicker mode.
Definition: gr533x_ll_pwm.h:690
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: gr533x_ll_pwm.h:1540
ll_pwm_get_waiting_time_level_c
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_c(pwm_regs_t *PWMx)
Get the channel_c waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:845
ll_pwm_set_flicker_stop_level_a
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_a stop level in flicker mode.
Definition: gr533x_ll_pwm.h:675
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: gr533x_ll_pwm.h:554
_ll_pwm_none_coding_channel_init_t::flickerstop_lvl
uint32_t flickerstop_lvl
Definition: gr533x_ll_pwm.h:102
_ll_pwm_none_coding_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr533x_ll_pwm.h:92
_ll_pwm_coding_mode_init_t
LL PWM coding mode Structure definition.
Definition: gr533x_ll_pwm.h:169
ll_pwm_set_waiting_time_level_b
__STATIC_INLINE void ll_pwm_set_waiting_time_level_b(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_b waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:799
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr533x_ll_pwm.h:1824
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: gr533x_ll_pwm.h:629
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr533x_ll_pwm.h:1707
_ll_pwm_coding_mode_init_t::ll_channel_b
ll_pwm_coding_channel_init_t ll_channel_b
Definition: gr533x_ll_pwm.h:186
ll_pwm_get_flicker_stop_level_b
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
Get the channel_b stop level in flicker mode.
Definition: gr533x_ll_pwm.h:721
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
LL_PWM_FLICKER_MODE
@ LL_PWM_FLICKER_MODE
Definition: gr533x_ll_pwm.h:72
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: gr533x_ll_pwm.h:1648
ll_pwm_get_waiting_time_level_a
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_a(pwm_regs_t *PWMx)
Get the channel_a waiting time level in coding mode.
Definition: gr533x_ll_pwm.h:783
_ll_pwm_coding_mode_init_t::ll_channel_c
ll_pwm_coding_channel_init_t ll_channel_c
Definition: gr533x_ll_pwm.h:189
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: gr533x_ll_pwm.h:1326
_ll_pwm_none_coding_mode_init_t::align
uint32_t align
Definition: gr533x_ll_pwm.h:132
ll_pwm_set_dma_enable
__STATIC_INLINE void ll_pwm_set_dma_enable(pwm_regs_t *PWMx)
Set DMA enable in coding mode.
Definition: gr533x_ll_pwm.h:860
ll_pwm_clr_coding_c_error_status
__STATIC_INLINE void ll_pwm_clr_coding_c_error_status(pwm_regs_t *PWMx)
Clear pwmc coding error status.
Definition: gr533x_ll_pwm.h:2190
ll_pwm_get_coding_b_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_b_error_status(pwm_regs_t *PWMx)
Get pwmb coding error status.
Definition: gr533x_ll_pwm.h:2175
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr533x_ll_pwm.h:1687
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: gr533x_ll_pwm.h:1086
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: gr533x_ll_pwm.h:1447
_ll_pwm_none_coding_mode_init_t::channel_b
ll_pwm_none_coding_channel_init_t channel_b
Definition: gr533x_ll_pwm.h:158
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr533x_ll_pwm.h:1804
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: gr533x_ll_pwm.h:1221
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: gr533x_ll_pwm.h:659
ll_pwm_clr_coding_a_error_status
__STATIC_INLINE void ll_pwm_clr_coding_a_error_status(pwm_regs_t *PWMx)
Clear pwma coding error status.
Definition: gr533x_ll_pwm.h:2130
ll_pwm_coding_channel_select
__STATIC_INLINE void ll_pwm_coding_channel_select(pwm_regs_t *PWMx, uint8_t coding_channel)
Choose 3 channels operation in coding mode or only choose channel A operation in coding mode.
Definition: gr533x_ll_pwm.h:906
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: gr533x_ll_pwm.h:1116
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr533x_ll_pwm.h:1843
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: gr533x_ll_pwm.h:539
ll_pwm_coding_mode_init_t
struct _ll_pwm_coding_mode_init_t ll_pwm_coding_mode_init_t
LL PWM coding mode Structure definition.
ll_pwm_get_coding_channel
__STATIC_INLINE uint8_t ll_pwm_get_coding_channel(pwm_regs_t *PWMx)
Get PWM coding channel.
Definition: gr533x_ll_pwm.h:921