gr533x_hal_xqspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_hal_xqspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of XQSPI HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_XQSPI XQSPI
47 * @brief XQSPI HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_HAL_XQSPI_H__
53 #define __GR533x_HAL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_ll_xqspi.h"
61 #include "gr533x_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
64 /** @addtogroup HAL_XQSPI_ENUMERATIONS Enumerations
65 * @{
66 */
67
68 /** @defgroup HAL_XQSPI_state HAL XQSPI state
69 * @{
70 */
71
72 /**
73 * @brief HAL XQSPI State Enumerations definition
74 */
75 typedef enum
76 {
77 HAL_XQSPI_STATE_RESET = 0x00, /**< Peripheral not initialized */
78 HAL_XQSPI_STATE_READY = 0x01, /**< Peripheral initialized and ready for use */
79 HAL_XQSPI_STATE_BUSY = 0x02, /**< Peripheral in indirect mode and busy */
80 HAL_XQSPI_STATE_BUSY_INDIRECT_TX = 0x12, /**< Peripheral in indirect mode with transmission ongoing */
81 HAL_XQSPI_STATE_BUSY_INDIRECT_RX = 0x22, /**< Peripheral in indirect mode with reception ongoing */
82 HAL_XQSPI_STATE_ABORT = 0x08, /**< Peripheral with abort request ongoing */
83 HAL_XQSPI_STATE_ERROR = 0x04 /**< Peripheral in error */
84
85 } hal_xqspi_state_t;
86
87 /** @} */
88
89 /** @} */
90
91 /** @addtogroup HAL_XQSPI_STRUCTURES Structures
92 * @{
93 */
94
95 /** @defgroup XQSPI_Configuration XQSPI Configuration
96 * @{
97 */
98
99 /**
100 * @brief XQSPI init Structure definition
101 */
102 typedef struct _xqspi_init_t
103 {
104 uint32_t work_mode; /**< Specifies the work mode for XQSPI.
105 This parameter can be a value of @ref XQSPI_Work_Mode */
106
107 uint32_t cache_mode; /**< Specifies the cache mode for XIP mode.
108 This parameter can be a value of @ref XQSPI_Cache_Mode */
109
110 uint32_t read_cmd; /**< Specifies the read command for transmit in XIP mode.
111 This parameter can be a value of @ref XQSPI_Read_CMD */
112
113 uint32_t baud_rate; /**< Specifies the serial clock speed for transmit in both XIP and QSPI mode.
114 This parameter can be a value of @ref XQSPI_Baud_Rate */
115
116 uint32_t clock_mode; /**< Specifies the Clock Mode. It indicates the level that clock takes between commands.
117 This parameter can be a value of @ref XQSPI_Clock_Mode */
118
119 uint32_t cache_direct_map_en; /**< Specifies the XQSPI Cache work on direct map or 4-way set associative.
120 This parameter can be a value of @ref XQSPI_Direct_Map_Cache_EN.*/
121
122 uint32_t cache_flush; /**< Specifies the XQSPI Cache will be flushed or not.
123 This parameter can be a value of @ref XQSPI_Cache_Flush_EN.*/
124
125 ll_xqspi_hp_init_t hp_init; /**< Specifies the XQSPI HP mode Configuration.
126 This structures is defined @ref ll_xqspi_hp_init_t.*/
127
128 } xqspi_init_t;
129 /** @} */
130
131 /** @defgroup XQSPI_handle XQSPI handle
132 * @{
133 */
134
135 /**
136 * @brief XQSPI handle Structure definition
137 */
138 typedef struct _xqspi_handle_t
139 {
140 xqspi_regs_t *p_instance; /**< XQSPI registers base address */
141
142 xqspi_init_t init; /**< XQSPI communication parameters */
143
144 uint8_t *p_tx_buffer; /**< Pointer to XQSPI Tx transfer Buffer */
145
146 __IO uint32_t tx_xfer_size; /**< XQSPI Tx Transfer size */
147
148 __IO uint32_t tx_xfer_count; /**< XQSPI Tx Transfer Counter */
149
150 uint8_t *p_rx_buffer; /**< Pointer to XQSPI Rx transfer Buffer */
151
152 __IO uint32_t rx_xfer_size; /**< XQSPI Rx Transfer size */
153
154 __IO uint32_t rx_xfer_count; /**< XQSPI Rx Transfer Counter */
155
156 __IO hal_lock_t lock; /**< Locking object */
157
158 __IO hal_xqspi_state_t state; /**< XQSPI communication state */
159
160 __IO uint32_t error_code; /**< XQSPI Error code */
161
162 uint32_t retry; /**< Retry for the XQSPI flag access */
163
164 } xqspi_handle_t;
165 /** @} */
166
167 /** @defgroup XQSPI_Command XQSPI command
168 * @{
169 */
170
171 /**
172 * @brief XQSPI command Structure definition
173 */
174 typedef struct _xqspi_command_t
175 {
176 uint32_t inst; /**< Specifies the Instruction to be sent.
177 This parameter can be a value (8-bit) between 0x00 and 0xFF */
178
179 uint32_t addr; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according to AddressSize).
180 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
181
182 uint32_t inst_size; /**< Specifies the Instruction Size.
183 This parameter can be a value of @ref XQSPI_Instruction_Size */
184
185 uint32_t addr_size; /**< Specifies the Address Size.
186 This parameter can be a value of @ref XQSPI_Address_Size */
187
188 uint32_t dummy_cycles; /**< Specifies the Number of Dummy Cycles.
189 This parameter can be a number between 0 and 31 */
190
191 uint32_t inst_addr_mode; /**< Specifies the Instruction and Address Mode.
192 This parameter can be a value of @ref XQSPI_Inst_Addr_Mode */
193
194 uint32_t data_mode; /**< Specifies the Data Mode (used for dummy cycles and data phases).
195 This parameter can be a value of @ref XQSPI_Data_Mode */
196
197 uint32_t length; /**< Specifies the number of data to transfer. (This is the number of bytes).
198 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
199 until end of memory) */
200
201 } xqspi_command_t;
202 /** @} */
203
204 /** @} */
205
206 /** @addtogroup HAL_XQSPI_CALLBACK_STRUCTURES Callback Structures
207 * @{
208 */
209
210 /** @defgroup HAL_XQSPI_Callback Callback
211 * @{
212 */
213
214 /**
215 * @brief HAL_XQSPI Callback function definition
216 */
217
218 typedef struct _hal_xqspi_callback
219 {
220 void (*xqspi_msp_init)(xqspi_handle_t *p_xqspi); /**< XQSPI init MSP callback */
221 void (*xqspi_msp_deinit)(xqspi_handle_t *p_xqspi); /**< XQSPI de-init MSP callback */
222 } hal_xqspi_callback_t;
223
224 /** @} */
225
226 /** @} */
227
228 /**
229 * @defgroup HAL_XQSPI_MACRO Defines
230 * @{
231 */
232
233 /* Exported constants --------------------------------------------------------*/
234 /** @defgroup XQSPI_Exported_Constants XQSPI Exported Constants
235 * @{
236 */
237
238 /** @defgroup XQSPI_Error_Code XQSPI Error Code
239 * @{
240 */
241 #define HAL_XQSPI_ERROR_NONE ((uint32_t)0x00000000) /**< No error */
242 #define HAL_XQSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /**< Timeout error */
243 #define HAL_XQSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /**< Transfer error */
244 #define HAL_XQSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /**< Invalid parameter error */
245 /** @} */
246
247 /** @defgroup XQSPI_HP_Mode_EN XQSPI in XIP mode
248 * @{
249 */
250 #define XQSPI_HP_MODE_DIS LL_XQSPI_HP_MODE_DIS /**< Disable XQSPI High Performance mode */
251 #define XQSPI_HP_MODE_EN LL_XQSPI_HP_MODE_EN /**< Enable XQSPI High Performance mode */
252 /** @} */
253
254 /** @defgroup XQSPI_Work_Mode XQSPI Work Mode
255 * @{
256 */
257 #define XQSPI_WORK_MODE_QSPI LL_XQSPI_MODE_QSPI /**< Work in QSPI mode */
258 #define XQSPI_WORK_MODE_XIP LL_XQSPI_MODE_XIP /**< Work in XIP mode */
259 /** @} */
260
261 /** @defgroup XQSPI_Cache_Mode XQSPI Cache Mode in XIP mode
262 * @{
263 */
264 #define XQSPI_CACHE_MODE_DIS LL_XQSPI_CACHE_DIS /**< Cache off in XIP mode */
265 #define XQSPI_CACHE_MODE_EN LL_XQSPI_CACHE_EN /**< Cache on in XIP mode */
266 /** @} */
267
268 /** @defgroup XQSPI_Direct_Map_Cache_EN XQSPI in XIP mode
269 * @{
270 */
271 #define XQSPI_CACHE_DIRECT_MAP_DIS LL_XQSPI_CACHE_DIRECT_MAP_DIS /**< Cache work on 4-Way Set Associative */
272 #define XQSPI_CACHE_DIRECT_MAP_EN LL_XQSPI_CACHE_DIRECT_MAP_EN /**< Cache work on Direct Map */
273 /** @} */
274
275 /** @defgroup XQSPI_Cache_Flush_EN XQSPI in XIP mode
276 * @{
277 */
278 #define XQSPI_CACHE_FLUSH_DIS LL_XQSPI_CACHE_FLUSH_DIS /**< Cache Flush Disable */
279 #define XQSPI_CACHE_FLUSH_EN LL_XQSPI_CACHE_FLUSH_EN /**< Cache Flush Enable */
280 /** @} */
281
282 /** @defgroup XQSPI_Read_CMD XQSPI Read Command in XIP mode
283 * @{
284 */
285 #define XQSPI_READ_CMD_READ LL_XQSPI_XIP_CMD_READ /**< Read mode */
286 #define XQSPI_READ_CMD_FAST_READ LL_XQSPI_XIP_CMD_FAST_READ /**< Fast Read mode */
287 #define XQSPI_READ_CMD_DUAL_OUT_READ LL_XQSPI_XIP_CMD_DUAL_OUT_READ /**< Dual-Out Fast Read mode */
288 #define XQSPI_READ_CMD_DUAL_IO_READ LL_XQSPI_XIP_CMD_DUAL_IO_READ /**< Dual-IO Fast Read mode */
289 #define XQSPI_READ_CMD_QUAD_OUT_READ LL_XQSPI_XIP_CMD_QUAD_OUT_READ /**< Quad-Out Fast Read mode */
290 #define XQSPI_READ_CMD_QUAD_IO_READ LL_XQSPI_XIP_CMD_QUAD_IO_READ /**< Quad-IO Fast Read mode */
291 /** @} */
292
293 /** @defgroup XQSPI_Clock_Mode XQSPI Clock Mode
294 * @{
295 */
296 #define XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE) /**< Inactive state of CLK is low,
297 CLK toggles at the start of first data bit */
298 #define XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE) /**< Inactive state of CLK is low,
299 CLK toggles in the middle of first data bit */
300 #define XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE) /**< Inactive state of CLK is high,
301 CLK toggles at the start of first data bit */
302 #define XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE) /**< Inactive state of CLK is high,
303 CLK toggles in the middle of first data bit */
304 /** @} */
305
306 /** @defgroup XQSPI_Baud_Rate XQSPI Clock Speed
307 * @{
308 */
309 #define XQSPI_BAUD_RATE_64M LL_XQSPI_BAUD_RATE_64M /**< Serial clock speed is 64 MHz */
310 #define XQSPI_BAUD_RATE_48M LL_XQSPI_BAUD_RATE_48M /**< Serial clock speed is 48 MHz */
311 #define XQSPI_BAUD_RATE_32M LL_XQSPI_BAUD_RATE_32M /**< Serial clock speed is 32 MHz */
312 #define XQSPI_BAUD_RATE_24M LL_XQSPI_BAUD_RATE_24M /**< Serial clock speed is 24 MHz */
313 #define XQSPI_BAUD_RATE_16M LL_XQSPI_BAUD_RATE_16M /**< Serial clock speed is 16 MHz */
314 /** @} */
315
316 /** @defgroup XQSPI_Data_Mode XQSPI Data Mode, only in QSPI mode
317 * @{
318 */
319 #define XQSPI_DATA_MODE_SPI LL_XQSPI_QSPI_FRF_SPI /**< Standard SPI Frame Format */
320 #define XQSPI_DATA_MODE_DUALSPI LL_XQSPI_QSPI_FRF_DUALSPI /**< Dual-SPI Frame Format */
321 #define XQSPI_DATA_MODE_QUADSPI LL_XQSPI_QSPI_FRF_QUADSPI /**< Quad-SPI Frame Format */
322 /** @} */
323
324 /** @defgroup XQSPI_FIFO_Threshold XQSPI FIFO Threshold, FIFO depth is 64*4bytes, only in QSPI mode
325 * @{
326 */
327 #define XQSPI_FIFO_THRESHOLD_1_8 LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 /**< FIFO depth/8 */
328 #define XQSPI_FIFO_THRESHOLD_1_4 LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 /**< FIFO depth/4 */
329 #define XQSPI_FIFO_THRESHOLD_1_2 LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 /**< FIFO depth/2 */
330 #define XQSPI_FIFO_THRESHOLD_3_4 LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 /**< FIFO depth*3/4 */
331 #define XQSPI_FIFO_DEPTH LL_XQSPI_QSPI_FIFO_DEPTH /**< FIFO full depth */
332 /** @} */
333
334 /** @defgroup XQSPI_Instruction_Size XQSPI Instruction Size, only in QSPI mode
335 * @{
336 */
337 #define XQSPI_INSTSIZE_00_BITS (0) /**< 0-bit (No Instruction) */
338 #define XQSPI_INSTSIZE_08_BITS (1) /**< 8-bit Instruction */
339 #define XQSPI_INSTSIZE_16_BITS (2) /**< 16-bit Instruction */
340 /** @} */
341
342 /** @defgroup XQSPI_Address_Size XQSPI Address Size, only in QSPI mode
343 * @{
344 */
345 #define XQSPI_ADDRSIZE_00_BITS (0) /**< 0-bit (No Address) */
346 #define XQSPI_ADDRSIZE_08_BITS (1) /**< 8-bit Address */
347 #define XQSPI_ADDRSIZE_16_BITS (2) /**< 16-bit Address */
348 #define XQSPI_ADDRSIZE_24_BITS (3) /**< 24-bit Address */
349 #define XQSPI_ADDRSIZE_32_BITS (4) /**< 32-bit Address */
350 /** @} */
351
352 /** @defgroup XQSPI_Inst_Addr_Mode XQSPI Instruction and Address Mode, only in QSPI mode
353 * @{
354 */
355 #define XQSPI_INST_ADDR_ALL_IN_SPI (0) /**< Instruction and address are sent in SPI mode */
356 #define XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1) /**< Instruction is sent in SPI mode, and address is sent in Daul/Quad SPI mode */
357 #define XQSPI_INST_ADDR_ALL_IN_SPIFRF (2) /**< Instruction and address are sent in Daul/Quad SPI mode */
358 /** @} */
359
360 /** @defgroup XQSPI_Flags XQSPI Flags, only in QSPI mode
361 * @{
362 */
363 #define XQSPI_FLAG_RFF LL_XQSPI_QSPI_STAT_RFF /**< Rx FIFO full flag */
364 #define XQSPI_FLAG_RFTF LL_XQSPI_QSPI_STAT_RFTF /**< Rx FIFO threshold flag */
365 #define XQSPI_FLAG_RFE LL_XQSPI_QSPI_STAT_RFE /**< Rx FIFO empty flag */
366 #define XQSPI_FLAG_TFF LL_XQSPI_QSPI_STAT_TFF /**< Tx FIFO full flag */
367 #define XQSPI_FLAG_TFTF LL_XQSPI_QSPI_STAT_TFTF /**< Tx FIFO threshold flag */
368 #define XQSPI_FLAG_TFE LL_XQSPI_QSPI_STAT_TFE /**< Tx FIFO empty flag */
369 #define XQSPI_FLAG_BUSY LL_XQSPI_QSPI_STAT_BUSY /**< Busy flag */
370 /** @} */
371
372 /** @defgroup XQSPI_Ctrl_Present Control Present Status, only in XIP mode
373 * @{
374 */
375 #define XQSPI_DISABLE_PRESENT LL_XQSPI_DISABLE_PRESENT /**< Disable Present */
376 #define XQSPI_ENABLE_PRESENT LL_XQSPI_ENABLE_PRESENT /**< Enable Present */
377 /** @} */
378
379 /**
380 * @brief XQSPI_Retry_definition XQSPI Retry definition
381 */
382 #define HAL_XQSPI_RETRY_DEFAULT_VALUE ((uint32_t)1000) /**< 1000 times */
383
384 /** @} */
385
386 /* Exported macro ------------------------------------------------------------*/
387 /** @defgroup XQSPI_Exported_Macros XQSPI Exported Macros
388 * @{
389 */
390
391 /** @brief Reset XQSPI handle states.
392 * @param __HANDLE__ XQSPI handle.
393 * @retval None
394 */
395 #define __HAL_XQSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_XQSPI_STATE_RESET)
396
397 /** @brief Enable the specified QSPI peripheral in XQSPI.
398 * @param __HANDLE__ specifies the XQSPI Handle.
399 * @retval None
400 */
401 #define __HAL_XQSPI_ENABLE_QSPI(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, XQSPI_QSPI_EN_EN)
402 /** @brief Disable the specified QSPI peripheral in XQSPI.
403 * @param __HANDLE__ specifies the XQSPI Handle.
404 * @retval None
405 */
406
407 #define __HAL_XQSPI_DISABLE_QSPI(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, XQSPI_QSPI_EN_EN)
408
409 /** @brief Enable the specified XIP peripheral in XQSPI.
410 * @param __HANDLE__ specifies the XQSPI Handle.
411 * @retval None
412 */
413
414 #define __HAL_XQSPI_ENABLE_XIP(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->XIP.CTRL3, XQSPI_QSPI_EN_EN);\
415 while(!ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
416
417 /** @brief Disable the specified XIP peripheral in XQSPI.
418 * @param __HANDLE__ specifies the XQSPI Handle.
419 * @retval None
420 */
421
422 #define __HAL_XQSPI_DISABLE_XIP(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->XIP.CTRL3, XQSPI_QSPI_EN_EN);\
423 while(ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
424
425 /** @brief Enable the specified CACHE peripheral in XQSPI.
426 * @param __HANDLE__ specifies the XQSPI Handle.
427 * @retval None
428 */
429 #define __HAL_XQSPI_ENABLE_CACHE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
430
431 /** @brief Disable the specified CACHE peripheral in XQSPI.
432 * @param __HANDLE__ specifies the XQSPI Handle.
433 * @retval None
434 */
435 #define __HAL_XQSPI_DISABLE_CACHE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
436
437 /** @brief Check whether the specified XQSPI flag is set or not.
438 * @param __HANDLE__ specifies the XQSPI Handle.
439 * @param __FLAG__ specifies the flag to check.
440 * This parameter can be one of the following values:
441 * @arg @ref XQSPI_FLAG_RFF Rx FIFO full flag
442 * @arg @ref XQSPI_FLAG_RFTF Rx FIFO threshold flag
443 * @arg @ref XQSPI_FLAG_RFE Rx FIFO empty flag
444 * @arg @ref XQSPI_FLAG_TFF Tx FIFO full flag
445 * @arg @ref XQSPI_FLAG_TFTF Tx FIFO threshold flag
446 * @arg @ref XQSPI_FLAG_TFE Tx FIFO empty flag
447 * @arg @ref XQSPI_FLAG_BUSY Busy flag
448 * @retval The new state of __FLAG__ (TRUE or FALSE).
449 */
450 #define __HAL_XQSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->QSPI.STAT, (__FLAG__)) != 0) ? SET : RESET)
451
452 /** @} */
453
454 /* Private macros ------------------------------------------------------------*/
455 /** @defgroup XQSPI_Private_Macro XQSPI Private Macros
456 * @{
457 */
458
459 /** @brief Check if XQSPI Work Mode is valid.
460 * @param __MODE__ XQSPI Work Mode.
461 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
462 */
463 #define IS_XQSPI_WORK_MODE(__MODE__) (((__MODE__) == XQSPI_WORK_MODE_QSPI) || \
464 ((__MODE__) == XQSPI_WORK_MODE_XIP))
465
466 /** @brief Check if XQSPI Cache Mode is valid.
467 * @param __MODE__ XQSPI Cache Mode.
468 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
469 */
470 #define IS_XQSPI_CACHE_MODE(__MODE__) (((__MODE__) == XQSPI_CACHE_MODE_DIS) || \
471 ((__MODE__) == XQSPI_CACHE_MODE_EN))
472
473 /** @brief Check if XQSPI Cache Direct Map is valid.
474 * @param __MODE__ XQSPI Cache Direct Map Enable Flag.
475 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
476 */
477 #define IS_XQSPI_CACHE_MAPPING(__MODE__) (((__MODE__) == XQSPI_CACHE_DIRECT_MAP_DIS) || \
478 ((__MODE__) == XQSPI_CACHE_DIRECT_MAP_EN))
479
480 /** @brief Check if XQSPI Cache Flush is valid.
481 * @param __MODE__ XQSPI Cache Flush Enable Flag.
482 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
483 */
484 #define IS_XQSPI_CACHE_FLUSH(__MODE__) (((__MODE__) == XQSPI_CACHE_FLUSH_DIS) || \
485 ((__MODE__) == XQSPI_CACHE_FLUSH_EN))
486
487 /** @brief Check if XQSPI Read CMD is valid.
488 * @param __CMD__ XQSPI Cache Mode.
489 * @retval SET (__CMD__ is valid) or RESET (__CMD__ is invalid)
490 */
491 #define IS_XQSPI_READ_CMD(__CMD__) (((__CMD__) == XQSPI_READ_CMD_READ ) || \
492 ((__CMD__) == XQSPI_READ_CMD_FAST_READ ) || \
493 ((__CMD__) == XQSPI_READ_CMD_DUAL_OUT_READ) || \
494 ((__CMD__) == XQSPI_READ_CMD_DUAL_IO_READ ) || \
495 ((__CMD__) == XQSPI_READ_CMD_QUAD_OUT_READ) || \
496 ((__CMD__) == XQSPI_READ_CMD_QUAD_IO_READ ))
497
498 /** @brief Check if XQSPI Clock Baud Rate is valid.
499 * @param __BAUD__ XQSPI Clock Baud Rate.
500 * @retval SET (__BAUD__ is valid) or RESET (__BAUD__ is invalid)
501 */
502 #define IS_XQSPI_BAUD_RATE(__BAUD__) (((__BAUD__) == XQSPI_BAUD_RATE_64M) || \
503 ((__BAUD__) == XQSPI_BAUD_RATE_48M) || \
504 ((__BAUD__) == XQSPI_BAUD_RATE_32M) || \
505 ((__BAUD__) == XQSPI_BAUD_RATE_24M) || \
506 ((__BAUD__) == XQSPI_BAUD_RATE_16M))
507
508 /** @brief Check if XQSPI Clock Mode is valid.
509 * @param __CLKMODE__ XQSPI Clock Mode.
510 * @retval SET (__CLKMODE__ is valid) or RESET (__CLKMODE__ is invalid)
511 */
512 #define IS_XQSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == XQSPI_CLOCK_MODE_0) || \
513 ((__CLKMODE__) == XQSPI_CLOCK_MODE_1) || \
514 ((__CLKMODE__) == XQSPI_CLOCK_MODE_2) || \
515 ((__CLKMODE__) == XQSPI_CLOCK_MODE_3))
516
517 /** @brief Check if XQSPI FIFO Threshold is valid.
518 * @param __THR__ XQSPI FIFO Threshold.
519 * @retval SET (__THR__ is valid) or RESET (__THR__ is invalid)
520 */
521 #define IS_XQSPI_FIFO_THRESHOLD(__THR__) (((__THR__) == XQSPI_FIFO_THRESHOLD_1_8) || \
522 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_4) || \
523 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_2) || \
524 ((__THR__) == XQSPI_FIFO_THRESHOLD_3_4))
525
526 /** @brief Check if XQSPI Instruction Size is valid.
527 * @param __INST_SIZE__ XQSPI Instruction Size.
528 * @retval SET (__INST_SIZE__ is valid) or RESET (__INST_SIZE__ is invalid)
529 */
530 #define IS_XQSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == XQSPI_INSTSIZE_00_BITS) || \
531 ((__INST_SIZE__) == XQSPI_INSTSIZE_08_BITS) || \
532 ((__INST_SIZE__) == XQSPI_INSTSIZE_16_BITS))
533
534 /** @brief Check if XQSPI Address Size is valid.
535 * @param __ADDR_SIZE__ XQSPI Address Size .
536 * @retval SET (__ADDR_SIZE__ is valid) or RESET (__ADDR_SIZE__ is invalid)
537 */
538 #define IS_XQSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == XQSPI_ADDRSIZE_00_BITS) || \
539 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_08_BITS) || \
540 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_16_BITS) || \
541 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_24_BITS) || \
542 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_32_BITS))
543
544 /** @brief Check if XQSPI Instruction and Address Mode is valid.
545 * @param __MODE__ XQSPI Instruction and Address Mode.
546 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
547 */
548 #define IS_XQSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPI) || \
549 ((__MODE__) == XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
550 ((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPIFRF))
551
552 /** @brief Check if XQSPI Data Mode is valid.
553 * @param __MODE__ XQSPI Data Mode.
554 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
555 */
556 #define IS_XQSPI_DATA_MODE(__MODE__) (((__MODE__) == XQSPI_DATA_MODE_SPI) || \
557 ((__MODE__) == XQSPI_DATA_MODE_DUALSPI) || \
558 ((__MODE__) == XQSPI_DATA_MODE_QUADSPI))
559
560 /** @} */
561
562 /** @} */
563
564 /* Exported functions --------------------------------------------------------*/
565 /** @addtogroup HAL_XQSPI_DRIVER_FUNCTIONS Functions
566 * @{
567 */
568
569 /** @defgroup XQSPI_Exported_Functions_Group1 Initialization and de-initialization functions
570 * @brief Initialization and de-initialization functions
571 *
572 @verbatim
573 ===============================================================================
574 ##### Initialization and de-initialization functions #####
575 ===============================================================================
576 [..] This subsection provides a set of functions allowing to initialize and
577 de-initialize the XQSPIx peripheral:
578
579 (+) User must implement hal_xqspi_msp_init() function in which he configures
580 all related peripherals resources (GPIO, DMA, IT and NVIC ).
581
582 (+) Call the function hal_xqspi_init() to configure the selected device with
583 the selected configuration:
584 (++) work_mode
585 (++) cache_mode
586 (++) read_cmd
587 (++) baud_rate
588 (++) clock_mode
589
590 (+) Call the function hal_xqspi_deinit() to restore the default configuration
591 of the selected XQSPIx peripheral.
592
593 @endverbatim
594 * @{
595 */
596
597 /**
598 ****************************************************************************************
599 * @brief Initialize the XQSPI according to the specified parameters
600 * in the xqspi_init_t and initialize the associated handle.
601 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
602 * @retval ::HAL_OK: Operation is OK.
603 * @retval ::HAL_ERROR: Parameter error or operation not supported.
604 * @retval ::HAL_BUSY: Driver is busy.
605 * @retval ::HAL_TIMEOUT: Timeout occurred.
606 ****************************************************************************************
607 */
608 hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi);
609
610 /**
611 ****************************************************************************************
612 * @brief De-initialize the XQSPI peripheral.
613 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
614 * @retval ::HAL_OK: Operation is OK.
615 * @retval ::HAL_ERROR: Parameter error or operation not supported.
616 * @retval ::HAL_BUSY: Driver is busy.
617 * @retval ::HAL_TIMEOUT: Timeout occurred.
618 ****************************************************************************************
619 */
620 hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi);
621
622 /**
623 ****************************************************************************************
624 * @brief Initialize the XQSPI MSP.
625 * @note This function should not be modified. When the callback is needed,
626 the hal_xqspi_msp_deinit can be implemented in the user file.
627 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
628 ****************************************************************************************
629 */
630 void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi);
631
632 /**
633 ****************************************************************************************
634 * @brief De-initialize the XQSPI MSP.
635 * @note This function should not be modified. When the callback is needed,
636 the hal_xqspi_msp_deinit can be implemented in the user file.
637 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
638 ****************************************************************************************
639 */
640 void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi);
641
642 /** @} */
643
644 /** @defgroup XQSPI_Exported_Functions_Group2 IO operation functions
645 * @brief Data transfers functions
646 *
647 @verbatim
648 ==============================================================================
649 ##### IO operation functions #####
650 ===============================================================================
651 [..]
652 This subsection provides a set of functions allowing to manage the XQSPI
653 data transfers.
654
655 [..] The XQSPI supports master and slave mode:
656
657 (#) There are one modes of transfer:
658 (++) Blocking mode: The communication is performed in polling mode.
659 The HAL status of all data processing is returned by the same function
660 after finishing transfer.
661
662 (#) APIs provided for only one transfer mode (Blocking mode)
663 exist for 1Line/2Line/4Line (simplex) modes.
664
665 @endverbatim
666 * @{
667 */
668
669 /**
670 ****************************************************************************************
671 * @brief Transmit an amount of data with specified instruction and address in blocking mode.
672 * @note This function is used only in Indirect Write Mode.
673 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
674 * @param[in] p_cmd: Pointer to a xqspi_command_t structure that contains the instruction and address for data transfer.
675 * @param[in] p_data: Pointer to data buffer
676 * @param[in] retry: Repeat times
677 * @retval ::HAL_OK: Operation is OK.
678 * @retval ::HAL_ERROR: Parameter error or operation not supported.
679 * @retval ::HAL_BUSY: Driver is busy.
680 * @retval ::HAL_TIMEOUT: Timeout occurred.
681 ****************************************************************************************
682 */
683 hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
684
685 /**
686 ****************************************************************************************
687 * @brief Receive an amount of data with specified instruction and address in blocking mode.
688 * @note This function is used only in Indirect Write Mode.
689 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
690 * @param[in] p_cmd: Pointer to a xqspi_command_t structure that contains the instruction and address for data transfer.
691 * @param[out] p_data: Pointer to data buffer
692 * @param[in] retry: Repeat times
693 * @retval ::HAL_OK: Operation is OK.
694 * @retval ::HAL_ERROR: Parameter error or operation not supported.
695 * @retval ::HAL_BUSY: Driver is busy.
696 * @retval ::HAL_TIMEOUT: Timeout occurred.
697 ****************************************************************************************
698 */
699 hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
700
701 #if defined RTL_SIM
702 hal_status_t hal_xqspi_command_receive_rtl(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
703 #endif
704
705
706 /**
707 ****************************************************************************************
708 * @brief Transmit an amount of data in blocking mode.
709 * @note This function is used only in Indirect Write Mode, only in standard SPI mode.
710 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
711 * @param[in] p_data: Pointer to data buffer
712 * @param[in] length: Amount of data to be sent in bytes
713 * @param[in] retry: Repeat times
714 * @retval ::HAL_OK: Operation is OK.
715 * @retval ::HAL_ERROR: Parameter error or operation not supported.
716 * @retval ::HAL_BUSY: Driver is busy.
717 * @retval ::HAL_TIMEOUT: Timeout occurred.
718 ****************************************************************************************
719 */
720 hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry);
721
722 /**
723 ****************************************************************************************
724 * @brief Receive an amount of data in blocking mode.
725 * @note This function is used only in Indirect Read Mode, only in standard SPI mode.
726 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
727 * @param[out] p_data: Pointer to data buffer
728 * @param[in] length: Amount of data to be received in bytes
729 * @param[in] retry: Repeat times
730 * @retval ::HAL_OK: Operation is OK.
731 * @retval ::HAL_ERROR: Parameter error or operation not supported.
732 * @retval ::HAL_BUSY: Driver is busy.
733 * @retval ::HAL_TIMEOUT: Timeout occurred.
734 ****************************************************************************************
735 */
736 hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry);
737
738 /** @} */
739
740 /** @defgroup XQSPI_Exported_Functions_Group3 Peripheral State and Errors functions
741 * @brief XQSPI control functions
742 *
743 @verbatim
744 ===============================================================================
745 ##### Peripheral State and Errors functions #####
746 ===============================================================================
747 [..]
748 This subsection provides a set of functions allowing to control the XQSPI.
749 (+) hal_xqspi_get_state()API can be helpful to check in run-time the state of the XQSPI peripheral.
750 (+) hal_xqspi_get_error() check in run-time Errors occurring during communication.
751 (+) hal_xqspi_set_retry() set the repeat times during internal process.
752 (+) hal_xqspi_set_tx_fifo_threshold() set the TX FIFO Threshold.
753 (+) hal_xqspi_set_rx_fifo_threshold() set the RX FIFO Threshold.
754 (+) hal_xqspi_get_tx_fifo_threshold() get the TX FIFO Threshold.
755 (+) hal_xqspi_get_rx_fifo_threshold() get the RX FIFO Threshold.
756 @endverbatim
757 * @{
758 */
759
760 /**
761 ****************************************************************************************
762 * @brief Return the XQSPI handle state.
763 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
764 * @retval ::HAL_XQSPI_STATE_RESET: Peripheral not initialized.
765 * @retval ::HAL_XQSPI_STATE_READY: Peripheral initialized and ready for use.
766 * @retval ::HAL_XQSPI_STATE_BUSY: Peripheral in indirect mode and busy.
767 * @retval ::HAL_XQSPI_STATE_BUSY_INDIRECT_TX: Peripheral in indirect mode with transmission ongoing.
768 * @retval ::HAL_XQSPI_STATE_BUSY_INDIRECT_RX: Peripheral in indirect mode with reception ongoing.
769 * @retval ::HAL_XQSPI_STATE_ABORT: Peripheral with abort request ongoing.
770 * @retval ::HAL_XQSPI_STATE_ERROR: Peripheral in error.
771 ****************************************************************************************
772 */
773 hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi);
774
775 /**
776 ****************************************************************************************
777 * @brief Return the XQSPI error code.
778 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
779 * @return XQSPI error code in bitmap format
780 ****************************************************************************************
781 */
782 uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi);
783
784 /**
785 ****************************************************************************************
786 * @brief Set the XQSPI internal process repeat times value.
787 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
788 * @param[in] retry: Internal process repeat times value.
789 ****************************************************************************************
790 */
791 void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry);
792
793 /**
794 ****************************************************************************************
795 * @brief Set the TXFIFO threshold.
796 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
797 * @param[in] threshold: TX FIFO threshold can be one of the following values:
798 * @arg @ref XQSPI_FIFO_THRESHOLD_1_8 threshold is 8 bytes
799 * @arg @ref XQSPI_FIFO_THRESHOLD_1_4 threshold is 16 bytes
800 * @arg @ref XQSPI_FIFO_THRESHOLD_1_2 threshold is 32 bytes
801 * @arg @ref XQSPI_FIFO_THRESHOLD_3_4 threshold is 48 bytes
802 * @retval ::HAL_OK: Operation is OK.
803 * @retval ::HAL_ERROR: Parameter error or operation not supported.
804 * @retval ::HAL_BUSY: Driver is busy.
805 * @retval ::HAL_TIMEOUT: Timeout occurred.
806 ****************************************************************************************
807 */
808 hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold);
809
810 /**
811 ****************************************************************************************
812 * @brief Set the RXFIFO threshold.
813 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
814 * @param[in] threshold: RX FIFO threshold can be one of the following values:
815 * @arg @ref XQSPI_FIFO_THRESHOLD_1_8 threshold is 8 bytes
816 * @arg @ref XQSPI_FIFO_THRESHOLD_1_4 threshold is 16 bytes
817 * @arg @ref XQSPI_FIFO_THRESHOLD_1_2 threshold is 32 bytes
818 * @arg @ref XQSPI_FIFO_THRESHOLD_3_4 threshold is 48 bytes
819 * @retval ::HAL_OK: Operation is OK.
820 * @retval ::HAL_ERROR: Parameter error or operation not supported.
821 * @retval ::HAL_BUSY: Driver is busy.
822 * @retval ::HAL_TIMEOUT: Timeout occurred.
823 ****************************************************************************************
824 */
825 hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold);
826
827 /**
828 ****************************************************************************************
829 * @brief Get the TXFIFO threshold.
830 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
831 * @return TX FIFO threshold
832 ****************************************************************************************
833 */
834 uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi);
835
836 /**
837 ****************************************************************************************
838 * @brief Get the RXFIFO threshold.
839 * @param[in] p_xqspi: Pointer to an XQSPI handle which contains the configuration information for the specified XQSPI module.
840 * @return RX FIFO threshold
841 ****************************************************************************************
842 */
843 uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi);
844
845 /** @} */
846
847 /** @} */
848
849 #ifdef __cplusplus
850 }
851 #endif
852
853 #endif /* __GR533x_HAL_XQSPI_H__ */
854
855 /** @} */
856
857 /** @} */
858
859 /** @} */
_xqspi_handle_t::tx_xfer_count
__IO uint32_t tx_xfer_count
Definition: gr533x_hal_xqspi.h:148
_hal_xqspi_callback::xqspi_msp_init
void(* xqspi_msp_init)(xqspi_handle_t *p_xqspi)
Definition: gr533x_hal_xqspi.h:220
hal_xqspi_msp_init
void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI MSP.
_xqspi_init_t::cache_mode
uint32_t cache_mode
Definition: gr533x_hal_xqspi.h:107
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr533x_hal_def.h:81
gr533x_ll_xqspi.h
Header file containing functions prototypes of XQSPI LL library.
hal_xqspi_deinit
hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI peripheral.
_xqspi_command_t::inst_size
uint32_t inst_size
Definition: gr533x_hal_xqspi.h:182
HAL_XQSPI_STATE_BUSY_INDIRECT_TX
@ HAL_XQSPI_STATE_BUSY_INDIRECT_TX
Definition: gr533x_hal_xqspi.h:80
_xqspi_command_t::inst_addr_mode
uint32_t inst_addr_mode
Definition: gr533x_hal_xqspi.h:191
_xqspi_command_t::addr_size
uint32_t addr_size
Definition: gr533x_hal_xqspi.h:185
hal_xqspi_get_rx_fifo_threshold
uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the RXFIFO threshold.
_xqspi_init_t::cache_flush
uint32_t cache_flush
Definition: gr533x_hal_xqspi.h:122
HAL_XQSPI_STATE_RESET
@ HAL_XQSPI_STATE_RESET
Definition: gr533x_hal_xqspi.h:77
hal_xqspi_receive
hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Receive an amount of data in blocking mode.
hal_xqspi_get_state
hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi)
Return the XQSPI handle state.
hal_xqspi_get_error
uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi)
Return the XQSPI error code.
_xqspi_command_t
XQSPI command Structure definition.
Definition: gr533x_hal_xqspi.h:175
hal_xqspi_state_t
hal_xqspi_state_t
HAL XQSPI State Enumerations definition.
Definition: gr533x_hal_xqspi.h:76
_xqspi_init_t::work_mode
uint32_t work_mode
Definition: gr533x_hal_xqspi.h:104
_xqspi_command_t::addr
uint32_t addr
Definition: gr533x_hal_xqspi.h:179
_xqspi_handle_t::retry
uint32_t retry
Definition: gr533x_hal_xqspi.h:162
HAL_XQSPI_STATE_READY
@ HAL_XQSPI_STATE_READY
Definition: gr533x_hal_xqspi.h:78
_xqspi_init_t::clock_mode
uint32_t clock_mode
Definition: gr533x_hal_xqspi.h:116
_xqspi_handle_t::p_rx_buffer
uint8_t * p_rx_buffer
Definition: gr533x_hal_xqspi.h:150
HAL_XQSPI_STATE_BUSY
@ HAL_XQSPI_STATE_BUSY
Definition: gr533x_hal_xqspi.h:79
_xqspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr533x_hal_xqspi.h:113
_ll_xqspi_hp_init_t
XQSPI High Performance mode init structures definition.
Definition: gr533x_ll_xqspi.h:77
_xqspi_handle_t::init
xqspi_init_t init
Definition: gr533x_hal_xqspi.h:142
_xqspi_handle_t::rx_xfer_count
__IO uint32_t rx_xfer_count
Definition: gr533x_hal_xqspi.h:154
_hal_xqspi_callback
HAL_XQSPI Callback function definition.
Definition: gr533x_hal_xqspi.h:219
_xqspi_init_t::read_cmd
uint32_t read_cmd
Definition: gr533x_hal_xqspi.h:110
xqspi_handle_t
struct _xqspi_handle_t xqspi_handle_t
XQSPI handle Structure definition.
hal_xqspi_set_retry
void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry)
Set the XQSPI internal process repeat times value.
xqspi_command_t
struct _xqspi_command_t xqspi_command_t
XQSPI command Structure definition.
_xqspi_handle_t
XQSPI handle Structure definition.
Definition: gr533x_hal_xqspi.h:139
hal_xqspi_set_rx_fifo_threshold
hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the RXFIFO threshold.
_xqspi_init_t::cache_direct_map_en
uint32_t cache_direct_map_en
Definition: gr533x_hal_xqspi.h:119
_xqspi_handle_t::p_instance
xqspi_regs_t * p_instance
Definition: gr533x_hal_xqspi.h:140
hal_xqspi_transmit
hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Transmit an amount of data in blocking mode.
HAL_XQSPI_STATE_ABORT
@ HAL_XQSPI_STATE_ABORT
Definition: gr533x_hal_xqspi.h:82
_xqspi_command_t::length
uint32_t length
Definition: gr533x_hal_xqspi.h:197
hal_xqspi_msp_deinit
void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI MSP.
hal_xqspi_command_transmit
hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Transmit an amount of data with specified instruction and address in blocking mode.
_xqspi_init_t
XQSPI init Structure definition.
Definition: gr533x_hal_xqspi.h:103
_xqspi_handle_t::p_tx_buffer
uint8_t * p_tx_buffer
Definition: gr533x_hal_xqspi.h:144
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr533x_hal_def.h:70
_xqspi_handle_t::rx_xfer_size
__IO uint32_t rx_xfer_size
Definition: gr533x_hal_xqspi.h:152
_xqspi_command_t::data_mode
uint32_t data_mode
Definition: gr533x_hal_xqspi.h:194
HAL_XQSPI_STATE_BUSY_INDIRECT_RX
@ HAL_XQSPI_STATE_BUSY_INDIRECT_RX
Definition: gr533x_hal_xqspi.h:81
hal_xqspi_init
hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI according to the specified parameters in the xqspi_init_t and initialize the ass...
hal_xqspi_get_tx_fifo_threshold
uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the TXFIFO threshold.
_xqspi_init_t::hp_init
ll_xqspi_hp_init_t hp_init
Definition: gr533x_hal_xqspi.h:125
_xqspi_handle_t::lock
__IO hal_lock_t lock
Definition: gr533x_hal_xqspi.h:156
HAL_XQSPI_STATE_ERROR
@ HAL_XQSPI_STATE_ERROR
Definition: gr533x_hal_xqspi.h:83
hal_xqspi_callback_t
struct _hal_xqspi_callback hal_xqspi_callback_t
HAL_XQSPI Callback function definition.
_xqspi_handle_t::state
__IO hal_xqspi_state_t state
Definition: gr533x_hal_xqspi.h:158
gr533x_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
_xqspi_handle_t::error_code
__IO uint32_t error_code
Definition: gr533x_hal_xqspi.h:160
hal_xqspi_command_receive
hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Receive an amount of data with specified instruction and address in blocking mode.
_xqspi_command_t::inst
uint32_t inst
Definition: gr533x_hal_xqspi.h:176
xqspi_init_t
struct _xqspi_init_t xqspi_init_t
XQSPI init Structure definition.
_xqspi_handle_t::tx_xfer_size
__IO uint32_t tx_xfer_size
Definition: gr533x_hal_xqspi.h:146
_xqspi_command_t::dummy_cycles
uint32_t dummy_cycles
Definition: gr533x_hal_xqspi.h:188
hal_xqspi_set_tx_fifo_threshold
hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the TXFIFO threshold.
_hal_xqspi_callback::xqspi_msp_deinit
void(* xqspi_msp_deinit)(xqspi_handle_t *p_xqspi)
Definition: gr533x_hal_xqspi.h:221