gr533x_ll_spi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_LL_SPI_H__
53 #define __GR533x_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined (SPIM) || defined (SPIS)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
87
88 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
89 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
90
91 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
92
93 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
94 This parameter can be a value of @ref SPI_LL_EC_PHASE.
95
96 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
97
98 uint32_t slave_select; /**< Specifies the SPI slave select.
99 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
100
101 This feature can be modified afterwards using unitary function @ref ll_spi_enable_ss().*/
102
103 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
104 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
105 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
108
109 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
110 This parameter can be a number between 0 and 0x7 */
111 } ll_spim_init_t;
112
113 /**
114 * @brief SPIS init structures definition
115 */
116 typedef struct _ll_spis_init_t
117 {
118 uint32_t data_size; /**< Specifies the SPI data width.
119 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
120
121 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
122
123 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
124 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
125
126 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
127
128 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
129 This parameter can be a value of @ref SPI_LL_EC_PHASE.
130
131 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
132
133 } ll_spis_init_t;
134
135 /** @} */
136
137 /** @} */
138
139 /**
140 * @defgroup SPI_LL_MACRO Defines
141 * @{
142 */
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
146 * @{
147 */
148
149
150 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
151 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
152 * @{
153 */
154 #define LL_SPI_SR_DCOL SPI_STAT_DATA_COLN_ERR /**< Data collision error flag */
155 #define LL_SPI_SR_TXE SPI_STAT_TX_ERR /**< Transmission error flag */
156 #define LL_SPI_SR_RFF SPI_STAT_RX_FIFO_FULL /**< Rx FIFO full flag */
157 #define LL_SPI_SR_RFNE SPI_STAT_RX_FIFO_NE /**< Rx FIFO not empty flag */
158 #define LL_SPI_SR_TFE SPI_STAT_TX_FIFO_EMPTY /**< Tx FIFO empty flag */
159 #define LL_SPI_SR_TFNF SPI_STAT_TX_FIFO_NF /**< Tx FIFO not full flag */
160 #define LL_SPI_SR_BUSY SPI_STAT_SSI_BUSY /**< Busy flag */
161 /** @} */
162
163 /** @defgroup SPI_LL_EC_IT IT Defines
164 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
165 * @{
166 */
167 #define LL_SPI_IM_MST SPI_INT_MASK_MULTI_M_CIM /**< Multi-Master Contention Interrupt enable */
168 #define LL_SPI_IM_RXF SPI_INT_MASK_RX_FIFO_FIM /**< Receive FIFO Full Interrupt enable */
169 #define LL_SPI_IM_RXO SPI_INT_MASK_RX_FIFO_OIM /**< Receive FIFO Overflow Interrupt enable */
170 #define LL_SPI_IM_RXU SPI_INT_MASK_RX_FIFO_UIM /**< Receive FIFO Underflow Interrupt enable */
171 #define LL_SPI_IM_TXO SPI_INT_MASK_TX_FIFO_OIM /**< Transmit FIFO Overflow Interrupt enable */
172 #define LL_SPI_IM_TXE SPI_INT_MASK_TX_FIFO_EIM /**< Transmit FIFO Empty Interrupt enable */
173
174 #define LL_SPI_IS_MST SPI_INT_STAT_MULTI_M_CIS /**< Multi-Master Contention Interrupt flag */
175 #define LL_SPI_IS_RXF SPI_INT_STAT_RX_FIFO_FIS /**< Receive FIFO Full Interrupt flag */
176 #define LL_SPI_IS_RXO SPI_INT_STAT_RX_FIFO_OIS /**< Receive FIFO Overflow Interrupt flag */
177 #define LL_SPI_IS_RXU SPI_INT_STAT_RX_FIFO_UIS /**< Receive FIFO Underflow Interrupt flag */
178 #define LL_SPI_IS_TXO SPI_INT_STAT_TX_FIFO_OIS /**< Transmit FIFO Overflow Interrupt flag */
179 #define LL_SPI_IS_TXE SPI_INT_STAT_TX_FIFO_EIS /**< Transmit FIFO Empty Interrupt flag */
180
181 #define LL_SPI_RIS_MST SPI_RAW_INT_STAT_MULTI_M_CRIS /**< Multi-Master Contention RAW Interrupt flag */
182 #define LL_SPI_RIS_RXF SPI_RAW_INT_STAT_RX_FIFO_FRIS /**< Receive FIFO Full RAW Interrupt flag */
183 #define LL_SPI_RIS_RXO SPI_RAW_INT_STAT_RX_FIFO_ORIS /**< Receive FIFO Overflow RAW Interrupt flag */
184 #define LL_SPI_RIS_RXU SPI_RAW_INT_STAT_RX_FIFO_URIS /**< Receive FIFO Underflow RAW Interrupt flag */
185 #define LL_SPI_RIS_TXO SPI_RAW_INT_STAT_TX_FIFO_ORIS /**< Transmit FIFO Overflow RAW Interrupt flag */
186 #define LL_SPI_RIS_TXE SPI_RAW_INT_STAT_TX_FIFO_ERIS /**< Transmit FIFO Empty RAW Interrupt flag */
187 /** @} */
188
189 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
190 * @{
191 */
192 #define LL_SPI_DATASIZE_4BIT (3UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 4 bits */
193 #define LL_SPI_DATASIZE_5BIT (4UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 5 bits */
194 #define LL_SPI_DATASIZE_6BIT (5UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 6 bits */
195 #define LL_SPI_DATASIZE_7BIT (6UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 7 bits */
196 #define LL_SPI_DATASIZE_8BIT (7UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 8 bits */
197 #define LL_SPI_DATASIZE_9BIT (8UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 9 bits */
198 #define LL_SPI_DATASIZE_10BIT (9UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 10 bits */
199 #define LL_SPI_DATASIZE_11BIT (10UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 11 bits */
200 #define LL_SPI_DATASIZE_12BIT (11UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 12 bits */
201 #define LL_SPI_DATASIZE_13BIT (12UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 13 bits */
202 #define LL_SPI_DATASIZE_14BIT (13UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 14 bits */
203 #define LL_SPI_DATASIZE_15BIT (14UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 15 bits */
204 #define LL_SPI_DATASIZE_16BIT (15UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 16 bits */
205 #define LL_SPI_DATASIZE_17BIT (16UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 17 bits */
206 #define LL_SPI_DATASIZE_18BIT (17UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 18 bits */
207 #define LL_SPI_DATASIZE_19BIT (18UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 19 bits */
208 #define LL_SPI_DATASIZE_20BIT (19UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 20 bits */
209 #define LL_SPI_DATASIZE_21BIT (20UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 21 bits */
210 #define LL_SPI_DATASIZE_22BIT (21UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 22 bits */
211 #define LL_SPI_DATASIZE_23BIT (22UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 23 bits */
212 #define LL_SPI_DATASIZE_24BIT (23UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 24 bits */
213 #define LL_SPI_DATASIZE_25BIT (24UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 25 bits */
214 #define LL_SPI_DATASIZE_26BIT (25UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 26 bits */
215 #define LL_SPI_DATASIZE_27BIT (26UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 27 bits */
216 #define LL_SPI_DATASIZE_28BIT (27UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 28 bits */
217 #define LL_SPI_DATASIZE_29BIT (28UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 29 bits */
218 #define LL_SPI_DATASIZE_30BIT (29UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 30 bits */
219 #define LL_SPI_DATASIZE_31BIT (30UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 31 bits */
220 #define LL_SPI_DATASIZE_32BIT (31UL << SPI_CTRL0_DATA_FRAME_SIZE_POS) /**< Data length for SPI transfer: 32 bits */
221 /** @} */
222
223 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
224 * @{
225 */
226 #define LL_SPI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
227 #define LL_SPI_MW_CMDSIZE_2BIT (1UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 2 bits */
228 #define LL_SPI_MW_CMDSIZE_3BIT (2UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 3 bits */
229 #define LL_SPI_MW_CMDSIZE_4BIT (3UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 4 bits */
230 #define LL_SPI_MW_CMDSIZE_5BIT (4UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 5 bits */
231 #define LL_SPI_MW_CMDSIZE_6BIT (5UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 6 bits */
232 #define LL_SPI_MW_CMDSIZE_7BIT (6UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 7 bits */
233 #define LL_SPI_MW_CMDSIZE_8BIT (7UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 8 bits */
234 #define LL_SPI_MW_CMDSIZE_9BIT (8UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 9 bits */
235 #define LL_SPI_MW_CMDSIZE_10BIT (9UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 10 bits */
236 #define LL_SPI_MW_CMDSIZE_11BIT (10UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 11 bits */
237 #define LL_SPI_MW_CMDSIZE_12BIT (11UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 12 bits */
238 #define LL_SPI_MW_CMDSIZE_13BIT (12UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 13 bits */
239 #define LL_SPI_MW_CMDSIZE_14BIT (13UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 14 bits */
240 #define LL_SPI_MW_CMDSIZE_15BIT (14UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 15 bits */
241 #define LL_SPI_MW_CMDSIZE_16BIT (15UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS) /**< CMD length for Microwire transfer: 16 bits */
242 /** @} */
243
244 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
245 * @{
246 */
247 #define LL_SPI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
248 #define LL_SPI_TEST_MODE (1UL << SPI_CTRL0_SHIFT_REG_LOOP_POS) /**< Test mode for SPI transfer: Rx and Tx connected inside */
249 /** @} */
250
251 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
252 * @{
253 */
254 #define LL_SPI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
255 #define LL_SPI_SLAVE_OUTEN (1UL << SPI_CTRL0_S_OUT_EN_POS) /**< Output disable for SPI transfer as slave */
256 /** @} */
257
258 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
259 * @{
260 */
261 #define LL_SPI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
262 #define LL_SPI_SIMPLEX_TX (1UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Tx mode. Tx transfer only on 1 line */
263 #define LL_SPI_SIMPLEX_RX (2UL << SPI_CTRL0_XFE_MODE_POS) /**< Simplex Rx mode. Rx transfer only on 1 line */
264 #define LL_SPI_READ_EEPROM (3UL << SPI_CTRL0_XFE_MODE_POS) /**< Read EEPROM mode. Rx transfer only on 1 line */
265 /** @} */
266
267 /** @defgroup SPI_LL_EC_PHASE Clock Phase
268 * @{
269 */
270 #define LL_SPI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
271 #define LL_SPI_SCPHA_2EDGE (1UL << SPI_CTRL0_SERIAL_CLK_PHASE_POS) /**< Second clock transition is the first data capture edge */
272 /** @} */
273
274 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
275 * @{
276 */
277 #define LL_SPI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
278 #define LL_SPI_SCPOL_HIGH (1UL << SPI_CTRL0_SERIAL_CLK_POL_POS) /**< Clock to 1 when idle */
279 /** @} */
280
281 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
282 * @{
283 */
284 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
285 #define LL_SPI_PROTOCOL_TI (1UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< TI mode */
286 #define LL_SPI_PROTOCOL_MICROWIRE (2UL << SPI_CTRL0_FRAME_FORMAT_POS) /**< Microwire mode */
287 /** @} */
288
289 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
290 * @{
291 */
292 #define LL_SPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
293 #define LL_SPI_MICROWIRE_HANDSHAKE_EN (1UL << SPI_MW_CTRL_MW_HSG_POS) /**< Disable Handshake for Microwire transfer */
294
295 #define LL_SPI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
296 #define LL_SPI_MICROWIRE_TX (1UL << SPI_MW_CTRL_MW_DIR_DW_POS) /**< Tx mode. Tx transfer at Microwire mode */
297
298 #define LL_SPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
299 #define LL_SPI_MICROWIRE_SEQUENTIAL (1UL << SPI_MW_CTRL_MW_XFE_MODE_POS) /**< Sequential for Microwire transfer */
300 /** @} */
301
302 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
303 * @{
304 */
305 #define LL_SPI_SLAVE1 SPI_SLA_S1_SEL_EN /**< Enable slave1 select pin for SPI transfer */
306 #define LL_SPI_SLAVE0 SPI_SLA_S0_SEL_EN /**< Enable slave0 select pin for SPI transfer */
307 /** @} */
308
309 /** @defgroup SPI_LL_EC_DMA DMA Defines
310 * @{
311 */
312 #define LL_SPI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
313 #define LL_SPI_DMA_TX_EN SPI_DMA_CTRL_TX_DMA_EN /**< Enable the transmit FIFO DMA channel */
314
315 #define LL_SPI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
316 #define LL_SPI_DMA_RX_EN SPI_DMA_CTRL_RX_DMA_EN /**< Enable the receive FIFO DMA channel */
317 /** @} */
318
319 /** @defgroup LL_SPI_x_FIFO_DEPTH Defines
320 * @{
321 */
322 #define LL_SPI_M_FIFO_DEPTH (8u) /**< FIFO Depth for SPI Master */
323 #define LL_SPI_S_FIFO_DEPTH (8u) /**< FIFO Depth for SPI Slave */
324 /** @} */
325
326 /** @defgroup LL_SPI_x_DEFAULT_CONFIG Defines
327 * @{
328 */
329
330 /**
331 * @brief LL SPIM InitStrcut default configuartion
332 */
333 #define LL_SPIM_DEFAULT_CONFIG \
334 { \
335 .transfer_direction = LL_SPI_FULL_DUPLEX, \
336 .data_size = LL_SPI_DATASIZE_8BIT, \
337 .clock_polarity = LL_SPI_SCPOL_LOW, \
338 .clock_phase = LL_SPI_SCPHA_1EDGE, \
339 .slave_select = LL_SPI_SLAVE0, \
340 .baud_rate = SystemCoreClock / 2000000, \
341 .rx_sample_delay = 0, \
342 }
343
344 /**
345 * @brief LL SPIS InitStrcut default configuartion
346 */
347 #define LL_SPIS_DEFAULT_CONFIG \
348 { \
349 .data_size = LL_SPI_DATASIZE_8BIT, \
350 .clock_polarity = LL_SPI_SCPOL_LOW, \
351 .clock_phase = LL_SPI_SCPHA_1EDGE, \
352 }
353 /** @} */
354
355 /** @} */
356
357 /* Exported macro ------------------------------------------------------------*/
358 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
359 * @{
360 */
361
362 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
363 * @{
364 */
365
366 /**
367 * @brief Write a value in SPI register
368 * @param __instance__ SPI instance
369 * @param __REG__ Register to be written
370 * @param __VALUE__ Value to be written in the register
371 * @retval None
372 */
373 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
374
375 /**
376 * @brief Read a value in SPI register
377 * @param __instance__ SPI instance
378 * @param __REG__ Register to be read
379 * @retval Register value
380 */
381 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
382
383 /** @} */
384
385 /** @} */
386
387 /** @} */
388
389 /* Exported functions --------------------------------------------------------*/
390 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
391 * @{
392 */
393
394 /** @defgroup SPI_LL_EF_Configuration Configuration functions
395 * @{
396 */
397
398 /**
399 * @brief Enable slave select toggle
400 * @note This bit should not be changed when communication is ongoing.
401 *
402 * Register|BitsName
403 * --------|--------
404 * CTRL0 | SSTEN
405 *
406 * @param SPIx SPI instance
407 * @retval None
408 */
409 __STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
410 {
411 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
412 }
413
414 /**
415 * @brief Disable slave select toggle
416 * @note This bit should not be changed when communication is ongoing.
417 *
418 * Register|BitsName
419 * --------|--------
420 * CTRL0 | SSTEN
421 *
422 * @param SPIx SPI instance
423 * @retval None
424 */
425 __STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
426 {
427 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
428 }
429
430 /**
431 * @brief Check if slave select toggle is enabled
432 * @note This bit should not be changed when communication is ongoing.
433 *
434 * Register|BitsName
435 * --------|--------
436 * CTRL0 | SSTEN
437 *
438 * @param SPIx SPI instance
439 * @retval State of bit (1 or 0).
440 */
441 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
442 {
443 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN) == (SPI_CTRL0_S_ST_EN));
444 }
445
446 /**
447 * @brief Set frame data size
448 *
449 * Register|BitsName
450 * --------|--------
451 * CTRL0 | DFS32
452 *
453 * @param SPIx SPI instance
454 * @param size This parameter can be one of the following values:
455 * @arg @ref LL_SPI_DATASIZE_4BIT
456 * @arg @ref LL_SPI_DATASIZE_5BIT
457 * @arg @ref LL_SPI_DATASIZE_6BIT
458 * @arg @ref LL_SPI_DATASIZE_7BIT
459 * @arg @ref LL_SPI_DATASIZE_8BIT
460 * @arg @ref LL_SPI_DATASIZE_9BIT
461 * @arg @ref LL_SPI_DATASIZE_10BIT
462 * @arg @ref LL_SPI_DATASIZE_11BIT
463 * @arg @ref LL_SPI_DATASIZE_12BIT
464 * @arg @ref LL_SPI_DATASIZE_13BIT
465 * @arg @ref LL_SPI_DATASIZE_14BIT
466 * @arg @ref LL_SPI_DATASIZE_15BIT
467 * @arg @ref LL_SPI_DATASIZE_16BIT
468 * @arg @ref LL_SPI_DATASIZE_17BIT
469 * @arg @ref LL_SPI_DATASIZE_18BIT
470 * @arg @ref LL_SPI_DATASIZE_19BIT
471 * @arg @ref LL_SPI_DATASIZE_20BIT
472 * @arg @ref LL_SPI_DATASIZE_21BIT
473 * @arg @ref LL_SPI_DATASIZE_22BIT
474 * @arg @ref LL_SPI_DATASIZE_23BIT
475 * @arg @ref LL_SPI_DATASIZE_24BIT
476 * @arg @ref LL_SPI_DATASIZE_25BIT
477 * @arg @ref LL_SPI_DATASIZE_26BIT
478 * @arg @ref LL_SPI_DATASIZE_27BIT
479 * @arg @ref LL_SPI_DATASIZE_28BIT
480 * @arg @ref LL_SPI_DATASIZE_29BIT
481 * @arg @ref LL_SPI_DATASIZE_30BIT
482 * @arg @ref LL_SPI_DATASIZE_31BIT
483 * @arg @ref LL_SPI_DATASIZE_32BIT
484 * @retval None
485 */
486 __STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
487 {
488 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE, size);
489 }
490
491 /**
492 * @brief Get frame data size
493 *
494 * Register|BitsName
495 * --------|--------
496 * CTRL0 | DFS32
497 *
498 * @param SPIx SPI instance
499 * @retval Returned value can be one of the following values:
500 * @arg @ref LL_SPI_DATASIZE_4BIT
501 * @arg @ref LL_SPI_DATASIZE_5BIT
502 * @arg @ref LL_SPI_DATASIZE_6BIT
503 * @arg @ref LL_SPI_DATASIZE_7BIT
504 * @arg @ref LL_SPI_DATASIZE_8BIT
505 * @arg @ref LL_SPI_DATASIZE_9BIT
506 * @arg @ref LL_SPI_DATASIZE_10BIT
507 * @arg @ref LL_SPI_DATASIZE_11BIT
508 * @arg @ref LL_SPI_DATASIZE_12BIT
509 * @arg @ref LL_SPI_DATASIZE_13BIT
510 * @arg @ref LL_SPI_DATASIZE_14BIT
511 * @arg @ref LL_SPI_DATASIZE_15BIT
512 * @arg @ref LL_SPI_DATASIZE_16BIT
513 * @arg @ref LL_SPI_DATASIZE_17BIT
514 * @arg @ref LL_SPI_DATASIZE_18BIT
515 * @arg @ref LL_SPI_DATASIZE_19BIT
516 * @arg @ref LL_SPI_DATASIZE_20BIT
517 * @arg @ref LL_SPI_DATASIZE_21BIT
518 * @arg @ref LL_SPI_DATASIZE_22BIT
519 * @arg @ref LL_SPI_DATASIZE_23BIT
520 * @arg @ref LL_SPI_DATASIZE_24BIT
521 * @arg @ref LL_SPI_DATASIZE_25BIT
522 * @arg @ref LL_SPI_DATASIZE_26BIT
523 * @arg @ref LL_SPI_DATASIZE_27BIT
524 * @arg @ref LL_SPI_DATASIZE_28BIT
525 * @arg @ref LL_SPI_DATASIZE_29BIT
526 * @arg @ref LL_SPI_DATASIZE_30BIT
527 * @arg @ref LL_SPI_DATASIZE_31BIT
528 * @arg @ref LL_SPI_DATASIZE_32BIT
529 */
530 __STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
531 {
532 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE));
533 }
534
535 /**
536 * @brief Set the length of the control word for the Microwire frame format
537 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
538 *
539 * Register|BitsName
540 * --------|--------
541 * CTRL0 | CFS
542 *
543 * @param SPIx SPI instance
544 * @param size This parameter can be one of the following values:
545 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
546 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
547 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
548 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
549 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
550 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
551 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
552 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
553 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
554 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
555 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
556 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
557 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
558 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
559 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
560 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
561 * @retval None
562 */
563 __STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
564 {
565 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE, size);
566 }
567
568 /**
569 * @brief Get the length of the control word for the Microwire frame format
570 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
571 *
572 * Register|BitsName
573 * --------|--------
574 * CTRL0 | CFS
575 *
576 * @param SPIx SPI instance
577 * @retval Returned value can be one of the following values:
578 * @arg @ref LL_SPI_MW_CMDSIZE_1BIT
579 * @arg @ref LL_SPI_MW_CMDSIZE_2BIT
580 * @arg @ref LL_SPI_MW_CMDSIZE_3BIT
581 * @arg @ref LL_SPI_MW_CMDSIZE_4BIT
582 * @arg @ref LL_SPI_MW_CMDSIZE_5BIT
583 * @arg @ref LL_SPI_MW_CMDSIZE_6BIT
584 * @arg @ref LL_SPI_MW_CMDSIZE_7BIT
585 * @arg @ref LL_SPI_MW_CMDSIZE_8BIT
586 * @arg @ref LL_SPI_MW_CMDSIZE_9BIT
587 * @arg @ref LL_SPI_MW_CMDSIZE_10BIT
588 * @arg @ref LL_SPI_MW_CMDSIZE_11BIT
589 * @arg @ref LL_SPI_MW_CMDSIZE_12BIT
590 * @arg @ref LL_SPI_MW_CMDSIZE_13BIT
591 * @arg @ref LL_SPI_MW_CMDSIZE_14BIT
592 * @arg @ref LL_SPI_MW_CMDSIZE_15BIT
593 * @arg @ref LL_SPI_MW_CMDSIZE_16BIT
594 */
595 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
596 {
597 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE));
598 }
599
600 /**
601 * @brief Enable SPI test mode
602 *
603 * Register|BitsName
604 * --------|--------
605 * CTRL0 | SRL
606 *
607 * @param SPIx SPI instance
608 * @retval None
609 */
610 __STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
611 {
612 SET_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
613 }
614
615 /**
616 * @brief Disable SPI test mode
617 *
618 * Register|BitsName
619 * --------|--------
620 * CTRL0 | SRL
621 *
622 * @param SPIx SPI instance
623 * @retval None
624 */
625 __STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
626 {
627 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
628 }
629
630 /**
631 * @brief Check if SPI test mode is enabled
632 *
633 * Register|BitsName
634 * --------|--------
635 * CTRL0 | SRL
636 *
637 * @param SPIx SPI instance
638 * @retval State of bit (1 or 0).
639 */
640 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
641 {
642 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP) == (SPI_CTRL0_SHIFT_REG_LOOP));
643 }
644
645 /**
646 * @brief Enable slave output
647 *
648 * Register|BitsName
649 * --------|--------
650 * CTRL0 | SLVOE
651 *
652 * @param SPIx SPI instance
653 * @retval None
654 */
655 __STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
656 {
657 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
658 }
659
660 /**
661 * @brief Disable slave output
662 *
663 * Register|BitsName
664 * --------|--------
665 * CTRL0 | SLVOE
666 *
667 * @param SPIx SPI instance
668 * @retval None
669 */
670 __STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
671 {
672 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
673 }
674
675 /**
676 * @brief Check if slave output is enabled
677 *
678 * Register|BitsName
679 * --------|--------
680 * CTRL0 | SLVOE
681 *
682 * @param SPIx SPI instance
683 * @retval State of bit (1 or 0).
684 */
685 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
686 {
687 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN) != (SPI_CTRL0_S_OUT_EN));
688 }
689
690 /**
691 * @brief Set transfer direction mode
692 *
693 * Register|BitsName
694 * --------|--------
695 * CTRL0 | TMOD
696 *
697 * @param SPIx SPI instance
698 * @param transfer_direction This parameter can be one of the following values:
699 * @arg @ref LL_SPI_FULL_DUPLEX
700 * @arg @ref LL_SPI_SIMPLEX_TX
701 * @arg @ref LL_SPI_SIMPLEX_RX
702 * @arg @ref LL_SPI_READ_EEPROM
703 * @retval None
704 */
705 __STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
706 {
707 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_XFE_MODE, transfer_direction);
708 }
709
710 /**
711 * @brief Get transfer direction mode
712 *
713 * Register|BitsName
714 * --------|--------
715 * CTRL0 | TMOD
716 *
717 * @param SPIx SPI instance
718 * @retval Returned value can be one of the following values:
719 * @arg @ref LL_SPI_FULL_DUPLEX
720 * @arg @ref LL_SPI_SIMPLEX_TX
721 * @arg @ref LL_SPI_SIMPLEX_RX
722 * @arg @ref LL_SPI_READ_EEPROM
723 */
724 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
725 {
726 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_XFE_MODE));
727 }
728
729 /**
730 * @brief Set clock polarity
731 * @note This bit should not be changed when communication is ongoing.
732 * This bit is not used in SPI TI mode.
733 *
734 * Register|BitsName
735 * --------|--------
736 * CTRL0 | SCPOL
737 *
738 * @param SPIx SPI instance
739 * @param clock_polarity This parameter can be one of the following values:
740 * @arg @ref LL_SPI_SCPOL_LOW
741 * @arg @ref LL_SPI_SCPOL_HIGH
742 * @retval None
743 */
744 __STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
745 {
746 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL, clock_polarity);
747 }
748
749 /**
750 * @brief Get clock polarity
751 *
752 * Register|BitsName
753 * --------|--------
754 * CTRL0 | SCPOL
755 *
756 * @param SPIx SPI instance
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_SPI_SCPOL_LOW
759 * @arg @ref LL_SPI_SCPOL_HIGH
760 */
761 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
762 {
763 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL));
764 }
765
766 /**
767 * @brief Set clock phase
768 * @note This bit should not be changed when communication is ongoing.
769 * This bit is not used in SPI TI mode.
770 *
771 * Register|BitsName
772 * --------|--------
773 * CTRL0 | SCPHA
774 *
775 * @param SPIx SPI instance
776 * @param clock_phase This parameter can be one of the following values:
777 * @arg @ref LL_SPI_SCPHA_1EDGE
778 * @arg @ref LL_SPI_SCPHA_2EDGE
779 * @retval None
780 */
781 __STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
782 {
783 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE, clock_phase);
784 }
785
786 /**
787 * @brief Get clock phase
788 *
789 * Register|BitsName
790 * --------|--------
791 * CTRL0 | SCPHA
792 *
793 * @param SPIx SPI instance
794 * @retval Returned value can be one of the following values:
795 * @arg @ref LL_SPI_SCPHA_1EDGE
796 * @arg @ref LL_SPI_SCPHA_2EDGE
797 */
798 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
799 {
800 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE));
801 }
802
803 /**
804 * @brief Set serial protocol used
805 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
806 *
807 * Register|BitsName
808 * --------|--------
809 * CTRL0 | FRF
810 *
811 * @param SPIx SPI instance
812 * @param standard This parameter can be one of the following values:
813 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
814 * @arg @ref LL_SPI_PROTOCOL_TI
815 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
816 * @retval None
817 */
818 __STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
819 {
820 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT, standard);
821 }
822
823 /**
824 * @brief Get serial protocol used
825 *
826 * Register|BitsName
827 * --------|--------
828 * CTRL0 | FRF
829 *
830 * @param SPIx SPI instance
831 * @retval Returned value can be one of the following values:
832 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
833 * @arg @ref LL_SPI_PROTOCOL_TI
834 * @arg @ref LL_SPI_PROTOCOL_MICROWIRE
835 */
836 __STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
837 {
838 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT));
839 }
840
841 /**
842 * @brief Set the number of data frames to be continuously received
843 * @note These bits should not be changed when communication is ongoing.
844 This bits are effect when TMOD = 2b10 or 2b11.
845 This bits are not effect in SPIS.
846 *
847 * Register|BitsName
848 * --------|--------
849 * CTRL1 | NDF
850 *
851 * @param SPIx SPI instance
852 * @param size This parameter can be one of the following values: 0 ~ 65535
853 * @retval None
854 */
855 __STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
856 {
857 MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME, size);
858 }
859
860 /**
861 * @brief Get the number of data frames to be continuously received
862 * @note These bits should not be changed when communication is ongoing.
863 This bits are effect when TMOD = 2b10 or 2b11.
864 This bits are not effect in SPIS.
865 *
866 * Register|BitsName
867 * --------|--------
868 * CTRL1 | NDF
869 *
870 * @param SPIx SPI instance
871 * @retval Returned value can be one of the following values: 0 ~ 65535
872 */
873 __STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
874 {
875 return (uint32_t)(READ_BITS(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME));
876 }
877
878 /**
879 * @brief Enable SPI peripheral
880 *
881 * Register|BitsName
882 * --------|--------
883 * SSI_EN | EN
884 *
885 * @param SPIx SPI instance
886 * @retval None
887 */
888 __STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
889 {
890 SET_BITS(SPIx->SSI_EN, SPI_SSI_EN);
891 }
892
893 /**
894 * @brief Disable SPI peripheral
895 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
896 *
897 * Register|BitsName
898 * --------|--------
899 * SSI_EN | EN
900 *
901 * @param SPIx SPI instance
902 * @retval None
903 */
904 __STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
905 {
906 CLEAR_BITS(SPIx->SSI_EN, SPI_SSI_EN);
907 }
908
909 /**
910 * @brief Check if SPI peripheral is enabled
911 *
912 * Register|BitsName
913 * --------|--------
914 * SSI_EN | EN
915 *
916 * @param SPIx SPI instance
917 * @retval State of bit (1 or 0).
918 */
919 __STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
920 {
921 return (READ_BITS(SPIx->SSI_EN, SPI_SSI_EN) == (SPI_SSI_EN));
922 }
923
924 /**
925 * @brief Enable Handshake in Microwire mode
926 *
927 * Register|BitsName
928 * --------|--------
929 * MWC | MHS
930 *
931 * @param SPIx SPI instance
932 * @retval None
933 */
934 __STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
935 {
936 SET_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
937 }
938
939 /**
940 * @brief Disable Handshake in Microwire mode
941 *
942 * Register|BitsName
943 * --------|--------
944 * MWC | MHS
945 *
946 * @param SPIx SPI instance
947 * @retval None
948 */
949 __STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
950 {
951 CLEAR_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
952 }
953
954 /**
955 * @brief Check if Handshake in Microwire mode is enabled
956 *
957 * Register|BitsName
958 * --------|--------
959 * MWC | MHS
960 *
961 * @param SPIx SPI instance
962 * @retval State of bit (1 or 0).
963 */
964 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
965 {
966 return (READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG) == (SPI_MW_CTRL_MW_HSG));
967 }
968
969 /**
970 * @brief Set transfer direction mode in Microwire mode
971 * @note This bit should not be changed when communication is ongoing.
972 *
973 * Register|BitsName
974 * --------|--------
975 * MWC | MDD
976 *
977 * @param SPIx SPI instance
978 * @param transfer_direction This parameter can be one of the following values:
979 * @arg @ref LL_SPI_MICROWIRE_RX
980 * @arg @ref LL_SPI_MICROWIRE_TX
981 * @retval None
982 */
983 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
984 {
985 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW, transfer_direction);
986 }
987
988 /**
989 * @brief Get transfer direction mode in Microwire mode
990 * @note This bit should not be changed when communication is ongoing.
991 *
992 * Register|BitsName
993 * --------|--------
994 * MWC | MDD
995 *
996 * @param SPIx SPI instance
997 * @retval Returned value can be one of the following values:
998 * @arg @ref LL_SPI_MICROWIRE_RX
999 * @arg @ref LL_SPI_MICROWIRE_TX
1000 */
1001 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
1002 {
1003 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW));
1004 }
1005
1006 /**
1007 * @brief Set transfer mode in Microwire mode
1008 * @note This bit should not be changed when communication is ongoing.
1009 *
1010 * Register|BitsName
1011 * --------|--------
1012 * MWC | MWMOD
1013 *
1014 * @param SPIx SPI instance
1015 * @param transfer_mode This parameter can be one of the following values:
1016 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1017 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1018 * @retval None
1019 */
1020 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
1021 {
1022 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE, transfer_mode);
1023 }
1024
1025 /**
1026 * @brief Get transfer mode in Microwire mode
1027 * @note This bit should not be changed when communication is ongoing.
1028 *
1029 * Register|BitsName
1030 * --------|--------
1031 * MWC | MWMOD
1032 *
1033 * @param SPIx SPI instance
1034 * @retval Returned value can be one of the following values:
1035 * @arg @ref LL_SPI_MICROWIRE_NON_SEQUENTIAL
1036 * @arg @ref LL_SPI_MICROWIRE_SEQUENTIAL
1037 */
1038 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
1039 {
1040 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE));
1041 }
1042
1043 /**
1044 * @brief Enable slave select
1045 *
1046 * Register|BitsName
1047 * --------|--------
1048 * SE | SLAVE1
1049 * SE | SLAVE0
1050 *
1051 * @param SPIx SPI instance
1052 * @param ss This parameter can be one of the following values:
1053 * @arg @ref LL_SPI_SLAVE1
1054 * @arg @ref LL_SPI_SLAVE0
1055 * @retval None
1056 */
1057 __STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
1058 {
1059 SET_BITS(SPIx->S_EN, ss);
1060 }
1061
1062 /**
1063 * @brief Disable slave select
1064 *
1065 * Register|BitsName
1066 * --------|--------
1067 * SE | SLAVE1
1068 * SE | SLAVE0
1069 *
1070 * @param SPIx SPI instance
1071 * @param ss This parameter can be one of the following values:
1072 * @arg @ref LL_SPI_SLAVE1
1073 * @arg @ref LL_SPI_SLAVE0
1074 * @retval None
1075 */
1076 __STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
1077 {
1078 CLEAR_BITS(SPIx->S_EN, ss);
1079 }
1080
1081 /**
1082 * @brief Check if slave select is enabled
1083 *
1084 * Register|BitsName
1085 * --------|--------
1086 * SE | SLAVE1
1087 * SE | SLAVE0
1088 *
1089 * @param SPIx SPI instance
1090 * @param ss This parameter can be one of the following values:
1091 * @arg @ref LL_SPI_SLAVE1
1092 * @arg @ref LL_SPI_SLAVE0
1093 * @retval State of bit (1 or 0).
1094 */
1095 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
1096 {
1097 return (READ_BITS(SPIx->S_EN, ss) == ss);
1098 }
1099
1100 /**
1101 * @brief Set baud rate prescaler
1102 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1103 *
1104 * Register|BitsName
1105 * --------|--------
1106 * BAUD | SCKDIV
1107 *
1108 * @param SPIx SPI instance
1109 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1110 * @retval None
1111 */
1112 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
1113 {
1114 WRITE_REG(SPIx->BAUD, baud_rate);
1115 }
1116
1117 /**
1118 * @brief Get baud rate prescaler
1119 *
1120 * Register|BitsName
1121 * --------|--------
1122 * BAUD | SCKDIV
1123 *
1124 * @param SPIx SPI instance
1125 * @retval Returned value can be one even value between 2 and 65534.
1126 */
1127 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
1128 {
1129 return (uint32_t)(READ_BITS(SPIx->BAUD, SPI_BAUD_CLK_DIV));
1130 }
1131
1132 /**
1133 * @brief Set threshold of TXFIFO that triggers an TXE event
1134 *
1135 * Register|BitsName
1136 * --------|--------
1137 * TXFTL | TFT
1138 *
1139 * @param SPIx SPI instance
1140 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1141 * @retval None
1142 */
1143 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1144 {
1145 WRITE_REG(SPIx->TX_FIFO_TL, threshold);
1146 }
1147
1148 /**
1149 * @brief Get threshold of TXFIFO that triggers an TXE event
1150 *
1151 * Register|BitsName
1152 * --------|--------
1153 * TXFTL | TFT
1154 *
1155 * @param SPIx SPI instance
1156 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1157 */
1158 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
1159 {
1160 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_TL, SPI_TX_FIFO_TL_TX_FIFO_THD));
1161 }
1162
1163 /**
1164 * @brief Set threshold of RXFIFO that triggers an RXNE event
1165 *
1166 * Register|BitsName
1167 * --------|--------
1168 * RXFTL | RFT
1169 *
1170 * @param SPIx SPI instance
1171 * @param threshold This parameter can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1172 * @retval None
1173 */
1174 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1175 {
1176 WRITE_REG(SPIx->RX_FIFO_TL, threshold);
1177 }
1178
1179 /**
1180 * @brief Get threshold of RXFIFO that triggers an RXNE event
1181 *
1182 * Register|BitsName
1183 * --------|--------
1184 * RXFTL | RFT
1185 *
1186 * @param SPIx SPI instance
1187 * @retval Returned value can be one of the following values: 0 ~ (LL_SPI_x_FIFO_DEPTH - 1)
1188 */
1189 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
1190 {
1191 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_TL, SPI_RX_FIFO_TL_RX_FIFO_THD));
1192 }
1193
1194 /**
1195 * @brief Get FIFO Transmission Level
1196 *
1197 * Register|BitsName
1198 * --------|--------
1199 * TXFL | TXTFL
1200 *
1201 * @param SPIx SPI instance
1202 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1203 */
1204 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
1205 {
1206 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_LEVEL, SPI_TX_FIFO_LEVEL_TX_FIFO_LEVEL));
1207 }
1208
1209 /**
1210 * @brief Get FIFO reception Level
1211 *
1212 * Register|BitsName
1213 * --------|--------
1214 * RXFL | RXTFL
1215 *
1216 * @param SPIx SPI instance
1217 * @retval Returned value can be one of the following values: 0 ~ LL_SPI_x_FIFO_DEPTH
1218 */
1219 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
1220 {
1221 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_LEVEL, SPI_RX_FIFO_LEVEL_RX_FIFO_LEVEL));
1222 }
1223
1224 /** @} */
1225
1226 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1227 * @{
1228 */
1229
1230 /**
1231 * @brief Enable interrupt
1232 * @note This bit controls the generation of an interrupt when an event occurs.
1233 *
1234 * Register|BitsName
1235 * --------|--------
1236 * INTMASK | INTMASK
1237 *
1238 * @param SPIx SPI instance
1239 * @param mask This parameter can be one of the following values:
1240 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1241 * @arg @ref LL_SPI_IM_RXF
1242 * @arg @ref LL_SPI_IM_RXO
1243 * @arg @ref LL_SPI_IM_RXU
1244 * @arg @ref LL_SPI_IM_TXO
1245 * @arg @ref LL_SPI_IM_TXE
1246 * @retval None
1247 */
1248 __STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
1249 {
1250 SET_BITS(SPIx->INT_MASK, mask);
1251 }
1252
1253 /**
1254 * @brief Disable interrupt
1255 * @note This bit controls the generation of an interrupt when an event occurs.
1256 *
1257 * Register|BitsName
1258 * --------|--------
1259 * INTMASK | INTMASK
1260 *
1261 * @param SPIx SPI instance
1262 * @param mask This parameter can be one of the following values:
1263 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1264 * @arg @ref LL_SPI_IM_RXF
1265 * @arg @ref LL_SPI_IM_RXO
1266 * @arg @ref LL_SPI_IM_RXU
1267 * @arg @ref LL_SPI_IM_TXO
1268 * @arg @ref LL_SPI_IM_TXE
1269 * @retval None
1270 */
1271 __STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
1272 {
1273 CLEAR_BITS(SPIx->INT_MASK, mask);
1274 }
1275
1276 /**
1277 * @brief Check if interrupt is enabled
1278 *
1279 * Register|BitsName
1280 * --------|--------
1281 * INTMASK | INTMASK
1282 *
1283 * @param SPIx SPI instance
1284 * @param mask This parameter can be one of the following values:
1285 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1286 * @arg @ref LL_SPI_IM_RXF
1287 * @arg @ref LL_SPI_IM_RXO
1288 * @arg @ref LL_SPI_IM_RXU
1289 * @arg @ref LL_SPI_IM_TXO
1290 * @arg @ref LL_SPI_IM_TXE
1291 * @retval State of bit (1 or 0).
1292 */
1293 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
1294 {
1295 return (READ_BITS(SPIx->INT_MASK, mask) == mask);
1296 }
1297
1298 /** @} */
1299
1300 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1301 * @{
1302 */
1303
1304 /**
1305 * @brief Get SPI status
1306 *
1307 * Register|BitsName
1308 * --------|--------
1309 * STAT | STAT
1310 *
1311 * @param SPIx SPI instance
1312 * @retval Returned value can be one or combination of the following values:
1313 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1314 * @arg @ref LL_SPI_SR_TXE
1315 * @arg @ref LL_SPI_SR_RFF
1316 * @arg @ref LL_SPI_SR_RFNE
1317 * @arg @ref LL_SPI_SR_TFE
1318 * @arg @ref LL_SPI_SR_TFNF
1319 * @arg @ref LL_SPI_SR_BUSY
1320 */
1321 __STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
1322 {
1323 return (uint32_t)(READ_REG(SPIx->STAT));
1324 }
1325
1326 /**
1327 * @brief Check active flag
1328 *
1329 * Register|BitsName
1330 * --------|--------
1331 * STAT | DCOL
1332 * STAT | TXE
1333 * STAT | RFF
1334 * STAT | RFNE
1335 * STAT | TFE
1336 * STAT | TFNF
1337 * STAT | BUSY
1338 *
1339 * @param SPIx SPI instance
1340 * @param flag This parameter can be one of the following values:
1341 * @arg @ref LL_SPI_SR_DCOL(no effect in SPIS)
1342 * @arg @ref LL_SPI_SR_TXE
1343 * @arg @ref LL_SPI_SR_RFF
1344 * @arg @ref LL_SPI_SR_RFNE
1345 * @arg @ref LL_SPI_SR_TFE
1346 * @arg @ref LL_SPI_SR_TFNF
1347 * @arg @ref LL_SPI_SR_BUSY
1348 * @retval State of bit (1 or 0).
1349 */
1350 __STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
1351 {
1352 return (READ_BITS(SPIx->STAT, flag) == (flag));
1353 }
1354
1355 /**
1356 * @brief Get SPI interrupt flags
1357 *
1358 * Register|BitsName
1359 * --------|--------
1360 * INTSTAT | INTSTAT
1361 *
1362 * @param SPIx SPI instance
1363 * @retval Returned value can be one or combination of the following values:
1364 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1365 * @arg @ref LL_SPI_IM_RXF
1366 * @arg @ref LL_SPI_IM_RXO
1367 * @arg @ref LL_SPI_IM_RXU
1368 * @arg @ref LL_SPI_IM_TXO
1369 * @arg @ref LL_SPI_IM_TXE
1370 */
1371 __STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
1372 {
1373 return (uint32_t)(READ_REG(SPIx->INT_STAT));
1374 }
1375
1376 /**
1377 * @brief Check interrupt flag
1378 *
1379 * Register|BitsName
1380 * --------|--------
1381 * INTSTAT | MSTIS
1382 * INTSTAT | RXFIS
1383 * INTSTAT | RXOIS
1384 * INTSTAT | RXUIS
1385 * INTSTAT | TXOIS
1386 * INTSTAT | TXEIS
1387 *
1388 * @param SPIx SPI instance
1389 * @param flag This parameter can be one of the following values:
1390 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1391 * @arg @ref LL_SPI_IM_RXF
1392 * @arg @ref LL_SPI_IM_RXO
1393 * @arg @ref LL_SPI_IM_RXU
1394 * @arg @ref LL_SPI_IM_TXO
1395 * @arg @ref LL_SPI_IM_TXE
1396 * @retval State of bit (1 or 0).
1397 */
1398 __STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
1399 {
1400 return (READ_BITS(SPIx->INT_STAT, flag) == flag);
1401 }
1402
1403 /**
1404 * @brief Get SPI raw interrupt flags
1405 *
1406 * Register|BitsName
1407 * --------|--------
1408 * RAW_INTSTAT | RAW_INTSTAT
1409 *
1410 * @param SPIx SPI instance
1411 * @retval Returned value can be one or combination of the following values:
1412 * @arg @ref LL_SPI_IM_MST(not effect in SPIS)
1413 * @arg @ref LL_SPI_IM_RXF
1414 * @arg @ref LL_SPI_IM_RXO
1415 * @arg @ref LL_SPI_IM_RXU
1416 * @arg @ref LL_SPI_IM_TXO
1417 * @arg @ref LL_SPI_IM_TXE
1418 */
1419 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
1420 {
1421 return (uint32_t)(READ_REG(SPIx->RAW_INT_STAT));
1422 }
1423
1424 /**
1425 * @brief Clear transmit FIFO overflow error flag
1426 * @note Clearing this flag is done by reading TXOIC register
1427 *
1428 * Register|BitsName
1429 * --------|--------
1430 * TXOIC | TXOIC
1431 *
1432 * @param SPIx SPI instance
1433 * @retval None
1434 */
1435 __STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
1436 {
1437 __IOM uint32_t tmpreg;
1438 tmpreg = SPIx->TX_FIFO_OIC;
1439 (void) tmpreg;
1440 }
1441
1442 /**
1443 * @brief Clear receive FIFO overflow error flag
1444 * @note Clearing this flag is done by reading RXOIC register
1445 *
1446 * Register|BitsName
1447 * --------|--------
1448 * RXOIC | RXOIC
1449 *
1450 * @param SPIx SPI instance
1451 * @retval None
1452 */
1453 __STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
1454 {
1455 __IOM uint32_t tmpreg;
1456 tmpreg = SPIx->RX_FIFO_OIC;
1457 (void) tmpreg;
1458 }
1459
1460 /**
1461 * @brief Clear receive FIFO underflow error flag
1462 * @note Clearing this flag is done by reading RXUIC register
1463 *
1464 * Register|BitsName
1465 * --------|--------
1466 * RXUIC | RXUIC
1467 *
1468 * @param SPIx SPI instance
1469 * @retval None
1470 */
1471 __STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
1472 {
1473 __IOM uint32_t tmpreg;
1474 tmpreg = SPIx->RX_FIFO_UIC;
1475 (void) tmpreg;
1476 }
1477
1478 /**
1479 * @brief Clear multi-master error flag
1480 * @note Clearing this flag is done by reading MSTIC register
1481 *
1482 * Register|BitsName
1483 * --------|--------
1484 * MSTIC | MSTIC
1485 *
1486 * @param SPIx SPI instance
1487 * @retval None
1488 */
1489 __STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
1490 {
1491 __IOM uint32_t tmpreg;
1492 tmpreg = SPIx->MULTI_M_IC;
1493 (void) tmpreg;
1494 }
1495
1496 /**
1497 * @brief Clear all error flag
1498 * @note Clearing this flag is done by reading INTCLR register
1499 *
1500 * Register|BitsName
1501 * --------|--------
1502 * INTCLR | INTCLR
1503 *
1504 * @param SPIx SPI instance
1505 * @retval None
1506 */
1507 __STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
1508 {
1509 __IOM uint32_t tmpreg;
1510 tmpreg = SPIx->INT_CLR;
1511 (void) tmpreg;
1512 }
1513
1514 /** @} */
1515
1516 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1517 * @{
1518 */
1519
1520 /**
1521 * @brief Enable DMA Tx
1522 *
1523 * Register|BitsName
1524 * --------|--------
1525 * DMAC | TDMAE
1526 *
1527 * @param SPIx SPI instance
1528 * @retval None
1529 */
1530 __STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
1531 {
1532 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1533 }
1534
1535 /**
1536 * @brief Disable DMA Tx
1537 *
1538 * Register|BitsName
1539 * --------|--------
1540 * DMAC | TDMAE
1541 *
1542 * @param SPIx SPI instance
1543 * @retval None
1544 */
1545 __STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
1546 {
1547 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1548 }
1549
1550 /**
1551 * @brief Check if DMA Tx is enabled
1552 *
1553 * Register|BitsName
1554 * --------|--------
1555 * DMAC | TDMAE
1556 *
1557 * @param SPIx SPI instance
1558 * @retval State of bit (1 or 0).
1559 */
1560 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
1561 {
1562 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN) == (SPI_DMA_CTRL_TX_DMA_EN));
1563 }
1564
1565 /**
1566 * @brief Enable DMA Rx
1567 *
1568 * Register|BitsName
1569 * --------|--------
1570 * DMAC | RDMAE
1571 *
1572 * @param SPIx SPI instance
1573 * @retval None
1574 */
1575 __STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
1576 {
1577 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1578 }
1579
1580 /**
1581 * @brief Disable DMA Rx
1582 *
1583 * Register|BitsName
1584 * --------|--------
1585 * DMAC | RDMAE
1586 *
1587 * @param SPIx SPI instance
1588 * @retval None
1589 */
1590 __STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
1591 {
1592 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1593 }
1594
1595 /**
1596 * @brief Check if DMA Rx is enabled
1597 *
1598 * Register|BitsName
1599 * --------|--------
1600 * DMAC | RDMAE
1601 *
1602 * @param SPIx SPI instance
1603 * @retval State of bit (1 or 0).
1604 */
1605 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
1606 {
1607 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN) == (SPI_DMA_CTRL_RX_DMA_EN));
1608 }
1609
1610 /**
1611 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
1612 *
1613 * Register|BitsName
1614 * --------|--------
1615 * DMATDL | DMATDL
1616 *
1617 * @param SPIx SPI instance
1618 * @param threshold This parameter can be one of the following values: 0 ~ 7
1619 * @retval None
1620 */
1621 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1622 {
1623 WRITE_REG(SPIx->DMA_TX_DL, threshold);
1624 }
1625
1626 /**
1627 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
1628 *
1629 * Register|BitsName
1630 * --------|--------
1631 * DMATDL | DMATDL
1632 *
1633 * @param SPIx SPI instance
1634 * @retval Returned value can be one of the following values: 0 ~ 7
1635 */
1636 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
1637 {
1638 return (uint32_t)(READ_BITS(SPIx->DMA_TX_DL, SPI_DMA_TX_DL_DMA_TX_DL));
1639 }
1640
1641 /**
1642 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
1643 *
1644 * Register|BitsName
1645 * --------|--------
1646 * DMARDL | DMARDL
1647 *
1648 * @param SPIx SPI instance
1649 * @param threshold This parameter can be one of the following values: 0 ~ 7
1650 * @retval None
1651 */
1652 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
1653 {
1654 WRITE_REG(SPIx->DMA_RX_DL, threshold);
1655 }
1656
1657 /**
1658 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
1659 *
1660 * Register|BitsName
1661 * --------|--------
1662 * DMARDL | DMARDL
1663 *
1664 * @param SPIx SPI instance
1665 * @retval Returned value can be one of the following values: 0 ~ 7
1666 */
1667 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
1668 {
1669 return (uint32_t)(READ_BITS(SPIx->DMA_RX_DL, SPI_DMA_RX_DL_DMA_RX_DL));
1670 }
1671
1672 /** @} */
1673
1674 /** @defgroup SPI_LL_EF_Data_Management Data_Management
1675 * @{
1676 */
1677
1678 /**
1679 * @brief Write 8-Bits in the data register
1680 *
1681 * Register|BitsName
1682 * --------|--------
1683 * DATA | DATA
1684 *
1685 * @param SPIx SPI instance
1686 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
1687 * @retval None
1688 */
1689 __STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
1690 {
1691 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1692 }
1693
1694 /**
1695 * @brief Write 16-Bits in the data register
1696 *
1697 * Register|BitsName
1698 * --------|--------
1699 * DATA | DATA
1700 *
1701 * @param SPIx SPI instance
1702 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
1703 * @retval None
1704 */
1705 __STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
1706 {
1707 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1708 }
1709
1710 /**
1711 * @brief Write 32-Bits in the data register
1712 *
1713 * Register|BitsName
1714 * --------|--------
1715 * DATA | DATA
1716 *
1717 * @param SPIx SPI instance
1718 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1719 * @retval None
1720 */
1721 __STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
1722 {
1723 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1724 }
1725
1726 /**
1727 * @brief Read 8-Bits in the data register
1728 *
1729 * Register|BitsName
1730 * --------|--------
1731 * DATA | DATA
1732 *
1733 * @param SPIx SPI instance
1734 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
1735 */
1736 __STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
1737 {
1738 return (uint8_t)(READ_REG(SPIx->DATA));
1739 }
1740
1741 /**
1742 * @brief Read 16-Bits in the data register
1743 *
1744 * Register|BitsName
1745 * --------|--------
1746 * DATA | DATA
1747 *
1748 * @param SPIx SPI instance
1749 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
1750 */
1751 __STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
1752 {
1753 return (uint16_t)(READ_REG(SPIx->DATA));
1754 }
1755
1756 /**
1757 * @brief Read 32-Bits in the data register
1758 *
1759 * Register|BitsName
1760 * --------|--------
1761 * DATA | DATA
1762 *
1763 * @param SPIx SPI instance
1764 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1765 */
1766 __STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
1767 {
1768 return (uint32_t)(READ_REG(SPIx->DATA));
1769 }
1770
1771 /**
1772 * @brief Set Rx sample delay
1773 * @note This bit should not be changed when communication is ongoing.
1774 *
1775 * Register|BitsName
1776 * --------|--------
1777 * RX_SAMPLEDLY | RX_SAMPLEDLY
1778 *
1779 * @param SPIx SPI instance
1780 * @param delay This parameter can be one of the following values: 0 ~ 7
1781 * @retval None
1782 */
1783 __STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
1784 {
1785 MODIFY_REG(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY, delay);
1786 }
1787
1788 /**
1789 * @brief Get Rx sample delay
1790 * @note This bit should not be changed when communication is ongoing.
1791 *
1792 * Register|BitsName
1793 * --------|--------
1794 * RX_SAMPLEDLY | RX_SAMPLEDLY
1795 *
1796 * @param SPIx SPI instance
1797 * @retval Returned value can be one of the following values: 0 ~ 7
1798 */
1799 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
1800 {
1801 return (uint32_t)(READ_BITS(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY));
1802 }
1803
1804 /** @} */
1805
1806 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
1807 * @{
1808 */
1809
1810 /**
1811 * @brief De-initialize SSI registers (Registers restored to their default values).
1812 * @param SPIx SSI instance
1813 * @retval An error_status_t enumeration value:
1814 * - SUCCESS: SSI registers are de-initialized
1815 * - ERROR: SSI registers are not de-initialized
1816 */
1817 error_status_t ll_spim_deinit(spi_regs_t *SPIx);
1818
1819 /**
1820 * @brief Initialize SPIM registers according to the specified
1821 * parameters in p_spi_init.
1822 * @param SPIx SSI instance
1823 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
1824 * information for the specified SPIM peripheral.
1825 * @retval An error_status_t enumeration value:
1826 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1827 * - ERROR: Problem occurred during SSI Registers initialization
1828 */
1829 error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
1830
1831 /**
1832 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
1833 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
1834 * whose fields will be set to default values.
1835 * @retval None
1836 */
1837 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
1838
1839 /** @} */
1840
1841 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
1842 * @{
1843 */
1844
1845 /**
1846 * @brief De-initialize SSI registers (Registers restored to their default values).
1847 * @param SPIx SSI instance
1848 * @retval An error_status_t enumeration value:
1849 * - SUCCESS: SSI registers are de-initialized
1850 * - ERROR: SSI registers are not de-initialized
1851 */
1852 error_status_t ll_spis_deinit(spi_regs_t *SPIx);
1853
1854 /**
1855 * @brief Initialize SSI registers according to the specified
1856 * parameters in p_spi_init.
1857 * @param SPIx SSI instance
1858 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
1859 * information for the specified SPIS peripheral.
1860 * @retval An error_status_t enumeration value:
1861 * - SUCCESS: SSI registers are initialized according to p_spi_init content
1862 * - ERROR: Problem occurred during SPI Registers initialization
1863 */
1864 error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
1865
1866 /**
1867 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
1868 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
1869 * whose fields will be set to default values.
1870 * @retval None
1871 */
1872 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
1873 /** @} */
1874
1875 /** @} */
1876
1877 #endif /* SPIM || SPIS */
1878
1879 #ifdef __cplusplus
1880 }
1881 #endif
1882
1883 #endif /* __GR533x_LL_SPI_H__ */
1884
1885 /** @} */
1886
1887 /** @} */
1888
1889 /** @} */
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr533x_ll_spi.h:1575
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr533x_ll_spi.h:640
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr533x_ll_spi.h:1143
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr533x_ll_spi.h:1689
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr533x_ll_spi.h:1799
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr533x_ll_spi.h:1590
_ll_spis_init_t
SPIS init structures definition.
Definition: gr533x_ll_spi.h:117
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr533x_ll_spi.h:1158
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr533x_ll_spi.h:1667
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Definition: gr533x_ll_spi.h:118
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr533x_ll_spi.h:1057
ll_spis_init
error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr533x_ll_spi.h:409
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr533x_ll_spi.h:1248
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr533x_ll_spi.h:610
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr533x_ll_spi.h:1621
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr533x_ll_spi.h:77
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
Enable slave output.
Definition: gr533x_ll_spi.h:655
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr533x_ll_spi.h:855
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr533x_ll_spi.h:1783
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr533x_ll_spi.h:1350
ll_spim_init
error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr533x_ll_spi.h:888
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
Clear all error flag.
Definition: gr533x_ll_spi.h:1507
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr533x_ll_spi.h:1189
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr533x_ll_spi.h:934
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr533x_ll_spi.h:425
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr533x_ll_spi.h:88
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr533x_ll_spi.h:1419
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
Disable slave output.
Definition: gr533x_ll_spi.h:670
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr533x_ll_spi.h:123
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr533x_ll_spi.h:1371
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr533x_ll_spi.h:1652
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr533x_ll_spi.h:904
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr533x_ll_spi.h:1766
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr533x_ll_spi.h:1112
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr533x_ll_spi.h:1636
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr533x_ll_spi.h:1001
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Definition: gr533x_ll_spi.h:103
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr533x_ll_spi.h:964
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr533x_ll_spi.h:595
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Definition: gr533x_ll_spi.h:78
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr533x_ll_spi.h:1705
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr533x_ll_spi.h:818
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Definition: gr533x_ll_spi.h:83
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
Get SPI status.
Definition: gr533x_ll_spi.h:1321
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
Get frame data size.
Definition: gr533x_ll_spi.h:530
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr533x_ll_spi.h:1038
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr533x_ll_spi.h:744
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr533x_ll_spi.h:983
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr533x_ll_spi.h:1204
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr533x_ll_spi.h:1560
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr533x_ll_spi.h:919
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr533x_ll_spi.h:486
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr533x_ll_spi.h:1530
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr533x_ll_spi.h:1076
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr533x_ll_spi.h:1174
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr533x_ll_spi.h:949
_ll_spim_init_t::slave_select
uint32_t slave_select
Definition: gr533x_ll_spi.h:98
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr533x_ll_spi.h:873
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
Get clock phase.
Definition: gr533x_ll_spi.h:798
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr533x_ll_spi.h:1219
ll_spim_deinit
error_status_t ll_spim_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr533x_ll_spi.h:1545
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr533x_ll_spi.h:1127
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr533x_ll_spi.h:1751
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr533x_ll_spi.h:685
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr533x_ll_spi.h:441
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
Get serial protocol used.
Definition: gr533x_ll_spi.h:836
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr533x_ll_spi.h:1453
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr533x_ll_spi.h:1435
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr533x_ll_spi.h:1721
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr533x_ll_spi.h:724
_ll_spim_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr533x_ll_spi.h:109
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr533x_ll_spi.h:1398
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Definition: gr533x_ll_spi.h:128
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Definition: gr533x_ll_spi.h:93
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr533x_ll_spi.h:563
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr533x_ll_spi.h:1736
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr533x_ll_spi.h:1605
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr533x_ll_spi.h:781
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr533x_ll_spi.h:1271
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr533x_ll_spi.h:1020
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr533x_ll_spi.h:1095
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr533x_ll_spi.h:1293
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr533x_ll_spi.h:705
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr533x_ll_spi.h:625
ll_spis_deinit
error_status_t ll_spis_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr533x_ll_spi.h:1489
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
Get clock polarity.
Definition: gr533x_ll_spi.h:761
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr533x_ll_spi.h:1471