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52 #ifndef __GR533x_LL_UART_H__
53 #define __GR533x_LL_UART_H__
62 #if defined (UART0) || defined (UART1) || \
63 defined (UART2) || defined (UART3) || \
64 defined (UART4) || defined (UART5)
123 #define LL_UART_LSR_OE UART_LSR_OE
124 #define LL_UART_LSR_PE UART_LSR_PE
125 #define LL_UART_LSR_FE UART_LSR_FE
126 #define LL_UART_LSR_BI UART_LSR_BI
127 #define LL_UART_LSR_THRE UART_LSR_THRE
128 #define LL_UART_LSR_TEMT UART_LSR_TEMT
129 #define LL_UART_LSR_RFE UART_LSR_RFE
131 #define LL_UART_IIR_MS UART_IIR_IID_MS
132 #define LL_UART_IIR_NIP UART_IIR_IID_NIP
133 #define LL_UART_IIR_THRE UART_IIR_IID_THRE
134 #define LL_UART_IIR_RDA UART_IIR_IID_RDA
135 #define LL_UART_IIR_RLS UART_IIR_IID_RLS
136 #define LL_UART_IIR_CTO UART_IIR_IID_CTO
138 #define LL_UART_USR_RFF UART_USR_RFF
139 #define LL_UART_USR_RFNE UART_USR_RFNE
140 #define LL_UART_USR_TFE UART_USR_TFE
141 #define LL_UART_USR_TFNF UART_USR_TFNF
148 #define LL_UART_IER_MS UART_IER_EDSSI
149 #define LL_UART_IER_RLS UART_IER_ERLS
150 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME)
151 #define LL_UART_IER_RDA UART_IER_ERBFI
157 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE
158 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD
159 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN
160 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0
161 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1
167 #define LL_UART_DATABITS_5B UART_LCR_DLS_5
168 #define LL_UART_DATABITS_6B UART_LCR_DLS_6
169 #define LL_UART_DATABITS_7B UART_LCR_DLS_7
170 #define LL_UART_DATABITS_8B UART_LCR_DLS_8
176 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1
177 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5
178 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2
184 #define LL_UART_HWCONTROL_NONE 0x00000000U
185 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS)
191 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U
192 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U
193 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U
194 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U
200 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U
201 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U
202 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U
203 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U
209 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U
210 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U
216 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U
217 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U
227 #define LL_UART_DEFAULT_CONFIG \
229 .baud_rate = 9600U, \
230 .data_bits = LL_UART_DATABITS_8B, \
231 .stop_bits = LL_UART_STOPBITS_1, \
232 .parity = LL_UART_PARITY_NONE, \
233 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
255 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
263 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
278 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
287 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
321 register uint32_t uartdiv =
__LL_UART_DIV(peripheral_clock, baud_rate);
323 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
324 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
325 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
326 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
327 WRITE_REG(UARTx->DLF,
__LL_UART_DLF(peripheral_clock, baud_rate));
345 register uint32_t uartdiv = 0x0U;
346 register uint32_t baud = 0x0U;
348 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
349 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
350 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
352 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
354 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
378 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
397 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
419 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
437 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
463 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
485 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
529 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
549 WRITE_REG(UARTx->SRTS, pin_state);
568 return (uint32_t)(READ_REG(UARTx->SRTS));
586 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
601 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
617 SET_BITS(UARTx->MCR, UART_MCR_SIRE);
633 CLEAR_BITS(UARTx->MCR, UART_MCR_SIRE);
649 return (READ_BITS(UARTx->MCR, UART_MCR_SIRE) == UART_MCR_SIRE);
669 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
687 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
702 WRITE_REG(UARTx->SBCR, 0x1U);
717 WRITE_REG(UARTx->SBCR, 0x0U);
732 return READ_REG(UARTx->SBCR);
747 WRITE_REG(UARTx->SFE, 0x1U);
762 WRITE_REG(UARTx->SFE, 0x0U);
777 return READ_REG(UARTx->SFE);
797 WRITE_REG(UARTx->STET, threshold);
816 return (uint32_t)(READ_REG(UARTx->STET));
836 WRITE_REG(UARTx->SRT, threshold);
855 return (uint32_t)(READ_REG(UARTx->SRT));
870 return (uint32_t)(READ_REG(UARTx->TFL));
885 return (uint32_t)(READ_REG(UARTx->RFL));
900 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
915 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
933 WRITE_REG(UARTx->SRR, UART_SRR_UR);
954 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
969 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
985 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1000 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1015 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1030 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1046 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1061 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1076 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1091 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1107 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1123 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1147 SET_BITS(UARTx->DLH_IER.IER, mask);
1171 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1195 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1231 return ((uint32_t)READ_REG(UARTx->LSR));
1251 __IO uint32_t tmpreg;
1252 tmpreg = READ_REG(UARTx->LSR);
1268 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1283 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1298 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1313 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1337 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1360 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1381 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1397 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
__STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
Configure SIR mode enable.
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
LL UART init Structure definition.
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
__STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
Configure SIR mode disable.
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
Return SIR mode state.
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.