52 #ifndef __GR533X_LL_ADC_H__
53 #define __GR533X_LL_ADC_H__
76 typedef struct _ll_adc_init
127 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos)
128 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos)
129 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos)
130 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos)
131 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos)
132 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos)
133 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos)
134 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos)
141 #define LL_ADC_REF_VALUE_0P8 (0x3UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
142 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
143 #define LL_ADC_REF_VALUE_1P6 (0xAUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
144 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
150 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos)
151 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL)
157 #define LL_ADC_INPUT_SRC_IO0 (0UL)
158 #define LL_ADC_INPUT_SRC_IO1 (1UL)
159 #define LL_ADC_INPUT_SRC_IO2 (2UL)
160 #define LL_ADC_INPUT_SRC_IO3 (3UL)
161 #define LL_ADC_INPUT_SRC_IO4 (4UL)
162 #define LL_ADC_INPUT_SRC_IO5 (5UL)
163 #define LL_ADC_INPUT_SRC_IO6 (6UL)
164 #define LL_ADC_INPUT_SRC_IO7 (7UL)
165 #define LL_ADC_INPUT_SRC_TMP (13UL)
166 #define LL_ADC_INPUT_SRC_BAT (14UL)
167 #define LL_ADC_INPUT_SRC_REF (15UL)
174 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL)
175 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
176 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
177 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
178 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
200 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
208 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
230 #define LL_ADC_DEFAULT_CONFIG \
232 .channel_p = LL_ADC_INPUT_SRC_IO0, \
233 .channel_n = LL_ADC_INPUT_SRC_IO1, \
234 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
235 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
236 .ref_value = LL_ADC_REF_VALUE_1P2, \
237 .clock = LL_ADC_CLK_16M \
264 __STATIC_INLINE
void ll_adc_enable(
void)
266 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
278 __STATIC_INLINE
void ll_adc_disable(
void)
280 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
292 __STATIC_INLINE uint32_t ll_adc_is_enabled(
void)
294 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
306 __STATIC_INLINE
void ll_adc_disable_clock(
void)
308 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
320 __STATIC_INLINE uint32_t ll_adc_is_enabled_clock(
void)
322 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
343 __STATIC_INLINE
void ll_adc_set_clock(uint32_t clk)
345 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
365 __STATIC_INLINE uint32_t ll_adc_get_clock(
void)
367 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
384 __STATIC_INLINE
void ll_adc_set_ref_value(uint32_t value)
386 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
402 __STATIC_INLINE uint32_t ll_adc_get_ref_value(
void)
404 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
416 __STATIC_INLINE
void ll_adc_enable_temp(
void)
418 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
430 __STATIC_INLINE
void ll_adc_disable_temp(
void)
432 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
444 __STATIC_INLINE uint32_t ll_adc_is_enabled_temp(
void)
446 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
458 __STATIC_INLINE
void ll_adc_enable_vbat(
void)
460 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
472 __STATIC_INLINE
void ll_adc_disable_vbat(
void)
474 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
486 __STATIC_INLINE uint32_t ll_adc_is_enabled_vbat(
void)
488 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
503 __STATIC_INLINE
void ll_adc_set_input_mode(uint32_t mode)
505 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
519 __STATIC_INLINE uint32_t ll_adc_get_input_mode(
void)
521 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk));
535 __STATIC_INLINE
void ll_adc_enable_ofs_cal(
void)
537 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
549 __STATIC_INLINE
void ll_adc_disable_ofs_cal(
void)
551 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
563 __STATIC_INLINE uint32_t ll_adc_is_enabled_ofs_cal(
void)
565 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
579 __STATIC_INLINE
void ll_adc_set_dynamic_rang(uint32_t rang)
581 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
593 __STATIC_INLINE uint32_t ll_adc_get_dynamic_rang(
void)
595 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
615 __STATIC_INLINE
void ll_adc_set_channelp(uint32_t source)
617 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
636 __STATIC_INLINE uint32_t ll_adc_get_channelp(
void)
638 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
658 __STATIC_INLINE
void ll_adc_set_channeln(uint32_t source)
660 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
679 __STATIC_INLINE uint32_t ll_adc_get_channeln(
void)
681 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
693 __STATIC_INLINE
void ll_adc_enable_mas_rst(
void)
695 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
707 __STATIC_INLINE
void ll_adc_disable_mas_rst(
void)
709 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
721 __STATIC_INLINE uint32_t ll_adc_is_enabled_mas_rst(
void)
723 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
741 __STATIC_INLINE
void ll_adc_set_ref(uint32_t source)
743 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
760 __STATIC_INLINE uint32_t ll_adc_get_ref(
void)
762 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
777 __STATIC_INLINE
void ll_adc_set_ref_current(uint32_t source)
779 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
791 __STATIC_INLINE uint32_t ll_adc_get_ref_current(
void)
793 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
812 __STATIC_INLINE uint32_t ll_adc_read_fifo(
void)
814 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
827 __STATIC_INLINE
void ll_adc_set_thresh(uint32_t thresh)
829 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
841 __STATIC_INLINE uint32_t ll_adc_get_thresh(
void)
843 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
855 __STATIC_INLINE
void ll_adc_enable_dma_req(
void)
857 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
869 __STATIC_INLINE
void ll_adc_disable_dma_req(
void)
871 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
883 __STATIC_INLINE uint32_t ll_adc_is_enabled_dma_req(
void)
885 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
897 __STATIC_INLINE uint32_t ll_adc_is_fifo_notempty(
void)
899 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
911 __STATIC_INLINE uint32_t ll_adc_get_fifo_count(
void)
913 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
925 __STATIC_INLINE
void ll_adc_flush_fifo(
void)
927 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
939 __STATIC_INLINE uint32_t ll_adc_try_lock_hw_token(
void)
941 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_HW) == MCU_SUB_SNSADC_TKN_LOCKED_HW);
953 __STATIC_INLINE
void ll_adc_release_hw_token(
void)
955 WRITE_REG(MCU_SUB->SENSE_ADC_RET_TKN_HW, 0x00);
967 __STATIC_INLINE uint32_t ll_adc_try_lock_sw_token(
void)
969 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
981 __STATIC_INLINE
void ll_adc_release_sw_token(
void)
983 WRITE_REG(MCU_SUB->SENSE_ADC_RET_TKN_SW, 0x00);
995 __STATIC_INLINE uint32_t ll_adc_get_token_state(
void)
997 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);
1012 error_status_t ll_adc_deinit(
void);
1023 error_status_t ll_adc_init(ll_adc_init_t *p_adc_init);
1031 void ll_adc_struct_init(ll_adc_init_t *p_adc_init);