52 #ifndef _LL_CALENDAR_H__
53 #define _LL_CALENDAR_H__
73 #define LL_CALENDAR_DIV_NONE ((uint32_t)0x00U)
74 #define LL_CALENDAR_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos)
75 #define LL_CALENDAR_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos)
76 #define LL_CALENDAR_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos)
77 #define LL_CALENDAR_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos)
78 #define LL_CALENDAR_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos)
79 #define LL_CALENDAR_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos)
80 #define LL_CALENDAR_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos)
89 #define LL_CLDR_TIMER_TICK (0x0U)
95 #define LL_CLDR_TIMER_TICK_TYPE_SINGLE (0x0U)
96 #define LL_CLDR_TIMER_TICK_TYPE_AUTO (0x1U)
103 #define CLDR_REG_READ (READ_BITS(CALENDAR->CFG0, RTC_CFG0_EN | \
104 RTC_CFG0_ALARM_EN | \
130 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN |
CLDR_REG_READ);
144 MODIFY_REG(CALENDAR->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
158 return (READ_BITS(CALENDAR->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
172 WRITE_REG(CALENDAR->TIMER_W, counter);
187 WRITE_REG(CALENDAR->TIMER_W, counter);
188 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_TIMER_SET |
CLDR_REG_READ);
202 WRITE_REG(CALENDAR->ALARM_W, alarm);
217 WRITE_REG(CALENDAR->ALARM_W, alarm);
218 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET |
CLDR_REG_READ);
232 return (uint32_t)READ_REG(CALENDAR->TIMER_W);
246 return (uint32_t)READ_REG(CALENDAR->TIMER_R);
260 return (uint32_t)READ_REG(CALENDAR->ALARM_W);
274 return (uint32_t)READ_REG(CALENDAR->ALARM_R);
288 return (uint32_t)READ_REG(CALENDAR->TICK_R);
303 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
317 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
331 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
346 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_WRAP_CLR |
CLDR_REG_READ);
369 MODIFY_REG(CALENDAR->CFG1, RTC_CFG1_DIV, div);
383 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN |
CLDR_REG_READ);
397 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM);
411 WRITE_REG(CALENDAR->CFG0, (
CLDR_REG_READ & (~RTC_CFG0_ALARM_EN)) | RTC_CFG0_CFG);
425 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM);
439 return (uint32_t)((READ_BITS(CALENDAR->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
440 (READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
459 WRITE_REG(CALENDAR->CFG0, (RTC_CFG0_CFG | RTC_CFG0_TICK_EN | (tick_mode << RTC_CFG0_TICK_MDOE_Pos) | (
CLDR_REG_READ & (~(1 << RTC_CFG0_TICK_MDOE_Pos)))));
475 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK);
491 WRITE_REG(CALENDAR->CFG0, (
CLDR_REG_READ & (~RTC_CFG0_TICK_EN)) | RTC_CFG0_CFG);
507 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK);
521 return (uint32_t)((READ_BITS(CALENDAR->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
522 (READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
540 WRITE_REG(CALENDAR->TICK_W, counter);
541 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET |
CLDR_REG_READ);
555 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP);
569 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP);
583 return (uint32_t)(READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
605 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
621 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
640 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
654 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_ALARM);
668 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_WRAP);
685 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_TICK);
695 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);