52 #ifndef _LL_AON_WDT_H__
53 #define _LL_AON_WDT_H__
70 #define AON_WDT_REG_READ (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN | \
71 AON_WDT_CFG0_ALARM_EN))
94 MODIFY_REG(AON_WDT->CFG0, AON_WDT_CFG0_EN, (AON_WDT_CFG0_EN | AON_WDT_CFG0_CFG));
107 MODIFY_REG(AON_WDT->CFG0, AON_WDT_CFG0_EN, AON_WDT_CFG0_CFG);
121 return (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN) == (AON_WDT_CFG0_EN));
135 WRITE_REG(AON_WDT->TIMER_W, counter);
149 return (uint32_t)READ_BITS(AON_WDT->TIMER_W, AON_WDT_TIMER_W_VAL);
163 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
178 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_TIMER_SET |
AON_WDT_REG_READ);
193 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
210 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
227 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
228 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_SET |
AON_WDT_REG_READ);
244 return (uint32_t)(READ_BITS(AON_WDT->ALARM_W, AON_WDT_ALARM_W_VAL));
258 return (uint32_t)(READ_BITS(AON_WDT->ALARM_R, AON_WDT_ALARM_R_VAL));
272 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_BUSY) == (AON_WDT_STAT_BUSY));
286 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_EN |
AON_WDT_REG_READ);
300 WRITE_REG(AON_WDT->CFG0, (
AON_WDT_REG_READ & (~AON_WDT_CFG0_ALARM_EN)) | AON_WDT_CFG0_CFG);
314 return (uint32_t)(READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_ALARM_EN) == AON_WDT_CFG0_ALARM_EN);
335 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_STAT) == (AON_WDT_STAT_STAT));
351 return (uint32_t)(READ_BITS(
AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_AON_WDT) == AON_CTL_SLP_EVENT_AON_WDT);
365 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_AON_WDT);
375 WRITE_REG(AON_WDT->LOCK, 0x15CC5A51 << 1);
385 WRITE_REG(AON_WDT->LOCK, 0 << 1);