52 #ifndef LL_DUAL_TIMER_H
53 #define LL_DUAL_TIMER_H
62 #if defined (DUAL_TIMER0) || defined (DUAL_TIMER1)
118 #define LL_DUAL_TIMER_FREERUNNING_MODE 0x00000000U
119 #define LL_DUAL_TIMER_PERIODIC_MODE DUAL_TIMER_CTRL_MODE
125 #define LL_DUAL_TIMER_PRESCALER_DIV0 0x00000000U
126 #define LL_DUAL_TIMER_PRESCALER_DIV16 (1UL << DUAL_TIMER_CTRL_PRE_Pos)
127 #define LL_DUAL_TIMER_PRESCALER_DIV256 (2UL << DUAL_TIMER_CTRL_PRE_Pos)
133 #define LL_DUAL_TIMER_COUNTERSIZE_16 0x00000000U
134 #define LL_DUAL_TIMER_COUNTERSIZE_32 DUAL_TIMER_CTRL_SIZE
140 #define LL_DUAL_TIMER_IO_ACTION_NONE 0x00000000U
141 #define LL_DUAL_TIMER_IO_ACTION_SET 0x00000001U
142 #define LL_DUAL_TIMER_IO_ACTION_RESET 0x00000002U
143 #define LL_DUAL_TIMER_IO_ACTION_TOGGLE 0x00000003U
149 #define LL_DUAL_TIMER_IO_INIT_RESET 0x00000000U
150 #define LL_DUAL_TIMER_IO_INIT_SET 0x00000001U
156 #define LL_DUAL_TIMER_INTSTAT_COUNTDONE DUAL_TIMER_ISR_TI
157 #define LL_DUAL_TIMER_INTSTAT_ACT_START DUAL_TIMER_INT_ACT_START
158 #define LL_DUAL_TIMER_INTSTAT_IOA_ACT_C1 DUAL_TIMER_INT_IOA_ACT_C1
159 #define LL_DUAL_TIMER_INTSTAT_IOA_ACT_C2 DUAL_TIMER_INT_IOA_ACT_C2
160 #define LL_DUAL_TIMER_INTSTAT_ACT_PERIOD DUAL_TIMER_INT_ACT_PERIOD
161 #define LL_DUAL_TIMER_INTSTAT_ACT_STOP DUAL_TIMER_INT_ACT_STOP
162 #define LL_DUAL_TIMER_INTSTAT_IOB_ACT_C1 DUAL_TIMER_INT_IOB_ACT_C1
163 #define LL_DUAL_TIMER_INTSTAT_IOB_ACT_C2 DUAL_TIMER_INT_IOB_ACT_C2
164 #define LL_DUAL_TIMER_INTSTAT_IOC_ACT_C1 DUAL_TIMER_INT_IOC_ACT_C1
165 #define LL_DUAL_TIMER_INTSTAT_IOC_ACT_C2 DUAL_TIMER_INT_IOC_ACT_C2
166 #define LL_DUAL_TIMER_INTSTAT_BLEPULSE1 DUAL_TIMER_INT_BLEPULSE1
167 #define LL_DUAL_TIMER_INTSTAT_BLEPULSE2 DUAL_TIMER_INT_BLEPULSE2
177 #define DUAL_TIMER_DEFAULT_CONFIG \
179 .prescaler = LL_DUAL_TIMER_PRESCALER_DIV0, \
180 .counter_size = LL_DUAL_TIMER_COUNTERSIZE_32, \
181 .counter_mode = LL_DUAL_TIMER_PERIODIC_MODE, \
182 .auto_reload = SystemCoreClock - 1U, \
204 #define LL_DUAL_TIMER_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
212 #define LL_DUAL_TIMER_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
242 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_EN);
257 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_EN);
272 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_EN) == (DUAL_TIMER_CTRL_EN));
290 MODIFY_REG(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_MODE, counter_mode);
307 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_MODE));
326 MODIFY_REG(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_PRE, prescaler);
344 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_PRE));
362 MODIFY_REG(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_SIZE, counter_size);
379 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_SIZE));
394 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ONESHOT);
409 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ONESHOT);
424 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ONESHOT) == (DUAL_TIMER_CTRL_ONESHOT));
439 return (uint32_t)(READ_REG(DUAL_TIMERx->VALUE));
456 WRITE_REG(DUAL_TIMERx->RELOAD, auto_reload);
471 return (uint32_t)(READ_REG(DUAL_TIMERx->RELOAD));
487 WRITE_REG(DUAL_TIMERx->BG_LOAD, background_reload);
502 return (uint32_t)(READ_REG(DUAL_TIMERx->BG_LOAD));
517 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA);
532 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA);
547 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA) == (DUAL_TIMER_CTRL_IOA));
562 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB);
577 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB);
592 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB) == (DUAL_TIMER_CTRL_IOB));
607 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC);
622 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC);
637 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC) == (DUAL_TIMER_CTRL_IOC));
652 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLE);
667 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLE);
682 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLE) == (DUAL_TIMER_CTRL_BLE));
698 WRITE_REG(DUAL_TIMERx->COUNT_A1IO, count_value);
713 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_A1IO));
729 WRITE_REG(DUAL_TIMERx->COUNT_A2IO, count_value);
744 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_A2IO));
760 WRITE_REG(DUAL_TIMERx->COUNT_B1IO, count_value);
775 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_B1IO));
791 WRITE_REG(DUAL_TIMERx->COUNT_B2IO, count_value);
806 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_B2IO));
822 WRITE_REG(DUAL_TIMERx->COUNT_C1IO, count_value);
837 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_C1IO));
853 WRITE_REG(DUAL_TIMERx->COUNT_C2IO, count_value);
868 return (uint32_t)(READ_REG(DUAL_TIMERx->COUNT_C2IO));
888 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_START, (action << DUAL_TIMER_IOA_ACT_CTRL_START_Pos));
907 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_START) >> DUAL_TIMER_IOA_ACT_CTRL_START_Pos));
927 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_C1, (action << DUAL_TIMER_IOA_ACT_CTRL_C1_Pos));
946 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_C1) >> DUAL_TIMER_IOA_ACT_CTRL_C1_Pos));
966 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_C2, (action << DUAL_TIMER_IOA_ACT_CTRL_C2_Pos));
985 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_C2) >> DUAL_TIMER_IOA_ACT_CTRL_C2_Pos));
1005 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_PERIOD, (action << DUAL_TIMER_IOA_ACT_CTRL_PERIOD_Pos));
1024 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_PERIOD) >> DUAL_TIMER_IOA_ACT_CTRL_PERIOD_Pos));
1044 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_STOP, (action << DUAL_TIMER_IOA_ACT_CTRL_STOP_Pos));
1063 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOA_ACT_CTRL_STOP) >> DUAL_TIMER_IOA_ACT_CTRL_STOP_Pos));
1083 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_START, (action << DUAL_TIMER_IOB_ACT_CTRL_START_Pos));
1102 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_START) >> DUAL_TIMER_IOB_ACT_CTRL_START_Pos));
1122 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_C1, (action << DUAL_TIMER_IOB_ACT_CTRL_C1_Pos));
1141 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_C1) >> DUAL_TIMER_IOB_ACT_CTRL_C1_Pos));
1161 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_C2, (action << DUAL_TIMER_IOB_ACT_CTRL_C2_Pos));
1180 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_C2) >> DUAL_TIMER_IOB_ACT_CTRL_C2_Pos));
1200 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_PERIOD, (action << DUAL_TIMER_IOB_ACT_CTRL_PERIOD_Pos));
1219 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_PERIOD) >> DUAL_TIMER_IOB_ACT_CTRL_PERIOD_Pos));
1239 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_STOP, (action << DUAL_TIMER_IOB_ACT_CTRL_STOP_Pos));
1258 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOB_ACT_CTRL_STOP) >> DUAL_TIMER_IOB_ACT_CTRL_STOP_Pos));
1278 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_START, (action << DUAL_TIMER_IOC_ACT_CTRL_START_Pos));
1297 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_START) >> DUAL_TIMER_IOC_ACT_CTRL_START_Pos));
1317 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_C1, (action << DUAL_TIMER_IOC_ACT_CTRL_C1_Pos));
1336 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_C1) >> DUAL_TIMER_IOC_ACT_CTRL_C1_Pos));
1356 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_C2, (action << DUAL_TIMER_IOC_ACT_CTRL_C2_Pos));
1375 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_C2) >> DUAL_TIMER_IOC_ACT_CTRL_C2_Pos));
1395 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_PERIOD, (action << DUAL_TIMER_IOC_ACT_CTRL_PERIOD_Pos));
1414 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_PERIOD) >> DUAL_TIMER_IOC_ACT_CTRL_PERIOD_Pos));
1434 MODIFY_REG(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_STOP, (action << DUAL_TIMER_IOC_ACT_CTRL_STOP_Pos));
1453 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_ACT_CTRL, DUAL_TIMER_IOC_ACT_CTRL_STOP) >> DUAL_TIMER_IOC_ACT_CTRL_STOP_Pos));
1471 MODIFY_REG(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOA_ACT_INIT, (value << DUAL_TIMER_IOA_ACT_INIT_Pos));
1488 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOA_ACT_INIT) >> DUAL_TIMER_IOA_ACT_INIT_Pos));
1506 MODIFY_REG(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOB_ACT_INIT, (value << DUAL_TIMER_IOB_ACT_INIT_Pos));
1523 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOB_ACT_INIT) >> DUAL_TIMER_IOB_ACT_INIT_Pos));
1541 MODIFY_REG(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOC_ACT_INIT, (value << DUAL_TIMER_IOC_ACT_INIT_Pos));
1558 return (uint32_t)((READ_BITS(DUAL_TIMERx->IO_INIT_SET, DUAL_TIMER_IOC_ACT_INIT) >> DUAL_TIMER_IOC_ACT_INIT_Pos));
1574 WRITE_REG(DUAL_TIMERx->TP_LOAD, onetime_reload);
1589 return (uint32_t)(READ_REG(DUAL_TIMERx->TP_LOAD));
1605 WRITE_REG(DUAL_TIMERx->BLE_COUNT1, count_value);
1620 return (uint32_t)(READ_REG(DUAL_TIMERx->BLE_COUNT1));
1636 WRITE_REG(DUAL_TIMERx->BLE_COUNT2, count_value);
1651 return (uint32_t)(READ_REG(DUAL_TIMERx->BLE_COUNT2));
1667 MODIFY_REG(DUAL_TIMERx->BLE_PULSEWIDTH, DUAL_TIMER_BLE_PULSEWIDTH, (width << DUAL_TIMER_BLE_PULSEWIDTH_Pos));
1682 return (uint32_t)((READ_BITS(DUAL_TIMERx->BLE_PULSEWIDTH, DUAL_TIMER_BLE_PULSEWIDTH) >> DUAL_TIMER_BLE_PULSEWIDTH_Pos));
1698 WRITE_REG(DUAL_TIMERx->PERIOD_COUNT, count);
1713 return (uint32_t)(READ_REG(DUAL_TIMERx->PERIOD_COUNT));
1733 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_INTEN);
1748 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_INTEN);
1763 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_INTEN) == (DUAL_TIMER_CTRL_INTEN));
1778 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_START_INTEN);
1793 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_START_INTEN);
1808 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_START_INTEN) == (DUAL_TIMER_CTRL_ACT_START_INTEN));
1823 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C1_INTEN);
1838 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C1_INTEN);
1853 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C1_INTEN) == (DUAL_TIMER_CTRL_IOA_ACT_C1_INTEN));
1868 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C2_INTEN);
1883 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C2_INTEN);
1898 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOA_ACT_C2_INTEN) == (DUAL_TIMER_CTRL_IOA_ACT_C2_INTEN));
1913 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_PERIOD_INTEN);
1928 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_PERIOD_INTEN);
1943 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_PERIOD_INTEN) == (DUAL_TIMER_CTRL_ACT_PERIOD_INTEN));
1958 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_STOP_INTEN);
1973 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_STOP_INTEN);
1988 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_ACT_STOP_INTEN) == (DUAL_TIMER_CTRL_ACT_STOP_INTEN));
2003 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C1_INTEN);
2018 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C1_INTEN);
2033 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C1_INTEN) == (DUAL_TIMER_CTRL_IOB_ACT_C1_INTEN));
2048 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C2_INTEN);
2063 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C2_INTEN);
2078 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOB_ACT_C2_INTEN) == (DUAL_TIMER_CTRL_IOB_ACT_C2_INTEN));
2093 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C1_INTEN);
2108 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C1_INTEN);
2123 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C1_INTEN) == (DUAL_TIMER_CTRL_IOC_ACT_C1_INTEN));
2138 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C2_INTEN);
2153 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C2_INTEN);
2168 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_IOC_ACT_C2_INTEN) == (DUAL_TIMER_CTRL_IOC_ACT_C2_INTEN));
2183 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE1_INTEN);
2198 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE1_INTEN);
2213 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE1_INTEN) == (DUAL_TIMER_CTRL_BLEPULSE1_INTEN));
2228 SET_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE2_INTEN);
2243 CLEAR_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE2_INTEN);
2258 return (READ_BITS(DUAL_TIMERx->CTRL, DUAL_TIMER_CTRL_BLEPULSE2_INTEN) == (DUAL_TIMER_CTRL_BLEPULSE2_INTEN));
2279 WRITE_REG(DUAL_TIMERx->INTCLR, DUAL_TIMER_INT_CLR);
2294 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_ISR_TI) == (DUAL_TIMER_ISR_TI));
2309 return (READ_REG(DUAL_TIMERx->RAW_INTSTAT));
2324 return (uint32_t )(READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_STAT));
2339 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_ACT_START) == (DUAL_TIMER_INT_ACT_START));
2354 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOA_ACT_C1) == (DUAL_TIMER_INT_IOA_ACT_C1));
2369 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOA_ACT_C2) == (DUAL_TIMER_INT_IOA_ACT_C2));
2384 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_ACT_PERIOD) == (DUAL_TIMER_INT_ACT_PERIOD));
2399 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_ACT_STOP) == (DUAL_TIMER_INT_ACT_STOP));
2414 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOB_ACT_C1) == (DUAL_TIMER_INT_IOB_ACT_C1));
2429 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOB_ACT_C2) == (DUAL_TIMER_INT_IOB_ACT_C2));
2444 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOC_ACT_C1) == (DUAL_TIMER_INT_IOC_ACT_C1));
2459 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_IOC_ACT_C2) == (DUAL_TIMER_INT_IOC_ACT_C2));
2474 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_BLEPULSE1) == (DUAL_TIMER_INT_BLEPULSE1));
2489 return (READ_BITS(DUAL_TIMERx->INTSTAT, DUAL_TIMER_INT_BLEPULSE2) == (DUAL_TIMER_INT_BLEPULSE2));
2504 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_ACT_START_INTCLR);
2519 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOA_ACT_C1_INTCLR);
2534 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOA_ACT_C2_INTCLR);
2549 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_ACT_PERIOD_INTCLR);
2564 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_ACT_STOP_INTCLR);
2579 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOB_ACT_C1_INTCLR);
2594 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOB_ACT_C2_INTCLR);
2609 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOC_ACT_C1_INTCLR);
2624 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IOC_ACT_C2_INTCLR);
2639 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_BLEPULSE1_INTCLR);
2654 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_BLEPULSE2_INTCLR);
2669 WRITE_REG(DUAL_TIMERx->IO_BLE_INTCLR, DUAL_TIMER_IO_ACT_ALL_INTCLR);