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52 #ifndef ___HAL_XQSPI_H__
53 #define ___HAL_XQSPI_H__
241 #define HAL_XQSPI_ERROR_NONE ((uint32_t)0x00000000)
242 #define HAL_XQSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
243 #define HAL_XQSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
244 #define HAL_XQSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
250 #define XQSPI_HP_MODE_DIS LL_XQSPI_HP_MODE_DIS
251 #define XQSPI_HP_MODE_EN LL_XQSPI_HP_MODE_EN
257 #define XQSPI_WORK_MODE_QSPI LL_XQSPI_MODE_QSPI
258 #define XQSPI_WORK_MODE_XIP LL_XQSPI_MODE_XIP
264 #define XQSPI_CACHE_MODE_DIS LL_XQSPI_CACHE_DIS
265 #define XQSPI_CACHE_MODE_EN LL_XQSPI_CACHE_EN
271 #define XQSPI_CACHE_DIRECT_MAP_DIS LL_XQSPI_CACHE_DIRECT_MAP_DIS
272 #define XQSPI_CACHE_DIRECT_MAP_EN LL_XQSPI_CACHE_DIRECT_MAP_EN
278 #define XQSPI_CACHE_FLUSH_DIS LL_XQSPI_CACHE_FLUSH_DIS
279 #define XQSPI_CACHE_FLUSH_EN LL_XQSPI_CACHE_FLUSH_EN
285 #define XQSPI_READ_CMD_READ LL_XQSPI_XIP_CMD_READ
286 #define XQSPI_READ_CMD_FAST_READ LL_XQSPI_XIP_CMD_FAST_READ
287 #define XQSPI_READ_CMD_DUAL_OUT_READ LL_XQSPI_XIP_CMD_DUAL_OUT_READ
288 #define XQSPI_READ_CMD_DUAL_IO_READ LL_XQSPI_XIP_CMD_DUAL_IO_READ
289 #define XQSPI_READ_CMD_QUAD_OUT_READ LL_XQSPI_XIP_CMD_QUAD_OUT_READ
290 #define XQSPI_READ_CMD_QUAD_IO_READ LL_XQSPI_XIP_CMD_QUAD_IO_READ
296 #define XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE)
298 #define XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE)
300 #define XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE)
302 #define XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE)
309 #define XQSPI_BAUD_RATE_64M LL_XQSPI_BAUD_RATE_64M
310 #define XQSPI_BAUD_RATE_48M LL_XQSPI_BAUD_RATE_48M
311 #define XQSPI_BAUD_RATE_32M LL_XQSPI_BAUD_RATE_32M
312 #define XQSPI_BAUD_RATE_24M LL_XQSPI_BAUD_RATE_24M
313 #define XQSPI_BAUD_RATE_16M LL_XQSPI_BAUD_RATE_16M
319 #define XQSPI_DATA_MODE_SPI LL_XQSPI_QSPI_FRF_SPI
320 #define XQSPI_DATA_MODE_DUALSPI LL_XQSPI_QSPI_FRF_DUALSPI
321 #define XQSPI_DATA_MODE_QUADSPI LL_XQSPI_QSPI_FRF_QUADSPI
327 #define XQSPI_FIFO_THRESHOLD_1_8 LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
328 #define XQSPI_FIFO_THRESHOLD_1_4 LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
329 #define XQSPI_FIFO_THRESHOLD_1_2 LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
330 #define XQSPI_FIFO_THRESHOLD_3_4 LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
331 #define XQSPI_FIFO_DEPTH LL_XQSPI_QSPI_FIFO_DEPTH
337 #define XQSPI_INSTSIZE_00_BITS (0)
338 #define XQSPI_INSTSIZE_08_BITS (1)
339 #define XQSPI_INSTSIZE_16_BITS (2)
345 #define XQSPI_ADDRSIZE_00_BITS (0)
346 #define XQSPI_ADDRSIZE_08_BITS (1)
347 #define XQSPI_ADDRSIZE_16_BITS (2)
348 #define XQSPI_ADDRSIZE_24_BITS (3)
349 #define XQSPI_ADDRSIZE_32_BITS (4)
355 #define XQSPI_INST_ADDR_ALL_IN_SPI (0)
356 #define XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1)
357 #define XQSPI_INST_ADDR_ALL_IN_SPIFRF (2)
363 #define XQSPI_FLAG_RFF LL_XQSPI_QSPI_STAT_RFF
364 #define XQSPI_FLAG_RFTF LL_XQSPI_QSPI_STAT_RFTF
365 #define XQSPI_FLAG_RFE LL_XQSPI_QSPI_STAT_RFE
366 #define XQSPI_FLAG_TFF LL_XQSPI_QSPI_STAT_TFF
367 #define XQSPI_FLAG_TFTF LL_XQSPI_QSPI_STAT_TFTF
368 #define XQSPI_FLAG_TFE LL_XQSPI_QSPI_STAT_TFE
369 #define XQSPI_FLAG_BUSY LL_XQSPI_QSPI_STAT_BUSY
375 #define XQSPI_DISABLE_PRESENT LL_XQSPI_DISABLE_PRESENT
376 #define XQSPI_ENABLE_PRESENT LL_XQSPI_ENABLE_PRESENT
382 #define HAL_XQSPI_RETRY_DEFAULT_VALUE ((uint32_t)1000)
395 #define __HAL_XQSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_XQSPI_STATE_RESET)
401 #define __HAL_XQSPI_ENABLE_QSPI(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, XQSPI_QSPI_EN_EN)
407 #define __HAL_XQSPI_DISABLE_QSPI(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, XQSPI_QSPI_EN_EN)
414 #define __HAL_XQSPI_ENABLE_XIP(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->XIP.CTRL3, XQSPI_QSPI_EN_EN);\
415 while(!ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
422 #define __HAL_XQSPI_DISABLE_XIP(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->XIP.CTRL3, XQSPI_QSPI_EN_EN);\
423 while(ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
429 #define __HAL_XQSPI_ENABLE_CACHE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
435 #define __HAL_XQSPI_DISABLE_CACHE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
450 #define __HAL_XQSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->QSPI.STAT, (__FLAG__)) != 0) ? SET : RESET)
463 #define IS_XQSPI_WORK_MODE(__MODE__) (((__MODE__) == XQSPI_WORK_MODE_QSPI) || \
464 ((__MODE__) == XQSPI_WORK_MODE_XIP))
470 #define IS_XQSPI_CACHE_MODE(__MODE__) (((__MODE__) == XQSPI_CACHE_MODE_DIS) || \
471 ((__MODE__) == XQSPI_CACHE_MODE_EN))
477 #define IS_XQSPI_CACHE_MAPPING(__MODE__) (((__MODE__) == XQSPI_CACHE_DIRECT_MAP_DIS) || \
478 ((__MODE__) == XQSPI_CACHE_DIRECT_MAP_EN))
484 #define IS_XQSPI_CACHE_FLUSH(__MODE__) (((__MODE__) == XQSPI_CACHE_FLUSH_DIS) || \
485 ((__MODE__) == XQSPI_CACHE_FLUSH_EN))
491 #define IS_XQSPI_READ_CMD(__CMD__) (((__CMD__) == XQSPI_READ_CMD_READ ) || \
492 ((__CMD__) == XQSPI_READ_CMD_FAST_READ ) || \
493 ((__CMD__) == XQSPI_READ_CMD_DUAL_OUT_READ) || \
494 ((__CMD__) == XQSPI_READ_CMD_DUAL_IO_READ ) || \
495 ((__CMD__) == XQSPI_READ_CMD_QUAD_OUT_READ) || \
496 ((__CMD__) == XQSPI_READ_CMD_QUAD_IO_READ ))
502 #define IS_XQSPI_BAUD_RATE(__BAUD__) (((__BAUD__) == XQSPI_BAUD_RATE_64M) || \
503 ((__BAUD__) == XQSPI_BAUD_RATE_48M) || \
504 ((__BAUD__) == XQSPI_BAUD_RATE_32M) || \
505 ((__BAUD__) == XQSPI_BAUD_RATE_24M) || \
506 ((__BAUD__) == XQSPI_BAUD_RATE_16M))
512 #define IS_XQSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == XQSPI_CLOCK_MODE_0) || \
513 ((__CLKMODE__) == XQSPI_CLOCK_MODE_1) || \
514 ((__CLKMODE__) == XQSPI_CLOCK_MODE_2) || \
515 ((__CLKMODE__) == XQSPI_CLOCK_MODE_3))
521 #define IS_XQSPI_FIFO_THRESHOLD(__THR__) (((__THR__) == XQSPI_FIFO_THRESHOLD_1_8) || \
522 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_4) || \
523 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_2) || \
524 ((__THR__) == XQSPI_FIFO_THRESHOLD_3_4))
530 #define IS_XQSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == XQSPI_INSTSIZE_00_BITS) || \
531 ((__INST_SIZE__) == XQSPI_INSTSIZE_08_BITS) || \
532 ((__INST_SIZE__) == XQSPI_INSTSIZE_16_BITS))
538 #define IS_XQSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == XQSPI_ADDRSIZE_00_BITS) || \
539 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_08_BITS) || \
540 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_16_BITS) || \
541 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_24_BITS) || \
542 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_32_BITS))
548 #define IS_XQSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPI) || \
549 ((__MODE__) == XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
550 ((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPIFRF))
556 #define IS_XQSPI_DATA_MODE(__MODE__) (((__MODE__) == XQSPI_DATA_MODE_SPI) || \
557 ((__MODE__) == XQSPI_DATA_MODE_DUALSPI) || \
558 ((__MODE__) == XQSPI_DATA_MODE_QUADSPI))
__IO uint32_t tx_xfer_count
void(* xqspi_msp_init)(xqspi_handle_t *p_xqspi)
void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI MSP.
Header file containing functions prototypes of XQSPI LL library.
hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI peripheral.
@ HAL_XQSPI_STATE_BUSY_INDIRECT_TX
hal_lock_t
HAL Lock Enumerations definition.
uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the RXFIFO threshold.
hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Receive an amount of data in blocking mode.
hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi)
Return the XQSPI handle state.
uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi)
Return the XQSPI error code.
XQSPI command Structure definition.
hal_xqspi_state_t
HAL XQSPI State Enumerations definition.
XQSPI High Performance mode init structures definition.
__IO uint32_t rx_xfer_count
HAL_XQSPI Callback function definition.
struct _xqspi_handle_t xqspi_handle_t
XQSPI handle Structure definition.
void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry)
Set the XQSPI internal process repeat times value.
struct _xqspi_command_t xqspi_command_t
XQSPI command Structure definition.
XQSPI handle Structure definition.
hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the RXFIFO threshold.
uint32_t cache_direct_map_en
xqspi_regs_t * p_instance
hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Transmit an amount of data in blocking mode.
void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI MSP.
hal_status_t
HAL Status structures definition.
hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Transmit an amount of data with specified instruction and address in blocking mode.
XQSPI init Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
__IO uint32_t rx_xfer_size
@ HAL_XQSPI_STATE_BUSY_INDIRECT_RX
hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI according to the specified parameters in the xqspi_init_t and initialize the ass...
uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the TXFIFO threshold.
ll_xqspi_hp_init_t hp_init
struct _hal_xqspi_callback hal_xqspi_callback_t
HAL_XQSPI Callback function definition.
__IO hal_xqspi_state_t state
hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Receive an amount of data with specified instruction and address in blocking mode.
struct _xqspi_init_t xqspi_init_t
XQSPI init Structure definition.
__IO uint32_t tx_xfer_size
hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the TXFIFO threshold.
void(* xqspi_msp_deinit)(xqspi_handle_t *p_xqspi)