Macros | |
#define | CGC_FRC_SECU_HCLK ((uint32_t)0x00000001U) |
#define | CGC_FRC_SIM_HCLK ((uint32_t)0x00000002U) |
#define | CGC_FRC_HTB_HCLK ((uint32_t)0x00000004U) |
#define | CGC_FRC_PWM_HCLK ((uint32_t)0x00000008U) |
#define | CGC_FRC_ROM_HCLK ((uint32_t)0x00000010U) |
#define | CGC_FRC_SNSADC_HCLK ((uint32_t)0x00000020U) |
#define | CGC_FRC_GPIO_HCLK ((uint32_t)0x00000040U) |
#define | CGC_FRC_DMA_HCLK ((uint32_t)0x00000080U) |
#define | CGC_FRC_BLE_BRG_HCLK ((uint32_t)0x00000100U) |
#define | CGC_FRC_APB_SUB_HCLK ((uint32_t)0x00000200U) |
#define | CGC_FRC_SERIAL_HCLK ((uint32_t)0x00000400U) |
#define | CGC_FRC_I2S_S_HCLK ((uint32_t)0x00000800U) |
#define | CGC_FRC_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) |
#define | CGC_FRC_XF_XQSPI_HCLK ((uint32_t)0x00002000U) |
#define | CGC_FRC_SRAM_HCLK ((uint32_t)0x00004000U) |
#define | CGC_FRC_UART0_HCLK ((uint32_t)0x00008000U) |
#define | CGC_FRC_UART1_HCLK ((uint32_t)0x00010000U) |
#define | CGC_FRC_I2C0_HCLK ((uint32_t)0x00020000U) |
#define | CGC_FRC_I2C1_HCLK ((uint32_t)0x00040000U) |
#define | CGC_FRC_SPIM_HCLK ((uint32_t)0x00080000U) |
#define | CGC_FRC_SPIS_HCLK ((uint32_t)0x00100000U) |
#define | CGC_FRC_QSPI0_HCLK ((uint32_t)0x00200000U) |
#define | CGC_FRC_QSPI1_HCLK ((uint32_t)0x00400000U) |
#define | CGC_FRC_I2S_HCLK ((uint32_t)0x00800000U) |
#define | CGC_FRC_SECU_DIV4_PCLK ((uint32_t)0x01000000U) |
#define | CGC_FRC_XQSPI_DIV4_PCLK ((uint32_t)0x04000000U) |
#define | CGC_FRC_ALL_CLK ((uint32_t)0x05FFFFFFU) |
#define CGC_FRC_ALL_CLK ((uint32_t)0x05FFFFFFU) |
#define CGC_FRC_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) |
#define CGC_FRC_APB_SUB_HCLK ((uint32_t)0x00000200U) |
#define CGC_FRC_BLE_BRG_HCLK ((uint32_t)0x00000100U) |
#define CGC_FRC_DMA_HCLK ((uint32_t)0x00000080U) |
#define CGC_FRC_GPIO_HCLK ((uint32_t)0x00000040U) |
#define CGC_FRC_HTB_HCLK ((uint32_t)0x00000004U) |
#define CGC_FRC_I2C0_HCLK ((uint32_t)0x00020000U) |
#define CGC_FRC_I2C1_HCLK ((uint32_t)0x00040000U) |
#define CGC_FRC_I2S_HCLK ((uint32_t)0x00800000U) |
#define CGC_FRC_I2S_S_HCLK ((uint32_t)0x00000800U) |
#define CGC_FRC_PWM_HCLK ((uint32_t)0x00000008U) |
#define CGC_FRC_QSPI0_HCLK ((uint32_t)0x00200000U) |
#define CGC_FRC_QSPI1_HCLK ((uint32_t)0x00400000U) |
#define CGC_FRC_ROM_HCLK ((uint32_t)0x00000010U) |
#define CGC_FRC_SECU_DIV4_PCLK ((uint32_t)0x01000000U) |
#define CGC_FRC_SECU_HCLK ((uint32_t)0x00000001U) |
#define CGC_FRC_SERIAL_HCLK ((uint32_t)0x00000400U) |
#define CGC_FRC_SIM_HCLK ((uint32_t)0x00000002U) |
#define CGC_FRC_SNSADC_HCLK ((uint32_t)0x00000020U) |
#define CGC_FRC_SPIM_HCLK ((uint32_t)0x00080000U) |
#define CGC_FRC_SPIS_HCLK ((uint32_t)0x00100000U) |
#define CGC_FRC_SRAM_HCLK ((uint32_t)0x00004000U) |
#define CGC_FRC_UART0_HCLK ((uint32_t)0x00008000U) |
#define CGC_FRC_UART1_HCLK ((uint32_t)0x00010000U) |
#define CGC_FRC_XF_XQSPI_HCLK ((uint32_t)0x00002000U) |