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234 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
235 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
236 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U)
237 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
238 #define HAL_DMA_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
245 #define DMA0_REQUEST_CTE LL_DMA0_PERIPH_CTE
246 #define DMA0_REQUEST_PWM0 LL_DMA0_PERIPH_PWM0
247 #define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX
248 #define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX
249 #define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX
250 #define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX
251 #define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX
252 #define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX
253 #define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX
254 #define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX
255 #define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC
256 #define DMA0_REQUEST_I2C0_TX LL_DMA0_PERIPH_I2C0_TX
257 #define DMA0_REQUEST_I2C0_RX LL_DMA0_PERIPH_I2C0_RX
258 #define DMA0_REQUEST_I2C1_TX LL_DMA0_PERIPH_I2C1_TX
259 #define DMA0_REQUEST_I2C1_RX LL_DMA0_PERIPH_I2C1_RX
260 #define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM
267 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
268 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
269 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
270 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH
276 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT
277 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT
278 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE
284 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT
285 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT
286 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE
292 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE
293 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD
294 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD
300 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE
301 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD
302 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD
310 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0
311 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_1
312 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_2
313 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_3
319 #define DMA_HAL_CHANNEL_LOCK_ENABLE LL_DMA_LOCK_CH_ENABLE
320 #define DMA_HAL_CHANNEL_LOCK_DISABLE LL_DMA_LOCK_CH_DISABLE
326 #define DMA_HAL_CHANNEL_LOCK_TFR LL_DMA_LOCK_CH_LEVEL_TFR
327 #define DMA_HAL_CHANNEL_LOCK_BLK LL_DMA_LOCK_CH_LEVEL_BLK
328 #define DMA_HAL_CHANNEL_LOCK_TRANS LL_DMA_LOCK_CH_LEVEL_TRANS
334 #define DMA_HAL_BUS_LOCK_ENABLE LL_DMA_LOCK_BUS_ENABLE
335 #define DMA_HAL_BUS_LOCK_DISABLE LL_DMA_LOCK_BUS_DISABLE
341 #define DMA_HAL_BUS_LOCK_TFR LL_DMA_LOCK_BUS_LEVEL_TFR
342 #define DMA_HAL_BUS_LOCK_BLK LL_DMA_LOCK_BUS_LEVEL_BLK
343 #define DMA_HAL_BUS_LOCK_TRANS LL_DMA_LOCK_BUS_LEVEL_TRANS
356 #define IS_DMA_ALL_P_INSTANCE(__p_instance__) (((__p_instance__) == DMA0))
363 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
364 ((__instance__) == DMA_Channel1) || \
365 ((__instance__) == DMA_Channel2) || \
366 ((__instance__) == DMA_Channel3) || \
367 ((__instance__) == DMA_Channel4))
376 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA0_REQUEST_SPIM_TX) || \
377 ((__REQUEST__) == DMA0_REQUEST_SPIM_RX) || \
378 ((__REQUEST__) == DMA0_REQUEST_SPIS_TX) || \
379 ((__REQUEST__) == DMA0_REQUEST_SPIS_RX) || \
380 ((__REQUEST__) == DMA0_REQUEST_UART0_TX) || \
381 ((__REQUEST__) == DMA0_REQUEST_UART0_RX) || \
382 ((__REQUEST__) == DMA0_REQUEST_UART1_TX) || \
383 ((__REQUEST__) == DMA0_REQUEST_UART1_RX) || \
384 ((__REQUEST__) == DMA0_REQUEST_SNSADC) || \
385 ((__REQUEST__) == DMA0_REQUEST_MEM) || \
386 ((__REQUEST__) == DMA0_REQUEST_I2C0_TX) || \
387 ((__REQUEST__) == DMA0_REQUEST_I2C0_RX) || \
388 ((__REQUEST__) == DMA0_REQUEST_I2C1_TX) || \
389 ((__REQUEST__) == DMA0_REQUEST_I2C1_RX))
395 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
396 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
397 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
398 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
404 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) <= 0xFFF))
410 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
411 ((__STATE__) == DMA_SRC_DECREMENT) || \
412 ((__STATE__) == DMA_SRC_NO_CHANGE))
418 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
419 ((__STATE__) == DMA_DST_DECREMENT) || \
420 ((__STATE__) == DMA_DST_NO_CHANGE))
426 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
427 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
428 ((__SIZE__) == DMA_SDATAALIGN_WORD))
434 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
435 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
436 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
442 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
443 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
444 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
445 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
void hal_pm_dma_resume(dma_handle_t *p_dma)
Resume the register of the specified DMA channel.
DMA Configuration Structure definition.
struct _dma_init dma_init_t
DMA Configuration Structure definition.
This file contains all the functions prototypes for the HAL module driver.
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
HAL DMA State Enumerations definition.
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Enabled.
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
hal_status_t hal_dma_start_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer whit channel lock and bus lock.
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
void hal_dma_suspend_channel(dma_handle_t *p_dma, uint32_t channel)
Suspend the register of the specified DMA channel.
hal_pm_status_t hal_pm_dma_suspend(dma_handle_t *p_dma)
Suspend the register of the specified DMA channel.
Header file containing functions prototypes of DMA LL library.
void hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
@ HAL_DMA_XFER_ABORT_CB_ID
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
__IO hal_dma_state_t state
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
void(* xfer_error_callback)(struct _dma_handle *p_dma)
hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Diabled.
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
hal_status_t
HAL Status structures definition.
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
This file contains HAL common definitions, enumeration, macros and structures definitions.
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
uint32_t channel_lock_level
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
uint32_t dst_data_alignment
struct _dma_lock_config dma_lock_config
DMA LOCK Structure definition.
void hal_dma_resume_channel(dma_handle_t *p_dma, uint32_t channel)
Resume the register of the specified DMA channel.
DMA LOCK Structure definition.
void hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep. This function must be used in conjun...
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
@ HAL_DMA_XFER_ERROR_CB_ID
uint32_t src_data_alignment
DMA handle Structure definition.
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
HAL DMA Channel Enumerations definition.
hal_status_t hal_dma_start_it_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer with interrupt enabled、channel lock and bus lock.