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62 #if defined (I2C0) || defined (I2C1)
109 #define LL_I2C_INTR_STAT_SCL_STUCK_AT_LOW I2C_RAW_INT_STAT_SCL_STUCKLOW
110 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_RAW_INT_STAT_M_HOLD
111 #define LL_I2C_INTR_STAT_RESTART_DET I2C_RAW_INT_STAT_RESTART_DET
112 #define LL_I2C_INTR_STAT_GEN_CALL I2C_RAW_INT_STAT_GEN_CALL
113 #define LL_I2C_INTR_STAT_START_DET I2C_RAW_INT_STAT_START_DET
114 #define LL_I2C_INTR_STAT_STOP_DET I2C_RAW_INT_STAT_STOP_DET
115 #define LL_I2C_INTR_STAT_ACTIVITY I2C_RAW_INT_STAT_ACTIVITY
116 #define LL_I2C_INTR_STAT_RX_DONE I2C_RAW_INT_STAT_RX_DONE
117 #define LL_I2C_INTR_STAT_TX_ABRT I2C_RAW_INT_STAT_TX_ABORT
118 #define LL_I2C_INTR_STAT_RD_REQ I2C_RAW_INT_STAT_RD_REQ
119 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_RAW_INT_STAT_TX_EMPTY
120 #define LL_I2C_INTR_STAT_TX_OVER I2C_RAW_INT_STAT_TX_OVER
121 #define LL_I2C_INTR_STAT_RX_FULL I2C_RAW_INT_STAT_RX_FULL
122 #define LL_I2C_INTR_STAT_RX_OVER I2C_RAW_INT_STAT_RX_OVER
123 #define LL_I2C_INTR_STAT_RX_UNDER I2C_RAW_INT_STAT_RX_UNDER
125 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABORT_SRC_TX_FLUSH_CNT
126 #define LL_I2C_ABRT_SDA_STUCK_AT_LOW I2C_TX_ABORT_SRC_ABORT_SDA_STUCK
127 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABORT_SRC_ABORT_USER_ABORT
128 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABORT_SRC_ABORT_SLVRD_INTX
129 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABORT_SRC_ABORT_S_ARBLOST
130 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABORT_SRC_ABORT_SLVFLUSH_TXFIFO
131 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABORT_SRC_ABORT_LOST
132 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABORT_SRC_ABORT_MASTER_DIS
133 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABORT_SRC_ABORT_10B_RD_NORSTR
134 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABORT_SRC_ABORT_SBYTE_NORSTRT
135 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABORT_SRC_ABORT_HS_NORSTRT
136 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABORT_SRC_ABORT_SBYTE_ACKDET
137 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABORT_SRC_ABORT_HS_ACKDET
138 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABORT_SRC_ABORT_GCALL_RD
139 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABORT_SRC_ABORT_GCALL_NOACK
140 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABORT_SRC_ABORT_TX_NOACK
141 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABORT_SRC_ABORT_10B2_NOACK
142 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABORT_SRC_ABORT_10B1_NOACK
143 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABORT_SRC_ABORT_7B_NOACK
150 #define LL_I2C_INTR_MASK_SCL_STUCK_AT_LOW I2C_INT_MASK_MASK_SCL_STUCKLOW
151 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INT_MASK_MASK_M_HOLD
152 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INT_MASK_MASK_RESTART_DET
153 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INT_MASK_MASK_GEN_CALL
154 #define LL_I2C_INTR_MASK_START_DET I2C_INT_MASK_MASK_START_DET
155 #define LL_I2C_INTR_MASK_STOP_DET I2C_INT_MASK_MASK_STOP_DET
156 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INT_MASK_MASK_ACTIVITY
157 #define LL_I2C_INTR_MASK_RX_DONE I2C_INT_MASK_MASK_RX_DONE
158 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INT_MASK_MASK_TX_ABORT
159 #define LL_I2C_INTR_MASK_RD_REQ I2C_INT_MASK_MASK_RD_REQ
160 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INT_MASK_MASK_TX_EMPTY
161 #define LL_I2C_INTR_MASK_TX_OVER I2C_INT_MASK_MASK_TX_OVER
162 #define LL_I2C_INTR_MASK_RX_FULL I2C_INT_MASK_MASK_RX_FULL
163 #define LL_I2C_INTR_MASK_RX_OVER I2C_INT_MASK_MASK_RX_OVER
164 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INT_MASK_MASK_RX_UNDER
166 #define LL_I2C_INTR_MASK_ALL 0x00007FFFU
172 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
173 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CTRL_ADDR_BIT_M
179 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U
180 #define LL_I2C_OWNADDRESS_10BIT I2C_CTRL_ADDR_BIT_S
187 #define LL_I2C_CMD_SLV_NONE 0x00000000U
188 #define LL_I2C_CMD_MST_WRITE 0x00000000U
189 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD
190 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP
191 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART
197 #define LL_I2C_SPEED_MODE_STANDARD (0x1UL << I2C_CTRL_SPEED_POS)
198 #define LL_I2C_SPEED_MODE_FAST (0x2UL << I2C_CTRL_SPEED_POS)
199 #define LL_I2C_SPEED_MODE_HIGH (0x3UL << I2C_CTRL_SPEED_POS)
205 #define LL_I2C_SPEED_100K (100000U)
206 #define LL_I2C_SPEED_400K (400000U)
207 #define LL_I2C_SPEED_1000K (1000000U)
208 #define LL_I2C_SPEED_2000K (2000000U)
214 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U
215 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U
216 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U
217 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U
218 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U
219 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U
220 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U
221 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U
222 #define LL_I2C_TX_FIFO_TH_CHAR_8 0x00000008U
223 #define LL_I2C_TX_FIFO_TH_CHAR_9 0x00000009U
224 #define LL_I2C_TX_FIFO_TH_CHAR_10 0x0000000AU
225 #define LL_I2C_TX_FIFO_TH_CHAR_11 0x0000000BU
226 #define LL_I2C_TX_FIFO_TH_CHAR_12 0x0000000CU
227 #define LL_I2C_TX_FIFO_TH_CHAR_13 0x0000000DU
228 #define LL_I2C_TX_FIFO_TH_CHAR_14 0x0000000EU
229 #define LL_I2C_TX_FIFO_TH_CHAR_15 0x0000000FU
230 #define LL_I2C_TX_FIFO_TH_CHAR_16 0x00000010U
231 #define LL_I2C_TX_FIFO_TH_CHAR_17 0x00000011U
232 #define LL_I2C_TX_FIFO_TH_CHAR_18 0x00000012U
233 #define LL_I2C_TX_FIFO_TH_CHAR_19 0x00000013U
234 #define LL_I2C_TX_FIFO_TH_CHAR_20 0x00000014U
235 #define LL_I2C_TX_FIFO_TH_CHAR_21 0x00000015U
236 #define LL_I2C_TX_FIFO_TH_CHAR_22 0x00000016U
237 #define LL_I2C_TX_FIFO_TH_CHAR_23 0x00000017U
238 #define LL_I2C_TX_FIFO_TH_CHAR_24 0x00000018U
239 #define LL_I2C_TX_FIFO_TH_CHAR_25 0x00000019U
240 #define LL_I2C_TX_FIFO_TH_CHAR_26 0x0000001AU
241 #define LL_I2C_TX_FIFO_TH_CHAR_27 0x0000001BU
242 #define LL_I2C_TX_FIFO_TH_CHAR_28 0x0000001CU
243 #define LL_I2C_TX_FIFO_TH_CHAR_29 0x0000001DU
244 #define LL_I2C_TX_FIFO_TH_CHAR_30 0x0000001EU
245 #define LL_I2C_TX_FIFO_TH_CHAR_31 0x0000001FU
246 #define LL_I2C_TX_FIFO_TH_CHAR_32 0x00000020U
253 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U
254 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U
255 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U
256 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U
257 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U
258 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U
259 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U
260 #define LL_I2C_RX_FIFO_TH_CHAR_8 0x00000007U
261 #define LL_I2C_RX_FIFO_TH_CHAR_9 0x00000008U
262 #define LL_I2C_RX_FIFO_TH_CHAR_10 0x00000009U
263 #define LL_I2C_RX_FIFO_TH_CHAR_11 0x0000000AU
264 #define LL_I2C_RX_FIFO_TH_CHAR_12 0x0000000BU
265 #define LL_I2C_RX_FIFO_TH_CHAR_13 0x0000000CU
266 #define LL_I2C_RX_FIFO_TH_CHAR_14 0x0000000DU
267 #define LL_I2C_RX_FIFO_TH_CHAR_15 0x0000000EU
268 #define LL_I2C_RX_FIFO_TH_CHAR_16 0x0000000FU
269 #define LL_I2C_RX_FIFO_TH_CHAR_17 0x00000010U
270 #define LL_I2C_RX_FIFO_TH_CHAR_18 0x00000011U
271 #define LL_I2C_RX_FIFO_TH_CHAR_19 0x00000012U
272 #define LL_I2C_RX_FIFO_TH_CHAR_20 0x00000013U
273 #define LL_I2C_RX_FIFO_TH_CHAR_21 0x00000014U
274 #define LL_I2C_RX_FIFO_TH_CHAR_22 0x00000015U
275 #define LL_I2C_RX_FIFO_TH_CHAR_23 0x00000016U
276 #define LL_I2C_RX_FIFO_TH_CHAR_24 0x00000017U
277 #define LL_I2C_RX_FIFO_TH_CHAR_25 0x00000018U
278 #define LL_I2C_RX_FIFO_TH_CHAR_26 0x00000019U
279 #define LL_I2C_RX_FIFO_TH_CHAR_27 0x0000001AU
280 #define LL_I2C_RX_FIFO_TH_CHAR_28 0x0000001BU
281 #define LL_I2C_RX_FIFO_TH_CHAR_29 0x0000001CU
282 #define LL_I2C_RX_FIFO_TH_CHAR_30 0x0000001DU
283 #define LL_I2C_RX_FIFO_TH_CHAR_31 0x0000001EU
284 #define LL_I2C_RX_FIFO_TH_CHAR_32 0x0000001FU
285 #define LL_I2C_RX_FIFO_TH_FULL 0x00000020U
295 #define LL_I2C_DEFAULT_CONFIG \
297 .speed = LL_I2C_SPEED_400K, \
298 .own_address = 0x55U, \
299 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
321 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
329 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
342 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
352 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
353 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
386 SET_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
406 CLEAR_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
421 return (READ_BITS(I2Cx->STAT, I2C_EN_STAT_EN) == (I2C_EN_STAT_EN));
436 SET_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
451 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
467 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS) == (I2C_CTRL_M_MODE | I2C_CTRL_S_DIS));
483 SET_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
499 CLEAR_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
514 return (READ_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL) == (I2C_ACK_GEN_CALL_ACK_GEN_CALL));
536 SET_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
552 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
567 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN) == (I2C_CTRL_RESTART_EN));
587 SET_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
603 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
619 SET_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
635 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
651 SET_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
667 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
683 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE) == (I2C_CTRL_BUS_CLR_FEATURE));
698 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT) == (I2C_CTRL_STOP_DET_INT));
717 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M, addressing_mode);
735 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M));
757 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_S, own_addr_size);
758 WRITE_REG(I2Cx->S_ADDR, own_address);
775 WRITE_REG(I2Cx->SS_CLK_HCOUNT, count);
790 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_HCOUNT, I2C_SS_CLK_HCOUNT_COUNT));
807 WRITE_REG(I2Cx->SS_CLK_LCOUNT, count);
822 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_LCOUNT, I2C_SS_CLK_LCOUNT_COUNT));
839 WRITE_REG(I2Cx->FS_CLK_HCOUNT, count);
854 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_HCOUNT, I2C_FS_CLK_HCOUNT_COUNT));
871 WRITE_REG(I2Cx->FS_CLK_LCOUNT, count);
886 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_LCOUNT, I2C_FS_CLK_LCOUNT_COUNT));
889 #ifdef HAL_I2C_VERSION_OLD
904 WRITE_REG(I2Cx->HS_CLK_HCOUNT, count);
919 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_HCOUNT, I2C_HS_CLK_HCOUNT_COUNT));
936 WRITE_REG(I2Cx->HS_CLK_LCOUNT, count);
951 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_LCOUNT, I2C_HS_CLK_LCOUNT_COUNT));
969 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
984 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
987 #ifdef HAL_I2C_VERSION_OLD
1002 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
1016 #ifdef HAL_I2C_VERSION_OLD
1019 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
1039 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_SPEED, speed_mode);
1057 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_SPEED));
1060 #ifdef HAL_I2C_VERSION_OLD
1075 WRITE_REG(I2Cx->M_HS_ADDR, code);
1090 return (uint32_t)(READ_BITS(I2Cx->M_HS_ADDR, I2C_M_HS_ADDR_HS_ADDR));
1109 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_POS);
1124 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_POS);
1142 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_POS);
1157 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_POS);
1176 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP, time);
1191 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP));
1241 WRITE_REG(I2Cx->TX_FIFO_THD, threshold);
1289 return (uint32_t)(READ_BITS(I2Cx->TX_FIFO_THD, I2C_TX_FIFO_THD_THD));
1339 WRITE_REG(I2Cx->RX_FIFO_THD, threshold);
1387 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_THD, I2C_RX_FIFO_THD_THD));
1402 return (uint16_t)(READ_BITS(I2Cx->TX_FIFO_LEVEL, I2C_TX_FIFO_LEVEL_LEVEL));
1417 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_LEVEL, I2C_RX_FIFO_LEVEL_LEVEL));
1431 SET_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1445 CLEAR_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1460 return (READ_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY) == (I2C_EN_SDA_STUCK_RECOVERY));
1475 SET_BITS(I2Cx->EN, I2C_EN_ABORT);
1490 return (READ_BITS(I2Cx->EN, I2C_EN_ABORT) == (I2C_EN_ABORT));
1543 return (uint32_t)(READ_REG(I2Cx->TX_ABORT_SRC) & (~I2C_TX_ABORT_SRC_TX_FLUSH_CNT));
1558 return (uint32_t)(READ_BITS(I2Cx->TX_ABORT_SRC, I2C_TX_ABORT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABORT_SRC_TX_FLUSH_CNT_POS);
1603 SET_BITS(I2Cx->INT_MASK, mask);
1642 CLEAR_BITS(I2Cx->INT_MASK, mask);
1681 return (READ_BITS(I2Cx->INT_MASK, mask) == (mask));
1696 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1710 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1724 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW) == (I2C_INT_MASK_MASK_SCL_STUCKLOW));
1727 #ifdef HAL_I2C_VERSION_OLD
1740 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1755 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1770 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD) == (I2C_INT_MASK_MASK_M_HOLD));
1785 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1800 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1815 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET) == (I2C_INT_MASK_MASK_RESTART_DET));
1831 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1846 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1861 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL) == (I2C_INT_MASK_MASK_GEN_CALL));
1876 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1891 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1906 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET) == (I2C_INT_MASK_MASK_START_DET));
1921 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1936 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1951 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET) == (I2C_INT_MASK_MASK_STOP_DET));
1966 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1981 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1996 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY) == (I2C_INT_MASK_MASK_ACTIVITY));
2011 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2026 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2041 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE) == (I2C_INT_MASK_MASK_RX_DONE));
2056 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2071 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2086 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT) == (I2C_INT_MASK_MASK_TX_ABORT));
2101 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2116 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2131 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ) == (I2C_INT_MASK_MASK_RD_REQ));
2146 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2161 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2176 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY) == (I2C_INT_MASK_MASK_TX_EMPTY));
2191 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2206 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2221 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER) == (I2C_INT_MASK_MASK_TX_OVER));
2236 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2251 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2266 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL) == (I2C_INT_MASK_MASK_RX_FULL));
2281 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2296 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2311 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER) == (I2C_INT_MASK_MASK_RX_OVER));
2326 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2341 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2356 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2404 return (uint32_t)(READ_REG(I2Cx->INT_STAT));
2446 return (uint32_t)(READ_REG(I2Cx->RAW_INT_STAT));
2463 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_SCL_STUCKLOW) == (I2C_INT_STAT_RAW_SCL_STUCKLOW));
2480 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_SCL_STUCKLOW) == (I2C_RAW_INT_STAT_SCL_STUCKLOW));
2483 #ifdef HAL_I2C_VERSION_OLD
2498 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_M_HOLD) == (I2C_INT_STAT_RAW_M_HOLD));
2515 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_M_HOLD) == (I2C_RAW_INT_STAT_M_HOLD));
2532 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RESTART_DET) == (I2C_INT_STAT_RAW_RESTART_DET));
2549 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RESTART_DET) == (I2C_RAW_INT_STAT_RESTART_DET));
2567 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_GEN_CALL) == (I2C_INT_STAT_RAW_GEN_CALL));
2584 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_GEN_CALL) == (I2C_RAW_INT_STAT_GEN_CALL));
2601 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_START_DET) == (I2C_INT_STAT_RAW_START_DET));
2618 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_START_DET) == (I2C_RAW_INT_STAT_START_DET));
2635 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_STOP_DET) == (I2C_INT_STAT_RAW_STOP_DET));
2652 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_STOP_DET) == (I2C_RAW_INT_STAT_STOP_DET));
2669 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_ACTIVITY) == (I2C_INT_STAT_RAW_ACTIVITY));
2686 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_ACTIVITY) == (I2C_RAW_INT_STAT_ACTIVITY));
2703 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_DONE) == (I2C_INT_STAT_RAW_RX_DONE));
2720 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_DONE) == (I2C_RAW_INT_STAT_RX_DONE));
2737 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_ABORT) == (I2C_INT_STAT_RAW_TX_ABORT));
2754 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_ABORT) == (I2C_RAW_INT_STAT_TX_ABORT));
2771 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RD_REQ) == (I2C_INT_STAT_RAW_RD_REQ));
2788 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RD_REQ) == (I2C_RAW_INT_STAT_RD_REQ));
2805 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_EMPTY) == (I2C_INT_STAT_RAW_TX_EMPTY));
2822 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_EMPTY) == (I2C_RAW_INT_STAT_TX_EMPTY));
2839 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_OVER) == (I2C_INT_STAT_RAW_TX_OVER));
2856 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_OVER) == (I2C_RAW_INT_STAT_TX_OVER));
2873 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_FULL) == (I2C_INT_STAT_RAW_RX_FULL));
2890 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_FULL) == (I2C_RAW_INT_STAT_RX_FULL));
2907 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_OVER) == (I2C_INT_STAT_RAW_RX_OVER));
2924 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_OVER) == (I2C_RAW_INT_STAT_RX_OVER));
2941 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2958 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_UNDER) == (I2C_RAW_INT_STAT_RX_UNDER));
2973 __IO uint32_t tmpreg;
2974 tmpreg = READ_REG(I2Cx->CLR_INT);
2990 __IO uint32_t tmpreg;
2991 tmpreg = READ_REG(I2Cx->CLR_SCL_STUCK_DET);
3007 __IO uint32_t tmpreg;
3008 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
3024 __IO uint32_t tmpreg;
3025 tmpreg = READ_REG(I2Cx->CLR_START_DET);
3041 __IO uint32_t tmpreg;
3042 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
3058 __IO uint32_t tmpreg;
3059 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
3075 __IO uint32_t tmpreg;
3076 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
3092 __IO uint32_t tmpreg;
3093 tmpreg = READ_REG(I2Cx->CLR_TX_ABORT);
3109 __IO uint32_t tmpreg;
3110 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
3126 __IO uint32_t tmpreg;
3127 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
3143 __IO uint32_t tmpreg;
3144 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
3160 __IO uint32_t tmpreg;
3161 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
3179 return (READ_BITS(I2Cx->STAT, I2C_STAT_SDA_STUCK_RCVR) == (I2C_STAT_SDA_STUCK_RCVR));
3196 return (READ_BITS(I2Cx->STAT, I2C_STAT_S_ACTIVITY) == (I2C_STAT_S_ACTIVITY));
3213 return (READ_BITS(I2Cx->STAT, I2C_STAT_M_ACTIVITY) == (I2C_STAT_M_ACTIVITY));
3230 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_CF) == (I2C_STAT_RX_FIFO_CF));
3247 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_NE) == (I2C_STAT_RX_FIFO_NE));
3264 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_CE) == (I2C_STAT_TX_FIFO_CE));
3281 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_NF) == (I2C_STAT_TX_FIFO_NF));
3298 return (READ_BITS(I2Cx->STAT, I2C_STAT_ACTIVITY) == (I2C_STAT_ACTIVITY));
3315 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_RX_DATA_LOST) == (I2C_EN_STAT_S_RX_DATA_LOST));
3332 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_DIS_BUSY) == (I2C_EN_STAT_S_DIS_BUSY));
3352 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3367 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3382 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN) == (I2C_DMA_CTRL_TX_EN));
3397 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3412 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3427 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN) == (I2C_DMA_CTRL_RX_EN));
3446 WRITE_REG(I2Cx->DMA_TX_LEVEL, level);
3461 return (uint32_t)(READ_BITS(I2Cx->DMA_TX_LEVEL, I2C_DMA_TX_LEVEL_LEVEL));
3482 WRITE_REG(I2Cx->DMA_RX_LEVEL, level);
3497 return (uint32_t)(READ_BITS(I2Cx->DMA_RX_LEVEL, I2C_DMA_RX_LEVEL_LEVEL));
3512 return ((uint32_t) & (I2Cx->DATA_CMD));
3528 WRITE_REG(I2Cx->SCL_STUCK_TIMEOUT, timeout);
3544 WRITE_REG(I2Cx->SDA_STUCK_TIMEOUT, timeout);
3567 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3582 return (uint32_t)(READ_BITS(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET) >> I2C_TARGET_ADDR_TARGET_POS);
3604 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3620 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DATA));
3644 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
__STATIC_INLINE void ll_i2c_enable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master initates the SDA stuck at low recovery mechanism.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_sda_stuck_recovery(i2c_regs_t *I2Cx)
the SDA stuck at low recovery mechanism is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_bus_clear_feature(i2c_regs_t *I2Cx)
check bus clear feature is enabled function.
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
__STATIC_INLINE void ll_i2c_set_sda_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Set sda stuck timeout time.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
__STATIC_INLINE void ll_i2c_overflow_if_rx_full(i2c_regs_t *I2Cx)
overflow when the RX FIFO if full function.
__STATIC_INLINE void ll_i2c_enable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Enable SCL_STUCK_AT_LOW interrupt.
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
__STATIC_INLINE void ll_i2c_disable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master disabled the SDA stuck at low recovery mechanism.
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_disable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Disable SCL_STUCK_AT_LOW interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
__STATIC_INLINE void ll_i2c_clear_flag_scl_stuck_det(i2c_regs_t *I2Cx)
Clear scl stuck interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
void ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
__STATIC_INLINE void ll_i2c_hold_bus_if_rx_full(i2c_regs_t *I2Cx)
Hold bus when the RX FIFO if full function.
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
LL I2C init Structure definition.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
void ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void ll_i2c_set_scl_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Set scl stuck timeout time.
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_scl_stuck_at_low(i2c_regs_t *I2Cx)
Indicate the status of SCL_STUCK_AT_LOW flag.
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_scl_stuck_at_low(i2c_regs_t *I2Cx)
Indicate the status of RAW_SCL_STUCK_AT_LOW flag.
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_sda_stuck_not_recovered(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS SDA stuck at low is not recovered flag.
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
__STATIC_INLINE void ll_i2c_disable_bus_clear_feature(i2c_regs_t *I2Cx)
disable bus clear feature function.
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
__STATIC_INLINE void ll_i2c_enable_bus_clear_feature(i2c_regs_t *I2Cx)
enable bus clear feature function.
__STATIC_INLINE void ll_i2c_disable_it_master_on_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
__STATIC_INLINE uint16_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Check if the SCL_STUCK_AT_LOW Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.