Macros | |
#define | LL_PWR_AON_IRQ_EN_BLE_PWR_ON AON_CTL_AON_IRQ_EN_BLE_PWR_ON |
#define | LL_PWR_AON_IRQ_EN_BLE_PWR_DN AON_CTL_AON_IRQ_EN_BLE_PWR_DN |
#define | LL_PWR_AON_IRQ_EN_BOD_RISE AON_CTL_AON_IRQ_EN_PMU_BOD_RISE |
#define | LL_PWR_AON_IRQ_EN_CPLL_DN AON_CTL_AON_IRQ_EN_AONPLL_CHG |
#define | LL_PWR_AON_IRQ_EN_BOD_FALL AON_CTL_AON_IRQ_EN_PMU_BOD_FALL |
#define | LL_PWR_AON_IRQ_EN_BLE_MAC AON_CTL_AON_IRQ_EN_BLE_MAC_IRQ |
#define | LL_PWR_AON_IRQ_EN_SLP_FAIL AON_CTL_AON_IRQ_EN_SLP_FAIL_IRQ |
#define | LL_PWR_AON_IRQ_EN_ALL AON_CTL_AON_IRQ_EN_ALL |
#define LL_PWR_AON_IRQ_EN_ALL AON_CTL_AON_IRQ_EN_ALL |
#define LL_PWR_AON_IRQ_EN_BLE_MAC AON_CTL_AON_IRQ_EN_BLE_MAC_IRQ |
#define LL_PWR_AON_IRQ_EN_BLE_PWR_DN AON_CTL_AON_IRQ_EN_BLE_PWR_DN |
#define LL_PWR_AON_IRQ_EN_BLE_PWR_ON AON_CTL_AON_IRQ_EN_BLE_PWR_ON |
#define LL_PWR_AON_IRQ_EN_BOD_FALL AON_CTL_AON_IRQ_EN_PMU_BOD_FALL |
#define LL_PWR_AON_IRQ_EN_BOD_RISE AON_CTL_AON_IRQ_EN_PMU_BOD_RISE |
#define LL_PWR_AON_IRQ_EN_CPLL_DN AON_CTL_AON_IRQ_EN_AONPLL_CHG |