151 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
152 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
153 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
154 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
155 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
156 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
162 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
163 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
164 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
165 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
171 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
172 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
173 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
179 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
180 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
181 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
187 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
188 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
189 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
190 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
191 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
192 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
193 #define LL_DMA_SRC_BURST_LENGTH_128 DMA_CTLL_SRC_MSIZE_128
194 #define LL_DMA_SRC_BURST_LENGTH_256 DMA_CTLL_SRC_MSIZE_256
200 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
201 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
202 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
203 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
204 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
205 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
206 #define LL_DMA_DST_BURST_LENGTH_128 DMA_CTLL_DST_MSIZE_128
207 #define LL_DMA_DST_BURST_LENGTH_256 DMA_CTLL_DST_MSIZE_256
213 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
214 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
215 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
221 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
222 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
223 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
229 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
230 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
231 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
232 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
233 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
234 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
235 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
236 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
242 #define LL_DMA_LOCK_CH_ENABLE DMA_CFGL_LOCK_CH_ENABLE
243 #define LL_DMA_LOCK_CH_DSIBALE DMA_CFGL_LOCK_CH_DISABLE
249 #define LL_DMA_LOCK_CH_LEVEL_TFR DMA_CFGL_LOCK_CH_L_TFR
250 #define LL_DMA_LOCK_CH_LEVEL_BLK DMA_CFGL_LOCK_CH_L_BLK
251 #define LL_DMA_LOCK_CH_LEVEL_TRANS DMA_CFGL_LOCK_CH_L_TRANS
257 #define LL_DMA_LOCK_BUS_ENABLE DMA_CFGL_LOCK_B_ENABLE
258 #define LL_DMA_LOCK_BUS_DSIBALE DMA_CFGL_LOCK_B_DISABLE
264 #define LL_DMA_LOCK_BUS_LEVEL_TFR DMA_CFGL_LOCK_B_L_TFR
265 #define LL_DMA_LOCK_BUS_LEVEL_BLK DMA_CFGL_LOCK_B_L_BLK
266 #define LL_DMA_LOCK_BUS_LEVEL_TRANS DMA_CFGL_LOCK_B_L_TRANS
272 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
273 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
279 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
280 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
287 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU)
290 #define LL_DMA0_PERIPH_CTE ((uint32_t)0x00000000U)
291 #define LL_DMA0_PERIPH_PWM0 ((uint32_t)0x00000001U)
292 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U)
293 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U)
294 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U)
295 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U)
296 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U)
297 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U)
298 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U)
299 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U)
300 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU)
301 #define LL_DMA0_PERIPH_I2C0_TX ((uint32_t)0x0000000CU)
302 #define LL_DMA0_PERIPH_I2C0_RX ((uint32_t)0x0000000DU)
303 #define LL_DMA0_PERIPH_I2C1_TX ((uint32_t)0x0000000EU)
304 #define LL_DMA0_PERIPH_I2C1_RX ((uint32_t)0x0000000FU)
326 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
334 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
365 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
384 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
399 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
422 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
443 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
466 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
489 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
511 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
532 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
553 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
588 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
589 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
615 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
640 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
665 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
689 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
714 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
738 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
763 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
787 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
812 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
836 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
861 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
885 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
910 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
934 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
961 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
987 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1010 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1033 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1064 uint32_t src_address,
1065 uint32_t dst_address,
1068 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1069 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1070 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1092 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1114 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1135 return READ_REG(DMAx->CHANNEL[channel].SAR);
1156 return READ_REG(DMAx->CHANNEL[channel].DAR);
1179 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1180 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1204 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1205 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1227 return READ_REG(DMAx->CHANNEL[channel].SAR);
1249 return READ_REG(DMAx->CHANNEL[channel].DAR);
1287 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1323 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1360 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1396 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
1423 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1424 src_handshaking | dst_handshaking);
1447 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
1470 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
1491 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1512 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1533 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH) == DMA_CFGL_LOCK_CH);
1554 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1575 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1596 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B) == DMA_CFGL_LOCK_B);
1621 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L, lock_level);
1645 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L);
1670 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L, lock_level);
1694 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L);
1716 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1717 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1738 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1761 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1762 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1763 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1785 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1786 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1808 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1809 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1830 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1853 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1854 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1855 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1877 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1878 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1899 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1914 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1929 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1944 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1959 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1980 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2001 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2022 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2043 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2064 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2085 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2100 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2115 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2130 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2145 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2160 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2182 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2197 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2212 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2227 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2242 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2257 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2279 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2294 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2309 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2324 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2339 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2354 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2375 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2390 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2405 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2420 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2435 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2450 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2471 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
2486 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
2501 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
2516 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
2531 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
2546 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
2567 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2582 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2597 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2612 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
2627 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
2642 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
2663 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
2678 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
2693 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
2708 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
2723 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
2738 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
2759 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
2774 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
2789 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
2804 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
2819 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
2834 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
2855 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
2870 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
2885 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
2900 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
2915 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
2930 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
2951 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
2966 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
2981 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
2996 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3011 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
3026 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
3053 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3074 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3095 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3116 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3137 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3158 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3179 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3200 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3221 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3242 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3263 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3284 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
3305 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
3326 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
3347 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
3368 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3389 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
3410 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);