52 #ifndef ___LL_EFUSE_H__
53 #define ___LL_EFUSE_H__
69 #define EFUSE_ZONE_SIZE_BYTE 32U
70 #define EFUSE_ZONE_SIZE_WORD (EFUSE_ZONE_SIZE_BYTE / 4U)
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK
88 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE
89 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS
90 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE
97 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE
98 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE
119 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
127 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
157 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
172 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
188 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
203 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
218 SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
233 CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
248 return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
265 WRITE_REG(EFUSEx->OPERATION, mode);
286 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
300 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
314 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
329 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN|AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
343 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN|AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
357 return (READ_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN) == AON_PMU_RF_REG_2_EFUSE_VDDQ_EN);
373 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_0, vddq_0 + (vddq_1 << 16));
374 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_1, vddq_2);
388 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_EN);
402 CLEAR_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_EN);
416 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_BGN);
431 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_STP);
447 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL_0, 0);
466 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL_1, flag) == (flag));