Macros | |
#define | CGC_WFI_SECU_HCLK ((uint32_t)0x00000001U) |
#define | CGC_WFI_SIM_HCLK ((uint32_t)0x00000002U) |
#define | CGC_WFI_HTB_HCLK ((uint32_t)0x00000004U) |
#define | CGC_WFI_PWM_HCLK ((uint32_t)0x00000008U) |
#define | CGC_WFI_ROM_HCLK ((uint32_t)0x00000010U) |
#define | CGC_WFI_SNSADC_HCLK ((uint32_t)0x00000020U) |
#define | CGC_WFI_GPIO_HCLK ((uint32_t)0x00000040U) |
#define | CGC_WFI_DMA_HCLK ((uint32_t)0x00000080U) |
#define | CGC_WFI_BLE_BRG_HCLK ((uint32_t)0x00000100U) |
#define | CGC_WFI_APB_SUB_HCLK ((uint32_t)0x00000200U) |
#define | CGC_WFI_SERIAL_HCLK ((uint32_t)0x00000400U) |
#define | CGC_WFI_I2S_S_HCLK ((uint32_t)0x00000800U) |
#define | CGC_WFI_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) |
#define | CGC_WFI_XF_XQSPI_HCLK ((uint32_t)0x00002000U) |
#define | CGC_WFI_SRAM_HCLK ((uint32_t)0x00004000U) |
#define | CGC_WFI_SECU_DIV4_PCLK ((uint32_t)0x00008000U) |
#define | CGC_WFI_XQSPI_DIV4_PCLK ((uint32_t)0x00020000U) |
#define | CGC_WFI_ALL_CLK ((uint32_t)0x0002FFFFU) |
#define CGC_WFI_ALL_CLK ((uint32_t)0x0002FFFFU) |
#define CGC_WFI_AON_MCUSUB_HCLK ((uint32_t)0x00001000U) |
#define CGC_WFI_APB_SUB_HCLK ((uint32_t)0x00000200U) |
#define CGC_WFI_BLE_BRG_HCLK ((uint32_t)0x00000100U) |
#define CGC_WFI_DMA_HCLK ((uint32_t)0x00000080U) |
#define CGC_WFI_GPIO_HCLK ((uint32_t)0x00000040U) |
#define CGC_WFI_HTB_HCLK ((uint32_t)0x00000004U) |
#define CGC_WFI_I2S_S_HCLK ((uint32_t)0x00000800U) |
#define CGC_WFI_PWM_HCLK ((uint32_t)0x00000008U) |
#define CGC_WFI_ROM_HCLK ((uint32_t)0x00000010U) |
#define CGC_WFI_SECU_DIV4_PCLK ((uint32_t)0x00008000U) |
#define CGC_WFI_SECU_HCLK ((uint32_t)0x00000001U) |
#define CGC_WFI_SERIAL_HCLK ((uint32_t)0x00000400U) |
#define CGC_WFI_SIM_HCLK ((uint32_t)0x00000002U) |
#define CGC_WFI_SNSADC_HCLK ((uint32_t)0x00000020U) |
#define CGC_WFI_SRAM_HCLK ((uint32_t)0x00004000U) |
#define CGC_WFI_XF_XQSPI_HCLK ((uint32_t)0x00002000U) |