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62 #if defined(AON_CTL) && defined(AON_IO)
76 #define LL_PWR_WKUP_COND_EXT AON_CTL_MCU_WAKEUP_CTRL_EXT
77 #define LL_PWR_WKUP_COND_TIMER AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER
78 #define LL_PWR_WKUP_COND_BLE AON_CTL_MCU_WAKEUP_CTRL_SMS_OSC
79 #define LL_PWR_WKUP_COND_CLDR AON_CTL_MCU_WAKEUP_CTRL_RTC0
80 #define LL_PWR_WKUP_COND_AON_WDT AON_CTL_MCU_WAKEUP_CTRL_AON_WDT
81 #define LL_PWR_WKUP_COND_COMP_RISE AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE
82 #define LL_PWR_WKUP_COND_COMP_FALL AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL
83 #define LL_PWR_WKUP_COND_ALL AON_CTL_WAKEUP_CTRL_SEL
90 #define LL_PWR_WKUP_EVENT_BLE AON_CTL_SLP_EVENT_SMS_OSC
91 #define LL_PWR_WKUP_EVENT_TIMER AON_CTL_SLP_EVENT_SLP_TIMER
92 #define LL_PWR_WKUP_EVENT_EXT AON_CTL_SLP_EVENT_EXT
93 #define LL_PWR_WKUP_EVENT_COMP_RISE AON_CTL_SLP_EVENT_COMP_RISE
94 #define LL_PWR_WKUP_EVENT_COMP_FALL AON_CTL_SLP_EVENT_COMP_FALL
95 #define LL_PWR_WKUP_EVENT_WDT AON_CTL_SLP_EVENT_AON_WDT
96 #define LL_PWR_WKUP_EVENT_CLDR AON_CTL_SLP_EVENT_RTC0
97 #define LL_PWR_WKUP_EVENT_ALL AON_CTL_SLP_EVENT_ALL
103 #define LL_PWR_AON_IRQ_EVT_BLE_PWR_ON AON_CTL_AON_IRQ_BLE_PWR
104 #define LL_PWR_AON_IRQ_EVT_BLE_PWR_DN AON_CTL_AON_IRQ_BLE_PWR_DN
105 #define LL_PWR_AON_IRQ_EVT_BOD_RISE AON_CTL_AON_IRQ_PMU_BOD_RISE
106 #define LL_PWR_AON_IRQ_EVT_CPLL_DN AON_CTL_AON_IRQ_AONPLL_CHG
107 #define LL_PWR_AON_IRQ_EVT_BOD_FALL AON_CTL_AON_IRQ_PMU_BOD_FALL
108 #define LL_PWR_AON_IRQ_EVT_BLE_MAC AON_CTL_AON_IRQ_BLE_MAC_IRQ
109 #define LL_PWR_AON_IRQ_EVT_SLP_FAIL AON_CTL_AON_IRQ_SLP_FAIL_IRQ
110 #define LL_PWR_AON_IRQ_EVT_ALL AON_CTL_AON_IRQ_BLE_ALL
117 #define LL_PWR_AON_IRQ_EN_BLE_PWR_ON AON_CTL_AON_IRQ_EN_BLE_PWR_ON
118 #define LL_PWR_AON_IRQ_EN_BLE_PWR_DN AON_CTL_AON_IRQ_EN_BLE_PWR_DN
119 #define LL_PWR_AON_IRQ_EN_BOD_RISE AON_CTL_AON_IRQ_EN_PMU_BOD_RISE
120 #define LL_PWR_AON_IRQ_EN_CPLL_DN AON_CTL_AON_IRQ_EN_AONPLL_CHG
121 #define LL_PWR_AON_IRQ_EN_BOD_FALL AON_CTL_AON_IRQ_EN_PMU_BOD_FALL
122 #define LL_PWR_AON_IRQ_EN_BLE_MAC AON_CTL_AON_IRQ_EN_BLE_MAC_IRQ
123 #define LL_PWR_AON_IRQ_EN_SLP_FAIL AON_CTL_AON_IRQ_EN_SLP_FAIL_IRQ
124 #define LL_PWR_AON_IRQ_EN_ALL AON_CTL_AON_IRQ_EN_ALL
138 #define LL_PWR_DPAD_LE_OFF (0x00000000U)
139 #define LL_PWR_DPAD_LE_ON (0x00000001U)
173 SET_BITS(
AON_CTL->MCU_WAKEUP_CTRL, condition);
196 CLEAR_BITS(
AON_CTL->MCU_WAKEUP_CTRL, condition);
287 SET_BITS(
AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
302 CLEAR_BITS(
AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
316 return (READ_BITS(
AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ) == AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
337 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_SLEEP, (sleep << AON_PWR_DPAD_LE_CTRL_SLEEP_Pos));
338 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_WAKEUP, (wakeup << AON_PWR_DPAD_LE_CTRL_WAKEUP_Pos));
360 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
375 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
389 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N) == 0x0U));
406 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
421 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
435 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_RST_N_RD) == 0x0U));
450 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
451 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
452 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
467 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
468 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
469 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
484 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN) == AON_PWR_COMM_TIMER_PWR_CTRL_EN));
499 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
500 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
515 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
516 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
531 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD) == AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD));
545 SET_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
560 CLEAR_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
574 return ((uint32_t)(READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN));
588 SET_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
603 CLEAR_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
617 return ((uint32_t)(READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN));
632 SET_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
647 CLEAR_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
661 return ((uint32_t)(READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON));
677 SET_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ);
692 return ((uint32_t)(READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ));
707 CLEAR_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
722 SET_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
736 return ((uint32_t)(READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
751 WRITE_REG(
AON_CTL->COMM_TIMER_CFG0, time);
765 return ((uint32_t)READ_REG(
AON_CTL->COMM_TIMER_CFG0));
779 return ((uint32_t)READ_REG(
AON_CTL->COMM_TIMER_STAT));
800 WRITE_REG(
AON_CTL->COMM_TIMER_CFG1, (twext << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWEXT_Pos) |
801 (twosc << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos) |
802 (twrm << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWRM_Pos));
818 return ((uint32_t)READ_REG(
AON_CTL->COMM_TIMER_CFG1));
828 return ((((uint32_t)READ_REG(
AON_CTL->COMM_TIMER_CFG1) & AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Msk)) >> AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos);
858 return ((uint32_t)(READ_BITS(
AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) >> AON_IO_EXT_WAKEUP_STAT_STAT_POS));
882 WRITE_REG(
AON_CTL->EXT_WAKEUP_STAT, ~(wakeup_pin << AON_IO_EXT_WAKEUP_STAT_STAT_POS));
919 return (READ_BITS(
AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT);
934 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
935 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
950 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DCDC, (value << AON_PWR_A_TIMING_CTRL0_DCDC_Pos));
965 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DIG_LDO, (value << AON_PWR_A_TIMING_CTRL0_DIG_LDO_Pos));
981 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_FAST_LDO, (value << AON_PWR_A_TIMING_CTRL1_FAST_LDO_Pos));
996 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_HF_OSC, (value << AON_PWR_A_TIMING_CTRL1_HF_OSC_Pos));
1011 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL_LOCK, (value << AON_PWR_A_TIMING_CTRL2_PLL_LOCK_Pos));
1026 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL, (value << AON_PWR_A_TIMING_CTRL2_PLL_Pos));
1041 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_PWR_SWITCH, (value << AON_PWR_A_TIMING_CTRL3_PWR_SWITCH_Pos));
1056 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_XO, (value << AON_PWR_A_TIMING_CTRL3_XO_Pos));
1071 MODIFY_REG(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_POWER_MODE,value << AON_PWR_AON_START_CFG_POWER_MODE_Pos);
1086 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1100 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1123 SET_BITS(
AON_CTL->AON_IRQ_EN, condition);
1146 CLEAR_BITS(
AON_CTL->AON_IRQ_EN, condition);
1169 CLEAR_BITS(
AON_CTL->AON_IRQ, condition);
__STATIC_INLINE void ll_pwr_set_fast_ldo_prepare_timing(uint32_t value)
Set fast LDO prepare timing.
__STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
__STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
__STATIC_INLINE void ll_pwr_set_dig_ldo_prepare_timing(uint32_t value)
Set digtal LDO prepare timing.
__STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
__STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
__STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
__STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
__STATIC_INLINE void ll_pwr_clear_aon_irq_event(uint32_t condition)
Clear the AON IRQ EVENT.
__STATIC_INLINE void ll_pwr_clear_wakeup_condition(uint32_t condition)
Clear the DeepSleep WakeUp Condition.
#define LL_PWR_WKUP_COND_ALL
__STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
__STATIC_INLINE void ll_pwr_set_dcdc_prepare_timing(uint32_t value)
Set DCDC prepare timing.
__STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
__STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
__STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
__STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
__STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
__STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
__STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
__STATIC_INLINE void ll_pwr_disable_aon_irq(uint32_t condition)
clear the AON IRQ Condition
__STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
__STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
__STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
__STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
#define LL_PWR_WKUP_EVENT_ALL
__STATIC_INLINE void ll_pwr_turn_off_enable_xo_pll_after_dcdc_ready(void)
Turn off enable xo/pll in warm boot.
__STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
__STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
__STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
__STATIC_INLINE void ll_pwr_set_xo_prepare_timing(uint32_t value)
Set Set XO prepare timing.
__STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
__STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_read_value(void)
Read the AON Sleep Timer counter current value.
__STATIC_INLINE void ll_pwr_set_hf_osc_prepare_timing(uint32_t value)
Set HF OSC prepare timing.
__STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
__STATIC_INLINE void ll_pwr_turn_on_enable_xo_pll_after_dcdc_ready(void)
Turn on enable xo/pll in srpg.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
__STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
__STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
__STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
__STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
__STATIC_INLINE void ll_pwr_set_pll_prepare_timing(uint32_t value)
Set PLL prepare timing.
__STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
__STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
__STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
__STATIC_INLINE void ll_pwr_set_pll_lock_timing(uint32_t value)
Set PLL lock prepare timing.
__STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
__STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
__STATIC_INLINE void ll_pwr_set_pwr_switch_prepare_timing(uint32_t value)
Set power switch prepare timing.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
__STATIC_INLINE void ll_pwr_set_pwr_mode(uint32_t value)
ll_pwr_set_pwr_mode
__STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
__STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
__STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
__STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
__STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
__STATIC_INLINE void ll_pwr_enable_aon_irq(uint32_t condition)
Set the AON IRQ Condition.
__STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
__STATIC_FORCEINLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.