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119 #define LL_COMP_INPUT_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
120 #define LL_COMP_INPUT_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
121 #define LL_COMP_INPUT_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
122 #define LL_COMP_INPUT_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
123 #define LL_COMP_INPUT_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
124 #define LL_COMP_INPUT_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
125 #define LL_COMP_INPUT_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
126 #define LL_COMP_INPUT_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
128 #define LL_COMP_INPUT_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
129 #define LL_COMP_INPUT_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
136 #define LL_COMP_REF_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
137 #define LL_COMP_REF_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
138 #define LL_COMP_REF_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
139 #define LL_COMP_REF_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
140 #define LL_COMP_REF_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
141 #define LL_COMP_REF_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
142 #define LL_COMP_REF_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
143 #define LL_COMP_REF_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
145 #define LL_COMP_REF_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
146 #define LL_COMP_REF_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
152 #define LL_COMP_HYST_POSITIVE (1UL << AON_PMU_COMP_REG_0_POSITIVE_HYS_EN_Pos )
153 #define LL_COMP_HYST_NEGATIVE (1UL << AON_PMU_COMP_REG_0_NEGATIVE_HYS_EN_Pos )
157 #define LL_COMP_RES_DEGENERATION_POSITIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_RES_DEGENERATION_Pos )
158 #define LL_COMP_RES_DEGENERATION_NEGATIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_RES_DEGENERATION_Pos )
165 #define LL_COMP_WAKEUP_EDGE_BOTH ( 0UL )
166 #define LL_COMP_WAKEUP_EDGE_FALLING ( 1UL )
167 #define LL_COMP_WAKEUP_EDGE_RISING ( 2UL )
187 #define LL_COMP_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
195 #define LL_COMP_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
216 #define LL_COMP_DEFAULT_CONFIG \
218 .channel_p = LL_COMP_CHANNEL_IO0, \
219 .channel_n = LL_COMP_CHANNEL_IO1, \
247 SET_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
261 CLEAR_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
286 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Msk, source);
311 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Msk, source);
327 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_Msk, level << AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_Pos);
343 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_REF_CTRL_Msk, level << AON_PMU_COMP_REG_1_COMP_REF_CTRL_Pos);
357 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_ICOMP_CTRL_Msk, level << AON_PMU_COMP_REG_0_ICOMP_CTRL_Pos);
372 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CASCRES_HALF_CTRL_Msk, level <<AON_PMU_COMP_REG_0_CASCRES_HALF_CTRL_Pos);
389 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_POSITIVE_HYS_EN , hyst);
406 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_NEGATIVE_HYS_EN , hyst);
423 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_RES_DEGENERATION , res_deg);
440 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_RES_DEGENERATION , res_deg);
454 BIT_ADDR((uint32_t)&
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 1;
468 BIT_ADDR((uint32_t)&
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 0;
482 return (READ_BITS(
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE) == AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE);
496 BIT_ADDR((uint32_t)&
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 1;
510 BIT_ADDR((uint32_t)&
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 0;
524 return (READ_BITS(
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL) == AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL);
538 return (READ_BITS(
AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_COMP_RISE) == AON_CTL_SLP_EVENT_COMP_RISE);
552 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_COMP_RISE);
566 return (READ_BITS(
AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_COMP_FALL) == AON_CTL_SLP_EVENT_COMP_FALL);
580 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_COMP_FALL);
594 MODIFY_REG(
AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE, cycle << AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);
608 return (uint32_t)(READ_BITS(
AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Msk) >> AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);
__STATIC_FORCEINLINE uint32_t ll_comp_is_rising_triger_flag_it(void)
Indicate if the COMP rising_triger Flag is set or not.
__STATIC_INLINE void ll_comp_enable_falling_wakeup(void)
Enable Wakeup Interrupt for COMP Falling.
__STATIC_INLINE void ll_comp_cascres_half_high(uint32_t level)
set power of comparator.
__STATIC_INLINE void ll_comp_enable_rising_wakeup(void)
Enable Wakeup Interrupt for COMP Rising.
struct _ll_comp_init ll_comp_init_t
LL COMP init Structure definition.
__STATIC_FORCEINLINE void ll_comp_clear_falling_triger_flag_it(void)
Clear falling_triger flag for COMP.
__STATIC_INLINE void ll_comp_set_current(uint32_t level)
set current of comparator.
__STATIC_INLINE void ll_comp_negative_degeneration(uint32_t res_deg)
Set calibration of comparator.
LL COMP init Structure definition.
void ll_comp_init(const ll_comp_init_t *p_comp_init)
Initialize COMP registers according to the specified. parameters in p_comp_init.
__STATIC_INLINE uint32_t ll_comp_get_remove_cycle(void)
Set compator glitch remove cycles.
__STATIC_INLINE void ll_comp_set_vref_lvl(uint32_t level)
Set VREF control level.
__STATIC_INLINE void ll_comp_disable_falling_wakeup(void)
Disable Wakeup Interrupt for COMP Falling.
__STATIC_INLINE void ll_comp_disable(void)
Disable COMP module.
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
__STATIC_INLINE void ll_comp_positive_hysteresis(uint32_t hyst)
Set positive hysteresis comparator.
__STATIC_INLINE void ll_comp_disable_rising_wakeup(void)
Disable Wakeup Interrupt for COMP Rising.
__STATIC_FORCEINLINE uint32_t ll_comp_is_falling_triger_flag_it(void)
Indicate if the COMP falling_triger Flag is set or not.
__STATIC_INLINE void ll_comp_enable(void)
Enable COMP module.
__STATIC_INLINE void ll_comp_set_remove_cycle(uint32_t cycle)
Set compator glitch remove cycles.
__STATIC_INLINE uint32_t ll_comp_is_enable_falling_wakeup(void)
Get Wakeup Interrupt for COMP Falling.
__STATIC_INLINE uint32_t ll_comp_is_enable_rising_wakeup(void)
Get Wakeup Interrupt for COMP Rising.
void ll_comp_struct_init(ll_comp_init_t *p_comp_init)
Set each field of a ll_comp_init_t type structure to default value.
void ll_comp_deinit(void)
De-initialize COMP registers (Registers restored to their default values).
__STATIC_INLINE void ll_comp_negative_hysteresis(uint32_t hyst)
Set negative hysteresis comparator.
__STATIC_INLINE void ll_comp_set_vbatt_lvl(uint32_t level)
Set VBATT control level.
__STATIC_FORCEINLINE void ll_comp_clear_rising_triger_flag_it(void)
Clear rising_triger flag for COMP.
__STATIC_INLINE void ll_comp_set_ref_src(uint32_t source)
Set channel of COMP reference source.
__STATIC_INLINE void ll_comp_positive_degeneration(uint32_t res_deg)
Set calibration of comparator.
__STATIC_INLINE void ll_comp_set_input_src(uint32_t source)
Set channel of COMP input source.