73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U)
74 #define LL_RTC_DIV_2 ((uint32_t)0x01UL << RTC_CFG1_DIV_Pos)
75 #define LL_RTC_DIV_4 ((uint32_t)0x02UL << RTC_CFG1_DIV_Pos)
76 #define LL_RTC_DIV_8 ((uint32_t)0x03UL << RTC_CFG1_DIV_Pos)
77 #define LL_RTC_DIV_16 ((uint32_t)0x04UL << RTC_CFG1_DIV_Pos)
78 #define LL_RTC_DIV_32 ((uint32_t)0x05UL << RTC_CFG1_DIV_Pos)
79 #define LL_RTC_DIV_64 ((uint32_t)0x06UL << RTC_CFG1_DIV_Pos)
80 #define LL_RTC_DIV_128 ((uint32_t)0x07UL << RTC_CFG1_DIV_Pos)
86 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U)
87 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U)
96 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
127 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
142 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
157 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
173 WRITE_REG(RTCx->TIMER_W, counter);
190 WRITE_REG(RTCx->TIMER_W, start_value);
191 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TIMER_SET | (
READ_CFG0_CFG(RTCx)));
207 WRITE_REG(RTCx->ALARM_W, value);
224 WRITE_REG(RTCx->ALARM_W, alarm_value);
225 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET | (
READ_CFG0_CFG(RTCx)));
241 WRITE_REG(RTCx->TICK_W, tick);
258 WRITE_REG(RTCx->ALARM_W, alarm_value);
259 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET | (
READ_CFG0_CFG(RTCx)));
274 return (uint32_t)READ_REG(RTCx->TIMER_W);
289 return (uint32_t)READ_REG(RTCx->TIMER_R);
304 return (uint32_t)READ_REG(RTCx->ALARM_W);
319 return (uint32_t)READ_REG(RTCx->ALARM_R);
334 return (uint32_t)READ_REG(RTCx->TICK_W);
349 return (uint32_t)READ_REG(RTCx->TICK_R);
365 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
380 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
395 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
411 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_WRAP_CLR | (
READ_CFG0_CFG(RTCx)));
435 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
451 WRITE_REG(RTCx->ALARM_W, value);
452 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET | (
READ_CFG0_CFG(RTCx)));
467 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
482 WRITE_REG(RTCx->CFG0, ((
READ_CFG0_CFG(RTCx)) & (~RTC_CFG0_ALARM_EN) & (~RTC_CFG0_ALARM_SET)) | RTC_CFG0_CFG);
497 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
512 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
513 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
533 CLEAR_BITS(RTCx->CFG0, ((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
537 SET_BITS(RTCx->CFG0, (tick_mode << RTC_CFG0_TICK_MDOE_Pos));
553 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
568 WRITE_REG(RTCx->CFG0, ((
READ_CFG0_CFG(RTCx)) & (~RTC_CFG0_TICK_EN) & (~RTC_CFG0_TICK_SET)) | RTC_CFG0_CFG);
583 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
599 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
600 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
617 WRITE_REG(RTCx->TICK_W, tick_reload);
618 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET | (
READ_CFG0_CFG(RTCx)));
633 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN | (
READ_CFG0_CFG(RTCx)));
648 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
663 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
678 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
701 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
718 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
735 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
750 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
765 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
780 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
795 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
810 WRITE_REG(
AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
825 SET_BITS(
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
840 CLEAR_BITS(
AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);