114 #define LL_BOD_BOD_ENABLE (0x1U)
115 #define LL_BOD_BOD_DISABLE (0x0U)
121 #define LL_BOD_BOD2_ENABLE (0x1U)
122 #define LL_BOD_BOD2_DISABLE (0x0U)
128 #define LL_BOD_STATIC_ENABLE (0x1U)
129 #define LL_BOD_STATIC_DISABLE (0x0U)
135 #define LL_BOD_BOD2_AUTO_POWER_BYPASS_ENABLE (0x1U)
136 #define LL_BOD_BOD2_AUTO_POWER_BYPASS_DISABLE (0x0U)
142 #define LL_BOD_BOD2_LEVEL_0 (0x0U)
143 #define LL_BOD_BOD2_LEVEL_1 (0x1U)
144 #define LL_BOD_BOD2_LEVEL_2 (0x2U)
145 #define LL_BOD_BOD2_LEVEL_3 (0x3U)
146 #define LL_BOD_BOD2_LEVEL_4 (0x4U)
147 #define LL_BOD_BOD2_LEVEL_5 (0x5U)
148 #define LL_BOD_BOD2_LEVEL_6 (0x6U)
149 #define LL_BOD_BOD2_LEVEL_7 (0x7U)
169 #if defined(BIT_BAND_SUPPORT)
170 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 1;
172 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
186 #if defined(BIT_BAND_SUPPORT)
187 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 0;
189 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
203 #if defined(BIT_BAND_SUPPORT)
204 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 1;
206 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
220 #if defined(BIT_BAND_SUPPORT)
221 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 0;
223 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
237 #if defined(BIT_BAND_SUPPORT)
238 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos) = (lvl_ctrl_lv & 0x01);
239 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos+1) = ((lvl_ctrl_lv>>1) & 0x01);
240 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos+2) = ((lvl_ctrl_lv>>2) & 0x01);
242 MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV, (lvl_ctrl_lv << AON_PMU_RF_REG_3_BOD2_LVL_CTRL_LV_Pos));
255 #if defined(BIT_BAND_SUPPORT)
256 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_Pos) = 1;
258 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_EN);
271 #if defined(BIT_BAND_SUPPORT)
272 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_Pos) = 0;
274 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_EN);
288 #if defined(BIT_BAND_SUPPORT)
289 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS_Pos) = 1;
291 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
305 #if defined(BIT_BAND_SUPPORT)
306 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS_Pos) = 0;
308 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
323 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_OK) == AON_PMU_RF_REG_3_BOD2_OK);
337 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_PWR_CTRL_POST) == AON_PMU_RF_REG_3_BOD2_PWR_CTRL_POST);
351 return (uint32_t)(READ_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_INT) == AON_PMU_RF_REG_3_BOD2_INT);
366 SET_BITS(
AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_FALL);
380 CLEAR_BITS(
AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_FALL);
394 SET_BITS(
AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_RISE);
408 CLEAR_BITS(
AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_EN_PMU_BOD_RISE);
422 return (uint32_t)(READ_BITS(
AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD_FALL) == AON_CTL_AON_IRQ_PMU_BOD_FALL);
436 WRITE_REG(
AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD_FALL);
450 return (uint32_t)(READ_BITS(
AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD_RISE) == AON_CTL_AON_IRQ_PMU_BOD_RISE);
464 WRITE_REG(
AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD_RISE);