51 #ifndef __GR5XX_LL_AES_H__
52 #define __GR5XX_LL_AES_H__
106 #define LL_AES_FLAG_DATAREADY AES_STAT_READY
107 #define LL_AES_FLAG_DMA_DONE AES_STAT_DMA_XFE_CPLT
108 #define LL_AES_FLAG_DMA_ERR AES_STAT_DMA_XFE_ERR
109 #define LL_AES_FLAG_KEY_VALID AES_STAT_KEY_STAT
115 #define LL_AES_KEY_SIZE_128 0x00000000U
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CFG_KEY_MODE_POS)
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CFG_KEY_MODE_POS)
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CFG_OPT_MODE_POS)
130 #define LL_AES_KEYTYPE_MCU 0x00000000U
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CFG_KEY_TYPE_POS)
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CFG_KEY_TYPE_POS)
138 #define LL_AES_KEYMODE_NORMAL 0x00000000U
139 #define LL_AES_KEYMODE_KEYWRAP (1UL << AES_CFG_KEY_WRAP_POS)
145 #define LL_AES_DMA_TRANSIZE_MIN (1)
146 #define LL_AES_DMA_TRANSIZE_MAX (2048)
152 #define LL_AES_KEYRAM_KEYSLOT_0 ((uint32_t)0x00000000U)
153 #define LL_AES_KEYRAM_KEYSLOT_1 ((uint32_t)0x00000010U)
154 #define LL_AES_KEYRAM_KEYSLOT_2 ((uint32_t)0x00000020U)
155 #define LL_AES_KEYRAM_KEYSLOT_3 ((uint32_t)0x00000030U)
156 #define LL_AES_KEYRAM_KEYSLOT_4 ((uint32_t)0x00000040U)
157 #define LL_AES_KEYRAM_KEYSLOT_5 ((uint32_t)0x00000050U)
158 #define LL_AES_KEYRAM_KEYSLOT_6 ((uint32_t)0x00000060U)
159 #define LL_AES_KEYRAM_KEYSLOT_7 ((uint32_t)0x00000070U)
160 #define LL_AES_KEYRAM_KEYSLOT_8 ((uint32_t)0x00000080U)
161 #define LL_AES_KEYRAM_KEYSLOT_9 ((uint32_t)0x00000090U)
162 #define LL_AES_KEYRAM_KEYSLOT_10 ((uint32_t)0x000000A0U)
163 #define LL_AES_KEYRAM_KEYSLOT_11 ((uint32_t)0x000000B0U)
164 #define LL_AES_KEYRAM_KEYSLOT_12 ((uint32_t)0x000000C0U)
165 #define LL_AES_KEYRAM_KEYSLOT_13 ((uint32_t)0x000000D0U)
166 #define LL_AES_KEYRAM_KEYSLOT_14 ((uint32_t)0x000000E0U)
167 #define LL_AES_KEYRAM_KEYSLOT_15 ((uint32_t)0x000000F0U)
188 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
196 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
225 SET_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
240 CLEAR_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
255 return (READ_BITS(AESx->CTRL, AES_CTRL_MODULE_EN) == (AES_CTRL_MODULE_EN));
270 SET_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
285 CLEAR_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
300 return (READ_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN) == (AES_CTRL_MCU_MODE_EN));
315 SET_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
330 CLEAR_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
345 return (READ_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN) == (AES_CTRL_DMA_MODE_EN));
360 SET_BITS(AESx->CTRL, AES_CTRL_FKEY_EN);
379 MODIFY_REG(AESx->CFG, AES_CFG_KEY_MODE, size);
397 return (READ_BITS(AESx->CFG, AES_CFG_KEY_MODE));
412 SET_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
427 CLEAR_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
442 return (READ_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN) == (AES_CFG_FULL_MASK_EN));
457 SET_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
472 CLEAR_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
487 return (READ_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL) == (AES_CFG_DEC_ENC_SEL));
502 SET_BITS(AESx->CFG, AES_CFG_LOAD_SEED);
517 SET_BITS(AESx->CFG, AES_CFG_FIRST_BLK);
532 SET_BITS(AESx->CFG, AES_CFG_ENDIAN);
547 CLEAR_BITS(AESx->CFG, AES_CFG_ENDIAN);
562 return (READ_BITS(AESx->CFG, AES_CFG_ENDIAN) == (AES_CFG_ENDIAN));
580 MODIFY_REG(AESx->CFG, AES_CFG_OPT_MODE, mode);
597 return (READ_BITS(AESx->CFG, AES_CFG_OPT_MODE));
616 MODIFY_REG(AESx->CFG, AES_CFG_KEY_TYPE, Type);
634 return (READ_BITS(AESx->CFG, AES_CFG_KEY_TYPE));
652 MODIFY_REG(AESx->CFG, AES_CFG_KEY_WRAP, mode);
669 return (READ_BITS(AESx->CFG, AES_CFG_KEY_WRAP));
690 SET_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
705 CLEAR_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
720 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_EN) == (AES_INT_CPLT_INT_EN));
741 return (READ_BITS(AESx->STAT, AES_STAT_READY) == AES_STAT_READY);
756 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_CPLT) == AES_STAT_DMA_XFE_CPLT);
771 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_ERR) == AES_STAT_DMA_XFE_ERR);
786 return (READ_BITS(AESx->STAT, AES_STAT_KEY_STAT) == AES_STAT_KEY_STAT);
801 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG) == AES_INT_CPLT_INT_FLAG);
816 SET_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG);
838 MODIFY_REG(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE, (block << 4) - 1);
853 return ((READ_BITS(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE) + 1) >> 4);
870 WRITE_REG(AESx->RD_START_ADDR, address);
885 return (READ_REG(AESx->RD_START_ADDR));
902 WRITE_REG(AESx->WR_START_ADDR, address);
917 return (READ_REG(AESx->WR_START_ADDR));
939 WRITE_REG(AESx->KEY_ADDR, address);
954 return (READ_REG(AESx->KEY_ADDR));
969 return (READ_REG(AESx->DATA_OUT0));
984 return (READ_REG(AESx->DATA_OUT1));
999 return (READ_REG(AESx->DATA_OUT2));
1014 return (READ_REG(AESx->DATA_OUT3));
1030 WRITE_REG(AESx->KEY0, key);
1046 WRITE_REG(AESx->KEY1, key);
1062 WRITE_REG(AESx->KEY2, key);
1078 WRITE_REG(AESx->KEY3, key);
1094 WRITE_REG(AESx->KEY4, key);
1110 WRITE_REG(AESx->KEY5, key);
1126 WRITE_REG(AESx->KEY6, key);
1142 WRITE_REG(AESx->KEY7, key);
1158 WRITE_REG(AESx->INIT_SSI, seed);
1173 return (READ_REG(AESx->INIT_SSI));
1189 WRITE_REG(AESx->INIT_SSO, seed);
1204 return (READ_REG(AESx->INIT_SSO));
1220 WRITE_REG(AESx->MASK_SSI, mask);
1235 return (READ_REG(AESx->MASK_SSI));
1251 WRITE_REG(AESx->MASK_SSO, mask);
1266 return (READ_REG(AESx->MASK_SSO));
1282 WRITE_REG(AESx->INIT_V0, vector);
1298 WRITE_REG(AESx->INIT_V1, vector);
1314 WRITE_REG(AESx->INIT_V2, vector);
1330 WRITE_REG(AESx->INIT_V3, vector);
1346 WRITE_REG(AESx->DATA_IN0, data);
1362 WRITE_REG(AESx->DATA_IN1, data);
1378 WRITE_REG(AESx->DATA_IN2, data);
1394 WRITE_REG(AESx->DATA_IN3, data);
1410 WRITE_REG(AESx->KEYPORT_MASK, mask);
1439 WRITE_REG(AESx->KEYRAM_OFS, offset);
1454 return (READ_REG(AESx->KEYRAM_OFS));
1469 SET_BITS(AESx->CBC_RST, AES_CBC_RST_CLR);