65 #define LL_CLK_SEL_SOURCE_CPLL_CLK (0UL)
66 #define LL_CLK_SEL_SOURCE_HF_OSC_CLK (1UL)
73 #define LL_SLOW_CLK_RNG AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RNG
74 #define LL_SLOW_CLK_RC AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RC
75 #define LL_SLOW_CLK_RTC AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RTC
81 #define LL_CLK_CPLL_S64M_CLK AON_CTL_MCU_CLK_CTRL_SEL_64M
82 #define LL_CLK_XO_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_XO_16M
83 #define LL_CLK_CPLL_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_16M
84 #define LL_CLK_CPLL_T32M_CLK AON_CTL_MCU_CLK_CTRL_SEL_32M
90 #define LL_CLK_XO_PLL_PLL_STAT (1UL)
91 #define LL_CLK_XO_PLL_XO_STAT (2UL)
92 #define LL_CLK_XO_PLL_HF_STAT (4UL)
98 #define LL_AON_SLOW_CLK_256K (0UL)
99 #define LL_AON_SLOW_CLK_32K (1UL)
118 return READ_BITS(
AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL);
138 MODIFY_REG(
AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL, clk_sel);
156 MODIFY_REG(
AON_CTL->AON_CLK, AON_CTL_AON_CLK_CAL_FST_CLK, src_sel);
171 MODIFY_REG(AON_PWR->XO_PLL_SET, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
186 MODIFY_REG(AON_PWR->XO_PLL_CLR, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
201 return READ_BITS(AON_PWR->XO_PLL_STAT, AON_PWR_XO_PLL_STAT_PLL_STAT |
202 AON_PWR_XO_PLL_STAT_XO_STAT |
203 AON_PWR_XO_PLL_STAT_HF_STAT);
218 return READ_BITS(
AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_SLOW_CLK_CTRL_SEL);
237 MODIFY_REG(
AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_SLOW_CLK_CTRL_SEL, clk_sel);
255 MODIFY_REG(
AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SLOW_CLK_SEL, (clk_sel << AON_CTL_MCU_CLK_CTRL_SLOW_CLK_SEL_Pos));