Macros | |
#define | LL_PWR_AON_IRQ_EVT_BLE_PWR_ON AON_CTL_AON_IRQ_BLE_PWR |
#define | LL_PWR_AON_IRQ_EVT_BLE_PWR_DN AON_CTL_AON_IRQ_BLE_PWR_DN |
#define | LL_PWR_AON_IRQ_EVT_BOD_RISE AON_CTL_AON_IRQ_PMU_BOD_RISE |
#define | LL_PWR_AON_IRQ_EVT_CPLL_DN AON_CTL_AON_IRQ_AONPLL_CHG |
#define | LL_PWR_AON_IRQ_EVT_BOD_FALL AON_CTL_AON_IRQ_PMU_BOD_FALL |
#define | LL_PWR_AON_IRQ_EVT_BLE_MAC AON_CTL_AON_IRQ_BLE_MAC_IRQ |
#define | LL_PWR_AON_IRQ_EVT_SLP_FAIL AON_CTL_AON_IRQ_SLP_FAIL_IRQ |
#define | LL_PWR_AON_IRQ_EVT_ALL AON_CTL_AON_IRQ_BLE_ALL |
#define LL_PWR_AON_IRQ_EVT_ALL AON_CTL_AON_IRQ_BLE_ALL |
#define LL_PWR_AON_IRQ_EVT_BLE_MAC AON_CTL_AON_IRQ_BLE_MAC_IRQ |
#define LL_PWR_AON_IRQ_EVT_BLE_PWR_DN AON_CTL_AON_IRQ_BLE_PWR_DN |
#define LL_PWR_AON_IRQ_EVT_BLE_PWR_ON AON_CTL_AON_IRQ_BLE_PWR |
#define LL_PWR_AON_IRQ_EVT_BOD_FALL AON_CTL_AON_IRQ_PMU_BOD_FALL |
#define LL_PWR_AON_IRQ_EVT_BOD_RISE AON_CTL_AON_IRQ_PMU_BOD_RISE |
#define LL_PWR_AON_IRQ_EVT_CPLL_DN AON_CTL_AON_IRQ_AONPLL_CHG |