77 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
90 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
105 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_GM, (value << AON_PMU_RF_REG_0_RTC_GM_Pos));
120 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1, (value << AON_PMU_RF_REG_0_IO_LDO_REG1_Pos));
135 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RET_LDO, (value << AON_PMU_RF_REG_0_RET_LDO_Pos));
150 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_AON_LDO, (value << AON_PMU_RF_REG_0_AON_LDO_Pos));
165 return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_AON_LDO) >> AON_PMU_RF_REG_0_AON_LDO_Pos);
180 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VREG, (value << AON_PMU_RF_REG_1_DCDC_VREG_Pos));
195 return (READ_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VREG) >> AON_PMU_RF_REG_1_DCDC_VREG_Pos);
209 CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VOLT_STEP);
223 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VOLT_STEP);
238 MODIFY_REG(AON_PMU->FS_REG_1, AON_PMU_FS_REG_1_SYSLDO_CODE, (value << AON_PMU_FS_REG_1_SYSLDO_CODE_Pos));
253 return (READ_BITS(AON_PMU->FS_REG_1, AON_PMU_FS_REG_1_SYSLDO_CODE) >> AON_PMU_FS_REG_1_SYSLDO_CODE_Pos);
266 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
279 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
292 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
305 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
320 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN, (enable << AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos));
335 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN) >> AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos);
350 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE, (value << AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE_Pos));
365 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE) >> AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE_Pos);
380 MODIFY_REG(AON_PMU->PMU_INTF_OVR_VAL_0, AON_PMU_VAL_AVS_CTL_REF, (value << AON_PMU_VAL_AVS_CTL_REF_Pos) );
381 SET_BITS(AON_PMU->PMU_INTF_OVR_EN_0, AON_PMU_AVS_CTL_REF_EN);
396 return ((AON_PMU->PMU_INTF_OVR_RD0 & AON_PMU_RD_AVS_CTL_REF_Msk) >> AON_PMU_RD_AVS_CTL_REF_Pos);
411 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_CLK_TRIM, (value << AON_PMU_RF_REG_1_BUCK_CLK_TRIM_Pos));
425 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_CLK);
439 CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_CLK);
454 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_PMMOSNUM_SEL, (value << AON_PMU_RF_REG_1_BUCK_PMMOSNUM_SEL_Pos));
469 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_DEADTIME_SEL, (value << AON_PMU_RF_REG_1_BUCK_DEADTIME_SEL_Pos));
484 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CS, (value << AON_PMU_RC_RTC_REG0_RTC_CS_Pos));
499 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP, (value << AON_PMU_RC_RTC_REG0_RTC_CAP_Pos));
514 return (READ_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP) >> AON_PMU_RC_RTC_REG0_RTC_CAP_Pos);
527 SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
540 CLEAR_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
554 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_ON, (value << AON_PMU_TON_CTRL_ON_Pos));
568 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_OFF, (value << AON_PMU_TON_CTRL_OFF_Pos));
582 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
595 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
607 WRITE_REG(AON_PWR->PWR_SET, AON_PWR_PWR_SET_DCDC_SET);
619 WRITE_REG(AON_PWR->PWR_CLR, AON_PWR_PWR_CLR_DCDC_CLR);
634 return (READ_BITS(AON_PWR->PWR_STAT, AON_PWR_PWR_STAT_DCDC_AVL) >> AON_PWR_PWR_STAT_DCDC_AVL_Pos);
647 WRITE_REG(AON_PWR->PWR_SET, AON_PWR_PWR_SET_FAST_LDO_SET);
659 WRITE_REG(AON_PWR->PWR_CLR, AON_PWR_PWR_CLR_FAST_LDO_CLR);
674 return (READ_BITS(AON_PWR->PWR_STAT, AON_PWR_PWR_STAT_FAST_LDO_AVL) >> AON_PWR_PWR_STAT_FAST_LDO_AVL_Pos);