Macros | |
#define | DMA0_REQUEST_CTE LL_DMA0_PERIPH_CTE |
#define | DMA0_REQUEST_PWM0 LL_DMA0_PERIPH_PWM0 |
#define | DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX |
#define | DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX |
#define | DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX |
#define | DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX |
#define | DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX |
#define | DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX |
#define | DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX |
#define | DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX |
#define | DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC |
#define | DMA0_REQUEST_I2C0_TX LL_DMA0_PERIPH_I2C0_TX |
#define | DMA0_REQUEST_I2C0_RX LL_DMA0_PERIPH_I2C0_RX |
#define | DMA0_REQUEST_I2C1_TX LL_DMA0_PERIPH_I2C1_TX |
#define | DMA0_REQUEST_I2C1_RX LL_DMA0_PERIPH_I2C1_RX |
#define | DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM |
#define DMA0_REQUEST_CTE LL_DMA0_PERIPH_CTE |
#define DMA0_REQUEST_I2C0_RX LL_DMA0_PERIPH_I2C0_RX |
#define DMA0_REQUEST_I2C0_TX LL_DMA0_PERIPH_I2C0_TX |
#define DMA0_REQUEST_I2C1_RX LL_DMA0_PERIPH_I2C1_RX |
#define DMA0_REQUEST_I2C1_TX LL_DMA0_PERIPH_I2C1_TX |
#define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM |
#define DMA0_REQUEST_PWM0 LL_DMA0_PERIPH_PWM0 |
#define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC |
#define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX |
#define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX |
#define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX |
#define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX |
#define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX |
#define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX |
#define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX |
#define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX |