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60 #if defined (PWM0) || defined (PWM1)
233 #define LL_PWM_EDGE_ALIGNED (0x00000000U)
234 #define LL_PWM_CENTER_ALIGNED (0x00000001U)
240 #define LL_PWM_STOP_LVL_LOW (0x00000000U)
241 #define LL_PWM_STOP_LVL_HIGH (0x00000001U)
247 #define LL_PWM_WAITING_TIME_LVL_LOW (0x00000000U)
248 #define LL_PWM_WAITING_TIME_LVL_HIGH (0x00000001U)
254 #define LL_PWM_CODING_CHANNEL_ALL (0x00000000U)
255 #define LL_PWM_CODING_CHANNEL_A (0x00000001U)
261 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U)
262 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U)
268 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U)
269 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U)
270 #define LL_PWM_ACTIONEVENT_SET (0x00000002U)
271 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U)
277 #define LL_PWM_PRESCALER_UNIT (128)
278 #define LL_PWM_BREATH_PRESCALER_UNIT (128)
279 #define LL_PWM_HOLD_PRESCALER_UNIT (10)
289 #define LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG \
292 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
293 .flickerstop_lvl = LL_PWM_STOP_LVL_LOW, \
299 #define LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG \
303 .ll_drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
304 .ll_waiting_time_lvl = LL_PWM_WAITING_TIME_LVL_LOW, \
310 #define LL_PWM_NONE_CODING_DEFAULT_CONFIG \
312 .align = LL_PWM_EDGE_ALIGNED, \
313 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
314 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
315 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
316 .breathstop_lvl = LL_PWM_STOP_LVL_LOW, \
317 .channel_a = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
318 .channel_b = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
319 .channel_c = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
325 #define LL_PWM_CODING_DEFAULT_CONFIG \
328 .ll_waiting_time = 640, \
329 .ll_data_width_valid = 0x1F, \
330 .ll_coding_channel_select = LL_PWM_CODING_CHANNEL_ALL, \
331 .ll_channel_a = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
332 .ll_channel_b = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
333 .ll_channel_c = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
339 #define LL_PWM_DEFAULT_CONFIG \
341 .ll_mode = LL_PWM_FLICKER_MODE, \
342 .ll_prd_cycles = 0x0, \
343 .none_coding_mode_cfg = LL_PWM_NONE_CODING_DEFAULT_CONFIG, \
344 .coding_mode_cfg = LL_PWM_CODING_DEFAULT_CONFIG, \
367 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
375 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
404 SET_BITS(PWMx->MODE, PWM_MODE_EN);
419 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
434 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
449 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
464 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
479 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
499 #ifdef HAL_PWM_FEATURE_LEGACY
502 MODIFY_REG(PWMx->MODE, PWM_MODE_CODINGEN, 0x1 << PWM_MODE_CODINGEN_POS);
504 CLEAR_BITS(PWMx->MODE, PWM_MODE_CODINGEN);
506 (0x1 << PWM_MODE_BREATHEN_POS) : (0x0 << PWM_MODE_BREATHEN_POS));
525 if(READ_BITS(PWMx->MODE, PWM_MODE_CODINGEN) == PWM_MODE_CODINGEN) {
544 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
559 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
574 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
589 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
604 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
619 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
634 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
649 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
664 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
680 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_A_POS);
695 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A));
711 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_B_POS);
726 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B));
742 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_C_POS);
757 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C));
773 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_A_POS);
788 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A) == (PWM_MODE_WAITING_TIME_LEVEL_A));
804 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_B_POS);
819 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B) == (PWM_MODE_WAITING_TIME_LEVEL_B));
835 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_C_POS);
850 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C) == (PWM_MODE_WAITING_TIME_LEVEL_C));
865 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x1 << PWM_MODE_DMA_EN_POS);
880 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x0 << PWM_MODE_DMA_EN_POS);
895 return (READ_BITS(PWMx->MODE, PWM_MODE_DMA_EN) == (PWM_MODE_DMA_EN));
911 MODIFY_REG(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT, coding_channel << PWM_MODE_CODING_CHANNEL_SELECT_POS);
926 return (READ_BITS(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT) == (PWM_MODE_CODING_CHANNEL_SELECT));
941 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
956 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
971 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
986 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
1001 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
1016 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
1031 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
1046 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1061 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1076 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
1091 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1106 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1121 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
1136 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1151 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1166 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
1181 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1196 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1211 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
1226 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1241 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1256 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
1271 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1286 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1301 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
1316 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1331 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1346 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
1361 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1376 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1391 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1406 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1421 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1436 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1452 WRITE_REG(PWMx->PRD, prescaler);
1467 return (READ_REG(PWMx->PRD));
1483 WRITE_REG(PWMx->CMPA0, compare);
1498 return (READ_REG(PWMx->CMPA0));
1514 WRITE_REG(PWMx->CMPA1, compare);
1529 return (READ_REG(PWMx->CMPA1));
1545 WRITE_REG(PWMx->CMPB0, compare);
1560 return (READ_REG(PWMx->CMPB0));
1576 WRITE_REG(PWMx->CMPB1, compare);
1591 return (READ_REG(PWMx->CMPB1));
1607 WRITE_REG(PWMx->CMPC0, compare);
1622 return (READ_REG(PWMx->CMPC0));
1638 WRITE_REG(PWMx->CMPC1, compare);
1653 return (READ_REG(PWMx->CMPC1));
1673 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_POS);
1692 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_POS);
1712 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_POS);
1731 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_POS);
1751 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_POS);
1770 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_POS);
1790 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_POS);
1809 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_POS);
1829 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_POS);
1848 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_POS);
1868 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_POS);
1887 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_POS);
1903 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1918 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1934 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1949 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1965 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL, breathstop_lvl << PWM_MODE_BREATH_PAUSE_LEVEL_POS);
1980 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL));
1996 WRITE_REG(PWMx->PRD_CYCLES, prd_cycles);
2011 return (READ_REG(PWMx->PRD_CYCLES));
2027 WRITE_REG(PWMx->WAIT_TIME, waiting_time);
2042 return (READ_REG(PWMx->WAIT_TIME));
2059 MODIFY_REG(PWMx->DATA_WIDTH_VALID, PWM_DATA_WIDTH_VALID, data_valid_width << PWM_DATA_WIDTH_VALID_POS);
2074 return (uint8_t)(READ_REG(PWMx->DATA_WIDTH_VALID) & PWM_DATA_WIDTH_VALID);
2090 WRITE_REG(PWMx->CODING_DATA, coding_data);
2105 return (READ_REG(PWMx->CODING_DATA));
2120 return (READ_REG(PWMx->CODING_STATUS));
2135 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_A_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_A_ERROR_CLR_POS);
2150 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_A_ERROR) == (PWM_CODING_STATUS_CODING_A_ERROR));
2165 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_B_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_B_ERROR_CLR_POS);
2180 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_B_ERROR) == (PWM_CODING_STATUS_CODING_B_ERROR));
2195 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_C_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_C_ERROR_CLR_POS);
2210 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_C_ERROR) == (PWM_CODING_STATUS_CODING_C_ERROR));
2225 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_DONE_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_DONE_CLR_POS);
2240 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_DONE) == (PWM_CODING_STATUS_CODING_DONE));
2255 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_LOAD_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_LOAD_CLR_POS);
2270 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_LOAD) == (PWM_CODING_STATUS_CODING_LOAD));
2285 return ((uint32_t) &(PWMx->CODING_DATA));
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, ll_pwm_mode_t mode)
Set PWM mode.
__STATIC_INLINE uint32_t ll_pwm_get_prd_cycles(pwm_regs_t *PWMx)
Get the number of PWM period cycle.
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
Get the channel_c stop level in flicker mode.
__STATIC_INLINE uint8_t ll_pwm_get_dma_en(pwm_regs_t *PWMx)
Get DMA enable or disable.
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
__STATIC_INLINE uint32_t ll_pwm_get_coding_status(pwm_regs_t *PWMx)
Get pwm coding status.
__STATIC_INLINE uint32_t ll_pwm_dma_get_register_address(pwm_regs_t *PWMx)
Get the coding data register address used for DMA transfer.
__STATIC_INLINE void ll_pwm_set_data_width_valid(pwm_regs_t *PWMx, uint8_t data_valid_width)
Set the valid coding data width in coding mode.
LL PWM init Structure definition.
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
__STATIC_INLINE void ll_pwm_set_dma_disable(pwm_regs_t *PWMx)
Set DMA disable in coding mode.
struct _ll_pwm_none_coding_mode_init_t ll_pwm_none_coding_mode_init_t
LL PWM none coding mode Structure definition.
__STATIC_INLINE uint32_t ll_pwm_get_waiting_time(pwm_regs_t *PWMx)
Get the waiting time count.
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
ll_pwm_none_coding_channel_init_t channel_c
__STATIC_INLINE uint8_t ll_pwm_get_coding_c_error_status(pwm_regs_t *PWMx)
Get pwmc coding error status.
ll_pwm_none_coding_mode_init_t none_coding_mode_cfg
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
__STATIC_INLINE uint8_t ll_pwm_get_coding_done_status(pwm_regs_t *PWMx)
Get PWM conding done status.
__STATIC_INLINE void ll_pwm_set_waiting_time_level_a(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_a waiting time level in coding mode.
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
uint8_t ll_drive_polarity
struct _ll_pwm_coding_channel_init_t ll_pwm_coding_channel_init_t
LL PWM Output Channel init Structure definition.
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
__STATIC_INLINE void ll_pwm_clr_coding_b_error_status(pwm_regs_t *PWMx)
Clear pwmb coding error status.
__STATIC_INLINE uint8_t ll_pwm_get_data_width_valid(pwm_regs_t *PWMx)
Get the valid coding data width.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
ll_pwm_coding_mode_init_t coding_mode_cfg
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
__STATIC_INLINE ll_pwm_mode_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
void ll_pwm_init(pwm_regs_t *PWMx, const ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
__STATIC_INLINE void ll_pwm_set_coding_data(pwm_regs_t *PWMx, uint32_t coding_data)
Set the PWM coding data in coding mode.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
LL PWM none coding mode Structure definition.
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
ll_pwm_coding_channel_init_t ll_channel_a
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
__STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
Set the stop level in breath mode.
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_b stop level in flicker mode.
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
__STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
Get the stop level in breath mode.
__STATIC_INLINE void ll_pwm_clr_coding_done_status(pwm_regs_t *PWMx)
Clear coding done status.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
uint8_t ll_waiting_time_lvl
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
__STATIC_INLINE uint8_t ll_pwm_get_coding_a_error_status(pwm_regs_t *PWMx)
Get pwma coding error status.
uint8_t ll_coding_channel_select
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
__STATIC_INLINE void ll_pwm_set_prd_cycles(pwm_regs_t *PWMx, uint32_t prd_cycles)
Set the number of PWM period cycle in flicker mode or coding mode.
struct _ll_pwm_none_coding_channel_init_t ll_pwm_none_coding_channel_init_t
LL PWM Output Channel init Structure definition.
__STATIC_INLINE uint32_t ll_pwm_get_coding_data(pwm_regs_t *PWMx)
Get the PWM coding data in coding mode.
uint8_t ll_data_width_valid
__STATIC_INLINE uint8_t ll_pwm_get_coding_load_status(pwm_regs_t *PWMx)
Get PWM conding load status.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
__STATIC_INLINE void ll_pwm_set_waiting_time(pwm_regs_t *PWMx, uint32_t waiting_time)
Set the waiting time count in coding mode.
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_b(pwm_regs_t *PWMx)
Get the channel_b waiting time level in coding mode.
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_c stop level in flicker mode.
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
__STATIC_INLINE void ll_pwm_set_waiting_time_level_c(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_c waiting time level in coding mode.
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
__STATIC_INLINE void ll_pwm_clr_coding_load_status(pwm_regs_t *PWMx)
Clear coding load status.
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
LL PWM Output Channel init Structure definition.
ll_pwm_none_coding_channel_init_t channel_a
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
Get the channel_a stop level in flicker mode.
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_c(pwm_regs_t *PWMx)
Get the channel_c waiting time level in coding mode.
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_a stop level in flicker mode.
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
LL PWM Output Channel init Structure definition.
LL PWM coding mode Structure definition.
__STATIC_INLINE void ll_pwm_set_waiting_time_level_b(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_b waiting time level in coding mode.
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
ll_pwm_coding_channel_init_t ll_channel_b
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
Get the channel_b stop level in flicker mode.
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_a(pwm_regs_t *PWMx)
Get the channel_a waiting time level in coding mode.
ll_pwm_coding_channel_init_t ll_channel_c
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
__STATIC_INLINE void ll_pwm_set_dma_enable(pwm_regs_t *PWMx)
Set DMA enable in coding mode.
__STATIC_INLINE void ll_pwm_clr_coding_c_error_status(pwm_regs_t *PWMx)
Clear pwmc coding error status.
__STATIC_INLINE uint8_t ll_pwm_get_coding_b_error_status(pwm_regs_t *PWMx)
Get pwmb coding error status.
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
ll_pwm_none_coding_channel_init_t channel_b
void ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
__STATIC_INLINE void ll_pwm_clr_coding_a_error_status(pwm_regs_t *PWMx)
Clear pwma coding error status.
__STATIC_INLINE void ll_pwm_coding_channel_select(pwm_regs_t *PWMx, uint8_t coding_channel)
Choose 3 channels operation in coding mode or only choose channel A operation in coding mode.
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
struct _ll_pwm_coding_mode_init_t ll_pwm_coding_mode_init_t
LL PWM coding mode Structure definition.
__STATIC_INLINE uint8_t ll_pwm_get_coding_channel(pwm_regs_t *PWMx)
Get PWM coding channel.