gr55xx_ll_msio.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_msio_init
77 {
78 uint32_t pin;
81 uint32_t direction;
86 uint32_t mode;
91 uint32_t pull;
96 uint32_t mux;
102 } ll_msio_init_t;
103
113 /* Exported constants --------------------------------------------------------*/
121 #define LL_MSIO_PIN_0 ((uint32_t)0x01U)
122 #define LL_MSIO_PIN_1 ((uint32_t)0x02U)
123 #define LL_MSIO_PIN_2 ((uint32_t)0x04U)
124 #define LL_MSIO_PIN_3 ((uint32_t)0x08U)
125 #define LL_MSIO_PIN_4 ((uint32_t)0x10U)
126 #define LL_MSIO_PIN_ALL ((uint32_t)0x1FU)
132 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U)
133 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U)
134 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U)
135 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U)
141 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U)
142 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U)
148 #define LL_MSIO_PULL_NO ((uint32_t)0x0U)
149 #define LL_MSIO_PULL_UP ((uint32_t)0x1U)
150 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U)
156 #define LL_MSIO_MUX_0 ((uint32_t)0x0U)
157 #define LL_MSIO_MUX_1 ((uint32_t)0x1U)
158 #define LL_MSIO_MUX_2 ((uint32_t)0x2U)
159 #define LL_MSIO_MUX_3 ((uint32_t)0x3U)
160 #define LL_MSIO_MUX_4 ((uint32_t)0x4U)
161 #define LL_MSIO_MUX_5 ((uint32_t)0x5U)
162 #define LL_MSIO_MUX_6 ((uint32_t)0x6U)
163 #define LL_MSIO_MUX_7 ((uint32_t)0x7U)
168 /* Exported macro ------------------------------------------------------------*/
169
184 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
185
192 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
193
198 /* Private types -------------------------------------------------------------*/
199 /* Private variables ---------------------------------------------------------*/
200 /* Private constants ---------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
213 #define LL_MSIO_DEFAULT_CONFIG \
214 { \
215 .pin = LL_MSIO_PIN_ALL, \
216 .direction = LL_MSIO_DIRECTION_INPUT, \
217 .mode = LL_MSIO_MODE_DIGITAL, \
218 .pull = LL_MSIO_PULL_DOWN, \
219 .mux = LL_MSIO_MUX_7, \
220 }
221
227 /* Exported functions --------------------------------------------------------*/
258 __STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
259 {
260 uint32_t oe_mask = (pin_mask << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
261 uint32_t ie_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
262 if (direction != LL_MSIO_DIRECTION_NONE)
263 {
264 if (direction != LL_MSIO_DIRECTION_INOUT)
265 MODIFY_REG(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask), (direction != LL_MSIO_DIRECTION_INPUT) ? ie_mask : oe_mask);
266 else
267 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
268 }
269 else
270 SET_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
271 }
272
295 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
296 {
297 uint32_t oe_mask = (pin << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
298 uint32_t ie_mask = (pin << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
299 uint32_t mask = READ_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
300 if (mask == (ie_mask | oe_mask))
301 return LL_MSIO_DIRECTION_NONE;
302 else
303 {
304 if (mask == 0)
305 return LL_MSIO_DIRECTION_INOUT;
306 else
307 return ((mask == ie_mask) ? LL_MSIO_DIRECTION_OUTPUT : LL_MSIO_DIRECTION_INPUT);
308 }
309 }
310
330 __STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
331 {
332 uint32_t ae_mask = (pin_mask << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
333 uint32_t ae_n = (mode != LL_MSIO_MODE_DIGITAL) ? 0U : ae_mask;
334 GLOBAL_EXCEPTION_DISABLE();
335 MODIFY_REG(AON->MSIO_PAD_CFG_1, ae_mask, ae_n);
336 GLOBAL_EXCEPTION_ENABLE();
337 }
338
358 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
359 {
360 uint32_t ae_mask = (pin << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
361 return ((READ_BITS(AON->MSIO_PAD_CFG_1, ae_mask) == ae_mask) ? LL_MSIO_MODE_DIGITAL : LL_MSIO_MODE_ANALOG);
362 }
363
385 __STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
386 {
387 if (pull != LL_MSIO_PULL_NO)
388 {
389 uint32_t rtype_mask = (pin_mask << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
390 uint32_t rtype = (pull != LL_MSIO_PULL_UP) ? 0U : rtype_mask;
391 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
392 GLOBAL_EXCEPTION_DISABLE();
393 MODIFY_REG(AON->MSIO_PAD_CFG_1, rtype_mask, rtype);
394 GLOBAL_EXCEPTION_ENABLE();
395 }
396 else
397 {
398 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
399 }
400 }
401
422 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
423 {
424 if (READ_BITS(AON->MSIO_PAD_CFG_0, (pin << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N))
425 {
426 return LL_MSIO_PULL_NO;
427 }
428 else
429 {
430 uint32_t rtype_mask = (pin << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
431 return ((READ_BITS(AON->MSIO_PAD_CFG_1, rtype_mask) != RESET) ? LL_MSIO_PULL_UP : LL_MSIO_PULL_DOWN);
432 }
433 }
434
462 __STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
463 {
464 uint32_t pos = POSITION_VAL(pin) << 2;
465 if(LL_MSIO_MUX_7 == mux)
466 {
467 GLOBAL_EXCEPTION_DISABLE();
468 CLEAR_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
469 GLOBAL_EXCEPTION_ENABLE();
470 }
471 else
472 {
473 MODIFY_REG(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos, mux << pos);
474 GLOBAL_EXCEPTION_DISABLE();
475 SET_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
476 GLOBAL_EXCEPTION_ENABLE();
477 }
478 }
479
504 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
505 {
506 if(READ_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos))
507 {
508 uint32_t pos = POSITION_VAL(pin) << 2;
509 return (READ_BITS(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos) >> pos);
510 }
511 else
512 {
513 return LL_MSIO_MUX_7;
514 }
515 }
516
532 __STATIC_INLINE uint32_t ll_msio_read_input_port(void)
533 {
534 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, MCU_SUB_MSIO_REG0_MSIO_C));
535 }
536
553 __STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
554 {
555 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, pin_mask) == pin_mask);
556 }
557
568 __STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
569 {
570 MODIFY_REG(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN, (port_value << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
571 }
572
582 __STATIC_INLINE uint32_t ll_msio_read_output_port(void)
583 {
584 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN) >> AON_MSIO_PAD_CFG_0_IN_Pos);
585 }
586
603 __STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
604 {
605 pin_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN;
606 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, pin_mask) == pin_mask);
607 }
608
625 __STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
626 {
627 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
628 }
629
646 __STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
647 {
648 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
649 }
650
667 __STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
668 {
669 WRITE_REG(AON->MSIO_PAD_CFG_0, (READ_REG(AON->MSIO_PAD_CFG_0) ^ ((pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN)));
670 }
671
684 error_status_t ll_msio_deinit(void);
685
695 error_status_t ll_msio_init(ll_msio_init_t *p_msio_init);
696
703 void ll_msio_struct_init(ll_msio_init_t *p_msio_init);
704
709 #endif /* AON */
710
711 #ifdef __cplusplus
712 }
713 #endif
714
715 #endif /* __GR55XX_LL_MSIO_H__ */
716
_ll_msio_init::mux
uint32_t mux
Definition: gr55xx_ll_msio.h:96
ll_msio_set_pin_direction
__STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
Set several MSIO pins to input/output direction.
Definition: gr55xx_ll_msio.h:258
ll_msio_get_pin_direction
__STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
Return gpio direction for a MSIO pin.
Definition: gr55xx_ll_msio.h:295
LL_MSIO_MODE_ANALOG
#define LL_MSIO_MODE_ANALOG
Definition: gr55xx_ll_msio.h:141
LL_MSIO_MODE_DIGITAL
#define LL_MSIO_MODE_DIGITAL
Definition: gr55xx_ll_msio.h:142
ll_msio_read_input_port
__STATIC_INLINE uint32_t ll_msio_read_input_port(void)
Return full input data register value of MSIO.
Definition: gr55xx_ll_msio.h:532
LL_MSIO_PULL_DOWN
#define LL_MSIO_PULL_DOWN
Definition: gr55xx_ll_msio.h:150
ll_msio_toggle_pin
__STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified MSIO pins.
Definition: gr55xx_ll_msio.h:667
ll_msio_set_pin_mode
__STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several MSIO pins to analog/digital mode.
Definition: gr55xx_ll_msio.h:330
ll_msio_init_t
struct _ll_msio_init ll_msio_init_t
LL MSIO init Structure definition.
ll_msio_get_pin_pull
__STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:422
ll_msio_get_pin_mode
__STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
Return gpio mode for a MSIO pin.
Definition: gr55xx_ll_msio.h:358
_ll_msio_init::mode
uint32_t mode
Definition: gr55xx_ll_msio.h:86
LL_MSIO_PULL_NO
#define LL_MSIO_PULL_NO
Definition: gr55xx_ll_msio.h:148
ll_msio_reset_output_pin
__STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
Set specified MSIO pins to low level.
Definition: gr55xx_ll_msio.h:646
ll_msio_set_output_pin
__STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
Set specified MSIO pins to high level.
Definition: gr55xx_ll_msio.h:625
LL_MSIO_MUX_7
#define LL_MSIO_MUX_7
Definition: gr55xx_ll_msio.h:163
LL_MSIO_DIRECTION_INOUT
#define LL_MSIO_DIRECTION_INOUT
Definition: gr55xx_ll_msio.h:135
LL_MSIO_DIRECTION_INPUT
#define LL_MSIO_DIRECTION_INPUT
Definition: gr55xx_ll_msio.h:133
ll_msio_get_pin_mux
__STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:504
ll_msio_set_pin_pull
__STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:385
_ll_msio_init::direction
uint32_t direction
Definition: gr55xx_ll_msio.h:81
ll_msio_write_output_port
__STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
Write output data register of MSIO.
Definition: gr55xx_ll_msio.h:568
ll_msio_read_output_port
__STATIC_INLINE uint32_t ll_msio_read_output_port(void)
Return full output data register value of MSIO.
Definition: gr55xx_ll_msio.h:582
ll_msio_init
error_status_t ll_msio_init(ll_msio_init_t *p_msio_init)
Initialize MSIO registers according to the specified. parameters in p_msio_init.
ll_msio_struct_init
void ll_msio_struct_init(ll_msio_init_t *p_msio_init)
Set each field of a ll_msio_init_t type structure to default value.
LL_MSIO_DIRECTION_OUTPUT
#define LL_MSIO_DIRECTION_OUTPUT
Definition: gr55xx_ll_msio.h:134
LL_MSIO_PULL_UP
#define LL_MSIO_PULL_UP
Definition: gr55xx_ll_msio.h:149
ll_msio_deinit
error_status_t ll_msio_deinit(void)
De-initialize MSIO registers (Registers restored to their default values).
_ll_msio_init
LL MSIO init Structure definition.
Definition: gr55xx_ll_msio.h:77
_ll_msio_init::pin
uint32_t pin
Definition: gr55xx_ll_msio.h:78
ll_msio_is_input_pin_set
__STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:553
_ll_msio_init::pull
uint32_t pull
Definition: gr55xx_ll_msio.h:91
ll_msio_is_output_pin_set
__STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:603
LL_MSIO_DIRECTION_NONE
#define LL_MSIO_DIRECTION_NONE
Definition: gr55xx_ll_msio.h:132
ll_msio_set_pin_mux
__STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:462