gr55xx_hal_dma.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_dma.h"
61 #include "gr55xx_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
75 typedef enum
76 {
77 HAL_DMA_STATE_RESET = 0x00U,
78 HAL_DMA_STATE_READY = 0x01U,
79 HAL_DMA_STATE_BUSY = 0x02U,
80 HAL_DMA_STATE_TIMEOUT = 0x03U,
81 HAL_DMA_STATE_ERROR = 0x04U,
82 } hal_dma_state_t;
92 typedef enum
93 {
94 DMA_Channel0 = 0U,
95 DMA_Channel1 = 1U,
96 DMA_Channel2 = 2U,
97 DMA_Channel3 = 3U,
98 DMA_Channel4 = 4U,
99 DMA_Channel5 = 5U,
100 DMA_Channel6 = 6U,
101 DMA_Channel7 = 7U,
102 } dma_channel_t;
112 typedef enum
113 {
114 HAL_DMA_XFER_TFR_CB_ID = 0x00,
115 HAL_DMA_XFER_BLK_CB_ID = 0x01,
116 HAL_DMA_XFER_ERROR_CB_ID = 0x02,
117 HAL_DMA_XFER_ABORT_CB_ID = 0x03,
118 HAL_DMA_XFER_ALL_CB_ID = 0x04
119 } hal_dma_callback_id_t;
136 typedef struct _dma_init
137 {
138 uint32_t src_request;
141 uint32_t dst_request;
144 uint32_t direction;
148 uint32_t src_increment;
151 uint32_t dst_increment;
154 uint32_t src_data_alignment;
157 uint32_t dst_data_alignment;
160 uint32_t mode;
165 uint32_t priority;
167 } dma_init_t;
168
178 typedef struct _dma_handle
179 {
180 dma_channel_t channel;
182 dma_init_t init;
184 hal_lock_t lock;
186 __IO hal_dma_state_t state;
188 void *p_parent;
190 void (* xfer_tfr_callback)(struct _dma_handle *p_dma);
192 void (* xfer_blk_callback)(struct _dma_handle *p_dma);
194 void (* xfer_error_callback)(struct _dma_handle *p_dma);
196 void (* xfer_abort_callback)(struct _dma_handle *p_dma);
198 __IO uint32_t error_code;
200 uint32_t retention[5];
201 } dma_handle_t;
202
213 /* Exported constants --------------------------------------------------------*/
221 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
222 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
223 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U)
224 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
230 #define DMA_REQUEST_SPIM_TX LL_DMA_PERIPH_SPIM_TX
231 #define DMA_REQUEST_SPIM_RX LL_DMA_PERIPH_SPIM_RX
232 #define DMA_REQUEST_SPIS_TX LL_DMA_PERIPH_SPIS_TX
233 #define DMA_REQUEST_SPIS_RX LL_DMA_PERIPH_SPIS_RX
234 #define DMA_REQUEST_QSPI0_TX LL_DMA_PERIPH_QSPI0_TX
235 #define DMA_REQUEST_QSPI0_RX LL_DMA_PERIPH_QSPI0_RX
236 #define DMA_REQUEST_I2C0_TX LL_DMA_PERIPH_I2C0_TX
237 #define DMA_REQUEST_I2C0_RX LL_DMA_PERIPH_I2C0_RX
238 #define DMA_REQUEST_I2C1_TX LL_DMA_PERIPH_I2C1_TX
239 #define DMA_REQUEST_I2C1_RX LL_DMA_PERIPH_I2C1_RX
240 #define DMA_REQUEST_I2S_S_TX LL_DMA_PERIPH_I2S_S_TX
241 #define DMA_REQUEST_I2S_S_RX LL_DMA_PERIPH_I2S_S_RX
242 #define DMA_REQUEST_UART0_TX LL_DMA_PERIPH_UART0_TX
243 #define DMA_REQUEST_UART0_RX LL_DMA_PERIPH_UART0_RX
244 #define DMA_REQUEST_QSPI1_TX LL_DMA_PERIPH_QSPI1_TX
245 #define DMA_REQUEST_QSPI1_RX LL_DMA_PERIPH_QSPI1_RX
246 #define DMA_REQUEST_I2S_M_TX LL_DMA_PERIPH_I2S_M_TX
247 #define DMA_REQUEST_I2S_M_RX LL_DMA_PERIPH_I2S_M_RX
248 #define DMA_REQUEST_SNSADC LL_DMA_PERIPH_SNSADC
249 #define DMA_REQUEST_MEM LL_DMA_PERIPH_MEM
255 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
256 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
257 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
258 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH
264 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT
265 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT
266 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE
272 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT
273 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT
274 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE
280 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE
281 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD
282 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD
288 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE
289 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD
290 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD
296 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK
297 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
304 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0
305 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_2
306 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_5
307 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_7
312 /* Private macros ------------------------------------------------------------*/
313
321 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
322 ((__instance__) == DMA_Channel1) || \
323 ((__instance__) == DMA_Channel2) || \
324 ((__instance__) == DMA_Channel3) || \
325 ((__instance__) == DMA_Channel4) || \
326 ((__instance__) == DMA_Channel5) || \
327 ((__instance__) == DMA_Channel6) || \
328 ((__instance__) == DMA_Channel7))
329
334 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA_REQUEST_SPIM_TX) || \
335 ((__REQUEST__) == DMA_REQUEST_SPIM_RX) || \
336 ((__REQUEST__) == DMA_REQUEST_SPIS_TX) || \
337 ((__REQUEST__) == DMA_REQUEST_SPIS_RX) || \
338 ((__REQUEST__) == DMA_REQUEST_QSPI0_TX) || \
339 ((__REQUEST__) == DMA_REQUEST_QSPI0_RX) || \
340 ((__REQUEST__) == DMA_REQUEST_I2C0_TX) || \
341 ((__REQUEST__) == DMA_REQUEST_I2C0_RX) || \
342 ((__REQUEST__) == DMA_REQUEST_I2C1_TX) || \
343 ((__REQUEST__) == DMA_REQUEST_I2C1_RX) || \
344 ((__REQUEST__) == DMA_REQUEST_I2S_S_TX) || \
345 ((__REQUEST__) == DMA_REQUEST_I2S_S_RX) || \
346 ((__REQUEST__) == DMA_REQUEST_UART0_TX) || \
347 ((__REQUEST__) == DMA_REQUEST_UART0_RX) || \
348 ((__REQUEST__) == DMA_REQUEST_QSPI1_TX) || \
349 ((__REQUEST__) == DMA_REQUEST_QSPI1_RX) || \
350 ((__REQUEST__) == DMA_REQUEST_I2S_M_TX) || \
351 ((__REQUEST__) == DMA_REQUEST_I2S_M_RX) || \
352 ((__REQUEST__) == DMA_REQUEST_SNSADC) || \
353 ((__REQUEST__) == DMA_REQUEST_MEM))
354
359 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
360 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
361 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
362 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
363
368 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF))
369
374 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
375 ((__STATE__) == DMA_SRC_DECREMENT) || \
376 ((__STATE__) == DMA_SRC_NO_CHANGE))
377
382 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
383 ((__STATE__) == DMA_DST_DECREMENT) || \
384 ((__STATE__) == DMA_DST_NO_CHANGE))
385
390 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
391 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
392 ((__SIZE__) == DMA_SDATAALIGN_WORD))
393
398 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
399 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
400 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
401
406 #define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_NORMAL ) || \
407 ((__MODE__) == DMA_CIRCULAR))
408
413 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
414 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
415 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
416 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
417
422 /* Exported functions --------------------------------------------------------*/
459 hal_status_t hal_dma_init(dma_handle_t *p_dma);
460
473 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
474
512 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
513
529 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
530
543 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
544
557 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
558
572 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
573
588 void hal_dma_irq_handler(dma_handle_t *p_dma);
589
608 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void (* callback)( dma_handle_t * p_dma));
609
628 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
629
661 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
662
672 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
673
685 hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma);
686
699 hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma);
700
705 #ifdef __cplusplus
706 }
707 #endif
708
709 #endif /* __GR55xx_HAL_DMA_H__*/
710
DMA_Channel4
@ DMA_Channel4
Definition: gr55xx_hal_dma.h:98
HAL_DMA_XFER_TFR_CB_ID
@ HAL_DMA_XFER_TFR_CB_ID
Definition: gr55xx_hal_dma.h:114
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
hal_dma_get_error
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA_Channel1
@ DMA_Channel1
Definition: gr55xx_hal_dma.h:95
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition: gr55xx_hal_dma.h:80
_dma_init
DMA Configuration Structure definition.
Definition: gr55xx_hal_dma.h:137
_dma_handle::error_code
__IO uint32_t error_code
Definition: gr55xx_hal_dma.h:198
DMA_Channel0
@ DMA_Channel0
Definition: gr55xx_hal_dma.h:94
dma_handle_t
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
hal_dma_state_t
HAL DMA State Enumerations definition.
Definition: gr55xx_hal_dma.h:76
hal_dma_start_it
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled.
hal_dma_abort_it
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: gr55xx_hal_dma.h:78
_dma_init::dst_increment
uint32_t dst_increment
Definition: gr55xx_hal_dma.h:151
DMA_Channel5
@ DMA_Channel5
Definition: gr55xx_hal_dma.h:99
_dma_handle::init
dma_init_t init
Definition: gr55xx_hal_dma.h:182
DMA_Channel2
@ DMA_Channel2
Definition: gr55xx_hal_dma.h:96
hal_dma_irq_handler
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
_dma_handle::xfer_blk_callback
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
Definition: gr55xx_hal_dma.h:192
hal_dma_suspend_reg
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
_dma_handle::retention
uint32_t retention[5]
Definition: gr55xx_hal_dma.h:200
gr55xx_ll_dma.h
Header file containing functions prototypes of DMA LL library.
_dma_init::priority
uint32_t priority
Definition: gr55xx_hal_dma.h:165
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: gr55xx_hal_dma.h:117
hal_dma_register_callback
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: gr55xx_hal_dma.h:118
_dma_init::dst_request
uint32_t dst_request
Definition: gr55xx_hal_dma.h:141
hal_dma_poll_for_transfer
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
DMA_Channel6
@ DMA_Channel6
Definition: gr55xx_hal_dma.h:100
hal_dma_start
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
hal_dma_resume_reg
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep. This function must be used in conjun...
_dma_handle::state
__IO hal_dma_state_t state
Definition: gr55xx_hal_dma.h:186
hal_dma_init
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
_dma_handle::xfer_error_callback
void(* xfer_error_callback)(struct _dma_handle *p_dma)
Definition: gr55xx_hal_dma.h:194
HAL_DMA_XFER_BLK_CB_ID
@ HAL_DMA_XFER_BLK_CB_ID
Definition: gr55xx_hal_dma.h:115
hal_dma_callback_id_t
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
Definition: gr55xx_hal_dma.h:113
DMA_Channel3
@ DMA_Channel3
Definition: gr55xx_hal_dma.h:97
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: gr55xx_hal_dma.h:81
_dma_handle::xfer_tfr_callback
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
Definition: gr55xx_hal_dma.h:190
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: gr55xx_hal_dma.h:79
_dma_handle::xfer_abort_callback
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
Definition: gr55xx_hal_dma.h:196
dma_init_t
struct _dma_init dma_init_t
DMA Configuration Structure definition.
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
_dma_init::direction
uint32_t direction
Definition: gr55xx_hal_dma.h:144
hal_dma_get_state
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
_dma_init::mode
uint32_t mode
Definition: gr55xx_hal_dma.h:160
DMA_Channel7
@ DMA_Channel7
Definition: gr55xx_hal_dma.h:101
hal_dma_unregister_callback
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
_dma_handle::channel
dma_channel_t channel
Definition: gr55xx_hal_dma.h:180
_dma_init::dst_data_alignment
uint32_t dst_data_alignment
Definition: gr55xx_hal_dma.h:157
_dma_handle::lock
hal_lock_t lock
Definition: gr55xx_hal_dma.h:184
_dma_handle::p_parent
void * p_parent
Definition: gr55xx_hal_dma.h:188
hal_dma_abort
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: gr55xx_hal_dma.h:116
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: gr55xx_hal_dma.h:77
_dma_init::src_request
uint32_t src_request
Definition: gr55xx_hal_dma.h:138
_dma_init::src_data_alignment
uint32_t src_data_alignment
Definition: gr55xx_hal_dma.h:154
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:179
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_dma_deinit
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr55xx_hal_dma.h:93
_dma_init::src_increment
uint32_t src_increment
Definition: gr55xx_hal_dma.h:148