gr55xx_ll_uart.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (UART0) || defined (UART1)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_uart_init_t
77 {
78 uint32_t baud_rate;
82 uint32_t data_bits;
87 uint32_t stop_bits;
92 uint32_t parity;
97 uint32_t hw_flow_ctrl;
101 } ll_uart_init_t;
102
112 /* Exported constants --------------------------------------------------------*/
121 #define LL_UART_LSR_OE UART_LSR_OE
122 #define LL_UART_LSR_PE UART_LSR_PE
123 #define LL_UART_LSR_FE UART_LSR_FE
124 #define LL_UART_LSR_BI UART_LSR_BI
125 #define LL_UART_LSR_THRE UART_LSR_THRE
126 #define LL_UART_LSR_TEMT UART_LSR_TEMT
127 #define LL_UART_LSR_RFE UART_LSR_RFE
129 #define LL_UART_IIR_MS UART_IIR_IID_MS
130 #define LL_UART_IIR_NIP UART_IIR_IID_NIP
131 #define LL_UART_IIR_THRE UART_IIR_IID_THRE
132 #define LL_UART_IIR_RDA UART_IIR_IID_RDA
133 #define LL_UART_IIR_RLS UART_IIR_IID_RLS
134 #define LL_UART_IIR_CTO UART_IIR_IID_CTO
136 #define LL_UART_USR_RFF UART_USR_RFF
137 #define LL_UART_USR_RFNE UART_USR_RFNE
138 #define LL_UART_USR_TFE UART_USR_TFE
139 #define LL_UART_USR_TFNF UART_USR_TFNF
146 #define LL_UART_IER_MS UART_IER_EDSSI
147 #define LL_UART_IER_RLS UART_IER_ERLS
148 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME)
149 #define LL_UART_IER_RDA UART_IER_ERBFI
155 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE
156 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD
157 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN
158 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0
159 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1
165 #define LL_UART_DATABITS_5B UART_LCR_DLS_5
166 #define LL_UART_DATABITS_6B UART_LCR_DLS_6
167 #define LL_UART_DATABITS_7B UART_LCR_DLS_7
168 #define LL_UART_DATABITS_8B UART_LCR_DLS_8
174 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1
175 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5
176 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2
182 #define LL_UART_HWCONTROL_NONE 0x00000000U
183 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS)
189 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U
190 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U
191 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U
192 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U
198 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U
199 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U
200 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U
201 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U
207 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U
208 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U
214 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U
215 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U
225 #define LL_UART_DEFAULT_CONFIG \
226 { \
227 .baud_rate = 9600U, \
228 .data_bits = LL_UART_DATABITS_8B, \
229 .stop_bits = LL_UART_STOPBITS_1, \
230 .parity = LL_UART_PARITY_NONE, \
231 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
232 }
233
237 /* Exported macro ------------------------------------------------------------*/
253 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
254
261 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262
276 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
277
285 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
286
293 /* Exported functions --------------------------------------------------------*/
317 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
318 {
319 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
320
321 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
322 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
323 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
324 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
325 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
326 }
327
341 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
342 {
343 register uint32_t uartdiv = 0x0U;
344 register uint32_t baud = 0x0U;
345
346 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
347 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
348 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
349
350 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
351 {
352 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
353 }
354
355 return baud;
356 }
357
374 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
375 {
376 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
377 }
378
393 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
394 {
395 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
396 }
397
415 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
416 {
417 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
418 }
419
433 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
434 {
435 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
436 }
437
459 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
460 {
461 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
462 }
463
481 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
482 {
483 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
484 }
485
522 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
523 uint32_t data_bits,
524 uint32_t parity,
525 uint32_t stop_bits)
526 {
527 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
528 }
529
545 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
546 {
547 WRITE_REG(UARTx->SRTS, pin_state);
548 }
549
564 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
565 {
566 return (uint32_t)(READ_REG(UARTx->SRTS));
567 }
568
582 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
583 {
584 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
585 }
586
597 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
598 {
599 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
600 }
601
617 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
618 {
619 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
620 }
621
635 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
636 {
637 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
638 }
639
650 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
651 {
652 WRITE_REG(UARTx->SBCR, 0x1U);
653 }
654
665 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
666 {
667 WRITE_REG(UARTx->SBCR, 0x0U);
668 }
669
680 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
681 {
682 return READ_REG(UARTx->SBCR);
683 }
684
695 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
696 {
697 WRITE_REG(UARTx->SFE, 0x1U);
698 }
699
710 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
711 {
712 WRITE_REG(UARTx->SFE, 0x0U);
713 }
714
725 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
726 {
727 return READ_REG(UARTx->SFE);
728 }
729
745 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
746 {
747 WRITE_REG(UARTx->STET, threshold);
748 }
749
764 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
765 {
766 return (uint32_t)(READ_REG(UARTx->STET));
767 }
768
784 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
785 {
786 WRITE_REG(UARTx->SRT, threshold);
787 }
788
803 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
804 {
805 return (uint32_t)(READ_REG(UARTx->SRT));
806 }
807
818 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
819 {
820 return (uint32_t)(READ_REG(UARTx->TFL));
821 }
822
833 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
834 {
835 return (uint32_t)(READ_REG(UARTx->RFL));
836 }
837
848 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
849 {
850 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
851 }
852
863 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
864 {
865 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
866 }
867
881 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
882 {
883 WRITE_REG(UARTx->SRR, UART_SRR_UR);
884 }
885
902 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
903 {
904 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
905 }
906
917 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
918 {
919 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
920 }
921
933 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
934 {
935 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
936 }
937
948 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
949 {
950 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
951 }
952
963 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
964 {
965 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
966 }
967
978 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
979 {
980 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
981 }
982
994 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
995 {
996 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
997 }
998
1009 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1010 {
1011 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1012 }
1013
1024 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1025 {
1026 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1027 }
1028
1039 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1040 {
1041 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1042 }
1043
1055 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1056 {
1057 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1058 }
1059
1071 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1072 {
1073 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1074 }
1075
1095 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1096 {
1097 SET_BITS(UARTx->DLH_IER.IER, mask);
1098 }
1099
1119 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1120 {
1121 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1122 }
1123
1143 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1144 {
1145 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1146 }
1147
1179 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1180 {
1181 return ((uint32_t)READ_REG(UARTx->LSR));
1182 }
1183
1199 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1200 {
1201 __IO uint32_t tmpreg;
1202 tmpreg = READ_REG(UARTx->LSR);
1203 (void) tmpreg;
1204 }
1205
1216 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1217 {
1218 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1219 }
1220
1231 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1232 {
1233 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1234 }
1235
1246 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1247 {
1248 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1249 }
1250
1261 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1262 {
1263 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1264 }
1265
1285 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1286 {
1287 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1288 }
1289
1308 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1309 {
1310 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1311 }
1312
1329 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1330 {
1331 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1332 }
1333
1345 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1346 {
1347 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1348 }
1349
1363 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1364
1375 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1376
1383 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1384
1389 #endif /* UART0 || UART1 */
1390
1391 #ifdef __cplusplus
1392 }
1393 #endif
1394
1395 #endif /* __GR55xx_LL_UART_H__ */
1396
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1231
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1024
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: gr55xx_ll_uart.h:545
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: gr55xx_ll_uart.h:680
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:994
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: gr55xx_ll_uart.h:415
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: gr55xx_ll_uart.h:317
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: gr55xx_ll_uart.h:725
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:933
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_uart.h:1308
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:902
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: gr55xx_ll_uart.h:459
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1009
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: gr55xx_ll_uart.h:285
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_uart.h:818
_ll_uart_init_t
LL UART init Structure definition.
Definition: gr55xx_ll_uart.h:77
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:803
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: gr55xx_ll_uart.h:564
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:917
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: gr55xx_ll_uart.h:665
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1055
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1216
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1095
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1179
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: gr55xx_ll_uart.h:650
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:710
ll_uart_init
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: gr55xx_ll_uart.h:393
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: gr55xx_ll_uart.h:582
_ll_uart_init_t::data_bits
uint32_t data_bits
Definition: gr55xx_ll_uart.h:82
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1039
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1199
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:948
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: gr55xx_ll_uart.h:341
_ll_uart_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_uart.h:78
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: gr55xx_ll_uart.h:1071
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1345
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1119
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:635
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:617
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:764
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:963
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:784
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: gr55xx_ll_uart.h:863
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1329
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: gr55xx_ll_uart.h:481
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: gr55xx_ll_uart.h:881
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:978
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Definition: gr55xx_ll_uart.h:87
_ll_uart_init_t::parity
uint32_t parity
Definition: gr55xx_ll_uart.h:92
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: gr55xx_ll_uart.h:833
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Definition: gr55xx_ll_uart.h:97
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1246
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: gr55xx_ll_uart.h:522
ll_uart_deinit
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:695
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:745
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: gr55xx_ll_uart.h:433
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: gr55xx_ll_uart.h:597
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1143
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1261
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: gr55xx_ll_uart.h:848
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: gr55xx_ll_uart.h:276
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: gr55xx_ll_uart.h:374
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: gr55xx_ll_uart.h:1285