Macros
DMA Private Macros
Peripheral Driver » HAL Driver » DMA » Defines

## Macros
#define | IS_DMA_ALL_INSTANCE(__instance__)
| Check if DMA channel instance is valid. More...
#define | IS_DMA_ALL_REQUEST(__REQUEST__)
| Check if DMA request is valid. More...
#define | IS_DMA_DIRECTION(__DIRECTION__)
| Check if DMA direction is valid. More...
#define | IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF))
| Check if DMA buffer size is valid. More...
#define | IS_DMA_SOURCE_INC_STATE(__STATE__)
| Check if DMA source address increment state is valid. More...
#define | IS_DMA_DESTINATION_INC_STATE(__STATE__)
| Check if DMA destination address increment state is valid. More...
#define | IS_DMA_SOURCE_DATA_SIZE(__SIZE__)
| Check if DMA source data size is valid. More...
#define | IS_DMA_DESTINATION_DATA_SIZE(__SIZE__)
| Check if DMA destination data size is valid. More...
#define | IS_DMA_MODE(__MODE__)
| Check if DMA mode is valid. More...
#define | IS_DMA_PRIORITY(__PRIORITY__)
| Check if DMA priority is valid. More...

## Detailed Description

## Macro Definition Documentation

## ◆ IS_DMA_ALL_INSTANCE

#define IS_DMA_ALL_INSTANCE | ( |  | __instance__ | ) |

Value:
(((__instance__) == DMA_Channel0) || \
((__instance__) == DMA_Channel1) || \
((__instance__) == DMA_Channel2) || \
((__instance__) == DMA_Channel3) || \
((__instance__) == DMA_Channel4) || \
((__instance__) == DMA_Channel5) || \
((__instance__) == DMA_Channel6) || \
((__instance__) == DMA_Channel7))

Check if DMA channel instance is valid.

Parameters

  <strong>instance</strong> | DMA channel instance.

Return values

  SET | (instance is valid) or RESET (instance is invalid)

## ◆ IS_DMA_ALL_REQUEST

#define IS_DMA_ALL_REQUEST | ( |  | __REQUEST__ | ) |

Value:
(((__REQUEST__) == DMA_REQUEST_SPIM_TX) || \
((__REQUEST__) == DMA_REQUEST_SPIM_RX) || \
((__REQUEST__) == DMA_REQUEST_SPIS_TX) || \
((__REQUEST__) == DMA_REQUEST_SPIS_RX) || \
((__REQUEST__) == DMA_REQUEST_QSPI0_TX) || \
((__REQUEST__) == DMA_REQUEST_QSPI0_RX) || \
((__REQUEST__) == DMA_REQUEST_I2C0_TX) || \
((__REQUEST__) == DMA_REQUEST_I2C0_RX) || \
((__REQUEST__) == DMA_REQUEST_I2C1_TX) || \
((__REQUEST__) == DMA_REQUEST_I2C1_RX) || \
((__REQUEST__) == DMA_REQUEST_I2S_S_TX) || \
((__REQUEST__) == DMA_REQUEST_I2S_S_RX) || \
((__REQUEST__) == DMA_REQUEST_UART0_TX) || \
((__REQUEST__) == DMA_REQUEST_UART0_RX) || \
((__REQUEST__) == DMA_REQUEST_QSPI1_TX) || \
((__REQUEST__) == DMA_REQUEST_QSPI1_RX) || \
((__REQUEST__) == DMA_REQUEST_I2S_M_TX) || \
((__REQUEST__) == DMA_REQUEST_I2S_M_RX) || \
((__REQUEST__) == DMA_REQUEST_SNSADC) || \
((__REQUEST__) == DMA_REQUEST_MEM))

Check if DMA request is valid.

Parameters

  <strong>REQUEST</strong> | DMA request.

Return values

  SET | (REQUEST is valid) or RESET (REQUEST is invalid)

## ◆ IS_DMA_BUFFER_SIZE

#define IS_DMA_BUFFER_SIZE | ( |  | __SIZE__ | ) | (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF))

Check if DMA buffer size is valid.

Parameters

  <strong>SIZE</strong> | DMA buffer size.

Return values

  SET | (SIZE is valid) or RESET (SIZE is invalid)

## ◆ IS_DMA_DESTINATION_DATA_SIZE

#define IS_DMA_DESTINATION_DATA_SIZE | ( |  | __SIZE__ | ) |

Value:
(((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
((__SIZE__) == DMA_DDATAALIGN_WORD ))

Check if DMA destination data size is valid.

Parameters

  <strong>SIZE</strong> | DMA destination data size.

Return values

  SET | (SIZE is valid) or RESET (SIZE is invalid)

## ◆ IS_DMA_DESTINATION_INC_STATE

#define IS_DMA_DESTINATION_INC_STATE | ( |  | __STATE__ | ) |

Value:
(((__STATE__) == DMA_DST_INCREMENT) || \
((__STATE__) == DMA_DST_DECREMENT) || \
((__STATE__) == DMA_DST_NO_CHANGE))

Check if DMA destination address increment state is valid.

Parameters

  <strong>STATE</strong> | DMA destination address increment state.

Return values

  SET | (STATE is valid) or RESET (STATE is invalid)

## ◆ IS_DMA_DIRECTION

#define IS_DMA_DIRECTION | ( |  | __DIRECTION__ | ) |

Value:
(((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))

Check if DMA direction is valid.

Parameters

  <strong>DIRECTION</strong> | DMA direction.

Return values

  SET | (DIRECTION is valid) or RESET (DIRECTION is invalid)

## ◆ IS_DMA_MODE

#define IS_DMA_MODE | ( |  | __MODE__ | ) |

Value:
(((__MODE__) == DMA_NORMAL ) || \
((__MODE__) == DMA_CIRCULAR))

Check if DMA mode is valid.

Parameters

  <strong>MODE</strong> | DMA mode.

Return values

  SET | (MODE is valid) or RESET (MODE is invalid)

## ◆ IS_DMA_PRIORITY

#define IS_DMA_PRIORITY | ( |  | __PRIORITY__ | ) |

Value:
(((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))

Check if DMA priority is valid.

Parameters

  <strong>PRIORITY</strong> | DMA priority.

Return values

  SET | (PRIORITY is valid) or RESET (PRIORITY is invalid)

## ◆ IS_DMA_SOURCE_DATA_SIZE

#define IS_DMA_SOURCE_DATA_SIZE | ( |  | __SIZE__ | ) |

Value:
(((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
((__SIZE__) == DMA_SDATAALIGN_WORD))

Check if DMA source data size is valid.

Parameters

  <strong>SIZE</strong> | DMA source data size.

Return values

  SET | (SIZE is valid) or RESET (SIZE is invalid)

## ◆ IS_DMA_SOURCE_INC_STATE

#define IS_DMA_SOURCE_INC_STATE | ( |  | __STATE__ | ) |

Value:
(((__STATE__) == DMA_SRC_INCREMENT) || \
((__STATE__) == DMA_SRC_DECREMENT) || \
((__STATE__) == DMA_SRC_NO_CHANGE))

Check if DMA source address increment state is valid.

Parameters

  <strong>STATE</strong> | DMA source address increment state.

Return values

  SET | (STATE is valid) or RESET (STATE is invalid)

DMA_Channel4
@ DMA_Channel4
Definition: gr55xx_hal_dma.h:98
DMA_PRIORITY_MEDIUM
#define DMA_PRIORITY_MEDIUM
Definition: gr55xx_hal_dma.h:305
DMA_REQUEST_SNSADC
#define DMA_REQUEST_SNSADC
Definition: gr55xx_hal_dma.h:248
DMA_SDATAALIGN_HALFWORD
#define DMA_SDATAALIGN_HALFWORD
Definition: gr55xx_hal_dma.h:281
DMA_REQUEST_SPIM_TX
#define DMA_REQUEST_SPIM_TX
Definition: gr55xx_hal_dma.h:230
DMA_Channel1
@ DMA_Channel1
Definition: gr55xx_hal_dma.h:95
DMA_REQUEST_QSPI0_TX
#define DMA_REQUEST_QSPI0_TX
Definition: gr55xx_hal_dma.h:234
DMA_REQUEST_QSPI1_TX
#define DMA_REQUEST_QSPI1_TX
Definition: gr55xx_hal_dma.h:244
DMA_Channel0
@ DMA_Channel0
Definition: gr55xx_hal_dma.h:94
DMA_REQUEST_SPIM_RX
#define DMA_REQUEST_SPIM_RX
Definition: gr55xx_hal_dma.h:231
DMA_REQUEST_I2C1_RX
#define DMA_REQUEST_I2C1_RX
Definition: gr55xx_hal_dma.h:239
DMA_REQUEST_I2C0_TX
#define DMA_REQUEST_I2C0_TX
Definition: gr55xx_hal_dma.h:236
DMA_SRC_NO_CHANGE
#define DMA_SRC_NO_CHANGE
Definition: gr55xx_hal_dma.h:266
DMA_PRIORITY_VERY_HIGH
#define DMA_PRIORITY_VERY_HIGH
Definition: gr55xx_hal_dma.h:307
DMA_REQUEST_MEM
#define DMA_REQUEST_MEM
Definition: gr55xx_hal_dma.h:249
DMA_SRC_DECREMENT
#define DMA_SRC_DECREMENT
Definition: gr55xx_hal_dma.h:265
DMA_DDATAALIGN_WORD
#define DMA_DDATAALIGN_WORD
Definition: gr55xx_hal_dma.h:290
DMA_Channel5
@ DMA_Channel5
Definition: gr55xx_hal_dma.h:99
DMA_REQUEST_QSPI0_RX
#define DMA_REQUEST_QSPI0_RX
Definition: gr55xx_hal_dma.h:235
DMA_REQUEST_I2S_M_TX
#define DMA_REQUEST_I2S_M_TX
Definition: gr55xx_hal_dma.h:246
DMA_DDATAALIGN_BYTE
#define DMA_DDATAALIGN_BYTE
Definition: gr55xx_hal_dma.h:288
DMA_REQUEST_UART0_RX
#define DMA_REQUEST_UART0_RX
Definition: gr55xx_hal_dma.h:243
DMA_Channel2
@ DMA_Channel2
Definition: gr55xx_hal_dma.h:96
DMA_REQUEST_UART0_TX
#define DMA_REQUEST_UART0_TX
Definition: gr55xx_hal_dma.h:242
DMA_PERIPH_TO_PERIPH
#define DMA_PERIPH_TO_PERIPH
Definition: gr55xx_hal_dma.h:258
DMA_REQUEST_I2S_S_TX
#define DMA_REQUEST_I2S_S_TX
Definition: gr55xx_hal_dma.h:240
DMA_REQUEST_I2C1_TX
#define DMA_REQUEST_I2C1_TX
Definition: gr55xx_hal_dma.h:238
DMA_PRIORITY_HIGH
#define DMA_PRIORITY_HIGH
Definition: gr55xx_hal_dma.h:306
DMA_REQUEST_SPIS_TX
#define DMA_REQUEST_SPIS_TX
Definition: gr55xx_hal_dma.h:232
DMA_SRC_INCREMENT
#define DMA_SRC_INCREMENT
Definition: gr55xx_hal_dma.h:264
DMA_SDATAALIGN_BYTE
#define DMA_SDATAALIGN_BYTE
Definition: gr55xx_hal_dma.h:280
DMA_DST_NO_CHANGE
#define DMA_DST_NO_CHANGE
Definition: gr55xx_hal_dma.h:274
DMA_CIRCULAR
#define DMA_CIRCULAR
Definition: gr55xx_hal_dma.h:297
DMA_REQUEST_SPIS_RX
#define DMA_REQUEST_SPIS_RX
Definition: gr55xx_hal_dma.h:233
DMA_Channel6
@ DMA_Channel6
Definition: gr55xx_hal_dma.h:100
DMA_MEMORY_TO_MEMORY
#define DMA_MEMORY_TO_MEMORY
Definition: gr55xx_hal_dma.h:255
DMA_DST_DECREMENT
#define DMA_DST_DECREMENT
Definition: gr55xx_hal_dma.h:273
DMA_SDATAALIGN_WORD
#define DMA_SDATAALIGN_WORD
Definition: gr55xx_hal_dma.h:282
DMA_Channel3
@ DMA_Channel3
Definition: gr55xx_hal_dma.h:97
DMA_Channel7
@ DMA_Channel7
Definition: gr55xx_hal_dma.h:101
DMA_PERIPH_TO_MEMORY
#define DMA_PERIPH_TO_MEMORY
Definition: gr55xx_hal_dma.h:257
DMA_PRIORITY_LOW
#define DMA_PRIORITY_LOW
Definition: gr55xx_hal_dma.h:304
DMA_REQUEST_I2S_S_RX
#define DMA_REQUEST_I2S_S_RX
Definition: gr55xx_hal_dma.h:241
DMA_REQUEST_QSPI1_RX
#define DMA_REQUEST_QSPI1_RX
Definition: gr55xx_hal_dma.h:245
DMA_NORMAL
#define DMA_NORMAL
Definition: gr55xx_hal_dma.h:296
DMA_REQUEST_I2S_M_RX
#define DMA_REQUEST_I2S_M_RX
Definition: gr55xx_hal_dma.h:247
DMA_REQUEST_I2C0_RX
#define DMA_REQUEST_I2C0_RX
Definition: gr55xx_hal_dma.h:237
DMA_MEMORY_TO_PERIPH
#define DMA_MEMORY_TO_PERIPH
Definition: gr55xx_hal_dma.h:256
DMA_DST_INCREMENT
#define DMA_DST_INCREMENT
Definition: gr55xx_hal_dma.h:272
DMA_DDATAALIGN_HALFWORD
#define DMA_DDATAALIGN_HALFWORD
Definition: gr55xx_hal_dma.h:289