gr55xx_ll_pwm.h
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1
51 #ifndef __GR55XX_LL_PWM_H__
52 #define __GR55XX_LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr55xx.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
66 /* Exported types ------------------------------------------------------------*/
74 typedef struct _ll_pwm_channel_init_t
75 {
76 uint8_t duty;
82 uint8_t drive_polarity;
88 } ll_pwm_channel_init_t;
89
93 typedef struct _ll_pwm_init_t
94 {
95 uint32_t mode;
100 uint32_t align;
103 uint32_t prescaler;
109 uint32_t bprescaler;
115 uint32_t hprescaler;
120 ll_pwm_channel_init_t channel_a;
123 ll_pwm_channel_init_t channel_b;
126 ll_pwm_channel_init_t channel_c;
129 } ll_pwm_init_t;
130
140 /* Exported constants --------------------------------------------------------*/
148 #define LL_PWM_FLICKER_MODE (0x00000000U)
149 #define LL_PWM_BREATH_MODE PWM_MODE_BREATHEN
155 #define LL_PWM_EDGE_ALIGNED (0x00000000U)
156 #define LL_PWM_CENTER_ALIGNED (0x00000001U)
162 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U)
163 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U)
169 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U)
170 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U)
171 #define LL_PWM_ACTIONEVENT_SET (0x00000002U)
172 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U)
178 #define LL_PWM_PRESCALER_UNIT (128)
179 #define LL_PWM_BREATH_PRESCALER_UNIT (128)
180 #define LL_PWM_HOLD_PRESCALER_UNIT (10)
190 #define LL_PWM_CHANNEL_DEFAULT_CONFIG \
191 { \
192 .duty = 50, \
193 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
194 }
195
199 #define LL_PWM_DEFAULT_CONFIG \
200 { \
201 .mode = LL_PWM_FLICKER_MODE, \
202 .align = LL_PWM_EDGE_ALIGNED, \
203 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
204 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
205 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
206 .channel_a = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
207 .channel_b = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
208 .channel_c = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
209 }
210
215 /* Exported macro ------------------------------------------------------------*/
231 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
232
239 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
240
247 /* Exported functions --------------------------------------------------------*/
266 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
267 {
268 SET_BITS(PWMx->MODE, PWM_MODE_EN);
269 }
270
281 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
282 {
283 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
284 }
285
296 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
297 {
298 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
299 }
300
311 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
312 {
313 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
314 }
315
326 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
327 {
328 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
329 }
330
341 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
342 {
343 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
344 }
345
359 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
360 {
361 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, mode);
362 }
363
376 __STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
377 {
378 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN));
379 }
380
391 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
392 {
393 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
394 }
395
406 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
407 {
408 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
409 }
410
421 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
422 {
423 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
424 }
425
436 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
437 {
438 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
439 }
440
451 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
452 {
453 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
454 }
455
466 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
467 {
468 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
469 }
470
481 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
482 {
483 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
484 }
485
496 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
497 {
498 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
499 }
500
511 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
512 {
513 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
514 }
515
526 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
527 {
528 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
529 }
530
541 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
542 {
543 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
544 }
545
556 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
557 {
558 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
559 }
560
571 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
572 {
573 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
574 }
575
586 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
587 {
588 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
589 }
590
601 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
602 {
603 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
604 }
605
616 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
617 {
618 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
619 }
620
631 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
632 {
633 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
634 }
635
646 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
647 {
648 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
649 }
650
661 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
662 {
663 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
664 }
665
676 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
677 {
678 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
679 }
680
691 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
692 {
693 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
694 }
695
706 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
707 {
708 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
709 }
710
721 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
722 {
723 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
724 }
725
736 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
737 {
738 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
739 }
740
751 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
752 {
753 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
754 }
755
766 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
767 {
768 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
769 }
770
781 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
782 {
783 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
784 }
785
796 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
797 {
798 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
799 }
800
811 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
812 {
813 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
814 }
815
826 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
827 {
828 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
829 }
830
841 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
842 {
843 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
844 }
845
856 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
857 {
858 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
859 }
860
871 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
872 {
873 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
874 }
875
886 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
887 {
888 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
889 }
890
901 __STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
902 {
903 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
904 }
905
916 __STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
917 {
918 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
919 }
920
931 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
932 {
933 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE) == (PWM_UPDATE_SSPAUSE));
934 }
935
946 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
947 {
948 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
949 }
950
961 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
962 {
963 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
964 }
965
976 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
977 {
978 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
979 }
980
991 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
992 {
993 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
994 }
995
1006 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1007 {
1008 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1009 }
1010
1021 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1022 {
1023 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1024 }
1025
1036 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1037 {
1038 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1039 }
1040
1051 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1052 {
1053 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1054 }
1055
1066 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1067 {
1068 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1069 }
1070
1082 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1083 {
1084 WRITE_REG(PWMx->PRD, prescaler);
1085 }
1086
1097 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1098 {
1099 return (READ_REG(PWMx->PRD));
1100 }
1101
1113 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1114 {
1115 WRITE_REG(PWMx->CMPA0, compare);
1116 }
1117
1128 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1129 {
1130 return (READ_REG(PWMx->CMPA0));
1131 }
1132
1144 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1145 {
1146 WRITE_REG(PWMx->CMPA1, compare);
1147 }
1148
1159 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1160 {
1161 return (READ_REG(PWMx->CMPA1));
1162 }
1163
1175 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1176 {
1177 WRITE_REG(PWMx->CMPB0, compare);
1178 }
1179
1190 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1191 {
1192 return (READ_REG(PWMx->CMPB0));
1193 }
1194
1206 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1207 {
1208 WRITE_REG(PWMx->CMPB1, compare);
1209 }
1210
1221 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1222 {
1223 return (READ_REG(PWMx->CMPB1));
1224 }
1225
1237 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1238 {
1239 WRITE_REG(PWMx->CMPC0, compare);
1240 }
1241
1252 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1253 {
1254 return (READ_REG(PWMx->CMPC0));
1255 }
1256
1268 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1269 {
1270 WRITE_REG(PWMx->CMPC1, compare);
1271 }
1272
1283 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1284 {
1285 return (READ_REG(PWMx->CMPC1));
1286 }
1287
1303 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1304 {
1305 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1306 }
1307
1322 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1323 {
1324 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1325 }
1326
1342 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1343 {
1344 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1345 }
1346
1361 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1362 {
1363 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1364 }
1365
1381 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1382 {
1383 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1384 }
1385
1400 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1401 {
1402 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1403 }
1404
1420 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1421 {
1422 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1423 }
1424
1439 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1440 {
1441 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1442 }
1443
1459 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1460 {
1461 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1462 }
1463
1478 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1479 {
1480 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1481 }
1482
1498 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1499 {
1500 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1501 }
1502
1517 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1518 {
1519 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1520 }
1521
1533 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1534 {
1535 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1536 }
1537
1548 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1549 {
1550 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1551 }
1552
1564 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1565 {
1566 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1567 }
1568
1579 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1580 {
1581 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1582 }
1583
1597 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
1598
1609 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
1610
1617 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
1618
1623 #endif /* PWM0 || PWM1 */
1624
1625 #ifdef __cplusplus
1626 }
1627 #endif
1628
1629 #endif /* __GR55XX_LL_PWM_H__ */
1630
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: gr55xx_ll_pwm.h:871
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: gr55xx_ll_pwm.h:466
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1237
_ll_pwm_init_t::channel_c
ll_pwm_channel_init_t channel_c
Definition: gr55xx_ll_pwm.h:126
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1381
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1252
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1268
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1113
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1517
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: gr55xx_ll_pwm.h:94
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: gr55xx_ll_pwm.h:1051
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: gr55xx_ll_pwm.h:736
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: gr55xx_ll_pwm.h:541
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1097
ll_pwm_init
error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1128
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1548
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: gr55xx_ll_pwm.h:1006
ll_pwm_deinit
error_status_t ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
_ll_pwm_channel_init_t::drive_polarity
uint8_t drive_polarity
Definition: gr55xx_ll_pwm.h:82
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: gr55xx_ll_pwm.h:796
_ll_pwm_init_t::bprescaler
uint32_t bprescaler
Definition: gr55xx_ll_pwm.h:109
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: gr55xx_ll_pwm.h:1036
ll_pwm_enable_update_pause
__STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
Enable update pause.
Definition: gr55xx_ll_pwm.h:901
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1303
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1144
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1221
ll_pwm_get_mode
__STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: gr55xx_ll_pwm.h:376
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: gr55xx_ll_pwm.h:571
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1420
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: gr55xx_ll_pwm.h:296
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: gr55xx_ll_pwm.h:826
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1400
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: gr55xx_ll_pwm.h:691
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: gr55xx_ll_pwm.h:311
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: gr55xx_ll_pwm.h:1066
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: gr55xx_ll_pwm.h:661
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: gr55xx_ll_pwm.h:751
_ll_pwm_init_t::mode
uint32_t mode
Definition: gr55xx_ll_pwm.h:95
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1190
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: gr55xx_ll_pwm.h:586
_ll_pwm_init_t::hprescaler
uint32_t hprescaler
Definition: gr55xx_ll_pwm.h:115
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: gr55xx_ll_pwm.h:991
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1533
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: gr55xx_ll_pwm.h:341
_ll_pwm_init_t::channel_b
ll_pwm_channel_init_t channel_b
Definition: gr55xx_ll_pwm.h:123
ll_pwm_disable_update_pause
__STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
Disable update pause.
Definition: gr55xx_ll_pwm.h:916
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: gr55xx_ll_pwm.h:856
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: gr55xx_ll_pwm.h:781
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: gr55xx_ll_pwm.h:326
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: gr55xx_ll_pwm.h:421
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1498
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1159
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: gr55xx_ll_pwm.h:616
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: gr55xx_ll_pwm.h:976
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: gr55xx_ll_pwm.h:721
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: gr55xx_ll_pwm.h:766
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: gr55xx_ll_pwm.h:601
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1579
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: gr55xx_ll_pwm.h:646
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: gr55xx_ll_pwm.h:946
_ll_pwm_init_t::align
uint32_t align
Definition: gr55xx_ll_pwm.h:100
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: gr55xx_ll_pwm.h:631
ll_pwm_channel_init_t
struct _ll_pwm_channel_init_t ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: gr55xx_ll_pwm.h:1021
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1361
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: gr55xx_ll_pwm.h:556
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: gr55xx_ll_pwm.h:526
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1564
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: gr55xx_ll_pwm.h:841
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:496
_ll_pwm_init_t::channel_a
ll_pwm_channel_init_t channel_a
Definition: gr55xx_ll_pwm.h:120
_ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr55xx_ll_pwm.h:75
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1206
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: gr55xx_ll_pwm.h:886
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:436
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: gr55xx_ll_pwm.h:266
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:451
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: gr55xx_ll_pwm.h:281
_ll_pwm_init_t::prescaler
uint32_t prescaler
Definition: gr55xx_ll_pwm.h:103
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1175
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:406
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1459
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:481
ll_pwm_is_enabled_update_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
Indicate whether the update pause is enabled.
Definition: gr55xx_ll_pwm.h:931
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1342
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1283
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: gr55xx_ll_pwm.h:961
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1322
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: gr55xx_ll_pwm.h:676
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1082
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1439
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: gr55xx_ll_pwm.h:811
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: gr55xx_ll_pwm.h:511
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
Set PWM mode.
Definition: gr55xx_ll_pwm.h:359
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: gr55xx_ll_pwm.h:706
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1478
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:391
_ll_pwm_channel_init_t::duty
uint8_t duty
Definition: gr55xx_ll_pwm.h:76