gr55xx_ll_i2c.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2C0) || defined (I2C1)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_i2c_init
77 {
78 uint32_t speed;
80 uint32_t own_address;
85 uint32_t own_addr_size;
89 } ll_i2c_init_t;
90
100 /* Exported constants --------------------------------------------------------*/
109 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_INTR_GEN_CALL
110 #define LL_I2C_INTR_STAT_RESTART_DET I2C_INTR_RESTART_DET
111 #define LL_I2C_INTR_STAT_GEN_CALL I2C_INTR_GEN_CALL
112 #define LL_I2C_INTR_STAT_START_DET I2C_INTR_START_DET
113 #define LL_I2C_INTR_STAT_STOP_DET I2C_INTR_STOP_DET
114 #define LL_I2C_INTR_STAT_ACTIVITY I2C_INTR_ACTIVITY
115 #define LL_I2C_INTR_STAT_RX_DONE I2C_INTR_RX_DONE
116 #define LL_I2C_INTR_STAT_TX_ABRT I2C_INTR_TX_ABRT
117 #define LL_I2C_INTR_STAT_RD_REQ I2C_INTR_RD_REQ
118 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_INTR_TX_EMPTY
119 #define LL_I2C_INTR_STAT_TX_OVER I2C_INTR_TX_OVER
120 #define LL_I2C_INTR_STAT_RX_FULL I2C_INTR_RX_FULL
121 #define LL_I2C_INTR_STAT_RX_OVER I2C_INTR_RX_OVER
122 #define LL_I2C_INTR_STAT_RX_UNDER I2C_INTR_RX_UNDER
124 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT
125 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT
126 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX
127 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST
128 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO
129 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST
130 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABRT_SRC_MST_DIS
131 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT
132 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT
133 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT
134 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET
135 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET
136 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ
137 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK
138 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK
139 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK
140 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK
141 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK
148 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INTR_GEN_CALL
149 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INTR_RESTART_DET
150 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INTR_GEN_CALL
151 #define LL_I2C_INTR_MASK_START_DET I2C_INTR_START_DET
152 #define LL_I2C_INTR_MASK_STOP_DET I2C_INTR_STOP_DET
153 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INTR_ACTIVITY
154 #define LL_I2C_INTR_MASK_RX_DONE I2C_INTR_RX_DONE
155 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INTR_TX_ABRT
156 #define LL_I2C_INTR_MASK_RD_REQ I2C_INTR_RD_REQ
157 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INTR_TX_EMPTY
158 #define LL_I2C_INTR_MASK_TX_OVER I2C_INTR_TX_OVER
159 #define LL_I2C_INTR_MASK_RX_FULL I2C_INTR_RX_FULL
160 #define LL_I2C_INTR_MASK_RX_OVER I2C_INTR_RX_OVER
161 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INTR_RX_UNDER
163 #define LL_I2C_INTR_MASK_ALL 0x00000FFFU
169 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
170 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CON_10BITADDR_MST
176 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U
177 #define LL_I2C_OWNADDRESS_10BIT I2C_CON_10BITADDR_SLV
184 #define LL_I2C_CMD_SLV_NONE 0x00000000U
185 #define LL_I2C_CMD_MST_WRITE 0x00000000U
186 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD
187 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP
188 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART
194 #define LL_I2C_SPEED_MODE_STANDARD I2C_CON_SPEED_STANDARD
195 #define LL_I2C_SPEED_MODE_FAST I2C_CON_SPEED_FAST
196 #define LL_I2C_SPEED_MODE_HIGH I2C_CON_SPEED_HIGH
202 #define LL_I2C_SPEED_100K (100000ul)
203 #define LL_I2C_SPEED_400K (400000ul)
204 #define LL_I2C_SPEED_1000K (1000000ul)
205 #define LL_I2C_SPEED_2000K (2000000ul)
211 #define LL_I2C_DIRECTION_NONE 0x00000000U
212 #define LL_I2C_DIRECTION_WRITE I2C_INTR_RX_FULL
213 #define LL_I2C_DIRECTION_READ I2C_INTR_RD_REQ
214 #define LL_I2C_DIRECTION_ERROR I2C_INTR_RX_FULL | I2C_INTR_RD_REQ
221 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U
222 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U
223 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U
224 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U
225 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U
226 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U
227 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U
228 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U
234 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U
235 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U
236 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U
237 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U
238 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U
239 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U
240 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U
241 #define LL_I2C_RX_FIFO_TH_FULL 0x00000007U
251 #define LL_I2C_DEFAULT_CONFIG \
252 { \
253 .speed = LL_I2C_SPEED_400K, \
254 .own_address = 0x55U, \
255 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
256 }
257
261 /* Exported macro ------------------------------------------------------------*/
277 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
278
285 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
286
298 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
299
308 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
309 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
310
316 /* Private types -------------------------------------------------------------*/
317 /* Private variables ---------------------------------------------------------*/
318 /* Private constants ---------------------------------------------------------*/
319 /* Private macros ------------------------------------------------------------*/
320
321 /* Exported functions --------------------------------------------------------*/
340 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
341 {
342 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
343 }
344
360 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
361 {
362 CLEAR_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
363 }
364
375 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
376 {
377 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_IC_EN) == (I2C_ENABLE_STATUS_IC_EN));
378 }
379
390 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
391 {
392 SET_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
393 }
394
405 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
406 {
407 CLEAR_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
408 }
409
421 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
422 {
423 return (READ_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS) == (I2C_CON_MST_MODE | I2C_CON_SLV_DIS));
424 }
425
437 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
438 {
439 SET_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
440 }
441
453 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
454 {
455 CLEAR_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
456 }
457
468 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
469 {
470 return (READ_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC) == (I2C_ACK_GENERAL_CALL_ACK_GC));
471 }
472
490 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
491 {
492 SET_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
493 }
494
506 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
507 {
508 CLEAR_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
509 }
510
521 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
522 {
523 return (READ_BITS(I2Cx->CON, I2C_CON_RESTART_EN) == (I2C_CON_RESTART_EN));
524 }
525
541 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
542 {
543 SET_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
544 }
545
557 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
558 {
559 CLEAR_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
560 }
561
572 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
573 {
574 return (READ_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED) == (I2C_CON_STOP_DET_IF_ADDRESSED));
575 }
576
591 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
592 {
593 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_MST, addressing_mode);
594 }
595
609 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
610 {
611 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_10BITADDR_MST));
612 }
613
631 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
632 {
633 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_SLV, own_addr_size);
634 WRITE_REG(I2Cx->SAR, own_address);
635 }
636
649 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
650 {
651 WRITE_REG(I2Cx->SS_SCL_HCNT, count);
652 }
653
664 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
665 {
666 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_HCNT, I2C_SS_SCL_HCNT));
667 }
668
681 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
682 {
683 WRITE_REG(I2Cx->SS_SCL_LCNT, count);
684 }
685
696 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
697 {
698 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_LCNT, I2C_SS_SCL_LCNT));
699 }
700
713 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
714 {
715 WRITE_REG(I2Cx->FS_SCL_HCNT, count);
716 }
717
728 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
729 {
730 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_HCNT, I2C_FS_SCL_HCNT));
731 }
732
745 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
746 {
747 WRITE_REG(I2Cx->FS_SCL_LCNT, count);
748 }
749
760 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
761 {
762 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_LCNT, I2C_FS_SCL_LCNT));
763 }
764
777 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
778 {
779 WRITE_REG(I2Cx->HS_SCL_HCNT, count);
780 }
781
792 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
793 {
794 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_HCNT, I2C_HS_SCL_HCNT));
795 }
796
809 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
810 {
811 WRITE_REG(I2Cx->HS_SCL_LCNT, count);
812 }
813
824 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
825 {
826 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_LCNT, I2C_HS_SCL_LCNT));
827 }
828
841 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
842 {
843 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
844 }
845
856 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
857 {
858 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
859 }
860
873 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
874 {
875 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
876 }
877
888 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
889 {
890 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
891 }
892
908 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
909 {
910 MODIFY_REG(I2Cx->CON, I2C_CON_SPEED, speed_mode);
911 }
912
926 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
927 {
928 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_SPEED));
929 }
930
943 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
944 {
945 WRITE_REG(I2Cx->HS_MADDR, code);
946 }
947
958 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
959 {
960 return (uint32_t)(READ_BITS(I2Cx->HS_MADDR, I2C_HS_MADDR_HS_MAR));
961 }
962
976 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
977 {
978 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_Pos);
979 }
980
991 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
992 {
993 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_Pos);
994 }
995
1009 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1010 {
1011 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_Pos);
1012 }
1013
1024 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1025 {
1026 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_Pos);
1027 }
1028
1043 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1044 {
1045 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP, time);
1046 }
1047
1058 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1059 {
1060 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP));
1061 }
1062
1083 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1084 {
1085 WRITE_REG(I2Cx->TX_TL, threshold);
1086 }
1087
1106 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1107 {
1108 return (uint32_t)(READ_BITS(I2Cx->TX_TL, I2C_TX_TL_TXTL));
1109 }
1110
1131 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1132 {
1133 WRITE_REG(I2Cx->RX_TL, threshold);
1134 }
1135
1154 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1155 {
1156 return (uint32_t)(READ_BITS(I2Cx->RX_TL, I2C_RX_TL_RXTL));
1157 }
1158
1169 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1170 {
1171 return (uint32_t)(READ_BITS(I2Cx->TXFLR, I2C_TXFLR_TXFLR));
1172 }
1173
1184 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1185 {
1186 return (uint32_t)(READ_BITS(I2Cx->RXFLR, I2C_RXFLR_RXFLR));
1187 }
1188
1199 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1200 {
1201 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT);
1202 }
1203
1214 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1215 {
1216 return (READ_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT) == (I2C_ENABLE_ABORT));
1217 }
1218
1267 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1268 {
1269 return (uint32_t)(READ_REG(I2Cx->TX_ABRT_SOURCE) & (~I2C_TX_ABRT_SRC_TX_FLUSH_CNT));
1270 }
1271
1282 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1283 {
1284 return (uint32_t)(READ_BITS(I2Cx->TX_ABRT_SOURCE, I2C_TX_ABRT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos);
1285 }
1286
1327 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1328 {
1329 SET_BITS(I2Cx->INTR_MASK, mask);
1330 }
1331
1366 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1367 {
1368 CLEAR_BITS(I2Cx->INTR_MASK, mask);
1369 }
1370
1405 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1406 {
1407 return (READ_BITS(I2Cx->INTR_MASK, mask) == (mask));
1408 }
1409
1420 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1421 {
1422 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1423 }
1424
1435 __STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
1436 {
1437 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1438 }
1439
1450 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1451 {
1452 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
1453 }
1454
1465 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1466 {
1467 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1468 }
1469
1480 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1481 {
1482 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1483 }
1484
1495 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1496 {
1497 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
1498 }
1499
1510 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1511 {
1512 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1513 }
1514
1525 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1526 {
1527 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1528 }
1529
1540 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1541 {
1542 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
1543 }
1544
1555 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1556 {
1557 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1558 }
1559
1570 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1571 {
1572 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1573 }
1574
1585 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1586 {
1587 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
1588 }
1589
1600 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1601 {
1602 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1603 }
1604
1615 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1616 {
1617 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1618 }
1619
1630 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1631 {
1632 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
1633 }
1634
1645 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1646 {
1647 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1648 }
1649
1660 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1661 {
1662 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1663 }
1664
1675 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1676 {
1677 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
1678 }
1679
1690 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
1691 {
1692 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1693 }
1694
1705 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
1706 {
1707 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1708 }
1709
1720 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
1721 {
1722 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
1723 }
1724
1735 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
1736 {
1737 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1738 }
1739
1750 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
1751 {
1752 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1753 }
1754
1765 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
1766 {
1767 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
1768 }
1769
1780 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
1781 {
1782 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1783 }
1784
1795 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
1796 {
1797 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1798 }
1799
1810 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
1811 {
1812 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
1813 }
1814
1825 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
1826 {
1827 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1828 }
1829
1840 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
1841 {
1842 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1843 }
1844
1855 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
1856 {
1857 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
1858 }
1859
1870 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
1871 {
1872 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1873 }
1874
1885 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
1886 {
1887 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1888 }
1889
1900 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
1901 {
1902 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
1903 }
1904
1915 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
1916 {
1917 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1918 }
1919
1930 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
1931 {
1932 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1933 }
1934
1945 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
1946 {
1947 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
1948 }
1949
1960 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
1961 {
1962 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1963 }
1964
1975 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
1976 {
1977 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1978 }
1979
1990 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
1991 {
1992 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
1993 }
1994
2005 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2006 {
2007 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2008 }
2009
2020 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2021 {
2022 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2023 }
2024
2035 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2036 {
2037 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2038 }
2039
2083 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2084 {
2085 return (uint32_t)(READ_REG(I2Cx->INTR_STAT));
2086 }
2087
2125 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2126 {
2127 return (uint32_t)(READ_REG(I2Cx->RAW_INTR_STAT));
2128 }
2129
2142 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2143 {
2144 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2145 }
2146
2159 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2160 {
2161 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2162 }
2163
2176 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2177 {
2178 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2179 }
2180
2193 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2194 {
2195 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2196 }
2197
2210 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2211 {
2212 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2213 }
2214
2227 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2228 {
2229 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2230 }
2231
2244 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2245 {
2246 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2247 }
2248
2261 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2262 {
2263 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2264 }
2265
2278 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2279 {
2280 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2281 }
2282
2295 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2296 {
2297 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2298 }
2299
2312 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2313 {
2314 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2315 }
2316
2329 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2330 {
2331 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2332 }
2333
2346 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2347 {
2348 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2349 }
2350
2363 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2364 {
2365 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2366 }
2367
2380 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2381 {
2382 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2383 }
2384
2397 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2398 {
2399 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2400 }
2401
2414 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2415 {
2416 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2417 }
2418
2431 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2432 {
2433 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2434 }
2435
2448 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2449 {
2450 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2451 }
2452
2465 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2466 {
2467 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2468 }
2469
2482 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2483 {
2484 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2485 }
2486
2499 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2500 {
2501 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2502 }
2503
2516 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
2517 {
2518 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2519 }
2520
2533 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
2534 {
2535 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2536 }
2537
2550 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
2551 {
2552 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2553 }
2554
2567 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
2568 {
2569 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2570 }
2571
2584 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
2585 {
2586 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2587 }
2588
2601 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
2602 {
2603 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2604 }
2605
2616 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
2617 {
2618 __IO uint32_t tmpreg;
2619 tmpreg = READ_REG(I2Cx->CLR_INTR);
2620 (void) tmpreg;
2621 }
2622
2633 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
2634 {
2635 __IO uint32_t tmpreg;
2636 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
2637 (void) tmpreg;
2638 }
2639
2650 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
2651 {
2652 __IO uint32_t tmpreg;
2653 tmpreg = READ_REG(I2Cx->CLR_START_DET);
2654 (void) tmpreg;
2655 }
2656
2667 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
2668 {
2669 __IO uint32_t tmpreg;
2670 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
2671 (void) tmpreg;
2672 }
2673
2684 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
2685 {
2686 __IO uint32_t tmpreg;
2687 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
2688 (void) tmpreg;
2689 }
2690
2701 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
2702 {
2703 __IO uint32_t tmpreg;
2704 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
2705 (void) tmpreg;
2706 }
2707
2718 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
2719 {
2720 __IO uint32_t tmpreg;
2721 tmpreg = READ_REG(I2Cx->CLR_TX_ABRT);
2722 (void) tmpreg;
2723 }
2724
2735 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
2736 {
2737 __IO uint32_t tmpreg;
2738 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
2739 (void) tmpreg;
2740 }
2741
2752 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
2753 {
2754 __IO uint32_t tmpreg;
2755 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
2756 (void) tmpreg;
2757 }
2758
2769 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
2770 {
2771 __IO uint32_t tmpreg;
2772 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
2773 (void) tmpreg;
2774 }
2775
2786 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
2787 {
2788 __IO uint32_t tmpreg;
2789 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
2790 (void) tmpreg;
2791 }
2792
2805 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
2806 {
2807 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_SLV_ACTIVITY) == (I2C_STATUS_SLV_ACTIVITY));
2808 }
2809
2822 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
2823 {
2824 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_MST_ACTIVITY) == (I2C_STATUS_MST_ACTIVITY));
2825 }
2826
2839 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
2840 {
2841 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFF) == (I2C_STATUS_RFF));
2842 }
2843
2856 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
2857 {
2858 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFNE) == (I2C_STATUS_RFNE));
2859 }
2860
2873 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
2874 {
2875 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFE) == (I2C_STATUS_TFE));
2876 }
2877
2890 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
2891 {
2892 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFNF) == (I2C_STATUS_TFNF));
2893 }
2894
2907 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
2908 {
2909 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_ACTIVITY) == (I2C_STATUS_ACTIVITY));
2910 }
2911
2924 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
2925 {
2926 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_RX_LOST) == (I2C_ENABLE_STATUS_SLV_RX_LOST));
2927 }
2928
2941 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
2942 {
2943 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY) == (I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY));
2944 }
2961 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
2962 {
2963 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2964 }
2965
2976 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
2977 {
2978 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2979 }
2980
2991 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
2992 {
2993 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE) == (I2C_DMA_CR_TDMAE));
2994 }
2995
3006 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3007 {
3008 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3009 }
3010
3021 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3022 {
3023 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3024 }
3025
3036 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3037 {
3038 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE) == (I2C_DMA_CR_RDMAE));
3039 }
3040
3055 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3056 {
3057 WRITE_REG(I2Cx->DMA_TDLR, level);
3058 }
3059
3070 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3071 {
3072 return (uint32_t)(READ_BITS(I2Cx->DMA_TDLR, I2C_DMA_TDLR_DMATDL));
3073 }
3074
3091 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3092 {
3093 WRITE_REG(I2Cx->DMA_RDLR, level);
3094 }
3095
3106 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3107 {
3108 return (uint32_t)(READ_BITS(I2Cx->DMA_RDLR, I2C_DMA_RDLR_DMARDL));
3109 }
3110
3121 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3122 {
3123 return ((uint32_t) & (I2Cx->DATA_CMD));
3124 }
3125
3144 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3145 {
3146 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3147 }
3148
3159 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3160 {
3161 return (uint32_t)(READ_BITS(I2Cx->TAR, I2C_TAR_ADDR) >> I2C_TAR_ADDR_Pos);
3162 }
3163
3181 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3182 {
3183 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3184 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3185 }
3186
3202 __STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
3203 {
3204 return (uint32_t)(READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ | I2C_INTR_RX_FULL));
3205 }
3206
3217 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3218 {
3219 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DAT));
3220 }
3221
3241 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3242 {
3243 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3244 }
3245
3259 error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx);
3260
3271 error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3272
3279 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3280
3285 #endif /* I2C0 || I2C1 */
3286
3287 #ifdef __cplusplus
3288 }
3289 #endif
3290
3291 #endif /* __GR55xx_LL_I2C_H__ */
3292
ll_i2c_is_active_flag_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2482
ll_i2c_enable
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
Definition: gr55xx_ll_i2c.h:340
_ll_i2c_init::own_addr_size
uint32_t own_addr_size
Definition: gr55xx_ll_i2c.h:85
ll_i2c_enable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:541
ll_i2c_is_active_flag_status_tfnf
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
Definition: gr55xx_ll_i2c.h:2890
ll_i2c_is_enabled_transfer_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1214
ll_i2c_is_active_flag_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2346
ll_i2c_get_clock_low_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:760
ll_i2c_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_i2c.h:1169
ll_i2c_is_enabled_it_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1630
ll_i2c_is_enabled_it_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1450
ll_i2c_set_speed_mode
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
Definition: gr55xx_ll_i2c.h:908
ll_i2c_enable_it_tx_over
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1870
ll_i2c_disable_it_tx_over
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1885
ll_i2c_is_active_flag_status_master_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:2822
ll_i2c_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1154
ll_i2c_get_abort_source
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
Definition: gr55xx_ll_i2c.h:1267
ll_i2c_is_active_flag_raw_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2159
ll_i2c_is_active_flag_status_rfne
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
Definition: gr55xx_ll_i2c.h:2856
ll_i2c_clear_flag_rx_under
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2786
ll_i2c_dma_get_register_address
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_i2c.h:3121
ll_i2c_clear_flag_tx_over
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2752
ll_i2c_disable_it_tx_empty
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1840
ll_i2c_is_active_flag_raw_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2397
ll_i2c_enable_dma_req_tx
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:2961
ll_i2c_is_enabled_it_start_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1585
ll_i2c_is_enabled_stop_det_if_addressed
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
Definition: gr55xx_ll_i2c.h:572
ll_i2c_enable_it_start_det
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1555
ll_i2c_get_data_setup_time
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1058
ll_i2c_is_active_flag_raw_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2431
ll_i2c_is_active_flag_status_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2907
ll_i2c_disable_it_master_om_hold
__STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1435
ll_i2c_enable_transfer_abort
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:1199
ll_i2c_get_spike_len_fs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:856
ll_i2c_deinit
error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
ll_i2c_is_active_flag_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2584
ll_i2c_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1083
ll_i2c_is_active_flag_raw_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2329
ll_i2c_get_clock_low_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:824
ll_i2c_is_active_flag_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2278
ll_i2c_is_enabled_master_mode
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
Definition: gr55xx_ll_i2c.h:421
ll_i2c_disable_dma_req_tx
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:2976
ll_i2c_disable_it_rx_over
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1975
_ll_i2c_init::speed
uint32_t speed
Definition: gr55xx_ll_i2c.h:78
ll_i2c_enable_it_read_req
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:1780
ll_i2c_is_active_flag_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2550
ll_i2c_is_enabled_it_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2035
ll_i2c_enable_it_stop_det
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1600
ll_i2c_disable_dma_req_rx
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3021
ll_i2c_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1131
ll_i2c_is_active_flag_status_tfe
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
Definition: gr55xx_ll_i2c.h:2873
ll_i2c_is_active_flag_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2176
ll_i2c_set_dma_rx_data_level
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
Definition: gr55xx_ll_i2c.h:3091
ll_i2c_disable_it_restart_det
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1480
ll_i2c_is_active_flag_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2142
ll_i2c_disable_it
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
Definition: gr55xx_ll_i2c.h:1366
ll_i2c_disable_master_restart
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
Definition: gr55xx_ll_i2c.h:506
ll_i2c_get_clock_high_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:792
ll_i2c_clear_flag_intr
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: gr55xx_ll_i2c.h:2616
ll_i2c_is_enabled_it_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1495
ll_i2c_get_tx_flush_count
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1282
ll_i2c_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_i2c.h:1106
ll_i2c_disable_it_stop_det
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1615
ll_i2c_is_enabled_it_activity
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1675
ll_i2c_get_data_rx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1024
ll_i2c_get_clock_high_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:664
ll_i2c_init
error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
ll_i2c_disbale_it_rx_full
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:1930
ll_i2c_get_slave_address
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3159
ll_i2c_is_active_flag_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2516
ll_i2c_enable_it_master_on_hold
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1420
ll_i2c_is_enabled_it_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1765
ll_i2c_set_own_address
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
Definition: gr55xx_ll_i2c.h:631
ll_i2c_clear_flag_start_det
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
Definition: gr55xx_ll_i2c.h:2650
ll_i2c_set_master_addressing_mode
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
Definition: gr55xx_ll_i2c.h:591
ll_i2c_disable_it_gen_call
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1525
ll_i2c_clear_flag_stop_det
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2667
ll_i2c_disable_it_start_det
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1570
ll_i2c_is_active_flag_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2312
ll_i2c_disable_master_mode
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
Definition: gr55xx_ll_i2c.h:405
ll_i2c_is_active_flag_raw_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2227
ll_i2c_get_master_addressing_mode
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
Definition: gr55xx_ll_i2c.h:609
ll_i2c_clear_flag_tx_abort
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2718
ll_i2c_disable_it_activity
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1660
ll_i2c_is_active_flag_slave_rx_data_lost
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
Definition: gr55xx_ll_i2c.h:2924
_ll_i2c_init
LL I2C init Structure definition.
Definition: gr55xx_ll_i2c.h:77
ll_i2c_is_active_flag_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2380
ll_i2c_disable_it_read_req
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:1795
ll_i2c_is_enabled_general_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
Definition: gr55xx_ll_i2c.h:468
ll_i2c_get_dma_rx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
Definition: gr55xx_ll_i2c.h:3106
ll_i2c_enable_it
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
Definition: gr55xx_ll_i2c.h:1327
ll_i2c_is_active_flag_slave_dis_whl_busy
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
Definition: gr55xx_ll_i2c.h:2941
ll_i2c_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:2991
ll_i2c_clear_flag_rx_done
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2701
ll_i2c_set_clock_low_period_ss
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:681
ll_i2c_clear_flag_rx_over
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2769
ll_i2c_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3036
ll_i2c_enable_dma_req_rx
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3006
ll_i2c_is_active_flag_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2448
ll_i2c_is_active_flag_raw_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2465
ll_i2c_is_enabled_it_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1990
ll_i2c_receive_data8
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
Definition: gr55xx_ll_i2c.h:3217
ll_i2c_struct_init
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
ll_i2c_disable_general_call
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:453
ll_i2c_is_enabled_it_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1900
ll_i2c_set_data_rx_hold_time
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1009
ll_i2c_set_spike_len_hs
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:873
ll_i2c_enable_it_rx_under
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2005
ll_i2c_enable_general_call
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:437
ll_i2c_is_active_flag_status_slave_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:2805
ll_i2c_set_dma_tx_data_level
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
Definition: gr55xx_ll_i2c.h:3055
ll_i2c_is_enabled_it
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1405
ll_i2c_get_dma_tx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
Definition: gr55xx_ll_i2c.h:3070
ll_i2c_is_active_flag_raw_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2363
ll_i2c_get_high_speed_master_code
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:958
ll_i2c_set_clock_high_period_fs
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:713
ll_i2c_enable_it_rx_over
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1960
ll_i2c_enable_it_activity
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1645
ll_i2c_is_active_flag_raw_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
Definition: gr55xx_ll_i2c.h:2261
ll_i2c_ls_enabled_it_rx_full
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1945
ll_i2c_set_clock_high_period_hs
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:777
ll_i2c_get_data_tx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:991
ll_i2c_clear_flag_read_req
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2735
ll_i2c_is_active_flag_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2414
ll_i2c_get_spike_len_hs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:888
ll_i2c_enable_it_rx_done
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:1690
ll_i2c_enable_master_restart
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
Definition: gr55xx_ll_i2c.h:490
ll_i2c_init_t
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
ll_i2c_is_enabled_it_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1855
ll_i2c_is_active_flag_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2210
ll_i2c_clear_flag_activity
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2684
ll_i2c_is_active_flag_status_rff
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
Definition: gr55xx_ll_i2c.h:2839
ll_i2c_set_data_setup_time
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1043
ll_i2c_enable_master_mode
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
Definition: gr55xx_ll_i2c.h:390
ll_i2c_set_clock_low_period_hs
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:809
ll_i2c_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
Definition: gr55xx_ll_i2c.h:1184
ll_i2c_get_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
Definition: gr55xx_ll_i2c.h:2083
ll_i2c_is_active_flag_raw_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2193
ll_i2c_is_enabled_it_read_req
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1810
ll_i2c_enable_it_gen_call
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1510
ll_i2c_disable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:557
ll_i2c_is_enabled_master_restart
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
Definition: gr55xx_ll_i2c.h:521
ll_i2c_get_speed_mode
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:926
ll_i2c_set_slave_address
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3144
ll_i2c_set_high_speed_master_code
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
Definition: gr55xx_ll_i2c.h:943
ll_i2c_disable_it_rx_done
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:1705
ll_i2c_is_enabled
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
Definition: gr55xx_ll_i2c.h:375
ll_i2c_enable_it_restart_det
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1465
ll_i2c_is_active_flag_raw_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2533
ll_i2c_is_active_flag_raw_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2601
ll_i2c_set_clock_high_period_ss
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:649
ll_i2c_is_active_flag_raw_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2499
ll_i2c_is_active_flag_raw_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2295
ll_i2c_disable_it_rx_under
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2020
ll_i2c_set_clock_low_period_fs
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:745
ll_i2c_is_enable_it_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1720
ll_i2c_handle_transfer
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
Definition: gr55xx_ll_i2c.h:3181
ll_i2c_clear_flag_gen_call
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2633
ll_i2c_get_transfer_direction
__STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
Indicate the value of transfer direction (slave mode).
Definition: gr55xx_ll_i2c.h:3202
ll_i2c_is_active_flag_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
Definition: gr55xx_ll_i2c.h:2244
ll_i2c_get_clock_high_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:728
ll_i2c_enable_it_rx_abort
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1735
ll_i2c_enable_it_tx_empty
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1825
ll_i2c_set_data_tx_hold_time
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:976
_ll_i2c_init::own_address
uint32_t own_address
Definition: gr55xx_ll_i2c.h:80
ll_i2c_disable
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
Definition: gr55xx_ll_i2c.h:360
ll_i2c_set_spike_len_fs
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:841
ll_i2c_is_enabled_it_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1540
ll_i2c_disable_it_tx_abort
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1750
ll_i2c_is_active_flag_raw_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2567
ll_i2c_get_raw_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
Definition: gr55xx_ll_i2c.h:2125
ll_i2c_get_clock_low_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:696
ll_i2c_transmit_data8
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
Definition: gr55xx_ll_i2c.h:3241
ll_i2c_enable_it_rx_full
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:1915