var group___x_q_s_p_i___exported___constants =
[
    [ "XQSPI Error Code", "dd/d9b/group___x_q_s_p_i___error___code.html", "dd/d9b/group___x_q_s_p_i___error___code" ],
    [ "XQSPI Work Mode", "de/d3d/group___x_q_s_p_i___work___mode.html", "de/d3d/group___x_q_s_p_i___work___mode" ],
    [ "XQSPI Cache Mode in XIP mode", "d4/d4f/group___x_q_s_p_i___cache___mode.html", "d4/d4f/group___x_q_s_p_i___cache___mode" ],
    [ "XQSPI Read Command in XIP mode", "d1/d5e/group___x_q_s_p_i___read___c_m_d.html", "d1/d5e/group___x_q_s_p_i___read___c_m_d" ],
    [ "XQSPI Clock Mode", "d3/d83/group___x_q_s_p_i___clock___mode.html", "d3/d83/group___x_q_s_p_i___clock___mode" ],
    [ "XQSPI Clock Speed", "d8/d30/group___x_q_s_p_i___baud___rate.html", "d8/d30/group___x_q_s_p_i___baud___rate" ],
    [ "XQSPI Data Mode, only in QSPI mode", "d3/d0b/group___x_q_s_p_i___data___mode.html", "d3/d0b/group___x_q_s_p_i___data___mode" ],
    [ "XQSPI FIFO Threshold, FIFO depth is 64*4bytes, only in QSPI mode", "dd/d8c/group___x_q_s_p_i___f_i_f_o___threshold.html", "dd/d8c/group___x_q_s_p_i___f_i_f_o___threshold" ],
    [ "XQSPI Instruction Size, only in QSPI mode", "d7/dc1/group___x_q_s_p_i___instruction___size.html", "d7/dc1/group___x_q_s_p_i___instruction___size" ],
    [ "XQSPI Address Size, only in QSPI mode", "d9/dce/group___x_q_s_p_i___address___size.html", "d9/dce/group___x_q_s_p_i___address___size" ],
    [ "XQSPI Instruction and Address Mode, only in QSPI mode", "d7/df5/group___x_q_s_p_i___inst___addr___mode.html", "d7/df5/group___x_q_s_p_i___inst___addr___mode" ],
    [ "XQSPI Flags, only in QSPI mode", "d2/dcd/group___x_q_s_p_i___flags.html", "d2/dcd/group___x_q_s_p_i___flags" ],
    [ "Control Present Status, only in XIP mode", "db/d39/group___x_q_s_p_i___ctrl___present.html", "db/d39/group___x_q_s_p_i___ctrl___present" ],
    [ "HAL_XQSPI_RETRY_DEFAULT_VALUE", "d1/dff/group___x_q_s_p_i___exported___constants.html#ga0ec989a809716246193c9a944ab830c7", null ]
];