gr55xx_ll_aes.h
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1
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "gr55xx.h"
60
61 #if defined (AES)
62
67 /* Exported types ------------------------------------------------------------*/
75 typedef struct _ll_aes_init
76 {
77 uint32_t key_size;
80 uint32_t *p_key;
82 uint32_t *p_init_vector;
84 uint32_t *p_seed;
86 } ll_aes_init_t;
87
97 /* Exported constants --------------------------------------------------------*/
106 #define LL_AES_FLAG_DATAREADY AES_STATUS_READY
107 #define LL_AES_FLAG_DMA_DONE AES_STATUS_TRANSDONE
108 #define LL_AES_FLAG_DMA_ERR AES_STATUS_TRANSERR
109 #define LL_AES_FLAG_KEY_VALID AES_STATUS_KEYVALID
115 #define LL_AES_KEY_SIZE_128 0x00000000U
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CONFIG_KEYMODE_Pos)
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CONFIG_KEYMODE_Pos)
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CONFIG_OPMODE_Pos)
130 #define LL_AES_KEYTYPE_MCU 0x00000000U
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CONFIG_KEYTYPE_Pos)
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CONFIG_KEYTYPE_Pos)
138 #define LL_AES_DMA_TRANSIZE_MIN (1)
139 #define LL_AES_DMA_TRANSIZE_MAX (2048)
144 /* Exported macro ------------------------------------------------------------*/
145
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
161
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
169
176 /* Exported functions --------------------------------------------------------*/
195 __STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
196 {
197 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE);
198 }
199
210 __STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
211 {
212 CLEAR_BITS(AESx->CTRL, AES_CTRL_ENABLE);
213 }
214
225 __STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
226 {
227 return (READ_BITS(AESx->CTRL, AES_CTRL_ENABLE) == (AES_CTRL_ENABLE));
228 }
229
240 __STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
241 {
242 SET_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
243 }
244
255 __STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
256 {
257 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
258 }
259
270 __STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
271 {
272 return (READ_BITS(AESx->CTRL, AES_CTRL_START_NORMAL) == (AES_CTRL_START_NORMAL));
273 }
274
285 __STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
286 {
287 SET_BITS(AESx->CTRL, AES_CTRL_START_DMA);
288 }
289
300 __STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
301 {
302 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_DMA);
303 }
304
315 __STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
316 {
317 return (READ_BITS(AESx->CTRL, AES_CTRL_START_DMA) == (AES_CTRL_START_DMA));
318 }
319
330 __STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
331 {
332 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE_RKEY);
333 }
334
349 __STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
350 {
351 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYMODE, size);
352 }
353
367 __STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
368 {
369 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYMODE));
370 }
371
382 __STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
383 {
384 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
385 }
386
397 __STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
398 {
399 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
400 }
401
412 __STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
413 {
414 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK) == (AES_CONFIG_ENABLE_FULLMASK));
415 }
416
427 __STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
428 {
429 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
430 }
431
442 __STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
443 {
444 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
445 }
446
457 __STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
458 {
459 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION) == (AES_CONFIG_ENABLE_ENCRYPTION));
460 }
461
472 __STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
473 {
474 SET_BITS(AESx->CONFIG, AES_CONFIG_LOADSEED);
475 }
476
487 __STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
488 {
489 SET_BITS(AESx->CONFIG, AES_CONFIG_FIRSTBLOCK);
490 }
491
502 __STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
503 {
504 SET_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
505 }
506
517 __STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
518 {
519 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
520 }
521
532 __STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
533 {
534 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN) == (AES_CONFIG_ENDIAN));
535 }
536
550 __STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
551 {
552 MODIFY_REG(AESx->CONFIG, AES_CONFIG_OPMODE, mode);
553 }
554
567 __STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
568 {
569 return (READ_BITS(AESx->CONFIG, AES_CONFIG_OPMODE));
570 }
571
586 __STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
587 {
588 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYTYPE, Type);
589 }
590
604 __STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
605 {
606 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYTYPE));
607 }
608
625 __STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
626 {
627 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
628 }
629
640 __STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
641 {
642 CLEAR_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
643 }
644
655 __STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
656 {
657 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE) == (AES_INTERRUPT_ENABLE));
658 }
659
676 __STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
677 {
678 return (READ_BITS(AESx->STATUS, AES_STATUS_READY) == AES_STATUS_READY);
679 }
680
691 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
692 {
693 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSDONE) == AES_STATUS_TRANSDONE);
694 }
695
706 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
707 {
708 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSERR) == AES_STATUS_TRANSERR);
709 }
710
721 __STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
722 {
723 return (READ_BITS(AESx->STATUS, AES_STATUS_KEYVALID) == AES_STATUS_KEYVALID);
724 }
725
736 __STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
737 {
738 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE) == AES_INTERRUPT_DONE);
739 }
740
751 __STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
752 {
753 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE);
754 }
755
773 __STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
774 {
775 MODIFY_REG(AESx->TRAN_SIZE, AES_TRAN_SIZE, (block << 4) - 1);
776 }
777
788 __STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
789 {
790 return ((READ_BITS(AESx->TRAN_SIZE, AES_TRAN_SIZE) + 1) >> 4);
791 }
792
805 __STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
806 {
807 WRITE_REG(AESx->RSTART_ADDR, address);
808 }
809
820 __STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
821 {
822 return (READ_REG(AESx->RSTART_ADDR));
823 }
824
837 __STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
838 {
839 WRITE_REG(AESx->WSTART_ADDR, address);
840 }
841
852 __STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
853 {
854 return (READ_REG(AESx->WSTART_ADDR));
855 }
856
874 __STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
875 {
876 WRITE_REG(AESx->KEY_ADDR, address);
877 }
878
889 __STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
890 {
891 return (READ_REG(AESx->KEY_ADDR));
892 }
893
904 __STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
905 {
906 return (READ_REG(AESx->DATA_OUT[0]));
907 }
908
919 __STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
920 {
921 return (READ_REG(AESx->DATA_OUT[1]));
922 }
923
934 __STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
935 {
936 return (READ_REG(AESx->DATA_OUT[2]));
937 }
938
949 __STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
950 {
951 return (READ_REG(AESx->DATA_OUT[3]));
952 }
953
965 __STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
966 {
967 WRITE_REG(AESx->KEY[0], key);
968 }
969
981 __STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
982 {
983 WRITE_REG(AESx->KEY[1], key);
984 }
985
997 __STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
998 {
999 WRITE_REG(AESx->KEY[2], key);
1000 }
1001
1013 __STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
1014 {
1015 WRITE_REG(AESx->KEY[3], key);
1016 }
1017
1029 __STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
1030 {
1031 WRITE_REG(AESx->KEY[4], key);
1032 }
1033
1045 __STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
1046 {
1047 WRITE_REG(AESx->KEY[5], key);
1048 }
1049
1061 __STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
1062 {
1063 WRITE_REG(AESx->KEY[6], key);
1064 }
1065
1077 __STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
1078 {
1079 WRITE_REG(AESx->KEY[7], key);
1080 }
1081
1093 __STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
1094 {
1095 WRITE_REG(AESx->SEED_IN, seed);
1096 }
1097
1108 __STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
1109 {
1110 return (READ_REG(AESx->SEED_IN));
1111 }
1112
1124 __STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
1125 {
1126 WRITE_REG(AESx->SEED_OUT, seed);
1127 }
1128
1139 __STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
1140 {
1141 return (READ_REG(AESx->SEED_OUT));
1142 }
1143
1155 __STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
1156 {
1157 WRITE_REG(AESx->SEED_IMASK, mask);
1158 }
1159
1170 __STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
1171 {
1172 return (READ_REG(AESx->SEED_IMASK));
1173 }
1174
1186 __STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
1187 {
1188 WRITE_REG(AESx->SEED_OSBOX, mask);
1189 }
1190
1201 __STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
1202 {
1203 return (READ_REG(AESx->SEED_OSBOX));
1204 }
1205
1217 __STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
1218 {
1219 WRITE_REG(AESx->VECTOR_INIT[0], vector);
1220 }
1221
1233 __STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
1234 {
1235 WRITE_REG(AESx->VECTOR_INIT[1], vector);
1236 }
1237
1249 __STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
1250 {
1251 WRITE_REG(AESx->VECTOR_INIT[2], vector);
1252 }
1253
1265 __STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
1266 {
1267 WRITE_REG(AESx->VECTOR_INIT[3], vector);
1268 }
1269
1281 __STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
1282 {
1283 WRITE_REG(AESx->DATA_IN[0], data);
1284 }
1285
1297 __STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
1298 {
1299 WRITE_REG(AESx->DATA_IN[1], data);
1300 }
1301
1313 __STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
1314 {
1315 WRITE_REG(AESx->DATA_IN[2], data);
1316 }
1317
1329 __STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
1330 {
1331 WRITE_REG(AESx->DATA_IN[3], data);
1332 }
1333
1345 __STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
1346 {
1347 WRITE_REG(AESx->KPORT_MASK, mask);
1348 }
1349
1363 error_status_t ll_aes_deinit(aes_regs_t *AESx);
1364
1375 error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init);
1376
1383 void ll_aes_struct_init(ll_aes_init_t *p_aes_init);
1384
1389 #endif /* AES */
1390
1391 #ifdef __cplusplus
1392 }
1393 #endif
1394
1395 #endif /* __GR55XX_LL_AES_H__ */
1396
ll_aes_enable_read_key
__STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
Enable fetch key through AHB/key port.
Definition: gr55xx_ll_aes.h:330
ll_aes_enable_encryption
__STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
Enable AES encryption mode.
Definition: gr55xx_ll_aes.h:427
ll_aes_disable_encryption
__STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
Disable AES encryption mode.
Definition: gr55xx_ll_aes.h:442
ll_aes_set_vector_127_96
__STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[127:96].
Definition: gr55xx_ll_aes.h:1217
_ll_aes_init::p_key
uint32_t * p_key
Definition: gr55xx_ll_aes.h:80
ll_aes_disable_start
__STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
Disable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:255
ll_aes_get_data_63_32
__STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
Get AES output data[63:32].
Definition: gr55xx_ll_aes.h:934
ll_aes_get_data_127_96
__STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
Get AES output data[127:96].
Definition: gr55xx_ll_aes.h:904
ll_aes_set_key_type
__STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
Set ways to obtain AES key.
Definition: gr55xx_ll_aes.h:586
ll_aes_disable
__STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
Disable AES.
Definition: gr55xx_ll_aes.h:210
ll_aes_set_data_63_32
__STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
Set AES input data[63:32].
Definition: gr55xx_ll_aes.h:1313
ll_aes_set_key_95_64
__STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
Set AES key[95:64].
Definition: gr55xx_ll_aes.h:1045
ll_aes_init_t
struct _ll_aes_init ll_aes_init_t
LL AES Init Structure definition.
ll_aes_get_data_95_64
__STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
Get AES output data[95:64].
Definition: gr55xx_ll_aes.h:919
ll_aes_get_dma_write_address
__STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
Get AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:852
ll_aes_is_action_flag_dma_error
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
Indicate whether the DMA transfer error flag is set.
Definition: gr55xx_ll_aes.h:706
ll_aes_set_operation_mode
__STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
Set AES operation mode.
Definition: gr55xx_ll_aes.h:550
ll_aes_set_key_31_0
__STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
Set AES key[31:0].
Definition: gr55xx_ll_aes.h:1077
ll_aes_is_enabled_it_done
__STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt is enabled.
Definition: gr55xx_ll_aes.h:655
ll_aes_set_vector_63_32
__STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[63:32].
Definition: gr55xx_ll_aes.h:1249
ll_aes_set_vector_31_0
__STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[31:0].
Definition: gr55xx_ll_aes.h:1265
ll_aes_is_action_flag_ready
__STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
Indicate whether the ready flag is set.
Definition: gr55xx_ll_aes.h:676
ll_aes_is_enabled_full_mask
__STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
Indicate whether the AES full mask is enabled.
Definition: gr55xx_ll_aes.h:412
ll_aes_set_seed_in
__STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
Set AES input seed.
Definition: gr55xx_ll_aes.h:1093
ll_aes_enable_full_mask
__STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
Enable AES full mask.
Definition: gr55xx_ll_aes.h:382
ll_aes_deinit
error_status_t ll_aes_deinit(aes_regs_t *AESx)
De-initialize AES registers (Registers restored to their default values).
_ll_aes_init
LL AES Init Structure definition.
Definition: gr55xx_ll_aes.h:76
ll_aes_disable_dma_start
__STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
Disable AES DMA mode.
Definition: gr55xx_ll_aes.h:300
ll_aes_is_enabled_little_endian
__STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
Indicate whether the AES is in little endian.
Definition: gr55xx_ll_aes.h:532
ll_aes_enable_start
__STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
Enable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:240
_ll_aes_init::p_init_vector
uint32_t * p_init_vector
Definition: gr55xx_ll_aes.h:82
ll_aes_set_key_191_160
__STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
Set AES key[191:160].
Definition: gr55xx_ll_aes.h:997
ll_aes_set_dma_write_address
__STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
Set AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:837
ll_aes_get_key_size
__STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
Get AES key size.
Definition: gr55xx_ll_aes.h:367
ll_aes_get_seed_Imask
__STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
Get sbox input data's mask.
Definition: gr55xx_ll_aes.h:1170
ll_aes_init
error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init)
Initialize AES registers according to the specified parameters in p_aes_init.
ll_aes_is_action_flag_dma_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
Indicate whether the DMA transfer done flag is set.
Definition: gr55xx_ll_aes.h:691
ll_aes_set_first_block
__STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
Definition: gr55xx_ll_aes.h:487
ll_aes_get_key_type
__STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
Get ways to obtain AES key.
Definition: gr55xx_ll_aes.h:604
ll_aes_set_data_95_64
__STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
Set AES input data[95:64].
Definition: gr55xx_ll_aes.h:1297
ll_aes_is_action_flag_it_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt flag is set.
Definition: gr55xx_ll_aes.h:736
ll_aes_set_data_127_96
__STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
Set AES input data[127:96].
Definition: gr55xx_ll_aes.h:1281
ll_aes_set_key_63_32
__STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
Set AES key[63:32].
Definition: gr55xx_ll_aes.h:1061
ll_aes_set_key_address
__STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
Set AES key address in memory.
Definition: gr55xx_ll_aes.h:874
ll_aes_disable_little_endian
__STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
Disable AES in little endian.
Definition: gr55xx_ll_aes.h:517
ll_aes_is_enabled_encryption
__STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
Indicate whether the AES encryption mode is enabled.
Definition: gr55xx_ll_aes.h:457
ll_aes_set_vector_95_64
__STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[95:64].
Definition: gr55xx_ll_aes.h:1233
ll_aes_set_key_159_128
__STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
Set AES key[159:128].
Definition: gr55xx_ll_aes.h:1013
ll_aes_get_dma_read_address
__STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
Get AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:820
ll_aes_is_action_flag_key_valid
__STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
Indicate whether the key valid flag is set.
Definition: gr55xx_ll_aes.h:721
ll_aes_get_seed_out
__STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
Get AES output seed.
Definition: gr55xx_ll_aes.h:1139
ll_aes_get_seed_Osbox
__STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
Get sbox output data's mask.
Definition: gr55xx_ll_aes.h:1201
ll_aes_struct_init
void ll_aes_struct_init(ll_aes_init_t *p_aes_init)
Set each field of a ll_aes_init_t type structure to default value.
ll_aes_disable_it_done
__STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
Disable AES the done interrupt.
Definition: gr55xx_ll_aes.h:640
ll_aes_enable_little_endian
__STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
Enable AES in little endian.
Definition: gr55xx_ll_aes.h:502
ll_aes_set_dma_read_address
__STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
Set AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:805
ll_aes_enable_it_done
__STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
Enable AES the done interrupt.
Definition: gr55xx_ll_aes.h:625
ll_aes_set_seed_out
__STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
Set AES output seed.
Definition: gr55xx_ll_aes.h:1124
_ll_aes_init::key_size
uint32_t key_size
Definition: gr55xx_ll_aes.h:77
ll_aes_set_data_31_0
__STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
Set AES input data[31:0].
Definition: gr55xx_ll_aes.h:1329
ll_aes_get_operation_mode
__STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
Get AES operation mode.
Definition: gr55xx_ll_aes.h:567
ll_aes_get_key_address
__STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
Get AES key address in memory.
Definition: gr55xx_ll_aes.h:889
ll_aes_set_seed_Imask
__STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
Set sbox input data's mask.
Definition: gr55xx_ll_aes.h:1155
ll_aes_get_data_31_0
__STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
Get AES output data[31:0].
Definition: gr55xx_ll_aes.h:949
ll_aes_disable_full_mask
__STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
Disable AES full mask.
Definition: gr55xx_ll_aes.h:397
ll_aes_set_key_255_224
__STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
Set AES key[255:224].
Definition: gr55xx_ll_aes.h:965
ll_aes_is_enabled_dma_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
Indicate whether the AES DMA mode is enabled.
Definition: gr55xx_ll_aes.h:315
ll_aes_set_dma_transfer_block
__STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
Set AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:773
ll_aes_set_key_port_mask
__STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
Set AES fetch key port mask.
Definition: gr55xx_ll_aes.h:1345
ll_aes_get_seed_in
__STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
Get AES input seed.
Definition: gr55xx_ll_aes.h:1108
ll_aes_clear_flag_it_done
__STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
Clear the done interrupt flag.
Definition: gr55xx_ll_aes.h:751
ll_aes_enable_dma_start
__STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
Enable AES DMA mode.
Definition: gr55xx_ll_aes.h:285
ll_aes_set_seed_Osbox
__STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
Set sbox output data's mask.
Definition: gr55xx_ll_aes.h:1186
ll_aes_enable
__STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
Enable AES.
Definition: gr55xx_ll_aes.h:195
ll_aes_set_key_127_96
__STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
Set AES key[127:96].
Definition: gr55xx_ll_aes.h:1029
ll_aes_set_load_seed
__STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
Set AES to load seed for LFSR.
Definition: gr55xx_ll_aes.h:472
ll_aes_is_enabled_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
Indicate whether the AES start in MCU mode is enabled.
Definition: gr55xx_ll_aes.h:270
ll_aes_is_enabled
__STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
Indicate whether the AES is enabled.
Definition: gr55xx_ll_aes.h:225
ll_aes_set_key_223_192
__STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
Set AES key[223:192].
Definition: gr55xx_ll_aes.h:981
ll_aes_set_key_size
__STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
Set AES key size.
Definition: gr55xx_ll_aes.h:349
_ll_aes_init::p_seed
uint32_t * p_seed
Definition: gr55xx_ll_aes.h:84
ll_aes_get_dma_transfer_block
__STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
Get AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:788