gr55xx_ll_pwr.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos)
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos)
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos)
86 /* Private macros ------------------------------------------------------------*/
87
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136 AON_SLP_EVENT_TIMER | \
137 AON_SLP_EVENT_EXTWKUP | \
138 AON_SLP_EVENT_PMU_BOD_FEDGE | \
139 AON_SLP_EVENT_PMU_MSIO_COMP | \
140 AON_SLP_EVENT_WDT_REBOOT | \
141 AON_SLP_EVENT_CALENDAR_TIMER_ALARM)
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U)
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U)
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U)
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U)
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U)
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U)
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U)
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U)
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU)
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
162 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
163 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U)
164 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
170 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK
171 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON
172 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD
173 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP
174 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF
175 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK
176 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK
177 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK
178 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK
179 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG
180 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG
181 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI
182 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO
183 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0
184 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1
185 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2
186 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3
195 #define LL_PWR_DPAD_LE_OFF (0x00000000U)
196 #define LL_PWR_DPAD_LE_ON (0x00000001U)
203 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER
204 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT
205 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER
206 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM
212 /* Exported macro ------------------------------------------------------------*/
213
227 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
228
234 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
235
237 /* Exported functions --------------------------------------------------------*/
263 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
264 {
265 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
266 }
267
284 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
285 {
286 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
287 }
288
309 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
310 {
311 return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
312 }
313
331 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
332 {
333 GLOBAL_EXCEPTION_DISABLE();
334 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
335 GLOBAL_EXCEPTION_ENABLE();
336 }
337
355 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
356 {
357 GLOBAL_EXCEPTION_DISABLE();
358 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
359 GLOBAL_EXCEPTION_ENABLE();
360 }
361
379 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
380 {
381 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
382 }
383
407 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
408 {
409 uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
410 uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
411 GLOBAL_EXCEPTION_DISABLE();
412 MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
413 GLOBAL_EXCEPTION_ENABLE();
414 }
415
439 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
440 {
441 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
442 }
443
456 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
457 {
458 WRITE_REG(AON->TIMER_VALUE, value);
459 }
460
470 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
471 {
472 return READ_REG(AON->TIMER_VALUE);
473 }
474
485 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
486 {
487 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
488 }
489
500 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
501 {
502 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
503 }
504
514 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
515 {
516 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
517 }
518
535 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
536 {
537 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
538 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
539 }
540
574 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
575 {
576 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
577 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
578 }
579
597 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
598 {
599 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
600 }
601
612 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
613 {
614 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
615 }
616
626 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
627 {
628 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
629 }
630
643 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
644 {
645 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
646 }
647
658 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
659 {
660 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
661 }
662
672 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
673 {
674 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
675 }
676
687 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
688 {
689 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
690 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
691 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
692 }
693
704 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
705 {
706 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
707 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
708 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
709 }
710
721 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
722 {
723 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
724 }
725
736 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
737 {
738 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
739 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
740 }
741
752 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
753 {
754 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
755 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
756 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
757 }
758
769 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
770 {
771 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
772 }
773
788 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
789 {
790 GLOBAL_EXCEPTION_DISABLE();
791 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
792 GLOBAL_EXCEPTION_ENABLE();
793 }
794
808 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
809 {
810 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
811 }
812
827 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
828 {
829 return ((uint32_t)READ_REG(AON->TIMER_VAL));
830 }
831
841 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
842 {
843 GLOBAL_EXCEPTION_DISABLE();
844 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
845 GLOBAL_EXCEPTION_ENABLE();
846 }
847
848
859 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
860 {
861 GLOBAL_EXCEPTION_DISABLE();
862 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
863 GLOBAL_EXCEPTION_ENABLE();
864 }
865
875 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
876 {
877 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
878 }
879
889 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
890 {
891 GLOBAL_EXCEPTION_DISABLE();
892 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
893 GLOBAL_EXCEPTION_ENABLE();
894 }
895
906 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
907 {
908 GLOBAL_EXCEPTION_DISABLE();
909 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
910 GLOBAL_EXCEPTION_ENABLE();
911 }
912
922 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
923 {
924 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
925 }
926
937 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
938 {
939 GLOBAL_EXCEPTION_DISABLE();
940 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
941 GLOBAL_EXCEPTION_ENABLE();
942 }
943
954 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
955 {
956 GLOBAL_EXCEPTION_DISABLE();
957 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
958 GLOBAL_EXCEPTION_ENABLE();
959 }
960
970 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
971 {
972 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
973 }
974
986 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
987 {
988 GLOBAL_EXCEPTION_DISABLE();
989 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
990 GLOBAL_EXCEPTION_ENABLE();
991 }
992
1003 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1004 {
1005 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1006 }
1007
1018 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1019 {
1020 GLOBAL_EXCEPTION_DISABLE();
1021 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1022 GLOBAL_EXCEPTION_ENABLE();
1023 }
1024
1035 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1036 {
1037 GLOBAL_EXCEPTION_DISABLE();
1038 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1039 GLOBAL_EXCEPTION_ENABLE();
1040 }
1041
1051 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1052 {
1053 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1054 }
1055
1066 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1067 {
1068 WRITE_REG(AON->PWR_RET28, time);
1069 }
1070
1080 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1081 {
1082 return ((uint32_t)READ_REG(AON->PWR_RET28));
1083 }
1084
1085
1095 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1096 {
1097 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1098 }
1099
1116 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1117 {
1118 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1119 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1120 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1121 }
1122
1123
1135 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1136 {
1137 return ((uint32_t)READ_REG(AON->PWR_RET29));
1138 }
1139
1145 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1146 {
1147 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1148 }
1149
1150
1174 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1175 {
1176 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1177 (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1178 }
1179
1197 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1198 {
1199 GLOBAL_EXCEPTION_DISABLE();
1200 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1201 GLOBAL_EXCEPTION_ENABLE();
1202 }
1203
1224 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1225 {
1226 WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1227 }
1228
1240 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1241 {
1242 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1243 }
1244
1255 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1256 {
1257 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1258 }
1259
1270 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1271 {
1272 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1273 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
1274 }
1275
1281 #endif /* defined(AON) */
1282
1283 #ifdef __cplusplus
1284 }
1285 #endif
1286
1287 #endif /* __GR55xx_LL_PWR_H__ */
1288
ll_pwr_disable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1035
ll_pwr_enable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:485
ll_pwr_get_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
Get which timer value was selected to read.
Definition: gr55xx_ll_pwr.h:808
ll_pwr_enable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1018
ll_pwr_set_dpad_le_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
Definition: gr55xx_ll_pwr.h:535
ll_pwr_disable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
Definition: gr55xx_ll_pwr.h:906
ll_pwr_is_enabled_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1003
ll_pwr_is_enabled_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:769
ll_pwr_set_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
Set the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:407
ll_pwr_is_enabled_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:970
ll_pwr_disable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
Definition: gr55xx_ll_pwr.h:658
ll_pwr_get_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1174
ll_pwr_read_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1135
ll_pwr_get_timer_read_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
Get current timer value based on the selection.
Definition: gr55xx_ll_pwr.h:827
ll_pwr_disable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
Definition: gr55xx_ll_pwr.h:859
ll_pwr_disable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
Definition: gr55xx_ll_pwr.h:612
ll_pwr_set_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:263
LL_PWR_EXTWKUP_PIN_ALL
#define LL_PWR_EXTWKUP_PIN_ALL
Definition: gr55xx_ll_pwr.h:155
ll_pwr_read_comm_wakeup_timing_twosc
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1145
ll_pwr_get_comm_sleep_duration
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
Definition: gr55xx_ll_pwr.h:1095
ll_pwr_set_comm_core_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1066
ll_pwr_is_enabled_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:672
ll_pwr_set_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:456
ll_pwr_is_active_flag_psc_cmd_busy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
Indicate if the Power State Controller is in busy state.
Definition: gr55xx_ll_pwr.h:1240
ll_pwr_enable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
Definition: gr55xx_ll_pwr.h:736
ll_pwr_disable_cache_module
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
Definition: gr55xx_ll_pwr.h:1270
ll_pwr_is_enabled_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
Check if the External WakeUp PINx functionality is enabled.
Definition: gr55xx_ll_pwr.h:379
ll_pwr_enable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
Definition: gr55xx_ll_pwr.h:643
ll_pwr_clear_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1197
ll_pwr_set_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
Select which timer value to read.
Definition: gr55xx_ll_pwr.h:788
ll_pwr_disable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:500
LL_PWR_WKUP_EVENT_ALL
#define LL_PWR_WKUP_EVENT_ALL
Definition: gr55xx_ll_pwr.h:135
LL_PWR_EXTWKUP_INVERT_LSB
#define LL_PWR_EXTWKUP_INVERT_LSB
Definition: gr55xx_ll_pwr.h:80
ll_pwr_is_enabled_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:514
ll_pwr_enable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
Definition: gr55xx_ll_pwr.h:597
ll_pwr_is_active_flag_comm_deep_sleep_stat
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1255
ll_pwr_disable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
Definition: gr55xx_ll_pwr.h:752
ll_pwr_clear_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:1224
ll_pwr_disable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
Disable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:355
ll_pwr_get_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:284
ll_pwr_enable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
Definition: gr55xx_ll_pwr.h:687
ll_pwr_set_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1116
ll_pwr_enable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:937
ll_pwr_disable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:954
ll_pwr_enable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
Enable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:331
ll_pwr_is_enabled_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1051
LL_PWR_EXTWKUP_TYPE_LSB
#define LL_PWR_EXTWKUP_TYPE_LSB
Definition: gr55xx_ll_pwr.h:79
ll_pwr_enable_comm_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
Definition: gr55xx_ll_pwr.h:986
ll_pwr_enable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
Definition: gr55xx_ll_pwr.h:889
ll_pwr_get_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:309
ll_pwr_enable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
Definition: gr55xx_ll_pwr.h:841
ll_pwr_get_comm_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1080
ll_pwr_is_enabled_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:626
ll_pwr_is_enabled_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:721
ll_pwr_get_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:470
ll_pwr_get_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
Get the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:439
ll_pwr_is_enabled_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:922
ll_pwr_is_enabled_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:875
ll_pwr_req_excute_psc_command
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
Request to excute the Power State Controller Command.
Definition: gr55xx_ll_pwr.h:574
ll_pwr_disable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
Definition: gr55xx_ll_pwr.h:704