gr55xx_ll_aon_gpio.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin;
81 uint32_t mode;
86 uint32_t pull;
91 uint32_t mux;
97 uint32_t trigger;
99 } ll_aon_gpio_init_t;
100
110 /* Exported constants --------------------------------------------------------*/
118 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U)
119 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U)
120 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U)
121 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U)
122 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U)
123 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U)
124 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U)
125 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U)
126 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU)
132 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U)
133 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U)
134 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U)
140 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N
141 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP
142 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U)
148 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U)
149 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U)
150 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U)
151 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U)
152 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U)
153 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U)
154 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U)
155 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U)
156 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U)
163 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U)
164 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U)
165 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U)
166 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U)
167 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U)
172 /* Exported macro ------------------------------------------------------------*/
173
188 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
189
196 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
197
202 /* Private types -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private constants ---------------------------------------------------------*/
205 /* Private macros ------------------------------------------------------------*/
213 #define LL_AON_GPIO_RE_N_Pos AON_PAD_CTL0_GPO_RE_N_Pos
214 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos)
215 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk
221 #define LL_AON_GPIO_RTYP_Pos AON_PAD_CTL0_GPO_RTYPE_Pos
222 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos)
223 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk
233 #define LL_AON_GPIO_DEFAULT_CONFIG \
234 { \
235 .pin = LL_AON_GPIO_PIN_ALL, \
236 .mode = LL_AON_GPIO_MODE_INPUT, \
237 .pull = LL_AON_GPIO_PULL_DOWN, \
238 .mux = LL_AON_GPIO_MUX_7, \
239 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
240 }
241
247 /* Exported functions --------------------------------------------------------*/
278 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
279 {
280 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
281 GLOBAL_EXCEPTION_DISABLE();
282 MODIFY_REG(AON->AON_PAD_CTL1, pin_mask, (mode == LL_AON_GPIO_MODE_INPUT) ? pin_mask : 0);
283 GLOBAL_EXCEPTION_ENABLE();
284 }
285
308 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
309 {
310 pin = (pin << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
311 return ((uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin) == LL_AON_GPIO_MODE_INPUT) ?
312 LL_AON_GPIO_MODE_OUTPUT : LL_AON_GPIO_MODE_INPUT);
313 }
314
340 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
341 {
342 uint32_t RTypeMask = (pin_mask << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
343 uint32_t REnMask = (pin_mask << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
344 uint32_t RType = (pull == LL_AON_GPIO_PULL_UP) ? RTypeMask : 0x0000U;
345 uint32_t REn = (pull == LL_AON_GPIO_PULL_NO) ? REnMask : 0x0000U;
346 MODIFY_REG(AON->AON_PAD_CTL0, REnMask | RTypeMask, REn | RType);
347 }
348
372 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
373 {
374 uint32_t RTypeMask = (pin << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
375 uint32_t REnMask = (pin << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
376 //return (READ_BITS(AON->AON_PAD_CTL0, REnMask | RTypeMask) >> POSITION_VAL(Pin));
377 return ((READ_BITS(AON->AON_PAD_CTL0, REnMask) != RESET) ? LL_AON_GPIO_PULL_NO :
378 ((READ_BITS(AON->AON_PAD_CTL0, RTypeMask) != RESET) ? LL_AON_GPIO_PULL_UP : LL_AON_GPIO_PULL_DOWN));
379 }
380
412 __STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
413 {
414 uint32_t pos = POSITION_VAL(pin) << 2;
415 if(LL_AON_GPIO_MUX_7 == mux)
416 {
417 CLEAR_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
418 }
419 else
420 {
421 MODIFY_REG(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
422 SET_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
423 }
424 }
425
454 __STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
455 {
456 if(READ_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos))
457 {
458 uint32_t pos = POSITION_VAL(pin) << 2;
459 return (READ_BITS(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
460 }
461 else
462 {
463 return LL_AON_GPIO_MUX_7;
464 }
465 }
466
476 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
477 {
478 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
479 }
480
490 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
491 {
492 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
493 }
494
504 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
505 {
506 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA) == AON_PWR_REG01_XO_2MHZ_ENA);
507 }
508
524 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
525 {
526 return (uint32_t)(READ_BITS(GPIO2->DATA, GPIO_DATA));
527 }
528
548 __STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
549 {
550 return (uint32_t)(READ_BITS(GPIO2->DATA, pin_mask) == pin_mask);
551 }
552
563 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
564 {
565 GLOBAL_EXCEPTION_DISABLE();
566 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO, (port_value << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
567 GLOBAL_EXCEPTION_ENABLE();
568 }
569
579 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
580 {
581 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO) >> AON_PAD_CTL1_AON_GPO_Pos);
582 }
583
603 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
604 {
605 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO;
606 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin_mask) == pin_mask);
607 }
608
628 __STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
629 {
630 GLOBAL_EXCEPTION_DISABLE();
631 SET_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
632 GLOBAL_EXCEPTION_ENABLE();
633 }
634
654 __STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
655 {
656 GLOBAL_EXCEPTION_DISABLE();
657 CLEAR_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
658 GLOBAL_EXCEPTION_ENABLE();
659 }
660
680 __STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
681 {
682 GLOBAL_EXCEPTION_DISABLE();
683 WRITE_REG(AON->AON_PAD_CTL1, (READ_REG(AON->AON_PAD_CTL1) ^ ((pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO)));
684 GLOBAL_EXCEPTION_ENABLE();
685 }
686
713 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
714 {
715 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
716 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
717 }
718
739 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
740 {
741 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
742 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
743 }
744
765 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
766 {
767 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
768 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
769 }
770
792 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
793 {
794 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
795 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
796 }
797
818 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
819 {
820 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
821 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
822 }
823
844 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
845 {
846 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
847 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
848 }
849
870 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
871 {
872 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
873 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
874 }
875
896 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
897 {
898 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
899 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
900 }
901
922 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
923 {
924 WRITE_REG(GPIO2->INTENSET, pin_mask);
925 }
926
947 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
948 {
949 WRITE_REG(GPIO2->INTENCLR, pin_mask);
950 }
951
971 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
972 {
973 return (READ_BITS(GPIO2->INTENSET, pin_mask) == (pin_mask));
974 }
975
1003 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1004 {
1005 uint32_t ext2 = READ_BITS(GPIO2->INTSTAT, pin_mask);
1006 uint32_t wkup = (READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1007 pin_mask & READ_BITS(AON->EXT_WKUP_CTL, LL_AON_GPIO_PIN_ALL);
1008 return (uint32_t)(ext2 | wkup);
1009 }
1010
1032 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1033 {
1034 return (READ_BITS(GPIO2->INTSTAT, pin_mask) == pin_mask);
1035 }
1036
1058 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1059 {
1060 WRITE_REG(GPIO2->INTSTAT, pin_mask);
1061 }
1062
1075 error_status_t ll_aon_gpio_deinit(void);
1076
1086 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1087
1094 void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1095
1100 #endif /* AON */
1101
1102 #ifdef __cplusplus
1103 }
1104 #endif
1105
1106 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1107
LL_AON_GPIO_PULL_UP
#define LL_AON_GPIO_PULL_UP
Definition: gr55xx_ll_aon_gpio.h:141
LL_AON_GPIO_PIN_ALL
#define LL_AON_GPIO_PIN_ALL
Definition: gr55xx_ll_aon_gpio.h:126
_ll_aon_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_aon_gpio.h:86
ll_aon_gpio_disable_it
__STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
Disable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:947
ll_aon_gpio_is_enabled_xo_2mhz_output
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:504
ll_aon_gpio_set_pin_pull
__STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:340
ll_aon_gpio_clear_flag_it
__STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
Clear Interrupt Status flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1058
ll_aon_gpio_struct_init
void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Set each field of a ll_aon_gpio_init_t type structure to default value.
ll_aon_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:971
ll_aon_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:603
ll_aon_gpio_reset_output_pin
__STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to low level.
Definition: gr55xx_ll_aon_gpio.h:654
ll_aon_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1032
ll_aon_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:372
ll_aon_gpio_write_output_port
__STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
Write output data register of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:563
LL_AON_GPIO_MODE_OUTPUT
#define LL_AON_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_aon_gpio.h:133
ll_aon_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:548
ll_aon_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:412
ll_aon_gpio_enable_low_trigger
__STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:870
LL_AON_GPIO_PULL_DOWN
#define LL_AON_GPIO_PULL_DOWN
Definition: gr55xx_ll_aon_gpio.h:142
ll_aon_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
Return gpio mode for a AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:308
ll_aon_gpio_enable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
Enable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:476
LL_AON_GPIO_MODE_INPUT
#define LL_AON_GPIO_MODE_INPUT
Definition: gr55xx_ll_aon_gpio.h:132
_ll_aon_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_aon_gpio.h:81
ll_aon_gpio_disable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
Disable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:490
ll_aon_gpio_toggle_pin
__STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:680
ll_aon_gpio_enable_falling_trigger
__STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:713
_ll_aon_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_aon_gpio.h:97
_ll_aon_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_aon_gpio.h:91
ll_aon_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:454
LL_AON_GPIO_MUX_7
#define LL_AON_GPIO_MUX_7
Definition: gr55xx_ll_aon_gpio.h:155
ll_aon_gpio_set_output_pin
__STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to high level.
Definition: gr55xx_ll_aon_gpio.h:628
_ll_aon_gpio_init
LL AON_GPIO init Structure definition.
Definition: gr55xx_ll_aon_gpio.h:77
ll_aon_gpio_deinit
error_status_t ll_aon_gpio_deinit(void)
De-initialize AON_GPIO registers (Registers restored to their default values).
ll_aon_gpio_enable_high_trigger
__STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:818
_ll_aon_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_aon_gpio.h:78
ll_aon_gpio_read_input_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
Return full input data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:524
ll_aon_gpio_init
error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Initialize AON_GPIO registers according to the specified. parameters in p_aon_gpio_init.
LL_AON_GPIO_PULL_NO
#define LL_AON_GPIO_PULL_NO
Definition: gr55xx_ll_aon_gpio.h:140
ll_aon_gpio_read_output_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
Return full output data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:579
ll_aon_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
Check if high level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:844
ll_aon_gpio_set_pin_mode
__STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several AON_GPIO pins to input/output mode.
Definition: gr55xx_ll_aon_gpio.h:278
ll_aon_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
Check if falling edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:739
ll_aon_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1003
ll_aon_gpio_init_t
struct _ll_aon_gpio_init ll_aon_gpio_init_t
LL AON_GPIO init Structure definition.
ll_aon_gpio_enable_it
__STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
Enable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:922
ll_aon_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
Check if low level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:896
ll_aon_gpio_enable_rising_trigger
__STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:765
ll_aon_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
Check if rising edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:792