gr55xx_hal_qspi.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_QSPI_H__
53 #define __GR55xx_HAL_QSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_spi.h"
61 #include "gr55xx_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
75 typedef enum
76 {
77 HAL_QSPI_STATE_RESET = 0x00,
78 HAL_QSPI_STATE_READY = 0x01,
79 HAL_QSPI_STATE_BUSY = 0x02,
80 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12,
81 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22,
82 HAL_QSPI_STATE_ABORT = 0x08,
83 HAL_QSPI_STATE_ERROR = 0x04
85 } hal_qspi_state_t;
86
102 typedef struct _qspi_init_t
103 {
104 uint32_t clock_prescaler;
107 uint32_t clock_mode;
110 uint32_t rx_sample_delay;
112 } qspi_init_t;
122 typedef struct _qspi_handle
123 {
124 ssi_regs_t *p_instance;
126 qspi_init_t init;
128 uint8_t *p_tx_buffer;
130 __IO uint32_t tx_xfer_size;
132 __IO uint32_t tx_xfer_count;
134 uint8_t *p_rx_buffer;
136 __IO uint32_t rx_xfer_size;
138 __IO uint32_t rx_xfer_count;
140 void (*write_fifo)(struct _qspi_handle *p_qspi);
142 void (*read_fifo)(struct _qspi_handle *p_qspi);
144 dma_handle_t *p_dma;
146 __IO hal_lock_t lock;
148 __IO hal_qspi_state_t state;
150 __IO uint32_t error_code;
152 uint32_t timeout;
154 uint32_t retention[9];
155 } qspi_handle_t;
165 typedef struct _qspi_command_t
166 {
167 uint32_t instruction;
170 uint32_t address;
173 uint32_t instruction_size;
176 uint32_t address_size;
179 uint32_t dummy_cycles;
182 uint32_t data_size;
185 uint32_t instruction_address_mode;
188 uint32_t data_mode;
191 uint32_t length;
195 } qspi_command_t;
212 typedef struct _hal_qspi_callback
213 {
214 void (*qspi_msp_init)(qspi_handle_t *p_qspi);
215 void (*qspi_msp_deinit)(qspi_handle_t *p_qspi);
216 void (*qspi_error_callback)(qspi_handle_t *p_qspi);
217 void (*qspi_abort_cplt_callback)(qspi_handle_t *p_qspi);
218 void (*qspi_fifo_threshold_callback)(qspi_handle_t *p_qspi);
219 void (*qspi_rx_cplt_callback)(qspi_handle_t *p_qspi);
220 void (*qspi_tx_cplt_callback)(qspi_handle_t *p_qspi);
221 } hal_qspi_callback_t;
222
232 /* Exported constants --------------------------------------------------------*/
240 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
241 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
242 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
243 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
244 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
250 #define QSPI_CLOCK_MODE_0 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_1EDGE)
252 #define QSPI_CLOCK_MODE_1 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_2EDGE)
254 #define QSPI_CLOCK_MODE_2 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_1EDGE)
256 #define QSPI_CLOCK_MODE_3 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_2EDGE)
263 #define QSPI_DATA_MODE_SPI LL_SSI_FRF_SPI
264 #define QSPI_DATA_MODE_DUALSPI LL_SSI_FRF_DUALSPI
265 #define QSPI_DATA_MODE_QUADSPI LL_SSI_FRF_QUADSPI
271 #define QSPI_INSTSIZE_00_BITS LL_SSI_INSTSIZE_0BIT
272 #define QSPI_INSTSIZE_04_BITS LL_SSI_INSTSIZE_4BIT
273 #define QSPI_INSTSIZE_08_BITS LL_SSI_INSTSIZE_8BIT
274 #define QSPI_INSTSIZE_16_BITS LL_SSI_INSTSIZE_16BIT
280 #define QSPI_ADDRSIZE_00_BITS LL_SSI_ADDRSIZE_0BIT
281 #define QSPI_ADDRSIZE_04_BITS LL_SSI_ADDRSIZE_4BIT
282 #define QSPI_ADDRSIZE_08_BITS LL_SSI_ADDRSIZE_8BIT
283 #define QSPI_ADDRSIZE_12_BITS LL_SSI_ADDRSIZE_12BIT
284 #define QSPI_ADDRSIZE_16_BITS LL_SSI_ADDRSIZE_16BIT
285 #define QSPI_ADDRSIZE_20_BITS LL_SSI_ADDRSIZE_20BIT
286 #define QSPI_ADDRSIZE_24_BITS LL_SSI_ADDRSIZE_24BIT
287 #define QSPI_ADDRSIZE_28_BITS LL_SSI_ADDRSIZE_28BIT
288 #define QSPI_ADDRSIZE_32_BITS LL_SSI_ADDRSIZE_32BIT
294 #define QSPI_DATASIZE_04_BITS LL_SSI_DATASIZE_4BIT
295 #define QSPI_DATASIZE_05_BITS LL_SSI_DATASIZE_5BIT
296 #define QSPI_DATASIZE_06_BITS LL_SSI_DATASIZE_6BIT
297 #define QSPI_DATASIZE_07_BITS LL_SSI_DATASIZE_7BIT
298 #define QSPI_DATASIZE_08_BITS LL_SSI_DATASIZE_8BIT
299 #define QSPI_DATASIZE_09_BITS LL_SSI_DATASIZE_9BIT
300 #define QSPI_DATASIZE_10_BITS LL_SSI_DATASIZE_10BIT
301 #define QSPI_DATASIZE_11_BITS LL_SSI_DATASIZE_11BIT
302 #define QSPI_DATASIZE_12_BITS LL_SSI_DATASIZE_12BIT
303 #define QSPI_DATASIZE_13_BITS LL_SSI_DATASIZE_13BIT
304 #define QSPI_DATASIZE_14_BITS LL_SSI_DATASIZE_14BIT
305 #define QSPI_DATASIZE_15_BITS LL_SSI_DATASIZE_15BIT
306 #define QSPI_DATASIZE_16_BITS LL_SSI_DATASIZE_16BIT
307 #define QSPI_DATASIZE_17_BITS LL_SSI_DATASIZE_17BIT
308 #define QSPI_DATASIZE_18_BITS LL_SSI_DATASIZE_18BIT
309 #define QSPI_DATASIZE_19_BITS LL_SSI_DATASIZE_19BIT
310 #define QSPI_DATASIZE_20_BITS LL_SSI_DATASIZE_20BIT
311 #define QSPI_DATASIZE_21_BITS LL_SSI_DATASIZE_21BIT
312 #define QSPI_DATASIZE_22_BITS LL_SSI_DATASIZE_22BIT
313 #define QSPI_DATASIZE_23_BITS LL_SSI_DATASIZE_23BIT
314 #define QSPI_DATASIZE_24_BITS LL_SSI_DATASIZE_24BIT
315 #define QSPI_DATASIZE_25_BITS LL_SSI_DATASIZE_25BIT
316 #define QSPI_DATASIZE_26_BITS LL_SSI_DATASIZE_26BIT
317 #define QSPI_DATASIZE_27_BITS LL_SSI_DATASIZE_27BIT
318 #define QSPI_DATASIZE_28_BITS LL_SSI_DATASIZE_28BIT
319 #define QSPI_DATASIZE_29_BITS LL_SSI_DATASIZE_29BIT
320 #define QSPI_DATASIZE_30_BITS LL_SSI_DATASIZE_30BIT
321 #define QSPI_DATASIZE_31_BITS LL_SSI_DATASIZE_31BIT
322 #define QSPI_DATASIZE_32_BITS LL_SSI_DATASIZE_32BIT
330 #define QSPI_INST_ADDR_ALL_IN_SPI LL_SSI_INST_ADDR_ALL_IN_SPI
331 #define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
332 #define QSPI_INST_ADDR_ALL_IN_SPIFRF LL_SSI_INST_ADDR_ALL_IN_SPIFRF
338 #define QSPI_FLAG_DCOL LL_SSI_SR_DCOL
339 #define QSPI_FLAG_TXE LL_SSI_SR_TXE
340 #define QSPI_FLAG_RFF LL_SSI_SR_RFF
341 #define QSPI_FLAG_RFNE LL_SSI_SR_RFNE
342 #define QSPI_FLAG_TFE LL_SSI_SR_TFE
343 #define QSPI_FLAG_TFNF LL_SSI_SR_TFNF
344 #define QSPI_FLAG_BUSY LL_SSI_SR_BUSY
350 #define QSPI_IT_MST LL_SSI_IS_MST
351 #define QSPI_IT_RXF LL_SSI_IS_RXF
352 #define QSPI_IT_RXO LL_SSI_IS_RXO
353 #define QSPI_IT_RXU LL_SSI_IS_RXU
354 #define QSPI_IT_TXO LL_SSI_IS_TXO
355 #define QSPI_IT_TXE LL_SSI_IS_TXE
361 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)
366 /* Exported macro ------------------------------------------------------------*/
367
375 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_QSPI_STATE_RESET)
376
381 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->SSI_EN, SSI_SSIEN_EN)
382
387 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->SSI_EN, SSI_SSIEN_EN)
388
393 #define __HAL_QSPI_ENABLE_DMATX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_TDMAE)
394
399 #define __HAL_QSPI_ENABLE_DMARX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_RDMAE)
400
405 #define __HAL_QSPI_DISABLE_DMATX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_TDMAE)
406
411 #define __HAL_QSPI_DISABLE_DMARX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_RDMAE)
412
425 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
426
439 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
440
453 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BITS((__HANDLE__)->p_instance->INTSTAT, (__INTERRUPT__)) == (__INTERRUPT__))
454
468 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__)) != 0) ? SET : RESET)
469
483 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__))
484
487 /* Private macros ------------------------------------------------------------*/
496 #define IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
497
502 #define IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= 7))
503
508 #define IS_QSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
509 ((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
510 ((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
511 ((__CLKMODE__) == QSPI_CLOCK_MODE_3))
512
517 #define IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
518 ((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
519 ((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
520 ((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))
521
526 #define IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
527 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
528 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
529 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
530 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
531 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
532 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
533 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
534 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))
535
540 #define IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
541
546 #define IS_QSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
547 ((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
548 ((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))
549
554 #define IS_QSPI_DATA_MODE(__MODE__) (((__MODE__) == QSPI_DATA_MODE_SPI) || \
555 ((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
556 ((__MODE__) == QSPI_DATA_MODE_QUADSPI))
557
563 /* Exported functions --------------------------------------------------------*/
604 hal_status_t hal_qspi_init(qspi_handle_t *p_qspi);
605
616 hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi);
617
626 void hal_qspi_msp_init(qspi_handle_t *p_qspi);
627
636 void hal_qspi_msp_deinit(qspi_handle_t *p_qspi);
637
687 hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
688
703 hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
704
718 hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout);
719
734 hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout);
735
750 hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout);
751
765 hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
766
780 hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
781
794 hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
795
809 hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length);
810
824 hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length);
825
839 hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
840
854 hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data);
855
868 hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd);
869
883 hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length);
884
898 hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length);
899
910 hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi);
911
922 hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi);
923
937 void hal_qspi_irq_handler(qspi_handle_t *p_qspi);
938
945 void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi);
946
953 void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi);
954
961 void hal_qspi_error_callback(qspi_handle_t *p_qspi);
962
969 void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi);
970
977 void hal_qspi_fifo_threshold_callback(qspi_handle_t *p_qspi);
978
1014 hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi);
1015
1023 uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi);
1024
1036 void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout);
1037
1049 hal_status_t hal_qspi_set_tx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold);
1050
1062 hal_status_t hal_qspi_set_rx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold);
1063
1071 uint32_t hal_qspi_get_tx_fifo_threshold(qspi_handle_t *p_qspi);
1072
1080 uint32_t hal_qspi_get_rx_fifo_threshold(qspi_handle_t *p_qspi);
1081
1093 hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi);
1094
1107 hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi);
1108
1113 #ifdef __cplusplus
1114 }
1115 #endif
1116
1117 #endif /* __GR55xx_HAL_QSPI_H__ */
1118
_hal_qspi_callback::qspi_msp_deinit
void(* qspi_msp_deinit)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:215
_qspi_handle::tx_xfer_size
__IO uint32_t tx_xfer_size
Definition: gr55xx_hal_qspi.h:130
_qspi_command_t::instruction_size
uint32_t instruction_size
Definition: gr55xx_hal_qspi.h:173
_qspi_handle::timeout
uint32_t timeout
Definition: gr55xx_hal_qspi.h:152
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
hal_qspi_fifo_threshold_callback
void hal_qspi_fifo_threshold_callback(qspi_handle_t *p_qspi)
FIFO Threshold callback.
_hal_qspi_callback::qspi_rx_cplt_callback
void(* qspi_rx_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:219
_qspi_command_t::data_size
uint32_t data_size
Definition: gr55xx_hal_qspi.h:182
hal_qspi_set_rx_fifo_threshold
hal_status_t hal_qspi_set_rx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold)
Set the RX FIFO threshold.
hal_qspi_get_rx_fifo_threshold
uint32_t hal_qspi_get_rx_fifo_threshold(qspi_handle_t *p_qspi)
Get the RX FIFO threshold.
hal_qspi_transmit_dma
hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with DMA.
hal_qspi_command_receive
hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
_qspi_command_t::instruction_address_mode
uint32_t instruction_address_mode
Definition: gr55xx_hal_qspi.h:185
HAL_QSPI_STATE_ABORT
@ HAL_QSPI_STATE_ABORT
Definition: gr55xx_hal_qspi.h:82
_hal_qspi_callback::qspi_fifo_threshold_callback
void(* qspi_fifo_threshold_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:218
_qspi_command_t::length
uint32_t length
Definition: gr55xx_hal_qspi.h:191
_qspi_handle::rx_xfer_size
__IO uint32_t rx_xfer_size
Definition: gr55xx_hal_qspi.h:136
_qspi_handle::state
__IO hal_qspi_state_t state
Definition: gr55xx_hal_qspi.h:148
hal_qspi_set_tx_fifo_threshold
hal_status_t hal_qspi_set_tx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold)
Set the TX FIFO threshold.
_hal_qspi_callback::qspi_error_callback
void(* qspi_error_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:216
_qspi_handle::rx_xfer_count
__IO uint32_t rx_xfer_count
Definition: gr55xx_hal_qspi.h:138
hal_qspi_deinit
hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI peripheral.
_qspi_handle::p_tx_buffer
uint8_t * p_tx_buffer
Definition: gr55xx_hal_qspi.h:128
_qspi_init_t
QSPI init Structure definition.
Definition: gr55xx_hal_qspi.h:103
hal_qspi_msp_init
void hal_qspi_msp_init(qspi_handle_t *p_qspi)
Initialize the QSPI MSP.
hal_qspi_receive
hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
HAL_QSPI_STATE_RESET
@ HAL_QSPI_STATE_RESET
Definition: gr55xx_hal_qspi.h:77
_qspi_command_t
QSPI command Structure definition.
Definition: gr55xx_hal_qspi.h:166
HAL_QSPI_STATE_READY
@ HAL_QSPI_STATE_READY
Definition: gr55xx_hal_qspi.h:78
_qspi_handle::p_instance
ssi_regs_t * p_instance
Definition: gr55xx_hal_qspi.h:124
_qspi_handle::write_fifo
void(* write_fifo)(struct _qspi_handle *p_qspi)
Definition: gr55xx_hal_qspi.h:140
hal_qspi_init
hal_status_t hal_qspi_init(qspi_handle_t *p_qspi)
Initialize the QSPI according to the specified parameters in the qspi_init_t and initialize the assoc...
_qspi_command_t::address_size
uint32_t address_size
Definition: gr55xx_hal_qspi.h:176
hal_qspi_msp_deinit
void hal_qspi_msp_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI MSP.
hal_qspi_command_transmit_it
hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with Inter...
hal_qspi_suspend_reg
hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi)
Suspend some registers related to QSPI configuration before sleep.
hal_qspi_tx_cplt_callback
void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi)
Tx Transfer completed callback.
hal_qspi_command_receive_dma
hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
hal_qspi_abort_cplt_callback
void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi)
QSPI Abort Complete callback.
hal_qspi_command_transmit
hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Transmit an amount of data with the specified instruction and address in blocking mode.
_hal_qspi_callback::qspi_tx_cplt_callback
void(* qspi_tx_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:220
_qspi_handle::p_dma
dma_handle_t * p_dma
Definition: gr55xx_hal_qspi.h:144
HAL_QSPI_STATE_ERROR
@ HAL_QSPI_STATE_ERROR
Definition: gr55xx_hal_qspi.h:83
_qspi_command_t::dummy_cycles
uint32_t dummy_cycles
Definition: gr55xx_hal_qspi.h:179
hal_qspi_irq_handler
void hal_qspi_irq_handler(qspi_handle_t *p_qspi)
Handle QSPI interrupt request.
hal_qspi_abort
hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi)
Abort the current transmission.
hal_qspi_receive_it
hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
_hal_qspi_callback
HAL_QSPI Callback function definition.
Definition: gr55xx_hal_qspi.h:213
hal_qspi_rx_cplt_callback
void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi)
Rx Transfer completed callback.
gr55xx_ll_spi.h
Header file containing functions prototypes of SPI LL library.
hal_qspi_abort_it
hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi)
Abort the current transmission (non-blocking function)
qspi_command_t
struct _qspi_command_t qspi_command_t
QSPI command Structure definition.
HAL_QSPI_STATE_BUSY_INDIRECT_RX
@ HAL_QSPI_STATE_BUSY_INDIRECT_RX
Definition: gr55xx_hal_qspi.h:81
_hal_qspi_callback::qspi_abort_cplt_callback
void(* qspi_abort_cplt_callback)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:217
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
hal_qspi_command
hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
_qspi_init_t::clock_prescaler
uint32_t clock_prescaler
Definition: gr55xx_hal_qspi.h:104
_qspi_handle::read_fifo
void(* read_fifo)(struct _qspi_handle *p_qspi)
Definition: gr55xx_hal_qspi.h:142
hal_qspi_receive_dma
hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with DMA.
_qspi_handle::error_code
__IO uint32_t error_code
Definition: gr55xx_hal_qspi.h:150
hal_qspi_resume_reg
hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi)
Restore some registers related to QSPI configuration after sleep. This function must be used in conju...
hal_qspi_command_receive_it
hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
_qspi_handle::init
qspi_init_t init
Definition: gr55xx_hal_qspi.h:126
_qspi_handle::lock
__IO hal_lock_t lock
Definition: gr55xx_hal_qspi.h:146
_qspi_command_t::instruction
uint32_t instruction
Definition: gr55xx_hal_qspi.h:167
_qspi_handle::tx_xfer_count
__IO uint32_t tx_xfer_count
Definition: gr55xx_hal_qspi.h:132
HAL_QSPI_STATE_BUSY_INDIRECT_TX
@ HAL_QSPI_STATE_BUSY_INDIRECT_TX
Definition: gr55xx_hal_qspi.h:80
hal_qspi_get_tx_fifo_threshold
uint32_t hal_qspi_get_tx_fifo_threshold(qspi_handle_t *p_qspi)
Get the TX FIFO threshold.
hal_qspi_command_transmit_dma
hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
hal_qspi_set_timeout
void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout)
Set the QSPI internal process timeout value.
qspi_handle_t
struct _qspi_handle qspi_handle_t
QSPI handle Structure definition.
hal_qspi_command_it
hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
_qspi_command_t::data_mode
uint32_t data_mode
Definition: gr55xx_hal_qspi.h:188
HAL_QSPI_STATE_BUSY
@ HAL_QSPI_STATE_BUSY
Definition: gr55xx_hal_qspi.h:79
qspi_init_t
struct _qspi_init_t qspi_init_t
QSPI init Structure definition.
hal_qspi_transmit
hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
hal_qspi_callback_t
struct _hal_qspi_callback hal_qspi_callback_t
HAL_QSPI Callback function definition.
hal_qspi_state_t
hal_qspi_state_t
HAL QSPI State Enumerations definition.
Definition: gr55xx_hal_qspi.h:76
hal_qspi_get_state
hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi)
Return the QSPI handle state.
_qspi_handle::retention
uint32_t retention[9]
Definition: gr55xx_hal_qspi.h:154
_hal_qspi_callback::qspi_msp_init
void(* qspi_msp_init)(qspi_handle_t *p_qspi)
Definition: gr55xx_hal_qspi.h:214
hal_qspi_command_dma
hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with DMA.
_qspi_handle::p_rx_buffer
uint8_t * p_rx_buffer
Definition: gr55xx_hal_qspi.h:134
_qspi_handle
QSPI handle Structure definition.
Definition: gr55xx_hal_qspi.h:123
_qspi_command_t::address
uint32_t address
Definition: gr55xx_hal_qspi.h:170
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:179
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_qspi_get_error
uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi)
Return the QSPI error code.
_qspi_init_t::clock_mode
uint32_t clock_mode
Definition: gr55xx_hal_qspi.h:107
hal_qspi_error_callback
void hal_qspi_error_callback(qspi_handle_t *p_qspi)
QSPI error callback.
hal_qspi_transmit_it
hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_hal_qspi.h:110