gr55xx_ll_cgc.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(MCU_SUB)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_cgc_init_t
77 {
78 uint32_t wfi_clk0;
81 uint32_t wfi_clk1;
84 uint32_t wfi_clk2;
87 uint32_t force_clk0;
90 uint32_t force_clk1;
93 uint32_t force_clk2;
95 } ll_cgc_init_t;
96
106 /* Exported constants --------------------------------------------------------*/
114 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK
115 #define LL_CGC_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK
116 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK
117 #define LL_CGC_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK
118 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK
119 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK
120 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK
121 #define LL_CGC_WFI_DMA_HCLK MCU_SUB_WFI_DMA_HCLK
122 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK
123 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK
124 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK
125 #define LL_CGC_WFI_I2S_S_HCLK MCU_SUB_WFI_I2S_S_HCLK
127 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x00000FFFU)
133 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK
134 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK
135 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK
137 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U)
143 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK
144 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK
146 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U)
153 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK
154 #define LL_CGC_FRC_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK
155 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK
156 #define LL_CGC_FRC_PWM_HCLK MCU_SUB_FORCE_PWM_HCLK
157 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK
158 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK
159 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK
160 #define LL_CGC_FRC_DMA_HCLK MCU_SUB_FORCE_DMA_HCLK
161 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK
162 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK
163 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK
164 #define LL_CGC_FRC_I2S_S_HCLK MCU_SUB_FORCE_I2S_S_HCLK
166 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000FFFU)
172 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK
173 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK
174 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK
176 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U)
182 #define LL_CGC_FRC_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK
183 #define LL_CGC_FRC_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK
184 #define LL_CGC_FRC_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK
185 #define LL_CGC_FRC_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK
186 #define LL_CGC_FRC_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK
187 #define LL_CGC_FRC_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK
188 #define LL_CGC_FRC_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK
189 #define LL_CGC_FRC_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK
190 #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK
191 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK
192 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK
194 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x0001FF00U)
195 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x0A01FF00U)
200 /* Exported macro ------------------------------------------------------------*/
201
216 #define LL_CGC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
217
224 #define LL_CGC_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
225
230 /* Private types -------------------------------------------------------------*/
231 /* Private variables ---------------------------------------------------------*/
232 /* Private constants ---------------------------------------------------------*/
233 /* Private macros ------------------------------------------------------------*/
245 #define LL_CGC_DEFAULT_CONFIG \
246 { \
247 .wfi_clk0 = ~LL_CGC_WFI_ALL_HCLK0, \
248 .wfi_clk1 = ~LL_CGC_WFI_ALL_HCLK1, \
249 .wfi_clk2 = ~LL_CGC_WFI_ALL_HCLK2, \
250 .force_clk0 = ~LL_CGC_FRC_ALL_HCLK0, \
251 .force_clk1 = ~LL_CGC_FRC_ALL_HCLK1, \
252 .force_clk2 = ~LL_CGC_FRC_ALL_HCLK2, \
253 }
254
261 /* Exported functions --------------------------------------------------------*/
304 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
305 {
306 WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], clk_mask);
307 }
308
342 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
343 {
344 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0]);
345 }
346
347
363 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
364 {
365 GLOBAL_EXCEPTION_DISABLE();
366 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1, clk_mask);
367 GLOBAL_EXCEPTION_ENABLE();
368 }
369
384 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
385 {
386 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1);
387 }
388
402 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
403 {
404 GLOBAL_EXCEPTION_DISABLE();
405 MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2, clk_mask);
406 GLOBAL_EXCEPTION_ENABLE();
407 }
408
421 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
422 {
423 return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2);
424 }
425
460 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
461 {
462 WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], clk_mask);
463 }
464
498 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
499 {
500 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1]);
501 }
502
503
519 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
520 {
521 GLOBAL_EXCEPTION_DISABLE();
522 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1, clk_mask);
523 GLOBAL_EXCEPTION_ENABLE();
524 }
525
540 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
541 {
542 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1);
543 }
544
577 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
578 {
579 GLOBAL_EXCEPTION_DISABLE();
580 MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2, clk_mask);
581 GLOBAL_EXCEPTION_ENABLE();
582 }
583
615 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
616 {
617 return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2);
618 }
619
629 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
630 {
631 GLOBAL_EXCEPTION_DISABLE();
632 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
633 GLOBAL_EXCEPTION_ENABLE();
634 }
635
645 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
646 {
647 GLOBAL_EXCEPTION_DISABLE();
648 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
649 GLOBAL_EXCEPTION_ENABLE();
650 }
651
661 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
662 {
663 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK) == (MCU_SUB_WFI_SECU_HCLK));
664 }
665
675 __STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
676 {
677 GLOBAL_EXCEPTION_DISABLE();
678 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
679 GLOBAL_EXCEPTION_ENABLE();
680 }
681
691 __STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
692 {
693 GLOBAL_EXCEPTION_DISABLE();
694 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
695 GLOBAL_EXCEPTION_ENABLE();
696 }
697
707 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
708 {
709 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK) == (MCU_SUB_WFI_SIM_HCLK));
710 }
711
721 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
722 {
723 GLOBAL_EXCEPTION_DISABLE();
724 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
725 GLOBAL_EXCEPTION_ENABLE();
726 }
727
737 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
738 {
739 GLOBAL_EXCEPTION_DISABLE();
740 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
741 GLOBAL_EXCEPTION_ENABLE();
742 }
743
753 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
754 {
755 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK) == (MCU_SUB_WFI_HTB_HCLK));
756 }
757
767 __STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
768 {
769 GLOBAL_EXCEPTION_DISABLE();
770 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
771 GLOBAL_EXCEPTION_ENABLE();
772 }
773
783 __STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
784 {
785 GLOBAL_EXCEPTION_DISABLE();
786 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
787 GLOBAL_EXCEPTION_ENABLE();
788 }
789
799 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
800 {
801 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK) == (MCU_SUB_WFI_PWM_HCLK));
802 }
803
813 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
814 {
815 GLOBAL_EXCEPTION_DISABLE();
816 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
817 GLOBAL_EXCEPTION_ENABLE();
818 }
819
829 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
830 {
831 GLOBAL_EXCEPTION_DISABLE();
832 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
833 GLOBAL_EXCEPTION_ENABLE();
834 }
835
845 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
846 {
847 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK) == (MCU_SUB_WFI_ROM_HCLK));
848 }
849
859 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
860 {
861 GLOBAL_EXCEPTION_DISABLE();
862 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
863 GLOBAL_EXCEPTION_ENABLE();
864 }
865
875 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
876 {
877 GLOBAL_EXCEPTION_DISABLE();
878 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
879 GLOBAL_EXCEPTION_ENABLE();
880 }
881
891 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
892 {
893 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK) == (MCU_SUB_WFI_SNSADC_HCLK));
894 }
895
905 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
906 {
907 GLOBAL_EXCEPTION_DISABLE();
908 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
909 GLOBAL_EXCEPTION_ENABLE();
910 }
911
921 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
922 {
923 GLOBAL_EXCEPTION_DISABLE();
924 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
925 GLOBAL_EXCEPTION_ENABLE();
926 }
927
937 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
938 {
939 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK) == (MCU_SUB_WFI_GPIO_HCLK));
940 }
941
951 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
952 {
953 GLOBAL_EXCEPTION_DISABLE();
954 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
955 GLOBAL_EXCEPTION_ENABLE();
956 }
957
967 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
968 {
969 GLOBAL_EXCEPTION_DISABLE();
970 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
971 GLOBAL_EXCEPTION_ENABLE();
972 }
973
983 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
984 {
985 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK) == (MCU_SUB_WFI_DMA_HCLK));
986 }
987
997 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
998 {
999 GLOBAL_EXCEPTION_DISABLE();
1000 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1001 GLOBAL_EXCEPTION_ENABLE();
1002 }
1003
1013 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1014 {
1015 GLOBAL_EXCEPTION_DISABLE();
1016 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1017 GLOBAL_EXCEPTION_ENABLE();
1018 }
1019
1029 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1030 {
1031 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK) == (MCU_SUB_WFI_BLE_BRG_HCLK));
1032 }
1033
1043 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1044 {
1045 GLOBAL_EXCEPTION_DISABLE();
1046 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1047 GLOBAL_EXCEPTION_ENABLE();
1048 }
1049
1059 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1060 {
1061 GLOBAL_EXCEPTION_DISABLE();
1062 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1063 GLOBAL_EXCEPTION_ENABLE();
1064 }
1065
1075 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1076 {
1077 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK) == (MCU_SUB_WFI_APB_SUB_HCLK));
1078 }
1079
1089 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1090 {
1091 GLOBAL_EXCEPTION_DISABLE();
1092 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1093 GLOBAL_EXCEPTION_ENABLE();
1094 }
1095
1105 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1106 {
1107 GLOBAL_EXCEPTION_DISABLE();
1108 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1109 GLOBAL_EXCEPTION_ENABLE();
1110 }
1111
1122 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1123 {
1124 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK) == (MCU_SUB_WFI_SERIAL_HCLK));
1125 }
1126
1136 __STATIC_INLINE void ll_cgc_enable_wfi_off_i2s_s_hclk(void)
1137 {
1138 GLOBAL_EXCEPTION_DISABLE();
1139 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1140 GLOBAL_EXCEPTION_ENABLE();
1141 }
1142
1152 __STATIC_INLINE void ll_cgc_disable_wfi_off_i2s_s_hclk(void)
1153 {
1154 GLOBAL_EXCEPTION_DISABLE();
1155 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1156 GLOBAL_EXCEPTION_ENABLE();
1157 }
1158
1168 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_i2s_s_hclk(void)
1169 {
1170 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK) == (MCU_SUB_WFI_I2S_S_HCLK));
1171 }
1172
1182 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1183 {
1184 GLOBAL_EXCEPTION_DISABLE();
1185 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1186 GLOBAL_EXCEPTION_ENABLE();
1187 }
1188
1198 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1199 {
1200 GLOBAL_EXCEPTION_DISABLE();
1201 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1202 GLOBAL_EXCEPTION_ENABLE();
1203 }
1204
1214 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1215 {
1216 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK) == (MCU_SUB_WFI_AON_MCUSUB_HCLK));
1217 }
1218
1228 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1229 {
1230 GLOBAL_EXCEPTION_DISABLE();
1231 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1232 GLOBAL_EXCEPTION_ENABLE();
1233 }
1234
1244 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1245 {
1246 GLOBAL_EXCEPTION_DISABLE();
1247 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1248 GLOBAL_EXCEPTION_ENABLE();
1249 }
1250
1260 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1261 {
1262 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK) == (MCU_SUB_WFI_XF_XQSPI_HCLK));
1263 }
1264
1274 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1275 {
1276 GLOBAL_EXCEPTION_DISABLE();
1277 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1278 GLOBAL_EXCEPTION_ENABLE();
1279 }
1280
1290 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1291 {
1292 GLOBAL_EXCEPTION_DISABLE();
1293 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1294 GLOBAL_EXCEPTION_ENABLE();
1295 }
1296
1306 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1307 {
1308 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK) == (MCU_SUB_WFI_SRAM_HCLK));
1309 }
1310
1320 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1321 {
1322 GLOBAL_EXCEPTION_DISABLE();
1323 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1324 GLOBAL_EXCEPTION_ENABLE();
1325 }
1326
1336 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1337 {
1338 GLOBAL_EXCEPTION_DISABLE();
1339
1340 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1341
1342 GLOBAL_EXCEPTION_ENABLE();
1343 }
1344
1355 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1356 {
1357 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK) == (MCU_SUB_WFI_SECU_DIV4_PCLK));
1358 }
1359
1369 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1370 {
1371 GLOBAL_EXCEPTION_DISABLE();
1372
1373 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1374
1375 GLOBAL_EXCEPTION_ENABLE();
1376 }
1377
1387 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1388 {
1389 GLOBAL_EXCEPTION_DISABLE();
1390
1391 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1392
1393 GLOBAL_EXCEPTION_ENABLE();
1394 }
1395
1405 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1406 {
1407 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK) == (MCU_SUB_WFI_XQSPI_DIV4_PCLK));
1408 }
1409
1419 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1420 {
1421 GLOBAL_EXCEPTION_DISABLE();
1422
1423 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1424
1425 GLOBAL_EXCEPTION_ENABLE();
1426 }
1427
1437 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1438 {
1439 GLOBAL_EXCEPTION_DISABLE();
1440
1441 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1442
1443 GLOBAL_EXCEPTION_ENABLE();
1444 }
1445
1455 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1456 {
1457 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK) == (MCU_SUB_FORCE_SECU_HCLK));
1458 }
1459
1469 __STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
1470 {
1471 GLOBAL_EXCEPTION_DISABLE();
1472
1473 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1474
1475 GLOBAL_EXCEPTION_ENABLE();
1476 }
1477
1487 __STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
1488 {
1489 GLOBAL_EXCEPTION_DISABLE();
1490
1491 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1492
1493 GLOBAL_EXCEPTION_ENABLE();
1494 }
1495
1505 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
1506 {
1507 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK) == (MCU_SUB_FORCE_SIM_HCLK));
1508 }
1509
1519 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1520 {
1521 GLOBAL_EXCEPTION_DISABLE();
1522
1523 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1524
1525 GLOBAL_EXCEPTION_ENABLE();
1526 }
1527
1537 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1538 {
1539 GLOBAL_EXCEPTION_DISABLE();
1540
1541 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1542
1543 GLOBAL_EXCEPTION_ENABLE();
1544 }
1545
1555 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1556 {
1557 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK) == (MCU_SUB_FORCE_HTB_HCLK));
1558 }
1559
1569 __STATIC_INLINE void ll_cgc_enable_force_off_pwm_hclk(void)
1570 {
1571 GLOBAL_EXCEPTION_DISABLE();
1572
1573 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1574
1575 GLOBAL_EXCEPTION_ENABLE();
1576 }
1577
1587 __STATIC_INLINE void ll_cgc_disable_force_off_pwm_hclk(void)
1588 {
1589 GLOBAL_EXCEPTION_DISABLE();
1590
1591 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1592
1593 GLOBAL_EXCEPTION_ENABLE();
1594 }
1595
1605 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm_hclk(void)
1606 {
1607 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK) == (MCU_SUB_FORCE_PWM_HCLK));
1608 }
1609
1619 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1620 {
1621 GLOBAL_EXCEPTION_DISABLE();
1622
1623 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1624
1625 GLOBAL_EXCEPTION_ENABLE();
1626 }
1627
1637 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1638 {
1639 GLOBAL_EXCEPTION_DISABLE();
1640
1641 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1642
1643 GLOBAL_EXCEPTION_ENABLE();
1644 }
1645
1655 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1656 {
1657 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK) == (MCU_SUB_FORCE_ROM_HCLK));
1658 }
1659
1669 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1670 {
1671 GLOBAL_EXCEPTION_DISABLE();
1672
1673 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1674
1675 GLOBAL_EXCEPTION_ENABLE();
1676 }
1677
1687 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1688 {
1689 GLOBAL_EXCEPTION_DISABLE();
1690
1691 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1692
1693 GLOBAL_EXCEPTION_ENABLE();
1694 }
1695
1705 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1706 {
1707 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK) == (MCU_SUB_FORCE_SNSADC_HCLK));
1708 }
1709
1719 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1720 {
1721 GLOBAL_EXCEPTION_DISABLE();
1722
1723 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1724
1725 GLOBAL_EXCEPTION_ENABLE();
1726 }
1727
1737 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1738 {
1739 GLOBAL_EXCEPTION_DISABLE();
1740
1741 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1742
1743 GLOBAL_EXCEPTION_ENABLE();
1744 }
1745
1755 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1756 {
1757 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK) == (MCU_SUB_FORCE_GPIO_HCLK));
1758 }
1759
1769 __STATIC_INLINE void ll_cgc_enable_force_off_dma_hclk(void)
1770 {
1771 GLOBAL_EXCEPTION_DISABLE();
1772
1773 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1774
1775 GLOBAL_EXCEPTION_ENABLE();
1776 }
1777
1787 __STATIC_INLINE void ll_cgc_disable_force_off_dma_hclk(void)
1788 {
1789 GLOBAL_EXCEPTION_DISABLE();
1790
1791 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1792
1793 GLOBAL_EXCEPTION_ENABLE();
1794 }
1795
1805 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma_hclk(void)
1806 {
1807 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK) == (MCU_SUB_FORCE_DMA_HCLK));
1808 }
1809
1819 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1820 {
1821 GLOBAL_EXCEPTION_DISABLE();
1822
1823 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1824
1825 GLOBAL_EXCEPTION_ENABLE();
1826 }
1827
1837 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1838 {
1839 GLOBAL_EXCEPTION_DISABLE();
1840
1841 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1842
1843 GLOBAL_EXCEPTION_ENABLE();
1844 }
1845
1855 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1856 {
1857 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK) == (MCU_SUB_FORCE_BLE_BRG_HCLK));
1858 }
1859
1869 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1870 {
1871 GLOBAL_EXCEPTION_DISABLE();
1872
1873 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1874
1875 GLOBAL_EXCEPTION_ENABLE();
1876 }
1877
1887 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1888 {
1889 GLOBAL_EXCEPTION_DISABLE();
1890
1891 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1892
1893 GLOBAL_EXCEPTION_ENABLE();
1894 }
1895
1905 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1906 {
1907 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK) == (MCU_SUB_FORCE_APB_SUB_HCLK));
1908 }
1909
1919 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1920 {
1921 GLOBAL_EXCEPTION_DISABLE();
1922
1923 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1924
1925 GLOBAL_EXCEPTION_ENABLE();
1926 }
1927
1937 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1938 {
1939 GLOBAL_EXCEPTION_DISABLE();
1940
1941 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1942
1943 GLOBAL_EXCEPTION_ENABLE();
1944 }
1945
1955 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1956 {
1957 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK) == (MCU_SUB_FORCE_SERIAL_HCLK));
1958 }
1959
1969 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_hclk(void)
1970 {
1971 GLOBAL_EXCEPTION_DISABLE();
1972
1973 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1974
1975 GLOBAL_EXCEPTION_ENABLE();
1976 }
1977
1987 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_hclk(void)
1988 {
1989 GLOBAL_EXCEPTION_DISABLE();
1990
1991 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1992
1993 GLOBAL_EXCEPTION_ENABLE();
1994 }
1995
2005 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_hclk(void)
2006 {
2007 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK) == (MCU_SUB_FORCE_I2S_S_HCLK));
2008 }
2009
2019 __STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
2020 {
2021 GLOBAL_EXCEPTION_DISABLE();
2022
2023 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2024
2025 GLOBAL_EXCEPTION_ENABLE();
2026 }
2027
2037 __STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
2038 {
2039 GLOBAL_EXCEPTION_DISABLE();
2040
2041 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2042
2043 GLOBAL_EXCEPTION_ENABLE();
2044 }
2045
2055 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
2056 {
2057 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK) == (MCU_SUB_FORCE_AON_MCUSUB_HCLK));
2058 }
2059
2069 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
2070 {
2071 GLOBAL_EXCEPTION_DISABLE();
2072
2073 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2074
2075 GLOBAL_EXCEPTION_ENABLE();
2076 }
2077
2087 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
2088 {
2089 GLOBAL_EXCEPTION_DISABLE();
2090
2091 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2092
2093 GLOBAL_EXCEPTION_ENABLE();
2094 }
2095
2105 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
2106 {
2107 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK) == (MCU_SUB_FORCE_XF_XQSPI_HCLK));
2108 }
2109
2119 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
2120 {
2121 GLOBAL_EXCEPTION_DISABLE();
2122
2123 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2124
2125 GLOBAL_EXCEPTION_ENABLE();
2126 }
2127
2137 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
2138 {
2139 GLOBAL_EXCEPTION_DISABLE();
2140
2141 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2142
2143 GLOBAL_EXCEPTION_ENABLE();
2144 }
2145
2155 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
2156 {
2157 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK) == (MCU_SUB_FORCE_SRAM_HCLK));
2158 }
2159
2169 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
2170 {
2171 GLOBAL_EXCEPTION_DISABLE();
2172
2173 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2174
2175 GLOBAL_EXCEPTION_ENABLE();
2176 }
2177
2187 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
2188 {
2189 GLOBAL_EXCEPTION_DISABLE();
2190
2191 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2192
2193 GLOBAL_EXCEPTION_ENABLE();
2194 }
2195
2205 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
2206 {
2207 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK) == (MCU_SUB_FORCE_UART0_HCLK));
2208 }
2209
2219 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
2220 {
2221 GLOBAL_EXCEPTION_DISABLE();
2222
2223 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2224
2225 GLOBAL_EXCEPTION_ENABLE();
2226 }
2227
2237 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
2238 {
2239 GLOBAL_EXCEPTION_DISABLE();
2240
2241 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2242
2243 GLOBAL_EXCEPTION_ENABLE();
2244 }
2245
2255 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
2256 {
2257 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK) == (MCU_SUB_FORCE_UART1_HCLK));
2258 }
2259
2269 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2270 {
2271 GLOBAL_EXCEPTION_DISABLE();
2272
2273 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2274
2275 GLOBAL_EXCEPTION_ENABLE();
2276 }
2277
2287 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2288 {
2289 GLOBAL_EXCEPTION_DISABLE();
2290
2291 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2292
2293 GLOBAL_EXCEPTION_ENABLE();
2294 }
2295
2305 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2306 {
2307 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK) == (MCU_SUB_FORCE_I2C0_HCLK));
2308 }
2309
2319 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2320 {
2321 GLOBAL_EXCEPTION_DISABLE();
2322
2323 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2324
2325 GLOBAL_EXCEPTION_ENABLE();
2326 }
2327
2337 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2338 {
2339 GLOBAL_EXCEPTION_DISABLE();
2340
2341 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2342
2343 GLOBAL_EXCEPTION_ENABLE();
2344 }
2345
2355 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2356 {
2357 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK) == (MCU_SUB_FORCE_I2C1_HCLK));
2358 }
2359
2369 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2370 {
2371 GLOBAL_EXCEPTION_DISABLE();
2372
2373 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2374
2375 GLOBAL_EXCEPTION_ENABLE();
2376 }
2377
2387 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2388 {
2389 GLOBAL_EXCEPTION_DISABLE();
2390
2391 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2392
2393 GLOBAL_EXCEPTION_ENABLE();
2394 }
2395
2405 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2406 {
2407 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK) == (MCU_SUB_FORCE_SPIM_HCLK));
2408 }
2409
2419 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2420 {
2421 GLOBAL_EXCEPTION_DISABLE();
2422
2423 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2424
2425 GLOBAL_EXCEPTION_ENABLE();
2426 }
2427
2437 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2438 {
2439 GLOBAL_EXCEPTION_DISABLE();
2440
2441 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2442
2443 GLOBAL_EXCEPTION_ENABLE();
2444 }
2445
2455 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2456 {
2457 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK) == (MCU_SUB_FORCE_SPIS_HCLK));
2458 }
2459
2469 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2470 {
2471 GLOBAL_EXCEPTION_DISABLE();
2472
2473 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2474
2475 GLOBAL_EXCEPTION_ENABLE();
2476 }
2477
2487 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2488 {
2489 GLOBAL_EXCEPTION_DISABLE();
2490
2491 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2492
2493 GLOBAL_EXCEPTION_ENABLE();
2494 }
2495
2505 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2506 {
2507 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK) == (MCU_SUB_FORCE_QSPI0_HCLK));
2508 }
2509
2519 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2520 {
2521 GLOBAL_EXCEPTION_DISABLE();
2522
2523 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2524
2525 GLOBAL_EXCEPTION_ENABLE();
2526 }
2527
2537 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2538 {
2539 GLOBAL_EXCEPTION_DISABLE();
2540
2541 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2542
2543 GLOBAL_EXCEPTION_ENABLE();
2544 }
2545
2555 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2556 {
2557 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK) == (MCU_SUB_FORCE_QSPI1_HCLK));
2558 }
2559
2569 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2570 {
2571 GLOBAL_EXCEPTION_DISABLE();
2572
2573 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2574
2575 GLOBAL_EXCEPTION_ENABLE();
2576 }
2577
2587 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2588 {
2589 GLOBAL_EXCEPTION_DISABLE();
2590
2591 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2592
2593 GLOBAL_EXCEPTION_ENABLE();
2594 }
2595
2605 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2606 {
2607 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK) == (MCU_SUB_FORCE_I2S_HCLK));
2608 }
2609
2619 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
2620 {
2621 GLOBAL_EXCEPTION_DISABLE();
2622
2623 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2624
2625 GLOBAL_EXCEPTION_ENABLE();
2626 }
2627
2637 __STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
2638 {
2639 GLOBAL_EXCEPTION_DISABLE();
2640
2641 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2642
2643 GLOBAL_EXCEPTION_ENABLE();
2644 }
2645
2655 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
2656 {
2657 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK) == (MCU_SUB_FORCE_SECU_DIV4_PCLK));
2658 }
2659
2660
2673 error_status_t ll_cgc_deinit(void);
2674
2684 error_status_t ll_cgc_init(ll_cgc_init_t *p_cgc_init);
2685
2692 void ll_cgc_struct_init(ll_cgc_init_t *p_cgc_init);
2693
2699 #endif /* CGC */
2700
2701 #ifdef __cplusplus
2702 }
2703 #endif
2704
2705 #endif /* __GR55XX_LL_CGC_H__ */
2706
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr55xx_ll_cgc.h:460
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:983
ll_cgc_disable_force_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma_hclk(void)
Disabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1787
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1887
ll_cgc_enable_wfi_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_i2s_s_hclk(void)
Enable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1136
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:875
_ll_cgc_init_t::wfi_clk2
uint32_t wfi_clk2
Definition: gr55xx_ll_cgc.h:84
ll_cgc_enable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:767
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:721
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1737
_ll_cgc_init_t::wfi_clk1
uint32_t wfi_clk1
Definition: gr55xx_ll_cgc.h:81
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/DMA/B...
Definition: gr55xx_ll_cgc.h:498
ll_cgc_disable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:783
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1198
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2269
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1437
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:937
ll_cgc_enable_force_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm_hclk(void)
Enabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1569
ll_cgc_init_t
struct _ll_cgc_init_t ll_cgc_init_t
LL CGC init Structure definition.
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:2055
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1182
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2587
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1306
_ll_cgc_init_t::force_clk0
uint32_t force_clk0
Definition: gr55xx_ll_cgc.h:87
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1013
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1919
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1214
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:891
ll_cgc_is_enabled_wfi_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:799
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:2155
ll_cgc_deinit
error_status_t ll_cgc_deinit(void)
De-initialize CGC registers (Registers restored to their default values).
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:540
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2087
ll_cgc_disable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:691
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2137
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:2255
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1555
ll_cgc_is_enabled_force_off_i2s_s_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2005
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2319
ll_cgc_enable_force_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma_hclk(void)
Enabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1769
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2387
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2419
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1819
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2305
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1637
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1669
ll_cgc_is_enabled_force_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm_hclk(void)
Indicate whether the clock for PWM is forced to close.
Definition: gr55xx_ll_cgc.h:1605
ll_cgc_disable_force_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm_hclk(void)
Disabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1587
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:967
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1105
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1405
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2505
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2355
ll_cgc_is_enabled_wfi_off_i2s_s_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_i2s_s_hclk(void)
Indicate whether the I2S slave automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1168
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2555
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2105
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1228
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:661
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr55xx_ll_cgc.h:342
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2069
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1755
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO...
Definition: gr55xx_ll_cgc.h:304
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:845
ll_cgc_disable_wfi_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_i2s_s_hclk(void)
Disable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1152
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:629
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:859
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2369
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1687
ll_cgc_enable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
Enabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1469
ll_cgc_disable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
Disabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1487
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/...
Definition: gr55xx_ll_cgc.h:615
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2637
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2337
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1869
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:921
_ll_cgc_init_t::wfi_clk0
uint32_t wfi_clk0
Definition: gr55xx_ll_cgc.h:78
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1122
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2287
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:905
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2437
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr55xx_ll_cgc.h:402
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:363
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:519
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2487
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1387
_ll_cgc_init_t::force_clk1
uint32_t force_clk1
Definition: gr55xx_ll_cgc.h:90
ll_cgc_disable_force_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1987
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1905
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1059
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1837
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1089
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1290
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:421
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2019
ll_cgc_init
error_status_t ll_cgc_init(ll_cgc_init_t *p_cgc_init)
Initialize CGC registers according to the specified. parameters in p_cgc_init.
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1955
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2037
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2519
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:737
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2469
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1029
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:2205
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1043
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:384
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2169
_ll_cgc_init_t::force_clk2
uint32_t force_clk2
Definition: gr55xx_ll_cgc.h:93
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2219
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1619
ll_cgc_is_enabled_wfi_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:707
ll_cgc_is_enabled_force_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
Indicate whether the clock for SIM is forced to close.
Definition: gr55xx_ll_cgc.h:1505
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1719
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:951
_ll_cgc_init_t
LL CGC init Structure definition.
Definition: gr55xx_ll_cgc.h:77
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1537
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:997
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1855
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2119
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1075
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1244
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/SPIM_HCLK...
Definition: gr55xx_ll_cgc.h:577
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1260
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1369
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2619
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1355
ll_cgc_enable_force_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1969
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2237
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:753
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1419
ll_cgc_struct_init
void ll_cgc_struct_init(ll_cgc_init_t *p_cgc_init)
Set each field of a ll_cgc_init_t type structure to default value.
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1336
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1320
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2405
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1655
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2605
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:645
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:813
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2537
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2569
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1519
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2455
ll_cgc_enable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:675
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2187
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1937
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1455
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:829
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1705
ll_cgc_is_enabled_force_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma_hclk(void)
Indicate whether the clock for DMA is forced to close.
Definition: gr55xx_ll_cgc.h:1805
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:2655
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1274