gr55xx_ll_spi.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (SPIM) || defined (SPIS) || defined (QSPI0) || defined (QSPI1)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction;
83 uint32_t data_size;
88 uint32_t clock_polarity;
93 uint32_t clock_phase;
98 uint32_t slave_select;
103 uint32_t baud_rate;
108 } ll_spim_init_t;
109
113 typedef struct _ll_spis_init_t
114 {
115 uint32_t data_size;
120 uint32_t clock_polarity;
125 uint32_t clock_phase;
130 } ll_spis_init_t;
131
135 typedef struct _ll_qspi_init_t
136 {
137 uint32_t transfer_direction;
142 uint32_t instruction_size;
147 uint32_t address_size;
152 uint32_t inst_addr_transfer_format;
157 uint32_t wait_cycles;
162 uint32_t data_size;
167 uint32_t clock_polarity;
172 uint32_t clock_phase;
177 uint32_t baud_rate;
183 uint32_t rx_sample_delay;
185 } ll_qspi_init_t;
186
196 /* Exported constants --------------------------------------------------------*/
205 #define LL_SSI_SR_DCOL SSI_STAT_DCOL
206 #define LL_SSI_SR_TXE SSI_STAT_TXE
207 #define LL_SSI_SR_RFF SSI_STAT_RFF
208 #define LL_SSI_SR_RFNE SSI_STAT_RFNE
209 #define LL_SSI_SR_TFE SSI_STAT_TFE
210 #define LL_SSI_SR_TFNF SSI_STAT_TFNF
211 #define LL_SSI_SR_BUSY SSI_STAT_BUSY
218 #define LL_SSI_IM_MST SSI_INTMASK_MSTIM
219 #define LL_SSI_IM_RXF SSI_INTMASK_RXFIM
220 #define LL_SSI_IM_RXO SSI_INTMASK_RXOIM
221 #define LL_SSI_IM_RXU SSI_INTMASK_RXUIM
222 #define LL_SSI_IM_TXO SSI_INTMASK_TXOIM
223 #define LL_SSI_IM_TXE SSI_INTMASK_TXEIM
225 #define LL_SSI_IS_MST SSI_INTSTAT_MSTIS
226 #define LL_SSI_IS_RXF SSI_INTSTAT_RXFIS
227 #define LL_SSI_IS_RXO SSI_INTSTAT_RXOIS
228 #define LL_SSI_IS_RXU SSI_INTSTAT_RXUIS
229 #define LL_SSI_IS_TXO SSI_INTSTAT_TXOIS
230 #define LL_SSI_IS_TXE SSI_INTSTAT_TXEIS
232 #define LL_SSI_RIS_MST SSI_RAW_INTSTAT_MSTIR
233 #define LL_SSI_RIS_RXF SSI_RAW_INTSTAT_RXFIR
234 #define LL_SSI_RIS_RXO SSI_RAW_INTSTAT_RXOIR
235 #define LL_SSI_RIS_RXU SSI_RAW_INTSTAT_RXUIR
236 #define LL_SSI_RIS_TXO SSI_RAW_INTSTAT_TXOIR
237 #define LL_SSI_RIS_TXE SSI_RAW_INTSTAT_TXEIR
243 #define LL_SSI_FRF_SPI 0x00000000UL
244 #define LL_SSI_FRF_DUALSPI (1UL << SSI_CTRL0_SPIFRF_Pos)
245 #define LL_SSI_FRF_QUADSPI (2UL << SSI_CTRL0_SPIFRF_Pos)
251 #define LL_SSI_DATASIZE_4BIT (3UL << SSI_CTRL0_DFS32_Pos)
252 #define LL_SSI_DATASIZE_5BIT (4UL << SSI_CTRL0_DFS32_Pos)
253 #define LL_SSI_DATASIZE_6BIT (5UL << SSI_CTRL0_DFS32_Pos)
254 #define LL_SSI_DATASIZE_7BIT (6UL << SSI_CTRL0_DFS32_Pos)
255 #define LL_SSI_DATASIZE_8BIT (7UL << SSI_CTRL0_DFS32_Pos)
256 #define LL_SSI_DATASIZE_9BIT (8UL << SSI_CTRL0_DFS32_Pos)
257 #define LL_SSI_DATASIZE_10BIT (9UL << SSI_CTRL0_DFS32_Pos)
258 #define LL_SSI_DATASIZE_11BIT (10UL << SSI_CTRL0_DFS32_Pos)
259 #define LL_SSI_DATASIZE_12BIT (11UL << SSI_CTRL0_DFS32_Pos)
260 #define LL_SSI_DATASIZE_13BIT (12UL << SSI_CTRL0_DFS32_Pos)
261 #define LL_SSI_DATASIZE_14BIT (13UL << SSI_CTRL0_DFS32_Pos)
262 #define LL_SSI_DATASIZE_15BIT (14UL << SSI_CTRL0_DFS32_Pos)
263 #define LL_SSI_DATASIZE_16BIT (15UL << SSI_CTRL0_DFS32_Pos)
264 #define LL_SSI_DATASIZE_17BIT (16UL << SSI_CTRL0_DFS32_Pos)
265 #define LL_SSI_DATASIZE_18BIT (17UL << SSI_CTRL0_DFS32_Pos)
266 #define LL_SSI_DATASIZE_19BIT (18UL << SSI_CTRL0_DFS32_Pos)
267 #define LL_SSI_DATASIZE_20BIT (19UL << SSI_CTRL0_DFS32_Pos)
268 #define LL_SSI_DATASIZE_21BIT (20UL << SSI_CTRL0_DFS32_Pos)
269 #define LL_SSI_DATASIZE_22BIT (21UL << SSI_CTRL0_DFS32_Pos)
270 #define LL_SSI_DATASIZE_23BIT (22UL << SSI_CTRL0_DFS32_Pos)
271 #define LL_SSI_DATASIZE_24BIT (23UL << SSI_CTRL0_DFS32_Pos)
272 #define LL_SSI_DATASIZE_25BIT (24UL << SSI_CTRL0_DFS32_Pos)
273 #define LL_SSI_DATASIZE_26BIT (25UL << SSI_CTRL0_DFS32_Pos)
274 #define LL_SSI_DATASIZE_27BIT (26UL << SSI_CTRL0_DFS32_Pos)
275 #define LL_SSI_DATASIZE_28BIT (27UL << SSI_CTRL0_DFS32_Pos)
276 #define LL_SSI_DATASIZE_29BIT (28UL << SSI_CTRL0_DFS32_Pos)
277 #define LL_SSI_DATASIZE_30BIT (29UL << SSI_CTRL0_DFS32_Pos)
278 #define LL_SSI_DATASIZE_31BIT (30UL << SSI_CTRL0_DFS32_Pos)
279 #define LL_SSI_DATASIZE_32BIT (31UL << SSI_CTRL0_DFS32_Pos)
285 #define LL_SSI_MW_CMDSIZE_1BIT 0x00000000UL
286 #define LL_SSI_MW_CMDSIZE_2BIT (1UL << SSI_CTRL0_CFS_Pos)
287 #define LL_SSI_MW_CMDSIZE_3BIT (2UL << SSI_CTRL0_CFS_Pos)
288 #define LL_SSI_MW_CMDSIZE_4BIT (3UL << SSI_CTRL0_CFS_Pos)
289 #define LL_SSI_MW_CMDSIZE_5BIT (4UL << SSI_CTRL0_CFS_Pos)
290 #define LL_SSI_MW_CMDSIZE_6BIT (5UL << SSI_CTRL0_CFS_Pos)
291 #define LL_SSI_MW_CMDSIZE_7BIT (6UL << SSI_CTRL0_CFS_Pos)
292 #define LL_SSI_MW_CMDSIZE_8BIT (7UL << SSI_CTRL0_CFS_Pos)
293 #define LL_SSI_MW_CMDSIZE_9BIT (8UL << SSI_CTRL0_CFS_Pos)
294 #define LL_SSI_MW_CMDSIZE_10BIT (9UL << SSI_CTRL0_CFS_Pos)
295 #define LL_SSI_MW_CMDSIZE_11BIT (10UL << SSI_CTRL0_CFS_Pos)
296 #define LL_SSI_MW_CMDSIZE_12BIT (11UL << SSI_CTRL0_CFS_Pos)
297 #define LL_SSI_MW_CMDSIZE_13BIT (12UL << SSI_CTRL0_CFS_Pos)
298 #define LL_SSI_MW_CMDSIZE_14BIT (13UL << SSI_CTRL0_CFS_Pos)
299 #define LL_SSI_MW_CMDSIZE_15BIT (14UL << SSI_CTRL0_CFS_Pos)
300 #define LL_SSI_MW_CMDSIZE_16BIT (15UL << SSI_CTRL0_CFS_Pos)
306 #define LL_SSI_NORMAL_MODE 0x00000000UL
307 #define LL_SSI_TEST_MODE (1UL << SSI_CTRL0_SRL_Pos)
313 #define LL_SSI_SLAVE_OUTDIS 0x00000000UL
314 #define LL_SSI_SLAVE_OUTEN (1UL << SSI_CTRL0_SLVOE_Pos)
320 #define LL_SSI_FULL_DUPLEX 0x00000000UL
321 #define LL_SSI_SIMPLEX_TX (1UL << SSI_CTRL0_TMOD_Pos)
322 #define LL_SSI_SIMPLEX_RX (2UL << SSI_CTRL0_TMOD_Pos)
323 #define LL_SSI_READ_EEPROM (3UL << SSI_CTRL0_TMOD_Pos)
329 #define LL_SSI_SCPHA_1EDGE 0x00000000UL
330 #define LL_SSI_SCPHA_2EDGE (1UL << SSI_CTRL0_SCPHA_Pos)
336 #define LL_SSI_SCPOL_LOW 0x00000000UL
337 #define LL_SSI_SCPOL_HIGH (1UL << SSI_CTRL0_SCPOL_Pos)
343 #define LL_SSI_PROTOCOL_MOTOROLA 0x00000000UL
344 #define LL_SSI_PROTOCOL_TI (1UL << SSI_CTRL0_FRF_Pos)
345 #define LL_SSI_PROTOCOL_MICROWIRE (2UL << SSI_CTRL0_FRF_Pos)
351 #define LL_SSI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL
352 #define LL_SSI_MICROWIRE_HANDSHAKE_EN (1UL << SSI_MWC_MHS_Pos)
354 #define LL_SSI_MICROWIRE_RX 0x00000000UL
355 #define LL_SSI_MICROWIRE_TX (1UL << SSI_MWC_MDD_Pos)
357 #define LL_SSI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL
358 #define LL_SSI_MICROWIRE_SEQUENTIAL (1UL << SSI_MWC_MWMOD_Pos)
364 #define LL_SSI_SLAVE1 SSI_SE_SLAVE1
365 #define LL_SSI_SLAVE0 SSI_SE_SLAVE0
371 #define LL_SSI_DMA_TX_DIS 0x00000000UL
372 #define LL_SSI_DMA_TX_EN SSI_DMAC_TDMAE
374 #define LL_SSI_DMA_RX_DIS 0x00000000UL
375 #define LL_SSI_DMA_RX_EN SSI_DMAC_RDMAE
381 #define LL_SSI_INSTSIZE_0BIT 0x00000000UL
382 #define LL_SSI_INSTSIZE_4BIT (1UL << SSI_SCTRL0_INSTL_Pos)
383 #define LL_SSI_INSTSIZE_8BIT (2UL << SSI_SCTRL0_INSTL_Pos)
384 #define LL_SSI_INSTSIZE_16BIT (3UL << SSI_SCTRL0_INSTL_Pos)
390 #define LL_SSI_ADDRSIZE_0BIT 0x00000000UL
391 #define LL_SSI_ADDRSIZE_4BIT (1UL << SSI_SCTRL0_ADDRL_Pos)
392 #define LL_SSI_ADDRSIZE_8BIT (2UL << SSI_SCTRL0_ADDRL_Pos)
393 #define LL_SSI_ADDRSIZE_12BIT (3UL << SSI_SCTRL0_ADDRL_Pos)
394 #define LL_SSI_ADDRSIZE_16BIT (4UL << SSI_SCTRL0_ADDRL_Pos)
395 #define LL_SSI_ADDRSIZE_20BIT (5UL << SSI_SCTRL0_ADDRL_Pos)
396 #define LL_SSI_ADDRSIZE_24BIT (6UL << SSI_SCTRL0_ADDRL_Pos)
397 #define LL_SSI_ADDRSIZE_28BIT (7UL << SSI_SCTRL0_ADDRL_Pos)
398 #define LL_SSI_ADDRSIZE_32BIT (8UL << SSI_SCTRL0_ADDRL_Pos)
399 #define LL_SSI_ADDRSIZE_36BIT (9UL << SSI_SCTRL0_ADDRL_Pos)
400 #define LL_SSI_ADDRSIZE_40BIT (10UL << SSI_SCTRL0_ADDRL_Pos)
401 #define LL_SSI_ADDRSIZE_44BIT (11UL << SSI_SCTRL0_ADDRL_Pos)
402 #define LL_SSI_ADDRSIZE_48BIT (12UL << SSI_SCTRL0_ADDRL_Pos)
403 #define LL_SSI_ADDRSIZE_52BIT (13UL << SSI_SCTRL0_ADDRL_Pos)
404 #define LL_SSI_ADDRSIZE_56BIT (14UL << SSI_SCTRL0_ADDRL_Pos)
405 #define LL_SSI_ADDRSIZE_60BIT (15UL << SSI_SCTRL0_ADDRL_Pos)
411 #define LL_SSI_INST_ADDR_ALL_IN_SPI 0x00000000UL
412 #define LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << SSI_SCTRL0_TRANSTYPE_Pos)
413 #define LL_SSI_INST_ADDR_ALL_IN_SPIFRF (2UL << SSI_SCTRL0_TRANSTYPE_Pos)
423 #define LL_SPIM_DEFAULT_CONFIG \
424 { \
425 .transfer_direction = LL_SSI_FULL_DUPLEX, \
426 .data_size = LL_SSI_DATASIZE_8BIT, \
427 .clock_polarity = LL_SSI_SCPOL_LOW, \
428 .clock_phase = LL_SSI_SCPHA_1EDGE, \
429 .slave_select = LL_SSI_SLAVE0, \
430 .baud_rate = SystemCoreClock / 2000000, \
431 }
432
436 #define LL_SPIS_DEFAULT_CONFIG \
437 { \
438 .data_size = LL_SSI_DATASIZE_8BIT, \
439 .clock_polarity = LL_SSI_SCPOL_LOW, \
440 .clock_phase = LL_SSI_SCPHA_1EDGE, \
441 }
442
446 #define LL_QSPI_DEFAULT_CONFIG \
447 { \
448 .transfer_direction = LL_SSI_SIMPLEX_TX, \
449 .instruction_size = LL_SSI_INSTSIZE_8BIT, \
450 .address_size = LL_SSI_ADDRSIZE_24BIT, \
451 .inst_addr_transfer_format = LL_SSI_INST_ADDR_ALL_IN_SPI,\
452 .wait_cycles = 0, \
453 .data_size = LL_SSI_DATASIZE_8BIT, \
454 .clock_polarity = LL_SSI_SCPOL_LOW, \
455 .clock_phase = LL_SSI_SCPHA_1EDGE, \
456 .baud_rate = SystemCoreClock / 1000000, \
457 .rx_sample_delay = 0, \
458 }
459
463 /* Exported macro ------------------------------------------------------------*/
479 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
480
487 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
488
495 /* Exported functions --------------------------------------------------------*/
515 __STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
516 {
517 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
518 }
519
531 __STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
532 {
533 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
534 }
535
547 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
548 {
549 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN) == (SSI_CTRL0_SSTEN));
550 }
551
567 __STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
568 {
569 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SPIFRF, frf);
570 }
571
586 __STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
587 {
588 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SPIFRF));
589 }
590
631 __STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
632 {
633 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_DFS32, size);
634 }
635
675 __STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
676 {
677 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_DFS32));
678 }
679
708 __STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
709 {
710 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_CFS, size);
711 }
712
740 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
741 {
742 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_CFS));
743 }
744
755 __STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
756 {
757 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
758 }
759
770 __STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
771 {
772 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
773 }
774
785 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
786 {
787 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SRL) == (SSI_CTRL0_SRL));
788 }
789
800 __STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
801 {
802 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
803 }
804
815 __STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
816 {
817 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
818 }
819
830 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
831 {
832 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE) != (SSI_CTRL0_SLVOE));
833 }
834
850 __STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
851 {
852 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_TMOD, transfer_direction);
853 }
854
869 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
870 {
871 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_TMOD));
872 }
873
889 __STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
890 {
891 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPOL, clock_polarity);
892 }
893
906 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
907 {
908 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPOL));
909 }
910
926 __STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
927 {
928 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPHA, clock_phase);
929 }
930
943 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
944 {
945 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPHA));
946 }
947
963 __STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
964 {
965 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_FRF, standard);
966 }
967
981 __STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
982 {
983 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_FRF));
984 }
985
1000 __STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
1001 {
1002 MODIFY_REG(SPIx->CTRL1, SSI_CTRL1_NDF, size);
1003 }
1004
1018 __STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
1019 {
1020 return (uint32_t)(READ_BITS(SPIx->CTRL1, SSI_CTRL1_NDF));
1021 }
1022
1033 __STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
1034 {
1035 SET_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1036 }
1037
1049 __STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
1050 {
1051 CLEAR_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1052 }
1053
1064 __STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
1065 {
1066 return (READ_BITS(SPIx->SSI_EN, SSI_SSIEN_EN) == (SSI_SSIEN_EN));
1067 }
1068
1079 __STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
1080 {
1081 SET_BITS(SPIx->MWC, SSI_MWC_MHS);
1082 }
1083
1094 __STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
1095 {
1096 CLEAR_BITS(SPIx->MWC, SSI_MWC_MHS);
1097 }
1098
1109 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
1110 {
1111 return (READ_BITS(SPIx->MWC, SSI_MWC_MHS) == (SSI_MWC_MHS));
1112 }
1113
1128 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
1129 {
1130 MODIFY_REG(SPIx->MWC, SSI_MWC_MDD, transfer_direction);
1131 }
1132
1146 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
1147 {
1148 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MDD));
1149 }
1150
1165 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
1166 {
1167 MODIFY_REG(SPIx->MWC, SSI_MWC_MWMOD, transfer_mode);
1168 }
1169
1183 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
1184 {
1185 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MWMOD));
1186 }
1187
1202 __STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
1203 {
1204 SET_BITS(SPIx->SE, ss);
1205 }
1206
1221 __STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
1222 {
1223 CLEAR_BITS(SPIx->SE, ss);
1224 }
1225
1240 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
1241 {
1242 return (READ_BITS(SPIx->SE, ss) == ss);
1243 }
1244
1257 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
1258 {
1259 WRITE_REG(SPIx->BAUD, baud_rate);
1260 }
1261
1272 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
1273 {
1274 return (uint32_t)(READ_BITS(SPIx->BAUD, SSI_BAUD_SCKDIV));
1275 }
1276
1288 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1289 {
1290 WRITE_REG(SPIx->TX_FTL, threshold);
1291 }
1292
1303 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
1304 {
1305 return (uint32_t)(READ_BITS(SPIx->TX_FTL, SSI_TXFTL_TFT));
1306 }
1307
1319 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1320 {
1321 WRITE_REG(SPIx->RX_FTL, threshold);
1322 }
1323
1334 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
1335 {
1336 return (uint32_t)(READ_BITS(SPIx->RX_FTL, SSI_RXFTL_RFT));
1337 }
1338
1349 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
1350 {
1351 return (uint32_t)(READ_BITS(SPIx->TX_FL, SSI_TXFL_TXTFL));
1352 }
1353
1364 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
1365 {
1366 return (uint32_t)(READ_BITS(SPIx->RX_FL, SSI_RXFL_RXTFL));
1367 }
1368
1379 __STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
1380 {
1381 return (uint32_t)(READ_BITS(SPIx->ID, SSI_IDCODE_ID));
1382 }
1383
1394 __STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
1395 {
1396 return (uint32_t)(READ_BITS(SPIx->VERSION_ID, SSI_COMP_VERSION));
1397 }
1398
1423 __STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
1424 {
1425 SET_BITS(SPIx->INTMASK, mask);
1426 }
1427
1446 __STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
1447 {
1448 CLEAR_BITS(SPIx->INTMASK, mask);
1449 }
1450
1468 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
1469 {
1470 return (READ_BITS(SPIx->INTMASK, mask) == mask);
1471 }
1472
1496 __STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
1497 {
1498 return (uint32_t)(READ_REG(SPIx->STAT));
1499 }
1500
1525 __STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
1526 {
1527 return (READ_BITS(SPIx->STAT, flag) == (flag));
1528 }
1529
1546 __STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
1547 {
1548 return (uint32_t)(READ_REG(SPIx->INTSTAT));
1549 }
1550
1573 __STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
1574 {
1575 return (READ_BITS(SPIx->INTSTAT, flag) == flag);
1576 }
1577
1594 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
1595 {
1596 return (uint32_t)(READ_REG(SPIx->RAW_INTSTAT));
1597 }
1598
1610 __STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
1611 {
1612 __IOM uint32_t tmpreg;
1613 tmpreg = SPIx->TXOIC;
1614 (void) tmpreg;
1615 }
1616
1628 __STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
1629 {
1630 __IOM uint32_t tmpreg;
1631 tmpreg = SPIx->RXOIC;
1632 (void) tmpreg;
1633 }
1634
1646 __STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
1647 {
1648 __IOM uint32_t tmpreg;
1649 tmpreg = SPIx->RXUIC;
1650 (void) tmpreg;
1651 }
1652
1664 __STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
1665 {
1666 __IOM uint32_t tmpreg;
1667 tmpreg = SPIx->MSTIC;
1668 (void) tmpreg;
1669 }
1670
1682 __STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
1683 {
1684 __IOM uint32_t tmpreg;
1685 tmpreg = SPIx->INTCLR;
1686 (void) tmpreg;
1687 }
1688
1705 __STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
1706 {
1707 SET_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1708 }
1709
1720 __STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
1721 {
1722 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1723 }
1724
1735 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
1736 {
1737 return (READ_BITS(SPIx->DMAC, SSI_DMAC_TDMAE) == (SSI_DMAC_TDMAE));
1738 }
1739
1750 __STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
1751 {
1752 SET_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1753 }
1754
1765 __STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
1766 {
1767 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1768 }
1769
1780 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
1781 {
1782 return (READ_BITS(SPIx->DMAC, SSI_DMAC_RDMAE) == (SSI_DMAC_RDMAE));
1783 }
1784
1796 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1797 {
1798 WRITE_REG(SPIx->DMA_TDL, threshold);
1799 }
1800
1811 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
1812 {
1813 return (uint32_t)(READ_BITS(SPIx->DMA_TDL, SSI_DMATDL_DMATDL));
1814 }
1815
1827 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1828 {
1829 WRITE_REG(SPIx->DMA_RDL, threshold);
1830 }
1831
1842 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
1843 {
1844 return (uint32_t)(READ_BITS(SPIx->DMA_RDL, SSI_DMARDL_DMARDL));
1845 }
1846
1864 __STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
1865 {
1866 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1867 }
1868
1880 __STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
1881 {
1882 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1883 }
1884
1896 __STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
1897 {
1898 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1899 }
1900
1911 __STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
1912 {
1913 return (uint8_t)(READ_REG(SPIx->DATA));
1914 }
1915
1926 __STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
1927 {
1928 return (uint16_t)(READ_REG(SPIx->DATA));
1929 }
1930
1941 __STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
1942 {
1943 return (uint32_t)(READ_REG(SPIx->DATA));
1944 }
1945
1958 __STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
1959 {
1960 WRITE_REG(SPIx->RX_SAMPLE_DLY, delay);
1961 }
1962
1974 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
1975 {
1976 return (uint32_t)(READ_REG(SPIx->RX_SAMPLE_DLY));
1977 }
1978
1991 __STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
1992 {
1993 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES, wait_cycles << SSI_SCTRL0_WAITCYCLES_Pos);
1994 }
1995
2007 __STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
2008 {
2009 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES) >> SSI_SCTRL0_WAITCYCLES_Pos);
2010 }
2011
2028 __STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
2029 {
2030 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL, size);
2031 }
2032
2048 __STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
2049 {
2050 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL));
2051 }
2052
2081 __STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
2082 {
2083 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL, size);
2084 }
2085
2113 __STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
2114 {
2115 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL));
2116 }
2117
2133 __STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
2134 {
2135 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE, format);
2136 }
2137
2152 __STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
2153 {
2154 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE));
2155 }
2156
2170 error_status_t ll_spim_deinit(ssi_regs_t *SPIx);
2171
2182 error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
2183
2190 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
2191
2205 error_status_t ll_spis_deinit(ssi_regs_t *SPIx);
2206
2217 error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
2218
2225 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
2239 error_status_t ll_qspi_deinit(ssi_regs_t *SPIx);
2240
2251 error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init);
2252
2259 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
2260
2265 #endif /* SPIM || SPIS || QSPI0 || QSPI1 */
2266
2267 #ifdef __cplusplus
2268 }
2269 #endif
2270
2271 #endif /* __GR55xx_LL_SPI_H__ */
2272
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr55xx_ll_spi.h:531
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1183
ll_spis_deinit
error_status_t ll_spis_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1079
ll_spim_init
error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1094
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_spi.h:1468
_ll_spis_init_t
SPIS init structures definition.
Definition: gr55xx_ll_spi.h:114
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1911
ll_spi_get_wait_cycles
__STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
Get number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:2007
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_spi.h:115
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1827
_ll_qspi_init_t::instruction_size
uint32_t instruction_size
Definition: gr55xx_ll_spi.h:142
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
Clear all error flag.
Definition: gr55xx_ll_spi.h:1682
ll_spi_get_frame_format
__STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
Get data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:586
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr55xx_ll_spi.h:1974
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr55xx_ll_spi.h:77
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_spi.h:1573
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr55xx_ll_spi.h:515
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_spi.h:1958
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_spi.h:1364
_ll_qspi_init_t::address_size
uint32_t address_size
Definition: gr55xx_ll_spi.h:147
ll_qspi_init_t
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_spi.h:889
_ll_qspi_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_spi.h:167
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1000
_ll_qspi_init_t::inst_addr_transfer_format
uint32_t inst_addr_transfer_format
Definition: gr55xx_ll_spi.h:152
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1288
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_spi.h:1780
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_spi.h:1064
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr55xx_ll_spi.h:770
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_spi.h:88
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_spi.h:1272
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_spi.h:120
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_spi.h:830
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_spi.h:1446
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr55xx_ll_spi.h:869
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
Get SPI status.
Definition: gr55xx_ll_spi.h:1496
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1018
_ll_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Definition: gr55xx_ll_spi.h:183
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1628
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1334
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_spi.h:631
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
_ll_qspi_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_spi.h:172
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_spi.h:103
ll_spi_set_address_size
__STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2081
ll_spis_init
error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_spi.h:963
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1303
_ll_qspi_init_t
QSPI init structures definition.
Definition: gr55xx_ll_spi.h:136
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Definition: gr55xx_ll_spi.h:78
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1165
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_spi.h:83
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr55xx_ll_spi.h:1705
ll_spi_set_add_inst_transfer_format
__STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2133
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr55xx_ll_spi.h:1765
ll_qspi_deinit
error_status_t ll_qspi_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_id_code
__STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
Get ID code.
Definition: gr55xx_ll_spi.h:1379
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_spi.h:1349
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1319
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1146
ll_spi_get_instruction_size
__STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2048
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_spi.h:1033
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1842
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1941
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:740
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr55xx_ll_spi.h:755
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_spi.h:1221
ll_spi_get_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2152
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_spi.h:1594
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:708
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
Get clock polarity.
Definition: gr55xx_ll_spi.h:906
ll_spi_set_frame_format
__STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:567
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1896
_ll_spim_init_t::slave_select
uint32_t slave_select
Definition: gr55xx_ll_spi.h:98
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1610
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
Get serial protocol used.
Definition: gr55xx_ll_spi.h:981
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_spi.h:1423
ll_spi_set_instruction_size
__STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2028
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr55xx_ll_spi.h:1720
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
Get frame data size.
Definition: gr55xx_ll_spi.h:675
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_spi.h:1546
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_spi.h:1049
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1926
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1864
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_spi.h:1664
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_spi.h:1525
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_spi.h:785
_ll_qspi_init_t::transfer_direction
uint32_t transfer_direction
Definition: gr55xx_ll_spi.h:137
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_spi.h:125
_ll_qspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_spi.h:177
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_spi.h:93
ll_spi_get_version
__STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
Get IP version.
Definition: gr55xx_ll_spi.h:1394
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_spi.h:547
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_spi.h:850
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_spi.h:926
ll_spi_set_wait_cycles
__STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:1991
_ll_qspi_init_t::wait_cycles
uint32_t wait_cycles
Definition: gr55xx_ll_spi.h:157
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_spi.h:1109
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr55xx_ll_spi.h:1750
ll_spim_deinit
error_status_t ll_spim_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1811
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_spi.h:1257
ll_qspi_struct_init
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1128
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1796
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_spi.h:1646
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_spi.h:1735
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_spi.h:1202
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
Disable slave output.
Definition: gr55xx_ll_spi.h:815
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
Enable slave output.
Definition: gr55xx_ll_spi.h:800
_ll_qspi_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_spi.h:162
ll_spi_get_address_size
__STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2113
ll_qspi_init
error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1880
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_spi.h:1240
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
Get clock phase.
Definition: gr55xx_ll_spi.h:943