gr55xx_ll_xqspi.h
Go to the documentation of this file.
1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (XQSPI)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_xqspi_init_t
77 {
78 uint32_t mode;
81 uint32_t cache_mode;
86 uint32_t read_cmd;
91 uint32_t data_size;
96 uint32_t data_order;
101 uint32_t clock_polarity;
106 uint32_t clock_phase;
111 uint32_t baud_rate;
116 } ll_xqspi_init_t;
117
127 /* Exported constants --------------------------------------------------------*/
135 #define LL_XQSPI_MODE_XIP 0
136 #define LL_XQSPI_MODE_QSPI 1
142 #define LL_XQSPI_XIP_CMD_READ 0x03
143 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B
144 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B
145 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB
146 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B
147 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB
153 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos)
154 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos)
155 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos)
156 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos)
162 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL
163 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4
169 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL
170 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32
176 #define LL_XQSPI_CACHE_DIS 0
177 #define LL_XQSPI_CACHE_EN 1
183 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL
184 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO
190 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL
191 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS
198 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK
199 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL
200 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY
201 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK
202 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL
203 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY
204 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP
211 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk
212 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk
213 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk
214 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk
215 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk
217 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk
218 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk
219 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk
220 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk
221 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk
227 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL
228 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL
229 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL
230 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL
231 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL
237 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL
238 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos)
239 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos)
245 #define LL_XQSPI_QSPI_LSB 0x00000000UL
246 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST
252 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL
253 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
254 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
255 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
256 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
257 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
258 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
259 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
265 #define LL_XQSPI_SCPHA_1EDGE 0
266 #define LL_XQSPI_SCPHA_2EDGE 1
272 #define LL_XQSPI_SCPOL_LOW 0
273 #define LL_XQSPI_SCPOL_HIGH 1
279 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL
280 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos)
281 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos)
282 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos)
283 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos)
289 #define LL_XQSPI_ENABLE_PRESENT 0
290 #define LL_XQSPI_DISABLE_PRESENT 1
296 #define LL_XQSPI_FLASH_WRITE_128BIT 0
297 #define LL_XQSPI_FLASH_WRITE_32BIT 1
307 #define LL_XQSPI_DEFAULT_CONFIG \
308 { \
309 .mode = LL_XQSPI_MODE_QSPI, \
310 .cache_mode = LL_XQSPI_CACHE_EN, \
311 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
312 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
313 .data_order = LL_XQSPI_QSPI_MSB, \
314 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
315 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
316 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
317 }
318
322 /* Exported macro ------------------------------------------------------------*/
338 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
339
346 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
347
354 /* Exported functions --------------------------------------------------------*/
374 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
375 {
376 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
377 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
378 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
379 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
380 }
381
393 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
394 {
395 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
396 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
397 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
398 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
399 }
400
411 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
412 {
413 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
414 }
415
427 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
428 {
429 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
430 }
431
443 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
444 {
445 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
446 }
447
458 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
459 {
460 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
461 }
462
477 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
478 {
479 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
480 }
481
495 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
496 {
497 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
498 }
499
514 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
515 {
516 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
517 }
518
532 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
533 {
534 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
535 }
536
549 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
550 {
551 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
552 }
553
564 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
565 {
566 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
567 }
568
580 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
581 {
582 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
583 }
584
596 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
597 {
598 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
599 }
600
611 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
612 {
613 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
614 }
615
627 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
628 {
629 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
630 }
631
643 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
644 {
645 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
646 }
647
659 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
660 {
661 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
662 }
663
688 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
689 {
690 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
691 }
692
709 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
710 {
711 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
712 }
713
725 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
726 {
727 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
728 }
729
741 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
742 {
743 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
744 }
745
756 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
757 {
758 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
759 }
760
777 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
778 {
779 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
780 }
781
796 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
797 {
798 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
799 }
800
815 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
816 {
817 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
818 }
819
832 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
833 {
834 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
835 }
836
851 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
852 {
853 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
854 }
855
868 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
869 {
870 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
871 }
872
887 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
888 {
889 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
890 }
891
904 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
905 {
906 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
907 }
908
923 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
924 {
925 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
926 }
927
940 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
941 {
942 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
943 }
944
958 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
959 {
960 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
961 }
962
973 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
974 {
975 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
976 }
977
994 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
995 {
996 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
997 }
998
1013 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1014 {
1015 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES));
1016 }
1017
1030 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1031 {
1032 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1033 }
1034
1045 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1046 {
1047 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1048 }
1049
1060 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1061 {
1062 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1063 }
1064
1075 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1076 {
1077 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1078 }
1079
1091 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1092 {
1093 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1094 }
1095
1107 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1108 {
1109 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1110 }
1111
1123 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1124 {
1125 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1126 }
1127
1139 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1140 {
1141 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1142 }
1143
1155 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1156 {
1157 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1158 }
1159
1171 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1172 {
1173 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1174 }
1175
1187 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1188 {
1189 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1190 }
1191
1209 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1210 {
1211 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1212 }
1213
1225 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1226 {
1227 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1228 }
1229
1241 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1242 {
1243 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1244 }
1245
1256 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1257 {
1258 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1259 }
1260
1271 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1272 {
1273 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1274 }
1275
1286 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1287 {
1288 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1289 }
1290
1307 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1308 {
1309 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1310 }
1311
1327 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1328 {
1329 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1330 }
1331
1348 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1349 {
1350 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1351 }
1352
1368 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1369 {
1370 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1371 }
1372
1383 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1384 {
1385 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1386 }
1387
1398 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1399 {
1400 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1401 }
1402
1413 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1414 {
1415 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1416 }
1417
1428 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1429 {
1430 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1431 }
1432
1443 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1444 {
1445 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1446 }
1447
1458 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1459 {
1460 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1461 }
1462
1477 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1478 {
1479 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1480 }
1481
1494 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1495 {
1496 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1497 }
1498
1513 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1514 {
1515 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1516 }
1517
1530 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1531 {
1532 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1533 }
1534
1548 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1549 {
1550 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1551 }
1552
1565 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1566 {
1567 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1568 }
1569
1580 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1581 {
1582 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1583 }
1584
1595 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1596 {
1597 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1598 }
1599
1610 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1611 {
1612 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1613 }
1614
1625 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1626 {
1627 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1628 }
1629
1640 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1641 {
1642 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1643 }
1644
1655 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1656 {
1657 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1658 }
1659
1680 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1681 {
1682 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1683 }
1684
1703 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1704 {
1705 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1706 }
1707
1718 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1719 {
1720 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1721 }
1722
1733 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1734 {
1735 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1736 }
1737
1748 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1749 {
1750 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1751 }
1752
1763 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1764 {
1765 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1766 }
1767
1778 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1779 {
1780 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1781 }
1782
1793 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1794 {
1795 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1796 }
1797
1813 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1814 {
1815 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1816 }
1817
1831 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1832 {
1833 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1834 }
1835
1853 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1854 {
1855 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1856 }
1857
1876 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1877 {
1878 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
1879 }
1880
1892 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1893 {
1894 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1895 }
1896
1908 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1909 {
1910 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1911 }
1912
1924 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
1925 {
1926 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
1927 }
1928
1939 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
1940 {
1941 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
1942 }
1943
1954 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
1955 {
1956 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
1957 }
1958
1969 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
1970 {
1971 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
1972 }
1973
1991 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
1992 {
1993 SET_BITS(XQSPIx->QSPI.INTEN, mask);
1994 }
1995
2013 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2014 {
2015 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2016 }
2017
2034 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2035 {
2036 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2037 }
2038
2054 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2055 {
2056 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2057 }
2058
2079 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2080 {
2081 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2082 }
2083
2101 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2102 {
2103 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2104 }
2105
2117 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2118 {
2119 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2120 }
2121
2132 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2133 {
2134 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2135 }
2136
2148 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2149 {
2150 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2151 }
2152
2163 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2164 {
2165 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2166 }
2167
2178 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2179 {
2180 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2181 }
2182
2196 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2197 {
2198 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2199 }
2200
2213 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2214 {
2215 //GR5515_C and future version.
2216 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2217 }
2218
2232 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2233 {
2234 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2235 }
2236
2249 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2250 {
2251 return READ_REG(XQSPIx->QSPI.BYPASS);
2252 }
2253
2264 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2265 {
2266 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2267 }
2268
2279 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2280 {
2281 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2282 }
2283
2293 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2294 {
2295 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN) == (AON_PWR_REG01_EFLASH_PAD_EN));
2296 }
2297
2313 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2314 {
2315 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL, speed);
2316 }
2317
2332 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2333 {
2334 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL));
2335 }
2336
2347 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2348 {
2349 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2350 }
2351
2362 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2363 {
2364 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2365 }
2366
2376 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2377 {
2378 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET) == (AON_PWR_REG01_XF_TAG_RET));
2379 }
2380
2381
2382
2396 error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2397
2408 error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2409
2416 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2417
2422 #endif /* XQSPI */
2423
2424 #ifdef __cplusplus
2425 }
2426 #endif
2427
2428 #endif /* __GR55xx_LL_XQSPI_H__ */
2429
ll_xqspi_set_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr55xx_ll_xqspi.h:1680
ll_xqspi_is_active_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_xqspi.h:1876
ll_xqspi_disable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr55xx_ll_xqspi.h:1075
ll_xqspi_is_enabled_cache
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr55xx_ll_xqspi.h:411
ll_xqspi_get_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:564
ll_xqspi_is_enabled_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr55xx_ll_xqspi.h:1610
ll_xqspi_set_xip_ss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr55xx_ll_xqspi.h:777
ll_xqspi_get_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr55xx_ll_xqspi.h:1565
ll_xqspi_is_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr55xx_ll_xqspi.h:2293
ll_xqspi_get_cache_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr55xx_ll_xqspi.h:659
ll_xqspi_is_enabled_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:1123
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr55xx_ll_xqspi.h:101
ll_xqspi_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr55xx_ll_xqspi.h:2347
ll_xqspi_enable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr55xx_ll_xqspi.h:1428
ll_xqspi_qspi_transmit_data16
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1225
ll_xqspi_get_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr55xx_ll_xqspi.h:709
ll_xqspi_disable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr55xx_ll_xqspi.h:741
ll_xqspi_get_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr55xx_ll_xqspi.h:495
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_ll_xqspi.h:111
ll_xqspi_get_xip_ss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr55xx_ll_xqspi.h:796
ll_xqspi_get_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:1494
ll_xqspi_disable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr55xx_ll_xqspi.h:2163
ll_xqspi_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr55xx_ll_xqspi.h:2264
ll_xqspi_disable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr55xx_ll_xqspi.h:2362
ll_xqspi_disable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1640
ll_xqspi_set_present_bypass
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
Set QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2232
ll_xqspi_set_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:1513
ll_xqspi_get_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr55xx_ll_xqspi.h:2054
ll_xqspi_get_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr55xx_ll_xqspi.h:904
_ll_xqspi_init_t::data_order
uint32_t data_order
Definition: gr55xx_ll_xqspi.h:96
ll_xqspi_enable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr55xx_ll_xqspi.h:580
ll_xqspi_is_enabled_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr55xx_ll_xqspi.h:611
ll_xqspi_enable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr55xx_ll_xqspi.h:725
ll_xqspi_is_enabled_cache_flush
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr55xx_ll_xqspi.h:458
ll_xqspi_set_flash_write
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2196
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Definition: gr55xx_ll_xqspi.h:81
ll_xqspi_disable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr55xx_ll_xqspi.h:596
ll_xqspi_get_xip_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr55xx_ll_xqspi.h:1107
ll_xqspi_enable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_xqspi.h:1991
ll_xqspi_set_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:549
ll_xqspi_is_enabled_xip_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr55xx_ll_xqspi.h:756
ll_xqspi_disable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1733
ll_xqspi_set_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr55xx_ll_xqspi.h:958
ll_xqspi_enable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1580
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_get_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1368
ll_xqspi_enable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr55xx_ll_xqspi.h:1060
ll_xqspi_init
error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_get_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2132
ll_xqspi_is_enabled_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1793
ll_xqspi_is_qspi_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_xqspi.h:2079
ll_xqspi_qspi_receive_data8
SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1256
ll_xqspi_get_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1045
ll_xqspi_is_enabled_qspi_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:2034
ll_xqspi_is_enabled_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr55xx_ll_xqspi.h:1458
ll_xqspi_is_enabled_xip
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr55xx_ll_xqspi.h:1091
ll_xqspi_get_req_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr55xx_ll_xqspi.h:1155
ll_xqspi_deinit
error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_enable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr55xx_ll_xqspi.h:2148
ll_xqspi_get_flash_write
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2213
ll_xqspi_disable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1398
ll_xqspi_set_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1307
ll_xqspi_get_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr55xx_ll_xqspi.h:1831
ll_xqspi_is_enabled_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr55xx_ll_xqspi.h:1413
ll_xqspi_enable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr55xx_ll_xqspi.h:1171
ll_xqspi_disable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1778
ll_xqspi_is_enabled_qspi
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr55xx_ll_xqspi.h:2178
ll_xqspi_set_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:815
ll_xqspi_clear_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr55xx_ll_xqspi.h:2101
ll_xqspi_get_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1939
ll_xqspi_qspi_transmit_data32
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1241
ll_xqspi_get_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2332
ll_xqspi_is_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr55xx_ll_xqspi.h:2376
ll_xqspi_disable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr55xx_ll_xqspi.h:2279
ll_xqspi_get_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:532
_ll_xqspi_init_t::mode
uint32_t mode
Definition: gr55xx_ll_xqspi.h:78
ll_xqspi_set_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2313
ll_xqspi_disable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_xqspi.h:2013
ll_xqspi_disable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr55xx_ll_xqspi.h:1443
ll_xqspi_qspi_receive_data32
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1286
ll_xqspi_enable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1625
ll_xqspi_set_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:851
ll_xqspi_get_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:868
ll_xqspi_enable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr55xx_ll_xqspi.h:374
ll_xqspi_is_enabled_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1748
ll_xqspi_disable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr55xx_ll_xqspi.h:1187
ll_xqspi_qspi_receive_data16
SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1271
ll_xqspi_get_qspi_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr55xx_ll_xqspi.h:1853
ll_xqspi_get_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:832
ll_xqspi_set_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr55xx_ll_xqspi.h:887
ll_xqspi_get_present_bypass
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
Get QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2249
ll_xqspi_set_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr55xx_ll_xqspi.h:1813
ll_xqspi_set_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2117
ll_xqspi_is_enabled_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr55xx_ll_xqspi.h:1655
ll_xqspi_set_xip_endian
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr55xx_ll_xqspi.h:923
ll_xqspi_set_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr55xx_ll_xqspi.h:1548
ll_xqspi_enable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr55xx_ll_xqspi.h:1892
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr55xx_ll_xqspi.h:77
ll_xqspi_disable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr55xx_ll_xqspi.h:1908
ll_xqspi_set_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:514
ll_xqspi_enable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1763
ll_xqspi_disable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1595
ll_xqspi_set_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr55xx_ll_xqspi.h:477
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Definition: gr55xx_ll_xqspi.h:106
ll_xqspi_get_flag_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr55xx_ll_xqspi.h:1139
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Definition: gr55xx_ll_xqspi.h:86
ll_xqspi_get_cache_hitcount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr55xx_ll_xqspi.h:627
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_get_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr55xx_ll_xqspi.h:973
ll_xqspi_get_cache_misscount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr55xx_ll_xqspi.h:643
ll_xqspi_set_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:1477
ll_xqspi_get_qspi_tx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_xqspi.h:1954
ll_xqspi_set_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1030
ll_xqspi_get_qspi_rx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_xqspi.h:1969
ll_xqspi_enable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr55xx_ll_xqspi.h:427
ll_xqspi_qspi_transmit_data8
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1209
ll_xqspi_get_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:1530
ll_xqspi_enable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1383
ll_xqspi_set_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:994
ll_xqspi_disable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr55xx_ll_xqspi.h:443
ll_xqspi_set_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1924
ll_xqspi_enable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1718
ll_xqspi_set_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr55xx_ll_xqspi.h:688
ll_xqspi_get_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1013
ll_xqspi_get_xip_endian
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr55xx_ll_xqspi.h:940
ll_xqspi_disable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr55xx_ll_xqspi.h:393
ll_xqspi_get_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1327
ll_xqspi_get_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr55xx_ll_xqspi.h:1703
ll_xqspi_set_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1348
_ll_xqspi_init_t::data_size
uint32_t data_size
Definition: gr55xx_ll_xqspi.h:91