gr55xx_hal_cortex.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_CORTEX_H__
53 #define __GR55xx_HAL_CORTEX_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal_def.h"
61
62 /* Exported types ------------------------------------------------------------*/
63
68 #if (__MPU_PRESENT == 1U)
69
77 typedef struct _mpu_region_init_t
78 {
79 uint8_t enable;
82 uint8_t number;
85 uint32_t base_address;
87 uint8_t size;
90 uint8_t subregion_disable;
93 uint8_t type_tex_field;
96 uint8_t access_permission;
99 uint8_t disable_exec;
102 uint8_t is_shareable;
105 uint8_t is_cacheable;
108 uint8_t is_bufferable;
111 } mpu_region_init_t;
112
115 #endif /* __MPU_PRESENT */
116
125 /* Exported constants --------------------------------------------------------*/
126
134 #define NVIC_PRIORITYGROUP_0 (0x00000007U)
136 #define NVIC_PRIORITYGROUP_1 (0x00000006U)
138 #define NVIC_PRIORITYGROUP_2 (0x00000005U)
140 #define NVIC_PRIORITYGROUP_3 (0x00000004U)
142 #define NVIC_PRIORITYGROUP_4 (0x00000003U)
144 #define NVIC_PRIORITYGROUP_5 (0x00000002U)
146 #define NVIC_PRIORITYGROUP_6 (0x00000001U)
148 #define NVIC_PRIORITYGROUP_7 (0x00000000U)
155 #define SYSTICK_CLKSOURCE_REFCLK (0x00000000U)
156 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
159 #if (__MPU_PRESENT == 1U)
160
163 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
164 #define MPU_HARDFAULT_NMI (0x00000002U)
165 #define MPU_PRIVILEGED_DEFAULT (0x00000004U)
166 #define MPU_HFNMI_PRIVDEF (0x00000006U)
172 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
173 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
179 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
180 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
186 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
187 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
193 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
194 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
200 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
201 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
207 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
208 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
209 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
215 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
216 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
217 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
218 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
219 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
220 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
221 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
222 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
223 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
224 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
225 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
226 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
227 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
228 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
229 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
230 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
231 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
232 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
233 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
234 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
235 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
236 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
237 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
238 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
239 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
240 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
241 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
242 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
248 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
249 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
250 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
251 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
252 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
253 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
259 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
260 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
261 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
262 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
263 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
264 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
265 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
266 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
268 #endif /* __MPU_PRESENT */
269
272 /* Exported Macros -----------------------------------------------------------*/
273 /* Private types -------------------------------------------------------------*/
274 /* Private variables ---------------------------------------------------------*/
275 /* Private constants ---------------------------------------------------------*/
276
277 /* Private macros ------------------------------------------------------------*/
287 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
288 ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
289 ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
290 ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
291 ((__GROUP__) == NVIC_PRIORITYGROUP_4) || \
292 ((__GROUP__) == NVIC_PRIORITYGROUP_5) || \
293 ((__GROUP__) == NVIC_PRIORITYGROUP_6) || \
294 ((__GROUP__) == NVIC_PRIORITYGROUP_7))
295
301 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x80U)
302
308 #define IS_NVIC_SUB_PRIORITY(__PRIORITY__) ((__PRIORITY__) <= 0xFFU)
309
315 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) >= 0x00)
316
322 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
323 ((__SOURCE__) == SYSTICK_CLKSOURCE_REFCLK))
324
325 #if (__MPU_PRESENT == 1U)
326
332 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
333 ((__STATE__) == MPU_REGION_DISABLE))
334
340 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
341 ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
342
348 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \
349 ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
350
356 #define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \
357 ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE))
358
364 #define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \
365 ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE))
366
372 #define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \
373 ((__TYPE__) == MPU_TEX_LEVEL1) || \
374 ((__TYPE__) == MPU_TEX_LEVEL2))
375
381 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \
382 ((__TYPE__) == MPU_REGION_PRIV_RW) || \
383 ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \
384 ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \
385 ((__TYPE__) == MPU_REGION_PRIV_RO) || \
386 ((__TYPE__) == MPU_REGION_PRIV_RO_URO))
387
393 #define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
394 ((__NUMBER__) == MPU_REGION_NUMBER1) || \
395 ((__NUMBER__) == MPU_REGION_NUMBER2) || \
396 ((__NUMBER__) == MPU_REGION_NUMBER3) || \
397 ((__NUMBER__) == MPU_REGION_NUMBER4) || \
398 ((__NUMBER__) == MPU_REGION_NUMBER5) || \
399 ((__NUMBER__) == MPU_REGION_NUMBER6) || \
400 ((__NUMBER__) == MPU_REGION_NUMBER7))
401
407 #define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \
408 ((__SIZE__) == MPU_REGION_SIZE_64B) || \
409 ((__SIZE__) == MPU_REGION_SIZE_128B) || \
410 ((__SIZE__) == MPU_REGION_SIZE_256B) || \
411 ((__SIZE__) == MPU_REGION_SIZE_512B) || \
412 ((__SIZE__) == MPU_REGION_SIZE_1KB) || \
413 ((__SIZE__) == MPU_REGION_SIZE_2KB) || \
414 ((__SIZE__) == MPU_REGION_SIZE_4KB) || \
415 ((__SIZE__) == MPU_REGION_SIZE_8KB) || \
416 ((__SIZE__) == MPU_REGION_SIZE_16KB) || \
417 ((__SIZE__) == MPU_REGION_SIZE_32KB) || \
418 ((__SIZE__) == MPU_REGION_SIZE_64KB) || \
419 ((__SIZE__) == MPU_REGION_SIZE_128KB) || \
420 ((__SIZE__) == MPU_REGION_SIZE_256KB) || \
421 ((__SIZE__) == MPU_REGION_SIZE_512KB) || \
422 ((__SIZE__) == MPU_REGION_SIZE_1MB) || \
423 ((__SIZE__) == MPU_REGION_SIZE_2MB) || \
424 ((__SIZE__) == MPU_REGION_SIZE_4MB) || \
425 ((__SIZE__) == MPU_REGION_SIZE_8MB) || \
426 ((__SIZE__) == MPU_REGION_SIZE_16MB) || \
427 ((__SIZE__) == MPU_REGION_SIZE_32MB) || \
428 ((__SIZE__) == MPU_REGION_SIZE_64MB) || \
429 ((__SIZE__) == MPU_REGION_SIZE_128MB) || \
430 ((__SIZE__) == MPU_REGION_SIZE_256MB) || \
431 ((__SIZE__) == MPU_REGION_SIZE_512MB) || \
432 ((__SIZE__) == MPU_REGION_SIZE_1GB) || \
433 ((__SIZE__) == MPU_REGION_SIZE_2GB) || \
434 ((__SIZE__) == MPU_REGION_SIZE_4GB))
435
436
442 #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)
443 #endif /* __MPU_PRESENT */
444
449 /* Exported functions --------------------------------------------------------*/
497 void hal_nvic_set_priority_grouping(uint32_t priority_group);
498
514 void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority);
515
528 void hal_nvic_enable_irq(IRQn_Type IRQn);
529
539 void hal_nvic_disable_irq(IRQn_Type IRQn);
540
546 void hal_nvic_system_reset(void);
547
548
561 uint32_t hal_systick_config(uint32_t ticks_number);
562
581 #if (__MPU_PRESENT == 1U)
582
590 void hal_mpu_config_region(mpu_region_init_t *p_mpu_init);
591 #endif /* __MPU_PRESENT */
592
600 uint32_t hal_nvic_get_priority_grouping(void);
601
631 void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority);
632
642 void hal_nvic_set_pending_irq(IRQn_Type IRQn);
643
658 uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn);
659
669 void hal_nvic_clear_pending_irq(IRQn_Type IRQn);
670
684 uint32_t hal_nvic_get_active(IRQn_Type IRQn);
685
696 void hal_systick_clk_source_config(uint32_t clk_source);
697
710 void hal_systick_irq_handler(void);
711
720 void hal_systick_callback(void);
721
724 /* Private functions ---------------------------------------------------------*/
730 #if (__MPU_PRESENT == 1U)
731
737 void hal_mpu_disable(void);
738
752 void hal_mpu_enable(uint32_t mpu_control);
753
754 #endif /* __MPU_PRESENT */
755
760 #ifdef __cplusplus
761 }
762 #endif
763
764 #endif /* __GR55xx_HAL_CORTEX_H__ */
765
hal_nvic_system_reset
void hal_nvic_system_reset(void)
Initiate a system reset request to reset the MCU.
hal_nvic_get_priority
void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority)
Get the priority of an interrupt.
hal_nvic_enable_irq
void hal_nvic_enable_irq(IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
hal_systick_clk_source_config
void hal_systick_clk_source_config(uint32_t clk_source)
Configure the SysTick clock source.
hal_nvic_set_pending_irq
void hal_nvic_set_pending_irq(IRQn_Type IRQn)
Set Pending bit of an external interrupt.
hal_systick_callback
void hal_systick_callback(void)
SYSTICK callback.
hal_nvic_set_priority
void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority)
Set the priority of an interrupt.
hal_nvic_get_priority_grouping
uint32_t hal_nvic_get_priority_grouping(void)
Get the priority grouping field from the NVIC Interrupt Controller.
hal_nvic_get_active
uint32_t hal_nvic_get_active(IRQn_Type IRQn)
Get active interrupt (reads the active register in NVIC and returns the active bit).
hal_systick_irq_handler
void hal_systick_irq_handler(void)
This function handles SYSTICK interrupt request.
hal_nvic_clear_pending_irq
void hal_nvic_clear_pending_irq(IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
hal_systick_config
uint32_t hal_systick_config(uint32_t ticks_number)
Initialize the System Timer and its interrupt, and start the System Tick Timer. Counter is in free ru...
hal_nvic_get_pending_irq
uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn)
Get Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the spe...
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_nvic_set_priority_grouping
void hal_nvic_set_priority_grouping(uint32_t priority_group)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequ...
hal_nvic_disable_irq
void hal_nvic_disable_irq(IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.