gr55xx_hal_xqspi.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_XQSPI_H__
53 #define __GR55xx_HAL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_xqspi.h"
61 #include "gr55xx_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
75 typedef enum
76 {
77 HAL_XQSPI_STATE_RESET = 0x00,
78 HAL_XQSPI_STATE_READY = 0x01,
79 HAL_XQSPI_STATE_BUSY = 0x02,
80 HAL_XQSPI_STATE_BUSY_INDIRECT_TX = 0x12,
81 HAL_XQSPI_STATE_BUSY_INDIRECT_RX = 0x22,
82 HAL_XQSPI_STATE_ABORT = 0x08,
83 HAL_XQSPI_STATE_ERROR = 0x04
85 } hal_xqspi_state_t;
86
102 typedef struct _xqspi_init_t
103 {
104 uint32_t work_mode;
107 uint32_t cache_mode;
110 uint32_t read_cmd;
113 uint32_t baud_rate;
116 uint32_t clock_mode;
119 } xqspi_init_t;
129 typedef struct _xqspi_handle_t
130 {
131 xqspi_regs_t *p_instance;
133 xqspi_init_t init;
135 uint8_t *p_tx_buffer;
137 __IO uint32_t tx_xfer_size;
139 __IO uint32_t tx_xfer_count;
141 uint8_t *p_rx_buffer;
143 __IO uint32_t rx_xfer_size;
145 __IO uint32_t rx_xfer_count;
147 __IO hal_lock_t lock;
149 __IO hal_xqspi_state_t state;
151 __IO uint32_t error_code;
153 uint32_t retry;
155 } xqspi_handle_t;
165 typedef struct _xqspi_command_t
166 {
167 uint32_t inst;
170 uint32_t addr;
173 uint32_t inst_size;
176 uint32_t addr_size;
179 uint32_t dummy_cycles;
182 uint32_t inst_addr_mode;
185 uint32_t data_mode;
188 uint32_t length;
192 } xqspi_command_t;
209 typedef struct _hal_xqspi_callback
210 {
211 void (*xqspi_msp_init)(xqspi_handle_t *p_xqspi);
212 void (*xqspi_msp_deinit)(xqspi_handle_t *p_xqspi);
213 } hal_xqspi_callback_t;
214
224 /* Exported constants --------------------------------------------------------*/
232 #define HAL_XQSPI_ERROR_NONE ((uint32_t)0x00000000)
233 #define HAL_XQSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
234 #define HAL_XQSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
235 #define HAL_XQSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
241 #define XQSPI_WORK_MODE_QSPI LL_XQSPI_MODE_QSPI
242 #define XQSPI_WORK_MODE_XIP LL_XQSPI_MODE_XIP
248 #define XQSPI_CACHE_MODE_DIS LL_XQSPI_CACHE_DIS
249 #define XQSPI_CACHE_MODE_EN LL_XQSPI_CACHE_EN
255 #define XQSPI_READ_CMD_READ LL_XQSPI_XIP_CMD_READ
256 #define XQSPI_READ_CMD_FAST_READ LL_XQSPI_XIP_CMD_FAST_READ
257 #define XQSPI_READ_CMD_DUAL_OUT_READ LL_XQSPI_XIP_CMD_DUAL_OUT_READ
258 #define XQSPI_READ_CMD_DUAL_IO_READ LL_XQSPI_XIP_CMD_DUAL_IO_READ
259 #define XQSPI_READ_CMD_QUAD_OUT_READ LL_XQSPI_XIP_CMD_QUAD_OUT_READ
260 #define XQSPI_READ_CMD_QUAD_IO_READ LL_XQSPI_XIP_CMD_QUAD_IO_READ
266 #define XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE)
268 #define XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE)
270 #define XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE)
272 #define XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE)
279 #define XQSPI_BAUD_RATE_64M LL_XQSPI_BAUD_RATE_64M
280 #define XQSPI_BAUD_RATE_48M LL_XQSPI_BAUD_RATE_48M
281 #define XQSPI_BAUD_RATE_32M LL_XQSPI_BAUD_RATE_32M
282 #define XQSPI_BAUD_RATE_24M LL_XQSPI_BAUD_RATE_24M
283 #define XQSPI_BAUD_RATE_16M LL_XQSPI_BAUD_RATE_16M
289 #define XQSPI_DATA_MODE_SPI LL_XQSPI_QSPI_FRF_SPI
290 #define XQSPI_DATA_MODE_DUALSPI LL_XQSPI_QSPI_FRF_DUALSPI
291 #define XQSPI_DATA_MODE_QUADSPI LL_XQSPI_QSPI_FRF_QUADSPI
297 #define XQSPI_FIFO_THRESHOLD_1_8 LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
298 #define XQSPI_FIFO_THRESHOLD_1_4 LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
299 #define XQSPI_FIFO_THRESHOLD_1_2 LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
300 #define XQSPI_FIFO_THRESHOLD_3_4 LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
301 #define XQSPI_FIFO_DEPTH LL_XQSPI_QSPI_FIFO_DEPTH
307 #define XQSPI_INSTSIZE_00_BITS (0)
308 #define XQSPI_INSTSIZE_08_BITS (1)
309 #define XQSPI_INSTSIZE_16_BITS (2)
315 #define XQSPI_ADDRSIZE_00_BITS (0)
316 #define XQSPI_ADDRSIZE_08_BITS (1)
317 #define XQSPI_ADDRSIZE_16_BITS (2)
318 #define XQSPI_ADDRSIZE_24_BITS (3)
319 #define XQSPI_ADDRSIZE_32_BITS (4)
325 #define XQSPI_INST_ADDR_ALL_IN_SPI (0)
326 #define XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1)
327 #define XQSPI_INST_ADDR_ALL_IN_SPIFRF (2)
333 #define XQSPI_FLAG_RFF LL_XQSPI_QSPI_STAT_RFF
334 #define XQSPI_FLAG_RFTF LL_XQSPI_QSPI_STAT_RFTF
335 #define XQSPI_FLAG_RFE LL_XQSPI_QSPI_STAT_RFE
336 #define XQSPI_FLAG_TFF LL_XQSPI_QSPI_STAT_TFF
337 #define XQSPI_FLAG_TFTF LL_XQSPI_QSPI_STAT_TFTF
338 #define XQSPI_FLAG_TFE LL_XQSPI_QSPI_STAT_TFE
339 #define XQSPI_FLAG_BUSY LL_XQSPI_QSPI_STAT_BUSY
345 #define XQSPI_DISABLE_PRESENT LL_XQSPI_DISABLE_PRESENT
346 #define XQSPI_ENABLE_PRESENT LL_XQSPI_ENABLE_PRESENT
352 #define HAL_XQSPI_RETRY_DEFAULT_VALUE ((uint32_t)1000)
356 /* Exported macro ------------------------------------------------------------*/
357
365 #define __HAL_XQSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_XQSPI_STATE_RESET)
366
371 #define __HAL_XQSPI_ENABLE_QSPI(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, SSI_SSIEN_EN)
372
377 #define __HAL_XQSPI_DISABLE_QSPI(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, SSI_SSIEN_EN)
378
383 #define __HAL_XQSPI_ENABLE_XIP(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->XIP.CTRL3, SSI_SSIEN_EN);\
384 while(!ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
385
390 #define __HAL_XQSPI_DISABLE_XIP(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->XIP.CTRL3, SSI_SSIEN_EN);\
391 while(ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
392
397 #define __HAL_XQSPI_ENABLE_CACHE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
398
403 #define __HAL_XQSPI_DISABLE_CACHE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
404
418 #define __HAL_XQSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->QSPI.STAT, (__FLAG__)) != 0) ? SET : RESET)
419
422 /* Private macros ------------------------------------------------------------*/
431 #define IS_XQSPI_WORK_MODE(__MODE__) (((__MODE__) == XQSPI_WORK_MODE_QSPI) || \
432 ((__MODE__) == XQSPI_WORK_MODE_XIP))
433
438 #define IS_XQSPI_CACHE_MODE(__MODE__) (((__MODE__) == XQSPI_CACHE_MODE_DIS) || \
439 ((__MODE__) == XQSPI_CACHE_MODE_EN))
440
445 #define IS_XQSPI_READ_CMD(__CMD__) (((__CMD__) == XQSPI_READ_CMD_READ ) || \
446 ((__CMD__) == XQSPI_READ_CMD_FAST_READ ) || \
447 ((__CMD__) == XQSPI_READ_CMD_DUAL_OUT_READ) || \
448 ((__CMD__) == XQSPI_READ_CMD_DUAL_IO_READ ) || \
449 ((__CMD__) == XQSPI_READ_CMD_QUAD_OUT_READ) || \
450 ((__CMD__) == XQSPI_READ_CMD_QUAD_IO_READ ))
451
456 #define IS_XQSPI_BAUD_RATE(__BAUD__) (((__BAUD__) == XQSPI_BAUD_RATE_64M) || \
457 ((__BAUD__) == XQSPI_BAUD_RATE_48M) || \
458 ((__BAUD__) == XQSPI_BAUD_RATE_32M) || \
459 ((__BAUD__) == XQSPI_BAUD_RATE_24M) || \
460 ((__BAUD__) == XQSPI_BAUD_RATE_16M))
461
466 #define IS_XQSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == XQSPI_CLOCK_MODE_0) || \
467 ((__CLKMODE__) == XQSPI_CLOCK_MODE_1) || \
468 ((__CLKMODE__) == XQSPI_CLOCK_MODE_2) || \
469 ((__CLKMODE__) == XQSPI_CLOCK_MODE_3))
470
475 #define IS_XQSPI_FIFO_THRESHOLD(__THR__) (((__THR__) == XQSPI_FIFO_THRESHOLD_1_8) || \
476 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_4) || \
477 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_2) || \
478 ((__THR__) == XQSPI_FIFO_THRESHOLD_3_4))
479
484 #define IS_XQSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == XQSPI_INSTSIZE_00_BITS) || \
485 ((__INST_SIZE__) == XQSPI_INSTSIZE_08_BITS) || \
486 ((__INST_SIZE__) == XQSPI_INSTSIZE_16_BITS))
487
492 #define IS_XQSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == XQSPI_ADDRSIZE_00_BITS) || \
493 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_08_BITS) || \
494 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_16_BITS) || \
495 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_24_BITS) || \
496 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_32_BITS))
497
502 #define IS_XQSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPI) || \
503 ((__MODE__) == XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
504 ((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPIFRF))
505
510 #define IS_XQSPI_DATA_MODE(__MODE__) (((__MODE__) == XQSPI_DATA_MODE_SPI) || \
511 ((__MODE__) == XQSPI_DATA_MODE_DUALSPI) || \
512 ((__MODE__) == XQSPI_DATA_MODE_QUADSPI))
513
519 /* Exported functions --------------------------------------------------------*/
563 hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi);
564
575 hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi);
576
585 void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi);
586
595 void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi);
596
638 hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
639
654 hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
655
656 #if defined RTL_SIM
657 hal_status_t hal_xqspi_command_receive_rtl(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry);
658 #endif
659
660
675 hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry);
676
691 hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry);
692
728 hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi);
729
737 uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi);
738
746 void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry);
747
763 hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold);
764
780 hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold);
781
789 uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi);
790
798 uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi);
799
810 void hal_xqspi_set_xip_present_status(xqspi_handle_t *p_xqspi, uint32_t status);
811
816 #ifdef __cplusplus
817 }
818 #endif
819
820 #endif /* __GR55xx_HAL_XQSPI_H__ */
821
_xqspi_handle_t::tx_xfer_count
__IO uint32_t tx_xfer_count
Definition: gr55xx_hal_xqspi.h:139
_hal_xqspi_callback::xqspi_msp_init
void(* xqspi_msp_init)(xqspi_handle_t *p_xqspi)
Definition: gr55xx_hal_xqspi.h:211
hal_xqspi_msp_init
void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI MSP.
_xqspi_init_t::cache_mode
uint32_t cache_mode
Definition: gr55xx_hal_xqspi.h:107
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
hal_xqspi_deinit
hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI peripheral.
_xqspi_command_t::inst_size
uint32_t inst_size
Definition: gr55xx_hal_xqspi.h:173
HAL_XQSPI_STATE_BUSY_INDIRECT_TX
@ HAL_XQSPI_STATE_BUSY_INDIRECT_TX
Definition: gr55xx_hal_xqspi.h:80
_xqspi_command_t::inst_addr_mode
uint32_t inst_addr_mode
Definition: gr55xx_hal_xqspi.h:182
_xqspi_command_t::addr_size
uint32_t addr_size
Definition: gr55xx_hal_xqspi.h:176
hal_xqspi_get_rx_fifo_threshold
uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the RXFIFO threshold.
HAL_XQSPI_STATE_RESET
@ HAL_XQSPI_STATE_RESET
Definition: gr55xx_hal_xqspi.h:77
hal_xqspi_receive
hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Receive an amount of data in blocking mode.
hal_xqspi_get_state
hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi)
Return the XQSPI handle state.
hal_xqspi_get_error
uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi)
Return the XQSPI error code.
_xqspi_command_t
XQSPI command Structure definition.
Definition: gr55xx_hal_xqspi.h:166
hal_xqspi_state_t
hal_xqspi_state_t
HAL XQSPI State Enumerations definition.
Definition: gr55xx_hal_xqspi.h:76
_xqspi_init_t::work_mode
uint32_t work_mode
Definition: gr55xx_hal_xqspi.h:104
_xqspi_command_t::addr
uint32_t addr
Definition: gr55xx_hal_xqspi.h:170
_xqspi_handle_t::retry
uint32_t retry
Definition: gr55xx_hal_xqspi.h:153
HAL_XQSPI_STATE_READY
@ HAL_XQSPI_STATE_READY
Definition: gr55xx_hal_xqspi.h:78
_xqspi_init_t::clock_mode
uint32_t clock_mode
Definition: gr55xx_hal_xqspi.h:116
_xqspi_handle_t::p_rx_buffer
uint8_t * p_rx_buffer
Definition: gr55xx_hal_xqspi.h:141
HAL_XQSPI_STATE_BUSY
@ HAL_XQSPI_STATE_BUSY
Definition: gr55xx_hal_xqspi.h:79
_xqspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr55xx_hal_xqspi.h:113
_xqspi_handle_t::init
xqspi_init_t init
Definition: gr55xx_hal_xqspi.h:133
_xqspi_handle_t::rx_xfer_count
__IO uint32_t rx_xfer_count
Definition: gr55xx_hal_xqspi.h:145
hal_xqspi_set_xip_present_status
void hal_xqspi_set_xip_present_status(xqspi_handle_t *p_xqspi, uint32_t status)
Turn on/off present module, only in XIP mode.
_hal_xqspi_callback
HAL_XQSPI Callback function definition.
Definition: gr55xx_hal_xqspi.h:210
_xqspi_init_t::read_cmd
uint32_t read_cmd
Definition: gr55xx_hal_xqspi.h:110
xqspi_handle_t
struct _xqspi_handle_t xqspi_handle_t
XQSPI handle Structure definition.
hal_xqspi_set_retry
void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry)
Set the XQSPI internal process repeat times value.
xqspi_command_t
struct _xqspi_command_t xqspi_command_t
XQSPI command Structure definition.
_xqspi_handle_t
XQSPI handle Structure definition.
Definition: gr55xx_hal_xqspi.h:130
hal_xqspi_set_rx_fifo_threshold
hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the RXFIFO threshold.
_xqspi_handle_t::p_instance
xqspi_regs_t * p_instance
Definition: gr55xx_hal_xqspi.h:131
hal_xqspi_transmit
hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Transmit an amount of data in blocking mode.
HAL_XQSPI_STATE_ABORT
@ HAL_XQSPI_STATE_ABORT
Definition: gr55xx_hal_xqspi.h:82
_xqspi_command_t::length
uint32_t length
Definition: gr55xx_hal_xqspi.h:188
hal_xqspi_msp_deinit
void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI MSP.
hal_xqspi_command_transmit
hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Transmit an amount of data with specified instruction and address in blocking mode.
_xqspi_init_t
XQSPI init Structure definition.
Definition: gr55xx_hal_xqspi.h:103
_xqspi_handle_t::p_tx_buffer
uint8_t * p_tx_buffer
Definition: gr55xx_hal_xqspi.h:135
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
_xqspi_handle_t::rx_xfer_size
__IO uint32_t rx_xfer_size
Definition: gr55xx_hal_xqspi.h:143
_xqspi_command_t::data_mode
uint32_t data_mode
Definition: gr55xx_hal_xqspi.h:185
HAL_XQSPI_STATE_BUSY_INDIRECT_RX
@ HAL_XQSPI_STATE_BUSY_INDIRECT_RX
Definition: gr55xx_hal_xqspi.h:81
hal_xqspi_init
hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI according to the specified parameters in the xqspi_init_t and initialize the ass...
hal_xqspi_get_tx_fifo_threshold
uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the TXFIFO threshold.
gr55xx_ll_xqspi.h
Header file containing functions prototypes of XQSPI LL library.
_xqspi_handle_t::lock
__IO hal_lock_t lock
Definition: gr55xx_hal_xqspi.h:147
HAL_XQSPI_STATE_ERROR
@ HAL_XQSPI_STATE_ERROR
Definition: gr55xx_hal_xqspi.h:83
hal_xqspi_callback_t
struct _hal_xqspi_callback hal_xqspi_callback_t
HAL_XQSPI Callback function definition.
_xqspi_handle_t::state
__IO hal_xqspi_state_t state
Definition: gr55xx_hal_xqspi.h:149
_xqspi_handle_t::error_code
__IO uint32_t error_code
Definition: gr55xx_hal_xqspi.h:151
hal_xqspi_command_receive
hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Receive an amount of data with specified instruction and address in blocking mode.
_xqspi_command_t::inst
uint32_t inst
Definition: gr55xx_hal_xqspi.h:167
xqspi_init_t
struct _xqspi_init_t xqspi_init_t
XQSPI init Structure definition.
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
_xqspi_handle_t::tx_xfer_size
__IO uint32_t tx_xfer_size
Definition: gr55xx_hal_xqspi.h:137
_xqspi_command_t::dummy_cycles
uint32_t dummy_cycles
Definition: gr55xx_hal_xqspi.h:179
hal_xqspi_set_tx_fifo_threshold
hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the TXFIFO threshold.
_hal_xqspi_callback::xqspi_msp_deinit
void(* xqspi_msp_deinit)(xqspi_handle_t *p_xqspi)
Definition: gr55xx_hal_xqspi.h:212