gr55xx_ll_i2s.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2S_M) || defined (I2S_S)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_i2s_init_t
77 {
78 uint32_t rxdata_size;
83 uint32_t txdata_size;
88 uint32_t rx_threshold;
93 uint32_t tx_threshold;
98 uint32_t clock_source;
103 uint32_t audio_freq;
107 } ll_i2s_init_t;
108
118 /* Exported constants --------------------------------------------------------*/
127 #define LL_I2S_STATUS_TXFO I2S_INTSTAT_TXFO
128 #define LL_I2S_STATUS_TXFE I2S_INTSTAT_TXFE
129 #define LL_I2S_STATUS_RXFO I2S_INTSTAT_RXFO
130 #define LL_I2S_STATUS_RXDA I2S_INTSTAT_RXDA
137 #define LL_I2S_INT_TXFO I2S_INTMASK_TXFO
138 #define LL_I2S_INT_TXFE I2S_INTMASK_TXFE
139 #define LL_I2S_INT_RXFO I2S_INTMASK_RXFO
140 #define LL_I2S_INT_RXDA I2S_INTMASK_RXDA
146 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL)
147 #define LL_I2S_CLOCK_SRC_32M (1UL << 18)
153 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL)
154 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RXSIZE_WLEN_Pos)
155 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RXSIZE_WLEN_Pos)
156 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RXSIZE_WLEN_Pos)
157 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RXSIZE_WLEN_Pos)
158 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RXSIZE_WLEN_Pos)
164 #define LL_I2S_SIMPLEX_TX (1UL)
165 #define LL_I2S_SIMPLEX_RX (2UL)
166 #define LL_I2S_FULL_DUPLEX (3UL)
172 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL)
173 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RXFIFO_TL_Pos)
174 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RXFIFO_TL_Pos)
175 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RXFIFO_TL_Pos)
176 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RXFIFO_TL_Pos)
177 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RXFIFO_TL_Pos)
178 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RXFIFO_TL_Pos)
179 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RXFIFO_TL_Pos)
180 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RXFIFO_TL_Pos)
181 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RXFIFO_TL_Pos)
182 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RXFIFO_TL_Pos)
183 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RXFIFO_TL_Pos)
184 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RXFIFO_TL_Pos)
185 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RXFIFO_TL_Pos)
186 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RXFIFO_TL_Pos)
187 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RXFIFO_TL_Pos)
193 #define LL_I2S_WS_CYCLES_16 (0x00000000UL)
194 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_CLKCONFIG_WSS_Pos)
195 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_CLKCONFIG_WSS_Pos)
201 #define LL_I2S_SCLKG_NONE (0x00000000UL)
202 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_CLKCONFIG_SCLKG_Pos)
203 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_CLKCONFIG_SCLKG_Pos)
204 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_CLKCONFIG_SCLKG_Pos)
205 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_CLKCONFIG_SCLKG_Pos)
211 #define LL_I2S_RESOLUTION_12BIT (0UL)
212 #define LL_I2S_RESOLUTION_16BIT (1UL)
213 #define LL_I2S_RESOLUTION_20BIT (2UL)
214 #define LL_I2S_RESOLUTION_24BIT (3UL)
215 #define LL_I2S_RESOLUTION_32BIT (4UL)
221 #define LL_I2S_CHANNEL_NUM_1 (0UL)
222 #define LL_I2S_CHANNEL_NUM_2 (1UL)
223 #define LL_I2S_CHANNEL_NUM_3 (2UL)
224 #define LL_I2S_CHANNEL_NUM_4 (3UL)
230 #define LL_I2S_FIFO_DEPTH_2 (0UL)
231 #define LL_I2S_FIFO_DEPTH_4 (1UL)
232 #define LL_I2S_FIFO_DEPTH_8 (2UL)
233 #define LL_I2S_FIFO_DEPTH_16 (3UL)
239 #define LL_I2S_APB_WIDTH_8BIT (0UL)
240 #define LL_I2S_APB_WIDTH_16BIT (1UL)
241 #define LL_I2S_APB_WIDTH_32BIT (2UL)
253 #define LL_I2S_DEFAULT_CONFIG \
254 { \
255 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
256 .txdata_size = LL_I2S_DATASIZE_16BIT, \
257 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
258 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
259 .clock_source = LL_I2S_CLOCK_SRC_32M, \
260 .audio_freq = 48000 \
261 }
262
265 /* Exported macro ------------------------------------------------------------*/
281 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
282
289 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
290
296 /* Exported functions --------------------------------------------------------*/
315 __STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
316 {
317 SET_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
318 }
319
330 __STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
331 {
332 CLEAR_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
333 }
334
345 __STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
346 {
347 return (READ_BITS(I2Sx->ENABLE, I2S_ENABLE_EN) == (I2S_ENABLE_EN));
348 }
349
360 __STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
361 {
362 SET_BITS(I2Sx->RBEN, I2S_RBEN_EN);
363 }
364
375 __STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
376 {
377 CLEAR_BITS(I2Sx->RBEN, I2S_RBEN_EN);
378 }
379
390 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
391 {
392 return (READ_BITS(I2Sx->RBEN, I2S_RBEN_EN) == (I2S_RBEN_EN));
393 }
394
405 __STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
406 {
407 SET_BITS(I2Sx->TBEN, I2S_TBEN_EN);
408 }
409
420 __STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
421 {
422 CLEAR_BITS(I2Sx->TBEN, I2S_TBEN_EN);
423 }
424
435 __STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
436 {
437 return (READ_BITS(I2Sx->TBEN, I2S_TBEN_EN) == (I2S_TBEN_EN));
438 }
439
450 __STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
451 {
452 SET_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
453 }
454
465 __STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
466 {
467 CLEAR_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
468 }
469
480 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
481 {
482 return (READ_BITS(I2Sx->CLKEN, I2S_CLKEN_EN) == (I2S_CLKEN_EN));
483 }
484
500 __STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
501 {
502 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS, cycles);
503 }
504
518 __STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
519 {
520 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS));
521 }
522
539 __STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
540 {
541 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG, cycles);
542 }
543
559 __STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
560 {
561 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG));
562 }
563
574 __STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
575 {
576 WRITE_REG(I2Sx->RXFIFO_RST, I2S_RXFIFO_RST);
577 }
578
589 __STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
590 {
591 WRITE_REG(I2Sx->TXFIFO_RST, I2S_TXFIFO_RST);
592 }
593
604 __STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
605 {
606 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
607 }
608
618 __STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
619 {
620 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
621 }
622
632 __STATIC_INLINE void ll_i2s_enable_clock_div(void)
633 {
634 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
635 }
636
646 __STATIC_INLINE void ll_i2s_disable_clock_div(void)
647 {
648 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
649 }
650
660 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
661 {
662 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
663 }
664
677 __STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
678 {
679 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
680 }
681
693 __STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
694 {
695 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
696 }
697
715 __STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
716 {
717 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_L));
718 }
719
731 __STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
732 {
733 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_R));
734 }
735
748 __STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
749 {
750 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_L, data);
751 }
752
765 __STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
766 {
767 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_R, data);
768 }
769
781 __STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
782 {
783 SET_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
784 }
785
797 __STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
798 {
799 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
800 }
801
813 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
814 {
815 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN) != (I2S_RXEN_EN));
816 }
817
829 __STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
830 {
831 SET_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
832 }
833
845 __STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
846 {
847 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
848 }
849
861 __STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
862 {
863 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN) != (I2S_TXEN_EN));
864 }
865
885 __STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
886 {
887 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN, size);
888 }
889
907 __STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
908 {
909 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN));
910 }
911
931 __STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
932 {
933 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN, size);
934 }
935
953 __STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
954 {
955 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN));
956 }
957
976 __STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
977 {
978 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, I2S_INTSTAT_TXFO | I2S_INTSTAT_TXFE | \
979 I2S_INTSTAT_RXFO | I2S_INTSTAT_RXDA));
980 }
981
1001 __STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
1002 {
1003 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, flag) == flag);
1004 }
1005
1025 __STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1026 {
1027 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1028 }
1029
1049 __STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1050 {
1051 SET_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1052 }
1053
1073 __STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1074 {
1075 return ((READ_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask) ^ (mask)) == (mask));
1076 }
1077
1089 __STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
1090 {
1091 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXOVR, I2S_RXOVR_RXCHO));
1092 }
1093
1105 __STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
1106 {
1107 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXOVR, I2S_TXOVR_TXCHO));
1108 }
1109
1138 __STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1139 {
1140 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, threshold);
1141 }
1142
1170 __STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1171 {
1172 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, I2S_RXFIFO_TL));
1173 }
1174
1203 __STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1204 {
1205 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, threshold);
1206 }
1207
1235 __STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1236 {
1237 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, I2S_TXFIFO_TL));
1238 }
1239
1251 __STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1252 {
1253 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_FLUSH, I2S_RXFIFO_FLUSH);
1254 }
1255
1267 __STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1268 {
1269 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_FLUSH, I2S_TXFIFO_FLUSH);
1270 }
1271
1289 __STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
1290 {
1291 WRITE_REG(I2Sx->RXDMA_RST, I2S_RXDMA_RST);
1292 }
1293
1305 __STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
1306 {
1307 WRITE_REG(I2Sx->TXDMA_RST, I2S_TXDMA_RST);
1308 }
1309
1310
1322 __STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
1323 {
1324 if (I2S_M == I2Sx)
1325 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1326 else
1327 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1328 }
1329
1341 __STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
1342 {
1343 if (I2S_M == I2Sx)
1344 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1345 else
1346 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1347 }
1348
1360 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
1361 {
1362 if (I2S_M == I2Sx)
1363 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM) == MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1364 else
1365 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS) == MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1366 }
1367
1368
1394 __STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1395 {
1396 uint32_t pos[4] = {I2S_PARAM2_RXSIZE_0_Pos, I2S_PARAM2_RXSIZE_1_Pos, \
1397 I2S_PARAM2_RXSIZE_2_Pos, I2S_PARAM2_RXSIZE_3_Pos
1398 };
1399 uint32_t mask[4] = {I2S_PARAM2_RXSIZE_0, I2S_PARAM2_RXSIZE_1, I2S_PARAM2_RXSIZE_2, I2S_PARAM2_RXSIZE_3};
1400
1401 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM2, mask[channel]) >> pos[channel]);
1402 }
1403
1423 __STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1424 {
1425 uint32_t pos[4] = {I2S_PARAM1_TXSIZE_0_Pos, I2S_PARAM1_TXSIZE_1_Pos, \
1426 I2S_PARAM1_TXSIZE_2_Pos, I2S_PARAM1_TXSIZE_3_Pos
1427 };
1428 uint32_t mask[4] = {I2S_PARAM1_TXSIZE_0, I2S_PARAM1_TXSIZE_1, I2S_PARAM1_TXSIZE_2, I2S_PARAM1_TXSIZE_3};
1429
1430 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, mask[channel]) >> pos[channel]);
1431 }
1432
1447 __STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
1448 {
1449 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXCHN) >> I2S_PARAM1_TXCHN_Pos);
1450 }
1451
1466 __STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
1467 {
1468 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXCHN) >> I2S_PARAM1_RXCHN_Pos);
1469 }
1470
1481 __STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
1482 {
1483 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXBLOCK) == I2S_PARAM1_RXBLOCK);
1484 }
1485
1496 __STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
1497 {
1498 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXBLOCK) == I2S_PARAM1_TXBLOCK);
1499 }
1500
1511 __STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
1512 {
1513 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_MODE) == I2S_PARAM1_MODE);
1514 }
1515
1530 __STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
1531 {
1532 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_FIFO_DEPTH) >> I2S_PARAM1_FIFO_DEPTH_Pos);
1533 }
1534
1548 __STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
1549 {
1550 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_APB_DATA_WIDTH) >> I2S_PARAM1_APB_DATA_WIDTH_Pos);
1551 }
1552
1563 __STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
1564 {
1565 return (uint32_t)(READ_REG(I2Sx->I2S_VERSION));
1566 }
1567
1578 __STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
1579 {
1580 return (uint32_t)(READ_REG(I2Sx->I2S_TYPE));
1581 }
1582
1596 error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx);
1597
1608 error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init);
1609
1616 void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init);
1617
1622 #endif /* I2S_M || I2S_S */
1623
1624 #ifdef __cplusplus
1625 }
1626 #endif
1627
1628 #endif /* __GR55xx_LL_I2S_H__ */
1629
ll_i2s_enable_clock
__STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
Enable I2S clock.
Definition: gr55xx_ll_i2s.h:450
ll_i2s_receive_rdata
__STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from right RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:731
ll_i2s_enable
__STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
Enable I2S.
Definition: gr55xx_ll_i2s.h:315
ll_i2s_get_wss
__STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
Get word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:518
ll_i2s_get_rx_block
__STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the receiver block is enabled or not.
Definition: gr55xx_ll_i2s.h:1481
ll_i2s_is_enabled_clock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
Check if I2S clock is enabled.
Definition: gr55xx_ll_i2s.h:480
ll_i2s_disable_txblock
__STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
Disable I2S TX block.
Definition: gr55xx_ll_i2s.h:420
ll_i2s_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1203
ll_i2s_get_rx_channels
__STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of rx channels.
Definition: gr55xx_ll_i2s.h:1466
ll_i2s_struct_init
void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init)
Set each field of a ll_i2s_init_t type structure to default value.
ll_i2s_clr_rxfifo_all
__STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
Clear I2S RX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:574
ll_i2s_clr_txfifo_all
__STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
Clear I2S TX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:589
ll_i2s_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1170
ll_i2s_clear_it_txovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1105
ll_i2s_transmit_ldata
__STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to left TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:748
ll_i2s_set_rxsize
__STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set receive data width in a channel.
Definition: gr55xx_ll_i2s.h:885
ll_i2s_disable_tx
__STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Disable TX in a channel.
Definition: gr55xx_ll_i2s.h:845
ll_i2s_disable_dma
__STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
Disable I2S DMA.
Definition: gr55xx_ll_i2s.h:1341
_ll_i2s_init_t::tx_threshold
uint32_t tx_threshold
Definition: gr55xx_ll_i2s.h:93
ll_i2s_set_wss
__STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
Set word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:500
ll_i2s_set_txsize
__STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:931
_ll_i2s_init_t::clock_source
uint32_t clock_source
Definition: gr55xx_ll_i2s.h:98
ll_i2s_enable_dma
__STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
Enable I2S DMA.
Definition: gr55xx_ll_i2s.h:1322
ll_i2s_get_tx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: tx resolution.
Definition: gr55xx_ll_i2s.h:1423
ll_i2s_rst_rxdma
__STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
Reset RX block DMA.
Definition: gr55xx_ll_i2s.h:1289
ll_i2s_clear_it_rxovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1089
_ll_i2s_init_t::rx_threshold
uint32_t rx_threshold
Definition: gr55xx_ll_i2s.h:88
ll_i2s_set_clock_src
__STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
Set I2S clock source.
Definition: gr55xx_ll_i2s.h:677
ll_i2s_is_enabled_rx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
Check if RX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:813
ll_i2s_disable_it
__STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Disable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1049
_ll_i2s_init_t::rxdata_size
uint32_t rxdata_size
Definition: gr55xx_ll_i2s.h:78
_ll_i2s_init_t::txdata_size
uint32_t txdata_size
Definition: gr55xx_ll_i2s.h:83
ll_i2s_is_enabled_clock_div
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
Check if I2S clock divider is enabled.
Definition: gr55xx_ll_i2s.h:660
ll_i2s_enable_rxblock
__STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
Enable I2S RX block.
Definition: gr55xx_ll_i2s.h:360
ll_i2s_get_rxsize
__STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
Get receive data width in a channel.
Definition: gr55xx_ll_i2s.h:907
ll_i2s_enable_txblock
__STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
Enable I2S TX block.
Definition: gr55xx_ll_i2s.h:405
_ll_i2s_init_t::audio_freq
uint32_t audio_freq
Definition: gr55xx_ll_i2s.h:103
ll_i2s_get_clock_src
__STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
Get I2S clock source.
Definition: gr55xx_ll_i2s.h:693
ll_i2s_get_sclkg
__STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
Get the gating of sclk.
Definition: gr55xx_ll_i2s.h:559
ll_i2s_get_apb_width
__STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
Get I2S component paramenters: APB data width.
Definition: gr55xx_ll_i2s.h:1548
ll_i2s_get_master_mode
__STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the master mode is enabled or not.
Definition: gr55xx_ll_i2s.h:1511
ll_i2s_init
error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init)
Initialize I2S_M registers according to the specified parameters in p_i2s_init.
ll_i2s_transmit_rdata
__STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to right TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:765
ll_i2s_disable_rxblock
__STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
Disable I2S RX block.
Definition: gr55xx_ll_i2s.h:375
ll_i2s_is_enabled
__STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
Check if I2S is enabled.
Definition: gr55xx_ll_i2s.h:345
ll_i2s_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1235
ll_i2s_enable_it
__STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Enable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1025
ll_i2s_get_tx_channels
__STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of tx channels.
Definition: gr55xx_ll_i2s.h:1447
ll_i2s_rst_txdma
__STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
Reset TX block DMA.
Definition: gr55xx_ll_i2s.h:1305
ll_i2s_is_enabled_rxblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
Check if I2S RX block is enabled.
Definition: gr55xx_ll_i2s.h:390
ll_i2s_enable_clock_div
__STATIC_INLINE void ll_i2s_enable_clock_div(void)
Enable I2S clock divider.
Definition: gr55xx_ll_i2s.h:632
ll_i2s_set_sclkg
__STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
Set the gating of sclk.
Definition: gr55xx_ll_i2s.h:539
ll_i2s_get_type
__STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
Get I2S component type.
Definition: gr55xx_ll_i2s.h:1578
ll_i2s_get_it_flag
__STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
Get interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:976
ll_i2s_get_version
__STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
Get I2S component version.
Definition: gr55xx_ll_i2s.h:1563
ll_i2s_is_active_it_flag
__STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
Check interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1001
ll_i2s_init_t
struct _ll_i2s_init_t ll_i2s_init_t
LL I2S init structures definition.
ll_i2s_is_enabled_txblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
Check if I2S TX block is enabled.
Definition: gr55xx_ll_i2s.h:435
ll_i2s_disable_rx
__STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Disable RX in a channel.
Definition: gr55xx_ll_i2s.h:797
ll_i2s_enable_tx
__STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Enable TX in a channel.
Definition: gr55xx_ll_i2s.h:829
ll_i2s_is_enabled_dma
__STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
Check if I2S DMA is enabled.
Definition: gr55xx_ll_i2s.h:1360
ll_i2s_get_rx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: rx resolution.
Definition: gr55xx_ll_i2s.h:1394
ll_i2s_get_fifo_depth
__STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
Get I2S component paramenters: FIOF depth.
Definition: gr55xx_ll_i2s.h:1530
ll_i2s_set_clock_div
__STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
Set I2S clock divider.
Definition: gr55xx_ll_i2s.h:604
ll_i2s_clr_txfifo_channel
__STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1267
ll_i2s_receive_ldata
__STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from left RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:715
ll_i2s_disable_clock
__STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
Disable I2S clock.
Definition: gr55xx_ll_i2s.h:465
ll_i2s_is_enabled_it
__STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Check if interrupt in a channel is enabled.
Definition: gr55xx_ll_i2s.h:1073
ll_i2s_enable_rx
__STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Enable RX in a channel.
Definition: gr55xx_ll_i2s.h:781
ll_i2s_is_enabled_tx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
Check if TX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:861
ll_i2s_get_tx_block
__STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the transmitter block is enabled or not.
Definition: gr55xx_ll_i2s.h:1496
ll_i2s_get_clock_div
__STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
Get I2S clock divider.
Definition: gr55xx_ll_i2s.h:618
ll_i2s_get_txsize
__STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
Get transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:953
ll_i2s_clr_rxfifo_channel
__STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1251
_ll_i2s_init_t
LL I2S init structures definition.
Definition: gr55xx_ll_i2s.h:77
ll_i2s_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1138
ll_i2s_deinit
error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx)
De-initialize I2S registers (Registers restored to their default values).
ll_i2s_disable_clock_div
__STATIC_INLINE void ll_i2s_disable_clock_div(void)
Disable I2S clock divider.
Definition: gr55xx_ll_i2s.h:646
ll_i2s_disable
__STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
Disable I2S.
Definition: gr55xx_ll_i2s.h:330