gr55xx_hal_i2s.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_I2S_H__
53 #define __GR55xx_HAL_I2S_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_i2s.h"
61 #include "gr55xx_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
75 typedef enum
76 {
77 HAL_I2S_STATE_RESET = 0x00,
78 HAL_I2S_STATE_READY = 0x01,
79 HAL_I2S_STATE_BUSY = 0x02,
80 HAL_I2S_STATE_BUSY_TX = 0x12,
81 HAL_I2S_STATE_BUSY_RX = 0x22,
82 HAL_I2S_STATE_BUSY_TX_RX = 0x32,
83 HAL_I2S_STATE_ABORT = 0x08,
84 HAL_I2S_STATE_ERROR = 0x04
86 } hal_i2s_state_t;
87
103 typedef struct _i2s_init
104 {
105 uint32_t data_size;
108 uint32_t clock_source;
111 uint32_t audio_freq;
114 #if I2S_CHANNEL_NUM > 1
115 uint32_t channel_active;
117 #endif
118
119 } i2s_init_t;
129 typedef struct _i2s_handle
130 {
131 i2s_regs_t *p_instance;
133 i2s_init_t init;
135 uint16_t *p_tx_buffer;
137 __IO uint32_t tx_xfer_size;
139 __IO uint32_t tx_xfer_count;
141 uint16_t *p_rx_buffer;
143 __IO uint32_t rx_xfer_size;
145 __IO uint32_t rx_xfer_count;
147 void (*write_fifo)(struct _i2s_handle *p_i2s);
149 void (*read_fifo)(struct _i2s_handle *p_i2s);
151 dma_handle_t *p_dmatx;
153 dma_handle_t *p_dmarx;
155 __IO hal_lock_t lock;
157 __IO hal_i2s_state_t state;
159 __IO uint32_t error_code;
161 uint32_t timeout;
163 uint32_t retention[7];
164 } i2s_handle_t;
181 typedef struct _hal_i2s_callback
182 {
183 void (*i2s_msp_init)(i2s_handle_t *p_i2s);
184 void (*i2s_msp_deinit)(i2s_handle_t *p_i2s);
185 void (*i2s_error_callback)(i2s_handle_t *p_i2s);
186 void (*i2s_rx_cplt_callback)(i2s_handle_t *p_i2s);
187 void (*i2s_tx_cplt_callback)(i2s_handle_t *p_i2s);
188 void (*i2s_tx_rx_cplt_callback)(i2s_handle_t *p_i2s);
189 } hal_i2s_callback_t;
190
200 /* Exported constants --------------------------------------------------------*/
208 #define I2S_DIRECTION_FULL_DUPLEX LL_I2S_FULL_DUPLEX
209 #define I2S_DIRECTION_SIMPLEX_TX LL_I2S_SIMPLEX_TX
210 #define I2S_DIRECTION_SIMPLEX_RX LL_I2S_SIMPLEX_RX
216 #define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000)
217 #define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001)
218 #define HAL_I2S_ERROR_TRANSFER ((uint32_t)0x00000002)
219 #define HAL_I2S_ERROR_DMA ((uint32_t)0x00000004)
220 #define HAL_I2S_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
226 #define I2S_DATASIZE_12BIT LL_I2S_DATASIZE_12BIT
227 #define I2S_DATASIZE_16BIT LL_I2S_DATASIZE_16BIT
228 #define I2S_DATASIZE_20BIT LL_I2S_DATASIZE_20BIT
229 #define I2S_DATASIZE_24BIT LL_I2S_DATASIZE_24BIT
230 #define I2S_DATASIZE_32BIT LL_I2S_DATASIZE_32BIT
236 #define I2S_CLOCK_SRC_96M LL_I2S_CLOCK_SRC_96M
237 #define I2S_CLOCK_SRC_32M LL_I2S_CLOCK_SRC_32M
243 #define I2S_TX_FIFO_LEVEL_MAX 16
244 #define I2S_RX_FIFO_LEVEL_MAX 16
250 #define I2S_FLAG_TXFO LL_I2S_STATUS_TXFO
251 #define I2S_FLAG_TXFE LL_I2S_STATUS_TXFE
252 #define I2S_FLAG_RXFO LL_I2S_STATUS_RXFO
253 #define I2S_FLAG_RXDA LL_I2S_STATUS_RXDA
259 #define I2S_IT_TXFO LL_I2S_INT_TXFO
260 #define I2S_IT_TXFE LL_I2S_INT_TXFE
261 #define I2S_IT_RXFO LL_I2S_INT_RXFO
262 #define I2S_IT_RXDA LL_I2S_INT_RXDA
268 #define HAL_I2S_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)
273 /* Exported macro ------------------------------------------------------------*/
274
282 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_I2S_STATE_RESET)
283
288 #define __HAL_I2S_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->ENABLE, I2S_ENABLE_EN)
289
294 #define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->ENABLE, I2S_ENABLE_EN)
295
300 #define __HAL_I2S_ENABLE_CLOCK(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CLKEN, I2S_CLKEN_EN)
301
306 #define __HAL_I2S_DISABLE_CLOCK(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CLKEN, I2S_CLKEN_EN)
307
312 #define __HAL_I2S_ENABLE_TX_BLOCK(__HANDLE__) ll_i2s_enable_txblock((__HANDLE__)->p_instance)
313
318 #define __HAL_I2S_DISABLE_TX_BLOCK(__HANDLE__) ll_i2s_disable_txblock((__HANDLE__)->p_instance)
319
324 #define __HAL_I2S_ENABLE_RX_BLOCK(__HANDLE__) ll_i2s_enable_rxblock((__HANDLE__)->p_instance)
325
330 #define __HAL_I2S_DISABLE_RX_BLOCK(__HANDLE__) ll_i2s_disable_rxblock((__HANDLE__)->p_instance)
331
337 #define __HAL_I2S_ENABLE_TX_CHANNEL(__HANDLE__, __CH__) ll_i2s_enable_tx((__HANDLE__)->p_instance, (__CH__))
338
344 #define __HAL_I2S_DISABLE_TX_CHANNEL(__HANDLE__, __CH__) ll_i2s_disable_tx((__HANDLE__)->p_instance, (__CH__))
345
351 #define __HAL_I2S_ENABLE_RX_CHANNEL(__HANDLE__, __CH__) ll_i2s_enable_rx((__HANDLE__)->p_instance, (__CH__))
352
358 #define __HAL_I2S_DISABLE_RX_CHANNEL(__HANDLE__, __CH__) ll_i2s_disable_rx((__HANDLE__)->p_instance, (__CH__))
359
364 #define __HAL_I2S_FLUSH_TX_FIFO(__HANDLE__) ll_i2s_clr_txfifo_all((__HANDLE__)->p_instance)
365
370 #define __HAL_I2S_FLUSH_RX_FIFO(__HANDLE__) ll_i2s_clr_rxfifo_all((__HANDLE__)->p_instance)
371
376 #define __HAL_I2S_ENABLE_DMA(__HANDLE__) ll_i2s_enable_dma(__HANDLE__->p_instance)
377
382 #define __HAL_I2S_DISABLE_DMA(__HANDLE__) ll_i2s_disable_dma(__HANDLE__->p_instance)
383
388 #define __HAL_I2S_RESET_TXDMA(__HANDLE__) WRITE_REG((__HANDLE__)->p_instance->TXDMA_RST, I2S_TXDMA_RST)
389
394 #define __HAL_I2S_RESET_RXDMA(__HANDLE__) WRITE_REG((__HANDLE__)->p_instance->RXDMA_RST, I2S_RXDMA_RST)
395
406 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTMASK, (__INTERRUPT__))
407
418 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTMASK, (__INTERRUPT__))
419
430 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTSTAT, (__FLAG__)) != 0) ? SET : RESET)
431
440 #define __HAL_I2S_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
441 if ((__FLAG__) & I2S_FLAG_RXFO) \
442 { \
443 READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].RXOVR, I2S_RXOVR_RXCHO);\
444 } \
445 if ((__FLAG__) & I2S_FLAG_TXFO) \
446 { \
447 READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].TXOVR, I2S_TXOVR_TXCHO);\
448 } \
449 } while(0);
450
453 /* Private macros ------------------------------------------------------------*/
462 #define IS_I2S_DIRECTION(__MODE__) (((__MODE__) == I2S_DIRECTION_FULL_DUPLEX) || \
463 ((__MODE__) == I2S_DIRECTION_SIMPLEX_TX) || \
464 ((__MODE__) == I2S_DIRECTION_SIMPLEX_RX))
465
470 #define IS_I2S_DATASIZE(__DATASIZE__) (((__DATASIZE__) == I2S_DATASIZE_12BIT) || \
471 ((__DATASIZE__) == I2S_DATASIZE_16BIT) || \
472 ((__DATASIZE__) == I2S_DATASIZE_20BIT) || \
473 ((__DATASIZE__) == I2S_DATASIZE_24BIT) || \
474 ((__DATASIZE__) == I2S_DATASIZE_32BIT))
475
480 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_POLARITY_LOW) || \
481 ((__CPOL__) == I2S_POLARITY_HIGH))
482
487 #define IS_I2S_AUDIO_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) > 0) && ((__FREQUENCY__) <= 1500000))
488
493 #define IS_I2S_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= I2S_TX_FIFO_LEVEL_MAX))
494
499 /* Exported functions --------------------------------------------------------*/
541 hal_status_t hal_i2s_init(i2s_handle_t *p_i2s);
542
553 hal_status_t hal_i2s_deinit(i2s_handle_t *p_i2s);
554
563 void hal_i2s_msp_init(i2s_handle_t *p_i2s);
564
573 void hal_i2s_msp_deinit(i2s_handle_t *p_i2s);
574
624 hal_status_t hal_i2s_transmit(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout);
625
640 hal_status_t hal_i2s_receive(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout);
641
656 hal_status_t hal_i2s_transmit_receive(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length, uint32_t timeout);
657
671 hal_status_t hal_i2s_transmit_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length);
672
686 hal_status_t hal_i2s_receive_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length);
687
701 hal_status_t hal_i2s_transmit_receive_it(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length);
702
716 hal_status_t hal_i2s_transmit_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length);
717
731 hal_status_t hal_i2s_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length);
732
746 hal_status_t hal_i2s_transmit_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length);
747
759 hal_status_t hal_i2s_start_clock(i2s_handle_t *p_i2s);
760
772 hal_status_t hal_i2s_stop_clock(i2s_handle_t *p_i2s);
773
792 hal_status_t hal_i2s_abort(i2s_handle_t *p_i2s);
793
807 void hal_i2s_irq_handler(i2s_handle_t *p_i2s);
808
815 void hal_i2s_tx_cplt_callback(i2s_handle_t *p_i2s);
816
823 void hal_i2s_rx_cplt_callback(i2s_handle_t *p_i2s);
824
831 void hal_i2s_tx_rx_cplt_callback(i2s_handle_t *p_i2s);
832
839 void hal_i2s_error_callback(i2s_handle_t *p_i2s);
840
876 hal_i2s_state_t hal_i2s_get_state(i2s_handle_t *p_i2s);
877
885 uint32_t hal_i2s_get_error(i2s_handle_t *p_i2s);
886
898 hal_status_t hal_i2s_set_tx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold);
899
911 hal_status_t hal_i2s_set_rx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold);
912
920 uint32_t hal_i2s_get_tx_fifo_threshold(i2s_handle_t *p_i2s);
921
929 uint32_t hal_i2s_get_rx_fifo_threshold(i2s_handle_t *p_i2s);
930
942 hal_status_t hal_i2s_suspend_reg(i2s_handle_t *p_i2s);
943
956 hal_status_t hal_i2s_resume_reg(i2s_handle_t *p_i2s);
957
958
963 #ifdef __cplusplus
964 }
965 #endif
966
967 #endif /* __GR55xx_HAL_I2S_H__ */
968
_i2s_init::data_size
uint32_t data_size
Definition: gr55xx_hal_i2s.h:105
HAL_I2S_STATE_BUSY_TX
@ HAL_I2S_STATE_BUSY_TX
Definition: gr55xx_hal_i2s.h:80
hal_i2s_init
hal_status_t hal_i2s_init(i2s_handle_t *p_i2s)
Initialize the I2S according to the specified parameters in the i2s_init_t and initialize the associa...
hal_i2s_receive_it
hal_status_t hal_i2s_receive_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode with Interrupt.
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
hal_i2s_deinit
hal_status_t hal_i2s_deinit(i2s_handle_t *p_i2s)
De-initialize the I2S peripheral.
_i2s_handle::p_rx_buffer
uint16_t * p_rx_buffer
Definition: gr55xx_hal_i2s.h:141
hal_i2s_transmit_receive_dma
hal_status_t hal_i2s_transmit_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length)
Transmit and Receive an amount of data in non-blocking mode with DMA.
hal_i2s_tx_cplt_callback
void hal_i2s_tx_cplt_callback(i2s_handle_t *p_i2s)
TX Transfer completed callback.
HAL_I2S_STATE_BUSY_RX
@ HAL_I2S_STATE_BUSY_RX
Definition: gr55xx_hal_i2s.h:81
hal_i2s_receive
hal_status_t hal_i2s_receive(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode.
_i2s_handle::write_fifo
void(* write_fifo)(struct _i2s_handle *p_i2s)
Definition: gr55xx_hal_i2s.h:147
HAL_I2S_STATE_ABORT
@ HAL_I2S_STATE_ABORT
Definition: gr55xx_hal_i2s.h:83
_i2s_handle::p_instance
i2s_regs_t * p_instance
Definition: gr55xx_hal_i2s.h:131
hal_i2s_error_callback
void hal_i2s_error_callback(i2s_handle_t *p_i2s)
I2S error callback.
_i2s_handle::read_fifo
void(* read_fifo)(struct _i2s_handle *p_i2s)
Definition: gr55xx_hal_i2s.h:149
hal_i2s_abort
hal_status_t hal_i2s_abort(i2s_handle_t *p_i2s)
Abort ongoing transfer (blocking mode).
i2s_init_t
struct _i2s_init i2s_init_t
I2S init Structure definition.
_i2s_handle::error_code
__IO uint32_t error_code
Definition: gr55xx_hal_i2s.h:159
_i2s_handle::p_tx_buffer
uint16_t * p_tx_buffer
Definition: gr55xx_hal_i2s.h:135
hal_i2s_receive_dma
hal_status_t hal_i2s_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode with DMA.
HAL_I2S_STATE_RESET
@ HAL_I2S_STATE_RESET
Definition: gr55xx_hal_i2s.h:77
_i2s_init::audio_freq
uint32_t audio_freq
Definition: gr55xx_hal_i2s.h:111
hal_i2s_transmit_receive_it
hal_status_t hal_i2s_transmit_receive_it(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
_hal_i2s_callback::i2s_tx_cplt_callback
void(* i2s_tx_cplt_callback)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:187
_hal_i2s_callback::i2s_msp_init
void(* i2s_msp_init)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:183
_hal_i2s_callback::i2s_msp_deinit
void(* i2s_msp_deinit)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:184
_i2s_handle::init
i2s_init_t init
Definition: gr55xx_hal_i2s.h:133
hal_i2s_tx_rx_cplt_callback
void hal_i2s_tx_rx_cplt_callback(i2s_handle_t *p_i2s)
TX/RX Transfer completed callback.
hal_i2s_transmit_it
hal_status_t hal_i2s_transmit_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode with Interrupt.
_i2s_handle::tx_xfer_count
__IO uint32_t tx_xfer_count
Definition: gr55xx_hal_i2s.h:139
HAL_I2S_STATE_READY
@ HAL_I2S_STATE_READY
Definition: gr55xx_hal_i2s.h:78
hal_i2s_rx_cplt_callback
void hal_i2s_rx_cplt_callback(i2s_handle_t *p_i2s)
RX Transfer completed callback.
hal_i2s_get_tx_fifo_threshold
uint32_t hal_i2s_get_tx_fifo_threshold(i2s_handle_t *p_i2s)
Get the TX FIFO threshold.
hal_i2s_transmit_dma
hal_status_t hal_i2s_transmit_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode with DMA.
_i2s_handle::timeout
uint32_t timeout
Definition: gr55xx_hal_i2s.h:161
_i2s_init::clock_source
uint32_t clock_source
Definition: gr55xx_hal_i2s.h:108
i2s_handle_t
struct _i2s_handle i2s_handle_t
I2S handle Structure definition.
hal_i2s_resume_reg
hal_status_t hal_i2s_resume_reg(i2s_handle_t *p_i2s)
Restore some registers related to I2S configuration after sleep. This function must be used in conjun...
_hal_i2s_callback::i2s_tx_rx_cplt_callback
void(* i2s_tx_rx_cplt_callback)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:188
HAL_I2S_STATE_BUSY
@ HAL_I2S_STATE_BUSY
Definition: gr55xx_hal_i2s.h:79
gr55xx_ll_i2s.h
Header file containing functions prototypes of I2S LL library.
hal_i2s_get_state
hal_i2s_state_t hal_i2s_get_state(i2s_handle_t *p_i2s)
Return the I2S handle state.
hal_i2s_get_rx_fifo_threshold
uint32_t hal_i2s_get_rx_fifo_threshold(i2s_handle_t *p_i2s)
Get the RX FIFO threshold.
_i2s_handle
I2S handle Structure definition.
Definition: gr55xx_hal_i2s.h:130
_i2s_handle::state
__IO hal_i2s_state_t state
Definition: gr55xx_hal_i2s.h:157
hal_i2s_start_clock
hal_status_t hal_i2s_start_clock(i2s_handle_t *p_i2s)
Start the I2S master clock.
_i2s_handle::tx_xfer_size
__IO uint32_t tx_xfer_size
Definition: gr55xx_hal_i2s.h:137
_i2s_handle::retention
uint32_t retention[7]
Definition: gr55xx_hal_i2s.h:163
_hal_i2s_callback::i2s_rx_cplt_callback
void(* i2s_rx_cplt_callback)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:186
hal_i2s_transmit_receive
hal_status_t hal_i2s_transmit_receive(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length, uint32_t timeout)
Transmit and Receive an amount of data in blocking mode.
_i2s_init
I2S init Structure definition.
Definition: gr55xx_hal_i2s.h:104
_hal_i2s_callback
HAL_I2S Callback function definition.
Definition: gr55xx_hal_i2s.h:182
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
_i2s_handle::lock
__IO hal_lock_t lock
Definition: gr55xx_hal_i2s.h:155
HAL_I2S_STATE_ERROR
@ HAL_I2S_STATE_ERROR
Definition: gr55xx_hal_i2s.h:84
HAL_I2S_STATE_BUSY_TX_RX
@ HAL_I2S_STATE_BUSY_TX_RX
Definition: gr55xx_hal_i2s.h:82
_i2s_handle::p_dmarx
dma_handle_t * p_dmarx
Definition: gr55xx_hal_i2s.h:153
_hal_i2s_callback::i2s_error_callback
void(* i2s_error_callback)(i2s_handle_t *p_i2s)
Definition: gr55xx_hal_i2s.h:185
hal_i2s_suspend_reg
hal_status_t hal_i2s_suspend_reg(i2s_handle_t *p_i2s)
Suspend some registers related to I2S configuration before sleep.
hal_i2s_transmit
hal_status_t hal_i2s_transmit(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode.
hal_i2s_callback_t
struct _hal_i2s_callback hal_i2s_callback_t
HAL_I2S Callback function definition.
hal_i2s_set_tx_fifo_threshold
hal_status_t hal_i2s_set_tx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold)
Set the TX FIFO threshold.
hal_i2s_get_error
uint32_t hal_i2s_get_error(i2s_handle_t *p_i2s)
Return the I2S error code.
hal_i2s_msp_init
void hal_i2s_msp_init(i2s_handle_t *p_i2s)
Initialize the I2S MSP.
_i2s_handle::rx_xfer_count
__IO uint32_t rx_xfer_count
Definition: gr55xx_hal_i2s.h:145
hal_i2s_irq_handler
void hal_i2s_irq_handler(i2s_handle_t *p_i2s)
Handle I2S interrupt request.
hal_i2s_state_t
hal_i2s_state_t
HAL I2S State Enumerations definition.
Definition: gr55xx_hal_i2s.h:76
hal_i2s_msp_deinit
void hal_i2s_msp_deinit(i2s_handle_t *p_i2s)
De-initialize the I2S MSP.
hal_i2s_stop_clock
hal_status_t hal_i2s_stop_clock(i2s_handle_t *p_i2s)
Stop the I2S master clock.
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:179
_i2s_handle::p_dmatx
dma_handle_t * p_dmatx
Definition: gr55xx_hal_i2s.h:151
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
_i2s_handle::rx_xfer_size
__IO uint32_t rx_xfer_size
Definition: gr55xx_hal_i2s.h:143
hal_i2s_set_rx_fifo_threshold
hal_status_t hal_i2s_set_rx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold)
Set the RX FIFO threshold.