gr55xx_ll_gpio.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPIO_H__
53 #define __GR55XX_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (GPIO0) || defined (GPIO1)
63
68 /* Exported types ------------------------------------------------------------*/
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin;
81 uint32_t mode;
86 uint32_t pull;
91 uint32_t mux;
97 uint32_t trigger;
100 } ll_gpio_init_t;
101
111 /* Exported constants --------------------------------------------------------*/
119 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U)
120 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U)
121 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U)
122 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U)
123 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U)
124 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U)
125 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U)
126 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U)
127 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U)
128 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U)
129 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U)
130 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U)
131 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U)
132 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U)
133 #define LL_GPIO_PIN_14 ((uint32_t)0x4000U)
134 #define LL_GPIO_PIN_15 ((uint32_t)0x8000U)
135 #define LL_GPIO_PIN_ALL ((uint32_t)0xFFFFU)
141 #define LL_GPIO_MODE_INPUT ((uint32_t)0x0U)
142 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x1U)
143 #define LL_GPIO_MODE_MUX ((uint32_t)0x2U)
149 #define LL_GPIO_PULL_NO LL_GPIO_RE_N
150 #define LL_GPIO_PULL_UP LL_GPIO_RTYP
151 #define LL_GPIO_PULL_DOWN ((uint32_t)0x0U)
157 #define LL_GPIO_MUX_0 ((uint32_t)0x0U)
158 #define LL_GPIO_MUX_1 ((uint32_t)0x1U)
159 #define LL_GPIO_MUX_2 ((uint32_t)0x2U)
160 #define LL_GPIO_MUX_3 ((uint32_t)0x3U)
161 #define LL_GPIO_MUX_4 ((uint32_t)0x4U)
162 #define LL_GPIO_MUX_5 ((uint32_t)0x5U)
163 #define LL_GPIO_MUX_6 ((uint32_t)0x6U)
164 #define LL_GPIO_MUX_7 ((uint32_t)0x7U)
165 #define LL_GPIO_MUX_8 ((uint32_t)0x8U)
171 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U)
172 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U)
173 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U)
174 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U)
175 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U)
185 #define LL_GPIO_DEFAULT_CONFIG \
186 { \
187 .pin = LL_GPIO_PIN_ALL, \
188 .mode = LL_GPIO_MODE_INPUT, \
189 .pull = LL_GPIO_PULL_DOWN, \
190 .mux = LL_GPIO_MUX_7, \
191 .trigger = LL_GPIO_TRIGGER_NONE, \
192 }
193
197 /* Exported macro ------------------------------------------------------------*/
213 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
214
221 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
222
227 /* Private types -------------------------------------------------------------*/
228 /* Private variables ---------------------------------------------------------*/
229 /* Private constants ---------------------------------------------------------*/
230 /* Private macros ------------------------------------------------------------*/
241 #define LL_GPIO_GET_RESISTOR_POS(__GPIOx__) (((__GPIOx__) == GPIO0) ? 0 : 16)
242
249 #define LL_GPIO_GET_REG_MUX_CTRL_0_7( __GPIOx__) \
250 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL0_7) : &(MCU_SUB->DPAD_MUX_CTL16_23))
251
258 #define LL_GPIO_GET_REG_MUX_CTRL_8_15( __GPIOx__) \
259 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL8_15) : &(MCU_SUB->DPAD_MUX_CTL24_31))
260
264 #define LL_GPIO_RE_N_Pos 0
265 #define LL_GPIO_RE_N_Msk (0x1U << LL_GPIO_RE_N_Pos)
266 #define LL_GPIO_RE_N LL_GPIO_RE_N_Msk
272 #define LL_GPIO_RTYP_Pos 1
273 #define LL_GPIO_RTYP_Msk (0x1U << LL_GPIO_RTYP_Pos)
274 #define LL_GPIO_RTYP LL_GPIO_RTYP_Msk
281 /* Exported functions --------------------------------------------------------*/
282
322 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
323 {
324 if (mode == LL_GPIO_MODE_OUTPUT)
325 {
326 WRITE_REG(GPIOx->OUTENSET, pin_mask);
327 }
328 else if(mode == LL_GPIO_MODE_INPUT)
329 {
330 WRITE_REG(GPIOx->OUTENCLR, pin_mask);
331 }
332 }
333
365 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
366 {
367 return (uint32_t)(READ_BITS(GPIOx->OUTENSET, pin) != RESET);
368 }
369
402 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
403 {
404 /* Get pin mask in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
405 pin_mask <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
406 MODIFY_REG(MCU_SUB->DPAD_RTYP_BUS, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
407 MODIFY_REG(MCU_SUB->DPAD_RE_N_BUS, pin_mask, (pull == LL_GPIO_PULL_NO) ? pin_mask : 0x0000U);
408 }
409
442 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
443 {
444 /* Get pin position in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
445 pin <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
446 return ((READ_BITS(MCU_SUB->DPAD_RE_N_BUS, pin) != RESET) ? LL_GPIO_PULL_NO :
447 ((READ_BITS(MCU_SUB->DPAD_RTYP_BUS, pin) != RESET) ? LL_GPIO_PULL_UP : LL_GPIO_PULL_DOWN));
448 }
449
482 __STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
483 {
484 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
485 uint32_t pos = POSITION_VAL(pin) << 2;
486 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
487 }
488
518 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
519 {
520 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
521 uint32_t pos = POSITION_VAL(pin) << 2;
522 return (READ_BITS(*pReg, 0xF << pos) >> pos);
523 }
524
557 __STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
558 {
559 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
560 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
561 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
562 }
563
594 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
595 {
596 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
597 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
598 return (READ_BITS(*pReg, 0xF << pos) >> pos);
599 }
600
617 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
618 {
619 return (uint32_t)(READ_REG(GPIOx->DATA));
620 }
621
650 __STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
651 {
652 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
653 }
654
666 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
667 {
668 WRITE_REG(GPIOx->DATAOUT, port_value);
669 }
670
681 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
682 {
683 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
684 }
685
714 __STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
715 {
716 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
717 }
718
747 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
748 {
749 #ifdef USE_GPIO_MASK_REGISTER
750 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
751 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
752 pin_mask & GPIO_MASKHIGHBYTE_DATA);
753 #else
754 SET_BITS(GPIOx->DATAOUT, pin_mask);
755 #endif
756 }
757
786 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
787 {
788 #ifdef USE_GPIO_MASK_REGISTER
789 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
790 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
791 #else
792 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
793 #endif
794 }
795
824 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
825 {
826 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
827 }
828
865 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
866 {
867 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
868 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
869 }
870
901 __STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
902 {
903 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
904 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
905 }
906
937 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
938 {
939 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
940 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
941 }
942
974 __STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
975 {
976 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
977 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
978 }
979
1010 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1011 {
1012 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1013 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1014 }
1015
1046 __STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1047 {
1048 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
1049 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1050 }
1051
1082 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1083 {
1084 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1085 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1086 }
1087
1118 __STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1119 {
1120 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
1121 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1122 }
1123
1153 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1154 {
1155 WRITE_REG(GPIOx->INTENSET, pin_mask);
1156 }
1157
1187 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1188 {
1189 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1190 }
1191
1220 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1221 {
1222 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1223 }
1224
1261 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1262 {
1263 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1264 }
1265
1296 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1297 {
1298 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1299 }
1300
1331 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1332 {
1333 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1334 }
1335
1349 error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx);
1350
1361 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1362
1369 void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init);
1370
1375 #endif /* defined (GPIO0) || defined (GPIO1) */
1376
1377 #ifdef __cplusplus
1378 }
1379 #endif
1380
1381 #endif /* __GR55xx_LL_GPIO_H__ */
1382
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:617
_ll_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_gpio.h:78
ll_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:518
ll_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if low level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1118
LL_GPIO_GET_RESISTOR_POS
#define LL_GPIO_GET_RESISTOR_POS(__GPIOx__)
Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
Definition: gr55xx_ll_gpio.h:241
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr55xx_ll_gpio.h:149
ll_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:714
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1010
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_gpio.h:1220
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr55xx_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
ll_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if rising edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:974
ll_gpio_set_mux_pin_8_15
__STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:557
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr55xx_ll_gpio.h:150
_ll_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_gpio.h:91
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_gpio.h:97
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:681
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:747
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:937
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1296
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1153
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:365
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:442
LL_GPIO_GET_REG_MUX_CTRL_0_7
#define LL_GPIO_GET_REG_MUX_CTRL_0_7(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:249
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:786
ll_gpio_deinit
error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr55xx_ll_gpio.h:151
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr55xx_ll_gpio.h:824
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr55xx_ll_gpio.h:666
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr55xx_ll_gpio.h:141
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1082
_ll_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_gpio.h:81
ll_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:482
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_gpio.h:142
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr55xx_ll_gpio.h:322
ll_gpio_get_mux_pin_8_15
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:594
ll_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:650
ll_gpio_struct_init
void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init)
Set each field of a ll_gpio_init_t type structure to default value.
_ll_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_gpio.h:86
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1261
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:865
ll_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if high level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1046
LL_GPIO_GET_REG_MUX_CTRL_8_15
#define LL_GPIO_GET_REG_MUX_CTRL_8_15(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:258
ll_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if falling edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:901
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1187
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:402
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1331