gr55xx_ll_efuse.h
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1
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_EFUSE_H__
53 #define __GR55xx_LL_EFUSE_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (EFUSE)
63
69 /* Exported constants --------------------------------------------------------*/
78 #define LL_EFUSE_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM
79 #define LL_EFUSE_READ_TRIM EFUSE_OPER_READ_TRIM
80 #define LL_EFUSE_CRC_CHECK EFUSE_OPER_CRC_CHECK
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK
82 #define LL_EFUSE_TEST_READ EFUSE_OPER_RD_TEST_MODE
89 #define LL_EFUSE_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY
90 #define LL_EFUSE_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE
91 #define LL_EFUSE_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE
92 #define LL_EFUSE_CRC_CHECK_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS
93 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE
94 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS
95 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE
96 #define LL_EFUSE_TEST_DONE EFUSE_STATUS_TEST_MODE_DONE
103 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE
104 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE
109 /* Exported macro ------------------------------------------------------------*/
110
125 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
126
133 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
134
141 /* Exported functions --------------------------------------------------------*/
161 __STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
162 {
163 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
164 }
165
176 __STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
177 {
178 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
179 }
180
191 __STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
192 {
193 SET_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
194 }
195
206 __STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
207 {
208 CLEAR_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
209 }
210
221 __STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
222 {
223 return (READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP) == (EFUSE_TPGM_MAIN_OR_BACKUP));
224 }
225
237 __STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
238 {
239 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN, length << EFUSE_TPGM_CRC_CHECK_LEN_Pos);
240 }
241
252 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
253 {
254 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN) >> EFUSE_TPGM_CRC_CHECK_LEN_Pos);
255 }
256
268 __STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
269 {
270 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
271 }
272
283 __STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
284 {
285 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
286 }
287
298 __STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
299 {
300 SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
301 }
302
313 __STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
314 {
315 CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
316 }
317
328 __STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
329 {
330 return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
331 }
332
344 __STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
345 {
346 return (uint32_t)(READ_BITS(EFUSEx->TEST_MODE, EFUSE_TEST_MODE));
347 }
348
369 __STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
370 {
371 WRITE_REG(EFUSEx->OPERATION, mode);
372 }
373
400 __STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
401 {
402 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
403 }
404
416 __STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
417 {
418 WRITE_REG(EFUSEx->KEY_MASK, mask);
419 }
420
431 __STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
432 {
433 return (uint32_t)(READ_REG(EFUSEx->KEY_MASK));
434 }
435
448 __STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
449 {
450 WRITE_REG(EFUSEx->CRC_ADDR, address);
451 }
452
463 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
464 {
465 return (uint32_t)(READ_REG(EFUSEx->CRC_ADDR));
466 }
467
478 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
479 {
480 return (uint32_t)(READ_REG(EFUSEx->CRC_OUTPUT));
481 }
482
495 __STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
496 {
497 WRITE_REG(EFUSEx->TRIM_ADDR, address);
498 }
499
510 __STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
511 {
512 return (uint32_t)(READ_REG(EFUSEx->TRIM_ADDR));
513 }
514
526 __STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
527 {
528 WRITE_REG(EFUSEx->TRIM_LEN, length & EFUSE_TRIM_LENGTH);
529 }
530
541 __STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
542 {
543 return (uint32_t)(READ_REG(EFUSEx->TRIM_LEN) & EFUSE_TRIM_LENGTH);
544 }
545
557 __STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
558 {
559 return (uint32_t)(READ_REG(EFUSEx->TRIM[indx]));
560 }
561
571 __STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
572 {
573 SET_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
574 }
575
585 __STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
586 {
587 CLEAR_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
588 }
589
601 __STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
602 {
603 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[0], vddq_0 + (vddq_1 << 16));
604 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[1], vddq_2);
605 }
606
617 __STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
618 {
619 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_BGN | MCU_SUB_EFUSE_PWR_CTL0_EN);
620 }
621
632 __STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
633 {
634 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_STP | MCU_SUB_EFUSE_PWR_CTL0_EN);
635 }
636
648 __STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
649 {
650 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], 0);
651 }
652
667 __STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
668 {
669 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL[1], flag) == (flag));
670 }
671
672
673
678 #endif /* EFUSE */
679
680 #ifdef __cplusplus
681 }
682 #endif
683
684 #endif /* __GR55xx_LL_EFUSE_H__ */
685
ll_efuse_disable_controller_power
__STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:648
ll_efuse_get_trim_value
__STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
Get trim value.
Definition: gr55xx_ll_efuse.h:557
ll_efuse_get_crc_check_addr
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
Get CRC check start address.
Definition: gr55xx_ll_efuse.h:463
ll_efuse_get_trim_addr
__STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
Get read trim start address.
Definition: gr55xx_ll_efuse.h:510
ll_efuse_enable_controller_power_begin
__STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:617
ll_efuse_set_crc_check_addr
__STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set CRC check start address.
Definition: gr55xx_ll_efuse.h:448
ll_efuse_get_test_mode
__STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
Get test mode.
Definition: gr55xx_ll_efuse.h:344
ll_efuse_set_trim_length
__STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
Set read trim length.
Definition: gr55xx_ll_efuse.h:526
ll_efuse_disable_main_backup
__STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
Disable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:206
ll_efuse_get_trim_length
__STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
Get read trim length.
Definition: gr55xx_ll_efuse.h:541
ll_efuse_set_key_mask
__STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
Set key mask.
Definition: gr55xx_ll_efuse.h:416
ll_efuse_disable_pgenb
__STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
Disable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:313
ll_efuse_is_enabled_main_backup
__STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
Check if read address through APB bus be a main address or backup address is enabled.
Definition: gr55xx_ll_efuse.h:221
ll_efuse_set_crc_check_len
__STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
Set CRC check length.
Definition: gr55xx_ll_efuse.h:237
ll_efuse_enable_power
__STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power on.
Definition: gr55xx_ll_efuse.h:571
ll_efuse_enable_controller_power_stop
__STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:632
ll_efuse_get_key_mask
__STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
Get key mask.
Definition: gr55xx_ll_efuse.h:431
ll_efuse_is_enabled_pgenb
__STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
Check if eFuse PGENB sigal is enabled.
Definition: gr55xx_ll_efuse.h:328
ll_efuse_get_interval
__STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
Get the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:283
ll_efuse_get_crc_check_result
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
Get CRC check results.
Definition: gr55xx_ll_efuse.h:478
ll_efuse_set_tpro
__STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
Set eFuse program time.
Definition: gr55xx_ll_efuse.h:161
ll_efuse_set_trim_addr
__STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set read trim start address.
Definition: gr55xx_ll_efuse.h:495
ll_efuse_is_active_flag
__STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_efuse.h:400
ll_efuse_set_operation
__STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
Set eFuse operation mode.
Definition: gr55xx_ll_efuse.h:369
ll_efuse_is_controller_power_flag
__STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check power controller active flag.
Definition: gr55xx_ll_efuse.h:667
ll_efuse_enable_main_backup
__STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
Enable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:191
ll_efuse_disable_power
__STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power off.
Definition: gr55xx_ll_efuse.h:585
ll_efuse_set_controller_power_timing
__STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
Set Efulse power controller timing pararmeter.
Definition: gr55xx_ll_efuse.h:601
ll_efuse_set_interval
__STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
Set the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:268
ll_efuse_enable_pgenb
__STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
Enable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:298
ll_efuse_get_crc_check_len
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
Get CRC check length.
Definition: gr55xx_ll_efuse.h:252
ll_efuse_get_tpro
__STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
Get eFuse program time.
Definition: gr55xx_ll_efuse.h:176