gr55xx_ll_uart.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (UART0) || defined (UART1)
63
64 /** @defgroup UART_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup UART_LL_ES_INIT UART Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL UART init Structure definition
75 */
76 typedef struct _ll_uart_init_t
77 {
78 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
79
80 This feature can be modified afterwards using unitary function @ref ll_uart_set_baud_rate().*/
81
82 uint32_t data_bits; /**< Specifies the number of data bits transmitted or received in a frame.
83 This parameter can be a value of @ref UART_LL_EC_DATABITS.
84
85 This feature can be modified afterwards using unitary function @ref ll_uart_set_data_bits_length().*/
86
87 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
88 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
89
90 This feature can be modified afterwards using unitary function @ref ll_uart_set_stop_bits_length().*/
91
92 uint32_t parity; /**< Specifies the parity mode.
93 This parameter can be a value of @ref UART_LL_EC_PARITY.
94
95 This feature can be modified afterwards using unitary function @ref ll_uart_set_parity().*/
96
97 uint32_t hw_flow_ctrl; /**< Specifies whether the hardware flow control mode is enabled or disabled.
98 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
99
100 This feature can be modified afterwards using unitary function @ref ll_uart_set_hw_flow_ctrl().*/
101 } ll_uart_init_t;
102
103 /** @} */
104
105 /** @} */
106
107 /**
108 * @defgroup UART_LL_MACRO Defines
109 * @{
110 */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
114 * @{
115 */
116
117 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
118 * @brief Flags definitions which can be used with LL_UART_ReadReg function
119 * @{
120 */
121 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
122 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
123 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
124 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
125 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register empty flag */
126 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
127 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
128
129 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
130 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
131 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
132 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
133 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
134 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
135
136 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
137 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
138 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
139 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
140 /** @} */
141
142 /** @defgroup UART_LL_EC_IT IT Defines
143 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
144 * @{
145 */
146 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status Interrupt */
147 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line Status Interrupt */
148 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding Register Empty Interrupt */
149 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available Interrupt and Character Timeout Interrupt */
150 /** @} */
151
152 /** @defgroup UART_LL_EC_PARITY Parity Control
153 * @{
154 */
155 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
156 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and Odd Parity is selected */
157 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and Even Parity is selected */
158 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and Stick Parity 0 is selected */
159 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and Stick Parity 1 is selected */
160 /** @} */
161
162 /** @defgroup UART_LL_EC_DATABITS Data Bits
163 * @{
164 */
165 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit, 5 data bits, n stop bits */
166 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit, 6 data bits, n stop bits */
167 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit, 7 data bits, n stop bits */
168 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit, 8 data bits, n stop bits */
169 /** @} */
170
171 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
172 * @{
173 */
174 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
175 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
176 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
177 /** @} */
178
179 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
180 * @{
181 */
182 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow control disabled */
183 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow control enabled */
184 /** @} */
185
186 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
187 * @{
188 */
189 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
190 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
191 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
192 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
193 /** @} */
194
195 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
196 * @{
197 */
198 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
199 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
200 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
201 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
202 /** @} */
203
204 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
205 * @{
206 */
207 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
208 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
209 /** @} */
210
211 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
212 * @{
213 */
214 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
215 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
216 /** @} */
217
218 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
219 * @{
220 */
221
222 /**
223 * @brief LL UART InitStrcut default configuartion
224 */
225 #define LL_UART_DEFAULT_CONFIG \
226 { \
227 .baud_rate = 9600U, \
228 .data_bits = LL_UART_DATABITS_8B, \
229 .stop_bits = LL_UART_STOPBITS_1, \
230 .parity = LL_UART_PARITY_NONE, \
231 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
232 }
233 /** @} */
234
235 /** @} */
236
237 /* Exported macro ------------------------------------------------------------*/
238 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
239 * @{
240 */
241
242 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
243 * @{
244 */
245
246 /**
247 * @brief Write a value in UART register
248 * @param __instance__ UART instance
249 * @param __REG__ Register to be written
250 * @param __VALUE__ Value to be written in the register
251 * @retval None
252 */
253 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
254
255 /**
256 * @brief Read a value in UART register
257 * @param __instance__ UART instance
258 * @param __REG__ Register to be read
259 * @retval Register value
260 */
261 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262
263 /** @} */
264
265 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
266 * @{
267 */
268
269 /**
270 * @brief Compute UARTDIV value according to Peripheral Clock and
271 * expected Baud Rate (32 bits value of UARTDIV is returned)
272 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
273 * @param __BAUDRATE__ Baud rate value to achieve
274 * @retval UARTDIV value to be used for DLL,DLH registers
275 */
276 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
277
278 /**
279 * @brief Compute UARTDLF value according to Peripheral Clock and
280 * expected Baud Rate (32 bits value of UARTDLF is returned)
281 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
282 * @param __BAUDRATE__ Baud rate value to achieve
283 * @retval UARTDLF value to be used for DLL,DLH registers
284 */
285 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
286
287 /** @} */
288
289 /** @} */
290
291 /** @} */
292
293 /* Exported functions --------------------------------------------------------*/
294 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
295 * @{
296 */
297
298 /** @defgroup UART_LL_EF_Configuration Configuration functions
299 * @{
300 */
301
302 /**
303 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
304 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
305 * (Baud rate value != 0)
306 *
307 * Register|BitsName
308 * --------|--------
309 * DLL | DLL
310 * DLH | DLH
311 *
312 * @param UARTx UART instance
313 * @param peripheral_clock Peripheral Clock
314 * @param baud_rate Baud Rate
315 * @retval None
316 */
317 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
318 {
319 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
320
321 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
322 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
323 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
324 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
325 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
326 }
327
328 /**
329 * @brief Return current Baud Rate value
330 * @note In case of non-initialized or invalid value stored in DLL,DLH and DLF register, the value 0 will be returned..
331 *
332 * Register|BitsName
333 * --------|--------
334 * DLL | DLL
335 * DLH | DLH
336 *
337 * @param UARTx UART instance
338 * @param peripheral_clock Peripheral Clock
339 * @retval Baud Rate
340 */
341 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
342 {
343 register uint32_t uartdiv = 0x0U;
344 register uint32_t baud = 0x0U;
345
346 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
347 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
348 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
349
350 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
351 {
352 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
353 }
354
355 return baud;
356 }
357
358 /**
359 * @brief Set the length of the data bits
360 *
361 * Register|BitsName
362 * --------|--------
363 * LCR | DLS
364 *
365 * @param UARTx UART instance
366 * @param data_bits This parameter can be one of the following values:
367 * @arg @ref LL_UART_DATABITS_5B
368 * @arg @ref LL_UART_DATABITS_6B
369 * @arg @ref LL_UART_DATABITS_7B
370 * @arg @ref LL_UART_DATABITS_8B
371 *
372 * @retval None
373 */
374 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
375 {
376 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
377 }
378
379 /**
380 * @brief Return the length of the data bits
381 *
382 * Register|BitsName
383 * --------|--------
384 * LCR | DLS
385 *
386 * @param UARTx UART instance
387 * @retval Returned value can be one of the following values:
388 * @arg @ref LL_UART_DATABITS_5B
389 * @arg @ref LL_UART_DATABITS_6B
390 * @arg @ref LL_UART_DATABITS_7B
391 * @arg @ref LL_UART_DATABITS_8B
392 */
393 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
394 {
395 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
396 }
397
398 /**
399 * @brief Set the length of the stop bits
400 *
401 * Register|BitsName
402 * --------|--------
403 * LCR | STOP
404 *
405 * @param UARTx UART instance
406 * @param stop_bits This parameter can be one of the following values:
407 * @arg @ref LL_UART_STOPBITS_1
408 * @arg @ref LL_UART_STOPBITS_1_5 (*)
409 * @arg @ref LL_UART_STOPBITS_2 (*)
410 *
411 * (*) STOPBITS_1_5 only valid when DataBits = 5
412 * (*) STOPBITS_2 is invalid when DataBits = 5
413 * @retval None
414 */
415 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
416 {
417 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
418 }
419
420 /**
421 * @brief Retrieve the length of the stop bits
422 *
423 * Register|BitsName
424 * --------|--------
425 * LCR | STOP
426 *
427 * @param UARTx UART instance
428 * @retval Returned value can be one of the following values:
429 * @arg @ref LL_UART_STOPBITS_1
430 * @arg @ref LL_UART_STOPBITS_1_5
431 * @arg @ref LL_UART_STOPBITS_2
432 */
433 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
434 {
435 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
436 }
437
438 /**
439 * @brief Configure Parity.
440 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
441 * When the parity control is enabled (Odd,Even,0,1), computed parity bit is inserted at the MSB position
442 * and parity is checked on the received data.
443 *
444 * Register|BitsName
445 * --------|--------
446 * LCR | SP
447 * LCR | EPS
448 * LCR | PEN
449 *
450 * @param UARTx UART instance
451 * @param parity This parameter can be one of the following values:
452 * @arg @ref LL_UART_PARITY_NONE
453 * @arg @ref LL_UART_PARITY_EVEN
454 * @arg @ref LL_UART_PARITY_ODD
455 * @arg @ref LL_UART_PARITY_SP0
456 * @arg @ref LL_UART_PARITY_SP1
457 * @retval None
458 */
459 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
460 {
461 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
462 }
463
464 /**
465 * @brief Return Parity configuration
466 *
467 * Register|BitsName
468 * --------|--------
469 * LCR | SP
470 * LCR | EPS
471 * LCR | PEN
472 *
473 * @param UARTx UART instance
474 * @retval Returned value can be one of the following values:
475 * @arg @ref LL_UART_PARITY_NONE
476 * @arg @ref LL_UART_PARITY_EVEN
477 * @arg @ref LL_UART_PARITY_ODD
478 * @arg @ref LL_UART_PARITY_SP0
479 * @arg @ref LL_UART_PARITY_SP1
480 */
481 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
482 {
483 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
484 }
485
486 /**
487 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
488 * @note This function call is equivalent to the following function call sequence :
489 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
490 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
491 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
492 *
493 * Register|BitsName
494 * --------|--------
495 * LCR | PS
496 * LCR | EPS
497 * LCR | PEN
498 * LCR | STOP
499 * LCR | DLS
500 *
501 * @param UARTx UART instance
502 * @param data_bits This parameter can be one of the following values:
503 * @arg @ref LL_UART_DATABITS_5B
504 * @arg @ref LL_UART_DATABITS_6B
505 * @arg @ref LL_UART_DATABITS_7B
506 * @arg @ref LL_UART_DATABITS_8B
507 * @param parity This parameter can be one of the following values:
508 * @arg @ref LL_UART_PARITY_NONE
509 * @arg @ref LL_UART_PARITY_EVEN
510 * @arg @ref LL_UART_PARITY_ODD
511 * @arg @ref LL_UART_PARITY_SP0
512 * @arg @ref LL_UART_PARITY_SP1
513 * @param stop_bits This parameter can be one of the following values:
514 * @arg @ref LL_UART_STOPBITS_1
515 * @arg @ref LL_UART_STOPBITS_1_5 (*)
516 * @arg @ref LL_UART_STOPBITS_2 (*)
517 *
518 * (*) STOPBITS_1_5 only valid when DataBits = 5
519 * (*) STOPBITS_2 is invalid when DataBits = 5
520 * @retval None
521 */
522 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
523 uint32_t data_bits,
524 uint32_t parity,
525 uint32_t stop_bits)
526 {
527 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
528 }
529
530 /**
531 * @brief Set UART RTS pin state to Active/Inactive
532 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
533 *
534 * Register|BitsName
535 * --------|--------
536 * SRTS | SRTS
537 * MCR | RTS
538 *
539 * @param UARTx UART instance
540 * @param pin_state This parameter can be one of the following values:
541 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
542 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
543 * @retval None
544 */
545 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
546 {
547 WRITE_REG(UARTx->SRTS, pin_state);
548 }
549
550 /**
551 * @brief Get UART RTS pin state
552 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
553 *
554 * Register|BitsName
555 * --------|--------
556 * SRTS | SRTS
557 * MCR | RTS
558 *
559 * @param UARTx UART instance
560 * @retval Returned value can be one of the following values:
561 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
562 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
563 */
564 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
565 {
566 return (uint32_t)(READ_REG(UARTx->SRTS));
567 }
568
569 /**
570 * @brief Get UART CTS pin state
571 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
572 *
573 * Register|BitsName
574 * --------|--------
575 * MSR | CTS
576 *
577 * @param UARTx UART instance
578 * @retval Returned value can be one of the following values:
579 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
580 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
581 */
582 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
583 {
584 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
585 }
586
587 /**
588 * @brief Indicate if CTS is changed since the last time the MSR was read
589 *
590 * Register|BitsName
591 * --------|--------
592 * MSR | DCTS
593 *
594 * @param UARTx UART instance
595 * @retval State of bit (1 or 0).
596 */
597 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
598 {
599 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
600 }
601
602 /**
603 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
604 * @note This function is used to Enable/Disable UART Auto Flow Control.
605 *
606 * Register|BitsName
607 * --------|--------
608 * MCR | AFCE
609 * MCR | RTS
610 *
611 * @param UARTx UART instance
612 * @param hw_flow_ctrl This parameter can be one of the following values:
613 * @arg @ref LL_UART_HWCONTROL_NONE
614 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
615 * @retval None
616 */
617 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
618 {
619 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
620 }
621
622 /**
623 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
624 *
625 * Register|BitsName
626 * --------|--------
627 * MCR | AFCE
628 * MCR | RTS
629 *
630 * @param UARTx UART instance
631 * @retval Returned value can be one of the following values:
632 * @arg @ref LL_UART_HWCONTROL_NONE
633 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
634 */
635 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
636 {
637 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
638 }
639
640 /**
641 * @brief Enable Break sending
642 *
643 * Register|BitsName
644 * --------|--------
645 * LCR | BC
646 *
647 * @param UARTx UART instance
648 * @retval None
649 */
650 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
651 {
652 WRITE_REG(UARTx->SBCR, 0x1U);
653 }
654
655 /**
656 * @brief Disable Break sending
657 *
658 * Register|BitsName
659 * --------|--------
660 * LCR | BC
661 *
662 * @param UARTx UART instance
663 * @retval None
664 */
665 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
666 {
667 WRITE_REG(UARTx->SBCR, 0x0U);
668 }
669
670 /**
671 * @brief Indicate if Break sending is enabled
672 *
673 * Register|BitsName
674 * --------|--------
675 * LCR | BC
676 *
677 * @param UARTx UART instance
678 * @retval State of bit (1 or 0).
679 */
680 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
681 {
682 return READ_REG(UARTx->SBCR);
683 }
684
685 /**
686 * @brief Enable TX FIFO and RX FIFO
687 *
688 * Register|BitsName
689 * --------|--------
690 * SFE | SFE
691 *
692 * @param UARTx UART instance
693 * @retval None
694 */
695 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
696 {
697 WRITE_REG(UARTx->SFE, 0x1U);
698 }
699
700 /**
701 * @brief Disable TX FIFO and RX FIFO
702 *
703 * Register|BitsName
704 * --------|--------
705 * SFE | SFE
706 *
707 * @param UARTx UART instance
708 * @retval None
709 */
710 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
711 {
712 WRITE_REG(UARTx->SFE, 0x0U);
713 }
714
715 /**
716 * @brief Indicate if TX FIFO and RX FIFO is enabled
717 *
718 * Register|BitsName
719 * --------|--------
720 * SFE | SFE
721 *
722 * @param UARTx UART instance
723 * @retval State of bit (1 or 0).
724 */
725 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
726 {
727 return READ_REG(UARTx->SFE);
728 }
729
730 /**
731 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
732 *
733 * Register|BitsName
734 * --------|--------
735 * STET | STET
736 *
737 * @param UARTx UART instance
738 * @param threshold This parameter can be one of the following values:
739 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
740 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
741 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
742 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
743 * @retval None
744 */
745 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
746 {
747 WRITE_REG(UARTx->STET, threshold);
748 }
749
750 /**
751 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
752 *
753 * Register|BitsName
754 * --------|--------
755 * STET | STET
756 *
757 * @param UARTx UART instance
758 * @retval Returned value can be one of the following values:
759 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
760 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
761 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
762 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
763 */
764 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
765 {
766 return (uint32_t)(READ_REG(UARTx->STET));
767 }
768
769 /**
770 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
771 *
772 * Register|BitsName
773 * --------|--------
774 * SRT | SRT
775 *
776 * @param UARTx UART instance
777 * @param threshold This parameter can be one of the following values:
778 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
779 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
780 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
781 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
782 * @retval None
783 */
784 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
785 {
786 WRITE_REG(UARTx->SRT, threshold);
787 }
788
789 /**
790 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
791 *
792 * Register|BitsName
793 * --------|--------
794 * SRT | SRT
795 *
796 * @param UARTx UART instance
797 * @retval Returned value can be one of the following values:
798 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
799 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
800 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
801 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
802 */
803 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
804 {
805 return (uint32_t)(READ_REG(UARTx->SRT));
806 }
807
808 /**
809 * @brief Get FIFO Transmission Level
810 *
811 * Register|BitsName
812 * --------|--------
813 * TFL | TFL
814 *
815 * @param UARTx UART instance
816 * @retval Returned value can be one of the following values:
817 */
818 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
819 {
820 return (uint32_t)(READ_REG(UARTx->TFL));
821 }
822
823 /**
824 * @brief Get FIFO reception Level
825 *
826 * Register|BitsName
827 * --------|--------
828 * RFL | RFL
829 *
830 * @param UARTx UART instance
831 * @retval Returned value can be one of the following values:
832 */
833 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
834 {
835 return (uint32_t)(READ_REG(UARTx->RFL));
836 }
837
838 /**
839 * @brief Flush Receive FIFO
840 *
841 * Register|BitsName
842 * --------|--------
843 * SRR | RFR
844 *
845 * @param UARTx UART instance
846 * @retval None
847 */
848 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
849 {
850 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
851 }
852
853 /**
854 * @brief Flush Transmit FIFO
855 *
856 * Register|BitsName
857 * --------|--------
858 * SRR | XFR
859 *
860 * @param UARTx UART instance
861 * @retval None
862 */
863 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
864 {
865 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
866 }
867
868 /**
869 * @brief Reset UART
870 * @note This function asynchronously resets the DW_apb_uart and synchronously
871 * removes the reset assertion. For a two clock implementation, both pclk
872 * and sclk domains will be reset.
873 *
874 * Register|BitsName
875 * --------|--------
876 * SRR | UR
877 *
878 * @param UARTx UART instance
879 * @retval None
880 */
881 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
882 {
883 WRITE_REG(UARTx->SRR, UART_SRR_UR);
884 }
885
886 /** @} */
887
888 /** @defgroup UART_LL_EF_IT_Management IT_Management
889 * @{
890 */
891
892 /**
893 * @brief Enable Modem Status Interrupt
894 *
895 * Register|BitsName
896 * --------|--------
897 * IER | EDSSI
898 *
899 * @param UARTx UART instance
900 * @retval None
901 */
902 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
903 {
904 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
905 }
906
907 /**
908 * @brief Enable Receiver Line Status Interrupt
909 *
910 * Register|BitsName
911 * --------|--------
912 * IER | RLS
913 *
914 * @param UARTx UART instance
915 * @retval None
916 */
917 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
918 {
919 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
920 }
921
922 /**
923 * @brief Enable Transmit Holding Register Empty Interrupt
924 *
925 * Register|BitsName
926 * --------|--------
927 * IER | PTIME
928 * IER | ETBEI
929 *
930 * @param UARTx UART instance
931 * @retval None
932 */
933 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
934 {
935 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
936 }
937
938 /**
939 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
940 *
941 * Register|BitsName
942 * --------|--------
943 * IER | ERBFI
944 *
945 * @param UARTx UART instance
946 * @retval None
947 */
948 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
949 {
950 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
951 }
952
953 /**
954 * @brief Disable Modem Status Interrupt
955 *
956 * Register|BitsName
957 * --------|--------
958 * IER | EDSSI
959 *
960 * @param UARTx UART instance
961 * @retval None
962 */
963 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
964 {
965 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
966 }
967
968 /**
969 * @brief Disable Receiver Line Status Interrupt
970 *
971 * Register|BitsName
972 * --------|--------
973 * IER | RLS
974 *
975 * @param UARTx UART instance
976 * @retval None
977 */
978 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
979 {
980 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
981 }
982
983 /**
984 * @brief Disable Transmit Holding Register Empty Interrupt
985 *
986 * Register|BitsName
987 * --------|--------
988 * IER | PTIME
989 * IER | ETBEI
990 *
991 * @param UARTx UART instance
992 * @retval None
993 */
994 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
995 {
996 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
997 }
998
999 /**
1000 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1001 *
1002 * Register|BitsName
1003 * --------|--------
1004 * IER | ERBFI
1005 *
1006 * @param UARTx UART instance
1007 * @retval None
1008 */
1009 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1010 {
1011 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1012 }
1013
1014 /**
1015 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1016 *
1017 * Register|BitsName
1018 * --------|--------
1019 * IER | EDSSI
1020 *
1021 * @param UARTx UART instance
1022 * @retval State of bit (1 or 0).
1023 */
1024 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1025 {
1026 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1027 }
1028
1029 /**
1030 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1031 *
1032 * Register|BitsName
1033 * --------|--------
1034 * IER | RLS
1035 *
1036 * @param UARTx UART instance
1037 * @retval State of bit (1 or 0).
1038 */
1039 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1040 {
1041 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1042 }
1043
1044 /**
1045 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1046 *
1047 * Register|BitsName
1048 * --------|--------
1049 * IER | PTIME
1050 * IER | ETBEI
1051 *
1052 * @param UARTx UART instance
1053 * @retval State of bit (1 or 0).
1054 */
1055 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1056 {
1057 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1058 }
1059
1060 /**
1061 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1062 * is enabled or disabled.
1063 *
1064 * Register|BitsName
1065 * --------|--------
1066 * IER | ERBFI
1067 *
1068 * @param UARTx UART instance
1069 * @retval State of bit (1 or 0).
1070 */
1071 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1072 {
1073 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1074 }
1075
1076 /**
1077 * @brief Enable the specified UART Interrupt.
1078 *
1079 * Register|BitsName
1080 * --------|--------
1081 * IER | EDSSI
1082 * IER | ERLS
1083 * IER | PTIME
1084 * IER | ETBEI
1085 * IER | ERBFI
1086 *
1087 * @param UARTx UART instance
1088 * @param mask This parameter can be a combination of the following values:
1089 * @arg @ref LL_UART_IER_MS
1090 * @arg @ref LL_UART_IER_RLS
1091 * @arg @ref LL_UART_IER_THRE
1092 * @arg @ref LL_UART_IER_RDA
1093 * @retval None
1094 */
1095 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1096 {
1097 SET_BITS(UARTx->DLH_IER.IER, mask);
1098 }
1099
1100 /**
1101 * @brief Disable the specified UART Interrupt.
1102 *
1103 * Register|BitsName
1104 * --------|--------
1105 * IER | EDSSI
1106 * IER | ERLS
1107 * IER | PTIME
1108 * IER | ETBEI
1109 * IER | ERBFI
1110 *
1111 * @param UARTx UART instance
1112 * @param mask This parameter can be a combination of the following values:
1113 * @arg @ref LL_UART_IER_MS
1114 * @arg @ref LL_UART_IER_RLS
1115 * @arg @ref LL_UART_IER_THRE
1116 * @arg @ref LL_UART_IER_RDA
1117 * @retval None
1118 */
1119 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1120 {
1121 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1122 }
1123
1124 /**
1125 * @brief Check if the specified UART Interrupt is enabled or disabled.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * IER | EDSSI
1130 * IER | ERLS
1131 * IER | PTIME
1132 * IER | ETBEI
1133 * IER | ERBFI
1134 *
1135 * @param UARTx UART instance
1136 * @param mask This parameter can be a combination of the following values:
1137 * @arg @ref LL_UART_IER_MS
1138 * @arg @ref LL_UART_IER_RLS
1139 * @arg @ref LL_UART_IER_THRE
1140 * @arg @ref LL_UART_IER_RDA
1141 * @retval State of bit (1 or 0).
1142 */
1143 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1144 {
1145 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1146 }
1147
1148 /** @} */
1149
1150 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1151 * @{
1152 */
1153
1154 /**
1155 * @brief Get UART Receive Line Status Flag
1156 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1157 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1158 *
1159 * Register|BitsName
1160 * --------|--------
1161 * LSR | OE
1162 * LSR | PE
1163 * LSR | FE
1164 * LSR | BI
1165 * LSR | THRE
1166 * LSR | TEMT
1167 * LSR | RFE
1168 *
1169 * @param UARTx UART instance
1170 * @retval Returned value can be a combination of the following values:
1171 * @arg @ref LL_UART_LSR_OE
1172 * @arg @ref LL_UART_LSR_PE
1173 * @arg @ref LL_UART_LSR_FE
1174 * @arg @ref LL_UART_LSR_BI
1175 * @arg @ref LL_UART_LSR_THRE
1176 * @arg @ref LL_UART_LSR_TEMT
1177 * @arg @ref LL_UART_LSR_RFE
1178 */
1179 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1180 {
1181 return ((uint32_t)READ_REG(UARTx->LSR));
1182 }
1183
1184 /**
1185 * @brief Clear UART Receive Line Status Flag
1186 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1187 *
1188 * Register|BitsName
1189 * --------|--------
1190 * LSR | OE
1191 * LSR | PE
1192 * LSR | FE
1193 * LSR | BI
1194 * LSR | RFE
1195 *
1196 * @param UARTx UART instance
1197 * @retval None
1198 */
1199 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1200 {
1201 __IO uint32_t tmpreg;
1202 tmpreg = READ_REG(UARTx->LSR);
1203 (void) tmpreg;
1204 }
1205
1206 /**
1207 * @brief Check if the UART Receive FIFO Full Flag is set or not
1208 *
1209 * Register|BitsName
1210 * --------|--------
1211 * USR | RFF
1212 *
1213 * @param UARTx UART instance
1214 * @retval State of bit (1 or 0).
1215 */
1216 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1217 {
1218 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1219 }
1220
1221 /**
1222 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1223 *
1224 * Register|BitsName
1225 * --------|--------
1226 * USR | RFNE
1227 *
1228 * @param UARTx UART instance
1229 * @retval State of bit (1 or 0).
1230 */
1231 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1232 {
1233 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1234 }
1235
1236 /**
1237 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1238 *
1239 * Register|BitsName
1240 * --------|--------
1241 * USR | TFE
1242 *
1243 * @param UARTx UART instance
1244 * @retval State of bit (1 or 0).
1245 */
1246 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1247 {
1248 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1249 }
1250
1251 /**
1252 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1253 *
1254 * Register|BitsName
1255 * --------|--------
1256 * USR | TFNF
1257 *
1258 * @param UARTx UART instance
1259 * @retval State of bit (1 or 0).
1260 */
1261 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1262 {
1263 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1264 }
1265
1266 /**
1267 * @brief Get UART interrupt flags
1268 * @note The interrupt flags will be cleared after reading IIR.
1269 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1270 * and No Interrupt Pending Flag will be RESET, read IIR again can get the pended interrupt
1271 *
1272 * Register|BitsName
1273 * --------|--------
1274 * IIR | IID
1275 *
1276 * @param UARTx UART instance
1277 * @retval Returned value can be one or combination of the following values:
1278 * @arg @ref LL_UART_IIR_MS
1279 * @arg @ref LL_UART_IIR_NIP
1280 * @arg @ref LL_UART_IIR_THRE
1281 * @arg @ref LL_UART_IIR_RDA
1282 * @arg @ref LL_UART_IIR_RLS
1283 * @arg @ref LL_UART_IIR_CTO
1284 */
1285 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1286 {
1287 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1288 }
1289
1290 /** @} */
1291
1292 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1293 * @{
1294 */
1295
1296 /**
1297 * @brief Get the data register address used for DMA transfer
1298 * @note The address of data register RBR is the same as the address of THR.
1299 *
1300 * Register|BitsName
1301 * --------|--------
1302 * RBR | RBR
1303 * THR | THR
1304 *
1305 * @param UARTx UART instance
1306 * @retval Address of data register
1307 */
1308 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1309 {
1310 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1311 }
1312
1313 /** @} */
1314
1315 /** @defgroup UART_LL_EF_Data_Management Data_Management
1316 * @{
1317 */
1318
1319 /**
1320 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1321 *
1322 * Register|BitsName
1323 * --------|--------
1324 * RBR | RBR
1325 *
1326 * @param UARTx UART instance
1327 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1328 */
1329 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1330 {
1331 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1332 }
1333
1334 /**
1335 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1336 *
1337 * Register|BitsName
1338 * --------|--------
1339 * THR | THR
1340 *
1341 * @param UARTx UART instance
1342 * @param value between Min_Data=0x00 and Max_Data=0xFF
1343 * @retval None
1344 */
1345 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1346 {
1347 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1348 }
1349
1350 /** @} */
1351
1352 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1353 * @{
1354 */
1355
1356 /**
1357 * @brief De-initialize UART registers (Registers restored to their default values).
1358 * @param UARTx UART instance
1359 * @retval An error_status_t enumeration value:
1360 * - SUCCESS: UART registers are de-initialized
1361 * - ERROR: UART registers are not de-initialized
1362 */
1363 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1364
1365 /**
1366 * @brief Initialize UART registers according to the specified
1367 * parameters in p_uart_init.
1368 * @param UARTx UART instance
1369 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1370 * information for the specified UART peripheral.
1371 * @retval An error_status_t enumeration value:
1372 * - SUCCESS: UART registers are initialized according to p_uart_init content
1373 * - ERROR: Problem occurred during UART Registers initialization
1374 */
1375 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1376
1377 /**
1378 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1379 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1380 * whose fields will be set to default values.
1381 * @retval None
1382 */
1383 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1384
1385 /** @} */
1386
1387 /** @} */
1388
1389 #endif /* UART0 || UART1 */
1390
1391 #ifdef __cplusplus
1392 }
1393 #endif
1394
1395 #endif /* __GR55xx_LL_UART_H__ */
1396
1397 /** @} */
1398
1399 /** @} */
1400
1401 /** @} */
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1231
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1024
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: gr55xx_ll_uart.h:545
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: gr55xx_ll_uart.h:680
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:994
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: gr55xx_ll_uart.h:415
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: gr55xx_ll_uart.h:317
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: gr55xx_ll_uart.h:725
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:933
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_uart.h:1308
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:902
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: gr55xx_ll_uart.h:459
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1009
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: gr55xx_ll_uart.h:285
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_uart.h:818
_ll_uart_init_t
LL UART init Structure definition.
Definition: gr55xx_ll_uart.h:77
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:803
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: gr55xx_ll_uart.h:564
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:917
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: gr55xx_ll_uart.h:665
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1055
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1216
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1095
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1179
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: gr55xx_ll_uart.h:650
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:710
ll_uart_init
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: gr55xx_ll_uart.h:393
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: gr55xx_ll_uart.h:582
_ll_uart_init_t::data_bits
uint32_t data_bits
Specifies the number of data bits transmitted or received in a frame.
Definition: gr55xx_ll_uart.h:82
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1039
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1199
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:948
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: gr55xx_ll_uart.h:341
_ll_uart_init_t::baud_rate
uint32_t baud_rate
This field defines expected Usart communication baud rate.
Definition: gr55xx_ll_uart.h:78
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: gr55xx_ll_uart.h:1071
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1345
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1119
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:635
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:617
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:764
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:963
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:784
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: gr55xx_ll_uart.h:863
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1329
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: gr55xx_ll_uart.h:481
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: gr55xx_ll_uart.h:881
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:978
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Specifies the number of stop bits transmitted.
Definition: gr55xx_ll_uart.h:87
_ll_uart_init_t::parity
uint32_t parity
Specifies the parity mode.
Definition: gr55xx_ll_uart.h:92
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: gr55xx_ll_uart.h:833
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Specifies whether the hardware flow control mode is enabled or disabled.
Definition: gr55xx_ll_uart.h:97
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1246
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: gr55xx_ll_uart.h:522
ll_uart_deinit
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:695
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:745
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: gr55xx_ll_uart.h:433
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: gr55xx_ll_uart.h:597
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1143
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1261
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: gr55xx_ll_uart.h:848
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: gr55xx_ll_uart.h:276
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: gr55xx_ll_uart.h:374
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: gr55xx_ll_uart.h:1285