gr55xx_ll_spi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (SPIM) || defined (SPIS) || defined (QSPI0) || defined (QSPI1)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
87
88 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
89 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
90
91 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
92
93 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
94 This parameter can be a value of @ref SPI_LL_EC_PHASE.
95
96 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
97
98 uint32_t slave_select; /**< Specifies the SPI slave select.
99 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
100
101 This feature can be modified afterwards using unitary function @ref ll_spi_enable_ss().*/
102
103 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
104 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
105 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
108 } ll_spim_init_t;
109
110 /**
111 * @brief SPIS init structures definition
112 */
113 typedef struct _ll_spis_init_t
114 {
115 uint32_t data_size; /**< Specifies the SPI data width.
116 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
117
118 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
119
120 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
121 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
122
123 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
124
125 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
126 This parameter can be a value of @ref SPI_LL_EC_PHASE.
127
128 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
129
130 } ll_spis_init_t;
131
132 /**
133 * @brief QSPI init structures definition
134 */
135 typedef struct _ll_qspi_init_t
136 {
137 uint32_t transfer_direction; /**< Specifies the QSPI transfer or receive mode.
138 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
139
140 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
141
142 uint32_t instruction_size; /**< Specifies the QSPI instruction width.
143 This parameter can be a value of @ref SPI_LL_EC_INSTRUCTIONSIZE.
144
145 This feature can be modified afterwards using unitary function @ref ll_spi_set_instruction_size().*/
146
147 uint32_t address_size; /**< Specifies the QSPI address width.
148 This parameter can be a value of @ref SPI_LL_EC_ADDRESSSIZE.
149
150 This feature can be modified afterwards using unitary function @ref ll_spi_set_address_size().*/
151
152 uint32_t inst_addr_transfer_format; /**< Specifies the QSPI instruction and address transfer format.
153 This parameter can be a value of @ref SPI_LL_EC_ADDRINSTTRNASFERFORMAT.
154
155 This feature can be modified afterwards using unitary function @ref ll_spi_set_add_inst_transfer_format().*/
156
157 uint32_t wait_cycles; /**< Specifies the QSPI dummy clock.
158 This parameter can be one of the following values: 0 ~ 31.
159
160 This feature can be modified afterwards using unitary function @ref ll_spi_set_wait_cycles().*/
161
162 uint32_t data_size; /**< Specifies the SPI data width.
163 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
164
165 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
166
167 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
168 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
169
170 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
171
172 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
173 This parameter can be a value of @ref SPI_LL_EC_PHASE.
174
175 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
176
177 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
178 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
179 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
180
181 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
182
183 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
184 This parameter can be a number between 0 and 0x7 */
185 } ll_qspi_init_t;
186
187 /** @} */
188
189 /** @} */
190
191 /**
192 * @defgroup SPI_LL_MACRO Defines
193 * @{
194 */
195
196 /* Exported constants --------------------------------------------------------*/
197 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
198 * @{
199 */
200
201 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
202 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
203 * @{
204 */
205 #define LL_SSI_SR_DCOL SSI_STAT_DCOL /**< Data collision error flag */
206 #define LL_SSI_SR_TXE SSI_STAT_TXE /**< Transmission error flag */
207 #define LL_SSI_SR_RFF SSI_STAT_RFF /**< Rx FIFO full flag */
208 #define LL_SSI_SR_RFNE SSI_STAT_RFNE /**< Rx FIFO not empty flag */
209 #define LL_SSI_SR_TFE SSI_STAT_TFE /**< Tx FIFO empty flag */
210 #define LL_SSI_SR_TFNF SSI_STAT_TFNF /**< Tx FIFO not full flag */
211 #define LL_SSI_SR_BUSY SSI_STAT_BUSY /**< Busy flag */
212 /** @} */
213
214 /** @defgroup SPI_LL_EC_IT IT Defines
215 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
216 * @{
217 */
218 #define LL_SSI_IM_MST SSI_INTMASK_MSTIM /**< Multi-Master Contention Interrupt enable */
219 #define LL_SSI_IM_RXF SSI_INTMASK_RXFIM /**< Receive FIFO Full Interrupt enable */
220 #define LL_SSI_IM_RXO SSI_INTMASK_RXOIM /**< Receive FIFO Overflow Interrupt enable */
221 #define LL_SSI_IM_RXU SSI_INTMASK_RXUIM /**< Receive FIFO Underflow Interrupt enable */
222 #define LL_SSI_IM_TXO SSI_INTMASK_TXOIM /**< Transmit FIFO Overflow Interrupt enable */
223 #define LL_SSI_IM_TXE SSI_INTMASK_TXEIM /**< Transmit FIFO Empty Interrupt enable */
224
225 #define LL_SSI_IS_MST SSI_INTSTAT_MSTIS /**< Multi-Master Contention Interrupt flag */
226 #define LL_SSI_IS_RXF SSI_INTSTAT_RXFIS /**< Receive FIFO Full Interrupt flag */
227 #define LL_SSI_IS_RXO SSI_INTSTAT_RXOIS /**< Receive FIFO Overflow Interrupt flag */
228 #define LL_SSI_IS_RXU SSI_INTSTAT_RXUIS /**< Receive FIFO Underflow Interrupt flag */
229 #define LL_SSI_IS_TXO SSI_INTSTAT_TXOIS /**< Transmit FIFO Overflow Interrupt flag */
230 #define LL_SSI_IS_TXE SSI_INTSTAT_TXEIS /**< Transmit FIFO Empty Interrupt flag */
231
232 #define LL_SSI_RIS_MST SSI_RAW_INTSTAT_MSTIR /**< Multi-Master Contention RAW Interrupt flag */
233 #define LL_SSI_RIS_RXF SSI_RAW_INTSTAT_RXFIR /**< Receive FIFO Full RAW Interrupt flag */
234 #define LL_SSI_RIS_RXO SSI_RAW_INTSTAT_RXOIR /**< Receive FIFO Overflow RAW Interrupt flag */
235 #define LL_SSI_RIS_RXU SSI_RAW_INTSTAT_RXUIR /**< Receive FIFO Underflow RAW Interrupt flag */
236 #define LL_SSI_RIS_TXO SSI_RAW_INTSTAT_TXOIR /**< Transmit FIFO Overflow RAW Interrupt flag */
237 #define LL_SSI_RIS_TXE SSI_RAW_INTSTAT_TXEIR /**< Transmit FIFO Empty RAW Interrupt flag */
238 /** @} */
239
240 /** @defgroup SPI_LL_EC_SPIFRAMEFORMAT SPI Frame Format
241 * @{
242 */
243 #define LL_SSI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
244 #define LL_SSI_FRF_DUALSPI (1UL << SSI_CTRL0_SPIFRF_Pos) /**< Dual-SPI frame format for transfer */
245 #define LL_SSI_FRF_QUADSPI (2UL << SSI_CTRL0_SPIFRF_Pos) /**< Quad-SPI frame format for transfer */
246 /** @} */
247
248 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
249 * @{
250 */
251 #define LL_SSI_DATASIZE_4BIT (3UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 4 bits */
252 #define LL_SSI_DATASIZE_5BIT (4UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 5 bits */
253 #define LL_SSI_DATASIZE_6BIT (5UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 6 bits */
254 #define LL_SSI_DATASIZE_7BIT (6UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 7 bits */
255 #define LL_SSI_DATASIZE_8BIT (7UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 8 bits */
256 #define LL_SSI_DATASIZE_9BIT (8UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 9 bits */
257 #define LL_SSI_DATASIZE_10BIT (9UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 10 bits */
258 #define LL_SSI_DATASIZE_11BIT (10UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 11 bits */
259 #define LL_SSI_DATASIZE_12BIT (11UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 12 bits */
260 #define LL_SSI_DATASIZE_13BIT (12UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 13 bits */
261 #define LL_SSI_DATASIZE_14BIT (13UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 14 bits */
262 #define LL_SSI_DATASIZE_15BIT (14UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 15 bits */
263 #define LL_SSI_DATASIZE_16BIT (15UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 16 bits */
264 #define LL_SSI_DATASIZE_17BIT (16UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 17 bits */
265 #define LL_SSI_DATASIZE_18BIT (17UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 18 bits */
266 #define LL_SSI_DATASIZE_19BIT (18UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 19 bits */
267 #define LL_SSI_DATASIZE_20BIT (19UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 20 bits */
268 #define LL_SSI_DATASIZE_21BIT (20UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 21 bits */
269 #define LL_SSI_DATASIZE_22BIT (21UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 22 bits */
270 #define LL_SSI_DATASIZE_23BIT (22UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 23 bits */
271 #define LL_SSI_DATASIZE_24BIT (23UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 24 bits */
272 #define LL_SSI_DATASIZE_25BIT (24UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 25 bits */
273 #define LL_SSI_DATASIZE_26BIT (25UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 26 bits */
274 #define LL_SSI_DATASIZE_27BIT (26UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 27 bits */
275 #define LL_SSI_DATASIZE_28BIT (27UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 28 bits */
276 #define LL_SSI_DATASIZE_29BIT (28UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 29 bits */
277 #define LL_SSI_DATASIZE_30BIT (29UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 30 bits */
278 #define LL_SSI_DATASIZE_31BIT (30UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 31 bits */
279 #define LL_SSI_DATASIZE_32BIT (31UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 32 bits */
280 /** @} */
281
282 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
283 * @{
284 */
285 #define LL_SSI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
286 #define LL_SSI_MW_CMDSIZE_2BIT (1UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 2 bits */
287 #define LL_SSI_MW_CMDSIZE_3BIT (2UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 3 bits */
288 #define LL_SSI_MW_CMDSIZE_4BIT (3UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 4 bits */
289 #define LL_SSI_MW_CMDSIZE_5BIT (4UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 5 bits */
290 #define LL_SSI_MW_CMDSIZE_6BIT (5UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 6 bits */
291 #define LL_SSI_MW_CMDSIZE_7BIT (6UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 7 bits */
292 #define LL_SSI_MW_CMDSIZE_8BIT (7UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 8 bits */
293 #define LL_SSI_MW_CMDSIZE_9BIT (8UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 9 bits */
294 #define LL_SSI_MW_CMDSIZE_10BIT (9UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 10 bits */
295 #define LL_SSI_MW_CMDSIZE_11BIT (10UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 11 bits */
296 #define LL_SSI_MW_CMDSIZE_12BIT (11UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 12 bits */
297 #define LL_SSI_MW_CMDSIZE_13BIT (12UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 13 bits */
298 #define LL_SSI_MW_CMDSIZE_14BIT (13UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 14 bits */
299 #define LL_SSI_MW_CMDSIZE_15BIT (14UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 15 bits */
300 #define LL_SSI_MW_CMDSIZE_16BIT (15UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 16 bits */
301 /** @} */
302
303 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
304 * @{
305 */
306 #define LL_SSI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
307 #define LL_SSI_TEST_MODE (1UL << SSI_CTRL0_SRL_Pos) /**< Test mode for SPI transfer: Rx and Tx connected inside */
308 /** @} */
309
310 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
311 * @{
312 */
313 #define LL_SSI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
314 #define LL_SSI_SLAVE_OUTEN (1UL << SSI_CTRL0_SLVOE_Pos) /**< Output disable for SPI transfer as slave */
315 /** @} */
316
317 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
318 * @{
319 */
320 #define LL_SSI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
321 #define LL_SSI_SIMPLEX_TX (1UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Tx mode. Tx transfer only on 1 line */
322 #define LL_SSI_SIMPLEX_RX (2UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Rx mode. Rx transfer only on 1 line */
323 #define LL_SSI_READ_EEPROM (3UL << SSI_CTRL0_TMOD_Pos) /**< Read EEPROM mode. Rx transfer only on 1 line */
324 /** @} */
325
326 /** @defgroup SPI_LL_EC_PHASE Clock Phase
327 * @{
328 */
329 #define LL_SSI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
330 #define LL_SSI_SCPHA_2EDGE (1UL << SSI_CTRL0_SCPHA_Pos) /**< Second clock transition is the first data capture edge */
331 /** @} */
332
333 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
334 * @{
335 */
336 #define LL_SSI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
337 #define LL_SSI_SCPOL_HIGH (1UL << SSI_CTRL0_SCPOL_Pos) /**< Clock to 1 when idle */
338 /** @} */
339
340 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
341 * @{
342 */
343 #define LL_SSI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
344 #define LL_SSI_PROTOCOL_TI (1UL << SSI_CTRL0_FRF_Pos) /**< TI mode */
345 #define LL_SSI_PROTOCOL_MICROWIRE (2UL << SSI_CTRL0_FRF_Pos) /**< Microwire mode */
346 /** @} */
347
348 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
349 * @{
350 */
351 #define LL_SSI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
352 #define LL_SSI_MICROWIRE_HANDSHAKE_EN (1UL << SSI_MWC_MHS_Pos) /**< Disable Handshake for Microwire transfer */
353
354 #define LL_SSI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
355 #define LL_SSI_MICROWIRE_TX (1UL << SSI_MWC_MDD_Pos) /**< Tx mode. Tx transfer at Microwire mode */
356
357 #define LL_SSI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
358 #define LL_SSI_MICROWIRE_SEQUENTIAL (1UL << SSI_MWC_MWMOD_Pos) /**< Sequential for Microwire transfer */
359 /** @} */
360
361 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
362 * @{
363 */
364 #define LL_SSI_SLAVE1 SSI_SE_SLAVE1 /**< Enable slave1 select pin for SPI transfer */
365 #define LL_SSI_SLAVE0 SSI_SE_SLAVE0 /**< Enable slave0 select pin for SPI transfer */
366 /** @} */
367
368 /** @defgroup SPI_LL_EC_DMA DMA Defines
369 * @{
370 */
371 #define LL_SSI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
372 #define LL_SSI_DMA_TX_EN SSI_DMAC_TDMAE /**< Enable the transmit FIFO DMA channel */
373
374 #define LL_SSI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
375 #define LL_SSI_DMA_RX_EN SSI_DMAC_RDMAE /**< Enable the receive FIFO DMA channel */
376 /** @} */
377
378 /** @defgroup SPI_LL_EC_INSTRUCTIONSIZE QSPI Instruction Size
379 * @{
380 */
381 #define LL_SSI_INSTSIZE_0BIT 0x00000000UL /**< Instruction length for QSPI transfer: 0 bits */
382 #define LL_SSI_INSTSIZE_4BIT (1UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 4 bits */
383 #define LL_SSI_INSTSIZE_8BIT (2UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 8 bits */
384 #define LL_SSI_INSTSIZE_16BIT (3UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 16 bits */
385 /** @} */
386
387 /** @defgroup SPI_LL_EC_ADDRESSSIZE QSPI Address Size
388 * @{
389 */
390 #define LL_SSI_ADDRSIZE_0BIT 0x00000000UL /**< Address length for QSPI transfer: 0 bits */
391 #define LL_SSI_ADDRSIZE_4BIT (1UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 4 bits */
392 #define LL_SSI_ADDRSIZE_8BIT (2UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 8 bits */
393 #define LL_SSI_ADDRSIZE_12BIT (3UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 12 bits */
394 #define LL_SSI_ADDRSIZE_16BIT (4UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 16 bits */
395 #define LL_SSI_ADDRSIZE_20BIT (5UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 20 bits */
396 #define LL_SSI_ADDRSIZE_24BIT (6UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 24 bits */
397 #define LL_SSI_ADDRSIZE_28BIT (7UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 28 bits */
398 #define LL_SSI_ADDRSIZE_32BIT (8UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 32 bits */
399 #define LL_SSI_ADDRSIZE_36BIT (9UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 36 bits */
400 #define LL_SSI_ADDRSIZE_40BIT (10UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 40 bits */
401 #define LL_SSI_ADDRSIZE_44BIT (11UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 44 bits */
402 #define LL_SSI_ADDRSIZE_48BIT (12UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 48 bits */
403 #define LL_SSI_ADDRSIZE_52BIT (13UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 52 bits */
404 #define LL_SSI_ADDRSIZE_56BIT (14UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 56 bits */
405 #define LL_SSI_ADDRSIZE_60BIT (15UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 60 bits */
406 /** @} */
407
408 /** @defgroup SPI_LL_EC_ADDRINSTTRNASFERFORMAT QSPI Address and Instruction Transfer Format
409 * @{
410 */
411 #define LL_SSI_INST_ADDR_ALL_IN_SPI 0x00000000UL /**< Instruction and address are sent in SPI mode */
412 #define LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
413 #define LL_SSI_INST_ADDR_ALL_IN_SPIFRF (2UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction and address are sent in Daul/Quad SPI mode */
414 /** @} */
415
416 /** @defgroup SPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
417 * @{
418 */
419
420 /**
421 * @brief LL SPIM InitStrcut default configuartion
422 */
423 #define LL_SPIM_DEFAULT_CONFIG \
424 { \
425 .transfer_direction = LL_SSI_FULL_DUPLEX, \
426 .data_size = LL_SSI_DATASIZE_8BIT, \
427 .clock_polarity = LL_SSI_SCPOL_LOW, \
428 .clock_phase = LL_SSI_SCPHA_1EDGE, \
429 .slave_select = LL_SSI_SLAVE0, \
430 .baud_rate = SystemCoreClock / 2000000, \
431 }
432
433 /**
434 * @brief LL SPIS InitStrcut default configuartion
435 */
436 #define LL_SPIS_DEFAULT_CONFIG \
437 { \
438 .data_size = LL_SSI_DATASIZE_8BIT, \
439 .clock_polarity = LL_SSI_SCPOL_LOW, \
440 .clock_phase = LL_SSI_SCPHA_1EDGE, \
441 }
442
443 /**
444 * @brief LL QSPI InitStrcut default configuartion
445 */
446 #define LL_QSPI_DEFAULT_CONFIG \
447 { \
448 .transfer_direction = LL_SSI_SIMPLEX_TX, \
449 .instruction_size = LL_SSI_INSTSIZE_8BIT, \
450 .address_size = LL_SSI_ADDRSIZE_24BIT, \
451 .inst_addr_transfer_format = LL_SSI_INST_ADDR_ALL_IN_SPI,\
452 .wait_cycles = 0, \
453 .data_size = LL_SSI_DATASIZE_8BIT, \
454 .clock_polarity = LL_SSI_SCPOL_LOW, \
455 .clock_phase = LL_SSI_SCPHA_1EDGE, \
456 .baud_rate = SystemCoreClock / 1000000, \
457 .rx_sample_delay = 0, \
458 }
459 /** @} */
460
461 /** @} */
462
463 /* Exported macro ------------------------------------------------------------*/
464 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
465 * @{
466 */
467
468 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
469 * @{
470 */
471
472 /**
473 * @brief Write a value in SPI register
474 * @param __instance__ SPI instance
475 * @param __REG__ Register to be written
476 * @param __VALUE__ Value to be written in the register
477 * @retval None
478 */
479 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
480
481 /**
482 * @brief Read a value in SPI register
483 * @param __instance__ SPI instance
484 * @param __REG__ Register to be read
485 * @retval Register value
486 */
487 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
488
489 /** @} */
490
491 /** @} */
492
493 /** @} */
494
495 /* Exported functions --------------------------------------------------------*/
496 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
497 * @{
498 */
499
500 /** @defgroup SPI_LL_EF_Configuration Configuration functions
501 * @{
502 */
503
504 /**
505 * @brief Enable slave select toggle
506 * @note This bit should not be changed when communication is ongoing.
507 *
508 * Register|BitsName
509 * --------|--------
510 * CTRL0 | SSTEN
511 *
512 * @param SPIx SPI instance
513 * @retval None
514 */
515 __STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
516 {
517 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
518 }
519
520 /**
521 * @brief Disable slave select toggle
522 * @note This bit should not be changed when communication is ongoing.
523 *
524 * Register|BitsName
525 * --------|--------
526 * CTRL0 | SSTEN
527 *
528 * @param SPIx SPI instance
529 * @retval None
530 */
531 __STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
532 {
533 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
534 }
535
536 /**
537 * @brief Check if slave select toggle is enabled
538 * @note This bit should not be changed when communication is ongoing.
539 *
540 * Register|BitsName
541 * --------|--------
542 * CTRL0 | SSTEN
543 *
544 * @param SPIx SPI instance
545 * @retval State of bit (1 or 0).
546 */
547 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
548 {
549 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN) == (SSI_CTRL0_SSTEN));
550 }
551
552 /**
553 * @brief Set data frame format for transmitting/receiving the data
554 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
555 *
556 * Register|BitsName
557 * --------|--------
558 * CTRL0 | SPIFRF
559 *
560 * @param SPIx SPI instance
561 * @param frf This parameter can be one of the following values:
562 * @arg @ref LL_SSI_FRF_SPI
563 * @arg @ref LL_SSI_FRF_DUALSPI
564 * @arg @ref LL_SSI_FRF_QUADSPI
565 * @retval None
566 */
567 __STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
568 {
569 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SPIFRF, frf);
570 }
571
572 /**
573 * @brief Get data frame format for transmitting/receiving the data
574 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
575 *
576 * Register|BitsName
577 * --------|--------
578 * CTRL0 | SPIFRF
579 *
580 * @param SPIx SPI instance
581 * @retval Returned value can be one of the following values:
582 * @arg @ref LL_SSI_FRF_SPI
583 * @arg @ref LL_SSI_FRF_DUALSPI
584 * @arg @ref LL_SSI_FRF_QUADSPI
585 */
586 __STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
587 {
588 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SPIFRF));
589 }
590
591 /**
592 * @brief Set frame data size
593 *
594 * Register|BitsName
595 * --------|--------
596 * CTRL0 | DFS32
597 *
598 * @param SPIx SPI instance
599 * @param size This parameter can be one of the following values:
600 * @arg @ref LL_SSI_DATASIZE_4BIT
601 * @arg @ref LL_SSI_DATASIZE_5BIT
602 * @arg @ref LL_SSI_DATASIZE_6BIT
603 * @arg @ref LL_SSI_DATASIZE_7BIT
604 * @arg @ref LL_SSI_DATASIZE_8BIT
605 * @arg @ref LL_SSI_DATASIZE_9BIT
606 * @arg @ref LL_SSI_DATASIZE_10BIT
607 * @arg @ref LL_SSI_DATASIZE_11BIT
608 * @arg @ref LL_SSI_DATASIZE_12BIT
609 * @arg @ref LL_SSI_DATASIZE_13BIT
610 * @arg @ref LL_SSI_DATASIZE_14BIT
611 * @arg @ref LL_SSI_DATASIZE_15BIT
612 * @arg @ref LL_SSI_DATASIZE_16BIT
613 * @arg @ref LL_SSI_DATASIZE_17BIT
614 * @arg @ref LL_SSI_DATASIZE_18BIT
615 * @arg @ref LL_SSI_DATASIZE_19BIT
616 * @arg @ref LL_SSI_DATASIZE_20BIT
617 * @arg @ref LL_SSI_DATASIZE_21BIT
618 * @arg @ref LL_SSI_DATASIZE_22BIT
619 * @arg @ref LL_SSI_DATASIZE_23BIT
620 * @arg @ref LL_SSI_DATASIZE_24BIT
621 * @arg @ref LL_SSI_DATASIZE_25BIT
622 * @arg @ref LL_SSI_DATASIZE_26BIT
623 * @arg @ref LL_SSI_DATASIZE_27BIT
624 * @arg @ref LL_SSI_DATASIZE_28BIT
625 * @arg @ref LL_SSI_DATASIZE_29BIT
626 * @arg @ref LL_SSI_DATASIZE_30BIT
627 * @arg @ref LL_SSI_DATASIZE_31BIT
628 * @arg @ref LL_SSI_DATASIZE_32BIT
629 * @retval None
630 */
631 __STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
632 {
633 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_DFS32, size);
634 }
635
636 /**
637 * @brief Get frame data size
638 *
639 * Register|BitsName
640 * --------|--------
641 * CTRL0 | DFS32
642 *
643 * @param SPIx SPI instance
644 * @retval Returned value can be one of the following values:
645 * @arg @ref LL_SSI_DATASIZE_4BIT
646 * @arg @ref LL_SSI_DATASIZE_5BIT
647 * @arg @ref LL_SSI_DATASIZE_6BIT
648 * @arg @ref LL_SSI_DATASIZE_7BIT
649 * @arg @ref LL_SSI_DATASIZE_8BIT
650 * @arg @ref LL_SSI_DATASIZE_9BIT
651 * @arg @ref LL_SSI_DATASIZE_10BIT
652 * @arg @ref LL_SSI_DATASIZE_11BIT
653 * @arg @ref LL_SSI_DATASIZE_12BIT
654 * @arg @ref LL_SSI_DATASIZE_13BIT
655 * @arg @ref LL_SSI_DATASIZE_14BIT
656 * @arg @ref LL_SSI_DATASIZE_15BIT
657 * @arg @ref LL_SSI_DATASIZE_16BIT
658 * @arg @ref LL_SSI_DATASIZE_17BIT
659 * @arg @ref LL_SSI_DATASIZE_18BIT
660 * @arg @ref LL_SSI_DATASIZE_19BIT
661 * @arg @ref LL_SSI_DATASIZE_20BIT
662 * @arg @ref LL_SSI_DATASIZE_21BIT
663 * @arg @ref LL_SSI_DATASIZE_22BIT
664 * @arg @ref LL_SSI_DATASIZE_23BIT
665 * @arg @ref LL_SSI_DATASIZE_24BIT
666 * @arg @ref LL_SSI_DATASIZE_25BIT
667 * @arg @ref LL_SSI_DATASIZE_26BIT
668 * @arg @ref LL_SSI_DATASIZE_27BIT
669 * @arg @ref LL_SSI_DATASIZE_28BIT
670 * @arg @ref LL_SSI_DATASIZE_29BIT
671 * @arg @ref LL_SSI_DATASIZE_30BIT
672 * @arg @ref LL_SSI_DATASIZE_31BIT
673 * @arg @ref LL_SSI_DATASIZE_32BIT
674 */
675 __STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
676 {
677 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_DFS32));
678 }
679
680 /**
681 * @brief Set the length of the control word for the Microwire frame format
682 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
683 *
684 * Register|BitsName
685 * --------|--------
686 * CTRL0 | CFS
687 *
688 * @param SPIx SPI instance
689 * @param size This parameter can be one of the following values:
690 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
691 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
692 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
693 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
694 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
695 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
696 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
697 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
698 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
699 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
700 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
701 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
702 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
703 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
704 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
705 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
706 * @retval None
707 */
708 __STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
709 {
710 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_CFS, size);
711 }
712
713 /**
714 * @brief Get the length of the control word for the Microwire frame format
715 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
716 *
717 * Register|BitsName
718 * --------|--------
719 * CTRL0 | CFS
720 *
721 * @param SPIx SPI instance
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
724 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
725 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
726 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
727 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
728 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
729 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
730 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
731 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
732 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
733 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
734 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
735 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
736 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
737 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
738 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
739 */
740 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
741 {
742 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_CFS));
743 }
744
745 /**
746 * @brief Enable SPI test mode
747 *
748 * Register|BitsName
749 * --------|--------
750 * CTRL0 | SRL
751 *
752 * @param SPIx SPI instance
753 * @retval None
754 */
755 __STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
756 {
757 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
758 }
759
760 /**
761 * @brief Disable SPI test mode
762 *
763 * Register|BitsName
764 * --------|--------
765 * CTRL0 | SRL
766 *
767 * @param SPIx SPI instance
768 * @retval None
769 */
770 __STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
771 {
772 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
773 }
774
775 /**
776 * @brief Check if SPI test mode is enabled
777 *
778 * Register|BitsName
779 * --------|--------
780 * CTRL0 | SRL
781 *
782 * @param SPIx SPI instance
783 * @retval State of bit (1 or 0).
784 */
785 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
786 {
787 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SRL) == (SSI_CTRL0_SRL));
788 }
789
790 /**
791 * @brief Enable slave output
792 *
793 * Register|BitsName
794 * --------|--------
795 * CTRL0 | SLVOE
796 *
797 * @param SPIx SPI instance
798 * @retval None
799 */
800 __STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
801 {
802 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
803 }
804
805 /**
806 * @brief Disable slave output
807 *
808 * Register|BitsName
809 * --------|--------
810 * CTRL0 | SLVOE
811 *
812 * @param SPIx SPI instance
813 * @retval None
814 */
815 __STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
816 {
817 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
818 }
819
820 /**
821 * @brief Check if slave output is enabled
822 *
823 * Register|BitsName
824 * --------|--------
825 * CTRL0 | SLVOE
826 *
827 * @param SPIx SPI instance
828 * @retval State of bit (1 or 0).
829 */
830 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
831 {
832 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE) != (SSI_CTRL0_SLVOE));
833 }
834
835 /**
836 * @brief Set transfer direction mode
837 *
838 * Register|BitsName
839 * --------|--------
840 * CTRL0 | TMOD
841 *
842 * @param SPIx SPI instance
843 * @param transfer_direction This parameter can be one of the following values:
844 * @arg @ref LL_SSI_FULL_DUPLEX
845 * @arg @ref LL_SSI_SIMPLEX_TX
846 * @arg @ref LL_SSI_SIMPLEX_RX
847 * @arg @ref LL_SSI_READ_EEPROM
848 * @retval None
849 */
850 __STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
851 {
852 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_TMOD, transfer_direction);
853 }
854
855 /**
856 * @brief Get transfer direction mode
857 *
858 * Register|BitsName
859 * --------|--------
860 * CTRL0 | TMOD
861 *
862 * @param SPIx SPI instance
863 * @retval Returned value can be one of the following values:
864 * @arg @ref LL_SSI_FULL_DUPLEX
865 * @arg @ref LL_SSI_SIMPLEX_TX
866 * @arg @ref LL_SSI_SIMPLEX_RX
867 * @arg @ref LL_SSI_READ_EEPROM
868 */
869 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
870 {
871 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_TMOD));
872 }
873
874 /**
875 * @brief Set clock polarity
876 * @note This bit should not be changed when communication is ongoing.
877 * This bit is not used in SPI TI mode.
878 *
879 * Register|BitsName
880 * --------|--------
881 * CTRL0 | SCPOL
882 *
883 * @param SPIx SPI instance
884 * @param clock_polarity This parameter can be one of the following values:
885 * @arg @ref LL_SSI_SCPOL_LOW
886 * @arg @ref LL_SSI_SCPOL_HIGH
887 * @retval None
888 */
889 __STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
890 {
891 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPOL, clock_polarity);
892 }
893
894 /**
895 * @brief Get clock polarity
896 *
897 * Register|BitsName
898 * --------|--------
899 * CTRL0 | SCPOL
900 *
901 * @param SPIx SPI instance
902 * @retval Returned value can be one of the following values:
903 * @arg @ref LL_SSI_SCPOL_LOW
904 * @arg @ref LL_SSI_SCPOL_HIGH
905 */
906 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
907 {
908 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPOL));
909 }
910
911 /**
912 * @brief Set clock phase
913 * @note This bit should not be changed when communication is ongoing.
914 * This bit is not used in SPI TI mode.
915 *
916 * Register|BitsName
917 * --------|--------
918 * CTRL0 | SCPHA
919 *
920 * @param SPIx SPI instance
921 * @param clock_phase This parameter can be one of the following values:
922 * @arg @ref LL_SSI_SCPHA_1EDGE
923 * @arg @ref LL_SSI_SCPHA_2EDGE
924 * @retval None
925 */
926 __STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
927 {
928 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPHA, clock_phase);
929 }
930
931 /**
932 * @brief Get clock phase
933 *
934 * Register|BitsName
935 * --------|--------
936 * CTRL0 | SCPHA
937 *
938 * @param SPIx SPI instance
939 * @retval Returned value can be one of the following values:
940 * @arg @ref LL_SSI_SCPHA_1EDGE
941 * @arg @ref LL_SSI_SCPHA_2EDGE
942 */
943 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
944 {
945 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPHA));
946 }
947
948 /**
949 * @brief Set serial protocol used
950 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
951 *
952 * Register|BitsName
953 * --------|--------
954 * CTRL0 | FRF
955 *
956 * @param SPIx SPI instance
957 * @param standard This parameter can be one of the following values:
958 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
959 * @arg @ref LL_SSI_PROTOCOL_TI
960 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
961 * @retval None
962 */
963 __STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
964 {
965 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_FRF, standard);
966 }
967
968 /**
969 * @brief Get serial protocol used
970 *
971 * Register|BitsName
972 * --------|--------
973 * CTRL0 | FRF
974 *
975 * @param SPIx SPI instance
976 * @retval Returned value can be one of the following values:
977 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
978 * @arg @ref LL_SSI_PROTOCOL_TI
979 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
980 */
981 __STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
982 {
983 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_FRF));
984 }
985
986 /**
987 * @brief Set the number of data frames to be continuously received
988 * @note These bits should not be changed when communication is ongoing.
989 This bits are effect when TMOD = 2b10 or 2b11.
990 This bits are not effect in SPIS.
991 *
992 * Register|BitsName
993 * --------|--------
994 * CTRL1 | NDF
995 *
996 * @param SPIx SPI instance
997 * @param size This parameter can be one of the following values: 0 ~ 65535
998 * @retval None
999 */
1000 __STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
1001 {
1002 MODIFY_REG(SPIx->CTRL1, SSI_CTRL1_NDF, size);
1003 }
1004
1005 /**
1006 * @brief Get the number of data frames to be continuously received
1007 * @note These bits should not be changed when communication is ongoing.
1008 This bits are effect when TMOD = 2b10 or 2b11.
1009 This bits are not effect in SPIS.
1010 *
1011 * Register|BitsName
1012 * --------|--------
1013 * CTRL1 | NDF
1014 *
1015 * @param SPIx SPI instance
1016 * @retval Returned value can be one of the following values: 0 ~ 65535
1017 */
1018 __STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
1019 {
1020 return (uint32_t)(READ_BITS(SPIx->CTRL1, SSI_CTRL1_NDF));
1021 }
1022
1023 /**
1024 * @brief Enable SPI peripheral
1025 *
1026 * Register|BitsName
1027 * --------|--------
1028 * SSI_EN | EN
1029 *
1030 * @param SPIx SPI instance
1031 * @retval None
1032 */
1033 __STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
1034 {
1035 SET_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1036 }
1037
1038 /**
1039 * @brief Disable SPI peripheral
1040 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
1041 *
1042 * Register|BitsName
1043 * --------|--------
1044 * SSI_EN | EN
1045 *
1046 * @param SPIx SPI instance
1047 * @retval None
1048 */
1049 __STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
1050 {
1051 CLEAR_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1052 }
1053
1054 /**
1055 * @brief Check if SPI peripheral is enabled
1056 *
1057 * Register|BitsName
1058 * --------|--------
1059 * SSI_EN | EN
1060 *
1061 * @param SPIx SPI instance
1062 * @retval State of bit (1 or 0).
1063 */
1064 __STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
1065 {
1066 return (READ_BITS(SPIx->SSI_EN, SSI_SSIEN_EN) == (SSI_SSIEN_EN));
1067 }
1068
1069 /**
1070 * @brief Enable Handshake in Microwire mode
1071 *
1072 * Register|BitsName
1073 * --------|--------
1074 * MWC | MHS
1075 *
1076 * @param SPIx SPI instance
1077 * @retval None
1078 */
1079 __STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
1080 {
1081 SET_BITS(SPIx->MWC, SSI_MWC_MHS);
1082 }
1083
1084 /**
1085 * @brief Disable Handshake in Microwire mode
1086 *
1087 * Register|BitsName
1088 * --------|--------
1089 * MWC | MHS
1090 *
1091 * @param SPIx SPI instance
1092 * @retval None
1093 */
1094 __STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
1095 {
1096 CLEAR_BITS(SPIx->MWC, SSI_MWC_MHS);
1097 }
1098
1099 /**
1100 * @brief Check if Handshake in Microwire mode is enabled
1101 *
1102 * Register|BitsName
1103 * --------|--------
1104 * MWC | MHS
1105 *
1106 * @param SPIx SPI instance
1107 * @retval State of bit (1 or 0).
1108 */
1109 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
1110 {
1111 return (READ_BITS(SPIx->MWC, SSI_MWC_MHS) == (SSI_MWC_MHS));
1112 }
1113
1114 /**
1115 * @brief Set transfer direction mode in Microwire mode
1116 * @note This bit should not be changed when communication is ongoing.
1117 *
1118 * Register|BitsName
1119 * --------|--------
1120 * MWC | MDD
1121 *
1122 * @param SPIx SPI instance
1123 * @param transfer_direction This parameter can be one of the following values:
1124 * @arg @ref LL_SSI_MICROWIRE_RX
1125 * @arg @ref LL_SSI_MICROWIRE_TX
1126 * @retval None
1127 */
1128 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
1129 {
1130 MODIFY_REG(SPIx->MWC, SSI_MWC_MDD, transfer_direction);
1131 }
1132
1133 /**
1134 * @brief Get transfer direction mode in Microwire mode
1135 * @note This bit should not be changed when communication is ongoing.
1136 *
1137 * Register|BitsName
1138 * --------|--------
1139 * MWC | MDD
1140 *
1141 * @param SPIx SPI instance
1142 * @retval Returned value can be one of the following values:
1143 * @arg @ref LL_SSI_MICROWIRE_RX
1144 * @arg @ref LL_SSI_MICROWIRE_TX
1145 */
1146 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
1147 {
1148 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MDD));
1149 }
1150
1151 /**
1152 * @brief Set transfer mode in Microwire mode
1153 * @note This bit should not be changed when communication is ongoing.
1154 *
1155 * Register|BitsName
1156 * --------|--------
1157 * MWC | MWMOD
1158 *
1159 * @param SPIx SPI instance
1160 * @param transfer_mode This parameter can be one of the following values:
1161 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1162 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1163 * @retval None
1164 */
1165 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
1166 {
1167 MODIFY_REG(SPIx->MWC, SSI_MWC_MWMOD, transfer_mode);
1168 }
1169
1170 /**
1171 * @brief Get transfer mode in Microwire mode
1172 * @note This bit should not be changed when communication is ongoing.
1173 *
1174 * Register|BitsName
1175 * --------|--------
1176 * MWC | MWMOD
1177 *
1178 * @param SPIx SPI instance
1179 * @retval Returned value can be one of the following values:
1180 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1181 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1182 */
1183 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
1184 {
1185 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MWMOD));
1186 }
1187
1188 /**
1189 * @brief Enable slave select
1190 *
1191 * Register|BitsName
1192 * --------|--------
1193 * SE | SLAVE1
1194 * SE | SLAVE0
1195 *
1196 * @param SPIx SPI instance
1197 * @param ss This parameter can be one of the following values:
1198 * @arg @ref LL_SSI_SLAVE1
1199 * @arg @ref LL_SSI_SLAVE0
1200 * @retval None
1201 */
1202 __STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
1203 {
1204 SET_BITS(SPIx->SE, ss);
1205 }
1206
1207 /**
1208 * @brief Disable slave select
1209 *
1210 * Register|BitsName
1211 * --------|--------
1212 * SE | SLAVE1
1213 * SE | SLAVE0
1214 *
1215 * @param SPIx SPI instance
1216 * @param ss This parameter can be one of the following values:
1217 * @arg @ref LL_SSI_SLAVE1
1218 * @arg @ref LL_SSI_SLAVE0
1219 * @retval None
1220 */
1221 __STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
1222 {
1223 CLEAR_BITS(SPIx->SE, ss);
1224 }
1225
1226 /**
1227 * @brief Check if slave select is enabled
1228 *
1229 * Register|BitsName
1230 * --------|--------
1231 * SE | SLAVE1
1232 * SE | SLAVE0
1233 *
1234 * @param SPIx SPI instance
1235 * @param ss This parameter can be one of the following values:
1236 * @arg @ref LL_SSI_SLAVE1
1237 * @arg @ref LL_SSI_SLAVE0
1238 * @retval State of bit (1 or 0).
1239 */
1240 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
1241 {
1242 return (READ_BITS(SPIx->SE, ss) == ss);
1243 }
1244
1245 /**
1246 * @brief Set baud rate prescaler
1247 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1248 *
1249 * Register|BitsName
1250 * --------|--------
1251 * BAUD | SCKDIV
1252 *
1253 * @param SPIx SPI instance
1254 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1255 * @retval None
1256 */
1257 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
1258 {
1259 WRITE_REG(SPIx->BAUD, baud_rate);
1260 }
1261
1262 /**
1263 * @brief Get baud rate prescaler
1264 *
1265 * Register|BitsName
1266 * --------|--------
1267 * BAUD | SCKDIV
1268 *
1269 * @param SPIx SPI instance
1270 * @retval Returned value can be one even value between 2 and 65534.
1271 */
1272 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
1273 {
1274 return (uint32_t)(READ_BITS(SPIx->BAUD, SSI_BAUD_SCKDIV));
1275 }
1276
1277 /**
1278 * @brief Set threshold of TXFIFO that triggers an TXE event
1279 *
1280 * Register|BitsName
1281 * --------|--------
1282 * TXFTL | TFT
1283 *
1284 * @param SPIx SPI instance
1285 * @param threshold This parameter can be one of the following values: 0 ~ 7
1286 * @retval None
1287 */
1288 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1289 {
1290 WRITE_REG(SPIx->TX_FTL, threshold);
1291 }
1292
1293 /**
1294 * @brief Get threshold of TXFIFO that triggers an TXE event
1295 *
1296 * Register|BitsName
1297 * --------|--------
1298 * TXFTL | TFT
1299 *
1300 * @param SPIx SPI instance
1301 * @retval Returned value can be one of the following values: 0 ~ 7
1302 */
1303 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
1304 {
1305 return (uint32_t)(READ_BITS(SPIx->TX_FTL, SSI_TXFTL_TFT));
1306 }
1307
1308 /**
1309 * @brief Set threshold of RXFIFO that triggers an RXNE event
1310 *
1311 * Register|BitsName
1312 * --------|--------
1313 * RXFTL | RFT
1314 *
1315 * @param SPIx SPI instance
1316 * @param threshold This parameter can be one of the following values: 0 ~ 7
1317 * @retval None
1318 */
1319 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1320 {
1321 WRITE_REG(SPIx->RX_FTL, threshold);
1322 }
1323
1324 /**
1325 * @brief Get threshold of RXFIFO that triggers an RXNE event
1326 *
1327 * Register|BitsName
1328 * --------|--------
1329 * RXFTL | RFT
1330 *
1331 * @param SPIx SPI instance
1332 * @retval Returned value can be one of the following values: 0 ~ 7
1333 */
1334 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
1335 {
1336 return (uint32_t)(READ_BITS(SPIx->RX_FTL, SSI_RXFTL_RFT));
1337 }
1338
1339 /**
1340 * @brief Get FIFO Transmission Level
1341 *
1342 * Register|BitsName
1343 * --------|--------
1344 * TXFL | TXTFL
1345 *
1346 * @param SPIx SPI instance
1347 * @retval Returned value can be one of the following values: 0 ~ 8
1348 */
1349 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
1350 {
1351 return (uint32_t)(READ_BITS(SPIx->TX_FL, SSI_TXFL_TXTFL));
1352 }
1353
1354 /**
1355 * @brief Get FIFO reception Level
1356 *
1357 * Register|BitsName
1358 * --------|--------
1359 * RXFL | RXTFL
1360 *
1361 * @param SPIx SPI instance
1362 * @retval Returned value can be one of the following values: 0 ~ 8
1363 */
1364 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
1365 {
1366 return (uint32_t)(READ_BITS(SPIx->RX_FL, SSI_RXFL_RXTFL));
1367 }
1368
1369 /**
1370 * @brief Get ID code
1371 *
1372 * Register|BitsName
1373 * --------|--------
1374 * IDCODE | ID
1375 *
1376 * @param SPIx SPI instance
1377 * @retval Returned value is const.
1378 */
1379 __STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
1380 {
1381 return (uint32_t)(READ_BITS(SPIx->ID, SSI_IDCODE_ID));
1382 }
1383
1384 /**
1385 * @brief Get IP version
1386 *
1387 * Register|BitsName
1388 * --------|--------
1389 * COMP | VERSION
1390 *
1391 * @param SPIx SPI instance
1392 * @retval Returned value is const.
1393 */
1394 __STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
1395 {
1396 return (uint32_t)(READ_BITS(SPIx->VERSION_ID, SSI_COMP_VERSION));
1397 }
1398
1399 /** @} */
1400
1401 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1402 * @{
1403 */
1404
1405 /**
1406 * @brief Enable interrupt
1407 * @note This bit controls the generation of an interrupt when an event occurs.
1408 *
1409 * Register|BitsName
1410 * --------|--------
1411 * INTMASK | INTMASK
1412 *
1413 * @param SPIx SPI instance
1414 * @param mask This parameter can be one of the following values:
1415 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1416 * @arg @ref LL_SSI_IM_RXF
1417 * @arg @ref LL_SSI_IM_RXO
1418 * @arg @ref LL_SSI_IM_RXU
1419 * @arg @ref LL_SSI_IM_TXO
1420 * @arg @ref LL_SSI_IM_TXE
1421 * @retval None
1422 */
1423 __STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
1424 {
1425 SET_BITS(SPIx->INTMASK, mask);
1426 }
1427
1428 /**
1429 * @brief Disable interrupt
1430 * @note This bit controls the generation of an interrupt when an event occurs.
1431 *
1432 * Register|BitsName
1433 * --------|--------
1434 * INTMASK | INTMASK
1435 *
1436 * @param SPIx SPI instance
1437 * @param mask This parameter can be one of the following values:
1438 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1439 * @arg @ref LL_SSI_IM_RXF
1440 * @arg @ref LL_SSI_IM_RXO
1441 * @arg @ref LL_SSI_IM_RXU
1442 * @arg @ref LL_SSI_IM_TXO
1443 * @arg @ref LL_SSI_IM_TXE
1444 * @retval None
1445 */
1446 __STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
1447 {
1448 CLEAR_BITS(SPIx->INTMASK, mask);
1449 }
1450
1451 /**
1452 * @brief Check if interrupt is enabled
1453 *
1454 * Register|BitsName
1455 * --------|--------
1456 * INTMASK | INTMASK
1457 *
1458 * @param SPIx SPI instance
1459 * @param mask This parameter can be one of the following values:
1460 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1461 * @arg @ref LL_SSI_IM_RXF
1462 * @arg @ref LL_SSI_IM_RXO
1463 * @arg @ref LL_SSI_IM_RXU
1464 * @arg @ref LL_SSI_IM_TXO
1465 * @arg @ref LL_SSI_IM_TXE
1466 * @retval State of bit (1 or 0).
1467 */
1468 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
1469 {
1470 return (READ_BITS(SPIx->INTMASK, mask) == mask);
1471 }
1472
1473 /** @} */
1474
1475 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1476 * @{
1477 */
1478
1479 /**
1480 * @brief Get SPI status
1481 *
1482 * Register|BitsName
1483 * --------|--------
1484 * STAT | STAT
1485 *
1486 * @param SPIx SPI instance
1487 * @retval Returned value can be one or combination of the following values:
1488 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1489 * @arg @ref LL_SSI_SR_TXE
1490 * @arg @ref LL_SSI_SR_RFF
1491 * @arg @ref LL_SSI_SR_RFNE
1492 * @arg @ref LL_SSI_SR_TFE
1493 * @arg @ref LL_SSI_SR_TFNF
1494 * @arg @ref LL_SSI_SR_BUSY
1495 */
1496 __STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
1497 {
1498 return (uint32_t)(READ_REG(SPIx->STAT));
1499 }
1500
1501 /**
1502 * @brief Check active flag
1503 *
1504 * Register|BitsName
1505 * --------|--------
1506 * STAT | DCOL
1507 * STAT | TXE
1508 * STAT | RFF
1509 * STAT | RFNE
1510 * STAT | TFE
1511 * STAT | TFNF
1512 * STAT | BUSY
1513 *
1514 * @param SPIx SPI instance
1515 * @param flag This parameter can be one of the following values:
1516 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1517 * @arg @ref LL_SSI_SR_TXE
1518 * @arg @ref LL_SSI_SR_RFF
1519 * @arg @ref LL_SSI_SR_RFNE
1520 * @arg @ref LL_SSI_SR_TFE
1521 * @arg @ref LL_SSI_SR_TFNF
1522 * @arg @ref LL_SSI_SR_BUSY
1523 * @retval State of bit (1 or 0).
1524 */
1525 __STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
1526 {
1527 return (READ_BITS(SPIx->STAT, flag) == (flag));
1528 }
1529
1530 /**
1531 * @brief Get SPI interrupt flags
1532 *
1533 * Register|BitsName
1534 * --------|--------
1535 * INTSTAT | INTSTAT
1536 *
1537 * @param SPIx SPI instance
1538 * @retval Returned value can be one or combination of the following values:
1539 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1540 * @arg @ref LL_SSI_IS_RXF
1541 * @arg @ref LL_SSI_IS_RXO
1542 * @arg @ref LL_SSI_IS_RXU
1543 * @arg @ref LL_SSI_IS_TXO
1544 * @arg @ref LL_SSI_IS_TXE
1545 */
1546 __STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
1547 {
1548 return (uint32_t)(READ_REG(SPIx->INTSTAT));
1549 }
1550
1551 /**
1552 * @brief Check interrupt flag
1553 *
1554 * Register|BitsName
1555 * --------|--------
1556 * INTSTAT | MSTIS
1557 * INTSTAT | RXFIS
1558 * INTSTAT | RXOIS
1559 * INTSTAT | RXUIS
1560 * INTSTAT | TXOIS
1561 * INTSTAT | TXEIS
1562 *
1563 * @param SPIx SPI instance
1564 * @param flag This parameter can be one of the following values:
1565 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1566 * @arg @ref LL_SSI_IS_RXF
1567 * @arg @ref LL_SSI_IS_RXO
1568 * @arg @ref LL_SSI_IS_RXU
1569 * @arg @ref LL_SSI_IS_TXO
1570 * @arg @ref LL_SSI_IS_TXE
1571 * @retval State of bit (1 or 0).
1572 */
1573 __STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
1574 {
1575 return (READ_BITS(SPIx->INTSTAT, flag) == flag);
1576 }
1577
1578 /**
1579 * @brief Get SPI raw interrupt flags
1580 *
1581 * Register|BitsName
1582 * --------|--------
1583 * RAW_INTSTAT | RAW_INTSTAT
1584 *
1585 * @param SPIx SPI instance
1586 * @retval Returned value can be one or combination of the following values:
1587 * @arg @ref LL_SSI_RIS_MST(no effect in SPIS)
1588 * @arg @ref LL_SSI_RIS_RXF
1589 * @arg @ref LL_SSI_RIS_RXO
1590 * @arg @ref LL_SSI_RIS_RXU
1591 * @arg @ref LL_SSI_RIS_TXO
1592 * @arg @ref LL_SSI_RIS_TXE
1593 */
1594 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
1595 {
1596 return (uint32_t)(READ_REG(SPIx->RAW_INTSTAT));
1597 }
1598
1599 /**
1600 * @brief Clear transmit FIFO overflow error flag
1601 * @note Clearing this flag is done by reading TXOIC register
1602 *
1603 * Register|BitsName
1604 * --------|--------
1605 * TXOIC | TXOIC
1606 *
1607 * @param SPIx SPI instance
1608 * @retval None
1609 */
1610 __STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
1611 {
1612 __IOM uint32_t tmpreg;
1613 tmpreg = SPIx->TXOIC;
1614 (void) tmpreg;
1615 }
1616
1617 /**
1618 * @brief Clear receive FIFO overflow error flag
1619 * @note Clearing this flag is done by reading RXOIC register
1620 *
1621 * Register|BitsName
1622 * --------|--------
1623 * RXOIC | RXOIC
1624 *
1625 * @param SPIx SPI instance
1626 * @retval None
1627 */
1628 __STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
1629 {
1630 __IOM uint32_t tmpreg;
1631 tmpreg = SPIx->RXOIC;
1632 (void) tmpreg;
1633 }
1634
1635 /**
1636 * @brief Clear receive FIFO underflow error flag
1637 * @note Clearing this flag is done by reading RXUIC register
1638 *
1639 * Register|BitsName
1640 * --------|--------
1641 * RXUIC | RXUIC
1642 *
1643 * @param SPIx SPI instance
1644 * @retval None
1645 */
1646 __STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
1647 {
1648 __IOM uint32_t tmpreg;
1649 tmpreg = SPIx->RXUIC;
1650 (void) tmpreg;
1651 }
1652
1653 /**
1654 * @brief Clear multi-master error flag
1655 * @note Clearing this flag is done by reading MSTIC register
1656 *
1657 * Register|BitsName
1658 * --------|--------
1659 * MSTIC | MSTIC
1660 *
1661 * @param SPIx SPI instance
1662 * @retval None
1663 */
1664 __STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
1665 {
1666 __IOM uint32_t tmpreg;
1667 tmpreg = SPIx->MSTIC;
1668 (void) tmpreg;
1669 }
1670
1671 /**
1672 * @brief Clear all error flag
1673 * @note Clearing this flag is done by reading INTCLR register
1674 *
1675 * Register|BitsName
1676 * --------|--------
1677 * INTCLR | INTCLR
1678 *
1679 * @param SPIx SPI instance
1680 * @retval None
1681 */
1682 __STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
1683 {
1684 __IOM uint32_t tmpreg;
1685 tmpreg = SPIx->INTCLR;
1686 (void) tmpreg;
1687 }
1688
1689 /** @} */
1690
1691 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1692 * @{
1693 */
1694
1695 /**
1696 * @brief Enable DMA Tx
1697 *
1698 * Register|BitsName
1699 * --------|--------
1700 * DMAC | TDMAE
1701 *
1702 * @param SPIx SPI instance
1703 * @retval None
1704 */
1705 __STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
1706 {
1707 SET_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1708 }
1709
1710 /**
1711 * @brief Disable DMA Tx
1712 *
1713 * Register|BitsName
1714 * --------|--------
1715 * DMAC | TDMAE
1716 *
1717 * @param SPIx SPI instance
1718 * @retval None
1719 */
1720 __STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
1721 {
1722 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1723 }
1724
1725 /**
1726 * @brief Check if DMA Tx is enabled
1727 *
1728 * Register|BitsName
1729 * --------|--------
1730 * DMAC | TDMAE
1731 *
1732 * @param SPIx SPI instance
1733 * @retval State of bit (1 or 0).
1734 */
1735 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
1736 {
1737 return (READ_BITS(SPIx->DMAC, SSI_DMAC_TDMAE) == (SSI_DMAC_TDMAE));
1738 }
1739
1740 /**
1741 * @brief Enable DMA Rx
1742 *
1743 * Register|BitsName
1744 * --------|--------
1745 * DMAC | RDMAE
1746 *
1747 * @param SPIx SPI instance
1748 * @retval None
1749 */
1750 __STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
1751 {
1752 SET_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1753 }
1754
1755 /**
1756 * @brief Disable DMA Rx
1757 *
1758 * Register|BitsName
1759 * --------|--------
1760 * DMAC | RDMAE
1761 *
1762 * @param SPIx SPI instance
1763 * @retval None
1764 */
1765 __STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
1766 {
1767 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1768 }
1769
1770 /**
1771 * @brief Check if DMA Rx is enabled
1772 *
1773 * Register|BitsName
1774 * --------|--------
1775 * DMAC | RDMAE
1776 *
1777 * @param SPIx SPI instance
1778 * @retval State of bit (1 or 0).
1779 */
1780 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
1781 {
1782 return (READ_BITS(SPIx->DMAC, SSI_DMAC_RDMAE) == (SSI_DMAC_RDMAE));
1783 }
1784
1785 /**
1786 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
1787 *
1788 * Register|BitsName
1789 * --------|--------
1790 * DMATDL | DMATDL
1791 *
1792 * @param SPIx SPI instance
1793 * @param threshold This parameter can be one of the following values: 0 ~ 7
1794 * @retval None
1795 */
1796 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1797 {
1798 WRITE_REG(SPIx->DMA_TDL, threshold);
1799 }
1800
1801 /**
1802 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
1803 *
1804 * Register|BitsName
1805 * --------|--------
1806 * DMATDL | DMATDL
1807 *
1808 * @param SPIx SPI instance
1809 * @retval Returned value can be one of the following values: 0 ~ 7
1810 */
1811 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
1812 {
1813 return (uint32_t)(READ_BITS(SPIx->DMA_TDL, SSI_DMATDL_DMATDL));
1814 }
1815
1816 /**
1817 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
1818 *
1819 * Register|BitsName
1820 * --------|--------
1821 * DMARDL | DMARDL
1822 *
1823 * @param SPIx SPI instance
1824 * @param threshold This parameter can be one of the following values: 0 ~ 7
1825 * @retval None
1826 */
1827 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1828 {
1829 WRITE_REG(SPIx->DMA_RDL, threshold);
1830 }
1831
1832 /**
1833 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
1834 *
1835 * Register|BitsName
1836 * --------|--------
1837 * DMARDL | DMARDL
1838 *
1839 * @param SPIx SPI instance
1840 * @retval Returned value can be one of the following values: 0 ~ 7
1841 */
1842 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
1843 {
1844 return (uint32_t)(READ_BITS(SPIx->DMA_RDL, SSI_DMARDL_DMARDL));
1845 }
1846
1847 /** @} */
1848
1849 /** @defgroup SPI_LL_EF_Data_Management Data_Management
1850 * @{
1851 */
1852
1853 /**
1854 * @brief Write 8-Bits in the data register
1855 *
1856 * Register|BitsName
1857 * --------|--------
1858 * DATA | DATA
1859 *
1860 * @param SPIx SPI instance
1861 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
1862 * @retval None
1863 */
1864 __STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
1865 {
1866 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1867 }
1868
1869 /**
1870 * @brief Write 16-Bits in the data register
1871 *
1872 * Register|BitsName
1873 * --------|--------
1874 * DATA | DATA
1875 *
1876 * @param SPIx SPI instance
1877 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
1878 * @retval None
1879 */
1880 __STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
1881 {
1882 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1883 }
1884
1885 /**
1886 * @brief Write 32-Bits in the data register
1887 *
1888 * Register|BitsName
1889 * --------|--------
1890 * DATA | DATA
1891 *
1892 * @param SPIx SPI instance
1893 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1894 * @retval None
1895 */
1896 __STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
1897 {
1898 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1899 }
1900
1901 /**
1902 * @brief Read 8-Bits in the data register
1903 *
1904 * Register|BitsName
1905 * --------|--------
1906 * DATA | DATA
1907 *
1908 * @param SPIx SPI instance
1909 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
1910 */
1911 __STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
1912 {
1913 return (uint8_t)(READ_REG(SPIx->DATA));
1914 }
1915
1916 /**
1917 * @brief Read 16-Bits in the data register
1918 *
1919 * Register|BitsName
1920 * --------|--------
1921 * DATA | DATA
1922 *
1923 * @param SPIx SPI instance
1924 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
1925 */
1926 __STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
1927 {
1928 return (uint16_t)(READ_REG(SPIx->DATA));
1929 }
1930
1931 /**
1932 * @brief Read 32-Bits in the data register
1933 *
1934 * Register|BitsName
1935 * --------|--------
1936 * DATA | DATA
1937 *
1938 * @param SPIx SPI instance
1939 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1940 */
1941 __STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
1942 {
1943 return (uint32_t)(READ_REG(SPIx->DATA));
1944 }
1945
1946 /**
1947 * @brief Set Rx sample delay
1948 * @note This bit should not be changed when communication is ongoing.
1949 *
1950 * Register|BitsName
1951 * --------|--------
1952 * RX_SAMPLEDLY | RX_SAMPLEDLY
1953 *
1954 * @param SPIx SPI instance
1955 * @param delay This parameter can be one of the following values: 0 ~ 256
1956 * @retval None
1957 */
1958 __STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
1959 {
1960 WRITE_REG(SPIx->RX_SAMPLE_DLY, delay);
1961 }
1962
1963 /**
1964 * @brief Get Rx sample delay
1965 * @note This bit should not be changed when communication is ongoing.
1966 *
1967 * Register|BitsName
1968 * --------|--------
1969 * RX_SAMPLEDLY | RX_SAMPLEDLY
1970 *
1971 * @param SPIx SPI instance
1972 * @retval Returned value can be one of the following values: 0 ~ 256
1973 */
1974 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
1975 {
1976 return (uint32_t)(READ_REG(SPIx->RX_SAMPLE_DLY));
1977 }
1978
1979 /**
1980 * @brief Set number of wait cycles in Dual/Quad SPI mode
1981 * @note This bit should not be changed when communication is ongoing.
1982 *
1983 * Register|BitsName
1984 * --------|--------
1985 * SCTRL0 | WAITCYCLES
1986 *
1987 * @param SPIx SPI instance
1988 * @param wait_cycles This parameter can be one of the following values: 0 ~ 31
1989 * @retval None
1990 */
1991 __STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
1992 {
1993 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES, wait_cycles << SSI_SCTRL0_WAITCYCLES_Pos);
1994 }
1995
1996 /**
1997 * @brief Get number of wait cycles in Dual/Quad SPI mode
1998 * @note This bit should not be changed when communication is ongoing.
1999 *
2000 * Register|BitsName
2001 * --------|--------
2002 * SCTRL0 | WAITCYCLES
2003 *
2004 * @param SPIx SPI instance
2005 * @retval Returned value can be one of the following values: 0 ~ 31
2006 */
2007 __STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
2008 {
2009 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES) >> SSI_SCTRL0_WAITCYCLES_Pos);
2010 }
2011
2012 /**
2013 * @brief Set Dual/Quad SPI mode instruction length in bits
2014 * @note This bit should not be changed when communication is ongoing.
2015 *
2016 * Register|BitsName
2017 * --------|--------
2018 * SCTRL0 | INSTL
2019 *
2020 * @param SPIx SPI instance
2021 * @param size This parameter can be one of the following values:
2022 * @arg @ref LL_SSI_INSTSIZE_0BIT
2023 * @arg @ref LL_SSI_INSTSIZE_4BIT
2024 * @arg @ref LL_SSI_INSTSIZE_8BIT
2025 * @arg @ref LL_SSI_INSTSIZE_16BIT
2026 * @retval None
2027 */
2028 __STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
2029 {
2030 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL, size);
2031 }
2032
2033 /**
2034 * @brief Get Dual/Quad SPI mode instruction length in bits
2035 * @note This bit should not be changed when communication is ongoing.
2036 *
2037 * Register|BitsName
2038 * --------|--------
2039 * SCTRL0 | INSTL
2040 *
2041 * @param SPIx SPI instance
2042 * @retval Returned value can be one of the following values:
2043 * @arg @ref LL_SSI_INSTSIZE_0BIT
2044 * @arg @ref LL_SSI_INSTSIZE_4BIT
2045 * @arg @ref LL_SSI_INSTSIZE_8BIT
2046 * @arg @ref LL_SSI_INSTSIZE_16BIT
2047 */
2048 __STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
2049 {
2050 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL));
2051 }
2052
2053 /**
2054 * @brief Set Dual/Quad SPI mode address length in bits
2055 * @note This bit should not be changed when communication is ongoing.
2056 *
2057 * Register|BitsName
2058 * --------|--------
2059 * SCTRL0 | ADDRL
2060 *
2061 * @param SPIx SPI instance
2062 * @param size This parameter can be one of the following values:
2063 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2064 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2065 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2066 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2067 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2068 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2069 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2070 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2071 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2072 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2073 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2074 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2075 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2076 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2077 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2078 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2079 * @retval None
2080 */
2081 __STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
2082 {
2083 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL, size);
2084 }
2085
2086 /**
2087 * @brief Get Dual/Quad SPI mode address length in bits
2088 * @note This bit should not be changed when communication is ongoing.
2089 *
2090 * Register|BitsName
2091 * --------|--------
2092 * SCTRL0 | ADDRL
2093 *
2094 * @param SPIx SPI instance
2095 * @retval Returned value can be one of the following values:
2096 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2097 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2098 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2099 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2100 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2101 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2102 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2103 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2104 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2105 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2106 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2107 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2108 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2109 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2110 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2111 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2112 */
2113 __STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
2114 {
2115 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL));
2116 }
2117
2118 /**
2119 * @brief Set Dual/Quad SPI mode address and instruction transfer format
2120 * @note This bit should not be changed when communication is ongoing.
2121 *
2122 * Register|BitsName
2123 * --------|--------
2124 * SCTRL0 | TRANSTYPE
2125 *
2126 * @param SPIx SPI instance
2127 * @param format This parameter can be one of the following values:
2128 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2129 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2130 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2131 * @retval None
2132 */
2133 __STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
2134 {
2135 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE, format);
2136 }
2137
2138 /**
2139 * @brief Get Dual/Quad SPI mode address and instruction transfer format
2140 * @note This bit should not be changed when communication is ongoing.
2141 *
2142 * Register|BitsName
2143 * --------|--------
2144 * SCTRL0 | TRANSTYPE
2145 *
2146 * @param SPIx SPI instance
2147 * @retval Returned value can be one of the following values:
2148 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2149 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2150 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2151 */
2152 __STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
2153 {
2154 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE));
2155 }
2156
2157 /** @} */
2158
2159 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
2160 * @{
2161 */
2162
2163 /**
2164 * @brief De-initialize SSI registers (Registers restored to their default values).
2165 * @param SPIx SSI instance
2166 * @retval An error_status_t enumeration value:
2167 * - SUCCESS: SSI registers are de-initialized
2168 * - ERROR: SSI registers are not de-initialized
2169 */
2170 error_status_t ll_spim_deinit(ssi_regs_t *SPIx);
2171
2172 /**
2173 * @brief Initialize SPIM registers according to the specified
2174 * parameters in p_spi_init.
2175 * @param SPIx SSI instance
2176 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
2177 * information for the specified SPIM peripheral.
2178 * @retval An error_status_t enumeration value:
2179 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2180 * - ERROR: Problem occurred during SSI Registers initialization
2181 */
2182 error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
2183
2184 /**
2185 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
2186 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
2187 * whose fields will be set to default values.
2188 * @retval None
2189 */
2190 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
2191
2192 /** @} */
2193
2194 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
2195 * @{
2196 */
2197
2198 /**
2199 * @brief De-initialize SSI registers (Registers restored to their default values).
2200 * @param SPIx SSI instance
2201 * @retval An error_status_t enumeration value:
2202 * - SUCCESS: SSI registers are de-initialized
2203 * - ERROR: SSI registers are not de-initialized
2204 */
2205 error_status_t ll_spis_deinit(ssi_regs_t *SPIx);
2206
2207 /**
2208 * @brief Initialize SSI registers according to the specified
2209 * parameters in p_spi_init.
2210 * @param SPIx SSI instance
2211 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
2212 * information for the specified SPIS peripheral.
2213 * @retval An error_status_t enumeration value:
2214 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2215 * - ERROR: Problem occurred during SPI Registers initialization
2216 */
2217 error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
2218
2219 /**
2220 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
2221 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
2222 * whose fields will be set to default values.
2223 * @retval None
2224 */
2225 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
2226 /** @} */
2227
2228 /** @defgroup QSPI_LL_Init QSPI Initialization and de-initialization functions
2229 * @{
2230 */
2231
2232 /**
2233 * @brief De-initialize SSI registers (Registers restored to their default values).
2234 * @param SPIx SSI instance
2235 * @retval An error_status_t enumeration value:
2236 * - SUCCESS: SSI registers are de-initialized
2237 * - ERROR: SSI registers are not de-initialized
2238 */
2239 error_status_t ll_qspi_deinit(ssi_regs_t *SPIx);
2240
2241 /**
2242 * @brief Initialize SSI registers according to the specified
2243 * parameters in SPI_InitStruct.
2244 * @param SPIx SSI instance
2245 * @param p_spi_init Pointer to a ll_qspi_init_t structure that contains the configuration
2246 * information for the specified QSPI peripheral.
2247 * @retval An error_status_t enumeration value:
2248 * - SUCCESS: SPI registers are initialized according to p_spi_init content
2249 * - ERROR: Problem occurred during SPI Registers initialization
2250 */
2251 error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init);
2252
2253 /**
2254 * @brief Set each field of a @ref ll_qspi_init_t type structure to default value.
2255 * @param p_spi_init Pointer to a @ref ll_qspi_init_t structure
2256 * whose fields will be set to default values.
2257 * @retval None
2258 */
2259 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
2260
2261 /** @} */
2262
2263 /** @} */
2264
2265 #endif /* SPIM || SPIS || QSPI0 || QSPI1 */
2266
2267 #ifdef __cplusplus
2268 }
2269 #endif
2270
2271 #endif /* __GR55xx_LL_SPI_H__ */
2272
2273 /** @} */
2274
2275 /** @} */
2276
2277 /** @} */
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr55xx_ll_spi.h:531
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1183
ll_spis_deinit
error_status_t ll_spis_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1079
ll_spim_init
error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1094
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_spi.h:1468
_ll_spis_init_t
SPIS init structures definition.
Definition: gr55xx_ll_spi.h:114
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1911
ll_spi_get_wait_cycles
__STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
Get number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:2007
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Specifies the SPI data width.
Definition: gr55xx_ll_spi.h:115
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1827
_ll_qspi_init_t::instruction_size
uint32_t instruction_size
Specifies the QSPI instruction width.
Definition: gr55xx_ll_spi.h:142
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
Clear all error flag.
Definition: gr55xx_ll_spi.h:1682
ll_spi_get_frame_format
__STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
Get data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:586
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr55xx_ll_spi.h:1974
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr55xx_ll_spi.h:77
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_spi.h:1573
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr55xx_ll_spi.h:515
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_spi.h:1958
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_spi.h:1364
_ll_qspi_init_t::address_size
uint32_t address_size
Specifies the QSPI address width.
Definition: gr55xx_ll_spi.h:147
ll_qspi_init_t
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_spi.h:889
_ll_qspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:167
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1000
_ll_qspi_init_t::inst_addr_transfer_format
uint32_t inst_addr_transfer_format
Specifies the QSPI instruction and address transfer format.
Definition: gr55xx_ll_spi.h:152
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1288
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_spi.h:1780
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_spi.h:1064
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr55xx_ll_spi.h:770
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:88
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_spi.h:1272
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:120
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_spi.h:830
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_spi.h:1446
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr55xx_ll_spi.h:869
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
Get SPI status.
Definition: gr55xx_ll_spi.h:1496
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1018
_ll_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_ll_spi.h:183
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1628
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1334
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_spi.h:631
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
_ll_qspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:172
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_spi.h:103
ll_spi_set_address_size
__STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2081
ll_spis_init
error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_spi.h:963
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1303
_ll_qspi_init_t
QSPI init structures definition.
Definition: gr55xx_ll_spi.h:136
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Specifies the SPI unidirectional or bidirectional data mode.
Definition: gr55xx_ll_spi.h:78
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1165
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Specifies the SPI data size.
Definition: gr55xx_ll_spi.h:83
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr55xx_ll_spi.h:1705
ll_spi_set_add_inst_transfer_format
__STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2133
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr55xx_ll_spi.h:1765
ll_qspi_deinit
error_status_t ll_qspi_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_id_code
__STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
Get ID code.
Definition: gr55xx_ll_spi.h:1379
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_spi.h:1349
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1319
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1146
ll_spi_get_instruction_size
__STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2048
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_spi.h:1033
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:1842
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1941
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:740
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr55xx_ll_spi.h:755
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_spi.h:1221
ll_spi_get_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2152
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_spi.h:1594
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:708
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
Get clock polarity.
Definition: gr55xx_ll_spi.h:906
ll_spi_set_frame_format
__STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:567
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:1896
_ll_spim_init_t::slave_select
uint32_t slave_select
Specifies the SPI slave select.
Definition: gr55xx_ll_spi.h:98
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1610
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
Get serial protocol used.
Definition: gr55xx_ll_spi.h:981
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_spi.h:1423
ll_spi_set_instruction_size
__STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2028
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr55xx_ll_spi.h:1720
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
Get frame data size.
Definition: gr55xx_ll_spi.h:675
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_spi.h:1546
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_spi.h:1049
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1926
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:1864
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_spi.h:1664
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_spi.h:1525
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_spi.h:785
_ll_qspi_init_t::transfer_direction
uint32_t transfer_direction
Specifies the QSPI transfer or receive mode.
Definition: gr55xx_ll_spi.h:137
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:125
_ll_qspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_spi.h:177
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:93
ll_spi_get_version
__STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
Get IP version.
Definition: gr55xx_ll_spi.h:1394
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_spi.h:547
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_spi.h:850
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_spi.h:926
ll_spi_set_wait_cycles
__STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:1991
_ll_qspi_init_t::wait_cycles
uint32_t wait_cycles
Specifies the QSPI dummy clock.
Definition: gr55xx_ll_spi.h:157
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_spi.h:1109
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr55xx_ll_spi.h:1750
ll_spim_deinit
error_status_t ll_spim_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1811
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_spi.h:1257
ll_qspi_struct_init
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1128
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:1796
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_spi.h:1646
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_spi.h:1735
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_spi.h:1202
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
Disable slave output.
Definition: gr55xx_ll_spi.h:815
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
Enable slave output.
Definition: gr55xx_ll_spi.h:800
_ll_qspi_init_t::data_size
uint32_t data_size
Specifies the SPI data width.
Definition: gr55xx_ll_spi.h:162
ll_spi_get_address_size
__STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2113
ll_qspi_init
error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:1880
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_spi.h:1240
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
Get clock phase.
Definition: gr55xx_ll_spi.h:943