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52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
221 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
222 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
223 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U)
224 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
230 #define DMA_REQUEST_SPIM_TX LL_DMA_PERIPH_SPIM_TX
231 #define DMA_REQUEST_SPIM_RX LL_DMA_PERIPH_SPIM_RX
232 #define DMA_REQUEST_SPIS_TX LL_DMA_PERIPH_SPIS_TX
233 #define DMA_REQUEST_SPIS_RX LL_DMA_PERIPH_SPIS_RX
234 #define DMA_REQUEST_QSPI0_TX LL_DMA_PERIPH_QSPI0_TX
235 #define DMA_REQUEST_QSPI0_RX LL_DMA_PERIPH_QSPI0_RX
236 #define DMA_REQUEST_I2C0_TX LL_DMA_PERIPH_I2C0_TX
237 #define DMA_REQUEST_I2C0_RX LL_DMA_PERIPH_I2C0_RX
238 #define DMA_REQUEST_I2C1_TX LL_DMA_PERIPH_I2C1_TX
239 #define DMA_REQUEST_I2C1_RX LL_DMA_PERIPH_I2C1_RX
240 #define DMA_REQUEST_I2S_S_TX LL_DMA_PERIPH_I2S_S_TX
241 #define DMA_REQUEST_I2S_S_RX LL_DMA_PERIPH_I2S_S_RX
242 #define DMA_REQUEST_UART0_TX LL_DMA_PERIPH_UART0_TX
243 #define DMA_REQUEST_UART0_RX LL_DMA_PERIPH_UART0_RX
244 #define DMA_REQUEST_QSPI1_TX LL_DMA_PERIPH_QSPI1_TX
245 #define DMA_REQUEST_QSPI1_RX LL_DMA_PERIPH_QSPI1_RX
246 #define DMA_REQUEST_I2S_M_TX LL_DMA_PERIPH_I2S_M_TX
247 #define DMA_REQUEST_I2S_M_RX LL_DMA_PERIPH_I2S_M_RX
248 #define DMA_REQUEST_SNSADC LL_DMA_PERIPH_SNSADC
249 #define DMA_REQUEST_MEM LL_DMA_PERIPH_MEM
255 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
256 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
257 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
258 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH
264 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT
265 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT
266 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE
272 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT
273 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT
274 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE
280 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE
281 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD
282 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD
288 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE
289 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD
290 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD
296 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK
297 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
304 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0
305 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_2
306 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_5
307 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_7
321 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
322 ((__instance__) == DMA_Channel1) || \
323 ((__instance__) == DMA_Channel2) || \
324 ((__instance__) == DMA_Channel3) || \
325 ((__instance__) == DMA_Channel4) || \
326 ((__instance__) == DMA_Channel5) || \
327 ((__instance__) == DMA_Channel6) || \
328 ((__instance__) == DMA_Channel7))
334 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA_REQUEST_SPIM_TX) || \
335 ((__REQUEST__) == DMA_REQUEST_SPIM_RX) || \
336 ((__REQUEST__) == DMA_REQUEST_SPIS_TX) || \
337 ((__REQUEST__) == DMA_REQUEST_SPIS_RX) || \
338 ((__REQUEST__) == DMA_REQUEST_QSPI0_TX) || \
339 ((__REQUEST__) == DMA_REQUEST_QSPI0_RX) || \
340 ((__REQUEST__) == DMA_REQUEST_I2C0_TX) || \
341 ((__REQUEST__) == DMA_REQUEST_I2C0_RX) || \
342 ((__REQUEST__) == DMA_REQUEST_I2C1_TX) || \
343 ((__REQUEST__) == DMA_REQUEST_I2C1_RX) || \
344 ((__REQUEST__) == DMA_REQUEST_I2S_S_TX) || \
345 ((__REQUEST__) == DMA_REQUEST_I2S_S_RX) || \
346 ((__REQUEST__) == DMA_REQUEST_UART0_TX) || \
347 ((__REQUEST__) == DMA_REQUEST_UART0_RX) || \
348 ((__REQUEST__) == DMA_REQUEST_QSPI1_TX) || \
349 ((__REQUEST__) == DMA_REQUEST_QSPI1_RX) || \
350 ((__REQUEST__) == DMA_REQUEST_I2S_M_TX) || \
351 ((__REQUEST__) == DMA_REQUEST_I2S_M_RX) || \
352 ((__REQUEST__) == DMA_REQUEST_SNSADC) || \
353 ((__REQUEST__) == DMA_REQUEST_MEM))
359 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
360 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
361 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
362 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
368 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF))
374 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
375 ((__STATE__) == DMA_SRC_DECREMENT) || \
376 ((__STATE__) == DMA_SRC_NO_CHANGE))
382 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
383 ((__STATE__) == DMA_DST_DECREMENT) || \
384 ((__STATE__) == DMA_DST_NO_CHANGE))
390 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
391 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
392 ((__SIZE__) == DMA_SDATAALIGN_WORD))
398 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
399 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
400 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
406 #define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_NORMAL ) || \
407 ((__MODE__) == DMA_CIRCULAR))
413 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
414 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
415 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
416 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
@ HAL_DMA_XFER_TFR_CB_ID
Full transfer
hal_lock_t
HAL Lock structures definition.
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
@ HAL_DMA_STATE_TIMEOUT
DMA timeout state
DMA Configuration Structure definition.
__IO uint32_t error_code
DMA Error code
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
HAL DMA State Enumerations definition.
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled.
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
@ HAL_DMA_STATE_READY
DMA process success and ready for use
uint32_t dst_increment
Specifies whether the destination address register should be incremented or decrement or not.
dma_init_t init
DMA communication parameters
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
DMA block complete callback
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
uint32_t retention[5]
DMA important register information.
Header file containing functions prototypes of DMA LL library.
uint32_t priority
Specifies the software priority for the DMA Channel.
@ HAL_DMA_XFER_ABORT_CB_ID
Abort
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
@ HAL_DMA_XFER_ALL_CB_ID
All
uint32_t dst_request
Specifies the destination request selected for the specified channel.
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep.
__IO hal_dma_state_t state
DMA transfer state
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
void(* xfer_error_callback)(struct _dma_handle *p_dma)
DMA transfer error callback
@ HAL_DMA_XFER_BLK_CB_ID
Block transfer
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
@ HAL_DMA_STATE_ERROR
DMA error state
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
DMA transfer complete callback
@ HAL_DMA_STATE_BUSY
DMA process is ongoing
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
DMA transfer abort callback
struct _dma_init dma_init_t
DMA Configuration Structure definition.
hal_status_t
HAL Status structures definition.
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
uint32_t mode
Specifies the operation mode of the DMA Channel(Normal or Circular).
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
dma_channel_t channel
DMA Channel Number
uint32_t dst_data_alignment
Specifies the destination data width.
hal_lock_t lock
DMA locking object
void * p_parent
Parent object state
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
@ HAL_DMA_XFER_ERROR_CB_ID
Error
@ HAL_DMA_STATE_RESET
DMA not yet initialized or disabled.
uint32_t src_request
Specifies the source request selected for the specified channel.
uint32_t src_data_alignment
Specifies the source data width.
DMA handle Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
HAL DMA Channel Enumerations definition.
uint32_t src_increment
Specifies whether the srouce address register should be incremented or decrement or not.