gr55xx_ll_i2c.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2c.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2C LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2C I2C
47 * @brief I2C LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2C0) || defined (I2C1)
63
64 /** @defgroup I2C_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2C_LL_ES_INIT I2C Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2C init Structure definition
75 */
76 typedef struct _ll_i2c_init
77 {
78 uint32_t speed; /**< Specifies the transfer speed. See @ref I2C_LL_EC_SPEED. */
79
80 uint32_t own_address; /**< Specifies the device own address.
81 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
82
83 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
84
85 uint32_t own_addr_size; /**< Specifies the device own address 1 size (7-bit or 10-bit).
86 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS
87
88 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
89 } ll_i2c_init_t;
90
91 /** @} */
92
93 /** @} */
94
95 /**
96 * @defgroup I2C_LL_MACRO Defines
97 * @{
98 */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
102 * @{
103 */
104
105 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
106 * @brief Flags definitions which can be used with LL_I2C_ReadReg function
107 * @{
108 */
109 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt flag */
110 #define LL_I2C_INTR_STAT_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt flag */
111 #define LL_I2C_INTR_STAT_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt flag */
112 #define LL_I2C_INTR_STAT_START_DET I2C_INTR_START_DET /**< START_DET interrupt flag */
113 #define LL_I2C_INTR_STAT_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt flag */
114 #define LL_I2C_INTR_STAT_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt flag */
115 #define LL_I2C_INTR_STAT_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt flag */
116 #define LL_I2C_INTR_STAT_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt flag */
117 #define LL_I2C_INTR_STAT_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt flag */
118 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt flag */
119 #define LL_I2C_INTR_STAT_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt flag */
120 #define LL_I2C_INTR_STAT_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt flag */
121 #define LL_I2C_INTR_STAT_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt flag */
122 #define LL_I2C_INTR_STAT_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt flag */
123
124 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT /**< Transfer abort detected by master */
125 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT /**< Transfer abort detected by master */
126 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX /**< Slave trying to transmit to remote master in read mode */
127 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST /**< Slave lost arbitration to remote master */
128 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO /**< Slave flushes existing data in TX-FIFO upon getting read command */
129 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST /**< Master or Slave Transmitter lost arbitration */
130 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABRT_SRC_MST_DIS /**< User intitating master operation when MASTER disabled */
131 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT /**< Master trying to read in 10-Bit addressing mode when RESTART disabled */
132 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT /**< User trying to send START byte when RESTART disabled */
133 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT /**< User trying to swidth Master to HS mode when RESTART disabled */
134 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET /**< ACK detected for START byte */
135 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET /**< HS Master code is ACKed in HS Mode */
136 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ /**< GCALL is followed by read from bus */
137 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK /**< GCALL is not ACKed by any slave */
138 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK /**< Transmitted data is not ACKed by addressed slave */
139 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK /**< Byte 2 of 10-Bit Address is not ACKed by any slave */
140 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK /**< Byte 1 of 10-Bit Address is not ACKed by any slave */
141 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK /**< 7Bit Address is not ACKed by any slave */
142 /** @} */
143
144 /** @defgroup I2C_LL_EC_IT IT Defines
145 * @brief Interrupt definitions which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
146 * @{
147 */
148 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt */
149 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt */
150 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt */
151 #define LL_I2C_INTR_MASK_START_DET I2C_INTR_START_DET /**< START_DET interrupt */
152 #define LL_I2C_INTR_MASK_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt */
153 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt */
154 #define LL_I2C_INTR_MASK_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt */
155 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt */
156 #define LL_I2C_INTR_MASK_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt */
157 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt */
158 #define LL_I2C_INTR_MASK_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt */
159 #define LL_I2C_INTR_MASK_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt */
160 #define LL_I2C_INTR_MASK_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt */
161 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt */
162
163 #define LL_I2C_INTR_MASK_ALL 0x00000FFFU /**< All interrupt */
164 /** @} */
165
166 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
167 * @{
168 */
169 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /**< Master operates in 7-bit addressing mode. */
170 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CON_10BITADDR_MST /**< Master operates in 10-bit addressing mode.*/
171 /** @} */
172
173 /** @defgroup I2C_LL_EC_OWNADDRESS Own Address Length
174 * @{
175 */
176 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U /**< Own address 1 is a 7-bit address. */
177 #define LL_I2C_OWNADDRESS_10BIT I2C_CON_10BITADDR_SLV /**< Own address 1 is a 10-bit address.*/
178 /** @} */
179
180
181 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
182 * @{
183 */
184 #define LL_I2C_CMD_SLV_NONE 0x00000000U /**< Slave No command. */
185 #define LL_I2C_CMD_MST_WRITE 0x00000000U /**< Master write command. */
186 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD /**< Master read command. */
187 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP /**< Master issue STOP after this command. */
188 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART /**< Master issue RESTART before this command. */
189 /** @} */
190
191 /** @defgroup I2C_LL_EC_SPEED_MODE Transfer Speed Mode
192 * @{
193 */
194 #define LL_I2C_SPEED_MODE_STANDARD I2C_CON_SPEED_STANDARD /**< Standard Speed mode(0 to 100 Kb/s) of operation. */
195 #define LL_I2C_SPEED_MODE_FAST I2C_CON_SPEED_FAST /**< Fast (鈮?400 Kb/s) or Fast Plus mode (鈮?1000 螝b/s) of operation. */
196 #define LL_I2C_SPEED_MODE_HIGH I2C_CON_SPEED_HIGH /**< High Speed mode (鈮?3.4 Mb/s) of operation. */
197 /** @} */
198
199 /** @defgroup I2C_LL_EC_SPEED Transfer Speed
200 * @{
201 */
202 #define LL_I2C_SPEED_100K (100000ul) /**< Standard Speed. */
203 #define LL_I2C_SPEED_400K (400000ul) /**< Fast Speed. */
204 #define LL_I2C_SPEED_1000K (1000000ul) /**< Fast Plus Speed. */
205 #define LL_I2C_SPEED_2000K (2000000ul) /**< High Speed. */
206 /** @} */
207
208 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
209 * @{
210 */
211 #define LL_I2C_DIRECTION_NONE 0x00000000U /**< No transfer request by master. */
212 #define LL_I2C_DIRECTION_WRITE I2C_INTR_RX_FULL /**< Write transfer request by master, slave enters receiver mode. */
213 #define LL_I2C_DIRECTION_READ I2C_INTR_RD_REQ /**< Read transfer request by master, slave enters transmitter mode.*/
214 #define LL_I2C_DIRECTION_ERROR I2C_INTR_RX_FULL | I2C_INTR_RD_REQ /**< Transfer request error. */
215 /** @} */
216
217
218 /** @defgroup I2C_LL_EC_TX_FIFO_TH TX FIFO Threshold
219 * @{
220 */
221 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
222 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U /**< 1 character in TX FIFO */
223 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U /**< 2 characters in TX FIFO */
224 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U /**< 3 characters in TX FIFO */
225 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U /**< 4 characters in TX FIFO */
226 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U /**< 5 characters in TX FIFO */
227 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U /**< 6 characters in TX FIFO */
228 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U /**< 7 characters in TX FIFO */
229 /** @} */
230
231 /** @defgroup I2C_LL_EC_RX_FIFO_TH RX FIFO Threshold
232 * @{
233 */
234 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
235 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in RX FIFO */
236 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U /**< 3 characters in RX FIFO */
237 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U /**< 4 characters in RX FIFO */
238 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U /**< 5 characters in RX FIFO */
239 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U /**< 6 characters in RX FIFO */
240 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U /**< 7 characters in RX FIFO */
241 #define LL_I2C_RX_FIFO_TH_FULL 0x00000007U /**< RX FIFO full */
242 /** @} */
243
244 /** @defgroup I2C_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
245 * @{
246 */
247
248 /**
249 * @brief LL I2C InitStrcut default configuartion
250 */
251 #define LL_I2C_DEFAULT_CONFIG \
252 { \
253 .speed = LL_I2C_SPEED_400K, \
254 .own_address = 0x55U, \
255 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
256 }
257 /** @} */
258
259 /** @} */
260
261 /* Exported macro ------------------------------------------------------------*/
262 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
263 * @{
264 */
265
266 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
267 * @{
268 */
269
270 /**
271 * @brief Write a value in I2C register
272 * @param __instance__ I2C instance
273 * @param __REG__ Register to be written
274 * @param __VALUE__ Value to be written in the register
275 * @retval None.
276 */
277 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
278
279 /**
280 * @brief Read a value in I2C register
281 * @param __instance__ I2C instance
282 * @param __REG__ Register to be read
283 * @retval Register value
284 */
285 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
286 /** @} */
287
288 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
289 * @{
290 */
291
292 /**
293 * @brief Compute CLK_SSL_CNT value according to Peripheral Clock and expected Speed.
294 * @param __PERIPHCLK__ Peripheral Clock frequency used for I2C instance
295 * @param __SPEED__ Speed value to achieve
296 * @retval CLK_SSL_CNT value to be used for XS_SCL_HCNT, XS_SCL_LCNT registers where X can be (S, F, H)
297 */
298 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
299
300 /**
301 * @brief Get Speed Mode according to expected Speed.
302 * @param __SPEED__ Speed value to achieve
303 * @retval Returned value can be one of the following values:
304 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
305 * @arg @ref LL_I2C_SPEED_MODE_FAST
306 * @arg @ref LL_I2C_SPEED_MODE_HIGH
307 */
308 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
309 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
310 /** @} */
311
312 /** @} */
313
314 /** @} */
315
316 /* Private types -------------------------------------------------------------*/
317 /* Private variables ---------------------------------------------------------*/
318 /* Private constants ---------------------------------------------------------*/
319 /* Private macros ------------------------------------------------------------*/
320
321 /* Exported functions --------------------------------------------------------*/
322 /** @defgroup I2C_LL_DRIVER_FUNCTIONS Functions
323 * @{
324 */
325
326 /** @defgroup I2C_LL_EF_Configuration Configuration
327 * @{
328 */
329
330 /**
331 * @brief Enable I2C peripheral (ENABLE = 1).
332 *
333 * Register|BitsName
334 * --------|--------
335 * IC_ENABLE | ENABLE
336 *
337 * @param I2Cx I2C instance.
338 * @retval None.
339 */
340 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
341 {
342 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
343 }
344
345 /**
346 * @brief Disable I2C peripheral (ENABLE = 0).
347 * @note When ENABLE = 0, the TX FIFO and RX FIFO get flushed.
348 * Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state.
349 * If the module is transmitting, it stops as well as deletes the contents of the transmit buffer
350 * after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops
351 * the current transfer at the end of the current byte and does not acknowledge the transfer..
352 *
353 * Register|BitsName
354 * --------|--------
355 * IC_ENABLE | ENABLE
356 *
357 * @param I2Cx I2C instance.
358 * @retval None.
359 */
360 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
361 {
362 CLEAR_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
363 }
364
365 /**
366 * @brief Check if the I2C peripheral is enabled or disabled.
367 *
368 * Register|BitsName
369 * --------|--------
370 * IC_ENABLE_STATUS | IC_EN
371 *
372 * @param I2Cx I2C instance.
373 * @retval State of bit (1 or 0).
374 */
375 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
376 {
377 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_IC_EN) == (I2C_ENABLE_STATUS_IC_EN));
378 }
379
380 /**
381 * @brief Enable I2C master mode.
382 *
383 * Register|BitsName
384 * --------|--------
385 * IC_CON | MASTER_ENABLE
386 * IC_CON | SLAVE_DISABLE
387 * @param I2Cx I2C instance.
388 * @retval None.
389 */
390 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
391 {
392 SET_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
393 }
394
395 /**
396 * @brief Disable I2C master mode and enable slave mode.
397 *
398 * Register|BitsName
399 * --------|--------
400 * IC_CON | MASTER_ENABLE
401 * IC_CON | SLAVE_DISABLE
402 * @param I2Cx I2C instance.
403 * @retval None.
404 */
405 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
406 {
407 CLEAR_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
408 }
409
410 /**
411 * @brief Check if I2C master mode is enabled or disabled.
412 *
413 * Register|BitsName
414 * --------|--------
415 * IC_CON | MASTER_ENABLE
416 * IC_CON | SLAVE_DISABLE
417 *
418 * @param I2Cx I2C instance.
419 * @retval State of bit (1 or 0).
420 */
421 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
422 {
423 return (READ_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS) == (I2C_CON_MST_MODE | I2C_CON_SLV_DIS));
424 }
425
426 /**
427 * @brief Enable General Call(slave mode).
428 * @note When enabled, the Address 0x00 is ACKed.
429 *
430 * Register|BitsName
431 * --------|--------
432 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
433 *
434 * @param I2Cx I2C instance.
435 * @retval None.
436 */
437 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
438 {
439 SET_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
440 }
441
442 /**
443 * @brief Disable General Call(slave mode).
444 * @note When disabled, the Address 0x00 is NACKed.
445 *
446 * Register|BitsName
447 * --------|--------
448 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
449 *
450 * @param I2Cx I2C instance.
451 * @retval None.
452 */
453 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
454 {
455 CLEAR_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
456 }
457
458 /**
459 * @brief Check if General Call is enabled or disabled(slave mode).
460 *
461 * Register|BitsName
462 * --------|--------
463 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
464 *
465 * @param I2Cx I2C instance.
466 * @retval State of bit (1 or 0).
467 */
468 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
469 {
470 return (READ_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC) == (I2C_ACK_GENERAL_CALL_ACK_GC));
471 }
472
473 /**
474 * @brief Enable Master Restart.
475 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
476 * This bit determines whether RESTART conditions may be sent when acting as a master.
477 * Some older slaves do not support handling RESTART conditions.
478 * When RESTART is disabled, the master is prohibited from performing the following functions:
479 * - Performing any high-speed mode operation.
480 * - Performing direction changes in combined format mode.
481 * - Performing a read operation with a 10-bit address.
482 *
483 * Register|BitsName
484 * --------|--------
485 * IC_CON | CON_RESTART_EN
486 *
487 * @param I2Cx I2C instance.
488 * @retval None.
489 */
490 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
491 {
492 SET_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
493 }
494
495 /**
496 * @brief Disable Master Restart.
497 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
498 *
499 * Register|BitsName
500 * --------|--------
501 * IC_CON | CON_RESTART_EN
502 *
503 * @param I2Cx I2C instance.
504 * @retval None.
505 */
506 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
507 {
508 CLEAR_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
509 }
510
511 /**
512 * @brief Check if Master Restart is enabled or disabled.
513 *
514 * Register|BitsName
515 * --------|--------
516 * IC_CON | CON_RESTART_EN
517 *
518 * @param I2Cx I2C instance.
519 * @retval State of bit (1 or 0).
520 */
521 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
522 {
523 return (READ_BITS(I2Cx->CON, I2C_CON_RESTART_EN) == (I2C_CON_RESTART_EN));
524 }
525
526 /**
527 * @brief Enable Slave issues STOP_DET interrupt only if addressed function.
528 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
529 * During a general call address, the slave does not issue the STOP_DET interrupt if
530 * STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address
531 * by generating ACK. The STOP_DET interrupt is generated only when the transmitted
532 * address matches the slave address (SAR).
533 *
534 * Register|BitsName
535 * --------|--------
536 * IC_CON | STOP_DET_IF_ADDRESSED
537 *
538 * @param I2Cx I2C instance.
539 * @retval None.
540 */
541 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
542 {
543 SET_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
544 }
545
546 /**
547 * @brief Disable Slave issues STOP_DET interrupt only if addressed function.
548 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
549 *
550 * Register|BitsName
551 * --------|--------
552 * IC_CON | STOP_DET_IF_ADDRESSED
553 *
554 * @param I2Cx I2C instance.
555 * @retval None.
556 */
557 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
558 {
559 CLEAR_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
560 }
561
562 /**
563 * @brief Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
564 *
565 * Register|BitsName
566 * --------|--------
567 * IC_CON | STOP_DET_IF_ADDRESSED
568 *
569 * @param I2Cx I2C instance.
570 * @retval State of bit (1 or 0).
571 */
572 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
573 {
574 return (READ_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED) == (I2C_CON_STOP_DET_IF_ADDRESSED));
575 }
576
577 /**
578 * @brief Configure the Master to transfers in 7-bit or 10-bit addressing mode.
579 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
580 *
581 * Register|BitsName
582 * --------|--------
583 * IC_CON | CON_10BITADDR_MST
584 *
585 * @param I2Cx I2C instance.
586 * @param addressing_mode This parameter can be one of the following values:
587 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
588 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
589 * @retval None.
590 */
591 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
592 {
593 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_MST, addressing_mode);
594 }
595
596 /**
597 * @brief Get the Master addressing mode.
598 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
599 *
600 * Register|BitsName
601 * --------|--------
602 * IC_CON | CON_10BITADDR_MST
603 *
604 * @param I2Cx I2C instance.
605 * @retval Returned value can be one of the following values:
606 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
607 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
608 */
609 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
610 {
611 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_10BITADDR_MST));
612 }
613
614 /**
615 * @brief Set the Own Address.
616 * @note The register IC_CON and IC_SAR can only be programmed when the I2C is disabled (IC_ENABLE = 0).
617 *
618 * Register|BitsName
619 * --------|--------
620 * IC_CON | CON_10BITADDR_SLV
621 * IC_SAR | SAR
622 *
623 * @param I2Cx I2C instance.
624 * @param own_address This parameter must be a value range between 0 ~ 0x3FF(10-bit mode) or 0 ~ 0x7F(7-bit mode).
625 * Reserved address 0x00 to 0x07, or 0x78 to 0x7f should not be configured.
626 * @param own_addr_size This parameter can be one of the following values:
627 * @arg @ref LL_I2C_OWNADDRESS_7BIT
628 * @arg @ref LL_I2C_OWNADDRESS_10BIT
629 * @retval None.
630 */
631 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
632 {
633 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_SLV, own_addr_size);
634 WRITE_REG(I2Cx->SAR, own_address);
635 }
636
637 /**
638 * @brief Set the SCL clock high-period count for standard speed.
639 * @note The register IC_SS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
640 *
641 * Register|BitsName
642 * --------|--------
643 * IC_SS_SCL_HCNT | SS_SCL_HCNT
644 *
645 * @param I2Cx I2C instance.
646 * @param count This parameter must be a value range between 6 ~ 0xFFF5.
647 * @retval None.
648 */
649 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
650 {
651 WRITE_REG(I2Cx->SS_SCL_HCNT, count);
652 }
653
654 /**
655 * @brief Get the SCL clock high-period count for standard speed.
656 *
657 * Register|BitsName
658 * --------|--------
659 * IC_SS_SCL_HCNT | SS_SCL_HCNT
660 *
661 * @param I2Cx I2C instance.
662 * @retval Value range between 0x6 and 0xFFF5.
663 */
664 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
665 {
666 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_HCNT, I2C_SS_SCL_HCNT));
667 }
668
669 /**
670 * @brief Set the SCL clock low-period count for standard speed.
671 * @note The register IC_SS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
672 *
673 * Register|BitsName
674 * --------|--------
675 * IC_SS_SCL_LCNT | SS_SCL_LCNT
676 *
677 * @param I2Cx I2C instance.
678 * @param count This parameter must be a value range between 0x8 and 0xFFFF.
679 * @retval None.
680 */
681 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
682 {
683 WRITE_REG(I2Cx->SS_SCL_LCNT, count);
684 }
685
686 /**
687 * @brief Get the SCL clock low-period count for standard speed.
688 *
689 * Register|BitsName
690 * --------|--------
691 * IC_SS_SCL_LCNT | SS_SCL_LCNT
692 *
693 * @param I2Cx I2C instance.
694 * @retval Value range between 0x8 and 0xFFFF.
695 */
696 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
697 {
698 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_LCNT, I2C_SS_SCL_LCNT));
699 }
700
701 /**
702 * @brief Set the SCL clock high-period count for fast speed.
703 * @note The register IC_FS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
704 *
705 * Register|BitsName
706 * --------|--------
707 * IC_FS_SCL_HCNT | FS_SCL_HCNT
708 *
709 * @param I2Cx I2C instance.
710 * @param count range between 0x6 and 0xFFFF.
711 * @retval None.
712 */
713 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
714 {
715 WRITE_REG(I2Cx->FS_SCL_HCNT, count);
716 }
717
718 /**
719 * @brief Get the SCL clock high-period count for fast speed.
720 *
721 * Register|BitsName
722 * --------|--------
723 * IC_FS_SCL_HCNT | FS_SCL_HCNT
724 *
725 * @param I2Cx I2C instance.
726 * @retval Value range between 0x6 and 0xFFFF.
727 */
728 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
729 {
730 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_HCNT, I2C_FS_SCL_HCNT));
731 }
732
733 /**
734 * @brief Set the SCL clock low-period count for fast speed.
735 * @note The register IC_FS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
736 *
737 * Register|BitsName
738 * --------|--------
739 * IC_FS_SCL_LCNT | FS_SCL_LCNT
740 *
741 * @param I2Cx I2C instance.
742 * @param count range between 0x8 and 0xFFFF
743 * @retval None.
744 */
745 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
746 {
747 WRITE_REG(I2Cx->FS_SCL_LCNT, count);
748 }
749
750 /**
751 * @brief Get the SCL clock low-period count for fast speed.
752 *
753 * Register|BitsName
754 * --------|--------
755 * IC_FS_SCL_LCNT | FS_SCL_LCNT
756 *
757 * @param I2Cx I2C instance.
758 * @retval Value range between 0x8 and 0xFFFF.
759 */
760 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
761 {
762 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_LCNT, I2C_FS_SCL_LCNT));
763 }
764
765 /**
766 * @brief Get the SCL clock high-period count for high speed.
767 * @note The register IC_HS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
768 *
769 * Register|BitsName
770 * --------|--------
771 * IC_HS_SCL_HCNT | HS_SCL_HCNT
772 *
773 * @param I2Cx I2C instance.
774 * @param count range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 5.
775 * @retval None.
776 */
777 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
778 {
779 WRITE_REG(I2Cx->HS_SCL_HCNT, count);
780 }
781
782 /**
783 * @brief Get the SCL clock high-period count for high speed.
784 *
785 * Register|BitsName
786 * --------|--------
787 * IC_HS_SCL_HCNT | HS_SCL_HCNT
788 *
789 * @param I2Cx I2C instance.
790 * @retval range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 7.
791 */
792 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
793 {
794 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_HCNT, I2C_HS_SCL_HCNT));
795 }
796
797 /**
798 * @brief Get the SCL clock low-period count for high speed.
799 * @note The register IC_HS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
800 *
801 * Register|BitsName
802 * --------|--------
803 * IC_HS_SCL_LCNT | HS_SCL_LCNT
804 *
805 * @param I2Cx I2C instance.
806 * @param count range between 0x8 and 0xFFFF
807 * @retval None.
808 */
809 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
810 {
811 WRITE_REG(I2Cx->HS_SCL_LCNT, count);
812 }
813
814 /**
815 * @brief Get the SCL clock low-period count for high speed.
816 *
817 * Register|BitsName
818 * --------|--------
819 * IC_HS_SCL_LCNT | HS_SCL_LCNT
820 *
821 * @param I2Cx I2C instance.
822 * @retval Value range between 0x8 and 0xFFFF
823 */
824 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
825 {
826 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_LCNT, I2C_HS_SCL_LCNT));
827 }
828
829 /**
830 * @brief Set the spike len in fast speed mode.
831 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
832 *
833 * Register|BitsName
834 * --------|--------
835 * IC_FS_SPKLEN | FS_SPKLEN
836 *
837 * @param I2Cx I2C instance.
838 * @param length Spike len.
839 * @retval None.
840 */
841 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
842 {
843 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
844 }
845
846 /**
847 * @brief Get the spike len in fast speed mode.
848 *
849 * Register|BitsName
850 * --------|--------
851 * IC_FS_SPKLEN | FS_SPKLEN
852 *
853 * @param I2Cx I2C instance.
854 * @retval Value range between 0x2 and 0xFF.
855 */
856 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
857 {
858 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
859 }
860
861 /**
862 * @brief Set the spike len in high speed mode.
863 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
864 *
865 * Register|BitsName
866 * --------|--------
867 * IC_HS_SPKLEN | HS_SPKLEN
868 *
869 * @param I2Cx I2C instance.
870 * @param length Spike len.
871 * @retval None.
872 */
873 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
874 {
875 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
876 }
877
878 /**
879 * @brief Get the spike len in high speed mode.
880 *
881 * Register|BitsName
882 * --------|--------
883 * IC_HS_SPKLEN | HS_SPKLEN
884 *
885 * @param I2Cx I2C instance.
886 * @retval Value range between 0x2 and 0xFF.
887 */
888 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
889 {
890 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
891 }
892
893 /**
894 * @brief Set I2C Speed mode.
895 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
896 *
897 * Register|BitsName
898 * --------|--------
899 * IC_CON | SPEED
900 *
901 * @param I2Cx I2C instance.
902 * @param speed_mode This parameter can be one of the following values:
903 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
904 * @arg @ref LL_I2C_SPEED_MODE_FAST
905 * @arg @ref LL_I2C_SPEED_MODE_HIGH
906 * @retval None.
907 */
908 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
909 {
910 MODIFY_REG(I2Cx->CON, I2C_CON_SPEED, speed_mode);
911 }
912
913 /**
914 * @brief Get I2C Speed mode.
915 *
916 * Register|BitsName
917 * --------|--------
918 * IC_CON | SPEED
919 *
920 * @param I2Cx I2C instance.
921 * @retval Value can be one of the following values:
922 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
923 * @arg @ref LL_I2C_SPEED_MODE_FAST
924 * @arg @ref LL_I2C_SPEED_MODE_HIGH
925 */
926 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
927 {
928 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_SPEED));
929 }
930
931 /**
932 * @brief Set I2C High Speed Master Code Address.
933 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
934 *
935 * Register|BitsName
936 * --------|--------
937 * IC_HS_MADDR | HS_MAR
938 *
939 * @param I2Cx I2C instance.
940 * @param code HS mode master code, range between 0x00 and 0x07.
941 * @retval None.
942 */
943 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
944 {
945 WRITE_REG(I2Cx->HS_MADDR, code);
946 }
947
948 /**
949 * @brief Get I2C Speed mode.
950 *
951 * Register|BitsName
952 * --------|--------
953 * IC_HS_MADDR | HS_MAR
954 *
955 * @param I2Cx I2C instance.
956 * @retval Returned value range between 0x00 and 0x07.
957 */
958 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
959 {
960 return (uint32_t)(READ_BITS(I2Cx->HS_MADDR, I2C_HS_MADDR_HS_MAR));
961 }
962
963 /**
964 * @brief Set the required transmit SDA hold time in units of ic_clk period.
965 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
966 *
967 * Register|BitsName
968 * --------|--------
969 * IC_SDA_HOLD | TX_HOLD
970 *
971 * @param I2Cx I2C instance.
972 * @param time SDA Tx hold time in units of ic_clk period.
973 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
974 * @retval None.
975 */
976 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
977 {
978 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_Pos);
979 }
980
981 /**
982 * @brief Get the required transmit SDA hold time in units of ic_clk period.
983 *
984 * Register|BitsName
985 * --------|--------
986 * IC_SDA_HOLD | TX_HOLD
987 *
988 * @param I2Cx I2C instance.
989 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
990 */
991 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
992 {
993 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_Pos);
994 }
995
996 /**
997 * @brief Set the required receive SDA hold time in units of ic_clk period.
998 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
999 *
1000 * Register|BitsName
1001 * --------|--------
1002 * IC_SDA_HOLD | RX_HOLD
1003 *
1004 * @param I2Cx I2C instance.
1005 * @param time SDA Tx hold time in units of ic_clk period.
1006 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1007 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1008 */
1009 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1010 {
1011 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_Pos);
1012 }
1013
1014 /**
1015 * @brief Get the required receive SDA hold time in units of ic_clk period.
1016 *
1017 * Register|BitsName
1018 * --------|--------
1019 * IC_SDA_HOLD | RX_HOLD
1020 *
1021 * @param I2Cx I2C instance.
1022 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1023 */
1024 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1025 {
1026 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_Pos);
1027 }
1028
1029 /**
1030 * @brief Set the SDA setup time when operating as a slave transmitter.
1031 * @note The register IC_SDA_SETUP can only be programmed when the I2C is disabled (ENABLE = 0).
1032 * The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the
1033 * user requires 10 ic_clk periods of setup time, they should program a value of 11.
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * IC_SDA_SETUP | SDA_SETUP
1038 *
1039 * @param I2Cx I2C instance.
1040 * @param time SDA data setup time in units of ic_clk period, range between 2 ~ 0xFF.
1041 * @retval None.
1042 */
1043 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1044 {
1045 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP, time);
1046 }
1047
1048 /**
1049 * @brief Get the SDA setup time when operating as a slave transmitter.
1050 *
1051 * Register|BitsName
1052 * --------|--------
1053 * IC_SDA_SETUP | SDA_SETUP
1054 *
1055 * @param I2Cx I2C instance.
1056 * @retval Value range between 0x02 and 0xFF.
1057 */
1058 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1059 {
1060 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP));
1061 }
1062
1063 /**
1064 * @brief Set threshold of entries (or below) that trigger the TX_EMPTY interrupt
1065 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * IC_TX_TL | TX_TL
1070 *
1071 * @param I2Cx I2C instance
1072 * @param threshold This parameter can be one of the following values:
1073 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1074 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1075 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1076 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1077 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1078 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1079 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1080 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1081 * @retval None.
1082 */
1083 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1084 {
1085 WRITE_REG(I2Cx->TX_TL, threshold);
1086 }
1087
1088 /**
1089 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
1090 *
1091 * Register|BitsName
1092 * --------|--------
1093 * IC_TX_TL | TX_TL
1094 *
1095 * @param I2Cx I2C instance
1096 * @retval Returned value can be one of the following values:
1097 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1098 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1099 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1100 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1101 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1102 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1103 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1104 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1105 */
1106 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1107 {
1108 return (uint32_t)(READ_BITS(I2Cx->TX_TL, I2C_TX_TL_TXTL));
1109 }
1110
1111 /**
1112 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
1113 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1114 *
1115 * Register|BitsName
1116 * --------|--------
1117 * IC_RX_TL | RX_TL
1118 *
1119 * @param I2Cx I2C instance
1120 * @param threshold This parameter can be one of the following values:
1121 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1122 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1123 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1124 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1125 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1126 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1127 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1128 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1129 * @retval None.
1130 */
1131 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1132 {
1133 WRITE_REG(I2Cx->RX_TL, threshold);
1134 }
1135
1136 /**
1137 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
1138 *
1139 * Register|BitsName
1140 * --------|--------
1141 * IC_RX_TL | RX_TL
1142 *
1143 * @param I2Cx I2C instance
1144 * @retval Returned value can be one of the following values:
1145 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1146 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1147 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1148 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1149 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1150 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1151 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1152 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1153 */
1154 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1155 {
1156 return (uint32_t)(READ_BITS(I2Cx->RX_TL, I2C_RX_TL_RXTL));
1157 }
1158
1159 /**
1160 * @brief Get FIFO Transmission Level
1161 *
1162 * Register|BitsName
1163 * --------|--------
1164 * IC_TXFLR | TXFLR
1165 *
1166 * @param I2Cx I2C instance
1167 * @retval Value range between 0x0 and 0x8.
1168 */
1169 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1170 {
1171 return (uint32_t)(READ_BITS(I2Cx->TXFLR, I2C_TXFLR_TXFLR));
1172 }
1173
1174 /**
1175 * @brief Get FIFO reception Level
1176 *
1177 * Register|BitsName
1178 * --------|--------
1179 * IC_RXFLR | RXFLR
1180 *
1181 * @param I2Cx I2C instance
1182 * @retval Value range between 0x0 and 0x8.
1183 */
1184 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1185 {
1186 return (uint32_t)(READ_BITS(I2Cx->RXFLR, I2C_RXFLR_RXFLR));
1187 }
1188
1189 /**
1190 * @brief Enable DMA reception requests.
1191 *
1192 * Register|BitsName
1193 * --------|--------
1194 * IC_ENABLE | ABORT
1195 *
1196 * @param I2Cx I2C instance.
1197 * @retval None.
1198 */
1199 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1200 {
1201 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT);
1202 }
1203
1204 /**
1205 * @brief Check if DMA reception requests are enabled or disabled.
1206 *
1207 * Register|BitsName
1208 * --------|--------
1209 * IC_ENABLE | ABORT
1210 *
1211 * @param I2Cx I2C instance.
1212 * @retval State of bit (1 or 0).
1213 */
1214 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1215 {
1216 return (READ_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT) == (I2C_ENABLE_ABORT));
1217 }
1218
1219 /**
1220 * @brief Get the transmit abort source.
1221 * @note This can be used to retrieve source of TX_ABRT interrupt.
1222 *
1223 * Register|BitsName
1224 * --------|--------
1225 * IC_TX_ABRT_SOURCE | ABRT_USER_ABRT
1226 * IC_TX_ABRT_SOURCE | ABRT_SLVRD_INTX
1227 * IC_TX_ABRT_SOURCE | ABRT_SLV_ARBLOST
1228 * IC_TX_ABRT_SOURCE | ABRT_SLVFLUSH_TXFIFO
1229 * IC_TX_ABRT_SOURCE | ABRT_ARB_LOST
1230 * IC_TX_ABRT_SOURCE | ABRT_MST_DIS
1231 * IC_TX_ABRT_SOURCE | ABRT_10B_RD_NORSTRT
1232 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_NORSTRT
1233 * IC_TX_ABRT_SOURCE | ABRT_HS_NORSTRT
1234 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_ACKDET
1235 * IC_TX_ABRT_SOURCE | ABRT_HS_ACKDET
1236 * IC_TX_ABRT_SOURCE | ABRT_GCALL_READ
1237 * IC_TX_ABRT_SOURCE | ABRT_GCALL_NOACK
1238 * IC_TX_ABRT_SOURCE | ABRT_TXDATA_NOACK
1239 * IC_TX_ABRT_SOURCE | ABRT_10ADDR2_NOACK
1240 * IC_TX_ABRT_SOURCE | ABRT_10ADDR1_NOACK
1241 * IC_TX_ABRT_SOURCE | ABRT_7B_ADDR_NOACK
1242 *
1243 * @param I2Cx I2C instance
1244 * @retval Returned value can be a combination of the following values:
1245 * @arg @ref LL_I2C_ABRT_USER_ABRT
1246 * @arg @ref LL_I2C_ABRT_SLVRD_INTX
1247 * @arg @ref LL_I2C_ABRT_SLV_ARBLOST
1248 * @arg @ref LL_I2C_ABRT_SLVFLUSH_TXFIFO
1249 * @arg @ref LL_I2C_ABRT_ARB_LOST
1250 * @arg @ref LL_I2C_ABRT_MST_DIS
1251 * @arg @ref LL_I2C_ABRT_10B_RD_NORSTRT
1252 * @arg @ref LL_I2C_ABRT_SBYTE_NORSTRT
1253 * @arg @ref LL_I2C_ABRT_HS_NORSTRT
1254 * @arg @ref LL_I2C_ABRT_SBYTE_ACKDET
1255 * @arg @ref LL_I2C_ABRT_HS_ACKDET
1256 * @arg @ref LL_I2C_ABRT_GCALL_READ
1257 * @arg @ref LL_I2C_ABRT_GCALL_NOACK
1258 * @arg @ref LL_I2C_ABRT_TXDATA_NOACK
1259 * @arg @ref LL_I2C_ABRT_10ADDR2_NOACK
1260 * @arg @ref LL_I2C_ABRT_10ADDR1_NOACK
1261 * @arg @ref LL_I2C_ABRT_7B_ADDR_NOACK
1262 *
1263 * @note @arg @ref LL_I2C_ABRT_TX_FLUSH_CNT can be used as a mask to get the
1264 * number of Tx FIFO Data Commands which are flushed due to TX_ABRT
1265 * interrupt.
1266 */
1267 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1268 {
1269 return (uint32_t)(READ_REG(I2Cx->TX_ABRT_SOURCE) & (~I2C_TX_ABRT_SRC_TX_FLUSH_CNT));
1270 }
1271
1272 /**
1273 * @brief Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
1274 *
1275 * Register|BitsName
1276 * --------|--------
1277 * IC_TX_ABRT_SOURCE | TX_FLUSH_CNT
1278 *
1279 * @param I2Cx I2C instance
1280 * @retval Tx flush count.
1281 */
1282 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1283 {
1284 return (uint32_t)(READ_BITS(I2Cx->TX_ABRT_SOURCE, I2C_TX_ABRT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos);
1285 }
1286
1287 /** @} */
1288
1289 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1290 * @{
1291 */
1292
1293 /**
1294 * @brief Enable specified interrupts.
1295 *
1296 * Register|BitsName
1297 * --------|--------
1298 * INTR_MASK | INTR_MASK_GEN_CALL
1299 * INTR_MASK | INTR_MASK_START_DET
1300 * INTR_MASK | INTR_MASK_STOP_DET
1301 * INTR_MASK | INTR_MASK_ACTIVITY
1302 * INTR_MASK | INTR_MASK_RX_DONE
1303 * INTR_MASK | INTR_MASK_TX_ABRT
1304 * INTR_MASK | INTR_MASK_RD_REQ
1305 * INTR_MASK | INTR_MASK_TX_EMPTY
1306 * INTR_MASK | INTR_MASK_TX_OVER
1307 * INTR_MASK | INTR_MASK_RX_FULL
1308 * INTR_MASK | INTR_MASK_RX_OVER
1309 * INTR_MASK | INTR_MASK_RX_UNDER
1310 *
1311 * @param I2Cx I2C instance.
1312 * @param mask This parameter can be a combination of the following values:
1313 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1314 * @arg @ref LL_I2C_INTR_MASK_START_DET
1315 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1316 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1317 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1318 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1319 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1320 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1321 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1322 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1323 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1324 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1325 * @retval None.
1326 */
1327 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1328 {
1329 SET_BITS(I2Cx->INTR_MASK, mask);
1330 }
1331
1332 /**
1333 * @brief Disable specified interrupts.
1334 *
1335 * Register|BitsName
1336 * --------|--------
1337 * INTR_MASK | INTR_MASK_GEN_CALL
1338 * INTR_MASK | INTR_MASK_START_DET
1339 * INTR_MASK | INTR_MASK_STOP_DET
1340 * INTR_MASK | INTR_MASK_ACTIVITY
1341 * INTR_MASK | INTR_MASK_RX_DONE
1342 * INTR_MASK | INTR_MASK_TX_ABRT
1343 * INTR_MASK | INTR_MASK_RD_REQ
1344 * INTR_MASK | INTR_MASK_TX_EMPTY
1345 * INTR_MASK | INTR_MASK_TX_OVER
1346 * INTR_MASK | INTR_MASK_RX_FULL
1347 * INTR_MASK | INTR_MASK_RX_OVER
1348 * INTR_MASK | INTR_MASK_RX_UNDER
1349 *
1350 * @param I2Cx I2C instance.
1351 * @param mask This parameter can be a combination of the following values:
1352 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1353 * @arg @ref LL_I2C_INTR_MASK_START_DET
1354 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1355 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1356 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1357 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1358 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1359 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1360 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1361 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1362 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1363 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1364 * @retval None.
1365 */
1366 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1367 {
1368 CLEAR_BITS(I2Cx->INTR_MASK, mask);
1369 }
1370
1371 /**
1372 * @brief Check if the specified interrupts are enabled or disabled.
1373 *
1374 * Register|BitsName
1375 * --------|--------
1376 * INTR_MASK | INTR_MASK_GEN_CALL
1377 * INTR_MASK | INTR_MASK_START_DET
1378 * INTR_MASK | INTR_MASK_STOP_DET
1379 * INTR_MASK | INTR_MASK_ACTIVITY
1380 * INTR_MASK | INTR_MASK_RX_DONE
1381 * INTR_MASK | INTR_MASK_TX_ABRT
1382 * INTR_MASK | INTR_MASK_RD_REQ
1383 * INTR_MASK | INTR_MASK_TX_EMPTY
1384 * INTR_MASK | INTR_MASK_TX_OVER
1385 * INTR_MASK | INTR_MASK_RX_FULL
1386 * INTR_MASK | INTR_MASK_RX_OVER
1387 * INTR_MASK | INTR_MASK_RX_UNDER
1388 *
1389 * @param I2Cx I2C instance.
1390 * @param mask This parameter can be a combination of the following values:
1391 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1392 * @arg @ref LL_I2C_INTR_MASK_START_DET
1393 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1394 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1395 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1396 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1397 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1398 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1399 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1400 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1401 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1402 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1403 * @retval State of bit (1 or 0).
1404 */
1405 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1406 {
1407 return (READ_BITS(I2Cx->INTR_MASK, mask) == (mask));
1408 }
1409
1410 /**
1411 * @brief Enable MASTER_ON_HOLD interrupt.
1412 *
1413 * Register|BitsName
1414 * --------|--------
1415 * INTR_MASK | MST_ON_HOLD
1416 *
1417 * @param I2Cx I2C instance.
1418 * @retval None.
1419 */
1420 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1421 {
1422 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1423 }
1424
1425 /**
1426 * @brief Disable MASTER_ON_HOLD interrupt.
1427 *
1428 * Register|BitsName
1429 * --------|--------
1430 * INTR_MASK | MST_ON_HOLD
1431 *
1432 * @param I2Cx I2C instance.
1433 * @retval None.
1434 */
1435 __STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
1436 {
1437 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1438 }
1439
1440 /**
1441 * @brief Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
1442 *
1443 * Register|BitsName
1444 * --------|--------
1445 * INTR_MASK | MST_ON_HOLD
1446 *
1447 * @param I2Cx I2C instance.
1448 * @retval State of bit (1 or 0).
1449 */
1450 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1451 {
1452 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
1453 }
1454
1455 /**
1456 * @brief Enable RESTART_DET interrupt.
1457 *
1458 * Register|BitsName
1459 * --------|--------
1460 * INTR_MASK | RESTART_DET
1461 *
1462 * @param I2Cx I2C instance.
1463 * @retval None.
1464 */
1465 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1466 {
1467 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1468 }
1469
1470 /**
1471 * @brief Disable RESTART_DET interrupt.
1472 *
1473 * Register|BitsName
1474 * --------|--------
1475 * INTR_MASK | RESTART_DET
1476 *
1477 * @param I2Cx I2C instance.
1478 * @retval None.
1479 */
1480 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1481 {
1482 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1483 }
1484
1485 /**
1486 * @brief Check if the RESTART_DET Interrupt is enabled or disabled.
1487 *
1488 * Register|BitsName
1489 * --------|--------
1490 * INTR_MASK | RESTART_DET
1491 *
1492 * @param I2Cx I2C instance.
1493 * @retval State of bit (1 or 0).
1494 */
1495 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1496 {
1497 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
1498 }
1499
1500 /**
1501 * @brief Enable GEN_CALL interrupt.
1502 *
1503 * Register|BitsName
1504 * --------|--------
1505 * INTR_MASK | GEN_CALL
1506 *
1507 * @param I2Cx I2C instance.
1508 * @retval None.
1509 */
1510 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1511 {
1512 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1513 }
1514
1515 /**
1516 * @brief Disable GEN_CALL interrupt.
1517 *
1518 * Register|BitsName
1519 * --------|--------
1520 * INTR_MASK | GEN_CALL
1521 *
1522 * @param I2Cx I2C instance.
1523 * @retval None.
1524 */
1525 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1526 {
1527 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1528 }
1529
1530 /**
1531 * @brief Check if GEN_CALL interrupt is enabled or disabled.
1532 *
1533 * Register|BitsName
1534 * --------|--------
1535 * INTR_MASK | GEN_CALL
1536 *
1537 * @param I2Cx I2C instance.
1538 * @retval State of bit (1 or 0).
1539 */
1540 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1541 {
1542 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
1543 }
1544
1545 /**
1546 * @brief Enable START_DET received interrupt.
1547 *
1548 * Register|BitsName
1549 * --------|--------
1550 * INTR_MASK | START_DET
1551 *
1552 * @param I2Cx I2C instance.
1553 * @retval None.
1554 */
1555 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1556 {
1557 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1558 }
1559
1560 /**
1561 * @brief Disable START_DET received interrupt.
1562 *
1563 * Register|BitsName
1564 * --------|--------
1565 * INTR_MASK | START_DET
1566 *
1567 * @param I2Cx I2C instance.
1568 * @retval None.
1569 */
1570 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1571 {
1572 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1573 }
1574
1575 /**
1576 * @brief Check if START_DET received interrupt is enabled or disabled.
1577 *
1578 * Register|BitsName
1579 * --------|--------
1580 * INTR_MASK | START_DET
1581 *
1582 * @param I2Cx I2C instance.
1583 * @retval State of bit (1 or 0).
1584 */
1585 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1586 {
1587 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
1588 }
1589
1590 /**
1591 * @brief Enable STOP_DET interrupt.
1592 *
1593 * Register|BitsName
1594 * --------|--------
1595 * INTR_MASK | STOP_DET
1596 *
1597 * @param I2Cx I2C instance.
1598 * @retval None.
1599 */
1600 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1601 {
1602 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1603 }
1604
1605 /**
1606 * @brief Disable STOP_DET interrupt.
1607 *
1608 * Register|BitsName
1609 * --------|--------
1610 * INTR_MASK | STOP_DET
1611 *
1612 * @param I2Cx I2C instance.
1613 * @retval None.
1614 */
1615 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1616 {
1617 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1618 }
1619
1620 /**
1621 * @brief Check if STOP_DET interrupt is enabled or disabled.
1622 *
1623 * Register|BitsName
1624 * --------|--------
1625 * INTR_MASK | STOP_DET
1626 *
1627 * @param I2Cx I2C instance.
1628 * @retval State of bit (1 or 0).
1629 */
1630 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1631 {
1632 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
1633 }
1634
1635 /**
1636 * @brief Enable ACTIVITY interrupt.
1637 *
1638 * Register|BitsName
1639 * --------|--------
1640 * INTR_MASK | ACTIVITY
1641 *
1642 * @param I2Cx I2C instance.
1643 * @retval None.
1644 */
1645 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1646 {
1647 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1648 }
1649
1650 /**
1651 * @brief Disable ACTIVITY interrupt.
1652 *
1653 * Register|BitsName
1654 * --------|--------
1655 * INTR_MASK | ACTIVITY
1656 *
1657 * @param I2Cx I2C instance.
1658 * @retval None.
1659 */
1660 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1661 {
1662 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1663 }
1664
1665 /**
1666 * @brief Check if ACTIVITY interrupt is enabled or disabled.
1667 *
1668 * Register|BitsName
1669 * --------|--------
1670 * INTR_MASK | ACTIVITY
1671 *
1672 * @param I2Cx I2C instance.
1673 * @retval State of bit (1 or 0).
1674 */
1675 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1676 {
1677 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
1678 }
1679
1680 /**
1681 * @brief Enable RX_DONE interrupt.
1682 *
1683 * Register|BitsName
1684 * --------|--------
1685 * INTR_MASK | RX_DONE
1686 *
1687 * @param I2Cx I2C instance.
1688 * @retval State of bit (1 or 0).
1689 */
1690 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
1691 {
1692 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1693 }
1694
1695 /**
1696 * @brief Disable RX_DONE interrupt.
1697 *
1698 * Register|BitsName
1699 * --------|--------
1700 * INTR_MASK | RX_DONE
1701 *
1702 * @param I2Cx I2C instance.
1703 * @retval None.
1704 */
1705 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
1706 {
1707 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1708 }
1709
1710 /**
1711 * @brief Check if RX_DONE interrupt is enabled or disabled.
1712 *
1713 * Register|BitsName
1714 * --------|--------
1715 * INTR_MASK | RX_DONE
1716 *
1717 * @param I2Cx I2C instance.
1718 * @retval State of bit (1 or 0).
1719 */
1720 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
1721 {
1722 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
1723 }
1724
1725 /**
1726 * @brief Enable TX_ABRT interrupt.
1727 *
1728 * Register|BitsName
1729 * --------|--------
1730 * INTR_MASK | TX_ABRT
1731 *
1732 * @param I2Cx I2C instance.
1733 * @retval None.
1734 */
1735 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
1736 {
1737 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1738 }
1739
1740 /**
1741 * @brief Disable TX_ABRT interrupt.
1742 *
1743 * Register|BitsName
1744 * --------|--------
1745 * INTR_MASK | TX_ABRT
1746 *
1747 * @param I2Cx I2C instance.
1748 * @retval None.
1749 */
1750 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
1751 {
1752 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1753 }
1754
1755 /**
1756 * @brief Check if TX_ABRT interrupt is enabled or disabled.
1757 *
1758 * Register|BitsName
1759 * --------|--------
1760 * INTR_MASK | TX_ABRT
1761 *
1762 * @param I2Cx I2C instance.
1763 * @retval None.
1764 */
1765 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
1766 {
1767 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
1768 }
1769
1770 /**
1771 * @brief Enable RD_REQ interrupt.
1772 *
1773 * Register|BitsName
1774 * --------|--------
1775 * INTR_MASK | RD_REQ
1776 *
1777 * @param I2Cx I2C instance.
1778 * @retval None.
1779 */
1780 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
1781 {
1782 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1783 }
1784
1785 /**
1786 * @brief Disable RD_REQ interrupt.
1787 *
1788 * Register|BitsName
1789 * --------|--------
1790 * INTR_MASK | RD_REQ
1791 *
1792 * @param I2Cx I2C instance.
1793 * @retval None.
1794 */
1795 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
1796 {
1797 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1798 }
1799
1800 /**
1801 * @brief Check if RD_REQ interrupt is enabled or disabled.
1802 *
1803 * Register|BitsName
1804 * --------|--------
1805 * INTR_MASK | RD_REQ
1806 *
1807 * @param I2Cx I2C instance.
1808 * @retval State of bit (1 or 0).
1809 */
1810 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
1811 {
1812 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
1813 }
1814
1815 /**
1816 * @brief Enable TX_EMPTY interrupt.
1817 *
1818 * Register|BitsName
1819 * --------|--------
1820 * INTR_MASK | TX_EMPTY
1821 *
1822 * @param I2Cx I2C instance.
1823 * @retval None.
1824 */
1825 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
1826 {
1827 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1828 }
1829
1830 /**
1831 * @brief Disable TX_EMPTY interrupt.
1832 *
1833 * Register|BitsName
1834 * --------|--------
1835 * INTR_MASK | TX_EMPTY
1836 *
1837 * @param I2Cx I2C instance.
1838 * @retval None.
1839 */
1840 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
1841 {
1842 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1843 }
1844
1845 /**
1846 * @brief Check if TX_EMPTY interrupt is enabled or disabled.
1847 *
1848 * Register|BitsName
1849 * --------|--------
1850 * INTR_MASK | TX_EMPTY
1851 *
1852 * @param I2Cx I2C instance.
1853 * @retval State of bit (1 or 0).
1854 */
1855 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
1856 {
1857 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
1858 }
1859
1860 /**
1861 * @brief Enable TX_OVER interrupt.
1862 *
1863 * Register|BitsName
1864 * --------|--------
1865 * INTR_MASK | TX_OVER
1866 *
1867 * @param I2Cx I2C instance.
1868 * @retval None.
1869 */
1870 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
1871 {
1872 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1873 }
1874
1875 /**
1876 * @brief Disable TX_OVER interrupt.
1877 *
1878 * Register|BitsName
1879 * --------|--------
1880 * INTR_MASK | TX_OVER
1881 *
1882 * @param I2Cx I2C instance.
1883 * @retval None.
1884 */
1885 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
1886 {
1887 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1888 }
1889
1890 /**
1891 * @brief Check if TX_OVER interrupt is enabled or disabled.
1892 *
1893 * Register|BitsName
1894 * --------|--------
1895 * INTR_MASK | TX_OVER
1896 *
1897 * @param I2Cx I2C instance.
1898 * @retval State of bit (1 or 0).
1899 */
1900 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
1901 {
1902 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
1903 }
1904
1905 /**
1906 * @brief Enable RX_FULL interrupt.
1907 *
1908 * Register|BitsName
1909 * --------|--------
1910 * INTR_MASK | RX_FULL
1911 *
1912 * @param I2Cx I2C instance.
1913 * @retval None.
1914 */
1915 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
1916 {
1917 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1918 }
1919
1920 /**
1921 * @brief Disable RX_FULL interrupt.
1922 *
1923 * Register|BitsName
1924 * --------|--------
1925 * INTR_MASK | RX_FULL
1926 *
1927 * @param I2Cx I2C instance.
1928 * @retval None.
1929 */
1930 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
1931 {
1932 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1933 }
1934
1935 /**
1936 * @brief Check if RX_FULL interrupt is enabled or disabled.
1937 *
1938 * Register|BitsName
1939 * --------|--------
1940 * INTR_MASK | RX_FULL
1941 *
1942 * @param I2Cx I2C instance.
1943 * @retval None.
1944 */
1945 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
1946 {
1947 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
1948 }
1949
1950 /**
1951 * @brief Enable RX_OVER interrupt.
1952 *
1953 * Register|BitsName
1954 * --------|--------
1955 * INTR_MASK | RX_OVER
1956 *
1957 * @param I2Cx I2C instance.
1958 * @retval None.
1959 */
1960 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
1961 {
1962 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1963 }
1964
1965 /**
1966 * @brief Disable RX_OVER interrupt.
1967 *
1968 * Register|BitsName
1969 * --------|--------
1970 * INTR_MASK | RX_OVER
1971 *
1972 * @param I2Cx I2C instance.
1973 * @retval None.
1974 */
1975 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
1976 {
1977 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1978 }
1979
1980 /**
1981 * @brief Check if RX_OVER interrupt is enabled or disabled.
1982 *
1983 * Register|BitsName
1984 * --------|--------
1985 * INTR_MASK | RX_OVER
1986 *
1987 * @param I2Cx I2C instance.
1988 * @retval None.
1989 */
1990 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
1991 {
1992 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
1993 }
1994
1995 /**
1996 * @brief Enable RX_UNDER interrupt.
1997 *
1998 * Register|BitsName
1999 * --------|--------
2000 * INTR_MASK | RX_UNDER
2001 *
2002 * @param I2Cx I2C instance.
2003 * @retval None.
2004 */
2005 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2006 {
2007 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2008 }
2009
2010 /**
2011 * @brief Disable RX_UNDER interrupt.
2012 *
2013 * Register|BitsName
2014 * --------|--------
2015 * INTR_MASK | RX_UNDER
2016 *
2017 * @param I2Cx I2C instance.
2018 * @retval None.
2019 */
2020 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2021 {
2022 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2023 }
2024
2025 /**
2026 * @brief Check if RX_UNDER interrupt is enabled or disabled.
2027 *
2028 * Register|BitsName
2029 * --------|--------
2030 * INTR_MASK | RX_UNDER
2031 *
2032 * @param I2Cx I2C instance.
2033 * @retval None.
2034 */
2035 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2036 {
2037 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2038 }
2039
2040 /** @} */
2041
2042 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
2043 * @{
2044 */
2045
2046 /**
2047 * @brief Get I2C interrupt flags
2048 *
2049 * Register|BitsName
2050 * --------|--------
2051 * IC_INTR_STAT | MST_ON_HOLD
2052 * IC_INTR_STAT | RESTART_DET
2053 * IC_INTR_STAT | GEN_CALL
2054 * IC_INTR_STAT | START_DET
2055 * IC_INTR_STAT | STOP_DET
2056 * IC_INTR_STAT | ACTIVITY
2057 * IC_INTR_STAT | RX_DONE
2058 * IC_INTR_STAT | TX_ABRT
2059 * IC_INTR_STAT | RD_REQ
2060 * IC_INTR_STAT | TX_EMPTY
2061 * IC_INTR_STAT | TX_OVER
2062 * IC_INTR_STAT | RX_FULL
2063 * IC_INTR_STAT | RX_OVER
2064 * IC_INTR_STAT | RX_UNDER
2065 *
2066 * @param I2Cx I2C instance.
2067 * @retval Returned value can be one or combination of the following values:
2068 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2069 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2070 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2071 * @arg @ref LL_I2C_INTR_STAT_START_DET
2072 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2073 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2074 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2075 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2076 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2077 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2078 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2079 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2080 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2081 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2082 */
2083 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2084 {
2085 return (uint32_t)(READ_REG(I2Cx->INTR_STAT));
2086 }
2087
2088 /**
2089 * @brief Get I2C RAW interrupt flags
2090 *
2091 * Register|BitsName
2092 * --------|--------
2093 * IC_RAW_INTR_STAT | RAW_MST_ON_HOLD
2094 * IC_RAW_INTR_STAT | RAW_RESTART_DET
2095 * IC_RAW_INTR_STAT | RAW_GEN_CALL
2096 * IC_RAW_INTR_STAT | RAW_START_DET
2097 * IC_RAW_INTR_STAT | RAW_STOP_DET
2098 * IC_RAW_INTR_STAT | RAW_ACTIVITY
2099 * IC_RAW_INTR_STAT | RAW_RX_DONE
2100 * IC_RAW_INTR_STAT | RAW_TX_ABRT
2101 * IC_RAW_INTR_STAT | RAW_RD_REQ
2102 * IC_RAW_INTR_STAT | RAW_TX_EMPTY
2103 * IC_RAW_INTR_STAT | RAW_TX_OVER
2104 * IC_RAW_INTR_STAT | RAW_RX_FULL
2105 * IC_RAW_INTR_STAT | RAW_RX_OVER
2106 * IC_RAW_INTR_STAT | RAW_RX_UNDER
2107 *
2108 * @param I2Cx I2C instance.
2109 * @retval Returned value can be one or combination of the following values:
2110 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2111 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2112 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2113 * @arg @ref LL_I2C_INTR_STAT_START_DET
2114 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2115 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2116 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2117 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2118 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2119 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2120 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2121 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2122 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2123 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2124 */
2125 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2126 {
2127 return (uint32_t)(READ_REG(I2Cx->RAW_INTR_STAT));
2128 }
2129
2130 /**
2131 * @brief Indicate the status of MST_ON_HOLD flag.
2132 * @note RESET: Clear default value.
2133 * SET : When MST_ON_HOLD interrupt is actived.
2134 *
2135 * Register|BitsName
2136 * --------|--------
2137 * RAW_INTR_STAT | MST_ON_HOLD
2138 *
2139 * @param I2Cx I2C instance.
2140 * @retval State of bit (1 or 0).
2141 */
2142 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2143 {
2144 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2145 }
2146
2147 /**
2148 * @brief Indicate the status of RAW_MST_ON_HOLD flag.
2149 * @note RESET: Clear default value.
2150 * SET : When unmasked MST_ON_HOLD interrupt is actived.
2151 *
2152 * Register|BitsName
2153 * --------|--------
2154 * IC_RAW_INTR_STAT | RAW_MST_ON_HOLD
2155 *
2156 * @param I2Cx I2C instance.
2157 * @retval State of bit (1 or 0).
2158 */
2159 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2160 {
2161 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2162 }
2163
2164 /**
2165 * @brief Indicate the status of RESTART_DET flag.
2166 * @note RESET: Clear default value.
2167 * SET : When masked RESTART_DET interrupt is actived.
2168 *
2169 * Register|BitsName
2170 * --------|--------
2171 * IC_INTR_STAT | RESTART_DET
2172 *
2173 * @param I2Cx I2C instance.
2174 * @retval State of bit (1 or 0).
2175 */
2176 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2177 {
2178 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2179 }
2180
2181 /**
2182 * @brief Indicate the status of RAW_RESTART_DET flag.
2183 * @note RESET: Clear default value.
2184 * SET : When unmasked RESTART_DET interrupt is actived.
2185 *
2186 * Register|BitsName
2187 * --------|--------
2188 * IC_RAW_INTR_STAT | RAW_RESTART_DET
2189 *
2190 * @param I2Cx I2C instance.
2191 * @retval State of bit (1 or 0).
2192 */
2193 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2194 {
2195 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2196 }
2197
2198 /**
2199 * @brief Indicate the status of GEN_CALL flag.
2200 * @note RESET: Clear default value.
2201 * SET : When masked GEN_CALL interrupt is actived.
2202 *
2203 * Register|BitsName
2204 * --------|--------
2205 * IC_INTR_STAT | GEN_CALL
2206 *
2207 * @param I2Cx I2C instance.
2208 * @retval State of bit (1 or 0).
2209 */
2210 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2211 {
2212 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2213 }
2214
2215 /**
2216 * @brief Indicate the status of RAW_GEN_CALL flag.
2217 * @note RESET: Clear default value.
2218 * SET : When unmasked GEN_CALL interrupt is actived.
2219 *
2220 * Register|BitsName
2221 * --------|--------
2222 * IC_RAW_INTR_STAT | RAW_GEN_CALL
2223 *
2224 * @param I2Cx I2C instance.
2225 * @retval State of bit (1 or 0).
2226 */
2227 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2228 {
2229 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2230 }
2231
2232 /**
2233 * @brief Indicate the status of START_DET flag.
2234 * @note RESET: Clear default value.
2235 * SET : When masked START_DET interrupt is actived.
2236 *
2237 * Register|BitsName
2238 * --------|--------
2239 * IC_INTR_STAT | START_DET
2240 *
2241 * @param I2Cx I2C instance.
2242 * @retval State of bit (1 or 0).
2243 */
2244 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2245 {
2246 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2247 }
2248
2249 /**
2250 * @brief Indicate the status of RAW_START_DET flag.
2251 * @note RESET: Clear default value.
2252 * SET : When unmasked START_DET interrupt is actived.
2253 *
2254 * Register|BitsName
2255 * --------|--------
2256 * IC_RAW_INTR_STAT | RAW_START_DET
2257 *
2258 * @param I2Cx I2C instance.
2259 * @retval State of bit (1 or 0).
2260 */
2261 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2262 {
2263 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2264 }
2265
2266 /**
2267 * @brief Indicate the status of STOP_DET flag.
2268 * @note RESET: Clear default value.
2269 * SET : When masked STOP_DET interrupt is actived.
2270 *
2271 * Register|BitsName
2272 * --------|--------
2273 * IC_INTR_STAT | STOP_DET
2274 *
2275 * @param I2Cx I2C instance.
2276 * @retval State of bit (1 or 0).
2277 */
2278 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2279 {
2280 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2281 }
2282
2283 /**
2284 * @brief Indicate the status of RAW_STOP_DET flag.
2285 * @note RESET: Clear default value.
2286 * SET : When unmasked STOP_DET interrupt is actived.
2287 *
2288 * Register|BitsName
2289 * --------|--------
2290 * IC_RAW_INTR_STAT | RAW_STOP_DET
2291 *
2292 * @param I2Cx I2C instance.
2293 * @retval State of bit (1 or 0).
2294 */
2295 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2296 {
2297 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2298 }
2299
2300 /**
2301 * @brief Indicate the status of ACTIVITY flag.
2302 * @note RESET: Clear default value.
2303 * SET : When masked ACTIVITY interrupt is actived.
2304 *
2305 * Register|BitsName
2306 * --------|--------
2307 * IC_INTR_STAT | ACTIVITY
2308 *
2309 * @param I2Cx I2C instance.
2310 * @retval State of bit (1 or 0).
2311 */
2312 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2313 {
2314 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2315 }
2316
2317 /**
2318 * @brief Indicate the status of RAW_ACTIVITY flag.
2319 * @note RESET: Clear default value.
2320 * SET : When unmasked ACTIVITY interrupt is actived.
2321 *
2322 * Register|BitsName
2323 * --------|--------
2324 * IC_RAW_INTR_STAT | RAW_ACTIVITY
2325 *
2326 * @param I2Cx I2C instance.
2327 * @retval State of bit (1 or 0).
2328 */
2329 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2330 {
2331 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2332 }
2333
2334 /**
2335 * @brief Indicate the status of RX_DONE flag.
2336 * @note RESET: Clear default value.
2337 * SET : When masked RX_DONE interrupt is actived.
2338 *
2339 * Register|BitsName
2340 * --------|--------
2341 * IC_INTR_STAT | RX_DONE
2342 *
2343 * @param I2Cx I2C instance.
2344 * @retval State of bit (1 or 0).
2345 */
2346 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2347 {
2348 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2349 }
2350
2351 /**
2352 * @brief Indicate the status of RAW_RX_DONE flag.
2353 * @note RESET: Clear default value.
2354 * SET : When unmasked RX_DONE interrupt is actived.
2355 *
2356 * Register|BitsName
2357 * --------|--------
2358 * IC_RAW_INTR_STAT | RAW_RX_DONE
2359 *
2360 * @param I2Cx I2C instance.
2361 * @retval State of bit (1 or 0).
2362 */
2363 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2364 {
2365 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2366 }
2367
2368 /**
2369 * @brief Indicate the status of TX_ABRT flag.
2370 * @note RESET: Clear default value.
2371 * SET : When masked TX_ABRT interrupt is actived.
2372 *
2373 * Register|BitsName
2374 * --------|--------
2375 * IC_INTR_STAT | TX_ABRT
2376 *
2377 * @param I2Cx I2C instance.
2378 * @retval State of bit (1 or 0).
2379 */
2380 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2381 {
2382 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2383 }
2384
2385 /**
2386 * @brief Indicate the status of RAW_TX_ABRT flag.
2387 * @note RESET: Clear default value.
2388 * SET : When unmasked TX_ABRT interrupt is actived.
2389 *
2390 * Register|BitsName
2391 * --------|--------
2392 * IC_RAW_INTR_STAT | RAW_TX_ABRT
2393 *
2394 * @param I2Cx I2C instance.
2395 * @retval State of bit (1 or 0).
2396 */
2397 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2398 {
2399 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2400 }
2401
2402 /**
2403 * @brief Indicate the status of RD_REQ flag.
2404 * @note RESET: Clear default value.
2405 * SET : When masked RD_REQ interrupt is actived.
2406 *
2407 * Register|BitsName
2408 * --------|--------
2409 * IC_INTR_STAT | RD_REQ
2410 *
2411 * @param I2Cx I2C instance.
2412 * @retval State of bit (1 or 0).
2413 */
2414 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2415 {
2416 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2417 }
2418
2419 /**
2420 * @brief Indicate the status of RAW_RD_REQ flag.
2421 * @note RESET: Clear default value.
2422 * SET : When unmasked RD_REQ interrupt is actived.
2423 *
2424 * Register|BitsName
2425 * --------|--------
2426 * IC_RAW_INTR_STAT | RAW_RD_REQ
2427 *
2428 * @param I2Cx I2C instance.
2429 * @retval State of bit (1 or 0).
2430 */
2431 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2432 {
2433 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2434 }
2435
2436 /**
2437 * @brief Indicate the status of TX_EMPTY flag.
2438 * @note RESET: Clear default value.
2439 * SET : When masked TX_EMPTY interrupt is actived.
2440 *
2441 * Register|BitsName
2442 * --------|--------
2443 * IC_INTR_STAT | TX_EMPTY
2444 *
2445 * @param I2Cx I2C instance.
2446 * @retval State of bit (1 or 0).
2447 */
2448 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2449 {
2450 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2451 }
2452
2453 /**
2454 * @brief Indicate the status of RAW_TX_EMPTY flag.
2455 * @note RESET: Clear default value.
2456 * SET : When unmasked TX_EMPTY interrupt is actived.
2457 *
2458 * Register|BitsName
2459 * --------|--------
2460 * IC_RAW_INTR_STAT | RAW_TX_EMPTY
2461 *
2462 * @param I2Cx I2C instance.
2463 * @retval State of bit (1 or 0).
2464 */
2465 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2466 {
2467 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2468 }
2469
2470 /**
2471 * @brief Indicate the status of TX_OVER flag.
2472 * @note RESET: Clear default value.
2473 * SET : When masked TX_OVER interrupt is actived.
2474 *
2475 * Register|BitsName
2476 * --------|--------
2477 * IC_INTR_STAT | TX_OVER
2478 *
2479 * @param I2Cx I2C instance.
2480 * @retval State of bit (1 or 0).
2481 */
2482 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2483 {
2484 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2485 }
2486
2487 /**
2488 * @brief Indicate the status of RAW_TX_OVER flag.
2489 * @note RESET: Clear default value.
2490 * SET : When unmasked TX_OVER interrupt is actived.
2491 *
2492 * Register|BitsName
2493 * --------|--------
2494 * IC_RAW_INTR_STAT | RAW_TX_OVER
2495 *
2496 * @param I2Cx I2C instance.
2497 * @retval State of bit (1 or 0).
2498 */
2499 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2500 {
2501 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2502 }
2503
2504 /**
2505 * @brief Indicate the status of RX_FULL flag.
2506 * @note RESET: Clear default value.
2507 * SET : When masked RX_FULL interrupt is actived.
2508 *
2509 * Register|BitsName
2510 * --------|--------
2511 * IC_INTR_STAT | RX_FULL
2512 *
2513 * @param I2Cx I2C instance.
2514 * @retval State of bit (1 or 0).
2515 */
2516 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
2517 {
2518 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2519 }
2520
2521 /**
2522 * @brief Indicate the status of RAW_RX_FULL flag.
2523 * @note RESET: Clear default value.
2524 * SET : When unmasked RX_FULL interrupt is actived.
2525 *
2526 * Register|BitsName
2527 * --------|--------
2528 * IC_RAW_INTR_STAT | RAW_RX_FULL
2529 *
2530 * @param I2Cx I2C instance.
2531 * @retval State of bit (1 or 0).
2532 */
2533 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
2534 {
2535 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2536 }
2537
2538 /**
2539 * @brief Indicate the status of RX_OVER flag.
2540 * @note RESET: Clear default value.
2541 * SET : When masked RX_OVER interrupt is actived.
2542 *
2543 * Register|BitsName
2544 * --------|--------
2545 * IC_INTR_STAT | RX_OVER
2546 *
2547 * @param I2Cx I2C instance.
2548 * @retval State of bit (1 or 0).
2549 */
2550 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
2551 {
2552 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2553 }
2554
2555 /**
2556 * @brief Indicate the status of RAW_RX_OVER flag.
2557 * @note RESET: Clear default value.
2558 * SET : When unmasked RX_OVER interrupt is actived.
2559 *
2560 * Register|BitsName
2561 * --------|--------
2562 * IC_RAW_INTR_STAT | RAW_RX_OVER
2563 *
2564 * @param I2Cx I2C instance.
2565 * @retval State of bit (1 or 0).
2566 */
2567 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
2568 {
2569 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2570 }
2571
2572 /**
2573 * @brief Indicate the status of RX_UNDER flag.
2574 * @note RESET: Clear default value.
2575 * SET : When masked RX_UNDER interrupt is actived.
2576 *
2577 * Register|BitsName
2578 * --------|--------
2579 * IC_INTR_STAT | RX_UNDER
2580 *
2581 * @param I2Cx I2C instance.
2582 * @retval State of bit (1 or 0).
2583 */
2584 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
2585 {
2586 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2587 }
2588
2589 /**
2590 * @brief Indicate the status of RAW_RX_UNDER flag.
2591 * @note RESET: Clear default value.
2592 * SET : When unmasked RX_UNDER interrupt is actived.
2593 *
2594 * Register|BitsName
2595 * --------|--------
2596 * IC_RAW_INTR_STAT | RAW_RX_UNDER
2597 *
2598 * @param I2Cx I2C instance.
2599 * @retval State of bit (1 or 0).
2600 */
2601 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
2602 {
2603 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2604 }
2605
2606 /**
2607 * @brief Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
2608 *
2609 * Register|BitsName
2610 * --------|--------
2611 * IC_CLR_INTR | CLR_INTR
2612 *
2613 * @param I2Cx I2C instance.
2614 * @retval None.
2615 */
2616 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
2617 {
2618 __IO uint32_t tmpreg;
2619 tmpreg = READ_REG(I2Cx->CLR_INTR);
2620 (void) tmpreg;
2621 }
2622
2623 /**
2624 * @brief Clear GEN_CALL flag.
2625 *
2626 * Register|BitsName
2627 * --------|--------
2628 * IC_CLR_GEN_CALL | CLR_GEN_CALL
2629 *
2630 * @param I2Cx I2C instance.
2631 * @retval None.
2632 */
2633 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
2634 {
2635 __IO uint32_t tmpreg;
2636 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
2637 (void) tmpreg;
2638 }
2639
2640 /**
2641 * @brief Clear START_DET flag.
2642 *
2643 * Register|BitsName
2644 * --------|--------
2645 * IC_CLR_START_DET | CLR_START_DET
2646 *
2647 * @param I2Cx I2C instance.
2648 * @retval None.
2649 */
2650 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
2651 {
2652 __IO uint32_t tmpreg;
2653 tmpreg = READ_REG(I2Cx->CLR_START_DET);
2654 (void) tmpreg;
2655 }
2656
2657 /**
2658 * @brief Clear STOP_DET flag.
2659 *
2660 * Register|BitsName
2661 * --------|--------
2662 * IC_CLR_STOP_DET | CLR_STOP_DET
2663 *
2664 * @param I2Cx I2C instance.
2665 * @retval None.
2666 */
2667 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
2668 {
2669 __IO uint32_t tmpreg;
2670 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
2671 (void) tmpreg;
2672 }
2673
2674 /**
2675 * @brief Clear ACTIVITY flag.
2676 *
2677 * Register|BitsName
2678 * --------|--------
2679 * IC_CLR_ACTIVITY | CLR_ACTIVITY
2680 *
2681 * @param I2Cx I2C instance.
2682 * @retval None.
2683 */
2684 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
2685 {
2686 __IO uint32_t tmpreg;
2687 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
2688 (void) tmpreg;
2689 }
2690
2691 /**
2692 * @brief Clear RX_DONE flag.
2693 *
2694 * Register|BitsName
2695 * --------|--------
2696 * IC_CLR_RX_DONE | CLR_RX_DONE
2697 *
2698 * @param I2Cx I2C instance.
2699 * @retval None.
2700 */
2701 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
2702 {
2703 __IO uint32_t tmpreg;
2704 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
2705 (void) tmpreg;
2706 }
2707
2708 /**
2709 * @brief Clear TX_ABRT flag.
2710 *
2711 * Register|BitsName
2712 * --------|--------
2713 * IC_CLR_TX_ABRT | CLR_TX_ABRT
2714 *
2715 * @param I2Cx I2C instance.
2716 * @retval None.
2717 */
2718 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
2719 {
2720 __IO uint32_t tmpreg;
2721 tmpreg = READ_REG(I2Cx->CLR_TX_ABRT);
2722 (void) tmpreg;
2723 }
2724
2725 /**
2726 * @brief Clear RD_REQ flag.
2727 *
2728 * Register|BitsName
2729 * --------|--------
2730 * IC_CLR_RD_REQ | CLR_RD_REQ
2731 *
2732 * @param I2Cx I2C instance.
2733 * @retval None.
2734 */
2735 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
2736 {
2737 __IO uint32_t tmpreg;
2738 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
2739 (void) tmpreg;
2740 }
2741
2742 /**
2743 * @brief Clear TX_OVER flag.
2744 *
2745 * Register|BitsName
2746 * --------|--------
2747 * IC_CLR_TX_OVER | CLR_TX_OVER
2748 *
2749 * @param I2Cx I2C instance.
2750 * @retval None.
2751 */
2752 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
2753 {
2754 __IO uint32_t tmpreg;
2755 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
2756 (void) tmpreg;
2757 }
2758
2759 /**
2760 * @brief Clear RX_OVER flag.
2761 *
2762 * Register|BitsName
2763 * --------|--------
2764 * IC_CLR_RX_OVER | CLR_RX_OVER
2765 *
2766 * @param I2Cx I2C instance.
2767 * @retval None.
2768 */
2769 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
2770 {
2771 __IO uint32_t tmpreg;
2772 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
2773 (void) tmpreg;
2774 }
2775
2776 /**
2777 * @brief Clear RX_UNDER flag.
2778 *
2779 * Register|BitsName
2780 * --------|--------
2781 * IC_CLR_RX_UNDER | CLR_RX_UNDER
2782 *
2783 * @param I2Cx I2C instance.
2784 * @retval None.
2785 */
2786 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
2787 {
2788 __IO uint32_t tmpreg;
2789 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
2790 (void) tmpreg;
2791 }
2792
2793 /**
2794 * @brief Indicate the status of IC_STATUS Slave FSM Activity Status flag.
2795 * @note RESET: Slave FSM is in IDLE state.
2796 * SET : When Slave FSM is not in IDLE state.
2797 *
2798 * Register|BitsName
2799 * --------|--------
2800 * IC_STATUS | SLV_ACTIVITY
2801 *
2802 * @param I2Cx I2C instance.
2803 * @retval State of bit (1 or 0).
2804 */
2805 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
2806 {
2807 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_SLV_ACTIVITY) == (I2C_STATUS_SLV_ACTIVITY));
2808 }
2809
2810 /**
2811 * @brief Indicate the status of IC_STATUS Master FSM Activity Status flag.
2812 * @note RESET: Master FSM is in IDLE state.
2813 * SET : When Master FSM is not in IDLE state.
2814 *
2815 * Register|BitsName
2816 * --------|--------
2817 * IC_STATUS | MST_ACTIVITY
2818 *
2819 * @param I2Cx I2C instance.
2820 * @retval State of bit (1 or 0).
2821 */
2822 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
2823 {
2824 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_MST_ACTIVITY) == (I2C_STATUS_MST_ACTIVITY));
2825 }
2826
2827 /**
2828 * @brief Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
2829 * @note RESET: Receive FIFO is not full.
2830 * SET : When Receive FIFO is full.
2831 *
2832 * Register|BitsName
2833 * --------|--------
2834 * IC_STATUS | RFF
2835 *
2836 * @param I2Cx I2C instance.
2837 * @retval State of bit (1 or 0).
2838 */
2839 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
2840 {
2841 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFF) == (I2C_STATUS_RFF));
2842 }
2843
2844 /**
2845 * @brief Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
2846 * @note RESET: Receive FIFO is empty.
2847 * SET : When Receive FIFO is not empty.
2848 *
2849 * Register|BitsName
2850 * --------|--------
2851 * IC_STATUS | RFNE
2852 *
2853 * @param I2Cx I2C instance.
2854 * @retval State of bit (1 or 0).
2855 */
2856 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
2857 {
2858 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFNE) == (I2C_STATUS_RFNE));
2859 }
2860
2861 /**
2862 * @brief Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
2863 * @note RESET: Transmit FIFO is not empty.
2864 * SET : When Transmit FIFO is empty.
2865 *
2866 * Register|BitsName
2867 * --------|--------
2868 * IC_STATUS | TFE
2869 *
2870 * @param I2Cx I2C instance.
2871 * @retval State of bit (1 or 0).
2872 */
2873 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
2874 {
2875 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFE) == (I2C_STATUS_TFE));
2876 }
2877
2878 /**
2879 * @brief Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
2880 * @note RESET: Transmit FIFO is full.
2881 * SET : When Transmit FIFO is not full.
2882 *
2883 * Register|BitsName
2884 * --------|--------
2885 * IC_STATUS | TFNF
2886 *
2887 * @param I2Cx I2C instance.
2888 * @retval State of bit (1 or 0).
2889 */
2890 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
2891 {
2892 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFNF) == (I2C_STATUS_TFNF));
2893 }
2894
2895 /**
2896 * @brief Indicate the status of IC_STATUS ACTIVITY flag.
2897 * @note RESET: I2C is idle.
2898 * SET : When I2C is active.
2899 *
2900 * Register|BitsName
2901 * --------|--------
2902 * IC_STATUS | ACTIVITY
2903 *
2904 * @param I2Cx I2C instance.
2905 * @retval State of bit (1 or 0).
2906 */
2907 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
2908 {
2909 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_ACTIVITY) == (I2C_STATUS_ACTIVITY));
2910 }
2911
2912 /**
2913 * @brief Indicate the status of Slave Received Data Lost flag.
2914 * @note RESET: Slave RX Data is not lost.
2915 * SET : Slave RX Data is lost.
2916 *
2917 * Register|BitsName
2918 * --------|--------
2919 * IC_ENABLE_STATUS | SLV_RX_LOST
2920 *
2921 * @param I2Cx I2C instance.
2922 * @retval State of bit (1 or 0).
2923 */
2924 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
2925 {
2926 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_RX_LOST) == (I2C_ENABLE_STATUS_SLV_RX_LOST));
2927 }
2928
2929 /**
2930 * @brief Indicate the status of Slave Disabled While Busy flag.
2931 * @note RESET: Slave is disabled when it is idle.
2932 * SET : Slave is disabled when it is active.
2933 *
2934 * Register|BitsName
2935 * --------|--------
2936 * IC_ENABLE_STATUS | SLV_DIS_WHL_BUSY
2937 *
2938 * @param I2Cx I2C instance.
2939 * @retval State of bit (1 or 0).
2940 */
2941 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
2942 {
2943 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY) == (I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY));
2944 }
2945 /** @} */
2946
2947 /** @defgroup I2C_LL_EF_DMA_Management DMA_Management
2948 * @{
2949 */
2950
2951 /**
2952 * @brief Enable DMA transmission requests.
2953 *
2954 * Register|BitsName
2955 * --------|--------
2956 * IC_DMA_CR | TDMAE
2957 *
2958 * @retval Value range between 0 ~ 0x8.
2959 * @retval None.
2960 */
2961 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
2962 {
2963 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2964 }
2965
2966 /**
2967 * @brief Disable DMA transmission requests.
2968 *
2969 * Register|BitsName
2970 * --------|--------
2971 * IC_DMA_CR | TDMAE
2972 *
2973 * @param I2Cx I2C instance.
2974 * @retval None.
2975 */
2976 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
2977 {
2978 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2979 }
2980
2981 /**
2982 * @brief Check if DMA transmission requests are enabled or disabled.
2983 *
2984 * Register|BitsName
2985 * --------|--------
2986 * IC_DMA_CR | TDMAE
2987 *
2988 * @param I2Cx I2C instance.
2989 * @retval State of bit (1 or 0).
2990 */
2991 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
2992 {
2993 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE) == (I2C_DMA_CR_TDMAE));
2994 }
2995
2996 /**
2997 * @brief Enable DMA reception requests.
2998 *
2999 * Register|BitsName
3000 * --------|--------
3001 * IC_DMA_CR | RDMAE
3002 *
3003 * @param I2Cx I2C instance.
3004 * @retval None.
3005 */
3006 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3007 {
3008 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3009 }
3010
3011 /**
3012 * @brief Disable DMA reception requests.
3013 *
3014 * Register|BitsName
3015 * --------|--------
3016 * IC_DMA_CR | RDMAE
3017 *
3018 * @param I2Cx I2C instance.
3019 * @retval None.
3020 */
3021 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3022 {
3023 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3024 }
3025
3026 /**
3027 * @brief Check if DMA reception requests are enabled or disabled.
3028 *
3029 * Register|BitsName
3030 * --------|--------
3031 * IC_DMA_CR | RDMAE
3032 *
3033 * @param I2Cx I2C instance.
3034 * @retval State of bit (1 or 0).
3035 */
3036 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3037 {
3038 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE) == (I2C_DMA_CR_RDMAE));
3039 }
3040
3041 /**
3042 * @brief Set level of TX FIFO that requests a DMA transmit.
3043 * @note TX data level should equal to the watermark level, that is, the dma_tx_req
3044 * signal is generated when the number of valid data entries in the transmit
3045 * FIFO is equal to or below this field value, and TDMAE = 1.
3046 *
3047 * Register|BitsName
3048 * --------|--------
3049 * IC_DMA_TDLR | DMATDL
3050 *
3051 * @param I2Cx I2C instance
3052 * @param level This parameter should range between 0x0 and 0x8.
3053 * @retval None.
3054 */
3055 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3056 {
3057 WRITE_REG(I2Cx->DMA_TDLR, level);
3058 }
3059
3060 /**
3061 * @brief Get level of TX FIFO that request a DMA transmit.
3062 *
3063 * Register|BitsName
3064 * --------|--------
3065 * IC_DMA_TDLR | DMATDL
3066 *
3067 * @param I2Cx I2C instance
3068 * @retval Returned value should range between 0x0 and 0x8.
3069 */
3070 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3071 {
3072 return (uint32_t)(READ_BITS(I2Cx->DMA_TDLR, I2C_DMA_TDLR_DMATDL));
3073 }
3074
3075 /**
3076 * @brief Set level of RX FIFO that requests a DMA receive.
3077 * @note The watermark level = DMARDL + 1, that is, dma_rx_req is generated when
3078 * the number of valid data entries in the receive FIFO is equal to or
3079 * more than this field value + 1, and RDMAE = 1. For instance, when DMARDL
3080 * is 0, then dma_rx_req is asserted when 1 or more data entries are present
3081 * in the receive FIFO.
3082 *
3083 * Register|BitsName
3084 * --------|--------
3085 * IC_DMA_RDLR | DMARDL
3086 *
3087 * @param I2Cx I2C instance
3088 * @param level This parameter should range between 0x0 and 0x8.
3089 * @retval None.
3090 */
3091 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3092 {
3093 WRITE_REG(I2Cx->DMA_RDLR, level);
3094 }
3095
3096 /**
3097 * @brief Get level of RX FIFO that request a DMA receive.
3098 *
3099 * Register|BitsName
3100 * --------|--------
3101 * IC_DMA_RDLR | DMARDL
3102 *
3103 * @param I2Cx I2C instance
3104 * @retval Returned value should range between 0x0 and 0x8.
3105 */
3106 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3107 {
3108 return (uint32_t)(READ_BITS(I2Cx->DMA_RDLR, I2C_DMA_RDLR_DMARDL));
3109 }
3110
3111 /**
3112 * @brief Get the data register address used for DMA transfer
3113 *
3114 * Register|BitsName
3115 * --------|--------
3116 * IC_DATA_CMD | DAT
3117 *
3118 * @param I2Cx I2C instance
3119 * @retval Address of data register
3120 */
3121 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3122 {
3123 return ((uint32_t) & (I2Cx->DATA_CMD));
3124 }
3125
3126 /** @} */
3127
3128 /** @defgroup I2C_LL_EF_Data_Management Data_Management
3129 * @{
3130 */
3131
3132 /**
3133 * @brief Configure the slave address for transfer (master mode).
3134 * @note The register IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3135 *
3136 * Register|BitsName
3137 * --------|--------
3138 * IC_TAR | TAR_ADDR
3139 *
3140 * @param I2Cx I2C instance.
3141 * @param slave_addr This parameter must be a value between 0x00 and 0x3F.
3142 * @retval None.
3143 */
3144 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3145 {
3146 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3147 }
3148
3149 /**
3150 * @brief Get the slave address programmed for transfer (master mode).
3151 *
3152 * Register|BitsName
3153 * --------|--------
3154 * IC_TAR | TAR_ADDR
3155 *
3156 * @param I2Cx I2C instance.
3157 * @retval Value between 0x0 and0x3F
3158 */
3159 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3160 {
3161 return (uint32_t)(READ_BITS(I2Cx->TAR, I2C_TAR_ADDR) >> I2C_TAR_ADDR_Pos);
3162 }
3163
3164 /**
3165 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
3166 * @note The register IC_CON and IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3167 *
3168 * Register|BitsName
3169 * --------|--------
3170 * IC_CON | CON_10BITADDR_MST
3171 * IC_TAR | TAR_ADDR
3172 *
3173 * @param I2Cx I2C instance.
3174 * @param slave_addr Specifies the slave address to be programmed.
3175 * @param slave_addr_size This parameter can be one of the following values:
3176 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
3177 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
3178 * @note SlaveAddrSize in IC_CON register can only be programmed when the I2C is disabled (IC_ENABLE = 0).
3179 * @retval None.
3180 */
3181 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3182 {
3183 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3184 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3185 }
3186
3187 /**
3188 * @brief Indicate the value of transfer direction (slave mode).
3189 * @note RESET: Write transfer, Slave enters in receiver mode.
3190 * SET: Read transfer, Slave enters in transmitter mode.
3191 *
3192 * Register|BitsName
3193 * --------|--------
3194 * IC_RAW_INTR_STAT | INTR_RD_REQ
3195 * IC_RAW_INTR_STAT | INTR_RX_FULL
3196 *
3197 * @param I2Cx I2C instance.
3198 * @retval Returned value can be one of the following values:
3199 * @arg @ref LL_I2C_DIRECTION_WRITE
3200 * @arg @ref LL_I2C_DIRECTION_READ
3201 */
3202 __STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
3203 {
3204 return (uint32_t)(READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ | I2C_INTR_RX_FULL));
3205 }
3206
3207 /**
3208 * @brief Read Receive Data register.
3209 *
3210 * Register|BitsName
3211 * --------|--------
3212 * IC_DATA_CMD | DAT
3213 *
3214 * @param I2Cx I2C instance.
3215 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3216 */
3217 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3218 {
3219 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DAT));
3220 }
3221
3222 /**
3223 * @brief Write in Transmit Data Register .
3224 *
3225 * Register|BitsName
3226 * --------|--------
3227 * IC_DATA_CMD | STOP
3228 * IC_DATA_CMD | CMD
3229 * IC_DATA_CMD | DAT
3230 *
3231 * @param I2Cx I2C instance.
3232 * @param data Value range between 0x00 and 0xFF.
3233 * @param cmd This parameter can be one of the following values:
3234 * @arg @ref LL_I2C_CMD_SLV_NONE
3235 * @arg @ref LL_I2C_CMD_MST_WRITE
3236 * @arg @ref LL_I2C_CMD_MST_READ
3237 * @arg @ref LL_I2C_CMD_MST_GEN_STOP
3238 * @arg @ref LL_I2C_CMD_MST_GEN_RESTART
3239 * @retval None.
3240 */
3241 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3242 {
3243 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3244 }
3245
3246 /** @} */
3247
3248 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
3249 * @{
3250 */
3251
3252 /**
3253 * @brief De-initialize I2C registers (Registers restored to their default values).
3254 * @param I2Cx I2C instance
3255 * @retval An error_status_t enumeration value:
3256 * - SUCCESS: I2C registers are de-initialized
3257 * - ERROR: I2C registers are not de-initialized
3258 */
3259 error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx);
3260
3261 /**
3262 * @brief Initialize I2C registers according to the specified
3263 * parameters in p_i2c_init.
3264 * @param I2Cx I2C instance
3265 * @param p_i2c_init Pointer to a ll_i2c_init_t structure that contains the configuration
3266 * information for the specified I2C peripheral.
3267 * @retval An error_status_t enumeration value:
3268 * - SUCCESS: I2C registers are initialized according to p_i2c_init content
3269 * - ERROR: Problem occurred during I2C Registers initialization
3270 */
3271 error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3272
3273 /**
3274 * @brief Set each field of a @ref ll_i2c_init_t type structure to default value.
3275 * @param p_i2c_init Pointer to a @ref ll_i2c_init_t structure
3276 * whose fields will be set to default values.
3277 * @retval None
3278 */
3279 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3280
3281 /** @} */
3282
3283 /** @} */
3284
3285 #endif /* I2C0 || I2C1 */
3286
3287 #ifdef __cplusplus
3288 }
3289 #endif
3290
3291 #endif /* __GR55xx_LL_I2C_H__ */
3292
3293 /** @} */
3294
3295 /** @} */
3296
3297 /** @} */
ll_i2c_is_active_flag_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2482
ll_i2c_enable
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
Definition: gr55xx_ll_i2c.h:340
_ll_i2c_init::own_addr_size
uint32_t own_addr_size
Specifies the device own address 1 size (7-bit or 10-bit).
Definition: gr55xx_ll_i2c.h:85
ll_i2c_enable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:541
ll_i2c_is_active_flag_status_tfnf
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
Definition: gr55xx_ll_i2c.h:2890
ll_i2c_is_enabled_transfer_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1214
ll_i2c_is_active_flag_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2346
ll_i2c_get_clock_low_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:760
ll_i2c_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_i2c.h:1169
ll_i2c_is_enabled_it_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1630
ll_i2c_is_enabled_it_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1450
ll_i2c_set_speed_mode
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
Definition: gr55xx_ll_i2c.h:908
ll_i2c_enable_it_tx_over
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1870
ll_i2c_disable_it_tx_over
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1885
ll_i2c_is_active_flag_status_master_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:2822
ll_i2c_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1154
ll_i2c_get_abort_source
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
Definition: gr55xx_ll_i2c.h:1267
ll_i2c_is_active_flag_raw_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2159
ll_i2c_is_active_flag_status_rfne
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
Definition: gr55xx_ll_i2c.h:2856
ll_i2c_clear_flag_rx_under
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2786
ll_i2c_dma_get_register_address
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_i2c.h:3121
ll_i2c_clear_flag_tx_over
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2752
ll_i2c_disable_it_tx_empty
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1840
ll_i2c_is_active_flag_raw_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2397
ll_i2c_enable_dma_req_tx
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:2961
ll_i2c_is_enabled_it_start_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1585
ll_i2c_is_enabled_stop_det_if_addressed
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
Definition: gr55xx_ll_i2c.h:572
ll_i2c_enable_it_start_det
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1555
ll_i2c_get_data_setup_time
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1058
ll_i2c_is_active_flag_raw_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2431
ll_i2c_is_active_flag_status_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2907
ll_i2c_disable_it_master_om_hold
__STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1435
ll_i2c_enable_transfer_abort
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:1199
ll_i2c_get_spike_len_fs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:856
ll_i2c_deinit
error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
ll_i2c_is_active_flag_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2584
ll_i2c_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1083
ll_i2c_is_active_flag_raw_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2329
ll_i2c_get_clock_low_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:824
ll_i2c_is_active_flag_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2278
ll_i2c_is_enabled_master_mode
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
Definition: gr55xx_ll_i2c.h:421
ll_i2c_disable_dma_req_tx
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:2976
ll_i2c_disable_it_rx_over
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1975
_ll_i2c_init::speed
uint32_t speed
Specifies the transfer speed.
Definition: gr55xx_ll_i2c.h:78
ll_i2c_enable_it_read_req
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:1780
ll_i2c_is_active_flag_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2550
ll_i2c_is_enabled_it_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2035
ll_i2c_enable_it_stop_det
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1600
ll_i2c_disable_dma_req_rx
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3021
ll_i2c_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1131
ll_i2c_is_active_flag_status_tfe
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
Definition: gr55xx_ll_i2c.h:2873
ll_i2c_is_active_flag_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2176
ll_i2c_set_dma_rx_data_level
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
Definition: gr55xx_ll_i2c.h:3091
ll_i2c_disable_it_restart_det
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1480
ll_i2c_is_active_flag_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2142
ll_i2c_disable_it
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
Definition: gr55xx_ll_i2c.h:1366
ll_i2c_disable_master_restart
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
Definition: gr55xx_ll_i2c.h:506
ll_i2c_get_clock_high_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:792
ll_i2c_clear_flag_intr
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: gr55xx_ll_i2c.h:2616
ll_i2c_is_enabled_it_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1495
ll_i2c_get_tx_flush_count
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1282
ll_i2c_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_i2c.h:1106
ll_i2c_disable_it_stop_det
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1615
ll_i2c_is_enabled_it_activity
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1675
ll_i2c_get_data_rx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1024
ll_i2c_get_clock_high_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:664
ll_i2c_init
error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
ll_i2c_disbale_it_rx_full
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:1930
ll_i2c_get_slave_address
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3159
ll_i2c_is_active_flag_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2516
ll_i2c_enable_it_master_on_hold
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1420
ll_i2c_is_enabled_it_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1765
ll_i2c_set_own_address
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
Definition: gr55xx_ll_i2c.h:631
ll_i2c_clear_flag_start_det
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
Definition: gr55xx_ll_i2c.h:2650
ll_i2c_set_master_addressing_mode
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
Definition: gr55xx_ll_i2c.h:591
ll_i2c_disable_it_gen_call
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1525
ll_i2c_clear_flag_stop_det
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2667
ll_i2c_disable_it_start_det
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1570
ll_i2c_is_active_flag_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2312
ll_i2c_disable_master_mode
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
Definition: gr55xx_ll_i2c.h:405
ll_i2c_is_active_flag_raw_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2227
ll_i2c_get_master_addressing_mode
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
Definition: gr55xx_ll_i2c.h:609
ll_i2c_clear_flag_tx_abort
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2718
ll_i2c_disable_it_activity
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1660
ll_i2c_is_active_flag_slave_rx_data_lost
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
Definition: gr55xx_ll_i2c.h:2924
_ll_i2c_init
LL I2C init Structure definition.
Definition: gr55xx_ll_i2c.h:77
ll_i2c_is_active_flag_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2380
ll_i2c_disable_it_read_req
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:1795
ll_i2c_is_enabled_general_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
Definition: gr55xx_ll_i2c.h:468
ll_i2c_get_dma_rx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
Definition: gr55xx_ll_i2c.h:3106
ll_i2c_enable_it
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
Definition: gr55xx_ll_i2c.h:1327
ll_i2c_is_active_flag_slave_dis_whl_busy
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
Definition: gr55xx_ll_i2c.h:2941
ll_i2c_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:2991
ll_i2c_clear_flag_rx_done
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2701
ll_i2c_set_clock_low_period_ss
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:681
ll_i2c_clear_flag_rx_over
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2769
ll_i2c_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3036
ll_i2c_enable_dma_req_rx
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3006
ll_i2c_is_active_flag_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2448
ll_i2c_is_active_flag_raw_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2465
ll_i2c_is_enabled_it_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1990
ll_i2c_receive_data8
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
Definition: gr55xx_ll_i2c.h:3217
ll_i2c_struct_init
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
ll_i2c_disable_general_call
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:453
ll_i2c_is_enabled_it_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1900
ll_i2c_set_data_rx_hold_time
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1009
ll_i2c_set_spike_len_hs
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:873
ll_i2c_enable_it_rx_under
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2005
ll_i2c_enable_general_call
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:437
ll_i2c_is_active_flag_status_slave_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:2805
ll_i2c_set_dma_tx_data_level
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
Definition: gr55xx_ll_i2c.h:3055
ll_i2c_is_enabled_it
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1405
ll_i2c_get_dma_tx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
Definition: gr55xx_ll_i2c.h:3070
ll_i2c_is_active_flag_raw_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2363
ll_i2c_get_high_speed_master_code
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:958
ll_i2c_set_clock_high_period_fs
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:713
ll_i2c_enable_it_rx_over
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:1960
ll_i2c_enable_it_activity
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1645
ll_i2c_is_active_flag_raw_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
Definition: gr55xx_ll_i2c.h:2261
ll_i2c_ls_enabled_it_rx_full
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1945
ll_i2c_set_clock_high_period_hs
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:777
ll_i2c_get_data_tx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:991
ll_i2c_clear_flag_read_req
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2735
ll_i2c_is_active_flag_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2414
ll_i2c_get_spike_len_hs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:888
ll_i2c_enable_it_rx_done
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:1690
ll_i2c_enable_master_restart
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
Definition: gr55xx_ll_i2c.h:490
ll_i2c_init_t
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
ll_i2c_is_enabled_it_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1855
ll_i2c_is_active_flag_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2210
ll_i2c_clear_flag_activity
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2684
ll_i2c_is_active_flag_status_rff
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
Definition: gr55xx_ll_i2c.h:2839
ll_i2c_set_data_setup_time
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1043
ll_i2c_enable_master_mode
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
Definition: gr55xx_ll_i2c.h:390
ll_i2c_set_clock_low_period_hs
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:809
ll_i2c_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
Definition: gr55xx_ll_i2c.h:1184
ll_i2c_get_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
Definition: gr55xx_ll_i2c.h:2083
ll_i2c_is_active_flag_raw_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2193
ll_i2c_is_enabled_it_read_req
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1810
ll_i2c_enable_it_gen_call
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1510
ll_i2c_disable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:557
ll_i2c_is_enabled_master_restart
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
Definition: gr55xx_ll_i2c.h:521
ll_i2c_get_speed_mode
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:926
ll_i2c_set_slave_address
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3144
ll_i2c_set_high_speed_master_code
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
Definition: gr55xx_ll_i2c.h:943
ll_i2c_disable_it_rx_done
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:1705
ll_i2c_is_enabled
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
Definition: gr55xx_ll_i2c.h:375
ll_i2c_enable_it_restart_det
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1465
ll_i2c_is_active_flag_raw_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
Definition: gr55xx_ll_i2c.h:2533
ll_i2c_is_active_flag_raw_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:2601
ll_i2c_set_clock_high_period_ss
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:649
ll_i2c_is_active_flag_raw_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2499
ll_i2c_is_active_flag_raw_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2295
ll_i2c_disable_it_rx_under
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2020
ll_i2c_set_clock_low_period_fs
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:745
ll_i2c_is_enable_it_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1720
ll_i2c_handle_transfer
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
Definition: gr55xx_ll_i2c.h:3181
ll_i2c_clear_flag_gen_call
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2633
ll_i2c_get_transfer_direction
__STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
Indicate the value of transfer direction (slave mode).
Definition: gr55xx_ll_i2c.h:3202
ll_i2c_is_active_flag_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
Definition: gr55xx_ll_i2c.h:2244
ll_i2c_get_clock_high_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:728
ll_i2c_enable_it_rx_abort
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1735
ll_i2c_enable_it_tx_empty
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1825
ll_i2c_set_data_tx_hold_time
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:976
_ll_i2c_init::own_address
uint32_t own_address
Specifies the device own address.
Definition: gr55xx_ll_i2c.h:80
ll_i2c_disable
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
Definition: gr55xx_ll_i2c.h:360
ll_i2c_set_spike_len_fs
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:841
ll_i2c_is_enabled_it_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1540
ll_i2c_disable_it_tx_abort
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1750
ll_i2c_is_active_flag_raw_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
Definition: gr55xx_ll_i2c.h:2567
ll_i2c_get_raw_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
Definition: gr55xx_ll_i2c.h:2125
ll_i2c_get_clock_low_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:696
ll_i2c_transmit_data8
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
Definition: gr55xx_ll_i2c.h:3241
ll_i2c_enable_it_rx_full
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:1915