Cache driver functions

Functions

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache (xqspi_regs_t *XQSPIx)
 Enable cache function. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache (xqspi_regs_t *XQSPIx)
 Disable cache function. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache (xqspi_regs_t *XQSPIx)
 Check if cache function is enabled. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush (xqspi_regs_t *XQSPIx)
 Enable tag memory flush. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush (xqspi_regs_t *XQSPIx)
 Disable tag memory flush. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush (xqspi_regs_t *XQSPIx)
 Check if tag memory flush is enabled. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo (xqspi_regs_t *XQSPIx, uint32_t mode)
 Set FIFO mode. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo (xqspi_regs_t *XQSPIx)
 Get FIFO mode. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss (xqspi_regs_t *XQSPIx, uint32_t mode)
 Set HIT/MISS mode. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss (xqspi_regs_t *XQSPIx)
 Get HIT/MISS mode. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus (xqspi_regs_t *XQSPIx, uint32_t sel)
 Set debugbus configurations signals. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus (xqspi_regs_t *XQSPIx)
 Get debugbus configurations signals. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux (xqspi_regs_t *XQSPIx)
 Enable debug bus mux. More...
 
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux (xqspi_regs_t *XQSPIx)
 Disable debug bus mux. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux (xqspi_regs_t *XQSPIx)
 Check if debug bus mux is enabled. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount (xqspi_regs_t *XQSPIx)
 Get hit counter. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount (xqspi_regs_t *XQSPIx)
 Get miss counter. More...
 
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag (xqspi_regs_t *XQSPIx)
 Get cache status. More...
 

Detailed Description

Function Documentation

◆ ll_xqspi_disable_cache()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache ( xqspi_regs_t *  XQSPIx)

Disable cache function.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 EN
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 393 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_disable_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux ( xqspi_regs_t *  XQSPIx)

Disable debug bus mux.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL1 DBGMUX_EN
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 596 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_disable_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush ( xqspi_regs_t *  XQSPIx)

Disable tag memory flush.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 TAG
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 443 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_enable_cache()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache ( xqspi_regs_t *  XQSPIx)

Enable cache function.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 EN
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 374 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_enable_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux ( xqspi_regs_t *  XQSPIx)

Enable debug bus mux.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL1 DBGMUX_EN
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 580 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_enable_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush ( xqspi_regs_t *  XQSPIx)

Enable tag memory flush.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 TAG
Parameters
XQSPIxXQSPI instance
Return values
None

Definition at line 427 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_dbgbus()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus ( xqspi_regs_t *  XQSPIx)

Get debugbus configurations signals.

Register BitsName
CTRL1 DBGBUS_SEL
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can between: 0 ~ 0x7

Definition at line 564 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_fifo()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo ( xqspi_regs_t *  XQSPIx)

Get FIFO mode.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 FIFO
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can be one of the following values:

Definition at line 495 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_flag()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag ( xqspi_regs_t *  XQSPIx)

Get cache status.

Note
This bit only be read.
Register BitsName
STAT STAT
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can between: 0 ~ 1

Definition at line 659 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_hitcount()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount ( xqspi_regs_t *  XQSPIx)

Get hit counter.

Note
This bit only be read.
Register BitsName
HIT_COUNT HITCOUNT
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can between: 0 ~ 0xFFFFFFFF

Definition at line 627 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_hitmiss()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss ( xqspi_regs_t *  XQSPIx)

Get HIT/MISS mode.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 HITMISS
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can be one of the following values:

Definition at line 532 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_get_cache_misscount()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount ( xqspi_regs_t *  XQSPIx)

Get miss counter.

Note
This bit only be read.
Register BitsName
MISS_COUNT MISSCOUNT
Parameters
XQSPIxXQSPI instance
Return values
ReturnedValue can between: 0 ~ 0xFFFFFFFF

Definition at line 643 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_is_enabled_cache()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache ( xqspi_regs_t *  XQSPIx)

Check if cache function is enabled.

Register BitsName
CTRL0 EN
Parameters
XQSPIxXQSPI instance
Return values
Stateof bit (1 or 0).

Definition at line 411 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_is_enabled_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux ( xqspi_regs_t *  XQSPIx)

Check if debug bus mux is enabled.

Register BitsName
CTRL1 DBGMUX_EN
Parameters
XQSPIxXQSPI instance
Return values
Stateof bit (1 or 0).

Definition at line 611 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_is_enabled_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush ( xqspi_regs_t *  XQSPIx)

Check if tag memory flush is enabled.

Register BitsName
CTRL0 TAG
Parameters
XQSPIxXQSPI instance
Return values
Stateof bit (1 or 0).

Definition at line 458 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_set_cache_dbgbus()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus ( xqspi_regs_t *  XQSPIx,
uint32_t  sel 
)

Set debugbus configurations signals.

Note
These bits should not be changed when XIP is ongoing.
Register BitsName
CTRL1 DBGBUS_SEL
Parameters
XQSPIxXQSPI instance
selThis parameter can between: 0 ~ 0x7
Return values
None

Definition at line 549 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_set_cache_fifo()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo ( xqspi_regs_t *  XQSPIx,
uint32_t  mode 
)

Set FIFO mode.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 FIFO
Parameters
XQSPIxXQSPI instance
modeThis parameter can be one of the following values:
Return values
None

Definition at line 477 of file gr55xx_ll_xqspi.h.

◆ ll_xqspi_set_cache_hitmiss()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss ( xqspi_regs_t *  XQSPIx,
uint32_t  mode 
)

Set HIT/MISS mode.

Note
This bit should not be changed when XIP is ongoing.
Register BitsName
CTRL0 HITMISS
Parameters
XQSPIxXQSPI instance
modeThis parameter can be one of the following values:
Return values
None

Definition at line 514 of file gr55xx_ll_xqspi.h.