gr55xx_ll_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_GPIO GPIO
47 * @brief GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPIO_H__
53 #define __GR55XX_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (GPIO0) || defined (GPIO1)
63
64 /** @defgroup GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup GPIO_LL_ES_INIT GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL GPIO init configuration definition
75 */
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin; /*!< Specifies the GPIO pins to be GPIO_InitStructured.
79 This parameter can be any value of @ref GPIO_LL_EC_PIN */
80
81 uint32_t mode; /*!< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref GPIO_LL_EC_MODE.
83
84 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_mode(). */
85
86 uint32_t pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref GPIO_LL_EC_PULL.
88
89 GPIO HW configuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref GPIO_LL_EC_MUX.
93
94 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_gpio_set_mux_pin_0_7() and ll_gpio_set_mux_pin_8_15(). */
96
97 uint32_t trigger; /*!< Specifies the trigger signal active edge.
98 This parameter can be a value of @ref GPIO_LL_EC_TRIGGER. */
99
100 } ll_gpio_init_t;
101
102 /** @} */
103
104 /** @} */
105
106 /**
107 * @defgroup GPIO_LL_MACRO Defines
108 * @{
109 */
110
111 /* Exported constants --------------------------------------------------------*/
112 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
113 * @{
114 */
115
116 /** @defgroup GPIO_LL_EC_PIN PIN
117 * @{
118 */
119 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U) /*!< Select pin 0 */
120 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U) /*!< Select pin 1 */
121 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U) /*!< Select pin 2 */
122 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U) /*!< Select pin 3 */
123 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U) /*!< Select pin 4 */
124 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U) /*!< Select pin 5 */
125 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U) /*!< Select pin 6 */
126 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U) /*!< Select pin 7 */
127 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U) /*!< Select pin 8 */
128 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U) /*!< Select pin 9 */
129 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U) /*!< Select pin 10 */
130 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U) /*!< Select pin 11 */
131 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U) /*!< Select pin 12 */
132 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U) /*!< Select pin 13 */
133 #define LL_GPIO_PIN_14 ((uint32_t)0x4000U) /*!< Select pin 14 */
134 #define LL_GPIO_PIN_15 ((uint32_t)0x8000U) /*!< Select pin 15 */
135 #define LL_GPIO_PIN_ALL ((uint32_t)0xFFFFU) /*!< Select all pins */
136 /** @} */
137
138 /** @defgroup GPIO_LL_EC_MODE Mode
139 * @{
140 */
141 #define LL_GPIO_MODE_INPUT ((uint32_t)0x0U) /*!< Select input mode */
142 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /*!< Select output mode */
143 #define LL_GPIO_MODE_MUX ((uint32_t)0x2U) /*!< Select mux peripheral mode */
144 /** @} */
145
146 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
147 * @{
148 */
149 #define LL_GPIO_PULL_NO LL_GPIO_RE_N /*!< Select I/O no pull */
150 #define LL_GPIO_PULL_UP LL_GPIO_RTYP /*!< Select I/O pull up */
151 #define LL_GPIO_PULL_DOWN ((uint32_t)0x0U) /*!< Select I/O pull down */
152 /** @} */
153
154 /** @defgroup GPIO_LL_EC_MUX Alternate Function
155 * @{
156 */
157 #define LL_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
158 #define LL_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
159 #define LL_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
160 #define LL_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
161 #define LL_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
162 #define LL_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
163 #define LL_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
164 #define LL_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
165 #define LL_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
166 /** @} */
167
168 /** @defgroup GPIO_LL_EC_TRIGGER Interrupt Trigger
169 * @{
170 */
171 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /*!< No Trigger Mode */
172 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /*!< Trigger Rising Mode */
173 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /*!< Trigger Falling Mode */
174 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /*!< Trigger High Mode */
175 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /*!< Trigger Low Mode */
176 /** @} */
177
178 /** @defgroup GPIO_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
179 * @{
180 */
181
182 /**
183 * @brief LL GPIO InitStrcut default configuartion
184 */
185 #define LL_GPIO_DEFAULT_CONFIG \
186 { \
187 .pin = LL_GPIO_PIN_ALL, \
188 .mode = LL_GPIO_MODE_INPUT, \
189 .pull = LL_GPIO_PULL_DOWN, \
190 .mux = LL_GPIO_MUX_7, \
191 .trigger = LL_GPIO_TRIGGER_NONE, \
192 }
193 /** @} */
194
195 /** @} */
196
197 /* Exported macro ------------------------------------------------------------*/
198 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
199 * @{
200 */
201
202 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
203 * @{
204 */
205
206 /**
207 * @brief Write a value in GPIO register
208 * @param __instance__ GPIO instance
209 * @param __REG__ Register to be written
210 * @param __VALUE__ Value to be written in the register
211 * @retval None
212 */
213 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
214
215 /**
216 * @brief Read a value in GPIO register
217 * @param __instance__ GPIO instance
218 * @param __REG__ Register to be read
219 * @retval Register value
220 */
221 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
222
223 /** @} */
224
225 /** @} */
226
227 /* Private types -------------------------------------------------------------*/
228 /* Private variables ---------------------------------------------------------*/
229 /* Private constants ---------------------------------------------------------*/
230 /* Private macros ------------------------------------------------------------*/
231 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
232 * @{
233 */
234
235 /** @brief Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
236 * @param __GPIOx__ This parameter can be one of the following values:
237 * @arg GPIO0
238 * @arg GPIO1
239 * @retval none
240 */
241 #define LL_GPIO_GET_RESISTOR_POS(__GPIOx__) (((__GPIOx__) == GPIO0) ? 0 : 16)
242
243 /** @brief Get mux control register address of specified GPIO instance.
244 * @param __GPIOx__ This parameter can be one of the following values:
245 * @arg GPIO0
246 * @arg GPIO1
247 * @retval none
248 */
249 #define LL_GPIO_GET_REG_MUX_CTRL_0_7( __GPIOx__) \
250 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL0_7) : &(MCU_SUB->DPAD_MUX_CTL16_23))
251
252 /** @brief Get mux control register address of specified GPIO instance.
253 * @param __GPIOx__ This parameter can be one of the following values:
254 * @arg GPIO0
255 * @arg GPIO1
256 * @retval none
257 */
258 #define LL_GPIO_GET_REG_MUX_CTRL_8_15( __GPIOx__) \
259 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL8_15) : &(MCU_SUB->DPAD_MUX_CTL24_31))
260
261 /** @defgroup GPIO_LL_PM_RESISTOR Resistor Enable
262 * @{
263 */
264 #define LL_GPIO_RE_N_Pos 0 /**< Resistor Enable bits position */
265 #define LL_GPIO_RE_N_Msk (0x1U << LL_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
266 #define LL_GPIO_RE_N LL_GPIO_RE_N_Msk /**< Resistor Enable bits */
267 /** @} */
268
269 /** @defgroup GPIO_LL_PM_RESISTOR_TYPE Resistor Type
270 * @{
271 */
272 #define LL_GPIO_RTYP_Pos 1 /**< Resistor Type bits position */
273 #define LL_GPIO_RTYP_Msk (0x1U << LL_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
274 #define LL_GPIO_RTYP LL_GPIO_RTYP_Msk /**< Resistor Type bits */
275 /** @} */
276
277 /** @} */
278
279 /** @} */
280
281 /* Exported functions --------------------------------------------------------*/
282 /** @defgroup GPIO_LL_DRIVER_FUNCTIONS Functions
283 * @{
284 */
285
286 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
287 * @{
288 */
289
290 /**
291 * @brief Set several pins to input/output mode on dedicated port.
292 *
293 * Register|BitsName
294 * --------|--------
295 * OUTENSET | OUTENSET
296 * OUTENCLR | OUTENCLR
297 *
298 * @param GPIOx GPIO Port
299 * @param pin_mask This parameter can be a combination of the following values:
300 * @arg @ref LL_GPIO_PIN_0
301 * @arg @ref LL_GPIO_PIN_1
302 * @arg @ref LL_GPIO_PIN_2
303 * @arg @ref LL_GPIO_PIN_3
304 * @arg @ref LL_GPIO_PIN_4
305 * @arg @ref LL_GPIO_PIN_5
306 * @arg @ref LL_GPIO_PIN_6
307 * @arg @ref LL_GPIO_PIN_7
308 * @arg @ref LL_GPIO_PIN_8
309 * @arg @ref LL_GPIO_PIN_9
310 * @arg @ref LL_GPIO_PIN_10
311 * @arg @ref LL_GPIO_PIN_11
312 * @arg @ref LL_GPIO_PIN_12
313 * @arg @ref LL_GPIO_PIN_13
314 * @arg @ref LL_GPIO_PIN_14
315 * @arg @ref LL_GPIO_PIN_15
316 * @arg @ref LL_GPIO_PIN_ALL
317 * @param mode This parameter can be one of the following values:
318 * @arg @ref LL_GPIO_MODE_INPUT
319 * @arg @ref LL_GPIO_MODE_OUTPUT
320 * @retval None
321 */
322 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
323 {
324 if (mode == LL_GPIO_MODE_OUTPUT)
325 {
326 WRITE_REG(GPIOx->OUTENSET, pin_mask);
327 }
328 else if(mode == LL_GPIO_MODE_INPUT)
329 {
330 WRITE_REG(GPIOx->OUTENCLR, pin_mask);
331 }
332 }
333
334 /**
335 * @brief Return gpio mode for a dedicated pin on dedicated port.
336 * @note I/O mode can be Input mode, General purpose output.
337 * @note Warning: only one pin can be passed as parameter.
338 *
339 * Register|BitsName
340 * --------|--------
341 * OUTENSET | OUTENSET
342 *
343 * @param GPIOx GPIO Port
344 * @param pin This parameter can be one of the following values:
345 * @arg @ref LL_GPIO_PIN_0
346 * @arg @ref LL_GPIO_PIN_1
347 * @arg @ref LL_GPIO_PIN_2
348 * @arg @ref LL_GPIO_PIN_3
349 * @arg @ref LL_GPIO_PIN_4
350 * @arg @ref LL_GPIO_PIN_5
351 * @arg @ref LL_GPIO_PIN_6
352 * @arg @ref LL_GPIO_PIN_7
353 * @arg @ref LL_GPIO_PIN_8
354 * @arg @ref LL_GPIO_PIN_9
355 * @arg @ref LL_GPIO_PIN_10
356 * @arg @ref LL_GPIO_PIN_11
357 * @arg @ref LL_GPIO_PIN_12
358 * @arg @ref LL_GPIO_PIN_13
359 * @arg @ref LL_GPIO_PIN_14
360 * @arg @ref LL_GPIO_PIN_15
361 * @retval Returned value can be one of the following values:
362 * @arg @ref LL_GPIO_MODE_INPUT
363 * @arg @ref LL_GPIO_MODE_OUTPUT
364 */
365 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
366 {
367 return (uint32_t)(READ_BITS(GPIOx->OUTENSET, pin) != RESET);
368 }
369
370 /**
371 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
372 *
373 * Register|BitsName
374 * --------|--------
375 * DPAD_RE_N_BUS | RE_N
376 * DPAD_RTYP_BUS | RTYP
377 *
378 * @param GPIOx GPIO Port
379 * @param pin_mask This parameter can be a combination of the following values:
380 * @arg @ref LL_GPIO_PIN_0
381 * @arg @ref LL_GPIO_PIN_1
382 * @arg @ref LL_GPIO_PIN_2
383 * @arg @ref LL_GPIO_PIN_3
384 * @arg @ref LL_GPIO_PIN_4
385 * @arg @ref LL_GPIO_PIN_5
386 * @arg @ref LL_GPIO_PIN_6
387 * @arg @ref LL_GPIO_PIN_7
388 * @arg @ref LL_GPIO_PIN_8
389 * @arg @ref LL_GPIO_PIN_9
390 * @arg @ref LL_GPIO_PIN_10
391 * @arg @ref LL_GPIO_PIN_11
392 * @arg @ref LL_GPIO_PIN_12
393 * @arg @ref LL_GPIO_PIN_13
394 * @arg @ref LL_GPIO_PIN_14
395 * @arg @ref LL_GPIO_PIN_15
396 * @param pull This parameter can be one of the following values:
397 * @arg @ref LL_GPIO_PULL_NO
398 * @arg @ref LL_GPIO_PULL_UP
399 * @arg @ref LL_GPIO_PULL_DOWN
400 * @retval None
401 */
402 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
403 {
404 /* Get pin mask in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
405 pin_mask <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
406 MODIFY_REG(MCU_SUB->DPAD_RTYP_BUS, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
407 MODIFY_REG(MCU_SUB->DPAD_RE_N_BUS, pin_mask, (pull == LL_GPIO_PULL_NO) ? pin_mask : 0x0000U);
408 }
409
410 /**
411 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
412 * @note Warning: only one pin can be passed as parameter.
413 *
414 * Register|BitsName
415 * --------|--------
416 * DPAD_RE_N_BUS | RE_N
417 * DPAD_RTYP_BUS | RTYP
418 *
419 * @param GPIOx GPIO Port
420 * @param pin This parameter can be one of the following values:
421 * @arg @ref LL_GPIO_PIN_0
422 * @arg @ref LL_GPIO_PIN_1
423 * @arg @ref LL_GPIO_PIN_2
424 * @arg @ref LL_GPIO_PIN_3
425 * @arg @ref LL_GPIO_PIN_4
426 * @arg @ref LL_GPIO_PIN_5
427 * @arg @ref LL_GPIO_PIN_6
428 * @arg @ref LL_GPIO_PIN_7
429 * @arg @ref LL_GPIO_PIN_8
430 * @arg @ref LL_GPIO_PIN_9
431 * @arg @ref LL_GPIO_PIN_10
432 * @arg @ref LL_GPIO_PIN_11
433 * @arg @ref LL_GPIO_PIN_12
434 * @arg @ref LL_GPIO_PIN_13
435 * @arg @ref LL_GPIO_PIN_14
436 * @arg @ref LL_GPIO_PIN_15
437 * @retval Returned value can be one of the following values:
438 * @arg @ref LL_GPIO_PULL_NO
439 * @arg @ref LL_GPIO_PULL_UP
440 * @arg @ref LL_GPIO_PULL_DOWN
441 */
442 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
443 {
444 /* Get pin position in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
445 pin <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
446 return ((READ_BITS(MCU_SUB->DPAD_RE_N_BUS, pin) != RESET) ? LL_GPIO_PULL_NO :
447 ((READ_BITS(MCU_SUB->DPAD_RTYP_BUS, pin) != RESET) ? LL_GPIO_PULL_UP : LL_GPIO_PULL_DOWN));
448 }
449
450 /**
451 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
452 * @note Possible values are from AF0 to AF15 depending on target.
453 * @note Warning: only one pin can be passed as parameter.
454 *
455 * Register|BitsName
456 * --------|--------
457 * DPAD_MUX_CTRL0_7 | CTRL0_7
458 * DPAD_MUX_CTRL16_23 | CTRL16_23
459 *
460 * @param GPIOx GPIO Port
461 * @param pin This parameter can be one of the following values:
462 * @arg @ref LL_GPIO_PIN_0
463 * @arg @ref LL_GPIO_PIN_1
464 * @arg @ref LL_GPIO_PIN_2
465 * @arg @ref LL_GPIO_PIN_3
466 * @arg @ref LL_GPIO_PIN_4
467 * @arg @ref LL_GPIO_PIN_5
468 * @arg @ref LL_GPIO_PIN_6
469 * @arg @ref LL_GPIO_PIN_7
470 * @param mux This parameter can be one of the following values:
471 * @arg @ref LL_GPIO_MUX_0
472 * @arg @ref LL_GPIO_MUX_1
473 * @arg @ref LL_GPIO_MUX_2
474 * @arg @ref LL_GPIO_MUX_3
475 * @arg @ref LL_GPIO_MUX_4
476 * @arg @ref LL_GPIO_MUX_5
477 * @arg @ref LL_GPIO_MUX_6
478 * @arg @ref LL_GPIO_MUX_7
479 * @arg @ref LL_GPIO_MUX_8
480 * @retval None
481 */
482 __STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
483 {
484 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
485 uint32_t pos = POSITION_VAL(pin) << 2;
486 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
487 }
488
489 /**
490 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
491 *
492 * Register|BitsName
493 * --------|--------
494 * DPAD_MUX_CTRL0_7 | CTRL0_7
495 * DPAD_MUX_CTRL16_23 | CTRL16_23
496 *
497 * @param GPIOx GPIO Port
498 * @param pin This parameter can be one of the following values:
499 * @arg @ref LL_GPIO_PIN_0
500 * @arg @ref LL_GPIO_PIN_1
501 * @arg @ref LL_GPIO_PIN_2
502 * @arg @ref LL_GPIO_PIN_3
503 * @arg @ref LL_GPIO_PIN_4
504 * @arg @ref LL_GPIO_PIN_5
505 * @arg @ref LL_GPIO_PIN_6
506 * @arg @ref LL_GPIO_PIN_7
507 * @retval Returned value can be one of the following values:
508 * @arg @ref LL_GPIO_MUX_0
509 * @arg @ref LL_GPIO_MUX_1
510 * @arg @ref LL_GPIO_MUX_2
511 * @arg @ref LL_GPIO_MUX_3
512 * @arg @ref LL_GPIO_MUX_4
513 * @arg @ref LL_GPIO_MUX_5
514 * @arg @ref LL_GPIO_MUX_6
515 * @arg @ref LL_GPIO_MUX_7
516 * @arg @ref LL_GPIO_MUX_8
517 */
518 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
519 {
520 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
521 uint32_t pos = POSITION_VAL(pin) << 2;
522 return (READ_BITS(*pReg, 0xF << pos) >> pos);
523 }
524
525 /**
526 * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
527 * @note Possible values are from AF0 to AF15 depending on target.
528 * @note Warning: only one pin can be passed as parameter.
529 *
530 * Register|BitsName
531 * --------|--------
532 * DPAD_MUX_CTRL8_15 | CTRL8_15
533 * DPAD_MUX_CTRL24_31 | CTRL24_31
534 *
535 * @param GPIOx GPIO Port
536 * @param pin This parameter can be one of the following values:
537 * @arg @ref LL_GPIO_PIN_8
538 * @arg @ref LL_GPIO_PIN_9
539 * @arg @ref LL_GPIO_PIN_10
540 * @arg @ref LL_GPIO_PIN_11
541 * @arg @ref LL_GPIO_PIN_12
542 * @arg @ref LL_GPIO_PIN_13
543 * @arg @ref LL_GPIO_PIN_14
544 * @arg @ref LL_GPIO_PIN_15
545 * @param mux This parameter can be one of the following values:
546 * @arg @ref LL_GPIO_MUX_0
547 * @arg @ref LL_GPIO_MUX_1
548 * @arg @ref LL_GPIO_MUX_2
549 * @arg @ref LL_GPIO_MUX_3
550 * @arg @ref LL_GPIO_MUX_4
551 * @arg @ref LL_GPIO_MUX_5
552 * @arg @ref LL_GPIO_MUX_6
553 * @arg @ref LL_GPIO_MUX_7
554 * @arg @ref LL_GPIO_MUX_8
555 * @retval None
556 */
557 __STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
558 {
559 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
560 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
561 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
562 }
563
564 /**
565 * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
566 * @note Possible values are from AF0 to AF15 depending on target.
567 *
568 * Register|BitsName
569 * --------|--------
570 * DPAD_MUX_CTRL8_15 | CTRL8_15
571 * DPAD_MUX_CTRL24_31 | CTRL24_31
572 *
573 * @param GPIOx GPIO Port
574 * @param pin This parameter can be one of the following values:
575 * @arg @ref LL_GPIO_PIN_8
576 * @arg @ref LL_GPIO_PIN_9
577 * @arg @ref LL_GPIO_PIN_10
578 * @arg @ref LL_GPIO_PIN_11
579 * @arg @ref LL_GPIO_PIN_12
580 * @arg @ref LL_GPIO_PIN_13
581 * @arg @ref LL_GPIO_PIN_14
582 * @arg @ref LL_GPIO_PIN_15
583 * @retval Returned value can be one of the following values:
584 * @arg @ref LL_GPIO_MUX_0
585 * @arg @ref LL_GPIO_MUX_1
586 * @arg @ref LL_GPIO_MUX_2
587 * @arg @ref LL_GPIO_MUX_3
588 * @arg @ref LL_GPIO_MUX_4
589 * @arg @ref LL_GPIO_MUX_5
590 * @arg @ref LL_GPIO_MUX_6
591 * @arg @ref LL_GPIO_MUX_7
592 * @arg @ref LL_GPIO_MUX_8
593 */
594 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
595 {
596 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
597 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
598 return (READ_BITS(*pReg, 0xF << pos) >> pos);
599 }
600
601 /** @} */
602
603 /** @defgroup GPIO_LL_EF_Data_Access Data Access
604 * @{
605 */
606
607 /**
608 * @brief Return full input data register value for a dedicated port.
609 *
610 * Register|BitsName
611 * --------|--------
612 * DATA | DATA
613 *
614 * @param GPIOx GPIO Port
615 * @retval Input data register value of port
616 */
617 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
618 {
619 return (uint32_t)(READ_REG(GPIOx->DATA));
620 }
621
622 /**
623 * @brief Return if input data level for several pins of dedicated port is high or low.
624 *
625 * Register|BitsName
626 * --------|--------
627 * DATA | DATA
628 *
629 * @param GPIOx GPIO Port
630 * @param pin_mask This parameter can be a combination of the following values:
631 * @arg @ref LL_GPIO_PIN_0
632 * @arg @ref LL_GPIO_PIN_1
633 * @arg @ref LL_GPIO_PIN_2
634 * @arg @ref LL_GPIO_PIN_3
635 * @arg @ref LL_GPIO_PIN_4
636 * @arg @ref LL_GPIO_PIN_5
637 * @arg @ref LL_GPIO_PIN_6
638 * @arg @ref LL_GPIO_PIN_7
639 * @arg @ref LL_GPIO_PIN_8
640 * @arg @ref LL_GPIO_PIN_9
641 * @arg @ref LL_GPIO_PIN_10
642 * @arg @ref LL_GPIO_PIN_11
643 * @arg @ref LL_GPIO_PIN_12
644 * @arg @ref LL_GPIO_PIN_13
645 * @arg @ref LL_GPIO_PIN_14
646 * @arg @ref LL_GPIO_PIN_15
647 * @arg @ref LL_GPIO_PIN_ALL
648 * @retval State of bit (1 or 0).
649 */
650 __STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
651 {
652 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
653 }
654
655 /**
656 * @brief Write output data register for the port.
657 *
658 * Register|BitsName
659 * --------|--------
660 * DATAOUT | DATAOUT
661 *
662 * @param GPIOx GPIO Port
663 * @param port_value Level value for each pin of the port
664 * @retval None
665 */
666 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
667 {
668 WRITE_REG(GPIOx->DATAOUT, port_value);
669 }
670
671 /**
672 * @brief Return full output data register value for a dedicated port.
673 *
674 * Register|BitsName
675 * --------|--------
676 * DATAOUT | DATAOUT
677 *
678 * @param GPIOx GPIO Port
679 * @retval Output data register value of port
680 */
681 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
682 {
683 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
684 }
685
686 /**
687 * @brief Return if input data level for several pins of dedicated port is high or low.
688 *
689 * Register|BitsName
690 * --------|--------
691 * DATAOUT | DATAOUT
692 *
693 * @param GPIOx GPIO Port
694 * @param pin_mask This parameter can be a combination of the following values:
695 * @arg @ref LL_GPIO_PIN_0
696 * @arg @ref LL_GPIO_PIN_1
697 * @arg @ref LL_GPIO_PIN_2
698 * @arg @ref LL_GPIO_PIN_3
699 * @arg @ref LL_GPIO_PIN_4
700 * @arg @ref LL_GPIO_PIN_5
701 * @arg @ref LL_GPIO_PIN_6
702 * @arg @ref LL_GPIO_PIN_7
703 * @arg @ref LL_GPIO_PIN_8
704 * @arg @ref LL_GPIO_PIN_9
705 * @arg @ref LL_GPIO_PIN_10
706 * @arg @ref LL_GPIO_PIN_11
707 * @arg @ref LL_GPIO_PIN_12
708 * @arg @ref LL_GPIO_PIN_13
709 * @arg @ref LL_GPIO_PIN_14
710 * @arg @ref LL_GPIO_PIN_15
711 * @arg @ref LL_GPIO_PIN_ALL
712 * @retval State of bit (1 or 0).
713 */
714 __STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
715 {
716 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
717 }
718
719 /**
720 * @brief Set several pins to high level on dedicated gpio port.
721 *
722 * Register|BitsName
723 * --------|--------
724 * DATAOUT | DATAOUT
725 *
726 * @param GPIOx GPIO Port
727 * @param pin_mask This parameter can be a combination of the following values:
728 * @arg @ref LL_GPIO_PIN_0
729 * @arg @ref LL_GPIO_PIN_1
730 * @arg @ref LL_GPIO_PIN_2
731 * @arg @ref LL_GPIO_PIN_3
732 * @arg @ref LL_GPIO_PIN_4
733 * @arg @ref LL_GPIO_PIN_5
734 * @arg @ref LL_GPIO_PIN_6
735 * @arg @ref LL_GPIO_PIN_7
736 * @arg @ref LL_GPIO_PIN_8
737 * @arg @ref LL_GPIO_PIN_9
738 * @arg @ref LL_GPIO_PIN_10
739 * @arg @ref LL_GPIO_PIN_11
740 * @arg @ref LL_GPIO_PIN_12
741 * @arg @ref LL_GPIO_PIN_13
742 * @arg @ref LL_GPIO_PIN_14
743 * @arg @ref LL_GPIO_PIN_15
744 * @arg @ref LL_GPIO_PIN_ALL
745 * @retval None
746 */
747 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
748 {
749 #ifdef USE_GPIO_MASK_REGISTER
750 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
751 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
752 pin_mask & GPIO_MASKHIGHBYTE_DATA);
753 #else
754 SET_BITS(GPIOx->DATAOUT, pin_mask);
755 #endif
756 }
757
758 /**
759 * @brief Set several pins to low level on dedicated gpio port.
760 *
761 * Register|BitsName
762 * --------|--------
763 * DATAOUT | DATAOUT
764 *
765 * @param GPIOx GPIO Port
766 * @param pin_mask This parameter can be a combination of the following values:
767 * @arg @ref LL_GPIO_PIN_0
768 * @arg @ref LL_GPIO_PIN_1
769 * @arg @ref LL_GPIO_PIN_2
770 * @arg @ref LL_GPIO_PIN_3
771 * @arg @ref LL_GPIO_PIN_4
772 * @arg @ref LL_GPIO_PIN_5
773 * @arg @ref LL_GPIO_PIN_6
774 * @arg @ref LL_GPIO_PIN_7
775 * @arg @ref LL_GPIO_PIN_8
776 * @arg @ref LL_GPIO_PIN_9
777 * @arg @ref LL_GPIO_PIN_10
778 * @arg @ref LL_GPIO_PIN_11
779 * @arg @ref LL_GPIO_PIN_12
780 * @arg @ref LL_GPIO_PIN_13
781 * @arg @ref LL_GPIO_PIN_14
782 * @arg @ref LL_GPIO_PIN_15
783 * @arg @ref LL_GPIO_PIN_ALL
784 * @retval None
785 */
786 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
787 {
788 #ifdef USE_GPIO_MASK_REGISTER
789 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
790 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
791 #else
792 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
793 #endif
794 }
795
796 /**
797 * @brief Toggle data value for several pin of dedicated port.
798 *
799 * Register|BitsName
800 * --------|--------
801 * DATAOUT | DATAOUT
802 *
803 * @param GPIOx GPIO Port
804 * @param pin_mask This parameter can be a combination of the following values:
805 * @arg @ref LL_GPIO_PIN_0
806 * @arg @ref LL_GPIO_PIN_1
807 * @arg @ref LL_GPIO_PIN_2
808 * @arg @ref LL_GPIO_PIN_3
809 * @arg @ref LL_GPIO_PIN_4
810 * @arg @ref LL_GPIO_PIN_5
811 * @arg @ref LL_GPIO_PIN_6
812 * @arg @ref LL_GPIO_PIN_7
813 * @arg @ref LL_GPIO_PIN_8
814 * @arg @ref LL_GPIO_PIN_9
815 * @arg @ref LL_GPIO_PIN_10
816 * @arg @ref LL_GPIO_PIN_11
817 * @arg @ref LL_GPIO_PIN_12
818 * @arg @ref LL_GPIO_PIN_13
819 * @arg @ref LL_GPIO_PIN_14
820 * @arg @ref LL_GPIO_PIN_15
821 * @arg @ref LL_GPIO_PIN_ALL
822 * @retval None
823 */
824 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
825 {
826 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
827 }
828
829 /** @} */
830
831 /** @defgroup GPIO_LL_EF_IT_Management IT_Management
832 * @{
833 */
834
835 /**
836 * @brief Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
837 * @note
838 *
839 * Register|BitsName
840 * --------|--------
841 * INTPOLCLR | INTPOLCLR
842 * INTTYPESET | INTTYPESET
843 *
844 * @param GPIOx GPIO instance.
845 * @param pin_mask This parameter can be a combination of the following values:
846 * @arg @ref LL_GPIO_PIN_0
847 * @arg @ref LL_GPIO_PIN_1
848 * @arg @ref LL_GPIO_PIN_2
849 * @arg @ref LL_GPIO_PIN_3
850 * @arg @ref LL_GPIO_PIN_4
851 * @arg @ref LL_GPIO_PIN_5
852 * @arg @ref LL_GPIO_PIN_6
853 * @arg @ref LL_GPIO_PIN_7
854 * @arg @ref LL_GPIO_PIN_8
855 * @arg @ref LL_GPIO_PIN_9
856 * @arg @ref LL_GPIO_PIN_10
857 * @arg @ref LL_GPIO_PIN_11
858 * @arg @ref LL_GPIO_PIN_12
859 * @arg @ref LL_GPIO_PIN_13
860 * @arg @ref LL_GPIO_PIN_14
861 * @arg @ref LL_GPIO_PIN_15
862 * @arg @ref LL_GPIO_PIN_ALL
863 * @retval None
864 */
865 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
866 {
867 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
868 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
869 }
870
871 /**
872 * @brief Check if falling edge trigger is enabled for pins in the range of 0 to 15.
873 * @note
874 *
875 * Register|BitsName
876 * --------|--------
877 * INTPOLCLR | INTPOLCLR
878 * INTTYPESET | INTTYPESET
879 *
880 * @param GPIOx GPIO instance.
881 * @param pin_mask This parameter can be a combination of the following values:
882 * @arg @ref LL_GPIO_PIN_0
883 * @arg @ref LL_GPIO_PIN_1
884 * @arg @ref LL_GPIO_PIN_2
885 * @arg @ref LL_GPIO_PIN_3
886 * @arg @ref LL_GPIO_PIN_4
887 * @arg @ref LL_GPIO_PIN_5
888 * @arg @ref LL_GPIO_PIN_6
889 * @arg @ref LL_GPIO_PIN_7
890 * @arg @ref LL_GPIO_PIN_8
891 * @arg @ref LL_GPIO_PIN_9
892 * @arg @ref LL_GPIO_PIN_10
893 * @arg @ref LL_GPIO_PIN_11
894 * @arg @ref LL_GPIO_PIN_12
895 * @arg @ref LL_GPIO_PIN_13
896 * @arg @ref LL_GPIO_PIN_14
897 * @arg @ref LL_GPIO_PIN_15
898 * @arg @ref LL_GPIO_PIN_ALL
899 * @retval State of bit (1 or 0).
900 */
901 __STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
902 {
903 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
904 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
905 }
906
907 /**
908 * @brief Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
909 * @note
910 *
911 * Register|BitsName
912 * --------|--------
913 * INTPOLSET | INTPOLSET
914 * INTTYPESET | INTTYPESET
915 *
916 * @param GPIOx GPIO instance.
917 * @param pin_mask This parameter can be a combination of the following values:
918 * @arg @ref LL_GPIO_PIN_0
919 * @arg @ref LL_GPIO_PIN_1
920 * @arg @ref LL_GPIO_PIN_2
921 * @arg @ref LL_GPIO_PIN_3
922 * @arg @ref LL_GPIO_PIN_4
923 * @arg @ref LL_GPIO_PIN_5
924 * @arg @ref LL_GPIO_PIN_6
925 * @arg @ref LL_GPIO_PIN_7
926 * @arg @ref LL_GPIO_PIN_8
927 * @arg @ref LL_GPIO_PIN_9
928 * @arg @ref LL_GPIO_PIN_10
929 * @arg @ref LL_GPIO_PIN_11
930 * @arg @ref LL_GPIO_PIN_12
931 * @arg @ref LL_GPIO_PIN_13
932 * @arg @ref LL_GPIO_PIN_14
933 * @arg @ref LL_GPIO_PIN_15
934 * @arg @ref LL_GPIO_PIN_ALL
935 * @retval None
936 */
937 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
938 {
939 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
940 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
941 }
942
943 /**
944 * @brief Check if rising edge trigger is enabled for pins in the range of 0 to 15.
945 * @note
946 *
947 * Register|BitsName
948 * --------|--------
949 * INTPOLSET | INTPOLSET
950 * INTTYPESET | INTTYPESET
951 *
952 * @param GPIOx GPIO instance.
953 * @param pin_mask This parameter can be a combination of the following values:
954 * @arg @ref LL_GPIO_PIN_0
955 * @arg @ref LL_GPIO_PIN_1
956 * @arg @ref LL_GPIO_PIN_2
957 * @arg @ref LL_GPIO_PIN_3
958 * @arg @ref LL_GPIO_PIN_4
959 * @arg @ref LL_GPIO_PIN_5
960 * @arg @ref LL_GPIO_PIN_6
961 * @arg @ref LL_GPIO_PIN_7
962 * @arg @ref LL_GPIO_PIN_8
963 * @arg @ref LL_GPIO_PIN_9
964 * @arg @ref LL_GPIO_PIN_10
965 * @arg @ref LL_GPIO_PIN_11
966 * @arg @ref LL_GPIO_PIN_12
967 * @arg @ref LL_GPIO_PIN_13
968 * @arg @ref LL_GPIO_PIN_14
969 * @arg @ref LL_GPIO_PIN_15
970 * @arg @ref LL_GPIO_PIN_ALL
971 * @note Please check each device line mapping for GPIO Line availability
972 * @retval State of bit (1 or 0).
973 */
974 __STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
975 {
976 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
977 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
978 }
979
980 /**
981 * @brief Enable GPIO High Level Trigger for pins in the range of 0 to 15.
982 * @note
983 *
984 * Register|BitsName
985 * --------|--------
986 * INTPOLSET | INTPOLSET
987 * INTTYPECLR | INTTYPECLR
988 *
989 * @param GPIOx GPIO instance.
990 * @param pin_mask This parameter can be a combination of the following values:
991 * @arg @ref LL_GPIO_PIN_0
992 * @arg @ref LL_GPIO_PIN_1
993 * @arg @ref LL_GPIO_PIN_2
994 * @arg @ref LL_GPIO_PIN_3
995 * @arg @ref LL_GPIO_PIN_4
996 * @arg @ref LL_GPIO_PIN_5
997 * @arg @ref LL_GPIO_PIN_6
998 * @arg @ref LL_GPIO_PIN_7
999 * @arg @ref LL_GPIO_PIN_8
1000 * @arg @ref LL_GPIO_PIN_9
1001 * @arg @ref LL_GPIO_PIN_10
1002 * @arg @ref LL_GPIO_PIN_11
1003 * @arg @ref LL_GPIO_PIN_12
1004 * @arg @ref LL_GPIO_PIN_13
1005 * @arg @ref LL_GPIO_PIN_14
1006 * @arg @ref LL_GPIO_PIN_15
1007 * @arg @ref LL_GPIO_PIN_ALL
1008 * @retval None
1009 */
1010 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1011 {
1012 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1013 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1014 }
1015
1016 /**
1017 * @brief Check if high level trigger is enabled for pins in the range of 0 to 15.
1018 * @note
1019 *
1020 * Register|BitsName
1021 * --------|--------
1022 * INTPOLSET | INTPOLSET
1023 * INTTYPECLR | INTTYPECLR
1024 *
1025 * @param GPIOx GPIO instance.
1026 * @param pin_mask This parameter can be a combination of the following values:
1027 * @arg @ref LL_GPIO_PIN_0
1028 * @arg @ref LL_GPIO_PIN_1
1029 * @arg @ref LL_GPIO_PIN_2
1030 * @arg @ref LL_GPIO_PIN_3
1031 * @arg @ref LL_GPIO_PIN_4
1032 * @arg @ref LL_GPIO_PIN_5
1033 * @arg @ref LL_GPIO_PIN_6
1034 * @arg @ref LL_GPIO_PIN_7
1035 * @arg @ref LL_GPIO_PIN_8
1036 * @arg @ref LL_GPIO_PIN_9
1037 * @arg @ref LL_GPIO_PIN_10
1038 * @arg @ref LL_GPIO_PIN_11
1039 * @arg @ref LL_GPIO_PIN_12
1040 * @arg @ref LL_GPIO_PIN_13
1041 * @arg @ref LL_GPIO_PIN_14
1042 * @arg @ref LL_GPIO_PIN_15
1043 * @arg @ref LL_GPIO_PIN_ALL
1044 * @retval State of bit (1 or 0).
1045 */
1046 __STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1047 {
1048 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
1049 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1050 }
1051
1052 /**
1053 * @brief Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
1054 * @note
1055 *
1056 * Register|BitsName
1057 * --------|--------
1058 * INTPOLCLR | INTPOLCLR
1059 * INTTYPECLR | INTTYPECLR
1060 *
1061 * @param GPIOx GPIO instance.
1062 * @param pin_mask This parameter can be a combination of the following values:
1063 * @arg @ref LL_GPIO_PIN_0
1064 * @arg @ref LL_GPIO_PIN_1
1065 * @arg @ref LL_GPIO_PIN_2
1066 * @arg @ref LL_GPIO_PIN_3
1067 * @arg @ref LL_GPIO_PIN_4
1068 * @arg @ref LL_GPIO_PIN_5
1069 * @arg @ref LL_GPIO_PIN_6
1070 * @arg @ref LL_GPIO_PIN_7
1071 * @arg @ref LL_GPIO_PIN_8
1072 * @arg @ref LL_GPIO_PIN_9
1073 * @arg @ref LL_GPIO_PIN_10
1074 * @arg @ref LL_GPIO_PIN_11
1075 * @arg @ref LL_GPIO_PIN_12
1076 * @arg @ref LL_GPIO_PIN_13
1077 * @arg @ref LL_GPIO_PIN_14
1078 * @arg @ref LL_GPIO_PIN_15
1079 * @arg @ref LL_GPIO_PIN_ALL
1080 * @retval None
1081 */
1082 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1083 {
1084 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1085 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1086 }
1087
1088 /**
1089 * @brief Check if low level trigger is enabled for pins in the range of 0 to 15
1090 * @note
1091 *
1092 * Register|BitsName
1093 * --------|--------
1094 * INTPOLCLR | INTPOLCLR
1095 * INTTYPECLR | INTTYPECLR
1096 *
1097 * @param GPIOx GPIO instance.
1098 * @param pin_mask This parameter can be a combination of the following values:
1099 * @arg @ref LL_GPIO_PIN_0
1100 * @arg @ref LL_GPIO_PIN_1
1101 * @arg @ref LL_GPIO_PIN_2
1102 * @arg @ref LL_GPIO_PIN_3
1103 * @arg @ref LL_GPIO_PIN_4
1104 * @arg @ref LL_GPIO_PIN_5
1105 * @arg @ref LL_GPIO_PIN_6
1106 * @arg @ref LL_GPIO_PIN_7
1107 * @arg @ref LL_GPIO_PIN_8
1108 * @arg @ref LL_GPIO_PIN_9
1109 * @arg @ref LL_GPIO_PIN_10
1110 * @arg @ref LL_GPIO_PIN_11
1111 * @arg @ref LL_GPIO_PIN_12
1112 * @arg @ref LL_GPIO_PIN_13
1113 * @arg @ref LL_GPIO_PIN_14
1114 * @arg @ref LL_GPIO_PIN_15
1115 * @arg @ref LL_GPIO_PIN_ALL
1116 * @retval State of bit (1 or 0).
1117 */
1118 __STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1119 {
1120 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
1121 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1122 }
1123
1124 /**
1125 * @brief Enable GPIO interrupts for pins in the range of 0 to 15.
1126 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1127 *
1128 * Register|BitsName
1129 * --------|--------
1130 * INTENSET | INTENSET
1131 *
1132 * @param GPIOx GPIO instance.
1133 * @param pin_mask This parameter can be a combination of the following values:
1134 * @arg @ref LL_GPIO_PIN_0
1135 * @arg @ref LL_GPIO_PIN_1
1136 * @arg @ref LL_GPIO_PIN_2
1137 * @arg @ref LL_GPIO_PIN_3
1138 * @arg @ref LL_GPIO_PIN_4
1139 * @arg @ref LL_GPIO_PIN_5
1140 * @arg @ref LL_GPIO_PIN_6
1141 * @arg @ref LL_GPIO_PIN_7
1142 * @arg @ref LL_GPIO_PIN_8
1143 * @arg @ref LL_GPIO_PIN_9
1144 * @arg @ref LL_GPIO_PIN_10
1145 * @arg @ref LL_GPIO_PIN_11
1146 * @arg @ref LL_GPIO_PIN_12
1147 * @arg @ref LL_GPIO_PIN_13
1148 * @arg @ref LL_GPIO_PIN_14
1149 * @arg @ref LL_GPIO_PIN_15
1150 * @arg @ref LL_GPIO_PIN_ALL
1151 * @retval None
1152 */
1153 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1154 {
1155 WRITE_REG(GPIOx->INTENSET, pin_mask);
1156 }
1157
1158 /**
1159 * @brief Disable GPIO interrupts for pins in the range of 0 to 15.
1160 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1161 *
1162 * Register|BitsName
1163 * --------|--------
1164 * INTENCLR | INTENCLR
1165 *
1166 * @param GPIOx GPIO instance.
1167 * @param pin_mask This parameter can be a combination of the following values:
1168 * @arg @ref LL_GPIO_PIN_0
1169 * @arg @ref LL_GPIO_PIN_1
1170 * @arg @ref LL_GPIO_PIN_2
1171 * @arg @ref LL_GPIO_PIN_3
1172 * @arg @ref LL_GPIO_PIN_4
1173 * @arg @ref LL_GPIO_PIN_5
1174 * @arg @ref LL_GPIO_PIN_6
1175 * @arg @ref LL_GPIO_PIN_7
1176 * @arg @ref LL_GPIO_PIN_8
1177 * @arg @ref LL_GPIO_PIN_9
1178 * @arg @ref LL_GPIO_PIN_10
1179 * @arg @ref LL_GPIO_PIN_11
1180 * @arg @ref LL_GPIO_PIN_12
1181 * @arg @ref LL_GPIO_PIN_13
1182 * @arg @ref LL_GPIO_PIN_14
1183 * @arg @ref LL_GPIO_PIN_15
1184 * @arg @ref LL_GPIO_PIN_ALL
1185 * @retval None
1186 */
1187 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1188 {
1189 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1190 }
1191
1192 /**
1193 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1194 *
1195 * Register|BitsName
1196 * --------|--------
1197 * INTENSET | INTENSET
1198 *
1199 * @param GPIOx GPIO instance.
1200 * @param pin_mask This parameter can be a combination of the following values:
1201 * @arg @ref LL_GPIO_PIN_0
1202 * @arg @ref LL_GPIO_PIN_1
1203 * @arg @ref LL_GPIO_PIN_2
1204 * @arg @ref LL_GPIO_PIN_3
1205 * @arg @ref LL_GPIO_PIN_4
1206 * @arg @ref LL_GPIO_PIN_5
1207 * @arg @ref LL_GPIO_PIN_6
1208 * @arg @ref LL_GPIO_PIN_7
1209 * @arg @ref LL_GPIO_PIN_8
1210 * @arg @ref LL_GPIO_PIN_9
1211 * @arg @ref LL_GPIO_PIN_10
1212 * @arg @ref LL_GPIO_PIN_11
1213 * @arg @ref LL_GPIO_PIN_12
1214 * @arg @ref LL_GPIO_PIN_13
1215 * @arg @ref LL_GPIO_PIN_14
1216 * @arg @ref LL_GPIO_PIN_15
1217 * @arg @ref LL_GPIO_PIN_ALL
1218 * @retval State of bit (1 or 0).
1219 */
1220 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1221 {
1222 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1223 }
1224
1225 /** @} */
1226
1227 /** @defgroup GPIO_LL_EF_Flag_Management Flag_Management
1228 * @{
1229 */
1230
1231 /**
1232 * @brief Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15
1233 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1234 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1235 *
1236 * Register|BitsName
1237 * --------|--------
1238 * INTSTATUS | INTSTATUS
1239 *
1240 * @param GPIOx GPIO instance.
1241 * @param pin_mask This parameter can be a combination of the following values:
1242 * @arg @ref LL_GPIO_PIN_0
1243 * @arg @ref LL_GPIO_PIN_1
1244 * @arg @ref LL_GPIO_PIN_2
1245 * @arg @ref LL_GPIO_PIN_3
1246 * @arg @ref LL_GPIO_PIN_4
1247 * @arg @ref LL_GPIO_PIN_5
1248 * @arg @ref LL_GPIO_PIN_6
1249 * @arg @ref LL_GPIO_PIN_7
1250 * @arg @ref LL_GPIO_PIN_8
1251 * @arg @ref LL_GPIO_PIN_9
1252 * @arg @ref LL_GPIO_PIN_10
1253 * @arg @ref LL_GPIO_PIN_11
1254 * @arg @ref LL_GPIO_PIN_12
1255 * @arg @ref LL_GPIO_PIN_13
1256 * @arg @ref LL_GPIO_PIN_14
1257 * @arg @ref LL_GPIO_PIN_15
1258 * @arg @ref LL_GPIO_PIN_ALL
1259 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1260 */
1261 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1262 {
1263 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1264 }
1265
1266 /**
1267 * @brief Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
1268 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1269 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1270 *
1271 * Register|BitsName
1272 * --------|--------
1273 * INTSTATUS | INTSTATUS
1274 *
1275 * @param GPIOx GPIO instance.
1276 * @param pin_mask This parameter can be a combination of the following values:
1277 * @arg @ref LL_GPIO_PIN_0
1278 * @arg @ref LL_GPIO_PIN_1
1279 * @arg @ref LL_GPIO_PIN_2
1280 * @arg @ref LL_GPIO_PIN_3
1281 * @arg @ref LL_GPIO_PIN_4
1282 * @arg @ref LL_GPIO_PIN_5
1283 * @arg @ref LL_GPIO_PIN_6
1284 * @arg @ref LL_GPIO_PIN_7
1285 * @arg @ref LL_GPIO_PIN_8
1286 * @arg @ref LL_GPIO_PIN_9
1287 * @arg @ref LL_GPIO_PIN_10
1288 * @arg @ref LL_GPIO_PIN_11
1289 * @arg @ref LL_GPIO_PIN_12
1290 * @arg @ref LL_GPIO_PIN_13
1291 * @arg @ref LL_GPIO_PIN_14
1292 * @arg @ref LL_GPIO_PIN_15
1293 * @arg @ref LL_GPIO_PIN_ALL
1294 * @retval State of bit (1 or 0).
1295 */
1296 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1297 {
1298 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1299 }
1300
1301 /**
1302 * @brief Clear Interrupt Status flag for pins in the range of 0 to 15.
1303 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1304 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1305 *
1306 * Register|BitsName
1307 * --------|--------
1308 * INTSTATUS | INTSTATUS
1309 *
1310 * @param GPIOx GPIO instance.
1311 * @param pin_mask This parameter can be a combination of the following values:
1312 * @arg @ref LL_GPIO_PIN_0
1313 * @arg @ref LL_GPIO_PIN_1
1314 * @arg @ref LL_GPIO_PIN_2
1315 * @arg @ref LL_GPIO_PIN_3
1316 * @arg @ref LL_GPIO_PIN_4
1317 * @arg @ref LL_GPIO_PIN_5
1318 * @arg @ref LL_GPIO_PIN_6
1319 * @arg @ref LL_GPIO_PIN_7
1320 * @arg @ref LL_GPIO_PIN_8
1321 * @arg @ref LL_GPIO_PIN_9
1322 * @arg @ref LL_GPIO_PIN_10
1323 * @arg @ref LL_GPIO_PIN_11
1324 * @arg @ref LL_GPIO_PIN_12
1325 * @arg @ref LL_GPIO_PIN_13
1326 * @arg @ref LL_GPIO_PIN_14
1327 * @arg @ref LL_GPIO_PIN_15
1328 * @arg @ref LL_GPIO_PIN_ALL
1329 * @retval None
1330 */
1331 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1332 {
1333 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1334 }
1335
1336 /** @} */
1337
1338 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
1339 * @{
1340 */
1341
1342 /**
1343 * @brief De-initialize GPIO registers (Registers restored to their default values).
1344 * @param GPIOx GPIO instance.
1345 * @retval An error_status_t enumeration value:
1346 * - SUCCESS: GPIO registers are de-initialized
1347 * - ERROR: GPIO registers are not de-initialized
1348 */
1349 error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx);
1350
1351 /**
1352 * @brief Initialize GPIO registers according to the specified
1353 * parameters in p_gpio_init.
1354 * @param GPIOx GPIO instance.
1355 * @param p_gpio_init Pointer to a ll_gpio_init_t structure that contains the configuration
1356 * information for the specified GPIO peripheral.
1357 * @retval An error_status_t enumeration value:
1358 * - SUCCESS: GPIO registers are initialized according to p_gpio_init content
1359 * - ERROR: Problem occurred during GPIO Registers initialization
1360 */
1361 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1362
1363 /**
1364 * @brief Set each field of a @ref ll_gpio_init_t type structure to default value.
1365 * @param p_gpio_init Pointer to a @ref ll_gpio_init_t structure
1366 * whose fields will be set to default values.
1367 * @retval None
1368 */
1369 void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init);
1370
1371 /** @} */
1372
1373 /** @} */
1374
1375 #endif /* defined (GPIO0) || defined (GPIO1) */
1376
1377 #ifdef __cplusplus
1378 }
1379 #endif
1380
1381 #endif /* __GR55xx_LL_GPIO_H__ */
1382
1383 /** @} */
1384
1385 /** @} */
1386
1387 /** @} */
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:617
_ll_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_gpio.h:78
ll_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:518
ll_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if low level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1118
LL_GPIO_GET_RESISTOR_POS
#define LL_GPIO_GET_RESISTOR_POS(__GPIOx__)
Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
Definition: gr55xx_ll_gpio.h:241
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr55xx_ll_gpio.h:149
ll_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:714
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1010
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_gpio.h:1220
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr55xx_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
ll_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if rising edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:974
ll_gpio_set_mux_pin_8_15
__STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:557
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr55xx_ll_gpio.h:150
_ll_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_gpio.h:91
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_gpio.h:97
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:681
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:747
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:937
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1296
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1153
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:365
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:442
LL_GPIO_GET_REG_MUX_CTRL_0_7
#define LL_GPIO_GET_REG_MUX_CTRL_0_7(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:249
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:786
ll_gpio_deinit
error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr55xx_ll_gpio.h:151
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr55xx_ll_gpio.h:824
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr55xx_ll_gpio.h:666
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr55xx_ll_gpio.h:141
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1082
_ll_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_gpio.h:81
ll_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:482
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_gpio.h:142
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr55xx_ll_gpio.h:322
ll_gpio_get_mux_pin_8_15
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:594
ll_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:650
ll_gpio_struct_init
void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init)
Set each field of a ll_gpio_init_t type structure to default value.
_ll_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_gpio.h:86
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1261
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:865
ll_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if high level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1046
LL_GPIO_GET_REG_MUX_CTRL_8_15
#define LL_GPIO_GET_REG_MUX_CTRL_8_15(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:258
ll_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if falling edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:901
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1187
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:402
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1331