gr55xx_ll_pwm.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef __GR55XX_LL_PWM_H__
52 #define __GR55XX_LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr55xx.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /** @defgroup PWM_LL_STRUCTURES Structures
63 * @{
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
68 * @{
69 */
70
71 /**
72 * @brief LL PWM Output Channel init Structure definition.
73 */
74 typedef struct _ll_pwm_channel_init_t
75 {
76 uint8_t duty; /**< Specifies the duty in PWM output mode.
77 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.
78
79 This feature can be modified afterwards using unitary function ll_pwm_set_compare_xn()
80 where X can be (A, B, C) and n can be (0, 1).*/
81
82 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
83 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
84
85 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
86 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
87
88 } ll_pwm_channel_init_t;
89
90 /**
91 * @brief LL PWM init Structure definition.
92 */
93 typedef struct _ll_pwm_init_t
94 {
95 uint32_t mode; /**< Specifies the PWM output mode.
96 This parameter can be a value of @ref PWM_LL_EC_MODE.
97
98 This feature can be modified afterwards using unitary function @ref ll_pwm_set_mode().*/
99
100 uint32_t align; /**< Specifies the PWM alignment pulses.
101 This parameter can be a value of @ref PWM_LL_EC_ALIGN.*/
102
103 uint32_t prescaler; /**< Specifies the prescaler value which will be used configure PWM output frequency.
104 This parameter must be a number ranges between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
105 This parameter should be larger than 128.
106
107 This feature can be modified afterwards using unitary function @ref ll_pwm_set_prescaler().*/
108
109 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
110 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
111 This parameter is recommended to be larger than 128*prescaler to guarantee an ideal breath effect.
112
113 This feature can be modified afterwards using unitary function @ref ll_pwm_set_breath_prescaler().*/
114
115 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
116 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFF.
117
118 This feature can be modified afterwards using unitary function @ref ll_pwm_set_hold_prescaler().*/
119
120 ll_pwm_channel_init_t channel_a; /**< Specifies the configuration of channelA.
121 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
122
123 ll_pwm_channel_init_t channel_b; /**< Specifies the configuration of channelB.
124 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
125
126 ll_pwm_channel_init_t channel_c; /**< Specifies the configuration of channelC.
127 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
128
129 } ll_pwm_init_t;
130
131 /** @} */
132
133 /** @} */
134
135 /**
136 * @defgroup PWM_LL_MACRO Defines
137 * @{
138 */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
142 * @{
143 */
144
145 /** @defgroup PWM_LL_EC_MODE PWM mode
146 * @{
147 */
148 #define LL_PWM_FLICKER_MODE (0x00000000U) /**< PWM flicker mode */
149 #define LL_PWM_BREATH_MODE PWM_MODE_BREATHEN /**< PWM breath mode */
150 /** @} */
151
152 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
153 * @{
154 */
155 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
156 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
157 /** @} */
158
159 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
160 * @{
161 */
162 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
163 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
164 /** @} */
165
166 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
167 * @{
168 */
169 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
170 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
171 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
172 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
173 /** @} */
174
175 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
176 * @{
177 */
178 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
179 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
180 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
181 /** @} */
182
183 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
184 * @{
185 */
186
187 /**
188 * @brief LL PWM Channel InitStrcut default configuartion
189 */
190 #define LL_PWM_CHANNEL_DEFAULT_CONFIG \
191 { \
192 .duty = 50, \
193 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
194 }
195
196 /**
197 * @brief LL PWM InitStrcut default configuartion
198 */
199 #define LL_PWM_DEFAULT_CONFIG \
200 { \
201 .mode = LL_PWM_FLICKER_MODE, \
202 .align = LL_PWM_EDGE_ALIGNED, \
203 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
204 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
205 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
206 .channel_a = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
207 .channel_b = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
208 .channel_c = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
209 }
210
211 /** @} */
212
213 /** @} */
214
215 /* Exported macro ------------------------------------------------------------*/
216 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
217 * @{
218 */
219
220 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
221 * @{
222 */
223
224 /**
225 * @brief Write a value in PWM register
226 * @param __instance__ PWM instance
227 * @param __REG__ Register to be written
228 * @param __VALUE__ Value to be written in the register
229 * @retval None
230 */
231 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
232
233 /**
234 * @brief Read a value in PWM register
235 * @param __instance__ PWM instance
236 * @param __REG__ Register to be read
237 * @retval Register value
238 */
239 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
240
241 /** @} */
242
243 /** @} */
244
245 /** @} */
246
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
249 * @{
250 */
251
252 /** @defgroup PWM_LL_EF_Configuration Configuration functions
253 * @{
254 */
255
256 /**
257 * @brief Enable PWM.
258 *
259 * Register|BitsName
260 * --------|--------
261 * MODE | EN
262 *
263 * @param PWMx PWM instance
264 * @retval None
265 */
266 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
267 {
268 SET_BITS(PWMx->MODE, PWM_MODE_EN);
269 }
270
271 /**
272 * @brief Disable PWM.
273 *
274 * Register|BitsName
275 * --------|--------
276 * MODE | EN
277 *
278 * @param PWMx PWM instance
279 * @retval None
280 */
281 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
282 {
283 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
284 }
285
286 /**
287 * @brief Indicate whether the PWM is enabled.
288 *
289 * Register|BitsName
290 * --------|--------
291 * MODE | EN
292 *
293 * @param PWMx PWM instance
294 * @retval State of bit (1 or 0).
295 */
296 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
297 {
298 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
299 }
300
301 /**
302 * @brief Enable PWM pause.
303 *
304 * Register|BitsName
305 * --------|--------
306 * MODE | PAUSE
307 *
308 * @param PWMx PWM instance
309 * @retval None
310 */
311 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
312 {
313 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
314 }
315
316 /**
317 * @brief Disable PWM pause.
318 *
319 * Register|BitsName
320 * --------|--------
321 * MODE | PAUSE
322 *
323 * @param PWMx PWM instance
324 * @retval None
325 */
326 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
327 {
328 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
329 }
330
331 /**
332 * @brief Indicate whether the PWM pause is enabled.
333 *
334 * Register|BitsName
335 * --------|--------
336 * MODE | PAUSE
337 *
338 * @param PWMx PWM instance
339 * @retval State of bit (1 or 0).
340 */
341 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
342 {
343 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
344 }
345
346 /**
347 * @brief Set PWM mode.
348 *
349 * Register|BitsName
350 * --------|--------
351 * MODE | BREATHEN
352 *
353 * @param PWMx PWM instance
354 * @param mode This parameter can be one of the following values:
355 * @arg @ref LL_PWM_FLICKER_MODE
356 * @arg @ref LL_PWM_BREATH_MODE
357 * @retval None
358 */
359 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
360 {
361 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, mode);
362 }
363
364 /**
365 * @brief Get PWM mode.
366 *
367 * Register|BitsName
368 * --------|--------
369 * MODE | BREATHEN
370 *
371 * @param PWMx PWM instance
372 * @retval Return value can be one of the following values:
373 * @arg @ref LL_PWM_FLICKER_MODE
374 * @arg @ref LL_PWM_BREATH_MODE
375 */
376 __STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
377 {
378 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN));
379 }
380
381 /**
382 * @brief Enable positive drive mode in channelA.
383 *
384 * Register|BitsName
385 * --------|--------
386 * MODE | DPENA
387 *
388 * @param PWMx PWM instance
389 * @retval None
390 */
391 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
392 {
393 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
394 }
395
396 /**
397 * @brief Disable positive drive mode in channelA.
398 *
399 * Register|BitsName
400 * --------|--------
401 * MODE | DPENA
402 *
403 * @param PWMx PWM instance
404 * @retval None
405 */
406 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
407 {
408 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
409 }
410
411 /**
412 * @brief Indicate whether the positive drive mode in channelA is enabled.
413 *
414 * Register|BitsName
415 * --------|--------
416 * MODE | DPENA
417 *
418 * @param PWMx PWM instance
419 * @retval State of bit (1 or 0).
420 */
421 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
422 {
423 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
424 }
425
426 /**
427 * @brief Enable positive drive mode in channelB.
428 *
429 * Register|BitsName
430 * --------|--------
431 * MODE | DPENB
432 *
433 * @param PWMx PWM instance
434 * @retval None
435 */
436 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
437 {
438 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
439 }
440
441 /**
442 * @brief Disable positive drive mode in channelB.
443 *
444 * Register|BitsName
445 * --------|--------
446 * MODE | DPENB
447 *
448 * @param PWMx PWM instance
449 * @retval None
450 */
451 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
452 {
453 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
454 }
455
456 /**
457 * @brief Indicate whether the positive drive mode in channelB is enabled.
458 *
459 * Register|BitsName
460 * --------|--------
461 * MODE | DPENB
462 *
463 * @param PWMx PWM instance
464 * @retval State of bit (1 or 0).
465 */
466 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
467 {
468 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
469 }
470
471 /**
472 * @brief Enable positive drive mode in channelC.
473 *
474 * Register|BitsName
475 * --------|--------
476 * MODE | DPENC
477 *
478 * @param PWMx PWM instance
479 * @retval None
480 */
481 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
482 {
483 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
484 }
485
486 /**
487 * @brief Disable positive drive mode in channelC.
488 *
489 * Register|BitsName
490 * --------|--------
491 * MODE | DPENC
492 *
493 * @param PWMx PWM instance
494 * @retval None
495 */
496 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
497 {
498 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
499 }
500
501 /**
502 * @brief Indicate whether the positive drive mode in channelC is enabled.
503 *
504 * Register|BitsName
505 * --------|--------
506 * MODE | DPENC
507 *
508 * @param PWMx PWM instance
509 * @retval State of bit (1 or 0).
510 */
511 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
512 {
513 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
514 }
515
516 /**
517 * @brief Check update active flag
518 *
519 * Register|BitsName
520 * --------|--------
521 * UPDATE | SAG
522 *
523 * @param PWMx PWM instance
524 * @retval State of bit (1 or 0).
525 */
526 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
527 {
528 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
529 }
530
531 /**
532 * @brief Enable update all parameters.
533 *
534 * Register|BitsName
535 * --------|--------
536 * UPDATE | SA
537 *
538 * @param PWMx PWM instance
539 * @retval None
540 */
541 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
542 {
543 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
544 }
545
546 /**
547 * @brief Disable update all parameters.
548 *
549 * Register|BitsName
550 * --------|--------
551 * UPDATE | SA
552 *
553 * @param PWMx PWM instance
554 * @retval None
555 */
556 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
557 {
558 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
559 }
560
561 /**
562 * @brief Indicate whether the update all parameters is enabled.
563 *
564 * Register|BitsName
565 * --------|--------
566 * UPDATE | SA
567 *
568 * @param PWMx PWM instance
569 * @retval State of bit (1 or 0).
570 */
571 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
572 {
573 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
574 }
575
576 /**
577 * @brief Enable update period.
578 *
579 * Register|BitsName
580 * --------|--------
581 * UPDATE | SSPRD
582 *
583 * @param PWMx PWM instance
584 * @retval None
585 */
586 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
587 {
588 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
589 }
590
591 /**
592 * @brief Disable update period.
593 *
594 * Register|BitsName
595 * --------|--------
596 * UPDATE | SSPRD
597 *
598 * @param PWMx PWM instance
599 * @retval None
600 */
601 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
602 {
603 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
604 }
605
606 /**
607 * @brief Indicate whether the update period is enabled.
608 *
609 * Register|BitsName
610 * --------|--------
611 * UPDATE | SSPRD
612 *
613 * @param PWMx PWM instance
614 * @retval State of bit (1 or 0).
615 */
616 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
617 {
618 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
619 }
620
621 /**
622 * @brief Enable update compareA0.
623 *
624 * Register|BitsName
625 * --------|--------
626 * UPDATE | SSCMPA0
627 *
628 * @param PWMx PWM instance
629 * @retval None
630 */
631 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
632 {
633 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
634 }
635
636 /**
637 * @brief Disable update compareA0.
638 *
639 * Register|BitsName
640 * --------|--------
641 * UPDATE | SSCMPA0
642 *
643 * @param PWMx PWM instance
644 * @retval None
645 */
646 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
647 {
648 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
649 }
650
651 /**
652 * @brief Indicate whether the update compareA0 is enabled.
653 *
654 * Register|BitsName
655 * --------|--------
656 * UPDATE | SSCMPA0
657 *
658 * @param PWMx PWM instance
659 * @retval State of bit (1 or 0).
660 */
661 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
662 {
663 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
664 }
665
666 /**
667 * @brief Enable update compareA1.
668 *
669 * Register|BitsName
670 * --------|--------
671 * UPDATE | SSCMPA1
672 *
673 * @param PWMx PWM instance
674 * @retval None
675 */
676 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
677 {
678 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
679 }
680
681 /**
682 * @brief Disable update compareA1.
683 *
684 * Register|BitsName
685 * --------|--------
686 * UPDATE | SSCMPA1
687 *
688 * @param PWMx PWM instance
689 * @retval None
690 */
691 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
692 {
693 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
694 }
695
696 /**
697 * @brief Indicate whether the update compareA1 is enabled.
698 *
699 * Register|BitsName
700 * --------|--------
701 * UPDATE | SSCMPA1
702 *
703 * @param PWMx PWM instance
704 * @retval State of bit (1 or 0).
705 */
706 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
707 {
708 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
709 }
710
711 /**
712 * @brief Enable update compareB0.
713 *
714 * Register|BitsName
715 * --------|--------
716 * UPDATE | SSCMPB0
717 *
718 * @param PWMx PWM instance
719 * @retval None
720 */
721 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
722 {
723 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
724 }
725
726 /**
727 * @brief Disable update compareB0.
728 *
729 * Register|BitsName
730 * --------|--------
731 * UPDATE | SSCMPB0
732 *
733 * @param PWMx PWM instance
734 * @retval None
735 */
736 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
737 {
738 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
739 }
740
741 /**
742 * @brief Indicate whether the update compareB0 is enabled.
743 *
744 * Register|BitsName
745 * --------|--------
746 * UPDATE | SSCMPB0
747 *
748 * @param PWMx PWM instance
749 * @retval State of bit (1 or 0).
750 */
751 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
752 {
753 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
754 }
755
756 /**
757 * @brief Enable update compareB1.
758 *
759 * Register|BitsName
760 * --------|--------
761 * UPDATE | SSCMPB1
762 *
763 * @param PWMx PWM instance
764 * @retval None
765 */
766 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
767 {
768 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
769 }
770
771 /**
772 * @brief Disable update compareB1.
773 *
774 * Register|BitsName
775 * --------|--------
776 * UPDATE | SSCMPB1
777 *
778 * @param PWMx PWM instance
779 * @retval None
780 */
781 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
782 {
783 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
784 }
785
786 /**
787 * @brief Indicate whether the update compareB1 is enabled.
788 *
789 * Register|BitsName
790 * --------|--------
791 * UPDATE | SSCMPB1
792 *
793 * @param PWMx PWM instance
794 * @retval State of bit (1 or 0).
795 */
796 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
797 {
798 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
799 }
800
801 /**
802 * @brief Enable update compareC0.
803 *
804 * Register|BitsName
805 * --------|--------
806 * UPDATE | SSCMPC0
807 *
808 * @param PWMx PWM instance
809 * @retval None
810 */
811 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
812 {
813 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
814 }
815
816 /**
817 * @brief Disable update compareC0.
818 *
819 * Register|BitsName
820 * --------|--------
821 * UPDATE | SSCMPC0
822 *
823 * @param PWMx PWM instance
824 * @retval None
825 */
826 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
827 {
828 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
829 }
830
831 /**
832 * @brief Indicate whether the update compareC0 is enabled.
833 *
834 * Register|BitsName
835 * --------|--------
836 * UPDATE | SSCMPC0
837 *
838 * @param PWMx PWM instance
839 * @retval State of bit (1 or 0).
840 */
841 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
842 {
843 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
844 }
845
846 /**
847 * @brief Enable update compareC1.
848 *
849 * Register|BitsName
850 * --------|--------
851 * UPDATE | SSCMPC1
852 *
853 * @param PWMx PWM instance
854 * @retval None
855 */
856 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
857 {
858 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
859 }
860
861 /**
862 * @brief Disable update compareC1.
863 *
864 * Register|BitsName
865 * --------|--------
866 * UPDATE | SSCMPC1
867 *
868 * @param PWMx PWM instance
869 * @retval None
870 */
871 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
872 {
873 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
874 }
875
876 /**
877 * @brief Indicate whether the update compareC1 is enabled.
878 *
879 * Register|BitsName
880 * --------|--------
881 * UPDATE | SSCMPC1
882 *
883 * @param PWMx PWM instance
884 * @retval State of bit (1 or 0).
885 */
886 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
887 {
888 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
889 }
890
891 /**
892 * @brief Enable update pause.
893 *
894 * Register|BitsName
895 * --------|--------
896 * UPDATE | SSPAUSE
897 *
898 * @param PWMx PWM instance
899 * @retval None
900 */
901 __STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
902 {
903 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
904 }
905
906 /**
907 * @brief Disable update pause.
908 *
909 * Register|BitsName
910 * --------|--------
911 * UPDATE | SSPAUSE
912 *
913 * @param PWMx PWM instance
914 * @retval None
915 */
916 __STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
917 {
918 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
919 }
920
921 /**
922 * @brief Indicate whether the update pause is enabled.
923 *
924 * Register|BitsName
925 * --------|--------
926 * UPDATE | SSPAUSE
927 *
928 * @param PWMx PWM instance
929 * @retval State of bit (1 or 0).
930 */
931 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
932 {
933 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE) == (PWM_UPDATE_SSPAUSE));
934 }
935
936 /**
937 * @brief Enable update breath period.
938 *
939 * Register|BitsName
940 * --------|--------
941 * UPDATE | SSBRPRD
942 *
943 * @param PWMx PWM instance
944 * @retval None
945 */
946 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
947 {
948 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
949 }
950
951 /**
952 * @brief Disable update breath period.
953 *
954 * Register|BitsName
955 * --------|--------
956 * UPDATE | SSBRPRD
957 *
958 * @param PWMx PWM instance
959 * @retval None
960 */
961 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
962 {
963 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
964 }
965
966 /**
967 * @brief Indicate whether the update breath period is enabled.
968 *
969 * Register|BitsName
970 * --------|--------
971 * UPDATE | SSBRPRD
972 *
973 * @param PWMx PWM instance
974 * @retval State of bit (1 or 0).
975 */
976 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
977 {
978 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
979 }
980
981 /**
982 * @brief Enable update hold period.
983 *
984 * Register|BitsName
985 * --------|--------
986 * UPDATE | SSHOLD
987 *
988 * @param PWMx PWM instance
989 * @retval None
990 */
991 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
992 {
993 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
994 }
995
996 /**
997 * @brief Disable update hold period.
998 *
999 * Register|BitsName
1000 * --------|--------
1001 * UPDATE | SSHOLD
1002 *
1003 * @param PWMx PWM instance
1004 * @retval None
1005 */
1006 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1007 {
1008 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1009 }
1010
1011 /**
1012 * @brief Indicate whether the update hold period is enabled.
1013 *
1014 * Register|BitsName
1015 * --------|--------
1016 * UPDATE | SSHOLD
1017 *
1018 * @param PWMx PWM instance
1019 * @retval State of bit (1 or 0).
1020 */
1021 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1022 {
1023 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1024 }
1025
1026 /**
1027 * @brief Enable update active event.
1028 *
1029 * Register|BitsName
1030 * --------|--------
1031 * UPDATE | SSAQCTRL
1032 *
1033 * @param PWMx PWM instance
1034 * @retval None
1035 */
1036 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1037 {
1038 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1039 }
1040
1041 /**
1042 * @brief Disable update active event.
1043 *
1044 * Register|BitsName
1045 * --------|--------
1046 * UPDATE | SSAQCTRL
1047 *
1048 * @param PWMx PWM instance
1049 * @retval None
1050 */
1051 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1052 {
1053 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1054 }
1055
1056 /**
1057 * @brief Indicate whether the update active event is enabled.
1058 *
1059 * Register|BitsName
1060 * --------|--------
1061 * UPDATE | SSAQCTRL
1062 *
1063 * @param PWMx PWM instance
1064 * @retval State of bit (1 or 0).
1065 */
1066 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1067 {
1068 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1069 }
1070
1071 /**
1072 * @brief Set the PWM prescaler.
1073 *
1074 * Register|BitsName
1075 * --------|--------
1076 * PRD | PRD
1077 *
1078 * @param PWMx PWM instance
1079 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1080 * @retval None
1081 */
1082 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1083 {
1084 WRITE_REG(PWMx->PRD, prescaler);
1085 }
1086
1087 /**
1088 * @brief Get the PWM prescaler.
1089 *
1090 * Register|BitsName
1091 * --------|--------
1092 * PRD | PRD
1093 *
1094 * @param PWMx PWM instance
1095 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1096 */
1097 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1098 {
1099 return (READ_REG(PWMx->PRD));
1100 }
1101
1102 /**
1103 * @brief Set the PWM compare counter A0.
1104 *
1105 * Register|BitsName
1106 * --------|--------
1107 * CMPA0 | CMPA0
1108 *
1109 * @param PWMx PWM instance
1110 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1111 * @retval None
1112 */
1113 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1114 {
1115 WRITE_REG(PWMx->CMPA0, compare);
1116 }
1117
1118 /**
1119 * @brief Get the PWM compare counter A0.
1120 *
1121 * Register|BitsName
1122 * --------|--------
1123 * CMPA0 | CMPA0
1124 *
1125 * @param PWMx PWM instance
1126 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1127 */
1128 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1129 {
1130 return (READ_REG(PWMx->CMPA0));
1131 }
1132
1133 /**
1134 * @brief Set the PWM compare counter A1.
1135 *
1136 * Register|BitsName
1137 * --------|--------
1138 * CMPA1 | CMPA1
1139 *
1140 * @param PWMx PWM instance
1141 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1142 * @retval None
1143 */
1144 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1145 {
1146 WRITE_REG(PWMx->CMPA1, compare);
1147 }
1148
1149 /**
1150 * @brief Get the PWM compare counter A1.
1151 *
1152 * Register|BitsName
1153 * --------|--------
1154 * CMPA1 | CMPA1
1155 *
1156 * @param PWMx PWM instance
1157 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1158 */
1159 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1160 {
1161 return (READ_REG(PWMx->CMPA1));
1162 }
1163
1164 /**
1165 * @brief Set the PWM compare counter B0.
1166 *
1167 * Register|BitsName
1168 * --------|--------
1169 * CMPB0 | CMPB0
1170 *
1171 * @param PWMx PWM instance
1172 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1173 * @retval None
1174 */
1175 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1176 {
1177 WRITE_REG(PWMx->CMPB0, compare);
1178 }
1179
1180 /**
1181 * @brief Get the PWM compare counter B0.
1182 *
1183 * Register|BitsName
1184 * --------|--------
1185 * CMPB0 | CMPB0
1186 *
1187 * @param PWMx PWM instance
1188 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1189 */
1190 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1191 {
1192 return (READ_REG(PWMx->CMPB0));
1193 }
1194
1195 /**
1196 * @brief Set the PWM compare counter B1.
1197 *
1198 * Register|BitsName
1199 * --------|--------
1200 * CMPB1 | CMPB1
1201 *
1202 * @param PWMx PWM instance
1203 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1204 * @retval None
1205 */
1206 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1207 {
1208 WRITE_REG(PWMx->CMPB1, compare);
1209 }
1210
1211 /**
1212 * @brief Get the PWM compare counter B1.
1213 *
1214 * Register|BitsName
1215 * --------|--------
1216 * CMPB1 | CMPB1
1217 *
1218 * @param PWMx PWM instance
1219 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1220 */
1221 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1222 {
1223 return (READ_REG(PWMx->CMPB1));
1224 }
1225
1226 /**
1227 * @brief Set the PWM compare counter C0.
1228 *
1229 * Register|BitsName
1230 * --------|--------
1231 * CMPC0 | CMPC0
1232 *
1233 * @param PWMx PWM instance
1234 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1235 * @retval None
1236 */
1237 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1238 {
1239 WRITE_REG(PWMx->CMPC0, compare);
1240 }
1241
1242 /**
1243 * @brief Get the PWM compare counter C0.
1244 *
1245 * Register|BitsName
1246 * --------|--------
1247 * CMPC0 | CMPC0
1248 *
1249 * @param PWMx PWM instance
1250 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1251 */
1252 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1253 {
1254 return (READ_REG(PWMx->CMPC0));
1255 }
1256
1257 /**
1258 * @brief Set the PWM compare counter C1.
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * CMPC1 | CMPC1
1263 *
1264 * @param PWMx PWM instance
1265 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1266 * @retval None
1267 */
1268 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1269 {
1270 WRITE_REG(PWMx->CMPC1, compare);
1271 }
1272
1273 /**
1274 * @brief Get the PWM compare counter C1.
1275 *
1276 * Register|BitsName
1277 * --------|--------
1278 * CMPC1 | CMPC1
1279 *
1280 * @param PWMx PWM instance
1281 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1282 */
1283 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1284 {
1285 return (READ_REG(PWMx->CMPC1));
1286 }
1287
1288 /**
1289 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1290 *
1291 * Register|BitsName
1292 * --------|--------
1293 * AQCTRL | A0
1294 *
1295 * @param PWMx PWM instance
1296 * @param action_event This parameter can be one of the following values:
1297 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1298 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1299 * @arg @ref LL_PWM_ACTIONEVENT_SET
1300 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1301 * @retval None
1302 */
1303 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1304 {
1305 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1306 }
1307
1308 /**
1309 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1310 *
1311 * Register|BitsName
1312 * --------|--------
1313 * AQCTRL | A0
1314 *
1315 * @param PWMx PWM instance
1316 * @retval Return value can be one of the following values:
1317 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1318 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1319 * @arg @ref LL_PWM_ACTIONEVENT_SET
1320 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1321 */
1322 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1323 {
1324 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1325 }
1326
1327 /**
1328 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1329 *
1330 * Register|BitsName
1331 * --------|--------
1332 * AQCTRL | A1
1333 *
1334 * @param PWMx PWM instance
1335 * @param action_event This parameter can be one of the following values:
1336 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1337 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1338 * @arg @ref LL_PWM_ACTIONEVENT_SET
1339 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1340 * @retval None
1341 */
1342 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1343 {
1344 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1345 }
1346
1347 /**
1348 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1349 *
1350 * Register|BitsName
1351 * --------|--------
1352 * AQCTRL | A1
1353 *
1354 * @param PWMx PWM instance
1355 * @retval Return value can be one of the following values:
1356 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1357 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1358 * @arg @ref LL_PWM_ACTIONEVENT_SET
1359 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1360 */
1361 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1362 {
1363 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1364 }
1365
1366 /**
1367 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1368 *
1369 * Register|BitsName
1370 * --------|--------
1371 * AQCTRL | B0
1372 *
1373 * @param PWMx PWM instance
1374 * @param action_event This parameter can be one of the following values:
1375 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1376 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1377 * @arg @ref LL_PWM_ACTIONEVENT_SET
1378 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1379 * @retval None
1380 */
1381 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1382 {
1383 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1384 }
1385
1386 /**
1387 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1388 *
1389 * Register|BitsName
1390 * --------|--------
1391 * AQCTRL | B0
1392 *
1393 * @param PWMx PWM instance
1394 * @retval Return value can be one of the following values:
1395 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1396 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1397 * @arg @ref LL_PWM_ACTIONEVENT_SET
1398 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1399 */
1400 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1401 {
1402 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1403 }
1404
1405 /**
1406 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1407 *
1408 * Register|BitsName
1409 * --------|--------
1410 * AQCTRL | B1
1411 *
1412 * @param PWMx PWM instance
1413 * @param action_event This parameter can be one of the following values:
1414 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1415 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1416 * @arg @ref LL_PWM_ACTIONEVENT_SET
1417 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1418 * @retval None
1419 */
1420 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1421 {
1422 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1423 }
1424
1425 /**
1426 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1427 *
1428 * Register|BitsName
1429 * --------|--------
1430 * AQCTRL | B1
1431 *
1432 * @param PWMx PWM instance
1433 * @retval Return value can be one of the following values:
1434 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1435 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1436 * @arg @ref LL_PWM_ACTIONEVENT_SET
1437 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1438 */
1439 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1440 {
1441 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1442 }
1443
1444 /**
1445 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1446 *
1447 * Register|BitsName
1448 * --------|--------
1449 * AQCTRL | C0
1450 *
1451 * @param PWMx PWM instance
1452 * @param action_event This parameter can be one of the following values:
1453 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1454 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1455 * @arg @ref LL_PWM_ACTIONEVENT_SET
1456 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1457 * @retval None
1458 */
1459 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1460 {
1461 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1462 }
1463
1464 /**
1465 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1466 *
1467 * Register|BitsName
1468 * --------|--------
1469 * AQCTRL | C0
1470 *
1471 * @param PWMx PWM instance
1472 * @retval Return value can be one of the following values:
1473 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1474 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1475 * @arg @ref LL_PWM_ACTIONEVENT_SET
1476 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1477 */
1478 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1479 {
1480 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1481 }
1482
1483 /**
1484 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1485 *
1486 * Register|BitsName
1487 * --------|--------
1488 * AQCTRL | C1
1489 *
1490 * @param PWMx PWM instance
1491 * @param action_event This parameter can be one of the following values:
1492 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1493 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1494 * @arg @ref LL_PWM_ACTIONEVENT_SET
1495 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1496 * @retval None
1497 */
1498 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1499 {
1500 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1501 }
1502
1503 /**
1504 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1505 *
1506 * Register|BitsName
1507 * --------|--------
1508 * AQCTRL | C1
1509 *
1510 * @param PWMx PWM instance
1511 * @retval Return value can be one of the following values:
1512 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1513 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1514 * @arg @ref LL_PWM_ACTIONEVENT_SET
1515 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1516 */
1517 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1518 {
1519 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1520 }
1521
1522 /**
1523 * @brief Set the breath prescaler in breath mode.
1524 *
1525 * Register|BitsName
1526 * --------|--------
1527 * BRPRD | BRPRD
1528 *
1529 * @param PWMx PWM instance
1530 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1531 * @retval None
1532 */
1533 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1534 {
1535 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1536 }
1537
1538 /**
1539 * @brief Get the breath prescaler in breath mode.
1540 *
1541 * Register|BitsName
1542 * --------|--------
1543 * BRPRD | BRPRD
1544 *
1545 * @param PWMx PWM instance
1546 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1547 */
1548 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1549 {
1550 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1551 }
1552
1553 /**
1554 * @brief Set the hold prescaler in breath mode.
1555 *
1556 * Register|BitsName
1557 * --------|--------
1558 * HOLD | HOLD
1559 *
1560 * @param PWMx PWM instance
1561 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1562 * @retval None
1563 */
1564 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1565 {
1566 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1567 }
1568
1569 /**
1570 * @brief Get the hold prescaler in breath mode.
1571 *
1572 * Register|BitsName
1573 * --------|--------
1574 * HOLD | HOLD
1575 *
1576 * @param PWMx PWM instance
1577 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1578 */
1579 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1580 {
1581 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1582 }
1583
1584 /** @} */
1585
1586 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
1587 * @{
1588 */
1589
1590 /**
1591 * @brief De-initialize PWM registers (Registers restored to their default values).
1592 * @param PWMx PWM instance
1593 * @retval An error_status_t enumeration value:
1594 * - SUCCESS: PWM registers are de-initialized
1595 * - ERROR: PWM registers are not de-initialized
1596 */
1597 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
1598
1599 /**
1600 * @brief Initialize PWM registers according to the specified
1601 * parameters in PWM_InitStruct.
1602 * @param PWMx PWM instance
1603 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
1604 * information for the specified PWM peripheral.
1605 * @retval An error_status_t enumeration value:
1606 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
1607 * - ERROR: Problem occurred during PWM Registers initialization
1608 */
1609 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
1610
1611 /**
1612 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
1613 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
1614 * whose fields will be set to default values.
1615 * @retval None
1616 */
1617 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
1618
1619 /** @} */
1620
1621 /** @} */
1622
1623 #endif /* PWM0 || PWM1 */
1624
1625 #ifdef __cplusplus
1626 }
1627 #endif
1628
1629 #endif /* __GR55XX_LL_PWM_H__ */
1630
1631 /** @} */
1632
1633 /** @} */
1634
1635 /** @} */
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: gr55xx_ll_pwm.h:871
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: gr55xx_ll_pwm.h:466
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1237
_ll_pwm_init_t::channel_c
ll_pwm_channel_init_t channel_c
Specifies the configuration of channelC.
Definition: gr55xx_ll_pwm.h:126
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1381
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1252
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1268
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1113
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1517
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: gr55xx_ll_pwm.h:94
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: gr55xx_ll_pwm.h:1051
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: gr55xx_ll_pwm.h:736
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: gr55xx_ll_pwm.h:541
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1097
ll_pwm_init
error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1128
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1548
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: gr55xx_ll_pwm.h:1006
ll_pwm_deinit
error_status_t ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
_ll_pwm_channel_init_t::drive_polarity
uint8_t drive_polarity
Specifies the drive polarity in PWM output mode.
Definition: gr55xx_ll_pwm.h:82
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: gr55xx_ll_pwm.h:796
_ll_pwm_init_t::bprescaler
uint32_t bprescaler
Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
Definition: gr55xx_ll_pwm.h:109
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: gr55xx_ll_pwm.h:1036
ll_pwm_enable_update_pause
__STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
Enable update pause.
Definition: gr55xx_ll_pwm.h:901
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1303
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1144
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1221
ll_pwm_get_mode
__STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: gr55xx_ll_pwm.h:376
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: gr55xx_ll_pwm.h:571
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1420
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: gr55xx_ll_pwm.h:296
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: gr55xx_ll_pwm.h:826
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1400
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: gr55xx_ll_pwm.h:691
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: gr55xx_ll_pwm.h:311
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: gr55xx_ll_pwm.h:1066
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: gr55xx_ll_pwm.h:661
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: gr55xx_ll_pwm.h:751
_ll_pwm_init_t::mode
uint32_t mode
Specifies the PWM output mode.
Definition: gr55xx_ll_pwm.h:95
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1190
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: gr55xx_ll_pwm.h:586
_ll_pwm_init_t::hprescaler
uint32_t hprescaler
Specifies the required prescaler in breath hold state.
Definition: gr55xx_ll_pwm.h:115
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: gr55xx_ll_pwm.h:991
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1533
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: gr55xx_ll_pwm.h:341
_ll_pwm_init_t::channel_b
ll_pwm_channel_init_t channel_b
Specifies the configuration of channelB.
Definition: gr55xx_ll_pwm.h:123
ll_pwm_disable_update_pause
__STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
Disable update pause.
Definition: gr55xx_ll_pwm.h:916
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: gr55xx_ll_pwm.h:856
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: gr55xx_ll_pwm.h:781
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: gr55xx_ll_pwm.h:326
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: gr55xx_ll_pwm.h:421
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1498
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1159
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: gr55xx_ll_pwm.h:616
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: gr55xx_ll_pwm.h:976
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: gr55xx_ll_pwm.h:721
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: gr55xx_ll_pwm.h:766
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: gr55xx_ll_pwm.h:601
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1579
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: gr55xx_ll_pwm.h:646
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: gr55xx_ll_pwm.h:946
_ll_pwm_init_t::align
uint32_t align
Specifies the PWM alignment pulses.
Definition: gr55xx_ll_pwm.h:100
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: gr55xx_ll_pwm.h:631
ll_pwm_channel_init_t
struct _ll_pwm_channel_init_t ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: gr55xx_ll_pwm.h:1021
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1361
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: gr55xx_ll_pwm.h:556
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: gr55xx_ll_pwm.h:526
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1564
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: gr55xx_ll_pwm.h:841
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:496
_ll_pwm_init_t::channel_a
ll_pwm_channel_init_t channel_a
Specifies the configuration of channelA.
Definition: gr55xx_ll_pwm.h:120
_ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr55xx_ll_pwm.h:75
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1206
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: gr55xx_ll_pwm.h:886
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:436
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: gr55xx_ll_pwm.h:266
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:451
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: gr55xx_ll_pwm.h:281
_ll_pwm_init_t::prescaler
uint32_t prescaler
Specifies the prescaler value which will be used configure PWM output frequency.
Definition: gr55xx_ll_pwm.h:103
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1175
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:406
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1459
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:481
ll_pwm_is_enabled_update_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
Indicate whether the update pause is enabled.
Definition: gr55xx_ll_pwm.h:931
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1342
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1283
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: gr55xx_ll_pwm.h:961
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1322
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: gr55xx_ll_pwm.h:676
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1082
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1439
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: gr55xx_ll_pwm.h:811
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: gr55xx_ll_pwm.h:511
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
Set PWM mode.
Definition: gr55xx_ll_pwm.h:359
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: gr55xx_ll_pwm.h:706
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1478
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:391
_ll_pwm_channel_init_t::duty
uint8_t duty
Specifies the duty in PWM output mode.
Definition: gr55xx_ll_pwm.h:76