gr55xx_ll_xqspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_xqspi.h
5 * @author BLE SDK Team
6 * @brief Header file containing functions prototypes of XQSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_XQSPI XQSPI
47 * @brief XQSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (XQSPI)
63
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief XQSPI init structures definition
75 */
76 typedef struct _ll_xqspi_init_t
77 {
78 uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
79 This parameter can be a value of @ref XQSPI_LL_EC_MODE.*/
80
81 uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
82 This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
83
84 This feature can be modified afterwards using unitary function @ref ll_xqspi_enable_cache().*/
85
86 uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
87 This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
88
89 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cmd().*/
90
91 uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
92 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
93
94 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_datasize().*/
95
96 uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
97 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
98
99 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_data_order().*/
100
101 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
102 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_POLARITY in XIP mode or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
103
104 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol().*/
105
106 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
107 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_PHASE in XIP mode or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
108
109 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha().*/
110
111 uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and receive SCK clock.
112 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
113
114 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_speed().*/
115
116 } ll_xqspi_init_t;
117
118 /** @} */
119
120 /** @} */
121
122 /**
123 * @defgroup XQSPI_LL_MACRO Defines
124 * @{
125 */
126
127 /* Exported constants --------------------------------------------------------*/
128 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
129 * @{
130 */
131
132 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
133 * @{
134 */
135 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
136 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
137 /** @} */
138
139 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
140 * @{
141 */
142 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
143 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
144 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
145 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
146 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
147 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
148 /** @} */
149
150 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
151 * @{
152 */
153 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
154 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
155 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
156 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
157 /** @} */
158
159 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
160 * @{
161 */
162 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
163 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
164 /** @} */
165
166 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
167 * @{
168 */
169 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
170 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
171 /** @} */
172
173 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
174 * @{
175 */
176 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
177 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
178 /** @} */
179
180 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
181 * @{
182 */
183 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
184 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
185 /** @} */
186
187 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
188 * @{
189 */
190 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
191 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
192 /** @} */
193
194 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
195 * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
196 * @{
197 */
198 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
199 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
200 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
201 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
202 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
203 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
204 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
205 /** @} */
206
207 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
208 * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
209 * @{
210 */
211 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
212 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
213 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt enable */
214 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt enable */
215 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
216
217 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
218 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
219 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
220 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt flag */
221 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
222 /** @} */
223
224 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
225 * @{
226 */
227 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
228 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
229 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
230 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
231 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL /**< FIFO full depth */
232 /** @} */
233
234 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
235 * @{
236 */
237 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
238 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format for transfer */
239 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format for transfer */
240 /** @} */
241
242 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
243 * @{
244 */
245 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
246 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
247 /** @} */
248
249 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
250 * @{
251 */
252 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI transfer: 4 bits */
253 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 8 bits */
254 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 12 bits */
255 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 16 bits */
256 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 20 bits */
257 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 24 bits */
258 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 28 bits */
259 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 32 bits */
260 /** @} */
261
262 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
263 * @{
264 */
265 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
266 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
267 /** @} */
268
269 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
270 * @{
271 */
272 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
273 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
274 /** @} */
275
276 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
277 * @{
278 */
279 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
280 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
281 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
282 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
283 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
284 /** @} */
285
286 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
287 * @{
288 */
289 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
290 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
291 /** @} */
292
293 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
294 * @{
295 */
296 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
297 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
298 /** @} */
299
300 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
301 * @{
302 */
303
304 /**
305 * @brief LL XQSPI InitStrcut default configuartion
306 */
307 #define LL_XQSPI_DEFAULT_CONFIG \
308 { \
309 .mode = LL_XQSPI_MODE_QSPI, \
310 .cache_mode = LL_XQSPI_CACHE_EN, \
311 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
312 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
313 .data_order = LL_XQSPI_QSPI_MSB, \
314 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
315 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
316 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
317 }
318 /** @} */
319
320 /** @} */
321
322 /* Exported macro ------------------------------------------------------------*/
323 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
324 * @{
325 */
326
327 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
328 * @{
329 */
330
331 /**
332 * @brief Write a value in XQSPI register
333 * @param __instance__ XQSPI instance
334 * @param __REG__ Register to be written
335 * @param __VALUE__ Value to be written in the register
336 * @retval None
337 */
338 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
339
340 /**
341 * @brief Read a value in XQSPI register
342 * @param __instance__ XQSPI instance
343 * @param __REG__ Register to be read
344 * @retval Register value
345 */
346 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
347
348 /** @} */
349
350 /** @} */
351
352 /** @} */
353
354 /* Exported functions --------------------------------------------------------*/
355 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
356 * @{
357 */
358
359 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
360 * @{
361 */
362
363 /**
364 * @brief Enable cache function
365 * @note This bit should not be changed when XIP is ongoing.
366 *
367 * Register|BitsName
368 * --------|--------
369 * CTRL0 |EN
370 *
371 * @param XQSPIx XQSPI instance
372 * @retval None
373 */
374 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
375 {
376 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
377 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
378 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
379 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
380 }
381
382 /**
383 * @brief Disable cache function
384 * @note This bit should not be changed when XIP is ongoing.
385 *
386 * Register|BitsName
387 * --------|--------
388 * CTRL0 |EN
389 *
390 * @param XQSPIx XQSPI instance
391 * @retval None
392 */
393 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
394 {
395 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
396 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
397 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
398 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
399 }
400
401 /**
402 * @brief Check if cache function is enabled
403 *
404 * Register|BitsName
405 * --------|--------
406 * CTRL0 |EN
407 *
408 * @param XQSPIx XQSPI instance
409 * @retval State of bit (1 or 0).
410 */
411 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
412 {
413 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
414 }
415
416 /**
417 * @brief Enable tag memory flush
418 * @note This bit should not be changed when XIP is ongoing.
419 *
420 * Register|BitsName
421 * --------|--------
422 * CTRL0 |TAG
423 *
424 * @param XQSPIx XQSPI instance
425 * @retval None
426 */
427 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
428 {
429 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
430 }
431
432 /**
433 * @brief Disable tag memory flush
434 * @note This bit should not be changed when XIP is ongoing.
435 *
436 * Register|BitsName
437 * --------|--------
438 * CTRL0 |TAG
439 *
440 * @param XQSPIx XQSPI instance
441 * @retval None
442 */
443 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
444 {
445 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
446 }
447
448 /**
449 * @brief Check if tag memory flush is enabled
450 *
451 * Register|BitsName
452 * --------|--------
453 * CTRL0 |TAG
454 *
455 * @param XQSPIx XQSPI instance
456 * @retval State of bit (1 or 0).
457 */
458 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
459 {
460 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
461 }
462
463 /**
464 * @brief Set FIFO mode
465 * @note This bit should not be changed when XIP is ongoing.
466 *
467 * Register|BitsName
468 * --------|--------
469 * CTRL0 |FIFO
470 *
471 * @param XQSPIx XQSPI instance
472 * @param mode This parameter can be one of the following values:
473 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
474 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
475 * @retval None
476 */
477 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
478 {
479 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
480 }
481
482 /**
483 * @brief Get FIFO mode
484 * @note This bit should not be changed when XIP is ongoing.
485 *
486 * Register|BitsName
487 * --------|--------
488 * CTRL0 |FIFO
489 *
490 * @param XQSPIx XQSPI instance
491 * @retval Returned Value can be one of the following values:
492 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
493 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
494 */
495 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
496 {
497 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
498 }
499
500 /**
501 * @brief Set HIT/MISS mode
502 * @note This bit should not be changed when XIP is ongoing.
503 *
504 * Register|BitsName
505 * --------|--------
506 * CTRL0 |HITMISS
507 *
508 * @param XQSPIx XQSPI instance
509 * @param mode This parameter can be one of the following values:
510 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
511 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
512 * @retval None
513 */
514 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
515 {
516 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
517 }
518
519 /**
520 * @brief Get HIT/MISS mode
521 * @note This bit should not be changed when XIP is ongoing.
522 *
523 * Register|BitsName
524 * --------|--------
525 * CTRL0 |HITMISS
526 *
527 * @param XQSPIx XQSPI instance
528 * @retval Returned Value can be one of the following values:
529 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
530 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
531 */
532 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
533 {
534 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
535 }
536
537 /**
538 * @brief Set debugbus configurations signals
539 * @note These bits should not be changed when XIP is ongoing.
540 *
541 * Register|BitsName
542 * --------|--------
543 * CTRL1 |DBGBUS_SEL
544 *
545 * @param XQSPIx XQSPI instance
546 * @param sel This parameter can between: 0 ~ 0x7
547 * @retval None
548 */
549 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
550 {
551 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
552 }
553
554 /**
555 * @brief Get debugbus configurations signals
556 *
557 * Register|BitsName
558 * --------|--------
559 * CTRL1 |DBGBUS_SEL
560 *
561 * @param XQSPIx XQSPI instance
562 * @retval Returned Value can between: 0 ~ 0x7
563 */
564 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
565 {
566 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
567 }
568
569 /**
570 * @brief Enable debug bus mux
571 * @note This bit should not be changed when XIP is ongoing.
572 *
573 * Register|BitsName
574 * --------|--------
575 * CTRL1 |DBGMUX_EN
576 *
577 * @param XQSPIx XQSPI instance
578 * @retval None
579 */
580 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
581 {
582 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
583 }
584
585 /**
586 * @brief Disable debug bus mux
587 * @note This bit should not be changed when XIP is ongoing.
588 *
589 * Register|BitsName
590 * --------|--------
591 * CTRL1 |DBGMUX_EN
592 *
593 * @param XQSPIx XQSPI instance
594 * @retval None
595 */
596 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
597 {
598 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
599 }
600
601 /**
602 * @brief Check if debug bus mux is enabled
603 *
604 * Register|BitsName
605 * --------|--------
606 * CTRL1 |DBGMUX_EN
607 *
608 * @param XQSPIx XQSPI instance
609 * @retval State of bit (1 or 0).
610 */
611 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
612 {
613 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
614 }
615
616 /**
617 * @brief Get hit counter
618 * @note This bit only be read.
619 *
620 * Register|BitsName
621 * --------|--------
622 * HIT_COUNT|HITCOUNT
623 *
624 * @param XQSPIx XQSPI instance
625 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
626 */
627 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
628 {
629 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
630 }
631
632 /**
633 * @brief Get miss counter
634 * @note This bit only be read.
635 *
636 * Register|BitsName
637 * --------|--------
638 * MISS_COUNT|MISSCOUNT
639 *
640 * @param XQSPIx XQSPI instance
641 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
642 */
643 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
644 {
645 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
646 }
647
648 /**
649 * @brief Get cache status
650 * @note This bit only be read.
651 *
652 * Register|BitsName
653 * --------|--------
654 * STAT |STAT
655 *
656 * @param XQSPIx XQSPI instance
657 * @retval Returned Value can between: 0 ~ 1
658 */
659 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
660 {
661 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
662 }
663
664 /** @} */
665
666 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
667 * @{
668 */
669
670 /**
671 * @brief Set read command
672 * @note These bits should not be changed when XIP is ongoing.
673 *
674 * Register|BitsName
675 * --------|--------
676 * CTRL0 |CFG_CMD
677 *
678 * @param XQSPIx XQSPI instance
679 * @param cmd This parameter can be one of the following values:
680 * @arg @ref LL_XQSPI_XIP_CMD_READ
681 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
682 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
683 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
684 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
685 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
686 * @retval None
687 */
688 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
689 {
690 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
691 }
692
693 /**
694 * @brief Get read command
695 *
696 * Register|BitsName
697 * --------|--------
698 * CTRL0 |CFG_CMD
699 *
700 * @param XQSPIx XQSPI instance
701 * @retval Returned Value can be one of the following values:
702 * @arg @ref LL_XQSPI_XIP_CMD_READ
703 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
704 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
705 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
706 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
707 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
708 */
709 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
710 {
711 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
712 }
713
714 /**
715 * @brief Enable high performance mode
716 * @note This bit should not be changed when XIP is ongoing.
717 *
718 * Register|BitsName
719 * --------|--------
720 * CTRL1 |CFG_HPEN
721 *
722 * @param XQSPIx XQSPI instance
723 * @retval None
724 */
725 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
726 {
727 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
728 }
729
730 /**
731 * @brief Disable high performance mode
732 * @note This bit should not be changed when XIP is ongoing.
733 *
734 * Register|BitsName
735 * --------|--------
736 * CTRL1 |CFG_HPEN
737 *
738 * @param XQSPIx XQSPI instance
739 * @retval None
740 */
741 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
742 {
743 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
744 }
745
746 /**
747 * @brief Check if high performance mode is enabled
748 *
749 * Register|BitsName
750 * --------|--------
751 * CTRL1 |CFG_HPEN
752 *
753 * @param XQSPIx XQSPI instance
754 * @retval State of bit (1 or 0).
755 */
756 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
757 {
758 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
759 }
760
761 /**
762 * @brief Set slave select
763 * @note These bits should not be changed when XIP is ongoing.
764 *
765 * Register|BitsName
766 * --------|--------
767 * CTRL1 |CFG_SS
768 *
769 * @param XQSPIx XQSPI instance
770 * @param ss This parameter can be one or more of the following values:
771 * @arg @ref LL_XQSPI_XIP_SS0
772 * @arg @ref LL_XQSPI_XIP_SS1
773 * @arg @ref LL_XQSPI_XIP_SS2
774 * @arg @ref LL_XQSPI_XIP_SS3
775 * @retval None
776 */
777 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
778 {
779 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
780 }
781
782 /**
783 * @brief Get slave select
784 *
785 * Register|BitsName
786 * --------|--------
787 * CTRL1 |CFG_SS
788 *
789 * @param XQSPIx XQSPI instance
790 * @retval Returned Value can be one of the following values:
791 * @arg @ref LL_XQSPI_XIP_SS0
792 * @arg @ref LL_XQSPI_XIP_SS1
793 * @arg @ref LL_XQSPI_XIP_SS2
794 * @arg @ref LL_XQSPI_XIP_SS3
795 */
796 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
797 {
798 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
799 }
800
801 /**
802 * @brief Set clock phase
803 * @note This bit should not be changed when XIP is ongoing.
804 *
805 * Register|BitsName
806 * --------|--------
807 * CTRL1 |CFG_CPHA
808 *
809 * @param XQSPIx XQSPI instance
810 * @param cpha This parameter can be one or more of the following values:
811 * @arg @ref LL_XQSPI_SCPHA_1EDGE
812 * @arg @ref LL_XQSPI_SCPHA_2EDGE
813 * @retval None
814 */
815 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
816 {
817 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
818 }
819
820 /**
821 * @brief Get clock phase
822 *
823 * Register|BitsName
824 * --------|--------
825 * CTRL1 |CFG_CPHA
826 *
827 * @param XQSPIx XQSPI instance
828 * @retval Returned Value can be one of the following values:
829 * @arg @ref LL_XQSPI_SCPHA_1EDGE
830 * @arg @ref LL_XQSPI_SCPHA_2EDGE
831 */
832 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
833 {
834 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
835 }
836
837 /**
838 * @brief Set clock polarity
839 * @note This bit should not be changed when XIP is ongoing.
840 *
841 * Register|BitsName
842 * --------|--------
843 * CTRL1 |CFG_CPOL
844 *
845 * @param XQSPIx XQSPI instance
846 * @param cpol This parameter can be one or more of the following values:
847 * @arg @ref LL_XQSPI_SCPOL_LOW
848 * @arg @ref LL_XQSPI_SCPOL_HIGH
849 * @retval None
850 */
851 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
852 {
853 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
854 }
855
856 /**
857 * @brief Get clock polarity
858 *
859 * Register|BitsName
860 * --------|--------
861 * CTRL1 |CFG_CPOL
862 *
863 * @param XQSPIx XQSPI instance
864 * @retval Returned Value can be one of the following values:
865 * @arg @ref LL_XQSPI_SCPOL_LOW
866 * @arg @ref LL_XQSPI_SCPOL_HIGH
867 */
868 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
869 {
870 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
871 }
872
873 /**
874 * @brief Set address bytes in command
875 * @note This bit should not be changed when XIP is ongoing.
876 *
877 * Register|BitsName
878 * --------|--------
879 * CTRL1 |CFG_ADDR4
880 *
881 * @param XQSPIx XQSPI instance
882 * @param size This parameter can be one or more of the following values:
883 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
884 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
885 * @retval None
886 */
887 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
888 {
889 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
890 }
891
892 /**
893 * @brief Get address bytes in command
894 *
895 * Register|BitsName
896 * --------|--------
897 * CTRL1 |CFG_ADDR4
898 *
899 * @param XQSPIx XQSPI instance
900 * @retval Returned Value can be one of the following values:
901 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
902 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
903 */
904 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
905 {
906 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
907 }
908
909 /**
910 * @brief Set endian in reading data
911 * @note This bit should not be changed when XIP is ongoing.
912 *
913 * Register|BitsName
914 * --------|--------
915 * CTRL1 |CFG_LE32
916 *
917 * @param XQSPIx XQSPI instance
918 * @param endian This parameter can be one or more of the following values:
919 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
920 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
921 * @retval None
922 */
923 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
924 {
925 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
926 }
927
928 /**
929 * @brief Get endian in reading data
930 *
931 * Register|BitsName
932 * --------|--------
933 * CTRL1 |CFG_LE32
934 *
935 * @param XQSPIx XQSPI instance
936 * @retval Returned Value can be one of the following values:
937 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
938 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
939 */
940 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
941 {
942 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
943 }
944
945 /**
946 * @brief Set high performance command
947 * @note These bits should not be changed when XIP is ongoing.
948 *
949 * Register|BitsName
950 * --------|--------
951 * CTRL2 |CFG_HPMODE
952 *
953 * @param XQSPIx XQSPI instance
954 * @param cmd This value is specified by different QSPI FLASH memory vendor to enter into its status register
955 * to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF.
956 * @retval None
957 */
958 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
959 {
960 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
961 }
962
963 /**
964 * @brief Get high performance command
965 *
966 * Register|BitsName
967 * --------|--------
968 * CTRL2 |CFG_HPMODE
969 *
970 * @param XQSPIx XQSPI instance
971 * @retval Returned Value can between: 0 ~ 0xFF.
972 */
973 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
974 {
975 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
976 }
977
978 /**
979 * @brief Set dummy cycles in command
980 * @note These bits should not be changed when XIP is ongoing.
981 * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
982 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
983 * - Fast Read Dual Out: dummycycles = 8 * cycles
984 * - Fast Read Quad Out: dummycycles = 8 * cycles
985 *
986 * Register|BitsName
987 * --------|--------
988 * CTRL2 |CFG_DUMMYCYCLES
989 *
990 * @param XQSPIx XQSPI instance
991 * @param cycles This parameter can between: 0 ~ 0xF.
992 * @retval None
993 */
994 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
995 {
996 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
997 }
998
999 /**
1000 * @brief Get dummy cycles in command
1001 * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1002 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1003 * - Fast Read Dual Out: dummycycles = 8 * cycles
1004 * - Fast Read Quad Out: dummycycles = 8 * cycles
1005 *
1006 * Register|BitsName
1007 * --------|--------
1008 * CTRL2 |CFG_DUMMYCYCLES
1009 *
1010 * @param XQSPIx XQSPI instance
1011 * @retval Returned Value can between: 0 ~ 0xF.
1012 */
1013 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1014 {
1015 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES));
1016 }
1017
1018 /**
1019 * @brief Set dummy cycles in high performance end
1020 * @note These bits should not be changed when XIP is ongoing.
1021 *
1022 * Register|BitsName
1023 * --------|--------
1024 * CTRL2 |CFG_ENDDUMMY
1025 *
1026 * @param XQSPIx XQSPI instance
1027 * @param cycles This parameter can between: 0 ~ 3.
1028 * @retval None
1029 */
1030 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1031 {
1032 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1033 }
1034
1035 /**
1036 * @brief Get dummy cycles in high performance end
1037 *
1038 * Register|BitsName
1039 * --------|--------
1040 * CTRL2 |CFG_ENDDUMMY
1041 *
1042 * @param XQSPIx XQSPI instance
1043 * @retval Returned Value can between: 0 ~ 3.
1044 */
1045 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1046 {
1047 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1048 }
1049
1050 /**
1051 * @brief Enable XIP mode
1052 *
1053 * Register|BitsName
1054 * --------|--------
1055 * CTRL3 |EN_REQ
1056 *
1057 * @param XQSPIx XQSPI instance
1058 * @retval None
1059 */
1060 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1061 {
1062 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1063 }
1064
1065 /**
1066 * @brief Disable XIP mode
1067 *
1068 * Register|BitsName
1069 * --------|--------
1070 * CTRL3 |EN_REQ
1071 *
1072 * @param XQSPIx XQSPI instance
1073 * @retval None
1074 */
1075 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1076 {
1077 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1078 }
1079
1080 /**
1081 * @brief Check if XIP mode is enabled
1082 * @note This bit should not be changed when XIP is ongoing.
1083 *
1084 * Register|BitsName
1085 * --------|--------
1086 * CTRL3 |EN_REQ
1087 *
1088 * @param XQSPIx XQSPI instance
1089 * @retval State of bit (1 or 0).
1090 */
1091 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1092 {
1093 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1094 }
1095
1096 /**
1097 * @brief Get XIP status
1098 * @note This bit is read-only.
1099 *
1100 * Register|BitsName
1101 * --------|--------
1102 * STAT |EN_OUT
1103 *
1104 * @param XQSPIx XQSPI instance
1105 * @retval Returned Value can between: 0 ~ 1
1106 */
1107 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1108 {
1109 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1110 }
1111
1112 /**
1113 * @brief Check if XIP interrupt is enabled
1114 * @note This bit is read-only.
1115 *
1116 * Register|BitsName
1117 * --------|--------
1118 * INTEN |INT_EN
1119 *
1120 * @param XQSPIx XQSPI instance
1121 * @retval Returned Value can between: 0 ~ 1
1122 */
1123 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1124 {
1125 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1126 }
1127
1128 /**
1129 * @brief Get XIP interrupt flag
1130 * @note This bit is read-only.
1131 *
1132 * Register|BitsName
1133 * --------|--------
1134 * INTSTAT |INT_STAT
1135 *
1136 * @param XQSPIx XQSPI instance
1137 * @retval Returned Value can between: 0 ~ 1
1138 */
1139 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1140 {
1141 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1142 }
1143
1144 /**
1145 * @brief Get XIP interrupt request
1146 * @note This bit is read-only.
1147 *
1148 * Register|BitsName
1149 * --------|--------
1150 * INTREQ |INT_REQ
1151 *
1152 * @param XQSPIx XQSPI instance
1153 * @retval Returned Value can between: 0 ~ 1
1154 */
1155 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1156 {
1157 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1158 }
1159
1160 /**
1161 * @brief Set XIP interrupt enable
1162 * @note This bit is write-only.
1163 *
1164 * Register|BitsName
1165 * --------|--------
1166 * INTSET |INT_SET
1167 *
1168 * @param XQSPIx XQSPI instance
1169 * @retval None
1170 */
1171 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1172 {
1173 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1174 }
1175
1176 /**
1177 * @brief Set XIP interrupt disable
1178 * @note This bit is write-only.
1179 *
1180 * Register|BitsName
1181 * --------|--------
1182 * INTCLR |INT_CLR
1183 *
1184 * @param XQSPIx XQSPI instance
1185 * @retval None
1186 */
1187 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1188 {
1189 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1190 }
1191
1192 /** @} */
1193
1194 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1195 * @{
1196 */
1197
1198 /**
1199 * @brief Write 8-bit in the data register
1200 *
1201 * Register|BitsName
1202 * --------|--------
1203 * TX_DATA | DATA
1204 *
1205 * @param XQSPIx XQSPI instance
1206 * @param tx_data This parameter can between: 0x00 ~ 0xFF
1207 * @retval None
1208 */
1209 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1210 {
1211 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1212 }
1213
1214 /**
1215 * @brief Write 16-bit in the data register
1216 *
1217 * Register|BitsName
1218 * --------|--------
1219 * TX_DATA | DATA
1220 *
1221 * @param XQSPIx XQSPI instance
1222 * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1223 * @retval None
1224 */
1225 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1226 {
1227 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1228 }
1229
1230 /**
1231 * @brief Write 32-bit in the data register
1232 *
1233 * Register|BitsName
1234 * --------|--------
1235 * TX_DATA | DATA
1236 *
1237 * @param XQSPIx XQSPI instance
1238 * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1239 * @retval None
1240 */
1241 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1242 {
1243 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1244 }
1245
1246 /**
1247 * @brief Read 8 bits in the data register
1248 *
1249 * Register|BitsName
1250 * --------|--------
1251 * RX_DATA | DATA
1252 *
1253 * @param XQSPIx XQSPI instance
1254 * @retval Returned Value between: 0x00 ~ 0xFF
1255 */
1256 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1257 {
1258 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1259 }
1260
1261 /**
1262 * @brief Read 16 bits in the data register
1263 *
1264 * Register|BitsName
1265 * --------|--------
1266 * RX_DATA | DATA
1267 *
1268 * @param XQSPIx XQSPI instance
1269 * @retval Returned Value between: 0x00 ~ 0xFFFF
1270 */
1271 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1272 {
1273 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1274 }
1275
1276 /**
1277 * @brief Read 32 bits in the data register
1278 *
1279 * Register|BitsName
1280 * --------|--------
1281 * RX_DATA | DATA
1282 *
1283 * @param XQSPIx XQSPI instance
1284 * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1285 */
1286 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1287 {
1288 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1289 }
1290
1291 /**
1292 * @brief Set TX FIFO threshold level
1293 * @note FIFO maximum depth is 16 units.
1294 *
1295 * Register|BitsName
1296 * --------|--------
1297 * CTRL |TXWMARK
1298 *
1299 * @param XQSPIx XQSPI instance
1300 * @param threshold This parameter can be one of the following values:
1301 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1302 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1303 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1304 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1305 * @retval None
1306 */
1307 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1308 {
1309 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1310 }
1311
1312 /**
1313 * @brief Get TX FIFO threshold level
1314 * @note FIFO maximum depth is 16 units.
1315 *
1316 * Register|BitsName
1317 * --------|--------
1318 * CTRL |TXWMARK
1319 *
1320 * @param XQSPIx XQSPI instance
1321 * @retval Returned Value can be one of the following values:
1322 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1323 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1324 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1325 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1326 */
1327 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1328 {
1329 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1330 }
1331
1332 /**
1333 * @brief Set RX FIFO threshold level
1334 * @note FIFO maximum depth is 16 units.
1335 *
1336 * Register|BitsName
1337 * --------|--------
1338 * CTRL |RXWMARK
1339 *
1340 * @param XQSPIx XQSPI instance
1341 * @param threshold This parameter can be one of the following values:
1342 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1343 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1344 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1345 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1346 * @retval None
1347 */
1348 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1349 {
1350 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1351 }
1352
1353 /**
1354 * @brief Get RX FIFO threshold level
1355 * @note FIFO maximum depth is 16 units.
1356 *
1357 * Register|BitsName
1358 * --------|--------
1359 * CTRL |RXWMARK
1360 *
1361 * @param XQSPIx XQSPI instance
1362 * @retval Returned Value can be one of the following values:
1363 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1364 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1365 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1366 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1367 */
1368 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1369 {
1370 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1371 }
1372
1373 /**
1374 * @brief Enable dummy cycles
1375 *
1376 * Register|BitsName
1377 * --------|--------
1378 * CTRL |MWAITEN
1379 *
1380 * @param XQSPIx XQSPI instance
1381 * @retval None
1382 */
1383 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1384 {
1385 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1386 }
1387
1388 /**
1389 * @brief Disable dummy cycles
1390 *
1391 * Register|BitsName
1392 * --------|--------
1393 * CTRL |MWAITEN
1394 *
1395 * @param XQSPIx XQSPI instance
1396 * @retval None
1397 */
1398 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1399 {
1400 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1401 }
1402
1403 /**
1404 * @brief Check if dummy cycles is enabled
1405 *
1406 * Register|BitsName
1407 * --------|--------
1408 * CTRL |MWAITEN
1409 *
1410 * @param XQSPIx XQSPI instance
1411 * @retval State of bit (1 or 0).
1412 */
1413 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1414 {
1415 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1416 }
1417
1418 /**
1419 * @brief Enable DMA mode
1420 *
1421 * Register|BitsName
1422 * --------|--------
1423 * CTRL |DMA
1424 *
1425 * @param XQSPIx XQSPI instance
1426 * @retval None
1427 */
1428 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1429 {
1430 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1431 }
1432
1433 /**
1434 * @brief Disable DMA mode
1435 *
1436 * Register|BitsName
1437 * --------|--------
1438 * CTRL |DMA
1439 *
1440 * @param XQSPIx XQSPI instance
1441 * @retval None
1442 */
1443 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1444 {
1445 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1446 }
1447
1448 /**
1449 * @brief Check if DMA mode is enabled
1450 *
1451 * Register|BitsName
1452 * --------|--------
1453 * CTRL |DMA
1454 *
1455 * @param XQSPIx XQSPI instance
1456 * @retval State of bit (1 or 0).
1457 */
1458 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1459 {
1460 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1461 }
1462
1463 /**
1464 * @brief Set clock polarity
1465 * @note This bit should not be changed when communication is ongoing.
1466 *
1467 * Register|BitsName
1468 * --------|--------
1469 * CTRL |CPOL
1470 *
1471 * @param XQSPIx XQSPI instance
1472 * @param cpol This parameter can be one of the following values:
1473 * @arg @ref LL_XQSPI_SCPOL_LOW
1474 * @arg @ref LL_XQSPI_SCPOL_HIGH
1475 * @retval None
1476 */
1477 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1478 {
1479 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1480 }
1481
1482 /**
1483 * @brief Get clock polarity
1484 *
1485 * Register|BitsName
1486 * --------|--------
1487 * CTRL |CPOL
1488 *
1489 * @param XQSPIx XQSPI instance
1490 * @retval Returned Value can be one of the following values:
1491 * @arg @ref LL_XQSPI_SCPOL_LOW
1492 * @arg @ref LL_XQSPI_SCPOL_HIGH
1493 */
1494 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1495 {
1496 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1497 }
1498
1499 /**
1500 * @brief Set clock phase
1501 * @note This bit should not be changed when communication is ongoing.
1502 *
1503 * Register|BitsName
1504 * --------|--------
1505 * CTRL |CPHA
1506 *
1507 * @param XQSPIx XQSPI instance
1508 * @param cpha This parameter can be one of the following values:
1509 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1510 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1511 * @retval None
1512 */
1513 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1514 {
1515 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1516 }
1517
1518 /**
1519 * @brief Get clock phase
1520 *
1521 * Register|BitsName
1522 * --------|--------
1523 * CTRL |CPHA
1524 *
1525 * @param XQSPIx XQSPI instance
1526 * @retval Returned Value can be one of the following values:
1527 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1528 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1529 */
1530 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1531 {
1532 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1533 }
1534
1535 /**
1536 * @brief Set serial data order
1537 *
1538 * Register|BitsName
1539 * --------|--------
1540 * CTRL |MSB1ST
1541 *
1542 * @param XQSPIx XQSPI instance
1543 * @param order This parameter can be one of the following values:
1544 * @arg @ref LL_XQSPI_QSPI_LSB
1545 * @arg @ref LL_XQSPI_QSPI_MSB
1546 * @retval None
1547 */
1548 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1549 {
1550 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1551 }
1552
1553 /**
1554 * @brief Get serial data order
1555 *
1556 * Register|BitsName
1557 * --------|--------
1558 * CTRL |MSB1ST
1559 *
1560 * @param XQSPIx XQSPI instance
1561 * @retval Returned Value can be one of the following values:
1562 * @arg @ref LL_XQSPI_QSPI_LSB
1563 * @arg @ref LL_XQSPI_QSPI_MSB
1564 */
1565 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1566 {
1567 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1568 }
1569
1570 /**
1571 * @brief Enable continuous transfer mode
1572 *
1573 * Register|BitsName
1574 * --------|--------
1575 * CTRL |CONTXFER
1576 *
1577 * @param XQSPIx XQSPI instance
1578 * @retval None
1579 */
1580 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1581 {
1582 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1583 }
1584
1585 /**
1586 * @brief Disable continuous transfer mode
1587 *
1588 * Register|BitsName
1589 * --------|--------
1590 * CTRL |CONTXFER
1591 *
1592 * @param XQSPIx XQSPI instance
1593 * @retval None
1594 */
1595 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1596 {
1597 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1598 }
1599
1600 /**
1601 * @brief Check if continuous transfer mode is enabled
1602 *
1603 * Register|BitsName
1604 * --------|--------
1605 * CTRL |CONTXFER
1606 *
1607 * @param XQSPIx XQSPI instance
1608 * @retval State of bit (1 or 0).
1609 */
1610 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1611 {
1612 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1613 }
1614
1615 /**
1616 * @brief Enable continuous transfer extend mode
1617 *
1618 * Register|BitsName
1619 * --------|--------
1620 * AUX_CTRL|CONTXFERX
1621 *
1622 * @param XQSPIx XQSPI instance
1623 * @retval None
1624 */
1625 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1626 {
1627 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1628 }
1629
1630 /**
1631 * @brief Disable continuous transfer extend mode
1632 *
1633 * Register|BitsName
1634 * --------|--------
1635 * AUX_CTRL|CONTXFERX
1636 *
1637 * @param XQSPIx XQSPI instance
1638 * @retval None
1639 */
1640 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1641 {
1642 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1643 }
1644
1645 /**
1646 * @brief Check if continuous transfer extend mode is enabled
1647 *
1648 * Register|BitsName
1649 * --------|--------
1650 * AUX_CTRL|CONTXFERX
1651 *
1652 * @param XQSPIx XQSPI instance
1653 * @retval State of bit (1 or 0).
1654 */
1655 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1656 {
1657 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1658 }
1659
1660 /**
1661 * @brief Set data size
1662 * @note These bits should not be changed when communication is ongoing.
1663 *
1664 * Register|BitsName
1665 * --------|--------
1666 * AUX_CTRL|BITSIZE
1667 *
1668 * @param XQSPIx XQSPI instance
1669 * @param szie This parameter can be one of the following values:
1670 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1671 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1672 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1673 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1674 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1675 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1676 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1677 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1678 * @retval None
1679 */
1680 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1681 {
1682 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1683 }
1684
1685 /**
1686 * @brief Get data size
1687 *
1688 * Register|BitsName
1689 * --------|--------
1690 * AUX_CTRL|BITSIZE
1691 *
1692 * @param XQSPIx XQSPI instance
1693 * @retval Returned Value can be one of the following values:
1694 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1695 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1696 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1697 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1698 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1699 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1700 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1701 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1702 */
1703 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1704 {
1705 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1706 }
1707
1708 /**
1709 * @brief Enable inhibt data input to RX FIFO
1710 *
1711 * Register|BitsName
1712 * --------|--------
1713 * AUX_CTRL|INHIBITDIN
1714 *
1715 * @param XQSPIx XQSPI instance
1716 * @retval None
1717 */
1718 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1719 {
1720 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1721 }
1722
1723 /**
1724 * @brief Disable inhibt data input to RX FIFO
1725 *
1726 * Register|BitsName
1727 * --------|--------
1728 * AUX_CTRL|INHIBITDIN
1729 *
1730 * @param XQSPIx XQSPI instance
1731 * @retval None
1732 */
1733 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1734 {
1735 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1736 }
1737
1738 /**
1739 * @brief Check if inhibt data input to RX FIFO is enabled
1740 *
1741 * Register|BitsName
1742 * --------|--------
1743 * AUX_CTRL|INHIBITDIN
1744 *
1745 * @param XQSPIx XQSPI instance
1746 * @retval State of bit (1 or 0).
1747 */
1748 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1749 {
1750 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1751 }
1752
1753 /**
1754 * @brief Enable inhibt data output to TX FIFO
1755 *
1756 * Register|BitsName
1757 * --------|--------
1758 * AUX_CTRL|INHIBITDOUT
1759 *
1760 * @param XQSPIx XQSPI instance
1761 * @retval None
1762 */
1763 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1764 {
1765 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1766 }
1767
1768 /**
1769 * @brief Disable inhibt data output to TX FIFO
1770 *
1771 * Register|BitsName
1772 * --------|--------
1773 * AUX_CTRL|INHIBITDOUT
1774 *
1775 * @param XQSPIx XQSPI instance
1776 * @retval None
1777 */
1778 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1779 {
1780 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1781 }
1782
1783 /**
1784 * @brief Check if inhibt data input to TX FIFO is enabled
1785 *
1786 * Register|BitsName
1787 * --------|--------
1788 * AUX_CTRL|INHIBITDOUT
1789 *
1790 * @param XQSPIx XQSPI instance
1791 * @retval State of bit (1 or 0).
1792 */
1793 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1794 {
1795 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1796 }
1797
1798 /**
1799 * @brief Set frame format
1800 * @note These bits should not be changed when communication is ongoing.
1801 *
1802 * Register|BitsName
1803 * --------|--------
1804 * AUX_CTRL|QMODE
1805 *
1806 * @param XQSPIx XQSPI instance
1807 * @param format This parameter can be one of the following values:
1808 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1809 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1810 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1811 * @retval None
1812 */
1813 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1814 {
1815 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1816 }
1817
1818 /**
1819 * @brief Get frame format
1820 *
1821 * Register|BitsName
1822 * --------|--------
1823 * AUX_CTRL|QMODE
1824 *
1825 * @param XQSPIx XQSPI instance
1826 * @retval Returned Value can be one even value:
1827 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1828 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1829 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1830 */
1831 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1832 {
1833 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1834 }
1835
1836 /**
1837 * @brief Get QSPI status
1838 *
1839 * Register|BitsName
1840 * --------|--------
1841 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1842 *
1843 * @param XQSPIx XQSPI instance
1844 * @retval Returned Value can be one or combination of the following values:
1845 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1846 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1847 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1848 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1849 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1850 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1851 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1852 */
1853 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1854 {
1855 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1856 }
1857
1858 /**
1859 * @brief Check active flag
1860 *
1861 * Register|BitsName
1862 * --------|--------
1863 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1864 *
1865 * @param XQSPIx XQSPI instance
1866 * @param flag This parameter can be one of the following values:
1867 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1868 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1869 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1870 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1871 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1872 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1873 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1874 * @retval State of bit (1 or 0).
1875 */
1876 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1877 {
1878 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
1879 }
1880
1881 /**
1882 * @brief Enable slave select output
1883 *
1884 * Register|BitsName
1885 * --------|--------
1886 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1887 *
1888 * @param XQSPIx XQSPI instance
1889 * @param ssout This parameter can between: 0 ~ 0xFF
1890 * @retval None
1891 */
1892 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1893 {
1894 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1895 }
1896
1897 /**
1898 * @brief Disable slave select output
1899 *
1900 * Register|BitsName
1901 * --------|--------
1902 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1903 *
1904 * @param XQSPIx XQSPI instance
1905 * @param ssout This parameter can between: 0 ~ 0xFF
1906 * @retval None
1907 */
1908 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1909 {
1910 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1911 }
1912
1913 /**
1914 * @brief Set slave select output polarity
1915 *
1916 * Register|BitsName
1917 * --------|--------
1918 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
1919 *
1920 * @param XQSPIx XQSPI instance
1921 * @param sspol This parameter can between: 0 ~ 0xFF
1922 * @retval None
1923 */
1924 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
1925 {
1926 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
1927 }
1928
1929 /**
1930 * @brief Get slave select output polarity
1931 *
1932 * Register|BitsName
1933 * --------|--------
1934 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
1935 *
1936 * @param XQSPIx XQSPI instance
1937 * @retval Returned Value can between: 0 ~ 0xFF
1938 */
1939 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
1940 {
1941 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
1942 }
1943
1944 /**
1945 * @brief Get FIFO Transmission Level
1946 *
1947 * Register|BitsName
1948 * --------|--------
1949 * TX_FIFO_LVL | TXFIFOLVL
1950 *
1951 * @param XQSPIx XQSPI instance
1952 * @retval Returned Value can between: 0 ~ 16
1953 */
1954 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
1955 {
1956 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
1957 }
1958
1959 /**
1960 * @brief Get FIFO reception Level
1961 *
1962 * Register|BitsName
1963 * --------|--------
1964 * RX_FIFO_LVL | RXFIFOLVL
1965 *
1966 * @param XQSPIx XQSPI instance
1967 * @retval Returned Value can between: 0 ~ 16
1968 */
1969 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
1970 {
1971 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
1972 }
1973
1974 /**
1975 * @brief Enable interrupt
1976 * @note This bit controls the generation of an interrupt when an event occurs.
1977 *
1978 * Register|BitsName
1979 * --------|--------
1980 * INTEN |INT_EN
1981 *
1982 * @param XQSPIx XQSPI instance
1983 * @param mask This parameter can be one of the following values:
1984 * @arg @ref LL_XQSPI_QSPI_IM_DONE
1985 * @arg @ref LL_XQSPI_QSPI_IM_RFF
1986 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
1987 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
1988 * @arg @ref LL_XQSPI_QSPI_IM_TFE
1989 * @retval None
1990 */
1991 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
1992 {
1993 SET_BITS(XQSPIx->QSPI.INTEN, mask);
1994 }
1995
1996 /**
1997 * @brief Disable interrupt
1998 * @note This bit controls the generation of an interrupt when an event occurs.
1999 *
2000 * Register|BitsName
2001 * --------|--------
2002 * INTEN |INT_EN
2003 *
2004 * @param XQSPIx XQSPI instance
2005 * @param mask This parameter can be one of the following values:
2006 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2007 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2008 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2009 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2010 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2011 * @retval None
2012 */
2013 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2014 {
2015 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2016 }
2017
2018 /**
2019 * @brief Check if interrupt is enabled
2020 *
2021 * Register|BitsName
2022 * --------|--------
2023 * INTEN |INT_EN
2024 *
2025 * @param XQSPIx XQSPI instance
2026 * @param mask This parameter can be one of the following values:
2027 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2028 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2029 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2030 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2031 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2032 * @retval State of bit (1 or 0).
2033 */
2034 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2035 {
2036 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2037 }
2038
2039 /**
2040 * @brief Get XQSPI interrupt flags
2041 *
2042 * Register|BitsName
2043 * --------|--------
2044 * INTSTAT |INT_STAT
2045 *
2046 * @param XQSPIx XQSPI instance
2047 * @retval Returned Value can be one or combination of the following values:
2048 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2049 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2050 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2051 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2052 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2053 */
2054 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2055 {
2056 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2057 }
2058
2059 /**
2060 * @brief Check interrupt flag
2061 *
2062 * Register|BitsName
2063 * --------|--------
2064 * INTSTAT | XFER_DPULSE
2065 * INTSTAT | RX_FPULSE
2066 * INTSTAT | RX_WPULSE
2067 * INTSTAT | TX_WPULSE
2068 * INTSTAT | TX_EPULSE
2069 *
2070 * @param XQSPIx XQSPI instance
2071 * @param flag This parameter can be one of the following values:
2072 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2073 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2074 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2075 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2076 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2077 * @retval State of bit (1 or 0).
2078 */
2079 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2080 {
2081 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2082 }
2083
2084 /**
2085 * @brief Clear interrupt flag
2086 * @note Clearing interrupt flag is done by writting INTCLR register
2087 *
2088 * Register|BitsName
2089 * --------|--------
2090 * INTCLR |INT_CLR
2091 *
2092 * @param XQSPIx XQSPI instance
2093 * @param flag This parameter can be one of the following values:
2094 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2095 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2096 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2097 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2098 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2099 * @retval None
2100 */
2101 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2102 {
2103 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2104 }
2105
2106 /**
2107 * @brief Set master inter-transfer delay
2108 *
2109 * Register|BitsName
2110 * --------|--------
2111 * MSTR_IT_DELAY | MWAIT
2112 *
2113 * @param XQSPIx XQSPI instance
2114 * @param wait This parameter can between: 0 ~ 255
2115 * @retval None
2116 */
2117 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2118 {
2119 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2120 }
2121
2122 /**
2123 * @brief Get master inter-transfer delay
2124 *
2125 * Register|BitsName
2126 * --------|--------
2127 * MSTR_IT_DELAY | MWAIT
2128 *
2129 * @param XQSPIx XQSPI instance
2130 * @retval Returned Value can between: 0 ~ 255
2131 */
2132 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2133 {
2134 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2135 }
2136
2137 /**
2138 * @brief Enable QSPI
2139 * @note This bit should not be enable when XIP is ongoing.
2140 *
2141 * Register|BitsName
2142 * --------|--------
2143 * SPIEN |EN
2144 *
2145 * @param XQSPIx XQSPI instance
2146 * @retval None
2147 */
2148 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2149 {
2150 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2151 }
2152
2153 /**
2154 * @brief Disable QSPI
2155 *
2156 * Register|BitsName
2157 * --------|--------
2158 * SPIEN |EN
2159 *
2160 * @param XQSPIx XQSPI instance
2161 * @retval None
2162 */
2163 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2164 {
2165 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2166 }
2167
2168 /**
2169 * @brief Check if QSPI is enabled
2170 *
2171 * Register|BitsName
2172 * --------|--------
2173 * SPIEN |EN
2174 *
2175 * @param XQSPIx XQSPI instance
2176 * @retval State of bit (1 or 0).
2177 */
2178 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2179 {
2180 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2181 }
2182
2183 /**
2184 * @brief Set QSPI Flash write bits
2185 *
2186 * Register|BitsName
2187 * --------|--------
2188 * FLASH_WRITE |FLASH_WRITE
2189 *
2190 * @param XQSPIx XQSPI instance
2191 * @param bits This parameter can be one of the following values:
2192 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2193 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2194 * @retval None
2195 */
2196 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2197 {
2198 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2199 }
2200
2201 /**
2202 * @brief Get QSPI Flash write bits
2203 *
2204 * Register|BitsName
2205 * --------|--------
2206 * FLASH_WRITE |FLASH_WRITE
2207 *
2208 * @param XQSPIx XQSPI instance
2209 * @retval Returned Value can be one of the following values:
2210 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2211 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2212 */
2213 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2214 {
2215 //GR5515_C and future version.
2216 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2217 }
2218
2219 /**
2220 * @brief Set QSPI Present Bypass
2221 *
2222 * Register|BitsName
2223 * --------|--------
2224 * BYPASS |BYPASS
2225 *
2226 * @param XQSPIx XQSPI instance
2227 * @param bypass This parameter can be one of the following values:
2228 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2229 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2230 * @retval None
2231 */
2232 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2233 {
2234 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2235 }
2236
2237 /**
2238 * @brief Get QSPI Present Bypass
2239 *
2240 * Register|BitsName
2241 * --------|--------
2242 * BYPASS |BYPASS
2243 *
2244 * @param XQSPIx XQSPI instance
2245 * @retval Returned Value can be one of the following values:
2246 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2247 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2248 */
2249 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2250 {
2251 return READ_REG(XQSPIx->QSPI.BYPASS);
2252 }
2253
2254 /**
2255 * @brief Enable exflash power
2256 * @note This bit should not be changed when XIP is ongoing.
2257 *
2258 * Register|BitsName
2259 * --------|--------
2260 * PWR_RET01 | EFLASH_PAD_EN
2261 *
2262 * @retval None
2263 */
2264 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2265 {
2266 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2267 }
2268
2269 /**
2270 * @brief Disable exflash power
2271 * @note This bit should not be changed when XIP is ongoing.
2272 *
2273 * Register|BitsName
2274 * --------|--------
2275 * PWR_RET01 | EFLASH_PAD_EN
2276 *
2277 * @retval None
2278 */
2279 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2280 {
2281 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2282 }
2283
2284 /**
2285 * @brief Check if exflash power is enabled
2286 *
2287 * Register|BitsName
2288 * --------|--------
2289 * PWR_RET01 | EFLASH_PAD_EN
2290 *
2291 * @retval State of bit (1 or 0).
2292 */
2293 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2294 {
2295 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN) == (AON_PWR_REG01_EFLASH_PAD_EN));
2296 }
2297
2298 /**
2299 * @brief Set XQSPI serial clock
2300 *
2301 * Register|BitsName
2302 * --------|--------
2303 * PWR_RET01 | XF_SCK_CLK_SEL
2304 *
2305 * @param speed This parameter can be one of the following values:
2306 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2307 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2308 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2309 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2310 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2311 * @retval None
2312 */
2313 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2314 {
2315 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL, speed);
2316 }
2317
2318 /**
2319 * @brief Get XQSPI serial clock
2320 *
2321 * Register|BitsName
2322 * --------|--------
2323 * PWR_RET01 | XF_SCK_CLK_SEL
2324 *
2325 * @retval Returned Value can be one of the following values:
2326 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2327 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2328 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2329 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2330 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2331 */
2332 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2333 {
2334 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL));
2335 }
2336
2337 /**
2338 * @brief Enable cache data retention.
2339 * @note This bit should not be changed when XIP is ongoing..
2340 *
2341 * Register|BitsName
2342 * --------|--------
2343 * PWR_RET01 | XF_TAG_RET
2344 *
2345 * @retval None
2346 */
2347 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2348 {
2349 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2350 }
2351
2352 /**
2353 * @brief Disable cache data retention.
2354 * @note This bit should not be changed when XIP is ongoing.
2355 *
2356 * Register|BitsName
2357 * --------|--------
2358 * PWR_RET01 | XF_TAG_RET
2359 *
2360 * @retval None
2361 */
2362 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2363 {
2364 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2365 }
2366
2367 /**
2368 * @brief Check if tag memory retention is enabled
2369 *
2370 * Register|BitsName
2371 * --------|--------
2372 * PWR_RET01 | XF_TAG_RET
2373 *
2374 * @retval State of bit (1 or 0).
2375 */
2376 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2377 {
2378 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET) == (AON_PWR_REG01_XF_TAG_RET));
2379 }
2380
2381
2382
2383 /** @} */
2384
2385 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2386 * @{
2387 */
2388
2389 /**
2390 * @brief De-initialize XQSPI registers (Registers restored to their default values).
2391 * @param XQSPIx XQSPI instance
2392 * @retval An error_status_t enumeration value:
2393 * - SUCCESS: XQSPI registers are de-initialized
2394 * - ERROR: XQSPI registers are not de-initialized
2395 */
2396 error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2397
2398 /**
2399 * @brief Initialize XQSPI registers according to the specified
2400 * parameters in default.
2401 * @param XQSPIx XQSPI instance
2402 * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2403 * information for the specified XQPSI peripheral.
2404 * @retval An error_status_t enumeration value:
2405 * - SUCCESS: XQSPI registers are initialized according to default
2406 * - ERROR: Problem occurred during XQSPI Registers initialization
2407 */
2408 error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2409
2410 /**
2411 * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2412 * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2413 * whose fields will be set to default values.
2414 * @retval None
2415 */
2416 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2417
2418 /** @} */
2419
2420 /** @} */
2421
2422 #endif /* XQSPI */
2423
2424 #ifdef __cplusplus
2425 }
2426 #endif
2427
2428 #endif /* __GR55xx_LL_XQSPI_H__ */
2429
2430 /** @} */
2431
2432 /** @} */
2433
2434 /** @} */
ll_xqspi_set_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr55xx_ll_xqspi.h:1680
ll_xqspi_is_active_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_xqspi.h:1876
ll_xqspi_disable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr55xx_ll_xqspi.h:1075
ll_xqspi_is_enabled_cache
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr55xx_ll_xqspi.h:411
ll_xqspi_get_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:564
ll_xqspi_is_enabled_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr55xx_ll_xqspi.h:1610
ll_xqspi_set_xip_ss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr55xx_ll_xqspi.h:777
ll_xqspi_get_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr55xx_ll_xqspi.h:1565
ll_xqspi_is_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr55xx_ll_xqspi.h:2293
ll_xqspi_get_cache_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr55xx_ll_xqspi.h:659
ll_xqspi_is_enabled_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:1123
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_xqspi.h:101
ll_xqspi_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr55xx_ll_xqspi.h:2347
ll_xqspi_enable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr55xx_ll_xqspi.h:1428
ll_xqspi_qspi_transmit_data16
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1225
ll_xqspi_get_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr55xx_ll_xqspi.h:709
ll_xqspi_disable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr55xx_ll_xqspi.h:741
ll_xqspi_get_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr55xx_ll_xqspi.h:495
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate be used to configure the transmit and receive SCK clock.
Definition: gr55xx_ll_xqspi.h:111
ll_xqspi_get_xip_ss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr55xx_ll_xqspi.h:796
ll_xqspi_get_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:1494
ll_xqspi_disable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr55xx_ll_xqspi.h:2163
ll_xqspi_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr55xx_ll_xqspi.h:2264
ll_xqspi_disable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr55xx_ll_xqspi.h:2362
ll_xqspi_disable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1640
ll_xqspi_set_present_bypass
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
Set QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2232
ll_xqspi_set_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:1513
ll_xqspi_get_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr55xx_ll_xqspi.h:2054
ll_xqspi_get_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr55xx_ll_xqspi.h:904
_ll_xqspi_init_t::data_order
uint32_t data_order
Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:96
ll_xqspi_enable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr55xx_ll_xqspi.h:580
ll_xqspi_is_enabled_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr55xx_ll_xqspi.h:611
ll_xqspi_enable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr55xx_ll_xqspi.h:725
ll_xqspi_is_enabled_cache_flush
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr55xx_ll_xqspi.h:458
ll_xqspi_set_flash_write
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2196
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Specifies the cache mode in XIP mode.
Definition: gr55xx_ll_xqspi.h:81
ll_xqspi_disable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr55xx_ll_xqspi.h:596
ll_xqspi_get_xip_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr55xx_ll_xqspi.h:1107
ll_xqspi_enable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_xqspi.h:1991
ll_xqspi_set_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:549
ll_xqspi_is_enabled_xip_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr55xx_ll_xqspi.h:756
ll_xqspi_disable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1733
ll_xqspi_set_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr55xx_ll_xqspi.h:958
ll_xqspi_enable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1580
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_get_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1368
ll_xqspi_enable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr55xx_ll_xqspi.h:1060
ll_xqspi_init
error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_get_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2132
ll_xqspi_is_enabled_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1793
ll_xqspi_is_qspi_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_xqspi.h:2079
ll_xqspi_qspi_receive_data8
SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1256
ll_xqspi_get_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1045
ll_xqspi_is_enabled_qspi_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:2034
ll_xqspi_is_enabled_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr55xx_ll_xqspi.h:1458
ll_xqspi_is_enabled_xip
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr55xx_ll_xqspi.h:1091
ll_xqspi_get_req_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr55xx_ll_xqspi.h:1155
ll_xqspi_deinit
error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_enable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr55xx_ll_xqspi.h:2148
ll_xqspi_get_flash_write
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2213
ll_xqspi_disable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1398
ll_xqspi_set_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1307
ll_xqspi_get_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr55xx_ll_xqspi.h:1831
ll_xqspi_is_enabled_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr55xx_ll_xqspi.h:1413
ll_xqspi_enable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr55xx_ll_xqspi.h:1171
ll_xqspi_disable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1778
ll_xqspi_is_enabled_qspi
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr55xx_ll_xqspi.h:2178
ll_xqspi_set_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:815
ll_xqspi_clear_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr55xx_ll_xqspi.h:2101
ll_xqspi_get_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1939
ll_xqspi_qspi_transmit_data32
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1241
ll_xqspi_get_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2332
ll_xqspi_is_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr55xx_ll_xqspi.h:2376
ll_xqspi_disable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr55xx_ll_xqspi.h:2279
ll_xqspi_get_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:532
_ll_xqspi_init_t::mode
uint32_t mode
Specifies the work mode, XIP mode or QSPI mode.
Definition: gr55xx_ll_xqspi.h:78
ll_xqspi_set_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2313
ll_xqspi_disable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_xqspi.h:2013
ll_xqspi_disable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr55xx_ll_xqspi.h:1443
ll_xqspi_qspi_receive_data32
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1286
ll_xqspi_enable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1625
ll_xqspi_set_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:851
ll_xqspi_get_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:868
ll_xqspi_enable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr55xx_ll_xqspi.h:374
ll_xqspi_is_enabled_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1748
ll_xqspi_disable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr55xx_ll_xqspi.h:1187
ll_xqspi_qspi_receive_data16
SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1271
ll_xqspi_get_qspi_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr55xx_ll_xqspi.h:1853
ll_xqspi_get_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:832
ll_xqspi_set_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr55xx_ll_xqspi.h:887
ll_xqspi_get_present_bypass
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
Get QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2249
ll_xqspi_set_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr55xx_ll_xqspi.h:1813
ll_xqspi_set_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2117
ll_xqspi_is_enabled_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr55xx_ll_xqspi.h:1655
ll_xqspi_set_xip_endian
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr55xx_ll_xqspi.h:923
ll_xqspi_set_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr55xx_ll_xqspi.h:1548
ll_xqspi_enable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr55xx_ll_xqspi.h:1892
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr55xx_ll_xqspi.h:77
ll_xqspi_disable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr55xx_ll_xqspi.h:1908
ll_xqspi_set_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:514
ll_xqspi_enable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1763
ll_xqspi_disable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1595
ll_xqspi_set_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr55xx_ll_xqspi.h:477
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_xqspi.h:106
ll_xqspi_get_flag_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr55xx_ll_xqspi.h:1139
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Specifies the XQSPI read command in XIP mode.
Definition: gr55xx_ll_xqspi.h:86
ll_xqspi_get_cache_hitcount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr55xx_ll_xqspi.h:627
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_get_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr55xx_ll_xqspi.h:973
ll_xqspi_get_cache_misscount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr55xx_ll_xqspi.h:643
ll_xqspi_set_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:1477
ll_xqspi_get_qspi_tx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_xqspi.h:1954
ll_xqspi_set_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1030
ll_xqspi_get_qspi_rx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_xqspi.h:1969
ll_xqspi_enable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr55xx_ll_xqspi.h:427
ll_xqspi_qspi_transmit_data8
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1209
ll_xqspi_get_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:1530
ll_xqspi_enable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1383
ll_xqspi_set_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:994
ll_xqspi_disable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr55xx_ll_xqspi.h:443
ll_xqspi_set_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1924
ll_xqspi_enable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1718
ll_xqspi_set_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr55xx_ll_xqspi.h:688
ll_xqspi_get_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1013
ll_xqspi_get_xip_endian
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr55xx_ll_xqspi.h:940
ll_xqspi_disable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr55xx_ll_xqspi.h:393
ll_xqspi_get_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1327
ll_xqspi_get_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr55xx_ll_xqspi.h:1703
ll_xqspi_set_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1348
_ll_xqspi_init_t::data_size
uint32_t data_size
Specifies the XQSPI data width, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:91