gr55xx_ll_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (DMA)
63
64 /** @defgroup DMA_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init
77 {
78 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
79
80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
81
82 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory or form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t mode; /**< Specifies the Single block or Multi-block operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref ll_dma_set_mode(). */
98
99 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
100 This parameter can be a value of @ref DMA_LL_EC_SOURCE
101
102 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_increment_mode(). */
103
104 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
105 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
106
107 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_increment_mode(). */
108
109 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
110 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
111
112 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_width(). */
113
114 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
115 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_width(). */
118
119 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
120 The data unit is equal to the source buffer configuration set in src_data_width parameters.
121 This parameter must be a value between Min_Data = 0 and Max_Data = 0x1FF
122
123 This feature can be modified afterwards using unitary function @ref ll_dma_set_block_size(). */
124
125 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
126 This parameter can be a value of @ref DMA_LL_EC_PERIPH
127
128 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_peripheral(). */
129
130 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
131 This parameter can be a value of @ref DMA_LL_EC_PERIPH
132
133 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_peripheral(). */
134
135 uint32_t priority; /**< Specifies the channel priority level.
136 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref ll_dma_set_channel_priority_level(). */
139
140 } ll_dma_init_t;
141
142 /** @} */
143
144 /** @} */
145
146 /**
147 * @defgroup DMA_LL_MACRO Defines
148 * @{
149 */
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
153 * @{
154 */
155
156 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
157 * @{
158 */
159 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
160 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
161 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
162 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
163 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
164 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /**< DMA Channel 5 */
165 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /**< DMA Channel 6 */
166 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /**< DMA Channel 7 */
167 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all (used only for function @ref ll_dma_deinit(). */
168 /** @} */
169
170 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
171 * @{
172 */
173 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
174 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
175 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
176 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
177 /** @} */
178
179
180 /** @defgroup DMA_LL_EC_MODE Transfer mode
181 * @{
182 */
183 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U) /**< Single block */
184 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC /**< Multi-block: src address reload, dst address contiguous */
185 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST /**< Multi-block: src address contiguous, dst address reload */
186 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST) /**< Multi-block: src address reload, dst address reload */
187 /** @} */
188
189 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
190 * @{
191 */
192 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
193 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
194 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
195 /** @} */
196
197 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
198 * @{
199 */
200 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
201 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
202 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
203 /** @} */
204
205 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
206 * @{
207 */
208 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
209 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
210 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
211 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
212 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
213 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
214 /** @} */
215
216 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
217 * @{
218 */
219 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
220 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
221 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
222 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
223 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
224 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
225 /** @} */
226
227 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
228 * @{
229 */
230 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
231 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
232 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
233 /** @} */
234
235 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
236 * @{
237 */
238 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
239 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
240 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
241 /** @} */
242
243 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
244 * @{
245 */
246 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
247 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
248 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
249 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
250 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
251 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
252 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
253 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
254 /** @} */
255
256 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
257 * @{
258 */
259 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
260 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
261 /** @} */
262
263 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
264 * @{
265 */
266 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
267 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
268 /** @} */
269
270 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
271 * @{
272 */
273 #define LL_DMA_PERIPH_SPIM_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is SPIM TX */
274 #define LL_DMA_PERIPH_SPIM_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is SPIM RX */
275 #define LL_DMA_PERIPH_SPIS_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIS TX */
276 #define LL_DMA_PERIPH_SPIS_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIS RX */
277 #define LL_DMA_PERIPH_QSPI0_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is QSPI0 TX */
278 #define LL_DMA_PERIPH_QSPI0_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is QSPI0 RX */
279 #define LL_DMA_PERIPH_I2C0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is I2C0 TX */
280 #define LL_DMA_PERIPH_I2C0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is I2C0 RX */
281 #define LL_DMA_PERIPH_I2C1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2C1 TX */
282 #define LL_DMA_PERIPH_I2C1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2C1 RX */
283 #define LL_DMA_PERIPH_I2S_S_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2S_S TX */
284 #define LL_DMA_PERIPH_I2S_S_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2S_S RX */
285 #define LL_DMA_PERIPH_UART0_TX ((uint32_t)0x0000000AU) /**< DMA Peripheral type is UART0 TX */
286 #define LL_DMA_PERIPH_UART0_RX ((uint32_t)0x0000000BU) /**< DMA Peripheral type is UART0 RX */
287 #define LL_DMA_PERIPH_QSPI1_TX ((uint32_t)0x0000000CU) /**< DMA peripheral type is QSPI1 TX */
288 #define LL_DMA_PERIPH_QSPI1_RX ((uint32_t)0x0000000DU) /**< DMA peripheral type is QSPI1 RX */
289 #define LL_DMA_PERIPH_I2S_M_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is I2S_M TX */
290 #define LL_DMA_PERIPH_I2S_M_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is I2S_M RX */
291 #define LL_DMA_PERIPH_SNSADC ((uint32_t)0x0000000EU) /**< DMA peripheral type is SNSADC */
292 #define LL_DMA_PERIPH_MEM ((uint32_t)0x0000000FU) /**< DMA peripheral type is Memory */
293 /** @} */
294
295 /** @} */
296
297 /* Exported macro ------------------------------------------------------------*/
298 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
299 * @{
300 */
301
302 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
303 * @{
304 */
305
306 /**
307 * @brief Write a value in DMA register
308 * @param __instance__ DMA instance
309 * @param __REG__ Register to be written
310 * @param __VALUE__ Value to be written in the register
311 * @retval None
312 */
313 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
314
315 /**
316 * @brief Read a value in DMA register
317 * @param __instance__ DMA instance
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
322
323 /** @} */
324
325 /** @} */
326
327 /** @} */
328
329 /* Exported functions --------------------------------------------------------*/
330 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
331 * @{
332 */
333
334 /** @defgroup DMA_LL_EF_Configuration Configuration functions
335 * @{
336 */
337
338 /**
339 * @brief Enable DMA Module.
340 * @note This function is used to enable the DMA Module, which must be done before any
341 * channel activity can begin.
342 *
343 * Register|BitsName
344 * --------|--------
345 * CFG_REG | CFG_EN
346 *
347 * @param DMAx DMA instance.
348 * @retval None
349 */
350 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
351 {
352 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
353 }
354
355 /**
356 * @brief Disable DMA Module.
357 * @note If the ll_dma_disable() function is called while any dma channel is still active,
358 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
359 * still active until hardware has terminated all cativity on all channels, at which
360 * point the ll_dma_is_enable() function returns 0.
361 *
362 * Register|BitsName
363 * --------|--------
364 * CFG_REG | CFG_EN
365 *
366 * @param DMAx DMA instance.
367 * @retval None
368 */
369 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
370 {
371 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
372 }
373
374 /**
375 * @brief Check if DMA Module is enabled or disabled.
376 *
377 * Register|BitsName
378 * --------|--------
379 * CFG_REG | CFG_EN
380 *
381 * @param DMAx DMA instance.
382 * @retval State of bit (1 or 0).
383 */
384 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
385 {
386 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
387 }
388
389 /**
390 * @brief Enable DMA channel.
391 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
392 * is ignored and call ll_dma_disable_channel() function will always returns 0.
393 *
394 * Register|BitsName
395 * --------|--------
396 * CH_EN_REG | CH_EN_WE&CH_EN
397 *
398 * @param DMAx DMA instance.
399 * @param channel This parameter can be one of the following values:
400 * @arg @ref LL_DMA_CHANNEL_0
401 * @arg @ref LL_DMA_CHANNEL_1
402 * @arg @ref LL_DMA_CHANNEL_2
403 * @arg @ref LL_DMA_CHANNEL_3
404 * @arg @ref LL_DMA_CHANNEL_4
405 * @arg @ref LL_DMA_CHANNEL_5
406 * @arg @ref LL_DMA_CHANNEL_6
407 * @arg @ref LL_DMA_CHANNEL_7
408 * @retval None
409 */
410 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
411 {
412 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
413 }
414
415 /**
416 * @brief Disable DMA channel.
417 *
418 * Register|BitsName
419 * --------|--------
420 * CH_EN_REG | CH_EN_WE&CH_EN
421 *
422 * @param DMAx DMA instance.
423 * @param channel This parameter can be one of the following values:
424 * @arg @ref LL_DMA_CHANNEL_0
425 * @arg @ref LL_DMA_CHANNEL_1
426 * @arg @ref LL_DMA_CHANNEL_2
427 * @arg @ref LL_DMA_CHANNEL_3
428 * @arg @ref LL_DMA_CHANNEL_4
429 * @arg @ref LL_DMA_CHANNEL_5
430 * @arg @ref LL_DMA_CHANNEL_6
431 * @arg @ref LL_DMA_CHANNEL_7
432 * @retval None
433 */
434 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
435 {
436 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
437 }
438
439 /**
440 * @brief Check if DMA channel is enabled or disabled.
441 * @note Software can therefore poll this function to determine when channel is free
442 * for a new DMA transfer.
443 *
444 * Register|BitsName
445 * --------|--------
446 * CH_EN_REG | CH_EN_WE&CH_EN
447 *
448 * @param DMAx DMA instance.
449 * @param channel This parameter can be one of the following values:
450 * @arg @ref LL_DMA_CHANNEL_0
451 * @arg @ref LL_DMA_CHANNEL_1
452 * @arg @ref LL_DMA_CHANNEL_2
453 * @arg @ref LL_DMA_CHANNEL_3
454 * @arg @ref LL_DMA_CHANNEL_4
455 * @arg @ref LL_DMA_CHANNEL_5
456 * @arg @ref LL_DMA_CHANNEL_6
457 * @arg @ref LL_DMA_CHANNEL_7
458 * @retval State of bit (1 or 0).
459 */
460 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
461 {
462 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
463 }
464
465 /**
466 * @brief Suspend a DMA channel transfer.
467 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
468 * function is called. The function may be called after enabling the DMA channel.
469 *
470 * Register|BitsName
471 * --------|--------
472 * CFGL | CH_SUSP
473 *
474 * @param DMAx DMA instance.
475 * @param channel This parameter can be one of the following values:
476 * @arg @ref LL_DMA_CHANNEL_0
477 * @arg @ref LL_DMA_CHANNEL_1
478 * @arg @ref LL_DMA_CHANNEL_2
479 * @arg @ref LL_DMA_CHANNEL_3
480 * @arg @ref LL_DMA_CHANNEL_4
481 * @arg @ref LL_DMA_CHANNEL_5
482 * @arg @ref LL_DMA_CHANNEL_6
483 * @arg @ref LL_DMA_CHANNEL_7
484 * @retval None
485 */
486 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
487 {
488 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
489 }
490
491 /**
492 * @brief Resume a DMA channel.
493 * @note The function may be called after enabling the DMA channel.
494 *
495 * Register|BitsName
496 * --------|--------
497 * CFGL | CH_SUSP
498 *
499 * @param DMAx DMA instance.
500 * @param channel This parameter can be one of the following values:
501 * @arg @ref LL_DMA_CHANNEL_0
502 * @arg @ref LL_DMA_CHANNEL_1
503 * @arg @ref LL_DMA_CHANNEL_2
504 * @arg @ref LL_DMA_CHANNEL_3
505 * @arg @ref LL_DMA_CHANNEL_4
506 * @arg @ref LL_DMA_CHANNEL_5
507 * @arg @ref LL_DMA_CHANNEL_6
508 * @arg @ref LL_DMA_CHANNEL_7
509 * @retval None
510 */
511 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
512 {
513 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
514 }
515
516 /**
517 * @brief Check if DMA channel is suspended or resumed.
518 *
519 * Register|BitsName
520 * --------|--------
521 * CFGL | CH_SUSP
522 *
523 * @param DMAx DMA instance.
524 * @param channel This parameter can be one of the following values:
525 * @arg @ref LL_DMA_CHANNEL_0
526 * @arg @ref LL_DMA_CHANNEL_1
527 * @arg @ref LL_DMA_CHANNEL_2
528 * @arg @ref LL_DMA_CHANNEL_3
529 * @arg @ref LL_DMA_CHANNEL_4
530 * @arg @ref LL_DMA_CHANNEL_5
531 * @arg @ref LL_DMA_CHANNEL_6
532 * @arg @ref LL_DMA_CHANNEL_7
533 * @retval State of bit (1 or 0).
534 */
535 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
536 {
537 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
538 }
539
540 /**
541 * @brief Check if DMA channel FIFO is empty.
542 *
543 * Register|BitsName
544 * --------|--------
545 * CFGL | FIFO_EMPTY
546 *
547 * @param DMAx DMA instance.
548 * @param channel This parameter can be one of the following values:
549 * @arg @ref LL_DMA_CHANNEL_0
550 * @arg @ref LL_DMA_CHANNEL_1
551 * @arg @ref LL_DMA_CHANNEL_2
552 * @arg @ref LL_DMA_CHANNEL_3
553 * @arg @ref LL_DMA_CHANNEL_4
554 * @arg @ref LL_DMA_CHANNEL_5
555 * @arg @ref LL_DMA_CHANNEL_6
556 * @arg @ref LL_DMA_CHANNEL_7
557 * @retval State of bit (1 or 0).
558 */
559 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
560 {
561 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
562 }
563
564 /**
565 * @brief Configure all parameters link to DMA transfer.
566 *
567 * Register|BitsName
568 * --------|--------
569 * CCR | DIR
570 * CCR | MEM2MEM
571 * CCR | CIRC
572 * CCR | PINC
573 * CCR | MINC
574 * CCR | PSIZE
575 * CCR | MSIZE
576 * CCR | PL
577 *
578 * @param DMAx DMAx instance
579 * @param channel This parameter can be one of the following values:
580 * @arg @ref LL_DMA_CHANNEL_0
581 * @arg @ref LL_DMA_CHANNEL_1
582 * @arg @ref LL_DMA_CHANNEL_2
583 * @arg @ref LL_DMA_CHANNEL_3
584 * @arg @ref LL_DMA_CHANNEL_4
585 * @arg @ref LL_DMA_CHANNEL_5
586 * @arg @ref LL_DMA_CHANNEL_6
587 * @arg @ref LL_DMA_CHANNEL_7
588 * @param configuration This parameter must be a combination of all the following values:
589 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK or @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
590 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
591 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
592 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
593 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
594 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
595 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
596 * @retval None
597 */
598 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
599 {
600 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
601 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC,
602 configuration);
603 }
604
605 /**
606 * @brief Set Data transfer direction (read from peripheral or from memory).
607 *
608 * Register|BitsName
609 * --------|--------
610 * CTL_LO | TT_FC
611 *
612 * @param DMAx DMAx instance
613 * @param channel This parameter can be one of the following values:
614 * @arg @ref LL_DMA_CHANNEL_0
615 * @arg @ref LL_DMA_CHANNEL_1
616 * @arg @ref LL_DMA_CHANNEL_2
617 * @arg @ref LL_DMA_CHANNEL_3
618 * @arg @ref LL_DMA_CHANNEL_4
619 * @arg @ref LL_DMA_CHANNEL_5
620 * @arg @ref LL_DMA_CHANNEL_6
621 * @arg @ref LL_DMA_CHANNEL_7
622 * @param direction This parameter can be one of the following values:
623 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
625 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
626 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
627 * @retval None
628 */
629 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
630 {
631 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
632 }
633
634 /**
635 * @brief Get Data transfer direction (read from peripheral or from memory).
636 *
637 * Register|BitsName
638 * --------|--------
639 * CTL_LO | TT_FC
640 *
641 * @param DMAx DMAx instance
642 * @param channel This parameter can be one of the following values:
643 * @arg @ref LL_DMA_CHANNEL_0
644 * @arg @ref LL_DMA_CHANNEL_1
645 * @arg @ref LL_DMA_CHANNEL_2
646 * @arg @ref LL_DMA_CHANNEL_3
647 * @arg @ref LL_DMA_CHANNEL_4
648 * @arg @ref LL_DMA_CHANNEL_5
649 * @arg @ref LL_DMA_CHANNEL_6
650 * @arg @ref LL_DMA_CHANNEL_7
651 * @retval Returned value can be one of the following values:
652 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
653 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
654 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
655 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
656 */
657 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
658 {
659 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
660 }
661
662 /**
663 * @brief Set DMA mode Single block or Multi block.
664 * @note The circular buffer mode cannot be used if the memory-to-memory
665 * data transfer is configured on the selected Channel.
666 *
667 * Register|BitsName
668 * --------|--------
669 * CFG_LO | RELOAD_DST
670 *
671 * @param DMAx DMAx instance
672 * @param channel This parameter can be one of the following values:
673 * @arg @ref LL_DMA_CHANNEL_0
674 * @arg @ref LL_DMA_CHANNEL_1
675 * @arg @ref LL_DMA_CHANNEL_2
676 * @arg @ref LL_DMA_CHANNEL_3
677 * @arg @ref LL_DMA_CHANNEL_4
678 * @arg @ref LL_DMA_CHANNEL_5
679 * @arg @ref LL_DMA_CHANNEL_6
680 * @arg @ref LL_DMA_CHANNEL_7
681 * @param mode This parameter can be one of the following values:
682 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
683 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
684 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
685 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
686 * @retval None
687 */
688 __STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
689 {
690 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
691 }
692
693
694 /**
695 * @brief Get DMA mode circular or normal.
696 *
697 * Register|BitsName
698 * --------|--------
699 * CFG_LO | RELOAD_DST
700 *
701 * @param DMAx DMAx instance
702 * @param channel This parameter can be one of the following values:
703 * @arg @ref LL_DMA_CHANNEL_0
704 * @arg @ref LL_DMA_CHANNEL_1
705 * @arg @ref LL_DMA_CHANNEL_2
706 * @arg @ref LL_DMA_CHANNEL_3
707 * @arg @ref LL_DMA_CHANNEL_4
708 * @arg @ref LL_DMA_CHANNEL_5
709 * @arg @ref LL_DMA_CHANNEL_6
710 * @arg @ref LL_DMA_CHANNEL_7
711 * @retval Returned value can be one of the following values:
712 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
713 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
714 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
715 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
716 */
717 __STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
718 {
719 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
720 }
721
722 /**
723 * @brief Set Source increment mode.
724 *
725 * Register|BitsName
726 * --------|--------
727 * CTL_LO | SINC
728 *
729 * @param DMAx DMAx instance
730 * @param channel This parameter can be one of the following values:
731 * @arg @ref LL_DMA_CHANNEL_0
732 * @arg @ref LL_DMA_CHANNEL_1
733 * @arg @ref LL_DMA_CHANNEL_2
734 * @arg @ref LL_DMA_CHANNEL_3
735 * @arg @ref LL_DMA_CHANNEL_4
736 * @arg @ref LL_DMA_CHANNEL_5
737 * @arg @ref LL_DMA_CHANNEL_6
738 * @arg @ref LL_DMA_CHANNEL_7
739 * @param src_increment_mode This parameter can be one of the following values:
740 * @arg @ref LL_DMA_SRC_INCREMENT
741 * @arg @ref LL_DMA_SRC_DECREMENT
742 * @arg @ref LL_DMA_SRC_NO_CHANGE
743 * @retval None
744 */
745 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
746 {
747 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
748 }
749
750 /**
751 * @brief Get Source increment mode.
752 *
753 * Register|BitsName
754 * --------|--------
755 * CTL_LO | SINC
756 *
757 * @param DMAx DMAx instance
758 * @param channel This parameter can be one of the following values:
759 * @arg @ref LL_DMA_CHANNEL_0
760 * @arg @ref LL_DMA_CHANNEL_1
761 * @arg @ref LL_DMA_CHANNEL_2
762 * @arg @ref LL_DMA_CHANNEL_3
763 * @arg @ref LL_DMA_CHANNEL_4
764 * @arg @ref LL_DMA_CHANNEL_5
765 * @arg @ref LL_DMA_CHANNEL_6
766 * @arg @ref LL_DMA_CHANNEL_7
767 * @retval Returned value can be one of the following values:
768 * @arg @ref LL_DMA_SRC_INCREMENT
769 * @arg @ref LL_DMA_SRC_DECREMENT
770 * @arg @ref LL_DMA_SRC_NO_CHANGE
771 */
772 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
773 {
774 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
775 }
776
777 /**
778 * @brief Set Destination increment mode.
779 *
780 * Register|BitsName
781 * --------|--------
782 * CTL_LO | DINC
783 *
784 * @param DMAx DMAx instance
785 * @param channel This parameter can be one of the following values:
786 * @arg @ref LL_DMA_CHANNEL_0
787 * @arg @ref LL_DMA_CHANNEL_1
788 * @arg @ref LL_DMA_CHANNEL_2
789 * @arg @ref LL_DMA_CHANNEL_3
790 * @arg @ref LL_DMA_CHANNEL_4
791 * @arg @ref LL_DMA_CHANNEL_5
792 * @arg @ref LL_DMA_CHANNEL_6
793 * @arg @ref LL_DMA_CHANNEL_7
794 * @param dst_increment_mode This parameter can be one of the following values:
795 * @arg @ref LL_DMA_DST_INCREMENT
796 * @arg @ref LL_DMA_DST_DECREMENT
797 * @arg @ref LL_DMA_DST_NO_CHANGE
798 * @retval None
799 */
800 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
801 {
802 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
803 }
804
805 /**
806 * @brief Get Destination increment mode.
807 *
808 * Register|BitsName
809 * --------|--------
810 * CTL_LO | DINC
811 *
812 * @param DMAx DMAx instance
813 * @param channel This parameter can be one of the following values:
814 * @arg @ref LL_DMA_CHANNEL_0
815 * @arg @ref LL_DMA_CHANNEL_1
816 * @arg @ref LL_DMA_CHANNEL_2
817 * @arg @ref LL_DMA_CHANNEL_3
818 * @arg @ref LL_DMA_CHANNEL_4
819 * @arg @ref LL_DMA_CHANNEL_5
820 * @arg @ref LL_DMA_CHANNEL_6
821 * @arg @ref LL_DMA_CHANNEL_7
822 * @retval Returned value can be one of the following values:
823 * @arg @ref LL_DMA_DST_INCREMENT
824 * @arg @ref LL_DMA_DST_DECREMENT
825 * @arg @ref LL_DMA_DST_NO_CHANGE
826 */
827 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
828 {
829 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
830 }
831
832 /**
833 * @brief Set Source transfer width.
834 *
835 * Register|BitsName
836 * --------|--------
837 * CTL_LO | SRC_TR_WIDTH
838 *
839 * @param DMAx DMAx instance
840 * @param channel This parameter can be one of the following values:
841 * @arg @ref LL_DMA_CHANNEL_0
842 * @arg @ref LL_DMA_CHANNEL_1
843 * @arg @ref LL_DMA_CHANNEL_2
844 * @arg @ref LL_DMA_CHANNEL_3
845 * @arg @ref LL_DMA_CHANNEL_4
846 * @arg @ref LL_DMA_CHANNEL_5
847 * @arg @ref LL_DMA_CHANNEL_6
848 * @arg @ref LL_DMA_CHANNEL_7
849 * @param src_width This parameter can be one of the following values:
850 * @arg @ref LL_DMA_SDATAALIGN_BYTE
851 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
852 * @arg @ref LL_DMA_SDATAALIGN_WORD
853 * @retval None
854 */
855 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
856 {
857 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
858 }
859
860 /**
861 * @brief Get Source transfer width.
862 *
863 * Register|BitsName
864 * --------|--------
865 * CTL_LO | SRC_TR_WIDTH
866 *
867 * @param DMAx DMAx instance
868 * @param channel This parameter can be one of the following values:
869 * @arg @ref LL_DMA_CHANNEL_0
870 * @arg @ref LL_DMA_CHANNEL_1
871 * @arg @ref LL_DMA_CHANNEL_2
872 * @arg @ref LL_DMA_CHANNEL_3
873 * @arg @ref LL_DMA_CHANNEL_4
874 * @arg @ref LL_DMA_CHANNEL_5
875 * @arg @ref LL_DMA_CHANNEL_6
876 * @arg @ref LL_DMA_CHANNEL_7
877 * @retval Returned value can be one of the following values:
878 * @arg @ref LL_DMA_SDATAALIGN_BYTE
879 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
880 * @arg @ref LL_DMA_SDATAALIGN_WORD
881 */
882 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
883 {
884 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
885 }
886
887 /**
888 * @brief Set Destination transfer width.
889 *
890 * Register|BitsName
891 * --------|--------
892 * CTL_LO | DST_TR_WIDTH
893 *
894 * @param DMAx DMAx instance
895 * @param channel This parameter can be one of the following values:
896 * @arg @ref LL_DMA_CHANNEL_0
897 * @arg @ref LL_DMA_CHANNEL_1
898 * @arg @ref LL_DMA_CHANNEL_2
899 * @arg @ref LL_DMA_CHANNEL_3
900 * @arg @ref LL_DMA_CHANNEL_4
901 * @arg @ref LL_DMA_CHANNEL_5
902 * @arg @ref LL_DMA_CHANNEL_6
903 * @arg @ref LL_DMA_CHANNEL_7
904 * @param dst_width This parameter can be one of the following values:
905 * @arg @ref LL_DMA_DDATAALIGN_BYTE
906 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
907 * @arg @ref LL_DMA_DDATAALIGN_WORD
908 * @retval None
909 */
910 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
911 {
912 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
913 }
914
915 /**
916 * @brief Get Destination transfer width.
917 *
918 * Register|BitsName
919 * --------|--------
920 * CTL_LO | DST_TR_WIDTH
921 *
922 * @param DMAx DMAx instance
923 * @param channel This parameter can be one of the following values:
924 * @arg @ref LL_DMA_CHANNEL_0
925 * @arg @ref LL_DMA_CHANNEL_1
926 * @arg @ref LL_DMA_CHANNEL_2
927 * @arg @ref LL_DMA_CHANNEL_3
928 * @arg @ref LL_DMA_CHANNEL_4
929 * @arg @ref LL_DMA_CHANNEL_5
930 * @arg @ref LL_DMA_CHANNEL_6
931 * @arg @ref LL_DMA_CHANNEL_7
932 * @retval Returned value can be one of the following values:
933 * @arg @ref LL_DMA_DDATAALIGN_BYTE
934 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
935 * @arg @ref LL_DMA_DDATAALIGN_WORD
936 */
937 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
938 {
939 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
940 }
941
942 /**
943 * @brief Set Source Burst Transaction Length.
944 *
945 * Register|BitsName
946 * --------|--------
947 * CTL_LO | SRC_MSIZE
948 *
949 * @param DMAx DMAx instance
950 * @param channel This parameter can be one of the following values:
951 * @arg @ref LL_DMA_CHANNEL_0
952 * @arg @ref LL_DMA_CHANNEL_1
953 * @arg @ref LL_DMA_CHANNEL_2
954 * @arg @ref LL_DMA_CHANNEL_3
955 * @arg @ref LL_DMA_CHANNEL_4
956 * @arg @ref LL_DMA_CHANNEL_5
957 * @arg @ref LL_DMA_CHANNEL_6
958 * @arg @ref LL_DMA_CHANNEL_7
959 * @param burst_length This parameter can be one of the following values:
960 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
961 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
962 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
963 * @retval None
964 */
965 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
966 {
967 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
968 }
969
970 /**
971 * @brief Get Burst Transaction Length.
972 *
973 * Register|BitsName
974 * --------|--------
975 * CTL_LO | SRC_MSIZE
976 *
977 * @param DMAx DMAx instance
978 * @param channel This parameter can be one of the following values:
979 * @arg @ref LL_DMA_CHANNEL_0
980 * @arg @ref LL_DMA_CHANNEL_1
981 * @arg @ref LL_DMA_CHANNEL_2
982 * @arg @ref LL_DMA_CHANNEL_3
983 * @arg @ref LL_DMA_CHANNEL_4
984 * @arg @ref LL_DMA_CHANNEL_5
985 * @arg @ref LL_DMA_CHANNEL_6
986 * @arg @ref LL_DMA_CHANNEL_7
987 * @retval Returned value can be one of the following values:
988 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
989 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
990 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
991 */
992 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
993 {
994 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
995 }
996
997 /**
998 * @brief Set Destination Burst Transaction Length.
999 *
1000 * Register|BitsName
1001 * --------|--------
1002 * CTL_LO | DST_MSIZE
1003 *
1004 * @param DMAx DMAx instance
1005 * @param channel This parameter can be one of the following values:
1006 * @arg @ref LL_DMA_CHANNEL_0
1007 * @arg @ref LL_DMA_CHANNEL_1
1008 * @arg @ref LL_DMA_CHANNEL_2
1009 * @arg @ref LL_DMA_CHANNEL_3
1010 * @arg @ref LL_DMA_CHANNEL_4
1011 * @arg @ref LL_DMA_CHANNEL_5
1012 * @arg @ref LL_DMA_CHANNEL_6
1013 * @arg @ref LL_DMA_CHANNEL_7
1014 * @param burst_length This parameter can be one of the following values:
1015 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1016 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1017 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1018 * @retval None
1019 */
1020 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1021 {
1022 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1023 }
1024
1025 /**
1026 * @brief Get Destination Burst Transaction Length.
1027 *
1028 * Register|BitsName
1029 * --------|--------
1030 * CTL_LO | DST_MSIZE
1031 *
1032 * @param DMAx DMAx instance
1033 * @param channel This parameter can be one of the following values:
1034 * @arg @ref LL_DMA_CHANNEL_0
1035 * @arg @ref LL_DMA_CHANNEL_1
1036 * @arg @ref LL_DMA_CHANNEL_2
1037 * @arg @ref LL_DMA_CHANNEL_3
1038 * @arg @ref LL_DMA_CHANNEL_4
1039 * @arg @ref LL_DMA_CHANNEL_5
1040 * @arg @ref LL_DMA_CHANNEL_6
1041 * @arg @ref LL_DMA_CHANNEL_7
1042 * @retval Returned value can be one of the following values:
1043 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1044 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1045 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1046 */
1047 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
1048 {
1049 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1050 }
1051
1052 /**
1053 * @brief Set Channel priority level.
1054 *
1055 * Register|BitsName
1056 * --------|--------
1057 * CFG_LO | CH_PRIOR
1058 *
1059 * @param DMAx DMAx instance
1060 * @param channel This parameter can be one of the following values:
1061 * @arg @ref LL_DMA_CHANNEL_0
1062 * @arg @ref LL_DMA_CHANNEL_1
1063 * @arg @ref LL_DMA_CHANNEL_2
1064 * @arg @ref LL_DMA_CHANNEL_3
1065 * @arg @ref LL_DMA_CHANNEL_4
1066 * @arg @ref LL_DMA_CHANNEL_5
1067 * @arg @ref LL_DMA_CHANNEL_6
1068 * @arg @ref LL_DMA_CHANNEL_7
1069 * @param priority This parameter can be one of the following values:
1070 * @arg @ref LL_DMA_PRIORITY_0
1071 * @arg @ref LL_DMA_PRIORITY_1
1072 * @arg @ref LL_DMA_PRIORITY_2
1073 * @arg @ref LL_DMA_PRIORITY_3
1074 * @arg @ref LL_DMA_PRIORITY_4
1075 * @arg @ref LL_DMA_PRIORITY_5
1076 * @arg @ref LL_DMA_PRIORITY_6
1077 * @arg @ref LL_DMA_PRIORITY_7
1078 * @retval None
1079 */
1080 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
1081 {
1082 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1083 }
1084
1085 /**
1086 * @brief Get Channel priority level.
1087 *
1088 * Register|BitsName
1089 * --------|--------
1090 * CFG_LO | CH_PRIOR
1091 *
1092 * @param DMAx DMAx instance
1093 * @param channel This parameter can be one of the following values:
1094 * @arg @ref LL_DMA_CHANNEL_0
1095 * @arg @ref LL_DMA_CHANNEL_1
1096 * @arg @ref LL_DMA_CHANNEL_2
1097 * @arg @ref LL_DMA_CHANNEL_3
1098 * @arg @ref LL_DMA_CHANNEL_4
1099 * @arg @ref LL_DMA_CHANNEL_5
1100 * @arg @ref LL_DMA_CHANNEL_6
1101 * @arg @ref LL_DMA_CHANNEL_7
1102 * @retval Returned value can be one of the following values:
1103 * @arg @ref LL_DMA_PRIORITY_0
1104 * @arg @ref LL_DMA_PRIORITY_1
1105 * @arg @ref LL_DMA_PRIORITY_2
1106 * @arg @ref LL_DMA_PRIORITY_3
1107 * @arg @ref LL_DMA_PRIORITY_4
1108 * @arg @ref LL_DMA_PRIORITY_5
1109 * @arg @ref LL_DMA_PRIORITY_6
1110 * @arg @ref LL_DMA_PRIORITY_7
1111 */
1112 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
1113 {
1114 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1115 }
1116
1117 /**
1118 * @brief Set the block size of a transfer.
1119 * @note This action has no effect if channel is enabled.
1120 *
1121 * Register|BitsName
1122 * --------|--------
1123 * CTL_HI | BLOCK_TS
1124 *
1125 * @param DMAx DMAx instance
1126 * @param channel This parameter can be one of the following values:
1127 * @arg @ref LL_DMA_CHANNEL_0
1128 * @arg @ref LL_DMA_CHANNEL_1
1129 * @arg @ref LL_DMA_CHANNEL_2
1130 * @arg @ref LL_DMA_CHANNEL_3
1131 * @arg @ref LL_DMA_CHANNEL_4
1132 * @arg @ref LL_DMA_CHANNEL_5
1133 * @arg @ref LL_DMA_CHANNEL_6
1134 * @arg @ref LL_DMA_CHANNEL_7
1135 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1136 * @retval None
1137 */
1138 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1139 {
1140 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1141 }
1142
1143 /**
1144 * @brief Get the block size of a transfer.
1145 * @note Once the channel is enabled, the return value indicate the
1146 * remaining bytes to be transmitted.
1147 *
1148 * Register|BitsName
1149 * --------|--------
1150 * CTL_HI | BLOCK_TS
1151 *
1152 * @param DMAx DMAx instance
1153 * @param channel This parameter can be one of the following values:
1154 * @arg @ref LL_DMA_CHANNEL_0
1155 * @arg @ref LL_DMA_CHANNEL_1
1156 * @arg @ref LL_DMA_CHANNEL_2
1157 * @arg @ref LL_DMA_CHANNEL_3
1158 * @arg @ref LL_DMA_CHANNEL_4
1159 * @arg @ref LL_DMA_CHANNEL_5
1160 * @arg @ref LL_DMA_CHANNEL_6
1161 * @arg @ref LL_DMA_CHANNEL_7
1162 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1163 */
1164 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1165 {
1166 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1167 }
1168
1169 /**
1170 * @brief Configure the Source and Destination addresses.
1171 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1172 *
1173 * Register|BitsName
1174 * --------|--------
1175 * SAR | SAR
1176 * DAR | DAR
1177 * CTL_LO | TT_FC
1178 *
1179 * @param DMAx DMAx instance
1180 * @param channel This parameter can be one of the following values:
1181 * @arg @ref LL_DMA_CHANNEL_0
1182 * @arg @ref LL_DMA_CHANNEL_1
1183 * @arg @ref LL_DMA_CHANNEL_2
1184 * @arg @ref LL_DMA_CHANNEL_3
1185 * @arg @ref LL_DMA_CHANNEL_4
1186 * @arg @ref LL_DMA_CHANNEL_5
1187 * @arg @ref LL_DMA_CHANNEL_6
1188 * @arg @ref LL_DMA_CHANNEL_7
1189 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1190 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1191 * @param direction This parameter can be one of the following values:
1192 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1193 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1194 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1195 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1196 * @retval None
1197 */
1198 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx,
1199 uint32_t channel,
1200 uint32_t src_address,
1201 uint32_t dst_address,
1202 uint32_t direction)
1203 {
1204 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1205 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1206 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1207 }
1208
1209 /**
1210 * @brief Set the Source address.
1211 *
1212 * Register|BitsName
1213 * --------|--------
1214 * SAR | SAR
1215 *
1216 * @param DMAx DMAx instance
1217 * @param channel This parameter can be one of the following values:
1218 * @arg @ref LL_DMA_CHANNEL_0
1219 * @arg @ref LL_DMA_CHANNEL_1
1220 * @arg @ref LL_DMA_CHANNEL_2
1221 * @arg @ref LL_DMA_CHANNEL_3
1222 * @arg @ref LL_DMA_CHANNEL_4
1223 * @arg @ref LL_DMA_CHANNEL_5
1224 * @arg @ref LL_DMA_CHANNEL_6
1225 * @arg @ref LL_DMA_CHANNEL_7
1226 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1227 * @retval None
1228 */
1229 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1230 {
1231 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1232 }
1233
1234 /**
1235 * @brief Set the Destination address.
1236 *
1237 * Register|BitsName
1238 * --------|--------
1239 * DAR | DAR
1240 *
1241 * @param DMAx DMAx instance
1242 * @param channel This parameter can be one of the following values:
1243 * @arg @ref LL_DMA_CHANNEL_0
1244 * @arg @ref LL_DMA_CHANNEL_1
1245 * @arg @ref LL_DMA_CHANNEL_2
1246 * @arg @ref LL_DMA_CHANNEL_3
1247 * @arg @ref LL_DMA_CHANNEL_4
1248 * @arg @ref LL_DMA_CHANNEL_5
1249 * @arg @ref LL_DMA_CHANNEL_6
1250 * @arg @ref LL_DMA_CHANNEL_7
1251 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1252 * @retval None
1253 */
1254 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1255 {
1256 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1257 }
1258
1259 /**
1260 * @brief Get Source address.
1261 *
1262 * Register|BitsName
1263 * --------|--------
1264 * SAR | SAR
1265 *
1266 * @param DMAx DMAx instance
1267 * @param channel This parameter can be one of the following values:
1268 * @arg @ref LL_DMA_CHANNEL_0
1269 * @arg @ref LL_DMA_CHANNEL_1
1270 * @arg @ref LL_DMA_CHANNEL_2
1271 * @arg @ref LL_DMA_CHANNEL_3
1272 * @arg @ref LL_DMA_CHANNEL_4
1273 * @arg @ref LL_DMA_CHANNEL_5
1274 * @arg @ref LL_DMA_CHANNEL_6
1275 * @arg @ref LL_DMA_CHANNEL_7
1276 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1277 */
1278 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1279 {
1280 return READ_REG(DMAx->CHANNEL[channel].SAR);
1281 }
1282
1283 /**
1284 * @brief Get Destination address.
1285 *
1286 * Register|BitsName
1287 * --------|--------
1288 * DAR | DAR
1289 *
1290 * @param DMAx DMAx instance
1291 * @param channel This parameter can be one of the following values:
1292 * @arg @ref LL_DMA_CHANNEL_0
1293 * @arg @ref LL_DMA_CHANNEL_1
1294 * @arg @ref LL_DMA_CHANNEL_2
1295 * @arg @ref LL_DMA_CHANNEL_3
1296 * @arg @ref LL_DMA_CHANNEL_4
1297 * @arg @ref LL_DMA_CHANNEL_5
1298 * @arg @ref LL_DMA_CHANNEL_6
1299 * @arg @ref LL_DMA_CHANNEL_7
1300 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1301 */
1302 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1303 {
1304 return READ_REG(DMAx->CHANNEL[channel].DAR);
1305 }
1306
1307 /**
1308 * @brief Set the Memory to Memory Source address.
1309 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1310 *
1311 * Register|BitsName
1312 * --------|--------
1313 * SAR | SAR
1314 * CTL_LO | TT_FC
1315 * @param DMAx DMAx instance
1316 * @param channel This parameter can be one of the following values:
1317 * @arg @ref LL_DMA_CHANNEL_0
1318 * @arg @ref LL_DMA_CHANNEL_1
1319 * @arg @ref LL_DMA_CHANNEL_2
1320 * @arg @ref LL_DMA_CHANNEL_3
1321 * @arg @ref LL_DMA_CHANNEL_4
1322 * @arg @ref LL_DMA_CHANNEL_5
1323 * @arg @ref LL_DMA_CHANNEL_6
1324 * @arg @ref LL_DMA_CHANNEL_7
1325 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1326 * @retval None
1327 */
1328 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1329 {
1330 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1331 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1332 }
1333
1334 /**
1335 * @brief Set the Memory to Memory Destination address.
1336 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1337 *
1338 * Register|BitsName
1339 * --------|--------
1340 * DAR | DAR
1341 * CTL_LO | TT_FC
1342 *
1343 * @param DMAx DMAx instance
1344 * @param channel This parameter can be one of the following values:
1345 * @arg @ref LL_DMA_CHANNEL_0
1346 * @arg @ref LL_DMA_CHANNEL_1
1347 * @arg @ref LL_DMA_CHANNEL_2
1348 * @arg @ref LL_DMA_CHANNEL_3
1349 * @arg @ref LL_DMA_CHANNEL_4
1350 * @arg @ref LL_DMA_CHANNEL_5
1351 * @arg @ref LL_DMA_CHANNEL_6
1352 * @arg @ref LL_DMA_CHANNEL_7
1353 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1354 * @retval None
1355 */
1356 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1357 {
1358 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1359 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1360 }
1361
1362 /**
1363 * @brief Get the Memory to Memory Source address.
1364 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1365 *
1366 * Register|BitsName
1367 * --------|--------
1368 * SAR | SAR
1369 *
1370 * @param DMAx DMAx instance
1371 * @param channel This parameter can be one of the following values:
1372 * @arg @ref LL_DMA_CHANNEL_0
1373 * @arg @ref LL_DMA_CHANNEL_1
1374 * @arg @ref LL_DMA_CHANNEL_2
1375 * @arg @ref LL_DMA_CHANNEL_3
1376 * @arg @ref LL_DMA_CHANNEL_4
1377 * @arg @ref LL_DMA_CHANNEL_5
1378 * @arg @ref LL_DMA_CHANNEL_6
1379 * @arg @ref LL_DMA_CHANNEL_7
1380 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1381 */
1382 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1383 {
1384 return READ_REG(DMAx->CHANNEL[channel].SAR);
1385 }
1386
1387 /**
1388 * @brief Get the Memory to Memory Destination address.
1389 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1390 *
1391 * Register|BitsName
1392 * --------|--------
1393 * DAR | DAR
1394 *
1395 * @param DMAx DMAx instance
1396 * @param channel This parameter can be one of the following values:
1397 * @arg @ref LL_DMA_CHANNEL_0
1398 * @arg @ref LL_DMA_CHANNEL_1
1399 * @arg @ref LL_DMA_CHANNEL_2
1400 * @arg @ref LL_DMA_CHANNEL_3
1401 * @arg @ref LL_DMA_CHANNEL_4
1402 * @arg @ref LL_DMA_CHANNEL_5
1403 * @arg @ref LL_DMA_CHANNEL_6
1404 * @arg @ref LL_DMA_CHANNEL_7
1405 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1406 */
1407 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
1408 {
1409 return READ_REG(DMAx->CHANNEL[channel].DAR);
1410 }
1411
1412 /**
1413 * @brief Set source peripheral for DMA instance on Channel x.
1414 *
1415 * Register|BitsName
1416 * --------|--------
1417 * CFG_HI | SRC_PER
1418 *
1419 * @param DMAx DMAx instance
1420 * @param channel This parameter can be one of the following values:
1421 * @arg @ref LL_DMA_CHANNEL_0
1422 * @arg @ref LL_DMA_CHANNEL_1
1423 * @arg @ref LL_DMA_CHANNEL_2
1424 * @arg @ref LL_DMA_CHANNEL_3
1425 * @arg @ref LL_DMA_CHANNEL_4
1426 * @arg @ref LL_DMA_CHANNEL_5
1427 * @arg @ref LL_DMA_CHANNEL_6
1428 * @arg @ref LL_DMA_CHANNEL_7
1429 * @param peripheral This parameter can be one of the following values:
1430 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1431 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1432 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1433 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1434 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1435 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1436 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1437 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1438 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1439 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1440 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1441 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1442 * @arg @ref LL_DMA_PERIPH_UART0_TX
1443 * @arg @ref LL_DMA_PERIPH_UART0_RX
1444 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1445 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1446 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1447 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1448 * @arg @ref LL_DMA_PERIPH_SNSADC
1449 * @retval None
1450 */
1451 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1452 {
1453 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1454 }
1455
1456 /**
1457 * @brief Get source peripheral for DMA instance on Channel x.
1458 *
1459 * Register|BitsName
1460 * --------|--------
1461 * CFG_HI | SRC_PER
1462 *
1463 * @param DMAx DMAx instance
1464 * @param channel This parameter can be one of the following values:
1465 * @arg @ref LL_DMA_CHANNEL_0
1466 * @arg @ref LL_DMA_CHANNEL_1
1467 * @arg @ref LL_DMA_CHANNEL_2
1468 * @arg @ref LL_DMA_CHANNEL_3
1469 * @arg @ref LL_DMA_CHANNEL_4
1470 * @arg @ref LL_DMA_CHANNEL_5
1471 * @arg @ref LL_DMA_CHANNEL_6
1472 * @arg @ref LL_DMA_CHANNEL_7
1473 * @retval Returned value can be one of the following values:
1474 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1475 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1476 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1477 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1478 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1479 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1480 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1481 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1482 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1483 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1484 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1485 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1486 * @arg @ref LL_DMA_PERIPH_UART0_TX
1487 * @arg @ref LL_DMA_PERIPH_UART0_RX
1488 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1489 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1490 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1491 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1492 * @arg @ref LL_DMA_PERIPH_SNSADC
1493 */
1494 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
1495 {
1496 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1497 }
1498
1499 /**
1500 * @brief Set destination peripheral for DMA instance on Channel x.
1501 *
1502 * Register|BitsName
1503 * --------|--------
1504 * CFG_HI | DST_PER
1505 *
1506 * @param DMAx DMAx instance
1507 * @param channel This parameter can be one of the following values:
1508 * @arg @ref LL_DMA_CHANNEL_0
1509 * @arg @ref LL_DMA_CHANNEL_1
1510 * @arg @ref LL_DMA_CHANNEL_2
1511 * @arg @ref LL_DMA_CHANNEL_3
1512 * @arg @ref LL_DMA_CHANNEL_4
1513 * @arg @ref LL_DMA_CHANNEL_5
1514 * @arg @ref LL_DMA_CHANNEL_6
1515 * @arg @ref LL_DMA_CHANNEL_7
1516 * @param peripheral This parameter can be one of the following values:
1517 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1518 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1519 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1520 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1521 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1522 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1523 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1524 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1525 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1526 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1527 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1528 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1529 * @arg @ref LL_DMA_PERIPH_UART0_TX
1530 * @arg @ref LL_DMA_PERIPH_UART0_RX
1531 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1532 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1533 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1534 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1535 * @arg @ref LL_DMA_PERIPH_SNSADC
1536 * @retval None
1537 */
1538 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1539 {
1540 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1541 }
1542
1543 /**
1544 * @brief Get destination peripheral for DMA instance on Channel x.
1545 *
1546 * Register|BitsName
1547 * --------|--------
1548 * CFG_HI | DST_PER
1549 *
1550 * @param DMAx DMAx instance
1551 * @param channel This parameter can be one of the following values:
1552 * @arg @ref LL_DMA_CHANNEL_0
1553 * @arg @ref LL_DMA_CHANNEL_1
1554 * @arg @ref LL_DMA_CHANNEL_2
1555 * @arg @ref LL_DMA_CHANNEL_3
1556 * @arg @ref LL_DMA_CHANNEL_4
1557 * @arg @ref LL_DMA_CHANNEL_5
1558 * @arg @ref LL_DMA_CHANNEL_6
1559 * @arg @ref LL_DMA_CHANNEL_7
1560 * @retval Returned value can be one of the following values:
1561 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1562 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1563 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1564 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1565 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1566 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1567 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1568 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1569 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1570 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1571 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1572 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1573 * @arg @ref LL_DMA_PERIPH_UART0_TX
1574 * @arg @ref LL_DMA_PERIPH_UART0_RX
1575 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1576 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1577 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1578 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1579 * @arg @ref LL_DMA_PERIPH_SNSADC
1580 */
1581 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
1582 {
1583 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos;
1584 }
1585
1586 /**
1587 * @brief Set source and destination source handshaking interface.
1588 *
1589 * Register|BitsName
1590 * --------|--------
1591 * CFG_HI | DST_PER
1592 *
1593 * @param DMAx DMAx instance
1594 * @param channel This parameter can be one of the following values:
1595 * @arg @ref LL_DMA_CHANNEL_0
1596 * @arg @ref LL_DMA_CHANNEL_1
1597 * @arg @ref LL_DMA_CHANNEL_2
1598 * @arg @ref LL_DMA_CHANNEL_3
1599 * @arg @ref LL_DMA_CHANNEL_4
1600 * @arg @ref LL_DMA_CHANNEL_5
1601 * @arg @ref LL_DMA_CHANNEL_6
1602 * @arg @ref LL_DMA_CHANNEL_7
1603 * @param src_handshaking This parameter can be one of the following values:
1604 * @arg @ref LL_DMA_SHANDSHAKING_HW
1605 * @arg @ref LL_DMA_SHANDSHAKING_HW
1606 * @param dst_handshaking This parameter can be one of the following values:
1607 * @arg @ref LL_DMA_DHANDSHAKING_HW
1608 * @arg @ref LL_DMA_DHANDSHAKING_HW
1609 * @retval None
1610 */
1611 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
1612 {
1613 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1614 src_handshaking | dst_handshaking);
1615 }
1616
1617 /**
1618 * @brief Source Single Transaction Request.
1619 *
1620 * Register|BitsName
1621 * --------|--------
1622 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1623 * REQ_SRC | SRC_WE&SRC
1624 *
1625 * @param DMAx DMA instance.
1626 * @param channel This parameter can be one of the following values:
1627 * @arg @ref LL_DMA_CHANNEL_0
1628 * @arg @ref LL_DMA_CHANNEL_1
1629 * @arg @ref LL_DMA_CHANNEL_2
1630 * @arg @ref LL_DMA_CHANNEL_3
1631 * @arg @ref LL_DMA_CHANNEL_4
1632 * @arg @ref LL_DMA_CHANNEL_5
1633 * @arg @ref LL_DMA_CHANNEL_6
1634 * @arg @ref LL_DMA_CHANNEL_7
1635 * @retval None
1636 */
1637 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1638 {
1639 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1640 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1641 }
1642
1643 /**
1644 * @brief Source Burst Transaction Request.
1645 *
1646 * Register|BitsName
1647 * --------|--------
1648 * REQ_SRC | SRC_WE&SRC
1649 *
1650 * @param DMAx DMA instance.
1651 * @param channel This parameter can be one of the following values:
1652 * @arg @ref LL_DMA_CHANNEL_0
1653 * @arg @ref LL_DMA_CHANNEL_1
1654 * @arg @ref LL_DMA_CHANNEL_2
1655 * @arg @ref LL_DMA_CHANNEL_3
1656 * @arg @ref LL_DMA_CHANNEL_4
1657 * @arg @ref LL_DMA_CHANNEL_5
1658 * @arg @ref LL_DMA_CHANNEL_6
1659 * @arg @ref LL_DMA_CHANNEL_7
1660 * @retval None
1661 */
1662 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1663 {
1664 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1665 }
1666
1667 /**
1668 * @brief Source Last Single Transaction Request.
1669 *
1670 * Register|BitsName
1671 * --------|--------
1672 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1673 * LST_SRC | LST_SRC_WE&LST_SRC
1674 * REQ_SRC | SRC_WE&SRC
1675 *
1676 * @param DMAx DMA instance.
1677 * @param channel This parameter can be one of the following values:
1678 * @arg @ref LL_DMA_CHANNEL_0
1679 * @arg @ref LL_DMA_CHANNEL_1
1680 * @arg @ref LL_DMA_CHANNEL_2
1681 * @arg @ref LL_DMA_CHANNEL_3
1682 * @arg @ref LL_DMA_CHANNEL_4
1683 * @arg @ref LL_DMA_CHANNEL_5
1684 * @arg @ref LL_DMA_CHANNEL_6
1685 * @arg @ref LL_DMA_CHANNEL_7
1686 * @retval None
1687 */
1688 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1689 {
1690 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1691 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1692 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1693 }
1694
1695 /**
1696 * @brief Source Last Burst Transaction Request.
1697 *
1698 * Register|BitsName
1699 * --------|--------
1700 * LST_SRC | LST_SRC_WE&LST_SRC
1701 * REQ_SRC | SRC_WE&SRC
1702 *
1703 * @param DMAx DMA instance.
1704 * @param channel This parameter can be one of the following values:
1705 * @arg @ref LL_DMA_CHANNEL_0
1706 * @arg @ref LL_DMA_CHANNEL_1
1707 * @arg @ref LL_DMA_CHANNEL_2
1708 * @arg @ref LL_DMA_CHANNEL_3
1709 * @arg @ref LL_DMA_CHANNEL_4
1710 * @arg @ref LL_DMA_CHANNEL_5
1711 * @arg @ref LL_DMA_CHANNEL_6
1712 * @arg @ref LL_DMA_CHANNEL_7
1713 * @retval None
1714 */
1715 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1716 {
1717 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1718 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1719 }
1720
1721 /**
1722 * @brief Destination Single Transaction Request.
1723 *
1724 * Register|BitsName
1725 * --------|--------
1726 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1727 * REQ_DST | DST_WE&DST
1728 *
1729 * @param DMAx DMA instance.
1730 * @param channel This parameter can be one of the following values:
1731 * @arg @ref LL_DMA_CHANNEL_0
1732 * @arg @ref LL_DMA_CHANNEL_1
1733 * @arg @ref LL_DMA_CHANNEL_2
1734 * @arg @ref LL_DMA_CHANNEL_3
1735 * @arg @ref LL_DMA_CHANNEL_4
1736 * @arg @ref LL_DMA_CHANNEL_5
1737 * @arg @ref LL_DMA_CHANNEL_6
1738 * @arg @ref LL_DMA_CHANNEL_7
1739 * @retval None
1740 */
1741 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1742 {
1743 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1744 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1745 }
1746
1747 /**
1748 * @brief Destination Burst Transaction Request.
1749 *
1750 * Register|BitsName
1751 * --------|--------
1752 * REQ_DST | DST_WE&DST
1753 *
1754 * @param DMAx DMA instance.
1755 * @param channel This parameter can be one of the following values:
1756 * @arg @ref LL_DMA_CHANNEL_0
1757 * @arg @ref LL_DMA_CHANNEL_1
1758 * @arg @ref LL_DMA_CHANNEL_2
1759 * @arg @ref LL_DMA_CHANNEL_3
1760 * @arg @ref LL_DMA_CHANNEL_4
1761 * @arg @ref LL_DMA_CHANNEL_5
1762 * @arg @ref LL_DMA_CHANNEL_6
1763 * @arg @ref LL_DMA_CHANNEL_7
1764 * @retval None
1765 */
1766 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1767 {
1768 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1769 }
1770
1771 /**
1772 * @brief Destination Last Single Transaction Request.
1773 *
1774 * Register|BitsName
1775 * --------|--------
1776 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1777 * LST_DST | LST_DST_WE&LST_DST
1778 * REQ_DST | DST_WE&DST
1779 *
1780 * @param DMAx DMA instance.
1781 * @param channel This parameter can be one of the following values:
1782 * @arg @ref LL_DMA_CHANNEL_0
1783 * @arg @ref LL_DMA_CHANNEL_1
1784 * @arg @ref LL_DMA_CHANNEL_2
1785 * @arg @ref LL_DMA_CHANNEL_3
1786 * @arg @ref LL_DMA_CHANNEL_4
1787 * @arg @ref LL_DMA_CHANNEL_5
1788 * @arg @ref LL_DMA_CHANNEL_6
1789 * @arg @ref LL_DMA_CHANNEL_7
1790 * @retval None
1791 */
1792 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1793 {
1794 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1795 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1796 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1797 }
1798
1799 /**
1800 * @brief Destination Last Burst Transaction Request.
1801 *
1802 * Register|BitsName
1803 * --------|--------
1804 * LST_DST | LST_DST_WE&LST_DST
1805 * REQ_DST | DST_WE&DST
1806 *
1807 * @param DMAx DMA instance.
1808 * @param channel This parameter can be one of the following values:
1809 * @arg @ref LL_DMA_CHANNEL_0
1810 * @arg @ref LL_DMA_CHANNEL_1
1811 * @arg @ref LL_DMA_CHANNEL_2
1812 * @arg @ref LL_DMA_CHANNEL_3
1813 * @arg @ref LL_DMA_CHANNEL_4
1814 * @arg @ref LL_DMA_CHANNEL_5
1815 * @arg @ref LL_DMA_CHANNEL_6
1816 * @arg @ref LL_DMA_CHANNEL_7
1817 * @retval None
1818 */
1819 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1820 {
1821 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1822 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1823 }
1824
1825 /** @} */
1826
1827 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Get DMA Module global transfer complete interrupt status.
1833 *
1834 * Register|BitsName
1835 * --------|--------
1836 * STATUS_INT | TFR
1837 *
1838 * @param DMAx DMAx instance
1839 * @retval State of bit (1 or 0).
1840 */
1841 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
1842 {
1843 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1844 }
1845
1846 /**
1847 * @brief Get DMA Module global block complete interrupt status.
1848 *
1849 * Register|BitsName
1850 * --------|--------
1851 * STATUS_INT | BLOCK
1852 *
1853 * @param DMAx DMAx instance
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
1857 {
1858 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1859 }
1860
1861 /**
1862 * @brief Get DMA Module global source transaction complete interrupt status.
1863 *
1864 * Register|BitsName
1865 * --------|--------
1866 * STATUS_INT | SRCT
1867 *
1868 * @param DMAx DMAx instance
1869 * @retval State of bit (1 or 0).
1870 */
1871 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
1872 {
1873 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1874 }
1875
1876 /**
1877 * @brief Get DMA Module global destination transaction complete interrupt status.
1878 *
1879 * Register|BitsName
1880 * --------|--------
1881 * STATUS_INT | DSTT
1882 *
1883 * @param DMAx DMAx instance
1884 * @retval State of bit (1 or 0).
1885 */
1886 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
1887 {
1888 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1889 }
1890
1891 /**
1892 * @brief Get DMA Module global error interrupt status.
1893 *
1894 * Register|BitsName
1895 * --------|--------
1896 * STATUS_INT | ERR
1897 *
1898 * @param DMAx DMAx instance
1899 * @retval State of bit (1 or 0).
1900 */
1901 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
1902 {
1903 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1904 }
1905
1906 /**
1907 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
1908 *
1909 * Register|BitsName
1910 * --------|--------
1911 * RAW_TFR | RAW
1912 *
1913 * @param DMAx DMAx instance
1914 * @param channel This parameter can be one of the following values:
1915 * @arg @ref LL_DMA_CHANNEL_0
1916 * @arg @ref LL_DMA_CHANNEL_1
1917 * @arg @ref LL_DMA_CHANNEL_2
1918 * @arg @ref LL_DMA_CHANNEL_3
1919 * @arg @ref LL_DMA_CHANNEL_4
1920 * @arg @ref LL_DMA_CHANNEL_5
1921 * @arg @ref LL_DMA_CHANNEL_6
1922 * @arg @ref LL_DMA_CHANNEL_7
1923 * @retval State of bit (1 or 0).
1924 */
1925 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
1926 {
1927 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
1928 }
1929
1930 /**
1931 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
1932 *
1933 * Register|BitsName
1934 * --------|--------
1935 * RAW_BLK | RAW
1936 *
1937 * @param DMAx DMAx instance
1938 * @param channel This parameter can be one of the following values:
1939 * @arg @ref LL_DMA_CHANNEL_0
1940 * @arg @ref LL_DMA_CHANNEL_1
1941 * @arg @ref LL_DMA_CHANNEL_2
1942 * @arg @ref LL_DMA_CHANNEL_3
1943 * @arg @ref LL_DMA_CHANNEL_4
1944 * @arg @ref LL_DMA_CHANNEL_5
1945 * @arg @ref LL_DMA_CHANNEL_6
1946 * @arg @ref LL_DMA_CHANNEL_7
1947 * @retval State of bit (1 or 0).
1948 */
1949 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
1950 {
1951 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
1952 }
1953
1954 /**
1955 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
1956 *
1957 * Register|BitsName
1958 * --------|--------
1959 * RAW_SRC_TRN | RAW
1960 *
1961 * @param DMAx DMAx instance
1962 * @param channel This parameter can be one of the following values:
1963 * @arg @ref LL_DMA_CHANNEL_0
1964 * @arg @ref LL_DMA_CHANNEL_1
1965 * @arg @ref LL_DMA_CHANNEL_2
1966 * @arg @ref LL_DMA_CHANNEL_3
1967 * @arg @ref LL_DMA_CHANNEL_4
1968 * @arg @ref LL_DMA_CHANNEL_5
1969 * @arg @ref LL_DMA_CHANNEL_6
1970 * @arg @ref LL_DMA_CHANNEL_7
1971 * @retval State of bit (1 or 0).
1972 */
1973 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
1974 {
1975 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
1976 }
1977
1978 /**
1979 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
1980 *
1981 * Register|BitsName
1982 * --------|--------
1983 * RAW_DST_TRN | RAW
1984 *
1985 * @param DMAx DMAx instance
1986 * @param channel This parameter can be one of the following values:
1987 * @arg @ref LL_DMA_CHANNEL_0
1988 * @arg @ref LL_DMA_CHANNEL_1
1989 * @arg @ref LL_DMA_CHANNEL_2
1990 * @arg @ref LL_DMA_CHANNEL_3
1991 * @arg @ref LL_DMA_CHANNEL_4
1992 * @arg @ref LL_DMA_CHANNEL_5
1993 * @arg @ref LL_DMA_CHANNEL_6
1994 * @arg @ref LL_DMA_CHANNEL_7
1995 * @retval State of bit (1 or 0).
1996 */
1997 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
1998 {
1999 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2000 }
2001
2002 /**
2003 * @brief Indicate the Raw Status of IntErr Interrupt flag.
2004 *
2005 * Register|BitsName
2006 * --------|--------
2007 * RAW_ERR | RAW
2008 *
2009 * @param DMAx DMAx instance
2010 * @param channel This parameter can be one of the following values:
2011 * @arg @ref LL_DMA_CHANNEL_0
2012 * @arg @ref LL_DMA_CHANNEL_1
2013 * @arg @ref LL_DMA_CHANNEL_2
2014 * @arg @ref LL_DMA_CHANNEL_3
2015 * @arg @ref LL_DMA_CHANNEL_4
2016 * @arg @ref LL_DMA_CHANNEL_5
2017 * @arg @ref LL_DMA_CHANNEL_6
2018 * @arg @ref LL_DMA_CHANNEL_7
2019 * @retval State of bit (1 or 0).
2020 */
2021 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
2022 {
2023 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2024 }
2025
2026 /**
2027 * @brief Indicate the status of DMA Channel transfer complete flag.
2028 *
2029 * Register|BitsName
2030 * --------|--------
2031 * STAT_TFR | STATUS
2032 *
2033 * @param DMAx DMAx instance
2034 * @param channel This parameter can be one of the following values:
2035 * @arg @ref LL_DMA_CHANNEL_0
2036 * @arg @ref LL_DMA_CHANNEL_1
2037 * @arg @ref LL_DMA_CHANNEL_2
2038 * @arg @ref LL_DMA_CHANNEL_3
2039 * @arg @ref LL_DMA_CHANNEL_4
2040 * @arg @ref LL_DMA_CHANNEL_5
2041 * @arg @ref LL_DMA_CHANNEL_6
2042 * @arg @ref LL_DMA_CHANNEL_7
2043 * @retval State of bit (1 or 0).
2044 */
2045 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2046 {
2047 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2048 }
2049
2050 /**
2051 * @brief Indicate the status of Channel 0 transfer complete flag.
2052 *
2053 * Register|BitsName
2054 * --------|--------
2055 * STAT_TFR | STATUS
2056 *
2057 * @param DMAx DMAx instance
2058 * @retval State of bit (1 or 0).
2059 */
2060 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
2061 {
2062 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2063 }
2064
2065 /**
2066 * @brief Indicate the status of Channel 1 transfer complete flag.
2067 *
2068 * Register|BitsName
2069 * --------|--------
2070 * STAT_TFR | STATUS
2071 *
2072 * @param DMAx DMAx instance
2073 * @retval State of bit (1 or 0).
2074 */
2075 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
2076 {
2077 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2078 }
2079
2080 /**
2081 * @brief Indicate the status of Channel 2 transfer complete flag.
2082 *
2083 * Register|BitsName
2084 * --------|--------
2085 * STAT_TFR | STATUS
2086 *
2087 * @param DMAx DMAx instance
2088 * @retval State of bit (1 or 0).
2089 */
2090 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
2091 {
2092 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2093 }
2094
2095 /**
2096 * @brief Indicate the status of Channel 3 transfer complete flag.
2097 *
2098 * Register|BitsName
2099 * --------|--------
2100 * STAT_TFR | STATUS
2101 *
2102 * @param DMAx DMAx instance
2103 * @retval State of bit (1 or 0).
2104 */
2105 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
2106 {
2107 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2108 }
2109
2110 /**
2111 * @brief Indicate the status of Channel 4 transfer complete flag.
2112 *
2113 * Register|BitsName
2114 * --------|--------
2115 * STAT_TFR | STATUS
2116 *
2117 * @param DMAx DMAx instance
2118 * @retval State of bit (1 or 0).
2119 */
2120 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
2121 {
2122 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2123 }
2124
2125 /**
2126 * @brief Indicate the status of Channel 5 transfer complete flag.
2127 *
2128 * Register|BitsName
2129 * --------|--------
2130 * STAT_TFR | STATUS
2131 *
2132 * @param DMAx DMAx instance
2133 * @retval State of bit (1 or 0).
2134 */
2135 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
2136 {
2137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
2138 }
2139
2140 /**
2141 * @brief Indicate the status of Channel 6 transfer complete flag.
2142 *
2143 * Register|BitsName
2144 * --------|--------
2145 * STAT_TFR | STATUS
2146 *
2147 * @param DMAx DMAx instance
2148 * @retval State of bit (1 or 0).
2149 */
2150 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
2151 {
2152 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
2153 }
2154
2155 /**
2156 * @brief Indicate the status of Channel 7 transfer complete flag.
2157 *
2158 * Register|BitsName
2159 * --------|--------
2160 * STAT_TFR | STATUS
2161 *
2162 * @param DMAx DMAx instance
2163 * @retval State of bit (1 or 0).
2164 */
2165 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
2166 {
2167 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
2168 }
2169
2170 /**
2171 * @brief Indicate the status of DMA Channel block complete flag.
2172 *
2173 * Register|BitsName
2174 * --------|--------
2175 * STAT_BLK | STATUS
2176 *
2177 * @param DMAx DMAx instance
2178 * @param channel This parameter can be one of the following values:
2179 * @arg @ref LL_DMA_CHANNEL_0
2180 * @arg @ref LL_DMA_CHANNEL_1
2181 * @arg @ref LL_DMA_CHANNEL_2
2182 * @arg @ref LL_DMA_CHANNEL_3
2183 * @arg @ref LL_DMA_CHANNEL_4
2184 * @arg @ref LL_DMA_CHANNEL_5
2185 * @arg @ref LL_DMA_CHANNEL_6
2186 * @arg @ref LL_DMA_CHANNEL_7
2187 * @retval State of bit (1 or 0).
2188 */
2189 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2190 {
2191 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2192 }
2193
2194 /**
2195 * @brief Indicate the status of Channel 0 block complete flag.
2196 *
2197 * Register|BitsName
2198 * --------|--------
2199 * STAT_BLK | STATUS
2200 *
2201 * @param DMAx DMAx instance
2202 * @retval State of bit (1 or 0).
2203 */
2204 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
2205 {
2206 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2207 }
2208
2209 /**
2210 * @brief Indicate the status of Channel 1 block complete flag.
2211 *
2212 * Register|BitsName
2213 * --------|--------
2214 * STAT_BLK | STATUS
2215 *
2216 * @param DMAx DMAx instance
2217 * @retval State of bit (1 or 0).
2218 */
2219 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
2220 {
2221 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2222 }
2223
2224 /**
2225 * @brief Indicate the status of Channel 2 block complete flag.
2226 *
2227 * Register|BitsName
2228 * --------|--------
2229 * STAT_BLK | STATUS
2230 *
2231 * @param DMAx DMAx instance
2232 * @retval State of bit (1 or 0).
2233 */
2234 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
2235 {
2236 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2237 }
2238
2239 /**
2240 * @brief Indicate the status of Channel 3 block complete flag.
2241 *
2242 * Register|BitsName
2243 * --------|--------
2244 * STAT_BLK | STATUS
2245 *
2246 * @param DMAx DMAx instance
2247 * @retval State of bit (1 or 0).
2248 */
2249 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
2250 {
2251 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2252 }
2253
2254 /**
2255 * @brief Indicate the status of Channel 4 block complete flag.
2256 *
2257 * Register|BitsName
2258 * --------|--------
2259 * STAT_BLK | STATUS
2260 *
2261 * @param DMAx DMAx instance
2262 * @retval State of bit (1 or 0).
2263 */
2264 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
2265 {
2266 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2267 }
2268
2269 /**
2270 * @brief Indicate the status of Channel 5 block complete flag.
2271 *
2272 * Register|BitsName
2273 * --------|--------
2274 * STAT_BLK | STATUS
2275 *
2276 * @param DMAx DMAx instance
2277 * @retval State of bit (1 or 0).
2278 */
2279 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
2280 {
2281 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
2282 }
2283
2284 /**
2285 * @brief Indicate the status of Channel 6 block complete flag.
2286 *
2287 * Register|BitsName
2288 * --------|--------
2289 * STAT_BLK | STATUS
2290 *
2291 * @param DMAx DMAx instance
2292 * @retval State of bit (1 or 0).
2293 */
2294 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
2295 {
2296 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
2297 }
2298
2299 /**
2300 * @brief Indicate the status of Channel 7 block complete flag.
2301 *
2302 * Register|BitsName
2303 * --------|--------
2304 * STAT_BLK | STATUS
2305 *
2306 * @param DMAx DMAx instance
2307 * @retval State of bit (1 or 0).
2308 */
2309 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
2310 {
2311 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
2312 }
2313
2314 /**
2315 * @brief Indicate the status of DMA Channel source transaction complete flag.
2316 *
2317 * Register|BitsName
2318 * --------|--------
2319 * STAT_SRC_TRN | STATUS
2320 *
2321 * @param DMAx DMAx instance
2322 * @param channel This parameter can be one of the following values:
2323 * @arg @ref LL_DMA_CHANNEL_0
2324 * @arg @ref LL_DMA_CHANNEL_1
2325 * @arg @ref LL_DMA_CHANNEL_2
2326 * @arg @ref LL_DMA_CHANNEL_3
2327 * @arg @ref LL_DMA_CHANNEL_4
2328 * @arg @ref LL_DMA_CHANNEL_5
2329 * @arg @ref LL_DMA_CHANNEL_6
2330 * @arg @ref LL_DMA_CHANNEL_7
2331 * @retval State of bit (1 or 0).
2332 */
2333 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2334 {
2335 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2336 }
2337
2338 /**
2339 * @brief Indicate the status of Channel 0 source transaction complete flag.
2340 *
2341 * Register|BitsName
2342 * --------|--------
2343 * STAT_SRC_TRN | STATUS
2344 *
2345 * @param DMAx DMAx instance
2346 * @retval State of bit (1 or 0).
2347 */
2348 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
2349 {
2350 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2351 }
2352
2353 /**
2354 * @brief Indicate the status of Channel 1 source transaction complete flag.
2355 *
2356 * Register|BitsName
2357 * --------|--------
2358 * STAT_SRC_TRN | STATUS
2359 *
2360 * @param DMAx DMAx instance
2361 * @retval State of bit (1 or 0).
2362 */
2363 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
2364 {
2365 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2366 }
2367
2368 /**
2369 * @brief Indicate the status of Channel 2 source transaction complete flag.
2370 *
2371 * Register|BitsName
2372 * --------|--------
2373 * STAT_SRC_TRN | STATUS
2374 *
2375 * @param DMAx DMAx instance
2376 * @retval State of bit (1 or 0).
2377 */
2378 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
2379 {
2380 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2381 }
2382
2383 /**
2384 * @brief Indicate the status of Channel 3 source transaction complete flag.
2385 *
2386 * Register|BitsName
2387 * --------|--------
2388 * STAT_SRC_TRN | STATUS
2389 *
2390 * @param DMAx DMAx instance
2391 * @retval State of bit (1 or 0).
2392 */
2393 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
2394 {
2395 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2396 }
2397
2398 /**
2399 * @brief Indicate the status of Channel 4 source transaction complete flag.
2400 *
2401 * Register|BitsName
2402 * --------|--------
2403 * STAT_SRC_TRN | STATUS
2404 *
2405 * @param DMAx DMAx instance
2406 * @retval State of bit (1 or 0).
2407 */
2408 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
2409 {
2410 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2411 }
2412
2413 /**
2414 * @brief Indicate the status of Channel 5 source transaction complete flag.
2415 *
2416 * Register|BitsName
2417 * --------|--------
2418 * STAT_SRC_TRN | STATUS
2419 *
2420 * @param DMAx DMAx instance
2421 * @retval State of bit (1 or 0).
2422 */
2423 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
2424 {
2425 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
2426 }
2427
2428 /**
2429 * @brief Indicate the status of Channel 6 source transaction complete flag.
2430 *
2431 * Register|BitsName
2432 * --------|--------
2433 * STAT_SRC_TRN | STATUS
2434 *
2435 * @param DMAx DMAx instance
2436 * @retval State of bit (1 or 0).
2437 */
2438 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
2439 {
2440 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
2441 }
2442
2443 /**
2444 * @brief Indicate the status of Channel 7 source transaction complete flag.
2445 *
2446 * Register|BitsName
2447 * --------|--------
2448 * STAT_SRC_TRN | STATUS
2449 *
2450 * @param DMAx DMAx instance
2451 * @retval State of bit (1 or 0).
2452 */
2453 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
2454 {
2455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
2456 }
2457
2458 /**
2459 * @brief Indicate the status of DMA Channel destination transaction complete flag.
2460 *
2461 * Register|BitsName
2462 * --------|--------
2463 * STAT_DST_TRN | STATUS
2464 *
2465 * @param DMAx DMAx instance
2466 * @param channel This parameter can be one of the following values:
2467 * @arg @ref LL_DMA_CHANNEL_0
2468 * @arg @ref LL_DMA_CHANNEL_1
2469 * @arg @ref LL_DMA_CHANNEL_2
2470 * @arg @ref LL_DMA_CHANNEL_3
2471 * @arg @ref LL_DMA_CHANNEL_4
2472 * @arg @ref LL_DMA_CHANNEL_5
2473 * @arg @ref LL_DMA_CHANNEL_6
2474 * @arg @ref LL_DMA_CHANNEL_7
2475 * @retval State of bit (1 or 0).
2476 */
2477 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2478 {
2479 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2480 }
2481
2482 /**
2483 * @brief Indicate the status of Channel 0 destination transaction complete flag.
2484 *
2485 * Register|BitsName
2486 * --------|--------
2487 * STAT_DST_TRN | STATUS
2488 *
2489 * @param DMAx DMAx instance
2490 * @retval State of bit (1 or 0).
2491 */
2492 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
2493 {
2494 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2495 }
2496
2497 /**
2498 * @brief Indicate the status of Channel 1 destination transaction complete flag.
2499 *
2500 * Register|BitsName
2501 * --------|--------
2502 * STAT_DST_TRN | STATUS
2503 *
2504 * @param DMAx DMAx instance
2505 * @retval State of bit (1 or 0).
2506 */
2507 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
2508 {
2509 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2510 }
2511
2512 /**
2513 * @brief Indicate the status of Channel 2 destination transaction complete flag.
2514 *
2515 * Register|BitsName
2516 * --------|--------
2517 * STAT_DST_TRN | STATUS
2518 *
2519 * @param DMAx DMAx instance
2520 * @retval State of bit (1 or 0).
2521 */
2522 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
2523 {
2524 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2525 }
2526
2527 /**
2528 * @brief Indicate the status of Channel 3 destination transaction complete flag.
2529 *
2530 * Register|BitsName
2531 * --------|--------
2532 * STAT_DST_TRN | STATUS
2533 *
2534 * @param DMAx DMAx instance
2535 * @retval State of bit (1 or 0).
2536 */
2537 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
2538 {
2539 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2540 }
2541
2542 /**
2543 * @brief Indicate the status of Channel 4 destination transaction complete flag.
2544 *
2545 * Register|BitsName
2546 * --------|--------
2547 * STAT_DST_TRN | STATUS
2548 *
2549 * @param DMAx DMAx instance
2550 * @retval State of bit (1 or 0).
2551 */
2552 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
2553 {
2554 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2555 }
2556
2557 /**
2558 * @brief Indicate the status of Channel 5 destination transaction complete flag.
2559 *
2560 * Register|BitsName
2561 * --------|--------
2562 * STAT_DST_TRN | STATUS
2563 *
2564 * @param DMAx DMAx instance
2565 * @retval State of bit (1 or 0).
2566 */
2567 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
2568 {
2569 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
2570 }
2571
2572 /**
2573 * @brief Indicate the status of Channel 6 destination transaction complete flag.
2574 *
2575 * Register|BitsName
2576 * --------|--------
2577 * STAT_DST_TRN | STATUS
2578 *
2579 * @param DMAx DMAx instance
2580 * @retval State of bit (1 or 0).
2581 */
2582 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
2583 {
2584 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
2585 }
2586
2587 /**
2588 * @brief Indicate the status of Channel 7 destination transaction complete flag.
2589 *
2590 * Register|BitsName
2591 * --------|--------
2592 * STAT_DST_TRN | STATUS
2593 *
2594 * @param DMAx DMAx instance
2595 * @retval State of bit (1 or 0).
2596 */
2597 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
2598 {
2599 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
2600 }
2601
2602 /**
2603 * @brief Indicate the status of DMA Channel error flag.
2604 *
2605 * Register|BitsName
2606 * --------|--------
2607 * STAT_ERR | STATUS
2608 *
2609 * @param DMAx DMAx instance
2610 * @param channel This parameter can be one of the following values:
2611 * @arg @ref LL_DMA_CHANNEL_0
2612 * @arg @ref LL_DMA_CHANNEL_1
2613 * @arg @ref LL_DMA_CHANNEL_2
2614 * @arg @ref LL_DMA_CHANNEL_3
2615 * @arg @ref LL_DMA_CHANNEL_4
2616 * @arg @ref LL_DMA_CHANNEL_5
2617 * @arg @ref LL_DMA_CHANNEL_6
2618 * @arg @ref LL_DMA_CHANNEL_7
2619 * @retval State of bit (1 or 0).
2620 */
2621 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
2622 {
2623 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
2624 }
2625
2626 /**
2627 * @brief Indicate the status of Channel 0 error flag.
2628 *
2629 * Register|BitsName
2630 * --------|--------
2631 * STAT_ERR | STATUS
2632 *
2633 * @param DMAx DMAx instance
2634 * @retval State of bit (1 or 0).
2635 */
2636 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
2637 {
2638 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
2639 }
2640
2641 /**
2642 * @brief Indicate the status of Channel 1 error flag.
2643 *
2644 * Register|BitsName
2645 * --------|--------
2646 * STAT_ERR | STATUS
2647 *
2648 * @param DMAx DMAx instance
2649 * @retval State of bit (1 or 0).
2650 */
2651 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
2652 {
2653 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
2654 }
2655
2656 /**
2657 * @brief Indicate the status of Channel 2 error flag.
2658 *
2659 * Register|BitsName
2660 * --------|--------
2661 * STAT_ERR | STATUS
2662 *
2663 * @param DMAx DMAx instance
2664 * @retval State of bit (1 or 0).
2665 */
2666 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
2667 {
2668 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
2669 }
2670
2671 /**
2672 * @brief Indicate the status of Channel 3 error flag.
2673 *
2674 * Register|BitsName
2675 * --------|--------
2676 * STAT_ERR | STATUS
2677 *
2678 * @param DMAx DMAx instance
2679 * @retval State of bit (1 or 0).
2680 */
2681 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
2682 {
2683 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
2684 }
2685
2686 /**
2687 * @brief Indicate the status of Channel 4 error flag.
2688 *
2689 * Register|BitsName
2690 * --------|--------
2691 * STAT_ERR | STATUS
2692 *
2693 * @param DMAx DMAx instance
2694 * @retval State of bit (1 or 0).
2695 */
2696 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
2697 {
2698 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
2699 }
2700
2701 /**
2702 * @brief Indicate the status of Channel 5 error flag.
2703 *
2704 * Register|BitsName
2705 * --------|--------
2706 * STAT_ERR | STATUS
2707 *
2708 * @param DMAx DMAx instance
2709 * @retval State of bit (1 or 0).
2710 */
2711 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
2712 {
2713 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
2714 }
2715
2716 /**
2717 * @brief Indicate the status of Channel 6 error flag.
2718 *
2719 * Register|BitsName
2720 * --------|--------
2721 * STAT_ERR | STATUS
2722 *
2723 * @param DMAx DMAx instance
2724 * @retval State of bit (1 or 0).
2725 */
2726 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
2727 {
2728 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
2729 }
2730
2731 /**
2732 * @brief Indicate the status of Channel 7 error flag.
2733 *
2734 * Register|BitsName
2735 * --------|--------
2736 * STAT_ERR | STATUS
2737 *
2738 * @param DMAx DMAx instance
2739 * @retval State of bit (1 or 0).
2740 */
2741 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
2742 {
2743 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
2744 }
2745
2746 /**
2747 * @brief Clear DMA Channel transfer complete flag.
2748 *
2749 * Register|BitsName
2750 * --------|--------
2751 * CLR_TFR | CLEAR
2752 *
2753 * @param DMAx DMAx instance
2754 * @param channel This parameter can be one of the following values:
2755 * @arg @ref LL_DMA_CHANNEL_0
2756 * @arg @ref LL_DMA_CHANNEL_1
2757 * @arg @ref LL_DMA_CHANNEL_2
2758 * @arg @ref LL_DMA_CHANNEL_3
2759 * @arg @ref LL_DMA_CHANNEL_4
2760 * @arg @ref LL_DMA_CHANNEL_5
2761 * @arg @ref LL_DMA_CHANNEL_6
2762 * @arg @ref LL_DMA_CHANNEL_7
2763 * @retval None.
2764 */
2765 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2766 {
2767 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2768 }
2769
2770 /**
2771 * @brief Clear Channel 0 transfer complete flag.
2772 *
2773 * Register|BitsName
2774 * --------|--------
2775 * CLR_TFR | CLEAR
2776 *
2777 * @param DMAx DMAx instance
2778 * @retval None.
2779 */
2780 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
2781 {
2782 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2783 }
2784
2785 /**
2786 * @brief Clear Channel 1 transfer complete flag.
2787 *
2788 * Register|BitsName
2789 * --------|--------
2790 * CLR_TFR | CLEAR
2791 *
2792 * @param DMAx DMAx instance
2793 * @retval None.
2794 */
2795 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
2796 {
2797 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2798 }
2799
2800 /**
2801 * @brief Clear Channel 2 transfer complete flag.
2802 *
2803 * Register|BitsName
2804 * --------|--------
2805 * CLR_TFR | CLEAR
2806 *
2807 * @param DMAx DMAx instance
2808 * @retval None.
2809 */
2810 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
2811 {
2812 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
2813 }
2814
2815 /**
2816 * @brief Clear Channel 3 transfer complete flag.
2817 *
2818 * Register|BitsName
2819 * --------|--------
2820 * CLR_TFR | CLEAR
2821 *
2822 * @param DMAx DMAx instance
2823 * @retval None.
2824 */
2825 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
2826 {
2827 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
2828 }
2829
2830 /**
2831 * @brief Clear Channel 4 transfer complete flag.
2832 *
2833 * Register|BitsName
2834 * --------|--------
2835 * CLR_TFR | CLEAR
2836 *
2837 * @param DMAx DMAx instance
2838 * @retval None.
2839 */
2840 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
2841 {
2842 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
2843 }
2844
2845 /**
2846 * @brief Clear Channel 5 transfer complete flag.
2847 *
2848 * Register|BitsName
2849 * --------|--------
2850 * CLR_TFR | CLEAR
2851 *
2852 * @param DMAx DMAx instance
2853 * @retval None.
2854 */
2855 __STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
2856 {
2857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
2858 }
2859
2860 /**
2861 * @brief Clear Channel 6 transfer complete flag.
2862 *
2863 * Register|BitsName
2864 * --------|--------
2865 * CLR_TFR | CLEAR
2866 *
2867 * @param DMAx DMAx instance
2868 * @retval None.
2869 */
2870 __STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
2871 {
2872 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
2873 }
2874
2875 /**
2876 * @brief Clear Channel 7 transfer complete flag.
2877 *
2878 * Register|BitsName
2879 * --------|--------
2880 * CLR_TFR | CLEAR
2881 *
2882 * @param DMAx DMAx instance
2883 * @retval None.
2884 */
2885 __STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
2886 {
2887 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
2888 }
2889
2890 /**
2891 * @brief Clear DMA Channel block complete flag.
2892 *
2893 * Register|BitsName
2894 * --------|--------
2895 * CLR_BLK | CLEAR
2896 *
2897 * @param DMAx DMAx instance
2898 * @param channel This parameter can be one of the following values:
2899 * @arg @ref LL_DMA_CHANNEL_0
2900 * @arg @ref LL_DMA_CHANNEL_1
2901 * @arg @ref LL_DMA_CHANNEL_2
2902 * @arg @ref LL_DMA_CHANNEL_3
2903 * @arg @ref LL_DMA_CHANNEL_4
2904 * @arg @ref LL_DMA_CHANNEL_5
2905 * @arg @ref LL_DMA_CHANNEL_6
2906 * @arg @ref LL_DMA_CHANNEL_7
2907 * @retval None.
2908 */
2909 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2910 {
2911 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
2912 }
2913
2914 /**
2915 * @brief Clear Channel 0 Block Complete flag.
2916 *
2917 * Register|BitsName
2918 * --------|--------
2919 * CLR_BLK | CLEAR
2920 *
2921 * @param DMAx DMAx instance
2922 * @retval None.
2923 */
2924 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
2925 {
2926 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
2927 }
2928
2929 /**
2930 * @brief Clear Channel 1 Block Complete flag.
2931 *
2932 * Register|BitsName
2933 * --------|--------
2934 * CLR_BLK | CLEAR
2935 *
2936 * @param DMAx DMAx instance
2937 * @retval None.
2938 */
2939 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
2940 {
2941 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
2942 }
2943
2944 /**
2945 * @brief Clear Channel 2 Block Complete flag.
2946 *
2947 * Register|BitsName
2948 * --------|--------
2949 * CLR_BLK | CLEAR
2950 *
2951 * @param DMAx DMAx instance
2952 * @retval None.
2953 */
2954 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
2955 {
2956 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
2957 }
2958
2959 /**
2960 * @brief Clear Channel 3 Block Complete flag.
2961 *
2962 * Register|BitsName
2963 * --------|--------
2964 * CLR_BLK | CLEAR
2965 *
2966 * @param DMAx DMAx instance
2967 * @retval None.
2968 */
2969 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
2970 {
2971 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
2972 }
2973
2974 /**
2975 * @brief Clear Channel 4 Block Complete flag.
2976 *
2977 * Register|BitsName
2978 * --------|--------
2979 * CLR_BLK | CLEAR
2980 *
2981 * @param DMAx DMAx instance
2982 * @retval None.
2983 */
2984 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
2985 {
2986 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
2987 }
2988
2989 /**
2990 * @brief Clear Channel 5 Block Complete flag.
2991 *
2992 * Register|BitsName
2993 * --------|--------
2994 * CLR_BLK | CLEAR
2995 *
2996 * @param DMAx DMAx instance
2997 * @retval None.
2998 */
2999 __STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
3000 {
3001 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
3002 }
3003
3004 /**
3005 * @brief Clear Channel 6 Block Cmplete flag.
3006 *
3007 * Register|BitsName
3008 * --------|--------
3009 * CLR_BLK | CLEAR
3010 *
3011 * @param DMAx DMAx instance
3012 * @retval None.
3013 */
3014 __STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
3015 {
3016 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
3017 }
3018
3019 /**
3020 * @brief Clear Channel 7 Block Complete flag.
3021 *
3022 * Register|BitsName
3023 * --------|--------
3024 * CLR_BLK | CLEAR
3025 *
3026 * @param DMAx DMAx instance
3027 * @retval None.
3028 */
3029 __STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
3030 {
3031 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
3032 }
3033
3034 /**
3035 * @brief Clear DMA Channel source transaction Complete flag.
3036 *
3037 * Register|BitsName
3038 * --------|--------
3039 * CLR_SRC_TRN | CLEAR
3040 *
3041 * @param DMAx DMAx instance
3042 * @param channel This parameter can be one of the following values:
3043 * @arg @ref LL_DMA_CHANNEL_0
3044 * @arg @ref LL_DMA_CHANNEL_1
3045 * @arg @ref LL_DMA_CHANNEL_2
3046 * @arg @ref LL_DMA_CHANNEL_3
3047 * @arg @ref LL_DMA_CHANNEL_4
3048 * @arg @ref LL_DMA_CHANNEL_5
3049 * @arg @ref LL_DMA_CHANNEL_6
3050 * @arg @ref LL_DMA_CHANNEL_7
3051 * @retval None.
3052 */
3053 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
3054 {
3055 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
3056 }
3057
3058 /**
3059 * @brief Clear Channel 0 source transaction Complete flag.
3060 *
3061 * Register|BitsName
3062 * --------|--------
3063 * CLR_SRC_TRN | CLEAR
3064 *
3065 * @param DMAx DMAx instance
3066 * @retval None.
3067 */
3068 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
3069 {
3070 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
3071 }
3072
3073 /**
3074 * @brief Clear Channel 1 source transaction Complete flag.
3075 *
3076 * Register|BitsName
3077 * --------|--------
3078 * CLR_SRC_TRN | CLEAR
3079 *
3080 * @param DMAx DMAx instance
3081 * @retval None.
3082 */
3083 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
3084 {
3085 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
3086 }
3087
3088 /**
3089 * @brief Clear Channel 2 source transaction Complete flag.
3090 *
3091 * Register|BitsName
3092 * --------|--------
3093 * CLR_SRC_TRN | CLEAR
3094 *
3095 * @param DMAx DMAx instance
3096 * @retval None.
3097 */
3098 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
3099 {
3100 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
3101 }
3102
3103 /**
3104 * @brief Clear Channel 3 source transaction Complete flag.
3105 *
3106 * Register|BitsName
3107 * --------|--------
3108 * CLR_SRC_TRN | CLEAR
3109 *
3110 * @param DMAx DMAx instance
3111 * @retval None.
3112 */
3113 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
3114 {
3115 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
3116 }
3117
3118 /**
3119 * @brief Clear Channel 4 source transaction Complete flag.
3120 *
3121 * Register|BitsName
3122 * --------|--------
3123 * CLR_SRC_TRN | CLEAR
3124 *
3125 * @param DMAx DMAx instance
3126 * @retval None.
3127 */
3128 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
3129 {
3130 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
3131 }
3132
3133 /**
3134 * @brief Clear Channel 5 source transaction Complete flag.
3135 *
3136 * Register|BitsName
3137 * --------|--------
3138 * CLR_SRC_TRN | CLEAR
3139 *
3140 * @param DMAx DMAx instance
3141 * @retval None.
3142 */
3143 __STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
3144 {
3145 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
3146 }
3147
3148 /**
3149 * @brief Clear Channel 6 source transaction Complete flag.
3150 *
3151 * Register|BitsName
3152 * --------|--------
3153 * CLR_SRC_TRN | CLEAR
3154 *
3155 * @param DMAx DMAx instance
3156 * @retval None.
3157 */
3158 __STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
3159 {
3160 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
3161 }
3162
3163 /**
3164 * @brief Clear Channel 7 source transaction Complete flag.
3165 *
3166 * Register|BitsName
3167 * --------|--------
3168 * CLR_SRC_TRN | CLEAR
3169 *
3170 * @param DMAx DMAx instance
3171 * @retval None.
3172 */
3173 __STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
3174 {
3175 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
3176 }
3177
3178 /**
3179 * @brief Clear DMA Channel destination transaction Complete flag.
3180 *
3181 * Register|BitsName
3182 * --------|--------
3183 * CLR_DST_TRN | CLEAR
3184 *
3185 * @param DMAx DMAx instance
3186 * @param channel This parameter can be one of the following values:
3187 * @arg @ref LL_DMA_CHANNEL_0
3188 * @arg @ref LL_DMA_CHANNEL_1
3189 * @arg @ref LL_DMA_CHANNEL_2
3190 * @arg @ref LL_DMA_CHANNEL_3
3191 * @arg @ref LL_DMA_CHANNEL_4
3192 * @arg @ref LL_DMA_CHANNEL_5
3193 * @arg @ref LL_DMA_CHANNEL_6
3194 * @arg @ref LL_DMA_CHANNEL_7
3195 * @retval None.
3196 */
3197 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
3198 {
3199 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
3200 }
3201
3202 /**
3203 * @brief Clear Channel 0 destination transaction Complete status.
3204 *
3205 * Register|BitsName
3206 * --------|--------
3207 * CLR_DST_TRN | CLEAR
3208 *
3209 * @param DMAx DMAx instance
3210 * @retval None.
3211 */
3212 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
3213 {
3214 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
3215 }
3216
3217 /**
3218 * @brief Clear Channel 1 destination transaction Complete flag.
3219 *
3220 * Register|BitsName
3221 * --------|--------
3222 * CLR_DST_TRN | CLEAR
3223 *
3224 * @param DMAx DMAx instance
3225 * @retval None.
3226 */
3227 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
3228 {
3229 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
3230 }
3231
3232 /**
3233 * @brief Clear Channel 2 destination transaction Complete flag.
3234 *
3235 * Register|BitsName
3236 * --------|--------
3237 * CLR_DST_TRN | CLEAR
3238 *
3239 * @param DMAx DMAx instance
3240 * @retval None.
3241 */
3242 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
3243 {
3244 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
3245 }
3246
3247 /**
3248 * @brief Clear Channel 3 destination transaction Complete flag.
3249 *
3250 * Register|BitsName
3251 * --------|--------
3252 * CLR_DST_TRN | CLEAR
3253 *
3254 * @param DMAx DMAx instance
3255 * @retval None.
3256 */
3257 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
3258 {
3259 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
3260 }
3261
3262 /**
3263 * @brief Clear Channel 4 destination transaction Complete flag.
3264 *
3265 * Register|BitsName
3266 * --------|--------
3267 * CLR_DST_TRN | CLEAR
3268 *
3269 * @param DMAx DMAx instance
3270 * @retval None.
3271 */
3272 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
3273 {
3274 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
3275 }
3276
3277 /**
3278 * @brief Clear Channel 5 destination transaction Complete flag.
3279 *
3280 * Register|BitsName
3281 * --------|--------
3282 * CLR_DST_TRN | CLEAR
3283 *
3284 * @param DMAx DMAx instance
3285 * @retval None.
3286 */
3287 __STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
3288 {
3289 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
3290 }
3291
3292 /**
3293 * @brief Clear Channel 6 destination transaction Complete flag.
3294 *
3295 * Register|BitsName
3296 * --------|--------
3297 * CLR_DST_TRN | CLEAR
3298 *
3299 * @param DMAx DMAx instance
3300 * @retval None.
3301 */
3302 __STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
3303 {
3304 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
3305 }
3306
3307 /**
3308 * @brief Clear Channel 7 destination transaction Complete flag.
3309 *
3310 * Register|BitsName
3311 * --------|--------
3312 * CLR_DST_TRN | CLEAR
3313 *
3314 * @param DMAx DMAx instance
3315 * @retval None.
3316 */
3317 __STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
3318 {
3319 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
3320 }
3321
3322 /**
3323 * @brief Clear DMA Channel error flag.
3324 *
3325 * Register|BitsName
3326 * --------|--------
3327 * CLR_ERR | CLEAR
3328 *
3329 * @param DMAx DMAx instance
3330 * @param channel This parameter can be one of the following values:
3331 * @arg @ref LL_DMA_CHANNEL_0
3332 * @arg @ref LL_DMA_CHANNEL_1
3333 * @arg @ref LL_DMA_CHANNEL_2
3334 * @arg @ref LL_DMA_CHANNEL_3
3335 * @arg @ref LL_DMA_CHANNEL_4
3336 * @arg @ref LL_DMA_CHANNEL_5
3337 * @arg @ref LL_DMA_CHANNEL_6
3338 * @arg @ref LL_DMA_CHANNEL_7
3339 * @retval None.
3340 */
3341 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
3342 {
3343 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
3344 }
3345
3346 /**
3347 * @brief Clear Channel 0 error flag.
3348 *
3349 * Register|BitsName
3350 * --------|--------
3351 * CLR_ERR | CLEAR
3352 *
3353 * @param DMAx DMAx instance
3354 * @retval None.
3355 */
3356 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
3357 {
3358 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
3359 }
3360
3361 /**
3362 * @brief Clear Channel 1 error flag.
3363 *
3364 * Register|BitsName
3365 * --------|--------
3366 * CLR_ERR | CLEAR
3367 *
3368 * @param DMAx DMAx instance
3369 * @retval None.
3370 */
3371 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
3372 {
3373 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
3374 }
3375
3376 /**
3377 * @brief Clear Channel 2 error flag.
3378 *
3379 * Register|BitsName
3380 * --------|--------
3381 * CLR_ERR | CLEAR
3382 *
3383 * @param DMAx DMAx instance
3384 * @retval None.
3385 */
3386 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
3387 {
3388 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3389 }
3390
3391 /**
3392 * @brief Clear Channel 3 error flag.
3393 *
3394 * Register|BitsName
3395 * --------|--------
3396 * CLR_ERR | CLEAR
3397 *
3398 * @param DMAx DMAx instance
3399 * @retval None.
3400 */
3401 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
3402 {
3403 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
3404 }
3405
3406 /**
3407 * @brief Clear Channel 4 error flag.
3408 *
3409 * Register|BitsName
3410 * --------|--------
3411 * CLR_ERR | CLEAR
3412 *
3413 * @param DMAx DMAx instance
3414 * @retval None.
3415 */
3416 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
3417 {
3418 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
3419 }
3420
3421 /**
3422 * @brief Clear Channel 5 error flag.
3423 *
3424 * Register|BitsName
3425 * --------|--------
3426 * CLR_ERR | CLEAR
3427 *
3428 * @param DMAx DMAx instance
3429 * @retval None.
3430 */
3431 __STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
3432 {
3433 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
3434 }
3435
3436 /**
3437 * @brief Clear Channel 6 error flag.
3438 *
3439 * Register|BitsName
3440 * --------|--------
3441 * CLR_ERR | CLEAR
3442 *
3443 * @param DMAx DMAx instance
3444 * @retval None.
3445 */
3446 __STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
3447 {
3448 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
3449 }
3450
3451 /**
3452 * @brief Clear Channel 7 error flag.
3453 *
3454 * Register|BitsName
3455 * --------|--------
3456 * CLR_ERR | CLEAR
3457 *
3458 * @param DMAx DMAx instance
3459 * @retval None.
3460 */
3461 __STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
3462 {
3463 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
3464 }
3465
3466 /** @} */
3467
3468 /** @defgroup DMA_LL_EF_IT_Management IT_Management
3469 * @{
3470 */
3471
3472 /**
3473 * @brief Enable Transfer Complete interrupt.
3474 *
3475 * Register|BitsName
3476 * --------|--------
3477 * MASK_TFR | TFR_WE&TFR
3478 *
3479 * @param DMAx DMAx instance
3480 * @param channel This parameter can be one of the following values:
3481 * @arg @ref LL_DMA_CHANNEL_0
3482 * @arg @ref LL_DMA_CHANNEL_1
3483 * @arg @ref LL_DMA_CHANNEL_2
3484 * @arg @ref LL_DMA_CHANNEL_3
3485 * @arg @ref LL_DMA_CHANNEL_4
3486 * @arg @ref LL_DMA_CHANNEL_5
3487 * @arg @ref LL_DMA_CHANNEL_6
3488 * @arg @ref LL_DMA_CHANNEL_7
3489 * @retval None
3490 */
3491 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3492 {
3493 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3494 }
3495
3496 /**
3497 * @brief Enable Block Complete interrupt.
3498 *
3499 * Register|BitsName
3500 * --------|--------
3501 * MASK_BLK | BLK_WE&BLK
3502 *
3503 * @param DMAx DMAx instance
3504 * @param channel This parameter can be one of the following values:
3505 * @arg @ref LL_DMA_CHANNEL_0
3506 * @arg @ref LL_DMA_CHANNEL_1
3507 * @arg @ref LL_DMA_CHANNEL_2
3508 * @arg @ref LL_DMA_CHANNEL_3
3509 * @arg @ref LL_DMA_CHANNEL_4
3510 * @arg @ref LL_DMA_CHANNEL_5
3511 * @arg @ref LL_DMA_CHANNEL_6
3512 * @arg @ref LL_DMA_CHANNEL_7
3513 * @retval None
3514 */
3515 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3516 {
3517 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3518 }
3519
3520 /**
3521 * @brief Enable source transaction Complete interrupt.
3522 *
3523 * Register|BitsName
3524 * --------|--------
3525 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3526 *
3527 * @param DMAx DMAx instance
3528 * @param channel This parameter can be one of the following values:
3529 * @arg @ref LL_DMA_CHANNEL_0
3530 * @arg @ref LL_DMA_CHANNEL_1
3531 * @arg @ref LL_DMA_CHANNEL_2
3532 * @arg @ref LL_DMA_CHANNEL_3
3533 * @arg @ref LL_DMA_CHANNEL_4
3534 * @arg @ref LL_DMA_CHANNEL_5
3535 * @arg @ref LL_DMA_CHANNEL_6
3536 * @arg @ref LL_DMA_CHANNEL_7
3537 * @retval None
3538 */
3539 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3540 {
3541 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3542 }
3543
3544 /**
3545 * @brief Enable destination transaction Complete interrupt.
3546 *
3547 * Register|BitsName
3548 * --------|--------
3549 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3550 *
3551 * @param DMAx DMAx instance
3552 * @param channel This parameter can be one of the following values:
3553 * @arg @ref LL_DMA_CHANNEL_0
3554 * @arg @ref LL_DMA_CHANNEL_1
3555 * @arg @ref LL_DMA_CHANNEL_2
3556 * @arg @ref LL_DMA_CHANNEL_3
3557 * @arg @ref LL_DMA_CHANNEL_4
3558 * @arg @ref LL_DMA_CHANNEL_5
3559 * @arg @ref LL_DMA_CHANNEL_6
3560 * @arg @ref LL_DMA_CHANNEL_7
3561 * @retval None
3562 */
3563 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3564 {
3565 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3566 }
3567
3568 /**
3569 * @brief Enable error interrupt.
3570 *
3571 * Register|BitsName
3572 * --------|--------
3573 * MASK_ERR | ERR_WE&ERR
3574 *
3575 * @param DMAx DMAx instance
3576 * @param channel This parameter can be one of the following values:
3577 * @arg @ref LL_DMA_CHANNEL_0
3578 * @arg @ref LL_DMA_CHANNEL_1
3579 * @arg @ref LL_DMA_CHANNEL_2
3580 * @arg @ref LL_DMA_CHANNEL_3
3581 * @arg @ref LL_DMA_CHANNEL_4
3582 * @arg @ref LL_DMA_CHANNEL_5
3583 * @arg @ref LL_DMA_CHANNEL_6
3584 * @arg @ref LL_DMA_CHANNEL_7
3585 * @retval None
3586 */
3587 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3588 {
3589 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3590 }
3591
3592 /**
3593 * @brief Disable Transfer Complete interrupt.
3594 *
3595 * Register|BitsName
3596 * --------|--------
3597 * MASK_TFR | TFR_WE&TFR
3598 *
3599 * @param DMAx DMAx instance
3600 * @param channel This parameter can be one of the following values:
3601 * @arg @ref LL_DMA_CHANNEL_0
3602 * @arg @ref LL_DMA_CHANNEL_1
3603 * @arg @ref LL_DMA_CHANNEL_2
3604 * @arg @ref LL_DMA_CHANNEL_3
3605 * @arg @ref LL_DMA_CHANNEL_4
3606 * @arg @ref LL_DMA_CHANNEL_5
3607 * @arg @ref LL_DMA_CHANNEL_6
3608 * @arg @ref LL_DMA_CHANNEL_7
3609 * @retval None
3610 */
3611 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3612 {
3613 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3614 }
3615
3616 /**
3617 * @brief Disable Block Complete interrupt.
3618 *
3619 * Register|BitsName
3620 * --------|--------
3621 * MASK_BLK | BLK_WE&BLK
3622 *
3623 * @param DMAx DMAx instance
3624 * @param channel This parameter can be one of the following values:
3625 * @arg @ref LL_DMA_CHANNEL_0
3626 * @arg @ref LL_DMA_CHANNEL_1
3627 * @arg @ref LL_DMA_CHANNEL_2
3628 * @arg @ref LL_DMA_CHANNEL_3
3629 * @arg @ref LL_DMA_CHANNEL_4
3630 * @arg @ref LL_DMA_CHANNEL_5
3631 * @arg @ref LL_DMA_CHANNEL_6
3632 * @arg @ref LL_DMA_CHANNEL_7
3633 * @retval None
3634 */
3635 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3636 {
3637 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3638 }
3639
3640 /**
3641 * @brief Disable source transaction Complete interrupt.
3642 *
3643 * Register|BitsName
3644 * --------|--------
3645 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3646 *
3647 * @param DMAx DMAx instance
3648 * @param channel This parameter can be one of the following values:
3649 * @arg @ref LL_DMA_CHANNEL_0
3650 * @arg @ref LL_DMA_CHANNEL_1
3651 * @arg @ref LL_DMA_CHANNEL_2
3652 * @arg @ref LL_DMA_CHANNEL_3
3653 * @arg @ref LL_DMA_CHANNEL_4
3654 * @arg @ref LL_DMA_CHANNEL_5
3655 * @arg @ref LL_DMA_CHANNEL_6
3656 * @arg @ref LL_DMA_CHANNEL_7
3657 * @retval None
3658 */
3659 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3660 {
3661 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3662 }
3663
3664 /**
3665 * @brief Disable destination transaction Complete interrupt.
3666 *
3667 * Register|BitsName
3668 * --------|--------
3669 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3670 *
3671 * @param DMAx DMAx instance
3672 * @param channel This parameter can be one of the following values:
3673 * @arg @ref LL_DMA_CHANNEL_0
3674 * @arg @ref LL_DMA_CHANNEL_1
3675 * @arg @ref LL_DMA_CHANNEL_2
3676 * @arg @ref LL_DMA_CHANNEL_3
3677 * @arg @ref LL_DMA_CHANNEL_4
3678 * @arg @ref LL_DMA_CHANNEL_5
3679 * @arg @ref LL_DMA_CHANNEL_6
3680 * @arg @ref LL_DMA_CHANNEL_7
3681 * @retval None
3682 */
3683 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3684 {
3685 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3686 }
3687
3688 /**
3689 * @brief Disable error interrupt.
3690 *
3691 * Register|BitsName
3692 * --------|--------
3693 * MASK_ERR | ERR_WE&ERR
3694 *
3695 * @param DMAx DMAx instance
3696 * @param channel This parameter can be one of the following values:
3697 * @arg @ref LL_DMA_CHANNEL_0
3698 * @arg @ref LL_DMA_CHANNEL_1
3699 * @arg @ref LL_DMA_CHANNEL_2
3700 * @arg @ref LL_DMA_CHANNEL_3
3701 * @arg @ref LL_DMA_CHANNEL_4
3702 * @arg @ref LL_DMA_CHANNEL_5
3703 * @arg @ref LL_DMA_CHANNEL_6
3704 * @arg @ref LL_DMA_CHANNEL_7
3705 * @retval None
3706 */
3707 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
3708 {
3709 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3710 }
3711
3712 /**
3713 * @brief Check if DMA Transfer interrupt is enabled or disabled.
3714 *
3715 * Register|BitsName
3716 * --------|--------
3717 * MASK_TFR | TFR
3718 *
3719 * @param DMAx DMA instance.
3720 * @param channel This parameter can be one of the following values:
3721 * @arg @ref LL_DMA_CHANNEL_0
3722 * @arg @ref LL_DMA_CHANNEL_1
3723 * @arg @ref LL_DMA_CHANNEL_2
3724 * @arg @ref LL_DMA_CHANNEL_3
3725 * @arg @ref LL_DMA_CHANNEL_4
3726 * @arg @ref LL_DMA_CHANNEL_5
3727 * @arg @ref LL_DMA_CHANNEL_6
3728 * @arg @ref LL_DMA_CHANNEL_7
3729 * @retval State of bit (1 or 0).
3730 */
3731 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3732 {
3733 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3734 }
3735
3736 /**
3737 * @brief Check if DMA block interrupt is enabled or disabled.
3738 *
3739 * Register|BitsName
3740 * --------|--------
3741 * MASK_BLK | BLK_WE&BLK
3742 *
3743 * @param DMAx DMA instance.
3744 * @param channel This parameter can be one of the following values:
3745 * @arg @ref LL_DMA_CHANNEL_0
3746 * @arg @ref LL_DMA_CHANNEL_1
3747 * @arg @ref LL_DMA_CHANNEL_2
3748 * @arg @ref LL_DMA_CHANNEL_3
3749 * @arg @ref LL_DMA_CHANNEL_4
3750 * @arg @ref LL_DMA_CHANNEL_5
3751 * @arg @ref LL_DMA_CHANNEL_6
3752 * @arg @ref LL_DMA_CHANNEL_7
3753 * @retval State of bit (1 or 0).
3754 */
3755 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3756 {
3757 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
3758 }
3759
3760 /**
3761 * @brief Check if DMA source transaction interrupt is enabled or disabled.
3762 *
3763 * Register|BitsName
3764 * --------|--------
3765 * MASK_SRC_TRN | SRC_TRN
3766 *
3767 * @param DMAx DMA instance.
3768 * @param channel This parameter can be one of the following values:
3769 * @arg @ref LL_DMA_CHANNEL_0
3770 * @arg @ref LL_DMA_CHANNEL_1
3771 * @arg @ref LL_DMA_CHANNEL_2
3772 * @arg @ref LL_DMA_CHANNEL_3
3773 * @arg @ref LL_DMA_CHANNEL_4
3774 * @arg @ref LL_DMA_CHANNEL_5
3775 * @arg @ref LL_DMA_CHANNEL_6
3776 * @arg @ref LL_DMA_CHANNEL_7
3777 * @retval State of bit (1 or 0).
3778 */
3779 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3780 {
3781 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
3782 }
3783
3784 /**
3785 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
3786 *
3787 * Register|BitsName
3788 * --------|--------
3789 * MASK_DST_TRN | DST_TRN
3790 *
3791 * @param DMAx DMA instance.
3792 * @param channel This parameter can be one of the following values:
3793 * @arg @ref LL_DMA_CHANNEL_0
3794 * @arg @ref LL_DMA_CHANNEL_1
3795 * @arg @ref LL_DMA_CHANNEL_2
3796 * @arg @ref LL_DMA_CHANNEL_3
3797 * @arg @ref LL_DMA_CHANNEL_4
3798 * @arg @ref LL_DMA_CHANNEL_5
3799 * @arg @ref LL_DMA_CHANNEL_6
3800 * @arg @ref LL_DMA_CHANNEL_7
3801 * @retval State of bit (1 or 0).
3802 */
3803 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3804 {
3805 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
3806 }
3807
3808 /**
3809 * @brief Check if DMA error interrupt is enabled or disabled.
3810 *
3811 * Register|BitsName
3812 * --------|--------
3813 * MASK_ERR | ERR
3814 *
3815 * @param DMAx DMA instance.
3816 * @param channel This parameter can be one of the following values:
3817 * @arg @ref LL_DMA_CHANNEL_0
3818 * @arg @ref LL_DMA_CHANNEL_1
3819 * @arg @ref LL_DMA_CHANNEL_2
3820 * @arg @ref LL_DMA_CHANNEL_3
3821 * @arg @ref LL_DMA_CHANNEL_4
3822 * @arg @ref LL_DMA_CHANNEL_5
3823 * @arg @ref LL_DMA_CHANNEL_6
3824 * @arg @ref LL_DMA_CHANNEL_7
3825 * @retval State of bit (1 or 0).
3826 */
3827 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3828 {
3829 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
3830 }
3831
3832 /**
3833 * @brief Enable DMA channel interrupt.
3834 *
3835 * Register|BitsName
3836 * --------|--------
3837 * CTLL | INI_EN
3838 *
3839 * @param DMAx DMA instance.
3840 * @param channel This parameter can be one of the following values:
3841 * @arg @ref LL_DMA_CHANNEL_0
3842 * @arg @ref LL_DMA_CHANNEL_1
3843 * @arg @ref LL_DMA_CHANNEL_2
3844 * @arg @ref LL_DMA_CHANNEL_3
3845 * @arg @ref LL_DMA_CHANNEL_4
3846 * @arg @ref LL_DMA_CHANNEL_5
3847 * @arg @ref LL_DMA_CHANNEL_6
3848 * @arg @ref LL_DMA_CHANNEL_7
3849 * @retval None
3850 */
3851 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
3852 {
3853 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3854 }
3855
3856 /**
3857 * @brief Disable DMA channel interrupt.
3858 *
3859 * Register|BitsName
3860 * --------|--------
3861 * CTLL | INI_EN
3862 *
3863 * @param DMAx DMA instance.
3864 * @param channel This parameter can be one of the following values:
3865 * @arg @ref LL_DMA_CHANNEL_0
3866 * @arg @ref LL_DMA_CHANNEL_1
3867 * @arg @ref LL_DMA_CHANNEL_2
3868 * @arg @ref LL_DMA_CHANNEL_3
3869 * @arg @ref LL_DMA_CHANNEL_4
3870 * @arg @ref LL_DMA_CHANNEL_5
3871 * @arg @ref LL_DMA_CHANNEL_6
3872 * @arg @ref LL_DMA_CHANNEL_7
3873 * @retval None
3874 */
3875 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
3876 {
3877 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
3878 }
3879
3880 /** @} */
3881
3882 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3883 * @{
3884 */
3885
3886 /**
3887 * @brief De-initialize the DMA registers to their default reset values.
3888 * @param DMAx DMAx instance
3889 * @param channel This parameter can be one of the following values:
3890 * @arg @ref LL_DMA_CHANNEL_0
3891 * @arg @ref LL_DMA_CHANNEL_1
3892 * @arg @ref LL_DMA_CHANNEL_2
3893 * @arg @ref LL_DMA_CHANNEL_3
3894 * @arg @ref LL_DMA_CHANNEL_4
3895 * @arg @ref LL_DMA_CHANNEL_5
3896 * @arg @ref LL_DMA_CHANNEL_6
3897 * @arg @ref LL_DMA_CHANNEL_7
3898 * @retval An error_status_t enumeration value:
3899 * - SUCCESS: DMA registers are de-initialized
3900 * - ERROR: DMA registers are not de-initialized
3901 */
3902 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
3903
3904 /**
3905 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
3906 * @param DMAx DMAx instance
3907 * @param channel This parameter can be one of the following values:
3908 * @arg @ref LL_DMA_CHANNEL_0
3909 * @arg @ref LL_DMA_CHANNEL_1
3910 * @arg @ref LL_DMA_CHANNEL_2
3911 * @arg @ref LL_DMA_CHANNEL_3
3912 * @arg @ref LL_DMA_CHANNEL_4
3913 * @arg @ref LL_DMA_CHANNEL_5
3914 * @arg @ref LL_DMA_CHANNEL_6
3915 * @arg @ref LL_DMA_CHANNEL_7
3916 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
3917 * @retval An error_status_t enumeration value:
3918 * - SUCCESS: DMA registers are initialized
3919 * - ERROR: Not applicable
3920 */
3921 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
3922
3923 /**
3924 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
3925 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
3926 * whose fields will be set to default values.
3927 * @retval None
3928 */
3929 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
3930
3931 /** @} */
3932
3933 /** @} */
3934
3935 #endif /* DMA */
3936
3937 #ifdef __cplusplus
3938 }
3939 #endif
3940
3941 #endif /* __GR55xx_LL_DMA_H__ */
3942
3943 /** @} */
3944
3945 /** @} */
3946
3947 /** @} */
ll_dma_clear_flag_err
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3341
ll_dma_get_source_burst_length
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: gr55xx_ll_dma.h:992
_ll_dma_init::mode
uint32_t mode
Specifies the Single block or Multi-block operation mode.
Definition: gr55xx_ll_dma.h:92
ll_dma_get_mode
__STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
Get DMA mode circular or normal.
Definition: gr55xx_ll_dma.h:717
_ll_dma_init::src_address
uint32_t src_address
Specifies the Source base address for DMA transfer.
Definition: gr55xx_ll_dma.h:78
ll_dma_get_source_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: gr55xx_ll_dma.h:772
ll_dma_get_channel_priority_level
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: gr55xx_ll_dma.h:1112
ll_dma_disable_it_err
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: gr55xx_ll_dma.h:3707
ll_dma_clear_flag_srct3
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3113
ll_dma_is_active_flag_dstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2477
ll_dma_clear_flag_tfr0
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:2780
ll_dma_clear_flag_tfr3
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:2825
ll_dma_clear_flag_blk3
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: gr55xx_ll_dma.h:2969
ll_dma_clear_flag_err7
__STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
Clear Channel 7 error flag.
Definition: gr55xx_ll_dma.h:3461
ll_dma_disable_channel
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: gr55xx_ll_dma.h:434
ll_dma_is_active_flag_tfr4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:2120
ll_dma_is_active_flag_dstt3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2537
ll_dma_clear_flag_dstt3
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3257
ll_dma_is_active_flag_blk0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: gr55xx_ll_dma.h:2204
ll_dma_init
error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
ll_dma_is_active_flag_err0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: gr55xx_ll_dma.h:2636
ll_dma_clear_flag_srct
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3053
ll_dma_disable
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: gr55xx_ll_dma.h:369
ll_dma_is_active_flag_err1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: gr55xx_ll_dma.h:2651
ll_dma_clear_flag_err4
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: gr55xx_ll_dma.h:3416
ll_dma_get_source_width
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: gr55xx_ll_dma.h:882
ll_dma_clear_flag_srct1
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3083
ll_dma_get_source_peripheral
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1494
ll_dma_config_transfer
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: gr55xx_ll_dma.h:598
ll_dma_is_active_flag_srct0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2348
ll_dma_get_destination_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: gr55xx_ll_dma.h:827
ll_dma_set_m2m_dst_address
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1356
ll_dma_deinit
error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
ll_dma_is_empty_fifo
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: gr55xx_ll_dma.h:559
ll_dma_clear_flag_srct4
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3128
ll_dma_disable_it_dstt
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3683
ll_dma_clear_flag_blk1
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: gr55xx_ll_dma.h:2939
ll_dma_clear_flag_tfr
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:2765
ll_dma_disable_it_srct
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3659
ll_dma_set_destination_width
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: gr55xx_ll_dma.h:910
ll_dma_clear_flag_dstt4
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3272
ll_dma_is_enabled_channel
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: gr55xx_ll_dma.h:460
ll_dma_get_m2m_src_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1382
ll_dma_get_destination_burst_length
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1047
ll_dma_clear_flag_blk6
__STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
Clear Channel 6 Block Cmplete flag.
Definition: gr55xx_ll_dma.h:3014
ll_dma_is_active_flag_dstt7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
Indicate the status of Channel 7 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2597
ll_dma_clear_flag_err0
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3356
ll_dma_clear_flag_dstt5
__STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
Clear Channel 5 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3287
ll_dma_clear_flag_err3
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3401
ll_dma_is_enable_it_dstt
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3803
ll_dma_clear_flag_tfr1
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:2795
ll_dma_req_src_burst_transaction
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1662
ll_dma_set_source_peripheral
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1451
ll_dma_set_block_size
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: gr55xx_ll_dma.h:1138
ll_dma_set_source_address
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: gr55xx_ll_dma.h:1229
ll_dma_is_active_flag_rdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: gr55xx_ll_dma.h:1997
ll_dma_is_active_flag_dstt0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2492
ll_dma_get_m2m_dst_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1407
ll_dma_is_active_flag_dstt4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2552
ll_dma_is_active_flag_srct7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
Indicate the status of Channel 7 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2453
ll_dma_config_address
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: gr55xx_ll_dma.h:1198
ll_dma_is_active_flag_tfr5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
Indicate the status of Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:2135
ll_dma_is_active_flag_srct5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
Indicate the status of Channel 5 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2423
ll_dma_req_dst_last_single_transaction
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:1792
ll_dma_disable_it_tfr
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:3611
ll_dma_is_active_flag_dstt5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
Indicate the status of Channel 5 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2567
ll_dma_set_destination_increment_mode
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: gr55xx_ll_dma.h:800
ll_dma_is_active_flag_blk1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: gr55xx_ll_dma.h:2219
ll_dma_is_enable_it_blk
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3755
ll_dma_disable_it
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:3875
ll_dma_is_active_flag_srct1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2363
_ll_dma_init
LL DMA init Structure definition.
Definition: gr55xx_ll_dma.h:77
ll_dma_clear_flag_dstt6
__STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
Clear Channel 6 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3302
ll_dma_is_active_flag_err3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: gr55xx_ll_dma.h:2681
ll_dma_is_active_flag_err5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
Indicate the status of Channel 5 error flag.
Definition: gr55xx_ll_dma.h:2711
ll_dma_struct_init
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
ll_dma_is_active_flag_tfr1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:2075
ll_dma_get_destination_address
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: gr55xx_ll_dma.h:1302
ll_dma_is_active_flag_err
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: gr55xx_ll_dma.h:2621
ll_dma_req_src_single_transaction
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: gr55xx_ll_dma.h:1637
ll_dma_clear_flag_tfr2
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:2810
ll_dma_is_enable_it_tfr
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3731
ll_dma_is_active_flag_srct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: gr55xx_ll_dma.h:2333
ll_dma_clear_flag_srct0
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3068
ll_dma_is_active_flag_dstt2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2522
ll_dma_is_active_flag_blk2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: gr55xx_ll_dma.h:2234
ll_dma_enable_it_tfr
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:3491
ll_dma_req_dst_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1766
ll_dma_enable_channel
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: gr55xx_ll_dma.h:410
ll_dma_clear_flag_blk7
__STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
Clear Channel 7 Block Complete flag.
Definition: gr55xx_ll_dma.h:3029
ll_dma_set_source_burst_length
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: gr55xx_ll_dma.h:965
ll_dma_is_active_flag_dstt1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2507
ll_dma_is_active_flag_srct4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2408
ll_dma_is_active_flag_tfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:2045
ll_dma_is_active_flag_srct2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2378
ll_dma_is_active_flag_gsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:1871
ll_dma_is_active_flag_err2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: gr55xx_ll_dma.h:2666
ll_dma_is_active_flag_tfr7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
Indicate the status of Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:2165
_ll_dma_init::block_size
uint32_t block_size
Specifies the number of data to transfer, in data unit.
Definition: gr55xx_ll_dma.h:119
ll_dma_get_source_address
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: gr55xx_ll_dma.h:1278
ll_dma_select_handshaking
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: gr55xx_ll_dma.h:1611
ll_dma_is_active_flag_blk7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
Indicate the status of Channel 7 block complete flag.
Definition: gr55xx_ll_dma.h:2309
_ll_dma_init::src_peripheral
uint32_t src_peripheral
Specifies the Source peripheral type.
Definition: gr55xx_ll_dma.h:125
ll_dma_is_active_flag_blk4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: gr55xx_ll_dma.h:2264
ll_dma_clear_flag_tfr5
__STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
Clear Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:2855
ll_dma_set_destination_peripheral
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1538
ll_dma_get_destination_width
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: gr55xx_ll_dma.h:937
_ll_dma_init::dst_data_width
uint32_t dst_data_width
Specifies the Destination transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:114
ll_dma_is_active_flag_gerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: gr55xx_ll_dma.h:1901
ll_dma_set_source_increment_mode
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: gr55xx_ll_dma.h:745
ll_dma_is_active_flag_gtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: gr55xx_ll_dma.h:1841
ll_dma_set_destination_address
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: gr55xx_ll_dma.h:1254
ll_dma_req_src_last_single_transaction
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:1688
ll_dma_is_active_flag_err7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
Indicate the status of Channel 7 error flag.
Definition: gr55xx_ll_dma.h:2741
ll_dma_is_active_flag_blk6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
Indicate the status of Channel 6 block complete flag.
Definition: gr55xx_ll_dma.h:2294
ll_dma_clear_flag_err5
__STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
Clear Channel 5 error flag.
Definition: gr55xx_ll_dma.h:3431
ll_dma_resume_channel
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: gr55xx_ll_dma.h:511
ll_dma_clear_flag_dstt0
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: gr55xx_ll_dma.h:3212
_ll_dma_init::src_data_width
uint32_t src_data_width
Specifies the Souce transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:109
ll_dma_clear_flag_err2
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3386
ll_dma_set_mode
__STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
Set DMA mode Single block or Multi block.
Definition: gr55xx_ll_dma.h:688
ll_dma_set_m2m_src_address
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1328
ll_dma_is_active_flag_srct6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
Indicate the status of Channel 6 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2438
ll_dma_enable_it_blk
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:3515
_ll_dma_init::direction
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
Definition: gr55xx_ll_dma.h:86
ll_dma_clear_flag_tfr6
__STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
Clear Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:2870
ll_dma_clear_flag_dstt
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3197
ll_dma_enable
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: gr55xx_ll_dma.h:350
ll_dma_clear_flag_blk0
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: gr55xx_ll_dma.h:2924
ll_dma_clear_flag_dstt2
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3242
_ll_dma_init::dst_peripheral
uint32_t dst_peripheral
Specifies the Destination peripheral type.
Definition: gr55xx_ll_dma.h:130
ll_dma_disable_it_blk
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:3635
_ll_dma_init::priority
uint32_t priority
Specifies the channel priority level.
Definition: gr55xx_ll_dma.h:135
ll_dma_is_active_flag_err4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: gr55xx_ll_dma.h:2696
ll_dma_is_active_flag_gdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:1886
ll_dma_req_dst_single_transaction
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: gr55xx_ll_dma.h:1741
ll_dma_get_data_transfer_direction
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:657
ll_dma_enable_it_err
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: gr55xx_ll_dma.h:3587
ll_dma_req_dst_last_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1819
ll_dma_clear_flag_dstt7
__STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
Clear Channel 7 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3317
ll_dma_is_active_flag_err6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
Indicate the status of Channel 6 error flag.
Definition: gr55xx_ll_dma.h:2726
ll_dma_clear_flag_tfr7
__STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
Clear Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:2885
ll_dma_is_active_flag_rerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: gr55xx_ll_dma.h:2021
_ll_dma_init::dst_increment_mode
uint32_t dst_increment_mode
Specifies whether the Destination address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:104
ll_dma_clear_flag_tfr4
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:2840
ll_dma_clear_flag_srct2
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3098
ll_dma_is_enable_it_srct
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3779
_ll_dma_init::dst_address
uint32_t dst_address
Specifies the Destination base address for DMA transfer.
Definition: gr55xx_ll_dma.h:82
ll_dma_clear_flag_srct6
__STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
Clear Channel 6 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3158
ll_dma_clear_flag_err6
__STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
Clear Channel 6 error flag.
Definition: gr55xx_ll_dma.h:3446
ll_dma_clear_flag_srct5
__STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
Clear Channel 5 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3143
ll_dma_is_active_flag_tfr2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:2090
ll_dma_is_active_flag_tfr6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
Indicate the status of Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:2150
ll_dma_is_enable
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: gr55xx_ll_dma.h:384
ll_dma_get_destination_peripheral
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1581
ll_dma_clear_flag_blk2
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: gr55xx_ll_dma.h:2954
ll_dma_set_destination_burst_length
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1020
ll_dma_req_src_last_burst_transaction
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1715
ll_dma_enable_it_dstt
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3563
_ll_dma_init::src_increment_mode
uint32_t src_increment_mode
Specifies whether the Source address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:99
ll_dma_set_data_transfer_direction
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:629
ll_dma_is_active_flag_tfr0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:2060
ll_dma_clear_flag_srct7
__STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
Clear Channel 7 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3173
ll_dma_is_active_flag_tfr3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:2105
ll_dma_is_suspended
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: gr55xx_ll_dma.h:535
ll_dma_init_t
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
ll_dma_clear_flag_blk5
__STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
Clear Channel 5 Block Complete flag.
Definition: gr55xx_ll_dma.h:2999
ll_dma_set_source_width
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: gr55xx_ll_dma.h:855
ll_dma_is_active_flag_rsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: gr55xx_ll_dma.h:1973
ll_dma_clear_flag_blk4
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: gr55xx_ll_dma.h:2984
ll_dma_is_active_flag_blk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:2189
ll_dma_is_active_flag_rtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: gr55xx_ll_dma.h:1925
ll_dma_is_active_flag_dstt6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
Indicate the status of Channel 6 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2582
ll_dma_suspend_channel
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: gr55xx_ll_dma.h:486
ll_dma_clear_flag_dstt1
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3227
ll_dma_clear_flag_blk
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:2909
ll_dma_is_active_flag_blk5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
Indicate the status of Channel 5 block complete flag.
Definition: gr55xx_ll_dma.h:2279
ll_dma_enable_it
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:3851
ll_dma_is_active_flag_blk3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: gr55xx_ll_dma.h:2249
ll_dma_is_active_flag_rblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: gr55xx_ll_dma.h:1949
ll_dma_set_channel_priority_level
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: gr55xx_ll_dma.h:1080
ll_dma_get_block_size
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: gr55xx_ll_dma.h:1164
ll_dma_is_active_flag_gblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: gr55xx_ll_dma.h:1856
ll_dma_enable_it_srct
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3539
ll_dma_is_enable_it_err
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3827
ll_dma_clear_flag_err1
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3371
ll_dma_is_active_flag_srct3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2393