gr55xx_ll_aon_gpio.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
79 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
80
81 uint32_t mode; /**< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
83
84 AON_GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_mode(). */
85
86 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
88
89 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref AON_GPIO_LL_EC_MUX.
93
94 GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_aon_gpio_set_mux_pin_0_7(). */
96
97 uint32_t trigger; /**< Specifies the trigger signal active edge.
98 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
99 } ll_aon_gpio_init_t;
100
101 /** @} */
102
103 /** @} */
104
105 /**
106 * @defgroup AON_GPIO_LL_MACRO Defines
107 * @{
108 */
109
110 /* Exported constants --------------------------------------------------------*/
111 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
112 * @{
113 */
114
115 /** @defgroup AON_GPIO_LL_EC_PIN PIN
116 * @{
117 */
118 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
119 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
120 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
121 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
122 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
123 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
124 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
125 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
126 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
127 /** @} */
128
129 /** @defgroup AON_GPIO_LL_EC_MODE Mode
130 * @{
131 */
132 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U) /**< Select input mode */
133 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /**< Select output mode */
134 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U) /**< Select mux peripheral mode */
135 /** @} */
136
137 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
138 * @{
139 */
140 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N /**< Select I/O no pull */
141 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP /**< Select I/O pull up */
142 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U) /**< Select I/O pull down */
143 /** @} */
144
145 /** @defgroup AON_GPIO_LL_EC_MUX Alternate Function
146 * @{
147 */
148 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
149 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
150 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
151 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
152 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
153 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
154 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
155 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
156 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
157 /** @} */
158
159
160 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
161 * @{
162 */
163 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
164 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
165 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
166 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
167 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
168 /** @} */
169
170 /** @} */
171
172 /* Exported macro ------------------------------------------------------------*/
173 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
174 * @{
175 */
176
177 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
178 * @{
179 */
180
181 /**
182 * @brief Write a value in AON_GPIO register
183 * @param __instance__ AON_GPIO instance
184 * @param __REG__ Register to be written
185 * @param __VALUE__ Value to be written in the register
186 * @retval None
187 */
188 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
189
190 /**
191 * @brief Read a value in AON_GPIO register
192 * @param __instance__ AON_GPIO instance
193 * @param __REG__ Register to be read
194 * @retval Register value
195 */
196 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
197
198 /** @} */
199
200 /** @} */
201
202 /* Private types -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private constants ---------------------------------------------------------*/
205 /* Private macros ------------------------------------------------------------*/
206 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
207 * @{
208 */
209
210 /** @defgroup AON_GPIO_LL_PM_RESISTOR Resistor Enable
211 * @{
212 */
213 #define LL_AON_GPIO_RE_N_Pos AON_PAD_CTL0_GPO_RE_N_Pos /**< Resistor Enable bits position */
214 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
215 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk /**< Resistor Enable bits */
216 /** @} */
217
218 /** @defgroup AON_GPIO_LL_PM_RESISTOR_TYPE Resistor Type
219 * @{
220 */
221 #define LL_AON_GPIO_RTYP_Pos AON_PAD_CTL0_GPO_RTYPE_Pos /**< Resistor Type bits position */
222 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
223 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk /**< Resistor Type bits */
224 /** @} */
225
226 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
227 * @{
228 */
229
230 /**
231 * @brief LL AON_GPIO InitStrcut default configuartion
232 */
233 #define LL_AON_GPIO_DEFAULT_CONFIG \
234 { \
235 .pin = LL_AON_GPIO_PIN_ALL, \
236 .mode = LL_AON_GPIO_MODE_INPUT, \
237 .pull = LL_AON_GPIO_PULL_DOWN, \
238 .mux = LL_AON_GPIO_MUX_7, \
239 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
240 }
241 /** @} */
242
243 /** @} */
244
245 /** @} */
246
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
249 * @{
250 */
251
252 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
253 * @{
254 */
255
256 /**
257 * @brief Set several AON_GPIO pins to input/output mode.
258 *
259 * Register|BitsName
260 * --------|--------
261 * AON_PAD_CTL1 | AON_GPO_OE_N
262 *
263 * @param pin_mask This parameter can be a combination of the following values:
264 * @arg @ref LL_AON_GPIO_PIN_0
265 * @arg @ref LL_AON_GPIO_PIN_1
266 * @arg @ref LL_AON_GPIO_PIN_2
267 * @arg @ref LL_AON_GPIO_PIN_3
268 * @arg @ref LL_AON_GPIO_PIN_4
269 * @arg @ref LL_AON_GPIO_PIN_5
270 * @arg @ref LL_AON_GPIO_PIN_6
271 * @arg @ref LL_AON_GPIO_PIN_7
272 * @arg @ref LL_AON_GPIO_PIN_ALL
273 * @param mode This parameter can be one of the following values:
274 * @arg @ref LL_AON_GPIO_MODE_INPUT
275 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
276 * @retval None
277 */
278 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
279 {
280 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
281 GLOBAL_EXCEPTION_DISABLE();
282 MODIFY_REG(AON->AON_PAD_CTL1, pin_mask, (mode == LL_AON_GPIO_MODE_INPUT) ? pin_mask : 0);
283 GLOBAL_EXCEPTION_ENABLE();
284 }
285
286 /**
287 * @brief Return gpio mode for a AON_GPIO pin.
288 * @note I/O mode can be Input mode. General purpose output.
289 * @note Warning: only one pin can be passed as parameter.
290 *
291 * Register|BitsName
292 * --------|--------
293 * AON_PAD_CTL1 | AON_GPO_OE_N
294 *
295 * @param pin This parameter can be one of the following values:
296 * @arg @ref LL_AON_GPIO_PIN_0
297 * @arg @ref LL_AON_GPIO_PIN_1
298 * @arg @ref LL_AON_GPIO_PIN_2
299 * @arg @ref LL_AON_GPIO_PIN_3
300 * @arg @ref LL_AON_GPIO_PIN_4
301 * @arg @ref LL_AON_GPIO_PIN_5
302 * @arg @ref LL_AON_GPIO_PIN_6
303 * @arg @ref LL_AON_GPIO_PIN_7
304 * @retval Returned value can be one of the following values:
305 * @arg @ref LL_AON_GPIO_MODE_INPUT
306 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
307 */
308 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
309 {
310 pin = (pin << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
311 return ((uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin) == LL_AON_GPIO_MODE_INPUT) ?
312 LL_AON_GPIO_MODE_OUTPUT : LL_AON_GPIO_MODE_INPUT);
313 }
314
315 /**
316 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
317 * @note Warning: only one pin can be passed as parameter.
318 *
319 * Register|BitsName
320 * --------|--------
321 * AON_PAD_CTL0 | GPO_RE_N
322 * AON_PAD_CTL0 | GPO_RTYPE
323 *
324 * @param pin_mask This parameter can be a combination of the following values:
325 * @arg @ref LL_AON_GPIO_PIN_0
326 * @arg @ref LL_AON_GPIO_PIN_1
327 * @arg @ref LL_AON_GPIO_PIN_2
328 * @arg @ref LL_AON_GPIO_PIN_3
329 * @arg @ref LL_AON_GPIO_PIN_4
330 * @arg @ref LL_AON_GPIO_PIN_5
331 * @arg @ref LL_AON_GPIO_PIN_6
332 * @arg @ref LL_AON_GPIO_PIN_7
333 * @arg @ref LL_AON_GPIO_PIN_ALL
334 * @param pull This parameter can be one of the following values:
335 * @arg @ref LL_AON_GPIO_PULL_NO
336 * @arg @ref LL_AON_GPIO_PULL_UP
337 * @arg @ref LL_AON_GPIO_PULL_DOWN
338 * @retval None
339 */
340 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
341 {
342 uint32_t RTypeMask = (pin_mask << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
343 uint32_t REnMask = (pin_mask << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
344 uint32_t RType = (pull == LL_AON_GPIO_PULL_UP) ? RTypeMask : 0x0000U;
345 uint32_t REn = (pull == LL_AON_GPIO_PULL_NO) ? REnMask : 0x0000U;
346 MODIFY_REG(AON->AON_PAD_CTL0, REnMask | RTypeMask, REn | RType);
347 }
348
349 /**
350 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
351 * @note Warning: only one pin can be passed as parameter.
352 *
353 * Register|BitsName
354 * --------|--------
355 * AON_PAD_CTL0 | GPO_RE_N
356 * AON_PAD_CTL0 | GPO_RTYPE
357 *
358 * @param pin This parameter can be one of the following values:
359 * @arg @ref LL_AON_GPIO_PIN_0
360 * @arg @ref LL_AON_GPIO_PIN_1
361 * @arg @ref LL_AON_GPIO_PIN_2
362 * @arg @ref LL_AON_GPIO_PIN_3
363 * @arg @ref LL_AON_GPIO_PIN_4
364 * @arg @ref LL_AON_GPIO_PIN_5
365 * @arg @ref LL_AON_GPIO_PIN_6
366 * @arg @ref LL_AON_GPIO_PIN_7
367 * @retval Returned value can be one of the following values:
368 * @arg @ref LL_AON_GPIO_PULL_NO
369 * @arg @ref LL_AON_GPIO_PULL_UP
370 * @arg @ref LL_AON_GPIO_PULL_DOWN
371 */
372 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
373 {
374 uint32_t RTypeMask = (pin << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
375 uint32_t REnMask = (pin << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
376 //return (READ_BITS(AON->AON_PAD_CTL0, REnMask | RTypeMask) >> POSITION_VAL(Pin));
377 return ((READ_BITS(AON->AON_PAD_CTL0, REnMask) != RESET) ? LL_AON_GPIO_PULL_NO :
378 ((READ_BITS(AON->AON_PAD_CTL0, RTypeMask) != RESET) ? LL_AON_GPIO_PULL_UP : LL_AON_GPIO_PULL_DOWN));
379 }
380
381 /**
382 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
383 * @note Possible values are from AF0 to AF15 depending on target.
384 * @note Warning: only one pin can be passed as parameter.
385 *
386 * Register|BitsName
387 * --------|--------
388 * AON_PAD_MUX_CTRL | CTRL0_7
389 * AON_PAD_CTL_0 | MCU_OVR
390 *
391 * @param pin This parameter can be one of the following values:
392 * @arg @ref LL_AON_GPIO_PIN_0
393 * @arg @ref LL_AON_GPIO_PIN_1
394 * @arg @ref LL_AON_GPIO_PIN_2
395 * @arg @ref LL_AON_GPIO_PIN_3
396 * @arg @ref LL_AON_GPIO_PIN_4
397 * @arg @ref LL_AON_GPIO_PIN_5
398 * @arg @ref LL_AON_GPIO_PIN_6
399 * @arg @ref LL_AON_GPIO_PIN_7
400 * @param mux This parameter can be one of the following values:
401 * @arg @ref LL_AON_GPIO_MUX_0
402 * @arg @ref LL_AON_GPIO_MUX_1
403 * @arg @ref LL_AON_GPIO_MUX_2
404 * @arg @ref LL_AON_GPIO_MUX_3
405 * @arg @ref LL_AON_GPIO_MUX_4
406 * @arg @ref LL_AON_GPIO_MUX_5
407 * @arg @ref LL_AON_GPIO_MUX_6
408 * @arg @ref LL_AON_GPIO_MUX_7
409 * @arg @ref LL_AON_GPIO_MUX_8
410 * @retval None
411 */
412 __STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
413 {
414 uint32_t pos = POSITION_VAL(pin) << 2;
415 if(LL_AON_GPIO_MUX_7 == mux)
416 {
417 CLEAR_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
418 }
419 else
420 {
421 MODIFY_REG(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
422 SET_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
423 }
424 }
425
426 /**
427 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
428 *
429 * Register|BitsName
430 * --------|--------
431 * AON_PAD_MUX_CTRL | CTRL0_7
432 * AON_PAD_CTL_0 | MCU_OVR
433 *
434 * @param pin This parameter can be one of the following values:
435 * @arg @ref LL_AON_GPIO_PIN_0
436 * @arg @ref LL_AON_GPIO_PIN_1
437 * @arg @ref LL_AON_GPIO_PIN_2
438 * @arg @ref LL_AON_GPIO_PIN_3
439 * @arg @ref LL_AON_GPIO_PIN_4
440 * @arg @ref LL_AON_GPIO_PIN_5
441 * @arg @ref LL_AON_GPIO_PIN_6
442 * @arg @ref LL_AON_GPIO_PIN_7
443 * @retval Returned value can be one of the following values:
444 * @arg @ref LL_AON_GPIO_MUX_0
445 * @arg @ref LL_AON_GPIO_MUX_1
446 * @arg @ref LL_AON_GPIO_MUX_2
447 * @arg @ref LL_AON_GPIO_MUX_3
448 * @arg @ref LL_AON_GPIO_MUX_4
449 * @arg @ref LL_AON_GPIO_MUX_5
450 * @arg @ref LL_AON_GPIO_MUX_6
451 * @arg @ref LL_AON_GPIO_MUX_7
452 * @arg @ref LL_AON_GPIO_MUX_8
453 */
454 __STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
455 {
456 if(READ_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos))
457 {
458 uint32_t pos = POSITION_VAL(pin) << 2;
459 return (READ_BITS(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
460 }
461 else
462 {
463 return LL_AON_GPIO_MUX_7;
464 }
465 }
466
467 /**
468 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
469 *
470 * Register|BitsName
471 * --------|--------
472 * PWR_RET01 | XO_2MHZ_ENA
473 *
474 * @retval None
475 */
476 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
477 {
478 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
479 }
480
481 /**
482 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
483 *
484 * Register|BitsName
485 * --------|--------
486 * PWR_RET01 | XO_2MHZ_ENA
487 *
488 * @retval None
489 */
490 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
491 {
492 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
493 }
494
495 /**
496 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
497 *
498 * Register|BitsName
499 * --------|--------
500 * PWR_RET01 | XO_2MHZ_ENA
501 *
502 * @retval None
503 */
504 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
505 {
506 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA) == AON_PWR_REG01_XO_2MHZ_ENA);
507 }
508
509 /** @} */
510
511 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
512 * @{
513 */
514
515 /**
516 * @brief Return full input data register value of AON_GPIO.
517 *
518 * Register|BitsName
519 * --------|--------
520 * AON_PAD_CTL1 | O_AON_GPI
521 *
522 * @retval Input data register value of port
523 */
524 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
525 {
526 return (uint32_t)(READ_BITS(GPIO2->DATA, GPIO_DATA));
527 }
528
529 /**
530 * @brief Return if input data level of several AON_GPIO pins is high or low.
531 *
532 * Register|BitsName
533 * --------|--------
534 * AON_PAD_CTL1 | O_AON_GPI
535 *
536 * @param pin_mask This parameter can be a combination of the following values:
537 * @arg @ref LL_AON_GPIO_PIN_0
538 * @arg @ref LL_AON_GPIO_PIN_1
539 * @arg @ref LL_AON_GPIO_PIN_2
540 * @arg @ref LL_AON_GPIO_PIN_3
541 * @arg @ref LL_AON_GPIO_PIN_4
542 * @arg @ref LL_AON_GPIO_PIN_5
543 * @arg @ref LL_AON_GPIO_PIN_6
544 * @arg @ref LL_AON_GPIO_PIN_7
545 * @arg @ref LL_AON_GPIO_PIN_ALL
546 * @retval State of bit (1 or 0).
547 */
548 __STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
549 {
550 return (uint32_t)(READ_BITS(GPIO2->DATA, pin_mask) == pin_mask);
551 }
552
553 /**
554 * @brief Write output data register of AON_GPIO.
555 *
556 * Register|BitsName
557 * --------|--------
558 * AON_PAD_CTL1 | AON_GPO
559 *
560 * @param port_value Level value for each pin of the port
561 * @retval None
562 */
563 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
564 {
565 GLOBAL_EXCEPTION_DISABLE();
566 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO, (port_value << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
567 GLOBAL_EXCEPTION_ENABLE();
568 }
569
570 /**
571 * @brief Return full output data register value of AON_GPIO.
572 *
573 * Register|BitsName
574 * --------|--------
575 * AON_PAD_CTL1 | AON_GPO
576 *
577 * @retval Output data register value of port
578 */
579 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
580 {
581 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO) >> AON_PAD_CTL1_AON_GPO_Pos);
582 }
583
584 /**
585 * @brief Return if input data level of several AON_GPIO pins is high or low.
586 *
587 * Register|BitsName
588 * --------|--------
589 * AON_PAD_CTL1 | AON_GPO
590 *
591 * @param pin_mask This parameter can be a combination of the following values:
592 * @arg @ref LL_AON_GPIO_PIN_0
593 * @arg @ref LL_AON_GPIO_PIN_1
594 * @arg @ref LL_AON_GPIO_PIN_2
595 * @arg @ref LL_AON_GPIO_PIN_3
596 * @arg @ref LL_AON_GPIO_PIN_4
597 * @arg @ref LL_AON_GPIO_PIN_5
598 * @arg @ref LL_AON_GPIO_PIN_6
599 * @arg @ref LL_AON_GPIO_PIN_7
600 * @arg @ref LL_AON_GPIO_PIN_ALL
601 * @retval State of bit (1 or 0).
602 */
603 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
604 {
605 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO;
606 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin_mask) == pin_mask);
607 }
608
609 /**
610 * @brief Set specified AON_GPIO pins to high level
611 *
612 * Register|BitsName
613 * --------|--------
614 * AON_PAD_CTL1 | AON_GPO
615 *
616 * @param pin_mask This parameter can be a combination of the following values:
617 * @arg @ref LL_AON_GPIO_PIN_0
618 * @arg @ref LL_AON_GPIO_PIN_1
619 * @arg @ref LL_AON_GPIO_PIN_2
620 * @arg @ref LL_AON_GPIO_PIN_3
621 * @arg @ref LL_AON_GPIO_PIN_4
622 * @arg @ref LL_AON_GPIO_PIN_5
623 * @arg @ref LL_AON_GPIO_PIN_6
624 * @arg @ref LL_AON_GPIO_PIN_7
625 * @arg @ref LL_AON_GPIO_PIN_ALL
626 * @retval None
627 */
628 __STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
629 {
630 GLOBAL_EXCEPTION_DISABLE();
631 SET_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
632 GLOBAL_EXCEPTION_ENABLE();
633 }
634
635 /**
636 * @brief Set specified AON_GPIO pins to low level.
637 *
638 * Register|BitsName
639 * --------|--------
640 * AON_PAD_CTL1 | AON_GPO
641 *
642 * @param pin_mask This parameter can be a combination of the following values:
643 * @arg @ref LL_AON_GPIO_PIN_0
644 * @arg @ref LL_AON_GPIO_PIN_1
645 * @arg @ref LL_AON_GPIO_PIN_2
646 * @arg @ref LL_AON_GPIO_PIN_3
647 * @arg @ref LL_AON_GPIO_PIN_4
648 * @arg @ref LL_AON_GPIO_PIN_5
649 * @arg @ref LL_AON_GPIO_PIN_6
650 * @arg @ref LL_AON_GPIO_PIN_7
651 * @arg @ref LL_AON_GPIO_PIN_ALL
652 * @retval None
653 */
654 __STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
655 {
656 GLOBAL_EXCEPTION_DISABLE();
657 CLEAR_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
658 GLOBAL_EXCEPTION_ENABLE();
659 }
660
661 /**
662 * @brief Toggle data value of specified AON_GPIO pins.
663 *
664 * Register|BitsName
665 * --------|--------
666 * AON_PAD_CTL1 | AON_GPO
667 *
668 * @param pin_mask This parameter can be a combination of the following values:
669 * @arg @ref LL_AON_GPIO_PIN_0
670 * @arg @ref LL_AON_GPIO_PIN_1
671 * @arg @ref LL_AON_GPIO_PIN_2
672 * @arg @ref LL_AON_GPIO_PIN_3
673 * @arg @ref LL_AON_GPIO_PIN_4
674 * @arg @ref LL_AON_GPIO_PIN_5
675 * @arg @ref LL_AON_GPIO_PIN_6
676 * @arg @ref LL_AON_GPIO_PIN_7
677 * @arg @ref LL_AON_GPIO_PIN_ALL
678 * @retval None
679 */
680 __STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
681 {
682 GLOBAL_EXCEPTION_DISABLE();
683 WRITE_REG(AON->AON_PAD_CTL1, (READ_REG(AON->AON_PAD_CTL1) ^ ((pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO)));
684 GLOBAL_EXCEPTION_ENABLE();
685 }
686
687 /** @} */
688
689 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
690 * @{
691 */
692
693 /**
694 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
695 *
696 * Register|BitsName
697 * --------|--------
698 * INTPOLCLR | INTPOLCLR
699 * INTTYPESET | INTTYPESET
700 *
701 * @param pin_mask This parameter can be a combination of the following values:
702 * @arg @ref LL_AON_GPIO_PIN_0
703 * @arg @ref LL_AON_GPIO_PIN_1
704 * @arg @ref LL_AON_GPIO_PIN_2
705 * @arg @ref LL_AON_GPIO_PIN_3
706 * @arg @ref LL_AON_GPIO_PIN_4
707 * @arg @ref LL_AON_GPIO_PIN_5
708 * @arg @ref LL_AON_GPIO_PIN_6
709 * @arg @ref LL_AON_GPIO_PIN_7
710 * @arg @ref LL_AON_GPIO_PIN_ALL
711 * @retval None
712 */
713 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
714 {
715 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
716 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
717 }
718
719 /**
720 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
721 *
722 * Register|BitsName
723 * --------|--------
724 * INTPOLCLR | INTPOLCLR
725 * INTTYPESET | INTTYPESET
726 *
727 * @param pin_mask This parameter can be a combination of the following values:
728 * @arg @ref LL_AON_GPIO_PIN_0
729 * @arg @ref LL_AON_GPIO_PIN_1
730 * @arg @ref LL_AON_GPIO_PIN_2
731 * @arg @ref LL_AON_GPIO_PIN_3
732 * @arg @ref LL_AON_GPIO_PIN_4
733 * @arg @ref LL_AON_GPIO_PIN_5
734 * @arg @ref LL_AON_GPIO_PIN_6
735 * @arg @ref LL_AON_GPIO_PIN_7
736 * @arg @ref LL_AON_GPIO_PIN_ALL
737 * @retval State of bit (1 or 0).
738 */
739 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
740 {
741 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
742 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
743 }
744
745 /**
746 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
747 *
748 * Register|BitsName
749 * --------|--------
750 * INTPOLSET | INTPOLSET
751 * INTTYPESET | INTTYPESET
752 *
753 * @param pin_mask This parameter can be a combination of the following values:
754 * @arg @ref LL_AON_GPIO_PIN_0
755 * @arg @ref LL_AON_GPIO_PIN_1
756 * @arg @ref LL_AON_GPIO_PIN_2
757 * @arg @ref LL_AON_GPIO_PIN_3
758 * @arg @ref LL_AON_GPIO_PIN_4
759 * @arg @ref LL_AON_GPIO_PIN_5
760 * @arg @ref LL_AON_GPIO_PIN_6
761 * @arg @ref LL_AON_GPIO_PIN_7
762 * @arg @ref LL_AON_GPIO_PIN_ALL
763 * @retval None
764 */
765 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
766 {
767 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
768 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
769 }
770
771 /**
772 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
773 * @note Please check each device line mapping for AON_GPIO Line availability
774 *
775 * Register|BitsName
776 * --------|--------
777 * INTPOLSET | INTPOLSET
778 * INTTYPESET | INTTYPESET
779 *
780 * @param pin_mask This parameter can be a combination of the following values:
781 * @arg @ref LL_AON_GPIO_PIN_0
782 * @arg @ref LL_AON_GPIO_PIN_1
783 * @arg @ref LL_AON_GPIO_PIN_2
784 * @arg @ref LL_AON_GPIO_PIN_3
785 * @arg @ref LL_AON_GPIO_PIN_4
786 * @arg @ref LL_AON_GPIO_PIN_5
787 * @arg @ref LL_AON_GPIO_PIN_6
788 * @arg @ref LL_AON_GPIO_PIN_7
789 * @arg @ref LL_AON_GPIO_PIN_ALL
790 * @retval State of bit (1 or 0).
791 */
792 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
793 {
794 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
795 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
796 }
797
798 /**
799 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
800 *
801 * Register|BitsName
802 * --------|--------
803 * INTPOLSET | INTPOLSET
804 * INTTYPECLR | INTTYPECLR
805 *
806 * @param pin_mask This parameter can be a combination of the following values:
807 * @arg @ref LL_AON_GPIO_PIN_0
808 * @arg @ref LL_AON_GPIO_PIN_1
809 * @arg @ref LL_AON_GPIO_PIN_2
810 * @arg @ref LL_AON_GPIO_PIN_3
811 * @arg @ref LL_AON_GPIO_PIN_4
812 * @arg @ref LL_AON_GPIO_PIN_5
813 * @arg @ref LL_AON_GPIO_PIN_6
814 * @arg @ref LL_AON_GPIO_PIN_7
815 * @arg @ref LL_AON_GPIO_PIN_ALL
816 * @retval None
817 */
818 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
819 {
820 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
821 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
822 }
823
824 /**
825 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
826 *
827 * Register|BitsName
828 * --------|--------
829 * INTPOLSET | INTPOLSET
830 * INTTYPECLR | INTTYPECLR
831 *
832 * @param pin_mask This parameter can be a combination of the following values:
833 * @arg @ref LL_AON_GPIO_PIN_0
834 * @arg @ref LL_AON_GPIO_PIN_1
835 * @arg @ref LL_AON_GPIO_PIN_2
836 * @arg @ref LL_AON_GPIO_PIN_3
837 * @arg @ref LL_AON_GPIO_PIN_4
838 * @arg @ref LL_AON_GPIO_PIN_5
839 * @arg @ref LL_AON_GPIO_PIN_6
840 * @arg @ref LL_AON_GPIO_PIN_7
841 * @arg @ref LL_AON_GPIO_PIN_ALL
842 * @retval State of bit (1 or 0).
843 */
844 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
845 {
846 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
847 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
848 }
849
850 /**
851 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
852 *
853 * Register|BitsName
854 * --------|--------
855 * INTPOLCLR | INTPOLCLR
856 * INTTYPECLR | INTTYPECLR
857 *
858 * @param pin_mask This parameter can be a combination of the following values:
859 * @arg @ref LL_AON_GPIO_PIN_0
860 * @arg @ref LL_AON_GPIO_PIN_1
861 * @arg @ref LL_AON_GPIO_PIN_2
862 * @arg @ref LL_AON_GPIO_PIN_3
863 * @arg @ref LL_AON_GPIO_PIN_4
864 * @arg @ref LL_AON_GPIO_PIN_5
865 * @arg @ref LL_AON_GPIO_PIN_6
866 * @arg @ref LL_AON_GPIO_PIN_7
867 * @arg @ref LL_AON_GPIO_PIN_ALL
868 * @retval None
869 */
870 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
871 {
872 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
873 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
874 }
875
876 /**
877 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
878 *
879 * Register|BitsName
880 * --------|--------
881 * INTPOLCLR | INTPOLCLR
882 * INTTYPECLR | INTTYPECLR
883 *
884 * @param pin_mask This parameter can be a combination of the following values:
885 * @arg @ref LL_AON_GPIO_PIN_0
886 * @arg @ref LL_AON_GPIO_PIN_1
887 * @arg @ref LL_AON_GPIO_PIN_2
888 * @arg @ref LL_AON_GPIO_PIN_3
889 * @arg @ref LL_AON_GPIO_PIN_4
890 * @arg @ref LL_AON_GPIO_PIN_5
891 * @arg @ref LL_AON_GPIO_PIN_6
892 * @arg @ref LL_AON_GPIO_PIN_7
893 * @arg @ref LL_AON_GPIO_PIN_ALL
894 * @retval State of bit (1 or 0).
895 */
896 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
897 {
898 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
899 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
900 }
901
902 /**
903 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
904 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
905 *
906 * Register|BitsName
907 * --------|--------
908 * INTENSET | INTENSET
909 *
910 * @param pin_mask This parameter can be a combination of the following values:
911 * @arg @ref LL_AON_GPIO_PIN_0
912 * @arg @ref LL_AON_GPIO_PIN_1
913 * @arg @ref LL_AON_GPIO_PIN_2
914 * @arg @ref LL_AON_GPIO_PIN_3
915 * @arg @ref LL_AON_GPIO_PIN_4
916 * @arg @ref LL_AON_GPIO_PIN_5
917 * @arg @ref LL_AON_GPIO_PIN_6
918 * @arg @ref LL_AON_GPIO_PIN_7
919 * @arg @ref LL_AON_GPIO_PIN_ALL
920 * @retval None
921 */
922 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
923 {
924 WRITE_REG(GPIO2->INTENSET, pin_mask);
925 }
926
927 /**
928 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
929 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
930 *
931 * Register|BitsName
932 * --------|--------
933 * INTENCLR | INTENCLR
934 *
935 * @param pin_mask This parameter can be a combination of the following values:
936 * @arg @ref LL_AON_GPIO_PIN_0
937 * @arg @ref LL_AON_GPIO_PIN_1
938 * @arg @ref LL_AON_GPIO_PIN_2
939 * @arg @ref LL_AON_GPIO_PIN_3
940 * @arg @ref LL_AON_GPIO_PIN_4
941 * @arg @ref LL_AON_GPIO_PIN_5
942 * @arg @ref LL_AON_GPIO_PIN_6
943 * @arg @ref LL_AON_GPIO_PIN_7
944 * @arg @ref LL_AON_GPIO_PIN_ALL
945 * @retval None
946 */
947 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
948 {
949 WRITE_REG(GPIO2->INTENCLR, pin_mask);
950 }
951
952 /**
953 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
954 *
955 * Register|BitsName
956 * --------|--------
957 * INTENSET | INTENSET
958 *
959 * @param pin_mask This parameter can be a combination of the following values:
960 * @arg @ref LL_AON_GPIO_PIN_0
961 * @arg @ref LL_AON_GPIO_PIN_1
962 * @arg @ref LL_AON_GPIO_PIN_2
963 * @arg @ref LL_AON_GPIO_PIN_3
964 * @arg @ref LL_AON_GPIO_PIN_4
965 * @arg @ref LL_AON_GPIO_PIN_5
966 * @arg @ref LL_AON_GPIO_PIN_6
967 * @arg @ref LL_AON_GPIO_PIN_7
968 * @arg @ref LL_AON_GPIO_PIN_ALL
969 * @retval State of bit (1 or 0).
970 */
971 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
972 {
973 return (READ_BITS(GPIO2->INTENSET, pin_mask) == (pin_mask));
974 }
975
976 /** @} */
977
978 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
979 * @{
980 */
981
982 /**
983 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
984 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
985 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
986 *
987 * Register|BitsName
988 * --------|--------
989 * INTSTATUS | INTSTATUS
990 *
991 * @param pin_mask This parameter can be a combination of the following values:
992 * @arg @ref LL_AON_GPIO_PIN_0
993 * @arg @ref LL_AON_GPIO_PIN_1
994 * @arg @ref LL_AON_GPIO_PIN_2
995 * @arg @ref LL_AON_GPIO_PIN_3
996 * @arg @ref LL_AON_GPIO_PIN_4
997 * @arg @ref LL_AON_GPIO_PIN_5
998 * @arg @ref LL_AON_GPIO_PIN_6
999 * @arg @ref LL_AON_GPIO_PIN_7
1000 * @arg @ref LL_AON_GPIO_PIN_ALL
1001 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1002 */
1003 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1004 {
1005 uint32_t ext2 = READ_BITS(GPIO2->INTSTAT, pin_mask);
1006 uint32_t wkup = (READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1007 pin_mask & READ_BITS(AON->EXT_WKUP_CTL, LL_AON_GPIO_PIN_ALL);
1008 return (uint32_t)(ext2 | wkup);
1009 }
1010
1011 /**
1012 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1013 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1014 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1015 *
1016 * Register|BitsName
1017 * --------|--------
1018 * INTSTATUS | INTSTATUS
1019 *
1020 * @param pin_mask This parameter can be a combination of the following values:
1021 * @arg @ref LL_AON_GPIO_PIN_0
1022 * @arg @ref LL_AON_GPIO_PIN_1
1023 * @arg @ref LL_AON_GPIO_PIN_2
1024 * @arg @ref LL_AON_GPIO_PIN_3
1025 * @arg @ref LL_AON_GPIO_PIN_4
1026 * @arg @ref LL_AON_GPIO_PIN_5
1027 * @arg @ref LL_AON_GPIO_PIN_6
1028 * @arg @ref LL_AON_GPIO_PIN_7
1029 * @arg @ref LL_AON_GPIO_PIN_ALL
1030 * @retval State of bit (1 or 0).
1031 */
1032 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1033 {
1034 return (READ_BITS(GPIO2->INTSTAT, pin_mask) == pin_mask);
1035 }
1036
1037 /**
1038 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1039 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1040 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1041 *
1042 * Register|BitsName
1043 * --------|--------
1044 * INTSTATUS | INTSTATUS
1045 *
1046 * @param pin_mask This parameter can be a combination of the following values:
1047 * @arg @ref LL_AON_GPIO_PIN_0
1048 * @arg @ref LL_AON_GPIO_PIN_1
1049 * @arg @ref LL_AON_GPIO_PIN_2
1050 * @arg @ref LL_AON_GPIO_PIN_3
1051 * @arg @ref LL_AON_GPIO_PIN_4
1052 * @arg @ref LL_AON_GPIO_PIN_5
1053 * @arg @ref LL_AON_GPIO_PIN_6
1054 * @arg @ref LL_AON_GPIO_PIN_7
1055 * @arg @ref LL_AON_GPIO_PIN_ALL
1056 * @retval None
1057 */
1058 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1059 {
1060 WRITE_REG(GPIO2->INTSTAT, pin_mask);
1061 }
1062
1063 /** @} */
1064
1065 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1066 * @{
1067 */
1068
1069 /**
1070 * @brief De-initialize AON_GPIO registers (Registers restored to their default values).
1071 * @retval An error_status_t enumeration value:
1072 * - SUCCESS: AON_GPIO registers are de-initialized
1073 * - ERROR: AON_GPIO registers are not de-initialized
1074 */
1075 error_status_t ll_aon_gpio_deinit(void);
1076
1077 /**
1078 * @brief Initialize AON_GPIO registers according to the specified.
1079 * parameters in p_aon_gpio_init.
1080 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1081 * information for the specified AON_GPIO peripheral.
1082 * @retval An error_status_t enumeration value:
1083 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1084 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1085 */
1086 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1087
1088 /**
1089 * @brief Set each field of a @ref ll_aon_gpio_init_t type structure to default value.
1090 * @param p_aon_gpio_init Pointer to a @ref ll_aon_gpio_init_t structure
1091 * whose fields will be set to default values.
1092 * @retval None
1093 */
1094 void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1095
1096 /** @} */
1097
1098 /** @} */
1099
1100 #endif /* AON */
1101
1102 #ifdef __cplusplus
1103 }
1104 #endif
1105
1106 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1107
1108 /** @} */
1109
1110 /** @} */
1111
1112 /** @} */
LL_AON_GPIO_PULL_UP
#define LL_AON_GPIO_PULL_UP
Select I/O pull up.
Definition: gr55xx_ll_aon_gpio.h:141
LL_AON_GPIO_PIN_ALL
#define LL_AON_GPIO_PIN_ALL
Select all pins.
Definition: gr55xx_ll_aon_gpio.h:126
_ll_aon_gpio_init::pull
uint32_t pull
Specifies the operating Pull-up/Pull down for the selected pins.
Definition: gr55xx_ll_aon_gpio.h:86
ll_aon_gpio_disable_it
__STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
Disable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:947
ll_aon_gpio_is_enabled_xo_2mhz_output
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:504
ll_aon_gpio_set_pin_pull
__STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:340
ll_aon_gpio_clear_flag_it
__STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
Clear Interrupt Status flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1058
ll_aon_gpio_struct_init
void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Set each field of a ll_aon_gpio_init_t type structure to default value.
ll_aon_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:971
ll_aon_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:603
ll_aon_gpio_reset_output_pin
__STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to low level.
Definition: gr55xx_ll_aon_gpio.h:654
ll_aon_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1032
ll_aon_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:372
ll_aon_gpio_write_output_port
__STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
Write output data register of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:563
LL_AON_GPIO_MODE_OUTPUT
#define LL_AON_GPIO_MODE_OUTPUT
Select output mode.
Definition: gr55xx_ll_aon_gpio.h:133
ll_aon_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:548
ll_aon_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:412
ll_aon_gpio_enable_low_trigger
__STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:870
LL_AON_GPIO_PULL_DOWN
#define LL_AON_GPIO_PULL_DOWN
Select I/O pull down.
Definition: gr55xx_ll_aon_gpio.h:142
ll_aon_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
Return gpio mode for a AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:308
ll_aon_gpio_enable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
Enable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:476
LL_AON_GPIO_MODE_INPUT
#define LL_AON_GPIO_MODE_INPUT
Select input mode.
Definition: gr55xx_ll_aon_gpio.h:132
_ll_aon_gpio_init::mode
uint32_t mode
Specifies the operating mode for the selected pins.
Definition: gr55xx_ll_aon_gpio.h:81
ll_aon_gpio_disable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
Disable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:490
ll_aon_gpio_toggle_pin
__STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:680
ll_aon_gpio_enable_falling_trigger
__STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:713
_ll_aon_gpio_init::trigger
uint32_t trigger
Specifies the trigger signal active edge.
Definition: gr55xx_ll_aon_gpio.h:97
_ll_aon_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_aon_gpio.h:91
ll_aon_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:454
LL_AON_GPIO_MUX_7
#define LL_AON_GPIO_MUX_7
Definition: gr55xx_ll_aon_gpio.h:155
ll_aon_gpio_set_output_pin
__STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to high level.
Definition: gr55xx_ll_aon_gpio.h:628
_ll_aon_gpio_init
LL AON_GPIO init Structure definition.
Definition: gr55xx_ll_aon_gpio.h:77
ll_aon_gpio_deinit
error_status_t ll_aon_gpio_deinit(void)
De-initialize AON_GPIO registers (Registers restored to their default values).
ll_aon_gpio_enable_high_trigger
__STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:818
_ll_aon_gpio_init::pin
uint32_t pin
Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
Definition: gr55xx_ll_aon_gpio.h:78
ll_aon_gpio_read_input_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
Return full input data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:524
ll_aon_gpio_init
error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Initialize AON_GPIO registers according to the specified.
LL_AON_GPIO_PULL_NO
#define LL_AON_GPIO_PULL_NO
Select I/O no pull.
Definition: gr55xx_ll_aon_gpio.h:140
ll_aon_gpio_read_output_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
Return full output data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:579
ll_aon_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
Check if high level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:844
ll_aon_gpio_set_pin_mode
__STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several AON_GPIO pins to input/output mode.
Definition: gr55xx_ll_aon_gpio.h:278
ll_aon_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
Check if falling edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:739
ll_aon_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1003
ll_aon_gpio_init_t
struct _ll_aon_gpio_init ll_aon_gpio_init_t
LL AON_GPIO init Structure definition.
ll_aon_gpio_enable_it
__STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
Enable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:922
ll_aon_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
Check if low level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:896
ll_aon_gpio_enable_rising_trigger
__STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:765
ll_aon_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
Check if rising edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:792