gr55xx_ll_msio.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL MSIO init Structure definition
75 */
76 typedef struct _ll_msio_init
77 {
78 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
79 This parameter can be any value of @ref MSIO_LL_EC_PIN */
80
81 uint32_t direction; /**< Specifies the direction for the selected pins.
82 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
83
84 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_direction(). */
85
86 uint32_t mode; /**< Specifies the operating mode for the selected pins.
87 This parameter can be a value of @ref MSIO_LL_EC_MODE.
88
89 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_mode(). */
90
91 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
92 This parameter can be a value of @ref MSIO_LL_EC_PULL.
93
94 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_pull().*/
95
96 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
97 This parameter can be a value of @ref MSIO_LL_EC_MUX.
98
99 GPIO HW MSIO_InitStructuration can be modified afterwards using unitary function
100 @ref ll_msio_set_pin_mux(). */
101
102 } ll_msio_init_t;
103
104 /** @} */
105
106 /** @} */
107
108 /**
109 * @defgroup MSIO_LL_MACRO Defines
110 * @{
111 */
112
113 /* Exported constants --------------------------------------------------------*/
114 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
115 * @{
116 */
117
118 /** @defgroup MSIO_LL_EC_PIN PIN
119 * @{
120 */
121 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
122 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
123 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
124 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
125 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
126 #define LL_MSIO_PIN_ALL ((uint32_t)0x1FU) /**< Select all pins */
127 /** @} */
128
129 /** @defgroup MSIO_LL_EC_DIRECTION Direction
130 * @{
131 */
132 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
133 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
134 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
135 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
136 /** @} */
137
138 /** @defgroup MSIO_LL_EC_MODE Mode
139 * @{
140 */
141 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U) /**< Select analog mode */
142 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U) /**< Enable digital mode */
143 /** @} */
144
145 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
146 * @{
147 */
148 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
149 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
150 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
151 /** @} */
152
153 /** @defgroup MSIO_LL_EC_MUX Alternate Function
154 * @{
155 */
156 #define LL_MSIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
157 #define LL_MSIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
158 #define LL_MSIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
159 #define LL_MSIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
160 #define LL_MSIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
161 #define LL_MSIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
162 #define LL_MSIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
163 #define LL_MSIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
164 /** @} */
165
166 /** @} */
167
168 /* Exported macro ------------------------------------------------------------*/
169 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
170 * @{
171 */
172
173 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
174 * @{
175 */
176
177 /**
178 * @brief Write a value in MSIO register
179 * @param __instance__ MSIO instance
180 * @param __REG__ Register to be written
181 * @param __VALUE__ Value to be written in the register
182 * @retval None
183 */
184 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
185
186 /**
187 * @brief Read a value in MSIO register
188 * @param __instance__ MSIO instance
189 * @param __REG__ Register to be read
190 * @retval Register value
191 */
192 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
193
194 /** @} */
195
196 /** @} */
197
198 /* Private types -------------------------------------------------------------*/
199 /* Private variables ---------------------------------------------------------*/
200 /* Private constants ---------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
202 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
203 * @{
204 */
205
206 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
207 * @{
208 */
209
210 /**
211 * @brief LL MSIO InitStrcut default configuartion
212 */
213 #define LL_MSIO_DEFAULT_CONFIG \
214 { \
215 .pin = LL_MSIO_PIN_ALL, \
216 .direction = LL_MSIO_DIRECTION_INPUT, \
217 .mode = LL_MSIO_MODE_DIGITAL, \
218 .pull = LL_MSIO_PULL_DOWN, \
219 .mux = LL_MSIO_MUX_7, \
220 }
221 /** @} */
222
223 /** @} */
224
225 /** @} */
226
227 /* Exported functions --------------------------------------------------------*/
228 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
229 * @{
230 */
231
232 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
233 * @{
234 */
235
236 /**
237 * @brief Set several MSIO pins to input/output direction.
238 *
239 * Register|BitsName
240 * --------|--------
241 * MSIO_PAD_CFG_0 | OE_N
242 * MSIO_PAD_CFG_0 | IE_N
243 *
244 * @param pin_mask This parameter can be a combination of the following values:
245 * @arg @ref LL_MSIO_PIN_0
246 * @arg @ref LL_MSIO_PIN_1
247 * @arg @ref LL_MSIO_PIN_2
248 * @arg @ref LL_MSIO_PIN_3
249 * @arg @ref LL_MSIO_PIN_4
250 * @arg @ref LL_MSIO_PIN_ALL
251 * @param direction This parameter can be one of the following values:
252 * @arg @ref LL_MSIO_DIRECTION_NONE
253 * @arg @ref LL_MSIO_DIRECTION_INPUT
254 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
255 * @arg @ref LL_MSIO_DIRECTION_INOUT
256 * @retval None
257 */
258 __STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
259 {
260 uint32_t oe_mask = (pin_mask << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
261 uint32_t ie_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
262 if (direction != LL_MSIO_DIRECTION_NONE)
263 {
264 if (direction != LL_MSIO_DIRECTION_INOUT)
265 MODIFY_REG(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask), (direction != LL_MSIO_DIRECTION_INPUT) ? ie_mask : oe_mask);
266 else
267 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
268 }
269 else
270 SET_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
271 }
272
273 /**
274 * @brief Return gpio direction for a MSIO pin.
275 * @note I/O direction can be Input direction, General purpose output.
276 * @note Warning: only one pin can be passed as parameter.
277 *
278 * Register|BitsName
279 * --------|--------
280 * MSIO_PAD_CFG_0 | OE_N
281 * MSIO_PAD_CFG_0 | IE_N
282 *
283 * @param pin This parameter can be one of the following values:
284 * @arg @ref LL_MSIO_PIN_0
285 * @arg @ref LL_MSIO_PIN_1
286 * @arg @ref LL_MSIO_PIN_2
287 * @arg @ref LL_MSIO_PIN_3
288 * @arg @ref LL_MSIO_PIN_4
289 * @retval Returned value can be one of the following values:
290 * @arg @ref LL_MSIO_DIRECTION_NONE
291 * @arg @ref LL_MSIO_DIRECTION_INPUT
292 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
293 * @arg @ref LL_MSIO_DIRECTION_INOUT
294 */
295 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
296 {
297 uint32_t oe_mask = (pin << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
298 uint32_t ie_mask = (pin << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
299 uint32_t mask = READ_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
300 if (mask == (ie_mask | oe_mask))
301 return LL_MSIO_DIRECTION_NONE;
302 else
303 {
304 if (mask == 0)
305 return LL_MSIO_DIRECTION_INOUT;
306 else
307 return ((mask == ie_mask) ? LL_MSIO_DIRECTION_OUTPUT : LL_MSIO_DIRECTION_INPUT);
308 }
309 }
310
311 /**
312 * @brief Set several MSIO pins to analog/digital mode.
313 *
314 * Register|BitsName
315 * --------|--------
316 * MSIO_PAD_CFG_1 | AE_N
317 *
318 * @param pin_mask This parameter can be a combination of the following values:
319 * @arg @ref LL_MSIO_PIN_0
320 * @arg @ref LL_MSIO_PIN_1
321 * @arg @ref LL_MSIO_PIN_2
322 * @arg @ref LL_MSIO_PIN_3
323 * @arg @ref LL_MSIO_PIN_4
324 * @arg @ref LL_MSIO_PIN_ALL
325 * @param mode This parameter can be one of the following values:
326 * @arg @ref LL_MSIO_MODE_ANALOG
327 * @arg @ref LL_MSIO_MODE_DIGITAL
328 * @retval None
329 */
330 __STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
331 {
332 uint32_t ae_mask = (pin_mask << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
333 uint32_t ae_n = (mode != LL_MSIO_MODE_DIGITAL) ? 0U : ae_mask;
334 GLOBAL_EXCEPTION_DISABLE();
335 MODIFY_REG(AON->MSIO_PAD_CFG_1, ae_mask, ae_n);
336 GLOBAL_EXCEPTION_ENABLE();
337 }
338
339 /**
340 * @brief Return gpio mode for a MSIO pin.
341 * @note I/O mode can be analog or digital.
342 * @note Warning: only one pin can be passed as parameter.
343 *
344 * Register|BitsName
345 * --------|--------
346 * MSIO_PAD_CFG_1 | AE_N
347 *
348 * @param pin This parameter can be one of the following values:
349 * @arg @ref LL_MSIO_PIN_0
350 * @arg @ref LL_MSIO_PIN_1
351 * @arg @ref LL_MSIO_PIN_2
352 * @arg @ref LL_MSIO_PIN_3
353 * @arg @ref LL_MSIO_PIN_4
354 * @retval Returned value can be one of the following values:
355 * @arg @ref LL_MSIO_MODE_ANALOG
356 * @arg @ref LL_MSIO_MODE_DIGITAL
357 */
358 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
359 {
360 uint32_t ae_mask = (pin << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
361 return ((READ_BITS(AON->MSIO_PAD_CFG_1, ae_mask) == ae_mask) ? LL_MSIO_MODE_DIGITAL : LL_MSIO_MODE_ANALOG);
362 }
363
364 /**
365 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
366 *
367 * Register|BitsName
368 * --------|--------
369 * MSIO_PAD_CFG_0 | RE_N
370 * MSIO_PAD_CFG_1 | RTYPE
371 *
372 * @param pin_mask This parameter can be a combination of the following values:
373 * @arg @ref LL_MSIO_PIN_0
374 * @arg @ref LL_MSIO_PIN_1
375 * @arg @ref LL_MSIO_PIN_2
376 * @arg @ref LL_MSIO_PIN_3
377 * @arg @ref LL_MSIO_PIN_4
378 * @arg @ref LL_MSIO_PIN_ALL
379 * @param pull This parameter can be one of the following values:
380 * @arg @ref LL_MSIO_PULL_NO
381 * @arg @ref LL_MSIO_PULL_UP
382 * @arg @ref LL_MSIO_PULL_DOWN
383 * @retval None
384 */
385 __STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
386 {
387 if (pull != LL_MSIO_PULL_NO)
388 {
389 uint32_t rtype_mask = (pin_mask << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
390 uint32_t rtype = (pull != LL_MSIO_PULL_UP) ? 0U : rtype_mask;
391 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
392 GLOBAL_EXCEPTION_DISABLE();
393 MODIFY_REG(AON->MSIO_PAD_CFG_1, rtype_mask, rtype);
394 GLOBAL_EXCEPTION_ENABLE();
395 }
396 else
397 {
398 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
399 }
400 }
401
402 /**
403 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
404 * @note Warning: only one pin can be passed as parameter.
405 *
406 * Register|BitsName
407 * --------|--------
408 * MSIO_PAD_CFG_0 | RE_N
409 * MSIO_PAD_CFG_1 | RTYPE
410 *
411 * @param pin This parameter can be one of the following values:
412 * @arg @ref LL_MSIO_PIN_0
413 * @arg @ref LL_MSIO_PIN_1
414 * @arg @ref LL_MSIO_PIN_2
415 * @arg @ref LL_MSIO_PIN_3
416 * @arg @ref LL_MSIO_PIN_4
417 * @retval Returned value can be one of the following values:
418 * @arg @ref LL_MSIO_PULL_NO
419 * @arg @ref LL_MSIO_PULL_UP
420 * @arg @ref LL_MSIO_PULL_DOWN
421 */
422 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
423 {
424 if (READ_BITS(AON->MSIO_PAD_CFG_0, (pin << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N))
425 {
426 return LL_MSIO_PULL_NO;
427 }
428 else
429 {
430 uint32_t rtype_mask = (pin << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
431 return ((READ_BITS(AON->MSIO_PAD_CFG_1, rtype_mask) != RESET) ? LL_MSIO_PULL_UP : LL_MSIO_PULL_DOWN);
432 }
433 }
434
435 /**
436 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
437 * @note Possible values are from AF0 to AF7 depending on target.
438 * @note Warning: only one pin can be passed as parameter.
439 *
440 * Register|BitsName
441 * --------|--------
442 * MSIO_PAD_MUX_CTL | CTL_00_04
443 * MSIO_PAD_CFG_1 | MCU_OVR
444 *
445 * @param pin This parameter can be one of the following values:
446 * @arg @ref LL_MSIO_PIN_0
447 * @arg @ref LL_MSIO_PIN_1
448 * @arg @ref LL_MSIO_PIN_2
449 * @arg @ref LL_MSIO_PIN_3
450 * @arg @ref LL_MSIO_PIN_4
451 * @param mux This parameter can be one of the following values:
452 * @arg @ref LL_MSIO_MUX_0
453 * @arg @ref LL_MSIO_MUX_1
454 * @arg @ref LL_MSIO_MUX_2
455 * @arg @ref LL_MSIO_MUX_3
456 * @arg @ref LL_MSIO_MUX_4
457 * @arg @ref LL_MSIO_MUX_5
458 * @arg @ref LL_MSIO_MUX_6
459 * @arg @ref LL_MSIO_MUX_7
460 * @retval None
461 */
462 __STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
463 {
464 uint32_t pos = POSITION_VAL(pin) << 2;
465 if(LL_MSIO_MUX_7 == mux)
466 {
467 GLOBAL_EXCEPTION_DISABLE();
468 CLEAR_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
469 GLOBAL_EXCEPTION_ENABLE();
470 }
471 else
472 {
473 MODIFY_REG(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos, mux << pos);
474 GLOBAL_EXCEPTION_DISABLE();
475 SET_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
476 GLOBAL_EXCEPTION_ENABLE();
477 }
478 }
479
480 /**
481 * @brief Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
482 *
483 * Register|BitsName
484 * --------|--------
485 * MSIO_PAD_MUX_CTL | CTL_00_04
486 * MSIO_PAD_CFG_1 | MCU_OVR
487 *
488 * @param pin This parameter can be one of the following values:
489 * @arg @ref LL_MSIO_PIN_0
490 * @arg @ref LL_MSIO_PIN_1
491 * @arg @ref LL_MSIO_PIN_2
492 * @arg @ref LL_MSIO_PIN_3
493 * @arg @ref LL_MSIO_PIN_4
494 * @retval Returned value can be one of the following values:
495 * @arg @ref LL_MSIO_MUX_0
496 * @arg @ref LL_MSIO_MUX_1
497 * @arg @ref LL_MSIO_MUX_2
498 * @arg @ref LL_MSIO_MUX_3
499 * @arg @ref LL_MSIO_MUX_4
500 * @arg @ref LL_MSIO_MUX_5
501 * @arg @ref LL_MSIO_MUX_6
502 * @arg @ref LL_MSIO_MUX_7
503 */
504 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
505 {
506 if(READ_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos))
507 {
508 uint32_t pos = POSITION_VAL(pin) << 2;
509 return (READ_BITS(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos) >> pos);
510 }
511 else
512 {
513 return LL_MSIO_MUX_7;
514 }
515 }
516
517 /** @} */
518
519 /** @defgroup MSIO_LL_EF_Data_Access Data Access
520 * @{
521 */
522
523 /**
524 * @brief Return full input data register value of MSIO.
525 *
526 * Register|BitsName
527 * --------|--------
528 * MSIO_REG0 | MSIO_C
529 *
530 * @retval Input data register value of port
531 */
532 __STATIC_INLINE uint32_t ll_msio_read_input_port(void)
533 {
534 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, MCU_SUB_MSIO_REG0_MSIO_C));
535 }
536
537 /**
538 * @brief Return if input data level of several MSIO pins is high or low.
539 *
540 * Register|BitsName
541 * --------|--------
542 * MSIO_REG0 | MSIO_C
543 *
544 * @param pin_mask This parameter can be a combination of the following values:
545 * @arg @ref LL_MSIO_PIN_0
546 * @arg @ref LL_MSIO_PIN_1
547 * @arg @ref LL_MSIO_PIN_2
548 * @arg @ref LL_MSIO_PIN_3
549 * @arg @ref LL_MSIO_PIN_4
550 * @arg @ref LL_MSIO_PIN_ALL
551 * @retval State of bit (1 or 0).
552 */
553 __STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
554 {
555 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, pin_mask) == pin_mask);
556 }
557
558 /**
559 * @brief Write output data register of MSIO.
560 *
561 * Register|BitsName
562 * --------|--------
563 * MSIO_PAD_CFG_0 | IN
564 *
565 * @param port_value Level value for each pin of the port
566 * @retval None
567 */
568 __STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
569 {
570 MODIFY_REG(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN, (port_value << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
571 }
572
573 /**
574 * @brief Return full output data register value of MSIO.
575 *
576 * Register|BitsName
577 * --------|--------
578 * MSIO_PAD_CFG_0 | IN
579 *
580 * @retval Output data register value of port
581 */
582 __STATIC_INLINE uint32_t ll_msio_read_output_port(void)
583 {
584 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN) >> AON_MSIO_PAD_CFG_0_IN_Pos);
585 }
586
587 /**
588 * @brief Return if input data level of several MSIO pins is high or low.
589 *
590 * Register|BitsName
591 * --------|--------
592 * MSIO_PAD_CFG_0 | IN
593 *
594 * @param pin_mask This parameter can be a combination of the following values:
595 * @arg @ref LL_MSIO_PIN_0
596 * @arg @ref LL_MSIO_PIN_1
597 * @arg @ref LL_MSIO_PIN_2
598 * @arg @ref LL_MSIO_PIN_3
599 * @arg @ref LL_MSIO_PIN_4
600 * @arg @ref LL_MSIO_PIN_ALL
601 * @retval State of bit (1 or 0).
602 */
603 __STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
604 {
605 pin_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN;
606 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, pin_mask) == pin_mask);
607 }
608
609 /**
610 * @brief Set specified MSIO pins to high level
611 *
612 * Register|BitsName
613 * --------|--------
614 * MSIO_PAD_CFG_0 | IN
615 *
616 * @param pin_mask This parameter can be a combination of the following values:
617 * @arg @ref LL_MSIO_PIN_0
618 * @arg @ref LL_MSIO_PIN_1
619 * @arg @ref LL_MSIO_PIN_2
620 * @arg @ref LL_MSIO_PIN_3
621 * @arg @ref LL_MSIO_PIN_4
622 * @arg @ref LL_MSIO_PIN_ALL
623 * @retval None
624 */
625 __STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
626 {
627 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
628 }
629
630 /**
631 * @brief Set specified MSIO pins to low level.
632 *
633 * Register|BitsName
634 * --------|--------
635 * MSIO_PAD_CFG_0 | IN
636 *
637 * @param pin_mask This parameter can be a combination of the following values:
638 * @arg @ref LL_MSIO_PIN_0
639 * @arg @ref LL_MSIO_PIN_1
640 * @arg @ref LL_MSIO_PIN_2
641 * @arg @ref LL_MSIO_PIN_3
642 * @arg @ref LL_MSIO_PIN_4
643 * @arg @ref LL_MSIO_PIN_ALL
644 * @retval None
645 */
646 __STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
647 {
648 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
649 }
650
651 /**
652 * @brief Toggle data value of specified MSIO pins.
653 *
654 * Register|BitsName
655 * --------|--------
656 * MSIO_PAD_CFG_0 | IN
657 *
658 * @param pin_mask This parameter can be a combination of the following values:
659 * @arg @ref LL_MSIO_PIN_0
660 * @arg @ref LL_MSIO_PIN_1
661 * @arg @ref LL_MSIO_PIN_2
662 * @arg @ref LL_MSIO_PIN_3
663 * @arg @ref LL_MSIO_PIN_4
664 * @arg @ref LL_MSIO_PIN_ALL
665 * @retval None
666 */
667 __STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
668 {
669 WRITE_REG(AON->MSIO_PAD_CFG_0, (READ_REG(AON->MSIO_PAD_CFG_0) ^ ((pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN)));
670 }
671
672 /** @} */
673
674 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
675 * @{
676 */
677
678 /**
679 * @brief De-initialize MSIO registers (Registers restored to their default values).
680 * @retval An error_status_t enumeration value:
681 * - SUCCESS: MSIO registers are de-initialized
682 * - ERROR: MSIO registers are not de-initialized
683 */
684 error_status_t ll_msio_deinit(void);
685
686 /**
687 * @brief Initialize MSIO registers according to the specified.
688 * parameters in p_msio_init.
689 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
690 * information for the specified MSIO peripheral.
691 * @retval An error_status_t enumeration value:
692 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
693 * - ERROR: Problem occurred during MSIO Registers initialization
694 */
695 error_status_t ll_msio_init(ll_msio_init_t *p_msio_init);
696
697 /**
698 * @brief Set each field of a @ref ll_msio_init_t type structure to default value.
699 * @param p_msio_init Pointer to a @ref ll_msio_init_t structure
700 * whose fields will be set to default values.
701 * @retval None
702 */
703 void ll_msio_struct_init(ll_msio_init_t *p_msio_init);
704
705 /** @} */
706
707 /** @} */
708
709 #endif /* AON */
710
711 #ifdef __cplusplus
712 }
713 #endif
714
715 #endif /* __GR55XX_LL_MSIO_H__ */
716
717 /** @} */
718
719 /** @} */
720
721 /** @} */
_ll_msio_init::mux
uint32_t mux
Definition: gr55xx_ll_msio.h:96
ll_msio_set_pin_direction
__STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
Set several MSIO pins to input/output direction.
Definition: gr55xx_ll_msio.h:258
ll_msio_get_pin_direction
__STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
Return gpio direction for a MSIO pin.
Definition: gr55xx_ll_msio.h:295
LL_MSIO_MODE_ANALOG
#define LL_MSIO_MODE_ANALOG
Select analog mode
Definition: gr55xx_ll_msio.h:141
LL_MSIO_MODE_DIGITAL
#define LL_MSIO_MODE_DIGITAL
Enable digital mode
Definition: gr55xx_ll_msio.h:142
ll_msio_read_input_port
__STATIC_INLINE uint32_t ll_msio_read_input_port(void)
Return full input data register value of MSIO.
Definition: gr55xx_ll_msio.h:532
LL_MSIO_PULL_DOWN
#define LL_MSIO_PULL_DOWN
Select I/O pull down.
Definition: gr55xx_ll_msio.h:150
ll_msio_toggle_pin
__STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified MSIO pins.
Definition: gr55xx_ll_msio.h:667
ll_msio_set_pin_mode
__STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several MSIO pins to analog/digital mode.
Definition: gr55xx_ll_msio.h:330
ll_msio_init_t
struct _ll_msio_init ll_msio_init_t
LL MSIO init Structure definition.
ll_msio_get_pin_pull
__STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:422
ll_msio_get_pin_mode
__STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
Return gpio mode for a MSIO pin.
Definition: gr55xx_ll_msio.h:358
_ll_msio_init::mode
uint32_t mode
Specifies the operating mode for the selected pins.
Definition: gr55xx_ll_msio.h:86
LL_MSIO_PULL_NO
#define LL_MSIO_PULL_NO
Select I/O no pull
Definition: gr55xx_ll_msio.h:148
ll_msio_reset_output_pin
__STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
Set specified MSIO pins to low level.
Definition: gr55xx_ll_msio.h:646
ll_msio_set_output_pin
__STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
Set specified MSIO pins to high level.
Definition: gr55xx_ll_msio.h:625
LL_MSIO_MUX_7
#define LL_MSIO_MUX_7
Definition: gr55xx_ll_msio.h:163
LL_MSIO_DIRECTION_INOUT
#define LL_MSIO_DIRECTION_INOUT
Enable input&output
Definition: gr55xx_ll_msio.h:135
LL_MSIO_DIRECTION_INPUT
#define LL_MSIO_DIRECTION_INPUT
Enable input
Definition: gr55xx_ll_msio.h:133
ll_msio_get_pin_mux
__STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:504
ll_msio_set_pin_pull
__STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:385
_ll_msio_init::direction
uint32_t direction
Specifies the direction for the selected pins.
Definition: gr55xx_ll_msio.h:81
ll_msio_write_output_port
__STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
Write output data register of MSIO.
Definition: gr55xx_ll_msio.h:568
ll_msio_read_output_port
__STATIC_INLINE uint32_t ll_msio_read_output_port(void)
Return full output data register value of MSIO.
Definition: gr55xx_ll_msio.h:582
ll_msio_init
error_status_t ll_msio_init(ll_msio_init_t *p_msio_init)
Initialize MSIO registers according to the specified.
ll_msio_struct_init
void ll_msio_struct_init(ll_msio_init_t *p_msio_init)
Set each field of a ll_msio_init_t type structure to default value.
LL_MSIO_DIRECTION_OUTPUT
#define LL_MSIO_DIRECTION_OUTPUT
Enable output
Definition: gr55xx_ll_msio.h:134
LL_MSIO_PULL_UP
#define LL_MSIO_PULL_UP
Select I/O pull up
Definition: gr55xx_ll_msio.h:149
ll_msio_deinit
error_status_t ll_msio_deinit(void)
De-initialize MSIO registers (Registers restored to their default values).
_ll_msio_init
LL MSIO init Structure definition.
Definition: gr55xx_ll_msio.h:77
_ll_msio_init::pin
uint32_t pin
Specifies the MSIO pins to be MSIO_InitStructured.
Definition: gr55xx_ll_msio.h:78
ll_msio_is_input_pin_set
__STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:553
_ll_msio_init::pull
uint32_t pull
Specifies the operating Pull-up/Pull down for the selected pins.
Definition: gr55xx_ll_msio.h:91
ll_msio_is_output_pin_set
__STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:603
LL_MSIO_DIRECTION_NONE
#define LL_MSIO_DIRECTION_NONE
Disable input/output
Definition: gr55xx_ll_msio.h:132
ll_msio_set_pin_mux
__STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:462