gr55xx_ll_pwr.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
73 * @{
74 */
75
76 /** @defgroup PWR_LL_PC_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
77 * @{
78 */
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos) /**< External wakeup level type */
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos) /**< External wakeup level invert */
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos) /**< External wakeup source enable */
82 /** @} */
83
84 /** @} */
85
86 /* Private macros ------------------------------------------------------------*/
87 /** @defgroup PWR_LL_Private_Macro PWR Private Macros
88 * @{
89 */
90
91 /** @defgroup PWR_LL_PM_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
92 * @{
93 */
94
95 /**
96 * @brief PWR_LL_PM_GET_MEM_PWR_MSK PWR Get Memory Power Value Mask
97 */
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100
101 /** @} */
102
103 /** @} */
104
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
108 * @{
109 */
110
111 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
112 * @{
113 */
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP /**< External wakeup: AON_GPIO */
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER /**< AON Timer wakeup */
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE /**< BLE wakeup */
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR /**< Calendar wakeup */
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE /**< PMU Bod falling edge wakeup */
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP /**< Msio comparator wakeup */
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL /**< All wakeup sources mask */
121 /** @} */
122
123
124 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
125 * @note Only available on GR5515_C and later version
126 * @{
127 */
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN /**< BLE Timer wakeup event */
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER /**< AON Timer wakeup event */
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP /**< External wakeup event: AON_GPIO */
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE /**< PMU Bod wakeup event */
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP /**< Msio comparator wakeup event */
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT /**< AON WDT wakeup event */
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM /**< Calendar wakeup event */
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136 AON_SLP_EVENT_TIMER | \
137 AON_SLP_EVENT_EXTWKUP | \
138 AON_SLP_EVENT_PMU_BOD_FEDGE | \
139 AON_SLP_EVENT_PMU_MSIO_COMP | \
140 AON_SLP_EVENT_WDT_REBOOT | \
141 AON_SLP_EVENT_CALENDAR_TIMER_ALARM) /**< All event mask */
142 /** @} */
143
144 /** @defgroup PWR_LL_EC_EXTWAKEUP_PIN External Wakeup Pins
145 * @{
146 */
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U) /**< WKUP pin 0 : AON_GPIO_PIN0 */
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U) /**< WKUP pin 1 : AON_GPIO_PIN1 */
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U) /**< WKUP pin 2 : AON_GPIO_PIN2 */
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U) /**< WKUP pin 3 : AON_GPIO_PIN3 */
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U) /**< WKUP pin 4 : AON_GPIO_PIN4 */
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U) /**< WKUP pin 5 : AON_GPIO_PIN5 */
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U) /**< WKUP pin 6 : AON_GPIO_PIN6 */
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U) /**< WKUP pin 7 : AON_GPIO_PIN7 */
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU) /**< WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7 */
156 /** @} */
157
158 /** @defgroup PWR_LL_EC_EXTWAKEUP_TYPE External Wakeup Type
159 * @{
160 */
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Low level wakeup */
162 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< High level wakeup */
163 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U) /**< Rising edge wakeup */
164 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Falling edge wakeup */
165 /** @} */
166
167 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
168 * @{
169 */
170 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK /**< Reserved command 0 */
171 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON /**< Reserved command 1 */
172 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD /**< Load sleep timer command */
173 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP /**< Enter Deep Sleep Mode command */
174 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF /**< Reserved command 2 */
175 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK /**< Select external clock (xo_32KHz) command */
176 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK /**< Select RING OSC clock command */
177 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK /**< Select RTC clock command */
178 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK /**< Select RING OSC clock command */
179 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG /**< Load memory sleep settings command */
180 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG /**< Load memory wakeup settings command */
181 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI /**< Force dpad_le high */
182 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO /**< Force dpad_le low */
183 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 /**< Enable sleep timer mode 0 command */
184 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 /**< Enable sleep timer mode 1 command */
185 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 /**< Enable sleep timer mode 2 command */
186 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 /**< Enable sleep timer mode 3 command */
187 /** @} */
188
189
190 /** @} */
191
192 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
193 * @{
194 */
195 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
196 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
197 /** @} */
198
199 /** @defgroup PWR_LL_EC_TIMER_READ_SEL Timer Read Select
200 * @note Only available on GR5515_C and later version
201 * @{
202 */
203 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER /**< Calendar timer */
204 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT /**< AON watchdog timer */
205 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER /**< Sleep timer */
206 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM /**< Calendar alarm */
207 /** @} */
208
209 /** @} */
210
211
212 /* Exported macro ------------------------------------------------------------*/
213 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
214 * @{
215 */
216
217 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
218 * @{
219 */
220
221 /**
222 * @brief Write a value in PWR register
223 * @param __REG__ Register to be written
224 * @param __VALUE__ Value to be written in the register
225 * @retval None
226 */
227 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
228
229 /**
230 * @brief Read a value in PWR register
231 * @param __REG__ Register to be read
232 * @retval Register value
233 */
234 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
235 /** @} */
236
237 /* Exported functions --------------------------------------------------------*/
238 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
239 * @{
240 */
241
242 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
243 * @{
244 */
245
246 /**
247 * @brief Set the DeepSleep WakeUp Condition
248 *
249 * Register|BitsName
250 * --------|--------
251 * EXT_WKUP_CTL | WAKE_UP_SEL
252 *
253 * @param condition This parameter can be one of the following values:
254 * @arg @ref LL_PWR_WKUP_COND_EXT
255 * @arg @ref LL_PWR_WKUP_COND_TIMER
256 * @arg @ref LL_PWR_WKUP_COND_BLE
257 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
258 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
259 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
260 * @arg @ref LL_PWR_WKUP_COND_ALL
261 * @retval None
262 */
263 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
264 {
265 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
266 }
267
268 /**
269 * @brief Get the Selected DeepSleep WakeUp Condition
270 *
271 * Register|BitsName
272 * --------|--------
273 * EXT_WKUP_CTL | WAKE_UP_SEL
274 *
275 * @retval Returned value can be one of the following values:
276 * @arg @ref LL_PWR_WKUP_COND_EXT
277 * @arg @ref LL_PWR_WKUP_COND_TIMER
278 * @arg @ref LL_PWR_WKUP_COND_BLE
279 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
280 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
281 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
282 * @arg @ref LL_PWR_WKUP_COND_ALL
283 */
284 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
285 {
286 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
287 }
288
289 /**
290 * @brief Get the Event that triggered the DeepSleep WakeUp.
291 * @note Only available on GR5515_C and later version
292 *
293 * Register|BitsName
294 * --------|--------
295 * SLP_EVENT | SMCOSCEN_EVENT
296 * SLP_EVENT | TIMER_EVENT
297 * SLP_EVENT | EXT_WKUP_EVENT
298 * SLP_EVENT | WATCHDOG_EVENT
299 *
300 * @retval Returned value can be combination of the following values:
301 * @arg @ref LL_PWR_WKUP_EVENT_BLE
302 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
303 * @arg @ref LL_PWR_WKUP_EVENT_EXT
304 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
305 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
306 * @arg @ref LL_PWR_WKUP_EVENT_WDT
307 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
308 */
309 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
310 {
311 return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
312 }
313
314 /**
315 * @brief Enable the External WakeUp PINx functionality
316 *
317 * Register|BitsName
318 * --------|--------
319 * EXT_WKUP_CTL | MASK
320 *
321 * @param wakeup_pin This parameter can be a combination of the following values:
322 * @arg @ref LL_PWR_EXTWKUP_PIN0
323 * @arg @ref LL_PWR_EXTWKUP_PIN1
324 * @arg @ref LL_PWR_EXTWKUP_PIN2
325 * @arg @ref LL_PWR_EXTWKUP_PIN3
326 * @arg @ref LL_PWR_EXTWKUP_PIN4
327 * @arg @ref LL_PWR_EXTWKUP_PIN5
328 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
329 * @retval None
330 */
331 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
332 {
333 GLOBAL_EXCEPTION_DISABLE();
334 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
335 GLOBAL_EXCEPTION_ENABLE();
336 }
337
338 /**
339 * @brief Disable the External WakeUp PINx functionality
340 *
341 * Register|BitsName
342 * --------|--------
343 * EXT_WKUP_CTL | MASK
344 *
345 * @param wakeup_pin This parameter can be a combination of the following values:
346 * @arg @ref LL_PWR_EXTWKUP_PIN0
347 * @arg @ref LL_PWR_EXTWKUP_PIN1
348 * @arg @ref LL_PWR_EXTWKUP_PIN2
349 * @arg @ref LL_PWR_EXTWKUP_PIN3
350 * @arg @ref LL_PWR_EXTWKUP_PIN4
351 * @arg @ref LL_PWR_EXTWKUP_PIN5
352 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
353 * @retval None
354 */
355 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
356 {
357 GLOBAL_EXCEPTION_DISABLE();
358 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
359 GLOBAL_EXCEPTION_ENABLE();
360 }
361
362 /**
363 * @brief Check if the External WakeUp PINx functionality is enabled
364 *
365 * Register|BitsName
366 * --------|--------
367 * EXT_WKUP_CTL | MASK
368 *
369 * @param wakeup_pin This parameter can be a combination of the following values:
370 * @arg @ref LL_PWR_EXTWKUP_PIN0
371 * @arg @ref LL_PWR_EXTWKUP_PIN1
372 * @arg @ref LL_PWR_EXTWKUP_PIN2
373 * @arg @ref LL_PWR_EXTWKUP_PIN3
374 * @arg @ref LL_PWR_EXTWKUP_PIN4
375 * @arg @ref LL_PWR_EXTWKUP_PIN5
376 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
377 * @retval State of bit (1 or 0).
378 */
379 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
380 {
381 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
382 }
383
384 /**
385 * @brief Set the WakeUp Type of External WakeUp PINx.
386 *
387 * Register|BitsName
388 * --------|--------
389 * EXT_WKUP_CTL | INVERT
390 * EXT_WKUP_CTL | TYPE
391 *
392 * @param wakeup_pin This parameter can be a combination of the following values:
393 * @arg @ref LL_PWR_EXTWKUP_PIN0
394 * @arg @ref LL_PWR_EXTWKUP_PIN1
395 * @arg @ref LL_PWR_EXTWKUP_PIN2
396 * @arg @ref LL_PWR_EXTWKUP_PIN3
397 * @arg @ref LL_PWR_EXTWKUP_PIN4
398 * @arg @ref LL_PWR_EXTWKUP_PIN5
399 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
400 * @param wakeup_type This parameter can be one of the following values:
401 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
402 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
403 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
404 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
405 * @retval None
406 */
407 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
408 {
409 uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
410 uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
411 GLOBAL_EXCEPTION_DISABLE();
412 MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
413 GLOBAL_EXCEPTION_ENABLE();
414 }
415
416 /**
417 * @brief Get the WakeUp Type of External WakeUp PINx.
418 * @note Warning: only one pin can be passed as parameter.
419 *
420 * Register|BitsName
421 * --------|--------
422 * EXT_WKUP_CTL | INVERT
423 * EXT_WKUP_CTL | TYPE
424 *
425 * @param wakeup_pin This parameter can be one of the following values:
426 * @arg @ref LL_PWR_EXTWKUP_PIN0
427 * @arg @ref LL_PWR_EXTWKUP_PIN1
428 * @arg @ref LL_PWR_EXTWKUP_PIN2
429 * @arg @ref LL_PWR_EXTWKUP_PIN3
430 * @arg @ref LL_PWR_EXTWKUP_PIN4
431 * @arg @ref LL_PWR_EXTWKUP_PIN5
432 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
433 * @retval Returned value can be one of the following values:
434 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
435 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
436 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
437 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
438 */
439 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
440 {
441 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
442 }
443
444 /**
445 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
446 * @note After the value was set, use @arg @ref LL_PWR_CMD_32_TIMER_LD command to
447 * load the configuration into Power State Controller.
448 *
449 * Register|BitsName
450 * --------|--------
451 * TIMER_VALUE | PWR_CTL_TIMER_32B
452 *
453 * @param value 32 bits count value loaded into the t32bit_timer
454 * @retval None
455 */
456 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
457 {
458 WRITE_REG(AON->TIMER_VALUE, value);
459 }
460
461 /**
462 * @brief Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
463 *
464 * Register|BitsName
465 * --------|--------
466 * TIMER_VALUE | PWR_CTL_TIMER_32B
467 *
468 * @retval 32 bit AON Timer Count Value
469 */
470 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
471 {
472 return READ_REG(AON->TIMER_VALUE);
473 }
474
475 /**
476 * @brief Enable the SMC WakeUp Request.
477 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
478 *
479 * Register|BitsName
480 * --------|--------
481 * PWR_RET01 | SMC_WAKEUP_REQ
482 *
483 * @retval None
484 */
485 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
486 {
487 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
488 }
489
490 /**
491 * @brief Disable the SMC WakeUp Request.
492 * @note This function is used to clear SMC WakeUp Request.
493 *
494 * Register|BitsName
495 * --------|--------
496 * PWR_RET01 | SMC_WAKEUP_REQ
497 *
498 * @retval None
499 */
500 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
501 {
502 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
503 }
504
505 /**
506 * @brief Check if the SMC WakeUp Request was enabled or disabled.
507 *
508 * Register|BitsName
509 * --------|--------
510 * PWR_RET01 | SMC_WAKEUP_REQ
511 *
512 * @retval State of bit (1 or 0).
513 */
514 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
515 {
516 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
517 }
518
519 /**
520 * @brief Set the DPAD LE value during sleep and after wake up.
521 *
522 * Register|BitsName
523 * --------|--------
524 * MEM_N_SLP_CTL | DPAD_LE_SLP_VAL
525 * MEM_N_SLP_CTL | DPAD_LE_WKUP_VAL
526 *
527 * @param sleep This parameter can be one of the following values:
528 * @arg @ref LL_PWR_DPAD_LE_OFF
529 * @arg @ref LL_PWR_DPAD_LE_ON
530 * @param wakeup This parameter can be one of the following values:
531 * @arg @ref LL_PWR_DPAD_LE_OFF
532 * @arg @ref LL_PWR_DPAD_LE_ON
533 * @retval None
534 */
535 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
536 {
537 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
538 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
539 }
540
541 /**
542 * @brief Request to excute the Power State Controller Command.
543 * @note The PSC command can only be excuted when Power State Controller is not in busy state.
544 * Use @ref ll_pwr_is_active_flag_psc_cmd_busy() to check the busy status, and make sure
545 * the last command has been finished.
546 *
547 * Register|BitsName
548 * --------|--------
549 * PSC_CMD_OPC | OPCODE
550 * PSC_CMD | MCU_PWR_REQ
551 *
552 * @param command This parameter can be one of the following values:
553 * @arg @ref LL_PWR_CMD_LOOPBACK
554 * @arg @ref LL_PWR_CMD_EF_DIR_ON
555 * @arg @ref LL_PWR_CMD_32_TIMER_LD
556 * @arg @ref LL_PWR_CMD_DEEP_SLEEP
557 * @arg @ref LL_PWR_CMD_EF_DIR_OFF
558 * @arg @ref LL_PWR_CMD_EXT_CLK
559 * @arg @ref LL_PWR_CMD_RNG_CLK
560 * @arg @ref LL_PWR_CMD_RTC_CLK
561 * @arg @ref LL_PWR_CMD_LD_MEM_SLP_CFG
562 * @arg @ref LL_PWR_CMD_LD_MEM_WKUP_CFG
563 * @arg @ref LL_PWR_CMD_DPAD_LE_HI (*)
564 * @arg @ref LL_PWR_CMD_DPAD_LE_LO (*)
565 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_NORMAL (*)
566 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_SINGLE (*)
567 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_RELOAD (*)
568 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_DISABLE (*)
569 *
570 * (*) Not available in A0 and B0
571 *
572 * @retval None
573 */
574 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
575 {
576 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
577 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
578 }
579
580 /** @} */
581
582 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
583 * @{
584 */
585
586 /**
587 * @brief Enable the Communication Timer Reset.
588 * @note Comm timer can be reset when all ble connection were disconnected and
589 * MCU was ready to enter into deepsleep mode.
590 *
591 * Register|BitsName
592 * --------|--------
593 * PWR_RET01 | COMM_TIMER_RST_N
594 *
595 * @retval None
596 */
597 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
598 {
599 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
600 }
601
602 /**
603 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
604 * @note After powered up, Comm Timer need to enter into running mode.
605 *
606 * Register|BitsName
607 * --------|--------
608 * PWR_RET01 | COMM_TIMER_RST_N
609 *
610 * @retval None
611 */
612 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
613 {
614 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
615 }
616
617 /**
618 * @brief Check if the Communication Timer Reset was enabled or disabled.
619 *
620 * Register|BitsName
621 * --------|--------
622 * PWR_RET01 | COMM_TIMER_RST_N
623 *
624 * @retval State of bit (1 or 0).
625 */
626 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
627 {
628 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
629 }
630
631 /**
632 * @brief Enable the Communication Core Reset.
633 * @note Comm Core can be reset when all ble connection were disconnected and
634 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
635 * is 0, the ble is held in reset.
636 *
637 * Register|BitsName
638 * --------|--------
639 * PWR_RET01 | COMM_CORE_RST_N
640 *
641 * @retval None
642 */
643 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
644 {
645 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
646 }
647
648 /**
649 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
650 * @note After powered up, Comm Core need to enter into running mode.
651 *
652 * Register|BitsName
653 * --------|--------
654 * PWR_RET01 | COMM_CORE_RST_N
655 *
656 * @retval None
657 */
658 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
659 {
660 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
661 }
662
663 /**
664 * @brief Check if the Communication Core Reset was enabled or disabled.
665 *
666 * Register|BitsName
667 * --------|--------
668 * PWR_RET01 | COMM_CORE_RST_N
669 *
670 * @retval State of bit (1 or 0).
671 */
672 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
673 {
674 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
675 }
676
677 /**
678 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
679 *
680 * Register|BitsName
681 * --------|--------
682 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
683 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
684 *
685 * @retval None
686 */
687 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
688 {
689 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
690 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
691 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
692 }
693
694 /**
695 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
696 *
697 * Register|BitsName
698 * --------|--------
699 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
700 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
701 *
702 * @retval None
703 */
704 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
705 {
706 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
707 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
708 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
709 }
710
711 /**
712 * @brief Check if the Communication Timer Power was enabled or disabled.
713 *
714 * Register|BitsName
715 * --------|--------
716 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
717 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
718 *
719 * @retval State of bit (1 or 0).
720 */
721 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
722 {
723 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
724 }
725
726 /**
727 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
728 *
729 * Register|BitsName
730 * --------|--------
731 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
732 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
733 *
734 * @retval None
735 */
736 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
737 {
738 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
739 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
740 }
741
742 /**
743 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
744 *
745 * Register|BitsName
746 * --------|--------
747 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
748 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
749 *
750 * @retval None
751 */
752 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
753 {
754 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
755 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
756 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
757 }
758
759 /**
760 * @brief Check if the Communication Core Power was enabled or disabled.
761 *
762 * Register|BitsName
763 * --------|--------
764 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
765 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
766 *
767 * @retval None
768 */
769 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
770 {
771 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
772 }
773
774 /**
775 * @brief Select which timer value to read
776 *
777 * Register|BitsName
778 * --------|--------
779 * PAD_CTL1 | TIMER_READ_SEL
780 *
781 * @param select This parameter can be one of the following values:
782 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
783 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
784 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
785 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
786 * @retval None
787 */
788 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
789 {
790 GLOBAL_EXCEPTION_DISABLE();
791 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
792 GLOBAL_EXCEPTION_ENABLE();
793 }
794
795 /**
796 * @brief Get which timer value was selected to read.
797 *
798 * Register|BitsName
799 * --------|--------
800 * PAD_CTL1 | TIMER_READ_SEL
801 *
802 * @retval Returned value can be one of the following values:
803 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
804 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
805 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
806 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
807 */
808 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
809 {
810 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
811 }
812
813 /**
814 * @brief Get current timer value based on the selection.
815 * @note Please read multiple times until get a stable value.
816 *
817 * Register|BitsName
818 * --------|--------
819 * PAD_CTL1 | TIMER_READ_SEL
820 *
821 * @retval Returned value can be one of the following values:
822 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
823 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
824 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
825 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
826 */
827 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
828 {
829 return ((uint32_t)READ_REG(AON->TIMER_VAL));
830 }
831
832 /**
833 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
834 *
835 * Register|BitsName
836 * --------|--------
837 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
838 *
839 * @retval None
840 */
841 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
842 {
843 GLOBAL_EXCEPTION_DISABLE();
844 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
845 GLOBAL_EXCEPTION_ENABLE();
846 }
847
848
849 /**
850 * @brief Disable high frequency crystal oscillator sleep mode.
851 * @note Switch OSC from sleep mode into normal active mode.
852 *
853 * Register|BitsName
854 * --------|--------
855 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
856 *
857 * @retval None
858 */
859 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
860 {
861 GLOBAL_EXCEPTION_DISABLE();
862 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
863 GLOBAL_EXCEPTION_ENABLE();
864 }
865
866 /**
867 * @brief Check if the OSC sleep mode was enabled or disabled.
868 *
869 * Register|BitsName
870 * --------|--------
871 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
872 *
873 * @retval State of bit (1 or 0).
874 */
875 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
876 {
877 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
878 }
879
880 /**
881 * @brief Enable Radio sleep mode, and disable Radio module.
882 *
883 * Register|BitsName
884 * --------|--------
885 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
886 *
887 * @retval None
888 */
889 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
890 {
891 GLOBAL_EXCEPTION_DISABLE();
892 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
893 GLOBAL_EXCEPTION_ENABLE();
894 }
895
896 /**
897 * @brief Disable Radio sleep mode.
898 * @note Switch Radio from sleep mode into normal active mode.
899 *
900 * Register|BitsName
901 * --------|--------
902 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
903 *
904 * @retval None
905 */
906 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
907 {
908 GLOBAL_EXCEPTION_DISABLE();
909 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
910 GLOBAL_EXCEPTION_ENABLE();
911 }
912
913 /**
914 * @brief Check if the Radio sleep mode was enabled or disabled.
915 *
916 * Register|BitsName
917 * --------|--------
918 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
919 *
920 * @retval State of bit (1 or 0).
921 */
922 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
923 {
924 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
925 }
926
927 /**
928 * @brief Enable Communication Core Deep Sleep Mode.
929 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
930 *
931 * Register|BitsName
932 * --------|--------
933 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
934 *
935 * @retval None
936 */
937 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
938 {
939 GLOBAL_EXCEPTION_DISABLE();
940 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
941 GLOBAL_EXCEPTION_ENABLE();
942 }
943
944 /**
945 * @brief Disable Communication Core Deep Sleep Mode.
946 * @note Switch Communication Core from sleep mode into normal active mode.
947 *
948 * Register|BitsName
949 * --------|--------
950 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
951 *
952 * @retval None
953 */
954 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
955 {
956 GLOBAL_EXCEPTION_DISABLE();
957 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
958 GLOBAL_EXCEPTION_ENABLE();
959 }
960
961 /**
962 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
963 *
964 * Register|BitsName
965 * --------|--------
966 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
967 *
968 * @retval State of bit (1 or 0).
969 */
970 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
971 {
972 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
973 }
974
975 /**
976 * @brief Enable Wake Up Request from Software.
977 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
978 * when written with a 1. No action happens if it is written with 0.
979 *
980 * Register|BitsName
981 * --------|--------
982 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
983 *
984 * @retval None
985 */
986 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
987 {
988 GLOBAL_EXCEPTION_DISABLE();
989 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
990 GLOBAL_EXCEPTION_ENABLE();
991 }
992
993 /**
994 * @brief Check if the Wake Up Request was enabled or disabled.
995 * @note Resets at 0 means request action is performed.
996 *
997 * Register|BitsName
998 * --------|--------
999 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
1000 *
1001 * @retval State of bit (1 or 0).
1002 */
1003 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1004 {
1005 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1006 }
1007
1008 /**
1009 * @brief Enable Communication Core external wakeup.
1010 * @note After this configuration, Communication Core can be woken up by external wake-up
1011 *
1012 * Register|BitsName
1013 * --------|--------
1014 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1015 *
1016 * @retval None
1017 */
1018 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1019 {
1020 GLOBAL_EXCEPTION_DISABLE();
1021 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1022 GLOBAL_EXCEPTION_ENABLE();
1023 }
1024
1025 /**
1026 * @brief Disable Communication Core external wakeup.
1027 * @note After this configuration, Communication Core cannot be woken up by external wake-up
1028 *
1029 * Register|BitsName
1030 * --------|--------
1031 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1032 *
1033 * @retval None
1034 */
1035 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1036 {
1037 GLOBAL_EXCEPTION_DISABLE();
1038 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1039 GLOBAL_EXCEPTION_ENABLE();
1040 }
1041
1042 /**
1043 * @brief Check if the Communication Core external wakeup was enabled or disabled.
1044 *
1045 * Register|BitsName
1046 * --------|--------
1047 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1048 *
1049 * @retval State of bit (1 or 0).
1050 */
1051 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1052 {
1053 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1054 }
1055
1056 /**
1057 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1058 *
1059 * Register|BitsName
1060 * --------|--------
1061 * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1062 *
1063 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1064 * @retval None
1065 */
1066 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1067 {
1068 WRITE_REG(AON->PWR_RET28, time);
1069 }
1070
1071 /**
1072 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1073 *
1074 * Register|BitsName
1075 * --------|--------
1076 * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1077 *
1078 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
1079 */
1080 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1081 {
1082 return ((uint32_t)READ_REG(AON->PWR_RET28));
1083 }
1084
1085
1086 /**
1087 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
1088 *
1089 * Register|BitsName
1090 * --------|--------
1091 * COMM_TMR_DEEPSLPSTAT | DEEPSLDUR
1092 *
1093 * @retval Sleep duration
1094 */
1095 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1096 {
1097 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1098 }
1099
1100 /**
1101 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1102 *
1103 * Register|BitsName
1104 * --------|--------
1105 * COMM_TMR_ENBPRESET | TWEXT
1106 * COMM_TMR_ENBPRESET | TWOSC
1107 * COMM_TMR_ENBPRESET | TWRM
1108 *
1109 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
1110 * oscillator following an external wake–up request (signal wakeup_req).
1111 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
1112 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
1113 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
1114 * @retval None
1115 */
1116 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1117 {
1118 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1119 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1120 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1121 }
1122
1123
1124 /**
1125 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * COMM_TMR_ENBPRESET | TWEXT
1130 * COMM_TMR_ENBPRESET | TWOSC
1131 * COMM_TMR_ENBPRESET | TWRM
1132 *
1133 * @retval COMM_TMR_ENBPRESET Register value
1134 */
1135 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1136 {
1137 return ((uint32_t)READ_REG(AON->PWR_RET29));
1138 }
1139
1140 /**
1141 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1142 *
1143 * @retval TWOSC value
1144 */
1145 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1146 {
1147 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1148 }
1149
1150
1151 /** @} */
1152
1153 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1154 * @{
1155 */
1156
1157 /**
1158 * @brief Get the External Wake Up Status.
1159 * @note 0 means not waked up and 1 means waked up.
1160 *
1161 * Register|BitsName
1162 * --------|--------
1163 * SLP_EVENT | EXT_WKUP_STATUS
1164 *
1165 * @retval Returned value can be a combination of the following values:
1166 * @arg @ref LL_PWR_EXTWKUP_PIN0
1167 * @arg @ref LL_PWR_EXTWKUP_PIN1
1168 * @arg @ref LL_PWR_EXTWKUP_PIN2
1169 * @arg @ref LL_PWR_EXTWKUP_PIN3
1170 * @arg @ref LL_PWR_EXTWKUP_PIN4
1171 * @arg @ref LL_PWR_EXTWKUP_PIN5
1172 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1173 */
1174 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1175 {
1176 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1177 (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1178 }
1179
1180 /**
1181 * @brief Clear the External Wake Up Status.
1182 *
1183 * Register|BitsName
1184 * --------|--------
1185 * SLP_EVENT | EXT_WKUP_STATUS
1186 *
1187 * @param wakeup_pin This parameter can be a combination of the following values:
1188 * @arg @ref LL_PWR_EXTWKUP_PIN0
1189 * @arg @ref LL_PWR_EXTWKUP_PIN1
1190 * @arg @ref LL_PWR_EXTWKUP_PIN2
1191 * @arg @ref LL_PWR_EXTWKUP_PIN3
1192 * @arg @ref LL_PWR_EXTWKUP_PIN4
1193 * @arg @ref LL_PWR_EXTWKUP_PIN5
1194 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1195 * @retval None
1196 */
1197 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1198 {
1199 GLOBAL_EXCEPTION_DISABLE();
1200 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1201 GLOBAL_EXCEPTION_ENABLE();
1202 }
1203
1204 /**
1205 * @brief Clear the Event that triggered the DeepSleep WakeUp.
1206 *
1207 * Register|BitsName
1208 * --------|--------
1209 * SLP_EVENT | SMCOSCEN_EVENT
1210 * SLP_EVENT | TIMER_EVENT
1211 * SLP_EVENT | EXT_WKUP_EVENT
1212 * SLP_EVENT | WATCHDOG_EVENT
1213 *
1214 * @param event This parameter can be a combination of the following values:
1215 * @arg @ref LL_PWR_WKUP_EVENT_BLE
1216 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
1217 * @arg @ref LL_PWR_WKUP_EVENT_EXT
1218 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
1219 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
1220 * @arg @ref LL_PWR_WKUP_EVENT_WDT
1221 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
1222 * @retval None
1223 */
1224 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1225 {
1226 WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1227 }
1228
1229 /**
1230 * @brief Indicate if the Power State Controller is in busy state.
1231 * @note This is bit set 1 when the PSC_CMD_REQ[0] is set to 1, and will remain 1 until
1232 * the PSC_CMD_OPC has been transferred to the PSC.
1233 *
1234 * Register|BitsName
1235 * --------|--------
1236 * PSC_CMD | MCU_PWR_BUSY
1237 *
1238 * @retval State of bit (1 or 0).
1239 */
1240 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1241 {
1242 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1243 }
1244
1245 /**
1246 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
1247 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
1248 *
1249 * Register|BitsName
1250 * --------|--------
1251 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT
1252 *
1253 * @retval State of bit (1 or 0).
1254 */
1255 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1256 {
1257 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1258 }
1259
1260 /**
1261 * @brief Disable cache function
1262 * @note The cache should be closed before chip go to deepsleep.
1263 *
1264 * Register|BitsName
1265 * --------|--------
1266 * CTRL0 |EN
1267 *
1268 * @retval None
1269 */
1270 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1271 {
1272 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1273 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
1274 }
1275
1276 /** @} */
1277
1278 /** @} */
1279 /** @} */
1280
1281 #endif /* defined(AON) */
1282
1283 #ifdef __cplusplus
1284 }
1285 #endif
1286
1287 #endif /* __GR55xx_LL_PWR_H__ */
1288
1289 /** @} */
1290
1291 /** @} */
1292
1293 /** @} */
ll_pwr_disable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1035
ll_pwr_enable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:485
ll_pwr_get_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
Get which timer value was selected to read.
Definition: gr55xx_ll_pwr.h:808
ll_pwr_enable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1018
ll_pwr_set_dpad_le_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
Definition: gr55xx_ll_pwr.h:535
ll_pwr_disable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
Definition: gr55xx_ll_pwr.h:906
ll_pwr_is_enabled_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1003
ll_pwr_is_enabled_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:769
ll_pwr_set_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
Set the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:407
ll_pwr_is_enabled_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:970
ll_pwr_disable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
Definition: gr55xx_ll_pwr.h:658
ll_pwr_get_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1174
ll_pwr_read_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1135
ll_pwr_get_timer_read_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
Get current timer value based on the selection.
Definition: gr55xx_ll_pwr.h:827
ll_pwr_disable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
Definition: gr55xx_ll_pwr.h:859
ll_pwr_disable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
Definition: gr55xx_ll_pwr.h:612
ll_pwr_set_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:263
LL_PWR_EXTWKUP_PIN_ALL
#define LL_PWR_EXTWKUP_PIN_ALL
WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7.
Definition: gr55xx_ll_pwr.h:155
ll_pwr_read_comm_wakeup_timing_twosc
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1145
ll_pwr_get_comm_sleep_duration
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
Definition: gr55xx_ll_pwr.h:1095
ll_pwr_set_comm_core_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1066
ll_pwr_is_enabled_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:672
ll_pwr_set_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:456
ll_pwr_is_active_flag_psc_cmd_busy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
Indicate if the Power State Controller is in busy state.
Definition: gr55xx_ll_pwr.h:1240
ll_pwr_enable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
Definition: gr55xx_ll_pwr.h:736
ll_pwr_disable_cache_module
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
Definition: gr55xx_ll_pwr.h:1270
ll_pwr_is_enabled_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
Check if the External WakeUp PINx functionality is enabled.
Definition: gr55xx_ll_pwr.h:379
ll_pwr_enable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
Definition: gr55xx_ll_pwr.h:643
ll_pwr_clear_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1197
ll_pwr_set_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
Select which timer value to read.
Definition: gr55xx_ll_pwr.h:788
ll_pwr_disable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:500
LL_PWR_WKUP_EVENT_ALL
#define LL_PWR_WKUP_EVENT_ALL
All event mask
Definition: gr55xx_ll_pwr.h:135
LL_PWR_EXTWKUP_INVERT_LSB
#define LL_PWR_EXTWKUP_INVERT_LSB
External wakeup level invert.
Definition: gr55xx_ll_pwr.h:80
ll_pwr_is_enabled_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:514
ll_pwr_enable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
Definition: gr55xx_ll_pwr.h:597
ll_pwr_is_active_flag_comm_deep_sleep_stat
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1255
ll_pwr_disable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
Definition: gr55xx_ll_pwr.h:752
ll_pwr_clear_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:1224
ll_pwr_disable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
Disable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:355
ll_pwr_get_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:284
ll_pwr_enable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
Definition: gr55xx_ll_pwr.h:687
ll_pwr_set_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1116
ll_pwr_enable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:937
ll_pwr_disable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:954
ll_pwr_enable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
Enable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:331
ll_pwr_is_enabled_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1051
LL_PWR_EXTWKUP_TYPE_LSB
#define LL_PWR_EXTWKUP_TYPE_LSB
External wakeup level type.
Definition: gr55xx_ll_pwr.h:79
ll_pwr_enable_comm_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
Definition: gr55xx_ll_pwr.h:986
ll_pwr_enable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
Definition: gr55xx_ll_pwr.h:889
ll_pwr_get_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:309
ll_pwr_enable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
Definition: gr55xx_ll_pwr.h:841
ll_pwr_get_comm_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1080
ll_pwr_is_enabled_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:626
ll_pwr_is_enabled_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:721
ll_pwr_get_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:470
ll_pwr_get_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
Get the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:439
ll_pwr_is_enabled_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:922
ll_pwr_is_enabled_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:875
ll_pwr_req_excute_psc_command
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
Request to excute the Power State Controller Command.
Definition: gr55xx_ll_pwr.h:574
ll_pwr_disable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
Definition: gr55xx_ll_pwr.h:704