51 #ifndef __GR55XX_LL_HMAC_H__
52 #define __GR55XX_LL_HMAC_H__
101 #define LL_HMAC_FLAG_DATAREADY_SHA HMAC_STATUS_DATAREADY_SHA
102 #define LL_HMAC_FLAG_DATAREADY_HMAC HMAC_STATUS_DATAREADY_HMAC
103 #define LL_HMAC_FLAG_DMA_MESSAGEDONE HMAC_STATUS_MESSAGEDONE_DMA
104 #define LL_HMAC_FLAG_DMA_DONE HMAC_STATUS_TRANSDONE_DMA
105 #define LL_HMAC_FLAG_DMA_ERR HMAC_STATUS_TRANSERR_DMA
106 #define LL_HMAC_FLAG_KEY_VALID HMAC_STATUS_KEYVALID
112 #define LL_HMAC_HASH_STANDARD 0x00000000U
113 #define LL_HMAC_HASH_USER (1UL << HMAC_CONFIG_ENABLE_USERHASH)
119 #define LL_HMAC_CALCULATETYPE_HMAC 0x00000000U
120 #define LL_HMAC_CALCULATETYPE_SHA (1UL << HMAC_CONFIG_CALCTYPE_Pos)
126 #define LL_HMAC_KEYTYPE_MCU 0x00000000U
127 #define LL_HMAC_KEYTYPE_AHB (1UL << HMAC_CONFIG_KEYTYPE_Pos)
128 #define LL_HMAC_KEYTYPE_KRAM (2UL << HMAC_CONFIG_KEYTYPE_Pos)
134 #define LL_HMAC_DMA_TRANSIZE_MIN (1)
135 #define LL_HMAC_DMA_TRANSIZE_MAX (512)
156 #define LL_HMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
164 #define LL_HMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
193 SET_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE);
208 CLEAR_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE);
223 return (READ_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE) == (HMAC_CTRL_ENABLE));
238 SET_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA);
253 CLEAR_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA);
268 return (READ_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA) == (HMAC_CTRL_START_DMA));
283 SET_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE_RKEY);
298 SET_BITS(HMACx->CTRL, HMAC_CTRL_LASTTRANSFER);
313 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH);
328 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH);
343 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH) == (HMAC_CONFIG_ENABLE_USERHASH));
358 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN);
373 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN);
388 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN) == (HMAC_CONFIG_ENDIAN));
407 MODIFY_REG(HMACx->CONFIG, HMAC_CONFIG_KEYTYPE, type);
425 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_KEYTYPE));
440 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE);
455 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE);
470 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE) == (HMAC_CONFIG_CALCTYPE));
485 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE);
500 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE);
515 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE) == (HMAC_CONFIG_PRIVATE));
536 SET_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE);
551 CLEAR_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE);
566 return (READ_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE) == (HMAC_INTERRUPT_ENABLE));
587 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_DATAREADY_SHA) == HMAC_STATUS_DATAREADY_SHA);
602 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_DATAREADY_HMAC) == HMAC_STATUS_DATAREADY_HMAC);
617 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_MESSAGEDONE_DMA) == HMAC_STATUS_MESSAGEDONE_DMA);
632 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_TRANSDONE_DMA) == HMAC_STATUS_TRANSDONE_DMA);
647 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_TRANSERR_DMA) == HMAC_STATUS_TRANSERR_DMA);
662 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_KEYVALID) == HMAC_STATUS_KEYVALID);
677 return (READ_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_DONE) == HMAC_INTERRUPT_DONE);
692 CLEAR_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_DONE);
714 MODIFY_REG(HMACx->TRAN_SIZE, HMAC_TRANSIZE, (block << 6) - 1);
729 return ((READ_BITS(HMACx->TRAN_SIZE, HMAC_TRANSIZE) + 1) >> 6);
745 WRITE_REG(HMACx->RSTART_ADDR, address);
760 return (READ_REG(HMACx->RSTART_ADDR));
776 WRITE_REG(HMACx->WSTART_ADDR, address);
791 return (READ_REG(HMACx->WSTART_ADDR));
813 WRITE_REG(HMACx->USER_HASH[0], hash);
829 WRITE_REG(HMACx->USER_HASH[1], hash);
845 WRITE_REG(HMACx->USER_HASH[2], hash);
861 WRITE_REG(HMACx->USER_HASH[3], hash);
877 WRITE_REG(HMACx->USER_HASH[4], hash);
893 WRITE_REG(HMACx->USER_HASH[5], hash);
909 WRITE_REG(HMACx->USER_HASH[6], hash);
925 WRITE_REG(HMACx->USER_HASH[7], hash);
940 return (READ_REG(HMACx->FIFO_OUT));
956 WRITE_REG(HMACx->MESSAGE_FIFO, data);
972 WRITE_REG(HMACx->KEY[0], key);
988 WRITE_REG(HMACx->KEY[1], key);
1004 WRITE_REG(HMACx->KEY[2], key);
1020 WRITE_REG(HMACx->KEY[3], key);
1036 WRITE_REG(HMACx->KEY[4], key);
1052 WRITE_REG(HMACx->KEY[5], key);
1068 WRITE_REG(HMACx->KEY[6], key);
1084 WRITE_REG(HMACx->KEY[7], key);
1100 WRITE_REG(HMACx->KEY_ADDR, address);
1115 return (READ_REG(HMACx->KEY_ADDR));
1131 WRITE_REG(HMACx->KPORT_MASK, mask);