gr55xx_ll_i2s.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2s.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2S LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2S I2S
47 * @brief I2S LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2S_M) || defined (I2S_S)
63
64 /** @defgroup LL_I2S_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2S_LL_ES_INIT I2S Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2S init structures definition
75 */
76 typedef struct _ll_i2s_init_t
77 {
78 uint32_t rxdata_size; /**< Specifies the I2S receive data size.
79 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
80
81 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rxsize().*/
82
83 uint32_t txdata_size; /**< Specifies the I2S transmit data size.
84 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_i2s_set_txsize().*/
87
88 uint32_t rx_threshold; /**< Specifies the I2S receive FIFO threshold.
89 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
90
91 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rx_fifo_threshold().*/
92
93 uint32_t tx_threshold; /**< Specifies the I2S transmit FIFO threshold.
94 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
95
96 This feature can be modified afterwards using unitary function @ref ll_i2s_set_tx_fifo_threshold().*/
97
98 uint32_t clock_source; /**< Specifies the source of the I2S clock.
99 This parameter can be a value of @ref I2S_LL_EC_CLOCK_SOURCE.
100
101 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_src().*/
102
103 uint32_t audio_freq; /**< Specifies the frequency selected for the I2S communication.
104
105 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_div().*/
106
107 } ll_i2s_init_t;
108
109 /** @} */
110
111 /** @} */
112
113 /**
114 * @defgroup I2S_LL_MACRO Defines
115 * @{
116 */
117
118 /* Exported constants --------------------------------------------------------*/
119 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
120 * @{
121 */
122
123 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
124 * @brief Flags definitions which can be used with LL_I2S_ReadReg function
125 * @{
126 */
127 #define LL_I2S_STATUS_TXFO I2S_INTSTAT_TXFO /**< TX FIFO write overflow flag */
128 #define LL_I2S_STATUS_TXFE I2S_INTSTAT_TXFE /**< TX FIFO threshold level is not reached flag */
129 #define LL_I2S_STATUS_RXFO I2S_INTSTAT_RXFO /**< RX FIFO receive overflow flag */
130 #define LL_I2S_STATUS_RXDA I2S_INTSTAT_RXDA /**< RX FIFO threshold level is reached flag */
131 /** @} */
132
133 /** @defgroup I2S_LL_EC_INTERRUPT Interrupt Defines
134 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
135 * @{
136 */
137 #define LL_I2S_INT_TXFO I2S_INTMASK_TXFO /**< TX FIFO write overflow interrupt */
138 #define LL_I2S_INT_TXFE I2S_INTMASK_TXFE /**< TX FIFO threshold level is not reached interrupt */
139 #define LL_I2S_INT_RXFO I2S_INTMASK_RXFO /**< RX FIFO receive overflow interrupt */
140 #define LL_I2S_INT_RXDA I2S_INTMASK_RXDA /**< RX FIFO threshold level is reached interrupt */
141 /** @} */
142
143 /** @defgroup I2S_LL_EC_CLOCK_SOURCE I2S Clock Source
144 * @{
145 */
146 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL) /**< I2S clock source select: 96M */
147 #define LL_I2S_CLOCK_SRC_32M (1UL << 18) /**< I2S clock source select: 32M */
148 /** @} */
149
150 /** @defgroup I2S_LL_EC_DATASIZE Transfer Data width
151 * @{
152 */
153 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL) /**< Data size for I2S transfer: 32 bits */
154 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 12 bits */
155 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 16 bits */
156 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 20 bits */
157 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 24 bits */
158 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 32 bits */
159 /** @} */
160
161 /** @defgroup I2S_LL_EC_TRANSFER_MODE Transfer Mode
162 * @{
163 */
164 #define LL_I2S_SIMPLEX_TX (1UL) /**< Simplex TX mode. */
165 #define LL_I2S_SIMPLEX_RX (2UL) /**< Simplex RX mode. */
166 #define LL_I2S_FULL_DUPLEX (3UL) /**< Full-Duplex mode. */
167 /** @} */
168
169 /** @defgroup I2S_LL_EC_FIFO_THRESHOLD FIFO Threshold
170 * @{
171 */
172 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL) /**< Trigger level for FIFO: 1 depth. */
173 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 2 depth. */
174 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 3 depth. */
175 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 4 depth. */
176 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 5 depth. */
177 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 6 depth. */
178 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 7 depth. */
179 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 8 depth. */
180 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 9 depth. */
181 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 10 depth. */
182 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 11 depth. */
183 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 12 depth. */
184 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 13 depth. */
185 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 14 depth. */
186 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 15 depth. */
187 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 16 depth. */
188 /** @} */
189
190 /** @defgroup I2S_LL_EC_WS_CYCLES Word Select Line Cycles
191 * @{
192 */
193 #define LL_I2S_WS_CYCLES_16 (0x00000000UL) /**< 16 SCLK cycles in word select line. */
194 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_CLKCONFIG_WSS_Pos) /**< 24 SCLK cycles in word select line. */
195 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_CLKCONFIG_WSS_Pos) /**< 32 SCLK cycles in word select line. */
196 /** @} */
197
198 /** @defgroup I2S_LL_EC_SCLK_GATE SCLK Gate
199 * @{
200 */
201 #define LL_I2S_SCLKG_NONE (0x00000000UL) /**< Clock gating is disabled. */
202 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 12 sclk cycles. */
203 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 16 sclk cycles. */
204 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 20 sclk cycles. */
205 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 24 sclk cycles. */
206 /** @} */
207
208 /** @defgroup I2S_LL_EC_RESOLUTION RX/TX resolution of one channel
209 * @{
210 */
211 #define LL_I2S_RESOLUTION_12BIT (0UL) /**< 12 bits resolution. */
212 #define LL_I2S_RESOLUTION_16BIT (1UL) /**< 16 bits resolution. */
213 #define LL_I2S_RESOLUTION_20BIT (2UL) /**< 20 bits resolution. */
214 #define LL_I2S_RESOLUTION_24BIT (3UL) /**< 24 bits resolution. */
215 #define LL_I2S_RESOLUTION_32BIT (4UL) /**< 32 bits resolution. */
216 /** @} */
217
218 /** @defgroup I2S_LL_EC_CHANNELS the number of RX/TX channels
219 * @{
220 */
221 #define LL_I2S_CHANNEL_NUM_1 (0UL) /**< 1 channel. */
222 #define LL_I2S_CHANNEL_NUM_2 (1UL) /**< 2 channels. */
223 #define LL_I2S_CHANNEL_NUM_3 (2UL) /**< 3 channels. */
224 #define LL_I2S_CHANNEL_NUM_4 (3UL) /**< 4 channels. */
225 /** @} */
226
227 /** @defgroup I2S_LL_EC_FIFO_DEPTH RX/TX FIFO depth
228 * @{
229 */
230 #define LL_I2S_FIFO_DEPTH_2 (0UL) /**< FIFO depth is 2 . */
231 #define LL_I2S_FIFO_DEPTH_4 (1UL) /**< FIFO depth is 4 . */
232 #define LL_I2S_FIFO_DEPTH_8 (2UL) /**< FIFO depth is 8 . */
233 #define LL_I2S_FIFO_DEPTH_16 (3UL) /**< FIFO depth is 16. */
234 /** @} */
235
236 /** @defgroup I2S_LL_EC_APB_WIDTH APB data width
237 * @{
238 */
239 #define LL_I2S_APB_WIDTH_8BIT (0UL) /**< 8 bits APB data width. */
240 #define LL_I2S_APB_WIDTH_16BIT (1UL) /**< 16 bits APB data width. */
241 #define LL_I2S_APB_WIDTH_32BIT (2UL) /**< 32 bits APB data width. */
242 /** @} */
243
244 /** @} */
245
246 /** @defgroup I2S_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
247 * @{
248 */
249
250 /**
251 * @brief LL I2S InitStrcut default configuartion
252 */
253 #define LL_I2S_DEFAULT_CONFIG \
254 { \
255 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
256 .txdata_size = LL_I2S_DATASIZE_16BIT, \
257 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
258 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
259 .clock_source = LL_I2S_CLOCK_SRC_32M, \
260 .audio_freq = 48000 \
261 }
262
263 /** @} */
264
265 /* Exported macro ------------------------------------------------------------*/
266 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
267 * @{
268 */
269
270 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
271 * @{
272 */
273
274 /**
275 * @brief Write a value in I2S register
276 * @param __instance__ I2S instance
277 * @param __REG__ Register to be written
278 * @param __VALUE__ Value to be written in the register
279 * @retval None
280 */
281 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
282
283 /**
284 * @brief Read a value in I2S register
285 * @param __instance__ I2S instance
286 * @param __REG__ Register to be read
287 * @retval Register value
288 */
289 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
290
291 /** @} */
292
293 /** @} */
294 /** @} */
295
296 /* Exported functions --------------------------------------------------------*/
297 /** @defgroup I2S_LL_DRIVER_FUNCTIONS Functions
298 * @{
299 */
300
301 /** @defgroup I2S_LL_EF_Configuration Configuration functions
302 * @{
303 */
304
305 /**
306 * @brief Enable I2S
307 *
308 * Register|BitsName
309 * --------|--------
310 * ENABLE | EN
311 *
312 * @param I2Sx I2S instance
313 * @retval None
314 */
315 __STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
316 {
317 SET_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
318 }
319
320 /**
321 * @brief Disable I2S
322 *
323 * Register|BitsName
324 * --------|--------
325 * ENABLE | EN
326 *
327 * @param I2Sx I2S instance
328 * @retval None
329 */
330 __STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
331 {
332 CLEAR_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
333 }
334
335 /**
336 * @brief Check if I2S is enabled
337 *
338 * Register|BitsName
339 * --------|--------
340 * ENABLE | EN
341 *
342 * @param I2Sx I2S instance
343 * @retval State of bit (1 or 0).
344 */
345 __STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
346 {
347 return (READ_BITS(I2Sx->ENABLE, I2S_ENABLE_EN) == (I2S_ENABLE_EN));
348 }
349
350 /**
351 * @brief Enable I2S RX block
352 *
353 * Register|BitsName
354 * --------|--------
355 * RBEN | EN
356 *
357 * @param I2Sx I2S instance
358 * @retval None
359 */
360 __STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
361 {
362 SET_BITS(I2Sx->RBEN, I2S_RBEN_EN);
363 }
364
365 /**
366 * @brief Disable I2S RX block
367 *
368 * Register|BitsName
369 * --------|--------
370 * RBEN | EN
371 *
372 * @param I2Sx I2S instance
373 * @retval None
374 */
375 __STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
376 {
377 CLEAR_BITS(I2Sx->RBEN, I2S_RBEN_EN);
378 }
379
380 /**
381 * @brief Check if I2S RX block is enabled
382 *
383 * Register|BitsName
384 * --------|--------
385 * RBEN | EN
386 *
387 * @param I2Sx I2S instance
388 * @retval State of bit (1 or 0).
389 */
390 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
391 {
392 return (READ_BITS(I2Sx->RBEN, I2S_RBEN_EN) == (I2S_RBEN_EN));
393 }
394
395 /**
396 * @brief Enable I2S TX block
397 *
398 * Register|BitsName
399 * --------|--------
400 * TBEN | EN
401 *
402 * @param I2Sx I2S instance
403 * @retval None
404 */
405 __STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
406 {
407 SET_BITS(I2Sx->TBEN, I2S_TBEN_EN);
408 }
409
410 /**
411 * @brief Disable I2S TX block
412 *
413 * Register|BitsName
414 * --------|--------
415 * TBEN | EN
416 *
417 * @param I2Sx I2S instance
418 * @retval None
419 */
420 __STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
421 {
422 CLEAR_BITS(I2Sx->TBEN, I2S_TBEN_EN);
423 }
424
425 /**
426 * @brief Check if I2S TX block is enabled
427 *
428 * Register|BitsName
429 * --------|--------
430 * TBEN | EN
431 *
432 * @param I2Sx I2S instance
433 * @retval State of bit (1 or 0).
434 */
435 __STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
436 {
437 return (READ_BITS(I2Sx->TBEN, I2S_TBEN_EN) == (I2S_TBEN_EN));
438 }
439
440 /**
441 * @brief Enable I2S clock
442 *
443 * Register|BitsName
444 * --------|--------
445 * CLKEN | EN
446 *
447 * @param I2Sx I2S instance
448 * @retval None
449 */
450 __STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
451 {
452 SET_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
453 }
454
455 /**
456 * @brief Disable I2S clock
457 *
458 * Register|BitsName
459 * --------|--------
460 * CLKEN | EN
461 *
462 * @param I2Sx I2S instance
463 * @retval None
464 */
465 __STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
466 {
467 CLEAR_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
468 }
469
470 /**
471 * @brief Check if I2S clock is enabled
472 *
473 * Register|BitsName
474 * --------|--------
475 * CLKEN | EN
476 *
477 * @param I2Sx I2S instance
478 * @retval State of bit (1 or 0).
479 */
480 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
481 {
482 return (READ_BITS(I2Sx->CLKEN, I2S_CLKEN_EN) == (I2S_CLKEN_EN));
483 }
484
485 /**
486 * @brief Set word select line cycles for left or right sample
487 * @note This bit should be written only when I2S is disabled (I2S_EN = 0) for correct operation.
488 *
489 * Register|BitsName
490 * --------|--------
491 * CLKCONFIG | WSS
492 *
493 * @param I2Sx I2S instance
494 * @param cycles This parameter can be one of the following values:
495 * @arg @ref LL_I2S_WS_CYCLES_16
496 * @arg @ref LL_I2S_WS_CYCLES_24
497 * @arg @ref LL_I2S_WS_CYCLES_32
498 * @retval None
499 */
500 __STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
501 {
502 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS, cycles);
503 }
504
505 /**
506 * @brief Get word select line cycles for left or right sample
507 *
508 * Register|BitsName
509 * --------|--------
510 * CLKCONFIG | WSS
511 *
512 * @param I2Sx I2S instance
513 * @retval Returned Value can be one of the following values:
514 * @arg @ref LL_I2S_WS_CYCLES_16
515 * @arg @ref LL_I2S_WS_CYCLES_24
516 * @arg @ref LL_I2S_WS_CYCLES_32
517 */
518 __STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
519 {
520 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS));
521 }
522
523 /**
524 * @brief Set the gating of sclk
525 *
526 * Register|BitsName
527 * --------|--------
528 * CLKCONFIG | SCLKG
529 *
530 * @param I2Sx I2S instance
531 * @param cycles This parameter can be one of the following values:
532 * @arg @ref LL_I2S_SCLKG_NONE
533 * @arg @ref LL_I2S_SCLKG_CYCLES_12
534 * @arg @ref LL_I2S_SCLKG_CYCLES_16
535 * @arg @ref LL_I2S_SCLKG_CYCLES_20
536 * @arg @ref LL_I2S_SCLKG_CYCLES_24
537 * @retval None
538 */
539 __STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
540 {
541 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG, cycles);
542 }
543
544 /**
545 * @brief Get the gating of sclk
546 *
547 * Register|BitsName
548 * --------|--------
549 * CLKCONFIG | SCLKG
550 *
551 * @param I2Sx I2S instance
552 * @retval Returned Value can be one of the following values:
553 * @arg @ref LL_I2S_SCLKG_NONE
554 * @arg @ref LL_I2S_SCLKG_CYCLES_12
555 * @arg @ref LL_I2S_SCLKG_CYCLES_16
556 * @arg @ref LL_I2S_SCLKG_CYCLES_20
557 * @arg @ref LL_I2S_SCLKG_CYCLES_24
558 */
559 __STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
560 {
561 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG));
562 }
563
564 /**
565 * @brief Clear I2S RX FIFO in all channels
566 *
567 * Register|BitsName
568 * --------|--------
569 * RXFIFO_RST | RST
570 *
571 * @param I2Sx I2S instance
572 * @retval None
573 */
574 __STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
575 {
576 WRITE_REG(I2Sx->RXFIFO_RST, I2S_RXFIFO_RST);
577 }
578
579 /**
580 * @brief Clear I2S TX FIFO in all channels
581 *
582 * Register|BitsName
583 * --------|--------
584 * TXFIFO_RST | RST
585 *
586 * @param I2Sx I2S instance
587 * @retval None
588 */
589 __STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
590 {
591 WRITE_REG(I2Sx->TXFIFO_RST, I2S_TXFIFO_RST);
592 }
593
594 /**
595 * @brief Set I2S clock divider
596 *
597 * Register|BitsName
598 * --------|--------
599 * I2S_CLK_CFG | DIV
600 *
601 * @param div This parameter can between: 0 ~ 0xFFF
602 * @retval None
603 */
604 __STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
605 {
606 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
607 }
608
609 /**
610 * @brief Get I2S clock divider
611 *
612 * Register|BitsName
613 * --------|--------
614 * I2S_CLK_CFG | DIV
615 *
616 * @retval Returned Value can between: 0 ~ 0xFFF
617 */
618 __STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
619 {
620 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
621 }
622
623 /**
624 * @brief Enable I2S clock divider
625 *
626 * Register|BitsName
627 * --------|--------
628 * I2S_CLK_CFG | DIV_EN
629 *
630 * @retval None
631 */
632 __STATIC_INLINE void ll_i2s_enable_clock_div(void)
633 {
634 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
635 }
636
637 /**
638 * @brief Disable I2S clock divider
639 *
640 * Register|BitsName
641 * --------|--------
642 * I2S_CLK_CFG | DIV_EN
643 *
644 * @retval None
645 */
646 __STATIC_INLINE void ll_i2s_disable_clock_div(void)
647 {
648 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
649 }
650
651 /**
652 * @brief Check if I2S clock divider is enabled
653 *
654 * Register|BitsName
655 * --------|--------
656 * I2S_CLK_CFG | DIV_EN
657 *
658 * @retval State of bit (1 or 0).
659 */
660 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
661 {
662 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
663 }
664
665 /**
666 * @brief Set I2S clock source
667 *
668 * Register|BitsName
669 * --------|--------
670 * I2S_CLK_CFG | SRC
671 *
672 * @param src This parameter can be one of the following values:
673 * @arg @ref LL_I2S_CLOCK_SRC_96M
674 * @arg @ref LL_I2S_CLOCK_SRC_32M
675 * @retval None
676 */
677 __STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
678 {
679 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
680 }
681
682 /**
683 * @brief Get I2S clock source
684 *
685 * Register|BitsName
686 * --------|--------
687 * I2S_CLK_CFG | SRC
688 *
689 * @retval Returned Value can be one of the following values:
690 * @arg @ref LL_I2S_CLOCK_SRC_96M
691 * @arg @ref LL_I2S_CLOCK_SRC_32M
692 */
693 __STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
694 {
695 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
696 }
697
698 /** @} */
699
700 /** @defgroup I2S_LL_EF_Channel Channel Configuration functions
701 * @{
702 */
703
704 /**
705 * @brief Read one data from left RX FIFO in a channel
706 *
707 * Register|BitsName
708 * --------|--------
709 * DATA_L | DATA
710 *
711 * @param I2Sx I2S instance
712 * @param channel The special channel: 0 ~ 3
713 * @retval None
714 */
715 __STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
716 {
717 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_L));
718 }
719
720 /**
721 * @brief Read one data from right RX FIFO in a channel
722 *
723 * Register|BitsName
724 * --------|--------
725 * DATA_R | DATA
726 *
727 * @param I2Sx I2S instance
728 * @param channel The special channel: 0 ~ 3
729 * @retval None
730 */
731 __STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
732 {
733 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_R));
734 }
735
736 /**
737 * @brief Write one data to left TX FIFO in a channel
738 *
739 * Register|BitsName
740 * --------|--------
741 * DATA_L | DATA
742 *
743 * @param I2Sx I2S instance
744 * @param channel The special channel: 0 ~ 3
745 * @param data The data to send
746 * @retval None
747 */
748 __STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
749 {
750 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_L, data);
751 }
752
753 /**
754 * @brief Write one data to right TX FIFO in a channel
755 *
756 * Register|BitsName
757 * --------|--------
758 * DATA_R | DATA
759 *
760 * @param I2Sx I2S instance
761 * @param channel The special channel: 0 ~ 3
762 * @param data The data to send
763 * @retval None
764 */
765 __STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
766 {
767 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_R, data);
768 }
769
770 /**
771 * @brief Enable RX in a channel
772 *
773 * Register|BitsName
774 * --------|--------
775 * RXEN | EN
776 *
777 * @param I2Sx I2S instance
778 * @param channel The special channel: 0 ~ 3
779 * @retval None
780 */
781 __STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
782 {
783 SET_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
784 }
785
786 /**
787 * @brief Disable RX in a channel
788 *
789 * Register|BitsName
790 * --------|--------
791 * RXEN | EN
792 *
793 * @param I2Sx I2S instance
794 * @param channel The special channel: 0 ~ 3
795 * @retval None
796 */
797 __STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
798 {
799 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
800 }
801
802 /**
803 * @brief Check if RX in a channel is enabled
804 *
805 * Register|BitsName
806 * --------|--------
807 * RXEN | EN
808 *
809 * @param I2Sx I2S instance
810 * @param channel The special channel: 0 ~ 3
811 * @retval State of bit (1 or 0).
812 */
813 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
814 {
815 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN) != (I2S_RXEN_EN));
816 }
817
818 /**
819 * @brief Enable TX in a channel
820 *
821 * Register|BitsName
822 * --------|--------
823 * TXEN | EN
824 *
825 * @param I2Sx I2S instance
826 * @param channel The special channel: 0 ~ 3
827 * @retval None
828 */
829 __STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
830 {
831 SET_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
832 }
833
834 /**
835 * @brief Disable TX in a channel
836 *
837 * Register|BitsName
838 * --------|--------
839 * TXEN | EN
840 *
841 * @param I2Sx I2S instance
842 * @param channel The special channel: 0 ~ 3
843 * @retval None
844 */
845 __STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
846 {
847 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
848 }
849
850 /**
851 * @brief Check if TX in a channel is enabled
852 *
853 * Register|BitsName
854 * --------|--------
855 * TXEN | EN
856 *
857 * @param I2Sx I2S instance
858 * @param channel The special channel: 0 ~ 3
859 * @retval State of bit (1 or 0).
860 */
861 __STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
862 {
863 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN) != (I2S_TXEN_EN));
864 }
865
866 /**
867 * @brief Set receive data width in a channel
868 * @note These bits should not be changed when channel is enabled.
869 *
870 * Register|BitsName
871 * --------|--------
872 * RXSIZE | WLEN
873 *
874 * @param I2Sx I2S instance
875 * @param channel The special channel: 0 ~ 3
876 * @param size This parameter can be one of the following values:
877 * @arg @ref LL_I2S_DATASIZE_IGNORE
878 * @arg @ref LL_I2S_DATASIZE_12BIT
879 * @arg @ref LL_I2S_DATASIZE_16BIT
880 * @arg @ref LL_I2S_DATASIZE_20BIT
881 * @arg @ref LL_I2S_DATASIZE_24BIT
882 * @arg @ref LL_I2S_DATASIZE_32BIT
883 * @retval None
884 */
885 __STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
886 {
887 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN, size);
888 }
889
890 /**
891 * @brief Get receive data width in a channel
892 *
893 * Register|BitsName
894 * --------|--------
895 * RXSIZE | WLEN
896 *
897 * @param I2Sx I2S instance
898 * @param channel The special channel: 0 ~ 3
899 * @retval Returned Value can be one of the following values:
900 * @arg @ref LL_I2S_DATASIZE_IGNORE
901 * @arg @ref LL_I2S_DATASIZE_12BIT
902 * @arg @ref LL_I2S_DATASIZE_16BIT
903 * @arg @ref LL_I2S_DATASIZE_20BIT
904 * @arg @ref LL_I2S_DATASIZE_24BIT
905 * @arg @ref LL_I2S_DATASIZE_32BIT
906 */
907 __STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
908 {
909 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN));
910 }
911
912 /**
913 * @brief Set transmit data width in a channel
914 * @note These bits should not be changed when channel is enabled.
915 *
916 * Register|BitsName
917 * --------|--------
918 * TXSIZE | WLEN
919 *
920 * @param I2Sx I2S instance
921 * @param channel The special channel: 0 ~ 3
922 * @param size This parameter can be one of the following values:
923 * @arg @ref LL_I2S_DATASIZE_IGNORE
924 * @arg @ref LL_I2S_DATASIZE_12BIT
925 * @arg @ref LL_I2S_DATASIZE_16BIT
926 * @arg @ref LL_I2S_DATASIZE_20BIT
927 * @arg @ref LL_I2S_DATASIZE_24BIT
928 * @arg @ref LL_I2S_DATASIZE_32BIT
929 * @retval None
930 */
931 __STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
932 {
933 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN, size);
934 }
935
936 /**
937 * @brief Get transmit data width in a channel
938 *
939 * Register|BitsName
940 * --------|--------
941 * TXSIZE | WLEN
942 *
943 * @param I2Sx I2S instance
944 * @param channel The special channel: 0 ~ 3
945 * @retval Returned Value can be one of the following values:
946 * @arg @ref LL_I2S_DATASIZE_IGNORE
947 * @arg @ref LL_I2S_DATASIZE_12BIT
948 * @arg @ref LL_I2S_DATASIZE_16BIT
949 * @arg @ref LL_I2S_DATASIZE_20BIT
950 * @arg @ref LL_I2S_DATASIZE_24BIT
951 * @arg @ref LL_I2S_DATASIZE_32BIT
952 */
953 __STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
954 {
955 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN));
956 }
957
958 /**
959 * @brief Get interrupt flag in a channel
960 *
961 * Register|BitsName
962 * --------|--------
963 * INTSTAT | TXFO
964 * INTSTAT | TXFE
965 * INTSTAT | RXFO
966 * INTSTAT | RXDA
967 *
968 * @param I2Sx I2S instance
969 * @param channel The special channel: 0 ~ 3
970 * @retval Returned Value can be one or more of the following values:
971 * @arg @ref LL_I2S_STATUS_TXFO
972 * @arg @ref LL_I2S_STATUS_TXFE
973 * @arg @ref LL_I2S_STATUS_RXFO
974 * @arg @ref LL_I2S_STATUS_RXDA
975 */
976 __STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
977 {
978 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, I2S_INTSTAT_TXFO | I2S_INTSTAT_TXFE | \
979 I2S_INTSTAT_RXFO | I2S_INTSTAT_RXDA));
980 }
981
982 /**
983 * @brief Check interrupt flag in a channel
984 *
985 * Register|BitsName
986 * --------|--------
987 * INTSTAT | TXFO
988 * INTSTAT | TXFE
989 * INTSTAT | RXFO
990 * INTSTAT | RXDA
991 *
992 * @param I2Sx I2S instance
993 * @param channel The special channel: 0 ~ 3
994 * @retval flag This parameter can be one or more of the following values:
995 * @arg @ref LL_I2S_STATUS_TXFO
996 * @arg @ref LL_I2S_STATUS_TXFE
997 * @arg @ref LL_I2S_STATUS_RXFO
998 * @arg @ref LL_I2S_STATUS_RXDA
999 * @retval State of bit (1 or 0).
1000 */
1001 __STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
1002 {
1003 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, flag) == flag);
1004 }
1005
1006 /**
1007 * @brief Enable interrupt in a channel
1008 *
1009 * Register|BitsName
1010 * --------|--------
1011 * INTMASK | TXFO
1012 * INTMASK | TXFE
1013 * INTMASK | RXFO
1014 * INTMASK | RXDA
1015 *
1016 * @param I2Sx I2S instance
1017 * @param channel The special channel: 0 ~ 3
1018 * @param mask This parameter can be one or more of the following values:
1019 * @arg @ref LL_I2S_INT_TXFO
1020 * @arg @ref LL_I2S_INT_TXFE
1021 * @arg @ref LL_I2S_INT_RXFO
1022 * @arg @ref LL_I2S_INT_RXDA
1023 * @retval None
1024 */
1025 __STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1026 {
1027 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1028 }
1029
1030 /**
1031 * @brief Disable interrupt in a channel
1032 *
1033 * Register|BitsName
1034 * --------|--------
1035 * INTMASK | TXFO
1036 * INTMASK | TXFE
1037 * INTMASK | RXFO
1038 * INTMASK | RXDA
1039 *
1040 * @param I2Sx I2S instance
1041 * @param channel The special channel: 0 ~ 3
1042 * @param mask This parameter can be one or more of the following values:
1043 * @arg @ref LL_I2S_INT_TXFO
1044 * @arg @ref LL_I2S_INT_TXFE
1045 * @arg @ref LL_I2S_INT_RXFO
1046 * @arg @ref LL_I2S_INT_RXDA
1047 * @retval None
1048 */
1049 __STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1050 {
1051 SET_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1052 }
1053
1054 /**
1055 * @brief Check if interrupt in a channel is enabled
1056 *
1057 * Register|BitsName
1058 * --------|--------
1059 * INTMASK | TXFO
1060 * INTMASK | TXFE
1061 * INTMASK | RXFO
1062 * INTMASK | RXDA
1063 *
1064 * @param I2Sx I2S instance
1065 * @param channel The special channel: 0 ~ 3
1066 * @param mask This parameter can be one or more of the following values:
1067 * @arg @ref LL_I2S_INT_TXFO
1068 * @arg @ref LL_I2S_INT_TXFE
1069 * @arg @ref LL_I2S_INT_RXFO
1070 * @arg @ref LL_I2S_INT_RXDA
1071 * @retval State of bit (1 or 0).
1072 */
1073 __STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1074 {
1075 return ((READ_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask) ^ (mask)) == (mask));
1076 }
1077
1078 /**
1079 * @brief Clear RX FIFO data overrun interrupt flag in a channel
1080 *
1081 * Register|BitsName
1082 * --------|--------
1083 * RXOVR | RXCHO
1084 *
1085 * @param I2Sx I2S instance
1086 * @param channel The special channel: 0 ~ 3
1087 * @retval State of bit (1 or 0).
1088 */
1089 __STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
1090 {
1091 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXOVR, I2S_RXOVR_RXCHO));
1092 }
1093
1094 /**
1095 * @brief Clear TX FIFO data overrun interrupt flag in a channel
1096 *
1097 * Register|BitsName
1098 * --------|--------
1099 * TXOVR | TXCHO
1100 *
1101 * @param I2Sx I2S instance
1102 * @param channel The special channel: 0 ~ 3
1103 * @retval State of bit (1 or 0).
1104 */
1105 __STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
1106 {
1107 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXOVR, I2S_TXOVR_TXCHO));
1108 }
1109
1110 /**
1111 * @brief Set threshold of RXFIFO in a channel that triggers an RXDA event
1112 *
1113 * Register|BitsName
1114 * --------|--------
1115 * RXFIFO_TL | TL
1116 *
1117 * @param I2Sx I2S instance
1118 * @param channel The special channel: 0 ~ 3
1119 * @param threshold This parameter can be one of the following values:
1120 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1121 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1122 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1123 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1124 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1125 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1126 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1127 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1128 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1129 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1130 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1131 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1132 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1133 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1134 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1135 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1136 * @retval None
1137 */
1138 __STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1139 {
1140 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, threshold);
1141 }
1142
1143 /**
1144 * @brief Get threshold of RXFIFO in a channel that triggers an RXDA event
1145 *
1146 * Register|BitsName
1147 * --------|--------
1148 * RXFIFO_TL | TL
1149 *
1150 * @param I2Sx I2S instance
1151 * @param channel The special channel: 0 ~ 3
1152 * @retval Returned Value can be one of the following values:
1153 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1154 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1155 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1156 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1157 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1158 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1159 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1160 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1161 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1162 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1163 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1164 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1165 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1166 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1167 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1168 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1169 */
1170 __STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1171 {
1172 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, I2S_RXFIFO_TL));
1173 }
1174
1175 /**
1176 * @brief Set threshold of TXFIFO in a channel that triggers an TXFE event
1177 *
1178 * Register|BitsName
1179 * --------|--------
1180 * TXFIFO_TL | TL
1181 *
1182 * @param I2Sx I2S instance
1183 * @param channel The special channel: 0 ~ 3
1184 * @param threshold This parameter can be one of the following values:
1185 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1186 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1187 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1188 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1189 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1190 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1191 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1192 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1193 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1194 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1195 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1196 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1197 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1198 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1199 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1200 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1201 * @retval None
1202 */
1203 __STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1204 {
1205 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, threshold);
1206 }
1207
1208 /**
1209 * @brief Get threshold of TXFIFO in a channel that triggers an TXFE event
1210 *
1211 * Register|BitsName
1212 * --------|--------
1213 * TXFIFO_TL | TL
1214 *
1215 * @param I2Sx I2S instance
1216 * @param channel The special channel: 0 ~ 3
1217 * @retval Returned Value can be one of the following values:
1218 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1219 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1220 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1221 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1222 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1223 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1224 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1225 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1226 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1227 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1228 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1229 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1230 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1231 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1232 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1233 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1234 */
1235 __STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1236 {
1237 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, I2S_TXFIFO_TL));
1238 }
1239
1240 /**
1241 * @brief Clear RX FIFO data in a channel
1242 *
1243 * Register|BitsName
1244 * --------|--------
1245 * RXFIFO_FLUSH | FLUSH
1246 *
1247 * @param I2Sx I2S instance
1248 * @param channel The special channel: 0 ~ 3
1249 * @retval None
1250 */
1251 __STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1252 {
1253 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_FLUSH, I2S_RXFIFO_FLUSH);
1254 }
1255
1256 /**
1257 * @brief Clear TX FIFO data in a channel
1258 *
1259 * Register|BitsName
1260 * --------|--------
1261 * TXFIFO_FLUSH | FLUSH
1262 *
1263 * @param I2Sx I2S instance
1264 * @param channel The special channel: 0 ~ 3
1265 * @retval None
1266 */
1267 __STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1268 {
1269 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_FLUSH, I2S_TXFIFO_FLUSH);
1270 }
1271
1272 /** @} */
1273
1274 /** @defgroup I2S_LL_EF_DMA_Management DMA Management Functions
1275 * @{
1276 */
1277
1278 /**
1279 * @brief Reset RX block DMA
1280 * @note The RX DMA can be reset to the lowest channel via this register.
1281 *
1282 * Register|BitsName
1283 * --------|--------
1284 * RXDMA_RST | RST
1285 *
1286 * @param I2Sx I2S instance
1287 * @retval None
1288 */
1289 __STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
1290 {
1291 WRITE_REG(I2Sx->RXDMA_RST, I2S_RXDMA_RST);
1292 }
1293
1294 /**
1295 * @brief Reset TX block DMA
1296 * @note The TX DMA can be reset to the lowest channel via this register.
1297 *
1298 * Register|BitsName
1299 * --------|--------
1300 * TXDMA_RST | RST
1301 *
1302 * @param I2Sx I2S instance
1303 * @retval None
1304 */
1305 __STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
1306 {
1307 WRITE_REG(I2Sx->TXDMA_RST, I2S_TXDMA_RST);
1308 }
1309
1310
1311 /**
1312 * @brief Enable I2S DMA
1313 *
1314 * Register|BitsName
1315 * --------|--------
1316 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1317 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1318 *
1319 * @param I2Sx I2S instance
1320 * @retval None
1321 */
1322 __STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
1323 {
1324 if (I2S_M == I2Sx)
1325 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1326 else
1327 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1328 }
1329
1330 /**
1331 * @brief Disable I2S DMA
1332 *
1333 * Register|BitsName
1334 * --------|--------
1335 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1336 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1337 *
1338 * @param I2Sx I2S instance
1339 * @retval None
1340 */
1341 __STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
1342 {
1343 if (I2S_M == I2Sx)
1344 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1345 else
1346 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1347 }
1348
1349 /**
1350 * @brief Check if I2S DMA is enabled
1351 *
1352 * Register|BitsName
1353 * --------|--------
1354 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1355 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1356 *
1357 * @param I2Sx I2S instance
1358 * @retval State of bit (1 or 0).
1359 */
1360 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
1361 {
1362 if (I2S_M == I2Sx)
1363 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM) == MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1364 else
1365 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS) == MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1366 }
1367
1368
1369 /** @} */
1370
1371 /** @defgroup I2S_LL_EF_Component Component Paraments Functions
1372 * @{
1373 */
1374
1375 /**
1376 * @brief Get I2S component paramenters: rx resolution
1377 *
1378 * Register|BitsName
1379 * --------|--------
1380 * I2S_PARAM2 | RXSIZE_3
1381 * I2S_PARAM2 | RXSIZE_2
1382 * I2S_PARAM2 | RXSIZE_1
1383 * I2S_PARAM2 | RXSIZE_0
1384 *
1385 * @param I2Sx I2S instance
1386 * @param channel The special channel: 0 ~ 3
1387 * @retval Returned Value can be one of the following values:
1388 * @arg @ref LL_I2S_RESOLUTION_12BIT
1389 * @arg @ref LL_I2S_RESOLUTION_16BIT
1390 * @arg @ref LL_I2S_RESOLUTION_20BIT
1391 * @arg @ref LL_I2S_RESOLUTION_24BIT
1392 * @arg @ref LL_I2S_RESOLUTION_32BIT
1393 */
1394 __STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1395 {
1396 uint32_t pos[4] = {I2S_PARAM2_RXSIZE_0_Pos, I2S_PARAM2_RXSIZE_1_Pos, \
1397 I2S_PARAM2_RXSIZE_2_Pos, I2S_PARAM2_RXSIZE_3_Pos
1398 };
1399 uint32_t mask[4] = {I2S_PARAM2_RXSIZE_0, I2S_PARAM2_RXSIZE_1, I2S_PARAM2_RXSIZE_2, I2S_PARAM2_RXSIZE_3};
1400
1401 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM2, mask[channel]) >> pos[channel]);
1402 }
1403
1404 /**
1405 * @brief Get I2S component paramenters: tx resolution
1406 *
1407 * Register|BitsName
1408 * --------|--------
1409 * I2S_PARAM1 | TXSIZE_3
1410 * I2S_PARAM1 | TXSIZE_2
1411 * I2S_PARAM1 | TXSIZE_1
1412 * I2S_PARAM1 | TXSIZE_0
1413 *
1414 * @param I2Sx I2S instance
1415 * @param channel The special channel: 0 ~ 3
1416 * @retval Returned Value can be one of the following values:
1417 * @arg @ref LL_I2S_RESOLUTION_12BIT
1418 * @arg @ref LL_I2S_RESOLUTION_16BIT
1419 * @arg @ref LL_I2S_RESOLUTION_20BIT
1420 * @arg @ref LL_I2S_RESOLUTION_24BIT
1421 * @arg @ref LL_I2S_RESOLUTION_32BIT
1422 */
1423 __STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1424 {
1425 uint32_t pos[4] = {I2S_PARAM1_TXSIZE_0_Pos, I2S_PARAM1_TXSIZE_1_Pos, \
1426 I2S_PARAM1_TXSIZE_2_Pos, I2S_PARAM1_TXSIZE_3_Pos
1427 };
1428 uint32_t mask[4] = {I2S_PARAM1_TXSIZE_0, I2S_PARAM1_TXSIZE_1, I2S_PARAM1_TXSIZE_2, I2S_PARAM1_TXSIZE_3};
1429
1430 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, mask[channel]) >> pos[channel]);
1431 }
1432
1433 /**
1434 * @brief Get I2S component paramenters: the number of tx channels
1435 *
1436 * Register|BitsName
1437 * --------|--------
1438 * I2S_PARAM1 | TXCHN
1439 *
1440 * @param I2Sx I2S instance
1441 * @retval Returned Value can be one of the following values:
1442 * @arg @ref LL_I2S_CHANNEL_NUM_1
1443 * @arg @ref LL_I2S_CHANNEL_NUM_2
1444 * @arg @ref LL_I2S_CHANNEL_NUM_3
1445 * @arg @ref LL_I2S_CHANNEL_NUM_4
1446 */
1447 __STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
1448 {
1449 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXCHN) >> I2S_PARAM1_TXCHN_Pos);
1450 }
1451
1452 /**
1453 * @brief Get I2S component paramenters: the number of rx channels
1454 *
1455 * Register|BitsName
1456 * --------|--------
1457 * I2S_PARAM1 | RXCHN
1458 *
1459 * @param I2Sx I2S instance
1460 * @retval Returned Value can be one of the following values:
1461 * @arg @ref LL_I2S_CHANNEL_NUM_1
1462 * @arg @ref LL_I2S_CHANNEL_NUM_2
1463 * @arg @ref LL_I2S_CHANNEL_NUM_3
1464 * @arg @ref LL_I2S_CHANNEL_NUM_4
1465 */
1466 __STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
1467 {
1468 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXCHN) >> I2S_PARAM1_RXCHN_Pos);
1469 }
1470
1471 /**
1472 * @brief Get I2S component paramenters: whether the receiver block is enabled or not
1473 *
1474 * Register|BitsName
1475 * --------|--------
1476 * I2S_PARAM1 | RXBLOCK
1477 *
1478 * @param I2Sx I2S instance
1479 * @retval State of bit (1 or 0).
1480 */
1481 __STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
1482 {
1483 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXBLOCK) == I2S_PARAM1_RXBLOCK);
1484 }
1485
1486 /**
1487 * @brief Get I2S component paramenters: whether the transmitter block is enabled or not
1488 *
1489 * Register|BitsName
1490 * --------|--------
1491 * I2S_PARAM1 | TXBLOCK
1492 *
1493 * @param I2Sx I2S instance
1494 * @retval State of bit (1 or 0).
1495 */
1496 __STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
1497 {
1498 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXBLOCK) == I2S_PARAM1_TXBLOCK);
1499 }
1500
1501 /**
1502 * @brief Get I2S component paramenters: whether the master mode is enabled or not
1503 *
1504 * Register|BitsName
1505 * --------|--------
1506 * I2S_PARAM1 | MODE
1507 *
1508 * @param I2Sx I2S instance
1509 * @retval State of bit (1 or 0).
1510 */
1511 __STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
1512 {
1513 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_MODE) == I2S_PARAM1_MODE);
1514 }
1515
1516 /**
1517 * @brief Get I2S component paramenters: FIOF depth
1518 *
1519 * Register|BitsName
1520 * --------|--------
1521 * I2S_PARAM1 | FIFO_DEPTH
1522 *
1523 * @param I2Sx I2S instance
1524 * @retval Returned Value can be one of the following values:
1525 * @arg @ref LL_I2S_FIFO_DEPTH_2
1526 * @arg @ref LL_I2S_FIFO_DEPTH_4
1527 * @arg @ref LL_I2S_FIFO_DEPTH_8
1528 * @arg @ref LL_I2S_FIFO_DEPTH_16
1529 */
1530 __STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
1531 {
1532 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_FIFO_DEPTH) >> I2S_PARAM1_FIFO_DEPTH_Pos);
1533 }
1534
1535 /**
1536 * @brief Get I2S component paramenters: APB data width
1537 *
1538 * Register|BitsName
1539 * --------|--------
1540 * I2S_PARAM1 | APB_DATA_WIDTH
1541 *
1542 * @param I2Sx I2S instance
1543 * @retval Returned Value can be one of the following values:
1544 * @arg @ref LL_I2S_APB_WIDTH_8BIT
1545 * @arg @ref LL_I2S_APB_WIDTH_16BIT
1546 * @arg @ref LL_I2S_APB_WIDTH_32BIT
1547 */
1548 __STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
1549 {
1550 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_APB_DATA_WIDTH) >> I2S_PARAM1_APB_DATA_WIDTH_Pos);
1551 }
1552
1553 /**
1554 * @brief Get I2S component version
1555 *
1556 * Register|BitsName
1557 * --------|--------
1558 * I2S_VERSION | VERSION
1559 *
1560 * @param I2Sx I2S instance
1561 * @retval Returned Value is const.
1562 */
1563 __STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
1564 {
1565 return (uint32_t)(READ_REG(I2Sx->I2S_VERSION));
1566 }
1567
1568 /**
1569 * @brief Get I2S component type
1570 *
1571 * Register|BitsName
1572 * --------|--------
1573 * I2S_TYPE | TYPE
1574 *
1575 * @param I2Sx I2S instance
1576 * @retval Returned Value is const.
1577 */
1578 __STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
1579 {
1580 return (uint32_t)(READ_REG(I2Sx->I2S_TYPE));
1581 }
1582
1583 /** @} */
1584
1585 /** @defgroup I2S_LL_EF_Init I2S_M Initialization and de-initialization functions
1586 * @{
1587 */
1588
1589 /**
1590 * @brief De-initialize I2S registers (Registers restored to their default values).
1591 * @param I2Sx I2S instance
1592 * @retval An error_status_t enumeration value:
1593 * - SUCCESS: I2S registers are de-initialized
1594 * - ERROR: I2S registers are not de-initialized
1595 */
1596 error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx);
1597
1598 /**
1599 * @brief Initialize I2S_M registers according to the specified
1600 * parameters in p_i2s_init.
1601 * @param I2Sx I2S instance
1602 * @param p_i2s_init Pointer to a ll_i2s_init_t structure that contains the configuration
1603 * information for the specified I2S_M peripheral.
1604 * @retval An error_status_t enumeration value:
1605 * - SUCCESS: I2S registers are initialized according to p_i2s_init content
1606 * - ERROR: Problem occurred during I2S Registers initialization
1607 */
1608 error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init);
1609
1610 /**
1611 * @brief Set each field of a @ref ll_i2s_init_t type structure to default value.
1612 * @param p_i2s_init Pointer to a @ref ll_i2s_init_t structure
1613 * whose fields will be set to default values.
1614 * @retval None
1615 */
1616 void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init);
1617
1618 /** @} */
1619
1620 /** @} */
1621
1622 #endif /* I2S_M || I2S_S */
1623
1624 #ifdef __cplusplus
1625 }
1626 #endif
1627
1628 #endif /* __GR55xx_LL_I2S_H__ */
1629
1630 /** @} */
1631
1632 /** @} */
1633
1634 /** @} */
ll_i2s_enable_clock
__STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
Enable I2S clock.
Definition: gr55xx_ll_i2s.h:450
ll_i2s_receive_rdata
__STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from right RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:731
ll_i2s_enable
__STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
Enable I2S.
Definition: gr55xx_ll_i2s.h:315
ll_i2s_get_wss
__STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
Get word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:518
ll_i2s_get_rx_block
__STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the receiver block is enabled or not.
Definition: gr55xx_ll_i2s.h:1481
ll_i2s_is_enabled_clock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
Check if I2S clock is enabled.
Definition: gr55xx_ll_i2s.h:480
ll_i2s_disable_txblock
__STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
Disable I2S TX block.
Definition: gr55xx_ll_i2s.h:420
ll_i2s_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1203
ll_i2s_get_rx_channels
__STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of rx channels.
Definition: gr55xx_ll_i2s.h:1466
ll_i2s_struct_init
void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init)
Set each field of a ll_i2s_init_t type structure to default value.
ll_i2s_clr_rxfifo_all
__STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
Clear I2S RX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:574
ll_i2s_clr_txfifo_all
__STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
Clear I2S TX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:589
ll_i2s_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1170
ll_i2s_clear_it_txovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1105
ll_i2s_transmit_ldata
__STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to left TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:748
ll_i2s_set_rxsize
__STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set receive data width in a channel.
Definition: gr55xx_ll_i2s.h:885
ll_i2s_disable_tx
__STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Disable TX in a channel.
Definition: gr55xx_ll_i2s.h:845
ll_i2s_disable_dma
__STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
Disable I2S DMA.
Definition: gr55xx_ll_i2s.h:1341
_ll_i2s_init_t::tx_threshold
uint32_t tx_threshold
Specifies the I2S transmit FIFO threshold.
Definition: gr55xx_ll_i2s.h:93
ll_i2s_set_wss
__STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
Set word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:500
ll_i2s_set_txsize
__STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:931
_ll_i2s_init_t::clock_source
uint32_t clock_source
Specifies the source of the I2S clock.
Definition: gr55xx_ll_i2s.h:98
ll_i2s_enable_dma
__STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
Enable I2S DMA.
Definition: gr55xx_ll_i2s.h:1322
ll_i2s_get_tx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: tx resolution.
Definition: gr55xx_ll_i2s.h:1423
ll_i2s_rst_rxdma
__STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
Reset RX block DMA.
Definition: gr55xx_ll_i2s.h:1289
ll_i2s_clear_it_rxovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1089
_ll_i2s_init_t::rx_threshold
uint32_t rx_threshold
Specifies the I2S receive FIFO threshold.
Definition: gr55xx_ll_i2s.h:88
ll_i2s_set_clock_src
__STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
Set I2S clock source.
Definition: gr55xx_ll_i2s.h:677
ll_i2s_is_enabled_rx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
Check if RX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:813
ll_i2s_disable_it
__STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Disable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1049
_ll_i2s_init_t::rxdata_size
uint32_t rxdata_size
Specifies the I2S receive data size.
Definition: gr55xx_ll_i2s.h:78
_ll_i2s_init_t::txdata_size
uint32_t txdata_size
Specifies the I2S transmit data size.
Definition: gr55xx_ll_i2s.h:83
ll_i2s_is_enabled_clock_div
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
Check if I2S clock divider is enabled.
Definition: gr55xx_ll_i2s.h:660
ll_i2s_enable_rxblock
__STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
Enable I2S RX block.
Definition: gr55xx_ll_i2s.h:360
ll_i2s_get_rxsize
__STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
Get receive data width in a channel.
Definition: gr55xx_ll_i2s.h:907
ll_i2s_enable_txblock
__STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
Enable I2S TX block.
Definition: gr55xx_ll_i2s.h:405
_ll_i2s_init_t::audio_freq
uint32_t audio_freq
Specifies the frequency selected for the I2S communication.
Definition: gr55xx_ll_i2s.h:103
ll_i2s_get_clock_src
__STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
Get I2S clock source.
Definition: gr55xx_ll_i2s.h:693
ll_i2s_get_sclkg
__STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
Get the gating of sclk.
Definition: gr55xx_ll_i2s.h:559
ll_i2s_get_apb_width
__STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
Get I2S component paramenters: APB data width.
Definition: gr55xx_ll_i2s.h:1548
ll_i2s_get_master_mode
__STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the master mode is enabled or not.
Definition: gr55xx_ll_i2s.h:1511
ll_i2s_init
error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init)
Initialize I2S_M registers according to the specified parameters in p_i2s_init.
ll_i2s_transmit_rdata
__STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to right TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:765
ll_i2s_disable_rxblock
__STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
Disable I2S RX block.
Definition: gr55xx_ll_i2s.h:375
ll_i2s_is_enabled
__STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
Check if I2S is enabled.
Definition: gr55xx_ll_i2s.h:345
ll_i2s_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1235
ll_i2s_enable_it
__STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Enable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1025
ll_i2s_get_tx_channels
__STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of tx channels.
Definition: gr55xx_ll_i2s.h:1447
ll_i2s_rst_txdma
__STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
Reset TX block DMA.
Definition: gr55xx_ll_i2s.h:1305
ll_i2s_is_enabled_rxblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
Check if I2S RX block is enabled.
Definition: gr55xx_ll_i2s.h:390
ll_i2s_enable_clock_div
__STATIC_INLINE void ll_i2s_enable_clock_div(void)
Enable I2S clock divider.
Definition: gr55xx_ll_i2s.h:632
ll_i2s_set_sclkg
__STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
Set the gating of sclk.
Definition: gr55xx_ll_i2s.h:539
ll_i2s_get_type
__STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
Get I2S component type.
Definition: gr55xx_ll_i2s.h:1578
ll_i2s_get_it_flag
__STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
Get interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:976
ll_i2s_get_version
__STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
Get I2S component version.
Definition: gr55xx_ll_i2s.h:1563
ll_i2s_is_active_it_flag
__STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
Check interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1001
ll_i2s_init_t
struct _ll_i2s_init_t ll_i2s_init_t
LL I2S init structures definition.
ll_i2s_is_enabled_txblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
Check if I2S TX block is enabled.
Definition: gr55xx_ll_i2s.h:435
ll_i2s_disable_rx
__STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Disable RX in a channel.
Definition: gr55xx_ll_i2s.h:797
ll_i2s_enable_tx
__STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Enable TX in a channel.
Definition: gr55xx_ll_i2s.h:829
ll_i2s_is_enabled_dma
__STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
Check if I2S DMA is enabled.
Definition: gr55xx_ll_i2s.h:1360
ll_i2s_get_rx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: rx resolution.
Definition: gr55xx_ll_i2s.h:1394
ll_i2s_get_fifo_depth
__STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
Get I2S component paramenters: FIOF depth.
Definition: gr55xx_ll_i2s.h:1530
ll_i2s_set_clock_div
__STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
Set I2S clock divider.
Definition: gr55xx_ll_i2s.h:604
ll_i2s_clr_txfifo_channel
__STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1267
ll_i2s_receive_ldata
__STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from left RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:715
ll_i2s_disable_clock
__STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
Disable I2S clock.
Definition: gr55xx_ll_i2s.h:465
ll_i2s_is_enabled_it
__STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Check if interrupt in a channel is enabled.
Definition: gr55xx_ll_i2s.h:1073
ll_i2s_enable_rx
__STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Enable RX in a channel.
Definition: gr55xx_ll_i2s.h:781
ll_i2s_is_enabled_tx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
Check if TX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:861
ll_i2s_get_tx_block
__STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the transmitter block is enabled or not.
Definition: gr55xx_ll_i2s.h:1496
ll_i2s_get_clock_div
__STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
Get I2S clock divider.
Definition: gr55xx_ll_i2s.h:618
ll_i2s_get_txsize
__STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
Get transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:953
ll_i2s_clr_rxfifo_channel
__STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1251
_ll_i2s_init_t
LL I2S init structures definition.
Definition: gr55xx_ll_i2s.h:77
ll_i2s_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1138
ll_i2s_deinit
error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx)
De-initialize I2S registers (Registers restored to their default values).
ll_i2s_disable_clock_div
__STATIC_INLINE void ll_i2s_disable_clock_div(void)
Disable I2S clock divider.
Definition: gr55xx_ll_i2s.h:646
ll_i2s_disable
__STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
Disable I2S.
Definition: gr55xx_ll_i2s.h:330