gr55xx_ll_efuse.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_efuse.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of eFuse LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_EFUSE EFUSE
47  * @brief eFuse LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_EFUSE_H__
53 #define __GR55xx_LL_EFUSE_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 #if defined (EFUSE)
63 
64 /**
65  * @defgroup EFUSE_LL_MACRO Defines
66  * @{
67  */
68 
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup EFUSE_LL_Exported_Constants EFUSE Exported Constants
71  * @{
72  */
73 
74 /** @defgroup EFUSE_LL_EC_OPERATION EFUSE Operation Defines
75  * @brief Operation defines which can be used with LL_EFUSE_WriteReg function
76  * @{
77  */
78 #define LL_EFUSE_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM /**< Read fwkay and rootkey from eFuse, and write to keyram */
79 #define LL_EFUSE_READ_TRIM EFUSE_OPER_READ_TRIM /**< Read analog trim from eFuse */
80 #define LL_EFUSE_CRC_CHECK EFUSE_OPER_CRC_CHECK /**< Read the special eFuse addr, and calculate CRC value */
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK /**< Read the whole eFuse value, and check this value with 0 */
82 #define LL_EFUSE_TEST_READ EFUSE_OPER_RD_TEST_MODE /**< Read eFuse test mode from eFuse */
83 /** @} */
84 
85 /** @defgroup EFUSE_LL_EC_GET_FLAG Get Flags Defines
86  * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
87  * @{
88  */
89 #define LL_EFUSE_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY /**< Write keyram operation is in processing */
90 #define LL_EFUSE_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE /**< Read trim from eFuse has done */
91 #define LL_EFUSE_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE /**< eFuse CRC check done */
92 #define LL_EFUSE_CRC_CHECK_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS /**< CRC check success */
93 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE /**< eFuse initial value check done */
94 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS /**< eFuse initial value check success */
95 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE /**< eFuse one word write done */
96 #define LL_EFUSE_TEST_DONE EFUSE_STATUS_TEST_MODE_DONE /**< Read from eFuse has done in test mode */
97 /** @} */
98 
99 /** @defgroup EFUSE_LL_EC_GET_CTL_FLAG Get Power Controller Flags Defines
100  * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
101  * @{
102  */
103 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE /**< eFuse power enable done */
104 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE /**< eFuse power disable done */
105 /** @} */
106 
107 /** @} */
108 
109 /* Exported macro ------------------------------------------------------------*/
110 /** @defgroup EFUSE_LL_Exported_Macros EFUSE Exported Macros
111  * @{
112  */
113 
114 /** @defgroup EFUSE_LL_EM_WRITE_READ Common Write and read registers Macros
115  * @{
116  */
117 
118 /**
119  * @brief Write a value in eFuse register
120  * @param __instance__ eFuse instance
121  * @param __REG__ Register to be written
122  * @param __VALUE__ Value to be written in the register
123  * @retval None
124  */
125 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
126 
127 /**
128  * @brief Read a value in eFuse register
129  * @param __instance__ eFuse instance
130  * @param __REG__ Register to be read
131  * @retval Register value
132  */
133 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
134 
135 /** @} */
136 
137 /** @} */
138 
139 /** @} */
140 
141 /* Exported functions --------------------------------------------------------*/
142 /** @defgroup EFUSE_LL_DRIVER_FUNCTIONS Functions
143  * @{
144  */
145 
146 /** @defgroup EFUSE_LL_EF_Configuration Configuration functions
147  * @{
148  */
149 
150 /**
151  * @brief Set eFuse program time
152  *
153  * Register|BitsName
154  * --------|--------
155  * TPGM | TIME
156  *
157  * @param EFUSEx eFuse instance
158  * @param time This parameter can be one of the following values: 0 ~ 0xFFF
159  * @retval None
160  */
161 __STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
162 {
163  MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
164 }
165 
166 /**
167  * @brief Get eFuse program time
168  *
169  * Register|BitsName
170  * --------|--------
171  * TPGM | TIME
172  *
173  * @param EFUSEx eFuse instance
174  * @retval Returned value can be one of the following values: 0 ~ 0xFFF
175  */
176 __STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
177 {
178  return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
179 }
180 
181 /**
182  * @brief Enable read address through APB bus be a main address or backup address
183  *
184  * Register|BitsName
185  * --------|--------
186  * TPGM | MAIN_OR_BACKUP
187  *
188  * @param EFUSEx eFuse instance
189  * @retval None
190  */
191 __STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
192 {
193  SET_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
194 }
195 
196 /**
197  * @brief Disable read address through APB bus be a main address or backup address
198  *
199  * Register|BitsName
200  * --------|--------
201  * TPGM | MAIN_OR_BACKUP
202  *
203  * @param EFUSEx eFuse instance
204  * @retval None
205  */
206 __STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
207 {
208  CLEAR_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
209 }
210 
211 /**
212  * @brief Check if read address through APB bus be a main address or backup address is enabled
213  *
214  * Register|BitsName
215  * --------|--------
216  * TPGM | MAIN_OR_BACKUP
217  *
218  * @param EFUSEx eFuse instance
219  * @retval State of bit (1 or 0).
220  */
221 __STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
222 {
223  return (READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP) == (EFUSE_TPGM_MAIN_OR_BACKUP));
224 }
225 
226 /**
227  * @brief Set CRC check length
228  *
229  * Register|BitsName
230  * --------|--------
231  * TPGM | CRC_CHECK_LEN
232  *
233  * @param EFUSEx eFuse instance
234  * @param length This parameter can be one of the following values: 1 ~ 60
235  * @retval None
236  */
237 __STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
238 {
239  MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN, length << EFUSE_TPGM_CRC_CHECK_LEN_Pos);
240 }
241 
242 /**
243  * @brief Get CRC check length
244  *
245  * Register|BitsName
246  * --------|--------
247  * TPGM | CRC_CHECK_LEN
248  *
249  * @param EFUSEx eFuse instance
250  * @retval Returned value can be one of the following values: 1 ~ 60
251  */
252 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
253 {
254  return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN) >> EFUSE_TPGM_CRC_CHECK_LEN_Pos);
255 }
256 
257 /**
258  * @brief Set the interval number of clk cycles between two bit fuse
259  *
260  * Register|BitsName
261  * --------|--------
262  * TPGM | WRITE_INTERVAL
263  *
264  * @param EFUSEx eFuse instance
265  * @param interval This parameter can be one of the following values: 0 ~ 0xFF
266  * @retval None
267  */
268 __STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
269 {
270  MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
271 }
272 
273 /**
274  * @brief Get the interval number of clk cycles between two bit fuse
275  *
276  * Register|BitsName
277  * --------|--------
278  * TPGM | WRITE_INTERVAL
279  *
280  * @param EFUSEx eFuse instance
281  * @retval Returned value can be one of the following values: 0 ~ 0xFF
282  */
283 __STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
284 {
285  return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
286 }
287 
288 /**
289  * @brief Enable eFuse PGENB sigal
290  *
291  * Register|BitsName
292  * --------|--------
293  * PGENB | PGENB_SIG
294  *
295  * @param EFUSEx eFuse instance
296  * @retval None
297  */
298 __STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
299 {
300  SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
301 }
302 
303 /**
304  * @brief Disable eFuse PGENB sigal
305  *
306  * Register|BitsName
307  * --------|--------
308  * PGENB | PGENB_SIG
309  *
310  * @param EFUSEx eFuse instance
311  * @retval None
312  */
313 __STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
314 {
315  CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
316 }
317 
318 /**
319  * @brief Check if eFuse PGENB sigal is enabled
320  *
321  * Register|BitsName
322  * --------|--------
323  * PGENB | PGENB_SIG
324  *
325  * @param EFUSEx eFuse instance
326  * @retval State of bit (1 or 0).
327  */
328 __STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
329 {
330  return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
331 }
332 
333 /**
334  * @brief Get test mode
335  * @note This bit should be read only.
336  *
337  * Register|BitsName
338  * --------|--------
339  * TEST_MODE | TEST_MODE
340  *
341  * @param EFUSEx eFuse instance
342  * @retval Returned value can be one of the following values: 0xFFFF
343  */
344 __STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
345 {
346  return (uint32_t)(READ_BITS(EFUSEx->TEST_MODE, EFUSE_TEST_MODE));
347 }
348 
349 /**
350  * @brief Set eFuse operation mode
351  *
352  * Register|BitsName
353  * --------|--------
354  * OPERATION | WRITE_KEYRAM
355  * OPERATION | INIT_CHECK
356  * OPERATION | CRC_CHECK
357  * OPERATION | READ_TRIM
358  * OPERATION | RD_TEST_MODE
359  *
360  * @param EFUSEx eFuse instance
361  * @param mode This parameter can be one of the following values:
362  * @arg @ref LL_EFUSE_WRITE_KEYRAM
363  * @arg @ref LL_EFUSE_READ_TRIM
364  * @arg @ref LL_EFUSE_CRC_CHECK
365  * @arg @ref LL_EFUSE_INIT_CHECK
366  * @arg @ref LL_EFUSE_TEST_READ
367  * @retval None
368  */
369 __STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
370 {
371  WRITE_REG(EFUSEx->OPERATION, mode);
372 }
373 
374 /**
375  * @brief Check active flag
376  *
377  * Register|BitsName
378  * --------|--------
379  * STAT | WRITE_KEYRAM_BUSY
380  * STAT | READ_TRIM_DONE
381  * STAT | TRIM_CRC_SUCCESS
382  * STAT | INIT_DONE
383  * STAT | INIT_SUCCESS
384  * STAT | CRC_CHECK_DONE
385  * STAT | WRITE_DONE
386  * STAT | TEST_MODE_DONE
387  *
388  * @param EFUSEx eFuse instance
389  * @param flag This parameter can be one of the following values:
390  * @arg @ref LL_EFUSE_WRITE_KEYRAM_BUSY
391  * @arg @ref LL_EFUSE_READ_TRIM_DONE
392  * @arg @ref LL_EFUSE_CRC_CHECK_DONE
393  * @arg @ref LL_EFUSE_CRC_CHECK_SUCCESS
394  * @arg @ref LL_EFUSE_INIT_CHECK_DONE
395  * @arg @ref LL_EFUSE_INIT_CHECK_SUCCESS
396  * @arg @ref LL_EFUSE_WRITE_DONE
397  * @arg @ref LL_EFUSE_TEST_DONE
398  * @retval State of bit (1 or 0).
399  */
400 __STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
401 {
402  return (READ_BITS(EFUSEx->STAT, flag) == (flag));
403 }
404 
405 /**
406  * @brief Set key mask
407  *
408  * Register|BitsName
409  * --------|--------
410  * KEY_MASK | KEY_MASK
411  *
412  * @param EFUSEx eFuse instance
413  * @param mask Key mask
414  * @retval None
415  */
416 __STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
417 {
418  WRITE_REG(EFUSEx->KEY_MASK, mask);
419 }
420 
421 /**
422  * @brief Get key mask
423  *
424  * Register|BitsName
425  * --------|--------
426  * KEY_MASK | KEY_MASK
427  *
428  * @param EFUSEx eFuse instance
429  * @retval None
430  */
431 __STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
432 {
433  return (uint32_t)(READ_REG(EFUSEx->KEY_MASK));
434 }
435 
436 /**
437  * @brief Set CRC check start address
438  * @note The address must be a main info address.
439  *
440  * Register|BitsName
441  * --------|--------
442  * CRC_ADDR | START_CHECK_ADDR
443  *
444  * @param EFUSEx eFuse instance
445  * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
446  * @retval None
447  */
448 __STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
449 {
450  WRITE_REG(EFUSEx->CRC_ADDR, address);
451 }
452 
453 /**
454  * @brief Get CRC check start address
455  *
456  * Register|BitsName
457  * --------|--------
458  * CRC_ADDR | START_CHECK_ADDR
459  *
460  * @param EFUSEx eFuse instance
461  * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
462  */
463 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
464 {
465  return (uint32_t)(READ_REG(EFUSEx->CRC_ADDR));
466 }
467 
468 /**
469  * @brief Get CRC check results
470  *
471  * Register|BitsName
472  * --------|--------
473  * CRC_OUTPUT | OUTPUT_VALUE
474  *
475  * @param EFUSEx eFuse instance
476  * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
477  */
478 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
479 {
480  return (uint32_t)(READ_REG(EFUSEx->CRC_OUTPUT));
481 }
482 
483 /**
484  * @brief Set read trim start address
485  * @note The address must be a main info address.
486  *
487  * Register|BitsName
488  * --------|--------
489  * TRIM_ADDR | START_ADDR
490  *
491  * @param EFUSEx eFuse instance
492  * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
493  * @retval None
494  */
495 __STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
496 {
497  WRITE_REG(EFUSEx->TRIM_ADDR, address);
498 }
499 
500 /**
501  * @brief Get read trim start address
502  *
503  * Register|BitsName
504  * --------|--------
505  * TRIM_ADDR | START_ADDR
506  *
507  * @param EFUSEx eFuse instance
508  * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
509  */
510 __STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
511 {
512  return (uint32_t)(READ_REG(EFUSEx->TRIM_ADDR));
513 }
514 
515 /**
516  * @brief Set read trim length
517  *
518  * Register|BitsName
519  * --------|--------
520  * TRIM_LEN | LENGTH
521  *
522  * @param EFUSEx eFuse instance
523  * @param length This parameter can be one of the following values: 1 ~ 14
524  * @retval None
525  */
526 __STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
527 {
528  WRITE_REG(EFUSEx->TRIM_LEN, length & EFUSE_TRIM_LENGTH);
529 }
530 
531 /**
532  * @brief Get read trim length
533  *
534  * Register|BitsName
535  * --------|--------
536  * TRIM_LEN | LENGTH
537  *
538  * @param EFUSEx eFuse instance
539  * @retval Returned value can be one of the following values: 1 ~ 14
540  */
541 __STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
542 {
543  return (uint32_t)(READ_REG(EFUSEx->TRIM_LEN) & EFUSE_TRIM_LENGTH);
544 }
545 
546 /**
547  * @brief Get trim value
548  *
549  * Register|BitsName
550  * --------|--------
551  * TRIM[n] | TRIM
552  *
553  * @param EFUSEx eFuse instance
554  * @param indx index of trim value registers: 0 ~ 13
555  * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
556  */
557 __STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
558 {
559  return (uint32_t)(READ_REG(EFUSEx->TRIM[indx]));
560 }
561 
562 /**
563  * @brief eFuse v1.1 power on.
564  *
565  * Register|BitsName
566  * --------|--------
567  * TPGM | CRC_CHECK_LEN
568  *
569  * @retval None
570  */
571 __STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
572 {
573  SET_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
574 }
575 
576 /**
577  * @brief eFuse v1.1 power off.
578  *
579  * Register|BitsName
580  * --------|--------
581  * TPGM | CRC_CHECK_LEN
582  *
583  * @retval None
584  */
585 __STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
586 {
587  CLEAR_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
588 }
589 
590 /**
591  * @brief Set Efulse power controller timing pararmeter.
592  *
593  * Register |BitsName
594  * ----------|--------
595  * PWR_DELTA| PWR_DELTA_0
596  * PWR_DELTA| PWR_DELTA_1
597  * PWR_DELTA| PWR_DELTA_2
598  *
599  * @retval None
600  */
601 __STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
602 {
603  WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[0], vddq_0 + (vddq_1 << 16));
604  WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[1], vddq_2);
605 }
606 
607 /**
608  * @brief Power sequencer begin.
609  *
610  * Register |BitsName
611  * -----------|--------
612  * PWR_CTRL0 | CTRL_ENABLE
613  * PWR_CTRL0 | SEQR_BEGIN
614  *
615  * @retval None
616  */
617 __STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
618 {
619  WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_BGN | MCU_SUB_EFUSE_PWR_CTL0_EN);
620 }
621 
622 /**
623  * @brief Power sequencer begin.
624  *
625  * Register |BitsName
626  * -----------|--------
627  * PWR_CTRL0 | CTRL_ENABLE
628  * PWR_CTRL0 | SEQR_STOP
629  *
630  * @retval None
631  */
632 __STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
633 {
634  WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_STP | MCU_SUB_EFUSE_PWR_CTL0_EN);
635 }
636 
637 /**
638  * @brief Power sequencer begin.
639  *
640  * Register |BitsName
641  * --------- -|--------
642  * PWR_CTRL0 | CTRL_ENABLE
643  * PWR_CTRL0 | SEQR_BEGIN
644  * PWR_CTRL0 | SEQR_STOP
645  *
646  * @retval None
647  */
648 __STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
649 {
650  WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], 0);
651 }
652 
653 /**
654  * @brief Check power controller active flag
655  *
656  * Register|BitsName
657  * --------|--------
658  * PWR_CTRL1 | EN_DONE
659  * PWR_CTRL1 | DIS_DONE
660  *
661  * @param EFUSEx eFuse instance
662  * @param flag This parameter can be one of the following values:
663  * @arg @ref LL_EFUSE_PWR_CTL_EN_DONE
664  * @arg @ref LL_EFUSE_PWR_CTL_DIS_DONE
665  * @retval State of bit (1 or 0).
666  */
667 __STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
668 {
669  return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL[1], flag) == (flag));
670 }
671 
672 
673 
674 /** @} */
675 
676 /** @} */
677 
678 #endif /* EFUSE */
679 
680 #ifdef __cplusplus
681 }
682 #endif
683 
684 #endif /* __GR55xx_LL_EFUSE_H__ */
685 
686 /** @} */
687 
688 /** @} */
689 
690 /** @} */
ll_efuse_disable_controller_power
__STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:648
ll_efuse_get_trim_value
__STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
Get trim value.
Definition: gr55xx_ll_efuse.h:557
ll_efuse_get_crc_check_addr
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
Get CRC check start address.
Definition: gr55xx_ll_efuse.h:463
ll_efuse_get_trim_addr
__STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
Get read trim start address.
Definition: gr55xx_ll_efuse.h:510
ll_efuse_enable_controller_power_begin
__STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:617
ll_efuse_set_crc_check_addr
__STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set CRC check start address.
Definition: gr55xx_ll_efuse.h:448
ll_efuse_get_test_mode
__STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
Get test mode.
Definition: gr55xx_ll_efuse.h:344
ll_efuse_set_trim_length
__STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
Set read trim length.
Definition: gr55xx_ll_efuse.h:526
ll_efuse_disable_main_backup
__STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
Disable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:206
ll_efuse_get_trim_length
__STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
Get read trim length.
Definition: gr55xx_ll_efuse.h:541
ll_efuse_set_key_mask
__STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
Set key mask.
Definition: gr55xx_ll_efuse.h:416
ll_efuse_disable_pgenb
__STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
Disable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:313
ll_efuse_is_enabled_main_backup
__STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
Check if read address through APB bus be a main address or backup address is enabled.
Definition: gr55xx_ll_efuse.h:221
ll_efuse_set_crc_check_len
__STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
Set CRC check length.
Definition: gr55xx_ll_efuse.h:237
ll_efuse_enable_power
__STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power on.
Definition: gr55xx_ll_efuse.h:571
ll_efuse_enable_controller_power_stop
__STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:632
ll_efuse_get_key_mask
__STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
Get key mask.
Definition: gr55xx_ll_efuse.h:431
ll_efuse_is_enabled_pgenb
__STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
Check if eFuse PGENB sigal is enabled.
Definition: gr55xx_ll_efuse.h:328
ll_efuse_get_interval
__STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
Get the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:283
ll_efuse_get_crc_check_result
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
Get CRC check results.
Definition: gr55xx_ll_efuse.h:478
ll_efuse_set_tpro
__STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
Set eFuse program time.
Definition: gr55xx_ll_efuse.h:161
ll_efuse_set_trim_addr
__STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set read trim start address.
Definition: gr55xx_ll_efuse.h:495
ll_efuse_is_active_flag
__STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_efuse.h:400
ll_efuse_set_operation
__STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
Set eFuse operation mode.
Definition: gr55xx_ll_efuse.h:369
ll_efuse_is_controller_power_flag
__STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check power controller active flag.
Definition: gr55xx_ll_efuse.h:667
ll_efuse_enable_main_backup
__STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
Enable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:191
ll_efuse_disable_power
__STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power off.
Definition: gr55xx_ll_efuse.h:585
ll_efuse_set_controller_power_timing
__STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
Set Efulse power controller timing pararmeter.
Definition: gr55xx_ll_efuse.h:601
ll_efuse_set_interval
__STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
Set the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:268
ll_efuse_enable_pgenb
__STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
Enable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:298
ll_efuse_get_crc_check_len
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
Get CRC check length.
Definition: gr55xx_ll_efuse.h:252
ll_efuse_get_tpro
__STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
Get eFuse program time.
Definition: gr55xx_ll_efuse.h:176