gr55xx_ll_pwr.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
73 * @{
74 */
75
76 /** @defgroup PWR_LL_PC_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
77 * @{
78 */
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos) /**< External wakeup level type */
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos) /**< External wakeup level invert */
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos) /**< External wakeup source enable */
82 /** @} */
83
84 /** @} */
85
86 /* Private macros ------------------------------------------------------------*/
87 /** @defgroup PWR_LL_Private_Macro PWR Private Macros
88 * @{
89 */
90
91 /** @defgroup PWR_LL_PM_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
92 * @{
93 */
94
95 /**
96 * @brief PWR_LL_PM_GET_MEM_PWR_MSK PWR Get Memory Power Value Mask
97 */
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100
101 /** @} */
102
103 /** @} */
104
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
108 * @{
109 */
110
111 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
112 * @{
113 */
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP /**< External wakeup: AON_GPIO */
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER /**< AON Timer wakeup */
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE /**< BLE wakeup */
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR /**< Calendar wakeup */
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE /**< PMU Bod falling edge wakeup */
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP /**< Msio comparator wakeup */
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL /**< All wakeup sources mask */
121 /** @} */
122
123
124 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
125 * @note Only available on GR5515_C and later version
126 * @{
127 */
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN /**< BLE Timer wakeup event */
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER /**< AON Timer wakeup event */
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP /**< External wakeup event: AON_GPIO */
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE /**< PMU Bod wakeup event */
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP /**< Msio comparator wakeup event */
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT /**< AON WDT wakeup event */
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM /**< Calendar wakeup event */
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136 AON_SLP_EVENT_TIMER | \
137 AON_SLP_EVENT_EXTWKUP | \
138 AON_SLP_EVENT_PMU_BOD_FEDGE | \
139 AON_SLP_EVENT_PMU_MSIO_COMP | \
140 AON_SLP_EVENT_WDT_REBOOT | \
141 AON_SLP_EVENT_CALENDAR_TIMER_ALARM) /**< All event mask */
142 /** @} */
143
144 /** @defgroup PWR_LL_EC_EXTWAKEUP_PIN External Wakeup Pins
145 * @{
146 */
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U) /**< WKUP pin 0 : AON_GPIO_PIN0 */
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U) /**< WKUP pin 1 : AON_GPIO_PIN1 */
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U) /**< WKUP pin 2 : AON_GPIO_PIN2 */
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U) /**< WKUP pin 3 : AON_GPIO_PIN3 */
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U) /**< WKUP pin 4 : AON_GPIO_PIN4 */
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U) /**< WKUP pin 5 : AON_GPIO_PIN5 */
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U) /**< WKUP pin 6 : AON_GPIO_PIN6 */
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U) /**< WKUP pin 7 : AON_GPIO_PIN7 */
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU) /**< WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7 */
156 /** @} */
157
158 /** @defgroup PWR_LL_EC_EXTWAKEUP_TYPE External Wakeup Type
159 * @{
160 */
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Low level wakeup */
162 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< High level wakeup */
163 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U) /**< Rising edge wakeup */
164 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Falling edge wakeup */
165 /** @} */
166
167 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
168 * @{
169 */
170 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK /**< Reserved command 0 */
171 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON /**< Reserved command 1 */
172 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD /**< Load sleep timer command */
173 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP /**< Enter Deep Sleep Mode command */
174 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF /**< Reserved command 2 */
175 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK /**< Select external clock (xo_32KHz) command */
176 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK /**< Select RING OSC clock command */
177 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK /**< Select RTC clock command */
178 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK /**< Select RING OSC clock command */
179 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG /**< Load memory sleep settings command */
180 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG /**< Load memory wakeup settings command */
181 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI /**< Force dpad_le high */
182 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO /**< Force dpad_le low */
183 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 /**< Enable sleep timer mode 0 command */
184 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 /**< Enable sleep timer mode 1 command */
185 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 /**< Enable sleep timer mode 2 command */
186 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 /**< Enable sleep timer mode 3 command */
187 /** @} */
188
189
190 /** @} */
191
192 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
193 * @{
194 */
195 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
196 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
197 /** @} */
198
199 /** @defgroup PWR_LL_EC_TIMER_READ_SEL Timer Read Select
200 * @note Only available on GR5515_C and later version
201 * @{
202 */
203 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER /**< Calendar timer */
204 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT /**< AON watchdog timer */
205 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER /**< Sleep timer */
206 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM /**< Calendar alarm */
207 /** @} */
208
209 /** @} */
210
211
212 /* Exported macro ------------------------------------------------------------*/
213 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
214 * @{
215 */
216
217 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
218 * @{
219 */
220
221 /**
222 * @brief Write a value in PWR register
223 * @param __REG__ Register to be written
224 * @param __VALUE__ Value to be written in the register
225 * @retval None
226 */
227 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
228
229 /**
230 * @brief Read a value in PWR register
231 * @param __REG__ Register to be read
232 * @retval Register value
233 */
234 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
235 /** @} */
236
237 /* Exported functions --------------------------------------------------------*/
238 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
239 * @{
240 */
241
242 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
243 * @{
244 */
245
246 /**
247 * @brief Set the DeepSleep WakeUp Condition
248 *
249 * \rst
250 * +----------------------+-----------------------------------+
251 * | Register | BitsName |
252 * +======================+===================================+
253 * | EXT_WKUP_CTL | WAKE_UP_SEL |
254 * +----------------------+-----------------------------------+
255 * \endrst
256 *
257 * @param condition This parameter can be one of the following values:
258 * @arg @ref LL_PWR_WKUP_COND_EXT
259 * @arg @ref LL_PWR_WKUP_COND_TIMER
260 * @arg @ref LL_PWR_WKUP_COND_BLE
261 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
262 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
263 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
264 * @arg @ref LL_PWR_WKUP_COND_ALL
265 * @retval None
266 */
267 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
268 {
269 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
270 }
271
272 /**
273 * @brief Get the Selected DeepSleep WakeUp Condition
274 *
275 * \rst
276 * +----------------------+-----------------------------------+
277 * | Register | BitsName |
278 * +======================+===================================+
279 * | EXT_WKUP_CTL | WAKE_UP_SEL |
280 * +----------------------+-----------------------------------+
281 * \endrst
282 *
283 * @retval Returned value can be one of the following values:
284 * @arg @ref LL_PWR_WKUP_COND_EXT
285 * @arg @ref LL_PWR_WKUP_COND_TIMER
286 * @arg @ref LL_PWR_WKUP_COND_BLE
287 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
288 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
289 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
290 * @arg @ref LL_PWR_WKUP_COND_ALL
291 */
292 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
293 {
294 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
295 }
296
297 /**
298 * @brief Get the Event that triggered the DeepSleep WakeUp.
299 * @note Only available on GR5515_C and later version
300 *
301 * \rst
302 * +----------------------+-----------------------------------+
303 * | Register | BitsName |
304 * +======================+===================================+
305 * | SLP_EVENT | SMCOSCEN_EVENT |
306 * +----------------------+-----------------------------------+
307 * \endrst
308 * SLP_EVENT | TIMER_EVENT
309 * SLP_EVENT | EXT_WKUP_EVENT
310 * SLP_EVENT | WATCHDOG_EVENT
311 *
312 * @retval Returned value can be combination of the following values:
313 * @arg @ref LL_PWR_WKUP_EVENT_BLE
314 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
315 * @arg @ref LL_PWR_WKUP_EVENT_EXT
316 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
317 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
318 * @arg @ref LL_PWR_WKUP_EVENT_WDT
319 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
320 */
321 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
322 {
323 return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
324 }
325
326 /**
327 * @brief Enable the External WakeUp PINx functionality
328 *
329 * \rst
330 * +----------------------+-----------------------------------+
331 * | Register | BitsName |
332 * +======================+===================================+
333 * | EXT_WKUP_CTL | MASK |
334 * +----------------------+-----------------------------------+
335 * \endrst
336 *
337 * @param wakeup_pin This parameter can be a combination of the following values:
338 * @arg @ref LL_PWR_EXTWKUP_PIN0
339 * @arg @ref LL_PWR_EXTWKUP_PIN1
340 * @arg @ref LL_PWR_EXTWKUP_PIN2
341 * @arg @ref LL_PWR_EXTWKUP_PIN3
342 * @arg @ref LL_PWR_EXTWKUP_PIN4
343 * @arg @ref LL_PWR_EXTWKUP_PIN5
344 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
345 * @retval None
346 */
347 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
348 {
349 GLOBAL_EXCEPTION_DISABLE();
350 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
351 GLOBAL_EXCEPTION_ENABLE();
352 }
353
354 /**
355 * @brief Disable the External WakeUp PINx functionality
356 *
357 * \rst
358 * +----------------------+-----------------------------------+
359 * | Register | BitsName |
360 * +======================+===================================+
361 * | EXT_WKUP_CTL | MASK |
362 * +----------------------+-----------------------------------+
363 * \endrst
364 *
365 * @param wakeup_pin This parameter can be a combination of the following values:
366 * @arg @ref LL_PWR_EXTWKUP_PIN0
367 * @arg @ref LL_PWR_EXTWKUP_PIN1
368 * @arg @ref LL_PWR_EXTWKUP_PIN2
369 * @arg @ref LL_PWR_EXTWKUP_PIN3
370 * @arg @ref LL_PWR_EXTWKUP_PIN4
371 * @arg @ref LL_PWR_EXTWKUP_PIN5
372 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
373 * @retval None
374 */
375 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
376 {
377 GLOBAL_EXCEPTION_DISABLE();
378 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
379 GLOBAL_EXCEPTION_ENABLE();
380 }
381
382 /**
383 * @brief Check if the External WakeUp PINx functionality is enabled
384 *
385 * \rst
386 * +----------------------+-----------------------------------+
387 * | Register | BitsName |
388 * +======================+===================================+
389 * | EXT_WKUP_CTL | MASK |
390 * +----------------------+-----------------------------------+
391 * \endrst
392 *
393 * @param wakeup_pin This parameter can be a combination of the following values:
394 * @arg @ref LL_PWR_EXTWKUP_PIN0
395 * @arg @ref LL_PWR_EXTWKUP_PIN1
396 * @arg @ref LL_PWR_EXTWKUP_PIN2
397 * @arg @ref LL_PWR_EXTWKUP_PIN3
398 * @arg @ref LL_PWR_EXTWKUP_PIN4
399 * @arg @ref LL_PWR_EXTWKUP_PIN5
400 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
401 * @retval State of bit (1 or 0).
402 */
403 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
404 {
405 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
406 }
407
408 /**
409 * @brief Set the WakeUp Type of External WakeUp PINx.
410 *
411 * \rst
412 * +----------------------+-----------------------------------+
413 * | Register | BitsName |
414 * +======================+===================================+
415 * | EXT_WKUP_CTL | INVERT |
416 * +----------------------+-----------------------------------+
417 * \endrst
418 * EXT_WKUP_CTL | TYPE
419 *
420 * @param wakeup_pin This parameter can be a combination of the following values:
421 * @arg @ref LL_PWR_EXTWKUP_PIN0
422 * @arg @ref LL_PWR_EXTWKUP_PIN1
423 * @arg @ref LL_PWR_EXTWKUP_PIN2
424 * @arg @ref LL_PWR_EXTWKUP_PIN3
425 * @arg @ref LL_PWR_EXTWKUP_PIN4
426 * @arg @ref LL_PWR_EXTWKUP_PIN5
427 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
428 * @param wakeup_type This parameter can be one of the following values:
429 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
430 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
431 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
432 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
433 * @retval None
434 */
435 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
436 {
437 uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
438 uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
439 GLOBAL_EXCEPTION_DISABLE();
440 MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
441 GLOBAL_EXCEPTION_ENABLE();
442 }
443
444 /**
445 * @brief Get the WakeUp Type of External WakeUp PINx.
446 * @note Warning: only one pin can be passed as parameter.
447 *
448 * \rst
449 * +----------------------+-----------------------------------+
450 * | Register | BitsName |
451 * +======================+===================================+
452 * | EXT_WKUP_CTL | INVERT |
453 * +----------------------+-----------------------------------+
454 * \endrst
455 * EXT_WKUP_CTL | TYPE
456 *
457 * @param wakeup_pin This parameter can be one of the following values:
458 * @arg @ref LL_PWR_EXTWKUP_PIN0
459 * @arg @ref LL_PWR_EXTWKUP_PIN1
460 * @arg @ref LL_PWR_EXTWKUP_PIN2
461 * @arg @ref LL_PWR_EXTWKUP_PIN3
462 * @arg @ref LL_PWR_EXTWKUP_PIN4
463 * @arg @ref LL_PWR_EXTWKUP_PIN5
464 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
465 * @retval Returned value can be one of the following values:
466 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
467 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
468 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
469 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
470 */
471 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
472 {
473 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
474 }
475
476 /**
477 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
478 * @note After the value was set, use @arg @ref LL_PWR_CMD_32_TIMER_LD command to
479 * load the configuration into Power State Controller.
480 *
481 * \rst
482 * +----------------------+-----------------------------------+
483 * | Register | BitsName |
484 * +======================+===================================+
485 * | TIMER_VALUE | PWR_CTL_TIMER_32B |
486 * +----------------------+-----------------------------------+
487 * \endrst
488 *
489 * @param value 32 bits count value loaded into the t32bit_timer
490 * @retval None
491 */
492 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
493 {
494 WRITE_REG(AON->TIMER_VALUE, value);
495 }
496
497 /**
498 * @brief Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
499 *
500 * \rst
501 * +----------------------+-----------------------------------+
502 * | Register | BitsName |
503 * +======================+===================================+
504 * | TIMER_VALUE | PWR_CTL_TIMER_32B |
505 * +----------------------+-----------------------------------+
506 * \endrst
507 *
508 * @retval 32 bit AON Timer Count Value
509 */
510 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
511 {
512 return READ_REG(AON->TIMER_VALUE);
513 }
514
515 /**
516 * @brief Enable the SMC WakeUp Request.
517 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
518 *
519 * \rst
520 * +----------------------+-----------------------------------+
521 * | Register | BitsName |
522 * +======================+===================================+
523 * | PWR_RET01 | SMC_WAKEUP_REQ |
524 * +----------------------+-----------------------------------+
525 * \endrst
526 *
527 * @retval None
528 */
529 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
530 {
531 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
532 }
533
534 /**
535 * @brief Disable the SMC WakeUp Request.
536 * @note This function is used to clear SMC WakeUp Request.
537 *
538 * \rst
539 * +----------------------+-----------------------------------+
540 * | Register | BitsName |
541 * +======================+===================================+
542 * | PWR_RET01 | SMC_WAKEUP_REQ |
543 * +----------------------+-----------------------------------+
544 * \endrst
545 *
546 * @retval None
547 */
548 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
549 {
550 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
551 }
552
553 /**
554 * @brief Check if the SMC WakeUp Request was enabled or disabled.
555 *
556 * \rst
557 * +----------------------+-----------------------------------+
558 * | Register | BitsName |
559 * +======================+===================================+
560 * | PWR_RET01 | SMC_WAKEUP_REQ |
561 * +----------------------+-----------------------------------+
562 * \endrst
563 *
564 * @retval State of bit (1 or 0).
565 */
566 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
567 {
568 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
569 }
570
571 /**
572 * @brief Set the DPAD LE value during sleep and after wake up.
573 *
574 * \rst
575 * +----------------------+-----------------------------------+
576 * | Register | BitsName |
577 * +======================+===================================+
578 * | MEM_N_SLP_CTL | DPAD_LE_SLP_VAL |
579 * +----------------------+-----------------------------------+
580 * | MEM_N_SLP_CTL | DPAD_LE_WKUP_VAL |
581 * +----------------------+-----------------------------------+
582 * \endrst
583 *
584 *
585 * @param sleep This parameter can be one of the following values:
586 * @arg @ref LL_PWR_DPAD_LE_OFF
587 * @arg @ref LL_PWR_DPAD_LE_ON
588 * @param wakeup This parameter can be one of the following values:
589 * @arg @ref LL_PWR_DPAD_LE_OFF
590 * @arg @ref LL_PWR_DPAD_LE_ON
591 * @retval None
592 */
593 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
594 {
595 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
596 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
597 }
598
599 /**
600 * @brief Request to excute the Power State Controller Command.
601 * @note The PSC command can only be excuted when Power State Controller is not in busy state.
602 * Use @ref ll_pwr_is_active_flag_psc_cmd_busy() to check the busy status, and make sure
603 * the last command has been finished.
604 *
605 * \rst
606 * +----------------------+-----------------------------------+
607 * | Register | BitsName |
608 * +======================+===================================+
609 * | PSC_CMD_OPC | OPCODE |
610 * +----------------------+-----------------------------------+
611 * | PSC_CMD | MCU_PWR_REQ |
612 * +----------------------+-----------------------------------+
613 * \endrst
614
615 *
616 * @param command This parameter can be one of the following values:
617 * @arg @ref LL_PWR_CMD_LOOPBACK
618 * @arg @ref LL_PWR_CMD_EF_DIR_ON
619 * @arg @ref LL_PWR_CMD_32_TIMER_LD
620 * @arg @ref LL_PWR_CMD_DEEP_SLEEP
621 * @arg @ref LL_PWR_CMD_EF_DIR_OFF
622 * @arg @ref LL_PWR_CMD_EXT_CLK
623 * @arg @ref LL_PWR_CMD_RNG_CLK
624 * @arg @ref LL_PWR_CMD_RTC_CLK
625 * @arg @ref LL_PWR_CMD_LD_MEM_SLP_CFG
626 * @arg @ref LL_PWR_CMD_LD_MEM_WKUP_CFG
627 * @arg @ref LL_PWR_CMD_DPAD_LE_HI (*)
628 * @arg @ref LL_PWR_CMD_DPAD_LE_LO (*)
629 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_NORMAL (*)
630 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_SINGLE (*)
631 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_RELOAD (*)
632 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_DISABLE (*)
633 *
634 * (*) Not available in A0 and B0
635 *
636 * @retval None
637 */
638 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
639 {
640 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
641 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
642 }
643
644 /** @} */
645
646 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
647 * @{
648 */
649
650 /**
651 * @brief Enable the Communication Timer Reset.
652 * @note Comm timer can be reset when all ble connection were disconnected and
653 * MCU was ready to enter into deepsleep mode.
654 *
655 * \rst
656 * +----------------------+-----------------------------------+
657 * | Register | BitsName |
658 * +======================+===================================+
659 * | PWR_RET01 | COMM_TIMER_RST_N |
660 * +----------------------+-----------------------------------+
661 * \endrst
662 *
663 * @retval None
664 */
665 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
666 {
667 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
668 }
669
670 /**
671 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
672 * @note After powered up, Comm Timer need to enter into running mode.
673 *
674 * \rst
675 * +----------------------+-----------------------------------+
676 * | Register | BitsName |
677 * +======================+===================================+
678 * | PWR_RET01 | COMM_TIMER_RST_N |
679 * +----------------------+-----------------------------------+
680 * \endrst
681 *
682 * @retval None
683 */
684 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
685 {
686 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
687 }
688
689 /**
690 * @brief Check if the Communication Timer Reset was enabled or disabled.
691 *
692 * \rst
693 * +----------------------+-----------------------------------+
694 * | Register | BitsName |
695 * +======================+===================================+
696 * | PWR_RET01 | COMM_TIMER_RST_N |
697 * +----------------------+-----------------------------------+
698 * \endrst
699 *
700 * @retval State of bit (1 or 0).
701 */
702 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
703 {
704 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
705 }
706
707 /**
708 * @brief Enable the Communication Core Reset.
709 * @note Comm Core can be reset when all ble connection were disconnected and
710 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
711 * is 0, the ble is held in reset.
712 *
713 * \rst
714 * +----------------------+-----------------------------------+
715 * | Register | BitsName |
716 * +======================+===================================+
717 * | PWR_RET01 | COMM_CORE_RST_N |
718 * +----------------------+-----------------------------------+
719 * \endrst
720 *
721 * @retval None
722 */
723 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
724 {
725 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
726 }
727
728 /**
729 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
730 * @note After powered up, Comm Core need to enter into running mode.
731 *
732 * \rst
733 * +----------------------+-----------------------------------+
734 * | Register | BitsName |
735 * +======================+===================================+
736 * | PWR_RET01 | COMM_CORE_RST_N |
737 * +----------------------+-----------------------------------+
738 * \endrst
739 *
740 * @retval None
741 */
742 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
743 {
744 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
745 }
746
747 /**
748 * @brief Check if the Communication Core Reset was enabled or disabled.
749 *
750 * \rst
751 * +----------------------+-----------------------------------+
752 * | Register | BitsName |
753 * +======================+===================================+
754 * | PWR_RET01 | COMM_CORE_RST_N |
755 * +----------------------+-----------------------------------+
756 * \endrst
757 *
758 * @retval State of bit (1 or 0).
759 */
760 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
761 {
762 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
763 }
764
765 /**
766 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
767 *
768 * \rst
769 * +----------------------+-----------------------------------+
770 * | Register | BitsName |
771 * +======================+===================================+
772 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
773 * +----------------------+-----------------------------------+
774 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
775 * +----------------------+-----------------------------------+
776 * \endrst
777
778 *
779 * @retval None
780 */
781 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
782 {
783 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
784 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
785 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
786 }
787
788 /**
789 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
790 *
791 * \rst
792 * +----------------------+-----------------------------------+
793 * | Register | BitsName |
794 * +======================+===================================+
795 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
796 * +----------------------+-----------------------------------+
797 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
798 * +----------------------+-----------------------------------+
799 * \endrst
800
801 *
802 * @retval None
803 */
804 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
805 {
806 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
807 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
808 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
809 }
810
811 /**
812 * @brief Check if the Communication Timer Power was enabled or disabled.
813 *
814 * \rst
815 * +----------------------+-----------------------------------+
816 * | Register | BitsName |
817 * +======================+===================================+
818 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
819 * +----------------------+-----------------------------------+
820 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
821 * +----------------------+-----------------------------------+
822 * \endrst
823 *
824 * @retval State of bit (1 or 0).
825 */
826 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
827 {
828 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
829 }
830
831 /**
832 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
833 *
834 * \rst
835 * +----------------------+-----------------------------------+
836 * | Register | BitsName |
837 * +======================+===================================+
838 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
839 * +----------------------+-----------------------------------+
840 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
841 * +----------------------+-----------------------------------+
842 * \endrst
843 *
844 * @retval None
845 */
846 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
847 {
848 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
849 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
850 }
851
852 /**
853 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
854 *
855 * \rst
856 * +----------------------+-----------------------------------+
857 * | Register | BitsName |
858 * +======================+===================================+
859 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
860 * +----------------------+-----------------------------------+
861 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
862 * +----------------------+-----------------------------------+
863 * \endrst
864 *
865 * @retval None
866 */
867 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
868 {
869 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
870 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
871 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
872 }
873
874 /**
875 * @brief Check if the Communication Core Power was enabled or disabled.
876 *
877 * \rst
878 * +----------------------+-----------------------------------+
879 * | Register | BitsName |
880 * +======================+===================================+
881 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
882 * +----------------------+-----------------------------------+
883 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
884 * +----------------------+-----------------------------------+
885 * \endrst
886 *
887 *
888 * @retval None
889 */
890 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
891 {
892 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
893 }
894
895 /**
896 * @brief Select which timer value to read
897 *
898 * \rst
899 * +----------------------+-----------------------------------+
900 * | Register | BitsName |
901 * +======================+===================================+
902 * | PAD_CTL1 | TIMER_READ_SEL |
903 * +----------------------+-----------------------------------+
904 * \endrst
905 *
906 * @param select This parameter can be one of the following values:
907 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
908 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
909 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
910 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
911 * @retval None
912 */
913 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
914 {
915 GLOBAL_EXCEPTION_DISABLE();
916 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
917 GLOBAL_EXCEPTION_ENABLE();
918 }
919
920 /**
921 * @brief Get which timer value was selected to read.
922 *
923 * \rst
924 * +----------------------+-----------------------------------+
925 * | Register | BitsName |
926 * +======================+===================================+
927 * | PAD_CTL1 | TIMER_READ_SEL |
928 * +----------------------+-----------------------------------+
929 * \endrst
930 *
931 * @retval Returned value can be one of the following values:
932 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
933 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
934 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
935 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
936 */
937 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
938 {
939 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
940 }
941
942 /**
943 * @brief Get current timer value based on the selection.
944 * @note Please read multiple times until get a stable value.
945 *
946 * \rst
947 * +----------------------+-----------------------------------+
948 * | Register | BitsName |
949 * +======================+===================================+
950 * | PAD_CTL1 | TIMER_READ_SEL |
951 * +----------------------+-----------------------------------+
952 * \endrst
953 *
954 * @retval Returned value can be one of the following values:
955 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
956 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
957 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
958 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
959 */
960 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
961 {
962 return ((uint32_t)READ_REG(AON->TIMER_VAL));
963 }
964
965 /**
966 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
967 *
968 * \rst
969 * +----------------------+-----------------------------------+
970 * | Register | BitsName |
971 * +======================+===================================+
972 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
973 * +----------------------+-----------------------------------+
974 * \endrst
975 *
976 * @retval None
977 */
978 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
979 {
980 GLOBAL_EXCEPTION_DISABLE();
981 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
982 GLOBAL_EXCEPTION_ENABLE();
983 }
984
985
986 /**
987 * @brief Disable high frequency crystal oscillator sleep mode.
988 * @note Switch OSC from sleep mode into normal active mode.
989 *
990 * \rst
991 * +----------------------+-----------------------------------+
992 * | Register | BitsName |
993 * +======================+===================================+
994 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
995 * +----------------------+-----------------------------------+
996 * \endrst
997 *
998 * @retval None
999 */
1000 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
1001 {
1002 GLOBAL_EXCEPTION_DISABLE();
1003 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
1004 GLOBAL_EXCEPTION_ENABLE();
1005 }
1006
1007 /**
1008 * @brief Check if the OSC sleep mode was enabled or disabled.
1009 *
1010 * \rst
1011 * +----------------------+-----------------------------------+
1012 * | Register | BitsName |
1013 * +======================+===================================+
1014 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
1015 * +----------------------+-----------------------------------+
1016 * \endrst
1017 *
1018 * @retval State of bit (1 or 0).
1019 */
1020 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
1021 {
1022 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
1023 }
1024
1025 /**
1026 * @brief Enable Radio sleep mode, and disable Radio module.
1027 *
1028 * \rst
1029 * +----------------------+-----------------------------------+
1030 * | Register | BitsName |
1031 * +======================+===================================+
1032 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1033 * +----------------------+-----------------------------------+
1034 * \endrst
1035 *
1036 * @retval None
1037 */
1038 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
1039 {
1040 GLOBAL_EXCEPTION_DISABLE();
1041 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
1042 GLOBAL_EXCEPTION_ENABLE();
1043 }
1044
1045 /**
1046 * @brief Disable Radio sleep mode.
1047 * @note Switch Radio from sleep mode into normal active mode.
1048 *
1049 * \rst
1050 * +----------------------+-----------------------------------+
1051 * | Register | BitsName |
1052 * +======================+===================================+
1053 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1054 * +----------------------+-----------------------------------+
1055 * \endrst
1056 *
1057 * @retval None
1058 */
1059 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
1060 {
1061 GLOBAL_EXCEPTION_DISABLE();
1062 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
1063 GLOBAL_EXCEPTION_ENABLE();
1064 }
1065
1066 /**
1067 * @brief Check if the Radio sleep mode was enabled or disabled.
1068 *
1069 * \rst
1070 * +----------------------+-----------------------------------+
1071 * | Register | BitsName |
1072 * +======================+===================================+
1073 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1074 * +----------------------+-----------------------------------+
1075 * \endrst
1076 *
1077 * @retval State of bit (1 or 0).
1078 */
1079 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
1080 {
1081 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
1082 }
1083
1084 /**
1085 * @brief Enable Communication Core Deep Sleep Mode.
1086 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
1087 *
1088 * \rst
1089 * +----------------------+-----------------------------------+
1090 * | Register | BitsName |
1091 * +======================+===================================+
1092 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1093 * +----------------------+-----------------------------------+
1094 * \endrst
1095 *
1096 * @retval None
1097 */
1098 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
1099 {
1100 GLOBAL_EXCEPTION_DISABLE();
1101 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
1102 GLOBAL_EXCEPTION_ENABLE();
1103 }
1104
1105 /**
1106 * @brief Disable Communication Core Deep Sleep Mode.
1107 * @note Switch Communication Core from sleep mode into normal active mode.
1108 *
1109 * \rst
1110 * +----------------------+-----------------------------------+
1111 * | Register | BitsName |
1112 * +======================+===================================+
1113 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1114 * +----------------------+-----------------------------------+
1115 * \endrst
1116 *
1117 * @retval None
1118 */
1119 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
1120 {
1121 GLOBAL_EXCEPTION_DISABLE();
1122 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
1123 GLOBAL_EXCEPTION_ENABLE();
1124 }
1125
1126 /**
1127 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
1128 *
1129 * \rst
1130 * +----------------------+-----------------------------------+
1131 * | Register | BitsName |
1132 * +======================+===================================+
1133 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1134 * +----------------------+-----------------------------------+
1135 * \endrst
1136 *
1137 * @retval State of bit (1 or 0).
1138 */
1139 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
1140 {
1141 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
1142 }
1143
1144 /**
1145 * @brief Enable Wake Up Request from Software.
1146 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
1147 * when written with a 1. No action happens if it is written with 0.
1148 *
1149 * \rst
1150 * +----------------------+-----------------------------------+
1151 * | Register | BitsName |
1152 * +======================+===================================+
1153 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ |
1154 * +----------------------+-----------------------------------+
1155 * \endrst
1156 *
1157 * @retval None
1158 */
1159 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
1160 {
1161 GLOBAL_EXCEPTION_DISABLE();
1162 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
1163 GLOBAL_EXCEPTION_ENABLE();
1164 }
1165
1166 /**
1167 * @brief Check if the Wake Up Request was enabled or disabled.
1168 * @note Resets at 0 means request action is performed.
1169 *
1170 * \rst
1171 * +----------------------+-----------------------------------+
1172 * | Register | BitsName |
1173 * +======================+===================================+
1174 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ |
1175 * +----------------------+-----------------------------------+
1176 * \endrst
1177 *
1178 * @retval State of bit (1 or 0).
1179 */
1180 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1181 {
1182 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1183 }
1184
1185 /**
1186 * @brief Enable Communication Core external wakeup.
1187 * @note After this configuration, Communication Core can be woken up by external wake-up
1188 *
1189 * \rst
1190 * +----------------------+-----------------------------------+
1191 * | Register | BitsName |
1192 * +======================+===================================+
1193 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1194 * +----------------------+-----------------------------------+
1195 * \endrst
1196 *
1197 * @retval None
1198 */
1199 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1200 {
1201 GLOBAL_EXCEPTION_DISABLE();
1202 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1203 GLOBAL_EXCEPTION_ENABLE();
1204 }
1205
1206 /**
1207 * @brief Disable Communication Core external wakeup.
1208 * @note After this configuration, Communication Core cannot be woken up by external wake-up
1209 *
1210 * \rst
1211 * +----------------------+-----------------------------------+
1212 * | Register | BitsName |
1213 * +======================+===================================+
1214 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1215 * +----------------------+-----------------------------------+
1216 * \endrst
1217 *
1218 * @retval None
1219 */
1220 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1221 {
1222 GLOBAL_EXCEPTION_DISABLE();
1223 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1224 GLOBAL_EXCEPTION_ENABLE();
1225 }
1226
1227 /**
1228 * @brief Check if the Communication Core external wakeup was enabled or disabled.
1229 *
1230 * \rst
1231 * +----------------------+-----------------------------------+
1232 * | Register | BitsName |
1233 * +======================+===================================+
1234 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1235 * +----------------------+-----------------------------------+
1236 * \endrst
1237 *
1238 * @retval State of bit (1 or 0).
1239 */
1240 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1241 {
1242 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1243 }
1244
1245 /**
1246 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1247 *
1248 * \rst
1249 * +----------------------+-----------------------------------+
1250 * | Register | BitsName |
1251 * +======================+===================================+
1252 * | COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME|
1253 * +----------------------+-----------------------------------+
1254 * \endrst
1255 *
1256 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1257 * @retval None
1258 */
1259 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1260 {
1261 WRITE_REG(AON->PWR_RET28, time);
1262 }
1263
1264 /**
1265 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1266 *
1267 * \rst
1268 * +----------------------+-----------------------------------+
1269 * | Register | BitsName |
1270 * +======================+===================================+
1271 * | COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME|
1272 * +----------------------+-----------------------------------+
1273 * \endrst
1274 *
1275 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
1276 */
1277 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1278 {
1279 return ((uint32_t)READ_REG(AON->PWR_RET28));
1280 }
1281
1282
1283 /**
1284 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
1285 *
1286 * \rst
1287 * +----------------------+-----------------------------------+
1288 * | Register | BitsName |
1289 * +======================+===================================+
1290 * | COMM_TMR_DEEPSLPSTAT | DEEPSLDUR |
1291 * +----------------------+-----------------------------------+
1292 * \endrst
1293 *
1294 * @retval Sleep duration
1295 */
1296 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1297 {
1298 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1299 }
1300
1301 /**
1302 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1303 *
1304 * \rst
1305 * +----------------------+-----------------------------------+
1306 * | Register | BitsName |
1307 * +======================+===================================+
1308 * | COMM_TMR_ENBPRESET | TWEXT |
1309 * +----------------------+-----------------------------------+
1310 * | COMM_TMR_ENBPRESET | TWOSC |
1311 * +----------------------+-----------------------------------+
1312 * | COMM_TMR_ENBPRESET | TWRM |
1313 * +----------------------+-----------------------------------+
1314 * \endrst
1315 *
1316 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
1317 * oscillator following an external wake–up request (signal wakeup_req).
1318 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
1319 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
1320 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
1321 * @retval None
1322 */
1323 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1324 {
1325 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1326 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1327 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1328 }
1329
1330
1331 /**
1332 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1333 *
1334 * \rst
1335 * +----------------------+-----------------------------------+
1336 * | Register | BitsName |
1337 * +======================+===================================+
1338 * | COMM_TMR_ENBPRESET | TWEXT |
1339 * +----------------------+-----------------------------------+
1340 * | COMM_TMR_ENBPRESET | TWOSC |
1341 * +----------------------+-----------------------------------+
1342 * | COMM_TMR_ENBPRESET | TWRM |
1343 * +----------------------+-----------------------------------+
1344 * \endrst
1345 *
1346 *
1347 * @retval COMM_TMR_ENBPRESET Register value
1348 */
1349 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1350 {
1351 return ((uint32_t)READ_REG(AON->PWR_RET29));
1352 }
1353
1354 /**
1355 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1356 *
1357 * @retval TWOSC value
1358 */
1359 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1360 {
1361 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1362 }
1363
1364
1365 /** @} */
1366
1367 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1368 * @{
1369 */
1370
1371 /**
1372 * @brief Get the External Wake Up Status.
1373 * @note 0 means not waked up and 1 means waked up.
1374 *
1375 * \rst
1376 * +----------------------+-----------------------------------+
1377 * | Register | BitsName |
1378 * +======================+===================================+
1379 * | SLP_EVENT | EXT_WKUP_STATUS |
1380 * +----------------------+-----------------------------------+
1381 * \endrst
1382 *
1383 * @retval Returned value can be a combination of the following values:
1384 * @arg @ref LL_PWR_EXTWKUP_PIN0
1385 * @arg @ref LL_PWR_EXTWKUP_PIN1
1386 * @arg @ref LL_PWR_EXTWKUP_PIN2
1387 * @arg @ref LL_PWR_EXTWKUP_PIN3
1388 * @arg @ref LL_PWR_EXTWKUP_PIN4
1389 * @arg @ref LL_PWR_EXTWKUP_PIN5
1390 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1391 */
1392 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1393 {
1394 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1395 (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1396 }
1397
1398 /**
1399 * @brief Clear the External Wake Up Status.
1400 *
1401 * \rst
1402 * +----------------------+-----------------------------------+
1403 * | Register | BitsName |
1404 * +======================+===================================+
1405 * | SLP_EVENT | EXT_WKUP_STATUS |
1406 * +----------------------+-----------------------------------+
1407 * \endrst
1408 *
1409 * @param wakeup_pin This parameter can be a combination of the following values:
1410 * @arg @ref LL_PWR_EXTWKUP_PIN0
1411 * @arg @ref LL_PWR_EXTWKUP_PIN1
1412 * @arg @ref LL_PWR_EXTWKUP_PIN2
1413 * @arg @ref LL_PWR_EXTWKUP_PIN3
1414 * @arg @ref LL_PWR_EXTWKUP_PIN4
1415 * @arg @ref LL_PWR_EXTWKUP_PIN5
1416 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1417 * @retval None
1418 */
1419 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1420 {
1421 GLOBAL_EXCEPTION_DISABLE();
1422 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1423 GLOBAL_EXCEPTION_ENABLE();
1424 }
1425
1426 /**
1427 * @brief Clear the Event that triggered the DeepSleep WakeUp.
1428 *
1429 * \rst
1430 * +----------------------+-----------------------------------+
1431 * | Register | BitsName |
1432 * +======================+===================================+
1433 * | SLP_EVENT | SMCOSCEN_EVENT |
1434 * +----------------------+-----------------------------------+
1435 * \endrst
1436 * SLP_EVENT | TIMER_EVENT
1437 * SLP_EVENT | EXT_WKUP_EVENT
1438 * SLP_EVENT | WATCHDOG_EVENT
1439 *
1440 * @param event This parameter can be a combination of the following values:
1441 * @arg @ref LL_PWR_WKUP_EVENT_BLE
1442 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
1443 * @arg @ref LL_PWR_WKUP_EVENT_EXT
1444 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
1445 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
1446 * @arg @ref LL_PWR_WKUP_EVENT_WDT
1447 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
1448 * @retval None
1449 */
1450 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1451 {
1452 WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1453 }
1454
1455 /**
1456 * @brief Indicate if the Power State Controller is in busy state.
1457 * @note This is bit set 1 when the PSC_CMD_REQ[0] is set to 1, and will remain 1 until
1458 * the PSC_CMD_OPC has been transferred to the PSC.
1459 *
1460 * \rst
1461 * +----------------------+-----------------------------------+
1462 * | Register | BitsName |
1463 * +======================+===================================+
1464 * | PSC_CMD | MCU_PWR_BUSY |
1465 * +----------------------+-----------------------------------+
1466 * \endrst
1467 *
1468 * @retval State of bit (1 or 0).
1469 */
1470 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1471 {
1472 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1473 }
1474
1475 /**
1476 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
1477 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
1478 *
1479 * \rst
1480 * +----------------------+-----------------------------------+
1481 * | Register | BitsName |
1482 * +======================+===================================+
1483 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT |
1484 * +----------------------+-----------------------------------+
1485 * \endrst
1486 *
1487 * @retval State of bit (1 or 0).
1488 */
1489 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1490 {
1491 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1492 }
1493
1494 /**
1495 * @brief Disable cache function
1496 * @note The cache should be closed before chip go to deepsleep.
1497 *
1498 * \rst
1499 * +----------------------+-----------------------------------+
1500 * | Register | BitsName |
1501 * +======================+===================================+
1502 * | CTRL0 | EN |
1503 * +----------------------+-----------------------------------+
1504 * \endrst
1505 *
1506 * @retval None
1507 */
1508 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1509 {
1510 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1511 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
1512 }
1513
1514 /** @} */
1515
1516 /** @} */
1517 /** @} */
1518
1519 #endif /* defined(AON) */
1520
1521 #ifdef __cplusplus
1522 }
1523 #endif
1524
1525 #endif /* __GR55xx_LL_PWR_H__ */
1526
1527 /** @} */
1528
1529 /** @} */
1530
1531 /** @} */
ll_pwr_disable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1220
ll_pwr_enable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:529
ll_pwr_get_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
Get which timer value was selected to read.
Definition: gr55xx_ll_pwr.h:937
ll_pwr_enable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1199
ll_pwr_set_dpad_le_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
Definition: gr55xx_ll_pwr.h:593
ll_pwr_disable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
Definition: gr55xx_ll_pwr.h:1059
ll_pwr_is_enabled_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1180
ll_pwr_is_enabled_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:890
ll_pwr_set_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
Set the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:435
ll_pwr_is_enabled_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1139
ll_pwr_disable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
Definition: gr55xx_ll_pwr.h:742
ll_pwr_get_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1392
ll_pwr_read_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1349
ll_pwr_get_timer_read_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
Get current timer value based on the selection.
Definition: gr55xx_ll_pwr.h:960
ll_pwr_disable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
Definition: gr55xx_ll_pwr.h:1000
ll_pwr_disable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
Definition: gr55xx_ll_pwr.h:684
ll_pwr_set_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:267
LL_PWR_EXTWKUP_PIN_ALL
#define LL_PWR_EXTWKUP_PIN_ALL
WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7.
Definition: gr55xx_ll_pwr.h:155
ll_pwr_read_comm_wakeup_timing_twosc
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1359
ll_pwr_get_comm_sleep_duration
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
Definition: gr55xx_ll_pwr.h:1296
ll_pwr_set_comm_core_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1259
ll_pwr_is_enabled_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:760
ll_pwr_set_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:492
ll_pwr_is_active_flag_psc_cmd_busy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
Indicate if the Power State Controller is in busy state.
Definition: gr55xx_ll_pwr.h:1470
ll_pwr_enable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
Definition: gr55xx_ll_pwr.h:846
ll_pwr_disable_cache_module
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
Definition: gr55xx_ll_pwr.h:1508
ll_pwr_is_enabled_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
Check if the External WakeUp PINx functionality is enabled.
Definition: gr55xx_ll_pwr.h:403
ll_pwr_enable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
Definition: gr55xx_ll_pwr.h:723
ll_pwr_clear_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1419
ll_pwr_set_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
Select which timer value to read.
Definition: gr55xx_ll_pwr.h:913
ll_pwr_disable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:548
LL_PWR_WKUP_EVENT_ALL
#define LL_PWR_WKUP_EVENT_ALL
All event mask
Definition: gr55xx_ll_pwr.h:135
LL_PWR_EXTWKUP_INVERT_LSB
#define LL_PWR_EXTWKUP_INVERT_LSB
External wakeup level invert.
Definition: gr55xx_ll_pwr.h:80
ll_pwr_is_enabled_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:566
ll_pwr_enable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
Definition: gr55xx_ll_pwr.h:665
ll_pwr_is_active_flag_comm_deep_sleep_stat
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1489
ll_pwr_disable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
Definition: gr55xx_ll_pwr.h:867
ll_pwr_clear_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:1450
ll_pwr_disable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
Disable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:375
ll_pwr_get_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:292
ll_pwr_enable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
Definition: gr55xx_ll_pwr.h:781
ll_pwr_set_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1323
ll_pwr_enable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1098
ll_pwr_disable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1119
ll_pwr_enable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
Enable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:347
ll_pwr_is_enabled_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1240
LL_PWR_EXTWKUP_TYPE_LSB
#define LL_PWR_EXTWKUP_TYPE_LSB
External wakeup level type.
Definition: gr55xx_ll_pwr.h:79
ll_pwr_enable_comm_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
Definition: gr55xx_ll_pwr.h:1159
ll_pwr_enable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
Definition: gr55xx_ll_pwr.h:1038
ll_pwr_get_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:321
ll_pwr_enable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
Definition: gr55xx_ll_pwr.h:978
ll_pwr_get_comm_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1277
ll_pwr_is_enabled_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:702
ll_pwr_is_enabled_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:826
ll_pwr_get_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:510
ll_pwr_get_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
Get the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:471
ll_pwr_is_enabled_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1079
ll_pwr_is_enabled_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1020
ll_pwr_req_excute_psc_command
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
Request to excute the Power State Controller Command.
Definition: gr55xx_ll_pwr.h:638
ll_pwr_disable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
Definition: gr55xx_ll_pwr.h:804