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GR551x API Reference  V1_6_06_B5676
gr55xx_ll_pwr.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_pwr.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of PWR LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_PWR PWR
47  * @brief PWR LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 #if defined(AON)
63 
64 /**
65  * @defgroup PWR_LL_MACRO Defines
66  * @{
67  */
68 
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
73  * @{
74  */
75 
76 /** @defgroup PWR_LL_PC_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
77  * @{
78  */
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos) /**< External wakeup level type */
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos) /**< External wakeup level invert */
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos) /**< External wakeup source enable */
82 /** @} */
83 
84 /** @} */
85 
86 /* Private macros ------------------------------------------------------------*/
87 /** @defgroup PWR_LL_Private_Macro PWR Private Macros
88  * @{
89  */
90 
91 /** @defgroup PWR_LL_PM_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
92  * @{
93  */
94 
95 /**
96  * @brief PWR_LL_PM_GET_MEM_PWR_MSK PWR Get Memory Power Value Mask
97  */
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99  (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100 
101 /** @} */
102 
103 /** @} */
104 
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
108  * @{
109  */
110 
111 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
112  * @{
113  */
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP /**< External wakeup: AON_GPIO */
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER /**< AON Timer wakeup */
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE /**< BLE wakeup */
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR /**< Calendar wakeup */
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE /**< PMU Bod falling edge wakeup */
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP /**< Msio comparator wakeup */
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL /**< All wakeup sources mask */
121 /** @} */
122 
123 
124 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
125  * @note Only available on GR551xx_B2 and later version
126  * @{
127  */
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN /**< BLE Timer wakeup event */
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER /**< AON Timer wakeup event */
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP /**< External wakeup event: AON_GPIO */
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE /**< PMU Bod wakeup event */
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP /**< Msio comparator wakeup event */
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT /**< AON WDT wakeup event */
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM /**< Calendar wakeup event */
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136  AON_SLP_EVENT_TIMER | \
137  AON_SLP_EVENT_EXTWKUP | \
138  AON_SLP_EVENT_PMU_BOD_FEDGE | \
139  AON_SLP_EVENT_PMU_MSIO_COMP | \
140  AON_SLP_EVENT_WDT_REBOOT | \
141  AON_SLP_EVENT_CALENDAR_TIMER_ALARM) /**< All event mask */
142 /** @} */
143 
144 /** @defgroup PWR_LL_EC_EXTWAKEUP_PIN External Wakeup Pins
145  * @{
146  */
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U) /**< WKUP pin 0 : AON_GPIO_PIN0 */
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U) /**< WKUP pin 1 : AON_GPIO_PIN1 */
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U) /**< WKUP pin 2 : AON_GPIO_PIN2 */
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U) /**< WKUP pin 3 : AON_GPIO_PIN3 */
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U) /**< WKUP pin 4 : AON_GPIO_PIN4 */
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U) /**< WKUP pin 5 : AON_GPIO_PIN5 */
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U) /**< WKUP pin 6 : AON_GPIO_PIN6 */
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U) /**< WKUP pin 7 : AON_GPIO_PIN7 */
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU) /**< WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7 */
156 /** @} */
157 
158 /** @defgroup PWR_LL_EC_EXTWAKEUP_TYPE External Wakeup Type
159  * @{
160  */
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Low level wakeup */
162 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< High level wakeup */
163 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U) /**< Rising edge wakeup */
164 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Falling edge wakeup */
165 /** @} */
166 
167 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
168  * @{
169  */
170 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK /**< Reserved command 0 */
171 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON /**< Reserved command 1 */
172 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD /**< Load sleep timer command */
173 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP /**< Enter Deep Sleep Mode command */
174 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF /**< Reserved command 2 */
175 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK /**< Select external clock (xo_32KHz) command */
176 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK /**< Select RING OSC clock command */
177 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK /**< Select RTC clock command */
178 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK /**< Select RING OSC clock command */
179 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG /**< Load memory sleep settings command */
180 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG /**< Load memory wakeup settings command */
181 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI /**< Force dpad_le high */
182 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO /**< Force dpad_le low */
183 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 /**< Enable sleep timer mode 0 command */
184 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 /**< Enable sleep timer mode 1 command */
185 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 /**< Enable sleep timer mode 2 command */
186 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 /**< Enable sleep timer mode 3 command */
187 /** @} */
188 
189 
190 /** @} */
191 
192 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
193  * @{
194  */
195 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
196 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
197 /** @} */
198 
199 /** @defgroup PWR_LL_EC_TIMER_READ_SEL Timer Read Select
200  * @note Only available on GR551xx_B2 and later version
201  * @{
202  */
203 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER /**< Calendar timer */
204 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT /**< AON watchdog timer */
205 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER /**< Sleep timer */
206 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM /**< Calendar alarm */
207 /** @} */
208 
209 /** @} */
210 
211 
212 /* Exported macro ------------------------------------------------------------*/
213 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
214  * @{
215  */
216 
217 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
218  * @{
219  */
220 
221 /**
222  * @brief Write a value in PWR register
223  * @param __REG__ Register to be written
224  * @param __VALUE__ Value to be written in the register
225  * @retval None
226  */
227 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
228 
229 /**
230  * @brief Read a value in PWR register
231  * @param __REG__ Register to be read
232  * @retval Register value
233  */
234 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
235 /** @} */
236 
237 
238 /* Exported functions --------------------------------------------------------*/
239 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
240  * @{
241  */
242 
243 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
244  * @{
245  */
246 
247 /**
248  * @brief Set the DeepSleep WakeUp Condition
249  *
250  * Register|BitsName
251  * --------|--------
252  * EXT_WKUP_CTL | WAKE_UP_SEL
253  *
254  * @param condition This parameter can be one of the following values:
255  * @arg @ref LL_PWR_WKUP_COND_EXT
256  * @arg @ref LL_PWR_WKUP_COND_TIMER
257  * @arg @ref LL_PWR_WKUP_COND_BLE
258  * @arg @ref LL_PWR_WKUP_COND_CALENDAR
259  * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
260  * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
261  * @arg @ref LL_PWR_WKUP_COND_ALL
262  * @retval None
263  */
264 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
265 {
266  MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
267 }
268 
269 /**
270  * @brief Get the Selected DeepSleep WakeUp Condition
271  *
272  * Register|BitsName
273  * --------|--------
274  * EXT_WKUP_CTL | WAKE_UP_SEL
275  *
276  * @retval Returned value can be one of the following values:
277  * @arg @ref LL_PWR_WKUP_COND_EXT
278  * @arg @ref LL_PWR_WKUP_COND_TIMER
279  * @arg @ref LL_PWR_WKUP_COND_BLE
280  * @arg @ref LL_PWR_WKUP_COND_CALENDAR
281  * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
282  * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
283  * @arg @ref LL_PWR_WKUP_COND_ALL
284  */
285 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
286 {
287  return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
288 }
289 
290 /**
291  * @brief Get the Event that triggered the DeepSleep WakeUp.
292  * @note Only available on GR551xx_B2 and later version
293  *
294  * Register|BitsName
295  * --------|--------
296  * SLP_EVENT | SMCOSCEN_EVENT
297  * SLP_EVENT | TIMER_EVENT
298  * SLP_EVENT | EXT_WKUP_EVENT
299  * SLP_EVENT | WATCHDOG_EVENT
300  *
301  * @retval Returned value can be combination of the following values:
302  * @arg @ref LL_PWR_WKUP_EVENT_BLE
303  * @arg @ref LL_PWR_WKUP_EVENT_TIMER
304  * @arg @ref LL_PWR_WKUP_EVENT_EXT
305  * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
306  * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
307  * @arg @ref LL_PWR_WKUP_EVENT_WDT
308  * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
309  */
310 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
311 {
312  return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
313 }
314 
315 /**
316  * @brief Enable the External WakeUp PINx functionality
317  *
318  * Register|BitsName
319  * --------|--------
320  * EXT_WKUP_CTL | MASK
321  *
322  * @param wakeup_pin This parameter can be a combination of the following values:
323  * @arg @ref LL_PWR_EXTWKUP_PIN0
324  * @arg @ref LL_PWR_EXTWKUP_PIN1
325  * @arg @ref LL_PWR_EXTWKUP_PIN2
326  * @arg @ref LL_PWR_EXTWKUP_PIN3
327  * @arg @ref LL_PWR_EXTWKUP_PIN4
328  * @arg @ref LL_PWR_EXTWKUP_PIN5
329  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
330  * @retval None
331  */
332 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
333 {
334  GLOBAL_EXCEPTION_DISABLE();
335  SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
336  GLOBAL_EXCEPTION_ENABLE();
337 }
338 
339 /**
340  * @brief Disable the External WakeUp PINx functionality
341  *
342  * Register|BitsName
343  * --------|--------
344  * EXT_WKUP_CTL | MASK
345  *
346  * @param wakeup_pin This parameter can be a combination of the following values:
347  * @arg @ref LL_PWR_EXTWKUP_PIN0
348  * @arg @ref LL_PWR_EXTWKUP_PIN1
349  * @arg @ref LL_PWR_EXTWKUP_PIN2
350  * @arg @ref LL_PWR_EXTWKUP_PIN3
351  * @arg @ref LL_PWR_EXTWKUP_PIN4
352  * @arg @ref LL_PWR_EXTWKUP_PIN5
353  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
354  * @retval None
355  */
356 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
357 {
358  GLOBAL_EXCEPTION_DISABLE();
359  CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
360  GLOBAL_EXCEPTION_ENABLE();
361 }
362 
363 /**
364  * @brief Check if the External WakeUp PINx functionality is enabled
365  *
366  * Register|BitsName
367  * --------|--------
368  * EXT_WKUP_CTL | MASK
369  *
370  * @param wakeup_pin This parameter can be a combination of the following values:
371  * @arg @ref LL_PWR_EXTWKUP_PIN0
372  * @arg @ref LL_PWR_EXTWKUP_PIN1
373  * @arg @ref LL_PWR_EXTWKUP_PIN2
374  * @arg @ref LL_PWR_EXTWKUP_PIN3
375  * @arg @ref LL_PWR_EXTWKUP_PIN4
376  * @arg @ref LL_PWR_EXTWKUP_PIN5
377  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
378  * @retval State of bit (1 or 0).
379  */
380 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
381 {
382  return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
383 }
384 
385 /**
386  * @brief Set the WakeUp Type of External WakeUp PINx.
387  *
388  * Register|BitsName
389  * --------|--------
390  * EXT_WKUP_CTL | INVERT
391  * EXT_WKUP_CTL | TYPE
392  *
393  * @param wakeup_pin This parameter can be a combination of the following values:
394  * @arg @ref LL_PWR_EXTWKUP_PIN0
395  * @arg @ref LL_PWR_EXTWKUP_PIN1
396  * @arg @ref LL_PWR_EXTWKUP_PIN2
397  * @arg @ref LL_PWR_EXTWKUP_PIN3
398  * @arg @ref LL_PWR_EXTWKUP_PIN4
399  * @arg @ref LL_PWR_EXTWKUP_PIN5
400  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
401  * @param wakeup_type This parameter can be one of the following values:
402  * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
403  * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
404  * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
405  * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
406  * @retval None
407  */
408 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
409 {
410  uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
411  uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
412  GLOBAL_EXCEPTION_DISABLE();
413  MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
414  GLOBAL_EXCEPTION_ENABLE();
415 }
416 
417 /**
418  * @brief Get the WakeUp Type of External WakeUp PINx.
419  * @note Warning: only one pin can be passed as parameter.
420  *
421  * Register|BitsName
422  * --------|--------
423  * EXT_WKUP_CTL | INVERT
424  * EXT_WKUP_CTL | TYPE
425  *
426  * @param wakeup_pin This parameter can be one of the following values:
427  * @arg @ref LL_PWR_EXTWKUP_PIN0
428  * @arg @ref LL_PWR_EXTWKUP_PIN1
429  * @arg @ref LL_PWR_EXTWKUP_PIN2
430  * @arg @ref LL_PWR_EXTWKUP_PIN3
431  * @arg @ref LL_PWR_EXTWKUP_PIN4
432  * @arg @ref LL_PWR_EXTWKUP_PIN5
433  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
434  * @retval Returned value can be one of the following values:
435  * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
436  * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
437  * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
438  * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
439  */
440 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
441 {
442  return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
443 }
444 
445 /**
446  * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
447  * @note After the value was set, use @arg @ref LL_PWR_CMD_32_TIMER_LD command to
448  * load the configuration into Power State Controller.
449  *
450  * Register|BitsName
451  * --------|--------
452  * TIMER_VALUE | PWR_CTL_TIMER_32B
453  *
454  * @param value 32 bits count value loaded into the t32bit_timer
455  * @retval None
456  */
457 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
458 {
459  WRITE_REG(AON->TIMER_VALUE, value);
460 }
461 
462 /**
463  * @brief Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
464  *
465  * Register|BitsName
466  * --------|--------
467  * TIMER_VALUE | PWR_CTL_TIMER_32B
468  *
469  * @retval 32 bit AON Timer Count Value
470  */
471 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
472 {
473  return READ_REG(AON->TIMER_VALUE);
474 }
475 
476 /**
477  * @brief Enable the SMC WakeUp Request.
478  * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
479  *
480  * Register|BitsName
481  * --------|--------
482  * PWR_RET01 | SMC_WAKEUP_REQ
483  *
484  * @retval None
485  */
486 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
487 {
488  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
489 }
490 
491 /**
492  * @brief Disable the SMC WakeUp Request.
493  * @note This function is used to clear SMC WakeUp Request.
494  *
495  * Register|BitsName
496  * --------|--------
497  * PWR_RET01 | SMC_WAKEUP_REQ
498  *
499  * @retval None
500  */
501 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
502 {
503  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
504 }
505 
506 /**
507  * @brief Check if the SMC WakeUp Request was enabled or disabled.
508  *
509  * Register|BitsName
510  * --------|--------
511  * PWR_RET01 | SMC_WAKEUP_REQ
512  *
513  * @retval State of bit (1 or 0).
514  */
515 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
516 {
517  return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
518 }
519 
520 /**
521  * @brief Set the DPAD LE value during sleep and after wake up.
522  *
523  * Register|BitsName
524  * --------|--------
525  * MEM_N_SLP_CTL | DPAD_LE_SLP_VAL
526  * MEM_N_SLP_CTL | DPAD_LE_WKUP_VAL
527  *
528  * @param sleep This parameter can be one of the following values:
529  * @arg @ref LL_PWR_DPAD_LE_OFF
530  * @arg @ref LL_PWR_DPAD_LE_ON
531  * @param wakeup This parameter can be one of the following values:
532  * @arg @ref LL_PWR_DPAD_LE_OFF
533  * @arg @ref LL_PWR_DPAD_LE_ON
534  * @retval None
535  */
536 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
537 {
538  MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
539  MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
540 }
541 
542 /**
543  * @brief Request to excute the Power State Controller Command.
544  * @note The PSC command can only be excuted when Power State Controller is not in busy state.
545  * Use @ref ll_pwr_is_active_flag_psc_cmd_busy() to check the busy status, and make sure
546  * the last command has been finished.
547  *
548  * Register|BitsName
549  * --------|--------
550  * PSC_CMD_OPC | OPCODE
551  * PSC_CMD | MCU_PWR_REQ
552  *
553  * @param command This parameter can be one of the following values:
554  * @arg @ref LL_PWR_CMD_LOOPBACK
555  * @arg @ref LL_PWR_CMD_EF_DIR_ON
556  * @arg @ref LL_PWR_CMD_32_TIMER_LD
557  * @arg @ref LL_PWR_CMD_DEEP_SLEEP
558  * @arg @ref LL_PWR_CMD_EF_DIR_OFF
559  * @arg @ref LL_PWR_CMD_EXT_CLK
560  * @arg @ref LL_PWR_CMD_RNG_CLK
561  * @arg @ref LL_PWR_CMD_RTC_CLK
562  * @arg @ref LL_PWR_CMD_LD_MEM_SLP_CFG
563  * @arg @ref LL_PWR_CMD_LD_MEM_WKUP_CFG
564  * @arg @ref LL_PWR_CMD_DPAD_LE_HI (*)
565  * @arg @ref LL_PWR_CMD_DPAD_LE_LO (*)
566  * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_NORMAL (*)
567  * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_SINGLE (*)
568  * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_RELOAD (*)
569  * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_DISABLE (*)
570  *
571  * (*) Not available in A0 and B0
572  *
573  * @retval None
574  */
575 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
576 {
577  WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
578  SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
579 }
580 
581 /** @} */
582 
583 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
584  * @{
585  */
586 
587 /**
588  * @brief Enable the Communication Timer Reset.
589  * @note Comm timer can be reset when all ble connection were disconnected and
590  * MCU was ready to enter into deepsleep mode.
591  *
592  * Register|BitsName
593  * --------|--------
594  * PWR_RET01 | COMM_TIMER_RST_N
595  *
596  * @retval None
597  */
598 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
599 {
600  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
601 }
602 
603 /**
604  * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
605  * @note After powered up, Comm Timer need to enter into running mode.
606  *
607  * Register|BitsName
608  * --------|--------
609  * PWR_RET01 | COMM_TIMER_RST_N
610  *
611  * @retval None
612  */
613 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
614 {
615  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
616 }
617 
618 /**
619  * @brief Check if the Communication Timer Reset was enabled or disabled.
620  *
621  * Register|BitsName
622  * --------|--------
623  * PWR_RET01 | COMM_TIMER_RST_N
624  *
625  * @retval State of bit (1 or 0).
626  */
627 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
628 {
629  return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
630 }
631 
632 /**
633  * @brief Enable the Communication Core Reset.
634  * @note Comm Core can be reset when all ble connection were disconnected and
635  * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
636  * is 0, the ble is held in reset.
637  *
638  * Register|BitsName
639  * --------|--------
640  * PWR_RET01 | COMM_CORE_RST_N
641  *
642  * @retval None
643  */
644 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
645 {
646  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
647 }
648 
649 /**
650  * @brief Disable the Communication Core Reset, and set Communication Core to running state.
651  * @note After powered up, Comm Core need to enter into running mode.
652  *
653  * Register|BitsName
654  * --------|--------
655  * PWR_RET01 | COMM_CORE_RST_N
656  *
657  * @retval None
658  */
659 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
660 {
661  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
662 }
663 
664 /**
665  * @brief Check if the Communication Core Reset was enabled or disabled.
666  *
667  * Register|BitsName
668  * --------|--------
669  * PWR_RET01 | COMM_CORE_RST_N
670  *
671  * @retval State of bit (1 or 0).
672  */
673 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
674 {
675  return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
676 }
677 
678 /**
679  * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
680  *
681  * Register|BitsName
682  * --------|--------
683  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
684  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
685  *
686  * @retval None
687  */
688 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
689 {
690  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
691  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
692  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
693 }
694 
695 /**
696  * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
697  *
698  * Register|BitsName
699  * --------|--------
700  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
701  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
702  *
703  * @retval None
704  */
705 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
706 {
707  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
708  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
709  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
710 }
711 
712 /**
713  * @brief Check if the Communication Timer Power was enabled or disabled.
714  *
715  * Register|BitsName
716  * --------|--------
717  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
718  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
719  *
720  * @retval State of bit (1 or 0).
721  */
722 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
723 {
724  return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
725 }
726 
727 /**
728  * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
729  *
730  * Register|BitsName
731  * --------|--------
732  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
733  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
734  *
735  * @retval None
736  */
737 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
738 {
739  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
740  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
741 }
742 
743 /**
744  * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
745  *
746  * Register|BitsName
747  * --------|--------
748  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
749  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
750  *
751  * @retval None
752  */
753 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
754 {
755  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
756  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
757  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
758 }
759 
760 /**
761  * @brief Check if the Communication Core Power was enabled or disabled.
762  *
763  * Register|BitsName
764  * --------|--------
765  * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
766  * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
767  *
768  * @retval None
769  */
770 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
771 {
772  return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
773 }
774 
775 /**
776  * @brief Select which timer value to read
777  *
778  * Register|BitsName
779  * --------|--------
780  * PAD_CTL1 | TIMER_READ_SEL
781  *
782  * @param select This parameter can be one of the following values:
783  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
784  * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
785  * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
786  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
787  * @retval None
788  */
789 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
790 {
791  GLOBAL_EXCEPTION_DISABLE();
792  MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
793  GLOBAL_EXCEPTION_ENABLE();
794 }
795 
796 /**
797  * @brief Get which timer value was selected to read.
798  *
799  * Register|BitsName
800  * --------|--------
801  * PAD_CTL1 | TIMER_READ_SEL
802  *
803  * @retval Returned value can be one of the following values:
804  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
805  * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
806  * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
807  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
808  */
809 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
810 {
811  return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
812 }
813 
814 /**
815  * @brief Get current timer value based on the selection.
816  * @note Please read multiple times until get a stable value.
817  *
818  * Register|BitsName
819  * --------|--------
820  * PAD_CTL1 | TIMER_READ_SEL
821  *
822  * @retval Returned value can be one of the following values:
823  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
824  * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
825  * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
826  * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
827  */
828 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
829 {
830  return ((uint32_t)READ_REG(AON->TIMER_VAL));
831 }
832 
833 /**
834  * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
835  *
836  * Register|BitsName
837  * --------|--------
838  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
839  *
840  * @retval None
841  */
842 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
843 {
844  GLOBAL_EXCEPTION_DISABLE();
845  SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
846  GLOBAL_EXCEPTION_ENABLE();
847 }
848 
849 
850 /**
851  * @brief Disable high frequency crystal oscillator sleep mode.
852  * @note Switch OSC from sleep mode into normal active mode.
853  *
854  * Register|BitsName
855  * --------|--------
856  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
857  *
858  * @retval None
859  */
860 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
861 {
862  GLOBAL_EXCEPTION_DISABLE();
863  CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
864  GLOBAL_EXCEPTION_ENABLE();
865 }
866 
867 /**
868  * @brief Check if the OSC sleep mode was enabled or disabled.
869  *
870  * Register|BitsName
871  * --------|--------
872  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
873  *
874  * @retval State of bit (1 or 0).
875  */
876 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
877 {
878  return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
879 }
880 
881 /**
882  * @brief Enable Radio sleep mode, and disable Radio module.
883  *
884  * Register|BitsName
885  * --------|--------
886  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
887  *
888  * @retval None
889  */
890 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
891 {
892  GLOBAL_EXCEPTION_DISABLE();
893  SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
894  GLOBAL_EXCEPTION_ENABLE();
895 }
896 
897 /**
898  * @brief Disable Radio sleep mode.
899  * @note Switch Radio from sleep mode into normal active mode.
900  *
901  * Register|BitsName
902  * --------|--------
903  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
904  *
905  * @retval None
906  */
907 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
908 {
909  GLOBAL_EXCEPTION_DISABLE();
910  CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
911  GLOBAL_EXCEPTION_ENABLE();
912 }
913 
914 /**
915  * @brief Check if the Radio sleep mode was enabled or disabled.
916  *
917  * Register|BitsName
918  * --------|--------
919  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
920  *
921  * @retval State of bit (1 or 0).
922  */
923 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
924 {
925  return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
926 }
927 
928 /**
929  * @brief Enable Communication Core Deep Sleep Mode.
930  * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
931  *
932  * Register|BitsName
933  * --------|--------
934  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
935  *
936  * @retval None
937  */
938 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
939 {
940  GLOBAL_EXCEPTION_DISABLE();
941  SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
942  GLOBAL_EXCEPTION_ENABLE();
943 }
944 
945 /**
946  * @brief Disable Communication Core Deep Sleep Mode.
947  * @note Switch Communication Core from sleep mode into normal active mode.
948  *
949  * Register|BitsName
950  * --------|--------
951  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
952  *
953  * @retval None
954  */
955 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
956 {
957  GLOBAL_EXCEPTION_DISABLE();
958  CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
959  GLOBAL_EXCEPTION_ENABLE();
960 }
961 
962 /**
963  * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
964  *
965  * Register|BitsName
966  * --------|--------
967  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
968  *
969  * @retval State of bit (1 or 0).
970  */
971 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
972 {
973  return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
974 }
975 
976 /**
977  * @brief Enable Wake Up Request from Software.
978  * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
979  * when written with a 1. No action happens if it is written with 0.
980  *
981  * Register|BitsName
982  * --------|--------
983  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
984  *
985  * @retval None
986  */
987 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
988 {
989  GLOBAL_EXCEPTION_DISABLE();
990  SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
991  GLOBAL_EXCEPTION_ENABLE();
992 }
993 
994 /**
995  * @brief Check if the Wake Up Request was enabled or disabled.
996  * @note Resets at 0 means request action is performed.
997  *
998  * Register|BitsName
999  * --------|--------
1000  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
1001  *
1002  * @retval State of bit (1 or 0).
1003  */
1004 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1005 {
1006  return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1007 }
1008 
1009 /**
1010  * @brief Enable Communication Core external wakeup.
1011  * @note After this configuration, Communication Core can be woken up by external wake-up
1012  *
1013  * Register|BitsName
1014  * --------|--------
1015  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1016  *
1017  * @retval None
1018  */
1019 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1020 {
1021  GLOBAL_EXCEPTION_DISABLE();
1022  CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1023  GLOBAL_EXCEPTION_ENABLE();
1024 }
1025 
1026 /**
1027  * @brief Disable Communication Core external wakeup.
1028  * @note After this configuration, Communication Core cannot be woken up by external wake-up
1029  *
1030  * Register|BitsName
1031  * --------|--------
1032  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1033  *
1034  * @retval None
1035  */
1036 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1037 {
1038  GLOBAL_EXCEPTION_DISABLE();
1039  SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1040  GLOBAL_EXCEPTION_ENABLE();
1041 }
1042 
1043 /**
1044  * @brief Check if the Communication Core external wakeup was enabled or disabled.
1045  *
1046  * Register|BitsName
1047  * --------|--------
1048  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1049  *
1050  * @retval State of bit (1 or 0).
1051  */
1052 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1053 {
1054  return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1055 }
1056 
1057 /**
1058  * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1059  *
1060  * Register|BitsName
1061  * --------|--------
1062  * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1063  *
1064  * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1065  * @retval None
1066  */
1067 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1068 {
1069  WRITE_REG(AON->PWR_RET28, time);
1070 }
1071 
1072 /**
1073  * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1074  *
1075  * Register|BitsName
1076  * --------|--------
1077  * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1078  *
1079  * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
1080  */
1081 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1082 {
1083  return ((uint32_t)READ_REG(AON->PWR_RET28));
1084 }
1085 
1086 
1087 /**
1088  * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
1089  *
1090  * Register|BitsName
1091  * --------|--------
1092  * COMM_TMR_DEEPSLPSTAT | DEEPSLDUR
1093  *
1094  * @retval Sleep duration
1095  */
1096 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1097 {
1098  return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1099 }
1100 
1101 /**
1102  * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1103  *
1104  * Register|BitsName
1105  * --------|--------
1106  * COMM_TMR_ENBPRESET | TWEXT
1107  * COMM_TMR_ENBPRESET | TWOSC
1108  * COMM_TMR_ENBPRESET | TWRM
1109  *
1110  * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
1111  * oscillator following an external wake–up request (signal wakeup_req).
1112  * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
1113  * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
1114  * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
1115  * @retval None
1116  */
1117 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1118 {
1119  WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1120  (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1121  (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1122 }
1123 
1124 
1125 /**
1126  * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1127  *
1128  * Register|BitsName
1129  * --------|--------
1130  * COMM_TMR_ENBPRESET | TWEXT
1131  * COMM_TMR_ENBPRESET | TWOSC
1132  * COMM_TMR_ENBPRESET | TWRM
1133  *
1134  * @retval COMM_TMR_ENBPRESET Register value
1135  */
1136 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1137 {
1138  return ((uint32_t)READ_REG(AON->PWR_RET29));
1139 }
1140 
1141 /**
1142  * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1143  *
1144  * @retval TWOSC value
1145  */
1146 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1147 {
1148  return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1149 }
1150 
1151 
1152 /** @} */
1153 
1154 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1155  * @{
1156  */
1157 
1158 /**
1159  * @brief Get the External Wake Up Status.
1160  * @note 0 means not waked up and 1 means waked up.
1161  *
1162  * Register|BitsName
1163  * --------|--------
1164  * SLP_EVENT | EXT_WKUP_STATUS
1165  *
1166  * @retval Returned value can be a combination of the following values:
1167  * @arg @ref LL_PWR_EXTWKUP_PIN0
1168  * @arg @ref LL_PWR_EXTWKUP_PIN1
1169  * @arg @ref LL_PWR_EXTWKUP_PIN2
1170  * @arg @ref LL_PWR_EXTWKUP_PIN3
1171  * @arg @ref LL_PWR_EXTWKUP_PIN4
1172  * @arg @ref LL_PWR_EXTWKUP_PIN5
1173  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1174  */
1175 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1176 {
1177  return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1178  (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1179 }
1180 
1181 /**
1182  * @brief Clear the External Wake Up Status.
1183  *
1184  * Register|BitsName
1185  * --------|--------
1186  * SLP_EVENT | EXT_WKUP_STATUS
1187  *
1188  * @param wakeup_pin This parameter can be a combination of the following values:
1189  * @arg @ref LL_PWR_EXTWKUP_PIN0
1190  * @arg @ref LL_PWR_EXTWKUP_PIN1
1191  * @arg @ref LL_PWR_EXTWKUP_PIN2
1192  * @arg @ref LL_PWR_EXTWKUP_PIN3
1193  * @arg @ref LL_PWR_EXTWKUP_PIN4
1194  * @arg @ref LL_PWR_EXTWKUP_PIN5
1195  * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1196  * @retval None
1197  */
1198 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1199 {
1200  GLOBAL_EXCEPTION_DISABLE();
1201  WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1202  GLOBAL_EXCEPTION_ENABLE();
1203 }
1204 
1205 /**
1206  * @brief Clear the Event that triggered the DeepSleep WakeUp.
1207  *
1208  * Register|BitsName
1209  * --------|--------
1210  * SLP_EVENT | SMCOSCEN_EVENT
1211  * SLP_EVENT | TIMER_EVENT
1212  * SLP_EVENT | EXT_WKUP_EVENT
1213  * SLP_EVENT | WATCHDOG_EVENT
1214  *
1215  * @param event This parameter can be a combination of the following values:
1216  * @arg @ref LL_PWR_WKUP_EVENT_BLE
1217  * @arg @ref LL_PWR_WKUP_EVENT_TIMER
1218  * @arg @ref LL_PWR_WKUP_EVENT_EXT
1219  * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
1220  * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
1221  * @arg @ref LL_PWR_WKUP_EVENT_WDT
1222  * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
1223  * @retval None
1224  */
1225 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1226 {
1227  WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1228 }
1229 
1230 /**
1231  * @brief Indicate if the Power State Controller is in busy state.
1232  * @note This is bit set 1 when the PSC_CMD_REQ[0] is set to 1, and will remain 1 until
1233  * the PSC_CMD_OPC has been transferred to the PSC.
1234  *
1235  * Register|BitsName
1236  * --------|--------
1237  * PSC_CMD | MCU_PWR_BUSY
1238  *
1239  * @retval State of bit (1 or 0).
1240  */
1241 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1242 {
1243  return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1244 }
1245 
1246 /**
1247  * @brief Indicate if the Communication Core is in Deep Sleep Mode.
1248  * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
1249  *
1250  * Register|BitsName
1251  * --------|--------
1252  * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT
1253  *
1254  * @retval State of bit (1 or 0).
1255  */
1256 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1257 {
1258  return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1259 }
1260 
1261 /**
1262  * @brief Disable cache function
1263  * @note The cache should be closed before chip go to deepsleep.
1264  *
1265  * Register|BitsName
1266  * --------|--------
1267  * CTRL0 |EN
1268  *
1269  * @retval None
1270  */
1271 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1272 {
1273  SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1274  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
1275 }
1276 
1277 /** @} */
1278 
1279 /** @} */
1280 /** @} */
1281 
1282 #endif /* defined(AON) */
1283 
1284 #ifdef __cplusplus
1285 }
1286 #endif
1287 
1288 #endif /* __GR55xx_LL_PWR_H__ */
1289 
1290 /** @} */
1291 
1292 /** @} */
1293 
1294 /** @} */
ll_pwr_disable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1036
ll_pwr_enable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:486
ll_pwr_get_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
Get which timer value was selected to read.
Definition: gr55xx_ll_pwr.h:809
ll_pwr_enable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1019
ll_pwr_set_dpad_le_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
Definition: gr55xx_ll_pwr.h:536
ll_pwr_disable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
Definition: gr55xx_ll_pwr.h:907
ll_pwr_is_enabled_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1004
ll_pwr_is_enabled_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:770
ll_pwr_set_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
Set the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:408
ll_pwr_is_enabled_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:971
ll_pwr_disable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
Definition: gr55xx_ll_pwr.h:659
ll_pwr_get_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1175
ll_pwr_read_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1136
ll_pwr_get_timer_read_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
Get current timer value based on the selection.
Definition: gr55xx_ll_pwr.h:828
ll_pwr_disable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
Definition: gr55xx_ll_pwr.h:860
ll_pwr_disable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
Definition: gr55xx_ll_pwr.h:613
ll_pwr_set_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:264
LL_PWR_EXTWKUP_PIN_ALL
#define LL_PWR_EXTWKUP_PIN_ALL
WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7.
Definition: gr55xx_ll_pwr.h:155
ll_pwr_read_comm_wakeup_timing_twosc
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1146
ll_pwr_get_comm_sleep_duration
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
Definition: gr55xx_ll_pwr.h:1096
ll_pwr_set_comm_core_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1067
ll_pwr_is_enabled_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:673
ll_pwr_set_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:457
ll_pwr_is_active_flag_psc_cmd_busy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
Indicate if the Power State Controller is in busy state.
Definition: gr55xx_ll_pwr.h:1241
ll_pwr_enable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
Definition: gr55xx_ll_pwr.h:737
ll_pwr_disable_cache_module
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
Definition: gr55xx_ll_pwr.h:1271
ll_pwr_is_enabled_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
Check if the External WakeUp PINx functionality is enabled.
Definition: gr55xx_ll_pwr.h:380
ll_pwr_enable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
Definition: gr55xx_ll_pwr.h:644
ll_pwr_clear_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1198
ll_pwr_set_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
Select which timer value to read.
Definition: gr55xx_ll_pwr.h:789
ll_pwr_disable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:501
LL_PWR_WKUP_EVENT_ALL
#define LL_PWR_WKUP_EVENT_ALL
All event mask
Definition: gr55xx_ll_pwr.h:135
LL_PWR_EXTWKUP_INVERT_LSB
#define LL_PWR_EXTWKUP_INVERT_LSB
External wakeup level invert.
Definition: gr55xx_ll_pwr.h:80
ll_pwr_is_enabled_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:515
ll_pwr_enable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
Definition: gr55xx_ll_pwr.h:598
ll_pwr_is_active_flag_comm_deep_sleep_stat
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1256
ll_pwr_disable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
Definition: gr55xx_ll_pwr.h:753
ll_pwr_clear_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:1225
ll_pwr_disable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
Disable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:356
ll_pwr_get_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:285
ll_pwr_enable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
Definition: gr55xx_ll_pwr.h:688
ll_pwr_set_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1117
ll_pwr_enable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:938
ll_pwr_disable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:955
ll_pwr_enable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
Enable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:332
ll_pwr_is_enabled_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1052
LL_PWR_EXTWKUP_TYPE_LSB
#define LL_PWR_EXTWKUP_TYPE_LSB
External wakeup level type.
Definition: gr55xx_ll_pwr.h:79
ll_pwr_enable_comm_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
Definition: gr55xx_ll_pwr.h:987
ll_pwr_enable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
Definition: gr55xx_ll_pwr.h:890
ll_pwr_get_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:310
ll_pwr_enable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
Definition: gr55xx_ll_pwr.h:842
ll_pwr_get_comm_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1081
ll_pwr_is_enabled_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:627
ll_pwr_is_enabled_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:722
ll_pwr_get_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:471
ll_pwr_get_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
Get the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:440
ll_pwr_is_enabled_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:923
ll_pwr_is_enabled_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:876
ll_pwr_req_excute_psc_command
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
Request to excute the Power State Controller Command.
Definition: gr55xx_ll_pwr.h:575
ll_pwr_disable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
Definition: gr55xx_ll_pwr.h:705