Goodix
GR551x API Reference  V1_6_06_B5676
gr55xx_ll_xqspi.h
Go to the documentation of this file.
1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_xqspi.h
5  * @author BLE SDK Team
6  * @brief Header file containing functions prototypes of XQSPI LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_XQSPI XQSPI
47  * @brief XQSPI LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 #if defined (XQSPI)
63 
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65  * @{
66  */
67 
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70  * @{
71  */
72 
73 /**
74  * @brief XQSPI init structures definition
75  */
76 typedef struct _ll_xqspi_init_t
77 {
78  uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
79  This parameter can be a value of @ref XQSPI_LL_EC_MODE.*/
80 
81  uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
82  This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
83 
84  This feature can be modified afterwards using unitary function @ref ll_xqspi_enable_cache().*/
85 
86  uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
87  This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
88 
89  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cmd().*/
90 
91  uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
92  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
93 
94  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_datasize().*/
95 
96  uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
97  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
98 
99  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_data_order().*/
100 
101  uint32_t clock_polarity; /**< Specifies the serial clock steady state.
102  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_POLARITY in XIP mode or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
103 
104  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol().*/
105 
106  uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
107  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_PHASE in XIP mode or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
108 
109  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha().*/
110 
111  uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and receive SCK clock.
112  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
113 
114  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_speed().*/
115 
117 
118 /** @} */
119 
120 /** @} */
121 
122 /**
123  * @defgroup XQSPI_LL_MACRO Defines
124  * @{
125  */
126 
127 /* Exported constants --------------------------------------------------------*/
128 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
129  * @{
130  */
131 
132 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
133  * @{
134  */
135 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
136 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
137 /** @} */
138 
139 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
140  * @{
141  */
142 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
143 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
144 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
145 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
146 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
147 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
148 /** @} */
149 
150 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
151  * @{
152  */
153 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
154 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
155 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
156 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
157 /** @} */
158 
159 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
160  * @{
161  */
162 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
163 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
164 /** @} */
165 
166 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
167  * @{
168  */
169 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
170 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
171 /** @} */
172 
173 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
174  * @{
175  */
176 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
177 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
178 /** @} */
179 
180 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
181  * @{
182  */
183 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
184 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
185 /** @} */
186 
187 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
188  * @{
189  */
190 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
191 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
192 /** @} */
193 
194 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
195  * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
196  * @{
197  */
198 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
199 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
200 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
201 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
202 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
203 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
204 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
205 /** @} */
206 
207 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
208  * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
209  * @{
210  */
211 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
212 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
213 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt enable */
214 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt enable */
215 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
216 
217 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
218 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
219 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
220 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt flag */
221 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
222 /** @} */
223 
224 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
225  * @{
226  */
227 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
228 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
229 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
230 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
231 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL /**< FIFO full depth */
232 /** @} */
233 
234 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
235  * @{
236  */
237 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
238 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format for transfer */
239 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format for transfer */
240 /** @} */
241 
242 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
243  * @{
244  */
245 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
246 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
247 /** @} */
248 
249 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
250  * @{
251  */
252 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI transfer: 4 bits */
253 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 8 bits */
254 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 12 bits */
255 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 16 bits */
256 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 20 bits */
257 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 24 bits */
258 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 28 bits */
259 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 32 bits */
260 /** @} */
261 
262 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
263  * @{
264  */
265 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
266 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
267 /** @} */
268 
269 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
270  * @{
271  */
272 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
273 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
274 /** @} */
275 
276 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
277  * @{
278  */
279 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
280 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
281 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
282 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
283 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
284 /** @} */
285 
286 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
287  * @{
288  */
289 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
290 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
291 /** @} */
292 
293 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
294  * @{
295  */
296 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
297 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
298 /** @} */
299 
300 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
301  * @{
302  */
303 
304 /**
305  * @brief LL XQSPI InitStrcut default configuartion
306  */
307 #define LL_XQSPI_DEFAULT_CONFIG \
308 { \
309  .mode = LL_XQSPI_MODE_QSPI, \
310  .cache_mode = LL_XQSPI_CACHE_EN, \
311  .read_cmd = LL_XQSPI_XIP_CMD_READ, \
312  .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
313  .data_order = LL_XQSPI_QSPI_MSB, \
314  .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
315  .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
316  .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
317 }
318 /** @} */
319 
320 /** @} */
321 
322 /* Exported macro ------------------------------------------------------------*/
323 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
324  * @{
325  */
326 
327 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
328  * @{
329  */
330 
331 /**
332  * @brief Write a value in XQSPI register
333  * @param __instance__ XQSPI instance
334  * @param __REG__ Register to be written
335  * @param __VALUE__ Value to be written in the register
336  * @retval None
337  */
338 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
339 
340 /**
341  * @brief Read a value in XQSPI register
342  * @param __instance__ XQSPI instance
343  * @param __REG__ Register to be read
344  * @retval Register value
345  */
346 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
347 
348 /** @} */
349 
350 /** @} */
351 
352 /** @} */
353 
354 /* Exported functions --------------------------------------------------------*/
355 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
356  * @{
357  */
358 
359 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
360  * @{
361  */
362 
363 /**
364  * @brief Enable cache function
365  * @note This bit should not be changed when XIP is ongoing.
366  *
367  * Register|BitsName
368  * --------|--------
369  * CTRL0 |EN
370  *
371  * @param XQSPIx XQSPI instance
372  * @retval None
373  */
374 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
375 {
376  CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
377  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
378 }
379 
380 /**
381  * @brief Disable cache function
382  * @note This bit should not be changed when XIP is ongoing.
383  *
384  * Register|BitsName
385  * --------|--------
386  * CTRL0 |EN
387  *
388  * @param XQSPIx XQSPI instance
389  * @retval None
390  */
391 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
392 {
393  SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
394  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
395 }
396 
397 /**
398  * @brief Check if cache function is enabled
399  *
400  * Register|BitsName
401  * --------|--------
402  * CTRL0 |EN
403  *
404  * @param XQSPIx XQSPI instance
405  * @retval State of bit (1 or 0).
406  */
407 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
408 {
409  return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
410 }
411 
412 /**
413  * @brief Enable tag memory flush
414  * @note This bit should not be changed when XIP is ongoing.
415  *
416  * Register|BitsName
417  * --------|--------
418  * CTRL0 |TAG
419  *
420  * @param XQSPIx XQSPI instance
421  * @retval None
422  */
423 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
424 {
425  SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
426 }
427 
428 /**
429  * @brief Disable tag memory flush
430  * @note This bit should not be changed when XIP is ongoing.
431  *
432  * Register|BitsName
433  * --------|--------
434  * CTRL0 |TAG
435  *
436  * @param XQSPIx XQSPI instance
437  * @retval None
438  */
439 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
440 {
441  CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
442 }
443 
444 /**
445  * @brief Check if tag memory flush is enabled
446  *
447  * Register|BitsName
448  * --------|--------
449  * CTRL0 |TAG
450  *
451  * @param XQSPIx XQSPI instance
452  * @retval State of bit (1 or 0).
453  */
454 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
455 {
456  return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
457 }
458 
459 /**
460  * @brief Set FIFO mode
461  * @note This bit should not be changed when XIP is ongoing.
462  *
463  * Register|BitsName
464  * --------|--------
465  * CTRL0 |FIFO
466  *
467  * @param XQSPIx XQSPI instance
468  * @param mode This parameter can be one of the following values:
469  * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
470  * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
471  * @retval None
472  */
473 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
474 {
475  MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
476 }
477 
478 /**
479  * @brief Get FIFO mode
480  * @note This bit should not be changed when XIP is ongoing.
481  *
482  * Register|BitsName
483  * --------|--------
484  * CTRL0 |FIFO
485  *
486  * @param XQSPIx XQSPI instance
487  * @retval Returned Value can be one of the following values:
488  * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
489  * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
490  */
491 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
492 {
493  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
494 }
495 
496 /**
497  * @brief Set HIT/MISS mode
498  * @note This bit should not be changed when XIP is ongoing.
499  *
500  * Register|BitsName
501  * --------|--------
502  * CTRL0 |HITMISS
503  *
504  * @param XQSPIx XQSPI instance
505  * @param mode This parameter can be one of the following values:
506  * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
507  * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
508  * @retval None
509  */
510 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
511 {
512  MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
513 }
514 
515 /**
516  * @brief Get HIT/MISS mode
517  * @note This bit should not be changed when XIP is ongoing.
518  *
519  * Register|BitsName
520  * --------|--------
521  * CTRL0 |HITMISS
522  *
523  * @param XQSPIx XQSPI instance
524  * @retval Returned Value can be one of the following values:
525  * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
526  * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
527  */
528 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
529 {
530  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
531 }
532 
533 /**
534  * @brief Set debugbus configurations signals
535  * @note These bits should not be changed when XIP is ongoing.
536  *
537  * Register|BitsName
538  * --------|--------
539  * CTRL1 |DBGBUS_SEL
540  *
541  * @param XQSPIx XQSPI instance
542  * @param sel This parameter can between: 0 ~ 0x7
543  * @retval None
544  */
545 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
546 {
547  MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
548 }
549 
550 /**
551  * @brief Get debugbus configurations signals
552  *
553  * Register|BitsName
554  * --------|--------
555  * CTRL1 |DBGBUS_SEL
556  *
557  * @param XQSPIx XQSPI instance
558  * @retval Returned Value can between: 0 ~ 0x7
559  */
560 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
561 {
562  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
563 }
564 
565 /**
566  * @brief Enable debug bus mux
567  * @note This bit should not be changed when XIP is ongoing.
568  *
569  * Register|BitsName
570  * --------|--------
571  * CTRL1 |DBGMUX_EN
572  *
573  * @param XQSPIx XQSPI instance
574  * @retval None
575  */
576 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
577 {
578  CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
579 }
580 
581 /**
582  * @brief Disable debug bus mux
583  * @note This bit should not be changed when XIP is ongoing.
584  *
585  * Register|BitsName
586  * --------|--------
587  * CTRL1 |DBGMUX_EN
588  *
589  * @param XQSPIx XQSPI instance
590  * @retval None
591  */
592 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
593 {
594  SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
595 }
596 
597 /**
598  * @brief Check if debug bus mux is enabled
599  *
600  * Register|BitsName
601  * --------|--------
602  * CTRL1 |DBGMUX_EN
603  *
604  * @param XQSPIx XQSPI instance
605  * @retval State of bit (1 or 0).
606  */
607 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
608 {
609  return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
610 }
611 
612 /**
613  * @brief Get hit counter
614  * @note This bit only be read.
615  *
616  * Register|BitsName
617  * --------|--------
618  * HIT_COUNT|HITCOUNT
619  *
620  * @param XQSPIx XQSPI instance
621  * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
622  */
623 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
624 {
625  return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
626 }
627 
628 /**
629  * @brief Get miss counter
630  * @note This bit only be read.
631  *
632  * Register|BitsName
633  * --------|--------
634  * MISS_COUNT|MISSCOUNT
635  *
636  * @param XQSPIx XQSPI instance
637  * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
638  */
639 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
640 {
641  return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
642 }
643 
644 /**
645  * @brief Get cache status
646  * @note This bit only be read.
647  *
648  * Register|BitsName
649  * --------|--------
650  * STAT |STAT
651  *
652  * @param XQSPIx XQSPI instance
653  * @retval Returned Value can between: 0 ~ 1
654  */
655 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
656 {
657  return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
658 }
659 
660 /** @} */
661 
662 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
663  * @{
664  */
665 
666 /**
667  * @brief Set read command
668  * @note These bits should not be changed when XIP is ongoing.
669  *
670  * Register|BitsName
671  * --------|--------
672  * CTRL0 |CFG_CMD
673  *
674  * @param XQSPIx XQSPI instance
675  * @param cmd This parameter can be one of the following values:
676  * @arg @ref LL_XQSPI_XIP_CMD_READ
677  * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
678  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
679  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
680  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
681  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
682  * @retval None
683  */
684 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
685 {
686  MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
687 }
688 
689 /**
690  * @brief Get read command
691  *
692  * Register|BitsName
693  * --------|--------
694  * CTRL0 |CFG_CMD
695  *
696  * @param XQSPIx XQSPI instance
697  * @retval Returned Value can be one of the following values:
698  * @arg @ref LL_XQSPI_XIP_CMD_READ
699  * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
700  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
701  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
702  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
703  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
704  */
705 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
706 {
707  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
708 }
709 
710 /**
711  * @brief Enable high performance mode
712  * @note This bit should not be changed when XIP is ongoing.
713  *
714  * Register|BitsName
715  * --------|--------
716  * CTRL1 |CFG_HPEN
717  *
718  * @param XQSPIx XQSPI instance
719  * @retval None
720  */
721 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
722 {
723  SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
724 }
725 
726 /**
727  * @brief Disable high performance mode
728  * @note This bit should not be changed when XIP is ongoing.
729  *
730  * Register|BitsName
731  * --------|--------
732  * CTRL1 |CFG_HPEN
733  *
734  * @param XQSPIx XQSPI instance
735  * @retval None
736  */
737 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
738 {
739  CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
740 }
741 
742 /**
743  * @brief Check if high performance mode is enabled
744  *
745  * Register|BitsName
746  * --------|--------
747  * CTRL1 |CFG_HPEN
748  *
749  * @param XQSPIx XQSPI instance
750  * @retval State of bit (1 or 0).
751  */
752 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
753 {
754  return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
755 }
756 
757 /**
758  * @brief Set slave select
759  * @note These bits should not be changed when XIP is ongoing.
760  *
761  * Register|BitsName
762  * --------|--------
763  * CTRL1 |CFG_SS
764  *
765  * @param XQSPIx XQSPI instance
766  * @param ss This parameter can be one or more of the following values:
767  * @arg @ref LL_XQSPI_XIP_SS0
768  * @arg @ref LL_XQSPI_XIP_SS1
769  * @arg @ref LL_XQSPI_XIP_SS2
770  * @arg @ref LL_XQSPI_XIP_SS3
771  * @retval None
772  */
773 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
774 {
775  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
776 }
777 
778 /**
779  * @brief Get slave select
780  *
781  * Register|BitsName
782  * --------|--------
783  * CTRL1 |CFG_SS
784  *
785  * @param XQSPIx XQSPI instance
786  * @retval Returned Value can be one of the following values:
787  * @arg @ref LL_XQSPI_XIP_SS0
788  * @arg @ref LL_XQSPI_XIP_SS1
789  * @arg @ref LL_XQSPI_XIP_SS2
790  * @arg @ref LL_XQSPI_XIP_SS3
791  */
792 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
793 {
794  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
795 }
796 
797 /**
798  * @brief Set clock phase
799  * @note This bit should not be changed when XIP is ongoing.
800  *
801  * Register|BitsName
802  * --------|--------
803  * CTRL1 |CFG_CPHA
804  *
805  * @param XQSPIx XQSPI instance
806  * @param cpha This parameter can be one or more of the following values:
807  * @arg @ref LL_XQSPI_SCPHA_1EDGE
808  * @arg @ref LL_XQSPI_SCPHA_2EDGE
809  * @retval None
810  */
811 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
812 {
813  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
814 }
815 
816 /**
817  * @brief Get clock phase
818  *
819  * Register|BitsName
820  * --------|--------
821  * CTRL1 |CFG_CPHA
822  *
823  * @param XQSPIx XQSPI instance
824  * @retval Returned Value can be one of the following values:
825  * @arg @ref LL_XQSPI_SCPHA_1EDGE
826  * @arg @ref LL_XQSPI_SCPHA_2EDGE
827  */
828 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
829 {
830  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
831 }
832 
833 /**
834  * @brief Set clock polarity
835  * @note This bit should not be changed when XIP is ongoing.
836  *
837  * Register|BitsName
838  * --------|--------
839  * CTRL1 |CFG_CPOL
840  *
841  * @param XQSPIx XQSPI instance
842  * @param cpol This parameter can be one or more of the following values:
843  * @arg @ref LL_XQSPI_SCPOL_LOW
844  * @arg @ref LL_XQSPI_SCPOL_HIGH
845  * @retval None
846  */
847 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
848 {
849  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
850 }
851 
852 /**
853  * @brief Get clock polarity
854  *
855  * Register|BitsName
856  * --------|--------
857  * CTRL1 |CFG_CPOL
858  *
859  * @param XQSPIx XQSPI instance
860  * @retval Returned Value can be one of the following values:
861  * @arg @ref LL_XQSPI_SCPOL_LOW
862  * @arg @ref LL_XQSPI_SCPOL_HIGH
863  */
864 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
865 {
866  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
867 }
868 
869 /**
870  * @brief Set address bytes in command
871  * @note This bit should not be changed when XIP is ongoing.
872  *
873  * Register|BitsName
874  * --------|--------
875  * CTRL1 |CFG_ADDR4
876  *
877  * @param XQSPIx XQSPI instance
878  * @param size This parameter can be one or more of the following values:
879  * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
880  * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
881  * @retval None
882  */
883 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
884 {
885  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
886 }
887 
888 /**
889  * @brief Get address bytes in command
890  *
891  * Register|BitsName
892  * --------|--------
893  * CTRL1 |CFG_ADDR4
894  *
895  * @param XQSPIx XQSPI instance
896  * @retval Returned Value can be one of the following values:
897  * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
898  * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
899  */
900 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
901 {
902  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
903 }
904 
905 /**
906  * @brief Set endian in reading data
907  * @note This bit should not be changed when XIP is ongoing.
908  *
909  * Register|BitsName
910  * --------|--------
911  * CTRL1 |CFG_LE32
912  *
913  * @param XQSPIx XQSPI instance
914  * @param endian This parameter can be one or more of the following values:
915  * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
916  * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
917  * @retval None
918  */
919 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
920 {
921  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
922 }
923 
924 /**
925  * @brief Get endian in reading data
926  *
927  * Register|BitsName
928  * --------|--------
929  * CTRL1 |CFG_LE32
930  *
931  * @param XQSPIx XQSPI instance
932  * @retval Returned Value can be one of the following values:
933  * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
934  * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
935  */
936 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
937 {
938  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
939 }
940 
941 /**
942  * @brief Set high performance command
943  * @note These bits should not be changed when XIP is ongoing.
944  *
945  * Register|BitsName
946  * --------|--------
947  * CTRL2 |CFG_HPMODE
948  *
949  * @param XQSPIx XQSPI instance
950  * @param cmd This value is specified by different QSPI FLASH memory vendor to enter into its status register
951  * to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF.
952  * @retval None
953  */
954 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
955 {
956  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
957 }
958 
959 /**
960  * @brief Get high performance command
961  *
962  * Register|BitsName
963  * --------|--------
964  * CTRL2 |CFG_HPMODE
965  *
966  * @param XQSPIx XQSPI instance
967  * @retval Returned Value can between: 0 ~ 0xFF.
968  */
969 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
970 {
971  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
972 }
973 
974 /**
975  * @brief Set dummy cycles in command
976  * @note These bits should not be changed when XIP is ongoing.
977  * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
978  * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
979  * - Fast Read Dual Out: dummycycles = 8 * cycles
980  * - Fast Read Quad Out: dummycycles = 8 * cycles
981  *
982  * Register|BitsName
983  * --------|--------
984  * CTRL2 |CFG_DUMMYCYCLES
985  *
986  * @param XQSPIx XQSPI instance
987  * @param cycles This parameter can between: 0 ~ 0xF.
988  * @retval None
989  */
990 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
991 {
992  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
993 }
994 
995 /**
996  * @brief Get dummy cycles in command
997  * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
998  * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
999  * - Fast Read Dual Out: dummycycles = 8 * cycles
1000  * - Fast Read Quad Out: dummycycles = 8 * cycles
1001  *
1002  * Register|BitsName
1003  * --------|--------
1004  * CTRL2 |CFG_DUMMYCYCLES
1005  *
1006  * @param XQSPIx XQSPI instance
1007  * @retval Returned Value can between: 0 ~ 0xF.
1008  */
1009 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1010 {
1011  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES));
1012 }
1013 
1014 /**
1015  * @brief Set dummy cycles in high performance end
1016  * @note These bits should not be changed when XIP is ongoing.
1017  *
1018  * Register|BitsName
1019  * --------|--------
1020  * CTRL2 |CFG_ENDDUMMY
1021  *
1022  * @param XQSPIx XQSPI instance
1023  * @param cycles This parameter can between: 0 ~ 3.
1024  * @retval None
1025  */
1026 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1027 {
1028  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1029 }
1030 
1031 /**
1032  * @brief Get dummy cycles in high performance end
1033  *
1034  * Register|BitsName
1035  * --------|--------
1036  * CTRL2 |CFG_ENDDUMMY
1037  *
1038  * @param XQSPIx XQSPI instance
1039  * @retval Returned Value can between: 0 ~ 3.
1040  */
1041 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1042 {
1043  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1044 }
1045 
1046 /**
1047  * @brief Enable XIP mode
1048  *
1049  * Register|BitsName
1050  * --------|--------
1051  * CTRL3 |EN_REQ
1052  *
1053  * @param XQSPIx XQSPI instance
1054  * @retval None
1055  */
1056 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1057 {
1058  SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1059 }
1060 
1061 /**
1062  * @brief Disable XIP mode
1063  *
1064  * Register|BitsName
1065  * --------|--------
1066  * CTRL3 |EN_REQ
1067  *
1068  * @param XQSPIx XQSPI instance
1069  * @retval None
1070  */
1071 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1072 {
1073  CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1074 }
1075 
1076 /**
1077  * @brief Check if XIP mode is enabled
1078  * @note This bit should not be changed when XIP is ongoing.
1079  *
1080  * Register|BitsName
1081  * --------|--------
1082  * CTRL3 |EN_REQ
1083  *
1084  * @param XQSPIx XQSPI instance
1085  * @retval State of bit (1 or 0).
1086  */
1087 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1088 {
1089  return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1090 }
1091 
1092 /**
1093  * @brief Get XIP status
1094  * @note This bit is read-only.
1095  *
1096  * Register|BitsName
1097  * --------|--------
1098  * STAT |EN_OUT
1099  *
1100  * @param XQSPIx XQSPI instance
1101  * @retval Returned Value can between: 0 ~ 1
1102  */
1103 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1104 {
1105  return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1106 }
1107 
1108 /**
1109  * @brief Check if XIP interrupt is enabled
1110  * @note This bit is read-only.
1111  *
1112  * Register|BitsName
1113  * --------|--------
1114  * INTEN |INT_EN
1115  *
1116  * @param XQSPIx XQSPI instance
1117  * @retval Returned Value can between: 0 ~ 1
1118  */
1119 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1120 {
1121  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1122 }
1123 
1124 /**
1125  * @brief Get XIP interrupt flag
1126  * @note This bit is read-only.
1127  *
1128  * Register|BitsName
1129  * --------|--------
1130  * INTSTAT |INT_STAT
1131  *
1132  * @param XQSPIx XQSPI instance
1133  * @retval Returned Value can between: 0 ~ 1
1134  */
1135 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1136 {
1137  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1138 }
1139 
1140 /**
1141  * @brief Get XIP interrupt request
1142  * @note This bit is read-only.
1143  *
1144  * Register|BitsName
1145  * --------|--------
1146  * INTREQ |INT_REQ
1147  *
1148  * @param XQSPIx XQSPI instance
1149  * @retval Returned Value can between: 0 ~ 1
1150  */
1151 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1152 {
1153  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1154 }
1155 
1156 /**
1157  * @brief Set XIP interrupt enable
1158  * @note This bit is write-only.
1159  *
1160  * Register|BitsName
1161  * --------|--------
1162  * INTSET |INT_SET
1163  *
1164  * @param XQSPIx XQSPI instance
1165  * @retval None
1166  */
1167 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1168 {
1169  SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1170 }
1171 
1172 /**
1173  * @brief Set XIP interrupt disable
1174  * @note This bit is write-only.
1175  *
1176  * Register|BitsName
1177  * --------|--------
1178  * INTCLR |INT_CLR
1179  *
1180  * @param XQSPIx XQSPI instance
1181  * @retval None
1182  */
1183 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1184 {
1185  SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1186 }
1187 
1188 /** @} */
1189 
1190 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1191  * @{
1192  */
1193 
1194 /**
1195  * @brief Write 8-bit in the data register
1196  *
1197  * Register|BitsName
1198  * --------|--------
1199  * TX_DATA | DATA
1200  *
1201  * @param XQSPIx XQSPI instance
1202  * @param tx_data This parameter can between: 0x00 ~ 0xFF
1203  * @retval None
1204  */
1205 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1206 {
1207  *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1208 }
1209 
1210 /**
1211  * @brief Write 16-bit in the data register
1212  *
1213  * Register|BitsName
1214  * --------|--------
1215  * TX_DATA | DATA
1216  *
1217  * @param XQSPIx XQSPI instance
1218  * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1219  * @retval None
1220  */
1221 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1222 {
1223  *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1224 }
1225 
1226 /**
1227  * @brief Write 32-bit in the data register
1228  *
1229  * Register|BitsName
1230  * --------|--------
1231  * TX_DATA | DATA
1232  *
1233  * @param XQSPIx XQSPI instance
1234  * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1235  * @retval None
1236  */
1237 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1238 {
1239  *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1240 }
1241 
1242 /**
1243  * @brief Read 8 bits in the data register
1244  *
1245  * Register|BitsName
1246  * --------|--------
1247  * RX_DATA | DATA
1248  *
1249  * @param XQSPIx XQSPI instance
1250  * @retval Returned Value between: 0x00 ~ 0xFF
1251  */
1252 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1253 {
1254  return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1255 }
1256 
1257 /**
1258  * @brief Read 16 bits in the data register
1259  *
1260  * Register|BitsName
1261  * --------|--------
1262  * RX_DATA | DATA
1263  *
1264  * @param XQSPIx XQSPI instance
1265  * @retval Returned Value between: 0x00 ~ 0xFFFF
1266  */
1267 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1268 {
1269  return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1270 }
1271 
1272 /**
1273  * @brief Read 32 bits in the data register
1274  *
1275  * Register|BitsName
1276  * --------|--------
1277  * RX_DATA | DATA
1278  *
1279  * @param XQSPIx XQSPI instance
1280  * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1281  */
1282 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1283 {
1284  return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1285 }
1286 
1287 /**
1288  * @brief Set TX FIFO threshold level
1289  * @note FIFO maximum depth is 16 units.
1290  *
1291  * Register|BitsName
1292  * --------|--------
1293  * CTRL |TXWMARK
1294  *
1295  * @param XQSPIx XQSPI instance
1296  * @param threshold This parameter can be one of the following values:
1297  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1298  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1299  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1300  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1301  * @retval None
1302  */
1303 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1304 {
1305  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1306 }
1307 
1308 /**
1309  * @brief Get TX FIFO threshold level
1310  * @note FIFO maximum depth is 16 units.
1311  *
1312  * Register|BitsName
1313  * --------|--------
1314  * CTRL |TXWMARK
1315  *
1316  * @param XQSPIx XQSPI instance
1317  * @retval Returned Value can be one of the following values:
1318  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1319  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1320  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1321  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1322  */
1323 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1324 {
1325  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1326 }
1327 
1328 /**
1329  * @brief Set RX FIFO threshold level
1330  * @note FIFO maximum depth is 16 units.
1331  *
1332  * Register|BitsName
1333  * --------|--------
1334  * CTRL |RXWMARK
1335  *
1336  * @param XQSPIx XQSPI instance
1337  * @param threshold This parameter can be one of the following values:
1338  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1339  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1340  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1341  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1342  * @retval None
1343  */
1344 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1345 {
1346  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1347 }
1348 
1349 /**
1350  * @brief Get RX FIFO threshold level
1351  * @note FIFO maximum depth is 16 units.
1352  *
1353  * Register|BitsName
1354  * --------|--------
1355  * CTRL |RXWMARK
1356  *
1357  * @param XQSPIx XQSPI instance
1358  * @retval Returned Value can be one of the following values:
1359  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1360  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1361  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1362  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1363  */
1364 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1365 {
1366  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1367 }
1368 
1369 /**
1370  * @brief Enable dummy cycles
1371  *
1372  * Register|BitsName
1373  * --------|--------
1374  * CTRL |MWAITEN
1375  *
1376  * @param XQSPIx XQSPI instance
1377  * @retval None
1378  */
1379 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1380 {
1381  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1382 }
1383 
1384 /**
1385  * @brief Disable dummy cycles
1386  *
1387  * Register|BitsName
1388  * --------|--------
1389  * CTRL |MWAITEN
1390  *
1391  * @param XQSPIx XQSPI instance
1392  * @retval None
1393  */
1394 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1395 {
1396  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1397 }
1398 
1399 /**
1400  * @brief Check if dummy cycles is enabled
1401  *
1402  * Register|BitsName
1403  * --------|--------
1404  * CTRL |MWAITEN
1405  *
1406  * @param XQSPIx XQSPI instance
1407  * @retval State of bit (1 or 0).
1408  */
1409 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1410 {
1411  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1412 }
1413 
1414 /**
1415  * @brief Enable DMA mode
1416  *
1417  * Register|BitsName
1418  * --------|--------
1419  * CTRL |DMA
1420  *
1421  * @param XQSPIx XQSPI instance
1422  * @retval None
1423  */
1424 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1425 {
1426  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1427 }
1428 
1429 /**
1430  * @brief Disable DMA mode
1431  *
1432  * Register|BitsName
1433  * --------|--------
1434  * CTRL |DMA
1435  *
1436  * @param XQSPIx XQSPI instance
1437  * @retval None
1438  */
1439 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1440 {
1441  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1442 }
1443 
1444 /**
1445  * @brief Check if DMA mode is enabled
1446  *
1447  * Register|BitsName
1448  * --------|--------
1449  * CTRL |DMA
1450  *
1451  * @param XQSPIx XQSPI instance
1452  * @retval State of bit (1 or 0).
1453  */
1454 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1455 {
1456  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1457 }
1458 
1459 /**
1460  * @brief Set clock polarity
1461  * @note This bit should not be changed when communication is ongoing.
1462  *
1463  * Register|BitsName
1464  * --------|--------
1465  * CTRL |CPOL
1466  *
1467  * @param XQSPIx XQSPI instance
1468  * @param cpol This parameter can be one of the following values:
1469  * @arg @ref LL_XQSPI_SCPOL_LOW
1470  * @arg @ref LL_XQSPI_SCPOL_HIGH
1471  * @retval None
1472  */
1473 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1474 {
1475  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1476 }
1477 
1478 /**
1479  * @brief Get clock polarity
1480  *
1481  * Register|BitsName
1482  * --------|--------
1483  * CTRL |CPOL
1484  *
1485  * @param XQSPIx XQSPI instance
1486  * @retval Returned Value can be one of the following values:
1487  * @arg @ref LL_XQSPI_SCPOL_LOW
1488  * @arg @ref LL_XQSPI_SCPOL_HIGH
1489  */
1490 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1491 {
1492  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1493 }
1494 
1495 /**
1496  * @brief Set clock phase
1497  * @note This bit should not be changed when communication is ongoing.
1498  *
1499  * Register|BitsName
1500  * --------|--------
1501  * CTRL |CPHA
1502  *
1503  * @param XQSPIx XQSPI instance
1504  * @param cpha This parameter can be one of the following values:
1505  * @arg @ref LL_XQSPI_SCPHA_1EDGE
1506  * @arg @ref LL_XQSPI_SCPHA_2EDGE
1507  * @retval None
1508  */
1509 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1510 {
1511  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1512 }
1513 
1514 /**
1515  * @brief Get clock phase
1516  *
1517  * Register|BitsName
1518  * --------|--------
1519  * CTRL |CPHA
1520  *
1521  * @param XQSPIx XQSPI instance
1522  * @retval Returned Value can be one of the following values:
1523  * @arg @ref LL_XQSPI_SCPHA_1EDGE
1524  * @arg @ref LL_XQSPI_SCPHA_2EDGE
1525  */
1526 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1527 {
1528  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1529 }
1530 
1531 /**
1532  * @brief Set serial data order
1533  *
1534  * Register|BitsName
1535  * --------|--------
1536  * CTRL |MSB1ST
1537  *
1538  * @param XQSPIx XQSPI instance
1539  * @param order This parameter can be one of the following values:
1540  * @arg @ref LL_XQSPI_QSPI_LSB
1541  * @arg @ref LL_XQSPI_QSPI_MSB
1542  * @retval None
1543  */
1544 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1545 {
1546  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1547 }
1548 
1549 /**
1550  * @brief Get serial data order
1551  *
1552  * Register|BitsName
1553  * --------|--------
1554  * CTRL |MSB1ST
1555  *
1556  * @param XQSPIx XQSPI instance
1557  * @retval Returned Value can be one of the following values:
1558  * @arg @ref LL_XQSPI_QSPI_LSB
1559  * @arg @ref LL_XQSPI_QSPI_MSB
1560  */
1561 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1562 {
1563  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1564 }
1565 
1566 /**
1567  * @brief Enable continuous transfer mode
1568  *
1569  * Register|BitsName
1570  * --------|--------
1571  * CTRL |CONTXFER
1572  *
1573  * @param XQSPIx XQSPI instance
1574  * @retval None
1575  */
1576 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1577 {
1578  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1579 }
1580 
1581 /**
1582  * @brief Disable continuous transfer mode
1583  *
1584  * Register|BitsName
1585  * --------|--------
1586  * CTRL |CONTXFER
1587  *
1588  * @param XQSPIx XQSPI instance
1589  * @retval None
1590  */
1591 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1592 {
1593  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1594 }
1595 
1596 /**
1597  * @brief Check if continuous transfer mode is enabled
1598  *
1599  * Register|BitsName
1600  * --------|--------
1601  * CTRL |CONTXFER
1602  *
1603  * @param XQSPIx XQSPI instance
1604  * @retval State of bit (1 or 0).
1605  */
1606 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1607 {
1608  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1609 }
1610 
1611 /**
1612  * @brief Enable continuous transfer extend mode
1613  *
1614  * Register|BitsName
1615  * --------|--------
1616  * AUX_CTRL|CONTXFERX
1617  *
1618  * @param XQSPIx XQSPI instance
1619  * @retval None
1620  */
1621 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1622 {
1623  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1624 }
1625 
1626 /**
1627  * @brief Disable continuous transfer extend mode
1628  *
1629  * Register|BitsName
1630  * --------|--------
1631  * AUX_CTRL|CONTXFERX
1632  *
1633  * @param XQSPIx XQSPI instance
1634  * @retval None
1635  */
1636 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1637 {
1638  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1639 }
1640 
1641 /**
1642  * @brief Check if continuous transfer extend mode is enabled
1643  *
1644  * Register|BitsName
1645  * --------|--------
1646  * AUX_CTRL|CONTXFERX
1647  *
1648  * @param XQSPIx XQSPI instance
1649  * @retval State of bit (1 or 0).
1650  */
1651 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1652 {
1653  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1654 }
1655 
1656 /**
1657  * @brief Set data size
1658  * @note These bits should not be changed when communication is ongoing.
1659  *
1660  * Register|BitsName
1661  * --------|--------
1662  * AUX_CTRL|BITSIZE
1663  *
1664  * @param XQSPIx XQSPI instance
1665  * @param szie This parameter can be one of the following values:
1666  * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1667  * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1668  * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1669  * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1670  * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1671  * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1672  * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1673  * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1674  * @retval None
1675  */
1676 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1677 {
1678  MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1679 }
1680 
1681 /**
1682  * @brief Get data size
1683  *
1684  * Register|BitsName
1685  * --------|--------
1686  * AUX_CTRL|BITSIZE
1687  *
1688  * @param XQSPIx XQSPI instance
1689  * @retval Returned Value can be one of the following values:
1690  * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1691  * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1692  * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1693  * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1694  * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1695  * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1696  * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1697  * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1698  */
1699 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1700 {
1701  return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1702 }
1703 
1704 /**
1705  * @brief Enable inhibt data input to RX FIFO
1706  *
1707  * Register|BitsName
1708  * --------|--------
1709  * AUX_CTRL|INHIBITDIN
1710  *
1711  * @param XQSPIx XQSPI instance
1712  * @retval None
1713  */
1714 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1715 {
1716  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1717 }
1718 
1719 /**
1720  * @brief Disable inhibt data input to RX FIFO
1721  *
1722  * Register|BitsName
1723  * --------|--------
1724  * AUX_CTRL|INHIBITDIN
1725  *
1726  * @param XQSPIx XQSPI instance
1727  * @retval None
1728  */
1729 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1730 {
1731  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1732 }
1733 
1734 /**
1735  * @brief Check if inhibt data input to RX FIFO is enabled
1736  *
1737  * Register|BitsName
1738  * --------|--------
1739  * AUX_CTRL|INHIBITDIN
1740  *
1741  * @param XQSPIx XQSPI instance
1742  * @retval State of bit (1 or 0).
1743  */
1744 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1745 {
1746  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1747 }
1748 
1749 /**
1750  * @brief Enable inhibt data output to TX FIFO
1751  *
1752  * Register|BitsName
1753  * --------|--------
1754  * AUX_CTRL|INHIBITDOUT
1755  *
1756  * @param XQSPIx XQSPI instance
1757  * @retval None
1758  */
1759 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1760 {
1761  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1762 }
1763 
1764 /**
1765  * @brief Disable inhibt data output to TX FIFO
1766  *
1767  * Register|BitsName
1768  * --------|--------
1769  * AUX_CTRL|INHIBITDOUT
1770  *
1771  * @param XQSPIx XQSPI instance
1772  * @retval None
1773  */
1774 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1775 {
1776  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1777 }
1778 
1779 /**
1780  * @brief Check if inhibt data input to TX FIFO is enabled
1781  *
1782  * Register|BitsName
1783  * --------|--------
1784  * AUX_CTRL|INHIBITDOUT
1785  *
1786  * @param XQSPIx XQSPI instance
1787  * @retval State of bit (1 or 0).
1788  */
1789 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1790 {
1791  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1792 }
1793 
1794 /**
1795  * @brief Set frame format
1796  * @note These bits should not be changed when communication is ongoing.
1797  *
1798  * Register|BitsName
1799  * --------|--------
1800  * AUX_CTRL|QMODE
1801  *
1802  * @param XQSPIx XQSPI instance
1803  * @param format This parameter can be one of the following values:
1804  * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1805  * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1806  * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1807  * @retval None
1808  */
1809 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1810 {
1811  MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1812 }
1813 
1814 /**
1815  * @brief Get frame format
1816  *
1817  * Register|BitsName
1818  * --------|--------
1819  * AUX_CTRL|QMODE
1820  *
1821  * @param XQSPIx XQSPI instance
1822  * @retval Returned Value can be one even value:
1823  * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1824  * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1825  * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1826  */
1827 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1828 {
1829  return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1830 }
1831 
1832 /**
1833  * @brief Get QSPI status
1834  *
1835  * Register|BitsName
1836  * --------|--------
1837  * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1838  *
1839  * @param XQSPIx XQSPI instance
1840  * @retval Returned Value can be one or combination of the following values:
1841  * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1842  * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1843  * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1844  * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1845  * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1846  * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1847  * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1848  */
1849 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1850 {
1851  return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1852 }
1853 
1854 /**
1855  * @brief Check active flag
1856  *
1857  * Register|BitsName
1858  * --------|--------
1859  * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1860  *
1861  * @param XQSPIx XQSPI instance
1862  * @param flag This parameter can be one of the following values:
1863  * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1864  * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1865  * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1866  * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1867  * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1868  * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1869  * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1870  * @retval State of bit (1 or 0).
1871  */
1872 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1873 {
1874  return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
1875 }
1876 
1877 /**
1878  * @brief Enable slave select output
1879  *
1880  * Register|BitsName
1881  * --------|--------
1882  * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1883  *
1884  * @param XQSPIx XQSPI instance
1885  * @param ssout This parameter can between: 0 ~ 0xFF
1886  * @retval None
1887  */
1888 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1889 {
1890  SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1891 }
1892 
1893 /**
1894  * @brief Disable slave select output
1895  *
1896  * Register|BitsName
1897  * --------|--------
1898  * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1899  *
1900  * @param XQSPIx XQSPI instance
1901  * @param ssout This parameter can between: 0 ~ 0xFF
1902  * @retval None
1903  */
1904 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1905 {
1906  CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1907 }
1908 
1909 /**
1910  * @brief Set slave select output polarity
1911  *
1912  * Register|BitsName
1913  * --------|--------
1914  * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
1915  *
1916  * @param XQSPIx XQSPI instance
1917  * @param sspol This parameter can between: 0 ~ 0xFF
1918  * @retval None
1919  */
1920 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
1921 {
1922  SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
1923 }
1924 
1925 /**
1926  * @brief Get slave select output polarity
1927  *
1928  * Register|BitsName
1929  * --------|--------
1930  * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
1931  *
1932  * @param XQSPIx XQSPI instance
1933  * @retval Returned Value can between: 0 ~ 0xFF
1934  */
1935 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
1936 {
1937  return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
1938 }
1939 
1940 /**
1941  * @brief Get FIFO Transmission Level
1942  *
1943  * Register|BitsName
1944  * --------|--------
1945  * TX_FIFO_LVL | TXFIFOLVL
1946  *
1947  * @param XQSPIx XQSPI instance
1948  * @retval Returned Value can between: 0 ~ 16
1949  */
1950 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
1951 {
1952  return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
1953 }
1954 
1955 /**
1956  * @brief Get FIFO reception Level
1957  *
1958  * Register|BitsName
1959  * --------|--------
1960  * RX_FIFO_LVL | RXFIFOLVL
1961  *
1962  * @param XQSPIx XQSPI instance
1963  * @retval Returned Value can between: 0 ~ 16
1964  */
1965 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
1966 {
1967  return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
1968 }
1969 
1970 /**
1971  * @brief Enable interrupt
1972  * @note This bit controls the generation of an interrupt when an event occurs.
1973  *
1974  * Register|BitsName
1975  * --------|--------
1976  * INTEN |INT_EN
1977  *
1978  * @param XQSPIx XQSPI instance
1979  * @param mask This parameter can be one of the following values:
1980  * @arg @ref LL_XQSPI_QSPI_IM_DONE
1981  * @arg @ref LL_XQSPI_QSPI_IM_RFF
1982  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
1983  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
1984  * @arg @ref LL_XQSPI_QSPI_IM_TFE
1985  * @retval None
1986  */
1987 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
1988 {
1989  SET_BITS(XQSPIx->QSPI.INTEN, mask);
1990 }
1991 
1992 /**
1993  * @brief Disable interrupt
1994  * @note This bit controls the generation of an interrupt when an event occurs.
1995  *
1996  * Register|BitsName
1997  * --------|--------
1998  * INTEN |INT_EN
1999  *
2000  * @param XQSPIx XQSPI instance
2001  * @param mask This parameter can be one of the following values:
2002  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2003  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2004  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2005  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2006  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2007  * @retval None
2008  */
2009 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2010 {
2011  CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2012 }
2013 
2014 /**
2015  * @brief Check if interrupt is enabled
2016  *
2017  * Register|BitsName
2018  * --------|--------
2019  * INTEN |INT_EN
2020  *
2021  * @param XQSPIx XQSPI instance
2022  * @param mask This parameter can be one of the following values:
2023  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2024  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2025  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2026  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2027  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2028  * @retval State of bit (1 or 0).
2029  */
2030 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2031 {
2032  return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2033 }
2034 
2035 /**
2036  * @brief Get XQSPI interrupt flags
2037  *
2038  * Register|BitsName
2039  * --------|--------
2040  * INTSTAT |INT_STAT
2041  *
2042  * @param XQSPIx XQSPI instance
2043  * @retval Returned Value can be one or combination of the following values:
2044  * @arg @ref LL_XQSPI_QSPI_IS_DONE
2045  * @arg @ref LL_XQSPI_QSPI_IS_RFF
2046  * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2047  * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2048  * @arg @ref LL_XQSPI_QSPI_IS_TFE
2049  */
2050 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2051 {
2052  return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2053 }
2054 
2055 /**
2056  * @brief Check interrupt flag
2057  *
2058  * Register|BitsName
2059  * --------|--------
2060  * INTSTAT | XFER_DPULSE
2061  * INTSTAT | RX_FPULSE
2062  * INTSTAT | RX_WPULSE
2063  * INTSTAT | TX_WPULSE
2064  * INTSTAT | TX_EPULSE
2065  *
2066  * @param XQSPIx XQSPI instance
2067  * @param flag This parameter can be one of the following values:
2068  * @arg @ref LL_XQSPI_QSPI_IS_DONE
2069  * @arg @ref LL_XQSPI_QSPI_IS_RFF
2070  * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2071  * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2072  * @arg @ref LL_XQSPI_QSPI_IS_TFE
2073  * @retval State of bit (1 or 0).
2074  */
2075 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2076 {
2077  return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2078 }
2079 
2080 /**
2081  * @brief Clear interrupt flag
2082  * @note Clearing interrupt flag is done by writting INTCLR register
2083  *
2084  * Register|BitsName
2085  * --------|--------
2086  * INTCLR |INT_CLR
2087  *
2088  * @param XQSPIx XQSPI instance
2089  * @param flag This parameter can be one of the following values:
2090  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2091  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2092  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2093  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2094  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2095  * @retval None
2096  */
2097 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2098 {
2099  WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2100 }
2101 
2102 /**
2103  * @brief Set master inter-transfer delay
2104  *
2105  * Register|BitsName
2106  * --------|--------
2107  * MSTR_IT_DELAY | MWAIT
2108  *
2109  * @param XQSPIx XQSPI instance
2110  * @param wait This parameter can between: 0 ~ 255
2111  * @retval None
2112  */
2113 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2114 {
2115  MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2116 }
2117 
2118 /**
2119  * @brief Get master inter-transfer delay
2120  *
2121  * Register|BitsName
2122  * --------|--------
2123  * MSTR_IT_DELAY | MWAIT
2124  *
2125  * @param XQSPIx XQSPI instance
2126  * @retval Returned Value can between: 0 ~ 255
2127  */
2128 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2129 {
2130  return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2131 }
2132 
2133 /**
2134  * @brief Enable QSPI
2135  * @note This bit should not be enable when XIP is ongoing.
2136  *
2137  * Register|BitsName
2138  * --------|--------
2139  * SPIEN |EN
2140  *
2141  * @param XQSPIx XQSPI instance
2142  * @retval None
2143  */
2144 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2145 {
2146  SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2147 }
2148 
2149 /**
2150  * @brief Disable QSPI
2151  *
2152  * Register|BitsName
2153  * --------|--------
2154  * SPIEN |EN
2155  *
2156  * @param XQSPIx XQSPI instance
2157  * @retval None
2158  */
2159 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2160 {
2161  CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2162 }
2163 
2164 /**
2165  * @brief Check if QSPI is enabled
2166  *
2167  * Register|BitsName
2168  * --------|--------
2169  * SPIEN |EN
2170  *
2171  * @param XQSPIx XQSPI instance
2172  * @retval State of bit (1 or 0).
2173  */
2174 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2175 {
2176  return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2177 }
2178 
2179 /**
2180  * @brief Set QSPI Flash write bits
2181  *
2182  * Register|BitsName
2183  * --------|--------
2184  * FLASH_WRITE |FLASH_WRITE
2185  *
2186  * @param XQSPIx XQSPI instance
2187  * @param bits This parameter can be one of the following values:
2188  * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2189  * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2190  * @retval None
2191  */
2192 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2193 {
2194  WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2195 }
2196 
2197 /**
2198  * @brief Get QSPI Flash write bits
2199  *
2200  * Register|BitsName
2201  * --------|--------
2202  * FLASH_WRITE |FLASH_WRITE
2203  *
2204  * @param XQSPIx XQSPI instance
2205  * @retval Returned Value can be one of the following values:
2206  * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2207  * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2208  */
2209 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2210 {
2211  //GR551xx_C0 and future version.
2212  return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2213 }
2214 
2215 /**
2216  * @brief Set QSPI Present Bypass
2217  *
2218  * Register|BitsName
2219  * --------|--------
2220  * BYPASS |BYPASS
2221  *
2222  * @param XQSPIx XQSPI instance
2223  * @param bypass This parameter can be one of the following values:
2224  * @arg @ref LL_XQSPI_ENABLE_PRESENT
2225  * @arg @ref LL_XQSPI_DISABLE_PRESENT
2226  * @retval None
2227  */
2228 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2229 {
2230  WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2231 }
2232 
2233 /**
2234  * @brief Get QSPI Present Bypass
2235  *
2236  * Register|BitsName
2237  * --------|--------
2238  * BYPASS |BYPASS
2239  *
2240  * @param XQSPIx XQSPI instance
2241  * @retval Returned Value can be one of the following values:
2242  * @arg @ref LL_XQSPI_ENABLE_PRESENT
2243  * @arg @ref LL_XQSPI_DISABLE_PRESENT
2244  */
2245 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2246 {
2247  return READ_REG(XQSPIx->QSPI.BYPASS);
2248 }
2249 
2250 /**
2251  * @brief Enable exflash power
2252  * @note This bit should not be changed when XIP is ongoing.
2253  *
2254  * Register|BitsName
2255  * --------|--------
2256  * PWR_RET01 | EFLASH_PAD_EN
2257  *
2258  * @retval None
2259  */
2260 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2261 {
2262  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2263 }
2264 
2265 /**
2266  * @brief Disable exflash power
2267  * @note This bit should not be changed when XIP is ongoing.
2268  *
2269  * Register|BitsName
2270  * --------|--------
2271  * PWR_RET01 | EFLASH_PAD_EN
2272  *
2273  * @retval None
2274  */
2275 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2276 {
2277  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2278 }
2279 
2280 /**
2281  * @brief Check if exflash power is enabled
2282  *
2283  * Register|BitsName
2284  * --------|--------
2285  * PWR_RET01 | EFLASH_PAD_EN
2286  *
2287  * @retval State of bit (1 or 0).
2288  */
2289 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2290 {
2291  return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN) == (AON_PWR_REG01_EFLASH_PAD_EN));
2292 }
2293 
2294 /**
2295  * @brief Set XQSPI serial clock
2296  *
2297  * Register|BitsName
2298  * --------|--------
2299  * PWR_RET01 | XF_SCK_CLK_SEL
2300  *
2301  * @param speed This parameter can be one of the following values:
2302  * @arg @ref LL_XQSPI_BAUD_RATE_64M
2303  * @arg @ref LL_XQSPI_BAUD_RATE_48M
2304  * @arg @ref LL_XQSPI_BAUD_RATE_32M
2305  * @arg @ref LL_XQSPI_BAUD_RATE_24M
2306  * @arg @ref LL_XQSPI_BAUD_RATE_16M
2307  * @retval None
2308  */
2309 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2310 {
2311  MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL, speed);
2312 }
2313 
2314 /**
2315  * @brief Get XQSPI serial clock
2316  *
2317  * Register|BitsName
2318  * --------|--------
2319  * PWR_RET01 | XF_SCK_CLK_SEL
2320  *
2321  * @retval Returned Value can be one of the following values:
2322  * @arg @ref LL_XQSPI_BAUD_RATE_64M
2323  * @arg @ref LL_XQSPI_BAUD_RATE_48M
2324  * @arg @ref LL_XQSPI_BAUD_RATE_32M
2325  * @arg @ref LL_XQSPI_BAUD_RATE_24M
2326  * @arg @ref LL_XQSPI_BAUD_RATE_16M
2327  */
2328 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2329 {
2330  return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL));
2331 }
2332 
2333 /**
2334  * @brief Enable cache data retention.
2335  * @note This bit should not be changed when XIP is ongoing..
2336  *
2337  * Register|BitsName
2338  * --------|--------
2339  * PWR_RET01 | XF_TAG_RET
2340  *
2341  * @retval None
2342  */
2343 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2344 {
2345  SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2346 }
2347 
2348 /**
2349  * @brief Disable cache data retention.
2350  * @note This bit should not be changed when XIP is ongoing.
2351  *
2352  * Register|BitsName
2353  * --------|--------
2354  * PWR_RET01 | XF_TAG_RET
2355  *
2356  * @retval None
2357  */
2358 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2359 {
2360  CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2361 }
2362 
2363 /**
2364  * @brief Check if tag memory retention is enabled
2365  *
2366  * Register|BitsName
2367  * --------|--------
2368  * PWR_RET01 | XF_TAG_RET
2369  *
2370  * @retval State of bit (1 or 0).
2371  */
2372 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2373 {
2374  return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET) == (AON_PWR_REG01_XF_TAG_RET));
2375 }
2376 
2377 
2378 
2379 /** @} */
2380 
2381 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2382  * @{
2383  */
2384 
2385 /**
2386  * @brief De-initialize XQSPI registers (Registers restored to their default values).
2387  * @param XQSPIx XQSPI instance
2388  * @retval An error_status_t enumeration value:
2389  * - SUCCESS: XQSPI registers are de-initialized
2390  * - ERROR: XQSPI registers are not de-initialized
2391  */
2392 error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2393 
2394 /**
2395  * @brief Initialize XQSPI registers according to the specified
2396  * parameters in default.
2397  * @param XQSPIx XQSPI instance
2398  * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2399  * information for the specified XQPSI peripheral.
2400  * @retval An error_status_t enumeration value:
2401  * - SUCCESS: XQSPI registers are initialized according to default
2402  * - ERROR: Problem occurred during XQSPI Registers initialization
2403  */
2404 error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2405 
2406 /**
2407  * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2408  * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2409  * whose fields will be set to default values.
2410  * @retval None
2411  */
2413 
2414 /** @} */
2415 
2416 /** @} */
2417 
2418 #endif /* XQSPI */
2419 
2420 #ifdef __cplusplus
2421 }
2422 #endif
2423 
2424 #endif /* __GR55xx_LL_XQSPI_H__ */
2425 
2426 /** @} */
2427 
2428 /** @} */
2429 
2430 /** @} */
ll_xqspi_set_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr55xx_ll_xqspi.h:1676
ll_xqspi_is_active_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_xqspi.h:1872
ll_xqspi_disable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr55xx_ll_xqspi.h:1071
ll_xqspi_is_enabled_cache
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr55xx_ll_xqspi.h:407
ll_xqspi_get_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:560
ll_xqspi_is_enabled_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr55xx_ll_xqspi.h:1606
ll_xqspi_set_xip_ss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr55xx_ll_xqspi.h:773
ll_xqspi_get_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr55xx_ll_xqspi.h:1561
ll_xqspi_is_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr55xx_ll_xqspi.h:2289
ll_xqspi_get_cache_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr55xx_ll_xqspi.h:655
ll_xqspi_is_enabled_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:1119
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_xqspi.h:101
ll_xqspi_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr55xx_ll_xqspi.h:2343
ll_xqspi_enable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr55xx_ll_xqspi.h:1424
ll_xqspi_qspi_transmit_data16
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1221
ll_xqspi_get_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr55xx_ll_xqspi.h:705
ll_xqspi_disable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr55xx_ll_xqspi.h:737
ll_xqspi_get_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr55xx_ll_xqspi.h:491
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate be used to configure the transmit and receive SCK clock.
Definition: gr55xx_ll_xqspi.h:111
ll_xqspi_get_xip_ss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr55xx_ll_xqspi.h:792
ll_xqspi_get_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:1490
ll_xqspi_disable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr55xx_ll_xqspi.h:2159
ll_xqspi_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr55xx_ll_xqspi.h:2260
ll_xqspi_disable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr55xx_ll_xqspi.h:2358
ll_xqspi_disable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1636
ll_xqspi_set_present_bypass
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
Set QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2228
ll_xqspi_set_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:1509
ll_xqspi_get_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr55xx_ll_xqspi.h:2050
ll_xqspi_get_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr55xx_ll_xqspi.h:900
_ll_xqspi_init_t::data_order
uint32_t data_order
Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:96
ll_xqspi_enable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr55xx_ll_xqspi.h:576
ll_xqspi_is_enabled_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr55xx_ll_xqspi.h:607
ll_xqspi_enable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr55xx_ll_xqspi.h:721
ll_xqspi_is_enabled_cache_flush
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr55xx_ll_xqspi.h:454
ll_xqspi_set_flash_write
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2192
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Specifies the cache mode in XIP mode.
Definition: gr55xx_ll_xqspi.h:81
ll_xqspi_disable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr55xx_ll_xqspi.h:592
ll_xqspi_get_xip_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr55xx_ll_xqspi.h:1103
ll_xqspi_enable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_xqspi.h:1987
ll_xqspi_set_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:545
ll_xqspi_is_enabled_xip_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr55xx_ll_xqspi.h:752
ll_xqspi_disable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1729
ll_xqspi_set_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr55xx_ll_xqspi.h:954
ll_xqspi_enable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1576
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_get_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1364
ll_xqspi_enable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr55xx_ll_xqspi.h:1056
ll_xqspi_init
error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_get_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2128
ll_xqspi_is_enabled_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1789
ll_xqspi_is_qspi_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_xqspi.h:2075
ll_xqspi_qspi_receive_data8
SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1252
ll_xqspi_get_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1041
ll_xqspi_is_enabled_qspi_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:2030
ll_xqspi_is_enabled_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr55xx_ll_xqspi.h:1454
ll_xqspi_is_enabled_xip
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr55xx_ll_xqspi.h:1087
ll_xqspi_get_req_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr55xx_ll_xqspi.h:1151
ll_xqspi_deinit
error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_enable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr55xx_ll_xqspi.h:2144
ll_xqspi_get_flash_write
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2209
ll_xqspi_disable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1394
ll_xqspi_set_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1303
ll_xqspi_get_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr55xx_ll_xqspi.h:1827
ll_xqspi_is_enabled_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr55xx_ll_xqspi.h:1409
ll_xqspi_enable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr55xx_ll_xqspi.h:1167
ll_xqspi_disable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1774
ll_xqspi_is_enabled_qspi
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr55xx_ll_xqspi.h:2174
ll_xqspi_set_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:811
ll_xqspi_clear_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr55xx_ll_xqspi.h:2097
ll_xqspi_get_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1935
ll_xqspi_qspi_transmit_data32
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1237
ll_xqspi_get_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2328
ll_xqspi_is_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr55xx_ll_xqspi.h:2372
ll_xqspi_disable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr55xx_ll_xqspi.h:2275
ll_xqspi_get_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:528
_ll_xqspi_init_t::mode
uint32_t mode
Specifies the work mode, XIP mode or QSPI mode.
Definition: gr55xx_ll_xqspi.h:78
ll_xqspi_set_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2309
ll_xqspi_disable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_xqspi.h:2009
ll_xqspi_disable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr55xx_ll_xqspi.h:1439
ll_xqspi_qspi_receive_data32
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1282
ll_xqspi_enable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1621
ll_xqspi_set_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:847
ll_xqspi_get_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:864
ll_xqspi_enable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr55xx_ll_xqspi.h:374
ll_xqspi_is_enabled_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:1744
ll_xqspi_disable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr55xx_ll_xqspi.h:1183
ll_xqspi_qspi_receive_data16
SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1267
ll_xqspi_get_qspi_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr55xx_ll_xqspi.h:1849
ll_xqspi_get_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:828
ll_xqspi_set_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr55xx_ll_xqspi.h:883
ll_xqspi_get_present_bypass
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
Get QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2245
ll_xqspi_set_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr55xx_ll_xqspi.h:1809
ll_xqspi_set_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2113
ll_xqspi_is_enabled_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr55xx_ll_xqspi.h:1651
ll_xqspi_set_xip_endian
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr55xx_ll_xqspi.h:919
ll_xqspi_set_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr55xx_ll_xqspi.h:1544
ll_xqspi_enable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr55xx_ll_xqspi.h:1888
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr55xx_ll_xqspi.h:77
ll_xqspi_disable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr55xx_ll_xqspi.h:1904
ll_xqspi_set_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:510
ll_xqspi_enable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:1759
ll_xqspi_disable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1591
ll_xqspi_set_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr55xx_ll_xqspi.h:473
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_xqspi.h:106
ll_xqspi_get_flag_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr55xx_ll_xqspi.h:1135
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Specifies the XQSPI read command in XIP mode.
Definition: gr55xx_ll_xqspi.h:86
ll_xqspi_get_cache_hitcount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr55xx_ll_xqspi.h:623
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_get_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr55xx_ll_xqspi.h:969
ll_xqspi_get_cache_misscount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr55xx_ll_xqspi.h:639
ll_xqspi_set_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:1473
ll_xqspi_get_qspi_tx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_xqspi.h:1950
ll_xqspi_set_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1026
ll_xqspi_get_qspi_rx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_xqspi.h:1965
ll_xqspi_enable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr55xx_ll_xqspi.h:423
ll_xqspi_qspi_transmit_data8
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1205
ll_xqspi_get_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:1526
ll_xqspi_enable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1379
ll_xqspi_set_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:990
ll_xqspi_disable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr55xx_ll_xqspi.h:439
ll_xqspi_set_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr55xx_ll_xqspi.h:1920
ll_xqspi_enable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:1714
ll_xqspi_set_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr55xx_ll_xqspi.h:684
ll_xqspi_get_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1009
ll_xqspi_get_xip_endian
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr55xx_ll_xqspi.h:936
ll_xqspi_disable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr55xx_ll_xqspi.h:391
ll_xqspi_get_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1323
ll_xqspi_get_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr55xx_ll_xqspi.h:1699
ll_xqspi_set_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1344
_ll_xqspi_init_t::data_size
uint32_t data_size
Specifies the XQSPI data width, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:91