52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos)
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos)
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos)
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136 AON_SLP_EVENT_TIMER | \
137 AON_SLP_EVENT_EXTWKUP | \
138 AON_SLP_EVENT_PMU_BOD_FEDGE | \
139 AON_SLP_EVENT_PMU_MSIO_COMP | \
140 AON_SLP_EVENT_WDT_REBOOT | \
141 AON_SLP_EVENT_CALENDAR_TIMER_ALARM)
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U)
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U)
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U)
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U)
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U)
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U)
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U)
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U)
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU)
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
162 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
163 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U)
164 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB)
170 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK
171 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON
172 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD
173 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP
174 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF
175 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK
176 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK
177 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK
178 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK
179 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG
180 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG
181 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI
182 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO
183 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0
184 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1
185 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2
186 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3
195 #define LL_PWR_DPAD_LE_OFF (0x00000000U)
196 #define LL_PWR_DPAD_LE_ON (0x00000001U)
203 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER
204 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT
205 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER
206 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM
227 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
234 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
266 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
287 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
334 GLOBAL_EXCEPTION_DISABLE();
335 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
336 GLOBAL_EXCEPTION_ENABLE();
358 GLOBAL_EXCEPTION_DISABLE();
359 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
360 GLOBAL_EXCEPTION_ENABLE();
382 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
412 GLOBAL_EXCEPTION_DISABLE();
413 MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
414 GLOBAL_EXCEPTION_ENABLE();
442 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
459 WRITE_REG(AON->TIMER_VALUE, value);
473 return READ_REG(AON->TIMER_VALUE);
488 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
503 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
517 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
538 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
539 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
577 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
578 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
600 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
615 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
629 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
646 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
661 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
675 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
690 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
691 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
692 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
707 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
708 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
709 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
724 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
739 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
740 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
755 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
756 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
757 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
772 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
791 GLOBAL_EXCEPTION_DISABLE();
792 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
793 GLOBAL_EXCEPTION_ENABLE();
811 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
830 return ((uint32_t)READ_REG(AON->TIMER_VAL));
844 GLOBAL_EXCEPTION_DISABLE();
845 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
846 GLOBAL_EXCEPTION_ENABLE();
862 GLOBAL_EXCEPTION_DISABLE();
863 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
864 GLOBAL_EXCEPTION_ENABLE();
878 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
892 GLOBAL_EXCEPTION_DISABLE();
893 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
894 GLOBAL_EXCEPTION_ENABLE();
909 GLOBAL_EXCEPTION_DISABLE();
910 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
911 GLOBAL_EXCEPTION_ENABLE();
925 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
940 GLOBAL_EXCEPTION_DISABLE();
941 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
942 GLOBAL_EXCEPTION_ENABLE();
957 GLOBAL_EXCEPTION_DISABLE();
958 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
959 GLOBAL_EXCEPTION_ENABLE();
973 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
989 GLOBAL_EXCEPTION_DISABLE();
990 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
991 GLOBAL_EXCEPTION_ENABLE();
1006 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1021 GLOBAL_EXCEPTION_DISABLE();
1022 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1023 GLOBAL_EXCEPTION_ENABLE();
1038 GLOBAL_EXCEPTION_DISABLE();
1039 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1040 GLOBAL_EXCEPTION_ENABLE();
1054 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1069 WRITE_REG(AON->PWR_RET28, time);
1083 return ((uint32_t)READ_REG(AON->PWR_RET28));
1098 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1119 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1120 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1121 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1138 return ((uint32_t)READ_REG(AON->PWR_RET29));
1148 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1177 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1200 GLOBAL_EXCEPTION_DISABLE();
1201 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1202 GLOBAL_EXCEPTION_ENABLE();
1243 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1258 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1273 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1274 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();