38 #ifndef __GR55xx_DELAY_H__
39 #define __GR55xx_DELAY_H__
48 #if defined ( __CC_ARM )
50 #ifndef __STATIC_FORCEINLINE
51 #define __STATIC_FORCEINLINE static __forceinline
54 #elif defined ( __GNUC__ )
56 #ifndef __STATIC_FORCEINLINE
57 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
62 #ifndef __STATIC_FORCEINLINE
63 #define __STATIC_FORCEINLINE __STATIC_INLINE
80 uint8_t clocks[] = {64, 48, 16, 24, 16, 32};
81 uint32_t cycles = number_of_us * (clocks[AON->PWR_RET01 & AON_PWR_REG01_SYS_CLK_SEL]);
83 uint8_t clocks[] = {96, 64, 16, 48, 24, 16, 32};
84 uint32_t cycles = number_of_us * clocks[AON_CTL->MCU_CLK_CTRL & AON_CTL_MCU_CLK_CTRL_SEL];
87 if (number_of_us == 0)
93 uint32_t core_debug_initial = CoreDebug->DEMCR;
95 CoreDebug->DEMCR = core_debug_initial | CoreDebug_DEMCR_TRCENA_Msk;
98 uint32_t dwt_ctrl_initial = DWT->CTRL;
100 DWT->CTRL = dwt_ctrl_initial | DWT_CTRL_CYCCNTENA_Msk;
103 uint32_t cyccnt_initial = DWT->CYCCNT;
106 while ((DWT->CYCCNT - cyccnt_initial) < cycles)
110 DWT->CTRL = dwt_ctrl_initial;
111 CoreDebug->DEMCR = core_debug_initial;