+ Collaboration diagram for XQSPI Clock Mode:

Macros

#define XQSPI_CLOCK_MODE_0   ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE)
 Inactive state of CLK is low, CLK toggles at the start of first data bit
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#define XQSPI_CLOCK_MODE_1   ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE)
 Inactive state of CLK is low, CLK toggles in the middle of first data bit
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#define XQSPI_CLOCK_MODE_2   ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE)
 Inactive state of CLK is high, CLK toggles at the start of first data bit
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#define XQSPI_CLOCK_MODE_3   ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE)
 Inactive state of CLK is high, CLK toggles in the middle of first data bit
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Detailed Description

Macro Definition Documentation

◆ XQSPI_CLOCK_MODE_0

#define XQSPI_CLOCK_MODE_0   ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE)

Inactive state of CLK is low, CLK toggles at the start of first data bit

Definition at line 267 of file gr55xx_hal_xqspi.h.

◆ XQSPI_CLOCK_MODE_1

#define XQSPI_CLOCK_MODE_1   ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE)

Inactive state of CLK is low, CLK toggles in the middle of first data bit

Definition at line 269 of file gr55xx_hal_xqspi.h.

◆ XQSPI_CLOCK_MODE_2

#define XQSPI_CLOCK_MODE_2   ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE)

Inactive state of CLK is high, CLK toggles at the start of first data bit

Definition at line 271 of file gr55xx_hal_xqspi.h.

◆ XQSPI_CLOCK_MODE_3

#define XQSPI_CLOCK_MODE_3   ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE)

Inactive state of CLK is high, CLK toggles in the middle of first data bit

Definition at line 273 of file gr55xx_hal_xqspi.h.