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52 #ifndef __GR55xx_HAL_QSPI_H__
53 #define __GR55xx_HAL_QSPI_H__
240 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
241 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
242 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
243 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
244 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
250 #define QSPI_CLOCK_MODE_0 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_1EDGE)
252 #define QSPI_CLOCK_MODE_1 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_2EDGE)
254 #define QSPI_CLOCK_MODE_2 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_1EDGE)
256 #define QSPI_CLOCK_MODE_3 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_2EDGE)
263 #define QSPI_DATA_MODE_SPI LL_SSI_FRF_SPI
264 #define QSPI_DATA_MODE_DUALSPI LL_SSI_FRF_DUALSPI
265 #define QSPI_DATA_MODE_QUADSPI LL_SSI_FRF_QUADSPI
271 #define QSPI_INSTSIZE_00_BITS LL_SSI_INSTSIZE_0BIT
272 #define QSPI_INSTSIZE_04_BITS LL_SSI_INSTSIZE_4BIT
273 #define QSPI_INSTSIZE_08_BITS LL_SSI_INSTSIZE_8BIT
274 #define QSPI_INSTSIZE_16_BITS LL_SSI_INSTSIZE_16BIT
280 #define QSPI_ADDRSIZE_00_BITS LL_SSI_ADDRSIZE_0BIT
281 #define QSPI_ADDRSIZE_04_BITS LL_SSI_ADDRSIZE_4BIT
282 #define QSPI_ADDRSIZE_08_BITS LL_SSI_ADDRSIZE_8BIT
283 #define QSPI_ADDRSIZE_12_BITS LL_SSI_ADDRSIZE_12BIT
284 #define QSPI_ADDRSIZE_16_BITS LL_SSI_ADDRSIZE_16BIT
285 #define QSPI_ADDRSIZE_20_BITS LL_SSI_ADDRSIZE_20BIT
286 #define QSPI_ADDRSIZE_24_BITS LL_SSI_ADDRSIZE_24BIT
287 #define QSPI_ADDRSIZE_28_BITS LL_SSI_ADDRSIZE_28BIT
288 #define QSPI_ADDRSIZE_32_BITS LL_SSI_ADDRSIZE_32BIT
294 #define QSPI_DATASIZE_04_BITS LL_SSI_DATASIZE_4BIT
295 #define QSPI_DATASIZE_05_BITS LL_SSI_DATASIZE_5BIT
296 #define QSPI_DATASIZE_06_BITS LL_SSI_DATASIZE_6BIT
297 #define QSPI_DATASIZE_07_BITS LL_SSI_DATASIZE_7BIT
298 #define QSPI_DATASIZE_08_BITS LL_SSI_DATASIZE_8BIT
299 #define QSPI_DATASIZE_09_BITS LL_SSI_DATASIZE_9BIT
300 #define QSPI_DATASIZE_10_BITS LL_SSI_DATASIZE_10BIT
301 #define QSPI_DATASIZE_11_BITS LL_SSI_DATASIZE_11BIT
302 #define QSPI_DATASIZE_12_BITS LL_SSI_DATASIZE_12BIT
303 #define QSPI_DATASIZE_13_BITS LL_SSI_DATASIZE_13BIT
304 #define QSPI_DATASIZE_14_BITS LL_SSI_DATASIZE_14BIT
305 #define QSPI_DATASIZE_15_BITS LL_SSI_DATASIZE_15BIT
306 #define QSPI_DATASIZE_16_BITS LL_SSI_DATASIZE_16BIT
307 #define QSPI_DATASIZE_17_BITS LL_SSI_DATASIZE_17BIT
308 #define QSPI_DATASIZE_18_BITS LL_SSI_DATASIZE_18BIT
309 #define QSPI_DATASIZE_19_BITS LL_SSI_DATASIZE_19BIT
310 #define QSPI_DATASIZE_20_BITS LL_SSI_DATASIZE_20BIT
311 #define QSPI_DATASIZE_21_BITS LL_SSI_DATASIZE_21BIT
312 #define QSPI_DATASIZE_22_BITS LL_SSI_DATASIZE_22BIT
313 #define QSPI_DATASIZE_23_BITS LL_SSI_DATASIZE_23BIT
314 #define QSPI_DATASIZE_24_BITS LL_SSI_DATASIZE_24BIT
315 #define QSPI_DATASIZE_25_BITS LL_SSI_DATASIZE_25BIT
316 #define QSPI_DATASIZE_26_BITS LL_SSI_DATASIZE_26BIT
317 #define QSPI_DATASIZE_27_BITS LL_SSI_DATASIZE_27BIT
318 #define QSPI_DATASIZE_28_BITS LL_SSI_DATASIZE_28BIT
319 #define QSPI_DATASIZE_29_BITS LL_SSI_DATASIZE_29BIT
320 #define QSPI_DATASIZE_30_BITS LL_SSI_DATASIZE_30BIT
321 #define QSPI_DATASIZE_31_BITS LL_SSI_DATASIZE_31BIT
322 #define QSPI_DATASIZE_32_BITS LL_SSI_DATASIZE_32BIT
330 #define QSPI_INST_ADDR_ALL_IN_SPI LL_SSI_INST_ADDR_ALL_IN_SPI
331 #define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
332 #define QSPI_INST_ADDR_ALL_IN_SPIFRF LL_SSI_INST_ADDR_ALL_IN_SPIFRF
338 #define QSPI_FLAG_DCOL LL_SSI_SR_DCOL
339 #define QSPI_FLAG_TXE LL_SSI_SR_TXE
340 #define QSPI_FLAG_RFF LL_SSI_SR_RFF
341 #define QSPI_FLAG_RFNE LL_SSI_SR_RFNE
342 #define QSPI_FLAG_TFE LL_SSI_SR_TFE
343 #define QSPI_FLAG_TFNF LL_SSI_SR_TFNF
344 #define QSPI_FLAG_BUSY LL_SSI_SR_BUSY
350 #define QSPI_IT_MST LL_SSI_IS_MST
351 #define QSPI_IT_RXF LL_SSI_IS_RXF
352 #define QSPI_IT_RXO LL_SSI_IS_RXO
353 #define QSPI_IT_RXU LL_SSI_IS_RXU
354 #define QSPI_IT_TXO LL_SSI_IS_TXO
355 #define QSPI_IT_TXE LL_SSI_IS_TXE
361 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)
375 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_QSPI_STATE_RESET)
381 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->SSI_EN, SSI_SSIEN_EN)
387 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->SSI_EN, SSI_SSIEN_EN)
393 #define __HAL_QSPI_ENABLE_DMATX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_TDMAE)
399 #define __HAL_QSPI_ENABLE_DMARX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_RDMAE)
405 #define __HAL_QSPI_DISABLE_DMATX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_TDMAE)
411 #define __HAL_QSPI_DISABLE_DMARX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, SSI_DMAC_RDMAE)
425 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
439 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
453 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BITS((__HANDLE__)->p_instance->INTSTAT, (__INTERRUPT__)) == (__INTERRUPT__))
468 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__)) != 0) ? SET : RESET)
483 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__))
496 #define IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
502 #define IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= 7))
508 #define IS_QSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
509 ((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
510 ((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
511 ((__CLKMODE__) == QSPI_CLOCK_MODE_3))
517 #define IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
518 ((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
519 ((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
520 ((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))
526 #define IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
527 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
528 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
529 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
530 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
531 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
532 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
533 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
534 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))
540 #define IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
546 #define IS_QSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
547 ((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
548 ((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))
554 #define IS_QSPI_DATA_MODE(__MODE__) (((__MODE__) == QSPI_DATA_MODE_SPI) || \
555 ((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
556 ((__MODE__) == QSPI_DATA_MODE_QUADSPI))
void(* qspi_msp_deinit)(qspi_handle_t *p_qspi)
QSPI de-init MSP callback
__IO uint32_t tx_xfer_size
QSPI Tx Transfer size
uint32_t instruction_size
Specifies the Instruction Size.
uint32_t timeout
Timeout for the QSPI memory access.
hal_lock_t
HAL Lock structures definition.
void hal_qspi_fifo_threshold_callback(qspi_handle_t *p_qspi)
FIFO Threshold callback.
void(* qspi_rx_cplt_callback)(qspi_handle_t *p_qspi)
QSPI rx transfer completed callback
uint32_t data_size
Specifies the QSPI address width.
hal_status_t hal_qspi_set_rx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold)
Set the RX FIFO threshold.
uint32_t hal_qspi_get_rx_fifo_threshold(qspi_handle_t *p_qspi)
Get the RX FIFO threshold.
hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with DMA.
hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
uint32_t instruction_address_mode
Specifies the Instruction and Address Mode.
@ HAL_QSPI_STATE_ABORT
Peripheral with abort request ongoing
void(* qspi_fifo_threshold_callback)(qspi_handle_t *p_qspi)
QSPI FIFO threshold callback
uint32_t length
Specifies the number of data to transfer.
__IO uint32_t rx_xfer_size
QSPI Rx Transfer size
__IO hal_qspi_state_t state
QSPI communication state
hal_status_t hal_qspi_set_tx_fifo_threshold(qspi_handle_t *p_qspi, uint32_t threshold)
Set the TX FIFO threshold.
void(* qspi_error_callback)(qspi_handle_t *p_qspi)
QSPI error callback
__IO uint32_t rx_xfer_count
QSPI Rx Transfer Counter
hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI peripheral.
uint8_t * p_tx_buffer
Pointer to QSPI Tx transfer Buffer.
QSPI init Structure definition.
void hal_qspi_msp_init(qspi_handle_t *p_qspi)
Initialize the QSPI MSP.
hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
@ HAL_QSPI_STATE_RESET
Peripheral not initialized
QSPI command Structure definition.
@ HAL_QSPI_STATE_READY
Peripheral initialized and ready for use
ssi_regs_t * p_instance
QSPI registers base address
void(* write_fifo)(struct _qspi_handle *p_qspi)
Pointer to QSPI Tx transfer FIFO write function.
hal_status_t hal_qspi_init(qspi_handle_t *p_qspi)
Initialize the QSPI according to the specified parameters in the qspi_init_t and initialize the assoc...
uint32_t address_size
Specifies the Address Size.
void hal_qspi_msp_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI MSP.
hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with Inter...
hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi)
Suspend some registers related to QSPI configuration before sleep.
void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi)
Tx Transfer completed callback.
hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi)
QSPI Abort Complete callback.
hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Transmit an amount of data with the specified instruction and address in blocking mode.
void(* qspi_tx_cplt_callback)(qspi_handle_t *p_qspi)
QSPI tx transfer completed callback
dma_handle_t * p_dma
QSPI Rx/Tx DMA Handle parameters
@ HAL_QSPI_STATE_ERROR
Peripheral in error
uint32_t dummy_cycles
Specifies the Number of Dummy Cycles.
void hal_qspi_irq_handler(qspi_handle_t *p_qspi)
Handle QSPI interrupt request.
hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi)
Abort the current transmission.
hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
HAL_QSPI Callback function definition.
void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi)
Rx Transfer completed callback.
Header file containing functions prototypes of SPI LL library.
hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi)
Abort the current transmission (non-blocking function)
struct _qspi_command_t qspi_command_t
QSPI command Structure definition.
@ HAL_QSPI_STATE_BUSY_INDIRECT_RX
Peripheral in indirect mode with reception ongoing
void(* qspi_abort_cplt_callback)(qspi_handle_t *p_qspi)
QSPI abort complete callback
hal_status_t
HAL Status structures definition.
hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
uint32_t clock_prescaler
Specifies the prescaler factor for generating clock based on the AHB clock.
void(* read_fifo)(struct _qspi_handle *p_qspi)
Pointer to QSPI Rx transfer FIFO read function
hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with DMA.
__IO uint32_t error_code
QSPI Error code
hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi)
Restore some registers related to QSPI configuration after sleep.
hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
qspi_init_t init
QSPI communication parameters
__IO hal_lock_t lock
Locking object
uint32_t instruction
Specifies the Instruction to be sent.
__IO uint32_t tx_xfer_count
QSPI Tx Transfer Counter
@ HAL_QSPI_STATE_BUSY_INDIRECT_TX
Peripheral in indirect mode with transmission ongoing.
uint32_t hal_qspi_get_tx_fifo_threshold(qspi_handle_t *p_qspi)
Get the TX FIFO threshold.
hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout)
Set the QSPI internal process timeout value.
struct _qspi_handle qspi_handle_t
QSPI handle Structure definition.
hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
uint32_t data_mode
Specifies the Data Mode (used for dummy cycles and data phases).
@ HAL_QSPI_STATE_BUSY
Peripheral in indirect mode and busy
struct _qspi_init_t qspi_init_t
QSPI init Structure definition.
hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
struct _hal_qspi_callback hal_qspi_callback_t
HAL_QSPI Callback function definition.
hal_qspi_state_t
HAL QSPI State Enumerations definition.
hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi)
Return the QSPI handle state.
uint32_t retention[9]
DMA important register information.
void(* qspi_msp_init)(qspi_handle_t *p_qspi)
QSPI init MSP callback
hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with DMA.
uint8_t * p_rx_buffer
Pointer to QSPI Rx transfer Buffer.
QSPI handle Structure definition.
uint32_t address
Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
DMA handle Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi)
Return the QSPI error code.
uint32_t clock_mode
Specifies the Clock Mode.
void hal_qspi_error_callback(qspi_handle_t *p_qspi)
QSPI error callback.
hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
uint32_t rx_sample_delay
Specifies the RX sample delay.