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51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
106 #define LL_AES_FLAG_DATAREADY AES_STATUS_READY
107 #define LL_AES_FLAG_DMA_DONE AES_STATUS_TRANSDONE
108 #define LL_AES_FLAG_DMA_ERR AES_STATUS_TRANSERR
109 #define LL_AES_FLAG_KEY_VALID AES_STATUS_KEYVALID
115 #define LL_AES_KEY_SIZE_128 0x00000000U
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CONFIG_KEYMODE_Pos)
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CONFIG_KEYMODE_Pos)
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CONFIG_OPMODE_Pos)
130 #define LL_AES_KEYTYPE_MCU 0x00000000U
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CONFIG_KEYTYPE_Pos)
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CONFIG_KEYTYPE_Pos)
138 #define LL_AES_DMA_TRANSIZE_MIN (1)
139 #define LL_AES_DMA_TRANSIZE_MAX (2048)
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
201 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE);
220 CLEAR_BITS(AESx->CTRL, AES_CTRL_ENABLE);
239 return (READ_BITS(AESx->CTRL, AES_CTRL_ENABLE) == (AES_CTRL_ENABLE));
258 SET_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
277 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
296 return (READ_BITS(AESx->CTRL, AES_CTRL_START_NORMAL) == (AES_CTRL_START_NORMAL));
315 SET_BITS(AESx->CTRL, AES_CTRL_START_DMA);
334 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_DMA);
353 return (READ_BITS(AESx->CTRL, AES_CTRL_START_DMA) == (AES_CTRL_START_DMA));
372 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE_RKEY);
395 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYMODE, size);
417 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYMODE));
436 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
455 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
474 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK) == (AES_CONFIG_ENABLE_FULLMASK));
493 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
512 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
531 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION) == (AES_CONFIG_ENABLE_ENCRYPTION));
550 SET_BITS(AESx->CONFIG, AES_CONFIG_LOADSEED);
569 SET_BITS(AESx->CONFIG, AES_CONFIG_FIRSTBLOCK);
588 SET_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
607 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
626 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN) == (AES_CONFIG_ENDIAN));
648 MODIFY_REG(AESx->CONFIG, AES_CONFIG_OPMODE, mode);
669 return (READ_BITS(AESx->CONFIG, AES_CONFIG_OPMODE));
692 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYTYPE, Type);
714 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYTYPE));
739 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
758 CLEAR_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
777 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE) == (AES_INTERRUPT_ENABLE));
802 return (READ_BITS(AESx->STATUS, AES_STATUS_READY) == AES_STATUS_READY);
821 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSDONE) == AES_STATUS_TRANSDONE);
840 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSERR) == AES_STATUS_TRANSERR);
859 return (READ_BITS(AESx->STATUS, AES_STATUS_KEYVALID) == AES_STATUS_KEYVALID);
878 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE) == AES_INTERRUPT_DONE);
897 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE);
923 MODIFY_REG(AESx->TRAN_SIZE, AES_TRAN_SIZE, (block << 4) - 1);
942 return ((READ_BITS(AESx->TRAN_SIZE, AES_TRAN_SIZE) + 1) >> 4);
963 WRITE_REG(AESx->RSTART_ADDR, address);
982 return (READ_REG(AESx->RSTART_ADDR));
1003 WRITE_REG(AESx->WSTART_ADDR, address);
1022 return (READ_REG(AESx->WSTART_ADDR));
1048 WRITE_REG(AESx->KEY_ADDR, address);
1067 return (READ_REG(AESx->KEY_ADDR));
1086 return (READ_REG(AESx->DATA_OUT[0]));
1105 return (READ_REG(AESx->DATA_OUT[1]));
1124 return (READ_REG(AESx->DATA_OUT[2]));
1143 return (READ_REG(AESx->DATA_OUT[3]));
1163 WRITE_REG(AESx->KEY[0], key);
1183 WRITE_REG(AESx->KEY[1], key);
1203 WRITE_REG(AESx->KEY[2], key);
1223 WRITE_REG(AESx->KEY[3], key);
1243 WRITE_REG(AESx->KEY[4], key);
1263 WRITE_REG(AESx->KEY[5], key);
1283 WRITE_REG(AESx->KEY[6], key);
1303 WRITE_REG(AESx->KEY[7], key);
1323 WRITE_REG(AESx->SEED_IN, seed);
1342 return (READ_REG(AESx->SEED_IN));
1362 WRITE_REG(AESx->SEED_OUT, seed);
1381 return (READ_REG(AESx->SEED_OUT));
1401 WRITE_REG(AESx->SEED_IMASK, mask);
1420 return (READ_REG(AESx->SEED_IMASK));
1440 WRITE_REG(AESx->SEED_OSBOX, mask);
1459 return (READ_REG(AESx->SEED_OSBOX));
1479 WRITE_REG(AESx->VECTOR_INIT[0], vector);
1499 WRITE_REG(AESx->VECTOR_INIT[1], vector);
1519 WRITE_REG(AESx->VECTOR_INIT[2], vector);
1539 WRITE_REG(AESx->VECTOR_INIT[3], vector);
1559 WRITE_REG(AESx->DATA_IN[0], data);
1579 WRITE_REG(AESx->DATA_IN[1], data);
1599 WRITE_REG(AESx->DATA_IN[2], data);
1619 WRITE_REG(AESx->DATA_IN[3], data);
1639 WRITE_REG(AESx->KPORT_MASK, mask);
__STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
Enable fetch key through AHB/key port.
__STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
Enable AES encryption mode.
__STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
Disable AES encryption mode.
__STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[127:96].
uint32_t * p_key
Encryption/Decryption Key.
__STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
Disable AES start in MCU mode.
__STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
Get AES output data[63:32].
__STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
Get AES output data[127:96].
__STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
Set ways to obtain AES key.
__STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
Disable AES.
__STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
Set AES input data[63:32].
__STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
Set AES key[95:64].
struct _ll_aes_init ll_aes_init_t
LL AES Init Structure definition.
__STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
Get AES output data[95:64].
__STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
Get AES write address of RAM in DMA mode.
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
Indicate whether the DMA transfer error flag is set.
__STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
Set AES operation mode.
__STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
Set AES key[31:0].
__STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt is enabled.
__STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[63:32].
__STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[31:0].
__STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
Indicate whether the ready flag is set.
__STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
Indicate whether the AES full mask is enabled.
__STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
Set AES input seed.
__STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
Enable AES full mask.
error_status_t ll_aes_deinit(aes_regs_t *AESx)
De-initialize AES registers (Registers restored to their default values).
LL AES Init Structure definition.
__STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
Disable AES DMA mode.
__STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
Indicate whether the AES is in little endian.
__STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
Enable AES start in MCU mode.
uint32_t * p_init_vector
Initialization Vector used for CBC modes.
__STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
Set AES key[191:160].
__STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
Set AES write address of RAM in DMA mode.
__STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
Get AES key size.
__STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
Get sbox input data's mask.
error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init)
Initialize AES registers according to the specified parameters in p_aes_init.
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
Indicate whether the DMA transfer done flag is set.
__STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
__STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
Get ways to obtain AES key.
__STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
Set AES input data[95:64].
__STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt flag is set.
__STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
Set AES input data[127:96].
__STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
Set AES key[63:32].
__STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
Set AES key address in memory.
__STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
Disable AES in little endian.
__STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
Indicate whether the AES encryption mode is enabled.
__STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[95:64].
__STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
Set AES key[159:128].
__STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
Get AES read address of RAM in DMA mode.
__STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
Indicate whether the key valid flag is set.
__STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
Get AES output seed.
__STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
Get sbox output data's mask.
void ll_aes_struct_init(ll_aes_init_t *p_aes_init)
Set each field of a ll_aes_init_t type structure to default value.
__STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
Disable AES the done interrupt.
__STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
Enable AES in little endian.
__STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
Set AES read address of RAM in DMA mode.
__STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
Enable AES the done interrupt.
__STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
Set AES output seed.
uint32_t key_size
128, 192 or 256-bit key length.
__STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
Set AES input data[31:0].
__STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
Get AES operation mode.
__STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
Get AES key address in memory.
__STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
Set sbox input data's mask.
__STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
Get AES output data[31:0].
__STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
Disable AES full mask.
__STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
Set AES key[255:224].
__STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
Indicate whether the AES DMA mode is enabled.
__STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
Set AES transfer blocks in DMA mode.
__STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
Set AES fetch key port mask.
__STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
Get AES input seed.
__STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
Clear the done interrupt flag.
__STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
Enable AES DMA mode.
__STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
Set sbox output data's mask.
__STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
Enable AES.
__STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
Set AES key[127:96].
__STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
Set AES to load seed for LFSR.
__STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
Indicate whether the AES start in MCU mode is enabled.
__STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
Indicate whether the AES is enabled.
__STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
Set AES key[223:192].
__STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
Set AES key size.
uint32_t * p_seed
Random seeds.
__STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
Get AES transfer blocks in DMA mode.