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52 #ifndef __GR55xx_HAL_XQSPI_H__
53 #define __GR55xx_HAL_XQSPI_H__
232 #define HAL_XQSPI_ERROR_NONE ((uint32_t)0x00000000)
233 #define HAL_XQSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
234 #define HAL_XQSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
235 #define HAL_XQSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
241 #define XQSPI_WORK_MODE_QSPI LL_XQSPI_MODE_QSPI
242 #define XQSPI_WORK_MODE_XIP LL_XQSPI_MODE_XIP
248 #define XQSPI_CACHE_MODE_DIS LL_XQSPI_CACHE_DIS
249 #define XQSPI_CACHE_MODE_EN LL_XQSPI_CACHE_EN
255 #define XQSPI_READ_CMD_READ LL_XQSPI_XIP_CMD_READ
256 #define XQSPI_READ_CMD_FAST_READ LL_XQSPI_XIP_CMD_FAST_READ
257 #define XQSPI_READ_CMD_DUAL_OUT_READ LL_XQSPI_XIP_CMD_DUAL_OUT_READ
258 #define XQSPI_READ_CMD_DUAL_IO_READ LL_XQSPI_XIP_CMD_DUAL_IO_READ
259 #define XQSPI_READ_CMD_QUAD_OUT_READ LL_XQSPI_XIP_CMD_QUAD_OUT_READ
260 #define XQSPI_READ_CMD_QUAD_IO_READ LL_XQSPI_XIP_CMD_QUAD_IO_READ
266 #define XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE)
268 #define XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE)
270 #define XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE)
272 #define XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE)
279 #define XQSPI_BAUD_RATE_64M LL_XQSPI_BAUD_RATE_64M
280 #define XQSPI_BAUD_RATE_48M LL_XQSPI_BAUD_RATE_48M
281 #define XQSPI_BAUD_RATE_32M LL_XQSPI_BAUD_RATE_32M
282 #define XQSPI_BAUD_RATE_24M LL_XQSPI_BAUD_RATE_24M
283 #define XQSPI_BAUD_RATE_16M LL_XQSPI_BAUD_RATE_16M
289 #define XQSPI_DATA_MODE_SPI LL_XQSPI_QSPI_FRF_SPI
290 #define XQSPI_DATA_MODE_DUALSPI LL_XQSPI_QSPI_FRF_DUALSPI
291 #define XQSPI_DATA_MODE_QUADSPI LL_XQSPI_QSPI_FRF_QUADSPI
297 #define XQSPI_FIFO_THRESHOLD_1_8 LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
298 #define XQSPI_FIFO_THRESHOLD_1_4 LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
299 #define XQSPI_FIFO_THRESHOLD_1_2 LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
300 #define XQSPI_FIFO_THRESHOLD_3_4 LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
301 #define XQSPI_FIFO_DEPTH LL_XQSPI_QSPI_FIFO_DEPTH
307 #define XQSPI_INSTSIZE_00_BITS (0)
308 #define XQSPI_INSTSIZE_08_BITS (1)
309 #define XQSPI_INSTSIZE_16_BITS (2)
315 #define XQSPI_ADDRSIZE_00_BITS (0)
316 #define XQSPI_ADDRSIZE_08_BITS (1)
317 #define XQSPI_ADDRSIZE_16_BITS (2)
318 #define XQSPI_ADDRSIZE_24_BITS (3)
319 #define XQSPI_ADDRSIZE_32_BITS (4)
325 #define XQSPI_INST_ADDR_ALL_IN_SPI (0)
326 #define XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1)
327 #define XQSPI_INST_ADDR_ALL_IN_SPIFRF (2)
333 #define XQSPI_FLAG_RFF LL_XQSPI_QSPI_STAT_RFF
334 #define XQSPI_FLAG_RFTF LL_XQSPI_QSPI_STAT_RFTF
335 #define XQSPI_FLAG_RFE LL_XQSPI_QSPI_STAT_RFE
336 #define XQSPI_FLAG_TFF LL_XQSPI_QSPI_STAT_TFF
337 #define XQSPI_FLAG_TFTF LL_XQSPI_QSPI_STAT_TFTF
338 #define XQSPI_FLAG_TFE LL_XQSPI_QSPI_STAT_TFE
339 #define XQSPI_FLAG_BUSY LL_XQSPI_QSPI_STAT_BUSY
345 #define XQSPI_DISABLE_PRESENT LL_XQSPI_DISABLE_PRESENT
346 #define XQSPI_ENABLE_PRESENT LL_XQSPI_ENABLE_PRESENT
352 #define HAL_XQSPI_RETRY_DEFAULT_VALUE ((uint32_t)1000)
365 #define __HAL_XQSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_XQSPI_STATE_RESET)
371 #define __HAL_XQSPI_ENABLE_QSPI(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, SSI_SSIEN_EN)
377 #define __HAL_XQSPI_DISABLE_QSPI(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI.SPIEN, SSI_SSIEN_EN)
383 #define __HAL_XQSPI_ENABLE_XIP(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->XIP.CTRL3, SSI_SSIEN_EN);\
384 while(!ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
390 #define __HAL_XQSPI_DISABLE_XIP(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->XIP.CTRL3, SSI_SSIEN_EN);\
391 while(ll_xqspi_get_xip_flag(__HANDLE__->p_instance))
397 #define __HAL_XQSPI_ENABLE_CACHE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
403 #define __HAL_XQSPI_DISABLE_CACHE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS)
418 #define __HAL_XQSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->QSPI.STAT, (__FLAG__)) != 0) ? SET : RESET)
431 #define IS_XQSPI_WORK_MODE(__MODE__) (((__MODE__) == XQSPI_WORK_MODE_QSPI) || \
432 ((__MODE__) == XQSPI_WORK_MODE_XIP))
438 #define IS_XQSPI_CACHE_MODE(__MODE__) (((__MODE__) == XQSPI_CACHE_MODE_DIS) || \
439 ((__MODE__) == XQSPI_CACHE_MODE_EN))
445 #define IS_XQSPI_READ_CMD(__CMD__) (((__CMD__) == XQSPI_READ_CMD_READ ) || \
446 ((__CMD__) == XQSPI_READ_CMD_FAST_READ ) || \
447 ((__CMD__) == XQSPI_READ_CMD_DUAL_OUT_READ) || \
448 ((__CMD__) == XQSPI_READ_CMD_DUAL_IO_READ ) || \
449 ((__CMD__) == XQSPI_READ_CMD_QUAD_OUT_READ) || \
450 ((__CMD__) == XQSPI_READ_CMD_QUAD_IO_READ ))
456 #define IS_XQSPI_BAUD_RATE(__BAUD__) (((__BAUD__) == XQSPI_BAUD_RATE_64M) || \
457 ((__BAUD__) == XQSPI_BAUD_RATE_48M) || \
458 ((__BAUD__) == XQSPI_BAUD_RATE_32M) || \
459 ((__BAUD__) == XQSPI_BAUD_RATE_24M) || \
460 ((__BAUD__) == XQSPI_BAUD_RATE_16M))
466 #define IS_XQSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == XQSPI_CLOCK_MODE_0) || \
467 ((__CLKMODE__) == XQSPI_CLOCK_MODE_1) || \
468 ((__CLKMODE__) == XQSPI_CLOCK_MODE_2) || \
469 ((__CLKMODE__) == XQSPI_CLOCK_MODE_3))
475 #define IS_XQSPI_FIFO_THRESHOLD(__THR__) (((__THR__) == XQSPI_FIFO_THRESHOLD_1_8) || \
476 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_4) || \
477 ((__THR__) == XQSPI_FIFO_THRESHOLD_1_2) || \
478 ((__THR__) == XQSPI_FIFO_THRESHOLD_3_4))
484 #define IS_XQSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == XQSPI_INSTSIZE_00_BITS) || \
485 ((__INST_SIZE__) == XQSPI_INSTSIZE_08_BITS) || \
486 ((__INST_SIZE__) == XQSPI_INSTSIZE_16_BITS))
492 #define IS_XQSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == XQSPI_ADDRSIZE_00_BITS) || \
493 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_08_BITS) || \
494 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_16_BITS) || \
495 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_24_BITS) || \
496 ((__ADDR_SIZE__) == XQSPI_ADDRSIZE_32_BITS))
502 #define IS_XQSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPI) || \
503 ((__MODE__) == XQSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
504 ((__MODE__) == XQSPI_INST_ADDR_ALL_IN_SPIFRF))
510 #define IS_XQSPI_DATA_MODE(__MODE__) (((__MODE__) == XQSPI_DATA_MODE_SPI) || \
511 ((__MODE__) == XQSPI_DATA_MODE_DUALSPI) || \
512 ((__MODE__) == XQSPI_DATA_MODE_QUADSPI))
__IO uint32_t tx_xfer_count
XQSPI Tx Transfer Counter
void(* xqspi_msp_init)(xqspi_handle_t *p_xqspi)
XQSPI init MSP callback
void hal_xqspi_msp_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI MSP.
uint32_t cache_mode
Specifies the cache mode for XIP mode.
hal_lock_t
HAL Lock structures definition.
hal_status_t hal_xqspi_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI peripheral.
uint32_t inst_size
Specifies the Instruction Size.
@ HAL_XQSPI_STATE_BUSY_INDIRECT_TX
Peripheral in indirect mode with transmission ongoing.
uint32_t inst_addr_mode
Specifies the Instruction and Address Mode.
uint32_t addr_size
Specifies the Address Size.
uint32_t hal_xqspi_get_rx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the RXFIFO threshold.
@ HAL_XQSPI_STATE_RESET
Peripheral not initialized
hal_status_t hal_xqspi_receive(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Receive an amount of data in blocking mode.
hal_xqspi_state_t hal_xqspi_get_state(xqspi_handle_t *p_xqspi)
Return the XQSPI handle state.
uint32_t hal_xqspi_get_error(xqspi_handle_t *p_xqspi)
Return the XQSPI error code.
XQSPI command Structure definition.
hal_xqspi_state_t
HAL XQSPI State Enumerations definition.
uint32_t work_mode
Specifies the work mode for XQSPI.
uint32_t addr
Specifies the Address to be sent (Size from 1 to 4 bytes according to AddressSize).
uint32_t retry
Retry for the XQSPI flag access
@ HAL_XQSPI_STATE_READY
Peripheral initialized and ready for use
uint32_t clock_mode
Specifies the Clock Mode.
uint8_t * p_rx_buffer
Pointer to XQSPI Rx transfer Buffer.
@ HAL_XQSPI_STATE_BUSY
Peripheral in indirect mode and busy
uint32_t baud_rate
Specifies the serial clock speed for transmit in both XIP and QSPI mode.
xqspi_init_t init
XQSPI communication parameters
__IO uint32_t rx_xfer_count
XQSPI Rx Transfer Counter
void hal_xqspi_set_xip_present_status(xqspi_handle_t *p_xqspi, uint32_t status)
Turn on/off present module, only in XIP mode.
HAL_XQSPI Callback function definition.
uint32_t read_cmd
Specifies the read command for transmit in XIP mode.
struct _xqspi_handle_t xqspi_handle_t
XQSPI handle Structure definition.
void hal_xqspi_set_retry(xqspi_handle_t *p_xqspi, uint32_t retry)
Set the XQSPI internal process repeat times value.
struct _xqspi_command_t xqspi_command_t
XQSPI command Structure definition.
XQSPI handle Structure definition.
hal_status_t hal_xqspi_set_rx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the RXFIFO threshold.
xqspi_regs_t * p_instance
XQSPI registers base address
hal_status_t hal_xqspi_transmit(xqspi_handle_t *p_xqspi, uint8_t *p_data, uint32_t length, uint32_t retry)
Transmit an amount of data in blocking mode.
@ HAL_XQSPI_STATE_ABORT
Peripheral with abort request ongoing
uint32_t length
Specifies the number of data to transfer.
void hal_xqspi_msp_deinit(xqspi_handle_t *p_xqspi)
De-initialize the XQSPI MSP.
hal_status_t hal_xqspi_command_transmit(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Transmit an amount of data with specified instruction and address in blocking mode.
XQSPI init Structure definition.
uint8_t * p_tx_buffer
Pointer to XQSPI Tx transfer Buffer.
hal_status_t
HAL Status structures definition.
__IO uint32_t rx_xfer_size
XQSPI Rx Transfer size
uint32_t data_mode
Specifies the Data Mode (used for dummy cycles and data phases).
@ HAL_XQSPI_STATE_BUSY_INDIRECT_RX
Peripheral in indirect mode with reception ongoing
hal_status_t hal_xqspi_init(xqspi_handle_t *p_xqspi)
Initialize the XQSPI according to the specified parameters in the xqspi_init_t and initialize the ass...
uint32_t hal_xqspi_get_tx_fifo_threshold(xqspi_handle_t *p_xqspi)
Get the TXFIFO threshold.
Header file containing functions prototypes of XQSPI LL library.
__IO hal_lock_t lock
Locking object
@ HAL_XQSPI_STATE_ERROR
Peripheral in error
struct _hal_xqspi_callback hal_xqspi_callback_t
HAL_XQSPI Callback function definition.
__IO hal_xqspi_state_t state
XQSPI communication state
__IO uint32_t error_code
XQSPI Error code
hal_status_t hal_xqspi_command_receive(xqspi_handle_t *p_xqspi, xqspi_command_t *p_cmd, uint8_t *p_data, uint32_t retry)
Receive an amount of data with specified instruction and address in blocking mode.
uint32_t inst
Specifies the Instruction to be sent.
struct _xqspi_init_t xqspi_init_t
XQSPI init Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
__IO uint32_t tx_xfer_size
XQSPI Tx Transfer size
uint32_t dummy_cycles
Specifies the Number of Dummy Cycles.
hal_status_t hal_xqspi_set_tx_fifo_threshold(xqspi_handle_t *p_xqspi, uint32_t threshold)
Set the TXFIFO threshold.
void(* xqspi_msp_deinit)(xqspi_handle_t *p_xqspi)
XQSPI de-init MSP callback