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52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
62 #if defined (I2C0) || defined (I2C1)
109 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_INTR_GEN_CALL
110 #define LL_I2C_INTR_STAT_RESTART_DET I2C_INTR_RESTART_DET
111 #define LL_I2C_INTR_STAT_GEN_CALL I2C_INTR_GEN_CALL
112 #define LL_I2C_INTR_STAT_START_DET I2C_INTR_START_DET
113 #define LL_I2C_INTR_STAT_STOP_DET I2C_INTR_STOP_DET
114 #define LL_I2C_INTR_STAT_ACTIVITY I2C_INTR_ACTIVITY
115 #define LL_I2C_INTR_STAT_RX_DONE I2C_INTR_RX_DONE
116 #define LL_I2C_INTR_STAT_TX_ABRT I2C_INTR_TX_ABRT
117 #define LL_I2C_INTR_STAT_RD_REQ I2C_INTR_RD_REQ
118 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_INTR_TX_EMPTY
119 #define LL_I2C_INTR_STAT_TX_OVER I2C_INTR_TX_OVER
120 #define LL_I2C_INTR_STAT_RX_FULL I2C_INTR_RX_FULL
121 #define LL_I2C_INTR_STAT_RX_OVER I2C_INTR_RX_OVER
122 #define LL_I2C_INTR_STAT_RX_UNDER I2C_INTR_RX_UNDER
124 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT
125 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT
126 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX
127 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST
128 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO
129 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST
130 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABRT_SRC_MST_DIS
131 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT
132 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT
133 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT
134 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET
135 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET
136 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ
137 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK
138 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK
139 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK
140 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK
141 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK
148 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INTR_GEN_CALL
149 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INTR_RESTART_DET
150 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INTR_GEN_CALL
151 #define LL_I2C_INTR_MASK_START_DET I2C_INTR_START_DET
152 #define LL_I2C_INTR_MASK_STOP_DET I2C_INTR_STOP_DET
153 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INTR_ACTIVITY
154 #define LL_I2C_INTR_MASK_RX_DONE I2C_INTR_RX_DONE
155 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INTR_TX_ABRT
156 #define LL_I2C_INTR_MASK_RD_REQ I2C_INTR_RD_REQ
157 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INTR_TX_EMPTY
158 #define LL_I2C_INTR_MASK_TX_OVER I2C_INTR_TX_OVER
159 #define LL_I2C_INTR_MASK_RX_FULL I2C_INTR_RX_FULL
160 #define LL_I2C_INTR_MASK_RX_OVER I2C_INTR_RX_OVER
161 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INTR_RX_UNDER
163 #define LL_I2C_INTR_MASK_ALL 0x00000FFFU
169 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
170 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CON_10BITADDR_MST
176 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U
177 #define LL_I2C_OWNADDRESS_10BIT I2C_CON_10BITADDR_SLV
184 #define LL_I2C_CMD_SLV_NONE 0x00000000U
185 #define LL_I2C_CMD_MST_WRITE 0x00000000U
186 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD
187 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP
188 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART
194 #define LL_I2C_SPEED_MODE_STANDARD I2C_CON_SPEED_STANDARD
195 #define LL_I2C_SPEED_MODE_FAST I2C_CON_SPEED_FAST
196 #define LL_I2C_SPEED_MODE_HIGH I2C_CON_SPEED_HIGH
202 #define LL_I2C_SPEED_100K (100000ul)
203 #define LL_I2C_SPEED_400K (400000ul)
204 #define LL_I2C_SPEED_1000K (1000000ul)
205 #define LL_I2C_SPEED_2000K (2000000ul)
211 #define LL_I2C_DIRECTION_NONE 0x00000000U
212 #define LL_I2C_DIRECTION_WRITE I2C_INTR_RX_FULL
213 #define LL_I2C_DIRECTION_READ I2C_INTR_RD_REQ
214 #define LL_I2C_DIRECTION_ERROR I2C_INTR_RX_FULL | I2C_INTR_RD_REQ
221 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U
222 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U
223 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U
224 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U
225 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U
226 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U
227 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U
228 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U
234 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U
235 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U
236 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U
237 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U
238 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U
239 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U
240 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U
241 #define LL_I2C_RX_FIFO_TH_FULL 0x00000007U
251 #define LL_I2C_DEFAULT_CONFIG \
253 .speed = LL_I2C_SPEED_400K, \
254 .own_address = 0x55U, \
255 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
277 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
285 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
298 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
308 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
309 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
346 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
370 CLEAR_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
389 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_IC_EN) == (I2C_ENABLE_STATUS_IC_EN));
408 SET_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
427 CLEAR_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
447 return (READ_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS) == (I2C_CON_MST_MODE | I2C_CON_SLV_DIS));
467 SET_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
487 CLEAR_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
506 return (READ_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC) == (I2C_ACK_GENERAL_CALL_ACK_GC));
532 SET_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
552 CLEAR_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
571 return (READ_BITS(I2Cx->CON, I2C_CON_RESTART_EN) == (I2C_CON_RESTART_EN));
595 SET_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
615 CLEAR_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
634 return (READ_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED) == (I2C_CON_STOP_DET_IF_ADDRESSED));
657 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_MST, addressing_mode);
679 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_10BITADDR_MST));
705 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_SLV, own_addr_size);
706 WRITE_REG(I2Cx->SAR, own_address);
727 WRITE_REG(I2Cx->SS_SCL_HCNT, count);
746 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_HCNT, I2C_SS_SCL_HCNT));
767 WRITE_REG(I2Cx->SS_SCL_LCNT, count);
786 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_LCNT, I2C_SS_SCL_LCNT));
807 WRITE_REG(I2Cx->FS_SCL_HCNT, count);
826 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_HCNT, I2C_FS_SCL_HCNT));
847 WRITE_REG(I2Cx->FS_SCL_LCNT, count);
866 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_LCNT, I2C_FS_SCL_LCNT));
887 WRITE_REG(I2Cx->HS_SCL_HCNT, count);
906 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_HCNT, I2C_HS_SCL_HCNT));
927 WRITE_REG(I2Cx->HS_SCL_LCNT, count);
946 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_LCNT, I2C_HS_SCL_LCNT));
967 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
986 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
1007 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
1026 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
1050 MODIFY_REG(I2Cx->CON, I2C_CON_SPEED, speed_mode);
1072 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_SPEED));
1093 WRITE_REG(I2Cx->HS_MADDR, code);
1112 return (uint32_t)(READ_BITS(I2Cx->HS_MADDR, I2C_HS_MADDR_HS_MAR));
1134 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_Pos);
1153 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_Pos);
1175 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_Pos);
1194 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_Pos);
1217 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP, time);
1236 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP));
1265 WRITE_REG(I2Cx->TX_TL, threshold);
1292 return (uint32_t)(READ_BITS(I2Cx->TX_TL, I2C_TX_TL_TXTL));
1321 WRITE_REG(I2Cx->RX_TL, threshold);
1348 return (uint32_t)(READ_BITS(I2Cx->RX_TL, I2C_RX_TL_RXTL));
1367 return (uint32_t)(READ_BITS(I2Cx->TXFLR, I2C_TXFLR_TXFLR));
1386 return (uint32_t)(READ_BITS(I2Cx->RXFLR, I2C_RXFLR_RXFLR));
1405 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT);
1424 return (READ_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT) == (I2C_ENABLE_ABORT));
1481 return (uint32_t)(READ_REG(I2Cx->TX_ABRT_SOURCE) & (~I2C_TX_ABRT_SRC_TX_FLUSH_CNT));
1500 return (uint32_t)(READ_BITS(I2Cx->TX_ABRT_SOURCE, I2C_TX_ABRT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos);
1549 SET_BITS(I2Cx->INTR_MASK, mask);
1592 CLEAR_BITS(I2Cx->INTR_MASK, mask);
1635 return (READ_BITS(I2Cx->INTR_MASK, mask) == (mask));
1654 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1673 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1692 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
1711 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1730 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1749 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
1768 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1787 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1806 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
1825 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1844 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1863 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
1882 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1901 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1920 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
1939 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1958 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1977 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
1996 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
2015 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
2034 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2053 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
2072 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
2091 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2110 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
2129 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
2148 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2167 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
2186 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
2205 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2224 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
2243 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
2262 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2281 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
2300 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
2319 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2338 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
2357 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
2376 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2395 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2414 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2433 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2485 return (uint32_t)(READ_REG(I2Cx->INTR_STAT));
2531 return (uint32_t)(READ_REG(I2Cx->RAW_INTR_STAT));
2552 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2573 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2594 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2615 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2636 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2657 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2678 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2699 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2720 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2741 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2762 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2783 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2804 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2825 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2846 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2867 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2888 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2909 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2930 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2951 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2972 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2993 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
3014 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
3035 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
3056 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
3077 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
3098 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
3119 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
3138 __IO uint32_t tmpreg;
3139 tmpreg = READ_REG(I2Cx->CLR_INTR);
3159 __IO uint32_t tmpreg;
3160 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
3180 __IO uint32_t tmpreg;
3181 tmpreg = READ_REG(I2Cx->CLR_START_DET);
3201 __IO uint32_t tmpreg;
3202 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
3222 __IO uint32_t tmpreg;
3223 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
3243 __IO uint32_t tmpreg;
3244 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
3264 __IO uint32_t tmpreg;
3265 tmpreg = READ_REG(I2Cx->CLR_TX_ABRT);
3285 __IO uint32_t tmpreg;
3286 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
3306 __IO uint32_t tmpreg;
3307 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
3327 __IO uint32_t tmpreg;
3328 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
3348 __IO uint32_t tmpreg;
3349 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
3371 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_SLV_ACTIVITY) == (I2C_STATUS_SLV_ACTIVITY));
3392 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_MST_ACTIVITY) == (I2C_STATUS_MST_ACTIVITY));
3413 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFF) == (I2C_STATUS_RFF));
3434 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFNE) == (I2C_STATUS_RFNE));
3455 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFE) == (I2C_STATUS_TFE));
3476 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFNF) == (I2C_STATUS_TFNF));
3497 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_ACTIVITY) == (I2C_STATUS_ACTIVITY));
3518 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_RX_LOST) == (I2C_ENABLE_STATUS_SLV_RX_LOST));
3539 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY) == (I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY));
3563 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
3582 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
3601 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE) == (I2C_DMA_CR_TDMAE));
3620 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3639 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3658 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE) == (I2C_DMA_CR_RDMAE));
3681 WRITE_REG(I2Cx->DMA_TDLR, level);
3700 return (uint32_t)(READ_BITS(I2Cx->DMA_TDLR, I2C_DMA_TDLR_DMATDL));
3725 WRITE_REG(I2Cx->DMA_RDLR, level);
3744 return (uint32_t)(READ_BITS(I2Cx->DMA_RDLR, I2C_DMA_RDLR_DMARDL));
3763 return ((uint32_t) & (I2Cx->DATA_CMD));
3790 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3809 return (uint32_t)(READ_BITS(I2Cx->TAR, I2C_TAR_ADDR) >> I2C_TAR_ADDR_Pos);
3835 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3860 return (uint32_t)(READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ | I2C_INTR_RX_FULL));
3879 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DAT));
3907 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
uint32_t own_addr_size
Specifies the device own address 1 size (7-bit or 10-bit).
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
__STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
uint32_t speed
Specifies the transfer speed.
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
LL I2C init Structure definition.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
__STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
uint32_t own_address
Specifies the device own address.
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.