52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
159 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
160 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
161 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
162 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
163 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
164 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
165 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
166 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
167 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
173 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
174 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
175 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
176 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
183 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U)
184 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC
185 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST
186 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST)
192 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
193 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
194 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
200 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
201 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
202 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
208 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
209 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
210 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
211 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
212 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
213 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
219 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
220 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
221 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
222 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
223 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
224 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
230 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
231 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
232 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
238 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
239 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
240 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
246 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
247 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
248 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
249 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
250 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
251 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
252 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
253 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
259 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
260 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
266 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
267 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
273 #define LL_DMA_PERIPH_SPIM_TX ((uint32_t)0x00000000U)
274 #define LL_DMA_PERIPH_SPIM_RX ((uint32_t)0x00000001U)
275 #define LL_DMA_PERIPH_SPIS_TX ((uint32_t)0x00000002U)
276 #define LL_DMA_PERIPH_SPIS_RX ((uint32_t)0x00000003U)
277 #define LL_DMA_PERIPH_QSPI0_TX ((uint32_t)0x00000004U)
278 #define LL_DMA_PERIPH_QSPI0_RX ((uint32_t)0x00000005U)
279 #define LL_DMA_PERIPH_I2C0_TX ((uint32_t)0x00000006U)
280 #define LL_DMA_PERIPH_I2C0_RX ((uint32_t)0x00000007U)
281 #define LL_DMA_PERIPH_I2C1_TX ((uint32_t)0x00000008U)
282 #define LL_DMA_PERIPH_I2C1_RX ((uint32_t)0x00000009U)
283 #define LL_DMA_PERIPH_I2S_S_TX ((uint32_t)0x00000008U)
284 #define LL_DMA_PERIPH_I2S_S_RX ((uint32_t)0x00000009U)
285 #define LL_DMA_PERIPH_UART0_TX ((uint32_t)0x0000000AU)
286 #define LL_DMA_PERIPH_UART0_RX ((uint32_t)0x0000000BU)
287 #define LL_DMA_PERIPH_QSPI1_TX ((uint32_t)0x0000000CU)
288 #define LL_DMA_PERIPH_QSPI1_RX ((uint32_t)0x0000000DU)
289 #define LL_DMA_PERIPH_I2S_M_TX ((uint32_t)0x0000000CU)
290 #define LL_DMA_PERIPH_I2S_M_RX ((uint32_t)0x0000000DU)
291 #define LL_DMA_PERIPH_SNSADC ((uint32_t)0x0000000EU)
292 #define LL_DMA_PERIPH_MEM ((uint32_t)0x0000000FU)
313 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
321 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
356 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
379 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
398 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
428 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
456 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
486 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
516 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
545 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
573 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
601 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
644 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
645 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC,
679 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
711 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
744 __STATIC_INLINE
void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
746 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
779 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
811 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
842 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
874 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
905 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
937 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
968 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
1000 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1031 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1063 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1094 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1126 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1157 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1194 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1230 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1260 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1290 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1328 uint32_t src_address,
1329 uint32_t dst_address,
1332 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1333 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1334 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1363 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1392 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1420 return READ_REG(DMAx->CHANNEL[channel].SAR);
1448 return READ_REG(DMAx->CHANNEL[channel].DAR);
1478 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1479 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1510 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1511 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1540 return READ_REG(DMAx->CHANNEL[channel].SAR);
1569 return READ_REG(DMAx->CHANNEL[channel].DAR);
1617 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1664 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1712 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1759 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos;
1793 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1794 src_handshaking | dst_handshaking);
1823 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1824 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1852 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1882 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1883 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1884 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1913 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1914 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1943 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1944 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1972 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2002 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2003 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2004 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2033 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2034 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2059 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2078 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2097 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2116 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2135 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2163 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2191 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2219 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2247 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2275 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2303 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2322 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2341 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2360 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2379 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2398 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2417 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
2436 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
2455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
2483 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2502 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2521 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2540 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2559 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2578 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2597 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
2616 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
2635 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
2663 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2682 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2701 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2720 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2739 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2758 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2777 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
2796 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
2815 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
2843 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2862 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2881 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2900 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2919 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2938 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2957 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
2976 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
2995 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
3023 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3042 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3061 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3080 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3099 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3118 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3156 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3175 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3203 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3222 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3241 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3260 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3279 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3298 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3317 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3336 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3355 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3383 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3402 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3421 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3440 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3459 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3478 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
3497 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
3516 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
3535 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
3563 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
3582 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
3601 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
3620 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
3639 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
3658 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
3677 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
3696 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
3715 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
3743 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
3762 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
3781 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
3800 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
3819 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
3838 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
3857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
3876 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
3895 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
3923 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
3942 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
3961 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
3980 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3999 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4018 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4037 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4056 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4075 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4109 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4137 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4165 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4193 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4221 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4249 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4277 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4305 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4333 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4361 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4389 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4417 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4445 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4473 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4501 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4529 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4557 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);