+ Collaboration diagram for ADC CLOCK:

Macros

#define LL_ADC_CLK_16   (0x00000000UL)
 16 MHz
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#define LL_ADC_CLK_8   (1UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
 8 MHz
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#define LL_ADC_CLK_4   (2UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
 4 MHz
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#define LL_ADC_CLK_2   (3UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
 2 MHz
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#define LL_ADC_CLK_1P6   (4UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
 1.6 MHz
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#define LL_ADC_CLK_1   (5UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
 1 MHz
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Detailed Description

Macro Definition Documentation

◆ LL_ADC_CLK_1

#define LL_ADC_CLK_1   (5UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)

1 MHz

Definition at line 132 of file gr55xx_ll_adc.h.

◆ LL_ADC_CLK_16

#define LL_ADC_CLK_16   (0x00000000UL)

16 MHz

Definition at line 127 of file gr55xx_ll_adc.h.

◆ LL_ADC_CLK_1P6

#define LL_ADC_CLK_1P6   (4UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)

1.6 MHz

Definition at line 131 of file gr55xx_ll_adc.h.

◆ LL_ADC_CLK_2

#define LL_ADC_CLK_2   (3UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)

2 MHz

Definition at line 130 of file gr55xx_ll_adc.h.

◆ LL_ADC_CLK_4

#define LL_ADC_CLK_4   (2UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)

4 MHz

Definition at line 129 of file gr55xx_ll_adc.h.

◆ LL_ADC_CLK_8

#define LL_ADC_CLK_8   (1UL << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)

8 MHz

Definition at line 128 of file gr55xx_ll_adc.h.