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52 #ifndef __GR55xx_HAL_I2S_H__
53 #define __GR55xx_HAL_I2S_H__
114 #if I2S_CHANNEL_NUM > 1
115 uint32_t channel_active;
208 #define I2S_DIRECTION_FULL_DUPLEX LL_I2S_FULL_DUPLEX
209 #define I2S_DIRECTION_SIMPLEX_TX LL_I2S_SIMPLEX_TX
210 #define I2S_DIRECTION_SIMPLEX_RX LL_I2S_SIMPLEX_RX
216 #define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000)
217 #define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001)
218 #define HAL_I2S_ERROR_TRANSFER ((uint32_t)0x00000002)
219 #define HAL_I2S_ERROR_DMA ((uint32_t)0x00000004)
220 #define HAL_I2S_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
221 #define HAL_I2S_ERROR_TX_OVERFLOW ((uint32_t)0x00000010)
222 #define HAL_I2S_ERROR_RX_OVERFLOW ((uint32_t)0x00000020)
228 #define I2S_DATASIZE_12BIT LL_I2S_DATASIZE_12BIT
229 #define I2S_DATASIZE_16BIT LL_I2S_DATASIZE_16BIT
230 #define I2S_DATASIZE_20BIT LL_I2S_DATASIZE_20BIT
231 #define I2S_DATASIZE_24BIT LL_I2S_DATASIZE_24BIT
232 #define I2S_DATASIZE_32BIT LL_I2S_DATASIZE_32BIT
238 #define I2S_CLOCK_SRC_96M LL_I2S_CLOCK_SRC_96M
239 #define I2S_CLOCK_SRC_32M LL_I2S_CLOCK_SRC_32M
245 #define I2S_TX_FIFO_LEVEL_MAX 16
246 #define I2S_RX_FIFO_LEVEL_MAX 16
252 #define I2S_FLAG_TXFO LL_I2S_STATUS_TXFO
253 #define I2S_FLAG_TXFE LL_I2S_STATUS_TXFE
254 #define I2S_FLAG_RXFO LL_I2S_STATUS_RXFO
255 #define I2S_FLAG_RXDA LL_I2S_STATUS_RXDA
261 #define I2S_IT_TXFO LL_I2S_INT_TXFO
262 #define I2S_IT_TXFE LL_I2S_INT_TXFE
263 #define I2S_IT_RXFO LL_I2S_INT_RXFO
264 #define I2S_IT_RXDA LL_I2S_INT_RXDA
270 #define HAL_I2S_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)
284 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_I2S_STATE_RESET)
290 #define __HAL_I2S_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->ENABLE, I2S_ENABLE_EN)
296 #define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->ENABLE, I2S_ENABLE_EN)
302 #define __HAL_I2S_ENABLE_CLOCK(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->CLKEN, I2S_CLKEN_EN)
308 #define __HAL_I2S_DISABLE_CLOCK(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->CLKEN, I2S_CLKEN_EN)
314 #define __HAL_I2S_ENABLE_TX_BLOCK(__HANDLE__) ll_i2s_enable_txblock((__HANDLE__)->p_instance)
320 #define __HAL_I2S_DISABLE_TX_BLOCK(__HANDLE__) ll_i2s_disable_txblock((__HANDLE__)->p_instance)
326 #define __HAL_I2S_ENABLE_RX_BLOCK(__HANDLE__) ll_i2s_enable_rxblock((__HANDLE__)->p_instance)
332 #define __HAL_I2S_DISABLE_RX_BLOCK(__HANDLE__) ll_i2s_disable_rxblock((__HANDLE__)->p_instance)
339 #define __HAL_I2S_ENABLE_TX_CHANNEL(__HANDLE__, __CH__) ll_i2s_enable_tx((__HANDLE__)->p_instance, (__CH__))
346 #define __HAL_I2S_DISABLE_TX_CHANNEL(__HANDLE__, __CH__) ll_i2s_disable_tx((__HANDLE__)->p_instance, (__CH__))
353 #define __HAL_I2S_ENABLE_RX_CHANNEL(__HANDLE__, __CH__) ll_i2s_enable_rx((__HANDLE__)->p_instance, (__CH__))
360 #define __HAL_I2S_DISABLE_RX_CHANNEL(__HANDLE__, __CH__) ll_i2s_disable_rx((__HANDLE__)->p_instance, (__CH__))
366 #define __HAL_I2S_FLUSH_TX_FIFO(__HANDLE__) ll_i2s_clr_txfifo_all((__HANDLE__)->p_instance)
372 #define __HAL_I2S_FLUSH_RX_FIFO(__HANDLE__) ll_i2s_clr_rxfifo_all((__HANDLE__)->p_instance)
378 #define __HAL_I2S_ENABLE_DMA(__HANDLE__) ll_i2s_enable_dma(__HANDLE__->p_instance)
384 #define __HAL_I2S_DISABLE_DMA(__HANDLE__) ll_i2s_disable_dma(__HANDLE__->p_instance)
390 #define __HAL_I2S_RESET_TXDMA(__HANDLE__) WRITE_REG((__HANDLE__)->p_instance->TXDMA_RST, I2S_TXDMA_RST)
396 #define __HAL_I2S_RESET_RXDMA(__HANDLE__) WRITE_REG((__HANDLE__)->p_instance->RXDMA_RST, I2S_RXDMA_RST)
408 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTMASK, (__INTERRUPT__))
420 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTMASK, (__INTERRUPT__))
432 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].INTSTAT, (__FLAG__)) != 0) ? SET : RESET)
442 #define __HAL_I2S_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
443 if ((__FLAG__) & I2S_FLAG_RXFO) \
445 READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].RXOVR, I2S_RXOVR_RXCHO);\
447 if ((__FLAG__) & I2S_FLAG_TXFO) \
449 READ_BITS((__HANDLE__)->p_instance->I2S_CHANNEL[0].TXOVR, I2S_TXOVR_TXCHO);\
464 #define IS_I2S_DIRECTION(__MODE__) (((__MODE__) == I2S_DIRECTION_FULL_DUPLEX) || \
465 ((__MODE__) == I2S_DIRECTION_SIMPLEX_TX) || \
466 ((__MODE__) == I2S_DIRECTION_SIMPLEX_RX))
472 #define IS_I2S_DATASIZE(__DATASIZE__) (((__DATASIZE__) == I2S_DATASIZE_12BIT) || \
473 ((__DATASIZE__) == I2S_DATASIZE_16BIT) || \
474 ((__DATASIZE__) == I2S_DATASIZE_20BIT) || \
475 ((__DATASIZE__) == I2S_DATASIZE_24BIT) || \
476 ((__DATASIZE__) == I2S_DATASIZE_32BIT))
482 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_POLARITY_LOW) || \
483 ((__CPOL__) == I2S_POLARITY_HIGH))
489 #define IS_I2S_AUDIO_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) > 0) && ((__FREQUENCY__) <= 1500000))
495 #define IS_I2S_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= I2S_TX_FIFO_LEVEL_MAX))
uint32_t data_size
Specifies the data size for I2S communication.
@ HAL_I2S_STATE_BUSY_TX
Data Transmission process is ongoing
hal_status_t hal_i2s_init(i2s_handle_t *p_i2s)
Initialize the I2S according to the specified parameters in the i2s_init_t and initialize the associa...
hal_status_t hal_i2s_receive_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode with Interrupt.
hal_lock_t
HAL Lock structures definition.
hal_status_t hal_i2s_deinit(i2s_handle_t *p_i2s)
De-initialize the I2S peripheral.
uint16_t * p_rx_buffer
Pointer to I2S RX transfer Buffer.
hal_status_t hal_i2s_transmit_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length)
Transmit and Receive an amount of data in non-blocking mode with DMA.
void hal_i2s_tx_cplt_callback(i2s_handle_t *p_i2s)
TX Transfer completed callback.
@ HAL_I2S_STATE_BUSY_RX
Data Reception process is ongoing
hal_status_t hal_i2s_receive(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode.
void(* write_fifo)(struct _i2s_handle *p_i2s)
Pointer to I2S Tx transfer FIFO write function.
@ HAL_I2S_STATE_ABORT
Peripheral with abort request ongoing
i2s_regs_t * p_instance
I2S registers base address
void hal_i2s_error_callback(i2s_handle_t *p_i2s)
I2S error callback.
void(* read_fifo)(struct _i2s_handle *p_i2s)
Pointer to I2S Rx transfer FIFO read function
hal_status_t hal_i2s_abort(i2s_handle_t *p_i2s)
Abort ongoing transfer (blocking mode).
struct _i2s_init i2s_init_t
I2S init Structure definition.
__IO uint32_t error_code
I2S Error code
uint16_t * p_tx_buffer
Pointer to I2S TX transfer Buffer.
hal_status_t hal_i2s_receive_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode with DMA.
@ HAL_I2S_STATE_RESET
Peripheral not initialized
uint32_t audio_freq
Specifies the frequency selected for the I2S communication.
hal_status_t hal_i2s_transmit_receive_it(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
void(* i2s_tx_cplt_callback)(i2s_handle_t *p_i2s)
I2S tx transfer completed callbac
void(* i2s_msp_init)(i2s_handle_t *p_i2s)
I2S init MSP callback
void(* i2s_msp_deinit)(i2s_handle_t *p_i2s)
I2S de-init MSP callback
i2s_init_t init
I2S communication parameters
void hal_i2s_tx_rx_cplt_callback(i2s_handle_t *p_i2s)
TX/RX Transfer completed callback.
hal_status_t hal_i2s_transmit_it(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode with Interrupt.
__IO uint32_t tx_xfer_count
I2S TX Transfer Counter
@ HAL_I2S_STATE_READY
Peripheral initialized and ready for use
void hal_i2s_rx_cplt_callback(i2s_handle_t *p_i2s)
RX Transfer completed callback.
uint32_t hal_i2s_get_tx_fifo_threshold(i2s_handle_t *p_i2s)
Get the TX FIFO threshold.
hal_status_t hal_i2s_transmit_dma(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode with DMA.
uint32_t timeout
Timeout for the I2S memory access.
uint32_t clock_source
Specifies the source of the I2S clock.
struct _i2s_handle i2s_handle_t
I2S handle Structure definition.
hal_status_t hal_i2s_resume_reg(i2s_handle_t *p_i2s)
Restore some registers related to I2S configuration after sleep.
void(* i2s_tx_rx_cplt_callback)(i2s_handle_t *p_i2s)
I2S tx/rx transfer completed callback
@ HAL_I2S_STATE_BUSY
An internal process is ongoing
Header file containing functions prototypes of I2S LL library.
hal_i2s_state_t hal_i2s_get_state(i2s_handle_t *p_i2s)
Return the I2S handle state.
uint32_t hal_i2s_get_rx_fifo_threshold(i2s_handle_t *p_i2s)
Get the RX FIFO threshold.
I2S handle Structure definition.
__IO hal_i2s_state_t state
I2S communication state
hal_status_t hal_i2s_start_clock(i2s_handle_t *p_i2s)
Start the I2S master clock.
__IO uint32_t tx_xfer_size
I2S TX Transfer size
uint32_t retention[7]
I2S important register information.
void(* i2s_rx_cplt_callback)(i2s_handle_t *p_i2s)
I2S rx transfer completed callback
hal_status_t hal_i2s_transmit_receive(i2s_handle_t *p_i2s, uint16_t *p_tx_data, uint16_t *p_rx_data, uint32_t length, uint32_t timeout)
Transmit and Receive an amount of data in blocking mode.
I2S init Structure definition.
HAL_I2S Callback function definition.
hal_status_t
HAL Status structures definition.
__IO hal_lock_t lock
Locking object
@ HAL_I2S_STATE_ERROR
Peripheral in error
@ HAL_I2S_STATE_BUSY_TX_RX
Data Transmission and Reception process is ongoing
dma_handle_t * p_dmarx
I2S RX DMA Handle parameters
void(* i2s_error_callback)(i2s_handle_t *p_i2s)
I2S error callback
hal_status_t hal_i2s_suspend_reg(i2s_handle_t *p_i2s)
Suspend some registers related to I2S configuration before sleep.
hal_status_t hal_i2s_transmit(i2s_handle_t *p_i2s, uint16_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode.
struct _hal_i2s_callback hal_i2s_callback_t
HAL_I2S Callback function definition.
hal_status_t hal_i2s_set_tx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold)
Set the TX FIFO threshold.
uint32_t hal_i2s_get_error(i2s_handle_t *p_i2s)
Return the I2S error code.
void hal_i2s_msp_init(i2s_handle_t *p_i2s)
Initialize the I2S MSP.
__IO uint32_t rx_xfer_count
I2S RX Transfer Counter
void hal_i2s_irq_handler(i2s_handle_t *p_i2s)
Handle I2S interrupt request.
hal_i2s_state_t
HAL I2S State Enumerations definition.
void hal_i2s_msp_deinit(i2s_handle_t *p_i2s)
De-initialize the I2S MSP.
hal_status_t hal_i2s_stop_clock(i2s_handle_t *p_i2s)
Stop the I2S master clock.
DMA handle Structure definition.
dma_handle_t * p_dmatx
I2S TX DMA Handle parameters
This file contains HAL common definitions, enumeration, macros and structures definitions.
__IO uint32_t rx_xfer_size
I2S RX Transfer size
hal_status_t hal_i2s_set_rx_fifo_threshold(i2s_handle_t *p_i2s, uint32_t threshold)
Set the RX FIFO threshold.