Macros
QSPI Private Macros
Peripheral Driver » HAL Driver » QSPI » Defines
Collaboration diagram for QSPI Private Macros:

## Macros
#define | IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
| Check if QSPI Clock Prescaler is valid. More...
#define | IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= 7))
| Check if QSPI FIFO Threshold is valid. More...
#define | IS_QSPI_CLOCK_MODE(__CLKMODE__)
| Check if QSPI Clock Mode is valid. More...
#define | IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__)
| Check if QSPI Instruction Size is valid. More...
#define | IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__)
| Check if QSPI Address Size is valid. More...
#define | IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
| Check if QSPI Dummy Cycle is valid. More...
#define | IS_QSPI_INSTADDR_MODE(__MODE__)
| Check if QSPI Instruction and Address Mode is valid. More...
#define | IS_QSPI_DATA_MODE(__MODE__)
| Check if QSPI Data Mode is valid. More...

## Detailed Description

## Macro Definition Documentation

## ◆ IS_QSPI_ADDRESS_SIZE

#define IS_QSPI_ADDRESS_SIZE | ( |  | __ADDR_SIZE__ | ) |

Value:
(((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))

Check if QSPI Address Size is valid.

Parameters

  <strong>ADDR_SIZE</strong> | QSPI Address Size .

Return values

  SET | (ADDR_SIZE is valid) or RESET (ADDR_SIZE is invalid)

Definition at line 526 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CLOCK_MODE

#define IS_QSPI_CLOCK_MODE | ( |  | __CLKMODE__ | ) |

Value:
(((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
((__CLKMODE__) == QSPI_CLOCK_MODE_3))

Check if QSPI Clock Mode is valid.

Parameters

  <strong>CLKMODE</strong> | QSPI Clock Mode.

Return values

  SET | (CLKMODE is valid) or RESET (CLKMODE is invalid)

Definition at line 508 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_CLOCK_PRESCALER

#define IS_QSPI_CLOCK_PRESCALER | ( |  | __PRESCALER__ | ) | ((__PRESCALER__) <= 0xFFFF)

Check if QSPI Clock Prescaler is valid.

Parameters

  <strong>PRESCALER</strong> | QSPI Clock Prescaler.

Return values

  SET | (PRESCALER is valid) or RESET (PRESCALER is invalid)

Definition at line 496 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_DATA_MODE

#define IS_QSPI_DATA_MODE | ( |  | __MODE__ | ) |

Value:
(((__MODE__) == QSPI_DATA_MODE_SPI) || \
((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
((__MODE__) == QSPI_DATA_MODE_QUADSPI))

Check if QSPI Data Mode is valid.

Parameters

  <strong>MODE</strong> | QSPI Data Mode.

Return values

  SET | (MODE is valid) or RESET (MODE is invalid)

Definition at line 554 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_DUMMY_CYCLES

#define IS_QSPI_DUMMY_CYCLES | ( |  | __DCY__ | ) | ((__DCY__) <= 31)

Check if QSPI Dummy Cycle is valid.

Parameters

  <strong>DCY</strong> | QSPI Dummy Cycle.

Return values

  SET | (DCY is valid) or RESET (DCY is invalid)

Definition at line 540 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_FIFO_THRESHOLD

#define IS_QSPI_FIFO_THRESHOLD | ( |  | __THR__ | ) | (((__THR__) >= 0) && ((__THR__) <= 7))

Check if QSPI FIFO Threshold is valid.

Parameters

  <strong>THR</strong> | QSPI FIFO Threshold.

Return values

  SET | (THR is valid) or RESET (THR is invalid)

Definition at line 502 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_INSTADDR_MODE

#define IS_QSPI_INSTADDR_MODE | ( |  | __MODE__ | ) |

Value:
(((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))

Check if QSPI Instruction and Address Mode is valid.

Parameters

  <strong>MODE</strong> | QSPI Instruction and Address Mode.

Return values

  SET | (MODE is valid) or RESET (MODE is invalid)

Definition at line 546 of file gr55xx_hal_qspi.h.

## ◆ IS_QSPI_INSTRUCTION_SIZE

#define IS_QSPI_INSTRUCTION_SIZE | ( |  | __INST_SIZE__ | ) |

Value:
(((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))

Check if QSPI Instruction Size is valid.

Parameters

  <strong>INST_SIZE</strong> | QSPI Instruction Size.

Return values

  SET | (INST_SIZE is valid) or RESET (INST_SIZE is invalid)

Definition at line 517 of file gr55xx_hal_qspi.h.

QSPI_ADDRSIZE_04_BITS
#define QSPI_ADDRSIZE_04_BITS
4-bit address
Definition: gr55xx_hal_qspi.h:281
QSPI_CLOCK_MODE_2
#define QSPI_CLOCK_MODE_2
Inactive state of CLK is high; CLK toggles at the start of the first data bit
Definition: gr55xx_hal_qspi.h:254
QSPI_ADDRSIZE_00_BITS
#define QSPI_ADDRSIZE_00_BITS
0-bit address
Definition: gr55xx_hal_qspi.h:280
QSPI_ADDRSIZE_08_BITS
#define QSPI_ADDRSIZE_08_BITS
8-bit address
Definition: gr55xx_hal_qspi.h:282
QSPI_ADDRSIZE_16_BITS
#define QSPI_ADDRSIZE_16_BITS
16-bit address
Definition: gr55xx_hal_qspi.h:284
QSPI_CLOCK_MODE_1
#define QSPI_CLOCK_MODE_1
Inactive state of CLK is low; CLK toggles in the middle of the first data bit
Definition: gr55xx_hal_qspi.h:252
QSPI_INSTSIZE_08_BITS
#define QSPI_INSTSIZE_08_BITS
8-bit Instruction
Definition: gr55xx_hal_qspi.h:273
QSPI_INSTSIZE_00_BITS
#define QSPI_INSTSIZE_00_BITS
0-bit (No Instruction)
Definition: gr55xx_hal_qspi.h:271
QSPI_ADDRSIZE_28_BITS
#define QSPI_ADDRSIZE_28_BITS
28-bit address
Definition: gr55xx_hal_qspi.h:287
QSPI_INST_ADDR_ALL_IN_SPI
#define QSPI_INST_ADDR_ALL_IN_SPI
Instruction and address are sent in SPI mode.
Definition: gr55xx_hal_qspi.h:330
QSPI_INST_ADDR_ALL_IN_SPIFRF
#define QSPI_INST_ADDR_ALL_IN_SPIFRF
Instruction and address are sent in Daul/Quad SPI mode.
Definition: gr55xx_hal_qspi.h:332
QSPI_ADDRSIZE_20_BITS
#define QSPI_ADDRSIZE_20_BITS
20-bit address
Definition: gr55xx_hal_qspi.h:285
QSPI_INSTSIZE_16_BITS
#define QSPI_INSTSIZE_16_BITS
16-bit Instruction
Definition: gr55xx_hal_qspi.h:274
QSPI_CLOCK_MODE_3
#define QSPI_CLOCK_MODE_3
Inactive state of CLK is high; CLK toggles in the middle of the first data bit
Definition: gr55xx_hal_qspi.h:256
QSPI_INSTSIZE_04_BITS
#define QSPI_INSTSIZE_04_BITS
4-bit Instruction
Definition: gr55xx_hal_qspi.h:272
QSPI_DATA_MODE_SPI
#define QSPI_DATA_MODE_SPI
Standard SPI Frame Format
Definition: gr55xx_hal_qspi.h:263
QSPI_DATA_MODE_QUADSPI
#define QSPI_DATA_MODE_QUADSPI
Quad SPI Frame Format
Definition: gr55xx_hal_qspi.h:265
QSPI_ADDRSIZE_12_BITS
#define QSPI_ADDRSIZE_12_BITS
12-bit address
Definition: gr55xx_hal_qspi.h:283
QSPI_CLOCK_MODE_0
#define QSPI_CLOCK_MODE_0
Inactive state of CLK is low; CLK toggles at the start of the first data bit
Definition: gr55xx_hal_qspi.h:250
QSPI_DATA_MODE_DUALSPI
#define QSPI_DATA_MODE_DUALSPI
Dual SPI Frame Format
Definition: gr55xx_hal_qspi.h:264
QSPI_ADDRSIZE_32_BITS
#define QSPI_ADDRSIZE_32_BITS
32-bit address
Definition: gr55xx_hal_qspi.h:288
QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
#define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
Instruction is sent in SPI mode, and address is sent in Daul/Quad SPI mode.
Definition: gr55xx_hal_qspi.h:331
QSPI_ADDRSIZE_24_BITS
#define QSPI_ADDRSIZE_24_BITS
24-bit address
Definition: gr55xx_hal_qspi.h:286