gr55xx_hal_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_DMA DMA
47 * @brief DMA HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_ll_dma.h"
61 #include "gr55xx_hal_def.h"
62
63 /* Exported types ------------------------------------------------------------*/
64 /** @addtogroup HAL_DMA_ENUMERATIONS Enumerations
65 * @{
66 */
67
68 /** @defgroup HAL_DMA_state HAL DMA state
69 * @{
70 */
71
72 /**
73 * @brief HAL DMA State Enumerations definition
74 */
75 typedef enum
76 {
77 HAL_DMA_STATE_RESET = 0x00U, /**< DMA not yet initialized or disabled */
78 HAL_DMA_STATE_READY = 0x01U, /**< DMA process success and ready for use */
79 HAL_DMA_STATE_BUSY = 0x02U, /**< DMA process is ongoing */
80 HAL_DMA_STATE_TIMEOUT = 0x03U, /**< DMA timeout state */
81 HAL_DMA_STATE_ERROR = 0x04U, /**< DMA error state */
82 } hal_dma_state_t;
83 /** @} */
84
85 /** @defgroup HAL_DMA_channel HAL DMA channel
86 * @{
87 */
88
89 /**
90 * @brief HAL DMA Channel Enumerations definition
91 */
92 typedef enum
93 {
94 DMA_Channel0 = 0U, /**< Channel 0 */
95 DMA_Channel1 = 1U, /**< Channel 1 */
96 DMA_Channel2 = 2U, /**< Channel 2 */
97 DMA_Channel3 = 3U, /**< Channel 3 */
98 DMA_Channel4 = 4U, /**< Channel 4 */
99 DMA_Channel5 = 5U, /**< Channel 5 */
100 DMA_Channel6 = 6U, /**< Channel 6 */
101 DMA_Channel7 = 7U, /**< Channel 7 */
102 } dma_channel_t;
103 /** @} */
104
105 /** @defgroup HAL_DMA_callback_ID HAL DMA callback ID
106 * @{
107 */
108
109 /**
110 * @brief HAL DMA Callback ID Enumerations definition
111 */
112 typedef enum
113 {
114 HAL_DMA_XFER_TFR_CB_ID = 0x00, /**< Full transfer */
115 HAL_DMA_XFER_BLK_CB_ID = 0x01, /**< Block transfer */
116 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /**< Error */
117 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /**< Abort */
118 HAL_DMA_XFER_ALL_CB_ID = 0x04 /**< All */
119 } hal_dma_callback_id_t;
120 /** @} */
121
122 /** @} */
123
124
125 /** @addtogroup HAL_DMA_STRUCTURES Structures
126 * @{
127 */
128
129 /** @defgroup DMA_Configuration DMA Configuration
130 * @{
131 */
132
133 /**
134 * @brief DMA Configuration Structure definition
135 */
136 typedef struct _dma_init
137 {
138 uint32_t src_request; /**< Specifies the source request selected for the specified channel.
139 This parameter can be a value of @ref DMA_request */
140
141 uint32_t dst_request; /**< Specifies the destination request selected for the specified channel.
142 This parameter can be a value of @ref DMA_request */
143
144 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
145 from memory to memory or from peripheral to memory.
146 This parameter can be a value of @ref DMA_Data_transfer_direction */
147
148 uint32_t src_increment; /**< Specifies whether the srouce address register should be incremented or decrement or not.
149 This parameter can be a value of @ref DMA_Source_incremented_mode */
150
151 uint32_t dst_increment; /**< Specifies whether the destination address register should be incremented or decrement or not.
152 This parameter can be a value of @ref DMA_Destination_incremented_mode */
153
154 uint32_t src_data_alignment; /**< Specifies the source data width.
155 This parameter can be a value of @ref DMA_Source_data_size */
156
157 uint32_t dst_data_alignment; /**< Specifies the destination data width.
158 This parameter can be a value of @ref DMA_Destination_data_size */
159
160 uint32_t mode; /**< Specifies the operation mode of the DMA Channel(Normal or Circular).
161 This parameter can be a value of @ref DMA_mode
162 @note The circular buffer mode cannot be used if the memory-to-memory
163 data transfer is configured on the selected Channel */
164
165 uint32_t priority; /**< Specifies the software priority for the DMA Channel.
166 This parameter can be a value of @ref DMA_Priority_level */
167 } dma_init_t;
168
169 /** @} */
170
171 /** @defgroup DMA_handle DMA handle
172 * @{
173 */
174
175 /**
176 * @brief DMA handle Structure definition
177 */
178 typedef struct _dma_handle
179 {
180 dma_channel_t channel; /**< DMA Channel Number */
181
182 dma_init_t init; /**< DMA communication parameters */
183
184 hal_lock_t lock; /**< DMA locking object */
185
186 __IO hal_dma_state_t state; /**< DMA transfer state */
187
188 void *p_parent; /**< Parent object state */
189
190 void (* xfer_tfr_callback)(struct _dma_handle *p_dma); /**< DMA transfer complete callback */
191
192 void (* xfer_blk_callback)(struct _dma_handle *p_dma); /**< DMA block complete callback */
193
194 void (* xfer_error_callback)(struct _dma_handle *p_dma); /**< DMA transfer error callback */
195
196 void (* xfer_abort_callback)(struct _dma_handle *p_dma); /**< DMA transfer abort callback */
197
198 __IO uint32_t error_code; /**< DMA Error code */
199
200 uint32_t retention[5]; /**< DMA important register information. */
201 } dma_handle_t;
202
203 /** @} */
204
205 /** @} */
206
207
208 /**
209 * @defgroup HAL_DMA_MACRO Defines
210 * @{
211 */
212
213 /* Exported constants --------------------------------------------------------*/
214 /** @defgroup DMA_Exported_Constants DMA Exported Constants
215 * @{
216 */
217
218 /** @defgroup DMA_Error_Code DMA Error Code
219 * @{
220 */
221 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /**< No error */
222 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /**< Transfer error */
223 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /**< no ongoing transfer */
224 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /**< Timeout error */
225 /** @} */
226
227 /** @defgroup DMA_request DMA request definitions
228 * @{
229 */
230 #define DMA_REQUEST_SPIM_TX LL_DMA_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
231 #define DMA_REQUEST_SPIM_RX LL_DMA_PERIPH_SPIM_RX /**< DMA SPIM receive request */
232 #define DMA_REQUEST_SPIS_TX LL_DMA_PERIPH_SPIS_TX /**< DMA SPIS transmit request */
233 #define DMA_REQUEST_SPIS_RX LL_DMA_PERIPH_SPIS_RX /**< DMA SPIS receive request */
234 #define DMA_REQUEST_QSPI0_TX LL_DMA_PERIPH_QSPI0_TX /**< DMA QSPI0 transmit request */
235 #define DMA_REQUEST_QSPI0_RX LL_DMA_PERIPH_QSPI0_RX /**< DMA QSPI0 receive request */
236 #define DMA_REQUEST_I2C0_TX LL_DMA_PERIPH_I2C0_TX /**< DMA I2C0 transmit request */
237 #define DMA_REQUEST_I2C0_RX LL_DMA_PERIPH_I2C0_RX /**< DMA I2C0 receive request */
238 #define DMA_REQUEST_I2C1_TX LL_DMA_PERIPH_I2C1_TX /**< DMA I2C1 transmit request */
239 #define DMA_REQUEST_I2C1_RX LL_DMA_PERIPH_I2C1_RX /**< DMA I2C1 receive request */
240 #define DMA_REQUEST_I2S_S_TX LL_DMA_PERIPH_I2S_S_TX /**< DMA I2S_S transmit request */
241 #define DMA_REQUEST_I2S_S_RX LL_DMA_PERIPH_I2S_S_RX /**< DMA I2S_S receive request */
242 #define DMA_REQUEST_UART0_TX LL_DMA_PERIPH_UART0_TX /**< DMA UART0 transmit request */
243 #define DMA_REQUEST_UART0_RX LL_DMA_PERIPH_UART0_RX /**< DMA UART0 receive request */
244 #define DMA_REQUEST_QSPI1_TX LL_DMA_PERIPH_QSPI1_TX /**< DMA QSPI1 transmit request */
245 #define DMA_REQUEST_QSPI1_RX LL_DMA_PERIPH_QSPI1_RX /**< DMA QSPI1 receive request */
246 #define DMA_REQUEST_I2S_M_TX LL_DMA_PERIPH_I2S_M_TX /**< DMA I2S_M transmit request */
247 #define DMA_REQUEST_I2S_M_RX LL_DMA_PERIPH_I2S_M_RX /**< DMA I2S_M receive request */
248 #define DMA_REQUEST_SNSADC LL_DMA_PERIPH_SNSADC /**< DMA SenseADC request */
249 #define DMA_REQUEST_MEM LL_DMA_PERIPH_MEM /**< DMA Memory request */
250
251 #define DMA0_REQUEST_SPIM_TX DMA_REQUEST_SPIM_TX /**< DMA SPIM transmit request */
252 #define DMA0_REQUEST_SPIM_RX DMA_REQUEST_SPIM_RX /**< DMA SPIM receive request */
253 #define DMA0_REQUEST_SPIS_TX DMA_REQUEST_SPIS_TX /**< DMA SPIS transmit request */
254 #define DMA0_REQUEST_SPIS_RX DMA_REQUEST_SPIS_RX /**< DMA SPIS receive request */
255 #define DMA0_REQUEST_QSPI0_TX DMA_REQUEST_QSPI0_TX /**< DMA QSPI0 transmit request */
256 #define DMA0_REQUEST_QSPI0_RX DMA_REQUEST_QSPI0_RX /**< DMA QSPI0 receive request */
257 #define DMA0_REQUEST_I2C0_TX DMA_REQUEST_I2C0_TX /**< DMA I2C0 transmit request */
258 #define DMA0_REQUEST_I2C0_RX DMA_REQUEST_I2C0_RX /**< DMA I2C0 receive request */
259 #define DMA0_REQUEST_I2C1_TX DMA_REQUEST_I2C1_TX /**< DMA I2C1 transmit request */
260 #define DMA0_REQUEST_I2C1_RX DMA_REQUEST_I2C1_RX /**< DMA I2C1 receive request */
261 #define DMA0_REQUEST_I2S_S_TX DMA_REQUEST_I2S_S_TX /**< DMA I2S_S transmit request */
262 #define DMA0_REQUEST_I2S_S_RX DMA_REQUEST_I2S_S_RX /**< DMA I2S_S receive request */
263 #define DMA0_REQUEST_UART0_TX DMA_REQUEST_UART0_TX /**< DMA UART0 transmit request */
264 #define DMA0_REQUEST_UART0_RX DMA_REQUEST_UART0_RX /**< DMA UART0 receive request */
265 #define DMA0_REQUEST_QSPI1_TX DMA_REQUEST_QSPI1_TX /**< DMA QSPI1 transmit request */
266 #define DMA0_REQUEST_QSPI1_RX DMA_REQUEST_QSPI1_RX /**< DMA QSPI1 receive request */
267 #define DMA0_REQUEST_I2S_M_TX DMA_REQUEST_I2S_M_TX /**< DMA I2S_M transmit request */
268 #define DMA0_REQUEST_I2S_M_RX DMA_REQUEST_I2S_M_RX /**< DMA I2S_M receive request */
269 #define DMA0_REQUEST_SNSADC DMA_REQUEST_SNSADC /**< DMA SenseADC request */
270 #define DMA0_REQUEST_MEM DMA_REQUEST_MEM /**< DMA Memory request */
271 /** @} */
272
273 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
274 * @{
275 */
276 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /**< Memory to memory direction */
277 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /**< Memory to peripheral direction */
278 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /**< Peripheral to memory direction */
279 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH /**< Peripheral to Peripheral direction */
280 /** @} */
281
282 /** @defgroup DMA_Source_incremented_mode DMA Source Incremented Mode
283 * @{
284 */
285 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT /**< Source increment mode */
286 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT /**< Source decrement mode */
287 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE /**< Source no change mode */
288 /** @} */
289
290 /** @defgroup DMA_Destination_incremented_mode DMA Destination Incremented Mode
291 * @{
292 */
293 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT /**< Destination increment mode */
294 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT /**< Destination decrement mode */
295 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE /**< Destination no change mode */
296 /** @} */
297
298 /** @defgroup DMA_Source_data_size DMA Source Data Size Alignment
299 * @{
300 */
301 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE /**< Source data alignment : Byte */
302 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD /**< Source data alignment : HalfWord */
303 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD /**< Source data alignment : Word */
304 /** @} */
305
306 /** @defgroup DMA_Destination_data_size DMA Destination Data Size Alignment
307 * @{
308 */
309 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE /**< Destination data alignment : Byte */
310 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD /**< Destination data alignment : HalfWord */
311 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD /**< Destination data alignment : Word */
312 /** @} */
313
314 /** @defgroup DMA_mode DMA Mode
315 * @{
316 */
317 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK /**< Normal Mode */
318 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD /**< Circular Mode */
319
320 /** @} */
321
322 /** @defgroup DMA_Priority_level DMA Priority Level
323 * @{
324 */
325 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0 /**< Priority level : Low */
326 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_2 /**< Priority level : Medium */
327 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_5 /**< Priority level : High */
328 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_7 /**< Priority level : Very High */
329 /** @} */
330
331 /** @} */
332
333 /* Private macros ------------------------------------------------------------*/
334 /** @defgroup DMA_Private_Macro DMA Private Macros
335 * @{
336 */
337
338 /** @brief Check if DMA channel instance is valid.
339 * @param __instance__ DMA channel instance.
340 * @retval SET (__instance__ is valid) or RESET (__instance__ is invalid)
341 */
342 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
343 ((__instance__) == DMA_Channel1) || \
344 ((__instance__) == DMA_Channel2) || \
345 ((__instance__) == DMA_Channel3) || \
346 ((__instance__) == DMA_Channel4) || \
347 ((__instance__) == DMA_Channel5) || \
348 ((__instance__) == DMA_Channel6) || \
349 ((__instance__) == DMA_Channel7))
350
351 /** @brief Check if DMA request is valid.
352 * @param __REQUEST__ DMA request.
353 * @retval SET (__REQUEST__ is valid) or RESET (__REQUEST__ is invalid)
354 */
355 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA_REQUEST_SPIM_TX) || \
356 ((__REQUEST__) == DMA_REQUEST_SPIM_RX) || \
357 ((__REQUEST__) == DMA_REQUEST_SPIS_TX) || \
358 ((__REQUEST__) == DMA_REQUEST_SPIS_RX) || \
359 ((__REQUEST__) == DMA_REQUEST_QSPI0_TX) || \
360 ((__REQUEST__) == DMA_REQUEST_QSPI0_RX) || \
361 ((__REQUEST__) == DMA_REQUEST_I2C0_TX) || \
362 ((__REQUEST__) == DMA_REQUEST_I2C0_RX) || \
363 ((__REQUEST__) == DMA_REQUEST_I2C1_TX) || \
364 ((__REQUEST__) == DMA_REQUEST_I2C1_RX) || \
365 ((__REQUEST__) == DMA_REQUEST_I2S_S_TX) || \
366 ((__REQUEST__) == DMA_REQUEST_I2S_S_RX) || \
367 ((__REQUEST__) == DMA_REQUEST_UART0_TX) || \
368 ((__REQUEST__) == DMA_REQUEST_UART0_RX) || \
369 ((__REQUEST__) == DMA_REQUEST_QSPI1_TX) || \
370 ((__REQUEST__) == DMA_REQUEST_QSPI1_RX) || \
371 ((__REQUEST__) == DMA_REQUEST_I2S_M_TX) || \
372 ((__REQUEST__) == DMA_REQUEST_I2S_M_RX) || \
373 ((__REQUEST__) == DMA_REQUEST_SNSADC) || \
374 ((__REQUEST__) == DMA_REQUEST_MEM))
375
376 /** @brief Check if DMA direction is valid.
377 * @param __DIRECTION__ DMA direction.
378 * @retval SET (__DIRECTION__ is valid) or RESET (__DIRECTION__ is invalid)
379 */
380 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
381 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
382 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
383 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
384
385 /** @brief Check if DMA buffer size is valid.
386 * @param __SIZE__ DMA buffer size.
387 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
388 */
389 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF))
390
391 /** @brief Check if DMA source address increment state is valid.
392 * @param __STATE__ DMA source address increment state.
393 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
394 */
395 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
396 ((__STATE__) == DMA_SRC_DECREMENT) || \
397 ((__STATE__) == DMA_SRC_NO_CHANGE))
398
399 /** @brief Check if DMA destination address increment state is valid.
400 * @param __STATE__ DMA destination address increment state.
401 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
402 */
403 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
404 ((__STATE__) == DMA_DST_DECREMENT) || \
405 ((__STATE__) == DMA_DST_NO_CHANGE))
406
407 /** @brief Check if DMA source data size is valid.
408 * @param __SIZE__ DMA source data size.
409 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
410 */
411 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
412 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
413 ((__SIZE__) == DMA_SDATAALIGN_WORD))
414
415 /** @brief Check if DMA destination data size is valid.
416 * @param __SIZE__ DMA destination data size.
417 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
418 */
419 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
420 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
421 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
422
423 /** @brief Check if DMA mode is valid.
424 * @param __MODE__ DMA mode.
425 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
426 */
427 #define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_NORMAL ) || \
428 ((__MODE__) == DMA_CIRCULAR))
429
430 /** @brief Check if DMA priority is valid.
431 * @param __PRIORITY__ DMA priority.
432 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid)
433 */
434 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
435 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
436 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
437 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
438 /** @} */
439
440 /** @} */
441
442
443 /* Exported functions --------------------------------------------------------*/
444 /** @addtogroup HAL_DMA_DRIVER_FUNCTIONS Functions
445 * @{
446 */
447
448 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
449 * @brief Initialization and de-initialization functions
450 *
451 @verbatim
452 ===============================================================================
453 ##### Initialization and de-initialization functions #####
454 ===============================================================================
455 [..]
456 This section provides functions allowing to initialize the DMA Channel source
457 and destination addresses, incrementation and data sizes, transfer direction,
458 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
459 [..]
460 The hal_dma_init() function follows the DMA configuration procedures as described in
461 reference manual.
462
463 @endverbatim
464 * @{
465 */
466
467 /**
468 ****************************************************************************************
469 * @brief Initialize the DMA according to the specified
470 * parameters in the dma_init_t and initialize the associated handle.
471 *
472 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
473 *
474 * @retval ::HAL_OK: Operation is OK.
475 * @retval ::HAL_ERROR: Parameter error or operation not supported.
476 * @retval ::HAL_BUSY: Driver is busy.
477 * @retval ::HAL_TIMEOUT: Timeout occurred.
478 ****************************************************************************************
479 */
480 hal_status_t hal_dma_init(dma_handle_t *p_dma);
481
482 /**
483 ****************************************************************************************
484 * @brief De-initialize the DMA peripheral.
485 *
486 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
487 *
488 * @retval ::HAL_OK: Operation is OK.
489 * @retval ::HAL_ERROR: Parameter error or operation not supported.
490 * @retval ::HAL_BUSY: Driver is busy.
491 * @retval ::HAL_TIMEOUT: Timeout occurred.
492 ****************************************************************************************
493 */
494 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
495
496 /** @} */
497
498
499 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
500 * @brief Input and Output operation functions
501 *
502 @verbatim
503 ===============================================================================
504 ##### IO operation functions #####
505 ===============================================================================
506 [..] This section provides functions allowing to:
507 (+) Configure the source, destination address and data length and Start DMA transfer
508 (+) Configure the source, destination address and data length and
509 Start DMA transfer with interrupt
510 (+) Abort DMA transfer
511 (+) Poll for transfer complete
512 (+) Handle DMA interrupt request
513
514 @endverbatim
515 * @{
516 */
517
518 /**
519 ****************************************************************************************
520 * @brief Start the DMA Transfer.
521 *
522 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
523 * @param[in] src_address: The source memory Buffer address
524 * @param[in] dst_address: The destination memory Buffer address
525 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
526 *
527 * @retval ::HAL_OK: Operation is OK.
528 * @retval ::HAL_ERROR: Parameter error or operation not supported.
529 * @retval ::HAL_BUSY: Driver is busy.
530 * @retval ::HAL_TIMEOUT: Timeout occurred.
531 ****************************************************************************************
532 */
533 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
534
535 /**
536 ****************************************************************************************
537 * @brief Start the DMA Transfer with interrupt enabled.
538 *
539 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
540 * @param[in] src_address: The source memory Buffer address
541 * @param[in] dst_address: The destination memory Buffer address
542 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
543 *
544 * @retval ::HAL_OK: Operation is OK.
545 * @retval ::HAL_ERROR: Parameter error or operation not supported.
546 * @retval ::HAL_BUSY: Driver is busy.
547 * @retval ::HAL_TIMEOUT: Timeout occurred.
548 ****************************************************************************************
549 */
550 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
551
552 /**
553 ****************************************************************************************
554 * @brief Abort the DMA Transfer.
555 *
556 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
557 *
558 * @retval ::HAL_OK: Operation is OK.
559 * @retval ::HAL_ERROR: Parameter error or operation not supported.
560 * @retval ::HAL_BUSY: Driver is busy.
561 * @retval ::HAL_TIMEOUT: Timeout occurred.
562 ****************************************************************************************
563 */
564 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
565
566 /**
567 ****************************************************************************************
568 * @brief Aborts the DMA Transfer in Interrupt mode.
569 *
570 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
571 *
572 * @retval ::HAL_OK: Operation is OK.
573 * @retval ::HAL_ERROR: Parameter error or operation not supported.
574 * @retval ::HAL_BUSY: Driver is busy.
575 * @retval ::HAL_TIMEOUT: Timeout occurred.
576 ****************************************************************************************
577 */
578 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
579
580 /**
581 ****************************************************************************************
582 * @brief Polling for transfer complete.
583 *
584 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
585 * @param[in] timeout: Timeout duration.
586 *
587 * @retval ::HAL_OK: Operation is OK.
588 * @retval ::HAL_ERROR: Parameter error or operation not supported.
589 * @retval ::HAL_BUSY: Driver is busy.
590 * @retval ::HAL_TIMEOUT: Timeout occurred.
591 ****************************************************************************************
592 */
593 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
594
595 /** @} */
596
597 /** @addtogroup DMA_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
598 * @brief IRQ Handler and Callbacks functions
599 * @{
600 */
601
602 /**
603 ****************************************************************************************
604 * @brief Handle DMA interrupt request.
605 *
606 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
607 ****************************************************************************************
608 */
609 void hal_dma_irq_handler(dma_handle_t *p_dma);
610
611 /**
612 ****************************************************************************************
613 * @brief Register callbacks
614 *
615 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
616 * @param[in] id: User Callback identifer. This parameter can be one of the following values:
617 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
618 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
619 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
620 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
621 * @param[in] callback: Pointer to private callbacsk function which has pointer to a dma_handle_t structure as parameter.
622 *
623 * @retval ::HAL_OK: Operation is OK.
624 * @retval ::HAL_ERROR: Parameter error or operation not supported.
625 * @retval ::HAL_BUSY: Driver is busy.
626 * @retval ::HAL_TIMEOUT: Timeout occurred.
627 ****************************************************************************************
628 */
629 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void (* callback)( dma_handle_t * p_dma));
630
631 /**
632 ****************************************************************************************
633 * @brief UnRegister callbacks
634 *
635 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
636 * @param[in] id: User Callback identifer. This parameter can be a combiantion of the following values:
637 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
638 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
639 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
640 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
641 * @arg @ref HAL_DMA_XFER_ALL_CB_ID
642 *
643 * @retval ::HAL_OK: Operation is OK.
644 * @retval ::HAL_ERROR: Parameter error or operation not supported.
645 * @retval ::HAL_BUSY: Driver is busy.
646 * @retval ::HAL_TIMEOUT: Timeout occurred.
647 ****************************************************************************************
648 */
649 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
650
651 /** @} */
652
653 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
654 * @brief Peripheral State and Errors functions
655 *
656 @verbatim
657 ===============================================================================
658 ##### Peripheral State and Errors functions #####
659 ===============================================================================
660 [..]
661 This subsection provides functions allowing to
662 (+) Check the DMA state
663 (+) Get error code
664
665 @endverbatim
666 * @{
667 */
668
669 /**
670 ****************************************************************************************
671 * @brief Return the DMA hande state.
672 *
673 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
674 *
675 * @retval ::HAL_DMA_STATE_RESET: DMA not yet initialized or disabled.
676 * @retval ::HAL_DMA_STATE_READY: DMA process succeeded and ready for use.
677 * @retval ::HAL_DMA_STATE_BUSY: DMA process is ongoing.
678 * @retval ::HAL_DMA_STATE_TIMEOUT: DMA timeout state.
679 * @retval ::HAL_DMA_STATE_ERROR: DMA error state.
680 ****************************************************************************************
681 */
682 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
683
684 /**
685 ****************************************************************************************
686 * @brief Return the DMA error code.
687 *
688 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
689 *
690 * @return DMA Error Code
691 ****************************************************************************************
692 */
693 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
694
695 /**
696 ****************************************************************************************
697 * @brief Suspend some registers related to DMA configuration before sleep.
698 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
699 * information for the specified DMA module.
700 * @retval ::HAL_OK: Operation is OK.
701 * @retval ::HAL_ERROR: Parameter error or operation not supported.
702 * @retval ::HAL_BUSY: Driver is busy.
703 * @retval ::HAL_TIMEOUT: Timeout occurred.
704 ****************************************************************************************
705 */
706 hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma);
707
708 /**
709 ****************************************************************************************
710 * @brief Restore some registers related to DMA configuration after sleep.
711 * This function must be used in conjunction with the hal_dma_resume_reg().
712 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
713 * information for the specified DMA module.
714 * @retval ::HAL_OK: Operation is OK.
715 * @retval ::HAL_ERROR: Parameter error or operation not supported.
716 * @retval ::HAL_BUSY: Driver is busy.
717 * @retval ::HAL_TIMEOUT: Timeout occurred.
718 ****************************************************************************************
719 */
720 hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma);
721
722 /** @} */
723
724 /** @} */
725
726 #ifdef __cplusplus
727 }
728 #endif
729
730 #endif /* __GR55xx_HAL_DMA_H__*/
731
732 /** @} */
733
734 /** @} */
735
736 /** @} */
DMA_Channel4
@ DMA_Channel4
Channel 4
Definition: gr55xx_hal_dma.h:98
HAL_DMA_XFER_TFR_CB_ID
@ HAL_DMA_XFER_TFR_CB_ID
Full transfer
Definition: gr55xx_hal_dma.h:114
hal_lock_t
hal_lock_t
HAL Lock structures definition.
Definition: gr55xx_hal_def.h:81
hal_dma_get_error
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA_Channel1
@ DMA_Channel1
Channel 1
Definition: gr55xx_hal_dma.h:95
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
DMA timeout state
Definition: gr55xx_hal_dma.h:80
_dma_init
DMA Configuration Structure definition.
Definition: gr55xx_hal_dma.h:137
_dma_handle::error_code
__IO uint32_t error_code
DMA Error code
Definition: gr55xx_hal_dma.h:198
DMA_Channel0
@ DMA_Channel0
Channel 0
Definition: gr55xx_hal_dma.h:94
dma_handle_t
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
hal_dma_state_t
HAL DMA State Enumerations definition.
Definition: gr55xx_hal_dma.h:76
hal_dma_start_it
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled.
hal_dma_abort_it
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
DMA process success and ready for use
Definition: gr55xx_hal_dma.h:78
_dma_init::dst_increment
uint32_t dst_increment
Specifies whether the destination address register should be incremented or decrement or not.
Definition: gr55xx_hal_dma.h:151
DMA_Channel5
@ DMA_Channel5
Channel 5
Definition: gr55xx_hal_dma.h:99
_dma_handle::init
dma_init_t init
DMA communication parameters
Definition: gr55xx_hal_dma.h:182
DMA_Channel2
@ DMA_Channel2
Channel 2
Definition: gr55xx_hal_dma.h:96
hal_dma_irq_handler
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
_dma_handle::xfer_blk_callback
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
DMA block complete callback
Definition: gr55xx_hal_dma.h:192
hal_dma_suspend_reg
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
_dma_handle::retention
uint32_t retention[5]
DMA important register information.
Definition: gr55xx_hal_dma.h:200
gr55xx_ll_dma.h
Header file containing functions prototypes of DMA LL library.
_dma_init::priority
uint32_t priority
Specifies the software priority for the DMA Channel.
Definition: gr55xx_hal_dma.h:165
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Abort
Definition: gr55xx_hal_dma.h:117
hal_dma_register_callback
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
All
Definition: gr55xx_hal_dma.h:118
_dma_init::dst_request
uint32_t dst_request
Specifies the destination request selected for the specified channel.
Definition: gr55xx_hal_dma.h:141
hal_dma_poll_for_transfer
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
DMA_Channel6
@ DMA_Channel6
Channel 6
Definition: gr55xx_hal_dma.h:100
hal_dma_start
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
hal_dma_resume_reg
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep.
_dma_handle::state
__IO hal_dma_state_t state
DMA transfer state
Definition: gr55xx_hal_dma.h:186
hal_dma_init
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
_dma_handle::xfer_error_callback
void(* xfer_error_callback)(struct _dma_handle *p_dma)
DMA transfer error callback
Definition: gr55xx_hal_dma.h:194
HAL_DMA_XFER_BLK_CB_ID
@ HAL_DMA_XFER_BLK_CB_ID
Block transfer
Definition: gr55xx_hal_dma.h:115
hal_dma_callback_id_t
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
Definition: gr55xx_hal_dma.h:113
DMA_Channel3
@ DMA_Channel3
Channel 3
Definition: gr55xx_hal_dma.h:97
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
DMA error state
Definition: gr55xx_hal_dma.h:81
_dma_handle::xfer_tfr_callback
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
DMA transfer complete callback
Definition: gr55xx_hal_dma.h:190
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
DMA process is ongoing
Definition: gr55xx_hal_dma.h:79
_dma_handle::xfer_abort_callback
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
DMA transfer abort callback
Definition: gr55xx_hal_dma.h:196
dma_init_t
struct _dma_init dma_init_t
DMA Configuration Structure definition.
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr55xx_hal_def.h:70
_dma_init::direction
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
Definition: gr55xx_hal_dma.h:144
hal_dma_get_state
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
_dma_init::mode
uint32_t mode
Specifies the operation mode of the DMA Channel(Normal or Circular).
Definition: gr55xx_hal_dma.h:160
DMA_Channel7
@ DMA_Channel7
Channel 7
Definition: gr55xx_hal_dma.h:101
hal_dma_unregister_callback
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
_dma_handle::channel
dma_channel_t channel
DMA Channel Number
Definition: gr55xx_hal_dma.h:180
_dma_init::dst_data_alignment
uint32_t dst_data_alignment
Specifies the destination data width.
Definition: gr55xx_hal_dma.h:157
_dma_handle::lock
hal_lock_t lock
DMA locking object
Definition: gr55xx_hal_dma.h:184
_dma_handle::p_parent
void * p_parent
Parent object state
Definition: gr55xx_hal_dma.h:188
hal_dma_abort
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Error
Definition: gr55xx_hal_dma.h:116
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
DMA not yet initialized or disabled.
Definition: gr55xx_hal_dma.h:77
_dma_init::src_request
uint32_t src_request
Specifies the source request selected for the specified channel.
Definition: gr55xx_hal_dma.h:138
_dma_init::src_data_alignment
uint32_t src_data_alignment
Specifies the source data width.
Definition: gr55xx_hal_dma.h:154
_dma_handle
DMA handle Structure definition.
Definition: gr55xx_hal_dma.h:179
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_dma_deinit
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr55xx_hal_dma.h:93
_dma_init::src_increment
uint32_t src_increment
Specifies whether the srouce address register should be incremented or decrement or not.
Definition: gr55xx_hal_dma.h:148