gr55xx_ll_xqspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_xqspi.h
5 * @author BLE SDK Team
6 * @brief Header file containing functions prototypes of XQSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_XQSPI XQSPI
47 * @brief XQSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (XQSPI)
63
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief XQSPI init structures definition
75 */
76 typedef struct _ll_xqspi_init_t
77 {
78 uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
79 This parameter can be a value of @ref XQSPI_LL_EC_MODE.*/
80
81 uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
82 This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
83
84 This feature can be modified afterwards using unitary function @ref ll_xqspi_enable_cache().*/
85
86 uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
87 This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
88
89 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cmd().*/
90
91 uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
92 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
93
94 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_datasize().*/
95
96 uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
97 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
98
99 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_data_order().*/
100
101 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
102 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_POLARITY in XIP mode or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
103
104 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol().*/
105
106 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
107 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_PHASE in XIP mode or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
108
109 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha().*/
110
111 uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and receive SCK clock.
112 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
113
114 This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_speed().*/
115
116 } ll_xqspi_init_t;
117
118 /** @} */
119
120 /** @} */
121
122 /**
123 * @defgroup XQSPI_LL_MACRO Defines
124 * @{
125 */
126
127 /* Exported constants --------------------------------------------------------*/
128 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
129 * @{
130 */
131
132 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
133 * @{
134 */
135 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
136 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
137 /** @} */
138
139 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
140 * @{
141 */
142 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
143 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
144 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
145 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
146 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
147 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
148 /** @} */
149
150 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
151 * @{
152 */
153 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
154 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
155 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
156 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
157 /** @} */
158
159 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
160 * @{
161 */
162 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
163 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
164 /** @} */
165
166 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
167 * @{
168 */
169 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
170 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
171 /** @} */
172
173 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
174 * @{
175 */
176 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
177 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
178 /** @} */
179
180 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
181 * @{
182 */
183 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
184 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
185 /** @} */
186
187 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
188 * @{
189 */
190 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
191 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
192 /** @} */
193
194 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
195 * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
196 * @{
197 */
198 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
199 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
200 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
201 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
202 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
203 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
204 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
205 /** @} */
206
207 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
208 * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
209 * @{
210 */
211 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
212 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
213 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt enable */
214 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt enable */
215 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
216
217 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
218 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
219 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
220 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt flag */
221 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
222 /** @} */
223
224 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
225 * @{
226 */
227 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
228 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
229 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
230 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
231 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL /**< FIFO full depth */
232 /** @} */
233
234 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
235 * @{
236 */
237 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
238 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format for transfer */
239 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format for transfer */
240 /** @} */
241
242 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
243 * @{
244 */
245 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
246 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
247 /** @} */
248
249 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
250 * @{
251 */
252 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI transfer: 4 bits */
253 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 8 bits */
254 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 12 bits */
255 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 16 bits */
256 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 20 bits */
257 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 24 bits */
258 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 28 bits */
259 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 32 bits */
260 /** @} */
261
262 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
263 * @{
264 */
265 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
266 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
267 /** @} */
268
269 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
270 * @{
271 */
272 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
273 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
274 /** @} */
275
276 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
277 * @{
278 */
279 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
280 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
281 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
282 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
283 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
284 /** @} */
285
286 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
287 * @{
288 */
289 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
290 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
291 /** @} */
292
293 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
294 * @{
295 */
296 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
297 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
298 /** @} */
299
300 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
301 * @{
302 */
303
304 /**
305 * @brief LL XQSPI InitStrcut default configuartion
306 */
307 #define LL_XQSPI_DEFAULT_CONFIG \
308 { \
309 .mode = LL_XQSPI_MODE_QSPI, \
310 .cache_mode = LL_XQSPI_CACHE_EN, \
311 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
312 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
313 .data_order = LL_XQSPI_QSPI_MSB, \
314 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
315 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
316 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
317 }
318 /** @} */
319
320 /** @} */
321
322 /* Exported macro ------------------------------------------------------------*/
323 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
324 * @{
325 */
326
327 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
328 * @{
329 */
330
331 /**
332 * @brief Write a value in XQSPI register
333 * @param __instance__ XQSPI instance
334 * @param __REG__ Register to be written
335 * @param __VALUE__ Value to be written in the register
336 * @retval None
337 */
338 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
339
340 /**
341 * @brief Read a value in XQSPI register
342 * @param __instance__ XQSPI instance
343 * @param __REG__ Register to be read
344 * @retval Register value
345 */
346 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
347
348 /** @} */
349
350 /** @} */
351
352 /** @} */
353
354 /* Exported functions --------------------------------------------------------*/
355 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
356 * @{
357 */
358
359 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
360 * @{
361 */
362
363 /**
364 * @brief Enable cache function
365 * @note This bit should not be changed when XIP is ongoing.
366 *
367 * \rst
368 * +----------------------+-----------------------------------+
369 * | Register | BitsName |
370 * +======================+===================================+
371 * | CTRL0 | EN |
372 * +----------------------+-----------------------------------+
373 * \endrst
374 *
375 * @param XQSPIx XQSPI instance
376 * @retval None
377 */
378 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
379 {
380 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
381 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
382 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
383 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
384 }
385
386 /**
387 * @brief Disable cache function
388 * @note This bit should not be changed when XIP is ongoing.
389 *
390 * \rst
391 * +----------------------+-----------------------------------+
392 * | Register | BitsName |
393 * +======================+===================================+
394 * | CTRL0 | EN |
395 * +----------------------+-----------------------------------+
396 * \endrst
397 *
398 * @param XQSPIx XQSPI instance
399 * @retval None
400 */
401 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
402 {
403 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
404 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
405 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
406 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
407 }
408
409 /**
410 * @brief Check if cache function is enabled
411 *
412 * \rst
413 * +----------------------+-----------------------------------+
414 * | Register | BitsName |
415 * +======================+===================================+
416 * | CTRL0 | EN |
417 * +----------------------+-----------------------------------+
418 * \endrst
419 *
420 * @param XQSPIx XQSPI instance
421 * @retval State of bit (1 or 0).
422 */
423 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
424 {
425 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
426 }
427
428 /**
429 * @brief Enable tag memory flush
430 * @note This bit should not be changed when XIP is ongoing.
431 *
432 * \rst
433 * +----------------------+-----------------------------------+
434 * | Register | BitsName |
435 * +======================+===================================+
436 * | CTRL0 | TAG |
437 * +----------------------+-----------------------------------+
438 * \endrst
439 *
440 * @param XQSPIx XQSPI instance
441 * @retval None
442 */
443 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
444 {
445 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
446 }
447
448 /**
449 * @brief Disable tag memory flush
450 * @note This bit should not be changed when XIP is ongoing.
451 *
452 * \rst
453 * +----------------------+-----------------------------------+
454 * | Register | BitsName |
455 * +======================+===================================+
456 * | CTRL0 | TAG |
457 * +----------------------+-----------------------------------+
458 * \endrst
459 *
460 * @param XQSPIx XQSPI instance
461 * @retval None
462 */
463 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
464 {
465 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
466 }
467
468 /**
469 * @brief Check if tag memory flush is enabled
470 *
471 * \rst
472 * +----------------------+-----------------------------------+
473 * | Register | BitsName |
474 * +======================+===================================+
475 * | CTRL0 | TAG |
476 * +----------------------+-----------------------------------+
477 * \endrst
478 *
479 * @param XQSPIx XQSPI instance
480 * @retval State of bit (1 or 0).
481 */
482 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
483 {
484 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
485 }
486
487 /**
488 * @brief Set FIFO mode
489 * @note This bit should not be changed when XIP is ongoing.
490 *
491 * \rst
492 * +----------------------+-----------------------------------+
493 * | Register | BitsName |
494 * +======================+===================================+
495 * | CTRL0 | FIFO |
496 * +----------------------+-----------------------------------+
497 * \endrst
498 *
499 * @param XQSPIx XQSPI instance
500 * @param mode This parameter can be one of the following values:
501 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
502 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
503 * @retval None
504 */
505 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
506 {
507 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
508 }
509
510 /**
511 * @brief Get FIFO mode
512 * @note This bit should not be changed when XIP is ongoing.
513 *
514 * \rst
515 * +----------------------+-----------------------------------+
516 * | Register | BitsName |
517 * +======================+===================================+
518 * | CTRL0 | FIFO |
519 * +----------------------+-----------------------------------+
520 * \endrst
521 *
522 * @param XQSPIx XQSPI instance
523 * @retval Returned Value can be one of the following values:
524 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
525 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
526 */
527 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
528 {
529 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
530 }
531
532 /**
533 * @brief Set HIT/MISS mode
534 * @note This bit should not be changed when XIP is ongoing.
535 *
536 * \rst
537 * +----------------------+-----------------------------------+
538 * | Register | BitsName |
539 * +======================+===================================+
540 * | CTRL0 | HITMISS |
541 * +----------------------+-----------------------------------+
542 * \endrst
543 *
544 * @param XQSPIx XQSPI instance
545 * @param mode This parameter can be one of the following values:
546 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
547 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
548 * @retval None
549 */
550 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
551 {
552 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
553 }
554
555 /**
556 * @brief Get HIT/MISS mode
557 * @note This bit should not be changed when XIP is ongoing.
558 *
559 * \rst
560 * +----------------------+-----------------------------------+
561 * | Register | BitsName |
562 * +======================+===================================+
563 * | CTRL0 | HITMISS |
564 * +----------------------+-----------------------------------+
565 * \endrst
566 *
567 * @param XQSPIx XQSPI instance
568 * @retval Returned Value can be one of the following values:
569 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
570 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
571 */
572 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
573 {
574 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
575 }
576
577 /**
578 * @brief Set debugbus configurations signals
579 * @note These bits should not be changed when XIP is ongoing.
580 *
581 * \rst
582 * +----------------------+-----------------------------------+
583 * | Register | BitsName |
584 * +======================+===================================+
585 * | CTRL1 | DBGBUS_SEL |
586 * +----------------------+-----------------------------------+
587 * \endrst
588 *
589 * @param XQSPIx XQSPI instance
590 * @param sel This parameter can between: 0 ~ 0x7
591 * @retval None
592 */
593 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
594 {
595 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
596 }
597
598 /**
599 * @brief Get debugbus configurations signals
600 *
601 * \rst
602 * +----------------------+-----------------------------------+
603 * | Register | BitsName |
604 * +======================+===================================+
605 * | CTRL1 | DBGBUS_SEL |
606 * +----------------------+-----------------------------------+
607 * \endrst
608 *
609 * @param XQSPIx XQSPI instance
610 * @retval Returned Value can between: 0 ~ 0x7
611 */
612 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
613 {
614 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
615 }
616
617 /**
618 * @brief Enable debug bus mux
619 * @note This bit should not be changed when XIP is ongoing.
620 *
621 * \rst
622 * +----------------------+-----------------------------------+
623 * | Register | BitsName |
624 * +======================+===================================+
625 * | CTRL1 | DBGMUX_EN |
626 * +----------------------+-----------------------------------+
627 * \endrst
628 *
629 * @param XQSPIx XQSPI instance
630 * @retval None
631 */
632 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
633 {
634 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
635 }
636
637 /**
638 * @brief Disable debug bus mux
639 * @note This bit should not be changed when XIP is ongoing.
640 *
641 * \rst
642 * +----------------------+-----------------------------------+
643 * | Register | BitsName |
644 * +======================+===================================+
645 * | CTRL1 | DBGMUX_EN |
646 * +----------------------+-----------------------------------+
647 * \endrst
648 *
649 * @param XQSPIx XQSPI instance
650 * @retval None
651 */
652 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
653 {
654 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
655 }
656
657 /**
658 * @brief Check if debug bus mux is enabled
659 *
660 * \rst
661 * +----------------------+-----------------------------------+
662 * | Register | BitsName |
663 * +======================+===================================+
664 * | CTRL1 | DBGMUX_EN |
665 * +----------------------+-----------------------------------+
666 * \endrst
667 *
668 * @param XQSPIx XQSPI instance
669 * @retval State of bit (1 or 0).
670 */
671 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
672 {
673 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
674 }
675
676 /**
677 * @brief Get hit counter
678 * @note This bit only be read.
679 *
680 * \rst
681 * +----------------------+-----------------------------------+
682 * | Register | BitsName |
683 * +======================+===================================+
684 * | HIT_COUNT | HITCOUNT |
685 * +----------------------+-----------------------------------+
686 * \endrst
687 *
688 * @param XQSPIx XQSPI instance
689 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
690 */
691 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
692 {
693 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
694 }
695
696 /**
697 * @brief Get miss counter
698 * @note This bit only be read.
699 *
700 * \rst
701 * +----------------------+-----------------------------------+
702 * | Register | BitsName |
703 * +======================+===================================+
704 * | MISS_COUNT | MISSCOUNT |
705 * +----------------------+-----------------------------------+
706 * \endrst
707 *
708 * @param XQSPIx XQSPI instance
709 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
710 */
711 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
712 {
713 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
714 }
715
716 /**
717 * @brief Get cache status
718 * @note This bit only be read.
719 *
720 * \rst
721 * +----------------------+-----------------------------------+
722 * | Register | BitsName |
723 * +======================+===================================+
724 * | STAT | STAT |
725 * +----------------------+-----------------------------------+
726 * \endrst
727 *
728 * @param XQSPIx XQSPI instance
729 * @retval Returned Value can between: 0 ~ 1
730 */
731 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
732 {
733 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
734 }
735
736 /** @} */
737
738 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
739 * @{
740 */
741
742 /**
743 * @brief Set read command
744 * @note These bits should not be changed when XIP is ongoing.
745 *
746 * \rst
747 * +----------------------+-----------------------------------+
748 * | Register | BitsName |
749 * +======================+===================================+
750 * | CTRL0 | CFG_CMD |
751 * +----------------------+-----------------------------------+
752 * \endrst
753 *
754 * @param XQSPIx XQSPI instance
755 * @param cmd This parameter can be one of the following values:
756 * @arg @ref LL_XQSPI_XIP_CMD_READ
757 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
758 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
759 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
760 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
761 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
762 * @retval None
763 */
764 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
765 {
766 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
767 }
768
769 /**
770 * @brief Get read command
771 *
772 * \rst
773 * +----------------------+-----------------------------------+
774 * | Register | BitsName |
775 * +======================+===================================+
776 * | CTRL0 | CFG_CMD |
777 * +----------------------+-----------------------------------+
778 * \endrst
779 *
780 * @param XQSPIx XQSPI instance
781 * @retval Returned Value can be one of the following values:
782 * @arg @ref LL_XQSPI_XIP_CMD_READ
783 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
784 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
785 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
786 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
787 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
788 */
789 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
790 {
791 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
792 }
793
794 /**
795 * @brief Enable high performance mode
796 * @note This bit should not be changed when XIP is ongoing.
797 *
798 * \rst
799 * +----------------------+-----------------------------------+
800 * | Register | BitsName |
801 * +======================+===================================+
802 * | CTRL1 | CFG_HPEN |
803 * +----------------------+-----------------------------------+
804 * \endrst
805 *
806 * @param XQSPIx XQSPI instance
807 * @retval None
808 */
809 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
810 {
811 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
812 }
813
814 /**
815 * @brief Disable high performance mode
816 * @note This bit should not be changed when XIP is ongoing.
817 *
818 * \rst
819 * +----------------------+-----------------------------------+
820 * | Register | BitsName |
821 * +======================+===================================+
822 * | CTRL1 | CFG_HPEN |
823 * +----------------------+-----------------------------------+
824 * \endrst
825 *
826 * @param XQSPIx XQSPI instance
827 * @retval None
828 */
829 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
830 {
831 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
832 }
833
834 /**
835 * @brief Check if high performance mode is enabled
836 *
837 * \rst
838 * +----------------------+-----------------------------------+
839 * | Register | BitsName |
840 * +======================+===================================+
841 * | CTRL1 | CFG_HPEN |
842 * +----------------------+-----------------------------------+
843 * \endrst
844 *
845 * @param XQSPIx XQSPI instance
846 * @retval State of bit (1 or 0).
847 */
848 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
849 {
850 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
851 }
852
853 /**
854 * @brief Set slave select
855 * @note These bits should not be changed when XIP is ongoing.
856 *
857 * \rst
858 * +----------------------+-----------------------------------+
859 * | Register | BitsName |
860 * +======================+===================================+
861 * | CTRL1 | CFG_SS |
862 * +----------------------+-----------------------------------+
863 * \endrst
864 *
865 * @param XQSPIx XQSPI instance
866 * @param ss This parameter can be one or more of the following values:
867 * @arg @ref LL_XQSPI_XIP_SS0
868 * @arg @ref LL_XQSPI_XIP_SS1
869 * @arg @ref LL_XQSPI_XIP_SS2
870 * @arg @ref LL_XQSPI_XIP_SS3
871 * @retval None
872 */
873 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
874 {
875 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
876 }
877
878 /**
879 * @brief Get slave select
880 *
881 * \rst
882 * +----------------------+-----------------------------------+
883 * | Register | BitsName |
884 * +======================+===================================+
885 * | CTRL1 | CFG_SS |
886 * +----------------------+-----------------------------------+
887 * \endrst
888 *
889 * @param XQSPIx XQSPI instance
890 * @retval Returned Value can be one of the following values:
891 * @arg @ref LL_XQSPI_XIP_SS0
892 * @arg @ref LL_XQSPI_XIP_SS1
893 * @arg @ref LL_XQSPI_XIP_SS2
894 * @arg @ref LL_XQSPI_XIP_SS3
895 */
896 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
897 {
898 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
899 }
900
901 /**
902 * @brief Set clock phase
903 * @note This bit should not be changed when XIP is ongoing.
904 *
905 * \rst
906 * +----------------------+-----------------------------------+
907 * | Register | BitsName |
908 * +======================+===================================+
909 * | CTRL1 | CFG_CPHA |
910 * +----------------------+-----------------------------------+
911 * \endrst
912 *
913 * @param XQSPIx XQSPI instance
914 * @param cpha This parameter can be one or more of the following values:
915 * @arg @ref LL_XQSPI_SCPHA_1EDGE
916 * @arg @ref LL_XQSPI_SCPHA_2EDGE
917 * @retval None
918 */
919 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
920 {
921 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
922 }
923
924 /**
925 * @brief Get clock phase
926 *
927 * \rst
928 * +----------------------+-----------------------------------+
929 * | Register | BitsName |
930 * +======================+===================================+
931 * | CTRL1 | CFG_CPHA |
932 * +----------------------+-----------------------------------+
933 * \endrst
934 *
935 * @param XQSPIx XQSPI instance
936 * @retval Returned Value can be one of the following values:
937 * @arg @ref LL_XQSPI_SCPHA_1EDGE
938 * @arg @ref LL_XQSPI_SCPHA_2EDGE
939 */
940 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
941 {
942 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
943 }
944
945 /**
946 * @brief Set clock polarity
947 * @note This bit should not be changed when XIP is ongoing.
948 *
949 * \rst
950 * +----------------------+-----------------------------------+
951 * | Register | BitsName |
952 * +======================+===================================+
953 * | CTRL1 | CFG_CPOL |
954 * +----------------------+-----------------------------------+
955 * \endrst
956 *
957 * @param XQSPIx XQSPI instance
958 * @param cpol This parameter can be one or more of the following values:
959 * @arg @ref LL_XQSPI_SCPOL_LOW
960 * @arg @ref LL_XQSPI_SCPOL_HIGH
961 * @retval None
962 */
963 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
964 {
965 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
966 }
967
968 /**
969 * @brief Get clock polarity
970 *
971 * \rst
972 * +----------------------+-----------------------------------+
973 * | Register | BitsName |
974 * +======================+===================================+
975 * | CTRL1 | CFG_CPOL |
976 * +----------------------+-----------------------------------+
977 * \endrst
978 *
979 * @param XQSPIx XQSPI instance
980 * @retval Returned Value can be one of the following values:
981 * @arg @ref LL_XQSPI_SCPOL_LOW
982 * @arg @ref LL_XQSPI_SCPOL_HIGH
983 */
984 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
985 {
986 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
987 }
988
989 /**
990 * @brief Set address bytes in command
991 * @note This bit should not be changed when XIP is ongoing.
992 *
993 * \rst
994 * +----------------------+-----------------------------------+
995 * | Register | BitsName |
996 * +======================+===================================+
997 * | CTRL1 | CFG_ADDR4 |
998 * +----------------------+-----------------------------------+
999 * \endrst
1000 *
1001 * @param XQSPIx XQSPI instance
1002 * @param size This parameter can be one or more of the following values:
1003 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1004 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1005 * @retval None
1006 */
1007 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
1008 {
1009 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
1010 }
1011
1012 /**
1013 * @brief Get address bytes in command
1014 *
1015 * \rst
1016 * +----------------------+-----------------------------------+
1017 * | Register | BitsName |
1018 * +======================+===================================+
1019 * | CTRL1 | CFG_ADDR4 |
1020 * +----------------------+-----------------------------------+
1021 * \endrst
1022 *
1023 * @param XQSPIx XQSPI instance
1024 * @retval Returned Value can be one of the following values:
1025 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1026 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1027 */
1028 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
1029 {
1030 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
1031 }
1032
1033 /**
1034 * @brief Set endian in reading data
1035 * @note This bit should not be changed when XIP is ongoing.
1036 *
1037 * \rst
1038 * +----------------------+-----------------------------------+
1039 * | Register | BitsName |
1040 * +======================+===================================+
1041 * | CTRL1 | CFG_LE32 |
1042 * +----------------------+-----------------------------------+
1043 * \endrst
1044 *
1045 * @param XQSPIx XQSPI instance
1046 * @param endian This parameter can be one or more of the following values:
1047 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1048 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1049 * @retval None
1050 */
1051 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
1052 {
1053 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
1054 }
1055
1056 /**
1057 * @brief Get endian in reading data
1058 *
1059 * \rst
1060 * +----------------------+-----------------------------------+
1061 * | Register | BitsName |
1062 * +======================+===================================+
1063 * | CTRL1 | CFG_LE32 |
1064 * +----------------------+-----------------------------------+
1065 * \endrst
1066 *
1067 * @param XQSPIx XQSPI instance
1068 * @retval Returned Value can be one of the following values:
1069 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1070 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1071 */
1072 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
1073 {
1074 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
1075 }
1076
1077 /**
1078 * @brief Set high performance command
1079 * @note These bits should not be changed when XIP is ongoing.
1080 *
1081 * \rst
1082 * +----------------------+-----------------------------------+
1083 * | Register | BitsName |
1084 * +======================+===================================+
1085 * | CTRL2 | CFG_HPMODE |
1086 * +----------------------+-----------------------------------+
1087 * \endrst
1088 *
1089 * @param XQSPIx XQSPI instance
1090 * @param cmd This value is specified by different QSPI FLASH memory vendor to enter into its status register
1091 * to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF.
1092 * @retval None
1093 */
1094 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
1095 {
1096 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
1097 }
1098
1099 /**
1100 * @brief Get high performance command
1101 *
1102 * \rst
1103 * +----------------------+-----------------------------------+
1104 * | Register | BitsName |
1105 * +======================+===================================+
1106 * | CTRL2 | CFG_HPMODE |
1107 * +----------------------+-----------------------------------+
1108 * \endrst
1109 *
1110 * @param XQSPIx XQSPI instance
1111 * @retval Returned Value can between: 0 ~ 0xFF.
1112 */
1113 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
1114 {
1115 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
1116 }
1117
1118 /**
1119 * @brief Set dummy cycles in command
1120 * @note These bits should not be changed when XIP is ongoing.
1121 * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1122 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1123 * - Fast Read Dual Out: dummycycles = 8 * cycles
1124 * - Fast Read Quad Out: dummycycles = 8 * cycles
1125 *
1126 * \rst
1127 * +----------------------+-----------------------------------+
1128 * | Register | BitsName |
1129 * +======================+===================================+
1130 * | CTRL2 | CFG_DUMMYCYCLES |
1131 * +----------------------+-----------------------------------+
1132 * \endrst
1133 *
1134 * @param XQSPIx XQSPI instance
1135 * @param cycles This parameter can between: 0 ~ 0xF.
1136 * @retval None
1137 */
1138 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
1139 {
1140 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1141 }
1142
1143 /**
1144 * @brief Get dummy cycles in command
1145 * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1146 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1147 * - Fast Read Dual Out: dummycycles = 8 * cycles
1148 * - Fast Read Quad Out: dummycycles = 8 * cycles
1149 *
1150 * \rst
1151 * +----------------------+-----------------------------------+
1152 * | Register | BitsName |
1153 * +======================+===================================+
1154 * | CTRL2 | CFG_DUMMYCYCLES |
1155 * +----------------------+-----------------------------------+
1156 * \endrst
1157 *
1158 * @param XQSPIx XQSPI instance
1159 * @retval Returned Value can between: 0 ~ 0xF.
1160 */
1161 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1162 {
1163 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES));
1164 }
1165
1166 /**
1167 * @brief Set dummy cycles in high performance end
1168 * @note These bits should not be changed when XIP is ongoing.
1169 *
1170 * \rst
1171 * +----------------------+-----------------------------------+
1172 * | Register | BitsName |
1173 * +======================+===================================+
1174 * | CTRL2 | CFG_ENDDUMMY |
1175 * +----------------------+-----------------------------------+
1176 * \endrst
1177 *
1178 * @param XQSPIx XQSPI instance
1179 * @param cycles This parameter can between: 0 ~ 3.
1180 * @retval None
1181 */
1182 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1183 {
1184 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1185 }
1186
1187 /**
1188 * @brief Get dummy cycles in high performance end
1189 *
1190 * \rst
1191 * +----------------------+-----------------------------------+
1192 * | Register | BitsName |
1193 * +======================+===================================+
1194 * | CTRL2 | CFG_ENDDUMMY |
1195 * +----------------------+-----------------------------------+
1196 * \endrst
1197 *
1198 * @param XQSPIx XQSPI instance
1199 * @retval Returned Value can between: 0 ~ 3.
1200 */
1201 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1202 {
1203 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1204 }
1205
1206 /**
1207 * @brief Enable XIP mode
1208 *
1209 * \rst
1210 * +----------------------+-----------------------------------+
1211 * | Register | BitsName |
1212 * +======================+===================================+
1213 * | CTRL3 | EN_REQ |
1214 * +----------------------+-----------------------------------+
1215 * \endrst
1216 *
1217 * @param XQSPIx XQSPI instance
1218 * @retval None
1219 */
1220 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1221 {
1222 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1223 }
1224
1225 /**
1226 * @brief Disable XIP mode
1227 *
1228 * \rst
1229 * +----------------------+-----------------------------------+
1230 * | Register | BitsName |
1231 * +======================+===================================+
1232 * | CTRL3 | EN_REQ |
1233 * +----------------------+-----------------------------------+
1234 * \endrst
1235 *
1236 * @param XQSPIx XQSPI instance
1237 * @retval None
1238 */
1239 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1240 {
1241 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1242 }
1243
1244 /**
1245 * @brief Check if XIP mode is enabled
1246 * @note This bit should not be changed when XIP is ongoing.
1247 *
1248 * \rst
1249 * +----------------------+-----------------------------------+
1250 * | Register | BitsName |
1251 * +======================+===================================+
1252 * | CTRL3 | EN_REQ |
1253 * +----------------------+-----------------------------------+
1254 * \endrst
1255 *
1256 * @param XQSPIx XQSPI instance
1257 * @retval State of bit (1 or 0).
1258 */
1259 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1260 {
1261 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1262 }
1263
1264 /**
1265 * @brief Get XIP status
1266 * @note This bit is read-only.
1267 *
1268 * \rst
1269 * +----------------------+-----------------------------------+
1270 * | Register | BitsName |
1271 * +======================+===================================+
1272 * | STAT | EN_OUT |
1273 * +----------------------+-----------------------------------+
1274 * \endrst
1275 *
1276 * @param XQSPIx XQSPI instance
1277 * @retval Returned Value can between: 0 ~ 1
1278 */
1279 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1280 {
1281 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1282 }
1283
1284 /**
1285 * @brief Check if XIP interrupt is enabled
1286 * @note This bit is read-only.
1287 *
1288 * \rst
1289 * +----------------------+-----------------------------------+
1290 * | Register | BitsName |
1291 * +======================+===================================+
1292 * | INTEN | INT_EN |
1293 * +----------------------+-----------------------------------+
1294 * \endrst
1295 *
1296 * @param XQSPIx XQSPI instance
1297 * @retval Returned Value can between: 0 ~ 1
1298 */
1299 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1300 {
1301 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1302 }
1303
1304 /**
1305 * @brief Get XIP interrupt flag
1306 * @note This bit is read-only.
1307 *
1308 * \rst
1309 * +----------------------+-----------------------------------+
1310 * | Register | BitsName |
1311 * +======================+===================================+
1312 * | INTSTAT | INT_STAT |
1313 * +----------------------+-----------------------------------+
1314 * \endrst
1315 *
1316 * @param XQSPIx XQSPI instance
1317 * @retval Returned Value can between: 0 ~ 1
1318 */
1319 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1320 {
1321 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1322 }
1323
1324 /**
1325 * @brief Get XIP interrupt request
1326 * @note This bit is read-only.
1327 *
1328 * \rst
1329 * +----------------------+-----------------------------------+
1330 * | Register | BitsName |
1331 * +======================+===================================+
1332 * | INTREQ | INT_REQ |
1333 * +----------------------+-----------------------------------+
1334 * \endrst
1335 *
1336 * @param XQSPIx XQSPI instance
1337 * @retval Returned Value can between: 0 ~ 1
1338 */
1339 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1340 {
1341 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1342 }
1343
1344 /**
1345 * @brief Set XIP interrupt enable
1346 * @note This bit is write-only.
1347 *
1348 * \rst
1349 * +----------------------+-----------------------------------+
1350 * | Register | BitsName |
1351 * +======================+===================================+
1352 * | INTSET | INT_SET |
1353 * +----------------------+-----------------------------------+
1354 * \endrst
1355 *
1356 * @param XQSPIx XQSPI instance
1357 * @retval None
1358 */
1359 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1360 {
1361 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1362 }
1363
1364 /**
1365 * @brief Set XIP interrupt disable
1366 * @note This bit is write-only.
1367 *
1368 * \rst
1369 * +----------------------+-----------------------------------+
1370 * | Register | BitsName |
1371 * +======================+===================================+
1372 * | INTCLR | INT_CLR |
1373 * +----------------------+-----------------------------------+
1374 * \endrst
1375 *
1376 * @param XQSPIx XQSPI instance
1377 * @retval None
1378 */
1379 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1380 {
1381 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1382 }
1383
1384 /** @} */
1385
1386 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1387 * @{
1388 */
1389
1390 /**
1391 * @brief Write 8-bit in the data register
1392 *
1393 * \rst
1394 * +----------------------+-----------------------------+
1395 * | Register | BitsName |
1396 * +======================+=============================+
1397 * | TX_DATA | DATA |
1398 * +----------------------+-----------------------------+
1399 * \endrst
1400 *
1401 * @param XQSPIx XQSPI instance
1402 * @param tx_data This parameter can between: 0x00 ~ 0xFF
1403 * @retval None
1404 */
1405 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1406 {
1407 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1408 }
1409
1410 /**
1411 * @brief Write 16-bit in the data register
1412 *
1413 * \rst
1414 * +----------------------+-----------------------------+
1415 * | Register | BitsName |
1416 * +======================+=============================+
1417 * | TX_DATA | DATA |
1418 * +----------------------+-----------------------------+
1419 * \endrst
1420 *
1421 * @param XQSPIx XQSPI instance
1422 * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1423 * @retval None
1424 */
1425 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1426 {
1427 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1428 }
1429
1430 /**
1431 * @brief Write 32-bit in the data register
1432 *
1433 * \rst
1434 * +----------------------+-----------------------------+
1435 * | Register | BitsName |
1436 * +======================+=============================+
1437 * | TX_DATA | DATA |
1438 * +----------------------+-----------------------------+
1439 * \endrst
1440 *
1441 * @param XQSPIx XQSPI instance
1442 * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1443 * @retval None
1444 */
1445 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1446 {
1447 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1448 }
1449
1450 /**
1451 * @brief Read 8 bits in the data register
1452 *
1453 * \rst
1454 * +----------------------+-----------------------------+
1455 * | Register | BitsName |
1456 * +======================+=============================+
1457 * | RX_DATA | DATA |
1458 * +----------------------+-----------------------------+
1459 * \endrst
1460 *
1461 * @param XQSPIx XQSPI instance
1462 * @retval Returned Value between: 0x00 ~ 0xFF
1463 */
1464 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1465 {
1466 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1467 }
1468
1469 /**
1470 * @brief Read 16 bits in the data register
1471 *
1472 * \rst
1473 * +----------------------+-----------------------------+
1474 * | Register | BitsName |
1475 * +======================+=============================+
1476 * | RX_DATA | DATA |
1477 * +----------------------+-----------------------------+
1478 * \endrst
1479 *
1480 * @param XQSPIx XQSPI instance
1481 * @retval Returned Value between: 0x00 ~ 0xFFFF
1482 */
1483 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1484 {
1485 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1486 }
1487
1488 /**
1489 * @brief Read 32 bits in the data register
1490 *
1491 * \rst
1492 * +----------------------+-----------------------------+
1493 * | Register | BitsName |
1494 * +======================+=============================+
1495 * | RX_DATA | DATA |
1496 * +----------------------+-----------------------------+
1497 * \endrst
1498 *
1499 * @param XQSPIx XQSPI instance
1500 * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1501 */
1502 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1503 {
1504 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1505 }
1506
1507 /**
1508 * @brief Set TX FIFO threshold level
1509 * @note FIFO maximum depth is 16 units.
1510 *
1511 * \rst
1512 * +----------------------+-----------------------------------+
1513 * | Register | BitsName |
1514 * +======================+===================================+
1515 * | CTRL | TXWMARK |
1516 * +----------------------+-----------------------------------+
1517 * \endrst
1518 *
1519 * @param XQSPIx XQSPI instance
1520 * @param threshold This parameter can be one of the following values:
1521 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1522 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1523 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1524 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1525 * @retval None
1526 */
1527 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1528 {
1529 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1530 }
1531
1532 /**
1533 * @brief Get TX FIFO threshold level
1534 * @note FIFO maximum depth is 16 units.
1535 *
1536 * \rst
1537 * +----------------------+-----------------------------------+
1538 * | Register | BitsName |
1539 * +======================+===================================+
1540 * | CTRL | TXWMARK |
1541 * +----------------------+-----------------------------------+
1542 * \endrst
1543 *
1544 * @param XQSPIx XQSPI instance
1545 * @retval Returned Value can be one of the following values:
1546 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1547 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1548 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1549 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1550 */
1551 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1552 {
1553 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1554 }
1555
1556 /**
1557 * @brief Set RX FIFO threshold level
1558 * @note FIFO maximum depth is 16 units.
1559 *
1560 * \rst
1561 * +----------------------+-----------------------------------+
1562 * | Register | BitsName |
1563 * +======================+===================================+
1564 * | CTRL | RXWMARK |
1565 * +----------------------+-----------------------------------+
1566 * \endrst
1567 *
1568 * @param XQSPIx XQSPI instance
1569 * @param threshold This parameter can be one of the following values:
1570 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1571 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1572 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1573 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1574 * @retval None
1575 */
1576 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1577 {
1578 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1579 }
1580
1581 /**
1582 * @brief Get RX FIFO threshold level
1583 * @note FIFO maximum depth is 16 units.
1584 *
1585 * \rst
1586 * +----------------------+-----------------------------------+
1587 * | Register | BitsName |
1588 * +======================+===================================+
1589 * | CTRL | RXWMARK |
1590 * +----------------------+-----------------------------------+
1591 * \endrst
1592 *
1593 * @param XQSPIx XQSPI instance
1594 * @retval Returned Value can be one of the following values:
1595 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1596 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1597 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1598 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1599 */
1600 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1601 {
1602 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1603 }
1604
1605 /**
1606 * @brief Enable dummy cycles
1607 *
1608 * \rst
1609 * +----------------------+-----------------------------------+
1610 * | Register | BitsName |
1611 * +======================+===================================+
1612 * | CTRL | MWAITEN |
1613 * +----------------------+-----------------------------------+
1614 * \endrst
1615 *
1616 * @param XQSPIx XQSPI instance
1617 * @retval None
1618 */
1619 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1620 {
1621 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1622 }
1623
1624 /**
1625 * @brief Disable dummy cycles
1626 *
1627 * \rst
1628 * +----------------------+-----------------------------------+
1629 * | Register | BitsName |
1630 * +======================+===================================+
1631 * | CTRL | MWAITEN |
1632 * +----------------------+-----------------------------------+
1633 * \endrst
1634 *
1635 * @param XQSPIx XQSPI instance
1636 * @retval None
1637 */
1638 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1639 {
1640 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1641 }
1642
1643 /**
1644 * @brief Check if dummy cycles is enabled
1645 *
1646 * \rst
1647 * +----------------------+-----------------------------------+
1648 * | Register | BitsName |
1649 * +======================+===================================+
1650 * | CTRL | MWAITEN |
1651 * +----------------------+-----------------------------------+
1652 * \endrst
1653 *
1654 * @param XQSPIx XQSPI instance
1655 * @retval State of bit (1 or 0).
1656 */
1657 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1658 {
1659 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1660 }
1661
1662 /**
1663 * @brief Enable DMA mode
1664 *
1665 * \rst
1666 * +----------------------+-----------------------------------+
1667 * | Register | BitsName |
1668 * +======================+===================================+
1669 * | CTRL | DMA |
1670 * +----------------------+-----------------------------------+
1671 * \endrst
1672 *
1673 * @param XQSPIx XQSPI instance
1674 * @retval None
1675 */
1676 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1677 {
1678 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1679 }
1680
1681 /**
1682 * @brief Disable DMA mode
1683 *
1684 * \rst
1685 * +----------------------+-----------------------------------+
1686 * | Register | BitsName |
1687 * +======================+===================================+
1688 * | CTRL | DMA |
1689 * +----------------------+-----------------------------------+
1690 * \endrst
1691 *
1692 * @param XQSPIx XQSPI instance
1693 * @retval None
1694 */
1695 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1696 {
1697 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1698 }
1699
1700 /**
1701 * @brief Check if DMA mode is enabled
1702 *
1703 * \rst
1704 * +----------------------+-----------------------------------+
1705 * | Register | BitsName |
1706 * +======================+===================================+
1707 * | CTRL | DMA |
1708 * +----------------------+-----------------------------------+
1709 * \endrst
1710 *
1711 * @param XQSPIx XQSPI instance
1712 * @retval State of bit (1 or 0).
1713 */
1714 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1715 {
1716 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1717 }
1718
1719 /**
1720 * @brief Set clock polarity
1721 * @note This bit should not be changed when communication is ongoing.
1722 *
1723 * \rst
1724 * +----------------------+-----------------------------------+
1725 * | Register | BitsName |
1726 * +======================+===================================+
1727 * | CTRL | CPOL |
1728 * +----------------------+-----------------------------------+
1729 * \endrst
1730 *
1731 * @param XQSPIx XQSPI instance
1732 * @param cpol This parameter can be one of the following values:
1733 * @arg @ref LL_XQSPI_SCPOL_LOW
1734 * @arg @ref LL_XQSPI_SCPOL_HIGH
1735 * @retval None
1736 */
1737 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1738 {
1739 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1740 }
1741
1742 /**
1743 * @brief Get clock polarity
1744 *
1745 * \rst
1746 * +----------------------+-----------------------------------+
1747 * | Register | BitsName |
1748 * +======================+===================================+
1749 * | CTRL | CPOL |
1750 * +----------------------+-----------------------------------+
1751 * \endrst
1752 *
1753 * @param XQSPIx XQSPI instance
1754 * @retval Returned Value can be one of the following values:
1755 * @arg @ref LL_XQSPI_SCPOL_LOW
1756 * @arg @ref LL_XQSPI_SCPOL_HIGH
1757 */
1758 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1759 {
1760 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1761 }
1762
1763 /**
1764 * @brief Set clock phase
1765 * @note This bit should not be changed when communication is ongoing.
1766 *
1767 * \rst
1768 * +----------------------+-----------------------------------+
1769 * | Register | BitsName |
1770 * +======================+===================================+
1771 * | CTRL | CPHA |
1772 * +----------------------+-----------------------------------+
1773 * \endrst
1774 *
1775 * @param XQSPIx XQSPI instance
1776 * @param cpha This parameter can be one of the following values:
1777 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1778 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1779 * @retval None
1780 */
1781 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1782 {
1783 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1784 }
1785
1786 /**
1787 * @brief Get clock phase
1788 *
1789 * \rst
1790 * +----------------------+-----------------------------------+
1791 * | Register | BitsName |
1792 * +======================+===================================+
1793 * | CTRL | CPHA |
1794 * +----------------------+-----------------------------------+
1795 * \endrst
1796 *
1797 * @param XQSPIx XQSPI instance
1798 * @retval Returned Value can be one of the following values:
1799 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1800 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1801 */
1802 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1803 {
1804 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1805 }
1806
1807 /**
1808 * @brief Set serial data order
1809 *
1810 * \rst
1811 * +----------------------+-----------------------------------+
1812 * | Register | BitsName |
1813 * +======================+===================================+
1814 * | CTRL | MSB1ST |
1815 * +----------------------+-----------------------------------+
1816 * \endrst
1817 *
1818 * @param XQSPIx XQSPI instance
1819 * @param order This parameter can be one of the following values:
1820 * @arg @ref LL_XQSPI_QSPI_LSB
1821 * @arg @ref LL_XQSPI_QSPI_MSB
1822 * @retval None
1823 */
1824 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1825 {
1826 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1827 }
1828
1829 /**
1830 * @brief Get serial data order
1831 *
1832 * \rst
1833 * +----------------------+-----------------------------------+
1834 * | Register | BitsName |
1835 * +======================+===================================+
1836 * | CTRL | MSB1ST |
1837 * +----------------------+-----------------------------------+
1838 * \endrst
1839 *
1840 * @param XQSPIx XQSPI instance
1841 * @retval Returned Value can be one of the following values:
1842 * @arg @ref LL_XQSPI_QSPI_LSB
1843 * @arg @ref LL_XQSPI_QSPI_MSB
1844 */
1845 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1846 {
1847 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1848 }
1849
1850 /**
1851 * @brief Enable continuous transfer mode
1852 *
1853 * \rst
1854 * +----------------------+-----------------------------------+
1855 * | Register | BitsName |
1856 * +======================+===================================+
1857 * | CTRL | CONTXFER |
1858 * +----------------------+-----------------------------------+
1859 * \endrst
1860 *
1861 * @param XQSPIx XQSPI instance
1862 * @retval None
1863 */
1864 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1865 {
1866 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1867 }
1868
1869 /**
1870 * @brief Disable continuous transfer mode
1871 *
1872 * \rst
1873 * +----------------------+-----------------------------------+
1874 * | Register | BitsName |
1875 * +======================+===================================+
1876 * | CTRL | CONTXFER |
1877 * +----------------------+-----------------------------------+
1878 * \endrst
1879 *
1880 * @param XQSPIx XQSPI instance
1881 * @retval None
1882 */
1883 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1884 {
1885 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1886 }
1887
1888 /**
1889 * @brief Check if continuous transfer mode is enabled
1890 *
1891 * \rst
1892 * +----------------------+-----------------------------------+
1893 * | Register | BitsName |
1894 * +======================+===================================+
1895 * | CTRL | CONTXFER |
1896 * +----------------------+-----------------------------------+
1897 * \endrst
1898 *
1899 * @param XQSPIx XQSPI instance
1900 * @retval State of bit (1 or 0).
1901 */
1902 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1903 {
1904 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1905 }
1906
1907 /**
1908 * @brief Enable continuous transfer extend mode
1909 *
1910 * \rst
1911 * +----------------------+-----------------------------------+
1912 * | Register | BitsName |
1913 * +======================+===================================+
1914 * | AUX_CTRL | CONTXFERX |
1915 * +----------------------+-----------------------------------+
1916 * \endrst
1917 *
1918 * @param XQSPIx XQSPI instance
1919 * @retval None
1920 */
1921 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1922 {
1923 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1924 }
1925
1926 /**
1927 * @brief Disable continuous transfer extend mode
1928 *
1929 * \rst
1930 * +----------------------+-----------------------------------+
1931 * | Register | BitsName |
1932 * +======================+===================================+
1933 * | AUX_CTRL | CONTXFERX |
1934 * +----------------------+-----------------------------------+
1935 * \endrst
1936 *
1937 * @param XQSPIx XQSPI instance
1938 * @retval None
1939 */
1940 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1941 {
1942 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1943 }
1944
1945 /**
1946 * @brief Check if continuous transfer extend mode is enabled
1947 *
1948 * \rst
1949 * +----------------------+-----------------------------------+
1950 * | Register | BitsName |
1951 * +======================+===================================+
1952 * | AUX_CTRL | CONTXFERX |
1953 * +----------------------+-----------------------------------+
1954 * \endrst
1955 *
1956 * @param XQSPIx XQSPI instance
1957 * @retval State of bit (1 or 0).
1958 */
1959 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1960 {
1961 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1962 }
1963
1964 /**
1965 * @brief Set data size
1966 * @note These bits should not be changed when communication is ongoing.
1967 *
1968 * \rst
1969 * +----------------------+-----------------------------------+
1970 * | Register | BitsName |
1971 * +======================+===================================+
1972 * | AUX_CTRL | BITSIZE |
1973 * +----------------------+-----------------------------------+
1974 * \endrst
1975 *
1976 * @param XQSPIx XQSPI instance
1977 * @param szie This parameter can be one of the following values:
1978 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1979 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1980 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1981 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1982 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1983 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1984 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1985 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1986 * @retval None
1987 */
1988 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1989 {
1990 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1991 }
1992
1993 /**
1994 * @brief Get data size
1995 *
1996 * \rst
1997 * +----------------------+-----------------------------------+
1998 * | Register | BitsName |
1999 * +======================+===================================+
2000 * | AUX_CTRL | BITSIZE |
2001 * +----------------------+-----------------------------------+
2002 * \endrst
2003 *
2004 * @param XQSPIx XQSPI instance
2005 * @retval Returned Value can be one of the following values:
2006 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
2007 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
2008 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
2009 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
2010 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
2011 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
2012 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
2013 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
2014 */
2015 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
2016 {
2017 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
2018 }
2019
2020 /**
2021 * @brief Enable inhibt data input to RX FIFO
2022 *
2023 * \rst
2024 * +----------------------+-----------------------------------+
2025 * | Register | BitsName |
2026 * +======================+===================================+
2027 * | AUX_CTRL | INHIBITDIN |
2028 * +----------------------+-----------------------------------+
2029 * \endrst
2030 *
2031 * @param XQSPIx XQSPI instance
2032 * @retval None
2033 */
2034 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
2035 {
2036 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
2037 }
2038
2039 /**
2040 * @brief Disable inhibt data input to RX FIFO
2041 *
2042 * \rst
2043 * +----------------------+-----------------------------------+
2044 * | Register | BitsName |
2045 * +======================+===================================+
2046 * | AUX_CTRL | INHIBITDIN |
2047 * +----------------------+-----------------------------------+
2048 * \endrst
2049 *
2050 * @param XQSPIx XQSPI instance
2051 * @retval None
2052 */
2053 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
2054 {
2055 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
2056 }
2057
2058 /**
2059 * @brief Check if inhibt data input to RX FIFO is enabled
2060 *
2061 * \rst
2062 * +----------------------+-----------------------------------+
2063 * | Register | BitsName |
2064 * +======================+===================================+
2065 * | AUX_CTRL | INHIBITDIN |
2066 * +----------------------+-----------------------------------+
2067 * \endrst
2068 *
2069 * @param XQSPIx XQSPI instance
2070 * @retval State of bit (1 or 0).
2071 */
2072 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
2073 {
2074 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
2075 }
2076
2077 /**
2078 * @brief Enable inhibt data output to TX FIFO
2079 *
2080 * \rst
2081 * +----------------------+-----------------------------------+
2082 * | Register | BitsName |
2083 * +======================+===================================+
2084 * | AUX_CTRL | INHIBITDOUT |
2085 * +----------------------+-----------------------------------+
2086 * \endrst
2087 *
2088 * @param XQSPIx XQSPI instance
2089 * @retval None
2090 */
2091 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
2092 {
2093 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
2094 }
2095
2096 /**
2097 * @brief Disable inhibt data output to TX FIFO
2098 *
2099 * \rst
2100 * +----------------------+-----------------------------------+
2101 * | Register | BitsName |
2102 * +======================+===================================+
2103 * | AUX_CTRL | INHIBITDOUT |
2104 * +----------------------+-----------------------------------+
2105 * \endrst
2106 *
2107 * @param XQSPIx XQSPI instance
2108 * @retval None
2109 */
2110 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
2111 {
2112 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
2113 }
2114
2115 /**
2116 * @brief Check if inhibt data input to TX FIFO is enabled
2117 *
2118 * \rst
2119 * +----------------------+-----------------------------------+
2120 * | Register | BitsName |
2121 * +======================+===================================+
2122 * | AUX_CTRL | INHIBITDOUT |
2123 * +----------------------+-----------------------------------+
2124 * \endrst
2125 *
2126 * @param XQSPIx XQSPI instance
2127 * @retval State of bit (1 or 0).
2128 */
2129 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
2130 {
2131 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
2132 }
2133
2134 /**
2135 * @brief Set frame format
2136 * @note These bits should not be changed when communication is ongoing.
2137 *
2138 * \rst
2139 * +----------------------+-----------------------------------+
2140 * | Register | BitsName |
2141 * +======================+===================================+
2142 * | AUX_CTRL | QMODE |
2143 * +----------------------+-----------------------------------+
2144 * \endrst
2145 *
2146 * @param XQSPIx XQSPI instance
2147 * @param format This parameter can be one of the following values:
2148 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
2149 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
2150 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
2151 * @retval None
2152 */
2153 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
2154 {
2155 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
2156 }
2157
2158 /**
2159 * @brief Get frame format
2160 *
2161 * \rst
2162 * +----------------------+-----------------------------------+
2163 * | Register | BitsName |
2164 * +======================+===================================+
2165 * | AUX_CTRL | QMODE |
2166 * +----------------------+-----------------------------------+
2167 * \endrst
2168 *
2169 * @param XQSPIx XQSPI instance
2170 * @retval Returned Value can be one even value:
2171 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
2172 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
2173 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
2174 */
2175 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
2176 {
2177 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
2178 }
2179
2180 /**
2181 * @brief Get QSPI status
2182 *
2183 * \rst
2184 * +----------------------+------------------------------------------------------+
2185 * | Register | BitsName |
2186 * +======================+======================================================+
2187 * | STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP |
2188 * +----------------------+------------------------------------------------------+
2189 * \endrst
2190 *
2191 * @param XQSPIx XQSPI instance
2192 * @retval Returned Value can be one or combination of the following values:
2193 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
2194 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
2195 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
2196 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
2197 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
2198 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
2199 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
2200 */
2201 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
2202 {
2203 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
2204 }
2205
2206 /**
2207 * @brief Check active flag
2208 *
2209 * \rst
2210 * +----------------------+------------------------------------------------------+
2211 * | Register | BitsName |
2212 * +======================+======================================================+
2213 * | STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP |
2214 * +----------------------+------------------------------------------------------+
2215 * \endrst
2216 *
2217 * @param XQSPIx XQSPI instance
2218 * @param flag This parameter can be one of the following values:
2219 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
2220 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
2221 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
2222 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
2223 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
2224 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
2225 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
2226 * @retval State of bit (1 or 0).
2227 */
2228 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2229 {
2230 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
2231 }
2232
2233 /**
2234 * @brief Enable slave select output
2235 *
2236 * \rst
2237 * +----------------------+-----------------------------------+
2238 * | Register | BitsName |
2239 * +======================+===================================+
2240 * | SLAVE_SEL | OUT3 OUT2 OUT1 OUT0 |
2241 * +----------------------+-----------------------------------+
2242 * \endrst
2243 *
2244 * @param XQSPIx XQSPI instance
2245 * @param ssout This parameter can between: 0 ~ 0xFF
2246 * @retval None
2247 */
2248 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2249 {
2250 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2251 }
2252
2253 /**
2254 * @brief Disable slave select output
2255 *
2256 * \rst
2257 * +----------------------+-----------------------------------+
2258 * | Register | BitsName |
2259 * +======================+===================================+
2260 * | SLAVE_SEL | OUT3 OUT2 OUT1 OUT0 |
2261 * +----------------------+-----------------------------------+
2262 * \endrst
2263 *
2264 * @param XQSPIx XQSPI instance
2265 * @param ssout This parameter can between: 0 ~ 0xFF
2266 * @retval None
2267 */
2268 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2269 {
2270 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2271 }
2272
2273 /**
2274 * @brief Set slave select output polarity
2275 *
2276 * \rst
2277 * +----------------------+-----------------------------------+
2278 * | Register | BitsName |
2279 * +======================+===================================+
2280 * | SLAVE_SEL_POL | POL3 POL2 POL1 POL0 |
2281 * +----------------------+-----------------------------------+
2282 * \endrst
2283 *
2284 * @param XQSPIx XQSPI instance
2285 * @param sspol This parameter can between: 0 ~ 0xFF
2286 * @retval None
2287 */
2288 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
2289 {
2290 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
2291 }
2292
2293 /**
2294 * @brief Get slave select output polarity
2295 *
2296 * \rst
2297 * +----------------------+-----------------------------------+
2298 * | Register | BitsName |
2299 * +======================+===================================+
2300 * | SLAVE_SEL_POL | POL3 POL2 POL1 POL0 |
2301 * +----------------------+-----------------------------------+
2302 * \endrst
2303 *
2304 * @param XQSPIx XQSPI instance
2305 * @retval Returned Value can between: 0 ~ 0xFF
2306 */
2307 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
2308 {
2309 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
2310 }
2311
2312 /**
2313 * @brief Get FIFO Transmission Level
2314 *
2315 * \rst
2316 * +----------------------+-----------------------------------+
2317 * | Register | BitsName |
2318 * +======================+===================================+
2319 * | TX_FIFO_LVL | TXFIFOLVL |
2320 * +----------------------+-----------------------------------+
2321 * \endrst
2322 *
2323 * @param XQSPIx XQSPI instance
2324 * @retval Returned Value can between: 0 ~ 16
2325 */
2326 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
2327 {
2328 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
2329 }
2330
2331 /**
2332 * @brief Get FIFO reception Level
2333 *
2334 * \rst
2335 * +----------------------+-----------------------------------+
2336 * | Register | BitsName |
2337 * +======================+===================================+
2338 * | RX_FIFO_LVL | RXFIFOLVL |
2339 * +----------------------+-----------------------------------+
2340 * \endrst
2341 *
2342 * @param XQSPIx XQSPI instance
2343 * @retval Returned Value can between: 0 ~ 16
2344 */
2345 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
2346 {
2347 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
2348 }
2349
2350 /**
2351 * @brief Enable interrupt
2352 * @note This bit controls the generation of an interrupt when an event occurs.
2353 *
2354 * \rst
2355 * +----------------------+-----------------------------------+
2356 * | Register | BitsName |
2357 * +======================+===================================+
2358 * | INTEN | INT_EN |
2359 * +----------------------+-----------------------------------+
2360 * \endrst
2361 *
2362 * @param XQSPIx XQSPI instance
2363 * @param mask This parameter can be one of the following values:
2364 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2365 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2366 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2367 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2368 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2369 * @retval None
2370 */
2371 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2372 {
2373 SET_BITS(XQSPIx->QSPI.INTEN, mask);
2374 }
2375
2376 /**
2377 * @brief Disable interrupt
2378 * @note This bit controls the generation of an interrupt when an event occurs.
2379 *
2380 * \rst
2381 * +----------------------+-----------------------------------+
2382 * | Register | BitsName |
2383 * +======================+===================================+
2384 * | INTEN | INT_EN |
2385 * +----------------------+-----------------------------------+
2386 * \endrst
2387 *
2388 * @param XQSPIx XQSPI instance
2389 * @param mask This parameter can be one of the following values:
2390 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2391 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2392 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2393 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2394 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2395 * @retval None
2396 */
2397 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2398 {
2399 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2400 }
2401
2402 /**
2403 * @brief Check if interrupt is enabled
2404 *
2405 * \rst
2406 * +----------------------+-----------------------------------+
2407 * | Register | BitsName |
2408 * +======================+===================================+
2409 * | INTEN | INT_EN |
2410 * +----------------------+-----------------------------------+
2411 * \endrst
2412 *
2413 * @param XQSPIx XQSPI instance
2414 * @param mask This parameter can be one of the following values:
2415 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2416 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2417 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2418 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2419 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2420 * @retval State of bit (1 or 0).
2421 */
2422 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2423 {
2424 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2425 }
2426
2427 /**
2428 * @brief Get XQSPI interrupt flags
2429 *
2430 * \rst
2431 * +----------------------+-----------------------------------+
2432 * | Register | BitsName |
2433 * +======================+===================================+
2434 * | INTSTAT | INT_STAT |
2435 * +----------------------+-----------------------------------+
2436 * \endrst
2437 *
2438 * @param XQSPIx XQSPI instance
2439 * @retval Returned Value can be one or combination of the following values:
2440 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2441 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2442 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2443 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2444 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2445 */
2446 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2447 {
2448 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2449 }
2450
2451 /**
2452 * @brief Check interrupt flag
2453 *
2454 * \rst
2455 * +----------------------+-----------------------------------+
2456 * | Register | BitsName |
2457 * +======================+===================================+
2458 * | INTSTAT | XFER_DPULSE |
2459 * +----------------------+-----------------------------------+
2460 * \endrst
2461 * INTSTAT | RX_FPULSE
2462 * INTSTAT | RX_WPULSE
2463 * INTSTAT | TX_WPULSE
2464 * INTSTAT | TX_EPULSE
2465 *
2466 * @param XQSPIx XQSPI instance
2467 * @param flag This parameter can be one of the following values:
2468 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2469 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2470 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2471 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2472 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2473 * @retval State of bit (1 or 0).
2474 */
2475 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2476 {
2477 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2478 }
2479
2480 /**
2481 * @brief Clear interrupt flag
2482 * @note Clearing interrupt flag is done by writting INTCLR register
2483 *
2484 * \rst
2485 * +----------------------+-----------------------------------+
2486 * | Register | BitsName |
2487 * +======================+===================================+
2488 * | INTCLR | INT_CLR |
2489 * +----------------------+-----------------------------------+
2490 * \endrst
2491 *
2492 * @param XQSPIx XQSPI instance
2493 * @param flag This parameter can be one of the following values:
2494 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2495 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2496 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2497 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2498 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2499 * @retval None
2500 */
2501 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2502 {
2503 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2504 }
2505
2506 /**
2507 * @brief Set master inter-transfer delay
2508 *
2509 * \rst
2510 * +----------------------+-----------------------------------+
2511 * | Register | BitsName |
2512 * +======================+===================================+
2513 * | MSTR_IT_DELAY | MWAIT |
2514 * +----------------------+-----------------------------------+
2515 * \endrst
2516 *
2517 * @param XQSPIx XQSPI instance
2518 * @param wait This parameter can between: 0 ~ 255
2519 * @retval None
2520 */
2521 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2522 {
2523 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2524 }
2525
2526 /**
2527 * @brief Get master inter-transfer delay
2528 *
2529 * \rst
2530 * +----------------------+-----------------------------------+
2531 * | Register | BitsName |
2532 * +======================+===================================+
2533 * | MSTR_IT_DELAY | MWAIT |
2534 * +----------------------+-----------------------------------+
2535 * \endrst
2536 *
2537 * @param XQSPIx XQSPI instance
2538 * @retval Returned Value can between: 0 ~ 255
2539 */
2540 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2541 {
2542 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2543 }
2544
2545 /**
2546 * @brief Enable QSPI
2547 * @note This bit should not be enable when XIP is ongoing.
2548 *
2549 * \rst
2550 * +----------------------+-----------------------------------+
2551 * | Register | BitsName |
2552 * +======================+===================================+
2553 * | SPIEN | EN |
2554 * +----------------------+-----------------------------------+
2555 * \endrst
2556 *
2557 * @param XQSPIx XQSPI instance
2558 * @retval None
2559 */
2560 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2561 {
2562 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2563 }
2564
2565 /**
2566 * @brief Disable QSPI
2567 *
2568 * \rst
2569 * +----------------------+-----------------------------------+
2570 * | Register | BitsName |
2571 * +======================+===================================+
2572 * | SPIEN | EN |
2573 * +----------------------+-----------------------------------+
2574 * \endrst
2575 *
2576 * @param XQSPIx XQSPI instance
2577 * @retval None
2578 */
2579 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2580 {
2581 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2582 }
2583
2584 /**
2585 * @brief Check if QSPI is enabled
2586 *
2587 * \rst
2588 * +----------------------+-----------------------------------+
2589 * | Register | BitsName |
2590 * +======================+===================================+
2591 * | SPIEN | EN |
2592 * +----------------------+-----------------------------------+
2593 * \endrst
2594 *
2595 * @param XQSPIx XQSPI instance
2596 * @retval State of bit (1 or 0).
2597 */
2598 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2599 {
2600 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2601 }
2602
2603 /**
2604 * @brief Set QSPI Flash write bits
2605 *
2606 * \rst
2607 * +----------------------+-----------------------------------+
2608 * | Register | BitsName |
2609 * +======================+===================================+
2610 * | FLASH_WRITE | FLASH_WRITE |
2611 * +----------------------+-----------------------------------+
2612 * \endrst
2613 *
2614 * @param XQSPIx XQSPI instance
2615 * @param bits This parameter can be one of the following values:
2616 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2617 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2618 * @retval None
2619 */
2620 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2621 {
2622 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2623 }
2624
2625 /**
2626 * @brief Get QSPI Flash write bits
2627 *
2628 * \rst
2629 * +----------------------+-----------------------------------+
2630 * | Register | BitsName |
2631 * +======================+===================================+
2632 * | FLASH_WRITE | FLASH_WRITE |
2633 * +----------------------+-----------------------------------+
2634 * \endrst
2635 *
2636 * @param XQSPIx XQSPI instance
2637 * @retval Returned Value can be one of the following values:
2638 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2639 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2640 */
2641 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2642 {
2643 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2644 }
2645
2646 /**
2647 * @brief Set QSPI Present Bypass
2648 *
2649 * \rst
2650 * +----------------------+-----------------------------------+
2651 * | Register | BitsName |
2652 * +======================+===================================+
2653 * | BYPASS | BYPASS |
2654 * +----------------------+-----------------------------------+
2655 * \endrst
2656 *
2657 * @param XQSPIx XQSPI instance
2658 * @param bypass This parameter can be one of the following values:
2659 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2660 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2661 * @retval None
2662 */
2663 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2664 {
2665 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2666 }
2667
2668 /**
2669 * @brief Get QSPI Present Bypass
2670 *
2671 * \rst
2672 * +----------------------+-----------------------------------+
2673 * | Register | BitsName |
2674 * +======================+===================================+
2675 * | BYPASS | BYPASS |
2676 * +----------------------+-----------------------------------+
2677 * \endrst
2678 *
2679 * @param XQSPIx XQSPI instance
2680 * @retval Returned Value can be one of the following values:
2681 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2682 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2683 */
2684 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2685 {
2686 return READ_REG(XQSPIx->QSPI.BYPASS);
2687 }
2688
2689 /**
2690 * @brief Enable exflash power
2691 * @note This bit should not be changed when XIP is ongoing.
2692 *
2693 * \rst
2694 * +----------------------+-----------------------------------+
2695 * | Register | BitsName |
2696 * +======================+===================================+
2697 * | PWR_RET01 | EFLASH_PAD_EN |
2698 * +----------------------+-----------------------------------+
2699 * \endrst
2700 *
2701 * @retval None
2702 */
2703 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2704 {
2705 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2706 }
2707
2708 /**
2709 * @brief Disable exflash power
2710 * @note This bit should not be changed when XIP is ongoing.
2711 *
2712 * \rst
2713 * +----------------------+-----------------------------------+
2714 * | Register | BitsName |
2715 * +======================+===================================+
2716 * | PWR_RET01 | EFLASH_PAD_EN |
2717 * +----------------------+-----------------------------------+
2718 * \endrst
2719 *
2720 * @retval None
2721 */
2722 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2723 {
2724 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2725 }
2726
2727 /**
2728 * @brief Check if exflash power is enabled
2729 *
2730 * \rst
2731 * +----------------------+-----------------------------------+
2732 * | Register | BitsName |
2733 * +======================+===================================+
2734 * | PWR_RET01 | EFLASH_PAD_EN |
2735 * +----------------------+-----------------------------------+
2736 * \endrst
2737 *
2738 * @retval State of bit (1 or 0).
2739 */
2740 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2741 {
2742 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN) == (AON_PWR_REG01_EFLASH_PAD_EN));
2743 }
2744
2745 /**
2746 * @brief Set XQSPI serial clock
2747 *
2748 * \rst
2749 * +----------------------+-----------------------------------+
2750 * | Register | BitsName |
2751 * +======================+===================================+
2752 * | PWR_RET01 | XF_SCK_CLK_SEL |
2753 * +----------------------+-----------------------------------+
2754 * \endrst
2755 *
2756 * @param speed This parameter can be one of the following values:
2757 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2758 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2759 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2760 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2761 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2762 * @retval None
2763 */
2764 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2765 {
2766 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL, speed);
2767 }
2768
2769 /**
2770 * @brief Get XQSPI serial clock
2771 *
2772 * \rst
2773 * +----------------------+-----------------------------------+
2774 * | Register | BitsName |
2775 * +======================+===================================+
2776 * | PWR_RET01 | XF_SCK_CLK_SEL |
2777 * +----------------------+-----------------------------------+
2778 * \endrst
2779 *
2780 * @retval Returned Value can be one of the following values:
2781 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2782 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2783 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2784 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2785 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2786 */
2787 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2788 {
2789 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL));
2790 }
2791
2792 /**
2793 * @brief Enable cache data retention.
2794 * @note This bit should not be changed when XIP is ongoing..
2795 *
2796 * \rst
2797 * +----------------------+-----------------------------------+
2798 * | Register | BitsName |
2799 * +======================+===================================+
2800 * | PWR_RET01 | XF_TAG_RET |
2801 * +----------------------+-----------------------------------+
2802 * \endrst
2803 *
2804 * @retval None
2805 */
2806 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2807 {
2808 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2809 }
2810
2811 /**
2812 * @brief Disable cache data retention.
2813 * @note This bit should not be changed when XIP is ongoing.
2814 *
2815 * \rst
2816 * +----------------------+-----------------------------------+
2817 * | Register | BitsName |
2818 * +======================+===================================+
2819 * | PWR_RET01 | XF_TAG_RET |
2820 * +----------------------+-----------------------------------+
2821 * \endrst
2822 *
2823 * @retval None
2824 */
2825 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2826 {
2827 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2828 }
2829
2830 /**
2831 * @brief Check if tag memory retention is enabled
2832 *
2833 * \rst
2834 * +----------------------+-----------------------------------+
2835 * | Register | BitsName |
2836 * +======================+===================================+
2837 * | PWR_RET01 | XF_TAG_RET |
2838 * +----------------------+-----------------------------------+
2839 * \endrst
2840 *
2841 * @retval State of bit (1 or 0).
2842 */
2843 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2844 {
2845 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET) == (AON_PWR_REG01_XF_TAG_RET));
2846 }
2847
2848
2849
2850 /** @} */
2851
2852 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2853 * @{
2854 */
2855
2856 /**
2857 * @brief De-initialize XQSPI registers (Registers restored to their default values).
2858 * @param XQSPIx XQSPI instance
2859 * @retval An error_status_t enumeration value:
2860 * - SUCCESS: XQSPI registers are de-initialized
2861 * - ERROR: XQSPI registers are not de-initialized
2862 */
2863 error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2864
2865 /**
2866 * @brief Initialize XQSPI registers according to the specified
2867 * parameters in default.
2868 * @param XQSPIx XQSPI instance
2869 * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2870 * information for the specified XQPSI peripheral.
2871 * @retval An error_status_t enumeration value:
2872 * - SUCCESS: XQSPI registers are initialized according to default
2873 * - ERROR: Problem occurred during XQSPI Registers initialization
2874 */
2875 error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2876
2877 /**
2878 * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2879 * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2880 * whose fields will be set to default values.
2881 * @retval None
2882 */
2883 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2884
2885 /** @} */
2886
2887 /** @} */
2888
2889 #endif /* XQSPI */
2890
2891 #ifdef __cplusplus
2892 }
2893 #endif
2894
2895 #endif /* __GR55xx_LL_XQSPI_H__ */
2896
2897 /** @} */
2898
2899 /** @} */
2900
2901 /** @} */
ll_xqspi_set_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr55xx_ll_xqspi.h:1988
ll_xqspi_is_active_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_xqspi.h:2228
ll_xqspi_disable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr55xx_ll_xqspi.h:1239
ll_xqspi_is_enabled_cache
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr55xx_ll_xqspi.h:423
ll_xqspi_get_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:612
ll_xqspi_is_enabled_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr55xx_ll_xqspi.h:1902
ll_xqspi_set_xip_ss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr55xx_ll_xqspi.h:873
ll_xqspi_get_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr55xx_ll_xqspi.h:1845
ll_xqspi_is_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr55xx_ll_xqspi.h:2740
ll_xqspi_get_cache_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr55xx_ll_xqspi.h:731
ll_xqspi_is_enabled_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:1299
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_xqspi.h:101
ll_xqspi_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr55xx_ll_xqspi.h:2806
ll_xqspi_enable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr55xx_ll_xqspi.h:1676
ll_xqspi_qspi_transmit_data16
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1425
ll_xqspi_get_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr55xx_ll_xqspi.h:789
ll_xqspi_disable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr55xx_ll_xqspi.h:829
ll_xqspi_get_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr55xx_ll_xqspi.h:527
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate be used to configure the transmit and receive SCK clock.
Definition: gr55xx_ll_xqspi.h:111
ll_xqspi_get_xip_ss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr55xx_ll_xqspi.h:896
ll_xqspi_get_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:1758
ll_xqspi_disable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr55xx_ll_xqspi.h:2579
ll_xqspi_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr55xx_ll_xqspi.h:2703
ll_xqspi_disable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr55xx_ll_xqspi.h:2825
ll_xqspi_disable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1940
ll_xqspi_set_present_bypass
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
Set QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2663
ll_xqspi_set_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:1781
ll_xqspi_get_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr55xx_ll_xqspi.h:2446
ll_xqspi_get_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr55xx_ll_xqspi.h:1028
_ll_xqspi_init_t::data_order
uint32_t data_order
Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:96
ll_xqspi_enable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr55xx_ll_xqspi.h:632
ll_xqspi_is_enabled_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr55xx_ll_xqspi.h:671
ll_xqspi_enable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr55xx_ll_xqspi.h:809
ll_xqspi_is_enabled_cache_flush
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr55xx_ll_xqspi.h:482
ll_xqspi_set_flash_write
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2620
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Specifies the cache mode in XIP mode.
Definition: gr55xx_ll_xqspi.h:81
ll_xqspi_disable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr55xx_ll_xqspi.h:652
ll_xqspi_get_xip_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr55xx_ll_xqspi.h:1279
ll_xqspi_enable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_xqspi.h:2371
ll_xqspi_set_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr55xx_ll_xqspi.h:593
ll_xqspi_is_enabled_xip_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr55xx_ll_xqspi.h:848
ll_xqspi_disable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:2053
ll_xqspi_set_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr55xx_ll_xqspi.h:1094
ll_xqspi_enable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1864
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_get_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1600
ll_xqspi_enable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr55xx_ll_xqspi.h:1220
ll_xqspi_init
error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_get_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2540
ll_xqspi_is_enabled_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:2129
ll_xqspi_is_qspi_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_xqspi.h:2475
ll_xqspi_qspi_receive_data8
SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1464
ll_xqspi_get_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1201
ll_xqspi_is_enabled_qspi_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_xqspi.h:2422
ll_xqspi_is_enabled_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr55xx_ll_xqspi.h:1714
ll_xqspi_is_enabled_xip
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr55xx_ll_xqspi.h:1259
ll_xqspi_get_req_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr55xx_ll_xqspi.h:1339
ll_xqspi_deinit
error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_enable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr55xx_ll_xqspi.h:2560
ll_xqspi_get_flash_write
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr55xx_ll_xqspi.h:2641
ll_xqspi_disable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1638
ll_xqspi_set_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1527
ll_xqspi_get_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr55xx_ll_xqspi.h:2175
ll_xqspi_is_enabled_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr55xx_ll_xqspi.h:1657
ll_xqspi_enable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr55xx_ll_xqspi.h:1359
ll_xqspi_disable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:2110
ll_xqspi_is_enabled_qspi
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr55xx_ll_xqspi.h:2598
ll_xqspi_set_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr55xx_ll_xqspi.h:919
ll_xqspi_clear_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr55xx_ll_xqspi.h:2501
ll_xqspi_get_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr55xx_ll_xqspi.h:2307
ll_xqspi_qspi_transmit_data32
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1445
ll_xqspi_get_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2787
ll_xqspi_is_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr55xx_ll_xqspi.h:2843
ll_xqspi_disable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr55xx_ll_xqspi.h:2722
ll_xqspi_get_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:572
_ll_xqspi_init_t::mode
uint32_t mode
Specifies the work mode, XIP mode or QSPI mode.
Definition: gr55xx_ll_xqspi.h:78
ll_xqspi_set_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr55xx_ll_xqspi.h:2764
ll_xqspi_disable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_xqspi.h:2397
ll_xqspi_disable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr55xx_ll_xqspi.h:1695
ll_xqspi_qspi_receive_data32
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1502
ll_xqspi_enable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr55xx_ll_xqspi.h:1921
ll_xqspi_set_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:963
ll_xqspi_get_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr55xx_ll_xqspi.h:984
ll_xqspi_enable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr55xx_ll_xqspi.h:378
ll_xqspi_is_enabled_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr55xx_ll_xqspi.h:2072
ll_xqspi_disable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr55xx_ll_xqspi.h:1379
ll_xqspi_qspi_receive_data16
SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr55xx_ll_xqspi.h:1483
ll_xqspi_get_qspi_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr55xx_ll_xqspi.h:2201
ll_xqspi_get_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:940
ll_xqspi_set_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr55xx_ll_xqspi.h:1007
ll_xqspi_get_present_bypass
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
Get QSPI Present Bypass.
Definition: gr55xx_ll_xqspi.h:2684
ll_xqspi_set_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr55xx_ll_xqspi.h:2153
ll_xqspi_set_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr55xx_ll_xqspi.h:2521
ll_xqspi_is_enabled_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr55xx_ll_xqspi.h:1959
ll_xqspi_set_xip_endian
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr55xx_ll_xqspi.h:1051
ll_xqspi_set_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr55xx_ll_xqspi.h:1824
ll_xqspi_enable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr55xx_ll_xqspi.h:2248
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr55xx_ll_xqspi.h:77
ll_xqspi_disable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr55xx_ll_xqspi.h:2268
ll_xqspi_set_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr55xx_ll_xqspi.h:550
ll_xqspi_enable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr55xx_ll_xqspi.h:2091
ll_xqspi_disable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr55xx_ll_xqspi.h:1883
ll_xqspi_set_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr55xx_ll_xqspi.h:505
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_xqspi.h:106
ll_xqspi_get_flag_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr55xx_ll_xqspi.h:1319
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Specifies the XQSPI read command in XIP mode.
Definition: gr55xx_ll_xqspi.h:86
ll_xqspi_get_cache_hitcount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr55xx_ll_xqspi.h:691
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_get_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr55xx_ll_xqspi.h:1113
ll_xqspi_get_cache_misscount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr55xx_ll_xqspi.h:711
ll_xqspi_set_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr55xx_ll_xqspi.h:1737
ll_xqspi_get_qspi_tx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_xqspi.h:2326
ll_xqspi_set_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr55xx_ll_xqspi.h:1182
ll_xqspi_get_qspi_rx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_xqspi.h:2345
ll_xqspi_enable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr55xx_ll_xqspi.h:443
ll_xqspi_qspi_transmit_data8
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr55xx_ll_xqspi.h:1405
ll_xqspi_get_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr55xx_ll_xqspi.h:1802
ll_xqspi_enable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr55xx_ll_xqspi.h:1619
ll_xqspi_set_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1138
ll_xqspi_disable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr55xx_ll_xqspi.h:463
ll_xqspi_set_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr55xx_ll_xqspi.h:2288
ll_xqspi_enable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr55xx_ll_xqspi.h:2034
ll_xqspi_set_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr55xx_ll_xqspi.h:764
ll_xqspi_get_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr55xx_ll_xqspi.h:1161
ll_xqspi_get_xip_endian
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr55xx_ll_xqspi.h:1072
ll_xqspi_disable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr55xx_ll_xqspi.h:401
ll_xqspi_get_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1551
ll_xqspi_get_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr55xx_ll_xqspi.h:2015
ll_xqspi_set_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr55xx_ll_xqspi.h:1576
_ll_xqspi_init_t::data_size
uint32_t data_size
Specifies the XQSPI data width, only in QSPI mode.
Definition: gr55xx_ll_xqspi.h:91