gr55xx_ll_spi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (SPIM) || defined (SPIS) || defined (QSPI0) || defined (QSPI1)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t
77 {
78 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
79 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
80
81 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
87
88 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
89 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
90
91 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
92
93 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
94 This parameter can be a value of @ref SPI_LL_EC_PHASE.
95
96 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
97
98 uint32_t slave_select; /**< Specifies the SPI slave select.
99 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
100
101 This feature can be modified afterwards using unitary function @ref ll_spi_enable_ss().*/
102
103 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
104 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
105 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
108 } ll_spim_init_t;
109
110 /**
111 * @brief SPIS init structures definition
112 */
113 typedef struct _ll_spis_init_t
114 {
115 uint32_t data_size; /**< Specifies the SPI data width.
116 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
117
118 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
119
120 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
121 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
122
123 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
124
125 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
126 This parameter can be a value of @ref SPI_LL_EC_PHASE.
127
128 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
129
130 } ll_spis_init_t;
131
132 /**
133 * @brief QSPI init structures definition
134 */
135 typedef struct _ll_qspi_init_t
136 {
137 uint32_t transfer_direction; /**< Specifies the QSPI transfer or receive mode.
138 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
139
140 This feature can be modified afterwards using unitary function @ref ll_spi_set_transfer_direction().*/
141
142 uint32_t instruction_size; /**< Specifies the QSPI instruction width.
143 This parameter can be a value of @ref SPI_LL_EC_INSTRUCTIONSIZE.
144
145 This feature can be modified afterwards using unitary function @ref ll_spi_set_instruction_size().*/
146
147 uint32_t address_size; /**< Specifies the QSPI address width.
148 This parameter can be a value of @ref SPI_LL_EC_ADDRESSSIZE.
149
150 This feature can be modified afterwards using unitary function @ref ll_spi_set_address_size().*/
151
152 uint32_t inst_addr_transfer_format; /**< Specifies the QSPI instruction and address transfer format.
153 This parameter can be a value of @ref SPI_LL_EC_ADDRINSTTRNASFERFORMAT.
154
155 This feature can be modified afterwards using unitary function @ref ll_spi_set_add_inst_transfer_format().*/
156
157 uint32_t wait_cycles; /**< Specifies the QSPI dummy clock.
158 This parameter can be one of the following values: 0 ~ 31.
159
160 This feature can be modified afterwards using unitary function @ref ll_spi_set_wait_cycles().*/
161
162 uint32_t data_size; /**< Specifies the SPI data width.
163 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
164
165 This feature can be modified afterwards using unitary function @ref ll_spi_set_data_size().*/
166
167 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
168 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
169
170 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_polarity().*/
171
172 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
173 This parameter can be a value of @ref SPI_LL_EC_PHASE.
174
175 This feature can be modified afterwards using unitary function @ref ll_spi_set_clock_phase().*/
176
177 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
178 This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
179 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
180
181 This feature can be modified afterwards using unitary function @ref ll_spi_set_baud_rate_prescaler().*/
182
183 uint32_t rx_sample_delay; /**< Specifies the RX sample delay. It is used to delay the sample of the RX input port.
184 This parameter can be a number between 0 and 0x7 */
185 } ll_qspi_init_t;
186
187 /** @} */
188
189 /** @} */
190
191 /**
192 * @defgroup SPI_LL_MACRO Defines
193 * @{
194 */
195
196 /* Exported constants --------------------------------------------------------*/
197 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
198 * @{
199 */
200
201 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
202 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
203 * @{
204 */
205 #define LL_SSI_SR_DCOL SSI_STAT_DCOL /**< Data collision error flag */
206 #define LL_SSI_SR_TXE SSI_STAT_TXE /**< Transmission error flag */
207 #define LL_SSI_SR_RFF SSI_STAT_RFF /**< Rx FIFO full flag */
208 #define LL_SSI_SR_RFNE SSI_STAT_RFNE /**< Rx FIFO not empty flag */
209 #define LL_SSI_SR_TFE SSI_STAT_TFE /**< Tx FIFO empty flag */
210 #define LL_SSI_SR_TFNF SSI_STAT_TFNF /**< Tx FIFO not full flag */
211 #define LL_SSI_SR_BUSY SSI_STAT_BUSY /**< Busy flag */
212 /** @} */
213
214 /** @defgroup SPI_LL_EC_IT IT Defines
215 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
216 * @{
217 */
218 #define LL_SSI_IM_MST SSI_INTMASK_MSTIM /**< Multi-Master Contention Interrupt enable */
219 #define LL_SSI_IM_RXF SSI_INTMASK_RXFIM /**< Receive FIFO Full Interrupt enable */
220 #define LL_SSI_IM_RXO SSI_INTMASK_RXOIM /**< Receive FIFO Overflow Interrupt enable */
221 #define LL_SSI_IM_RXU SSI_INTMASK_RXUIM /**< Receive FIFO Underflow Interrupt enable */
222 #define LL_SSI_IM_TXO SSI_INTMASK_TXOIM /**< Transmit FIFO Overflow Interrupt enable */
223 #define LL_SSI_IM_TXE SSI_INTMASK_TXEIM /**< Transmit FIFO Empty Interrupt enable */
224
225 #define LL_SSI_IS_MST SSI_INTSTAT_MSTIS /**< Multi-Master Contention Interrupt flag */
226 #define LL_SSI_IS_RXF SSI_INTSTAT_RXFIS /**< Receive FIFO Full Interrupt flag */
227 #define LL_SSI_IS_RXO SSI_INTSTAT_RXOIS /**< Receive FIFO Overflow Interrupt flag */
228 #define LL_SSI_IS_RXU SSI_INTSTAT_RXUIS /**< Receive FIFO Underflow Interrupt flag */
229 #define LL_SSI_IS_TXO SSI_INTSTAT_TXOIS /**< Transmit FIFO Overflow Interrupt flag */
230 #define LL_SSI_IS_TXE SSI_INTSTAT_TXEIS /**< Transmit FIFO Empty Interrupt flag */
231
232 #define LL_SSI_RIS_MST SSI_RAW_INTSTAT_MSTIR /**< Multi-Master Contention RAW Interrupt flag */
233 #define LL_SSI_RIS_RXF SSI_RAW_INTSTAT_RXFIR /**< Receive FIFO Full RAW Interrupt flag */
234 #define LL_SSI_RIS_RXO SSI_RAW_INTSTAT_RXOIR /**< Receive FIFO Overflow RAW Interrupt flag */
235 #define LL_SSI_RIS_RXU SSI_RAW_INTSTAT_RXUIR /**< Receive FIFO Underflow RAW Interrupt flag */
236 #define LL_SSI_RIS_TXO SSI_RAW_INTSTAT_TXOIR /**< Transmit FIFO Overflow RAW Interrupt flag */
237 #define LL_SSI_RIS_TXE SSI_RAW_INTSTAT_TXEIR /**< Transmit FIFO Empty RAW Interrupt flag */
238 /** @} */
239
240 /** @defgroup SPI_LL_EC_SPIFRAMEFORMAT SPI Frame Format
241 * @{
242 */
243 #define LL_SSI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
244 #define LL_SSI_FRF_DUALSPI (1UL << SSI_CTRL0_SPIFRF_Pos) /**< Dual-SPI frame format for transfer */
245 #define LL_SSI_FRF_QUADSPI (2UL << SSI_CTRL0_SPIFRF_Pos) /**< Quad-SPI frame format for transfer */
246 /** @} */
247
248 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
249 * @{
250 */
251 #define LL_SSI_DATASIZE_4BIT (3UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 4 bits */
252 #define LL_SSI_DATASIZE_5BIT (4UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 5 bits */
253 #define LL_SSI_DATASIZE_6BIT (5UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 6 bits */
254 #define LL_SSI_DATASIZE_7BIT (6UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 7 bits */
255 #define LL_SSI_DATASIZE_8BIT (7UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 8 bits */
256 #define LL_SSI_DATASIZE_9BIT (8UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 9 bits */
257 #define LL_SSI_DATASIZE_10BIT (9UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 10 bits */
258 #define LL_SSI_DATASIZE_11BIT (10UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 11 bits */
259 #define LL_SSI_DATASIZE_12BIT (11UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 12 bits */
260 #define LL_SSI_DATASIZE_13BIT (12UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 13 bits */
261 #define LL_SSI_DATASIZE_14BIT (13UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 14 bits */
262 #define LL_SSI_DATASIZE_15BIT (14UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 15 bits */
263 #define LL_SSI_DATASIZE_16BIT (15UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 16 bits */
264 #define LL_SSI_DATASIZE_17BIT (16UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 17 bits */
265 #define LL_SSI_DATASIZE_18BIT (17UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 18 bits */
266 #define LL_SSI_DATASIZE_19BIT (18UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 19 bits */
267 #define LL_SSI_DATASIZE_20BIT (19UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 20 bits */
268 #define LL_SSI_DATASIZE_21BIT (20UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 21 bits */
269 #define LL_SSI_DATASIZE_22BIT (21UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 22 bits */
270 #define LL_SSI_DATASIZE_23BIT (22UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 23 bits */
271 #define LL_SSI_DATASIZE_24BIT (23UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 24 bits */
272 #define LL_SSI_DATASIZE_25BIT (24UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 25 bits */
273 #define LL_SSI_DATASIZE_26BIT (25UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 26 bits */
274 #define LL_SSI_DATASIZE_27BIT (26UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 27 bits */
275 #define LL_SSI_DATASIZE_28BIT (27UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 28 bits */
276 #define LL_SSI_DATASIZE_29BIT (28UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 29 bits */
277 #define LL_SSI_DATASIZE_30BIT (29UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 30 bits */
278 #define LL_SSI_DATASIZE_31BIT (30UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 31 bits */
279 #define LL_SSI_DATASIZE_32BIT (31UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 32 bits */
280 /** @} */
281
282 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
283 * @{
284 */
285 #define LL_SSI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire transfer: 1 bits */
286 #define LL_SSI_MW_CMDSIZE_2BIT (1UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 2 bits */
287 #define LL_SSI_MW_CMDSIZE_3BIT (2UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 3 bits */
288 #define LL_SSI_MW_CMDSIZE_4BIT (3UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 4 bits */
289 #define LL_SSI_MW_CMDSIZE_5BIT (4UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 5 bits */
290 #define LL_SSI_MW_CMDSIZE_6BIT (5UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 6 bits */
291 #define LL_SSI_MW_CMDSIZE_7BIT (6UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 7 bits */
292 #define LL_SSI_MW_CMDSIZE_8BIT (7UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 8 bits */
293 #define LL_SSI_MW_CMDSIZE_9BIT (8UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 9 bits */
294 #define LL_SSI_MW_CMDSIZE_10BIT (9UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 10 bits */
295 #define LL_SSI_MW_CMDSIZE_11BIT (10UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 11 bits */
296 #define LL_SSI_MW_CMDSIZE_12BIT (11UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 12 bits */
297 #define LL_SSI_MW_CMDSIZE_13BIT (12UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 13 bits */
298 #define LL_SSI_MW_CMDSIZE_14BIT (13UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 14 bits */
299 #define LL_SSI_MW_CMDSIZE_15BIT (14UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 15 bits */
300 #define LL_SSI_MW_CMDSIZE_16BIT (15UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire transfer: 16 bits */
301 /** @} */
302
303 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
304 * @{
305 */
306 #define LL_SSI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
307 #define LL_SSI_TEST_MODE (1UL << SSI_CTRL0_SRL_Pos) /**< Test mode for SPI transfer: Rx and Tx connected inside */
308 /** @} */
309
310 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
311 * @{
312 */
313 #define LL_SSI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer as slave */
314 #define LL_SSI_SLAVE_OUTEN (1UL << SSI_CTRL0_SLVOE_Pos) /**< Output disable for SPI transfer as slave */
315 /** @} */
316
317 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
318 * @{
319 */
320 #define LL_SSI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode. Rx and Tx transfer on 2 lines */
321 #define LL_SSI_SIMPLEX_TX (1UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Tx mode. Tx transfer only on 1 line */
322 #define LL_SSI_SIMPLEX_RX (2UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Rx mode. Rx transfer only on 1 line */
323 #define LL_SSI_READ_EEPROM (3UL << SSI_CTRL0_TMOD_Pos) /**< Read EEPROM mode. Rx transfer only on 1 line */
324 /** @} */
325
326 /** @defgroup SPI_LL_EC_PHASE Clock Phase
327 * @{
328 */
329 #define LL_SSI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is the first data capture edge */
330 #define LL_SSI_SCPHA_2EDGE (1UL << SSI_CTRL0_SCPHA_Pos) /**< Second clock transition is the first data capture edge */
331 /** @} */
332
333 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
334 * @{
335 */
336 #define LL_SSI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
337 #define LL_SSI_SCPOL_HIGH (1UL << SSI_CTRL0_SCPOL_Pos) /**< Clock to 1 when idle */
338 /** @} */
339
340 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
341 * @{
342 */
343 #define LL_SSI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
344 #define LL_SSI_PROTOCOL_TI (1UL << SSI_CTRL0_FRF_Pos) /**< TI mode */
345 #define LL_SSI_PROTOCOL_MICROWIRE (2UL << SSI_CTRL0_FRF_Pos) /**< Microwire mode */
346 /** @} */
347
348 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
349 * @{
350 */
351 #define LL_SSI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire transfer */
352 #define LL_SSI_MICROWIRE_HANDSHAKE_EN (1UL << SSI_MWC_MHS_Pos) /**< Disable Handshake for Microwire transfer */
353
354 #define LL_SSI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
355 #define LL_SSI_MICROWIRE_TX (1UL << SSI_MWC_MDD_Pos) /**< Tx mode. Tx transfer at Microwire mode */
356
357 #define LL_SSI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
358 #define LL_SSI_MICROWIRE_SEQUENTIAL (1UL << SSI_MWC_MWMOD_Pos) /**< Sequential for Microwire transfer */
359 /** @} */
360
361 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
362 * @{
363 */
364 #define LL_SSI_SLAVE1 SSI_SE_SLAVE1 /**< Enable slave1 select pin for SPI transfer */
365 #define LL_SSI_SLAVE0 SSI_SE_SLAVE0 /**< Enable slave0 select pin for SPI transfer */
366 /** @} */
367
368 /** @defgroup SPI_LL_EC_DMA DMA Defines
369 * @{
370 */
371 #define LL_SSI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
372 #define LL_SSI_DMA_TX_EN SSI_DMAC_TDMAE /**< Enable the transmit FIFO DMA channel */
373
374 #define LL_SSI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
375 #define LL_SSI_DMA_RX_EN SSI_DMAC_RDMAE /**< Enable the receive FIFO DMA channel */
376 /** @} */
377
378 /** @defgroup SPI_LL_EC_INSTRUCTIONSIZE QSPI Instruction Size
379 * @{
380 */
381 #define LL_SSI_INSTSIZE_0BIT 0x00000000UL /**< Instruction length for QSPI transfer: 0 bits */
382 #define LL_SSI_INSTSIZE_4BIT (1UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 4 bits */
383 #define LL_SSI_INSTSIZE_8BIT (2UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 8 bits */
384 #define LL_SSI_INSTSIZE_16BIT (3UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI transfer: 16 bits */
385 /** @} */
386
387 /** @defgroup SPI_LL_EC_ADDRESSSIZE QSPI Address Size
388 * @{
389 */
390 #define LL_SSI_ADDRSIZE_0BIT 0x00000000UL /**< Address length for QSPI transfer: 0 bits */
391 #define LL_SSI_ADDRSIZE_4BIT (1UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 4 bits */
392 #define LL_SSI_ADDRSIZE_8BIT (2UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 8 bits */
393 #define LL_SSI_ADDRSIZE_12BIT (3UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 12 bits */
394 #define LL_SSI_ADDRSIZE_16BIT (4UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 16 bits */
395 #define LL_SSI_ADDRSIZE_20BIT (5UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 20 bits */
396 #define LL_SSI_ADDRSIZE_24BIT (6UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 24 bits */
397 #define LL_SSI_ADDRSIZE_28BIT (7UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 28 bits */
398 #define LL_SSI_ADDRSIZE_32BIT (8UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 32 bits */
399 #define LL_SSI_ADDRSIZE_36BIT (9UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 36 bits */
400 #define LL_SSI_ADDRSIZE_40BIT (10UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 40 bits */
401 #define LL_SSI_ADDRSIZE_44BIT (11UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 44 bits */
402 #define LL_SSI_ADDRSIZE_48BIT (12UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 48 bits */
403 #define LL_SSI_ADDRSIZE_52BIT (13UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 52 bits */
404 #define LL_SSI_ADDRSIZE_56BIT (14UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 56 bits */
405 #define LL_SSI_ADDRSIZE_60BIT (15UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI transfer: 60 bits */
406 /** @} */
407
408 /** @defgroup SPI_LL_EC_ADDRINSTTRNASFERFORMAT QSPI Address and Instruction Transfer Format
409 * @{
410 */
411 #define LL_SSI_INST_ADDR_ALL_IN_SPI 0x00000000UL /**< Instruction and address are sent in SPI mode */
412 #define LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction is in sent in SPI mode and address is sent in Daul/Quad SPI mode */
413 #define LL_SSI_INST_ADDR_ALL_IN_SPIFRF (2UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction and address are sent in Daul/Quad SPI mode */
414 /** @} */
415
416 /** @defgroup SPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
417 * @{
418 */
419
420 /**
421 * @brief LL SPIM InitStrcut default configuartion
422 */
423 #define LL_SPIM_DEFAULT_CONFIG \
424 { \
425 .transfer_direction = LL_SSI_FULL_DUPLEX, \
426 .data_size = LL_SSI_DATASIZE_8BIT, \
427 .clock_polarity = LL_SSI_SCPOL_LOW, \
428 .clock_phase = LL_SSI_SCPHA_1EDGE, \
429 .slave_select = LL_SSI_SLAVE0, \
430 .baud_rate = SystemCoreClock / 2000000, \
431 }
432
433 /**
434 * @brief LL SPIS InitStrcut default configuartion
435 */
436 #define LL_SPIS_DEFAULT_CONFIG \
437 { \
438 .data_size = LL_SSI_DATASIZE_8BIT, \
439 .clock_polarity = LL_SSI_SCPOL_LOW, \
440 .clock_phase = LL_SSI_SCPHA_1EDGE, \
441 }
442
443 /**
444 * @brief LL QSPI InitStrcut default configuartion
445 */
446 #define LL_QSPI_DEFAULT_CONFIG \
447 { \
448 .transfer_direction = LL_SSI_SIMPLEX_TX, \
449 .instruction_size = LL_SSI_INSTSIZE_8BIT, \
450 .address_size = LL_SSI_ADDRSIZE_24BIT, \
451 .inst_addr_transfer_format = LL_SSI_INST_ADDR_ALL_IN_SPI,\
452 .wait_cycles = 0, \
453 .data_size = LL_SSI_DATASIZE_8BIT, \
454 .clock_polarity = LL_SSI_SCPOL_LOW, \
455 .clock_phase = LL_SSI_SCPHA_1EDGE, \
456 .baud_rate = SystemCoreClock / 1000000, \
457 .rx_sample_delay = 0, \
458 }
459 /** @} */
460
461 /** @} */
462
463 /* Exported macro ------------------------------------------------------------*/
464 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
465 * @{
466 */
467
468 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
469 * @{
470 */
471
472 /**
473 * @brief Write a value in SPI register
474 * @param __instance__ SPI instance
475 * @param __REG__ Register to be written
476 * @param __VALUE__ Value to be written in the register
477 * @retval None
478 */
479 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
480
481 /**
482 * @brief Read a value in SPI register
483 * @param __instance__ SPI instance
484 * @param __REG__ Register to be read
485 * @retval Register value
486 */
487 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
488
489 /** @} */
490
491 /** @} */
492
493 /** @} */
494
495 /* Exported functions --------------------------------------------------------*/
496 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
497 * @{
498 */
499
500 /** @defgroup SPI_LL_EF_Configuration Configuration functions
501 * @{
502 */
503
504 /**
505 * @brief Enable slave select toggle
506 * @note This bit should not be changed when communication is ongoing.
507 *
508 * \rst
509 * +----------------------+-----------------------------------+
510 * | Register | BitsName |
511 * +======================+===================================+
512 * | CTRL0 | SSTEN |
513 * +----------------------+-----------------------------------+
514 * \endrst
515 *
516 * @param SPIx SPI instance
517 * @retval None
518 */
519 __STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
520 {
521 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
522 }
523
524 /**
525 * @brief Disable slave select toggle
526 * @note This bit should not be changed when communication is ongoing.
527 *
528 * \rst
529 * +----------------------+-----------------------------------+
530 * | Register | BitsName |
531 * +======================+===================================+
532 * | CTRL0 | SSTEN |
533 * +----------------------+-----------------------------------+
534 * \endrst
535 *
536 * @param SPIx SPI instance
537 * @retval None
538 */
539 __STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
540 {
541 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
542 }
543
544 /**
545 * @brief Check if slave select toggle is enabled
546 * @note This bit should not be changed when communication is ongoing.
547 *
548 * \rst
549 * +----------------------+-----------------------------------+
550 * | Register | BitsName |
551 * +======================+===================================+
552 * | CTRL0 | SSTEN |
553 * +----------------------+-----------------------------------+
554 * \endrst
555 *
556 * @param SPIx SPI instance
557 * @retval State of bit (1 or 0).
558 */
559 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
560 {
561 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN) == (SSI_CTRL0_SSTEN));
562 }
563
564 /**
565 * @brief Set data frame format for transmitting/receiving the data
566 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
567 *
568 * \rst
569 * +----------------------+-----------------------------------+
570 * | Register | BitsName |
571 * +======================+===================================+
572 * | CTRL0 | SPIFRF |
573 * +----------------------+-----------------------------------+
574 * \endrst
575 *
576 * @param SPIx SPI instance
577 * @param frf This parameter can be one of the following values:
578 * @arg @ref LL_SSI_FRF_SPI
579 * @arg @ref LL_SSI_FRF_DUALSPI
580 * @arg @ref LL_SSI_FRF_QUADSPI
581 * @retval None
582 */
583 __STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
584 {
585 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SPIFRF, frf);
586 }
587
588 /**
589 * @brief Get data frame format for transmitting/receiving the data
590 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
591 *
592 * \rst
593 * +----------------------+-----------------------------------+
594 * | Register | BitsName |
595 * +======================+===================================+
596 * | CTRL0 | SPIFRF |
597 * +----------------------+-----------------------------------+
598 * \endrst
599 *
600 * @param SPIx SPI instance
601 * @retval Returned value can be one of the following values:
602 * @arg @ref LL_SSI_FRF_SPI
603 * @arg @ref LL_SSI_FRF_DUALSPI
604 * @arg @ref LL_SSI_FRF_QUADSPI
605 */
606 __STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
607 {
608 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SPIFRF));
609 }
610
611 /**
612 * @brief Set frame data size
613 *
614 * \rst
615 * +----------------------+-----------------------------------+
616 * | Register | BitsName |
617 * +======================+===================================+
618 * | CTRL0 | DFS32 |
619 * +----------------------+-----------------------------------+
620 * \endrst
621 *
622 * @param SPIx SPI instance
623 * @param size This parameter can be one of the following values:
624 * @arg @ref LL_SSI_DATASIZE_4BIT
625 * @arg @ref LL_SSI_DATASIZE_5BIT
626 * @arg @ref LL_SSI_DATASIZE_6BIT
627 * @arg @ref LL_SSI_DATASIZE_7BIT
628 * @arg @ref LL_SSI_DATASIZE_8BIT
629 * @arg @ref LL_SSI_DATASIZE_9BIT
630 * @arg @ref LL_SSI_DATASIZE_10BIT
631 * @arg @ref LL_SSI_DATASIZE_11BIT
632 * @arg @ref LL_SSI_DATASIZE_12BIT
633 * @arg @ref LL_SSI_DATASIZE_13BIT
634 * @arg @ref LL_SSI_DATASIZE_14BIT
635 * @arg @ref LL_SSI_DATASIZE_15BIT
636 * @arg @ref LL_SSI_DATASIZE_16BIT
637 * @arg @ref LL_SSI_DATASIZE_17BIT
638 * @arg @ref LL_SSI_DATASIZE_18BIT
639 * @arg @ref LL_SSI_DATASIZE_19BIT
640 * @arg @ref LL_SSI_DATASIZE_20BIT
641 * @arg @ref LL_SSI_DATASIZE_21BIT
642 * @arg @ref LL_SSI_DATASIZE_22BIT
643 * @arg @ref LL_SSI_DATASIZE_23BIT
644 * @arg @ref LL_SSI_DATASIZE_24BIT
645 * @arg @ref LL_SSI_DATASIZE_25BIT
646 * @arg @ref LL_SSI_DATASIZE_26BIT
647 * @arg @ref LL_SSI_DATASIZE_27BIT
648 * @arg @ref LL_SSI_DATASIZE_28BIT
649 * @arg @ref LL_SSI_DATASIZE_29BIT
650 * @arg @ref LL_SSI_DATASIZE_30BIT
651 * @arg @ref LL_SSI_DATASIZE_31BIT
652 * @arg @ref LL_SSI_DATASIZE_32BIT
653 * @retval None
654 */
655 __STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
656 {
657 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_DFS32, size);
658 }
659
660 /**
661 * @brief Get frame data size
662 *
663 * \rst
664 * +----------------------+-----------------------------------+
665 * | Register | BitsName |
666 * +======================+===================================+
667 * | CTRL0 | DFS32 |
668 * +----------------------+-----------------------------------+
669 * \endrst
670 *
671 * @param SPIx SPI instance
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_SSI_DATASIZE_4BIT
674 * @arg @ref LL_SSI_DATASIZE_5BIT
675 * @arg @ref LL_SSI_DATASIZE_6BIT
676 * @arg @ref LL_SSI_DATASIZE_7BIT
677 * @arg @ref LL_SSI_DATASIZE_8BIT
678 * @arg @ref LL_SSI_DATASIZE_9BIT
679 * @arg @ref LL_SSI_DATASIZE_10BIT
680 * @arg @ref LL_SSI_DATASIZE_11BIT
681 * @arg @ref LL_SSI_DATASIZE_12BIT
682 * @arg @ref LL_SSI_DATASIZE_13BIT
683 * @arg @ref LL_SSI_DATASIZE_14BIT
684 * @arg @ref LL_SSI_DATASIZE_15BIT
685 * @arg @ref LL_SSI_DATASIZE_16BIT
686 * @arg @ref LL_SSI_DATASIZE_17BIT
687 * @arg @ref LL_SSI_DATASIZE_18BIT
688 * @arg @ref LL_SSI_DATASIZE_19BIT
689 * @arg @ref LL_SSI_DATASIZE_20BIT
690 * @arg @ref LL_SSI_DATASIZE_21BIT
691 * @arg @ref LL_SSI_DATASIZE_22BIT
692 * @arg @ref LL_SSI_DATASIZE_23BIT
693 * @arg @ref LL_SSI_DATASIZE_24BIT
694 * @arg @ref LL_SSI_DATASIZE_25BIT
695 * @arg @ref LL_SSI_DATASIZE_26BIT
696 * @arg @ref LL_SSI_DATASIZE_27BIT
697 * @arg @ref LL_SSI_DATASIZE_28BIT
698 * @arg @ref LL_SSI_DATASIZE_29BIT
699 * @arg @ref LL_SSI_DATASIZE_30BIT
700 * @arg @ref LL_SSI_DATASIZE_31BIT
701 * @arg @ref LL_SSI_DATASIZE_32BIT
702 */
703 __STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
704 {
705 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_DFS32));
706 }
707
708 /**
709 * @brief Set the length of the control word for the Microwire frame format
710 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
711 *
712 * \rst
713 * +----------------------+-----------------------------------+
714 * | Register | BitsName |
715 * +======================+===================================+
716 * | CTRL0 | CFS |
717 * +----------------------+-----------------------------------+
718 * \endrst
719 *
720 * @param SPIx SPI instance
721 * @param size This parameter can be one of the following values:
722 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
723 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
724 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
725 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
726 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
727 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
728 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
729 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
730 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
731 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
732 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
733 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
734 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
735 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
736 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
737 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
738 * @retval None
739 */
740 __STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
741 {
742 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_CFS, size);
743 }
744
745 /**
746 * @brief Get the length of the control word for the Microwire frame format
747 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
748 *
749 * \rst
750 * +----------------------+-----------------------------------+
751 * | Register | BitsName |
752 * +======================+===================================+
753 * | CTRL0 | CFS |
754 * +----------------------+-----------------------------------+
755 * \endrst
756 *
757 * @param SPIx SPI instance
758 * @retval Returned value can be one of the following values:
759 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
760 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
761 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
762 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
763 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
764 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
765 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
766 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
767 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
768 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
769 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
770 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
771 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
772 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
773 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
774 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
775 */
776 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
777 {
778 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_CFS));
779 }
780
781 /**
782 * @brief Enable SPI test mode
783 *
784 * \rst
785 * +----------------------+-----------------------------------+
786 * | Register | BitsName |
787 * +======================+===================================+
788 * | CTRL0 | SRL |
789 * +----------------------+-----------------------------------+
790 * \endrst
791 *
792 * @param SPIx SPI instance
793 * @retval None
794 */
795 __STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
796 {
797 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
798 }
799
800 /**
801 * @brief Disable SPI test mode
802 *
803 * \rst
804 * +----------------------+-----------------------------------+
805 * | Register | BitsName |
806 * +======================+===================================+
807 * | CTRL0 | SRL |
808 * +----------------------+-----------------------------------+
809 * \endrst
810 *
811 * @param SPIx SPI instance
812 * @retval None
813 */
814 __STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
815 {
816 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
817 }
818
819 /**
820 * @brief Check if SPI test mode is enabled
821 *
822 * \rst
823 * +----------------------+-----------------------------------+
824 * | Register | BitsName |
825 * +======================+===================================+
826 * | CTRL0 | SRL |
827 * +----------------------+-----------------------------------+
828 * \endrst
829 *
830 * @param SPIx SPI instance
831 * @retval State of bit (1 or 0).
832 */
833 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
834 {
835 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SRL) == (SSI_CTRL0_SRL));
836 }
837
838 /**
839 * @brief Enable slave output
840 *
841 * \rst
842 * +----------------------+-----------------------------------+
843 * | Register | BitsName |
844 * +======================+===================================+
845 * | CTRL0 | SLVOE |
846 * +----------------------+-----------------------------------+
847 * \endrst
848 *
849 * @param SPIx SPI instance
850 * @retval None
851 */
852 __STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
853 {
854 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
855 }
856
857 /**
858 * @brief Disable slave output
859 *
860 * \rst
861 * +----------------------+-----------------------------------+
862 * | Register | BitsName |
863 * +======================+===================================+
864 * | CTRL0 | SLVOE |
865 * +----------------------+-----------------------------------+
866 * \endrst
867 *
868 * @param SPIx SPI instance
869 * @retval None
870 */
871 __STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
872 {
873 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
874 }
875
876 /**
877 * @brief Check if slave output is enabled
878 *
879 * \rst
880 * +----------------------+-----------------------------------+
881 * | Register | BitsName |
882 * +======================+===================================+
883 * | CTRL0 | SLVOE |
884 * +----------------------+-----------------------------------+
885 * \endrst
886 *
887 * @param SPIx SPI instance
888 * @retval State of bit (1 or 0).
889 */
890 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
891 {
892 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE) != (SSI_CTRL0_SLVOE));
893 }
894
895 /**
896 * @brief Set transfer direction mode
897 *
898 * \rst
899 * +----------------------+-----------------------------------+
900 * | Register | BitsName |
901 * +======================+===================================+
902 * | CTRL0 | TMOD |
903 * +----------------------+-----------------------------------+
904 * \endrst
905 *
906 * @param SPIx SPI instance
907 * @param transfer_direction This parameter can be one of the following values:
908 * @arg @ref LL_SSI_FULL_DUPLEX
909 * @arg @ref LL_SSI_SIMPLEX_TX
910 * @arg @ref LL_SSI_SIMPLEX_RX
911 * @arg @ref LL_SSI_READ_EEPROM
912 * @retval None
913 */
914 __STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
915 {
916 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_TMOD, transfer_direction);
917 }
918
919 /**
920 * @brief Get transfer direction mode
921 *
922 * \rst
923 * +----------------------+-----------------------------------+
924 * | Register | BitsName |
925 * +======================+===================================+
926 * | CTRL0 | TMOD |
927 * +----------------------+-----------------------------------+
928 * \endrst
929 *
930 * @param SPIx SPI instance
931 * @retval Returned value can be one of the following values:
932 * @arg @ref LL_SSI_FULL_DUPLEX
933 * @arg @ref LL_SSI_SIMPLEX_TX
934 * @arg @ref LL_SSI_SIMPLEX_RX
935 * @arg @ref LL_SSI_READ_EEPROM
936 */
937 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
938 {
939 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_TMOD));
940 }
941
942 /**
943 * @brief Set clock polarity
944 * @note This bit should not be changed when communication is ongoing.
945 * This bit is not used in SPI TI mode.
946 *
947 * \rst
948 * +----------------------+-----------------------------------+
949 * | Register | BitsName |
950 * +======================+===================================+
951 * | CTRL0 | SCPOL |
952 * +----------------------+-----------------------------------+
953 * \endrst
954 *
955 * @param SPIx SPI instance
956 * @param clock_polarity This parameter can be one of the following values:
957 * @arg @ref LL_SSI_SCPOL_LOW
958 * @arg @ref LL_SSI_SCPOL_HIGH
959 * @retval None
960 */
961 __STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
962 {
963 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPOL, clock_polarity);
964 }
965
966 /**
967 * @brief Get clock polarity
968 *
969 * \rst
970 * +----------------------+-----------------------------------+
971 * | Register | BitsName |
972 * +======================+===================================+
973 * | CTRL0 | SCPOL |
974 * +----------------------+-----------------------------------+
975 * \endrst
976 *
977 * @param SPIx SPI instance
978 * @retval Returned value can be one of the following values:
979 * @arg @ref LL_SSI_SCPOL_LOW
980 * @arg @ref LL_SSI_SCPOL_HIGH
981 */
982 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
983 {
984 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPOL));
985 }
986
987 /**
988 * @brief Set clock phase
989 * @note This bit should not be changed when communication is ongoing.
990 * This bit is not used in SPI TI mode.
991 *
992 * \rst
993 * +----------------------+-----------------------------------+
994 * | Register | BitsName |
995 * +======================+===================================+
996 * | CTRL0 | SCPHA |
997 * +----------------------+-----------------------------------+
998 * \endrst
999 *
1000 * @param SPIx SPI instance
1001 * @param clock_phase This parameter can be one of the following values:
1002 * @arg @ref LL_SSI_SCPHA_1EDGE
1003 * @arg @ref LL_SSI_SCPHA_2EDGE
1004 * @retval None
1005 */
1006 __STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
1007 {
1008 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPHA, clock_phase);
1009 }
1010
1011 /**
1012 * @brief Get clock phase
1013 *
1014 * \rst
1015 * +----------------------+-----------------------------------+
1016 * | Register | BitsName |
1017 * +======================+===================================+
1018 * | CTRL0 | SCPHA |
1019 * +----------------------+-----------------------------------+
1020 * \endrst
1021 *
1022 * @param SPIx SPI instance
1023 * @retval Returned value can be one of the following values:
1024 * @arg @ref LL_SSI_SCPHA_1EDGE
1025 * @arg @ref LL_SSI_SCPHA_2EDGE
1026 */
1027 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
1028 {
1029 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPHA));
1030 }
1031
1032 /**
1033 * @brief Set serial protocol used
1034 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
1035 *
1036 * \rst
1037 * +----------------------+-----------------------------------+
1038 * | Register | BitsName |
1039 * +======================+===================================+
1040 * | CTRL0 | FRF |
1041 * +----------------------+-----------------------------------+
1042 * \endrst
1043 *
1044 * @param SPIx SPI instance
1045 * @param standard This parameter can be one of the following values:
1046 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
1047 * @arg @ref LL_SSI_PROTOCOL_TI
1048 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
1049 * @retval None
1050 */
1051 __STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
1052 {
1053 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_FRF, standard);
1054 }
1055
1056 /**
1057 * @brief Get serial protocol used
1058 *
1059 * \rst
1060 * +----------------------+-----------------------------------+
1061 * | Register | BitsName |
1062 * +======================+===================================+
1063 * | CTRL0 | FRF |
1064 * +----------------------+-----------------------------------+
1065 * \endrst
1066 *
1067 * @param SPIx SPI instance
1068 * @retval Returned value can be one of the following values:
1069 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
1070 * @arg @ref LL_SSI_PROTOCOL_TI
1071 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
1072 */
1073 __STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
1074 {
1075 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_FRF));
1076 }
1077
1078 /**
1079 * @brief Set the number of data frames to be continuously received
1080 * @note These bits should not be changed when communication is ongoing.
1081 This bits are effect when TMOD = 2b10 or 2b11.
1082 This bits are not effect in SPIS.
1083 *
1084 * \rst
1085 * +----------------------+-----------------------------------+
1086 * | Register | BitsName |
1087 * +======================+===================================+
1088 * | CTRL1 | NDF |
1089 * +----------------------+-----------------------------------+
1090 * \endrst
1091 *
1092 * @param SPIx SPI instance
1093 * @param size This parameter can be one of the following values: 0 ~ 65535
1094 * @retval None
1095 */
1096 __STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
1097 {
1098 MODIFY_REG(SPIx->CTRL1, SSI_CTRL1_NDF, size);
1099 }
1100
1101 /**
1102 * @brief Get the number of data frames to be continuously received
1103 * @note These bits should not be changed when communication is ongoing.
1104 This bits are effect when TMOD = 2b10 or 2b11.
1105 This bits are not effect in SPIS.
1106 *
1107 * \rst
1108 * +----------------------+-----------------------------------+
1109 * | Register | BitsName |
1110 * +======================+===================================+
1111 * | CTRL1 | NDF |
1112 * +----------------------+-----------------------------------+
1113 * \endrst
1114 *
1115 * @param SPIx SPI instance
1116 * @retval Returned value can be one of the following values: 0 ~ 65535
1117 */
1118 __STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
1119 {
1120 return (uint32_t)(READ_BITS(SPIx->CTRL1, SSI_CTRL1_NDF));
1121 }
1122
1123 /**
1124 * @brief Enable SPI peripheral
1125 *
1126 * \rst
1127 * +----------------------+-----------------------------------+
1128 * | Register | BitsName |
1129 * +======================+===================================+
1130 * | SSI_EN | EN |
1131 * +----------------------+-----------------------------------+
1132 * \endrst
1133 *
1134 * @param SPIx SPI instance
1135 * @retval None
1136 */
1137 __STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
1138 {
1139 SET_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1140 }
1141
1142 /**
1143 * @brief Disable SPI peripheral
1144 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
1145 *
1146 * \rst
1147 * +----------------------+-----------------------------------+
1148 * | Register | BitsName |
1149 * +======================+===================================+
1150 * | SSI_EN | EN |
1151 * +----------------------+-----------------------------------+
1152 * \endrst
1153 *
1154 * @param SPIx SPI instance
1155 * @retval None
1156 */
1157 __STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
1158 {
1159 CLEAR_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1160 }
1161
1162 /**
1163 * @brief Check if SPI peripheral is enabled
1164 *
1165 * \rst
1166 * +----------------------+-----------------------------------+
1167 * | Register | BitsName |
1168 * +======================+===================================+
1169 * | SSI_EN | EN |
1170 * +----------------------+-----------------------------------+
1171 * \endrst
1172 *
1173 * @param SPIx SPI instance
1174 * @retval State of bit (1 or 0).
1175 */
1176 __STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
1177 {
1178 return (READ_BITS(SPIx->SSI_EN, SSI_SSIEN_EN) == (SSI_SSIEN_EN));
1179 }
1180
1181 /**
1182 * @brief Enable Handshake in Microwire mode
1183 *
1184 * \rst
1185 * +----------------------+-----------------------------------+
1186 * | Register | BitsName |
1187 * +======================+===================================+
1188 * | MWC | MHS |
1189 * +----------------------+-----------------------------------+
1190 * \endrst
1191 *
1192 * @param SPIx SPI instance
1193 * @retval None
1194 */
1195 __STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
1196 {
1197 SET_BITS(SPIx->MWC, SSI_MWC_MHS);
1198 }
1199
1200 /**
1201 * @brief Disable Handshake in Microwire mode
1202 *
1203 * \rst
1204 * +----------------------+-----------------------------------+
1205 * | Register | BitsName |
1206 * +======================+===================================+
1207 * | MWC | MHS |
1208 * +----------------------+-----------------------------------+
1209 * \endrst
1210 *
1211 * @param SPIx SPI instance
1212 * @retval None
1213 */
1214 __STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
1215 {
1216 CLEAR_BITS(SPIx->MWC, SSI_MWC_MHS);
1217 }
1218
1219 /**
1220 * @brief Check if Handshake in Microwire mode is enabled
1221 *
1222 * \rst
1223 * +----------------------+-----------------------------------+
1224 * | Register | BitsName |
1225 * +======================+===================================+
1226 * | MWC | MHS |
1227 * +----------------------+-----------------------------------+
1228 * \endrst
1229 *
1230 * @param SPIx SPI instance
1231 * @retval State of bit (1 or 0).
1232 */
1233 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
1234 {
1235 return (READ_BITS(SPIx->MWC, SSI_MWC_MHS) == (SSI_MWC_MHS));
1236 }
1237
1238 /**
1239 * @brief Set transfer direction mode in Microwire mode
1240 * @note This bit should not be changed when communication is ongoing.
1241 *
1242 * \rst
1243 * +----------------------+-----------------------------------+
1244 * | Register | BitsName |
1245 * +======================+===================================+
1246 * | MWC | MDD |
1247 * +----------------------+-----------------------------------+
1248 * \endrst
1249 *
1250 * @param SPIx SPI instance
1251 * @param transfer_direction This parameter can be one of the following values:
1252 * @arg @ref LL_SSI_MICROWIRE_RX
1253 * @arg @ref LL_SSI_MICROWIRE_TX
1254 * @retval None
1255 */
1256 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
1257 {
1258 MODIFY_REG(SPIx->MWC, SSI_MWC_MDD, transfer_direction);
1259 }
1260
1261 /**
1262 * @brief Get transfer direction mode in Microwire mode
1263 * @note This bit should not be changed when communication is ongoing.
1264 *
1265 * \rst
1266 * +----------------------+-----------------------------------+
1267 * | Register | BitsName |
1268 * +======================+===================================+
1269 * | MWC | MDD |
1270 * +----------------------+-----------------------------------+
1271 * \endrst
1272 *
1273 * @param SPIx SPI instance
1274 * @retval Returned value can be one of the following values:
1275 * @arg @ref LL_SSI_MICROWIRE_RX
1276 * @arg @ref LL_SSI_MICROWIRE_TX
1277 */
1278 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
1279 {
1280 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MDD));
1281 }
1282
1283 /**
1284 * @brief Set transfer mode in Microwire mode
1285 * @note This bit should not be changed when communication is ongoing.
1286 *
1287 * \rst
1288 * +----------------------+-----------------------------------+
1289 * | Register | BitsName |
1290 * +======================+===================================+
1291 * | MWC | MWMOD |
1292 * +----------------------+-----------------------------------+
1293 * \endrst
1294 *
1295 * @param SPIx SPI instance
1296 * @param transfer_mode This parameter can be one of the following values:
1297 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1298 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1299 * @retval None
1300 */
1301 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
1302 {
1303 MODIFY_REG(SPIx->MWC, SSI_MWC_MWMOD, transfer_mode);
1304 }
1305
1306 /**
1307 * @brief Get transfer mode in Microwire mode
1308 * @note This bit should not be changed when communication is ongoing.
1309 *
1310 * \rst
1311 * +----------------------+-----------------------------------+
1312 * | Register | BitsName |
1313 * +======================+===================================+
1314 * | MWC | MWMOD |
1315 * +----------------------+-----------------------------------+
1316 * \endrst
1317 *
1318 * @param SPIx SPI instance
1319 * @retval Returned value can be one of the following values:
1320 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1321 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1322 */
1323 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
1324 {
1325 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MWMOD));
1326 }
1327
1328 /**
1329 * @brief Enable slave select
1330 *
1331 * \rst
1332 * +----------------------+-----------------------------------+
1333 * | Register | BitsName |
1334 * +======================+===================================+
1335 * | SE | SLAVE1 |
1336 * +----------------------+-----------------------------------+
1337 * \endrst
1338 * SE | SLAVE0
1339 *
1340 * @param SPIx SPI instance
1341 * @param ss This parameter can be one of the following values:
1342 * @arg @ref LL_SSI_SLAVE1
1343 * @arg @ref LL_SSI_SLAVE0
1344 * @retval None
1345 */
1346 __STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
1347 {
1348 SET_BITS(SPIx->SE, ss);
1349 }
1350
1351 /**
1352 * @brief Disable slave select
1353 *
1354 * \rst
1355 * +----------------------+-----------------------------------+
1356 * | Register | BitsName |
1357 * +======================+===================================+
1358 * | SE | SLAVE1 |
1359 * +----------------------+-----------------------------------+
1360 * \endrst
1361 * SE | SLAVE0
1362 *
1363 * @param SPIx SPI instance
1364 * @param ss This parameter can be one of the following values:
1365 * @arg @ref LL_SSI_SLAVE1
1366 * @arg @ref LL_SSI_SLAVE0
1367 * @retval None
1368 */
1369 __STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
1370 {
1371 CLEAR_BITS(SPIx->SE, ss);
1372 }
1373
1374 /**
1375 * @brief Check if slave select is enabled
1376 *
1377 * \rst
1378 * +----------------------+-----------------------------------+
1379 * | Register | BitsName |
1380 * +======================+===================================+
1381 * | SE | SLAVE1 |
1382 * +----------------------+-----------------------------------+
1383 * \endrst
1384 * SE | SLAVE0
1385 *
1386 * @param SPIx SPI instance
1387 * @param ss This parameter can be one of the following values:
1388 * @arg @ref LL_SSI_SLAVE1
1389 * @arg @ref LL_SSI_SLAVE0
1390 * @retval State of bit (1 or 0).
1391 */
1392 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
1393 {
1394 return (READ_BITS(SPIx->SE, ss) == ss);
1395 }
1396
1397 /**
1398 * @brief Set baud rate prescaler
1399 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
1400 *
1401 * \rst
1402 * +----------------------+-----------------------------------+
1403 * | Register | BitsName |
1404 * +======================+===================================+
1405 * | BAUD | SCKDIV |
1406 * +----------------------+-----------------------------------+
1407 * \endrst
1408 *
1409 * @param SPIx SPI instance
1410 * @param baud_rate This parameter can be one even value between 2 and 65534, if the value is 0, the SCLK is disable.
1411 * @retval None
1412 */
1413 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
1414 {
1415 WRITE_REG(SPIx->BAUD, baud_rate);
1416 }
1417
1418 /**
1419 * @brief Get baud rate prescaler
1420 *
1421 * \rst
1422 * +----------------------+-----------------------------------+
1423 * | Register | BitsName |
1424 * +======================+===================================+
1425 * | BAUD | SCKDIV |
1426 * +----------------------+-----------------------------------+
1427 * \endrst
1428 *
1429 * @param SPIx SPI instance
1430 * @retval Returned value can be one even value between 2 and 65534.
1431 */
1432 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
1433 {
1434 return (uint32_t)(READ_BITS(SPIx->BAUD, SSI_BAUD_SCKDIV));
1435 }
1436
1437 /**
1438 * @brief Set threshold of TXFIFO that triggers an TXE event
1439 *
1440 * \rst
1441 * +----------------------+-----------------------------------+
1442 * | Register | BitsName |
1443 * +======================+===================================+
1444 * | TXFTL | TFT |
1445 * +----------------------+-----------------------------------+
1446 * \endrst
1447 *
1448 * @param SPIx SPI instance
1449 * @param threshold This parameter can be one of the following values: 0 ~ 7
1450 * @retval None
1451 */
1452 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1453 {
1454 WRITE_REG(SPIx->TX_FTL, threshold);
1455 }
1456
1457 /**
1458 * @brief Get threshold of TXFIFO that triggers an TXE event
1459 *
1460 * \rst
1461 * +----------------------+-----------------------------------+
1462 * | Register | BitsName |
1463 * +======================+===================================+
1464 * | TXFTL | TFT |
1465 * +----------------------+-----------------------------------+
1466 * \endrst
1467 *
1468 * @param SPIx SPI instance
1469 * @retval Returned value can be one of the following values: 0 ~ 7
1470 */
1471 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
1472 {
1473 return (uint32_t)(READ_BITS(SPIx->TX_FTL, SSI_TXFTL_TFT));
1474 }
1475
1476 /**
1477 * @brief Set threshold of RXFIFO that triggers an RXNE event
1478 *
1479 * \rst
1480 * +----------------------+-----------------------------------+
1481 * | Register | BitsName |
1482 * +======================+===================================+
1483 * | RXFTL | RFT |
1484 * +----------------------+-----------------------------------+
1485 * \endrst
1486 *
1487 * @param SPIx SPI instance
1488 * @param threshold This parameter can be one of the following values: 0 ~ 7
1489 * @retval None
1490 */
1491 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1492 {
1493 WRITE_REG(SPIx->RX_FTL, threshold);
1494 }
1495
1496 /**
1497 * @brief Get threshold of RXFIFO that triggers an RXNE event
1498 *
1499 * \rst
1500 * +----------------------+-----------------------------------+
1501 * | Register | BitsName |
1502 * +======================+===================================+
1503 * | RXFTL | RFT |
1504 * +----------------------+-----------------------------------+
1505 * \endrst
1506 *
1507 * @param SPIx SPI instance
1508 * @retval Returned value can be one of the following values: 0 ~ 7
1509 */
1510 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
1511 {
1512 return (uint32_t)(READ_BITS(SPIx->RX_FTL, SSI_RXFTL_RFT));
1513 }
1514
1515 /**
1516 * @brief Get FIFO Transmission Level
1517 *
1518 * \rst
1519 * +----------------------+-----------------------------------+
1520 * | Register | BitsName |
1521 * +======================+===================================+
1522 * | TXFL | TXTFL |
1523 * +----------------------+-----------------------------------+
1524 * \endrst
1525 *
1526 * @param SPIx SPI instance
1527 * @retval Returned value can be one of the following values: 0 ~ 8
1528 */
1529 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
1530 {
1531 return (uint32_t)(READ_BITS(SPIx->TX_FL, SSI_TXFL_TXTFL));
1532 }
1533
1534 /**
1535 * @brief Get FIFO reception Level
1536 *
1537 * \rst
1538 * +----------------------+-----------------------------------+
1539 * | Register | BitsName |
1540 * +======================+===================================+
1541 * | RXFL | RXTFL |
1542 * +----------------------+-----------------------------------+
1543 * \endrst
1544 *
1545 * @param SPIx SPI instance
1546 * @retval Returned value can be one of the following values: 0 ~ 8
1547 */
1548 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
1549 {
1550 return (uint32_t)(READ_BITS(SPIx->RX_FL, SSI_RXFL_RXTFL));
1551 }
1552
1553 /**
1554 * @brief Get ID code
1555 *
1556 * \rst
1557 * +----------------------+-----------------------------------+
1558 * | Register | BitsName |
1559 * +======================+===================================+
1560 * | IDCODE | ID |
1561 * +----------------------+-----------------------------------+
1562 * \endrst
1563 *
1564 * @param SPIx SPI instance
1565 * @retval Returned value is const.
1566 */
1567 __STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
1568 {
1569 return (uint32_t)(READ_BITS(SPIx->ID, SSI_IDCODE_ID));
1570 }
1571
1572 /**
1573 * @brief Get IP version
1574 *
1575 * \rst
1576 * +----------------------+-----------------------------------+
1577 * | Register | BitsName |
1578 * +======================+===================================+
1579 * | COMP | VERSION |
1580 * +----------------------+-----------------------------------+
1581 * \endrst
1582 *
1583 * @param SPIx SPI instance
1584 * @retval Returned value is const.
1585 */
1586 __STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
1587 {
1588 return (uint32_t)(READ_BITS(SPIx->VERSION_ID, SSI_COMP_VERSION));
1589 }
1590
1591 /** @} */
1592
1593 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1594 * @{
1595 */
1596
1597 /**
1598 * @brief Enable interrupt
1599 * @note This bit controls the generation of an interrupt when an event occurs.
1600 *
1601 * \rst
1602 * +----------------------+-----------------------------------+
1603 * | Register | BitsName |
1604 * +======================+===================================+
1605 * | INTMASK | INTMASK |
1606 * +----------------------+-----------------------------------+
1607 * \endrst
1608 *
1609 * @param SPIx SPI instance
1610 * @param mask This parameter can be one of the following values:
1611 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1612 * @arg @ref LL_SSI_IM_RXF
1613 * @arg @ref LL_SSI_IM_RXO
1614 * @arg @ref LL_SSI_IM_RXU
1615 * @arg @ref LL_SSI_IM_TXO
1616 * @arg @ref LL_SSI_IM_TXE
1617 * @retval None
1618 */
1619 __STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
1620 {
1621 SET_BITS(SPIx->INTMASK, mask);
1622 }
1623
1624 /**
1625 * @brief Disable interrupt
1626 * @note This bit controls the generation of an interrupt when an event occurs.
1627 *
1628 * \rst
1629 * +----------------------+-----------------------------------+
1630 * | Register | BitsName |
1631 * +======================+===================================+
1632 * | INTMASK | INTMASK |
1633 * +----------------------+-----------------------------------+
1634 * \endrst
1635 *
1636 * @param SPIx SPI instance
1637 * @param mask This parameter can be one of the following values:
1638 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1639 * @arg @ref LL_SSI_IM_RXF
1640 * @arg @ref LL_SSI_IM_RXO
1641 * @arg @ref LL_SSI_IM_RXU
1642 * @arg @ref LL_SSI_IM_TXO
1643 * @arg @ref LL_SSI_IM_TXE
1644 * @retval None
1645 */
1646 __STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
1647 {
1648 CLEAR_BITS(SPIx->INTMASK, mask);
1649 }
1650
1651 /**
1652 * @brief Check if interrupt is enabled
1653 *
1654 * \rst
1655 * +----------------------+-----------------------------------+
1656 * | Register | BitsName |
1657 * +======================+===================================+
1658 * | INTMASK | INTMASK |
1659 * +----------------------+-----------------------------------+
1660 * \endrst
1661 *
1662 * @param SPIx SPI instance
1663 * @param mask This parameter can be one of the following values:
1664 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1665 * @arg @ref LL_SSI_IM_RXF
1666 * @arg @ref LL_SSI_IM_RXO
1667 * @arg @ref LL_SSI_IM_RXU
1668 * @arg @ref LL_SSI_IM_TXO
1669 * @arg @ref LL_SSI_IM_TXE
1670 * @retval State of bit (1 or 0).
1671 */
1672 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
1673 {
1674 return (READ_BITS(SPIx->INTMASK, mask) == mask);
1675 }
1676
1677 /** @} */
1678
1679 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1680 * @{
1681 */
1682
1683 /**
1684 * @brief Get SPI status
1685 *
1686 * \rst
1687 * +----------------------+-----------------------------------+
1688 * | Register | BitsName |
1689 * +======================+===================================+
1690 * | STAT | STAT |
1691 * +----------------------+-----------------------------------+
1692 * \endrst
1693 *
1694 * @param SPIx SPI instance
1695 * @retval Returned value can be one or combination of the following values:
1696 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1697 * @arg @ref LL_SSI_SR_TXE
1698 * @arg @ref LL_SSI_SR_RFF
1699 * @arg @ref LL_SSI_SR_RFNE
1700 * @arg @ref LL_SSI_SR_TFE
1701 * @arg @ref LL_SSI_SR_TFNF
1702 * @arg @ref LL_SSI_SR_BUSY
1703 */
1704 __STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
1705 {
1706 return (uint32_t)(READ_REG(SPIx->STAT));
1707 }
1708
1709 /**
1710 * @brief Check active flag
1711 *
1712 * \rst
1713 * +----------------------+-----------------------------------+
1714 * | Register | BitsName |
1715 * +======================+===================================+
1716 * | STAT | DCOL |
1717 * +----------------------+-----------------------------------+
1718 * | STAT | TXE |
1719 * +----------------------+-----------------------------------+
1720 * | STAT | RFF |
1721 * +----------------------+-----------------------------------+
1722 * | STAT | RFNE |
1723 * +----------------------+-----------------------------------+
1724 * | STAT | TFE |
1725 * +----------------------+-----------------------------------+
1726 * | STAT | TFNF |
1727 * +----------------------+-----------------------------------+
1728 * | STAT | BUSY |
1729 * +----------------------+-----------------------------------+
1730 * \endrst
1731 *
1732 * @param SPIx SPI instance
1733 * @param flag This parameter can be one of the following values:
1734 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1735 * @arg @ref LL_SSI_SR_TXE
1736 * @arg @ref LL_SSI_SR_RFF
1737 * @arg @ref LL_SSI_SR_RFNE
1738 * @arg @ref LL_SSI_SR_TFE
1739 * @arg @ref LL_SSI_SR_TFNF
1740 * @arg @ref LL_SSI_SR_BUSY
1741 * @retval State of bit (1 or 0).
1742 */
1743 __STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
1744 {
1745 return (READ_BITS(SPIx->STAT, flag) == (flag));
1746 }
1747
1748 /**
1749 * @brief Get SPI interrupt flags
1750 *
1751 * \rst
1752 * +----------------------+-----------------------------------+
1753 * | Register | BitsName |
1754 * +======================+===================================+
1755 * | INTSTAT | INTSTAT |
1756 * +----------------------+-----------------------------------+
1757 * \endrst
1758 *
1759 * @param SPIx SPI instance
1760 * @retval Returned value can be one or combination of the following values:
1761 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1762 * @arg @ref LL_SSI_IS_RXF
1763 * @arg @ref LL_SSI_IS_RXO
1764 * @arg @ref LL_SSI_IS_RXU
1765 * @arg @ref LL_SSI_IS_TXO
1766 * @arg @ref LL_SSI_IS_TXE
1767 */
1768 __STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
1769 {
1770 return (uint32_t)(READ_REG(SPIx->INTSTAT));
1771 }
1772
1773 /**
1774 * @brief Check interrupt flag
1775 *
1776 * \rst
1777 * +----------------------+-----------------------------------+
1778 * | Register | BitsName |
1779 * +======================+===================================+
1780 * | INTSTAT | MSTIS |
1781 * +----------------------+-----------------------------------+
1782 * \endrst
1783 * INTSTAT | RXFIS
1784 * INTSTAT | RXOIS
1785 * INTSTAT | RXUIS
1786 * INTSTAT | TXOIS
1787 * INTSTAT | TXEIS
1788 *
1789 * @param SPIx SPI instance
1790 * @param flag This parameter can be one of the following values:
1791 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1792 * @arg @ref LL_SSI_IS_RXF
1793 * @arg @ref LL_SSI_IS_RXO
1794 * @arg @ref LL_SSI_IS_RXU
1795 * @arg @ref LL_SSI_IS_TXO
1796 * @arg @ref LL_SSI_IS_TXE
1797 * @retval State of bit (1 or 0).
1798 */
1799 __STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
1800 {
1801 return (READ_BITS(SPIx->INTSTAT, flag) == flag);
1802 }
1803
1804 /**
1805 * @brief Get SPI raw interrupt flags
1806 *
1807 * \rst
1808 * +----------------------+-----------------------------------+
1809 * | Register | BitsName |
1810 * +======================+===================================+
1811 * | RAW_INTSTAT | RAW_INTSTAT |
1812 * +----------------------+-----------------------------------+
1813 * \endrst
1814 *
1815 * @param SPIx SPI instance
1816 * @retval Returned value can be one or combination of the following values:
1817 * @arg @ref LL_SSI_RIS_MST(no effect in SPIS)
1818 * @arg @ref LL_SSI_RIS_RXF
1819 * @arg @ref LL_SSI_RIS_RXO
1820 * @arg @ref LL_SSI_RIS_RXU
1821 * @arg @ref LL_SSI_RIS_TXO
1822 * @arg @ref LL_SSI_RIS_TXE
1823 */
1824 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
1825 {
1826 return (uint32_t)(READ_REG(SPIx->RAW_INTSTAT));
1827 }
1828
1829 /**
1830 * @brief Clear transmit FIFO overflow error flag
1831 * @note Clearing this flag is done by reading TXOIC register
1832 *
1833 * \rst
1834 * +----------------------+-----------------------------------+
1835 * | Register | BitsName |
1836 * +======================+===================================+
1837 * | TXOIC | TXOIC |
1838 * +----------------------+-----------------------------------+
1839 * \endrst
1840 *
1841 * @param SPIx SPI instance
1842 * @retval None
1843 */
1844 __STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
1845 {
1846 __IOM uint32_t tmpreg;
1847 tmpreg = SPIx->TXOIC;
1848 (void) tmpreg;
1849 }
1850
1851 /**
1852 * @brief Clear receive FIFO overflow error flag
1853 * @note Clearing this flag is done by reading RXOIC register
1854 *
1855 * \rst
1856 * +----------------------+-----------------------------------+
1857 * | Register | BitsName |
1858 * +======================+===================================+
1859 * | RXOIC | RXOIC |
1860 * +----------------------+-----------------------------------+
1861 * \endrst
1862 *
1863 * @param SPIx SPI instance
1864 * @retval None
1865 */
1866 __STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
1867 {
1868 __IOM uint32_t tmpreg;
1869 tmpreg = SPIx->RXOIC;
1870 (void) tmpreg;
1871 }
1872
1873 /**
1874 * @brief Clear receive FIFO underflow error flag
1875 * @note Clearing this flag is done by reading RXUIC register
1876 *
1877 * \rst
1878 * +----------------------+-----------------------------------+
1879 * | Register | BitsName |
1880 * +======================+===================================+
1881 * | RXUIC | RXUIC |
1882 * +----------------------+-----------------------------------+
1883 * \endrst
1884 *
1885 * @param SPIx SPI instance
1886 * @retval None
1887 */
1888 __STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
1889 {
1890 __IOM uint32_t tmpreg;
1891 tmpreg = SPIx->RXUIC;
1892 (void) tmpreg;
1893 }
1894
1895 /**
1896 * @brief Clear multi-master error flag
1897 * @note Clearing this flag is done by reading MSTIC register
1898 *
1899 * \rst
1900 * +----------------------+-----------------------------------+
1901 * | Register | BitsName |
1902 * +======================+===================================+
1903 * | MSTIC | MSTIC |
1904 * +----------------------+-----------------------------------+
1905 * \endrst
1906 *
1907 * @param SPIx SPI instance
1908 * @retval None
1909 */
1910 __STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
1911 {
1912 __IOM uint32_t tmpreg;
1913 tmpreg = SPIx->MSTIC;
1914 (void) tmpreg;
1915 }
1916
1917 /**
1918 * @brief Clear all error flag
1919 * @note Clearing this flag is done by reading INTCLR register
1920 *
1921 * \rst
1922 * +----------------------+-----------------------------------+
1923 * | Register | BitsName |
1924 * +======================+===================================+
1925 * | INTCLR | INTCLR |
1926 * +----------------------+-----------------------------------+
1927 * \endrst
1928 *
1929 * @param SPIx SPI instance
1930 * @retval None
1931 */
1932 __STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
1933 {
1934 __IOM uint32_t tmpreg;
1935 tmpreg = SPIx->INTCLR;
1936 (void) tmpreg;
1937 }
1938
1939 /** @} */
1940
1941 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1942 * @{
1943 */
1944
1945 /**
1946 * @brief Enable DMA Tx
1947 *
1948 * \rst
1949 * +----------------------+-----------------------------------+
1950 * | Register | BitsName |
1951 * +======================+===================================+
1952 * | DMAC | TDMAE |
1953 * +----------------------+-----------------------------------+
1954 * \endrst
1955 *
1956 * @param SPIx SPI instance
1957 * @retval None
1958 */
1959 __STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
1960 {
1961 SET_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1962 }
1963
1964 /**
1965 * @brief Disable DMA Tx
1966 *
1967 * \rst
1968 * +----------------------+-----------------------------------+
1969 * | Register | BitsName |
1970 * +======================+===================================+
1971 * | DMAC | TDMAE |
1972 * +----------------------+-----------------------------------+
1973 * \endrst
1974 *
1975 * @param SPIx SPI instance
1976 * @retval None
1977 */
1978 __STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
1979 {
1980 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1981 }
1982
1983 /**
1984 * @brief Check if DMA Tx is enabled
1985 *
1986 * \rst
1987 * +----------------------+-----------------------------------+
1988 * | Register | BitsName |
1989 * +======================+===================================+
1990 * | DMAC | TDMAE |
1991 * +----------------------+-----------------------------------+
1992 * \endrst
1993 *
1994 * @param SPIx SPI instance
1995 * @retval State of bit (1 or 0).
1996 */
1997 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
1998 {
1999 return (READ_BITS(SPIx->DMAC, SSI_DMAC_TDMAE) == (SSI_DMAC_TDMAE));
2000 }
2001
2002 /**
2003 * @brief Enable DMA Rx
2004 *
2005 * \rst
2006 * +----------------------+-----------------------------------+
2007 * | Register | BitsName |
2008 * +======================+===================================+
2009 * | DMAC | RDMAE |
2010 * +----------------------+-----------------------------------+
2011 * \endrst
2012 *
2013 * @param SPIx SPI instance
2014 * @retval None
2015 */
2016 __STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
2017 {
2018 SET_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
2019 }
2020
2021 /**
2022 * @brief Disable DMA Rx
2023 *
2024 * \rst
2025 * +----------------------+-----------------------------------+
2026 * | Register | BitsName |
2027 * +======================+===================================+
2028 * | DMAC | RDMAE |
2029 * +----------------------+-----------------------------------+
2030 * \endrst
2031 *
2032 * @param SPIx SPI instance
2033 * @retval None
2034 */
2035 __STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
2036 {
2037 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
2038 }
2039
2040 /**
2041 * @brief Check if DMA Rx is enabled
2042 *
2043 * \rst
2044 * +----------------------+-----------------------------------+
2045 * | Register | BitsName |
2046 * +======================+===================================+
2047 * | DMAC | RDMAE |
2048 * +----------------------+-----------------------------------+
2049 * \endrst
2050 *
2051 * @param SPIx SPI instance
2052 * @retval State of bit (1 or 0).
2053 */
2054 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
2055 {
2056 return (READ_BITS(SPIx->DMAC, SSI_DMAC_RDMAE) == (SSI_DMAC_RDMAE));
2057 }
2058
2059 /**
2060 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
2061 *
2062 * \rst
2063 * +----------------------+-----------------------------------+
2064 * | Register | BitsName |
2065 * +======================+===================================+
2066 * | DMATDL | DMATDL |
2067 * +----------------------+-----------------------------------+
2068 * \endrst
2069 *
2070 * @param SPIx SPI instance
2071 * @param threshold This parameter can be one of the following values: 0 ~ 7
2072 * @retval None
2073 */
2074 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
2075 {
2076 WRITE_REG(SPIx->DMA_TDL, threshold);
2077 }
2078
2079 /**
2080 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
2081 *
2082 * \rst
2083 * +----------------------+-----------------------------------+
2084 * | Register | BitsName |
2085 * +======================+===================================+
2086 * | DMATDL | DMATDL |
2087 * +----------------------+-----------------------------------+
2088 * \endrst
2089 *
2090 * @param SPIx SPI instance
2091 * @retval Returned value can be one of the following values: 0 ~ 7
2092 */
2093 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
2094 {
2095 return (uint32_t)(READ_BITS(SPIx->DMA_TDL, SSI_DMATDL_DMATDL));
2096 }
2097
2098 /**
2099 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
2100 *
2101 * \rst
2102 * +----------------------+-----------------------------------+
2103 * | Register | BitsName |
2104 * +======================+===================================+
2105 * | DMARDL | DMARDL |
2106 * +----------------------+-----------------------------------+
2107 * \endrst
2108 *
2109 * @param SPIx SPI instance
2110 * @param threshold This parameter can be one of the following values: 0 ~ 7
2111 * @retval None
2112 */
2113 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
2114 {
2115 WRITE_REG(SPIx->DMA_RDL, threshold);
2116 }
2117
2118 /**
2119 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
2120 *
2121 * \rst
2122 * +----------------------+-----------------------------------+
2123 * | Register | BitsName |
2124 * +======================+===================================+
2125 * | DMARDL | DMARDL |
2126 * +----------------------+-----------------------------------+
2127 * \endrst
2128 *
2129 * @param SPIx SPI instance
2130 * @retval Returned value can be one of the following values: 0 ~ 7
2131 */
2132 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
2133 {
2134 return (uint32_t)(READ_BITS(SPIx->DMA_RDL, SSI_DMARDL_DMARDL));
2135 }
2136
2137 /** @} */
2138
2139 /** @defgroup SPI_LL_EF_Data_Management Data_Management
2140 * @{
2141 */
2142
2143 /**
2144 * @brief Write 8-Bits in the data register
2145 *
2146 * \rst
2147 * +----------------------+-----------------------------------+
2148 * | Register | BitsName |
2149 * +======================+===================================+
2150 * | DATA | DATA |
2151 * +----------------------+-----------------------------------+
2152 * \endrst
2153 *
2154 * @param SPIx SPI instance
2155 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
2156 * @retval None
2157 */
2158 __STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
2159 {
2160 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
2161 }
2162
2163 /**
2164 * @brief Write 16-Bits in the data register
2165 *
2166 * \rst
2167 * +----------------------+-----------------------------------+
2168 * | Register | BitsName |
2169 * +======================+===================================+
2170 * | DATA | DATA |
2171 * +----------------------+-----------------------------------+
2172 * \endrst
2173 *
2174 * @param SPIx SPI instance
2175 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
2176 * @retval None
2177 */
2178 __STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
2179 {
2180 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
2181 }
2182
2183 /**
2184 * @brief Write 32-Bits in the data register
2185 *
2186 * \rst
2187 * +----------------------+-----------------------------------+
2188 * | Register | BitsName |
2189 * +======================+===================================+
2190 * | DATA | DATA |
2191 * +----------------------+-----------------------------------+
2192 * \endrst
2193 *
2194 * @param SPIx SPI instance
2195 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2196 * @retval None
2197 */
2198 __STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
2199 {
2200 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
2201 }
2202
2203 /**
2204 * @brief Read 8-Bits in the data register
2205 *
2206 * \rst
2207 * +----------------------+-----------------------------------+
2208 * | Register | BitsName |
2209 * +======================+===================================+
2210 * | DATA | DATA |
2211 * +----------------------+-----------------------------------+
2212 * \endrst
2213 *
2214 * @param SPIx SPI instance
2215 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
2216 */
2217 __STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
2218 {
2219 return (uint8_t)(READ_REG(SPIx->DATA));
2220 }
2221
2222 /**
2223 * @brief Read 16-Bits in the data register
2224 *
2225 * \rst
2226 * +----------------------+-----------------------------------+
2227 * | Register | BitsName |
2228 * +======================+===================================+
2229 * | DATA | DATA |
2230 * +----------------------+-----------------------------------+
2231 * \endrst
2232 *
2233 * @param SPIx SPI instance
2234 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
2235 */
2236 __STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
2237 {
2238 return (uint16_t)(READ_REG(SPIx->DATA));
2239 }
2240
2241 /**
2242 * @brief Read 32-Bits in the data register
2243 *
2244 * \rst
2245 * +----------------------+-----------------------------------+
2246 * | Register | BitsName |
2247 * +======================+===================================+
2248 * | DATA | DATA |
2249 * +----------------------+-----------------------------------+
2250 * \endrst
2251 *
2252 * @param SPIx SPI instance
2253 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2254 */
2255 __STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
2256 {
2257 return (uint32_t)(READ_REG(SPIx->DATA));
2258 }
2259
2260 /**
2261 * @brief Set Rx sample delay
2262 * @note This bit should not be changed when communication is ongoing.
2263 *
2264 * \rst
2265 * +----------------------+-----------------------------------+
2266 * | Register | BitsName |
2267 * +======================+===================================+
2268 * | RX_SAMPLEDLY | RX_SAMPLEDLY |
2269 * +----------------------+-----------------------------------+
2270 * \endrst
2271 *
2272 * @param SPIx SPI instance
2273 * @param delay This parameter can be one of the following values: 0 ~ 256
2274 * @retval None
2275 */
2276 __STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
2277 {
2278 WRITE_REG(SPIx->RX_SAMPLE_DLY, delay);
2279 }
2280
2281 /**
2282 * @brief Get Rx sample delay
2283 * @note This bit should not be changed when communication is ongoing.
2284 *
2285 * \rst
2286 * +----------------------+-----------------------------------+
2287 * | Register | BitsName |
2288 * +======================+===================================+
2289 * | RX_SAMPLEDLY | RX_SAMPLEDLY |
2290 * +----------------------+-----------------------------------+
2291 * \endrst
2292 *
2293 * @param SPIx SPI instance
2294 * @retval Returned value can be one of the following values: 0 ~ 256
2295 */
2296 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
2297 {
2298 return (uint32_t)(READ_REG(SPIx->RX_SAMPLE_DLY));
2299 }
2300
2301 /**
2302 * @brief Set number of wait cycles in Dual/Quad SPI mode
2303 * @note This bit should not be changed when communication is ongoing.
2304 *
2305 * \rst
2306 * +----------------------+-----------------------------------+
2307 * | Register | BitsName |
2308 * +======================+===================================+
2309 * | SCTRL0 | WAITCYCLES |
2310 * +----------------------+-----------------------------------+
2311 * \endrst
2312 *
2313 * @param SPIx SPI instance
2314 * @param wait_cycles This parameter can be one of the following values: 0 ~ 31
2315 * @retval None
2316 */
2317 __STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
2318 {
2319 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES, wait_cycles << SSI_SCTRL0_WAITCYCLES_Pos);
2320 }
2321
2322 /**
2323 * @brief Get number of wait cycles in Dual/Quad SPI mode
2324 * @note This bit should not be changed when communication is ongoing.
2325 *
2326 * \rst
2327 * +----------------------+-----------------------------------+
2328 * | Register | BitsName |
2329 * +======================+===================================+
2330 * | SCTRL0 | WAITCYCLES |
2331 * +----------------------+-----------------------------------+
2332 * \endrst
2333 *
2334 * @param SPIx SPI instance
2335 * @retval Returned value can be one of the following values: 0 ~ 31
2336 */
2337 __STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
2338 {
2339 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES) >> SSI_SCTRL0_WAITCYCLES_Pos);
2340 }
2341
2342 /**
2343 * @brief Set Dual/Quad SPI mode instruction length in bits
2344 * @note This bit should not be changed when communication is ongoing.
2345 *
2346 * \rst
2347 * +----------------------+-----------------------------------+
2348 * | Register | BitsName |
2349 * +======================+===================================+
2350 * | SCTRL0 | INSTL |
2351 * +----------------------+-----------------------------------+
2352 * \endrst
2353 *
2354 * @param SPIx SPI instance
2355 * @param size This parameter can be one of the following values:
2356 * @arg @ref LL_SSI_INSTSIZE_0BIT
2357 * @arg @ref LL_SSI_INSTSIZE_4BIT
2358 * @arg @ref LL_SSI_INSTSIZE_8BIT
2359 * @arg @ref LL_SSI_INSTSIZE_16BIT
2360 * @retval None
2361 */
2362 __STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
2363 {
2364 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL, size);
2365 }
2366
2367 /**
2368 * @brief Get Dual/Quad SPI mode instruction length in bits
2369 * @note This bit should not be changed when communication is ongoing.
2370 *
2371 * \rst
2372 * +----------------------+-----------------------------------+
2373 * | Register | BitsName |
2374 * +======================+===================================+
2375 * | SCTRL0 | INSTL |
2376 * +----------------------+-----------------------------------+
2377 * \endrst
2378 *
2379 * @param SPIx SPI instance
2380 * @retval Returned value can be one of the following values:
2381 * @arg @ref LL_SSI_INSTSIZE_0BIT
2382 * @arg @ref LL_SSI_INSTSIZE_4BIT
2383 * @arg @ref LL_SSI_INSTSIZE_8BIT
2384 * @arg @ref LL_SSI_INSTSIZE_16BIT
2385 */
2386 __STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
2387 {
2388 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL));
2389 }
2390
2391 /**
2392 * @brief Set Dual/Quad SPI mode address length in bits
2393 * @note This bit should not be changed when communication is ongoing.
2394 *
2395 * \rst
2396 * +----------------------+-----------------------------------+
2397 * | Register | BitsName |
2398 * +======================+===================================+
2399 * | SCTRL0 | ADDRL |
2400 * +----------------------+-----------------------------------+
2401 * \endrst
2402 *
2403 * @param SPIx SPI instance
2404 * @param size This parameter can be one of the following values:
2405 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2406 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2407 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2408 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2409 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2410 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2411 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2412 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2413 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2414 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2415 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2416 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2417 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2418 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2419 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2420 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2421 * @retval None
2422 */
2423 __STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
2424 {
2425 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL, size);
2426 }
2427
2428 /**
2429 * @brief Get Dual/Quad SPI mode address length in bits
2430 * @note This bit should not be changed when communication is ongoing.
2431 *
2432 * \rst
2433 * +----------------------+-----------------------------------+
2434 * | Register | BitsName |
2435 * +======================+===================================+
2436 * | SCTRL0 | ADDRL |
2437 * +----------------------+-----------------------------------+
2438 * \endrst
2439 *
2440 * @param SPIx SPI instance
2441 * @retval Returned value can be one of the following values:
2442 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2443 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2444 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2445 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2446 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2447 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2448 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2449 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2450 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2451 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2452 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2453 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2454 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2455 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2456 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2457 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2458 */
2459 __STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
2460 {
2461 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL));
2462 }
2463
2464 /**
2465 * @brief Set Dual/Quad SPI mode address and instruction transfer format
2466 * @note This bit should not be changed when communication is ongoing.
2467 *
2468 * \rst
2469 * +----------------------+-----------------------------------+
2470 * | Register | BitsName |
2471 * +======================+===================================+
2472 * | SCTRL0 | TRANSTYPE |
2473 * +----------------------+-----------------------------------+
2474 * \endrst
2475 *
2476 * @param SPIx SPI instance
2477 * @param format This parameter can be one of the following values:
2478 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2479 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2480 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2481 * @retval None
2482 */
2483 __STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
2484 {
2485 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE, format);
2486 }
2487
2488 /**
2489 * @brief Get Dual/Quad SPI mode address and instruction transfer format
2490 * @note This bit should not be changed when communication is ongoing.
2491 *
2492 * \rst
2493 * +----------------------+-----------------------------------+
2494 * | Register | BitsName |
2495 * +======================+===================================+
2496 * | SCTRL0 | TRANSTYPE |
2497 * +----------------------+-----------------------------------+
2498 * \endrst
2499 *
2500 * @param SPIx SPI instance
2501 * @retval Returned value can be one of the following values:
2502 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2503 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2504 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2505 */
2506 __STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
2507 {
2508 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE));
2509 }
2510
2511 /** @} */
2512
2513 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
2514 * @{
2515 */
2516
2517 /**
2518 * @brief De-initialize SSI registers (Registers restored to their default values).
2519 * @param SPIx SSI instance
2520 * @retval An error_status_t enumeration value:
2521 * - SUCCESS: SSI registers are de-initialized
2522 * - ERROR: SSI registers are not de-initialized
2523 */
2524 error_status_t ll_spim_deinit(ssi_regs_t *SPIx);
2525
2526 /**
2527 * @brief Initialize SPIM registers according to the specified
2528 * parameters in p_spi_init.
2529 * @param SPIx SSI instance
2530 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
2531 * information for the specified SPIM peripheral.
2532 * @retval An error_status_t enumeration value:
2533 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2534 * - ERROR: Problem occurred during SSI Registers initialization
2535 */
2536 error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
2537
2538 /**
2539 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
2540 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
2541 * whose fields will be set to default values.
2542 * @retval None
2543 */
2544 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
2545
2546 /** @} */
2547
2548 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
2549 * @{
2550 */
2551
2552 /**
2553 * @brief De-initialize SSI registers (Registers restored to their default values).
2554 * @param SPIx SSI instance
2555 * @retval An error_status_t enumeration value:
2556 * - SUCCESS: SSI registers are de-initialized
2557 * - ERROR: SSI registers are not de-initialized
2558 */
2559 error_status_t ll_spis_deinit(ssi_regs_t *SPIx);
2560
2561 /**
2562 * @brief Initialize SSI registers according to the specified
2563 * parameters in p_spi_init.
2564 * @param SPIx SSI instance
2565 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
2566 * information for the specified SPIS peripheral.
2567 * @retval An error_status_t enumeration value:
2568 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2569 * - ERROR: Problem occurred during SPI Registers initialization
2570 */
2571 error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
2572
2573 /**
2574 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
2575 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
2576 * whose fields will be set to default values.
2577 * @retval None
2578 */
2579 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
2580 /** @} */
2581
2582 /** @defgroup QSPI_LL_Init QSPI Initialization and de-initialization functions
2583 * @{
2584 */
2585
2586 /**
2587 * @brief De-initialize SSI registers (Registers restored to their default values).
2588 * @param SPIx SSI instance
2589 * @retval An error_status_t enumeration value:
2590 * - SUCCESS: SSI registers are de-initialized
2591 * - ERROR: SSI registers are not de-initialized
2592 */
2593 error_status_t ll_qspi_deinit(ssi_regs_t *SPIx);
2594
2595 /**
2596 * @brief Initialize SSI registers according to the specified
2597 * parameters in SPI_InitStruct.
2598 * @param SPIx SSI instance
2599 * @param p_spi_init Pointer to a ll_qspi_init_t structure that contains the configuration
2600 * information for the specified QSPI peripheral.
2601 * @retval An error_status_t enumeration value:
2602 * - SUCCESS: SPI registers are initialized according to p_spi_init content
2603 * - ERROR: Problem occurred during SPI Registers initialization
2604 */
2605 error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init);
2606
2607 /**
2608 * @brief Set each field of a @ref ll_qspi_init_t type structure to default value.
2609 * @param p_spi_init Pointer to a @ref ll_qspi_init_t structure
2610 * whose fields will be set to default values.
2611 * @retval None
2612 */
2613 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
2614
2615 /** @} */
2616
2617 /** @} */
2618
2619 #endif /* SPIM || SPIS || QSPI0 || QSPI1 */
2620
2621 #ifdef __cplusplus
2622 }
2623 #endif
2624
2625 #endif /* __GR55xx_LL_SPI_H__ */
2626
2627 /** @} */
2628
2629 /** @} */
2630
2631 /** @} */
ll_spi_disable_ss_toggle
__STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
Disable slave select toggle.
Definition: gr55xx_ll_spi.h:539
ll_spi_get_micro_transfer_mode
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
Get transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1323
ll_spis_deinit
error_status_t ll_spis_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_enable_micro_handshake
__STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
Enable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1195
ll_spim_init
error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
ll_spi_disable_micro_handshake
__STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
Disable Handshake in Microwire mode.
Definition: gr55xx_ll_spi.h:1214
ll_spi_is_enabled_it
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr55xx_ll_spi.h:1672
_ll_spis_init_t
SPIS init structures definition.
Definition: gr55xx_ll_spi.h:114
ll_spi_receive_data8
__STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
Read 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:2217
ll_spi_get_wait_cycles
__STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
Get number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:2337
ll_spim_struct_init
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
_ll_spis_init_t::data_size
uint32_t data_size
Specifies the SPI data width.
Definition: gr55xx_ll_spi.h:115
ll_spi_set_dma_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:2113
_ll_qspi_init_t::instruction_size
uint32_t instruction_size
Specifies the QSPI instruction width.
Definition: gr55xx_ll_spi.h:142
ll_spi_clear_flag_all
__STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
Clear all error flag.
Definition: gr55xx_ll_spi.h:1932
ll_spi_get_frame_format
__STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
Get data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:606
ll_spi_get_rx_sample_delay
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
Get Rx sample delay.
Definition: gr55xx_ll_spi.h:2296
_ll_spim_init_t
LL SPIM init structures definition.
Definition: gr55xx_ll_spi.h:77
ll_spi_is_it_flag
__STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
Definition: gr55xx_ll_spi.h:1799
ll_spi_enable_ss_toggle
__STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
Enable slave select toggle.
Definition: gr55xx_ll_spi.h:519
ll_spi_set_rx_sample_delay
__STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
Definition: gr55xx_ll_spi.h:2276
ll_spi_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
Get FIFO reception Level.
Definition: gr55xx_ll_spi.h:1548
_ll_qspi_init_t::address_size
uint32_t address_size
Specifies the QSPI address width.
Definition: gr55xx_ll_spi.h:147
ll_qspi_init_t
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
ll_spi_set_clock_polarity
__STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
Definition: gr55xx_ll_spi.h:961
_ll_qspi_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:167
ll_spi_set_receive_size
__STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1096
_ll_qspi_init_t::inst_addr_transfer_format
uint32_t inst_addr_transfer_format
Specifies the QSPI instruction and address transfer format.
Definition: gr55xx_ll_spi.h:152
ll_spi_set_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1452
ll_spi_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
Check if DMA Rx is enabled.
Definition: gr55xx_ll_spi.h:2054
ll_spis_struct_init
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
ll_spi_is_enabled
__STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
Check if SPI peripheral is enabled.
Definition: gr55xx_ll_spi.h:1176
ll_spi_disable_test_mode
__STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
Disable SPI test mode.
Definition: gr55xx_ll_spi.h:814
_ll_spim_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:88
ll_spi_get_baud_rate_prescaler
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
Get baud rate prescaler.
Definition: gr55xx_ll_spi.h:1432
_ll_spis_init_t::clock_polarity
uint32_t clock_polarity
Specifies the serial clock steady state.
Definition: gr55xx_ll_spi.h:120
ll_spi_is_enabled_slave_out
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
Check if slave output is enabled.
Definition: gr55xx_ll_spi.h:890
ll_spi_disable_it
__STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
Definition: gr55xx_ll_spi.h:1646
ll_spi_get_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode.
Definition: gr55xx_ll_spi.h:937
ll_spi_get_status
__STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
Get SPI status.
Definition: gr55xx_ll_spi.h:1704
ll_spi_get_receive_size
__STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
Get the number of data frames to be continuously received.
Definition: gr55xx_ll_spi.h:1118
_ll_qspi_init_t::rx_sample_delay
uint32_t rx_sample_delay
Specifies the RX sample delay.
Definition: gr55xx_ll_spi.h:183
ll_spi_clear_flag_rxo
__STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1866
ll_spi_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1510
ll_spi_set_data_size
__STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
Set frame data size.
Definition: gr55xx_ll_spi.h:655
ll_spim_init_t
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
_ll_qspi_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:172
_ll_spim_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_spi.h:103
ll_spi_set_address_size
__STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2423
ll_spis_init
error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
ll_spi_set_standard
__STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
Definition: gr55xx_ll_spi.h:1051
ll_spi_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
Definition: gr55xx_ll_spi.h:1471
_ll_qspi_init_t
QSPI init structures definition.
Definition: gr55xx_ll_spi.h:136
_ll_spim_init_t::transfer_direction
uint32_t transfer_direction
Specifies the SPI unidirectional or bidirectional data mode.
Definition: gr55xx_ll_spi.h:78
ll_spi_set_micro_transfer_mode
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1301
ll_spis_init_t
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
_ll_spim_init_t::data_size
uint32_t data_size
Specifies the SPI data size.
Definition: gr55xx_ll_spi.h:83
ll_spi_enable_dma_req_tx
__STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
Enable DMA Tx.
Definition: gr55xx_ll_spi.h:1959
ll_spi_set_add_inst_transfer_format
__STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2483
ll_spi_disable_dma_req_rx
__STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
Disable DMA Rx.
Definition: gr55xx_ll_spi.h:2035
ll_qspi_deinit
error_status_t ll_qspi_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_id_code
__STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
Get ID code.
Definition: gr55xx_ll_spi.h:1567
ll_spi_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_spi.h:1529
ll_spi_set_rx_fifo_threshold
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
Definition: gr55xx_ll_spi.h:1491
ll_spi_get_micro_transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1278
ll_spi_get_instruction_size
__STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2386
ll_spi_enable
__STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
Enable SPI peripheral.
Definition: gr55xx_ll_spi.h:1137
ll_spi_get_dma_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
Definition: gr55xx_ll_spi.h:2132
ll_spi_receive_data32
__STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
Read 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:2255
ll_spi_get_control_frame_size
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:776
ll_spi_enable_test_mode
__STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
Enable SPI test mode.
Definition: gr55xx_ll_spi.h:795
ll_spi_disable_ss
__STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
Disable slave select.
Definition: gr55xx_ll_spi.h:1369
ll_spi_get_addr_inst_transfer_format
__STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
Definition: gr55xx_ll_spi.h:2506
ll_spi_get_raw_if_flag
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
Get SPI raw interrupt flags.
Definition: gr55xx_ll_spi.h:1824
ll_spi_set_control_frame_size
__STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
Definition: gr55xx_ll_spi.h:740
ll_spi_get_clock_polarity
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
Get clock polarity.
Definition: gr55xx_ll_spi.h:982
ll_spi_set_frame_format
__STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
Definition: gr55xx_ll_spi.h:583
ll_spi_transmit_data32
__STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
Definition: gr55xx_ll_spi.h:2198
_ll_spim_init_t::slave_select
uint32_t slave_select
Specifies the SPI slave select.
Definition: gr55xx_ll_spi.h:98
ll_spi_clear_flag_txo
__STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
Definition: gr55xx_ll_spi.h:1844
ll_spi_get_standard
__STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
Get serial protocol used.
Definition: gr55xx_ll_spi.h:1073
ll_spi_enable_it
__STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
Definition: gr55xx_ll_spi.h:1619
ll_spi_set_instruction_size
__STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
Definition: gr55xx_ll_spi.h:2362
ll_spi_disable_dma_req_tx
__STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
Disable DMA Tx.
Definition: gr55xx_ll_spi.h:1978
ll_spi_get_data_size
__STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
Get frame data size.
Definition: gr55xx_ll_spi.h:703
ll_spi_get_it_flag
__STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
Get SPI interrupt flags.
Definition: gr55xx_ll_spi.h:1768
ll_spi_disable
__STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
Disable SPI peripheral.
Definition: gr55xx_ll_spi.h:1157
ll_spi_receive_data16
__STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
Read 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:2236
ll_spi_transmit_data8
__STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
Definition: gr55xx_ll_spi.h:2158
ll_spi_clear_flag_mst
__STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
Clear multi-master error flag.
Definition: gr55xx_ll_spi.h:1910
ll_spi_is_active_flag
__STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_spi.h:1743
ll_spi_is_enabled_test_mode
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
Check if SPI test mode is enabled.
Definition: gr55xx_ll_spi.h:833
_ll_qspi_init_t::transfer_direction
uint32_t transfer_direction
Specifies the QSPI transfer or receive mode.
Definition: gr55xx_ll_spi.h:137
_ll_spis_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:125
_ll_qspi_init_t::baud_rate
uint32_t baud_rate
Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK c...
Definition: gr55xx_ll_spi.h:177
_ll_spim_init_t::clock_phase
uint32_t clock_phase
Specifies the clock active edge for the bit capture.
Definition: gr55xx_ll_spi.h:93
ll_spi_get_version
__STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
Get IP version.
Definition: gr55xx_ll_spi.h:1586
ll_spi_is_enabled_ss_toggle
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
Check if slave select toggle is enabled.
Definition: gr55xx_ll_spi.h:559
ll_spi_set_transfer_direction
__STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
Definition: gr55xx_ll_spi.h:914
ll_spi_set_clock_phase
__STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
Definition: gr55xx_ll_spi.h:1006
ll_spi_set_wait_cycles
__STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
Definition: gr55xx_ll_spi.h:2317
_ll_qspi_init_t::wait_cycles
uint32_t wait_cycles
Specifies the QSPI dummy clock.
Definition: gr55xx_ll_spi.h:157
ll_spi_is_enabled_micro_handshake
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
Definition: gr55xx_ll_spi.h:1233
ll_spi_enable_dma_req_rx
__STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
Enable DMA Rx.
Definition: gr55xx_ll_spi.h:2016
ll_spim_deinit
error_status_t ll_spim_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
ll_spi_get_dma_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:2093
ll_spi_set_baud_rate_prescaler
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
Definition: gr55xx_ll_spi.h:1413
ll_qspi_struct_init
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
ll_spi_set_micro_transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
Definition: gr55xx_ll_spi.h:1256
ll_spi_set_dma_tx_fifo_threshold
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
Definition: gr55xx_ll_spi.h:2074
ll_spi_clear_flag_rxu
__STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
Definition: gr55xx_ll_spi.h:1888
ll_spi_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
Check if DMA Tx is enabled.
Definition: gr55xx_ll_spi.h:1997
ll_spi_enable_ss
__STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
Enable slave select.
Definition: gr55xx_ll_spi.h:1346
ll_spi_disable_salve_out
__STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
Disable slave output.
Definition: gr55xx_ll_spi.h:871
ll_spi_enable_slave_out
__STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
Enable slave output.
Definition: gr55xx_ll_spi.h:852
_ll_qspi_init_t::data_size
uint32_t data_size
Specifies the SPI data width.
Definition: gr55xx_ll_spi.h:162
ll_spi_get_address_size
__STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address length in bits.
Definition: gr55xx_ll_spi.h:2459
ll_qspi_init
error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
ll_spi_transmit_data16
__STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
Definition: gr55xx_ll_spi.h:2178
ll_spi_is_enabled_ss
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
Definition: gr55xx_ll_spi.h:1392
ll_spi_get_clock_phase
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
Get clock phase.
Definition: gr55xx_ll_spi.h:1027