gr55xx_ll_uart.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (UART0) || defined (UART1)
63
64 /** @defgroup UART_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup UART_LL_ES_INIT UART Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL UART init Structure definition
75 */
76 typedef struct _ll_uart_init_t
77 {
78 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
79
80 This feature can be modified afterwards using unitary function @ref ll_uart_set_baud_rate().*/
81
82 uint32_t data_bits; /**< Specifies the number of data bits transmitted or received in a frame.
83 This parameter can be a value of @ref UART_LL_EC_DATABITS.
84
85 This feature can be modified afterwards using unitary function @ref ll_uart_set_data_bits_length().*/
86
87 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
88 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
89
90 This feature can be modified afterwards using unitary function @ref ll_uart_set_stop_bits_length().*/
91
92 uint32_t parity; /**< Specifies the parity mode.
93 This parameter can be a value of @ref UART_LL_EC_PARITY.
94
95 This feature can be modified afterwards using unitary function @ref ll_uart_set_parity().*/
96
97 uint32_t hw_flow_ctrl; /**< Specifies whether the hardware flow control mode is enabled or disabled.
98 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
99
100 This feature can be modified afterwards using unitary function @ref ll_uart_set_hw_flow_ctrl().*/
101 } ll_uart_init_t;
102
103 /** @} */
104
105 /** @} */
106
107 /**
108 * @defgroup UART_LL_MACRO Defines
109 * @{
110 */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
114 * @{
115 */
116
117 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
118 * @brief Flags definitions which can be used with LL_UART_ReadReg function
119 * @{
120 */
121 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
122 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
123 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
124 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
125 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register empty flag */
126 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
127 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
128
129 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
130 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
131 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
132 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
133 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
134 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
135
136 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
137 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
138 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
139 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
140 /** @} */
141
142 /** @defgroup UART_LL_EC_IT IT Defines
143 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
144 * @{
145 */
146 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status Interrupt */
147 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line Status Interrupt */
148 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding Register Empty Interrupt */
149 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available Interrupt and Character Timeout Interrupt */
150 /** @} */
151
152 /** @defgroup UART_LL_EC_PARITY Parity Control
153 * @{
154 */
155 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
156 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and Odd Parity is selected */
157 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and Even Parity is selected */
158 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and Stick Parity 0 is selected */
159 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and Stick Parity 1 is selected */
160 /** @} */
161
162 /** @defgroup UART_LL_EC_DATABITS Data Bits
163 * @{
164 */
165 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit, 5 data bits, n stop bits */
166 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit, 6 data bits, n stop bits */
167 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit, 7 data bits, n stop bits */
168 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit, 8 data bits, n stop bits */
169 /** @} */
170
171 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
172 * @{
173 */
174 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
175 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
176 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
177 /** @} */
178
179 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
180 * @{
181 */
182 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow control disabled */
183 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow control enabled */
184 /** @} */
185
186 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
187 * @{
188 */
189 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
190 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
191 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
192 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
193 /** @} */
194
195 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
196 * @{
197 */
198 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
199 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
200 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
201 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
202 /** @} */
203
204 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
205 * @{
206 */
207 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
208 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
209 /** @} */
210
211 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
212 * @{
213 */
214 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
215 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
216 /** @} */
217
218 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
219 * @{
220 */
221
222 /**
223 * @brief LL UART InitStrcut default configuartion
224 */
225 #define LL_UART_DEFAULT_CONFIG \
226 { \
227 .baud_rate = 9600U, \
228 .data_bits = LL_UART_DATABITS_8B, \
229 .stop_bits = LL_UART_STOPBITS_1, \
230 .parity = LL_UART_PARITY_NONE, \
231 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
232 }
233 /** @} */
234
235 /** @} */
236
237 /* Exported macro ------------------------------------------------------------*/
238 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
239 * @{
240 */
241
242 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
243 * @{
244 */
245
246 /**
247 * @brief Write a value in UART register
248 * @param __instance__ UART instance
249 * @param __REG__ Register to be written
250 * @param __VALUE__ Value to be written in the register
251 * @retval None
252 */
253 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
254
255 /**
256 * @brief Read a value in UART register
257 * @param __instance__ UART instance
258 * @param __REG__ Register to be read
259 * @retval Register value
260 */
261 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262
263 /** @} */
264
265 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
266 * @{
267 */
268
269 /**
270 * @brief Compute UARTDIV value according to Peripheral Clock and
271 * expected Baud Rate (32 bits value of UARTDIV is returned)
272 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
273 * @param __BAUDRATE__ Baud rate value to achieve
274 * @retval UARTDIV value to be used for DLL,DLH registers
275 */
276 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
277
278 /**
279 * @brief Compute UARTDLF value according to Peripheral Clock and
280 * expected Baud Rate (32 bits value of UARTDLF is returned)
281 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
282 * @param __BAUDRATE__ Baud rate value to achieve
283 * @retval UARTDLF value to be used for DLL,DLH registers
284 */
285 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
286
287 /** @} */
288
289 /** @} */
290
291 /** @} */
292
293 /* Exported functions --------------------------------------------------------*/
294 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
295 * @{
296 */
297
298 /** @defgroup UART_LL_EF_Configuration Configuration functions
299 * @{
300 */
301
302 /**
303 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
304 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
305 * (Baud rate value != 0)
306 *
307 * \rst
308 * +----------------------+-----------------------------------+
309 * | Register | BitsName |
310 * +======================+===================================+
311 * | DLL | DLL |
312 * +----------------------+-----------------------------------+
313 * \endrst
314 * DLH | DLH
315 *
316 * @param UARTx UART instance
317 * @param peripheral_clock Peripheral Clock
318 * @param baud_rate Baud Rate
319 * @retval None
320 */
321 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
322 {
323 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
324
325 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
326 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
327 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
328 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
329 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
330 }
331
332 /**
333 * @brief Return current Baud Rate value
334 * @note In case of non-initialized or invalid value stored in DLL,DLH and DLF register, the value 0 will be returned..
335 *
336 * \rst
337 * +----------------------+-----------------------------------+
338 * | Register | BitsName |
339 * +======================+===================================+
340 * | DLL | DLL |
341 * +----------------------+-----------------------------------+
342 * \endrst
343 * DLH | DLH
344 *
345 * @param UARTx UART instance
346 * @param peripheral_clock Peripheral Clock
347 * @retval Baud Rate
348 */
349 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
350 {
351 register uint32_t uartdiv = 0x0U;
352 register uint32_t baud = 0x0U;
353
354 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
355 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
356 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
357
358 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
359 {
360 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
361 }
362
363 return baud;
364 }
365
366 /**
367 * @brief Set the length of the data bits
368 *
369 * \rst
370 * +----------------------+-----------------------------------+
371 * | Register | BitsName |
372 * +======================+===================================+
373 * | LCR | DLS |
374 * +----------------------+-----------------------------------+
375 * \endrst
376 *
377 * @param UARTx UART instance
378 * @param data_bits This parameter can be one of the following values:
379 * @arg @ref LL_UART_DATABITS_5B
380 * @arg @ref LL_UART_DATABITS_6B
381 * @arg @ref LL_UART_DATABITS_7B
382 * @arg @ref LL_UART_DATABITS_8B
383 *
384 * @retval None
385 */
386 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
387 {
388 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
389 }
390
391 /**
392 * @brief Return the length of the data bits
393 *
394 * \rst
395 * +----------------------+-----------------------------------+
396 * | Register | BitsName |
397 * +======================+===================================+
398 * | LCR | DLS |
399 * +----------------------+-----------------------------------+
400 * \endrst
401 *
402 * @param UARTx UART instance
403 * @retval Returned value can be one of the following values:
404 * @arg @ref LL_UART_DATABITS_5B
405 * @arg @ref LL_UART_DATABITS_6B
406 * @arg @ref LL_UART_DATABITS_7B
407 * @arg @ref LL_UART_DATABITS_8B
408 */
409 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
410 {
411 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
412 }
413
414 /**
415 * @brief Set the length of the stop bits
416 *
417 * \rst
418 * +----------------------+-----------------------------------+
419 * | Register | BitsName |
420 * +======================+===================================+
421 * | LCR | STOP |
422 * +----------------------+-----------------------------------+
423 * \endrst
424 *
425 * @param UARTx UART instance
426 * @param stop_bits This parameter can be one of the following values:
427 * @arg @ref LL_UART_STOPBITS_1
428 * @arg @ref LL_UART_STOPBITS_1_5 (*)
429 * @arg @ref LL_UART_STOPBITS_2 (*)
430 *
431 * (*) STOPBITS_1_5 only valid when DataBits = 5
432 * (*) STOPBITS_2 is invalid when DataBits = 5
433 * @retval None
434 */
435 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
436 {
437 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
438 }
439
440 /**
441 * @brief Retrieve the length of the stop bits
442 *
443 * \rst
444 * +----------------------+-----------------------------------+
445 * | Register | BitsName |
446 * +======================+===================================+
447 * | LCR | STOP |
448 * +----------------------+-----------------------------------+
449 * \endrst
450 *
451 * @param UARTx UART instance
452 * @retval Returned value can be one of the following values:
453 * @arg @ref LL_UART_STOPBITS_1
454 * @arg @ref LL_UART_STOPBITS_1_5
455 * @arg @ref LL_UART_STOPBITS_2
456 */
457 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
458 {
459 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
460 }
461
462 /**
463 * @brief Configure Parity.
464 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
465 * When the parity control is enabled (Odd,Even,0,1), computed parity bit is inserted at the MSB position
466 * and parity is checked on the received data.
467 *
468 * \rst
469 * +----------------------+-----------------------------------+
470 * | Register | BitsName |
471 * +======================+===================================+
472 * | LCR | SP |
473 * +----------------------+-----------------------------------+
474 * \endrst
475 * LCR | EPS
476 * LCR | PEN
477 *
478 * @param UARTx UART instance
479 * @param parity This parameter can be one of the following values:
480 * @arg @ref LL_UART_PARITY_NONE
481 * @arg @ref LL_UART_PARITY_EVEN
482 * @arg @ref LL_UART_PARITY_ODD
483 * @arg @ref LL_UART_PARITY_SP0
484 * @arg @ref LL_UART_PARITY_SP1
485 * @retval None
486 */
487 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
488 {
489 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
490 }
491
492 /**
493 * @brief Return Parity configuration
494 *
495 * \rst
496 * +----------------------+-----------------------------------+
497 * | Register | BitsName |
498 * +======================+===================================+
499 * | LCR | SP |
500 * +----------------------+-----------------------------------+
501 * \endrst
502 * LCR | EPS
503 * LCR | PEN
504 *
505 * @param UARTx UART instance
506 * @retval Returned value can be one of the following values:
507 * @arg @ref LL_UART_PARITY_NONE
508 * @arg @ref LL_UART_PARITY_EVEN
509 * @arg @ref LL_UART_PARITY_ODD
510 * @arg @ref LL_UART_PARITY_SP0
511 * @arg @ref LL_UART_PARITY_SP1
512 */
513 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
514 {
515 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
516 }
517
518 /**
519 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
520 * @note This function call is equivalent to the following function call sequence :
521 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
522 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
523 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
524 *
525 * \rst
526 * +----------------------+-----------------------------------+
527 * | Register | BitsName |
528 * +======================+===================================+
529 * | LCR | PS |
530 * +----------------------+-----------------------------------+
531 * \endrst
532 * LCR | EPS
533 * LCR | PEN
534 * LCR | STOP
535 * LCR | DLS
536 *
537 * @param UARTx UART instance
538 * @param data_bits This parameter can be one of the following values:
539 * @arg @ref LL_UART_DATABITS_5B
540 * @arg @ref LL_UART_DATABITS_6B
541 * @arg @ref LL_UART_DATABITS_7B
542 * @arg @ref LL_UART_DATABITS_8B
543 * @param parity This parameter can be one of the following values:
544 * @arg @ref LL_UART_PARITY_NONE
545 * @arg @ref LL_UART_PARITY_EVEN
546 * @arg @ref LL_UART_PARITY_ODD
547 * @arg @ref LL_UART_PARITY_SP0
548 * @arg @ref LL_UART_PARITY_SP1
549 * @param stop_bits This parameter can be one of the following values:
550 * @arg @ref LL_UART_STOPBITS_1
551 * @arg @ref LL_UART_STOPBITS_1_5 (*)
552 * @arg @ref LL_UART_STOPBITS_2 (*)
553 *
554 * (*) STOPBITS_1_5 only valid when DataBits = 5
555 * (*) STOPBITS_2 is invalid when DataBits = 5
556 * @retval None
557 */
558 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
559 uint32_t data_bits,
560 uint32_t parity,
561 uint32_t stop_bits)
562 {
563 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
564 }
565
566 /**
567 * @brief Set UART RTS pin state to Active/Inactive
568 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
569 *
570 * \rst
571 * +----------------------+-----------------------------------+
572 * | Register | BitsName |
573 * +======================+===================================+
574 * | SRTS | SRTS |
575 * +----------------------+-----------------------------------+
576 * \endrst
577 * MCR | RTS
578 *
579 * @param UARTx UART instance
580 * @param pin_state This parameter can be one of the following values:
581 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
582 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
583 * @retval None
584 */
585 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
586 {
587 WRITE_REG(UARTx->SRTS, pin_state);
588 }
589
590 /**
591 * @brief Get UART RTS pin state
592 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
593 *
594 * \rst
595 * +----------------------+-----------------------------------+
596 * | Register | BitsName |
597 * +======================+===================================+
598 * | SRTS | SRTS |
599 * +----------------------+-----------------------------------+
600 * \endrst
601 * MCR | RTS
602 *
603 * @param UARTx UART instance
604 * @retval Returned value can be one of the following values:
605 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
606 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
607 */
608 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
609 {
610 return (uint32_t)(READ_REG(UARTx->SRTS));
611 }
612
613 /**
614 * @brief Get UART CTS pin state
615 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
616 *
617 * \rst
618 * +----------------------+-----------------------------------+
619 * | Register | BitsName |
620 * +======================+===================================+
621 * | MSR | CTS |
622 * +----------------------+-----------------------------------+
623 * \endrst
624 *
625 * @param UARTx UART instance
626 * @retval Returned value can be one of the following values:
627 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
628 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
629 */
630 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
631 {
632 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
633 }
634
635 /**
636 * @brief Indicate if CTS is changed since the last time the MSR was read
637 *
638 * \rst
639 * +----------------------+-----------------------------------+
640 * | Register | BitsName |
641 * +======================+===================================+
642 * | MSR | DCTS |
643 * +----------------------+-----------------------------------+
644 * \endrst
645 *
646 * @param UARTx UART instance
647 * @retval State of bit (1 or 0).
648 */
649 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
650 {
651 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
652 }
653
654 /**
655 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
656 * @note This function is used to Enable/Disable UART Auto Flow Control.
657 *
658 * \rst
659 * +----------------------+-----------------------------------+
660 * | Register | BitsName |
661 * +======================+===================================+
662 * | MCR | AFCE |
663 * +----------------------+-----------------------------------+
664 * \endrst
665 * MCR | RTS
666 *
667 * @param UARTx UART instance
668 * @param hw_flow_ctrl This parameter can be one of the following values:
669 * @arg @ref LL_UART_HWCONTROL_NONE
670 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
671 * @retval None
672 */
673 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
674 {
675 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
676 }
677
678 /**
679 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
680 *
681 * \rst
682 * +----------------------+-----------------------------------+
683 * | Register | BitsName |
684 * +======================+===================================+
685 * | MCR | AFCE |
686 * +----------------------+-----------------------------------+
687 * \endrst
688 * MCR | RTS
689 *
690 * @param UARTx UART instance
691 * @retval Returned value can be one of the following values:
692 * @arg @ref LL_UART_HWCONTROL_NONE
693 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
694 */
695 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
696 {
697 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
698 }
699
700 /**
701 * @brief Enable Break sending
702 *
703 * \rst
704 * +----------------------+-----------------------------------+
705 * | Register | BitsName |
706 * +======================+===================================+
707 * | LCR | BC |
708 * +----------------------+-----------------------------------+
709 * \endrst
710 *
711 * @param UARTx UART instance
712 * @retval None
713 */
714 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
715 {
716 WRITE_REG(UARTx->SBCR, 0x1U);
717 }
718
719 /**
720 * @brief Disable Break sending
721 *
722 * \rst
723 * +----------------------+-----------------------------------+
724 * | Register | BitsName |
725 * +======================+===================================+
726 * | LCR | BC |
727 * +----------------------+-----------------------------------+
728 * \endrst
729 *
730 * @param UARTx UART instance
731 * @retval None
732 */
733 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
734 {
735 WRITE_REG(UARTx->SBCR, 0x0U);
736 }
737
738 /**
739 * @brief Indicate if Break sending is enabled
740 *
741 * \rst
742 * +----------------------+-----------------------------------+
743 * | Register | BitsName |
744 * +======================+===================================+
745 * | LCR | BC |
746 * +----------------------+-----------------------------------+
747 * \endrst
748 *
749 * @param UARTx UART instance
750 * @retval State of bit (1 or 0).
751 */
752 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
753 {
754 return READ_REG(UARTx->SBCR);
755 }
756
757 /**
758 * @brief Enable TX FIFO and RX FIFO
759 *
760 * \rst
761 * +----------------------+-----------------------------------+
762 * | Register | BitsName |
763 * +======================+===================================+
764 * | SFE | SFE |
765 * +----------------------+-----------------------------------+
766 * \endrst
767 *
768 * @param UARTx UART instance
769 * @retval None
770 */
771 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
772 {
773 WRITE_REG(UARTx->SFE, 0x1U);
774 }
775
776 /**
777 * @brief Disable TX FIFO and RX FIFO
778 *
779 * \rst
780 * +----------------------+-----------------------------------+
781 * | Register | BitsName |
782 * +======================+===================================+
783 * | SFE | SFE |
784 * +----------------------+-----------------------------------+
785 * \endrst
786 *
787 * @param UARTx UART instance
788 * @retval None
789 */
790 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
791 {
792 WRITE_REG(UARTx->SFE, 0x0U);
793 }
794
795 /**
796 * @brief Indicate if TX FIFO and RX FIFO is enabled
797 *
798 * \rst
799 * +----------------------+-----------------------------------+
800 * | Register | BitsName |
801 * +======================+===================================+
802 * | SFE | SFE |
803 * +----------------------+-----------------------------------+
804 * \endrst
805 *
806 * @param UARTx UART instance
807 * @retval State of bit (1 or 0).
808 */
809 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
810 {
811 return READ_REG(UARTx->SFE);
812 }
813
814 /**
815 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
816 *
817 * \rst
818 * +----------------------+-----------------------------------+
819 * | Register | BitsName |
820 * +======================+===================================+
821 * | STET | STET |
822 * +----------------------+-----------------------------------+
823 * \endrst
824 *
825 * @param UARTx UART instance
826 * @param threshold This parameter can be one of the following values:
827 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
828 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
829 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
830 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
831 * @retval None
832 */
833 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
834 {
835 WRITE_REG(UARTx->STET, threshold);
836 }
837
838 /**
839 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
840 *
841 * \rst
842 * +----------------------+-----------------------------------+
843 * | Register | BitsName |
844 * +======================+===================================+
845 * | STET | STET |
846 * +----------------------+-----------------------------------+
847 * \endrst
848 *
849 * @param UARTx UART instance
850 * @retval Returned value can be one of the following values:
851 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
852 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
853 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
854 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
855 */
856 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
857 {
858 return (uint32_t)(READ_REG(UARTx->STET));
859 }
860
861 /**
862 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
863 *
864 * \rst
865 * +----------------------+-----------------------------------+
866 * | Register | BitsName |
867 * +======================+===================================+
868 * | SRT | SRT |
869 * +----------------------+-----------------------------------+
870 * \endrst
871 *
872 * @param UARTx UART instance
873 * @param threshold This parameter can be one of the following values:
874 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
875 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
876 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
877 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
878 * @retval None
879 */
880 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
881 {
882 WRITE_REG(UARTx->SRT, threshold);
883 }
884
885 /**
886 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
887 *
888 * \rst
889 * +----------------------+-----------------------------------+
890 * | Register | BitsName |
891 * +======================+===================================+
892 * | SRT | SRT |
893 * +----------------------+-----------------------------------+
894 * \endrst
895 *
896 * @param UARTx UART instance
897 * @retval Returned value can be one of the following values:
898 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
899 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
900 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
901 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
902 */
903 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
904 {
905 return (uint32_t)(READ_REG(UARTx->SRT));
906 }
907
908 /**
909 * @brief Get FIFO Transmission Level
910 *
911 * \rst
912 * +----------------------+-----------------------------------+
913 * | Register | BitsName |
914 * +======================+===================================+
915 * | TFL | TFL |
916 * +----------------------+-----------------------------------+
917 * \endrst
918 *
919 * @param UARTx UART instance
920 * @retval Returned value can be one of the following values:
921 */
922 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
923 {
924 return (uint32_t)(READ_REG(UARTx->TFL));
925 }
926
927 /**
928 * @brief Get FIFO reception Level
929 *
930 * \rst
931 * +----------------------+-----------------------------------+
932 * | Register | BitsName |
933 * +======================+===================================+
934 * | RFL | RFL |
935 * +----------------------+-----------------------------------+
936 * \endrst
937 *
938 * @param UARTx UART instance
939 * @retval Returned value can be one of the following values:
940 */
941 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
942 {
943 return (uint32_t)(READ_REG(UARTx->RFL));
944 }
945
946 /**
947 * @brief Flush Receive FIFO
948 *
949 * \rst
950 * +----------------------+-----------------------------------+
951 * | Register | BitsName |
952 * +======================+===================================+
953 * | SRR | RFR |
954 * +----------------------+-----------------------------------+
955 * \endrst
956 *
957 * @param UARTx UART instance
958 * @retval None
959 */
960 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
961 {
962 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
963 }
964
965 /**
966 * @brief Flush Transmit FIFO
967 *
968 * \rst
969 * +----------------------+-----------------------------------+
970 * | Register | BitsName |
971 * +======================+===================================+
972 * | SRR | XFR |
973 * +----------------------+-----------------------------------+
974 * \endrst
975 *
976 * @param UARTx UART instance
977 * @retval None
978 */
979 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
980 {
981 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
982 }
983
984 /**
985 * @brief Reset UART
986 * @note This function asynchronously resets the DW_apb_uart and synchronously
987 * removes the reset assertion. For a two clock implementation, both pclk
988 * and sclk domains will be reset.
989 *
990 * \rst
991 * +----------------------+-----------------------------------+
992 * | Register | BitsName |
993 * +======================+===================================+
994 * | SRR | UR |
995 * +----------------------+-----------------------------------+
996 * \endrst
997 *
998 * @param UARTx UART instance
999 * @retval None
1000 */
1001 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
1002 {
1003 WRITE_REG(UARTx->SRR, UART_SRR_UR);
1004 }
1005
1006 /** @} */
1007
1008 /** @defgroup UART_LL_EF_IT_Management IT_Management
1009 * @{
1010 */
1011
1012 /**
1013 * @brief Enable Modem Status Interrupt
1014 *
1015 * \rst
1016 * +----------------------+-----------------------------------+
1017 * | Register | BitsName |
1018 * +======================+===================================+
1019 * | IER | EDSSI |
1020 * +----------------------+-----------------------------------+
1021 * \endrst
1022 *
1023 * @param UARTx UART instance
1024 * @retval None
1025 */
1026 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
1027 {
1028 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1029 }
1030
1031 /**
1032 * @brief Enable Receiver Line Status Interrupt
1033 *
1034 * \rst
1035 * +----------------------+-----------------------------------+
1036 * | Register | BitsName |
1037 * +======================+===================================+
1038 * | IER | RLS |
1039 * +----------------------+-----------------------------------+
1040 * \endrst
1041 *
1042 * @param UARTx UART instance
1043 * @retval None
1044 */
1045 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
1046 {
1047 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1048 }
1049
1050 /**
1051 * @brief Enable Transmit Holding Register Empty Interrupt
1052 *
1053 * \rst
1054 * +----------------------+-----------------------------------+
1055 * | Register | BitsName |
1056 * +======================+===================================+
1057 * | IER | PTIME |
1058 * +----------------------+-----------------------------------+
1059 * \endrst
1060 * IER | ETBEI
1061 *
1062 * @param UARTx UART instance
1063 * @retval None
1064 */
1065 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
1066 {
1067 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1068 }
1069
1070 /**
1071 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
1072 *
1073 * \rst
1074 * +----------------------+-----------------------------------+
1075 * | Register | BitsName |
1076 * +======================+===================================+
1077 * | IER | ERBFI |
1078 * +----------------------+-----------------------------------+
1079 * \endrst
1080 *
1081 * @param UARTx UART instance
1082 * @retval None
1083 */
1084 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
1085 {
1086 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1087 }
1088
1089 /**
1090 * @brief Disable Modem Status Interrupt
1091 *
1092 * \rst
1093 * +----------------------+-----------------------------------+
1094 * | Register | BitsName |
1095 * +======================+===================================+
1096 * | IER | EDSSI |
1097 * +----------------------+-----------------------------------+
1098 * \endrst
1099 *
1100 * @param UARTx UART instance
1101 * @retval None
1102 */
1103 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
1104 {
1105 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1106 }
1107
1108 /**
1109 * @brief Disable Receiver Line Status Interrupt
1110 *
1111 * \rst
1112 * +----------------------+-----------------------------------+
1113 * | Register | BitsName |
1114 * +======================+===================================+
1115 * | IER | RLS |
1116 * +----------------------+-----------------------------------+
1117 * \endrst
1118 *
1119 * @param UARTx UART instance
1120 * @retval None
1121 */
1122 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
1123 {
1124 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1125 }
1126
1127 /**
1128 * @brief Disable Transmit Holding Register Empty Interrupt
1129 *
1130 * \rst
1131 * +----------------------+-----------------------------------+
1132 * | Register | BitsName |
1133 * +======================+===================================+
1134 * | IER | PTIME |
1135 * +----------------------+-----------------------------------+
1136 * \endrst
1137 * IER | ETBEI
1138 *
1139 * @param UARTx UART instance
1140 * @retval None
1141 */
1142 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
1143 {
1144 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1145 }
1146
1147 /**
1148 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1149 *
1150 * \rst
1151 * +----------------------+-----------------------------------+
1152 * | Register | BitsName |
1153 * +======================+===================================+
1154 * | IER | ERBFI |
1155 * +----------------------+-----------------------------------+
1156 * \endrst
1157 *
1158 * @param UARTx UART instance
1159 * @retval None
1160 */
1161 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1162 {
1163 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1164 }
1165
1166 /**
1167 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1168 *
1169 * \rst
1170 * +----------------------+-----------------------------------+
1171 * | Register | BitsName |
1172 * +======================+===================================+
1173 * | IER | EDSSI |
1174 * +----------------------+-----------------------------------+
1175 * \endrst
1176 *
1177 * @param UARTx UART instance
1178 * @retval State of bit (1 or 0).
1179 */
1180 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1181 {
1182 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1183 }
1184
1185 /**
1186 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1187 *
1188 * \rst
1189 * +----------------------+-----------------------------------+
1190 * | Register | BitsName |
1191 * +======================+===================================+
1192 * | IER | RLS |
1193 * +----------------------+-----------------------------------+
1194 * \endrst
1195 *
1196 * @param UARTx UART instance
1197 * @retval State of bit (1 or 0).
1198 */
1199 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1200 {
1201 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1202 }
1203
1204 /**
1205 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1206 *
1207 * \rst
1208 * +----------------------+-----------------------------------+
1209 * | Register | BitsName |
1210 * +======================+===================================+
1211 * | IER | PTIME |
1212 * +----------------------+-----------------------------------+
1213 * \endrst
1214 * IER | ETBEI
1215 *
1216 * @param UARTx UART instance
1217 * @retval State of bit (1 or 0).
1218 */
1219 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1220 {
1221 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1222 }
1223
1224 /**
1225 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1226 * is enabled or disabled.
1227 *
1228 * \rst
1229 * +----------------------+-----------------------------------+
1230 * | Register | BitsName |
1231 * +======================+===================================+
1232 * | IER | ERBFI |
1233 * +----------------------+-----------------------------------+
1234 * \endrst
1235 *
1236 * @param UARTx UART instance
1237 * @retval State of bit (1 or 0).
1238 */
1239 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1240 {
1241 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1242 }
1243
1244 /**
1245 * @brief Enable the specified UART Interrupt.
1246 *
1247 * \rst
1248 * +----------------------+-----------------------------------+
1249 * | Register | BitsName |
1250 * +======================+===================================+
1251 * | IER | EDSSI |
1252 * +----------------------+-----------------------------------+
1253 * \endrst
1254 * IER | ERLS
1255 * IER | PTIME
1256 * IER | ETBEI
1257 * IER | ERBFI
1258 *
1259 * @param UARTx UART instance
1260 * @param mask This parameter can be a combination of the following values:
1261 * @arg @ref LL_UART_IER_MS
1262 * @arg @ref LL_UART_IER_RLS
1263 * @arg @ref LL_UART_IER_THRE
1264 * @arg @ref LL_UART_IER_RDA
1265 * @retval None
1266 */
1267 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1268 {
1269 SET_BITS(UARTx->DLH_IER.IER, mask);
1270 }
1271
1272 /**
1273 * @brief Disable the specified UART Interrupt.
1274 *
1275 * \rst
1276 * +----------------------+-----------------------------------+
1277 * | Register | BitsName |
1278 * +======================+===================================+
1279 * | IER | EDSSI |
1280 * +----------------------+-----------------------------------+
1281 * \endrst
1282 * IER | ERLS
1283 * IER | PTIME
1284 * IER | ETBEI
1285 * IER | ERBFI
1286 *
1287 * @param UARTx UART instance
1288 * @param mask This parameter can be a combination of the following values:
1289 * @arg @ref LL_UART_IER_MS
1290 * @arg @ref LL_UART_IER_RLS
1291 * @arg @ref LL_UART_IER_THRE
1292 * @arg @ref LL_UART_IER_RDA
1293 * @retval None
1294 */
1295 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1296 {
1297 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1298 }
1299
1300 /**
1301 * @brief Check if the specified UART Interrupt is enabled or disabled.
1302 *
1303 * \rst
1304 * +----------------------+-----------------------------------+
1305 * | Register | BitsName |
1306 * +======================+===================================+
1307 * | IER | EDSSI |
1308 * +----------------------+-----------------------------------+
1309 * \endrst
1310 * IER | ERLS
1311 * IER | PTIME
1312 * IER | ETBEI
1313 * IER | ERBFI
1314 *
1315 * @param UARTx UART instance
1316 * @param mask This parameter can be a combination of the following values:
1317 * @arg @ref LL_UART_IER_MS
1318 * @arg @ref LL_UART_IER_RLS
1319 * @arg @ref LL_UART_IER_THRE
1320 * @arg @ref LL_UART_IER_RDA
1321 * @retval State of bit (1 or 0).
1322 */
1323 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1324 {
1325 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1326 }
1327
1328 /** @} */
1329
1330 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1331 * @{
1332 */
1333
1334 /**
1335 * @brief Get UART Receive Line Status Flag
1336 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1337 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1338 *
1339 * \rst
1340 * +----------------------+-----------------------------------+
1341 * | Register | BitsName |
1342 * +======================+===================================+
1343 * | LSR | OE |
1344 * +----------------------+-----------------------------------+
1345 * \endrst
1346 * LSR | PE
1347 * LSR | FE
1348 * LSR | BI
1349 * LSR | THRE
1350 * LSR | TEMT
1351 * LSR | RFE
1352 *
1353 * @param UARTx UART instance
1354 * @retval Returned value can be a combination of the following values:
1355 * @arg @ref LL_UART_LSR_OE
1356 * @arg @ref LL_UART_LSR_PE
1357 * @arg @ref LL_UART_LSR_FE
1358 * @arg @ref LL_UART_LSR_BI
1359 * @arg @ref LL_UART_LSR_THRE
1360 * @arg @ref LL_UART_LSR_TEMT
1361 * @arg @ref LL_UART_LSR_RFE
1362 */
1363 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1364 {
1365 return ((uint32_t)READ_REG(UARTx->LSR));
1366 }
1367
1368 /**
1369 * @brief Clear UART Receive Line Status Flag
1370 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1371 *
1372 * \rst
1373 * +----------------------+-----------------------------------+
1374 * | Register | BitsName |
1375 * +======================+===================================+
1376 * | LSR | OE |
1377 * +----------------------+-----------------------------------+
1378 * \endrst
1379 * LSR | PE
1380 * LSR | FE
1381 * LSR | BI
1382 * LSR | RFE
1383 *
1384 * @param UARTx UART instance
1385 * @retval None
1386 */
1387 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1388 {
1389 __IO uint32_t tmpreg;
1390 tmpreg = READ_REG(UARTx->LSR);
1391 (void) tmpreg;
1392 }
1393
1394 /**
1395 * @brief Check if the UART Receive FIFO Full Flag is set or not
1396 *
1397 * \rst
1398 * +----------------------+-----------------------------------+
1399 * | Register | BitsName |
1400 * +======================+===================================+
1401 * | USR | RFF |
1402 * +----------------------+-----------------------------------+
1403 * \endrst
1404 *
1405 * @param UARTx UART instance
1406 * @retval State of bit (1 or 0).
1407 */
1408 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1409 {
1410 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1411 }
1412
1413 /**
1414 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1415 *
1416 * \rst
1417 * +----------------------+-----------------------------------+
1418 * | Register | BitsName |
1419 * +======================+===================================+
1420 * | USR | RFNE |
1421 * +----------------------+-----------------------------------+
1422 * \endrst
1423 *
1424 * @param UARTx UART instance
1425 * @retval State of bit (1 or 0).
1426 */
1427 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1428 {
1429 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1430 }
1431
1432 /**
1433 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1434 *
1435 * \rst
1436 * +----------------------+-----------------------------------+
1437 * | Register | BitsName |
1438 * +======================+===================================+
1439 * | USR | TFE |
1440 * +----------------------+-----------------------------------+
1441 * \endrst
1442 *
1443 * @param UARTx UART instance
1444 * @retval State of bit (1 or 0).
1445 */
1446 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1447 {
1448 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1449 }
1450
1451 /**
1452 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1453 *
1454 * \rst
1455 * +----------------------+-----------------------------------+
1456 * | Register | BitsName |
1457 * +======================+===================================+
1458 * | USR | TFNF |
1459 * +----------------------+-----------------------------------+
1460 * \endrst
1461 *
1462 * @param UARTx UART instance
1463 * @retval State of bit (1 or 0).
1464 */
1465 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1466 {
1467 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1468 }
1469
1470 /**
1471 * @brief Get UART interrupt flags
1472 * @note The interrupt flags will be cleared after reading IIR.
1473 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1474 * and No Interrupt Pending Flag will be RESET, read IIR again can get the pended interrupt
1475 *
1476 * \rst
1477 * +----------------------+-----------------------------------+
1478 * | Register | BitsName |
1479 * +======================+===================================+
1480 * | IIR | IID |
1481 * +----------------------+-----------------------------------+
1482 * \endrst
1483 *
1484 * @param UARTx UART instance
1485 * @retval Returned value can be one or combination of the following values:
1486 * @arg @ref LL_UART_IIR_MS
1487 * @arg @ref LL_UART_IIR_NIP
1488 * @arg @ref LL_UART_IIR_THRE
1489 * @arg @ref LL_UART_IIR_RDA
1490 * @arg @ref LL_UART_IIR_RLS
1491 * @arg @ref LL_UART_IIR_CTO
1492 */
1493 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1494 {
1495 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1496 }
1497
1498 /** @} */
1499
1500 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1501 * @{
1502 */
1503
1504 /**
1505 * @brief Get the data register address used for DMA transfer
1506 * @note The address of data register RBR is the same as the address of THR.
1507 *
1508 * \rst
1509 * +----------------------+-----------------------------------+
1510 * | Register | BitsName |
1511 * +======================+===================================+
1512 * | RBR | RBR |
1513 * +----------------------+-----------------------------------+
1514 * \endrst
1515 * THR | THR
1516 *
1517 * @param UARTx UART instance
1518 * @retval Address of data register
1519 */
1520 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1521 {
1522 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1523 }
1524
1525 /** @} */
1526
1527 /** @defgroup UART_LL_EF_Data_Management Data_Management
1528 * @{
1529 */
1530
1531 /**
1532 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1533 *
1534 * \rst
1535 * +----------------------+-----------------------------------+
1536 * | Register | BitsName |
1537 * +======================+===================================+
1538 * | RBR | RBR |
1539 * +----------------------+-----------------------------------+
1540 * \endrst
1541 *
1542 * @param UARTx UART instance
1543 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1544 */
1545 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1546 {
1547 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1548 }
1549
1550 /**
1551 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1552 *
1553 * \rst
1554 * +----------------------+-----------------------------------+
1555 * | Register | BitsName |
1556 * +======================+===================================+
1557 * | THR | THR |
1558 * +----------------------+-----------------------------------+
1559 * \endrst
1560 *
1561 * @param UARTx UART instance
1562 * @param value between Min_Data=0x00 and Max_Data=0xFF
1563 * @retval None
1564 */
1565 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1566 {
1567 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1568 }
1569
1570 /** @} */
1571
1572 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1573 * @{
1574 */
1575
1576 /**
1577 * @brief De-initialize UART registers (Registers restored to their default values).
1578 * @param UARTx UART instance
1579 * @retval An error_status_t enumeration value:
1580 * - SUCCESS: UART registers are de-initialized
1581 * - ERROR: UART registers are not de-initialized
1582 */
1583 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1584
1585 /**
1586 * @brief Initialize UART registers according to the specified
1587 * parameters in p_uart_init.
1588 * @param UARTx UART instance
1589 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1590 * information for the specified UART peripheral.
1591 * @retval An error_status_t enumeration value:
1592 * - SUCCESS: UART registers are initialized according to p_uart_init content
1593 * - ERROR: Problem occurred during UART Registers initialization
1594 */
1595 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1596
1597 /**
1598 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1599 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1600 * whose fields will be set to default values.
1601 * @retval None
1602 */
1603 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1604
1605 /** @} */
1606
1607 /** @} */
1608
1609 #endif /* UART0 || UART1 */
1610
1611 #ifdef __cplusplus
1612 }
1613 #endif
1614
1615 #endif /* __GR55xx_LL_UART_H__ */
1616
1617 /** @} */
1618
1619 /** @} */
1620
1621 /** @} */
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1427
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1180
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: gr55xx_ll_uart.h:585
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: gr55xx_ll_uart.h:752
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:1142
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: gr55xx_ll_uart.h:435
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: gr55xx_ll_uart.h:321
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: gr55xx_ll_uart.h:809
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: gr55xx_ll_uart.h:1065
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_uart.h:1520
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:1026
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: gr55xx_ll_uart.h:487
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1161
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: gr55xx_ll_uart.h:285
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_uart.h:922
_ll_uart_init_t
LL UART init Structure definition.
Definition: gr55xx_ll_uart.h:77
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:903
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: gr55xx_ll_uart.h:608
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:1045
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: gr55xx_ll_uart.h:733
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1219
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1408
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1267
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1363
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: gr55xx_ll_uart.h:714
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:790
ll_uart_init
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: gr55xx_ll_uart.h:409
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: gr55xx_ll_uart.h:630
_ll_uart_init_t::data_bits
uint32_t data_bits
Specifies the number of data bits transmitted or received in a frame.
Definition: gr55xx_ll_uart.h:82
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1199
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: gr55xx_ll_uart.h:1387
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: gr55xx_ll_uart.h:1084
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: gr55xx_ll_uart.h:349
_ll_uart_init_t::baud_rate
uint32_t baud_rate
This field defines expected Usart communication baud rate.
Definition: gr55xx_ll_uart.h:78
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: gr55xx_ll_uart.h:1239
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1565
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: gr55xx_ll_uart.h:1295
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:695
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: gr55xx_ll_uart.h:673
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:856
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: gr55xx_ll_uart.h:1103
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_uart.h:880
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: gr55xx_ll_uart.h:979
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: gr55xx_ll_uart.h:1545
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: gr55xx_ll_uart.h:513
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: gr55xx_ll_uart.h:1001
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: gr55xx_ll_uart.h:1122
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Specifies the number of stop bits transmitted.
Definition: gr55xx_ll_uart.h:87
_ll_uart_init_t::parity
uint32_t parity
Specifies the parity mode.
Definition: gr55xx_ll_uart.h:92
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: gr55xx_ll_uart.h:941
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Specifies whether the hardware flow control mode is enabled or disabled.
Definition: gr55xx_ll_uart.h:97
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: gr55xx_ll_uart.h:1446
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: gr55xx_ll_uart.h:558
ll_uart_deinit
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: gr55xx_ll_uart.h:771
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_uart.h:833
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: gr55xx_ll_uart.h:457
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: gr55xx_ll_uart.h:649
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: gr55xx_ll_uart.h:1323
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: gr55xx_ll_uart.h:1465
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: gr55xx_ll_uart.h:960
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: gr55xx_ll_uart.h:276
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: gr55xx_ll_uart.h:386
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: gr55xx_ll_uart.h:1493