gr55xx_ll_pwr.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
73 * @{
74 */
75
76 /** @defgroup PWR_LL_PC_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
77 * @{
78 */
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos) /**< External wakeup level type */
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos) /**< External wakeup level invert */
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos) /**< External wakeup source enable */
82 /** @} */
83
84 /** @} */
85
86 /* Private macros ------------------------------------------------------------*/
87 /** @defgroup PWR_LL_Private_Macro PWR Private Macros
88 * @{
89 */
90
91 /** @defgroup PWR_LL_PM_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
92 * @{
93 */
94
95 /**
96 * @brief PWR_LL_PM_GET_MEM_PWR_MSK PWR Get Memory Power Value Mask
97 */
98 #define __LL_PWR_GET_MEM_PWR_MASK(__POWER__) (((__POWER__) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((__POWER__) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100
101 /** @} */
102
103 /** @} */
104
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
108 * @{
109 */
110
111 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
112 * @{
113 */
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP /**< External wakeup: AON_GPIO */
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER /**< AON Timer wakeup */
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE /**< BLE wakeup */
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR /**< Calendar wakeup */
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE /**< PMU Bod falling edge wakeup */
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP /**< Msio comparator wakeup */
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL /**< All wakeup sources mask */
121 /** @} */
122
123
124 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
125 * @{
126 */
127 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN /**< BLE Timer wakeup event */
128 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER /**< AON Timer wakeup event */
129 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP /**< External wakeup event: AON_GPIO */
130 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE /**< PMU Bod wakeup event */
131 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP /**< Msio comparator wakeup event */
132 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT /**< AON WDT wakeup event */
133 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM /**< Calendar wakeup event */
134 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
135 AON_SLP_EVENT_TIMER | \
136 AON_SLP_EVENT_EXTWKUP | \
137 AON_SLP_EVENT_PMU_BOD_FEDGE | \
138 AON_SLP_EVENT_PMU_MSIO_COMP | \
139 AON_SLP_EVENT_WDT_REBOOT | \
140 AON_SLP_EVENT_CALENDAR_TIMER_ALARM) /**< All event mask */
141 /** @} */
142
143 /** @defgroup PWR_LL_EC_EXTWAKEUP_PIN External Wakeup Pins
144 * @{
145 */
146 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U) /**< WKUP pin 0 : AON_GPIO_PIN0 */
147 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U) /**< WKUP pin 1 : AON_GPIO_PIN1 */
148 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U) /**< WKUP pin 2 : AON_GPIO_PIN2 */
149 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U) /**< WKUP pin 3 : AON_GPIO_PIN3 */
150 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U) /**< WKUP pin 4 : AON_GPIO_PIN4 */
151 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U) /**< WKUP pin 5 : AON_GPIO_PIN5 */
152 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U) /**< WKUP pin 6 : AON_GPIO_PIN6 */
153 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U) /**< WKUP pin 7 : AON_GPIO_PIN7 */
154 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU) /**< WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7 */
155 /** @} */
156
157 /** @defgroup PWR_LL_EC_EXTWAKEUP_TYPE External Wakeup Type
158 * @{
159 */
160 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Low level wakeup */
161 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< High level wakeup */
162 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U) /**< Rising edge wakeup */
163 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Falling edge wakeup */
164 /** @} */
165
166 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
167 * @{
168 */
169 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK /**< Reserved command 0 */
170 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON /**< Reserved command 1 */
171 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD /**< Load sleep timer command */
172 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP /**< Enter Deep Sleep Mode command */
173 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF /**< Reserved command 2 */
174 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK /**< Select external clock (xo_32KHz) command */
175 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK /**< Select RING OSC clock command */
176 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK /**< Select RTC clock command */
177 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK /**< Select RING OSC clock command */
178 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG /**< Load memory sleep settings command */
179 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG /**< Load memory wakeup settings command */
180 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI /**< Force dpad_le high */
181 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO /**< Force dpad_le low */
182 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 /**< Enable sleep timer mode 0 command */
183 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 /**< Enable sleep timer mode 1 command */
184 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 /**< Enable sleep timer mode 2 command */
185 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 /**< Enable sleep timer mode 3 command */
186 /** @} */
187
188
189 /** @} */
190
191 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
192 * @{
193 */
194 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
195 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
196 /** @} */
197
198 /** @defgroup PWR_LL_EC_TIMER_READ_SEL Timer Read Select
199 * @{
200 */
201 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER /**< Calendar timer */
202 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT /**< AON watchdog timer */
203 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER /**< Sleep timer */
204 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM /**< Calendar alarm */
205 /** @} */
206
207 /** @} */
208
209
210 /* Exported macro ------------------------------------------------------------*/
211 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
212 * @{
213 */
214
215 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
216 * @{
217 */
218
219 /**
220 * @brief Write a value in PWR register
221 * @param __REG__ Register to be written
222 * @param __VALUE__ Value to be written in the register
223 * @retval None
224 */
225 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
226
227 /**
228 * @brief Read a value in PWR register
229 * @param __REG__ Register to be read
230 * @retval Register value
231 */
232 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
233 /** @} */
234
235 /* Exported functions --------------------------------------------------------*/
236 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
237 * @{
238 */
239
240 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
241 * @{
242 */
243
244 /**
245 * @brief Set the DeepSleep WakeUp Condition
246 *
247 * \rst
248 * +----------------------+-----------------------------------+
249 * | Register | BitsName |
250 * +======================+===================================+
251 * | EXT_WKUP_CTL | WAKE_UP_SEL |
252 * +----------------------+-----------------------------------+
253 * \endrst
254 *
255 * @param condition This parameter can be one of the following values:
256 * @arg @ref LL_PWR_WKUP_COND_EXT
257 * @arg @ref LL_PWR_WKUP_COND_TIMER
258 * @arg @ref LL_PWR_WKUP_COND_BLE
259 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
260 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
261 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
262 * @arg @ref LL_PWR_WKUP_COND_ALL
263 * @retval None
264 */
265 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
266 {
267 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
268 }
269
270 /**
271 * @brief Get the Selected DeepSleep WakeUp Condition
272 *
273 * \rst
274 * +----------------------+-----------------------------------+
275 * | Register | BitsName |
276 * +======================+===================================+
277 * | EXT_WKUP_CTL | WAKE_UP_SEL |
278 * +----------------------+-----------------------------------+
279 * \endrst
280 *
281 * @retval Returned value can be one of the following values:
282 * @arg @ref LL_PWR_WKUP_COND_EXT
283 * @arg @ref LL_PWR_WKUP_COND_TIMER
284 * @arg @ref LL_PWR_WKUP_COND_BLE
285 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
286 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
287 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
288 * @arg @ref LL_PWR_WKUP_COND_ALL
289 */
290 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
291 {
292 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
293 }
294
295 /**
296 * @brief Get the Event that triggered the DeepSleep WakeUp.
297 *
298 * \rst
299 * +----------------------+-----------------------------------+
300 * | Register | BitsName |
301 * +======================+===================================+
302 * | SLP_EVENT | SMCOSCEN_EVENT |
303 * +----------------------+-----------------------------------+
304 * \endrst
305 * SLP_EVENT | TIMER_EVENT
306 * SLP_EVENT | EXT_WKUP_EVENT
307 * SLP_EVENT | WATCHDOG_EVENT
308 *
309 * @retval Returned value can be combination of the following values:
310 * @arg @ref LL_PWR_WKUP_EVENT_BLE
311 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
312 * @arg @ref LL_PWR_WKUP_EVENT_EXT
313 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
314 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
315 * @arg @ref LL_PWR_WKUP_EVENT_WDT
316 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
317 */
318 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
319 {
320 return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
321 }
322
323 /**
324 * @brief Enable the External WakeUp PINx functionality
325 *
326 * \rst
327 * +----------------------+-----------------------------------+
328 * | Register | BitsName |
329 * +======================+===================================+
330 * | EXT_WKUP_CTL | MASK |
331 * +----------------------+-----------------------------------+
332 * \endrst
333 *
334 * @param wakeup_pin This parameter can be a combination of the following values:
335 * @arg @ref LL_PWR_EXTWKUP_PIN0
336 * @arg @ref LL_PWR_EXTWKUP_PIN1
337 * @arg @ref LL_PWR_EXTWKUP_PIN2
338 * @arg @ref LL_PWR_EXTWKUP_PIN3
339 * @arg @ref LL_PWR_EXTWKUP_PIN4
340 * @arg @ref LL_PWR_EXTWKUP_PIN5
341 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
342 * @retval None
343 */
344 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
345 {
346 GLOBAL_EXCEPTION_DISABLE();
347 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
348 GLOBAL_EXCEPTION_ENABLE();
349 }
350
351 /**
352 * @brief Disable the External WakeUp PINx functionality
353 *
354 * \rst
355 * +----------------------+-----------------------------------+
356 * | Register | BitsName |
357 * +======================+===================================+
358 * | EXT_WKUP_CTL | MASK |
359 * +----------------------+-----------------------------------+
360 * \endrst
361 *
362 * @param wakeup_pin This parameter can be a combination of the following values:
363 * @arg @ref LL_PWR_EXTWKUP_PIN0
364 * @arg @ref LL_PWR_EXTWKUP_PIN1
365 * @arg @ref LL_PWR_EXTWKUP_PIN2
366 * @arg @ref LL_PWR_EXTWKUP_PIN3
367 * @arg @ref LL_PWR_EXTWKUP_PIN4
368 * @arg @ref LL_PWR_EXTWKUP_PIN5
369 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
370 * @retval None
371 */
372 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
373 {
374 GLOBAL_EXCEPTION_DISABLE();
375 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
376 GLOBAL_EXCEPTION_ENABLE();
377 }
378
379 /**
380 * @brief Check if the External WakeUp PINx functionality is enabled
381 *
382 * \rst
383 * +----------------------+-----------------------------------+
384 * | Register | BitsName |
385 * +======================+===================================+
386 * | EXT_WKUP_CTL | MASK |
387 * +----------------------+-----------------------------------+
388 * \endrst
389 *
390 * @param wakeup_pin This parameter can be a combination of the following values:
391 * @arg @ref LL_PWR_EXTWKUP_PIN0
392 * @arg @ref LL_PWR_EXTWKUP_PIN1
393 * @arg @ref LL_PWR_EXTWKUP_PIN2
394 * @arg @ref LL_PWR_EXTWKUP_PIN3
395 * @arg @ref LL_PWR_EXTWKUP_PIN4
396 * @arg @ref LL_PWR_EXTWKUP_PIN5
397 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
398 * @retval State of bit (1 or 0).
399 */
400 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
401 {
402 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
403 }
404
405 /**
406 * @brief Set the WakeUp Type of External WakeUp PINx.
407 *
408 * \rst
409 * +----------------------+-----------------------------------+
410 * | Register | BitsName |
411 * +======================+===================================+
412 * | EXT_WKUP_CTL | INVERT |
413 * +----------------------+-----------------------------------+
414 * \endrst
415 * EXT_WKUP_CTL | TYPE
416 *
417 * @param wakeup_pin This parameter can be a combination of the following values:
418 * @arg @ref LL_PWR_EXTWKUP_PIN0
419 * @arg @ref LL_PWR_EXTWKUP_PIN1
420 * @arg @ref LL_PWR_EXTWKUP_PIN2
421 * @arg @ref LL_PWR_EXTWKUP_PIN3
422 * @arg @ref LL_PWR_EXTWKUP_PIN4
423 * @arg @ref LL_PWR_EXTWKUP_PIN5
424 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
425 * @param wakeup_type This parameter can be one of the following values:
426 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
427 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
428 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
429 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
430 * @retval None
431 */
432 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
433 {
434 uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
435 uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
436 GLOBAL_EXCEPTION_DISABLE();
437 MODIFY_REG(AON->EXT_WKUP_CTL, (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos), invert | type);
438 GLOBAL_EXCEPTION_ENABLE();
439 }
440
441 /**
442 * @brief Get the WakeUp Type of External WakeUp PINx.
443 * @note Warning: only one pin can be passed as parameter.
444 *
445 * \rst
446 * +----------------------+-----------------------------------+
447 * | Register | BitsName |
448 * +======================+===================================+
449 * | EXT_WKUP_CTL | INVERT |
450 * +----------------------+-----------------------------------+
451 * \endrst
452 * EXT_WKUP_CTL | TYPE
453 *
454 * @param wakeup_pin This parameter can be one of the following values:
455 * @arg @ref LL_PWR_EXTWKUP_PIN0
456 * @arg @ref LL_PWR_EXTWKUP_PIN1
457 * @arg @ref LL_PWR_EXTWKUP_PIN2
458 * @arg @ref LL_PWR_EXTWKUP_PIN3
459 * @arg @ref LL_PWR_EXTWKUP_PIN4
460 * @arg @ref LL_PWR_EXTWKUP_PIN5
461 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
462 * @retval Returned value can be one of the following values:
463 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
464 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
465 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
466 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
467 */
468 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
469 {
470 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> POSITION_VAL(wakeup_pin)));
471 }
472
473 /**
474 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
475 * @note After the value was set, use @arg @ref LL_PWR_CMD_32_TIMER_LD command to
476 * load the configuration into Power State Controller.
477 *
478 * \rst
479 * +----------------------+-----------------------------------+
480 * | Register | BitsName |
481 * +======================+===================================+
482 * | TIMER_VALUE | PWR_CTL_TIMER_32B |
483 * +----------------------+-----------------------------------+
484 * \endrst
485 *
486 * @param value 32 bits count value loaded into the t32bit_timer
487 * @retval None
488 */
489 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
490 {
491 WRITE_REG(AON->TIMER_VALUE, value);
492 }
493
494 /**
495 * @brief Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
496 *
497 * \rst
498 * +----------------------+-----------------------------------+
499 * | Register | BitsName |
500 * +======================+===================================+
501 * | TIMER_VALUE | PWR_CTL_TIMER_32B |
502 * +----------------------+-----------------------------------+
503 * \endrst
504 *
505 * @retval 32 bit AON Timer Count Value
506 */
507 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
508 {
509 return READ_REG(AON->TIMER_VALUE);
510 }
511
512 /**
513 * @brief Enable the SMC WakeUp Request.
514 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
515 *
516 * \rst
517 * +----------------------+-----------------------------------+
518 * | Register | BitsName |
519 * +======================+===================================+
520 * | PWR_RET01 | SMC_WAKEUP_REQ |
521 * +----------------------+-----------------------------------+
522 * \endrst
523 *
524 * @retval None
525 */
526 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
527 {
528 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
529 }
530
531 /**
532 * @brief Disable the SMC WakeUp Request.
533 * @note This function is used to clear SMC WakeUp Request.
534 *
535 * \rst
536 * +----------------------+-----------------------------------+
537 * | Register | BitsName |
538 * +======================+===================================+
539 * | PWR_RET01 | SMC_WAKEUP_REQ |
540 * +----------------------+-----------------------------------+
541 * \endrst
542 *
543 * @retval None
544 */
545 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
546 {
547 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
548 }
549
550 /**
551 * @brief Check if the SMC WakeUp Request was enabled or disabled.
552 *
553 * \rst
554 * +----------------------+-----------------------------------+
555 * | Register | BitsName |
556 * +======================+===================================+
557 * | PWR_RET01 | SMC_WAKEUP_REQ |
558 * +----------------------+-----------------------------------+
559 * \endrst
560 *
561 * @retval State of bit (1 or 0).
562 */
563 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
564 {
565 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
566 }
567
568 /**
569 * @brief Set the DPAD LE value during sleep and after wake up.
570 *
571 * \rst
572 * +----------------------+-----------------------------------+
573 * | Register | BitsName |
574 * +======================+===================================+
575 * | MEM_N_SLP_CTL | DPAD_LE_SLP_VAL |
576 * +----------------------+-----------------------------------+
577 * | MEM_N_SLP_CTL | DPAD_LE_WKUP_VAL |
578 * +----------------------+-----------------------------------+
579 * \endrst
580 *
581 *
582 * @param sleep This parameter can be one of the following values:
583 * @arg @ref LL_PWR_DPAD_LE_OFF
584 * @arg @ref LL_PWR_DPAD_LE_ON
585 * @param wakeup This parameter can be one of the following values:
586 * @arg @ref LL_PWR_DPAD_LE_OFF
587 * @arg @ref LL_PWR_DPAD_LE_ON
588 * @retval None
589 */
590 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
591 {
592 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
593 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
594 }
595
596 /**
597 * @brief Request to excute the Power State Controller Command.
598 * @note The PSC command can only be excuted when Power State Controller is not in busy state.
599 * Use @ref ll_pwr_is_active_flag_psc_cmd_busy() to check the busy status, and make sure
600 * the last command has been finished.
601 *
602 * \rst
603 * +----------------------+-----------------------------------+
604 * | Register | BitsName |
605 * +======================+===================================+
606 * | PSC_CMD_OPC | OPCODE |
607 * +----------------------+-----------------------------------+
608 * | PSC_CMD | MCU_PWR_REQ |
609 * +----------------------+-----------------------------------+
610 * \endrst
611
612 *
613 * @param command This parameter can be one of the following values:
614 * @arg @ref LL_PWR_CMD_LOOPBACK
615 * @arg @ref LL_PWR_CMD_EF_DIR_ON
616 * @arg @ref LL_PWR_CMD_32_TIMER_LD
617 * @arg @ref LL_PWR_CMD_DEEP_SLEEP
618 * @arg @ref LL_PWR_CMD_EF_DIR_OFF
619 * @arg @ref LL_PWR_CMD_EXT_CLK
620 * @arg @ref LL_PWR_CMD_RNG_CLK
621 * @arg @ref LL_PWR_CMD_RTC_CLK
622 * @arg @ref LL_PWR_CMD_LD_MEM_SLP_CFG
623 * @arg @ref LL_PWR_CMD_LD_MEM_WKUP_CFG
624 * @arg @ref LL_PWR_CMD_DPAD_LE_HI (*)
625 * @arg @ref LL_PWR_CMD_DPAD_LE_LO (*)
626 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_NORMAL (*)
627 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_SINGLE (*)
628 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_RELOAD (*)
629 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_DISABLE (*)
630 *
631 * (*) Not available in A0 and B0
632 *
633 * @retval None
634 */
635 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
636 {
637 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
638 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
639 }
640
641 /** @} */
642
643 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
644 * @{
645 */
646
647 /**
648 * @brief Enable the Communication Timer Reset.
649 * @note Comm timer can be reset when all ble connection were disconnected and
650 * MCU was ready to enter into deepsleep mode.
651 *
652 * \rst
653 * +----------------------+-----------------------------------+
654 * | Register | BitsName |
655 * +======================+===================================+
656 * | PWR_RET01 | COMM_TIMER_RST_N |
657 * +----------------------+-----------------------------------+
658 * \endrst
659 *
660 * @retval None
661 */
662 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
663 {
664 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
665 }
666
667 /**
668 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
669 * @note After powered up, Comm Timer need to enter into running mode.
670 *
671 * \rst
672 * +----------------------+-----------------------------------+
673 * | Register | BitsName |
674 * +======================+===================================+
675 * | PWR_RET01 | COMM_TIMER_RST_N |
676 * +----------------------+-----------------------------------+
677 * \endrst
678 *
679 * @retval None
680 */
681 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
682 {
683 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
684 }
685
686 /**
687 * @brief Check if the Communication Timer Reset was enabled or disabled.
688 *
689 * \rst
690 * +----------------------+-----------------------------------+
691 * | Register | BitsName |
692 * +======================+===================================+
693 * | PWR_RET01 | COMM_TIMER_RST_N |
694 * +----------------------+-----------------------------------+
695 * \endrst
696 *
697 * @retval State of bit (1 or 0).
698 */
699 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
700 {
701 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
702 }
703
704 /**
705 * @brief Enable the Communication Core Reset.
706 * @note Comm Core can be reset when all ble connection were disconnected and
707 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
708 * is 0, the ble is held in reset.
709 *
710 * \rst
711 * +----------------------+-----------------------------------+
712 * | Register | BitsName |
713 * +======================+===================================+
714 * | PWR_RET01 | COMM_CORE_RST_N |
715 * +----------------------+-----------------------------------+
716 * \endrst
717 *
718 * @retval None
719 */
720 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
721 {
722 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
723 }
724
725 /**
726 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
727 * @note After powered up, Comm Core need to enter into running mode.
728 *
729 * \rst
730 * +----------------------+-----------------------------------+
731 * | Register | BitsName |
732 * +======================+===================================+
733 * | PWR_RET01 | COMM_CORE_RST_N |
734 * +----------------------+-----------------------------------+
735 * \endrst
736 *
737 * @retval None
738 */
739 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
740 {
741 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
742 }
743
744 /**
745 * @brief Check if the Communication Core Reset was enabled or disabled.
746 *
747 * \rst
748 * +----------------------+-----------------------------------+
749 * | Register | BitsName |
750 * +======================+===================================+
751 * | PWR_RET01 | COMM_CORE_RST_N |
752 * +----------------------+-----------------------------------+
753 * \endrst
754 *
755 * @retval State of bit (1 or 0).
756 */
757 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
758 {
759 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
760 }
761
762 /**
763 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
764 *
765 * \rst
766 * +----------------------+-----------------------------------+
767 * | Register | BitsName |
768 * +======================+===================================+
769 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
770 * +----------------------+-----------------------------------+
771 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
772 * +----------------------+-----------------------------------+
773 * \endrst
774
775 *
776 * @retval None
777 */
778 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
779 {
780 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
781 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
782 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
783 }
784
785 /**
786 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
787 *
788 * \rst
789 * +----------------------+-----------------------------------+
790 * | Register | BitsName |
791 * +======================+===================================+
792 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
793 * +----------------------+-----------------------------------+
794 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
795 * +----------------------+-----------------------------------+
796 * \endrst
797
798 *
799 * @retval None
800 */
801 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
802 {
803 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
804 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
805 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
806 }
807
808 /**
809 * @brief Check if the Communication Timer Power was enabled or disabled.
810 *
811 * \rst
812 * +----------------------+-----------------------------------+
813 * | Register | BitsName |
814 * +======================+===================================+
815 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER |
816 * +----------------------+-----------------------------------+
817 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER |
818 * +----------------------+-----------------------------------+
819 * \endrst
820 *
821 * @retval State of bit (1 or 0).
822 */
823 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
824 {
825 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
826 }
827
828 /**
829 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
830 *
831 * \rst
832 * +----------------------+-----------------------------------+
833 * | Register | BitsName |
834 * +======================+===================================+
835 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
836 * +----------------------+-----------------------------------+
837 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
838 * +----------------------+-----------------------------------+
839 * \endrst
840 *
841 * @retval None
842 */
843 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
844 {
845 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
846 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
847 }
848
849 /**
850 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
851 *
852 * \rst
853 * +----------------------+-----------------------------------+
854 * | Register | BitsName |
855 * +======================+===================================+
856 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
857 * +----------------------+-----------------------------------+
858 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
859 * +----------------------+-----------------------------------+
860 * \endrst
861 *
862 * @retval None
863 */
864 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
865 {
866 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
867 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
868 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
869 }
870
871 /**
872 * @brief Check if the Communication Core Power was enabled or disabled.
873 *
874 * \rst
875 * +----------------------+-----------------------------------+
876 * | Register | BitsName |
877 * +======================+===================================+
878 * | CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE |
879 * +----------------------+-----------------------------------+
880 * | CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE |
881 * +----------------------+-----------------------------------+
882 * \endrst
883 *
884 *
885 * @retval None
886 */
887 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
888 {
889 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
890 }
891
892 /**
893 * @brief Select which timer value to read
894 *
895 * \rst
896 * +----------------------+-----------------------------------+
897 * | Register | BitsName |
898 * +======================+===================================+
899 * | PAD_CTL1 | TIMER_READ_SEL |
900 * +----------------------+-----------------------------------+
901 * \endrst
902 *
903 * @param select This parameter can be one of the following values:
904 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
905 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
906 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
907 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
908 * @retval None
909 */
910 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
911 {
912 GLOBAL_EXCEPTION_DISABLE();
913 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
914 GLOBAL_EXCEPTION_ENABLE();
915 }
916
917 /**
918 * @brief Get which timer value was selected to read.
919 *
920 * \rst
921 * +----------------------+-----------------------------------+
922 * | Register | BitsName |
923 * +======================+===================================+
924 * | PAD_CTL1 | TIMER_READ_SEL |
925 * +----------------------+-----------------------------------+
926 * \endrst
927 *
928 * @retval Returned value can be one of the following values:
929 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
930 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
931 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
932 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
933 */
934 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
935 {
936 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
937 }
938
939 /**
940 * @brief Get current timer value based on the selection.
941 * @note Please read multiple times until get a stable value.
942 *
943 * \rst
944 * +----------------------+-----------------------------------+
945 * | Register | BitsName |
946 * +======================+===================================+
947 * | PAD_CTL1 | TIMER_READ_SEL |
948 * +----------------------+-----------------------------------+
949 * \endrst
950 *
951 * @retval Returned value can be one of the following values:
952 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
953 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
954 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
955 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
956 */
957 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
958 {
959 return ((uint32_t)READ_REG(AON->TIMER_VAL));
960 }
961
962 /**
963 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
964 *
965 * \rst
966 * +----------------------+-----------------------------------+
967 * | Register | BitsName |
968 * +======================+===================================+
969 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
970 * +----------------------+-----------------------------------+
971 * \endrst
972 *
973 * @retval None
974 */
975 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
976 {
977 GLOBAL_EXCEPTION_DISABLE();
978 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
979 GLOBAL_EXCEPTION_ENABLE();
980 }
981
982
983 /**
984 * @brief Disable high frequency crystal oscillator sleep mode.
985 * @note Switch OSC from sleep mode into normal active mode.
986 *
987 * \rst
988 * +----------------------+-----------------------------------+
989 * | Register | BitsName |
990 * +======================+===================================+
991 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
992 * +----------------------+-----------------------------------+
993 * \endrst
994 *
995 * @retval None
996 */
997 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
998 {
999 GLOBAL_EXCEPTION_DISABLE();
1000 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
1001 GLOBAL_EXCEPTION_ENABLE();
1002 }
1003
1004 /**
1005 * @brief Check if the OSC sleep mode was enabled or disabled.
1006 *
1007 * \rst
1008 * +----------------------+-----------------------------------+
1009 * | Register | BitsName |
1010 * +======================+===================================+
1011 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN |
1012 * +----------------------+-----------------------------------+
1013 * \endrst
1014 *
1015 * @retval State of bit (1 or 0).
1016 */
1017 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
1018 {
1019 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
1020 }
1021
1022 /**
1023 * @brief Enable Radio sleep mode, and disable Radio module.
1024 *
1025 * \rst
1026 * +----------------------+-----------------------------------+
1027 * | Register | BitsName |
1028 * +======================+===================================+
1029 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1030 * +----------------------+-----------------------------------+
1031 * \endrst
1032 *
1033 * @retval None
1034 */
1035 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
1036 {
1037 GLOBAL_EXCEPTION_DISABLE();
1038 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
1039 GLOBAL_EXCEPTION_ENABLE();
1040 }
1041
1042 /**
1043 * @brief Disable Radio sleep mode.
1044 * @note Switch Radio from sleep mode into normal active mode.
1045 *
1046 * \rst
1047 * +----------------------+-----------------------------------+
1048 * | Register | BitsName |
1049 * +======================+===================================+
1050 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1051 * +----------------------+-----------------------------------+
1052 * \endrst
1053 *
1054 * @retval None
1055 */
1056 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
1057 {
1058 GLOBAL_EXCEPTION_DISABLE();
1059 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
1060 GLOBAL_EXCEPTION_ENABLE();
1061 }
1062
1063 /**
1064 * @brief Check if the Radio sleep mode was enabled or disabled.
1065 *
1066 * \rst
1067 * +----------------------+-----------------------------------+
1068 * | Register | BitsName |
1069 * +======================+===================================+
1070 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN |
1071 * +----------------------+-----------------------------------+
1072 * \endrst
1073 *
1074 * @retval State of bit (1 or 0).
1075 */
1076 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
1077 {
1078 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
1079 }
1080
1081 /**
1082 * @brief Enable Communication Core Deep Sleep Mode.
1083 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
1084 *
1085 * \rst
1086 * +----------------------+-----------------------------------+
1087 * | Register | BitsName |
1088 * +======================+===================================+
1089 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1090 * +----------------------+-----------------------------------+
1091 * \endrst
1092 *
1093 * @retval None
1094 */
1095 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
1096 {
1097 GLOBAL_EXCEPTION_DISABLE();
1098 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
1099 GLOBAL_EXCEPTION_ENABLE();
1100 }
1101
1102 /**
1103 * @brief Disable Communication Core Deep Sleep Mode.
1104 * @note Switch Communication Core from sleep mode into normal active mode.
1105 *
1106 * \rst
1107 * +----------------------+-----------------------------------+
1108 * | Register | BitsName |
1109 * +======================+===================================+
1110 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1111 * +----------------------+-----------------------------------+
1112 * \endrst
1113 *
1114 * @retval None
1115 */
1116 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
1117 {
1118 GLOBAL_EXCEPTION_DISABLE();
1119 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
1120 GLOBAL_EXCEPTION_ENABLE();
1121 }
1122
1123 /**
1124 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
1125 *
1126 * \rst
1127 * +----------------------+-----------------------------------+
1128 * | Register | BitsName |
1129 * +======================+===================================+
1130 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON |
1131 * +----------------------+-----------------------------------+
1132 * \endrst
1133 *
1134 * @retval State of bit (1 or 0).
1135 */
1136 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
1137 {
1138 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
1139 }
1140
1141 /**
1142 * @brief Enable Wake Up Request from Software.
1143 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
1144 * when written with a 1. No action happens if it is written with 0.
1145 *
1146 * \rst
1147 * +----------------------+-----------------------------------+
1148 * | Register | BitsName |
1149 * +======================+===================================+
1150 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ |
1151 * +----------------------+-----------------------------------+
1152 * \endrst
1153 *
1154 * @retval None
1155 */
1156 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
1157 {
1158 GLOBAL_EXCEPTION_DISABLE();
1159 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
1160 GLOBAL_EXCEPTION_ENABLE();
1161 }
1162
1163 /**
1164 * @brief Check if the Wake Up Request was enabled or disabled.
1165 * @note Resets at 0 means request action is performed.
1166 *
1167 * \rst
1168 * +----------------------+-----------------------------------+
1169 * | Register | BitsName |
1170 * +======================+===================================+
1171 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ |
1172 * +----------------------+-----------------------------------+
1173 * \endrst
1174 *
1175 * @retval State of bit (1 or 0).
1176 */
1177 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1178 {
1179 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1180 }
1181
1182 /**
1183 * @brief Enable Communication Core external wakeup.
1184 * @note After this configuration, Communication Core can be woken up by external wake-up
1185 *
1186 * \rst
1187 * +----------------------+-----------------------------------+
1188 * | Register | BitsName |
1189 * +======================+===================================+
1190 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1191 * +----------------------+-----------------------------------+
1192 * \endrst
1193 *
1194 * @retval None
1195 */
1196 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1197 {
1198 GLOBAL_EXCEPTION_DISABLE();
1199 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1200 GLOBAL_EXCEPTION_ENABLE();
1201 }
1202
1203 /**
1204 * @brief Disable Communication Core external wakeup.
1205 * @note After this configuration, Communication Core cannot be woken up by external wake-up
1206 *
1207 * \rst
1208 * +----------------------+-----------------------------------+
1209 * | Register | BitsName |
1210 * +======================+===================================+
1211 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1212 * +----------------------+-----------------------------------+
1213 * \endrst
1214 *
1215 * @retval None
1216 */
1217 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1218 {
1219 GLOBAL_EXCEPTION_DISABLE();
1220 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1221 GLOBAL_EXCEPTION_ENABLE();
1222 }
1223
1224 /**
1225 * @brief Check if the Communication Core external wakeup was enabled or disabled.
1226 *
1227 * \rst
1228 * +----------------------+-----------------------------------+
1229 * | Register | BitsName |
1230 * +======================+===================================+
1231 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB |
1232 * +----------------------+-----------------------------------+
1233 * \endrst
1234 *
1235 * @retval State of bit (1 or 0).
1236 */
1237 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1238 {
1239 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1240 }
1241
1242 /**
1243 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1244 *
1245 * \rst
1246 * +----------------------+-----------------------------------+
1247 * | Register | BitsName |
1248 * +======================+===================================+
1249 * | COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME|
1250 * +----------------------+-----------------------------------+
1251 * \endrst
1252 *
1253 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1254 * @retval None
1255 */
1256 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1257 {
1258 WRITE_REG(AON->PWR_RET28, time);
1259 }
1260
1261 /**
1262 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1263 *
1264 * \rst
1265 * +----------------------+-----------------------------------+
1266 * | Register | BitsName |
1267 * +======================+===================================+
1268 * | COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME|
1269 * +----------------------+-----------------------------------+
1270 * \endrst
1271 *
1272 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
1273 */
1274 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1275 {
1276 return ((uint32_t)READ_REG(AON->PWR_RET28));
1277 }
1278
1279
1280 /**
1281 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
1282 *
1283 * \rst
1284 * +----------------------+-----------------------------------+
1285 * | Register | BitsName |
1286 * +======================+===================================+
1287 * | COMM_TMR_DEEPSLPSTAT | DEEPSLDUR |
1288 * +----------------------+-----------------------------------+
1289 * \endrst
1290 *
1291 * @retval Sleep duration
1292 */
1293 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1294 {
1295 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1296 }
1297
1298 /**
1299 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1300 *
1301 * \rst
1302 * +----------------------+-----------------------------------+
1303 * | Register | BitsName |
1304 * +======================+===================================+
1305 * | COMM_TMR_ENBPRESET | TWEXT |
1306 * +----------------------+-----------------------------------+
1307 * | COMM_TMR_ENBPRESET | TWOSC |
1308 * +----------------------+-----------------------------------+
1309 * | COMM_TMR_ENBPRESET | TWRM |
1310 * +----------------------+-----------------------------------+
1311 * \endrst
1312 *
1313 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
1314 * oscillator following an external wake–up request (signal wakeup_req).
1315 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
1316 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
1317 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
1318 * @retval None
1319 */
1320 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1321 {
1322 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1323 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1324 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1325 }
1326
1327
1328 /**
1329 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1330 *
1331 * \rst
1332 * +----------------------+-----------------------------------+
1333 * | Register | BitsName |
1334 * +======================+===================================+
1335 * | COMM_TMR_ENBPRESET | TWEXT |
1336 * +----------------------+-----------------------------------+
1337 * | COMM_TMR_ENBPRESET | TWOSC |
1338 * +----------------------+-----------------------------------+
1339 * | COMM_TMR_ENBPRESET | TWRM |
1340 * +----------------------+-----------------------------------+
1341 * \endrst
1342 *
1343 *
1344 * @retval COMM_TMR_ENBPRESET Register value
1345 */
1346 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1347 {
1348 return ((uint32_t)READ_REG(AON->PWR_RET29));
1349 }
1350
1351 /**
1352 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1353 *
1354 * @retval TWOSC value
1355 */
1356 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1357 {
1358 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1359 }
1360
1361
1362 /** @} */
1363
1364 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1365 * @{
1366 */
1367
1368 /**
1369 * @brief Get the External Wake Up Status.
1370 * @note 0 means not waked up and 1 means waked up.
1371 *
1372 * \rst
1373 * +----------------------+-----------------------------------+
1374 * | Register | BitsName |
1375 * +======================+===================================+
1376 * | SLP_EVENT | EXT_WKUP_STATUS |
1377 * +----------------------+-----------------------------------+
1378 * \endrst
1379 *
1380 * @retval Returned value can be a combination of the following values:
1381 * @arg @ref LL_PWR_EXTWKUP_PIN0
1382 * @arg @ref LL_PWR_EXTWKUP_PIN1
1383 * @arg @ref LL_PWR_EXTWKUP_PIN2
1384 * @arg @ref LL_PWR_EXTWKUP_PIN3
1385 * @arg @ref LL_PWR_EXTWKUP_PIN4
1386 * @arg @ref LL_PWR_EXTWKUP_PIN5
1387 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1388 */
1389 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1390 {
1391 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1392 (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1393 }
1394
1395 /**
1396 * @brief Clear the External Wake Up Status.
1397 *
1398 * \rst
1399 * +----------------------+-----------------------------------+
1400 * | Register | BitsName |
1401 * +======================+===================================+
1402 * | SLP_EVENT | EXT_WKUP_STATUS |
1403 * +----------------------+-----------------------------------+
1404 * \endrst
1405 *
1406 * @param wakeup_pin This parameter can be a combination of the following values:
1407 * @arg @ref LL_PWR_EXTWKUP_PIN0
1408 * @arg @ref LL_PWR_EXTWKUP_PIN1
1409 * @arg @ref LL_PWR_EXTWKUP_PIN2
1410 * @arg @ref LL_PWR_EXTWKUP_PIN3
1411 * @arg @ref LL_PWR_EXTWKUP_PIN4
1412 * @arg @ref LL_PWR_EXTWKUP_PIN5
1413 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1414 * @retval None
1415 */
1416 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1417 {
1418 GLOBAL_EXCEPTION_DISABLE();
1419 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1420 GLOBAL_EXCEPTION_ENABLE();
1421 }
1422
1423 /**
1424 * @brief Clear the Event that triggered the DeepSleep WakeUp.
1425 *
1426 * \rst
1427 * +----------------------+-----------------------------------+
1428 * | Register | BitsName |
1429 * +======================+===================================+
1430 * | SLP_EVENT | SMCOSCEN_EVENT |
1431 * +----------------------+-----------------------------------+
1432 * \endrst
1433 * SLP_EVENT | TIMER_EVENT
1434 * SLP_EVENT | EXT_WKUP_EVENT
1435 * SLP_EVENT | WATCHDOG_EVENT
1436 *
1437 * @param event This parameter can be a combination of the following values:
1438 * @arg @ref LL_PWR_WKUP_EVENT_BLE
1439 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
1440 * @arg @ref LL_PWR_WKUP_EVENT_EXT
1441 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
1442 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
1443 * @arg @ref LL_PWR_WKUP_EVENT_WDT
1444 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
1445 * @retval None
1446 */
1447 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1448 {
1449 WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1450 }
1451
1452 /**
1453 * @brief Read the sleep timer interrupt status flag.
1454 *
1455 * Register |BitsName
1456 * --------------|--------
1457 * AON_SLP_EVENT | SLP_TIMER
1458 *
1459 * @retval interrupt flag of sleep timer (1 or 0).
1460 */
1461 __STATIC_INLINE uint32_t ll_sleep_timer_read_flag_it(void)
1462 {
1463 return (uint32_t)(READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_TIMER) == LL_PWR_WKUP_EVENT_TIMER);
1464 }
1465
1466 /**
1467 * @brief Indicate if the Power State Controller is in busy state.
1468 * @note This is bit set 1 when the PSC_CMD_REQ[0] is set to 1, and will remain 1 until
1469 * the PSC_CMD_OPC has been transferred to the PSC.
1470 *
1471 * \rst
1472 * +----------------------+-----------------------------------+
1473 * | Register | BitsName |
1474 * +======================+===================================+
1475 * | PSC_CMD | MCU_PWR_BUSY |
1476 * +----------------------+-----------------------------------+
1477 * \endrst
1478 *
1479 * @retval State of bit (1 or 0).
1480 */
1481 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1482 {
1483 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1484 }
1485
1486 /**
1487 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
1488 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
1489 *
1490 * \rst
1491 * +----------------------+-----------------------------------+
1492 * | Register | BitsName |
1493 * +======================+===================================+
1494 * | MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT |
1495 * +----------------------+-----------------------------------+
1496 * \endrst
1497 *
1498 * @retval State of bit (1 or 0).
1499 */
1500 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1501 {
1502 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1503 }
1504
1505 /**
1506 * @brief Disable cache function
1507 * @note The cache should be closed before chip go to deepsleep.
1508 *
1509 * \rst
1510 * +----------------------+-----------------------------------+
1511 * | Register | BitsName |
1512 * +======================+===================================+
1513 * | CTRL0 | EN |
1514 * +----------------------+-----------------------------------+
1515 * \endrst
1516 *
1517 * @retval None
1518 */
1519 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1520 {
1521 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1522 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
1523 }
1524
1525 /** @} */
1526
1527 /** @} */
1528 /** @} */
1529
1530 #endif /* defined(AON) */
1531
1532 #ifdef __cplusplus
1533 }
1534 #endif
1535
1536 #endif /* __GR55xx_LL_PWR_H__ */
1537
1538 /** @} */
1539
1540 /** @} */
1541
1542 /** @} */
ll_pwr_disable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
Disable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1217
ll_pwr_enable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
Enable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:526
ll_pwr_get_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
Get which timer value was selected to read.
Definition: gr55xx_ll_pwr.h:934
ll_pwr_enable_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
Enable Communication Core external wakeup.
Definition: gr55xx_ll_pwr.h:1196
ll_pwr_set_dpad_le_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
Set the DPAD LE value during sleep and after wake up.
Definition: gr55xx_ll_pwr.h:590
ll_pwr_disable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
Disable Radio sleep mode.
Definition: gr55xx_ll_pwr.h:1056
ll_pwr_is_enabled_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
Check if the Wake Up Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1177
ll_pwr_is_enabled_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
Check if the Communication Core Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:887
ll_pwr_set_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
Set the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:432
ll_pwr_is_enabled_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
Check if the Communication Core Deep Sleep Mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1136
ll_pwr_disable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
Disable the Communication Core Reset, and set Communication Core to running state.
Definition: gr55xx_ll_pwr.h:739
ll_pwr_get_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
Get the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1389
ll_pwr_read_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1346
ll_pwr_get_timer_read_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
Get current timer value based on the selection.
Definition: gr55xx_ll_pwr.h:957
ll_pwr_disable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
Disable high frequency crystal oscillator sleep mode.
Definition: gr55xx_ll_pwr.h:997
ll_pwr_disable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
Disable the Communication Timer Reset, and set Communication Timer to running state.
Definition: gr55xx_ll_pwr.h:681
ll_pwr_set_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
Set the DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:265
LL_PWR_EXTWKUP_PIN_ALL
#define LL_PWR_EXTWKUP_PIN_ALL
WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7.
Definition: gr55xx_ll_pwr.h:154
ll_pwr_read_comm_wakeup_timing_twosc
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1356
ll_pwr_get_comm_sleep_duration
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
Definition: gr55xx_ll_pwr.h:1293
ll_pwr_set_comm_core_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1256
ll_pwr_is_enabled_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
Check if the Communication Core Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:757
ll_pwr_set_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:489
ll_pwr_is_active_flag_psc_cmd_busy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
Indicate if the Power State Controller is in busy state.
Definition: gr55xx_ll_pwr.h:1481
ll_pwr_enable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
Enable the Communication Core Power, the Communication Core will be Powered Up.
Definition: gr55xx_ll_pwr.h:843
ll_pwr_disable_cache_module
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
Disable cache function.
Definition: gr55xx_ll_pwr.h:1519
ll_pwr_is_enabled_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
Check if the External WakeUp PINx functionality is enabled.
Definition: gr55xx_ll_pwr.h:400
ll_pwr_enable_comm_core_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
Enable the Communication Core Reset.
Definition: gr55xx_ll_pwr.h:720
ll_pwr_clear_ext_wakeup_status
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
Clear the External Wake Up Status.
Definition: gr55xx_ll_pwr.h:1416
ll_pwr_set_timer_read_select
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
Select which timer value to read.
Definition: gr55xx_ll_pwr.h:910
ll_pwr_disable_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
Disable the SMC WakeUp Request.
Definition: gr55xx_ll_pwr.h:545
LL_PWR_WKUP_EVENT_ALL
#define LL_PWR_WKUP_EVENT_ALL
All event mask
Definition: gr55xx_ll_pwr.h:134
LL_PWR_EXTWKUP_INVERT_LSB
#define LL_PWR_EXTWKUP_INVERT_LSB
External wakeup level invert.
Definition: gr55xx_ll_pwr.h:80
ll_pwr_is_enabled_smc_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
Check if the SMC WakeUp Request was enabled or disabled.
Definition: gr55xx_ll_pwr.h:563
ll_pwr_enable_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
Enable the Communication Timer Reset.
Definition: gr55xx_ll_pwr.h:662
ll_pwr_is_active_flag_comm_deep_sleep_stat
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
Indicate if the Communication Core is in Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1500
LL_PWR_WKUP_EVENT_TIMER
#define LL_PWR_WKUP_EVENT_TIMER
AON Timer wakeup event
Definition: gr55xx_ll_pwr.h:128
ll_pwr_disable_comm_core_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
Disable the Communication Core Power, the Communication Core will be Powered Down.
Definition: gr55xx_ll_pwr.h:864
ll_pwr_clear_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
Clear the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:1447
ll_pwr_disable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
Disable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:372
ll_pwr_get_wakeup_condition
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
Get the Selected DeepSleep WakeUp Condition.
Definition: gr55xx_ll_pwr.h:290
ll_pwr_enable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
Enable the Communication Timer Power, the Communication Timer will be Powered Up.
Definition: gr55xx_ll_pwr.h:778
ll_pwr_set_comm_wakeup_timing
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
Definition: gr55xx_ll_pwr.h:1320
ll_pwr_enable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
Enable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1095
ll_pwr_disable_comm_core_deep_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
Disable Communication Core Deep Sleep Mode.
Definition: gr55xx_ll_pwr.h:1116
ll_pwr_enable_ext_wakeup_pin
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
Enable the External WakeUp PINx functionality.
Definition: gr55xx_ll_pwr.h:344
ll_pwr_is_enabled_comm_core_ext_wakeup
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
Check if the Communication Core external wakeup was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1237
LL_PWR_EXTWKUP_TYPE_LSB
#define LL_PWR_EXTWKUP_TYPE_LSB
External wakeup level type.
Definition: gr55xx_ll_pwr.h:79
ll_pwr_enable_comm_soft_wakeup_req
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
Enable Wake Up Request from Software.
Definition: gr55xx_ll_pwr.h:1156
ll_pwr_enable_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
Enable Radio sleep mode, and disable Radio module.
Definition: gr55xx_ll_pwr.h:1035
ll_pwr_get_wakeup_event
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
Get the Event that triggered the DeepSleep WakeUp.
Definition: gr55xx_ll_pwr.h:318
ll_pwr_enable_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
Enable high frequency crystal oscillator sleep mode, and diable OSC.
Definition: gr55xx_ll_pwr.h:975
ll_pwr_get_comm_wakeup_time
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
Definition: gr55xx_ll_pwr.h:1274
ll_sleep_timer_read_flag_it
__STATIC_INLINE uint32_t ll_sleep_timer_read_flag_it(void)
Read the sleep timer interrupt status flag.
Definition: gr55xx_ll_pwr.h:1461
ll_pwr_is_enabled_comm_timer_reset
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
Check if the Communication Timer Reset was enabled or disabled.
Definition: gr55xx_ll_pwr.h:699
ll_pwr_is_enabled_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
Check if the Communication Timer Power was enabled or disabled.
Definition: gr55xx_ll_pwr.h:823
ll_pwr_get_sleep_timer_value
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
Definition: gr55xx_ll_pwr.h:507
ll_pwr_get_ext_wakeup_type
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
Get the WakeUp Type of External WakeUp PINx.
Definition: gr55xx_ll_pwr.h:468
ll_pwr_is_enabled_radio_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
Check if the Radio sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1076
ll_pwr_is_enabled_osc_sleep
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
Check if the OSC sleep mode was enabled or disabled.
Definition: gr55xx_ll_pwr.h:1017
ll_pwr_req_excute_psc_command
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
Request to excute the Power State Controller Command.
Definition: gr55xx_ll_pwr.h:635
ll_pwr_disable_comm_timer_power
SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
Disable the Communication Timer Power, the Communication Timer will be Powered Down.
Definition: gr55xx_ll_pwr.h:801