Functions
Cache driver functions
Peripheral Driver » LL Driver » XQSPI » Functions
Collaboration diagram for Cache driver functions:

## Functions
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_cache (xqspi_regs_t *XQSPIx)
| Enable cache function. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_cache (xqspi_regs_t *XQSPIx)
| Disable cache function. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_cache (xqspi_regs_t *XQSPIx)
| Check if cache function is enabled. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_cache_flush (xqspi_regs_t *XQSPIx)
| Enable tag memory flush. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_cache_flush (xqspi_regs_t *XQSPIx)
| Disable tag memory flush. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_cache_flush (xqspi_regs_t *XQSPIx)
| Check if tag memory flush is enabled. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_cache_fifo (xqspi_regs_t *XQSPIx, uint32_t mode)
| Set FIFO mode. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_fifo (xqspi_regs_t *XQSPIx)
| Get FIFO mode. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_cache_hitmiss (xqspi_regs_t *XQSPIx, uint32_t mode)
| Set HIT/MISS mode. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_hitmiss (xqspi_regs_t *XQSPIx)
| Get HIT/MISS mode. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_cache_dbgbus (xqspi_regs_t *XQSPIx, uint32_t sel)
| Set debugbus configurations signals. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_dbgbus (xqspi_regs_t *XQSPIx)
| Get debugbus configurations signals. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_cache_dbgmux (xqspi_regs_t *XQSPIx)
| Enable debug bus mux. More...
SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_cache_dbgmux (xqspi_regs_t *XQSPIx)
| Disable debug bus mux. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_cache_dbgmux (xqspi_regs_t *XQSPIx)
| Check if debug bus mux is enabled. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_hitcount (xqspi_regs_t *XQSPIx)
| Get hit counter. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_misscount (xqspi_regs_t *XQSPIx)
| Get miss counter. More...
SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_cache_flag (xqspi_regs_t *XQSPIx)
| Get cache status. More...

## Detailed Description

## Function Documentation

## ◆ ll_xqspi_disable_cache()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache | ( | xqspi_regs_t * | XQSPIx | ) |

Disable cache function.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 401 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_disable_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux | ( | xqspi_regs_t * | XQSPIx | ) |

Disable debug bus mux.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL1 | DBGMUX_EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 652 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_disable_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush | ( | xqspi_regs_t * | XQSPIx | ) |

Disable tag memory flush.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | TAG | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 463 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_enable_cache()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache | ( | xqspi_regs_t * | XQSPIx | ) |

Enable cache function.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 378 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_enable_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux | ( | xqspi_regs_t * | XQSPIx | ) |

Enable debug bus mux.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL1 | DBGMUX_EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 632 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_enable_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush | ( | xqspi_regs_t * | XQSPIx | ) |

Enable tag memory flush.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | TAG | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  None |

Definition at line 443 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_dbgbus()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus | ( | xqspi_regs_t * | XQSPIx | ) |

Get debugbus configurations signals.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL1 | DBGBUS_SEL | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can between: 0 ~ 0x7

Definition at line 612 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_fifo()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo | ( | xqspi_regs_t * | XQSPIx | ) |

Get FIFO mode.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | FIFO | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can be one of the following values: LL_XQSPI_CACHE_FIFO_NORMAL LL_XQSPI_CACHE_FIFO_CLEAR

Definition at line 527 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_flag()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag | ( | xqspi_regs_t * | XQSPIx | ) |

Get cache status.

Note
  This bit only be read.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | STAT | STAT | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can between: 0 ~ 1

Definition at line 731 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_hitcount()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount | ( | xqspi_regs_t * | XQSPIx | ) |

Get hit counter.

Note
  This bit only be read.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | HIT_COUNT | HITCOUNT | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can between: 0 ~ 0xFFFFFFFF

Definition at line 691 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_hitmiss()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss | ( | xqspi_regs_t * | XQSPIx | ) |

Get HIT/MISS mode.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | HITMISS | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can be one of the following values: LL_XQSPI_CACHE_HITMISS_NORMAL LL_XQSPI_CACHE_HITMISS_CLEAR

Definition at line 572 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_get_cache_misscount()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount | ( | xqspi_regs_t * | XQSPIx | ) |

Get miss counter.

Note
  This bit only be read.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | MISS_COUNT | MISSCOUNT | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  Returned | Value can between: 0 ~ 0xFFFFFFFF

Definition at line 711 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_is_enabled_cache()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache | ( | xqspi_regs_t * | XQSPIx | ) |

Check if cache function is enabled.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  State | of bit (1 or 0).

Definition at line 423 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_is_enabled_cache_dbgmux()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux | ( | xqspi_regs_t * | XQSPIx | ) |

Check if debug bus mux is enabled.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL1 | DBGMUX_EN | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  State | of bit (1 or 0).

Definition at line 671 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_is_enabled_cache_flush()

SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush | ( | xqspi_regs_t * | XQSPIx | ) |

Check if tag memory flush is enabled.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | TAG | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance

Return values

  State | of bit (1 or 0).

Definition at line 482 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_set_cache_dbgbus()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus | ( | xqspi_regs_t * | XQSPIx,
|  | uint32_t | sel
| ) |  |

Set debugbus configurations signals.

Note
  These bits should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL1 | DBGBUS_SEL | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance
  sel | This parameter can between: 0 ~ 0x7

Return values

  None |

Definition at line 593 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_set_cache_fifo()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo | ( | xqspi_regs_t * | XQSPIx,
|  | uint32_t | mode
| ) |  |

Set FIFO mode.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | FIFO | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance
  mode | This parameter can be one of the following values: LL_XQSPI_CACHE_FIFO_NORMAL LL_XQSPI_CACHE_FIFO_CLEAR

Return values

  None |

Definition at line 505 of file gr55xx_ll_xqspi.h.

## ◆ ll_xqspi_set_cache_hitmiss()

SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss | ( | xqspi_regs_t * | XQSPIx,
|  | uint32_t | mode
| ) |  |

Set HIT/MISS mode.

Note
  This bit should not be changed when XIP is ongoing.

\rst +-------------------—+--------------------------------—+ | Register | BitsName | +======================+===================================+ | CTRL0 | HITMISS | +-------------------—+--------------------------------—+ \endrst

Parameters

  XQSPIx | XQSPI instance
  mode | This parameter can be one of the following values: LL_XQSPI_CACHE_HITMISS_NORMAL LL_XQSPI_CACHE_HITMISS_CLEAR

Return values

  None |

Definition at line 550 of file gr55xx_ll_xqspi.h.