gr55xx_ll_i2c.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2c.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2C LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2C I2C
47 * @brief I2C LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2C0) || defined (I2C1)
63
64 /** @defgroup I2C_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2C_LL_ES_INIT I2C Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2C init Structure definition
75 */
76 typedef struct _ll_i2c_init
77 {
78 uint32_t speed; /**< Specifies the transfer speed. See @ref I2C_LL_EC_SPEED. */
79
80 uint32_t own_address; /**< Specifies the device own address.
81 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
82
83 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
84
85 uint32_t own_addr_size; /**< Specifies the device own address 1 size (7-bit or 10-bit).
86 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS
87
88 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
89 } ll_i2c_init_t;
90
91 /** @} */
92
93 /** @} */
94
95 /**
96 * @defgroup I2C_LL_MACRO Defines
97 * @{
98 */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
102 * @{
103 */
104
105 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
106 * @brief Flags definitions which can be used with LL_I2C_ReadReg function
107 * @{
108 */
109 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt flag */
110 #define LL_I2C_INTR_STAT_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt flag */
111 #define LL_I2C_INTR_STAT_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt flag */
112 #define LL_I2C_INTR_STAT_START_DET I2C_INTR_START_DET /**< START_DET interrupt flag */
113 #define LL_I2C_INTR_STAT_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt flag */
114 #define LL_I2C_INTR_STAT_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt flag */
115 #define LL_I2C_INTR_STAT_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt flag */
116 #define LL_I2C_INTR_STAT_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt flag */
117 #define LL_I2C_INTR_STAT_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt flag */
118 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt flag */
119 #define LL_I2C_INTR_STAT_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt flag */
120 #define LL_I2C_INTR_STAT_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt flag */
121 #define LL_I2C_INTR_STAT_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt flag */
122 #define LL_I2C_INTR_STAT_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt flag */
123
124 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT /**< Transfer abort detected by master */
125 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT /**< Transfer abort detected by master */
126 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX /**< Slave trying to transmit to remote master in read mode */
127 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST /**< Slave lost arbitration to remote master */
128 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO /**< Slave flushes existing data in TX-FIFO upon getting read command */
129 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST /**< Master or Slave Transmitter lost arbitration */
130 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABRT_SRC_MST_DIS /**< User intitating master operation when MASTER disabled */
131 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT /**< Master trying to read in 10-Bit addressing mode when RESTART disabled */
132 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT /**< User trying to send START byte when RESTART disabled */
133 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT /**< User trying to swidth Master to HS mode when RESTART disabled */
134 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET /**< ACK detected for START byte */
135 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET /**< HS Master code is ACKed in HS Mode */
136 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ /**< GCALL is followed by read from bus */
137 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK /**< GCALL is not ACKed by any slave */
138 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK /**< Transmitted data is not ACKed by addressed slave */
139 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK /**< Byte 2 of 10-Bit Address is not ACKed by any slave */
140 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK /**< Byte 1 of 10-Bit Address is not ACKed by any slave */
141 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK /**< 7Bit Address is not ACKed by any slave */
142 /** @} */
143
144 /** @defgroup I2C_LL_EC_IT IT Defines
145 * @brief Interrupt definitions which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
146 * @{
147 */
148 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt */
149 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt */
150 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt */
151 #define LL_I2C_INTR_MASK_START_DET I2C_INTR_START_DET /**< START_DET interrupt */
152 #define LL_I2C_INTR_MASK_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt */
153 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt */
154 #define LL_I2C_INTR_MASK_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt */
155 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt */
156 #define LL_I2C_INTR_MASK_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt */
157 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt */
158 #define LL_I2C_INTR_MASK_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt */
159 #define LL_I2C_INTR_MASK_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt */
160 #define LL_I2C_INTR_MASK_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt */
161 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt */
162
163 #define LL_I2C_INTR_MASK_ALL 0x00000FFFU /**< All interrupt */
164 /** @} */
165
166 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
167 * @{
168 */
169 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /**< Master operates in 7-bit addressing mode. */
170 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CON_10BITADDR_MST /**< Master operates in 10-bit addressing mode.*/
171 /** @} */
172
173 /** @defgroup I2C_LL_EC_OWNADDRESS Own Address Length
174 * @{
175 */
176 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U /**< Own address 1 is a 7-bit address. */
177 #define LL_I2C_OWNADDRESS_10BIT I2C_CON_10BITADDR_SLV /**< Own address 1 is a 10-bit address.*/
178 /** @} */
179
180
181 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
182 * @{
183 */
184 #define LL_I2C_CMD_SLV_NONE 0x00000000U /**< Slave No command. */
185 #define LL_I2C_CMD_MST_WRITE 0x00000000U /**< Master write command. */
186 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD /**< Master read command. */
187 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP /**< Master issue STOP after this command. */
188 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART /**< Master issue RESTART before this command. */
189 /** @} */
190
191 /** @defgroup I2C_LL_EC_SPEED_MODE Transfer Speed Mode
192 * @{
193 */
194 #define LL_I2C_SPEED_MODE_STANDARD I2C_CON_SPEED_STANDARD /**< Standard Speed mode(0 to 100 Kb/s) of operation. */
195 #define LL_I2C_SPEED_MODE_FAST I2C_CON_SPEED_FAST /**< Fast (鈮?400 Kb/s) or Fast Plus mode (鈮?1000 螝b/s) of operation. */
196 #define LL_I2C_SPEED_MODE_HIGH I2C_CON_SPEED_HIGH /**< High Speed mode (鈮?3.4 Mb/s) of operation. */
197 /** @} */
198
199 /** @defgroup I2C_LL_EC_SPEED Transfer Speed
200 * @{
201 */
202 #define LL_I2C_SPEED_100K (100000ul) /**< Standard Speed. */
203 #define LL_I2C_SPEED_400K (400000ul) /**< Fast Speed. */
204 #define LL_I2C_SPEED_1000K (1000000ul) /**< Fast Plus Speed. */
205 #define LL_I2C_SPEED_2000K (2000000ul) /**< High Speed. */
206 /** @} */
207
208 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
209 * @{
210 */
211 #define LL_I2C_DIRECTION_NONE 0x00000000U /**< No transfer request by master. */
212 #define LL_I2C_DIRECTION_WRITE I2C_INTR_RX_FULL /**< Write transfer request by master, slave enters receiver mode. */
213 #define LL_I2C_DIRECTION_READ I2C_INTR_RD_REQ /**< Read transfer request by master, slave enters transmitter mode.*/
214 #define LL_I2C_DIRECTION_ERROR I2C_INTR_RX_FULL | I2C_INTR_RD_REQ /**< Transfer request error. */
215 /** @} */
216
217
218 /** @defgroup I2C_LL_EC_TX_FIFO_TH TX FIFO Threshold
219 * @{
220 */
221 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
222 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U /**< 1 character in TX FIFO */
223 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U /**< 2 characters in TX FIFO */
224 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U /**< 3 characters in TX FIFO */
225 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U /**< 4 characters in TX FIFO */
226 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U /**< 5 characters in TX FIFO */
227 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U /**< 6 characters in TX FIFO */
228 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U /**< 7 characters in TX FIFO */
229 /** @} */
230
231 /** @defgroup I2C_LL_EC_RX_FIFO_TH RX FIFO Threshold
232 * @{
233 */
234 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
235 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in RX FIFO */
236 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U /**< 3 characters in RX FIFO */
237 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U /**< 4 characters in RX FIFO */
238 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U /**< 5 characters in RX FIFO */
239 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U /**< 6 characters in RX FIFO */
240 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U /**< 7 characters in RX FIFO */
241 #define LL_I2C_RX_FIFO_TH_FULL 0x00000007U /**< RX FIFO full */
242 /** @} */
243
244 /** @defgroup I2C_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
245 * @{
246 */
247
248 /**
249 * @brief LL I2C InitStrcut default configuartion
250 */
251 #define LL_I2C_DEFAULT_CONFIG \
252 { \
253 .speed = LL_I2C_SPEED_400K, \
254 .own_address = 0x55U, \
255 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
256 }
257 /** @} */
258
259 /** @} */
260
261 /* Exported macro ------------------------------------------------------------*/
262 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
263 * @{
264 */
265
266 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
267 * @{
268 */
269
270 /**
271 * @brief Write a value in I2C register
272 * @param __instance__ I2C instance
273 * @param __REG__ Register to be written
274 * @param __VALUE__ Value to be written in the register
275 * @retval None.
276 */
277 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
278
279 /**
280 * @brief Read a value in I2C register
281 * @param __instance__ I2C instance
282 * @param __REG__ Register to be read
283 * @retval Register value
284 */
285 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
286 /** @} */
287
288 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
289 * @{
290 */
291
292 /**
293 * @brief Compute CLK_SSL_CNT value according to Peripheral Clock and expected Speed.
294 * @param __PERIPHCLK__ Peripheral Clock frequency used for I2C instance
295 * @param __SPEED__ Speed value to achieve
296 * @retval CLK_SSL_CNT value to be used for XS_SCL_HCNT, XS_SCL_LCNT registers where X can be (S, F, H)
297 */
298 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
299
300 /**
301 * @brief Get Speed Mode according to expected Speed.
302 * @param __SPEED__ Speed value to achieve
303 * @retval Returned value can be one of the following values:
304 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
305 * @arg @ref LL_I2C_SPEED_MODE_FAST
306 * @arg @ref LL_I2C_SPEED_MODE_HIGH
307 */
308 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
309 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
310 /** @} */
311
312 /** @} */
313
314 /** @} */
315
316 /* Private types -------------------------------------------------------------*/
317 /* Private variables ---------------------------------------------------------*/
318 /* Private constants ---------------------------------------------------------*/
319 /* Private macros ------------------------------------------------------------*/
320
321 /* Exported functions --------------------------------------------------------*/
322 /** @defgroup I2C_LL_DRIVER_FUNCTIONS Functions
323 * @{
324 */
325
326 /** @defgroup I2C_LL_EF_Configuration Configuration
327 * @{
328 */
329
330 /**
331 * @brief Enable I2C peripheral (ENABLE = 1).
332 *
333 * \rst
334 * +----------------------+-----------------------------------+
335 * | Register | BitsName |
336 * +======================+===================================+
337 * | IC_ENABLE | ENABLE |
338 * +----------------------+-----------------------------------+
339 * \endrst
340 *
341 * @param I2Cx I2C instance.
342 * @retval None.
343 */
344 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
345 {
346 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
347 }
348
349 /**
350 * @brief Disable I2C peripheral (ENABLE = 0).
351 * @note When ENABLE = 0, the TX FIFO and RX FIFO get flushed.
352 * Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state.
353 * If the module is transmitting, it stops as well as deletes the contents of the transmit buffer
354 * after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops
355 * the current transfer at the end of the current byte and does not acknowledge the transfer..
356 *
357 * \rst
358 * +----------------------+-----------------------------------+
359 * | Register | BitsName |
360 * +======================+===================================+
361 * | IC_ENABLE | ENABLE |
362 * +----------------------+-----------------------------------+
363 * \endrst
364 *
365 * @param I2Cx I2C instance.
366 * @retval None.
367 */
368 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
369 {
370 CLEAR_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
371 }
372
373 /**
374 * @brief Check if the I2C peripheral is enabled or disabled.
375 *
376 * \rst
377 * +----------------------+-----------------------------------+
378 * | Register | BitsName |
379 * +======================+===================================+
380 * | IC_ENABLE_STATUS | IC_EN |
381 * +----------------------+-----------------------------------+
382 * \endrst
383 *
384 * @param I2Cx I2C instance.
385 * @retval State of bit (1 or 0).
386 */
387 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
388 {
389 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_IC_EN) == (I2C_ENABLE_STATUS_IC_EN));
390 }
391
392 /**
393 * @brief Enable I2C master mode.
394 *
395 * \rst
396 * +----------------------+-----------------------------------+
397 * | Register | BitsName |
398 * +======================+===================================+
399 * | IC_CON | MASTER_ENABLE |
400 * +----------------------+-----------------------------------+
401 * \endrst
402 * IC_CON | SLAVE_DISABLE
403 * @param I2Cx I2C instance.
404 * @retval None.
405 */
406 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
407 {
408 SET_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
409 }
410
411 /**
412 * @brief Disable I2C master mode and enable slave mode.
413 *
414 * \rst
415 * +----------------------+-----------------------------------+
416 * | Register | BitsName |
417 * +======================+===================================+
418 * | IC_CON | MASTER_ENABLE |
419 * +----------------------+-----------------------------------+
420 * \endrst
421 * IC_CON | SLAVE_DISABLE
422 * @param I2Cx I2C instance.
423 * @retval None.
424 */
425 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
426 {
427 CLEAR_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
428 }
429
430 /**
431 * @brief Check if I2C master mode is enabled or disabled.
432 *
433 * \rst
434 * +----------------------+-----------------------------------+
435 * | Register | BitsName |
436 * +======================+===================================+
437 * | IC_CON | MASTER_ENABLE |
438 * +----------------------+-----------------------------------+
439 * \endrst
440 * IC_CON | SLAVE_DISABLE
441 *
442 * @param I2Cx I2C instance.
443 * @retval State of bit (1 or 0).
444 */
445 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
446 {
447 return (READ_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS) == (I2C_CON_MST_MODE | I2C_CON_SLV_DIS));
448 }
449
450 /**
451 * @brief Enable General Call(slave mode).
452 * @note When enabled, the Address 0x00 is ACKed.
453 *
454 * \rst
455 * +----------------------+-----------------------------------+
456 * | Register | BitsName |
457 * +======================+===================================+
458 * | IC_ACK_GENERAL_CALL | ACK_GEN_CALL |
459 * +----------------------+-----------------------------------+
460 * \endrst
461 *
462 * @param I2Cx I2C instance.
463 * @retval None.
464 */
465 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
466 {
467 SET_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
468 }
469
470 /**
471 * @brief Disable General Call(slave mode).
472 * @note When disabled, the Address 0x00 is NACKed.
473 *
474 * \rst
475 * +----------------------+-----------------------------------+
476 * | Register | BitsName |
477 * +======================+===================================+
478 * | IC_ACK_GENERAL_CALL | ACK_GEN_CALL |
479 * +----------------------+-----------------------------------+
480 * \endrst
481 *
482 * @param I2Cx I2C instance.
483 * @retval None.
484 */
485 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
486 {
487 CLEAR_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
488 }
489
490 /**
491 * @brief Check if General Call is enabled or disabled(slave mode).
492 *
493 * \rst
494 * +----------------------+-----------------------------------+
495 * | Register | BitsName |
496 * +======================+===================================+
497 * | IC_ACK_GENERAL_CALL | ACK_GEN_CALL |
498 * +----------------------+-----------------------------------+
499 * \endrst
500 *
501 * @param I2Cx I2C instance.
502 * @retval State of bit (1 or 0).
503 */
504 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
505 {
506 return (READ_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC) == (I2C_ACK_GENERAL_CALL_ACK_GC));
507 }
508
509 /**
510 * @brief Enable Master Restart.
511 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
512 * This bit determines whether RESTART conditions may be sent when acting as a master.
513 * Some older slaves do not support handling RESTART conditions.
514 * When RESTART is disabled, the master is prohibited from performing the following functions:
515 * - Performing any high-speed mode operation.
516 * - Performing direction changes in combined format mode.
517 * - Performing a read operation with a 10-bit address.
518 *
519 * \rst
520 * +----------------------+-----------------------------------+
521 * | Register | BitsName |
522 * +======================+===================================+
523 * | IC_CON | CON_RESTART_EN |
524 * +----------------------+-----------------------------------+
525 * \endrst
526 *
527 * @param I2Cx I2C instance.
528 * @retval None.
529 */
530 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
531 {
532 SET_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
533 }
534
535 /**
536 * @brief Disable Master Restart.
537 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
538 *
539 * \rst
540 * +----------------------+-----------------------------------+
541 * | Register | BitsName |
542 * +======================+===================================+
543 * | IC_CON | CON_RESTART_EN |
544 * +----------------------+-----------------------------------+
545 * \endrst
546 *
547 * @param I2Cx I2C instance.
548 * @retval None.
549 */
550 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
551 {
552 CLEAR_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
553 }
554
555 /**
556 * @brief Check if Master Restart is enabled or disabled.
557 *
558 * \rst
559 * +----------------------+-----------------------------------+
560 * | Register | BitsName |
561 * +======================+===================================+
562 * | IC_CON | CON_RESTART_EN |
563 * +----------------------+-----------------------------------+
564 * \endrst
565 *
566 * @param I2Cx I2C instance.
567 * @retval State of bit (1 or 0).
568 */
569 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
570 {
571 return (READ_BITS(I2Cx->CON, I2C_CON_RESTART_EN) == (I2C_CON_RESTART_EN));
572 }
573
574 /**
575 * @brief Enable Slave issues STOP_DET interrupt only if addressed function.
576 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
577 * During a general call address, the slave does not issue the STOP_DET interrupt if
578 * STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address
579 * by generating ACK. The STOP_DET interrupt is generated only when the transmitted
580 * address matches the slave address (SAR).
581 *
582 * \rst
583 * +----------------------+-----------------------------------+
584 * | Register | BitsName |
585 * +======================+===================================+
586 * | IC_CON | STOP_DET_IF_ADDRESSED |
587 * +----------------------+-----------------------------------+
588 * \endrst
589 *
590 * @param I2Cx I2C instance.
591 * @retval None.
592 */
593 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
594 {
595 SET_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
596 }
597
598 /**
599 * @brief Disable Slave issues STOP_DET interrupt only if addressed function.
600 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
601 *
602 * \rst
603 * +----------------------+-----------------------------------+
604 * | Register | BitsName |
605 * +======================+===================================+
606 * | IC_CON | STOP_DET_IF_ADDRESSED |
607 * +----------------------+-----------------------------------+
608 * \endrst
609 *
610 * @param I2Cx I2C instance.
611 * @retval None.
612 */
613 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
614 {
615 CLEAR_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
616 }
617
618 /**
619 * @brief Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
620 *
621 * \rst
622 * +----------------------+-----------------------------------+
623 * | Register | BitsName |
624 * +======================+===================================+
625 * | IC_CON | STOP_DET_IF_ADDRESSED |
626 * +----------------------+-----------------------------------+
627 * \endrst
628 *
629 * @param I2Cx I2C instance.
630 * @retval State of bit (1 or 0).
631 */
632 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
633 {
634 return (READ_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED) == (I2C_CON_STOP_DET_IF_ADDRESSED));
635 }
636
637 /**
638 * @brief Configure the Master to transfers in 7-bit or 10-bit addressing mode.
639 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
640 *
641 * \rst
642 * +----------------------+-----------------------------------+
643 * | Register | BitsName |
644 * +======================+===================================+
645 * | IC_CON | CON_10BITADDR_MST |
646 * +----------------------+-----------------------------------+
647 * \endrst
648 *
649 * @param I2Cx I2C instance.
650 * @param addressing_mode This parameter can be one of the following values:
651 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
652 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
653 * @retval None.
654 */
655 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
656 {
657 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_MST, addressing_mode);
658 }
659
660 /**
661 * @brief Get the Master addressing mode.
662 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
663 *
664 * \rst
665 * +----------------------+-----------------------------------+
666 * | Register | BitsName |
667 * +======================+===================================+
668 * | IC_CON | CON_10BITADDR_MST |
669 * +----------------------+-----------------------------------+
670 * \endrst
671 *
672 * @param I2Cx I2C instance.
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
675 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
676 */
677 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
678 {
679 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_10BITADDR_MST));
680 }
681
682 /**
683 * @brief Set the Own Address.
684 * @note The register IC_CON and IC_SAR can only be programmed when the I2C is disabled (IC_ENABLE = 0).
685 *
686 * \rst
687 * +----------------------+-----------------------------------+
688 * | Register | BitsName |
689 * +======================+===================================+
690 * | IC_CON | CON_10BITADDR_SLV |
691 * +----------------------+-----------------------------------+
692 * \endrst
693 * IC_SAR | SAR
694 *
695 * @param I2Cx I2C instance.
696 * @param own_address This parameter must be a value range between 0 ~ 0x3FF(10-bit mode) or 0 ~ 0x7F(7-bit mode).
697 * Reserved address 0x00 to 0x07, or 0x78 to 0x7f should not be configured.
698 * @param own_addr_size This parameter can be one of the following values:
699 * @arg @ref LL_I2C_OWNADDRESS_7BIT
700 * @arg @ref LL_I2C_OWNADDRESS_10BIT
701 * @retval None.
702 */
703 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
704 {
705 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_SLV, own_addr_size);
706 WRITE_REG(I2Cx->SAR, own_address);
707 }
708
709 /**
710 * @brief Set the SCL clock high-period count for standard speed.
711 * @note The register IC_SS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
712 *
713 * \rst
714 * +----------------------+-----------------------------------+
715 * | Register | BitsName |
716 * +======================+===================================+
717 * | IC_SS_SCL_HCNT | SS_SCL_HCNT |
718 * +----------------------+-----------------------------------+
719 * \endrst
720 *
721 * @param I2Cx I2C instance.
722 * @param count This parameter must be a value range between 6 ~ 0xFFF5.
723 * @retval None.
724 */
725 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
726 {
727 WRITE_REG(I2Cx->SS_SCL_HCNT, count);
728 }
729
730 /**
731 * @brief Get the SCL clock high-period count for standard speed.
732 *
733 * \rst
734 * +----------------------+-----------------------------------+
735 * | Register | BitsName |
736 * +======================+===================================+
737 * | IC_SS_SCL_HCNT | SS_SCL_HCNT |
738 * +----------------------+-----------------------------------+
739 * \endrst
740 *
741 * @param I2Cx I2C instance.
742 * @retval Value range between 0x6 and 0xFFF5.
743 */
744 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
745 {
746 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_HCNT, I2C_SS_SCL_HCNT));
747 }
748
749 /**
750 * @brief Set the SCL clock low-period count for standard speed.
751 * @note The register IC_SS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
752 *
753 * \rst
754 * +----------------------+-----------------------------------+
755 * | Register | BitsName |
756 * +======================+===================================+
757 * | IC_SS_SCL_LCNT | SS_SCL_LCNT |
758 * +----------------------+-----------------------------------+
759 * \endrst
760 *
761 * @param I2Cx I2C instance.
762 * @param count This parameter must be a value range between 0x8 and 0xFFFF.
763 * @retval None.
764 */
765 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
766 {
767 WRITE_REG(I2Cx->SS_SCL_LCNT, count);
768 }
769
770 /**
771 * @brief Get the SCL clock low-period count for standard speed.
772 *
773 * \rst
774 * +----------------------+-----------------------------------+
775 * | Register | BitsName |
776 * +======================+===================================+
777 * | IC_SS_SCL_LCNT | SS_SCL_LCNT |
778 * +----------------------+-----------------------------------+
779 * \endrst
780 *
781 * @param I2Cx I2C instance.
782 * @retval Value range between 0x8 and 0xFFFF.
783 */
784 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
785 {
786 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_LCNT, I2C_SS_SCL_LCNT));
787 }
788
789 /**
790 * @brief Set the SCL clock high-period count for fast speed.
791 * @note The register IC_FS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
792 *
793 * \rst
794 * +----------------------+-----------------------------------+
795 * | Register | BitsName |
796 * +======================+===================================+
797 * | IC_FS_SCL_HCNT | FS_SCL_HCNT |
798 * +----------------------+-----------------------------------+
799 * \endrst
800 *
801 * @param I2Cx I2C instance.
802 * @param count range between 0x6 and 0xFFFF.
803 * @retval None.
804 */
805 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
806 {
807 WRITE_REG(I2Cx->FS_SCL_HCNT, count);
808 }
809
810 /**
811 * @brief Get the SCL clock high-period count for fast speed.
812 *
813 * \rst
814 * +----------------------+-----------------------------------+
815 * | Register | BitsName |
816 * +======================+===================================+
817 * | IC_FS_SCL_HCNT | FS_SCL_HCNT |
818 * +----------------------+-----------------------------------+
819 * \endrst
820 *
821 * @param I2Cx I2C instance.
822 * @retval Value range between 0x6 and 0xFFFF.
823 */
824 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
825 {
826 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_HCNT, I2C_FS_SCL_HCNT));
827 }
828
829 /**
830 * @brief Set the SCL clock low-period count for fast speed.
831 * @note The register IC_FS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
832 *
833 * \rst
834 * +----------------------+-----------------------------------+
835 * | Register | BitsName |
836 * +======================+===================================+
837 * | IC_FS_SCL_LCNT | FS_SCL_LCNT |
838 * +----------------------+-----------------------------------+
839 * \endrst
840 *
841 * @param I2Cx I2C instance.
842 * @param count range between 0x8 and 0xFFFF
843 * @retval None.
844 */
845 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
846 {
847 WRITE_REG(I2Cx->FS_SCL_LCNT, count);
848 }
849
850 /**
851 * @brief Get the SCL clock low-period count for fast speed.
852 *
853 * \rst
854 * +----------------------+-----------------------------------+
855 * | Register | BitsName |
856 * +======================+===================================+
857 * | IC_FS_SCL_LCNT | FS_SCL_LCNT |
858 * +----------------------+-----------------------------------+
859 * \endrst
860 *
861 * @param I2Cx I2C instance.
862 * @retval Value range between 0x8 and 0xFFFF.
863 */
864 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
865 {
866 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_LCNT, I2C_FS_SCL_LCNT));
867 }
868
869 /**
870 * @brief Get the SCL clock high-period count for high speed.
871 * @note The register IC_HS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
872 *
873 * \rst
874 * +----------------------+-----------------------------------+
875 * | Register | BitsName |
876 * +======================+===================================+
877 * | IC_HS_SCL_HCNT | HS_SCL_HCNT |
878 * +----------------------+-----------------------------------+
879 * \endrst
880 *
881 * @param I2Cx I2C instance.
882 * @param count range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 5.
883 * @retval None.
884 */
885 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
886 {
887 WRITE_REG(I2Cx->HS_SCL_HCNT, count);
888 }
889
890 /**
891 * @brief Get the SCL clock high-period count for high speed.
892 *
893 * \rst
894 * +----------------------+-----------------------------------+
895 * | Register | BitsName |
896 * +======================+===================================+
897 * | IC_HS_SCL_HCNT | HS_SCL_HCNT |
898 * +----------------------+-----------------------------------+
899 * \endrst
900 *
901 * @param I2Cx I2C instance.
902 * @retval range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 7.
903 */
904 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
905 {
906 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_HCNT, I2C_HS_SCL_HCNT));
907 }
908
909 /**
910 * @brief Get the SCL clock low-period count for high speed.
911 * @note The register IC_HS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
912 *
913 * \rst
914 * +----------------------+-----------------------------------+
915 * | Register | BitsName |
916 * +======================+===================================+
917 * | IC_HS_SCL_LCNT | HS_SCL_LCNT |
918 * +----------------------+-----------------------------------+
919 * \endrst
920 *
921 * @param I2Cx I2C instance.
922 * @param count range between 0x8 and 0xFFFF
923 * @retval None.
924 */
925 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
926 {
927 WRITE_REG(I2Cx->HS_SCL_LCNT, count);
928 }
929
930 /**
931 * @brief Get the SCL clock low-period count for high speed.
932 *
933 * \rst
934 * +----------------------+-----------------------------------+
935 * | Register | BitsName |
936 * +======================+===================================+
937 * | IC_HS_SCL_LCNT | HS_SCL_LCNT |
938 * +----------------------+-----------------------------------+
939 * \endrst
940 *
941 * @param I2Cx I2C instance.
942 * @retval Value range between 0x8 and 0xFFFF
943 */
944 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
945 {
946 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_LCNT, I2C_HS_SCL_LCNT));
947 }
948
949 /**
950 * @brief Set the spike len in fast speed mode.
951 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
952 *
953 * \rst
954 * +----------------------+-----------------------------------+
955 * | Register | BitsName |
956 * +======================+===================================+
957 * | IC_FS_SPKLEN | FS_SPKLEN |
958 * +----------------------+-----------------------------------+
959 * \endrst
960 *
961 * @param I2Cx I2C instance.
962 * @param length Spike len.
963 * @retval None.
964 */
965 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
966 {
967 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
968 }
969
970 /**
971 * @brief Get the spike len in fast speed mode.
972 *
973 * \rst
974 * +----------------------+-----------------------------------+
975 * | Register | BitsName |
976 * +======================+===================================+
977 * | IC_FS_SPKLEN | FS_SPKLEN |
978 * +----------------------+-----------------------------------+
979 * \endrst
980 *
981 * @param I2Cx I2C instance.
982 * @retval Value range between 0x2 and 0xFF.
983 */
984 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
985 {
986 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
987 }
988
989 /**
990 * @brief Set the spike len in high speed mode.
991 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
992 *
993 * \rst
994 * +----------------------+-----------------------------------+
995 * | Register | BitsName |
996 * +======================+===================================+
997 * | IC_HS_SPKLEN | HS_SPKLEN |
998 * +----------------------+-----------------------------------+
999 * \endrst
1000 *
1001 * @param I2Cx I2C instance.
1002 * @param length Spike len.
1003 * @retval None.
1004 */
1005 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
1006 {
1007 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
1008 }
1009
1010 /**
1011 * @brief Get the spike len in high speed mode.
1012 *
1013 * \rst
1014 * +----------------------+-----------------------------------+
1015 * | Register | BitsName |
1016 * +======================+===================================+
1017 * | IC_HS_SPKLEN | HS_SPKLEN |
1018 * +----------------------+-----------------------------------+
1019 * \endrst
1020 *
1021 * @param I2Cx I2C instance.
1022 * @retval Value range between 0x2 and 0xFF.
1023 */
1024 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
1025 {
1026 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
1027 }
1028
1029 /**
1030 * @brief Set I2C Speed mode.
1031 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1032 *
1033 * \rst
1034 * +----------------------+-----------------------------------+
1035 * | Register | BitsName |
1036 * +======================+===================================+
1037 * | IC_CON | SPEED |
1038 * +----------------------+-----------------------------------+
1039 * \endrst
1040 *
1041 * @param I2Cx I2C instance.
1042 * @param speed_mode This parameter can be one of the following values:
1043 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1044 * @arg @ref LL_I2C_SPEED_MODE_FAST
1045 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1046 * @retval None.
1047 */
1048 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
1049 {
1050 MODIFY_REG(I2Cx->CON, I2C_CON_SPEED, speed_mode);
1051 }
1052
1053 /**
1054 * @brief Get I2C Speed mode.
1055 *
1056 * \rst
1057 * +----------------------+-----------------------------------+
1058 * | Register | BitsName |
1059 * +======================+===================================+
1060 * | IC_CON | SPEED |
1061 * +----------------------+-----------------------------------+
1062 * \endrst
1063 *
1064 * @param I2Cx I2C instance.
1065 * @retval Value can be one of the following values:
1066 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1067 * @arg @ref LL_I2C_SPEED_MODE_FAST
1068 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1069 */
1070 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
1071 {
1072 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_SPEED));
1073 }
1074
1075 /**
1076 * @brief Set I2C High Speed Master Code Address.
1077 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1078 *
1079 * \rst
1080 * +----------------------+-----------------------------------+
1081 * | Register | BitsName |
1082 * +======================+===================================+
1083 * | IC_HS_MADDR | HS_MAR |
1084 * +----------------------+-----------------------------------+
1085 * \endrst
1086 *
1087 * @param I2Cx I2C instance.
1088 * @param code HS mode master code, range between 0x00 and 0x07.
1089 * @retval None.
1090 */
1091 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
1092 {
1093 WRITE_REG(I2Cx->HS_MADDR, code);
1094 }
1095
1096 /**
1097 * @brief Get I2C Speed mode.
1098 *
1099 * \rst
1100 * +----------------------+-----------------------------------+
1101 * | Register | BitsName |
1102 * +======================+===================================+
1103 * | IC_HS_MADDR | HS_MAR |
1104 * +----------------------+-----------------------------------+
1105 * \endrst
1106 *
1107 * @param I2Cx I2C instance.
1108 * @retval Returned value range between 0x00 and 0x07.
1109 */
1110 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
1111 {
1112 return (uint32_t)(READ_BITS(I2Cx->HS_MADDR, I2C_HS_MADDR_HS_MAR));
1113 }
1114
1115 /**
1116 * @brief Set the required transmit SDA hold time in units of ic_clk period.
1117 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1118 *
1119 * \rst
1120 * +----------------------+-----------------------------------+
1121 * | Register | BitsName |
1122 * +======================+===================================+
1123 * | IC_SDA_HOLD | TX_HOLD |
1124 * +----------------------+-----------------------------------+
1125 * \endrst
1126 *
1127 * @param I2Cx I2C instance.
1128 * @param time SDA Tx hold time in units of ic_clk period.
1129 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1130 * @retval None.
1131 */
1132 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1133 {
1134 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_Pos);
1135 }
1136
1137 /**
1138 * @brief Get the required transmit SDA hold time in units of ic_clk period.
1139 *
1140 * \rst
1141 * +----------------------+-----------------------------------+
1142 * | Register | BitsName |
1143 * +======================+===================================+
1144 * | IC_SDA_HOLD | TX_HOLD |
1145 * +----------------------+-----------------------------------+
1146 * \endrst
1147 *
1148 * @param I2Cx I2C instance.
1149 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1150 */
1151 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
1152 {
1153 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_Pos);
1154 }
1155
1156 /**
1157 * @brief Set the required receive SDA hold time in units of ic_clk period.
1158 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1159 *
1160 * \rst
1161 * +----------------------+-----------------------------------+
1162 * | Register | BitsName |
1163 * +======================+===================================+
1164 * | IC_SDA_HOLD | RX_HOLD |
1165 * +----------------------+-----------------------------------+
1166 * \endrst
1167 *
1168 * @param I2Cx I2C instance.
1169 * @param time SDA Tx hold time in units of ic_clk period.
1170 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1171 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1172 */
1173 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1174 {
1175 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_Pos);
1176 }
1177
1178 /**
1179 * @brief Get the required receive SDA hold time in units of ic_clk period.
1180 *
1181 * \rst
1182 * +----------------------+-----------------------------------+
1183 * | Register | BitsName |
1184 * +======================+===================================+
1185 * | IC_SDA_HOLD | RX_HOLD |
1186 * +----------------------+-----------------------------------+
1187 * \endrst
1188 *
1189 * @param I2Cx I2C instance.
1190 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1191 */
1192 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1193 {
1194 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_Pos);
1195 }
1196
1197 /**
1198 * @brief Set the SDA setup time when operating as a slave transmitter.
1199 * @note The register IC_SDA_SETUP can only be programmed when the I2C is disabled (ENABLE = 0).
1200 * The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the
1201 * user requires 10 ic_clk periods of setup time, they should program a value of 11.
1202 *
1203 * \rst
1204 * +----------------------+-----------------------------------+
1205 * | Register | BitsName |
1206 * +======================+===================================+
1207 * | IC_SDA_SETUP | SDA_SETUP |
1208 * +----------------------+-----------------------------------+
1209 * \endrst
1210 *
1211 * @param I2Cx I2C instance.
1212 * @param time SDA data setup time in units of ic_clk period, range between 2 ~ 0xFF.
1213 * @retval None.
1214 */
1215 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1216 {
1217 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP, time);
1218 }
1219
1220 /**
1221 * @brief Get the SDA setup time when operating as a slave transmitter.
1222 *
1223 * \rst
1224 * +----------------------+-----------------------------------+
1225 * | Register | BitsName |
1226 * +======================+===================================+
1227 * | IC_SDA_SETUP | SDA_SETUP |
1228 * +----------------------+-----------------------------------+
1229 * \endrst
1230 *
1231 * @param I2Cx I2C instance.
1232 * @retval Value range between 0x02 and 0xFF.
1233 */
1234 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1235 {
1236 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP));
1237 }
1238
1239 /**
1240 * @brief Set threshold of entries (or below) that trigger the TX_EMPTY interrupt
1241 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1242 *
1243 * \rst
1244 * +----------------------+-----------------------------------+
1245 * | Register | BitsName |
1246 * +======================+===================================+
1247 * | IC_TX_TL | TX_TL |
1248 * +----------------------+-----------------------------------+
1249 * \endrst
1250 *
1251 * @param I2Cx I2C instance
1252 * @param threshold This parameter can be one of the following values:
1253 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1254 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1255 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1256 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1257 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1258 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1259 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1260 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1261 * @retval None.
1262 */
1263 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1264 {
1265 WRITE_REG(I2Cx->TX_TL, threshold);
1266 }
1267
1268 /**
1269 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
1270 *
1271 * \rst
1272 * +----------------------+-----------------------------------+
1273 * | Register | BitsName |
1274 * +======================+===================================+
1275 * | IC_TX_TL | TX_TL |
1276 * +----------------------+-----------------------------------+
1277 * \endrst
1278 *
1279 * @param I2Cx I2C instance
1280 * @retval Returned value can be one of the following values:
1281 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1282 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1283 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1284 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1285 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1286 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1287 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1288 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1289 */
1290 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1291 {
1292 return (uint32_t)(READ_BITS(I2Cx->TX_TL, I2C_TX_TL_TXTL));
1293 }
1294
1295 /**
1296 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
1297 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1298 *
1299 * \rst
1300 * +----------------------+-----------------------------------+
1301 * | Register | BitsName |
1302 * +======================+===================================+
1303 * | IC_RX_TL | RX_TL |
1304 * +----------------------+-----------------------------------+
1305 * \endrst
1306 *
1307 * @param I2Cx I2C instance
1308 * @param threshold This parameter can be one of the following values:
1309 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1310 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1311 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1312 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1313 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1314 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1315 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1316 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1317 * @retval None.
1318 */
1319 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1320 {
1321 WRITE_REG(I2Cx->RX_TL, threshold);
1322 }
1323
1324 /**
1325 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
1326 *
1327 * \rst
1328 * +----------------------+-----------------------------------+
1329 * | Register | BitsName |
1330 * +======================+===================================+
1331 * | IC_RX_TL | RX_TL |
1332 * +----------------------+-----------------------------------+
1333 * \endrst
1334 *
1335 * @param I2Cx I2C instance
1336 * @retval Returned value can be one of the following values:
1337 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1338 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1339 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1340 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1341 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1342 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1343 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1344 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1345 */
1346 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1347 {
1348 return (uint32_t)(READ_BITS(I2Cx->RX_TL, I2C_RX_TL_RXTL));
1349 }
1350
1351 /**
1352 * @brief Get FIFO Transmission Level
1353 *
1354 * \rst
1355 * +----------------------+-----------------------------------+
1356 * | Register | BitsName |
1357 * +======================+===================================+
1358 * | IC_TXFLR | TXFLR |
1359 * +----------------------+-----------------------------------+
1360 * \endrst
1361 *
1362 * @param I2Cx I2C instance
1363 * @retval Value range between 0x0 and 0x8.
1364 */
1365 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1366 {
1367 return (uint32_t)(READ_BITS(I2Cx->TXFLR, I2C_TXFLR_TXFLR));
1368 }
1369
1370 /**
1371 * @brief Get FIFO reception Level
1372 *
1373 * \rst
1374 * +----------------------+-----------------------------------+
1375 * | Register | BitsName |
1376 * +======================+===================================+
1377 * | IC_RXFLR | RXFLR |
1378 * +----------------------+-----------------------------------+
1379 * \endrst
1380 *
1381 * @param I2Cx I2C instance
1382 * @retval Value range between 0x0 and 0x8.
1383 */
1384 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1385 {
1386 return (uint32_t)(READ_BITS(I2Cx->RXFLR, I2C_RXFLR_RXFLR));
1387 }
1388
1389 /**
1390 * @brief Enable DMA reception requests.
1391 *
1392 * \rst
1393 * +----------------------+-----------------------------------+
1394 * | Register | BitsName |
1395 * +======================+===================================+
1396 * | IC_ENABLE | ABORT |
1397 * +----------------------+-----------------------------------+
1398 * \endrst
1399 *
1400 * @param I2Cx I2C instance.
1401 * @retval None.
1402 */
1403 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1404 {
1405 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT);
1406 }
1407
1408 /**
1409 * @brief Check if DMA reception requests are enabled or disabled.
1410 *
1411 * \rst
1412 * +----------------------+-----------------------------------+
1413 * | Register | BitsName |
1414 * +======================+===================================+
1415 * | IC_ENABLE | ABORT |
1416 * +----------------------+-----------------------------------+
1417 * \endrst
1418 *
1419 * @param I2Cx I2C instance.
1420 * @retval State of bit (1 or 0).
1421 */
1422 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1423 {
1424 return (READ_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT) == (I2C_ENABLE_ABORT));
1425 }
1426
1427 /**
1428 * @brief Get the transmit abort source.
1429 * @note This can be used to retrieve source of TX_ABRT interrupt.
1430 *
1431 * \rst
1432 * +----------------------+-----------------------------------+
1433 * | Register | BitsName |
1434 * +======================+===================================+
1435 * | IC_TX_ABRT_SOURCE | ABRT_USER_ABRT |
1436 * +----------------------+-----------------------------------+
1437 * \endrst
1438 * IC_TX_ABRT_SOURCE | ABRT_SLVRD_INTX
1439 * IC_TX_ABRT_SOURCE | ABRT_SLV_ARBLOST
1440 * IC_TX_ABRT_SOURCE | ABRT_SLVFLUSH_TXFIFO
1441 * IC_TX_ABRT_SOURCE | ABRT_ARB_LOST
1442 * IC_TX_ABRT_SOURCE | ABRT_MST_DIS
1443 * IC_TX_ABRT_SOURCE | ABRT_10B_RD_NORSTRT
1444 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_NORSTRT
1445 * IC_TX_ABRT_SOURCE | ABRT_HS_NORSTRT
1446 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_ACKDET
1447 * IC_TX_ABRT_SOURCE | ABRT_HS_ACKDET
1448 * IC_TX_ABRT_SOURCE | ABRT_GCALL_READ
1449 * IC_TX_ABRT_SOURCE | ABRT_GCALL_NOACK
1450 * IC_TX_ABRT_SOURCE | ABRT_TXDATA_NOACK
1451 * IC_TX_ABRT_SOURCE | ABRT_10ADDR2_NOACK
1452 * IC_TX_ABRT_SOURCE | ABRT_10ADDR1_NOACK
1453 * IC_TX_ABRT_SOURCE | ABRT_7B_ADDR_NOACK
1454 *
1455 * @param I2Cx I2C instance
1456 * @retval Returned value can be a combination of the following values:
1457 * @arg @ref LL_I2C_ABRT_USER_ABRT
1458 * @arg @ref LL_I2C_ABRT_SLVRD_INTX
1459 * @arg @ref LL_I2C_ABRT_SLV_ARBLOST
1460 * @arg @ref LL_I2C_ABRT_SLVFLUSH_TXFIFO
1461 * @arg @ref LL_I2C_ABRT_ARB_LOST
1462 * @arg @ref LL_I2C_ABRT_MST_DIS
1463 * @arg @ref LL_I2C_ABRT_10B_RD_NORSTRT
1464 * @arg @ref LL_I2C_ABRT_SBYTE_NORSTRT
1465 * @arg @ref LL_I2C_ABRT_HS_NORSTRT
1466 * @arg @ref LL_I2C_ABRT_SBYTE_ACKDET
1467 * @arg @ref LL_I2C_ABRT_HS_ACKDET
1468 * @arg @ref LL_I2C_ABRT_GCALL_READ
1469 * @arg @ref LL_I2C_ABRT_GCALL_NOACK
1470 * @arg @ref LL_I2C_ABRT_TXDATA_NOACK
1471 * @arg @ref LL_I2C_ABRT_10ADDR2_NOACK
1472 * @arg @ref LL_I2C_ABRT_10ADDR1_NOACK
1473 * @arg @ref LL_I2C_ABRT_7B_ADDR_NOACK
1474 *
1475 * @note @arg @ref LL_I2C_ABRT_TX_FLUSH_CNT can be used as a mask to get the
1476 * number of Tx FIFO Data Commands which are flushed due to TX_ABRT
1477 * interrupt.
1478 */
1479 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1480 {
1481 return (uint32_t)(READ_REG(I2Cx->TX_ABRT_SOURCE) & (~I2C_TX_ABRT_SRC_TX_FLUSH_CNT));
1482 }
1483
1484 /**
1485 * @brief Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
1486 *
1487 * \rst
1488 * +----------------------+-----------------------------------+
1489 * | Register | BitsName |
1490 * +======================+===================================+
1491 * | IC_TX_ABRT_SOURCE | TX_FLUSH_CNT |
1492 * +----------------------+-----------------------------------+
1493 * \endrst
1494 *
1495 * @param I2Cx I2C instance
1496 * @retval Tx flush count.
1497 */
1498 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1499 {
1500 return (uint32_t)(READ_BITS(I2Cx->TX_ABRT_SOURCE, I2C_TX_ABRT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos);
1501 }
1502
1503 /** @} */
1504
1505 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Enable specified interrupts.
1511 *
1512 * \rst
1513 * +----------------------+-----------------------------------+
1514 * | Register | BitsName |
1515 * +======================+===================================+
1516 * | INTR_MASK | INTR_MASK_GEN_CALL |
1517 * +----------------------+-----------------------------------+
1518 * \endrst
1519 * INTR_MASK | INTR_MASK_START_DET
1520 * INTR_MASK | INTR_MASK_STOP_DET
1521 * INTR_MASK | INTR_MASK_ACTIVITY
1522 * INTR_MASK | INTR_MASK_RX_DONE
1523 * INTR_MASK | INTR_MASK_TX_ABRT
1524 * INTR_MASK | INTR_MASK_RD_REQ
1525 * INTR_MASK | INTR_MASK_TX_EMPTY
1526 * INTR_MASK | INTR_MASK_TX_OVER
1527 * INTR_MASK | INTR_MASK_RX_FULL
1528 * INTR_MASK | INTR_MASK_RX_OVER
1529 * INTR_MASK | INTR_MASK_RX_UNDER
1530 *
1531 * @param I2Cx I2C instance.
1532 * @param mask This parameter can be a combination of the following values:
1533 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1534 * @arg @ref LL_I2C_INTR_MASK_START_DET
1535 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1536 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1537 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1538 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1539 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1540 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1541 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1542 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1543 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1544 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1545 * @retval None.
1546 */
1547 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1548 {
1549 SET_BITS(I2Cx->INTR_MASK, mask);
1550 }
1551
1552 /**
1553 * @brief Disable specified interrupts.
1554 *
1555 * \rst
1556 * +----------------------+-----------------------------------+
1557 * | Register | BitsName |
1558 * +======================+===================================+
1559 * | INTR_MASK | INTR_MASK_GEN_CALL |
1560 * +----------------------+-----------------------------------+
1561 * \endrst
1562 * INTR_MASK | INTR_MASK_START_DET
1563 * INTR_MASK | INTR_MASK_STOP_DET
1564 * INTR_MASK | INTR_MASK_ACTIVITY
1565 * INTR_MASK | INTR_MASK_RX_DONE
1566 * INTR_MASK | INTR_MASK_TX_ABRT
1567 * INTR_MASK | INTR_MASK_RD_REQ
1568 * INTR_MASK | INTR_MASK_TX_EMPTY
1569 * INTR_MASK | INTR_MASK_TX_OVER
1570 * INTR_MASK | INTR_MASK_RX_FULL
1571 * INTR_MASK | INTR_MASK_RX_OVER
1572 * INTR_MASK | INTR_MASK_RX_UNDER
1573 *
1574 * @param I2Cx I2C instance.
1575 * @param mask This parameter can be a combination of the following values:
1576 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1577 * @arg @ref LL_I2C_INTR_MASK_START_DET
1578 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1579 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1580 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1581 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1582 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1583 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1584 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1585 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1586 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1587 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1588 * @retval None.
1589 */
1590 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1591 {
1592 CLEAR_BITS(I2Cx->INTR_MASK, mask);
1593 }
1594
1595 /**
1596 * @brief Check if the specified interrupts are enabled or disabled.
1597 *
1598 * \rst
1599 * +----------------------+-----------------------------------+
1600 * | Register | BitsName |
1601 * +======================+===================================+
1602 * | INTR_MASK | INTR_MASK_GEN_CALL |
1603 * +----------------------+-----------------------------------+
1604 * \endrst
1605 * INTR_MASK | INTR_MASK_START_DET
1606 * INTR_MASK | INTR_MASK_STOP_DET
1607 * INTR_MASK | INTR_MASK_ACTIVITY
1608 * INTR_MASK | INTR_MASK_RX_DONE
1609 * INTR_MASK | INTR_MASK_TX_ABRT
1610 * INTR_MASK | INTR_MASK_RD_REQ
1611 * INTR_MASK | INTR_MASK_TX_EMPTY
1612 * INTR_MASK | INTR_MASK_TX_OVER
1613 * INTR_MASK | INTR_MASK_RX_FULL
1614 * INTR_MASK | INTR_MASK_RX_OVER
1615 * INTR_MASK | INTR_MASK_RX_UNDER
1616 *
1617 * @param I2Cx I2C instance.
1618 * @param mask This parameter can be a combination of the following values:
1619 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1620 * @arg @ref LL_I2C_INTR_MASK_START_DET
1621 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1622 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1623 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1624 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1625 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1626 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1627 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1628 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1629 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1630 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1631 * @retval State of bit (1 or 0).
1632 */
1633 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1634 {
1635 return (READ_BITS(I2Cx->INTR_MASK, mask) == (mask));
1636 }
1637
1638 /**
1639 * @brief Enable MASTER_ON_HOLD interrupt.
1640 *
1641 * \rst
1642 * +----------------------+-----------------------------------+
1643 * | Register | BitsName |
1644 * +======================+===================================+
1645 * | INTR_MASK | MST_ON_HOLD |
1646 * +----------------------+-----------------------------------+
1647 * \endrst
1648 *
1649 * @param I2Cx I2C instance.
1650 * @retval None.
1651 */
1652 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1653 {
1654 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1655 }
1656
1657 /**
1658 * @brief Disable MASTER_ON_HOLD interrupt.
1659 *
1660 * \rst
1661 * +----------------------+-----------------------------------+
1662 * | Register | BitsName |
1663 * +======================+===================================+
1664 * | INTR_MASK | MST_ON_HOLD |
1665 * +----------------------+-----------------------------------+
1666 * \endrst
1667 *
1668 * @param I2Cx I2C instance.
1669 * @retval None.
1670 */
1671 __STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
1672 {
1673 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1674 }
1675
1676 /**
1677 * @brief Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
1678 *
1679 * \rst
1680 * +----------------------+-----------------------------------+
1681 * | Register | BitsName |
1682 * +======================+===================================+
1683 * | INTR_MASK | MST_ON_HOLD |
1684 * +----------------------+-----------------------------------+
1685 * \endrst
1686 *
1687 * @param I2Cx I2C instance.
1688 * @retval State of bit (1 or 0).
1689 */
1690 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1691 {
1692 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
1693 }
1694
1695 /**
1696 * @brief Enable RESTART_DET interrupt.
1697 *
1698 * \rst
1699 * +----------------------+-----------------------------------+
1700 * | Register | BitsName |
1701 * +======================+===================================+
1702 * | INTR_MASK | RESTART_DET |
1703 * +----------------------+-----------------------------------+
1704 * \endrst
1705 *
1706 * @param I2Cx I2C instance.
1707 * @retval None.
1708 */
1709 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1710 {
1711 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1712 }
1713
1714 /**
1715 * @brief Disable RESTART_DET interrupt.
1716 *
1717 * \rst
1718 * +----------------------+-----------------------------------+
1719 * | Register | BitsName |
1720 * +======================+===================================+
1721 * | INTR_MASK | RESTART_DET |
1722 * +----------------------+-----------------------------------+
1723 * \endrst
1724 *
1725 * @param I2Cx I2C instance.
1726 * @retval None.
1727 */
1728 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1729 {
1730 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1731 }
1732
1733 /**
1734 * @brief Check if the RESTART_DET Interrupt is enabled or disabled.
1735 *
1736 * \rst
1737 * +----------------------+-----------------------------------+
1738 * | Register | BitsName |
1739 * +======================+===================================+
1740 * | INTR_MASK | RESTART_DET |
1741 * +----------------------+-----------------------------------+
1742 * \endrst
1743 *
1744 * @param I2Cx I2C instance.
1745 * @retval State of bit (1 or 0).
1746 */
1747 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1748 {
1749 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
1750 }
1751
1752 /**
1753 * @brief Enable GEN_CALL interrupt.
1754 *
1755 * \rst
1756 * +----------------------+-----------------------------------+
1757 * | Register | BitsName |
1758 * +======================+===================================+
1759 * | INTR_MASK | GEN_CALL |
1760 * +----------------------+-----------------------------------+
1761 * \endrst
1762 *
1763 * @param I2Cx I2C instance.
1764 * @retval None.
1765 */
1766 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1767 {
1768 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1769 }
1770
1771 /**
1772 * @brief Disable GEN_CALL interrupt.
1773 *
1774 * \rst
1775 * +----------------------+-----------------------------------+
1776 * | Register | BitsName |
1777 * +======================+===================================+
1778 * | INTR_MASK | GEN_CALL |
1779 * +----------------------+-----------------------------------+
1780 * \endrst
1781 *
1782 * @param I2Cx I2C instance.
1783 * @retval None.
1784 */
1785 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1786 {
1787 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1788 }
1789
1790 /**
1791 * @brief Check if GEN_CALL interrupt is enabled or disabled.
1792 *
1793 * \rst
1794 * +----------------------+-----------------------------------+
1795 * | Register | BitsName |
1796 * +======================+===================================+
1797 * | INTR_MASK | GEN_CALL |
1798 * +----------------------+-----------------------------------+
1799 * \endrst
1800 *
1801 * @param I2Cx I2C instance.
1802 * @retval State of bit (1 or 0).
1803 */
1804 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1805 {
1806 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
1807 }
1808
1809 /**
1810 * @brief Enable START_DET received interrupt.
1811 *
1812 * \rst
1813 * +----------------------+-----------------------------------+
1814 * | Register | BitsName |
1815 * +======================+===================================+
1816 * | INTR_MASK | START_DET |
1817 * +----------------------+-----------------------------------+
1818 * \endrst
1819 *
1820 * @param I2Cx I2C instance.
1821 * @retval None.
1822 */
1823 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1824 {
1825 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1826 }
1827
1828 /**
1829 * @brief Disable START_DET received interrupt.
1830 *
1831 * \rst
1832 * +----------------------+-----------------------------------+
1833 * | Register | BitsName |
1834 * +======================+===================================+
1835 * | INTR_MASK | START_DET |
1836 * +----------------------+-----------------------------------+
1837 * \endrst
1838 *
1839 * @param I2Cx I2C instance.
1840 * @retval None.
1841 */
1842 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1843 {
1844 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1845 }
1846
1847 /**
1848 * @brief Check if START_DET received interrupt is enabled or disabled.
1849 *
1850 * \rst
1851 * +----------------------+-----------------------------------+
1852 * | Register | BitsName |
1853 * +======================+===================================+
1854 * | INTR_MASK | START_DET |
1855 * +----------------------+-----------------------------------+
1856 * \endrst
1857 *
1858 * @param I2Cx I2C instance.
1859 * @retval State of bit (1 or 0).
1860 */
1861 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1862 {
1863 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
1864 }
1865
1866 /**
1867 * @brief Enable STOP_DET interrupt.
1868 *
1869 * \rst
1870 * +----------------------+-----------------------------------+
1871 * | Register | BitsName |
1872 * +======================+===================================+
1873 * | INTR_MASK | STOP_DET |
1874 * +----------------------+-----------------------------------+
1875 * \endrst
1876 *
1877 * @param I2Cx I2C instance.
1878 * @retval None.
1879 */
1880 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1881 {
1882 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1883 }
1884
1885 /**
1886 * @brief Disable STOP_DET interrupt.
1887 *
1888 * \rst
1889 * +----------------------+-----------------------------------+
1890 * | Register | BitsName |
1891 * +======================+===================================+
1892 * | INTR_MASK | STOP_DET |
1893 * +----------------------+-----------------------------------+
1894 * \endrst
1895 *
1896 * @param I2Cx I2C instance.
1897 * @retval None.
1898 */
1899 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1900 {
1901 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1902 }
1903
1904 /**
1905 * @brief Check if STOP_DET interrupt is enabled or disabled.
1906 *
1907 * \rst
1908 * +----------------------+-----------------------------------+
1909 * | Register | BitsName |
1910 * +======================+===================================+
1911 * | INTR_MASK | STOP_DET |
1912 * +----------------------+-----------------------------------+
1913 * \endrst
1914 *
1915 * @param I2Cx I2C instance.
1916 * @retval State of bit (1 or 0).
1917 */
1918 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1919 {
1920 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
1921 }
1922
1923 /**
1924 * @brief Enable ACTIVITY interrupt.
1925 *
1926 * \rst
1927 * +----------------------+-----------------------------------+
1928 * | Register | BitsName |
1929 * +======================+===================================+
1930 * | INTR_MASK | ACTIVITY |
1931 * +----------------------+-----------------------------------+
1932 * \endrst
1933 *
1934 * @param I2Cx I2C instance.
1935 * @retval None.
1936 */
1937 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1938 {
1939 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1940 }
1941
1942 /**
1943 * @brief Disable ACTIVITY interrupt.
1944 *
1945 * \rst
1946 * +----------------------+-----------------------------------+
1947 * | Register | BitsName |
1948 * +======================+===================================+
1949 * | INTR_MASK | ACTIVITY |
1950 * +----------------------+-----------------------------------+
1951 * \endrst
1952 *
1953 * @param I2Cx I2C instance.
1954 * @retval None.
1955 */
1956 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1957 {
1958 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1959 }
1960
1961 /**
1962 * @brief Check if ACTIVITY interrupt is enabled or disabled.
1963 *
1964 * \rst
1965 * +----------------------+-----------------------------------+
1966 * | Register | BitsName |
1967 * +======================+===================================+
1968 * | INTR_MASK | ACTIVITY |
1969 * +----------------------+-----------------------------------+
1970 * \endrst
1971 *
1972 * @param I2Cx I2C instance.
1973 * @retval State of bit (1 or 0).
1974 */
1975 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1976 {
1977 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
1978 }
1979
1980 /**
1981 * @brief Enable RX_DONE interrupt.
1982 *
1983 * \rst
1984 * +----------------------+-----------------------------------+
1985 * | Register | BitsName |
1986 * +======================+===================================+
1987 * | INTR_MASK | RX_DONE |
1988 * +----------------------+-----------------------------------+
1989 * \endrst
1990 *
1991 * @param I2Cx I2C instance.
1992 * @retval State of bit (1 or 0).
1993 */
1994 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
1995 {
1996 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1997 }
1998
1999 /**
2000 * @brief Disable RX_DONE interrupt.
2001 *
2002 * \rst
2003 * +----------------------+-----------------------------------+
2004 * | Register | BitsName |
2005 * +======================+===================================+
2006 * | INTR_MASK | RX_DONE |
2007 * +----------------------+-----------------------------------+
2008 * \endrst
2009 *
2010 * @param I2Cx I2C instance.
2011 * @retval None.
2012 */
2013 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
2014 {
2015 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
2016 }
2017
2018 /**
2019 * @brief Check if RX_DONE interrupt is enabled or disabled.
2020 *
2021 * \rst
2022 * +----------------------+-----------------------------------+
2023 * | Register | BitsName |
2024 * +======================+===================================+
2025 * | INTR_MASK | RX_DONE |
2026 * +----------------------+-----------------------------------+
2027 * \endrst
2028 *
2029 * @param I2Cx I2C instance.
2030 * @retval State of bit (1 or 0).
2031 */
2032 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
2033 {
2034 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2035 }
2036
2037 /**
2038 * @brief Enable TX_ABRT interrupt.
2039 *
2040 * \rst
2041 * +----------------------+-----------------------------------+
2042 * | Register | BitsName |
2043 * +======================+===================================+
2044 * | INTR_MASK | TX_ABRT |
2045 * +----------------------+-----------------------------------+
2046 * \endrst
2047 *
2048 * @param I2Cx I2C instance.
2049 * @retval None.
2050 */
2051 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
2052 {
2053 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
2054 }
2055
2056 /**
2057 * @brief Disable TX_ABRT interrupt.
2058 *
2059 * \rst
2060 * +----------------------+-----------------------------------+
2061 * | Register | BitsName |
2062 * +======================+===================================+
2063 * | INTR_MASK | TX_ABRT |
2064 * +----------------------+-----------------------------------+
2065 * \endrst
2066 *
2067 * @param I2Cx I2C instance.
2068 * @retval None.
2069 */
2070 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
2071 {
2072 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
2073 }
2074
2075 /**
2076 * @brief Check if TX_ABRT interrupt is enabled or disabled.
2077 *
2078 * \rst
2079 * +----------------------+-----------------------------------+
2080 * | Register | BitsName |
2081 * +======================+===================================+
2082 * | INTR_MASK | TX_ABRT |
2083 * +----------------------+-----------------------------------+
2084 * \endrst
2085 *
2086 * @param I2Cx I2C instance.
2087 * @retval None.
2088 */
2089 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
2090 {
2091 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2092 }
2093
2094 /**
2095 * @brief Enable RD_REQ interrupt.
2096 *
2097 * \rst
2098 * +----------------------+-----------------------------------+
2099 * | Register | BitsName |
2100 * +======================+===================================+
2101 * | INTR_MASK | RD_REQ |
2102 * +----------------------+-----------------------------------+
2103 * \endrst
2104 *
2105 * @param I2Cx I2C instance.
2106 * @retval None.
2107 */
2108 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
2109 {
2110 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
2111 }
2112
2113 /**
2114 * @brief Disable RD_REQ interrupt.
2115 *
2116 * \rst
2117 * +----------------------+-----------------------------------+
2118 * | Register | BitsName |
2119 * +======================+===================================+
2120 * | INTR_MASK | RD_REQ |
2121 * +----------------------+-----------------------------------+
2122 * \endrst
2123 *
2124 * @param I2Cx I2C instance.
2125 * @retval None.
2126 */
2127 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
2128 {
2129 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
2130 }
2131
2132 /**
2133 * @brief Check if RD_REQ interrupt is enabled or disabled.
2134 *
2135 * \rst
2136 * +----------------------+-----------------------------------+
2137 * | Register | BitsName |
2138 * +======================+===================================+
2139 * | INTR_MASK | RD_REQ |
2140 * +----------------------+-----------------------------------+
2141 * \endrst
2142 *
2143 * @param I2Cx I2C instance.
2144 * @retval State of bit (1 or 0).
2145 */
2146 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
2147 {
2148 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2149 }
2150
2151 /**
2152 * @brief Enable TX_EMPTY interrupt.
2153 *
2154 * \rst
2155 * +----------------------+-----------------------------------+
2156 * | Register | BitsName |
2157 * +======================+===================================+
2158 * | INTR_MASK | TX_EMPTY |
2159 * +----------------------+-----------------------------------+
2160 * \endrst
2161 *
2162 * @param I2Cx I2C instance.
2163 * @retval None.
2164 */
2165 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
2166 {
2167 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
2168 }
2169
2170 /**
2171 * @brief Disable TX_EMPTY interrupt.
2172 *
2173 * \rst
2174 * +----------------------+-----------------------------------+
2175 * | Register | BitsName |
2176 * +======================+===================================+
2177 * | INTR_MASK | TX_EMPTY |
2178 * +----------------------+-----------------------------------+
2179 * \endrst
2180 *
2181 * @param I2Cx I2C instance.
2182 * @retval None.
2183 */
2184 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
2185 {
2186 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
2187 }
2188
2189 /**
2190 * @brief Check if TX_EMPTY interrupt is enabled or disabled.
2191 *
2192 * \rst
2193 * +----------------------+-----------------------------------+
2194 * | Register | BitsName |
2195 * +======================+===================================+
2196 * | INTR_MASK | TX_EMPTY |
2197 * +----------------------+-----------------------------------+
2198 * \endrst
2199 *
2200 * @param I2Cx I2C instance.
2201 * @retval State of bit (1 or 0).
2202 */
2203 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
2204 {
2205 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2206 }
2207
2208 /**
2209 * @brief Enable TX_OVER interrupt.
2210 *
2211 * \rst
2212 * +----------------------+-----------------------------------+
2213 * | Register | BitsName |
2214 * +======================+===================================+
2215 * | INTR_MASK | TX_OVER |
2216 * +----------------------+-----------------------------------+
2217 * \endrst
2218 *
2219 * @param I2Cx I2C instance.
2220 * @retval None.
2221 */
2222 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
2223 {
2224 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
2225 }
2226
2227 /**
2228 * @brief Disable TX_OVER interrupt.
2229 *
2230 * \rst
2231 * +----------------------+-----------------------------------+
2232 * | Register | BitsName |
2233 * +======================+===================================+
2234 * | INTR_MASK | TX_OVER |
2235 * +----------------------+-----------------------------------+
2236 * \endrst
2237 *
2238 * @param I2Cx I2C instance.
2239 * @retval None.
2240 */
2241 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
2242 {
2243 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
2244 }
2245
2246 /**
2247 * @brief Check if TX_OVER interrupt is enabled or disabled.
2248 *
2249 * \rst
2250 * +----------------------+-----------------------------------+
2251 * | Register | BitsName |
2252 * +======================+===================================+
2253 * | INTR_MASK | TX_OVER |
2254 * +----------------------+-----------------------------------+
2255 * \endrst
2256 *
2257 * @param I2Cx I2C instance.
2258 * @retval State of bit (1 or 0).
2259 */
2260 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
2261 {
2262 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2263 }
2264
2265 /**
2266 * @brief Enable RX_FULL interrupt.
2267 *
2268 * \rst
2269 * +----------------------+-----------------------------------+
2270 * | Register | BitsName |
2271 * +======================+===================================+
2272 * | INTR_MASK | RX_FULL |
2273 * +----------------------+-----------------------------------+
2274 * \endrst
2275 *
2276 * @param I2Cx I2C instance.
2277 * @retval None.
2278 */
2279 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
2280 {
2281 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
2282 }
2283
2284 /**
2285 * @brief Disable RX_FULL interrupt.
2286 *
2287 * \rst
2288 * +----------------------+-----------------------------------+
2289 * | Register | BitsName |
2290 * +======================+===================================+
2291 * | INTR_MASK | RX_FULL |
2292 * +----------------------+-----------------------------------+
2293 * \endrst
2294 *
2295 * @param I2Cx I2C instance.
2296 * @retval None.
2297 */
2298 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
2299 {
2300 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
2301 }
2302
2303 /**
2304 * @brief Check if RX_FULL interrupt is enabled or disabled.
2305 *
2306 * \rst
2307 * +----------------------+-----------------------------------+
2308 * | Register | BitsName |
2309 * +======================+===================================+
2310 * | INTR_MASK | RX_FULL |
2311 * +----------------------+-----------------------------------+
2312 * \endrst
2313 *
2314 * @param I2Cx I2C instance.
2315 * @retval None.
2316 */
2317 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
2318 {
2319 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2320 }
2321
2322 /**
2323 * @brief Enable RX_OVER interrupt.
2324 *
2325 * \rst
2326 * +----------------------+-----------------------------------+
2327 * | Register | BitsName |
2328 * +======================+===================================+
2329 * | INTR_MASK | RX_OVER |
2330 * +----------------------+-----------------------------------+
2331 * \endrst
2332 *
2333 * @param I2Cx I2C instance.
2334 * @retval None.
2335 */
2336 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
2337 {
2338 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
2339 }
2340
2341 /**
2342 * @brief Disable RX_OVER interrupt.
2343 *
2344 * \rst
2345 * +----------------------+-----------------------------------+
2346 * | Register | BitsName |
2347 * +======================+===================================+
2348 * | INTR_MASK | RX_OVER |
2349 * +----------------------+-----------------------------------+
2350 * \endrst
2351 *
2352 * @param I2Cx I2C instance.
2353 * @retval None.
2354 */
2355 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
2356 {
2357 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
2358 }
2359
2360 /**
2361 * @brief Check if RX_OVER interrupt is enabled or disabled.
2362 *
2363 * \rst
2364 * +----------------------+-----------------------------------+
2365 * | Register | BitsName |
2366 * +======================+===================================+
2367 * | INTR_MASK | RX_OVER |
2368 * +----------------------+-----------------------------------+
2369 * \endrst
2370 *
2371 * @param I2Cx I2C instance.
2372 * @retval None.
2373 */
2374 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
2375 {
2376 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2377 }
2378
2379 /**
2380 * @brief Enable RX_UNDER interrupt.
2381 *
2382 * \rst
2383 * +----------------------+-----------------------------------+
2384 * | Register | BitsName |
2385 * +======================+===================================+
2386 * | INTR_MASK | RX_UNDER |
2387 * +----------------------+-----------------------------------+
2388 * \endrst
2389 *
2390 * @param I2Cx I2C instance.
2391 * @retval None.
2392 */
2393 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2394 {
2395 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2396 }
2397
2398 /**
2399 * @brief Disable RX_UNDER interrupt.
2400 *
2401 * \rst
2402 * +----------------------+-----------------------------------+
2403 * | Register | BitsName |
2404 * +======================+===================================+
2405 * | INTR_MASK | RX_UNDER |
2406 * +----------------------+-----------------------------------+
2407 * \endrst
2408 *
2409 * @param I2Cx I2C instance.
2410 * @retval None.
2411 */
2412 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2413 {
2414 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2415 }
2416
2417 /**
2418 * @brief Check if RX_UNDER interrupt is enabled or disabled.
2419 *
2420 * \rst
2421 * +----------------------+-----------------------------------+
2422 * | Register | BitsName |
2423 * +======================+===================================+
2424 * | INTR_MASK | RX_UNDER |
2425 * +----------------------+-----------------------------------+
2426 * \endrst
2427 *
2428 * @param I2Cx I2C instance.
2429 * @retval None.
2430 */
2431 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2432 {
2433 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2434 }
2435
2436 /** @} */
2437
2438 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
2439 * @{
2440 */
2441
2442 /**
2443 * @brief Get I2C interrupt flags
2444 *
2445 * \rst
2446 * +----------------------+-----------------------------------+
2447 * | Register | BitsName |
2448 * +======================+===================================+
2449 * | IC_INTR_STAT | MST_ON_HOLD |
2450 * +----------------------+-----------------------------------+
2451 * \endrst
2452 * IC_INTR_STAT | RESTART_DET
2453 * IC_INTR_STAT | GEN_CALL
2454 * IC_INTR_STAT | START_DET
2455 * IC_INTR_STAT | STOP_DET
2456 * IC_INTR_STAT | ACTIVITY
2457 * IC_INTR_STAT | RX_DONE
2458 * IC_INTR_STAT | TX_ABRT
2459 * IC_INTR_STAT | RD_REQ
2460 * IC_INTR_STAT | TX_EMPTY
2461 * IC_INTR_STAT | TX_OVER
2462 * IC_INTR_STAT | RX_FULL
2463 * IC_INTR_STAT | RX_OVER
2464 * IC_INTR_STAT | RX_UNDER
2465 *
2466 * @param I2Cx I2C instance.
2467 * @retval Returned value can be one or combination of the following values:
2468 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2469 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2470 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2471 * @arg @ref LL_I2C_INTR_STAT_START_DET
2472 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2473 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2474 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2475 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2476 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2477 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2478 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2479 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2480 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2481 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2482 */
2483 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2484 {
2485 return (uint32_t)(READ_REG(I2Cx->INTR_STAT));
2486 }
2487
2488 /**
2489 * @brief Get I2C RAW interrupt flags
2490 *
2491 * \rst
2492 * +----------------------+-----------------------------------+
2493 * | Register | BitsName |
2494 * +======================+===================================+
2495 * | IC_RAW_INTR_STAT | RAW_MST_ON_HOLD |
2496 * +----------------------+-----------------------------------+
2497 * \endrst
2498 * IC_RAW_INTR_STAT | RAW_RESTART_DET
2499 * IC_RAW_INTR_STAT | RAW_GEN_CALL
2500 * IC_RAW_INTR_STAT | RAW_START_DET
2501 * IC_RAW_INTR_STAT | RAW_STOP_DET
2502 * IC_RAW_INTR_STAT | RAW_ACTIVITY
2503 * IC_RAW_INTR_STAT | RAW_RX_DONE
2504 * IC_RAW_INTR_STAT | RAW_TX_ABRT
2505 * IC_RAW_INTR_STAT | RAW_RD_REQ
2506 * IC_RAW_INTR_STAT | RAW_TX_EMPTY
2507 * IC_RAW_INTR_STAT | RAW_TX_OVER
2508 * IC_RAW_INTR_STAT | RAW_RX_FULL
2509 * IC_RAW_INTR_STAT | RAW_RX_OVER
2510 * IC_RAW_INTR_STAT | RAW_RX_UNDER
2511 *
2512 * @param I2Cx I2C instance.
2513 * @retval Returned value can be one or combination of the following values:
2514 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2515 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2516 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2517 * @arg @ref LL_I2C_INTR_STAT_START_DET
2518 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2519 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2520 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2521 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2522 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2523 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2524 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2525 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2526 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2527 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2528 */
2529 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2530 {
2531 return (uint32_t)(READ_REG(I2Cx->RAW_INTR_STAT));
2532 }
2533
2534 /**
2535 * @brief Indicate the status of MST_ON_HOLD flag.
2536 * @note RESET: Clear default value.
2537 * SET : When MST_ON_HOLD interrupt is actived.
2538 *
2539 * \rst
2540 * +----------------------+-----------------------------------+
2541 * | Register | BitsName |
2542 * +======================+===================================+
2543 * | RAW_INTR_STAT | MST_ON_HOLD |
2544 * +----------------------+-----------------------------------+
2545 * \endrst
2546 *
2547 * @param I2Cx I2C instance.
2548 * @retval State of bit (1 or 0).
2549 */
2550 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2551 {
2552 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2553 }
2554
2555 /**
2556 * @brief Indicate the status of RAW_MST_ON_HOLD flag.
2557 * @note RESET: Clear default value.
2558 * SET : When unmasked MST_ON_HOLD interrupt is actived.
2559 *
2560 * \rst
2561 * +----------------------+-----------------------------------+
2562 * | Register | BitsName |
2563 * +======================+===================================+
2564 * | IC_RAW_INTR_STAT | RAW_MST_ON_HOLD |
2565 * +----------------------+-----------------------------------+
2566 * \endrst
2567 *
2568 * @param I2Cx I2C instance.
2569 * @retval State of bit (1 or 0).
2570 */
2571 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2572 {
2573 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2574 }
2575
2576 /**
2577 * @brief Indicate the status of RESTART_DET flag.
2578 * @note RESET: Clear default value.
2579 * SET : When masked RESTART_DET interrupt is actived.
2580 *
2581 * \rst
2582 * +----------------------+-----------------------------------+
2583 * | Register | BitsName |
2584 * +======================+===================================+
2585 * | IC_INTR_STAT | RESTART_DET |
2586 * +----------------------+-----------------------------------+
2587 * \endrst
2588 *
2589 * @param I2Cx I2C instance.
2590 * @retval State of bit (1 or 0).
2591 */
2592 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2593 {
2594 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2595 }
2596
2597 /**
2598 * @brief Indicate the status of RAW_RESTART_DET flag.
2599 * @note RESET: Clear default value.
2600 * SET : When unmasked RESTART_DET interrupt is actived.
2601 *
2602 * \rst
2603 * +----------------------+-----------------------------------+
2604 * | Register | BitsName |
2605 * +======================+===================================+
2606 * | IC_RAW_INTR_STAT | RAW_RESTART_DET |
2607 * +----------------------+-----------------------------------+
2608 * \endrst
2609 *
2610 * @param I2Cx I2C instance.
2611 * @retval State of bit (1 or 0).
2612 */
2613 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2614 {
2615 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2616 }
2617
2618 /**
2619 * @brief Indicate the status of GEN_CALL flag.
2620 * @note RESET: Clear default value.
2621 * SET : When masked GEN_CALL interrupt is actived.
2622 *
2623 * \rst
2624 * +----------------------+-----------------------------------+
2625 * | Register | BitsName |
2626 * +======================+===================================+
2627 * | IC_INTR_STAT | GEN_CALL |
2628 * +----------------------+-----------------------------------+
2629 * \endrst
2630 *
2631 * @param I2Cx I2C instance.
2632 * @retval State of bit (1 or 0).
2633 */
2634 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2635 {
2636 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2637 }
2638
2639 /**
2640 * @brief Indicate the status of RAW_GEN_CALL flag.
2641 * @note RESET: Clear default value.
2642 * SET : When unmasked GEN_CALL interrupt is actived.
2643 *
2644 * \rst
2645 * +----------------------+-----------------------------------+
2646 * | Register | BitsName |
2647 * +======================+===================================+
2648 * | IC_RAW_INTR_STAT | RAW_GEN_CALL |
2649 * +----------------------+-----------------------------------+
2650 * \endrst
2651 *
2652 * @param I2Cx I2C instance.
2653 * @retval State of bit (1 or 0).
2654 */
2655 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2656 {
2657 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2658 }
2659
2660 /**
2661 * @brief Indicate the status of START_DET flag.
2662 * @note RESET: Clear default value.
2663 * SET : When masked START_DET interrupt is actived.
2664 *
2665 * \rst
2666 * +----------------------+-----------------------------------+
2667 * | Register | BitsName |
2668 * +======================+===================================+
2669 * | IC_INTR_STAT | START_DET |
2670 * +----------------------+-----------------------------------+
2671 * \endrst
2672 *
2673 * @param I2Cx I2C instance.
2674 * @retval State of bit (1 or 0).
2675 */
2676 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2677 {
2678 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2679 }
2680
2681 /**
2682 * @brief Indicate the status of RAW_START_DET flag.
2683 * @note RESET: Clear default value.
2684 * SET : When unmasked START_DET interrupt is actived.
2685 *
2686 * \rst
2687 * +----------------------+-----------------------------------+
2688 * | Register | BitsName |
2689 * +======================+===================================+
2690 * | IC_RAW_INTR_STAT | RAW_START_DET |
2691 * +----------------------+-----------------------------------+
2692 * \endrst
2693 *
2694 * @param I2Cx I2C instance.
2695 * @retval State of bit (1 or 0).
2696 */
2697 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2698 {
2699 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2700 }
2701
2702 /**
2703 * @brief Indicate the status of STOP_DET flag.
2704 * @note RESET: Clear default value.
2705 * SET : When masked STOP_DET interrupt is actived.
2706 *
2707 * \rst
2708 * +----------------------+-----------------------------------+
2709 * | Register | BitsName |
2710 * +======================+===================================+
2711 * | IC_INTR_STAT | STOP_DET |
2712 * +----------------------+-----------------------------------+
2713 * \endrst
2714 *
2715 * @param I2Cx I2C instance.
2716 * @retval State of bit (1 or 0).
2717 */
2718 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2719 {
2720 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2721 }
2722
2723 /**
2724 * @brief Indicate the status of RAW_STOP_DET flag.
2725 * @note RESET: Clear default value.
2726 * SET : When unmasked STOP_DET interrupt is actived.
2727 *
2728 * \rst
2729 * +----------------------+-----------------------------------+
2730 * | Register | BitsName |
2731 * +======================+===================================+
2732 * | IC_RAW_INTR_STAT | RAW_STOP_DET |
2733 * +----------------------+-----------------------------------+
2734 * \endrst
2735 *
2736 * @param I2Cx I2C instance.
2737 * @retval State of bit (1 or 0).
2738 */
2739 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2740 {
2741 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2742 }
2743
2744 /**
2745 * @brief Indicate the status of ACTIVITY flag.
2746 * @note RESET: Clear default value.
2747 * SET : When masked ACTIVITY interrupt is actived.
2748 *
2749 * \rst
2750 * +----------------------+-----------------------------------+
2751 * | Register | BitsName |
2752 * +======================+===================================+
2753 * | IC_INTR_STAT | ACTIVITY |
2754 * +----------------------+-----------------------------------+
2755 * \endrst
2756 *
2757 * @param I2Cx I2C instance.
2758 * @retval State of bit (1 or 0).
2759 */
2760 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2761 {
2762 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2763 }
2764
2765 /**
2766 * @brief Indicate the status of RAW_ACTIVITY flag.
2767 * @note RESET: Clear default value.
2768 * SET : When unmasked ACTIVITY interrupt is actived.
2769 *
2770 * \rst
2771 * +----------------------+-----------------------------------+
2772 * | Register | BitsName |
2773 * +======================+===================================+
2774 * | IC_RAW_INTR_STAT | RAW_ACTIVITY |
2775 * +----------------------+-----------------------------------+
2776 * \endrst
2777 *
2778 * @param I2Cx I2C instance.
2779 * @retval State of bit (1 or 0).
2780 */
2781 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2782 {
2783 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2784 }
2785
2786 /**
2787 * @brief Indicate the status of RX_DONE flag.
2788 * @note RESET: Clear default value.
2789 * SET : When masked RX_DONE interrupt is actived.
2790 *
2791 * \rst
2792 * +----------------------+-----------------------------------+
2793 * | Register | BitsName |
2794 * +======================+===================================+
2795 * | IC_INTR_STAT | RX_DONE |
2796 * +----------------------+-----------------------------------+
2797 * \endrst
2798 *
2799 * @param I2Cx I2C instance.
2800 * @retval State of bit (1 or 0).
2801 */
2802 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2803 {
2804 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2805 }
2806
2807 /**
2808 * @brief Indicate the status of RAW_RX_DONE flag.
2809 * @note RESET: Clear default value.
2810 * SET : When unmasked RX_DONE interrupt is actived.
2811 *
2812 * \rst
2813 * +----------------------+-----------------------------------+
2814 * | Register | BitsName |
2815 * +======================+===================================+
2816 * | IC_RAW_INTR_STAT | RAW_RX_DONE |
2817 * +----------------------+-----------------------------------+
2818 * \endrst
2819 *
2820 * @param I2Cx I2C instance.
2821 * @retval State of bit (1 or 0).
2822 */
2823 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2824 {
2825 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2826 }
2827
2828 /**
2829 * @brief Indicate the status of TX_ABRT flag.
2830 * @note RESET: Clear default value.
2831 * SET : When masked TX_ABRT interrupt is actived.
2832 *
2833 * \rst
2834 * +----------------------+-----------------------------------+
2835 * | Register | BitsName |
2836 * +======================+===================================+
2837 * | IC_INTR_STAT | TX_ABRT |
2838 * +----------------------+-----------------------------------+
2839 * \endrst
2840 *
2841 * @param I2Cx I2C instance.
2842 * @retval State of bit (1 or 0).
2843 */
2844 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2845 {
2846 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2847 }
2848
2849 /**
2850 * @brief Indicate the status of RAW_TX_ABRT flag.
2851 * @note RESET: Clear default value.
2852 * SET : When unmasked TX_ABRT interrupt is actived.
2853 *
2854 * \rst
2855 * +----------------------+-----------------------------------+
2856 * | Register | BitsName |
2857 * +======================+===================================+
2858 * | IC_RAW_INTR_STAT | RAW_TX_ABRT |
2859 * +----------------------+-----------------------------------+
2860 * \endrst
2861 *
2862 * @param I2Cx I2C instance.
2863 * @retval State of bit (1 or 0).
2864 */
2865 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2866 {
2867 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2868 }
2869
2870 /**
2871 * @brief Indicate the status of RD_REQ flag.
2872 * @note RESET: Clear default value.
2873 * SET : When masked RD_REQ interrupt is actived.
2874 *
2875 * \rst
2876 * +----------------------+-----------------------------------+
2877 * | Register | BitsName |
2878 * +======================+===================================+
2879 * | IC_INTR_STAT | RD_REQ |
2880 * +----------------------+-----------------------------------+
2881 * \endrst
2882 *
2883 * @param I2Cx I2C instance.
2884 * @retval State of bit (1 or 0).
2885 */
2886 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2887 {
2888 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2889 }
2890
2891 /**
2892 * @brief Indicate the status of RAW_RD_REQ flag.
2893 * @note RESET: Clear default value.
2894 * SET : When unmasked RD_REQ interrupt is actived.
2895 *
2896 * \rst
2897 * +----------------------+-----------------------------------+
2898 * | Register | BitsName |
2899 * +======================+===================================+
2900 * | IC_RAW_INTR_STAT | RAW_RD_REQ |
2901 * +----------------------+-----------------------------------+
2902 * \endrst
2903 *
2904 * @param I2Cx I2C instance.
2905 * @retval State of bit (1 or 0).
2906 */
2907 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2908 {
2909 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2910 }
2911
2912 /**
2913 * @brief Indicate the status of TX_EMPTY flag.
2914 * @note RESET: Clear default value.
2915 * SET : When masked TX_EMPTY interrupt is actived.
2916 *
2917 * \rst
2918 * +----------------------+-----------------------------------+
2919 * | Register | BitsName |
2920 * +======================+===================================+
2921 * | IC_INTR_STAT | TX_EMPTY |
2922 * +----------------------+-----------------------------------+
2923 * \endrst
2924 *
2925 * @param I2Cx I2C instance.
2926 * @retval State of bit (1 or 0).
2927 */
2928 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2929 {
2930 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2931 }
2932
2933 /**
2934 * @brief Indicate the status of RAW_TX_EMPTY flag.
2935 * @note RESET: Clear default value.
2936 * SET : When unmasked TX_EMPTY interrupt is actived.
2937 *
2938 * \rst
2939 * +----------------------+-----------------------------------+
2940 * | Register | BitsName |
2941 * +======================+===================================+
2942 * | IC_RAW_INTR_STAT | RAW_TX_EMPTY |
2943 * +----------------------+-----------------------------------+
2944 * \endrst
2945 *
2946 * @param I2Cx I2C instance.
2947 * @retval State of bit (1 or 0).
2948 */
2949 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2950 {
2951 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2952 }
2953
2954 /**
2955 * @brief Indicate the status of TX_OVER flag.
2956 * @note RESET: Clear default value.
2957 * SET : When masked TX_OVER interrupt is actived.
2958 *
2959 * \rst
2960 * +----------------------+-----------------------------------+
2961 * | Register | BitsName |
2962 * +======================+===================================+
2963 * | IC_INTR_STAT | TX_OVER |
2964 * +----------------------+-----------------------------------+
2965 * \endrst
2966 *
2967 * @param I2Cx I2C instance.
2968 * @retval State of bit (1 or 0).
2969 */
2970 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2971 {
2972 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2973 }
2974
2975 /**
2976 * @brief Indicate the status of RAW_TX_OVER flag.
2977 * @note RESET: Clear default value.
2978 * SET : When unmasked TX_OVER interrupt is actived.
2979 *
2980 * \rst
2981 * +----------------------+-----------------------------------+
2982 * | Register | BitsName |
2983 * +======================+===================================+
2984 * | IC_RAW_INTR_STAT | RAW_TX_OVER |
2985 * +----------------------+-----------------------------------+
2986 * \endrst
2987 *
2988 * @param I2Cx I2C instance.
2989 * @retval State of bit (1 or 0).
2990 */
2991 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2992 {
2993 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2994 }
2995
2996 /**
2997 * @brief Indicate the status of RX_FULL flag.
2998 * @note RESET: Clear default value.
2999 * SET : When masked RX_FULL interrupt is actived.
3000 *
3001 * \rst
3002 * +----------------------+-----------------------------------+
3003 * | Register | BitsName |
3004 * +======================+===================================+
3005 * | IC_INTR_STAT | RX_FULL |
3006 * +----------------------+-----------------------------------+
3007 * \endrst
3008 *
3009 * @param I2Cx I2C instance.
3010 * @retval State of bit (1 or 0).
3011 */
3012 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
3013 {
3014 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
3015 }
3016
3017 /**
3018 * @brief Indicate the status of RAW_RX_FULL flag.
3019 * @note RESET: Clear default value.
3020 * SET : When unmasked RX_FULL interrupt is actived.
3021 *
3022 * \rst
3023 * +----------------------+-----------------------------------+
3024 * | Register | BitsName |
3025 * +======================+===================================+
3026 * | IC_RAW_INTR_STAT | RAW_RX_FULL |
3027 * +----------------------+-----------------------------------+
3028 * \endrst
3029 *
3030 * @param I2Cx I2C instance.
3031 * @retval State of bit (1 or 0).
3032 */
3033 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
3034 {
3035 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
3036 }
3037
3038 /**
3039 * @brief Indicate the status of RX_OVER flag.
3040 * @note RESET: Clear default value.
3041 * SET : When masked RX_OVER interrupt is actived.
3042 *
3043 * \rst
3044 * +----------------------+-----------------------------------+
3045 * | Register | BitsName |
3046 * +======================+===================================+
3047 * | IC_INTR_STAT | RX_OVER |
3048 * +----------------------+-----------------------------------+
3049 * \endrst
3050 *
3051 * @param I2Cx I2C instance.
3052 * @retval State of bit (1 or 0).
3053 */
3054 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
3055 {
3056 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
3057 }
3058
3059 /**
3060 * @brief Indicate the status of RAW_RX_OVER flag.
3061 * @note RESET: Clear default value.
3062 * SET : When unmasked RX_OVER interrupt is actived.
3063 *
3064 * \rst
3065 * +----------------------+-----------------------------------+
3066 * | Register | BitsName |
3067 * +======================+===================================+
3068 * | IC_RAW_INTR_STAT | RAW_RX_OVER |
3069 * +----------------------+-----------------------------------+
3070 * \endrst
3071 *
3072 * @param I2Cx I2C instance.
3073 * @retval State of bit (1 or 0).
3074 */
3075 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
3076 {
3077 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
3078 }
3079
3080 /**
3081 * @brief Indicate the status of RX_UNDER flag.
3082 * @note RESET: Clear default value.
3083 * SET : When masked RX_UNDER interrupt is actived.
3084 *
3085 * \rst
3086 * +----------------------+-----------------------------------+
3087 * | Register | BitsName |
3088 * +======================+===================================+
3089 * | IC_INTR_STAT | RX_UNDER |
3090 * +----------------------+-----------------------------------+
3091 * \endrst
3092 *
3093 * @param I2Cx I2C instance.
3094 * @retval State of bit (1 or 0).
3095 */
3096 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
3097 {
3098 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
3099 }
3100
3101 /**
3102 * @brief Indicate the status of RAW_RX_UNDER flag.
3103 * @note RESET: Clear default value.
3104 * SET : When unmasked RX_UNDER interrupt is actived.
3105 *
3106 * \rst
3107 * +----------------------+-----------------------------------+
3108 * | Register | BitsName |
3109 * +======================+===================================+
3110 * | IC_RAW_INTR_STAT | RAW_RX_UNDER |
3111 * +----------------------+-----------------------------------+
3112 * \endrst
3113 *
3114 * @param I2Cx I2C instance.
3115 * @retval State of bit (1 or 0).
3116 */
3117 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
3118 {
3119 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
3120 }
3121
3122 /**
3123 * @brief Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
3124 *
3125 * \rst
3126 * +----------------------+-----------------------------------+
3127 * | Register | BitsName |
3128 * +======================+===================================+
3129 * | IC_CLR_INTR | CLR_INTR |
3130 * +----------------------+-----------------------------------+
3131 * \endrst
3132 *
3133 * @param I2Cx I2C instance.
3134 * @retval None.
3135 */
3136 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
3137 {
3138 __IO uint32_t tmpreg;
3139 tmpreg = READ_REG(I2Cx->CLR_INTR);
3140 (void) tmpreg;
3141 }
3142
3143 /**
3144 * @brief Clear GEN_CALL flag.
3145 *
3146 * \rst
3147 * +----------------------+-----------------------------------+
3148 * | Register | BitsName |
3149 * +======================+===================================+
3150 * | IC_CLR_GEN_CALL | CLR_GEN_CALL |
3151 * +----------------------+-----------------------------------+
3152 * \endrst
3153 *
3154 * @param I2Cx I2C instance.
3155 * @retval None.
3156 */
3157 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
3158 {
3159 __IO uint32_t tmpreg;
3160 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
3161 (void) tmpreg;
3162 }
3163
3164 /**
3165 * @brief Clear START_DET flag.
3166 *
3167 * \rst
3168 * +----------------------+-----------------------------------+
3169 * | Register | BitsName |
3170 * +======================+===================================+
3171 * | IC_CLR_START_DET | CLR_START_DET |
3172 * +----------------------+-----------------------------------+
3173 * \endrst
3174 *
3175 * @param I2Cx I2C instance.
3176 * @retval None.
3177 */
3178 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
3179 {
3180 __IO uint32_t tmpreg;
3181 tmpreg = READ_REG(I2Cx->CLR_START_DET);
3182 (void) tmpreg;
3183 }
3184
3185 /**
3186 * @brief Clear STOP_DET flag.
3187 *
3188 * \rst
3189 * +----------------------+-----------------------------------+
3190 * | Register | BitsName |
3191 * +======================+===================================+
3192 * | IC_CLR_STOP_DET | CLR_STOP_DET |
3193 * +----------------------+-----------------------------------+
3194 * \endrst
3195 *
3196 * @param I2Cx I2C instance.
3197 * @retval None.
3198 */
3199 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
3200 {
3201 __IO uint32_t tmpreg;
3202 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
3203 (void) tmpreg;
3204 }
3205
3206 /**
3207 * @brief Clear ACTIVITY flag.
3208 *
3209 * \rst
3210 * +----------------------+-----------------------------------+
3211 * | Register | BitsName |
3212 * +======================+===================================+
3213 * | IC_CLR_ACTIVITY | CLR_ACTIVITY |
3214 * +----------------------+-----------------------------------+
3215 * \endrst
3216 *
3217 * @param I2Cx I2C instance.
3218 * @retval None.
3219 */
3220 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
3221 {
3222 __IO uint32_t tmpreg;
3223 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
3224 (void) tmpreg;
3225 }
3226
3227 /**
3228 * @brief Clear RX_DONE flag.
3229 *
3230 * \rst
3231 * +----------------------+-----------------------------------+
3232 * | Register | BitsName |
3233 * +======================+===================================+
3234 * | IC_CLR_RX_DONE | CLR_RX_DONE |
3235 * +----------------------+-----------------------------------+
3236 * \endrst
3237 *
3238 * @param I2Cx I2C instance.
3239 * @retval None.
3240 */
3241 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
3242 {
3243 __IO uint32_t tmpreg;
3244 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
3245 (void) tmpreg;
3246 }
3247
3248 /**
3249 * @brief Clear TX_ABRT flag.
3250 *
3251 * \rst
3252 * +----------------------+-----------------------------------+
3253 * | Register | BitsName |
3254 * +======================+===================================+
3255 * | IC_CLR_TX_ABRT | CLR_TX_ABRT |
3256 * +----------------------+-----------------------------------+
3257 * \endrst
3258 *
3259 * @param I2Cx I2C instance.
3260 * @retval None.
3261 */
3262 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
3263 {
3264 __IO uint32_t tmpreg;
3265 tmpreg = READ_REG(I2Cx->CLR_TX_ABRT);
3266 (void) tmpreg;
3267 }
3268
3269 /**
3270 * @brief Clear RD_REQ flag.
3271 *
3272 * \rst
3273 * +----------------------+-----------------------------------+
3274 * | Register | BitsName |
3275 * +======================+===================================+
3276 * | IC_CLR_RD_REQ | CLR_RD_REQ |
3277 * +----------------------+-----------------------------------+
3278 * \endrst
3279 *
3280 * @param I2Cx I2C instance.
3281 * @retval None.
3282 */
3283 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
3284 {
3285 __IO uint32_t tmpreg;
3286 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
3287 (void) tmpreg;
3288 }
3289
3290 /**
3291 * @brief Clear TX_OVER flag.
3292 *
3293 * \rst
3294 * +----------------------+-----------------------------------+
3295 * | Register | BitsName |
3296 * +======================+===================================+
3297 * | IC_CLR_TX_OVER | CLR_TX_OVER |
3298 * +----------------------+-----------------------------------+
3299 * \endrst
3300 *
3301 * @param I2Cx I2C instance.
3302 * @retval None.
3303 */
3304 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
3305 {
3306 __IO uint32_t tmpreg;
3307 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
3308 (void) tmpreg;
3309 }
3310
3311 /**
3312 * @brief Clear RX_OVER flag.
3313 *
3314 * \rst
3315 * +----------------------+-----------------------------------+
3316 * | Register | BitsName |
3317 * +======================+===================================+
3318 * | IC_CLR_RX_OVER | CLR_RX_OVER |
3319 * +----------------------+-----------------------------------+
3320 * \endrst
3321 *
3322 * @param I2Cx I2C instance.
3323 * @retval None.
3324 */
3325 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
3326 {
3327 __IO uint32_t tmpreg;
3328 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
3329 (void) tmpreg;
3330 }
3331
3332 /**
3333 * @brief Clear RX_UNDER flag.
3334 *
3335 * \rst
3336 * +----------------------+-----------------------------------+
3337 * | Register | BitsName |
3338 * +======================+===================================+
3339 * | IC_CLR_RX_UNDER | CLR_RX_UNDER |
3340 * +----------------------+-----------------------------------+
3341 * \endrst
3342 *
3343 * @param I2Cx I2C instance.
3344 * @retval None.
3345 */
3346 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
3347 {
3348 __IO uint32_t tmpreg;
3349 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
3350 (void) tmpreg;
3351 }
3352
3353 /**
3354 * @brief Indicate the status of IC_STATUS Slave FSM Activity Status flag.
3355 * @note RESET: Slave FSM is in IDLE state.
3356 * SET : When Slave FSM is not in IDLE state.
3357 *
3358 * \rst
3359 * +----------------------+-----------------------------------+
3360 * | Register | BitsName |
3361 * +======================+===================================+
3362 * | IC_STATUS | SLV_ACTIVITY |
3363 * +----------------------+-----------------------------------+
3364 * \endrst
3365 *
3366 * @param I2Cx I2C instance.
3367 * @retval State of bit (1 or 0).
3368 */
3369 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
3370 {
3371 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_SLV_ACTIVITY) == (I2C_STATUS_SLV_ACTIVITY));
3372 }
3373
3374 /**
3375 * @brief Indicate the status of IC_STATUS Master FSM Activity Status flag.
3376 * @note RESET: Master FSM is in IDLE state.
3377 * SET : When Master FSM is not in IDLE state.
3378 *
3379 * \rst
3380 * +----------------------+-----------------------------------+
3381 * | Register | BitsName |
3382 * +======================+===================================+
3383 * | IC_STATUS | MST_ACTIVITY |
3384 * +----------------------+-----------------------------------+
3385 * \endrst
3386 *
3387 * @param I2Cx I2C instance.
3388 * @retval State of bit (1 or 0).
3389 */
3390 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
3391 {
3392 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_MST_ACTIVITY) == (I2C_STATUS_MST_ACTIVITY));
3393 }
3394
3395 /**
3396 * @brief Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
3397 * @note RESET: Receive FIFO is not full.
3398 * SET : When Receive FIFO is full.
3399 *
3400 * \rst
3401 * +----------------------+-----------------------------------+
3402 * | Register | BitsName |
3403 * +======================+===================================+
3404 * | IC_STATUS | RFF |
3405 * +----------------------+-----------------------------------+
3406 * \endrst
3407 *
3408 * @param I2Cx I2C instance.
3409 * @retval State of bit (1 or 0).
3410 */
3411 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
3412 {
3413 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFF) == (I2C_STATUS_RFF));
3414 }
3415
3416 /**
3417 * @brief Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
3418 * @note RESET: Receive FIFO is empty.
3419 * SET : When Receive FIFO is not empty.
3420 *
3421 * \rst
3422 * +----------------------+-----------------------------------+
3423 * | Register | BitsName |
3424 * +======================+===================================+
3425 * | IC_STATUS | RFNE |
3426 * +----------------------+-----------------------------------+
3427 * \endrst
3428 *
3429 * @param I2Cx I2C instance.
3430 * @retval State of bit (1 or 0).
3431 */
3432 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
3433 {
3434 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFNE) == (I2C_STATUS_RFNE));
3435 }
3436
3437 /**
3438 * @brief Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
3439 * @note RESET: Transmit FIFO is not empty.
3440 * SET : When Transmit FIFO is empty.
3441 *
3442 * \rst
3443 * +----------------------+-----------------------------------+
3444 * | Register | BitsName |
3445 * +======================+===================================+
3446 * | IC_STATUS | TFE |
3447 * +----------------------+-----------------------------------+
3448 * \endrst
3449 *
3450 * @param I2Cx I2C instance.
3451 * @retval State of bit (1 or 0).
3452 */
3453 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
3454 {
3455 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFE) == (I2C_STATUS_TFE));
3456 }
3457
3458 /**
3459 * @brief Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
3460 * @note RESET: Transmit FIFO is full.
3461 * SET : When Transmit FIFO is not full.
3462 *
3463 * \rst
3464 * +----------------------+-----------------------------------+
3465 * | Register | BitsName |
3466 * +======================+===================================+
3467 * | IC_STATUS | TFNF |
3468 * +----------------------+-----------------------------------+
3469 * \endrst
3470 *
3471 * @param I2Cx I2C instance.
3472 * @retval State of bit (1 or 0).
3473 */
3474 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
3475 {
3476 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFNF) == (I2C_STATUS_TFNF));
3477 }
3478
3479 /**
3480 * @brief Indicate the status of IC_STATUS ACTIVITY flag.
3481 * @note RESET: I2C is idle.
3482 * SET : When I2C is active.
3483 *
3484 * \rst
3485 * +----------------------+-----------------------------------+
3486 * | Register | BitsName |
3487 * +======================+===================================+
3488 * | IC_STATUS | ACTIVITY |
3489 * +----------------------+-----------------------------------+
3490 * \endrst
3491 *
3492 * @param I2Cx I2C instance.
3493 * @retval State of bit (1 or 0).
3494 */
3495 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
3496 {
3497 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_ACTIVITY) == (I2C_STATUS_ACTIVITY));
3498 }
3499
3500 /**
3501 * @brief Indicate the status of Slave Received Data Lost flag.
3502 * @note RESET: Slave RX Data is not lost.
3503 * SET : Slave RX Data is lost.
3504 *
3505 * \rst
3506 * +----------------------+-----------------------------------+
3507 * | Register | BitsName |
3508 * +======================+===================================+
3509 * | IC_ENABLE_STATUS | SLV_RX_LOST |
3510 * +----------------------+-----------------------------------+
3511 * \endrst
3512 *
3513 * @param I2Cx I2C instance.
3514 * @retval State of bit (1 or 0).
3515 */
3516 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
3517 {
3518 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_RX_LOST) == (I2C_ENABLE_STATUS_SLV_RX_LOST));
3519 }
3520
3521 /**
3522 * @brief Indicate the status of Slave Disabled While Busy flag.
3523 * @note RESET: Slave is disabled when it is idle.
3524 * SET : Slave is disabled when it is active.
3525 *
3526 * \rst
3527 * +----------------------+-----------------------------------+
3528 * | Register | BitsName |
3529 * +======================+===================================+
3530 * | IC_ENABLE_STATUS | SLV_DIS_WHL_BUSY |
3531 * +----------------------+-----------------------------------+
3532 * \endrst
3533 *
3534 * @param I2Cx I2C instance.
3535 * @retval State of bit (1 or 0).
3536 */
3537 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
3538 {
3539 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY) == (I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY));
3540 }
3541 /** @} */
3542
3543 /** @defgroup I2C_LL_EF_DMA_Management DMA_Management
3544 * @{
3545 */
3546
3547 /**
3548 * @brief Enable DMA transmission requests.
3549 *
3550 * \rst
3551 * +----------------------+-----------------------------------+
3552 * | Register | BitsName |
3553 * +======================+===================================+
3554 * | IC_DMA_CR | TDMAE |
3555 * +----------------------+-----------------------------------+
3556 * \endrst
3557 *
3558 * @retval Value range between 0 ~ 0x8.
3559 * @retval None.
3560 */
3561 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
3562 {
3563 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
3564 }
3565
3566 /**
3567 * @brief Disable DMA transmission requests.
3568 *
3569 * \rst
3570 * +----------------------+-----------------------------------+
3571 * | Register | BitsName |
3572 * +======================+===================================+
3573 * | IC_DMA_CR | TDMAE |
3574 * +----------------------+-----------------------------------+
3575 * \endrst
3576 *
3577 * @param I2Cx I2C instance.
3578 * @retval None.
3579 */
3580 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
3581 {
3582 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
3583 }
3584
3585 /**
3586 * @brief Check if DMA transmission requests are enabled or disabled.
3587 *
3588 * \rst
3589 * +----------------------+-----------------------------------+
3590 * | Register | BitsName |
3591 * +======================+===================================+
3592 * | IC_DMA_CR | TDMAE |
3593 * +----------------------+-----------------------------------+
3594 * \endrst
3595 *
3596 * @param I2Cx I2C instance.
3597 * @retval State of bit (1 or 0).
3598 */
3599 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
3600 {
3601 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE) == (I2C_DMA_CR_TDMAE));
3602 }
3603
3604 /**
3605 * @brief Enable DMA reception requests.
3606 *
3607 * \rst
3608 * +----------------------+-----------------------------------+
3609 * | Register | BitsName |
3610 * +======================+===================================+
3611 * | IC_DMA_CR | RDMAE |
3612 * +----------------------+-----------------------------------+
3613 * \endrst
3614 *
3615 * @param I2Cx I2C instance.
3616 * @retval None.
3617 */
3618 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3619 {
3620 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3621 }
3622
3623 /**
3624 * @brief Disable DMA reception requests.
3625 *
3626 * \rst
3627 * +----------------------+-----------------------------------+
3628 * | Register | BitsName |
3629 * +======================+===================================+
3630 * | IC_DMA_CR | RDMAE |
3631 * +----------------------+-----------------------------------+
3632 * \endrst
3633 *
3634 * @param I2Cx I2C instance.
3635 * @retval None.
3636 */
3637 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3638 {
3639 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3640 }
3641
3642 /**
3643 * @brief Check if DMA reception requests are enabled or disabled.
3644 *
3645 * \rst
3646 * +----------------------+-----------------------------------+
3647 * | Register | BitsName |
3648 * +======================+===================================+
3649 * | IC_DMA_CR | RDMAE |
3650 * +----------------------+-----------------------------------+
3651 * \endrst
3652 *
3653 * @param I2Cx I2C instance.
3654 * @retval State of bit (1 or 0).
3655 */
3656 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3657 {
3658 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE) == (I2C_DMA_CR_RDMAE));
3659 }
3660
3661 /**
3662 * @brief Set level of TX FIFO that requests a DMA transmit.
3663 * @note TX data level should equal to the watermark level, that is, the dma_tx_req
3664 * signal is generated when the number of valid data entries in the transmit
3665 * FIFO is equal to or below this field value, and TDMAE = 1.
3666 *
3667 * \rst
3668 * +----------------------+-----------------------------------+
3669 * | Register | BitsName |
3670 * +======================+===================================+
3671 * | IC_DMA_TDLR | DMATDL |
3672 * +----------------------+-----------------------------------+
3673 * \endrst
3674 *
3675 * @param I2Cx I2C instance
3676 * @param level This parameter should range between 0x0 and 0x8.
3677 * @retval None.
3678 */
3679 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3680 {
3681 WRITE_REG(I2Cx->DMA_TDLR, level);
3682 }
3683
3684 /**
3685 * @brief Get level of TX FIFO that request a DMA transmit.
3686 *
3687 * \rst
3688 * +----------------------+-----------------------------------+
3689 * | Register | BitsName |
3690 * +======================+===================================+
3691 * | IC_DMA_TDLR | DMATDL |
3692 * +----------------------+-----------------------------------+
3693 * \endrst
3694 *
3695 * @param I2Cx I2C instance
3696 * @retval Returned value should range between 0x0 and 0x8.
3697 */
3698 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3699 {
3700 return (uint32_t)(READ_BITS(I2Cx->DMA_TDLR, I2C_DMA_TDLR_DMATDL));
3701 }
3702
3703 /**
3704 * @brief Set level of RX FIFO that requests a DMA receive.
3705 * @note The watermark level = DMARDL + 1, that is, dma_rx_req is generated when
3706 * the number of valid data entries in the receive FIFO is equal to or
3707 * more than this field value + 1, and RDMAE = 1. For instance, when DMARDL
3708 * is 0, then dma_rx_req is asserted when 1 or more data entries are present
3709 * in the receive FIFO.
3710 *
3711 * \rst
3712 * +----------------------+-----------------------------------+
3713 * | Register | BitsName |
3714 * +======================+===================================+
3715 * | IC_DMA_RDLR | DMARDL |
3716 * +----------------------+-----------------------------------+
3717 * \endrst
3718 *
3719 * @param I2Cx I2C instance
3720 * @param level This parameter should range between 0x0 and 0x8.
3721 * @retval None.
3722 */
3723 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3724 {
3725 WRITE_REG(I2Cx->DMA_RDLR, level);
3726 }
3727
3728 /**
3729 * @brief Get level of RX FIFO that request a DMA receive.
3730 *
3731 * \rst
3732 * +----------------------+-----------------------------------+
3733 * | Register | BitsName |
3734 * +======================+===================================+
3735 * | IC_DMA_RDLR | DMARDL |
3736 * +----------------------+-----------------------------------+
3737 * \endrst
3738 *
3739 * @param I2Cx I2C instance
3740 * @retval Returned value should range between 0x0 and 0x8.
3741 */
3742 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3743 {
3744 return (uint32_t)(READ_BITS(I2Cx->DMA_RDLR, I2C_DMA_RDLR_DMARDL));
3745 }
3746
3747 /**
3748 * @brief Get the data register address used for DMA transfer
3749 *
3750 * \rst
3751 * +----------------------+-----------------------------------+
3752 * | Register | BitsName |
3753 * +======================+===================================+
3754 * | IC_DATA_CMD | DAT |
3755 * +----------------------+-----------------------------------+
3756 * \endrst
3757 *
3758 * @param I2Cx I2C instance
3759 * @retval Address of data register
3760 */
3761 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3762 {
3763 return ((uint32_t) & (I2Cx->DATA_CMD));
3764 }
3765
3766 /** @} */
3767
3768 /** @defgroup I2C_LL_EF_Data_Management Data_Management
3769 * @{
3770 */
3771
3772 /**
3773 * @brief Configure the slave address for transfer (master mode).
3774 * @note The register IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3775 *
3776 * \rst
3777 * +----------------------+-----------------------------------+
3778 * | Register | BitsName |
3779 * +======================+===================================+
3780 * | IC_TAR | TAR_ADDR |
3781 * +----------------------+-----------------------------------+
3782 * \endrst
3783 *
3784 * @param I2Cx I2C instance.
3785 * @param slave_addr This parameter must be a value between 0x00 and 0x3F.
3786 * @retval None.
3787 */
3788 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3789 {
3790 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3791 }
3792
3793 /**
3794 * @brief Get the slave address programmed for transfer (master mode).
3795 *
3796 * \rst
3797 * +----------------------+-----------------------------------+
3798 * | Register | BitsName |
3799 * +======================+===================================+
3800 * | IC_TAR | TAR_ADDR |
3801 * +----------------------+-----------------------------------+
3802 * \endrst
3803 *
3804 * @param I2Cx I2C instance.
3805 * @retval Value between 0x0 and0x3F
3806 */
3807 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3808 {
3809 return (uint32_t)(READ_BITS(I2Cx->TAR, I2C_TAR_ADDR) >> I2C_TAR_ADDR_Pos);
3810 }
3811
3812 /**
3813 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
3814 * @note The register IC_CON and IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3815 *
3816 * \rst
3817 * +----------------------+-----------------------------------+
3818 * | Register | BitsName |
3819 * +======================+===================================+
3820 * | IC_CON | CON_10BITADDR_MST |
3821 * +----------------------+-----------------------------------+
3822 * \endrst
3823 * IC_TAR | TAR_ADDR
3824 *
3825 * @param I2Cx I2C instance.
3826 * @param slave_addr Specifies the slave address to be programmed.
3827 * @param slave_addr_size This parameter can be one of the following values:
3828 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
3829 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
3830 * @note SlaveAddrSize in IC_CON register can only be programmed when the I2C is disabled (IC_ENABLE = 0).
3831 * @retval None.
3832 */
3833 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3834 {
3835 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3836 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3837 }
3838
3839 /**
3840 * @brief Indicate the value of transfer direction (slave mode).
3841 * @note RESET: Write transfer, Slave enters in receiver mode.
3842 * SET: Read transfer, Slave enters in transmitter mode.
3843 *
3844 * \rst
3845 * +----------------------+-----------------------------------+
3846 * | Register | BitsName |
3847 * +======================+===================================+
3848 * | IC_RAW_INTR_STAT | INTR_RD_REQ |
3849 * +----------------------+-----------------------------------+
3850 * \endrst
3851 * IC_RAW_INTR_STAT | INTR_RX_FULL
3852 *
3853 * @param I2Cx I2C instance.
3854 * @retval Returned value can be one of the following values:
3855 * @arg @ref LL_I2C_DIRECTION_WRITE
3856 * @arg @ref LL_I2C_DIRECTION_READ
3857 */
3858 __STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
3859 {
3860 return (uint32_t)(READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ | I2C_INTR_RX_FULL));
3861 }
3862
3863 /**
3864 * @brief Read Receive Data register.
3865 *
3866 * \rst
3867 * +----------------------+-----------------------------------+
3868 * | Register | BitsName |
3869 * +======================+===================================+
3870 * | IC_DATA_CMD | DAT |
3871 * +----------------------+-----------------------------------+
3872 * \endrst
3873 *
3874 * @param I2Cx I2C instance.
3875 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3876 */
3877 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3878 {
3879 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DAT));
3880 }
3881
3882 /**
3883 * @brief Write in Transmit Data Register .
3884 *
3885 * \rst
3886 * +----------------------+-----------------------------------+
3887 * | Register | BitsName |
3888 * +======================+===================================+
3889 * | IC_DATA_CMD | STOP |
3890 * +----------------------+-----------------------------------+
3891 * \endrst
3892 * IC_DATA_CMD | CMD
3893 * IC_DATA_CMD | DAT
3894 *
3895 * @param I2Cx I2C instance.
3896 * @param data Value range between 0x00 and 0xFF.
3897 * @param cmd This parameter can be one of the following values:
3898 * @arg @ref LL_I2C_CMD_SLV_NONE
3899 * @arg @ref LL_I2C_CMD_MST_WRITE
3900 * @arg @ref LL_I2C_CMD_MST_READ
3901 * @arg @ref LL_I2C_CMD_MST_GEN_STOP
3902 * @arg @ref LL_I2C_CMD_MST_GEN_RESTART
3903 * @retval None.
3904 */
3905 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3906 {
3907 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3908 }
3909
3910 /** @} */
3911
3912 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
3913 * @{
3914 */
3915
3916 /**
3917 * @brief De-initialize I2C registers (Registers restored to their default values).
3918 * @param I2Cx I2C instance
3919 * @retval An error_status_t enumeration value:
3920 * - SUCCESS: I2C registers are de-initialized
3921 * - ERROR: I2C registers are not de-initialized
3922 */
3923 error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx);
3924
3925 /**
3926 * @brief Initialize I2C registers according to the specified
3927 * parameters in p_i2c_init.
3928 * @param I2Cx I2C instance
3929 * @param p_i2c_init Pointer to a ll_i2c_init_t structure that contains the configuration
3930 * information for the specified I2C peripheral.
3931 * @retval An error_status_t enumeration value:
3932 * - SUCCESS: I2C registers are initialized according to p_i2c_init content
3933 * - ERROR: Problem occurred during I2C Registers initialization
3934 */
3935 error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3936
3937 /**
3938 * @brief Set each field of a @ref ll_i2c_init_t type structure to default value.
3939 * @param p_i2c_init Pointer to a @ref ll_i2c_init_t structure
3940 * whose fields will be set to default values.
3941 * @retval None
3942 */
3943 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3944
3945 /** @} */
3946
3947 /** @} */
3948
3949 #endif /* I2C0 || I2C1 */
3950
3951 #ifdef __cplusplus
3952 }
3953 #endif
3954
3955 #endif /* __GR55xx_LL_I2C_H__ */
3956
3957 /** @} */
3958
3959 /** @} */
3960
3961 /** @} */
ll_i2c_is_active_flag_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2970
ll_i2c_enable
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
Definition: gr55xx_ll_i2c.h:344
_ll_i2c_init::own_addr_size
uint32_t own_addr_size
Specifies the device own address 1 size (7-bit or 10-bit).
Definition: gr55xx_ll_i2c.h:85
ll_i2c_enable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:593
ll_i2c_is_active_flag_status_tfnf
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
Definition: gr55xx_ll_i2c.h:3474
ll_i2c_is_enabled_transfer_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1422
ll_i2c_is_active_flag_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2802
ll_i2c_get_clock_low_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:864
ll_i2c_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
Definition: gr55xx_ll_i2c.h:1365
ll_i2c_is_enabled_it_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1918
ll_i2c_is_enabled_it_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1690
ll_i2c_set_speed_mode
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1048
ll_i2c_enable_it_tx_over
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2222
ll_i2c_disable_it_tx_over
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2241
ll_i2c_is_active_flag_status_master_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:3390
ll_i2c_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1346
ll_i2c_get_abort_source
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
Definition: gr55xx_ll_i2c.h:1479
ll_i2c_is_active_flag_raw_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2571
ll_i2c_is_active_flag_status_rfne
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
Definition: gr55xx_ll_i2c.h:3432
ll_i2c_clear_flag_rx_under
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:3346
ll_i2c_dma_get_register_address
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
Definition: gr55xx_ll_i2c.h:3761
ll_i2c_clear_flag_tx_over
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
Definition: gr55xx_ll_i2c.h:3304
ll_i2c_disable_it_tx_empty
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:2184
ll_i2c_is_active_flag_raw_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2865
ll_i2c_enable_dma_req_tx
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:3561
ll_i2c_is_enabled_it_start_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1861
ll_i2c_is_enabled_stop_det_if_addressed
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
Definition: gr55xx_ll_i2c.h:632
ll_i2c_enable_it_start_det
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1823
ll_i2c_get_data_setup_time
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1234
ll_i2c_is_active_flag_raw_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2907
ll_i2c_is_active_flag_status_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:3495
ll_i2c_disable_it_master_om_hold
__STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1671
ll_i2c_enable_transfer_abort
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:1403
ll_i2c_get_spike_len_fs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:984
ll_i2c_deinit
error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
ll_i2c_is_active_flag_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:3096
ll_i2c_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:1263
ll_i2c_is_active_flag_raw_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2781
ll_i2c_get_clock_low_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:944
ll_i2c_is_active_flag_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2718
ll_i2c_is_enabled_master_mode
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
Definition: gr55xx_ll_i2c.h:445
ll_i2c_disable_dma_req_tx
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
Definition: gr55xx_ll_i2c.h:3580
ll_i2c_disable_it_rx_over
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2355
_ll_i2c_init::speed
uint32_t speed
Specifies the transfer speed.
Definition: gr55xx_ll_i2c.h:78
ll_i2c_enable_it_read_req
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:2108
ll_i2c_is_active_flag_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
Definition: gr55xx_ll_i2c.h:3054
ll_i2c_is_enabled_it_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2431
ll_i2c_enable_it_stop_det
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1880
ll_i2c_disable_dma_req_rx
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3637
ll_i2c_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: gr55xx_ll_i2c.h:1319
ll_i2c_is_active_flag_status_tfe
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
Definition: gr55xx_ll_i2c.h:3453
ll_i2c_is_active_flag_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2592
ll_i2c_set_dma_rx_data_level
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
Definition: gr55xx_ll_i2c.h:3723
ll_i2c_disable_it_restart_det
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1728
ll_i2c_is_active_flag_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
Definition: gr55xx_ll_i2c.h:2550
ll_i2c_disable_it
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
Definition: gr55xx_ll_i2c.h:1590
ll_i2c_disable_master_restart
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
Definition: gr55xx_ll_i2c.h:550
ll_i2c_get_clock_high_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:904
ll_i2c_clear_flag_intr
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: gr55xx_ll_i2c.h:3136
ll_i2c_is_enabled_it_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1747
ll_i2c_get_tx_flush_count
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:1498
ll_i2c_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: gr55xx_ll_i2c.h:1290
ll_i2c_disable_it_stop_det
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
Definition: gr55xx_ll_i2c.h:1899
ll_i2c_is_enabled_it_activity
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1975
ll_i2c_get_data_rx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1192
ll_i2c_get_clock_high_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:744
ll_i2c_init
error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
ll_i2c_disbale_it_rx_full
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:2298
ll_i2c_get_slave_address
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3807
ll_i2c_is_active_flag_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
Definition: gr55xx_ll_i2c.h:3012
ll_i2c_enable_it_master_on_hold
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
Definition: gr55xx_ll_i2c.h:1652
ll_i2c_is_enabled_it_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2089
ll_i2c_set_own_address
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
Definition: gr55xx_ll_i2c.h:703
ll_i2c_clear_flag_start_det
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
Definition: gr55xx_ll_i2c.h:3178
ll_i2c_set_master_addressing_mode
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
Definition: gr55xx_ll_i2c.h:655
ll_i2c_disable_it_gen_call
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1785
ll_i2c_clear_flag_stop_det
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
Definition: gr55xx_ll_i2c.h:3199
ll_i2c_disable_it_start_det
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
Definition: gr55xx_ll_i2c.h:1842
ll_i2c_is_active_flag_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:2760
ll_i2c_disable_master_mode
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
Definition: gr55xx_ll_i2c.h:425
ll_i2c_is_active_flag_raw_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2655
ll_i2c_get_master_addressing_mode
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
Definition: gr55xx_ll_i2c.h:677
ll_i2c_clear_flag_tx_abort
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:3262
ll_i2c_disable_it_activity
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1956
ll_i2c_is_active_flag_slave_rx_data_lost
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
Definition: gr55xx_ll_i2c.h:3516
_ll_i2c_init
LL I2C init Structure definition.
Definition: gr55xx_ll_i2c.h:77
ll_i2c_is_active_flag_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
Definition: gr55xx_ll_i2c.h:2844
ll_i2c_disable_it_read_req
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
Definition: gr55xx_ll_i2c.h:2127
ll_i2c_is_enabled_general_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
Definition: gr55xx_ll_i2c.h:504
ll_i2c_get_dma_rx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
Definition: gr55xx_ll_i2c.h:3742
ll_i2c_enable_it
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
Definition: gr55xx_ll_i2c.h:1547
ll_i2c_is_active_flag_slave_dis_whl_busy
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
Definition: gr55xx_ll_i2c.h:3537
ll_i2c_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3599
ll_i2c_clear_flag_rx_done
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
Definition: gr55xx_ll_i2c.h:3241
ll_i2c_set_clock_low_period_ss
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:765
ll_i2c_clear_flag_rx_over
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
Definition: gr55xx_ll_i2c.h:3325
ll_i2c_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: gr55xx_ll_i2c.h:3656
ll_i2c_enable_dma_req_rx
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: gr55xx_ll_i2c.h:3618
ll_i2c_is_active_flag_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2928
ll_i2c_is_active_flag_raw_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
Definition: gr55xx_ll_i2c.h:2949
ll_i2c_is_enabled_it_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2374
ll_i2c_receive_data8
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
Definition: gr55xx_ll_i2c.h:3877
ll_i2c_struct_init
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
ll_i2c_disable_general_call
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:485
ll_i2c_is_enabled_it_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2260
ll_i2c_set_data_rx_hold_time
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1173
ll_i2c_set_spike_len_hs
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:1005
ll_i2c_enable_it_rx_under
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2393
ll_i2c_enable_general_call
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
Definition: gr55xx_ll_i2c.h:465
ll_i2c_is_active_flag_status_slave_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
Definition: gr55xx_ll_i2c.h:3369
ll_i2c_set_dma_tx_data_level
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
Definition: gr55xx_ll_i2c.h:3679
ll_i2c_is_enabled_it
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
Definition: gr55xx_ll_i2c.h:1633
ll_i2c_get_dma_tx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
Definition: gr55xx_ll_i2c.h:3698
ll_i2c_is_active_flag_raw_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
Definition: gr55xx_ll_i2c.h:2823
ll_i2c_get_high_speed_master_code
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1110
ll_i2c_set_clock_high_period_fs
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:805
ll_i2c_enable_it_rx_over
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
Definition: gr55xx_ll_i2c.h:2336
ll_i2c_enable_it_activity
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
Definition: gr55xx_ll_i2c.h:1937
ll_i2c_is_active_flag_raw_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
Definition: gr55xx_ll_i2c.h:2697
ll_i2c_ls_enabled_it_rx_full
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2317
ll_i2c_set_clock_high_period_hs
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
Definition: gr55xx_ll_i2c.h:885
ll_i2c_get_data_tx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1151
ll_i2c_clear_flag_read_req
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
Definition: gr55xx_ll_i2c.h:3283
ll_i2c_is_active_flag_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
Definition: gr55xx_ll_i2c.h:2886
ll_i2c_get_spike_len_hs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
Definition: gr55xx_ll_i2c.h:1024
ll_i2c_enable_it_rx_done
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:1994
ll_i2c_enable_master_restart
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
Definition: gr55xx_ll_i2c.h:530
ll_i2c_init_t
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
ll_i2c_is_enabled_it_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2203
ll_i2c_is_active_flag_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:2634
ll_i2c_clear_flag_activity
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
Definition: gr55xx_ll_i2c.h:3220
ll_i2c_is_active_flag_status_rff
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
Definition: gr55xx_ll_i2c.h:3411
ll_i2c_set_data_setup_time
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
Definition: gr55xx_ll_i2c.h:1215
ll_i2c_enable_master_mode
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
Definition: gr55xx_ll_i2c.h:406
ll_i2c_set_clock_low_period_hs
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
Definition: gr55xx_ll_i2c.h:925
ll_i2c_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
Definition: gr55xx_ll_i2c.h:1384
ll_i2c_get_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
Definition: gr55xx_ll_i2c.h:2483
ll_i2c_is_active_flag_raw_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
Definition: gr55xx_ll_i2c.h:2613
ll_i2c_is_enabled_it_read_req
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2146
ll_i2c_enable_it_gen_call
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
Definition: gr55xx_ll_i2c.h:1766
ll_i2c_disable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
Definition: gr55xx_ll_i2c.h:613
ll_i2c_is_enabled_master_restart
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
Definition: gr55xx_ll_i2c.h:569
ll_i2c_get_speed_mode
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: gr55xx_ll_i2c.h:1070
ll_i2c_set_slave_address
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
Definition: gr55xx_ll_i2c.h:3788
ll_i2c_set_high_speed_master_code
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
Definition: gr55xx_ll_i2c.h:1091
ll_i2c_disable_it_rx_done
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
Definition: gr55xx_ll_i2c.h:2013
ll_i2c_is_enabled
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
Definition: gr55xx_ll_i2c.h:387
ll_i2c_enable_it_restart_det
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
Definition: gr55xx_ll_i2c.h:1709
ll_i2c_is_active_flag_raw_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
Definition: gr55xx_ll_i2c.h:3033
ll_i2c_is_active_flag_raw_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
Definition: gr55xx_ll_i2c.h:3117
ll_i2c_set_clock_high_period_ss
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
Definition: gr55xx_ll_i2c.h:725
ll_i2c_is_active_flag_raw_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
Definition: gr55xx_ll_i2c.h:2991
ll_i2c_is_active_flag_raw_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
Definition: gr55xx_ll_i2c.h:2739
ll_i2c_disable_it_rx_under
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
Definition: gr55xx_ll_i2c.h:2412
ll_i2c_set_clock_low_period_fs
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
Definition: gr55xx_ll_i2c.h:845
ll_i2c_is_enable_it_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:2032
ll_i2c_handle_transfer
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
Definition: gr55xx_ll_i2c.h:3833
ll_i2c_clear_flag_gen_call
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
Definition: gr55xx_ll_i2c.h:3157
ll_i2c_get_transfer_direction
__STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
Indicate the value of transfer direction (slave mode).
Definition: gr55xx_ll_i2c.h:3858
ll_i2c_is_active_flag_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
Definition: gr55xx_ll_i2c.h:2676
ll_i2c_get_clock_high_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
Definition: gr55xx_ll_i2c.h:824
ll_i2c_enable_it_rx_abort
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:2051
ll_i2c_enable_it_tx_empty
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
Definition: gr55xx_ll_i2c.h:2165
ll_i2c_set_data_tx_hold_time
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
Definition: gr55xx_ll_i2c.h:1132
_ll_i2c_init::own_address
uint32_t own_address
Specifies the device own address.
Definition: gr55xx_ll_i2c.h:80
ll_i2c_disable
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
Definition: gr55xx_ll_i2c.h:368
ll_i2c_set_spike_len_fs
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
Definition: gr55xx_ll_i2c.h:965
ll_i2c_is_enabled_it_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
Definition: gr55xx_ll_i2c.h:1804
ll_i2c_disable_it_tx_abort
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
Definition: gr55xx_ll_i2c.h:2070
ll_i2c_is_active_flag_raw_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
Definition: gr55xx_ll_i2c.h:3075
ll_i2c_get_raw_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
Definition: gr55xx_ll_i2c.h:2529
ll_i2c_get_clock_low_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
Definition: gr55xx_ll_i2c.h:784
ll_i2c_transmit_data8
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
Definition: gr55xx_ll_i2c.h:3905
ll_i2c_enable_it_rx_full
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.
Definition: gr55xx_ll_i2c.h:2279