gr55xx_ll_i2s.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2s.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2S LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2S I2S
47 * @brief I2S LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (I2S_M) || defined (I2S_S)
63
64 /** @defgroup LL_I2S_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2S_LL_ES_INIT I2S Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2S init structures definition
75 */
76 typedef struct _ll_i2s_init_t
77 {
78 uint32_t rxdata_size; /**< Specifies the I2S receive data size.
79 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
80
81 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rxsize().*/
82
83 uint32_t txdata_size; /**< Specifies the I2S transmit data size.
84 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function @ref ll_i2s_set_txsize().*/
87
88 uint32_t rx_threshold; /**< Specifies the I2S receive FIFO threshold.
89 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
90
91 This feature can be modified afterwards using unitary function @ref ll_i2s_set_rx_fifo_threshold().*/
92
93 uint32_t tx_threshold; /**< Specifies the I2S transmit FIFO threshold.
94 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
95
96 This feature can be modified afterwards using unitary function @ref ll_i2s_set_tx_fifo_threshold().*/
97
98 uint32_t clock_source; /**< Specifies the source of the I2S clock.
99 This parameter can be a value of @ref I2S_LL_EC_CLOCK_SOURCE.
100
101 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_src().*/
102
103 uint32_t audio_freq; /**< Specifies the frequency selected for the I2S communication.
104
105 This feature can be modified afterwards using unitary function @ref ll_i2s_set_clock_div().*/
106
107 } ll_i2s_init_t;
108
109 /** @} */
110
111 /** @} */
112
113 /**
114 * @defgroup I2S_LL_MACRO Defines
115 * @{
116 */
117
118 /* Exported constants --------------------------------------------------------*/
119 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
120 * @{
121 */
122
123 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
124 * @brief Flags definitions which can be used with LL_I2S_ReadReg function
125 * @{
126 */
127 #define LL_I2S_STATUS_TXFO I2S_INTSTAT_TXFO /**< TX FIFO write overflow flag */
128 #define LL_I2S_STATUS_TXFE I2S_INTSTAT_TXFE /**< TX FIFO threshold level is not reached flag */
129 #define LL_I2S_STATUS_RXFO I2S_INTSTAT_RXFO /**< RX FIFO receive overflow flag */
130 #define LL_I2S_STATUS_RXDA I2S_INTSTAT_RXDA /**< RX FIFO threshold level is reached flag */
131 /** @} */
132
133 /** @defgroup I2S_LL_EC_INTERRUPT Interrupt Defines
134 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
135 * @{
136 */
137 #define LL_I2S_INT_TXFO I2S_INTMASK_TXFO /**< TX FIFO write overflow interrupt */
138 #define LL_I2S_INT_TXFE I2S_INTMASK_TXFE /**< TX FIFO threshold level is not reached interrupt */
139 #define LL_I2S_INT_RXFO I2S_INTMASK_RXFO /**< RX FIFO receive overflow interrupt */
140 #define LL_I2S_INT_RXDA I2S_INTMASK_RXDA /**< RX FIFO threshold level is reached interrupt */
141 /** @} */
142
143 /** @defgroup I2S_LL_EC_CLOCK_SOURCE I2S Clock Source
144 * @{
145 */
146 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL) /**< I2S clock source select: 96M */
147 #define LL_I2S_CLOCK_SRC_32M (1UL << 18) /**< I2S clock source select: 32M */
148 /** @} */
149
150 /** @defgroup I2S_LL_EC_DATASIZE Transfer Data width
151 * @{
152 */
153 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL) /**< Data size for I2S transfer: 32 bits */
154 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 12 bits */
155 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 16 bits */
156 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 20 bits */
157 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 24 bits */
158 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 32 bits */
159 /** @} */
160
161 /** @defgroup I2S_LL_EC_TRANSFER_MODE Transfer Mode
162 * @{
163 */
164 #define LL_I2S_SIMPLEX_TX (1UL) /**< Simplex TX mode. */
165 #define LL_I2S_SIMPLEX_RX (2UL) /**< Simplex RX mode. */
166 #define LL_I2S_FULL_DUPLEX (3UL) /**< Full-Duplex mode. */
167 /** @} */
168
169 /** @defgroup I2S_LL_EC_FIFO_THRESHOLD FIFO Threshold
170 * @{
171 */
172 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL) /**< Trigger level for FIFO: 1 depth. */
173 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 2 depth. */
174 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 3 depth. */
175 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 4 depth. */
176 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 5 depth. */
177 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 6 depth. */
178 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 7 depth. */
179 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 8 depth. */
180 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 9 depth. */
181 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 10 depth. */
182 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 11 depth. */
183 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 12 depth. */
184 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 13 depth. */
185 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 14 depth. */
186 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 15 depth. */
187 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 16 depth. */
188 /** @} */
189
190 /** @defgroup I2S_LL_EC_WS_CYCLES Word Select Line Cycles
191 * @{
192 */
193 #define LL_I2S_WS_CYCLES_16 (0x00000000UL) /**< 16 SCLK cycles in word select line. */
194 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_CLKCONFIG_WSS_Pos) /**< 24 SCLK cycles in word select line. */
195 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_CLKCONFIG_WSS_Pos) /**< 32 SCLK cycles in word select line. */
196 /** @} */
197
198 /** @defgroup I2S_LL_EC_SCLK_GATE SCLK Gate
199 * @{
200 */
201 #define LL_I2S_SCLKG_NONE (0x00000000UL) /**< Clock gating is disabled. */
202 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 12 sclk cycles. */
203 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 16 sclk cycles. */
204 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 20 sclk cycles. */
205 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 24 sclk cycles. */
206 /** @} */
207
208 /** @defgroup I2S_LL_EC_RESOLUTION RX/TX resolution of one channel
209 * @{
210 */
211 #define LL_I2S_RESOLUTION_12BIT (0UL) /**< 12 bits resolution. */
212 #define LL_I2S_RESOLUTION_16BIT (1UL) /**< 16 bits resolution. */
213 #define LL_I2S_RESOLUTION_20BIT (2UL) /**< 20 bits resolution. */
214 #define LL_I2S_RESOLUTION_24BIT (3UL) /**< 24 bits resolution. */
215 #define LL_I2S_RESOLUTION_32BIT (4UL) /**< 32 bits resolution. */
216 /** @} */
217
218 /** @defgroup I2S_LL_EC_CHANNELS the number of RX/TX channels
219 * @{
220 */
221 #define LL_I2S_CHANNEL_NUM_1 (0UL) /**< 1 channel. */
222 #define LL_I2S_CHANNEL_NUM_2 (1UL) /**< 2 channels. */
223 #define LL_I2S_CHANNEL_NUM_3 (2UL) /**< 3 channels. */
224 #define LL_I2S_CHANNEL_NUM_4 (3UL) /**< 4 channels. */
225 /** @} */
226
227 /** @defgroup I2S_LL_EC_FIFO_DEPTH RX/TX FIFO depth
228 * @{
229 */
230 #define LL_I2S_FIFO_DEPTH_2 (0UL) /**< FIFO depth is 2 . */
231 #define LL_I2S_FIFO_DEPTH_4 (1UL) /**< FIFO depth is 4 . */
232 #define LL_I2S_FIFO_DEPTH_8 (2UL) /**< FIFO depth is 8 . */
233 #define LL_I2S_FIFO_DEPTH_16 (3UL) /**< FIFO depth is 16. */
234 /** @} */
235
236 /** @defgroup I2S_LL_EC_APB_WIDTH APB data width
237 * @{
238 */
239 #define LL_I2S_APB_WIDTH_8BIT (0UL) /**< 8 bits APB data width. */
240 #define LL_I2S_APB_WIDTH_16BIT (1UL) /**< 16 bits APB data width. */
241 #define LL_I2S_APB_WIDTH_32BIT (2UL) /**< 32 bits APB data width. */
242 /** @} */
243
244 /** @} */
245
246 /** @defgroup I2S_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
247 * @{
248 */
249
250 /**
251 * @brief LL I2S InitStrcut default configuartion
252 */
253 #define LL_I2S_DEFAULT_CONFIG \
254 { \
255 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
256 .txdata_size = LL_I2S_DATASIZE_16BIT, \
257 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
258 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
259 .clock_source = LL_I2S_CLOCK_SRC_32M, \
260 .audio_freq = 48000 \
261 }
262
263 /** @} */
264
265 /* Exported macro ------------------------------------------------------------*/
266 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
267 * @{
268 */
269
270 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
271 * @{
272 */
273
274 /**
275 * @brief Write a value in I2S register
276 * @param __instance__ I2S instance
277 * @param __REG__ Register to be written
278 * @param __VALUE__ Value to be written in the register
279 * @retval None
280 */
281 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
282
283 /**
284 * @brief Read a value in I2S register
285 * @param __instance__ I2S instance
286 * @param __REG__ Register to be read
287 * @retval Register value
288 */
289 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
290
291 /** @} */
292
293 /** @} */
294 /** @} */
295
296 /* Exported functions --------------------------------------------------------*/
297 /** @defgroup I2S_LL_DRIVER_FUNCTIONS Functions
298 * @{
299 */
300
301 /** @defgroup I2S_LL_EF_Configuration Configuration functions
302 * @{
303 */
304
305 /**
306 * @brief Enable I2S
307 *
308 * \rst
309 * +----------------------+-----------------------------------+
310 * | Register | BitsName |
311 * +======================+===================================+
312 * | ENABLE | EN |
313 * +----------------------+-----------------------------------+
314 * \endrst
315 *
316 * @param I2Sx I2S instance
317 * @retval None
318 */
319 __STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
320 {
321 SET_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
322 }
323
324 /**
325 * @brief Disable I2S
326 *
327 * \rst
328 * +----------------------+-----------------------------------+
329 * | Register | BitsName |
330 * +======================+===================================+
331 * | ENABLE | EN |
332 * +----------------------+-----------------------------------+
333 * \endrst
334 *
335 * @param I2Sx I2S instance
336 * @retval None
337 */
338 __STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
339 {
340 CLEAR_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
341 }
342
343 /**
344 * @brief Check if I2S is enabled
345 *
346 * \rst
347 * +----------------------+-----------------------------------+
348 * | Register | BitsName |
349 * +======================+===================================+
350 * | ENABLE | EN |
351 * +----------------------+-----------------------------------+
352 * \endrst
353 *
354 * @param I2Sx I2S instance
355 * @retval State of bit (1 or 0).
356 */
357 __STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
358 {
359 return (READ_BITS(I2Sx->ENABLE, I2S_ENABLE_EN) == (I2S_ENABLE_EN));
360 }
361
362 /**
363 * @brief Enable I2S RX block
364 *
365 * \rst
366 * +----------------------+-----------------------------------+
367 * | Register | BitsName |
368 * +======================+===================================+
369 * | RBEN | EN |
370 * +----------------------+-----------------------------------+
371 * \endrst
372 *
373 * @param I2Sx I2S instance
374 * @retval None
375 */
376 __STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
377 {
378 SET_BITS(I2Sx->RBEN, I2S_RBEN_EN);
379 }
380
381 /**
382 * @brief Disable I2S RX block
383 *
384 * \rst
385 * +----------------------+-----------------------------------+
386 * | Register | BitsName |
387 * +======================+===================================+
388 * | RBEN | EN |
389 * +----------------------+-----------------------------------+
390 * \endrst
391 *
392 * @param I2Sx I2S instance
393 * @retval None
394 */
395 __STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
396 {
397 CLEAR_BITS(I2Sx->RBEN, I2S_RBEN_EN);
398 }
399
400 /**
401 * @brief Check if I2S RX block is enabled
402 *
403 * \rst
404 * +----------------------+-----------------------------------+
405 * | Register | BitsName |
406 * +======================+===================================+
407 * | RBEN | EN |
408 * +----------------------+-----------------------------------+
409 * \endrst
410 *
411 * @param I2Sx I2S instance
412 * @retval State of bit (1 or 0).
413 */
414 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
415 {
416 return (READ_BITS(I2Sx->RBEN, I2S_RBEN_EN) == (I2S_RBEN_EN));
417 }
418
419 /**
420 * @brief Enable I2S TX block
421 *
422 * \rst
423 * +----------------------+-----------------------------------+
424 * | Register | BitsName |
425 * +======================+===================================+
426 * | TBEN | EN |
427 * +----------------------+-----------------------------------+
428 * \endrst
429 *
430 * @param I2Sx I2S instance
431 * @retval None
432 */
433 __STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
434 {
435 SET_BITS(I2Sx->TBEN, I2S_TBEN_EN);
436 }
437
438 /**
439 * @brief Disable I2S TX block
440 *
441 * \rst
442 * +----------------------+-----------------------------------+
443 * | Register | BitsName |
444 * +======================+===================================+
445 * | TBEN | EN |
446 * +----------------------+-----------------------------------+
447 * \endrst
448 *
449 * @param I2Sx I2S instance
450 * @retval None
451 */
452 __STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
453 {
454 CLEAR_BITS(I2Sx->TBEN, I2S_TBEN_EN);
455 }
456
457 /**
458 * @brief Check if I2S TX block is enabled
459 *
460 * \rst
461 * +----------------------+-----------------------------------+
462 * | Register | BitsName |
463 * +======================+===================================+
464 * | TBEN | EN |
465 * +----------------------+-----------------------------------+
466 * \endrst
467 *
468 * @param I2Sx I2S instance
469 * @retval State of bit (1 or 0).
470 */
471 __STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
472 {
473 return (READ_BITS(I2Sx->TBEN, I2S_TBEN_EN) == (I2S_TBEN_EN));
474 }
475
476 /**
477 * @brief Enable I2S clock
478 *
479 * \rst
480 * +----------------------+-----------------------------------+
481 * | Register | BitsName |
482 * +======================+===================================+
483 * | CLKEN | EN |
484 * +----------------------+-----------------------------------+
485 * \endrst
486 *
487 * @param I2Sx I2S instance
488 * @retval None
489 */
490 __STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
491 {
492 SET_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
493 }
494
495 /**
496 * @brief Disable I2S clock
497 *
498 * \rst
499 * +----------------------+-----------------------------------+
500 * | Register | BitsName |
501 * +======================+===================================+
502 * | CLKEN | EN |
503 * +----------------------+-----------------------------------+
504 * \endrst
505 *
506 * @param I2Sx I2S instance
507 * @retval None
508 */
509 __STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
510 {
511 CLEAR_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
512 }
513
514 /**
515 * @brief Check if I2S clock is enabled
516 *
517 * \rst
518 * +----------------------+-----------------------------------+
519 * | Register | BitsName |
520 * +======================+===================================+
521 * | CLKEN | EN |
522 * +----------------------+-----------------------------------+
523 * \endrst
524 *
525 * @param I2Sx I2S instance
526 * @retval State of bit (1 or 0).
527 */
528 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
529 {
530 return (READ_BITS(I2Sx->CLKEN, I2S_CLKEN_EN) == (I2S_CLKEN_EN));
531 }
532
533 /**
534 * @brief Set word select line cycles for left or right sample
535 * @note This bit should be written only when I2S is disabled (I2S_EN = 0) for correct operation.
536 *
537 * \rst
538 * +----------------------+-----------------------------------+
539 * | Register | BitsName |
540 * +======================+===================================+
541 * | CLKCONFIG | WSS |
542 * +----------------------+-----------------------------------+
543 * \endrst
544 *
545 * @param I2Sx I2S instance
546 * @param cycles This parameter can be one of the following values:
547 * @arg @ref LL_I2S_WS_CYCLES_16
548 * @arg @ref LL_I2S_WS_CYCLES_24
549 * @arg @ref LL_I2S_WS_CYCLES_32
550 * @retval None
551 */
552 __STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
553 {
554 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS, cycles);
555 }
556
557 /**
558 * @brief Get word select line cycles for left or right sample
559 *
560 * \rst
561 * +----------------------+-----------------------------------+
562 * | Register | BitsName |
563 * +======================+===================================+
564 * | CLKCONFIG | WSS |
565 * +----------------------+-----------------------------------+
566 * \endrst
567 *
568 * @param I2Sx I2S instance
569 * @retval Returned Value can be one of the following values:
570 * @arg @ref LL_I2S_WS_CYCLES_16
571 * @arg @ref LL_I2S_WS_CYCLES_24
572 * @arg @ref LL_I2S_WS_CYCLES_32
573 */
574 __STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
575 {
576 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS));
577 }
578
579 /**
580 * @brief Set the gating of sclk
581 *
582 * \rst
583 * +----------------------+-----------------------------------+
584 * | Register | BitsName |
585 * +======================+===================================+
586 * | CLKCONFIG | SCLKG |
587 * +----------------------+-----------------------------------+
588 * \endrst
589 *
590 * @param I2Sx I2S instance
591 * @param cycles This parameter can be one of the following values:
592 * @arg @ref LL_I2S_SCLKG_NONE
593 * @arg @ref LL_I2S_SCLKG_CYCLES_12
594 * @arg @ref LL_I2S_SCLKG_CYCLES_16
595 * @arg @ref LL_I2S_SCLKG_CYCLES_20
596 * @arg @ref LL_I2S_SCLKG_CYCLES_24
597 * @retval None
598 */
599 __STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
600 {
601 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG, cycles);
602 }
603
604 /**
605 * @brief Get the gating of sclk
606 *
607 * \rst
608 * +----------------------+-----------------------------------+
609 * | Register | BitsName |
610 * +======================+===================================+
611 * | CLKCONFIG | SCLKG |
612 * +----------------------+-----------------------------------+
613 * \endrst
614 *
615 * @param I2Sx I2S instance
616 * @retval Returned Value can be one of the following values:
617 * @arg @ref LL_I2S_SCLKG_NONE
618 * @arg @ref LL_I2S_SCLKG_CYCLES_12
619 * @arg @ref LL_I2S_SCLKG_CYCLES_16
620 * @arg @ref LL_I2S_SCLKG_CYCLES_20
621 * @arg @ref LL_I2S_SCLKG_CYCLES_24
622 */
623 __STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
624 {
625 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG));
626 }
627
628 /**
629 * @brief Clear I2S RX FIFO in all channels
630 *
631 * \rst
632 * +----------------------+-----------------------------------+
633 * | Register | BitsName |
634 * +======================+===================================+
635 * | RXFIFO_RST | RST |
636 * +----------------------+-----------------------------------+
637 * \endrst
638 *
639 * @param I2Sx I2S instance
640 * @retval None
641 */
642 __STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
643 {
644 WRITE_REG(I2Sx->RXFIFO_RST, I2S_RXFIFO_RST);
645 }
646
647 /**
648 * @brief Clear I2S TX FIFO in all channels
649 *
650 * \rst
651 * +----------------------+-----------------------------------+
652 * | Register | BitsName |
653 * +======================+===================================+
654 * | TXFIFO_RST | RST |
655 * +----------------------+-----------------------------------+
656 * \endrst
657 *
658 * @param I2Sx I2S instance
659 * @retval None
660 */
661 __STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
662 {
663 WRITE_REG(I2Sx->TXFIFO_RST, I2S_TXFIFO_RST);
664 }
665
666 /**
667 * @brief Set I2S clock divider
668 *
669 * \rst
670 * +----------------------+-----------------------------------+
671 * | Register | BitsName |
672 * +======================+===================================+
673 * | I2S_CLK_CFG | DIV |
674 * +----------------------+-----------------------------------+
675 * \endrst
676 *
677 * @param div This parameter can between: 0 ~ 0xFFF
678 * @retval None
679 */
680 __STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
681 {
682 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
683 }
684
685 /**
686 * @brief Get I2S clock divider
687 *
688 * \rst
689 * +----------------------+-----------------------------------+
690 * | Register | BitsName |
691 * +======================+===================================+
692 * | I2S_CLK_CFG | DIV |
693 * +----------------------+-----------------------------------+
694 * \endrst
695 *
696 * @retval Returned Value can between: 0 ~ 0xFFF
697 */
698 __STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
699 {
700 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
701 }
702
703 /**
704 * @brief Enable I2S clock divider
705 *
706 * \rst
707 * +----------------------+-----------------------------------+
708 * | Register | BitsName |
709 * +======================+===================================+
710 * | I2S_CLK_CFG | DIV_EN |
711 * +----------------------+-----------------------------------+
712 * \endrst
713 *
714 * @retval None
715 */
716 __STATIC_INLINE void ll_i2s_enable_clock_div(void)
717 {
718 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
719 }
720
721 /**
722 * @brief Disable I2S clock divider
723 *
724 * \rst
725 * +----------------------+-----------------------------------+
726 * | Register | BitsName |
727 * +======================+===================================+
728 * | I2S_CLK_CFG | DIV_EN |
729 * +----------------------+-----------------------------------+
730 * \endrst
731 *
732 * @retval None
733 */
734 __STATIC_INLINE void ll_i2s_disable_clock_div(void)
735 {
736 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
737 }
738
739 /**
740 * @brief Check if I2S clock divider is enabled
741 *
742 * \rst
743 * +----------------------+-----------------------------------+
744 * | Register | BitsName |
745 * +======================+===================================+
746 * | I2S_CLK_CFG | DIV_EN |
747 * +----------------------+-----------------------------------+
748 * \endrst
749 *
750 * @retval State of bit (1 or 0).
751 */
752 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
753 {
754 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
755 }
756
757 /**
758 * @brief Set I2S clock source
759 *
760 * \rst
761 * +----------------------+-----------------------------------+
762 * | Register | BitsName |
763 * +======================+===================================+
764 * | I2S_CLK_CFG | SRC |
765 * +----------------------+-----------------------------------+
766 * \endrst
767 *
768 * @param src This parameter can be one of the following values:
769 * @arg @ref LL_I2S_CLOCK_SRC_96M
770 * @arg @ref LL_I2S_CLOCK_SRC_32M
771 * @retval None
772 */
773 __STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
774 {
775 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
776 }
777
778 /**
779 * @brief Get I2S clock source
780 *
781 * \rst
782 * +----------------------+-----------------------------------+
783 * | Register | BitsName |
784 * +======================+===================================+
785 * | I2S_CLK_CFG | SRC |
786 * +----------------------+-----------------------------------+
787 * \endrst
788 *
789 * @retval Returned Value can be one of the following values:
790 * @arg @ref LL_I2S_CLOCK_SRC_96M
791 * @arg @ref LL_I2S_CLOCK_SRC_32M
792 */
793 __STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
794 {
795 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
796 }
797
798 /** @} */
799
800 /** @defgroup I2S_LL_EF_Channel Channel Configuration functions
801 * @{
802 */
803
804 /**
805 * @brief Read one data from left RX FIFO in a channel
806 *
807 * \rst
808 * +----------------------+-----------------------------------+
809 * | Register | BitsName |
810 * +======================+===================================+
811 * | DATA_L | DATA |
812 * +----------------------+-----------------------------------+
813 * \endrst
814 *
815 * @param I2Sx I2S instance
816 * @param channel The special channel: 0 ~ 3
817 * @retval None
818 */
819 __STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
820 {
821 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_L));
822 }
823
824 /**
825 * @brief Read one data from right RX FIFO in a channel
826 *
827 * \rst
828 * +----------------------+-----------------------------------+
829 * | Register | BitsName |
830 * +======================+===================================+
831 * | DATA_R | DATA |
832 * +----------------------+-----------------------------------+
833 * \endrst
834 *
835 * @param I2Sx I2S instance
836 * @param channel The special channel: 0 ~ 3
837 * @retval None
838 */
839 __STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
840 {
841 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_R));
842 }
843
844 /**
845 * @brief Write one data to left TX FIFO in a channel
846 *
847 * \rst
848 * +----------------------+-----------------------------------+
849 * | Register | BitsName |
850 * +======================+===================================+
851 * | DATA_L | DATA |
852 * +----------------------+-----------------------------------+
853 * \endrst
854 *
855 * @param I2Sx I2S instance
856 * @param channel The special channel: 0 ~ 3
857 * @param data The data to send
858 * @retval None
859 */
860 __STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
861 {
862 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_L, data);
863 }
864
865 /**
866 * @brief Write one data to right TX FIFO in a channel
867 *
868 * \rst
869 * +----------------------+-----------------------------------+
870 * | Register | BitsName |
871 * +======================+===================================+
872 * | DATA_R | DATA |
873 * +----------------------+-----------------------------------+
874 * \endrst
875 *
876 * @param I2Sx I2S instance
877 * @param channel The special channel: 0 ~ 3
878 * @param data The data to send
879 * @retval None
880 */
881 __STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
882 {
883 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_R, data);
884 }
885
886 /**
887 * @brief Enable RX in a channel
888 *
889 * \rst
890 * +----------------------+-----------------------------------+
891 * | Register | BitsName |
892 * +======================+===================================+
893 * | RXEN | EN |
894 * +----------------------+-----------------------------------+
895 * \endrst
896 *
897 * @param I2Sx I2S instance
898 * @param channel The special channel: 0 ~ 3
899 * @retval None
900 */
901 __STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
902 {
903 SET_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
904 }
905
906 /**
907 * @brief Disable RX in a channel
908 *
909 * \rst
910 * +----------------------+-----------------------------------+
911 * | Register | BitsName |
912 * +======================+===================================+
913 * | RXEN | EN |
914 * +----------------------+-----------------------------------+
915 * \endrst
916 *
917 * @param I2Sx I2S instance
918 * @param channel The special channel: 0 ~ 3
919 * @retval None
920 */
921 __STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
922 {
923 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
924 }
925
926 /**
927 * @brief Check if RX in a channel is enabled
928 *
929 * \rst
930 * +----------------------+-----------------------------------+
931 * | Register | BitsName |
932 * +======================+===================================+
933 * | RXEN | EN |
934 * +----------------------+-----------------------------------+
935 * \endrst
936 *
937 * @param I2Sx I2S instance
938 * @param channel The special channel: 0 ~ 3
939 * @retval State of bit (1 or 0).
940 */
941 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
942 {
943 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN) != (I2S_RXEN_EN));
944 }
945
946 /**
947 * @brief Enable TX in a channel
948 *
949 * \rst
950 * +----------------------+-----------------------------------+
951 * | Register | BitsName |
952 * +======================+===================================+
953 * | TXEN | EN |
954 * +----------------------+-----------------------------------+
955 * \endrst
956 *
957 * @param I2Sx I2S instance
958 * @param channel The special channel: 0 ~ 3
959 * @retval None
960 */
961 __STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
962 {
963 SET_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
964 }
965
966 /**
967 * @brief Disable TX in a channel
968 *
969 * \rst
970 * +----------------------+-----------------------------------+
971 * | Register | BitsName |
972 * +======================+===================================+
973 * | TXEN | EN |
974 * +----------------------+-----------------------------------+
975 * \endrst
976 *
977 * @param I2Sx I2S instance
978 * @param channel The special channel: 0 ~ 3
979 * @retval None
980 */
981 __STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
982 {
983 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
984 }
985
986 /**
987 * @brief Check if TX in a channel is enabled
988 *
989 * \rst
990 * +----------------------+-----------------------------------+
991 * | Register | BitsName |
992 * +======================+===================================+
993 * | TXEN | EN |
994 * +----------------------+-----------------------------------+
995 * \endrst
996 *
997 * @param I2Sx I2S instance
998 * @param channel The special channel: 0 ~ 3
999 * @retval State of bit (1 or 0).
1000 */
1001 __STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
1002 {
1003 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN) != (I2S_TXEN_EN));
1004 }
1005
1006 /**
1007 * @brief Set receive data width in a channel
1008 * @note These bits should not be changed when channel is enabled.
1009 *
1010 * \rst
1011 * +----------------------+-----------------------------------+
1012 * | Register | BitsName |
1013 * +======================+===================================+
1014 * | RXSIZE | WLEN |
1015 * +----------------------+-----------------------------------+
1016 * \endrst
1017 *
1018 * @param I2Sx I2S instance
1019 * @param channel The special channel: 0 ~ 3
1020 * @param size This parameter can be one of the following values:
1021 * @arg @ref LL_I2S_DATASIZE_IGNORE
1022 * @arg @ref LL_I2S_DATASIZE_12BIT
1023 * @arg @ref LL_I2S_DATASIZE_16BIT
1024 * @arg @ref LL_I2S_DATASIZE_20BIT
1025 * @arg @ref LL_I2S_DATASIZE_24BIT
1026 * @arg @ref LL_I2S_DATASIZE_32BIT
1027 * @retval None
1028 */
1029 __STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
1030 {
1031 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN, size);
1032 }
1033
1034 /**
1035 * @brief Get receive data width in a channel
1036 *
1037 * \rst
1038 * +----------------------+-----------------------------------+
1039 * | Register | BitsName |
1040 * +======================+===================================+
1041 * | RXSIZE | WLEN |
1042 * +----------------------+-----------------------------------+
1043 * \endrst
1044 *
1045 * @param I2Sx I2S instance
1046 * @param channel The special channel: 0 ~ 3
1047 * @retval Returned Value can be one of the following values:
1048 * @arg @ref LL_I2S_DATASIZE_IGNORE
1049 * @arg @ref LL_I2S_DATASIZE_12BIT
1050 * @arg @ref LL_I2S_DATASIZE_16BIT
1051 * @arg @ref LL_I2S_DATASIZE_20BIT
1052 * @arg @ref LL_I2S_DATASIZE_24BIT
1053 * @arg @ref LL_I2S_DATASIZE_32BIT
1054 */
1055 __STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
1056 {
1057 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN));
1058 }
1059
1060 /**
1061 * @brief Set transmit data width in a channel
1062 * @note These bits should not be changed when channel is enabled.
1063 *
1064 * \rst
1065 * +----------------------+-----------------------------------+
1066 * | Register | BitsName |
1067 * +======================+===================================+
1068 * | TXSIZE | WLEN |
1069 * +----------------------+-----------------------------------+
1070 * \endrst
1071 *
1072 * @param I2Sx I2S instance
1073 * @param channel The special channel: 0 ~ 3
1074 * @param size This parameter can be one of the following values:
1075 * @arg @ref LL_I2S_DATASIZE_IGNORE
1076 * @arg @ref LL_I2S_DATASIZE_12BIT
1077 * @arg @ref LL_I2S_DATASIZE_16BIT
1078 * @arg @ref LL_I2S_DATASIZE_20BIT
1079 * @arg @ref LL_I2S_DATASIZE_24BIT
1080 * @arg @ref LL_I2S_DATASIZE_32BIT
1081 * @retval None
1082 */
1083 __STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
1084 {
1085 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN, size);
1086 }
1087
1088 /**
1089 * @brief Get transmit data width in a channel
1090 *
1091 * \rst
1092 * +----------------------+-----------------------------------+
1093 * | Register | BitsName |
1094 * +======================+===================================+
1095 * | TXSIZE | WLEN |
1096 * +----------------------+-----------------------------------+
1097 * \endrst
1098 *
1099 * @param I2Sx I2S instance
1100 * @param channel The special channel: 0 ~ 3
1101 * @retval Returned Value can be one of the following values:
1102 * @arg @ref LL_I2S_DATASIZE_IGNORE
1103 * @arg @ref LL_I2S_DATASIZE_12BIT
1104 * @arg @ref LL_I2S_DATASIZE_16BIT
1105 * @arg @ref LL_I2S_DATASIZE_20BIT
1106 * @arg @ref LL_I2S_DATASIZE_24BIT
1107 * @arg @ref LL_I2S_DATASIZE_32BIT
1108 */
1109 __STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
1110 {
1111 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN));
1112 }
1113
1114 /**
1115 * @brief Get interrupt flag in a channel
1116 *
1117 * \rst
1118 * +----------------------+-----------------------------------+
1119 * | Register | BitsName |
1120 * +======================+===================================+
1121 * | INTSTAT | TXFO |
1122 * +----------------------+-----------------------------------+
1123 * \endrst
1124 * INTSTAT | TXFE
1125 * INTSTAT | RXFO
1126 * INTSTAT | RXDA
1127 *
1128 * @param I2Sx I2S instance
1129 * @param channel The special channel: 0 ~ 3
1130 * @retval Returned Value can be one or more of the following values:
1131 * @arg @ref LL_I2S_STATUS_TXFO
1132 * @arg @ref LL_I2S_STATUS_TXFE
1133 * @arg @ref LL_I2S_STATUS_RXFO
1134 * @arg @ref LL_I2S_STATUS_RXDA
1135 */
1136 __STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
1137 {
1138 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, I2S_INTSTAT_TXFO | I2S_INTSTAT_TXFE | \
1139 I2S_INTSTAT_RXFO | I2S_INTSTAT_RXDA));
1140 }
1141
1142 /**
1143 * @brief Check interrupt flag in a channel
1144 *
1145 * \rst
1146 * +----------------------+-----------------------------------+
1147 * | Register | BitsName |
1148 * +======================+===================================+
1149 * | INTSTAT | TXFO |
1150 * +----------------------+-----------------------------------+
1151 * \endrst
1152 * INTSTAT | TXFE
1153 * INTSTAT | RXFO
1154 * INTSTAT | RXDA
1155 *
1156 * @param I2Sx I2S instance
1157 * @param channel The special channel: 0 ~ 3
1158 * @param flag This parameter can be one or more of the following values:
1159 * @arg @ref LL_I2S_STATUS_TXFO
1160 * @arg @ref LL_I2S_STATUS_TXFE
1161 * @arg @ref LL_I2S_STATUS_RXFO
1162 * @arg @ref LL_I2S_STATUS_RXDA
1163 * @retval State of bit (1 or 0).
1164 */
1165 __STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
1166 {
1167 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, flag) == flag);
1168 }
1169
1170 /**
1171 * @brief Enable interrupt in a channel
1172 *
1173 * \rst
1174 * +----------------------+-----------------------------------+
1175 * | Register | BitsName |
1176 * +======================+===================================+
1177 * | INTMASK | TXFO |
1178 * +----------------------+-----------------------------------+
1179 * \endrst
1180 * INTMASK | TXFE
1181 * INTMASK | RXFO
1182 * INTMASK | RXDA
1183 *
1184 * @param I2Sx I2S instance
1185 * @param channel The special channel: 0 ~ 3
1186 * @param mask This parameter can be one or more of the following values:
1187 * @arg @ref LL_I2S_INT_TXFO
1188 * @arg @ref LL_I2S_INT_TXFE
1189 * @arg @ref LL_I2S_INT_RXFO
1190 * @arg @ref LL_I2S_INT_RXDA
1191 * @retval None
1192 */
1193 __STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1194 {
1195 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1196 }
1197
1198 /**
1199 * @brief Disable interrupt in a channel
1200 *
1201 * \rst
1202 * +----------------------+-----------------------------------+
1203 * | Register | BitsName |
1204 * +======================+===================================+
1205 * | INTMASK | TXFO |
1206 * +----------------------+-----------------------------------+
1207 * \endrst
1208 * INTMASK | TXFE
1209 * INTMASK | RXFO
1210 * INTMASK | RXDA
1211 *
1212 * @param I2Sx I2S instance
1213 * @param channel The special channel: 0 ~ 3
1214 * @param mask This parameter can be one or more of the following values:
1215 * @arg @ref LL_I2S_INT_TXFO
1216 * @arg @ref LL_I2S_INT_TXFE
1217 * @arg @ref LL_I2S_INT_RXFO
1218 * @arg @ref LL_I2S_INT_RXDA
1219 * @retval None
1220 */
1221 __STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1222 {
1223 SET_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1224 }
1225
1226 /**
1227 * @brief Check if interrupt in a channel is enabled
1228 *
1229 * \rst
1230 * +----------------------+-----------------------------------+
1231 * | Register | BitsName |
1232 * +======================+===================================+
1233 * | INTMASK | TXFO |
1234 * +----------------------+-----------------------------------+
1235 * \endrst
1236 * INTMASK | TXFE
1237 * INTMASK | RXFO
1238 * INTMASK | RXDA
1239 *
1240 * @param I2Sx I2S instance
1241 * @param channel The special channel: 0 ~ 3
1242 * @param mask This parameter can be one or more of the following values:
1243 * @arg @ref LL_I2S_INT_TXFO
1244 * @arg @ref LL_I2S_INT_TXFE
1245 * @arg @ref LL_I2S_INT_RXFO
1246 * @arg @ref LL_I2S_INT_RXDA
1247 * @retval State of bit (1 or 0).
1248 */
1249 __STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1250 {
1251 return ((READ_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask) ^ (mask)) == (mask));
1252 }
1253
1254 /**
1255 * @brief Clear RX FIFO data overrun interrupt flag in a channel
1256 *
1257 * \rst
1258 * +----------------------+-----------------------------------+
1259 * | Register | BitsName |
1260 * +======================+===================================+
1261 * | RXOVR | RXCHO |
1262 * +----------------------+-----------------------------------+
1263 * \endrst
1264 *
1265 * @param I2Sx I2S instance
1266 * @param channel The special channel: 0 ~ 3
1267 * @retval State of bit (1 or 0).
1268 */
1269 __STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
1270 {
1271 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXOVR, I2S_RXOVR_RXCHO));
1272 }
1273
1274 /**
1275 * @brief Clear TX FIFO data overrun interrupt flag in a channel
1276 *
1277 * \rst
1278 * +----------------------+-----------------------------------+
1279 * | Register | BitsName |
1280 * +======================+===================================+
1281 * | TXOVR | TXCHO |
1282 * +----------------------+-----------------------------------+
1283 * \endrst
1284 *
1285 * @param I2Sx I2S instance
1286 * @param channel The special channel: 0 ~ 3
1287 * @retval State of bit (1 or 0).
1288 */
1289 __STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
1290 {
1291 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXOVR, I2S_TXOVR_TXCHO));
1292 }
1293
1294 /**
1295 * @brief Set threshold of RXFIFO in a channel that triggers an RXDA event
1296 *
1297 * \rst
1298 * +----------------------+-----------------------------------+
1299 * | Register | BitsName |
1300 * +======================+===================================+
1301 * | RXFIFO_TL | TL |
1302 * +----------------------+-----------------------------------+
1303 * \endrst
1304 *
1305 * @param I2Sx I2S instance
1306 * @param channel The special channel: 0 ~ 3
1307 * @param threshold This parameter can be one of the following values:
1308 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1309 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1310 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1311 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1312 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1313 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1314 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1315 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1316 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1317 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1318 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1319 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1320 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1321 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1322 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1323 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1324 * @retval None
1325 */
1326 __STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1327 {
1328 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, threshold);
1329 }
1330
1331 /**
1332 * @brief Get threshold of RXFIFO in a channel that triggers an RXDA event
1333 *
1334 * \rst
1335 * +----------------------+-----------------------------------+
1336 * | Register | BitsName |
1337 * +======================+===================================+
1338 * | RXFIFO_TL | TL |
1339 * +----------------------+-----------------------------------+
1340 * \endrst
1341 *
1342 * @param I2Sx I2S instance
1343 * @param channel The special channel: 0 ~ 3
1344 * @retval Returned Value can be one of the following values:
1345 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1346 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1347 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1348 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1349 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1350 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1351 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1352 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1353 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1354 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1355 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1356 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1357 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1358 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1359 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1360 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1361 */
1362 __STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1363 {
1364 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, I2S_RXFIFO_TL));
1365 }
1366
1367 /**
1368 * @brief Set threshold of TXFIFO in a channel that triggers an TXFE event
1369 *
1370 * \rst
1371 * +----------------------+-----------------------------------+
1372 * | Register | BitsName |
1373 * +======================+===================================+
1374 * | TXFIFO_TL | TL |
1375 * +----------------------+-----------------------------------+
1376 * \endrst
1377 *
1378 * @param I2Sx I2S instance
1379 * @param channel The special channel: 0 ~ 3
1380 * @param threshold This parameter can be one of the following values:
1381 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1382 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1383 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1384 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1385 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1386 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1387 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1388 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1389 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1390 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1391 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1392 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1393 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1394 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1395 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1396 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1397 * @retval None
1398 */
1399 __STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1400 {
1401 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, threshold);
1402 }
1403
1404 /**
1405 * @brief Get threshold of TXFIFO in a channel that triggers an TXFE event
1406 *
1407 * \rst
1408 * +----------------------+-----------------------------------+
1409 * | Register | BitsName |
1410 * +======================+===================================+
1411 * | TXFIFO_TL | TL |
1412 * +----------------------+-----------------------------------+
1413 * \endrst
1414 *
1415 * @param I2Sx I2S instance
1416 * @param channel The special channel: 0 ~ 3
1417 * @retval Returned Value can be one of the following values:
1418 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1419 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1420 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1421 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1422 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1423 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1424 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1425 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1426 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1427 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1428 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1429 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1430 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1431 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1432 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1433 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1434 */
1435 __STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1436 {
1437 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, I2S_TXFIFO_TL));
1438 }
1439
1440 /**
1441 * @brief Clear RX FIFO data in a channel
1442 *
1443 * \rst
1444 * +----------------------+-----------------------------------+
1445 * | Register | BitsName |
1446 * +======================+===================================+
1447 * | RXFIFO_FLUSH | FLUSH |
1448 * +----------------------+-----------------------------------+
1449 * \endrst
1450 *
1451 * @param I2Sx I2S instance
1452 * @param channel The special channel: 0 ~ 3
1453 * @retval None
1454 */
1455 __STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1456 {
1457 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_FLUSH, I2S_RXFIFO_FLUSH);
1458 }
1459
1460 /**
1461 * @brief Clear TX FIFO data in a channel
1462 *
1463 * \rst
1464 * +----------------------+-----------------------------------+
1465 * | Register | BitsName |
1466 * +======================+===================================+
1467 * | TXFIFO_FLUSH | FLUSH |
1468 * +----------------------+-----------------------------------+
1469 * \endrst
1470 *
1471 * @param I2Sx I2S instance
1472 * @param channel The special channel: 0 ~ 3
1473 * @retval None
1474 */
1475 __STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1476 {
1477 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_FLUSH, I2S_TXFIFO_FLUSH);
1478 }
1479
1480 /** @} */
1481
1482 /** @defgroup I2S_LL_EF_DMA_Management DMA Management Functions
1483 * @{
1484 */
1485
1486 /**
1487 * @brief Reset RX block DMA
1488 * @note The RX DMA can be reset to the lowest channel via this register.
1489 *
1490 * \rst
1491 * +----------------------+-----------------------------------+
1492 * | Register | BitsName |
1493 * +======================+===================================+
1494 * | RXDMA_RST | RST |
1495 * +----------------------+-----------------------------------+
1496 * \endrst
1497 *
1498 * @param I2Sx I2S instance
1499 * @retval None
1500 */
1501 __STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
1502 {
1503 WRITE_REG(I2Sx->RXDMA_RST, I2S_RXDMA_RST);
1504 }
1505
1506 /**
1507 * @brief Reset TX block DMA
1508 * @note The TX DMA can be reset to the lowest channel via this register.
1509 *
1510 * \rst
1511 * +----------------------+-----------------------------------+
1512 * | Register | BitsName |
1513 * +======================+===================================+
1514 * | TXDMA_RST | RST |
1515 * +----------------------+-----------------------------------+
1516 * \endrst
1517 *
1518 * @param I2Sx I2S instance
1519 * @retval None
1520 */
1521 __STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
1522 {
1523 WRITE_REG(I2Sx->TXDMA_RST, I2S_TXDMA_RST);
1524 }
1525
1526
1527 /**
1528 * @brief Enable I2S DMA
1529 *
1530 * \rst
1531 * +----------------------+-----------------------------------+
1532 * | Register | BitsName |
1533 * +======================+===================================+
1534 * | DMA_ACC_SEL | QSPI1_I2S_M_SEL |
1535 * +----------------------+-----------------------------------+
1536 * \endrst
1537 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1538 *
1539 * @param I2Sx I2S instance
1540 * @retval None
1541 */
1542 __STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
1543 {
1544 if (I2S_M == I2Sx)
1545 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1546 else
1547 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1548 }
1549
1550 /**
1551 * @brief Disable I2S DMA
1552 *
1553 * \rst
1554 * +----------------------+-----------------------------------+
1555 * | Register | BitsName |
1556 * +======================+===================================+
1557 * | DMA_ACC_SEL | QSPI1_I2S_M_SEL |
1558 * +----------------------+-----------------------------------+
1559 * \endrst
1560 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1561 *
1562 * @param I2Sx I2S instance
1563 * @retval None
1564 */
1565 __STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
1566 {
1567 if (I2S_M == I2Sx)
1568 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1569 else
1570 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1571 }
1572
1573 /**
1574 * @brief Check if I2S DMA is enabled
1575 *
1576 * \rst
1577 * +----------------------+-----------------------------------+
1578 * | Register | BitsName |
1579 * +======================+===================================+
1580 * | DMA_ACC_SEL | QSPI1_I2S_M_SEL |
1581 * +----------------------+-----------------------------------+
1582 * \endrst
1583 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1584 *
1585 * @param I2Sx I2S instance
1586 * @retval State of bit (1 or 0).
1587 */
1588 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
1589 {
1590 if (I2S_M == I2Sx)
1591 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM) == MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1592 else
1593 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS) == MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1594 }
1595
1596
1597 /** @} */
1598
1599 /** @defgroup I2S_LL_EF_Component Component Paraments Functions
1600 * @{
1601 */
1602
1603 /**
1604 * @brief Get I2S component paramenters: rx resolution
1605 *
1606 * \rst
1607 * +----------------------+-----------------------------------+
1608 * | Register | BitsName |
1609 * +======================+===================================+
1610 * | I2S_PARAM2 | RXSIZE_3 |
1611 * +----------------------+-----------------------------------+
1612 * \endrst
1613 * I2S_PARAM2 | RXSIZE_2
1614 * I2S_PARAM2 | RXSIZE_1
1615 * I2S_PARAM2 | RXSIZE_0
1616 *
1617 * @param I2Sx I2S instance
1618 * @param channel The special channel: 0 ~ 3
1619 * @retval Returned Value can be one of the following values:
1620 * @arg @ref LL_I2S_RESOLUTION_12BIT
1621 * @arg @ref LL_I2S_RESOLUTION_16BIT
1622 * @arg @ref LL_I2S_RESOLUTION_20BIT
1623 * @arg @ref LL_I2S_RESOLUTION_24BIT
1624 * @arg @ref LL_I2S_RESOLUTION_32BIT
1625 */
1626 __STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1627 {
1628 uint32_t pos[4] = {I2S_PARAM2_RXSIZE_0_Pos, I2S_PARAM2_RXSIZE_1_Pos, \
1629 I2S_PARAM2_RXSIZE_2_Pos, I2S_PARAM2_RXSIZE_3_Pos
1630 };
1631 uint32_t mask[4] = {I2S_PARAM2_RXSIZE_0, I2S_PARAM2_RXSIZE_1, I2S_PARAM2_RXSIZE_2, I2S_PARAM2_RXSIZE_3};
1632
1633 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM2, mask[channel]) >> pos[channel]);
1634 }
1635
1636 /**
1637 * @brief Get I2S component paramenters: tx resolution
1638 *
1639 * \rst
1640 * +----------------------+-----------------------------------+
1641 * | Register | BitsName |
1642 * +======================+===================================+
1643 * | I2S_PARAM1 | TXSIZE_3 |
1644 * +----------------------+-----------------------------------+
1645 * \endrst
1646 * I2S_PARAM1 | TXSIZE_2
1647 * I2S_PARAM1 | TXSIZE_1
1648 * I2S_PARAM1 | TXSIZE_0
1649 *
1650 * @param I2Sx I2S instance
1651 * @param channel The special channel: 0 ~ 3
1652 * @retval Returned Value can be one of the following values:
1653 * @arg @ref LL_I2S_RESOLUTION_12BIT
1654 * @arg @ref LL_I2S_RESOLUTION_16BIT
1655 * @arg @ref LL_I2S_RESOLUTION_20BIT
1656 * @arg @ref LL_I2S_RESOLUTION_24BIT
1657 * @arg @ref LL_I2S_RESOLUTION_32BIT
1658 */
1659 __STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1660 {
1661 uint32_t pos[4] = {I2S_PARAM1_TXSIZE_0_Pos, I2S_PARAM1_TXSIZE_1_Pos, \
1662 I2S_PARAM1_TXSIZE_2_Pos, I2S_PARAM1_TXSIZE_3_Pos
1663 };
1664 uint32_t mask[4] = {I2S_PARAM1_TXSIZE_0, I2S_PARAM1_TXSIZE_1, I2S_PARAM1_TXSIZE_2, I2S_PARAM1_TXSIZE_3};
1665
1666 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, mask[channel]) >> pos[channel]);
1667 }
1668
1669 /**
1670 * @brief Get I2S component paramenters: the number of tx channels
1671 *
1672 * \rst
1673 * +----------------------+-----------------------------------+
1674 * | Register | BitsName |
1675 * +======================+===================================+
1676 * | I2S_PARAM1 | TXCHN |
1677 * +----------------------+-----------------------------------+
1678 * \endrst
1679 *
1680 * @param I2Sx I2S instance
1681 * @retval Returned Value can be one of the following values:
1682 * @arg @ref LL_I2S_CHANNEL_NUM_1
1683 * @arg @ref LL_I2S_CHANNEL_NUM_2
1684 * @arg @ref LL_I2S_CHANNEL_NUM_3
1685 * @arg @ref LL_I2S_CHANNEL_NUM_4
1686 */
1687 __STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
1688 {
1689 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXCHN) >> I2S_PARAM1_TXCHN_Pos);
1690 }
1691
1692 /**
1693 * @brief Get I2S component paramenters: the number of rx channels
1694 *
1695 * \rst
1696 * +----------------------+-----------------------------------+
1697 * | Register | BitsName |
1698 * +======================+===================================+
1699 * | I2S_PARAM1 | RXCHN |
1700 * +----------------------+-----------------------------------+
1701 * \endrst
1702 *
1703 * @param I2Sx I2S instance
1704 * @retval Returned Value can be one of the following values:
1705 * @arg @ref LL_I2S_CHANNEL_NUM_1
1706 * @arg @ref LL_I2S_CHANNEL_NUM_2
1707 * @arg @ref LL_I2S_CHANNEL_NUM_3
1708 * @arg @ref LL_I2S_CHANNEL_NUM_4
1709 */
1710 __STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
1711 {
1712 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXCHN) >> I2S_PARAM1_RXCHN_Pos);
1713 }
1714
1715 /**
1716 * @brief Get I2S component paramenters: whether the receiver block is enabled or not
1717 *
1718 * \rst
1719 * +----------------------+-----------------------------------+
1720 * | Register | BitsName |
1721 * +======================+===================================+
1722 * | I2S_PARAM1 | RXBLOCK |
1723 * +----------------------+-----------------------------------+
1724 * \endrst
1725 *
1726 * @param I2Sx I2S instance
1727 * @retval State of bit (1 or 0).
1728 */
1729 __STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
1730 {
1731 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXBLOCK) == I2S_PARAM1_RXBLOCK);
1732 }
1733
1734 /**
1735 * @brief Get I2S component paramenters: whether the transmitter block is enabled or not
1736 *
1737 * \rst
1738 * +----------------------+-----------------------------------+
1739 * | Register | BitsName |
1740 * +======================+===================================+
1741 * | I2S_PARAM1 | TXBLOCK |
1742 * +----------------------+-----------------------------------+
1743 * \endrst
1744 *
1745 * @param I2Sx I2S instance
1746 * @retval State of bit (1 or 0).
1747 */
1748 __STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
1749 {
1750 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXBLOCK) == I2S_PARAM1_TXBLOCK);
1751 }
1752
1753 /**
1754 * @brief Get I2S component paramenters: whether the master mode is enabled or not
1755 *
1756 * \rst
1757 * +----------------------+-----------------------------------+
1758 * | Register | BitsName |
1759 * +======================+===================================+
1760 * | I2S_PARAM1 | MODE |
1761 * +----------------------+-----------------------------------+
1762 * \endrst
1763 *
1764 * @param I2Sx I2S instance
1765 * @retval State of bit (1 or 0).
1766 */
1767 __STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
1768 {
1769 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_MODE) == I2S_PARAM1_MODE);
1770 }
1771
1772 /**
1773 * @brief Get I2S component paramenters: FIOF depth
1774 *
1775 * \rst
1776 * +----------------------+-----------------------------------+
1777 * | Register | BitsName |
1778 * +======================+===================================+
1779 * | I2S_PARAM1 | FIFO_DEPTH |
1780 * +----------------------+-----------------------------------+
1781 * \endrst
1782 *
1783 * @param I2Sx I2S instance
1784 * @retval Returned Value can be one of the following values:
1785 * @arg @ref LL_I2S_FIFO_DEPTH_2
1786 * @arg @ref LL_I2S_FIFO_DEPTH_4
1787 * @arg @ref LL_I2S_FIFO_DEPTH_8
1788 * @arg @ref LL_I2S_FIFO_DEPTH_16
1789 */
1790 __STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
1791 {
1792 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_FIFO_DEPTH) >> I2S_PARAM1_FIFO_DEPTH_Pos);
1793 }
1794
1795 /**
1796 * @brief Get I2S component paramenters: APB data width
1797 *
1798 * \rst
1799 * +----------------------+-----------------------------------+
1800 * | Register | BitsName |
1801 * +======================+===================================+
1802 * | I2S_PARAM1 | APB_DATA_WIDTH |
1803 * +----------------------+-----------------------------------+
1804 * \endrst
1805 *
1806 * @param I2Sx I2S instance
1807 * @retval Returned Value can be one of the following values:
1808 * @arg @ref LL_I2S_APB_WIDTH_8BIT
1809 * @arg @ref LL_I2S_APB_WIDTH_16BIT
1810 * @arg @ref LL_I2S_APB_WIDTH_32BIT
1811 */
1812 __STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
1813 {
1814 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_APB_DATA_WIDTH) >> I2S_PARAM1_APB_DATA_WIDTH_Pos);
1815 }
1816
1817 /**
1818 * @brief Get I2S component version
1819 *
1820 * \rst
1821 * +----------------------+-----------------------------------+
1822 * | Register | BitsName |
1823 * +======================+===================================+
1824 * | I2S_VERSION | VERSION |
1825 * +----------------------+-----------------------------------+
1826 * \endrst
1827 *
1828 * @param I2Sx I2S instance
1829 * @retval Returned Value is const.
1830 */
1831 __STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
1832 {
1833 return (uint32_t)(READ_REG(I2Sx->I2S_VERSION));
1834 }
1835
1836 /**
1837 * @brief Get I2S component type
1838 *
1839 * \rst
1840 * +----------------------+-----------------------------------+
1841 * | Register | BitsName |
1842 * +======================+===================================+
1843 * | I2S_TYPE | TYPE |
1844 * +----------------------+-----------------------------------+
1845 * \endrst
1846 *
1847 * @param I2Sx I2S instance
1848 * @retval Returned Value is const.
1849 */
1850 __STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
1851 {
1852 return (uint32_t)(READ_REG(I2Sx->I2S_TYPE));
1853 }
1854
1855 /** @} */
1856
1857 /** @defgroup I2S_LL_EF_Init I2S_M Initialization and de-initialization functions
1858 * @{
1859 */
1860
1861 /**
1862 * @brief De-initialize I2S registers (Registers restored to their default values).
1863 * @param I2Sx I2S instance
1864 * @retval An error_status_t enumeration value:
1865 * - SUCCESS: I2S registers are de-initialized
1866 * - ERROR: I2S registers are not de-initialized
1867 */
1868 error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx);
1869
1870 /**
1871 * @brief Initialize I2S_M registers according to the specified
1872 * parameters in p_i2s_init.
1873 * @param I2Sx I2S instance
1874 * @param p_i2s_init Pointer to a ll_i2s_init_t structure that contains the configuration
1875 * information for the specified I2S_M peripheral.
1876 * @retval An error_status_t enumeration value:
1877 * - SUCCESS: I2S registers are initialized according to p_i2s_init content
1878 * - ERROR: Problem occurred during I2S Registers initialization
1879 */
1880 error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init);
1881
1882 /**
1883 * @brief Set each field of a @ref ll_i2s_init_t type structure to default value.
1884 * @param p_i2s_init Pointer to a @ref ll_i2s_init_t structure
1885 * whose fields will be set to default values.
1886 * @retval None
1887 */
1888 void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init);
1889
1890 /** @} */
1891
1892 /** @} */
1893
1894 #endif /* I2S_M || I2S_S */
1895
1896 #ifdef __cplusplus
1897 }
1898 #endif
1899
1900 #endif /* __GR55xx_LL_I2S_H__ */
1901
1902 /** @} */
1903
1904 /** @} */
1905
1906 /** @} */
ll_i2s_enable_clock
__STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
Enable I2S clock.
Definition: gr55xx_ll_i2s.h:490
ll_i2s_receive_rdata
__STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from right RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:839
ll_i2s_enable
__STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
Enable I2S.
Definition: gr55xx_ll_i2s.h:319
ll_i2s_get_wss
__STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
Get word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:574
ll_i2s_get_rx_block
__STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the receiver block is enabled or not.
Definition: gr55xx_ll_i2s.h:1729
ll_i2s_is_enabled_clock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
Check if I2S clock is enabled.
Definition: gr55xx_ll_i2s.h:528
ll_i2s_disable_txblock
__STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
Disable I2S TX block.
Definition: gr55xx_ll_i2s.h:452
ll_i2s_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1399
ll_i2s_get_rx_channels
__STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of rx channels.
Definition: gr55xx_ll_i2s.h:1710
ll_i2s_struct_init
void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init)
Set each field of a ll_i2s_init_t type structure to default value.
ll_i2s_clr_rxfifo_all
__STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
Clear I2S RX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:642
ll_i2s_clr_txfifo_all
__STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
Clear I2S TX FIFO in all channels.
Definition: gr55xx_ll_i2s.h:661
ll_i2s_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1362
ll_i2s_clear_it_txovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1289
ll_i2s_transmit_ldata
__STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to left TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:860
ll_i2s_set_rxsize
__STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set receive data width in a channel.
Definition: gr55xx_ll_i2s.h:1029
ll_i2s_disable_tx
__STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Disable TX in a channel.
Definition: gr55xx_ll_i2s.h:981
ll_i2s_disable_dma
__STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
Disable I2S DMA.
Definition: gr55xx_ll_i2s.h:1565
_ll_i2s_init_t::tx_threshold
uint32_t tx_threshold
Specifies the I2S transmit FIFO threshold.
Definition: gr55xx_ll_i2s.h:93
ll_i2s_set_wss
__STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
Set word select line cycles for left or right sample.
Definition: gr55xx_ll_i2s.h:552
ll_i2s_set_txsize
__STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
Set transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:1083
_ll_i2s_init_t::clock_source
uint32_t clock_source
Specifies the source of the I2S clock.
Definition: gr55xx_ll_i2s.h:98
ll_i2s_enable_dma
__STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
Enable I2S DMA.
Definition: gr55xx_ll_i2s.h:1542
ll_i2s_get_tx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: tx resolution.
Definition: gr55xx_ll_i2s.h:1659
ll_i2s_rst_rxdma
__STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
Reset RX block DMA.
Definition: gr55xx_ll_i2s.h:1501
ll_i2s_clear_it_rxovr
__STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data overrun interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1269
_ll_i2s_init_t::rx_threshold
uint32_t rx_threshold
Specifies the I2S receive FIFO threshold.
Definition: gr55xx_ll_i2s.h:88
ll_i2s_set_clock_src
__STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
Set I2S clock source.
Definition: gr55xx_ll_i2s.h:773
ll_i2s_is_enabled_rx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
Check if RX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:941
ll_i2s_disable_it
__STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Disable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1221
_ll_i2s_init_t::rxdata_size
uint32_t rxdata_size
Specifies the I2S receive data size.
Definition: gr55xx_ll_i2s.h:78
_ll_i2s_init_t::txdata_size
uint32_t txdata_size
Specifies the I2S transmit data size.
Definition: gr55xx_ll_i2s.h:83
ll_i2s_is_enabled_clock_div
__STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
Check if I2S clock divider is enabled.
Definition: gr55xx_ll_i2s.h:752
ll_i2s_enable_rxblock
__STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
Enable I2S RX block.
Definition: gr55xx_ll_i2s.h:376
ll_i2s_get_rxsize
__STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
Get receive data width in a channel.
Definition: gr55xx_ll_i2s.h:1055
ll_i2s_enable_txblock
__STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
Enable I2S TX block.
Definition: gr55xx_ll_i2s.h:433
_ll_i2s_init_t::audio_freq
uint32_t audio_freq
Specifies the frequency selected for the I2S communication.
Definition: gr55xx_ll_i2s.h:103
ll_i2s_get_clock_src
__STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
Get I2S clock source.
Definition: gr55xx_ll_i2s.h:793
ll_i2s_get_sclkg
__STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
Get the gating of sclk.
Definition: gr55xx_ll_i2s.h:623
ll_i2s_get_apb_width
__STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
Get I2S component paramenters: APB data width.
Definition: gr55xx_ll_i2s.h:1812
ll_i2s_get_master_mode
__STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the master mode is enabled or not.
Definition: gr55xx_ll_i2s.h:1767
ll_i2s_init
error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init)
Initialize I2S_M registers according to the specified parameters in p_i2s_init.
ll_i2s_transmit_rdata
__STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
Write one data to right TX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:881
ll_i2s_disable_rxblock
__STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
Disable I2S RX block.
Definition: gr55xx_ll_i2s.h:395
ll_i2s_is_enabled
__STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
Check if I2S is enabled.
Definition: gr55xx_ll_i2s.h:357
ll_i2s_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
Get threshold of TXFIFO in a channel that triggers an TXFE event.
Definition: gr55xx_ll_i2s.h:1435
ll_i2s_enable_it
__STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Enable interrupt in a channel.
Definition: gr55xx_ll_i2s.h:1193
ll_i2s_get_tx_channels
__STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
Get I2S component paramenters: the number of tx channels.
Definition: gr55xx_ll_i2s.h:1687
ll_i2s_rst_txdma
__STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
Reset TX block DMA.
Definition: gr55xx_ll_i2s.h:1521
ll_i2s_is_enabled_rxblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
Check if I2S RX block is enabled.
Definition: gr55xx_ll_i2s.h:414
ll_i2s_enable_clock_div
__STATIC_INLINE void ll_i2s_enable_clock_div(void)
Enable I2S clock divider.
Definition: gr55xx_ll_i2s.h:716
ll_i2s_set_sclkg
__STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
Set the gating of sclk.
Definition: gr55xx_ll_i2s.h:599
ll_i2s_get_type
__STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
Get I2S component type.
Definition: gr55xx_ll_i2s.h:1850
ll_i2s_get_it_flag
__STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
Get interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1136
ll_i2s_get_version
__STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
Get I2S component version.
Definition: gr55xx_ll_i2s.h:1831
ll_i2s_is_active_it_flag
__STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
Check interrupt flag in a channel.
Definition: gr55xx_ll_i2s.h:1165
ll_i2s_init_t
struct _ll_i2s_init_t ll_i2s_init_t
LL I2S init structures definition.
ll_i2s_is_enabled_txblock
__STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
Check if I2S TX block is enabled.
Definition: gr55xx_ll_i2s.h:471
ll_i2s_disable_rx
__STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Disable RX in a channel.
Definition: gr55xx_ll_i2s.h:921
ll_i2s_enable_tx
__STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
Enable TX in a channel.
Definition: gr55xx_ll_i2s.h:961
ll_i2s_is_enabled_dma
__STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
Check if I2S DMA is enabled.
Definition: gr55xx_ll_i2s.h:1588
ll_i2s_get_rx_resolution
__STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
Get I2S component paramenters: rx resolution.
Definition: gr55xx_ll_i2s.h:1626
ll_i2s_get_fifo_depth
__STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
Get I2S component paramenters: FIOF depth.
Definition: gr55xx_ll_i2s.h:1790
ll_i2s_set_clock_div
__STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
Set I2S clock divider.
Definition: gr55xx_ll_i2s.h:680
ll_i2s_clr_txfifo_channel
__STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear TX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1475
ll_i2s_receive_ldata
__STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
Read one data from left RX FIFO in a channel.
Definition: gr55xx_ll_i2s.h:819
ll_i2s_disable_clock
__STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
Disable I2S clock.
Definition: gr55xx_ll_i2s.h:509
ll_i2s_is_enabled_it
__STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
Check if interrupt in a channel is enabled.
Definition: gr55xx_ll_i2s.h:1249
ll_i2s_enable_rx
__STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
Enable RX in a channel.
Definition: gr55xx_ll_i2s.h:901
ll_i2s_is_enabled_tx
__STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
Check if TX in a channel is enabled.
Definition: gr55xx_ll_i2s.h:1001
ll_i2s_get_tx_block
__STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
Get I2S component paramenters: whether the transmitter block is enabled or not.
Definition: gr55xx_ll_i2s.h:1748
ll_i2s_get_clock_div
__STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
Get I2S clock divider.
Definition: gr55xx_ll_i2s.h:698
ll_i2s_get_txsize
__STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
Get transmit data width in a channel.
Definition: gr55xx_ll_i2s.h:1109
ll_i2s_clr_rxfifo_channel
__STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
Clear RX FIFO data in a channel.
Definition: gr55xx_ll_i2s.h:1455
_ll_i2s_init_t
LL I2S init structures definition.
Definition: gr55xx_ll_i2s.h:77
ll_i2s_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
Set threshold of RXFIFO in a channel that triggers an RXDA event.
Definition: gr55xx_ll_i2s.h:1326
ll_i2s_deinit
error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx)
De-initialize I2S registers (Registers restored to their default values).
ll_i2s_disable_clock_div
__STATIC_INLINE void ll_i2s_disable_clock_div(void)
Disable I2S clock divider.
Definition: gr55xx_ll_i2s.h:734
ll_i2s_disable
__STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
Disable I2S.
Definition: gr55xx_ll_i2s.h:338