gr55xx_ll_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (DMA)
63
64 /** @defgroup DMA_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init
77 {
78 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
79
80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
81
82 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory or form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t mode; /**< Specifies the Single block or Multi-block operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref ll_dma_set_mode(). */
98
99 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
100 This parameter can be a value of @ref DMA_LL_EC_SOURCE
101
102 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_increment_mode(). */
103
104 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
105 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
106
107 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_increment_mode(). */
108
109 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
110 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
111
112 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_width(). */
113
114 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
115 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_width(). */
118
119 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
120 The data unit is equal to the source buffer configuration set in src_data_width parameters.
121 This parameter must be a value between Min_Data = 0 and Max_Data = 0x1FF
122
123 This feature can be modified afterwards using unitary function @ref ll_dma_set_block_size(). */
124
125 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
126 This parameter can be a value of @ref DMA_LL_EC_PERIPH
127
128 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_peripheral(). */
129
130 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
131 This parameter can be a value of @ref DMA_LL_EC_PERIPH
132
133 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_peripheral(). */
134
135 uint32_t priority; /**< Specifies the channel priority level.
136 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref ll_dma_set_channel_priority_level(). */
139
140 } ll_dma_init_t;
141
142 /** @} */
143
144 /** @} */
145
146 /**
147 * @defgroup DMA_LL_MACRO Defines
148 * @{
149 */
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
153 * @{
154 */
155
156 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
157 * @{
158 */
159 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
160 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
161 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
162 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
163 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
164 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /**< DMA Channel 5 */
165 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /**< DMA Channel 6 */
166 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /**< DMA Channel 7 */
167 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all (used only for function @ref ll_dma_deinit(). */
168 /** @} */
169
170 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
171 * @{
172 */
173 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
174 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
175 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
176 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
177 /** @} */
178
179
180 /** @defgroup DMA_LL_EC_MODE Transfer mode
181 * @{
182 */
183 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U) /**< Single block */
184 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC /**< Multi-block: src address reload, dst address contiguous */
185 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST /**< Multi-block: src address contiguous, dst address reload */
186 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST) /**< Multi-block: src address reload, dst address reload */
187 /** @} */
188
189 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
190 * @{
191 */
192 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
193 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
194 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
195 /** @} */
196
197 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
198 * @{
199 */
200 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
201 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
202 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
203 /** @} */
204
205 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
206 * @{
207 */
208 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
209 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
210 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
211 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
212 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
213 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
214 /** @} */
215
216 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
217 * @{
218 */
219 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
220 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
221 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
222 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
223 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
224 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
225 /** @} */
226
227 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
228 * @{
229 */
230 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
231 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
232 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
233 /** @} */
234
235 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
236 * @{
237 */
238 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
239 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
240 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
241 /** @} */
242
243 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
244 * @{
245 */
246 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
247 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
248 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
249 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
250 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
251 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
252 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
253 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
254 /** @} */
255
256 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
257 * @{
258 */
259 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
260 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
261 /** @} */
262
263 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
264 * @{
265 */
266 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
267 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
268 /** @} */
269
270 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
271 * @{
272 */
273 #define LL_DMA_PERIPH_SPIM_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is SPIM TX */
274 #define LL_DMA_PERIPH_SPIM_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is SPIM RX */
275 #define LL_DMA_PERIPH_SPIS_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIS TX */
276 #define LL_DMA_PERIPH_SPIS_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIS RX */
277 #define LL_DMA_PERIPH_QSPI0_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is QSPI0 TX */
278 #define LL_DMA_PERIPH_QSPI0_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is QSPI0 RX */
279 #define LL_DMA_PERIPH_I2C0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is I2C0 TX */
280 #define LL_DMA_PERIPH_I2C0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is I2C0 RX */
281 #define LL_DMA_PERIPH_I2C1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2C1 TX */
282 #define LL_DMA_PERIPH_I2C1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2C1 RX */
283 #define LL_DMA_PERIPH_I2S_S_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2S_S TX */
284 #define LL_DMA_PERIPH_I2S_S_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2S_S RX */
285 #define LL_DMA_PERIPH_UART0_TX ((uint32_t)0x0000000AU) /**< DMA Peripheral type is UART0 TX */
286 #define LL_DMA_PERIPH_UART0_RX ((uint32_t)0x0000000BU) /**< DMA Peripheral type is UART0 RX */
287 #define LL_DMA_PERIPH_QSPI1_TX ((uint32_t)0x0000000CU) /**< DMA peripheral type is QSPI1 TX */
288 #define LL_DMA_PERIPH_QSPI1_RX ((uint32_t)0x0000000DU) /**< DMA peripheral type is QSPI1 RX */
289 #define LL_DMA_PERIPH_I2S_M_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is I2S_M TX */
290 #define LL_DMA_PERIPH_I2S_M_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is I2S_M RX */
291 #define LL_DMA_PERIPH_SNSADC ((uint32_t)0x0000000EU) /**< DMA peripheral type is SNSADC */
292 #define LL_DMA_PERIPH_MEM ((uint32_t)0x0000000FU) /**< DMA peripheral type is Memory */
293 /** @} */
294
295 /** @} */
296
297 /* Exported macro ------------------------------------------------------------*/
298 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
299 * @{
300 */
301
302 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
303 * @{
304 */
305
306 /**
307 * @brief Write a value in DMA register
308 * @param __instance__ DMA instance
309 * @param __REG__ Register to be written
310 * @param __VALUE__ Value to be written in the register
311 * @retval None
312 */
313 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
314
315 /**
316 * @brief Read a value in DMA register
317 * @param __instance__ DMA instance
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
322
323 /** @} */
324
325 /** @} */
326
327 /** @} */
328
329 /* Exported functions --------------------------------------------------------*/
330 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
331 * @{
332 */
333
334 /** @defgroup DMA_LL_EF_Configuration Configuration functions
335 * @{
336 */
337
338 /**
339 * @brief Enable DMA Module.
340 * @note This function is used to enable the DMA Module, which must be done before any
341 * channel activity can begin.
342 *
343 * \rst
344 * +----------------------+-----------------------------------+
345 * | Register | BitsName |
346 * +======================+===================================+
347 * | CFG_REG | CFG_EN |
348 * +----------------------+-----------------------------------+
349 * \endrst
350 *
351 * @param DMAx DMA instance.
352 * @retval None
353 */
354 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
355 {
356 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
357 }
358
359 /**
360 * @brief Disable DMA Module.
361 * @note If the ll_dma_disable() function is called while any dma channel is still active,
362 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
363 * still active until hardware has terminated all cativity on all channels, at which
364 * point the ll_dma_is_enable() function returns 0.
365 *
366 * \rst
367 * +----------------------+-----------------------------------+
368 * | Register | BitsName |
369 * +======================+===================================+
370 * | CFG_REG | CFG_EN |
371 * +----------------------+-----------------------------------+
372 * \endrst
373 *
374 * @param DMAx DMA instance.
375 * @retval None
376 */
377 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
378 {
379 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
380 }
381
382 /**
383 * @brief Check if DMA Module is enabled or disabled.
384 *
385 * \rst
386 * +----------------------+-----------------------------------+
387 * | Register | BitsName |
388 * +======================+===================================+
389 * | CFG_REG | CFG_EN |
390 * +----------------------+-----------------------------------+
391 * \endrst
392 *
393 * @param DMAx DMA instance.
394 * @retval State of bit (1 or 0).
395 */
396 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
397 {
398 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
399 }
400
401 /**
402 * @brief Enable DMA channel.
403 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
404 * is ignored and call ll_dma_disable_channel() function will always returns 0.
405 *
406 * \rst
407 * +----------------------+-----------------------------------+
408 * | Register | BitsName |
409 * +======================+===================================+
410 * | CH_EN_REG | CH_EN_WE&CH_EN |
411 * +----------------------+-----------------------------------+
412 * \endrst
413 *
414 * @param DMAx DMA instance.
415 * @param channel This parameter can be one of the following values:
416 * @arg @ref LL_DMA_CHANNEL_0
417 * @arg @ref LL_DMA_CHANNEL_1
418 * @arg @ref LL_DMA_CHANNEL_2
419 * @arg @ref LL_DMA_CHANNEL_3
420 * @arg @ref LL_DMA_CHANNEL_4
421 * @arg @ref LL_DMA_CHANNEL_5
422 * @arg @ref LL_DMA_CHANNEL_6
423 * @arg @ref LL_DMA_CHANNEL_7
424 * @retval None
425 */
426 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
427 {
428 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
429 }
430
431 /**
432 * @brief Disable DMA channel.
433 *
434 * \rst
435 * +----------------------+-----------------------------------+
436 * | Register | BitsName |
437 * +======================+===================================+
438 * | CH_EN_REG | CH_EN_WE&CH_EN |
439 * +----------------------+-----------------------------------+
440 * \endrst
441 *
442 * @param DMAx DMA instance.
443 * @param channel This parameter can be one of the following values:
444 * @arg @ref LL_DMA_CHANNEL_0
445 * @arg @ref LL_DMA_CHANNEL_1
446 * @arg @ref LL_DMA_CHANNEL_2
447 * @arg @ref LL_DMA_CHANNEL_3
448 * @arg @ref LL_DMA_CHANNEL_4
449 * @arg @ref LL_DMA_CHANNEL_5
450 * @arg @ref LL_DMA_CHANNEL_6
451 * @arg @ref LL_DMA_CHANNEL_7
452 * @retval None
453 */
454 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
455 {
456 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
457 }
458
459 /**
460 * @brief Check if DMA channel is enabled or disabled.
461 * @note Software can therefore poll this function to determine when channel is free
462 * for a new DMA transfer.
463 *
464 * \rst
465 * +----------------------+-----------------------------------+
466 * | Register | BitsName |
467 * +======================+===================================+
468 * | CH_EN_REG | CH_EN_WE&CH_EN |
469 * +----------------------+-----------------------------------+
470 * \endrst
471 *
472 * @param DMAx DMA instance.
473 * @param channel This parameter can be one of the following values:
474 * @arg @ref LL_DMA_CHANNEL_0
475 * @arg @ref LL_DMA_CHANNEL_1
476 * @arg @ref LL_DMA_CHANNEL_2
477 * @arg @ref LL_DMA_CHANNEL_3
478 * @arg @ref LL_DMA_CHANNEL_4
479 * @arg @ref LL_DMA_CHANNEL_5
480 * @arg @ref LL_DMA_CHANNEL_6
481 * @arg @ref LL_DMA_CHANNEL_7
482 * @retval State of bit (1 or 0).
483 */
484 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
485 {
486 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
487 }
488
489 /**
490 * @brief Suspend a DMA channel transfer.
491 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
492 * function is called. The function may be called after enabling the DMA channel.
493 *
494 * \rst
495 * +----------------------+-----------------------------------+
496 * | Register | BitsName |
497 * +======================+===================================+
498 * | CFGL | CH_SUSP |
499 * +----------------------+-----------------------------------+
500 * \endrst
501 *
502 * @param DMAx DMA instance.
503 * @param channel This parameter can be one of the following values:
504 * @arg @ref LL_DMA_CHANNEL_0
505 * @arg @ref LL_DMA_CHANNEL_1
506 * @arg @ref LL_DMA_CHANNEL_2
507 * @arg @ref LL_DMA_CHANNEL_3
508 * @arg @ref LL_DMA_CHANNEL_4
509 * @arg @ref LL_DMA_CHANNEL_5
510 * @arg @ref LL_DMA_CHANNEL_6
511 * @arg @ref LL_DMA_CHANNEL_7
512 * @retval None
513 */
514 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
515 {
516 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
517 }
518
519 /**
520 * @brief Resume a DMA channel.
521 * @note The function may be called after enabling the DMA channel.
522 *
523 * \rst
524 * +----------------------+-----------------------------------+
525 * | Register | BitsName |
526 * +======================+===================================+
527 * | CFGL | CH_SUSP |
528 * +----------------------+-----------------------------------+
529 * \endrst
530 *
531 * @param DMAx DMA instance.
532 * @param channel This parameter can be one of the following values:
533 * @arg @ref LL_DMA_CHANNEL_0
534 * @arg @ref LL_DMA_CHANNEL_1
535 * @arg @ref LL_DMA_CHANNEL_2
536 * @arg @ref LL_DMA_CHANNEL_3
537 * @arg @ref LL_DMA_CHANNEL_4
538 * @arg @ref LL_DMA_CHANNEL_5
539 * @arg @ref LL_DMA_CHANNEL_6
540 * @arg @ref LL_DMA_CHANNEL_7
541 * @retval None
542 */
543 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
544 {
545 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
546 }
547
548 /**
549 * @brief Check if DMA channel is suspended or resumed.
550 *
551 * \rst
552 * +----------------------+-----------------------------------+
553 * | Register | BitsName |
554 * +======================+===================================+
555 * | CFGL | CH_SUSP |
556 * +----------------------+-----------------------------------+
557 * \endrst
558 *
559 * @param DMAx DMA instance.
560 * @param channel This parameter can be one of the following values:
561 * @arg @ref LL_DMA_CHANNEL_0
562 * @arg @ref LL_DMA_CHANNEL_1
563 * @arg @ref LL_DMA_CHANNEL_2
564 * @arg @ref LL_DMA_CHANNEL_3
565 * @arg @ref LL_DMA_CHANNEL_4
566 * @arg @ref LL_DMA_CHANNEL_5
567 * @arg @ref LL_DMA_CHANNEL_6
568 * @arg @ref LL_DMA_CHANNEL_7
569 * @retval State of bit (1 or 0).
570 */
571 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
572 {
573 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
574 }
575
576 /**
577 * @brief Check if DMA channel FIFO is empty.
578 *
579 * \rst
580 * +----------------------+-----------------------------------+
581 * | Register | BitsName |
582 * +======================+===================================+
583 * | CFGL | FIFO_EMPTY |
584 * +----------------------+-----------------------------------+
585 * \endrst
586 *
587 * @param DMAx DMA instance.
588 * @param channel This parameter can be one of the following values:
589 * @arg @ref LL_DMA_CHANNEL_0
590 * @arg @ref LL_DMA_CHANNEL_1
591 * @arg @ref LL_DMA_CHANNEL_2
592 * @arg @ref LL_DMA_CHANNEL_3
593 * @arg @ref LL_DMA_CHANNEL_4
594 * @arg @ref LL_DMA_CHANNEL_5
595 * @arg @ref LL_DMA_CHANNEL_6
596 * @arg @ref LL_DMA_CHANNEL_7
597 * @retval State of bit (1 or 0).
598 */
599 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
600 {
601 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
602 }
603
604 /**
605 * @brief Configure all parameters link to DMA transfer.
606 *
607 * \rst
608 * +----------------------+-----------------------------------+
609 * | Register | BitsName |
610 * +======================+===================================+
611 * | CCR | DIR |
612 * +----------------------+-----------------------------------+
613 * \endrst
614 * CCR | MEM2MEM
615 * CCR | CIRC
616 * CCR | PINC
617 * CCR | MINC
618 * CCR | PSIZE
619 * CCR | MSIZE
620 * CCR | PL
621 *
622 * @param DMAx DMAx instance
623 * @param channel This parameter can be one of the following values:
624 * @arg @ref LL_DMA_CHANNEL_0
625 * @arg @ref LL_DMA_CHANNEL_1
626 * @arg @ref LL_DMA_CHANNEL_2
627 * @arg @ref LL_DMA_CHANNEL_3
628 * @arg @ref LL_DMA_CHANNEL_4
629 * @arg @ref LL_DMA_CHANNEL_5
630 * @arg @ref LL_DMA_CHANNEL_6
631 * @arg @ref LL_DMA_CHANNEL_7
632 * @param configuration This parameter must be a combination of all the following values:
633 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK or @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
634 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
635 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
636 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
637 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
638 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
639 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
640 * @retval None
641 */
642 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
643 {
644 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
645 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC,
646 configuration);
647 }
648
649 /**
650 * @brief Set Data transfer direction (read from peripheral or from memory).
651 *
652 * \rst
653 * +----------------------+-----------------------------------+
654 * | Register | BitsName |
655 * +======================+===================================+
656 * | CTL_LO | TT_FC |
657 * +----------------------+-----------------------------------+
658 * \endrst
659 *
660 * @param DMAx DMAx instance
661 * @param channel This parameter can be one of the following values:
662 * @arg @ref LL_DMA_CHANNEL_0
663 * @arg @ref LL_DMA_CHANNEL_1
664 * @arg @ref LL_DMA_CHANNEL_2
665 * @arg @ref LL_DMA_CHANNEL_3
666 * @arg @ref LL_DMA_CHANNEL_4
667 * @arg @ref LL_DMA_CHANNEL_5
668 * @arg @ref LL_DMA_CHANNEL_6
669 * @arg @ref LL_DMA_CHANNEL_7
670 * @param direction This parameter can be one of the following values:
671 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
672 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
673 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
674 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
675 * @retval None
676 */
677 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
678 {
679 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
680 }
681
682 /**
683 * @brief Get Data transfer direction (read from peripheral or from memory).
684 *
685 * \rst
686 * +----------------------+-----------------------------------+
687 * | Register | BitsName |
688 * +======================+===================================+
689 * | CTL_LO | TT_FC |
690 * +----------------------+-----------------------------------+
691 * \endrst
692 *
693 * @param DMAx DMAx instance
694 * @param channel This parameter can be one of the following values:
695 * @arg @ref LL_DMA_CHANNEL_0
696 * @arg @ref LL_DMA_CHANNEL_1
697 * @arg @ref LL_DMA_CHANNEL_2
698 * @arg @ref LL_DMA_CHANNEL_3
699 * @arg @ref LL_DMA_CHANNEL_4
700 * @arg @ref LL_DMA_CHANNEL_5
701 * @arg @ref LL_DMA_CHANNEL_6
702 * @arg @ref LL_DMA_CHANNEL_7
703 * @retval Returned value can be one of the following values:
704 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
705 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
706 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
707 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
708 */
709 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
710 {
711 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
712 }
713
714 /**
715 * @brief Set DMA mode Single block or Multi block.
716 * @note The circular buffer mode cannot be used if the memory-to-memory
717 * data transfer is configured on the selected Channel.
718 *
719 * \rst
720 * +----------------------+-----------------------------------+
721 * | Register | BitsName |
722 * +======================+===================================+
723 * | CFG_LO | RELOAD_DST |
724 * +----------------------+-----------------------------------+
725 * \endrst
726 *
727 * @param DMAx DMAx instance
728 * @param channel This parameter can be one of the following values:
729 * @arg @ref LL_DMA_CHANNEL_0
730 * @arg @ref LL_DMA_CHANNEL_1
731 * @arg @ref LL_DMA_CHANNEL_2
732 * @arg @ref LL_DMA_CHANNEL_3
733 * @arg @ref LL_DMA_CHANNEL_4
734 * @arg @ref LL_DMA_CHANNEL_5
735 * @arg @ref LL_DMA_CHANNEL_6
736 * @arg @ref LL_DMA_CHANNEL_7
737 * @param mode This parameter can be one of the following values:
738 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
739 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
740 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
741 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
742 * @retval None
743 */
744 __STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
745 {
746 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
747 }
748
749
750 /**
751 * @brief Get DMA mode circular or normal.
752 *
753 * \rst
754 * +----------------------+-----------------------------------+
755 * | Register | BitsName |
756 * +======================+===================================+
757 * | CFG_LO | RELOAD_DST |
758 * +----------------------+-----------------------------------+
759 * \endrst
760 *
761 * @param DMAx DMAx instance
762 * @param channel This parameter can be one of the following values:
763 * @arg @ref LL_DMA_CHANNEL_0
764 * @arg @ref LL_DMA_CHANNEL_1
765 * @arg @ref LL_DMA_CHANNEL_2
766 * @arg @ref LL_DMA_CHANNEL_3
767 * @arg @ref LL_DMA_CHANNEL_4
768 * @arg @ref LL_DMA_CHANNEL_5
769 * @arg @ref LL_DMA_CHANNEL_6
770 * @arg @ref LL_DMA_CHANNEL_7
771 * @retval Returned value can be one of the following values:
772 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
773 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
774 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
775 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
776 */
777 __STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
778 {
779 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
780 }
781
782 /**
783 * @brief Set Source increment mode.
784 *
785 * \rst
786 * +----------------------+-----------------------------------+
787 * | Register | BitsName |
788 * +======================+===================================+
789 * | CTL_LO | SINC |
790 * +----------------------+-----------------------------------+
791 * \endrst
792 *
793 * @param DMAx DMAx instance
794 * @param channel This parameter can be one of the following values:
795 * @arg @ref LL_DMA_CHANNEL_0
796 * @arg @ref LL_DMA_CHANNEL_1
797 * @arg @ref LL_DMA_CHANNEL_2
798 * @arg @ref LL_DMA_CHANNEL_3
799 * @arg @ref LL_DMA_CHANNEL_4
800 * @arg @ref LL_DMA_CHANNEL_5
801 * @arg @ref LL_DMA_CHANNEL_6
802 * @arg @ref LL_DMA_CHANNEL_7
803 * @param src_increment_mode This parameter can be one of the following values:
804 * @arg @ref LL_DMA_SRC_INCREMENT
805 * @arg @ref LL_DMA_SRC_DECREMENT
806 * @arg @ref LL_DMA_SRC_NO_CHANGE
807 * @retval None
808 */
809 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
810 {
811 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
812 }
813
814 /**
815 * @brief Get Source increment mode.
816 *
817 * \rst
818 * +----------------------+-----------------------------------+
819 * | Register | BitsName |
820 * +======================+===================================+
821 * | CTL_LO | SINC |
822 * +----------------------+-----------------------------------+
823 * \endrst
824 *
825 * @param DMAx DMAx instance
826 * @param channel This parameter can be one of the following values:
827 * @arg @ref LL_DMA_CHANNEL_0
828 * @arg @ref LL_DMA_CHANNEL_1
829 * @arg @ref LL_DMA_CHANNEL_2
830 * @arg @ref LL_DMA_CHANNEL_3
831 * @arg @ref LL_DMA_CHANNEL_4
832 * @arg @ref LL_DMA_CHANNEL_5
833 * @arg @ref LL_DMA_CHANNEL_6
834 * @arg @ref LL_DMA_CHANNEL_7
835 * @retval Returned value can be one of the following values:
836 * @arg @ref LL_DMA_SRC_INCREMENT
837 * @arg @ref LL_DMA_SRC_DECREMENT
838 * @arg @ref LL_DMA_SRC_NO_CHANGE
839 */
840 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
841 {
842 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
843 }
844
845 /**
846 * @brief Set Destination increment mode.
847 *
848 * \rst
849 * +----------------------+-----------------------------------+
850 * | Register | BitsName |
851 * +======================+===================================+
852 * | CTL_LO | DINC |
853 * +----------------------+-----------------------------------+
854 * \endrst
855 *
856 * @param DMAx DMAx instance
857 * @param channel This parameter can be one of the following values:
858 * @arg @ref LL_DMA_CHANNEL_0
859 * @arg @ref LL_DMA_CHANNEL_1
860 * @arg @ref LL_DMA_CHANNEL_2
861 * @arg @ref LL_DMA_CHANNEL_3
862 * @arg @ref LL_DMA_CHANNEL_4
863 * @arg @ref LL_DMA_CHANNEL_5
864 * @arg @ref LL_DMA_CHANNEL_6
865 * @arg @ref LL_DMA_CHANNEL_7
866 * @param dst_increment_mode This parameter can be one of the following values:
867 * @arg @ref LL_DMA_DST_INCREMENT
868 * @arg @ref LL_DMA_DST_DECREMENT
869 * @arg @ref LL_DMA_DST_NO_CHANGE
870 * @retval None
871 */
872 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
873 {
874 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
875 }
876
877 /**
878 * @brief Get Destination increment mode.
879 *
880 * \rst
881 * +----------------------+-----------------------------------+
882 * | Register | BitsName |
883 * +======================+===================================+
884 * | CTL_LO | DINC |
885 * +----------------------+-----------------------------------+
886 * \endrst
887 *
888 * @param DMAx DMAx instance
889 * @param channel This parameter can be one of the following values:
890 * @arg @ref LL_DMA_CHANNEL_0
891 * @arg @ref LL_DMA_CHANNEL_1
892 * @arg @ref LL_DMA_CHANNEL_2
893 * @arg @ref LL_DMA_CHANNEL_3
894 * @arg @ref LL_DMA_CHANNEL_4
895 * @arg @ref LL_DMA_CHANNEL_5
896 * @arg @ref LL_DMA_CHANNEL_6
897 * @arg @ref LL_DMA_CHANNEL_7
898 * @retval Returned value can be one of the following values:
899 * @arg @ref LL_DMA_DST_INCREMENT
900 * @arg @ref LL_DMA_DST_DECREMENT
901 * @arg @ref LL_DMA_DST_NO_CHANGE
902 */
903 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
904 {
905 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
906 }
907
908 /**
909 * @brief Set Source transfer width.
910 *
911 * \rst
912 * +----------------------+-----------------------------------+
913 * | Register | BitsName |
914 * +======================+===================================+
915 * | CTL_LO | SRC_TR_WIDTH |
916 * +----------------------+-----------------------------------+
917 * \endrst
918 *
919 * @param DMAx DMAx instance
920 * @param channel This parameter can be one of the following values:
921 * @arg @ref LL_DMA_CHANNEL_0
922 * @arg @ref LL_DMA_CHANNEL_1
923 * @arg @ref LL_DMA_CHANNEL_2
924 * @arg @ref LL_DMA_CHANNEL_3
925 * @arg @ref LL_DMA_CHANNEL_4
926 * @arg @ref LL_DMA_CHANNEL_5
927 * @arg @ref LL_DMA_CHANNEL_6
928 * @arg @ref LL_DMA_CHANNEL_7
929 * @param src_width This parameter can be one of the following values:
930 * @arg @ref LL_DMA_SDATAALIGN_BYTE
931 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
932 * @arg @ref LL_DMA_SDATAALIGN_WORD
933 * @retval None
934 */
935 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
936 {
937 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
938 }
939
940 /**
941 * @brief Get Source transfer width.
942 *
943 * \rst
944 * +----------------------+-----------------------------------+
945 * | Register | BitsName |
946 * +======================+===================================+
947 * | CTL_LO | SRC_TR_WIDTH |
948 * +----------------------+-----------------------------------+
949 * \endrst
950 *
951 * @param DMAx DMAx instance
952 * @param channel This parameter can be one of the following values:
953 * @arg @ref LL_DMA_CHANNEL_0
954 * @arg @ref LL_DMA_CHANNEL_1
955 * @arg @ref LL_DMA_CHANNEL_2
956 * @arg @ref LL_DMA_CHANNEL_3
957 * @arg @ref LL_DMA_CHANNEL_4
958 * @arg @ref LL_DMA_CHANNEL_5
959 * @arg @ref LL_DMA_CHANNEL_6
960 * @arg @ref LL_DMA_CHANNEL_7
961 * @retval Returned value can be one of the following values:
962 * @arg @ref LL_DMA_SDATAALIGN_BYTE
963 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
964 * @arg @ref LL_DMA_SDATAALIGN_WORD
965 */
966 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
967 {
968 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
969 }
970
971 /**
972 * @brief Set Destination transfer width.
973 *
974 * \rst
975 * +----------------------+-----------------------------------+
976 * | Register | BitsName |
977 * +======================+===================================+
978 * | CTL_LO | DST_TR_WIDTH |
979 * +----------------------+-----------------------------------+
980 * \endrst
981 *
982 * @param DMAx DMAx instance
983 * @param channel This parameter can be one of the following values:
984 * @arg @ref LL_DMA_CHANNEL_0
985 * @arg @ref LL_DMA_CHANNEL_1
986 * @arg @ref LL_DMA_CHANNEL_2
987 * @arg @ref LL_DMA_CHANNEL_3
988 * @arg @ref LL_DMA_CHANNEL_4
989 * @arg @ref LL_DMA_CHANNEL_5
990 * @arg @ref LL_DMA_CHANNEL_6
991 * @arg @ref LL_DMA_CHANNEL_7
992 * @param dst_width This parameter can be one of the following values:
993 * @arg @ref LL_DMA_DDATAALIGN_BYTE
994 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
995 * @arg @ref LL_DMA_DDATAALIGN_WORD
996 * @retval None
997 */
998 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
999 {
1000 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1001 }
1002
1003 /**
1004 * @brief Get Destination transfer width.
1005 *
1006 * \rst
1007 * +----------------------+-----------------------------------+
1008 * | Register | BitsName |
1009 * +======================+===================================+
1010 * | CTL_LO | DST_TR_WIDTH |
1011 * +----------------------+-----------------------------------+
1012 * \endrst
1013 *
1014 * @param DMAx DMAx instance
1015 * @param channel This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_CHANNEL_0
1017 * @arg @ref LL_DMA_CHANNEL_1
1018 * @arg @ref LL_DMA_CHANNEL_2
1019 * @arg @ref LL_DMA_CHANNEL_3
1020 * @arg @ref LL_DMA_CHANNEL_4
1021 * @arg @ref LL_DMA_CHANNEL_5
1022 * @arg @ref LL_DMA_CHANNEL_6
1023 * @arg @ref LL_DMA_CHANNEL_7
1024 * @retval Returned value can be one of the following values:
1025 * @arg @ref LL_DMA_DDATAALIGN_BYTE
1026 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
1027 * @arg @ref LL_DMA_DDATAALIGN_WORD
1028 */
1029 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
1030 {
1031 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1032 }
1033
1034 /**
1035 * @brief Set Source Burst Transaction Length.
1036 *
1037 * \rst
1038 * +----------------------+-----------------------------------+
1039 * | Register | BitsName |
1040 * +======================+===================================+
1041 * | CTL_LO | SRC_MSIZE |
1042 * +----------------------+-----------------------------------+
1043 * \endrst
1044 *
1045 * @param DMAx DMAx instance
1046 * @param channel This parameter can be one of the following values:
1047 * @arg @ref LL_DMA_CHANNEL_0
1048 * @arg @ref LL_DMA_CHANNEL_1
1049 * @arg @ref LL_DMA_CHANNEL_2
1050 * @arg @ref LL_DMA_CHANNEL_3
1051 * @arg @ref LL_DMA_CHANNEL_4
1052 * @arg @ref LL_DMA_CHANNEL_5
1053 * @arg @ref LL_DMA_CHANNEL_6
1054 * @arg @ref LL_DMA_CHANNEL_7
1055 * @param burst_length This parameter can be one of the following values:
1056 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1057 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1058 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1059 * @retval None
1060 */
1061 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1062 {
1063 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1064 }
1065
1066 /**
1067 * @brief Get Burst Transaction Length.
1068 *
1069 * \rst
1070 * +----------------------+-----------------------------------+
1071 * | Register | BitsName |
1072 * +======================+===================================+
1073 * | CTL_LO | SRC_MSIZE |
1074 * +----------------------+-----------------------------------+
1075 * \endrst
1076 *
1077 * @param DMAx DMAx instance
1078 * @param channel This parameter can be one of the following values:
1079 * @arg @ref LL_DMA_CHANNEL_0
1080 * @arg @ref LL_DMA_CHANNEL_1
1081 * @arg @ref LL_DMA_CHANNEL_2
1082 * @arg @ref LL_DMA_CHANNEL_3
1083 * @arg @ref LL_DMA_CHANNEL_4
1084 * @arg @ref LL_DMA_CHANNEL_5
1085 * @arg @ref LL_DMA_CHANNEL_6
1086 * @arg @ref LL_DMA_CHANNEL_7
1087 * @retval Returned value can be one of the following values:
1088 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
1089 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1090 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1091 */
1092 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
1093 {
1094 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1095 }
1096
1097 /**
1098 * @brief Set Destination Burst Transaction Length.
1099 *
1100 * \rst
1101 * +----------------------+-----------------------------------+
1102 * | Register | BitsName |
1103 * +======================+===================================+
1104 * | CTL_LO | DST_MSIZE |
1105 * +----------------------+-----------------------------------+
1106 * \endrst
1107 *
1108 * @param DMAx DMAx instance
1109 * @param channel This parameter can be one of the following values:
1110 * @arg @ref LL_DMA_CHANNEL_0
1111 * @arg @ref LL_DMA_CHANNEL_1
1112 * @arg @ref LL_DMA_CHANNEL_2
1113 * @arg @ref LL_DMA_CHANNEL_3
1114 * @arg @ref LL_DMA_CHANNEL_4
1115 * @arg @ref LL_DMA_CHANNEL_5
1116 * @arg @ref LL_DMA_CHANNEL_6
1117 * @arg @ref LL_DMA_CHANNEL_7
1118 * @param burst_length This parameter can be one of the following values:
1119 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1120 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1121 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1122 * @retval None
1123 */
1124 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1125 {
1126 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1127 }
1128
1129 /**
1130 * @brief Get Destination Burst Transaction Length.
1131 *
1132 * \rst
1133 * +----------------------+-----------------------------------+
1134 * | Register | BitsName |
1135 * +======================+===================================+
1136 * | CTL_LO | DST_MSIZE |
1137 * +----------------------+-----------------------------------+
1138 * \endrst
1139 *
1140 * @param DMAx DMAx instance
1141 * @param channel This parameter can be one of the following values:
1142 * @arg @ref LL_DMA_CHANNEL_0
1143 * @arg @ref LL_DMA_CHANNEL_1
1144 * @arg @ref LL_DMA_CHANNEL_2
1145 * @arg @ref LL_DMA_CHANNEL_3
1146 * @arg @ref LL_DMA_CHANNEL_4
1147 * @arg @ref LL_DMA_CHANNEL_5
1148 * @arg @ref LL_DMA_CHANNEL_6
1149 * @arg @ref LL_DMA_CHANNEL_7
1150 * @retval Returned value can be one of the following values:
1151 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1152 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1153 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1154 */
1155 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
1156 {
1157 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1158 }
1159
1160 /**
1161 * @brief Set Channel priority level.
1162 *
1163 * \rst
1164 * +----------------------+-----------------------------------+
1165 * | Register | BitsName |
1166 * +======================+===================================+
1167 * | CFG_LO | CH_PRIOR |
1168 * +----------------------+-----------------------------------+
1169 * \endrst
1170 *
1171 * @param DMAx DMAx instance
1172 * @param channel This parameter can be one of the following values:
1173 * @arg @ref LL_DMA_CHANNEL_0
1174 * @arg @ref LL_DMA_CHANNEL_1
1175 * @arg @ref LL_DMA_CHANNEL_2
1176 * @arg @ref LL_DMA_CHANNEL_3
1177 * @arg @ref LL_DMA_CHANNEL_4
1178 * @arg @ref LL_DMA_CHANNEL_5
1179 * @arg @ref LL_DMA_CHANNEL_6
1180 * @arg @ref LL_DMA_CHANNEL_7
1181 * @param priority This parameter can be one of the following values:
1182 * @arg @ref LL_DMA_PRIORITY_0
1183 * @arg @ref LL_DMA_PRIORITY_1
1184 * @arg @ref LL_DMA_PRIORITY_2
1185 * @arg @ref LL_DMA_PRIORITY_3
1186 * @arg @ref LL_DMA_PRIORITY_4
1187 * @arg @ref LL_DMA_PRIORITY_5
1188 * @arg @ref LL_DMA_PRIORITY_6
1189 * @arg @ref LL_DMA_PRIORITY_7
1190 * @retval None
1191 */
1192 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
1193 {
1194 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1195 }
1196
1197 /**
1198 * @brief Get Channel priority level.
1199 *
1200 * \rst
1201 * +----------------------+-----------------------------------+
1202 * | Register | BitsName |
1203 * +======================+===================================+
1204 * | CFG_LO | CH_PRIOR |
1205 * +----------------------+-----------------------------------+
1206 * \endrst
1207 *
1208 * @param DMAx DMAx instance
1209 * @param channel This parameter can be one of the following values:
1210 * @arg @ref LL_DMA_CHANNEL_0
1211 * @arg @ref LL_DMA_CHANNEL_1
1212 * @arg @ref LL_DMA_CHANNEL_2
1213 * @arg @ref LL_DMA_CHANNEL_3
1214 * @arg @ref LL_DMA_CHANNEL_4
1215 * @arg @ref LL_DMA_CHANNEL_5
1216 * @arg @ref LL_DMA_CHANNEL_6
1217 * @arg @ref LL_DMA_CHANNEL_7
1218 * @retval Returned value can be one of the following values:
1219 * @arg @ref LL_DMA_PRIORITY_0
1220 * @arg @ref LL_DMA_PRIORITY_1
1221 * @arg @ref LL_DMA_PRIORITY_2
1222 * @arg @ref LL_DMA_PRIORITY_3
1223 * @arg @ref LL_DMA_PRIORITY_4
1224 * @arg @ref LL_DMA_PRIORITY_5
1225 * @arg @ref LL_DMA_PRIORITY_6
1226 * @arg @ref LL_DMA_PRIORITY_7
1227 */
1228 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
1229 {
1230 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1231 }
1232
1233 /**
1234 * @brief Set the block size of a transfer.
1235 * @note This action has no effect if channel is enabled.
1236 *
1237 * \rst
1238 * +----------------------+-----------------------------------+
1239 * | Register | BitsName |
1240 * +======================+===================================+
1241 * | CTL_HI | BLOCK_TS |
1242 * +----------------------+-----------------------------------+
1243 * \endrst
1244 *
1245 * @param DMAx DMAx instance
1246 * @param channel This parameter can be one of the following values:
1247 * @arg @ref LL_DMA_CHANNEL_0
1248 * @arg @ref LL_DMA_CHANNEL_1
1249 * @arg @ref LL_DMA_CHANNEL_2
1250 * @arg @ref LL_DMA_CHANNEL_3
1251 * @arg @ref LL_DMA_CHANNEL_4
1252 * @arg @ref LL_DMA_CHANNEL_5
1253 * @arg @ref LL_DMA_CHANNEL_6
1254 * @arg @ref LL_DMA_CHANNEL_7
1255 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1256 * @retval None
1257 */
1258 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1259 {
1260 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1261 }
1262
1263 /**
1264 * @brief Get the block size of a transfer.
1265 * @note Once the channel is enabled, the return value indicate the
1266 * remaining bytes to be transmitted.
1267 *
1268 * \rst
1269 * +----------------------+-----------------------------------+
1270 * | Register | BitsName |
1271 * +======================+===================================+
1272 * | CTL_HI | BLOCK_TS |
1273 * +----------------------+-----------------------------------+
1274 * \endrst
1275 *
1276 * @param DMAx DMAx instance
1277 * @param channel This parameter can be one of the following values:
1278 * @arg @ref LL_DMA_CHANNEL_0
1279 * @arg @ref LL_DMA_CHANNEL_1
1280 * @arg @ref LL_DMA_CHANNEL_2
1281 * @arg @ref LL_DMA_CHANNEL_3
1282 * @arg @ref LL_DMA_CHANNEL_4
1283 * @arg @ref LL_DMA_CHANNEL_5
1284 * @arg @ref LL_DMA_CHANNEL_6
1285 * @arg @ref LL_DMA_CHANNEL_7
1286 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1287 */
1288 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1289 {
1290 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1291 }
1292
1293 /**
1294 * @brief Configure the Source and Destination addresses.
1295 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1296 *
1297 * \rst
1298 * +----------------------+-----------------------------------+
1299 * | Register | BitsName |
1300 * +======================+===================================+
1301 * | SAR | SAR |
1302 * +----------------------+-----------------------------------+
1303 * \endrst
1304 * DAR | DAR
1305 * CTL_LO | TT_FC
1306 *
1307 * @param DMAx DMAx instance
1308 * @param channel This parameter can be one of the following values:
1309 * @arg @ref LL_DMA_CHANNEL_0
1310 * @arg @ref LL_DMA_CHANNEL_1
1311 * @arg @ref LL_DMA_CHANNEL_2
1312 * @arg @ref LL_DMA_CHANNEL_3
1313 * @arg @ref LL_DMA_CHANNEL_4
1314 * @arg @ref LL_DMA_CHANNEL_5
1315 * @arg @ref LL_DMA_CHANNEL_6
1316 * @arg @ref LL_DMA_CHANNEL_7
1317 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1318 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1319 * @param direction This parameter can be one of the following values:
1320 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1321 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1322 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1323 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1324 * @retval None
1325 */
1326 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx,
1327 uint32_t channel,
1328 uint32_t src_address,
1329 uint32_t dst_address,
1330 uint32_t direction)
1331 {
1332 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1333 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1334 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1335 }
1336
1337 /**
1338 * @brief Set the Source address.
1339 *
1340 * \rst
1341 * +----------------------+-----------------------------------+
1342 * | Register | BitsName |
1343 * +======================+===================================+
1344 * | SAR | SAR |
1345 * +----------------------+-----------------------------------+
1346 * \endrst
1347 *
1348 * @param DMAx DMAx instance
1349 * @param channel This parameter can be one of the following values:
1350 * @arg @ref LL_DMA_CHANNEL_0
1351 * @arg @ref LL_DMA_CHANNEL_1
1352 * @arg @ref LL_DMA_CHANNEL_2
1353 * @arg @ref LL_DMA_CHANNEL_3
1354 * @arg @ref LL_DMA_CHANNEL_4
1355 * @arg @ref LL_DMA_CHANNEL_5
1356 * @arg @ref LL_DMA_CHANNEL_6
1357 * @arg @ref LL_DMA_CHANNEL_7
1358 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1359 * @retval None
1360 */
1361 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1362 {
1363 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1364 }
1365
1366 /**
1367 * @brief Set the Destination address.
1368 *
1369 * \rst
1370 * +----------------------+-----------------------------------+
1371 * | Register | BitsName |
1372 * +======================+===================================+
1373 * | DAR | DAR |
1374 * +----------------------+-----------------------------------+
1375 * \endrst
1376 *
1377 * @param DMAx DMAx instance
1378 * @param channel This parameter can be one of the following values:
1379 * @arg @ref LL_DMA_CHANNEL_0
1380 * @arg @ref LL_DMA_CHANNEL_1
1381 * @arg @ref LL_DMA_CHANNEL_2
1382 * @arg @ref LL_DMA_CHANNEL_3
1383 * @arg @ref LL_DMA_CHANNEL_4
1384 * @arg @ref LL_DMA_CHANNEL_5
1385 * @arg @ref LL_DMA_CHANNEL_6
1386 * @arg @ref LL_DMA_CHANNEL_7
1387 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1388 * @retval None
1389 */
1390 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1391 {
1392 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1393 }
1394
1395 /**
1396 * @brief Get Source address.
1397 *
1398 * \rst
1399 * +----------------------+-----------------------------------+
1400 * | Register | BitsName |
1401 * +======================+===================================+
1402 * | SAR | SAR |
1403 * +----------------------+-----------------------------------+
1404 * \endrst
1405 *
1406 * @param DMAx DMAx instance
1407 * @param channel This parameter can be one of the following values:
1408 * @arg @ref LL_DMA_CHANNEL_0
1409 * @arg @ref LL_DMA_CHANNEL_1
1410 * @arg @ref LL_DMA_CHANNEL_2
1411 * @arg @ref LL_DMA_CHANNEL_3
1412 * @arg @ref LL_DMA_CHANNEL_4
1413 * @arg @ref LL_DMA_CHANNEL_5
1414 * @arg @ref LL_DMA_CHANNEL_6
1415 * @arg @ref LL_DMA_CHANNEL_7
1416 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1417 */
1418 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1419 {
1420 return READ_REG(DMAx->CHANNEL[channel].SAR);
1421 }
1422
1423 /**
1424 * @brief Get Destination address.
1425 *
1426 * \rst
1427 * +----------------------+-----------------------------------+
1428 * | Register | BitsName |
1429 * +======================+===================================+
1430 * | DAR | DAR |
1431 * +----------------------+-----------------------------------+
1432 * \endrst
1433 *
1434 * @param DMAx DMAx instance
1435 * @param channel This parameter can be one of the following values:
1436 * @arg @ref LL_DMA_CHANNEL_0
1437 * @arg @ref LL_DMA_CHANNEL_1
1438 * @arg @ref LL_DMA_CHANNEL_2
1439 * @arg @ref LL_DMA_CHANNEL_3
1440 * @arg @ref LL_DMA_CHANNEL_4
1441 * @arg @ref LL_DMA_CHANNEL_5
1442 * @arg @ref LL_DMA_CHANNEL_6
1443 * @arg @ref LL_DMA_CHANNEL_7
1444 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1445 */
1446 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1447 {
1448 return READ_REG(DMAx->CHANNEL[channel].DAR);
1449 }
1450
1451 /**
1452 * @brief Set the Memory to Memory Source address.
1453 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1454 *
1455 * \rst
1456 * +----------------------+-----------------------------------+
1457 * | Register | BitsName |
1458 * +======================+===================================+
1459 * | SAR | SAR |
1460 * +----------------------+-----------------------------------+
1461 * \endrst
1462 * CTL_LO | TT_FC
1463 * @param DMAx DMAx instance
1464 * @param channel This parameter can be one of the following values:
1465 * @arg @ref LL_DMA_CHANNEL_0
1466 * @arg @ref LL_DMA_CHANNEL_1
1467 * @arg @ref LL_DMA_CHANNEL_2
1468 * @arg @ref LL_DMA_CHANNEL_3
1469 * @arg @ref LL_DMA_CHANNEL_4
1470 * @arg @ref LL_DMA_CHANNEL_5
1471 * @arg @ref LL_DMA_CHANNEL_6
1472 * @arg @ref LL_DMA_CHANNEL_7
1473 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1474 * @retval None
1475 */
1476 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1477 {
1478 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1479 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1480 }
1481
1482 /**
1483 * @brief Set the Memory to Memory Destination address.
1484 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1485 *
1486 * \rst
1487 * +----------------------+-----------------------------------+
1488 * | Register | BitsName |
1489 * +======================+===================================+
1490 * | DAR | DAR |
1491 * +----------------------+-----------------------------------+
1492 * \endrst
1493 * CTL_LO | TT_FC
1494 *
1495 * @param DMAx DMAx instance
1496 * @param channel This parameter can be one of the following values:
1497 * @arg @ref LL_DMA_CHANNEL_0
1498 * @arg @ref LL_DMA_CHANNEL_1
1499 * @arg @ref LL_DMA_CHANNEL_2
1500 * @arg @ref LL_DMA_CHANNEL_3
1501 * @arg @ref LL_DMA_CHANNEL_4
1502 * @arg @ref LL_DMA_CHANNEL_5
1503 * @arg @ref LL_DMA_CHANNEL_6
1504 * @arg @ref LL_DMA_CHANNEL_7
1505 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1506 * @retval None
1507 */
1508 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1509 {
1510 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1511 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1512 }
1513
1514 /**
1515 * @brief Get the Memory to Memory Source address.
1516 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1517 *
1518 * \rst
1519 * +----------------------+-----------------------------------+
1520 * | Register | BitsName |
1521 * +======================+===================================+
1522 * | SAR | SAR |
1523 * +----------------------+-----------------------------------+
1524 * \endrst
1525 *
1526 * @param DMAx DMAx instance
1527 * @param channel This parameter can be one of the following values:
1528 * @arg @ref LL_DMA_CHANNEL_0
1529 * @arg @ref LL_DMA_CHANNEL_1
1530 * @arg @ref LL_DMA_CHANNEL_2
1531 * @arg @ref LL_DMA_CHANNEL_3
1532 * @arg @ref LL_DMA_CHANNEL_4
1533 * @arg @ref LL_DMA_CHANNEL_5
1534 * @arg @ref LL_DMA_CHANNEL_6
1535 * @arg @ref LL_DMA_CHANNEL_7
1536 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1537 */
1538 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1539 {
1540 return READ_REG(DMAx->CHANNEL[channel].SAR);
1541 }
1542
1543 /**
1544 * @brief Get the Memory to Memory Destination address.
1545 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1546 *
1547 * \rst
1548 * +----------------------+-----------------------------------+
1549 * | Register | BitsName |
1550 * +======================+===================================+
1551 * | DAR | DAR |
1552 * +----------------------+-----------------------------------+
1553 * \endrst
1554 *
1555 * @param DMAx DMAx instance
1556 * @param channel This parameter can be one of the following values:
1557 * @arg @ref LL_DMA_CHANNEL_0
1558 * @arg @ref LL_DMA_CHANNEL_1
1559 * @arg @ref LL_DMA_CHANNEL_2
1560 * @arg @ref LL_DMA_CHANNEL_3
1561 * @arg @ref LL_DMA_CHANNEL_4
1562 * @arg @ref LL_DMA_CHANNEL_5
1563 * @arg @ref LL_DMA_CHANNEL_6
1564 * @arg @ref LL_DMA_CHANNEL_7
1565 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1566 */
1567 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
1568 {
1569 return READ_REG(DMAx->CHANNEL[channel].DAR);
1570 }
1571
1572 /**
1573 * @brief Set source peripheral for DMA instance on Channel x.
1574 *
1575 * \rst
1576 * +----------------------+-----------------------------------+
1577 * | Register | BitsName |
1578 * +======================+===================================+
1579 * | CFG_HI | SRC_PER |
1580 * +----------------------+-----------------------------------+
1581 * \endrst
1582 *
1583 * @param DMAx DMAx instance
1584 * @param channel This parameter can be one of the following values:
1585 * @arg @ref LL_DMA_CHANNEL_0
1586 * @arg @ref LL_DMA_CHANNEL_1
1587 * @arg @ref LL_DMA_CHANNEL_2
1588 * @arg @ref LL_DMA_CHANNEL_3
1589 * @arg @ref LL_DMA_CHANNEL_4
1590 * @arg @ref LL_DMA_CHANNEL_5
1591 * @arg @ref LL_DMA_CHANNEL_6
1592 * @arg @ref LL_DMA_CHANNEL_7
1593 * @param peripheral This parameter can be one of the following values:
1594 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1595 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1596 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1597 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1598 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1599 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1600 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1601 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1602 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1603 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1604 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1605 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1606 * @arg @ref LL_DMA_PERIPH_UART0_TX
1607 * @arg @ref LL_DMA_PERIPH_UART0_RX
1608 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1609 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1610 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1611 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1612 * @arg @ref LL_DMA_PERIPH_SNSADC
1613 * @retval None
1614 */
1615 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1616 {
1617 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1618 }
1619
1620 /**
1621 * @brief Get source peripheral for DMA instance on Channel x.
1622 *
1623 * \rst
1624 * +----------------------+-----------------------------------+
1625 * | Register | BitsName |
1626 * +======================+===================================+
1627 * | CFG_HI | SRC_PER |
1628 * +----------------------+-----------------------------------+
1629 * \endrst
1630 *
1631 * @param DMAx DMAx instance
1632 * @param channel This parameter can be one of the following values:
1633 * @arg @ref LL_DMA_CHANNEL_0
1634 * @arg @ref LL_DMA_CHANNEL_1
1635 * @arg @ref LL_DMA_CHANNEL_2
1636 * @arg @ref LL_DMA_CHANNEL_3
1637 * @arg @ref LL_DMA_CHANNEL_4
1638 * @arg @ref LL_DMA_CHANNEL_5
1639 * @arg @ref LL_DMA_CHANNEL_6
1640 * @arg @ref LL_DMA_CHANNEL_7
1641 * @retval Returned value can be one of the following values:
1642 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1643 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1644 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1645 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1646 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1647 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1648 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1649 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1650 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1651 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1652 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1653 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1654 * @arg @ref LL_DMA_PERIPH_UART0_TX
1655 * @arg @ref LL_DMA_PERIPH_UART0_RX
1656 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1657 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1658 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1659 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1660 * @arg @ref LL_DMA_PERIPH_SNSADC
1661 */
1662 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
1663 {
1664 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1665 }
1666
1667 /**
1668 * @brief Set destination peripheral for DMA instance on Channel x.
1669 *
1670 * \rst
1671 * +----------------------+-----------------------------------+
1672 * | Register | BitsName |
1673 * +======================+===================================+
1674 * | CFG_HI | DST_PER |
1675 * +----------------------+-----------------------------------+
1676 * \endrst
1677 *
1678 * @param DMAx DMAx instance
1679 * @param channel This parameter can be one of the following values:
1680 * @arg @ref LL_DMA_CHANNEL_0
1681 * @arg @ref LL_DMA_CHANNEL_1
1682 * @arg @ref LL_DMA_CHANNEL_2
1683 * @arg @ref LL_DMA_CHANNEL_3
1684 * @arg @ref LL_DMA_CHANNEL_4
1685 * @arg @ref LL_DMA_CHANNEL_5
1686 * @arg @ref LL_DMA_CHANNEL_6
1687 * @arg @ref LL_DMA_CHANNEL_7
1688 * @param peripheral This parameter can be one of the following values:
1689 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1690 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1691 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1692 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1693 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1694 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1695 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1696 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1697 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1698 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1699 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1700 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1701 * @arg @ref LL_DMA_PERIPH_UART0_TX
1702 * @arg @ref LL_DMA_PERIPH_UART0_RX
1703 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1704 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1705 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1706 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1707 * @arg @ref LL_DMA_PERIPH_SNSADC
1708 * @retval None
1709 */
1710 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1711 {
1712 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1713 }
1714
1715 /**
1716 * @brief Get destination peripheral for DMA instance on Channel x.
1717 *
1718 * \rst
1719 * +----------------------+-----------------------------------+
1720 * | Register | BitsName |
1721 * +======================+===================================+
1722 * | CFG_HI | DST_PER |
1723 * +----------------------+-----------------------------------+
1724 * \endrst
1725 *
1726 * @param DMAx DMAx instance
1727 * @param channel This parameter can be one of the following values:
1728 * @arg @ref LL_DMA_CHANNEL_0
1729 * @arg @ref LL_DMA_CHANNEL_1
1730 * @arg @ref LL_DMA_CHANNEL_2
1731 * @arg @ref LL_DMA_CHANNEL_3
1732 * @arg @ref LL_DMA_CHANNEL_4
1733 * @arg @ref LL_DMA_CHANNEL_5
1734 * @arg @ref LL_DMA_CHANNEL_6
1735 * @arg @ref LL_DMA_CHANNEL_7
1736 * @retval Returned value can be one of the following values:
1737 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1738 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1739 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1740 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1741 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1742 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1743 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1744 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1745 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1746 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1747 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1748 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1749 * @arg @ref LL_DMA_PERIPH_UART0_TX
1750 * @arg @ref LL_DMA_PERIPH_UART0_RX
1751 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1752 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1753 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1754 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1755 * @arg @ref LL_DMA_PERIPH_SNSADC
1756 */
1757 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
1758 {
1759 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos;
1760 }
1761
1762 /**
1763 * @brief Set source and destination source handshaking interface.
1764 *
1765 * \rst
1766 * +----------------------+-----------------------------------+
1767 * | Register | BitsName |
1768 * +======================+===================================+
1769 * | CFG_HI | DST_PER |
1770 * +----------------------+-----------------------------------+
1771 * \endrst
1772 *
1773 * @param DMAx DMAx instance
1774 * @param channel This parameter can be one of the following values:
1775 * @arg @ref LL_DMA_CHANNEL_0
1776 * @arg @ref LL_DMA_CHANNEL_1
1777 * @arg @ref LL_DMA_CHANNEL_2
1778 * @arg @ref LL_DMA_CHANNEL_3
1779 * @arg @ref LL_DMA_CHANNEL_4
1780 * @arg @ref LL_DMA_CHANNEL_5
1781 * @arg @ref LL_DMA_CHANNEL_6
1782 * @arg @ref LL_DMA_CHANNEL_7
1783 * @param src_handshaking This parameter can be one of the following values:
1784 * @arg @ref LL_DMA_SHANDSHAKING_HW
1785 * @arg @ref LL_DMA_SHANDSHAKING_HW
1786 * @param dst_handshaking This parameter can be one of the following values:
1787 * @arg @ref LL_DMA_DHANDSHAKING_HW
1788 * @arg @ref LL_DMA_DHANDSHAKING_HW
1789 * @retval None
1790 */
1791 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
1792 {
1793 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1794 src_handshaking | dst_handshaking);
1795 }
1796
1797 /**
1798 * @brief Source Single Transaction Request.
1799 *
1800 * \rst
1801 * +----------------------+-----------------------------------+
1802 * | Register | BitsName |
1803 * +======================+===================================+
1804 * | SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC |
1805 * +----------------------+-----------------------------------+
1806 * \endrst
1807 * REQ_SRC | SRC_WE&SRC
1808 *
1809 * @param DMAx DMA instance.
1810 * @param channel This parameter can be one of the following values:
1811 * @arg @ref LL_DMA_CHANNEL_0
1812 * @arg @ref LL_DMA_CHANNEL_1
1813 * @arg @ref LL_DMA_CHANNEL_2
1814 * @arg @ref LL_DMA_CHANNEL_3
1815 * @arg @ref LL_DMA_CHANNEL_4
1816 * @arg @ref LL_DMA_CHANNEL_5
1817 * @arg @ref LL_DMA_CHANNEL_6
1818 * @arg @ref LL_DMA_CHANNEL_7
1819 * @retval None
1820 */
1821 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1822 {
1823 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1824 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1825 }
1826
1827 /**
1828 * @brief Source Burst Transaction Request.
1829 *
1830 * \rst
1831 * +----------------------+-----------------------------------+
1832 * | Register | BitsName |
1833 * +======================+===================================+
1834 * | REQ_SRC | SRC_WE&SRC |
1835 * +----------------------+-----------------------------------+
1836 * \endrst
1837 *
1838 * @param DMAx DMA instance.
1839 * @param channel This parameter can be one of the following values:
1840 * @arg @ref LL_DMA_CHANNEL_0
1841 * @arg @ref LL_DMA_CHANNEL_1
1842 * @arg @ref LL_DMA_CHANNEL_2
1843 * @arg @ref LL_DMA_CHANNEL_3
1844 * @arg @ref LL_DMA_CHANNEL_4
1845 * @arg @ref LL_DMA_CHANNEL_5
1846 * @arg @ref LL_DMA_CHANNEL_6
1847 * @arg @ref LL_DMA_CHANNEL_7
1848 * @retval None
1849 */
1850 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1851 {
1852 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1853 }
1854
1855 /**
1856 * @brief Source Last Single Transaction Request.
1857 *
1858 * \rst
1859 * +----------------------+-----------------------------------+
1860 * | Register | BitsName |
1861 * +======================+===================================+
1862 * | SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC |
1863 * +----------------------+-----------------------------------+
1864 * \endrst
1865 * LST_SRC | LST_SRC_WE&LST_SRC
1866 * REQ_SRC | SRC_WE&SRC
1867 *
1868 * @param DMAx DMA instance.
1869 * @param channel This parameter can be one of the following values:
1870 * @arg @ref LL_DMA_CHANNEL_0
1871 * @arg @ref LL_DMA_CHANNEL_1
1872 * @arg @ref LL_DMA_CHANNEL_2
1873 * @arg @ref LL_DMA_CHANNEL_3
1874 * @arg @ref LL_DMA_CHANNEL_4
1875 * @arg @ref LL_DMA_CHANNEL_5
1876 * @arg @ref LL_DMA_CHANNEL_6
1877 * @arg @ref LL_DMA_CHANNEL_7
1878 * @retval None
1879 */
1880 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1881 {
1882 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1883 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1884 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1885 }
1886
1887 /**
1888 * @brief Source Last Burst Transaction Request.
1889 *
1890 * \rst
1891 * +----------------------+-----------------------------------+
1892 * | Register | BitsName |
1893 * +======================+===================================+
1894 * | LST_SRC | LST_SRC_WE&LST_SRC |
1895 * +----------------------+-----------------------------------+
1896 * \endrst
1897 * REQ_SRC | SRC_WE&SRC
1898 *
1899 * @param DMAx DMA instance.
1900 * @param channel This parameter can be one of the following values:
1901 * @arg @ref LL_DMA_CHANNEL_0
1902 * @arg @ref LL_DMA_CHANNEL_1
1903 * @arg @ref LL_DMA_CHANNEL_2
1904 * @arg @ref LL_DMA_CHANNEL_3
1905 * @arg @ref LL_DMA_CHANNEL_4
1906 * @arg @ref LL_DMA_CHANNEL_5
1907 * @arg @ref LL_DMA_CHANNEL_6
1908 * @arg @ref LL_DMA_CHANNEL_7
1909 * @retval None
1910 */
1911 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1912 {
1913 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1914 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1915 }
1916
1917 /**
1918 * @brief Destination Single Transaction Request.
1919 *
1920 * \rst
1921 * +----------------------+-----------------------------------+
1922 * | Register | BitsName |
1923 * +======================+===================================+
1924 * | SGL_REQ_DST | REQ_DST_WE&REQ_DST |
1925 * +----------------------+-----------------------------------+
1926 * \endrst
1927 * REQ_DST | DST_WE&DST
1928 *
1929 * @param DMAx DMA instance.
1930 * @param channel This parameter can be one of the following values:
1931 * @arg @ref LL_DMA_CHANNEL_0
1932 * @arg @ref LL_DMA_CHANNEL_1
1933 * @arg @ref LL_DMA_CHANNEL_2
1934 * @arg @ref LL_DMA_CHANNEL_3
1935 * @arg @ref LL_DMA_CHANNEL_4
1936 * @arg @ref LL_DMA_CHANNEL_5
1937 * @arg @ref LL_DMA_CHANNEL_6
1938 * @arg @ref LL_DMA_CHANNEL_7
1939 * @retval None
1940 */
1941 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1942 {
1943 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1944 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1945 }
1946
1947 /**
1948 * @brief Destination Burst Transaction Request.
1949 *
1950 * \rst
1951 * +----------------------+-----------------------------------+
1952 * | Register | BitsName |
1953 * +======================+===================================+
1954 * | REQ_DST | DST_WE&DST |
1955 * +----------------------+-----------------------------------+
1956 * \endrst
1957 *
1958 * @param DMAx DMA instance.
1959 * @param channel This parameter can be one of the following values:
1960 * @arg @ref LL_DMA_CHANNEL_0
1961 * @arg @ref LL_DMA_CHANNEL_1
1962 * @arg @ref LL_DMA_CHANNEL_2
1963 * @arg @ref LL_DMA_CHANNEL_3
1964 * @arg @ref LL_DMA_CHANNEL_4
1965 * @arg @ref LL_DMA_CHANNEL_5
1966 * @arg @ref LL_DMA_CHANNEL_6
1967 * @arg @ref LL_DMA_CHANNEL_7
1968 * @retval None
1969 */
1970 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1971 {
1972 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1973 }
1974
1975 /**
1976 * @brief Destination Last Single Transaction Request.
1977 *
1978 * \rst
1979 * +----------------------+-----------------------------------+
1980 * | Register | BitsName |
1981 * +======================+===================================+
1982 * | SGL_REQ_DST | REQ_DST_WE&REQ_DST |
1983 * +----------------------+-----------------------------------+
1984 * \endrst
1985 * LST_DST | LST_DST_WE&LST_DST
1986 * REQ_DST | DST_WE&DST
1987 *
1988 * @param DMAx DMA instance.
1989 * @param channel This parameter can be one of the following values:
1990 * @arg @ref LL_DMA_CHANNEL_0
1991 * @arg @ref LL_DMA_CHANNEL_1
1992 * @arg @ref LL_DMA_CHANNEL_2
1993 * @arg @ref LL_DMA_CHANNEL_3
1994 * @arg @ref LL_DMA_CHANNEL_4
1995 * @arg @ref LL_DMA_CHANNEL_5
1996 * @arg @ref LL_DMA_CHANNEL_6
1997 * @arg @ref LL_DMA_CHANNEL_7
1998 * @retval None
1999 */
2000 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
2001 {
2002 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2003 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2004 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2005 }
2006
2007 /**
2008 * @brief Destination Last Burst Transaction Request.
2009 *
2010 * \rst
2011 * +----------------------+-----------------------------------+
2012 * | Register | BitsName |
2013 * +======================+===================================+
2014 * | LST_DST | LST_DST_WE&LST_DST |
2015 * +----------------------+-----------------------------------+
2016 * \endrst
2017 * REQ_DST | DST_WE&DST
2018 *
2019 * @param DMAx DMA instance.
2020 * @param channel This parameter can be one of the following values:
2021 * @arg @ref LL_DMA_CHANNEL_0
2022 * @arg @ref LL_DMA_CHANNEL_1
2023 * @arg @ref LL_DMA_CHANNEL_2
2024 * @arg @ref LL_DMA_CHANNEL_3
2025 * @arg @ref LL_DMA_CHANNEL_4
2026 * @arg @ref LL_DMA_CHANNEL_5
2027 * @arg @ref LL_DMA_CHANNEL_6
2028 * @arg @ref LL_DMA_CHANNEL_7
2029 * @retval None
2030 */
2031 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
2032 {
2033 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2034 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2035 }
2036
2037 /** @} */
2038
2039 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2040 * @{
2041 */
2042
2043 /**
2044 * @brief Get DMA Module global transfer complete interrupt status.
2045 *
2046 * \rst
2047 * +----------------------+-----------------------------------+
2048 * | Register | BitsName |
2049 * +======================+===================================+
2050 * | STATUS_INT | TFR |
2051 * +----------------------+-----------------------------------+
2052 * \endrst
2053 *
2054 * @param DMAx DMAx instance
2055 * @retval State of bit (1 or 0).
2056 */
2057 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
2058 {
2059 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2060 }
2061
2062 /**
2063 * @brief Get DMA Module global block complete interrupt status.
2064 *
2065 * \rst
2066 * +----------------------+-----------------------------------+
2067 * | Register | BitsName |
2068 * +======================+===================================+
2069 * | STATUS_INT | BLOCK |
2070 * +----------------------+-----------------------------------+
2071 * \endrst
2072 *
2073 * @param DMAx DMAx instance
2074 * @retval State of bit (1 or 0).
2075 */
2076 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
2077 {
2078 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2079 }
2080
2081 /**
2082 * @brief Get DMA Module global source transaction complete interrupt status.
2083 *
2084 * \rst
2085 * +----------------------+-----------------------------------+
2086 * | Register | BitsName |
2087 * +======================+===================================+
2088 * | STATUS_INT | SRCT |
2089 * +----------------------+-----------------------------------+
2090 * \endrst
2091 *
2092 * @param DMAx DMAx instance
2093 * @retval State of bit (1 or 0).
2094 */
2095 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
2096 {
2097 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2098 }
2099
2100 /**
2101 * @brief Get DMA Module global destination transaction complete interrupt status.
2102 *
2103 * \rst
2104 * +----------------------+-----------------------------------+
2105 * | Register | BitsName |
2106 * +======================+===================================+
2107 * | STATUS_INT | DSTT |
2108 * +----------------------+-----------------------------------+
2109 * \endrst
2110 *
2111 * @param DMAx DMAx instance
2112 * @retval State of bit (1 or 0).
2113 */
2114 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
2115 {
2116 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2117 }
2118
2119 /**
2120 * @brief Get DMA Module global error interrupt status.
2121 *
2122 * \rst
2123 * +----------------------+-----------------------------------+
2124 * | Register | BitsName |
2125 * +======================+===================================+
2126 * | STATUS_INT | ERR |
2127 * +----------------------+-----------------------------------+
2128 * \endrst
2129 *
2130 * @param DMAx DMAx instance
2131 * @retval State of bit (1 or 0).
2132 */
2133 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
2134 {
2135 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2136 }
2137
2138 /**
2139 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
2140 *
2141 * \rst
2142 * +----------------------+-----------------------------------+
2143 * | Register | BitsName |
2144 * +======================+===================================+
2145 * | RAW_TFR | RAW |
2146 * +----------------------+-----------------------------------+
2147 * \endrst
2148 *
2149 * @param DMAx DMAx instance
2150 * @param channel This parameter can be one of the following values:
2151 * @arg @ref LL_DMA_CHANNEL_0
2152 * @arg @ref LL_DMA_CHANNEL_1
2153 * @arg @ref LL_DMA_CHANNEL_2
2154 * @arg @ref LL_DMA_CHANNEL_3
2155 * @arg @ref LL_DMA_CHANNEL_4
2156 * @arg @ref LL_DMA_CHANNEL_5
2157 * @arg @ref LL_DMA_CHANNEL_6
2158 * @arg @ref LL_DMA_CHANNEL_7
2159 * @retval State of bit (1 or 0).
2160 */
2161 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
2162 {
2163 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2164 }
2165
2166 /**
2167 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
2168 *
2169 * \rst
2170 * +----------------------+-----------------------------------+
2171 * | Register | BitsName |
2172 * +======================+===================================+
2173 * | RAW_BLK | RAW |
2174 * +----------------------+-----------------------------------+
2175 * \endrst
2176 *
2177 * @param DMAx DMAx instance
2178 * @param channel This parameter can be one of the following values:
2179 * @arg @ref LL_DMA_CHANNEL_0
2180 * @arg @ref LL_DMA_CHANNEL_1
2181 * @arg @ref LL_DMA_CHANNEL_2
2182 * @arg @ref LL_DMA_CHANNEL_3
2183 * @arg @ref LL_DMA_CHANNEL_4
2184 * @arg @ref LL_DMA_CHANNEL_5
2185 * @arg @ref LL_DMA_CHANNEL_6
2186 * @arg @ref LL_DMA_CHANNEL_7
2187 * @retval State of bit (1 or 0).
2188 */
2189 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
2190 {
2191 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2192 }
2193
2194 /**
2195 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
2196 *
2197 * \rst
2198 * +----------------------+-----------------------------------+
2199 * | Register | BitsName |
2200 * +======================+===================================+
2201 * | RAW_SRC_TRN | RAW |
2202 * +----------------------+-----------------------------------+
2203 * \endrst
2204 *
2205 * @param DMAx DMAx instance
2206 * @param channel This parameter can be one of the following values:
2207 * @arg @ref LL_DMA_CHANNEL_0
2208 * @arg @ref LL_DMA_CHANNEL_1
2209 * @arg @ref LL_DMA_CHANNEL_2
2210 * @arg @ref LL_DMA_CHANNEL_3
2211 * @arg @ref LL_DMA_CHANNEL_4
2212 * @arg @ref LL_DMA_CHANNEL_5
2213 * @arg @ref LL_DMA_CHANNEL_6
2214 * @arg @ref LL_DMA_CHANNEL_7
2215 * @retval State of bit (1 or 0).
2216 */
2217 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
2218 {
2219 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2220 }
2221
2222 /**
2223 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
2224 *
2225 * \rst
2226 * +----------------------+-----------------------------------+
2227 * | Register | BitsName |
2228 * +======================+===================================+
2229 * | RAW_DST_TRN | RAW |
2230 * +----------------------+-----------------------------------+
2231 * \endrst
2232 *
2233 * @param DMAx DMAx instance
2234 * @param channel This parameter can be one of the following values:
2235 * @arg @ref LL_DMA_CHANNEL_0
2236 * @arg @ref LL_DMA_CHANNEL_1
2237 * @arg @ref LL_DMA_CHANNEL_2
2238 * @arg @ref LL_DMA_CHANNEL_3
2239 * @arg @ref LL_DMA_CHANNEL_4
2240 * @arg @ref LL_DMA_CHANNEL_5
2241 * @arg @ref LL_DMA_CHANNEL_6
2242 * @arg @ref LL_DMA_CHANNEL_7
2243 * @retval State of bit (1 or 0).
2244 */
2245 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
2246 {
2247 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2248 }
2249
2250 /**
2251 * @brief Indicate the Raw Status of IntErr Interrupt flag.
2252 *
2253 * \rst
2254 * +----------------------+-----------------------------------+
2255 * | Register | BitsName |
2256 * +======================+===================================+
2257 * | RAW_ERR | RAW |
2258 * +----------------------+-----------------------------------+
2259 * \endrst
2260 *
2261 * @param DMAx DMAx instance
2262 * @param channel This parameter can be one of the following values:
2263 * @arg @ref LL_DMA_CHANNEL_0
2264 * @arg @ref LL_DMA_CHANNEL_1
2265 * @arg @ref LL_DMA_CHANNEL_2
2266 * @arg @ref LL_DMA_CHANNEL_3
2267 * @arg @ref LL_DMA_CHANNEL_4
2268 * @arg @ref LL_DMA_CHANNEL_5
2269 * @arg @ref LL_DMA_CHANNEL_6
2270 * @arg @ref LL_DMA_CHANNEL_7
2271 * @retval State of bit (1 or 0).
2272 */
2273 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
2274 {
2275 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2276 }
2277
2278 /**
2279 * @brief Indicate the status of DMA Channel transfer complete flag.
2280 *
2281 * \rst
2282 * +----------------------+-----------------------------------+
2283 * | Register | BitsName |
2284 * +======================+===================================+
2285 * | STAT_TFR | STATUS |
2286 * +----------------------+-----------------------------------+
2287 * \endrst
2288 *
2289 * @param DMAx DMAx instance
2290 * @param channel This parameter can be one of the following values:
2291 * @arg @ref LL_DMA_CHANNEL_0
2292 * @arg @ref LL_DMA_CHANNEL_1
2293 * @arg @ref LL_DMA_CHANNEL_2
2294 * @arg @ref LL_DMA_CHANNEL_3
2295 * @arg @ref LL_DMA_CHANNEL_4
2296 * @arg @ref LL_DMA_CHANNEL_5
2297 * @arg @ref LL_DMA_CHANNEL_6
2298 * @arg @ref LL_DMA_CHANNEL_7
2299 * @retval State of bit (1 or 0).
2300 */
2301 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2302 {
2303 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2304 }
2305
2306 /**
2307 * @brief Indicate the status of Channel 0 transfer complete flag.
2308 *
2309 * \rst
2310 * +----------------------+-----------------------------------+
2311 * | Register | BitsName |
2312 * +======================+===================================+
2313 * | STAT_TFR | STATUS |
2314 * +----------------------+-----------------------------------+
2315 * \endrst
2316 *
2317 * @param DMAx DMAx instance
2318 * @retval State of bit (1 or 0).
2319 */
2320 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
2321 {
2322 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2323 }
2324
2325 /**
2326 * @brief Indicate the status of Channel 1 transfer complete flag.
2327 *
2328 * \rst
2329 * +----------------------+-----------------------------------+
2330 * | Register | BitsName |
2331 * +======================+===================================+
2332 * | STAT_TFR | STATUS |
2333 * +----------------------+-----------------------------------+
2334 * \endrst
2335 *
2336 * @param DMAx DMAx instance
2337 * @retval State of bit (1 or 0).
2338 */
2339 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
2340 {
2341 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2342 }
2343
2344 /**
2345 * @brief Indicate the status of Channel 2 transfer complete flag.
2346 *
2347 * \rst
2348 * +----------------------+-----------------------------------+
2349 * | Register | BitsName |
2350 * +======================+===================================+
2351 * | STAT_TFR | STATUS |
2352 * +----------------------+-----------------------------------+
2353 * \endrst
2354 *
2355 * @param DMAx DMAx instance
2356 * @retval State of bit (1 or 0).
2357 */
2358 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
2359 {
2360 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2361 }
2362
2363 /**
2364 * @brief Indicate the status of Channel 3 transfer complete flag.
2365 *
2366 * \rst
2367 * +----------------------+-----------------------------------+
2368 * | Register | BitsName |
2369 * +======================+===================================+
2370 * | STAT_TFR | STATUS |
2371 * +----------------------+-----------------------------------+
2372 * \endrst
2373 *
2374 * @param DMAx DMAx instance
2375 * @retval State of bit (1 or 0).
2376 */
2377 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
2378 {
2379 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2380 }
2381
2382 /**
2383 * @brief Indicate the status of Channel 4 transfer complete flag.
2384 *
2385 * \rst
2386 * +----------------------+-----------------------------------+
2387 * | Register | BitsName |
2388 * +======================+===================================+
2389 * | STAT_TFR | STATUS |
2390 * +----------------------+-----------------------------------+
2391 * \endrst
2392 *
2393 * @param DMAx DMAx instance
2394 * @retval State of bit (1 or 0).
2395 */
2396 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
2397 {
2398 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2399 }
2400
2401 /**
2402 * @brief Indicate the status of Channel 5 transfer complete flag.
2403 *
2404 * \rst
2405 * +----------------------+-----------------------------------+
2406 * | Register | BitsName |
2407 * +======================+===================================+
2408 * | STAT_TFR | STATUS |
2409 * +----------------------+-----------------------------------+
2410 * \endrst
2411 *
2412 * @param DMAx DMAx instance
2413 * @retval State of bit (1 or 0).
2414 */
2415 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
2416 {
2417 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
2418 }
2419
2420 /**
2421 * @brief Indicate the status of Channel 6 transfer complete flag.
2422 *
2423 * \rst
2424 * +----------------------+-----------------------------------+
2425 * | Register | BitsName |
2426 * +======================+===================================+
2427 * | STAT_TFR | STATUS |
2428 * +----------------------+-----------------------------------+
2429 * \endrst
2430 *
2431 * @param DMAx DMAx instance
2432 * @retval State of bit (1 or 0).
2433 */
2434 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
2435 {
2436 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
2437 }
2438
2439 /**
2440 * @brief Indicate the status of Channel 7 transfer complete flag.
2441 *
2442 * \rst
2443 * +----------------------+-----------------------------------+
2444 * | Register | BitsName |
2445 * +======================+===================================+
2446 * | STAT_TFR | STATUS |
2447 * +----------------------+-----------------------------------+
2448 * \endrst
2449 *
2450 * @param DMAx DMAx instance
2451 * @retval State of bit (1 or 0).
2452 */
2453 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
2454 {
2455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
2456 }
2457
2458 /**
2459 * @brief Indicate the status of DMA Channel block complete flag.
2460 *
2461 * \rst
2462 * +----------------------+-----------------------------------+
2463 * | Register | BitsName |
2464 * +======================+===================================+
2465 * | STAT_BLK | STATUS |
2466 * +----------------------+-----------------------------------+
2467 * \endrst
2468 *
2469 * @param DMAx DMAx instance
2470 * @param channel This parameter can be one of the following values:
2471 * @arg @ref LL_DMA_CHANNEL_0
2472 * @arg @ref LL_DMA_CHANNEL_1
2473 * @arg @ref LL_DMA_CHANNEL_2
2474 * @arg @ref LL_DMA_CHANNEL_3
2475 * @arg @ref LL_DMA_CHANNEL_4
2476 * @arg @ref LL_DMA_CHANNEL_5
2477 * @arg @ref LL_DMA_CHANNEL_6
2478 * @arg @ref LL_DMA_CHANNEL_7
2479 * @retval State of bit (1 or 0).
2480 */
2481 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2482 {
2483 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2484 }
2485
2486 /**
2487 * @brief Indicate the status of Channel 0 block complete flag.
2488 *
2489 * \rst
2490 * +----------------------+-----------------------------------+
2491 * | Register | BitsName |
2492 * +======================+===================================+
2493 * | STAT_BLK | STATUS |
2494 * +----------------------+-----------------------------------+
2495 * \endrst
2496 *
2497 * @param DMAx DMAx instance
2498 * @retval State of bit (1 or 0).
2499 */
2500 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
2501 {
2502 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2503 }
2504
2505 /**
2506 * @brief Indicate the status of Channel 1 block complete flag.
2507 *
2508 * \rst
2509 * +----------------------+-----------------------------------+
2510 * | Register | BitsName |
2511 * +======================+===================================+
2512 * | STAT_BLK | STATUS |
2513 * +----------------------+-----------------------------------+
2514 * \endrst
2515 *
2516 * @param DMAx DMAx instance
2517 * @retval State of bit (1 or 0).
2518 */
2519 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
2520 {
2521 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2522 }
2523
2524 /**
2525 * @brief Indicate the status of Channel 2 block complete flag.
2526 *
2527 * \rst
2528 * +----------------------+-----------------------------------+
2529 * | Register | BitsName |
2530 * +======================+===================================+
2531 * | STAT_BLK | STATUS |
2532 * +----------------------+-----------------------------------+
2533 * \endrst
2534 *
2535 * @param DMAx DMAx instance
2536 * @retval State of bit (1 or 0).
2537 */
2538 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
2539 {
2540 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2541 }
2542
2543 /**
2544 * @brief Indicate the status of Channel 3 block complete flag.
2545 *
2546 * \rst
2547 * +----------------------+-----------------------------------+
2548 * | Register | BitsName |
2549 * +======================+===================================+
2550 * | STAT_BLK | STATUS |
2551 * +----------------------+-----------------------------------+
2552 * \endrst
2553 *
2554 * @param DMAx DMAx instance
2555 * @retval State of bit (1 or 0).
2556 */
2557 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
2558 {
2559 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2560 }
2561
2562 /**
2563 * @brief Indicate the status of Channel 4 block complete flag.
2564 *
2565 * \rst
2566 * +----------------------+-----------------------------------+
2567 * | Register | BitsName |
2568 * +======================+===================================+
2569 * | STAT_BLK | STATUS |
2570 * +----------------------+-----------------------------------+
2571 * \endrst
2572 *
2573 * @param DMAx DMAx instance
2574 * @retval State of bit (1 or 0).
2575 */
2576 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
2577 {
2578 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2579 }
2580
2581 /**
2582 * @brief Indicate the status of Channel 5 block complete flag.
2583 *
2584 * \rst
2585 * +----------------------+-----------------------------------+
2586 * | Register | BitsName |
2587 * +======================+===================================+
2588 * | STAT_BLK | STATUS |
2589 * +----------------------+-----------------------------------+
2590 * \endrst
2591 *
2592 * @param DMAx DMAx instance
2593 * @retval State of bit (1 or 0).
2594 */
2595 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
2596 {
2597 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
2598 }
2599
2600 /**
2601 * @brief Indicate the status of Channel 6 block complete flag.
2602 *
2603 * \rst
2604 * +----------------------+-----------------------------------+
2605 * | Register | BitsName |
2606 * +======================+===================================+
2607 * | STAT_BLK | STATUS |
2608 * +----------------------+-----------------------------------+
2609 * \endrst
2610 *
2611 * @param DMAx DMAx instance
2612 * @retval State of bit (1 or 0).
2613 */
2614 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
2615 {
2616 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
2617 }
2618
2619 /**
2620 * @brief Indicate the status of Channel 7 block complete flag.
2621 *
2622 * \rst
2623 * +----------------------+-----------------------------------+
2624 * | Register | BitsName |
2625 * +======================+===================================+
2626 * | STAT_BLK | STATUS |
2627 * +----------------------+-----------------------------------+
2628 * \endrst
2629 *
2630 * @param DMAx DMAx instance
2631 * @retval State of bit (1 or 0).
2632 */
2633 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
2634 {
2635 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
2636 }
2637
2638 /**
2639 * @brief Indicate the status of DMA Channel source transaction complete flag.
2640 *
2641 * \rst
2642 * +----------------------+-----------------------------------+
2643 * | Register | BitsName |
2644 * +======================+===================================+
2645 * | STAT_SRC_TRN | STATUS |
2646 * +----------------------+-----------------------------------+
2647 * \endrst
2648 *
2649 * @param DMAx DMAx instance
2650 * @param channel This parameter can be one of the following values:
2651 * @arg @ref LL_DMA_CHANNEL_0
2652 * @arg @ref LL_DMA_CHANNEL_1
2653 * @arg @ref LL_DMA_CHANNEL_2
2654 * @arg @ref LL_DMA_CHANNEL_3
2655 * @arg @ref LL_DMA_CHANNEL_4
2656 * @arg @ref LL_DMA_CHANNEL_5
2657 * @arg @ref LL_DMA_CHANNEL_6
2658 * @arg @ref LL_DMA_CHANNEL_7
2659 * @retval State of bit (1 or 0).
2660 */
2661 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2662 {
2663 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2664 }
2665
2666 /**
2667 * @brief Indicate the status of Channel 0 source transaction complete flag.
2668 *
2669 * \rst
2670 * +----------------------+-----------------------------------+
2671 * | Register | BitsName |
2672 * +======================+===================================+
2673 * | STAT_SRC_TRN | STATUS |
2674 * +----------------------+-----------------------------------+
2675 * \endrst
2676 *
2677 * @param DMAx DMAx instance
2678 * @retval State of bit (1 or 0).
2679 */
2680 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
2681 {
2682 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2683 }
2684
2685 /**
2686 * @brief Indicate the status of Channel 1 source transaction complete flag.
2687 *
2688 * \rst
2689 * +----------------------+-----------------------------------+
2690 * | Register | BitsName |
2691 * +======================+===================================+
2692 * | STAT_SRC_TRN | STATUS |
2693 * +----------------------+-----------------------------------+
2694 * \endrst
2695 *
2696 * @param DMAx DMAx instance
2697 * @retval State of bit (1 or 0).
2698 */
2699 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
2700 {
2701 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2702 }
2703
2704 /**
2705 * @brief Indicate the status of Channel 2 source transaction complete flag.
2706 *
2707 * \rst
2708 * +----------------------+-----------------------------------+
2709 * | Register | BitsName |
2710 * +======================+===================================+
2711 * | STAT_SRC_TRN | STATUS |
2712 * +----------------------+-----------------------------------+
2713 * \endrst
2714 *
2715 * @param DMAx DMAx instance
2716 * @retval State of bit (1 or 0).
2717 */
2718 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
2719 {
2720 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2721 }
2722
2723 /**
2724 * @brief Indicate the status of Channel 3 source transaction complete flag.
2725 *
2726 * \rst
2727 * +----------------------+-----------------------------------+
2728 * | Register | BitsName |
2729 * +======================+===================================+
2730 * | STAT_SRC_TRN | STATUS |
2731 * +----------------------+-----------------------------------+
2732 * \endrst
2733 *
2734 * @param DMAx DMAx instance
2735 * @retval State of bit (1 or 0).
2736 */
2737 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
2738 {
2739 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2740 }
2741
2742 /**
2743 * @brief Indicate the status of Channel 4 source transaction complete flag.
2744 *
2745 * \rst
2746 * +----------------------+-----------------------------------+
2747 * | Register | BitsName |
2748 * +======================+===================================+
2749 * | STAT_SRC_TRN | STATUS |
2750 * +----------------------+-----------------------------------+
2751 * \endrst
2752 *
2753 * @param DMAx DMAx instance
2754 * @retval State of bit (1 or 0).
2755 */
2756 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
2757 {
2758 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2759 }
2760
2761 /**
2762 * @brief Indicate the status of Channel 5 source transaction complete flag.
2763 *
2764 * \rst
2765 * +----------------------+-----------------------------------+
2766 * | Register | BitsName |
2767 * +======================+===================================+
2768 * | STAT_SRC_TRN | STATUS |
2769 * +----------------------+-----------------------------------+
2770 * \endrst
2771 *
2772 * @param DMAx DMAx instance
2773 * @retval State of bit (1 or 0).
2774 */
2775 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
2776 {
2777 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
2778 }
2779
2780 /**
2781 * @brief Indicate the status of Channel 6 source transaction complete flag.
2782 *
2783 * \rst
2784 * +----------------------+-----------------------------------+
2785 * | Register | BitsName |
2786 * +======================+===================================+
2787 * | STAT_SRC_TRN | STATUS |
2788 * +----------------------+-----------------------------------+
2789 * \endrst
2790 *
2791 * @param DMAx DMAx instance
2792 * @retval State of bit (1 or 0).
2793 */
2794 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
2795 {
2796 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
2797 }
2798
2799 /**
2800 * @brief Indicate the status of Channel 7 source transaction complete flag.
2801 *
2802 * \rst
2803 * +----------------------+-----------------------------------+
2804 * | Register | BitsName |
2805 * +======================+===================================+
2806 * | STAT_SRC_TRN | STATUS |
2807 * +----------------------+-----------------------------------+
2808 * \endrst
2809 *
2810 * @param DMAx DMAx instance
2811 * @retval State of bit (1 or 0).
2812 */
2813 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
2814 {
2815 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
2816 }
2817
2818 /**
2819 * @brief Indicate the status of DMA Channel destination transaction complete flag.
2820 *
2821 * \rst
2822 * +----------------------+-----------------------------------+
2823 * | Register | BitsName |
2824 * +======================+===================================+
2825 * | STAT_DST_TRN | STATUS |
2826 * +----------------------+-----------------------------------+
2827 * \endrst
2828 *
2829 * @param DMAx DMAx instance
2830 * @param channel This parameter can be one of the following values:
2831 * @arg @ref LL_DMA_CHANNEL_0
2832 * @arg @ref LL_DMA_CHANNEL_1
2833 * @arg @ref LL_DMA_CHANNEL_2
2834 * @arg @ref LL_DMA_CHANNEL_3
2835 * @arg @ref LL_DMA_CHANNEL_4
2836 * @arg @ref LL_DMA_CHANNEL_5
2837 * @arg @ref LL_DMA_CHANNEL_6
2838 * @arg @ref LL_DMA_CHANNEL_7
2839 * @retval State of bit (1 or 0).
2840 */
2841 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2842 {
2843 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2844 }
2845
2846 /**
2847 * @brief Indicate the status of Channel 0 destination transaction complete flag.
2848 *
2849 * \rst
2850 * +----------------------+-----------------------------------+
2851 * | Register | BitsName |
2852 * +======================+===================================+
2853 * | STAT_DST_TRN | STATUS |
2854 * +----------------------+-----------------------------------+
2855 * \endrst
2856 *
2857 * @param DMAx DMAx instance
2858 * @retval State of bit (1 or 0).
2859 */
2860 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
2861 {
2862 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2863 }
2864
2865 /**
2866 * @brief Indicate the status of Channel 1 destination transaction complete flag.
2867 *
2868 * \rst
2869 * +----------------------+-----------------------------------+
2870 * | Register | BitsName |
2871 * +======================+===================================+
2872 * | STAT_DST_TRN | STATUS |
2873 * +----------------------+-----------------------------------+
2874 * \endrst
2875 *
2876 * @param DMAx DMAx instance
2877 * @retval State of bit (1 or 0).
2878 */
2879 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
2880 {
2881 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2882 }
2883
2884 /**
2885 * @brief Indicate the status of Channel 2 destination transaction complete flag.
2886 *
2887 * \rst
2888 * +----------------------+-----------------------------------+
2889 * | Register | BitsName |
2890 * +======================+===================================+
2891 * | STAT_DST_TRN | STATUS |
2892 * +----------------------+-----------------------------------+
2893 * \endrst
2894 *
2895 * @param DMAx DMAx instance
2896 * @retval State of bit (1 or 0).
2897 */
2898 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
2899 {
2900 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2901 }
2902
2903 /**
2904 * @brief Indicate the status of Channel 3 destination transaction complete flag.
2905 *
2906 * \rst
2907 * +----------------------+-----------------------------------+
2908 * | Register | BitsName |
2909 * +======================+===================================+
2910 * | STAT_DST_TRN | STATUS |
2911 * +----------------------+-----------------------------------+
2912 * \endrst
2913 *
2914 * @param DMAx DMAx instance
2915 * @retval State of bit (1 or 0).
2916 */
2917 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
2918 {
2919 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2920 }
2921
2922 /**
2923 * @brief Indicate the status of Channel 4 destination transaction complete flag.
2924 *
2925 * \rst
2926 * +----------------------+-----------------------------------+
2927 * | Register | BitsName |
2928 * +======================+===================================+
2929 * | STAT_DST_TRN | STATUS |
2930 * +----------------------+-----------------------------------+
2931 * \endrst
2932 *
2933 * @param DMAx DMAx instance
2934 * @retval State of bit (1 or 0).
2935 */
2936 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
2937 {
2938 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2939 }
2940
2941 /**
2942 * @brief Indicate the status of Channel 5 destination transaction complete flag.
2943 *
2944 * \rst
2945 * +----------------------+-----------------------------------+
2946 * | Register | BitsName |
2947 * +======================+===================================+
2948 * | STAT_DST_TRN | STATUS |
2949 * +----------------------+-----------------------------------+
2950 * \endrst
2951 *
2952 * @param DMAx DMAx instance
2953 * @retval State of bit (1 or 0).
2954 */
2955 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
2956 {
2957 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
2958 }
2959
2960 /**
2961 * @brief Indicate the status of Channel 6 destination transaction complete flag.
2962 *
2963 * \rst
2964 * +----------------------+-----------------------------------+
2965 * | Register | BitsName |
2966 * +======================+===================================+
2967 * | STAT_DST_TRN | STATUS |
2968 * +----------------------+-----------------------------------+
2969 * \endrst
2970 *
2971 * @param DMAx DMAx instance
2972 * @retval State of bit (1 or 0).
2973 */
2974 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
2975 {
2976 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
2977 }
2978
2979 /**
2980 * @brief Indicate the status of Channel 7 destination transaction complete flag.
2981 *
2982 * \rst
2983 * +----------------------+-----------------------------------+
2984 * | Register | BitsName |
2985 * +======================+===================================+
2986 * | STAT_DST_TRN | STATUS |
2987 * +----------------------+-----------------------------------+
2988 * \endrst
2989 *
2990 * @param DMAx DMAx instance
2991 * @retval State of bit (1 or 0).
2992 */
2993 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
2994 {
2995 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
2996 }
2997
2998 /**
2999 * @brief Indicate the status of DMA Channel error flag.
3000 *
3001 * \rst
3002 * +----------------------+-----------------------------------+
3003 * | Register | BitsName |
3004 * +======================+===================================+
3005 * | STAT_ERR | STATUS |
3006 * +----------------------+-----------------------------------+
3007 * \endrst
3008 *
3009 * @param DMAx DMAx instance
3010 * @param channel This parameter can be one of the following values:
3011 * @arg @ref LL_DMA_CHANNEL_0
3012 * @arg @ref LL_DMA_CHANNEL_1
3013 * @arg @ref LL_DMA_CHANNEL_2
3014 * @arg @ref LL_DMA_CHANNEL_3
3015 * @arg @ref LL_DMA_CHANNEL_4
3016 * @arg @ref LL_DMA_CHANNEL_5
3017 * @arg @ref LL_DMA_CHANNEL_6
3018 * @arg @ref LL_DMA_CHANNEL_7
3019 * @retval State of bit (1 or 0).
3020 */
3021 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
3022 {
3023 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3024 }
3025
3026 /**
3027 * @brief Indicate the status of Channel 0 error flag.
3028 *
3029 * \rst
3030 * +----------------------+-----------------------------------+
3031 * | Register | BitsName |
3032 * +======================+===================================+
3033 * | STAT_ERR | STATUS |
3034 * +----------------------+-----------------------------------+
3035 * \endrst
3036 *
3037 * @param DMAx DMAx instance
3038 * @retval State of bit (1 or 0).
3039 */
3040 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
3041 {
3042 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3043 }
3044
3045 /**
3046 * @brief Indicate the status of Channel 1 error flag.
3047 *
3048 * \rst
3049 * +----------------------+-----------------------------------+
3050 * | Register | BitsName |
3051 * +======================+===================================+
3052 * | STAT_ERR | STATUS |
3053 * +----------------------+-----------------------------------+
3054 * \endrst
3055 *
3056 * @param DMAx DMAx instance
3057 * @retval State of bit (1 or 0).
3058 */
3059 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
3060 {
3061 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3062 }
3063
3064 /**
3065 * @brief Indicate the status of Channel 2 error flag.
3066 *
3067 * \rst
3068 * +----------------------+-----------------------------------+
3069 * | Register | BitsName |
3070 * +======================+===================================+
3071 * | STAT_ERR | STATUS |
3072 * +----------------------+-----------------------------------+
3073 * \endrst
3074 *
3075 * @param DMAx DMAx instance
3076 * @retval State of bit (1 or 0).
3077 */
3078 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
3079 {
3080 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3081 }
3082
3083 /**
3084 * @brief Indicate the status of Channel 3 error flag.
3085 *
3086 * \rst
3087 * +----------------------+-----------------------------------+
3088 * | Register | BitsName |
3089 * +======================+===================================+
3090 * | STAT_ERR | STATUS |
3091 * +----------------------+-----------------------------------+
3092 * \endrst
3093 *
3094 * @param DMAx DMAx instance
3095 * @retval State of bit (1 or 0).
3096 */
3097 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
3098 {
3099 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3100 }
3101
3102 /**
3103 * @brief Indicate the status of Channel 4 error flag.
3104 *
3105 * \rst
3106 * +----------------------+-----------------------------------+
3107 * | Register | BitsName |
3108 * +======================+===================================+
3109 * | STAT_ERR | STATUS |
3110 * +----------------------+-----------------------------------+
3111 * \endrst
3112 *
3113 * @param DMAx DMAx instance
3114 * @retval State of bit (1 or 0).
3115 */
3116 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
3117 {
3118 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3119 }
3120
3121 /**
3122 * @brief Indicate the status of Channel 5 error flag.
3123 *
3124 * \rst
3125 * +----------------------+-----------------------------------+
3126 * | Register | BitsName |
3127 * +======================+===================================+
3128 * | STAT_ERR | STATUS |
3129 * +----------------------+-----------------------------------+
3130 * \endrst
3131 *
3132 * @param DMAx DMAx instance
3133 * @retval State of bit (1 or 0).
3134 */
3135 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
3136 {
3137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3138 }
3139
3140 /**
3141 * @brief Indicate the status of Channel 6 error flag.
3142 *
3143 * \rst
3144 * +----------------------+-----------------------------------+
3145 * | Register | BitsName |
3146 * +======================+===================================+
3147 * | STAT_ERR | STATUS |
3148 * +----------------------+-----------------------------------+
3149 * \endrst
3150 *
3151 * @param DMAx DMAx instance
3152 * @retval State of bit (1 or 0).
3153 */
3154 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
3155 {
3156 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3157 }
3158
3159 /**
3160 * @brief Indicate the status of Channel 7 error flag.
3161 *
3162 * \rst
3163 * +----------------------+-----------------------------------+
3164 * | Register | BitsName |
3165 * +======================+===================================+
3166 * | STAT_ERR | STATUS |
3167 * +----------------------+-----------------------------------+
3168 * \endrst
3169 *
3170 * @param DMAx DMAx instance
3171 * @retval State of bit (1 or 0).
3172 */
3173 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
3174 {
3175 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3176 }
3177
3178 /**
3179 * @brief Clear DMA Channel transfer complete flag.
3180 *
3181 * \rst
3182 * +----------------------+-----------------------------------+
3183 * | Register | BitsName |
3184 * +======================+===================================+
3185 * | CLR_TFR | CLEAR |
3186 * +----------------------+-----------------------------------+
3187 * \endrst
3188 *
3189 * @param DMAx DMAx instance
3190 * @param channel This parameter can be one of the following values:
3191 * @arg @ref LL_DMA_CHANNEL_0
3192 * @arg @ref LL_DMA_CHANNEL_1
3193 * @arg @ref LL_DMA_CHANNEL_2
3194 * @arg @ref LL_DMA_CHANNEL_3
3195 * @arg @ref LL_DMA_CHANNEL_4
3196 * @arg @ref LL_DMA_CHANNEL_5
3197 * @arg @ref LL_DMA_CHANNEL_6
3198 * @arg @ref LL_DMA_CHANNEL_7
3199 * @retval None.
3200 */
3201 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
3202 {
3203 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3204 }
3205
3206 /**
3207 * @brief Clear Channel 0 transfer complete flag.
3208 *
3209 * \rst
3210 * +----------------------+-----------------------------------+
3211 * | Register | BitsName |
3212 * +======================+===================================+
3213 * | CLR_TFR | CLEAR |
3214 * +----------------------+-----------------------------------+
3215 * \endrst
3216 *
3217 * @param DMAx DMAx instance
3218 * @retval None.
3219 */
3220 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
3221 {
3222 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3223 }
3224
3225 /**
3226 * @brief Clear Channel 1 transfer complete flag.
3227 *
3228 * \rst
3229 * +----------------------+-----------------------------------+
3230 * | Register | BitsName |
3231 * +======================+===================================+
3232 * | CLR_TFR | CLEAR |
3233 * +----------------------+-----------------------------------+
3234 * \endrst
3235 *
3236 * @param DMAx DMAx instance
3237 * @retval None.
3238 */
3239 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
3240 {
3241 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3242 }
3243
3244 /**
3245 * @brief Clear Channel 2 transfer complete flag.
3246 *
3247 * \rst
3248 * +----------------------+-----------------------------------+
3249 * | Register | BitsName |
3250 * +======================+===================================+
3251 * | CLR_TFR | CLEAR |
3252 * +----------------------+-----------------------------------+
3253 * \endrst
3254 *
3255 * @param DMAx DMAx instance
3256 * @retval None.
3257 */
3258 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
3259 {
3260 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3261 }
3262
3263 /**
3264 * @brief Clear Channel 3 transfer complete flag.
3265 *
3266 * \rst
3267 * +----------------------+-----------------------------------+
3268 * | Register | BitsName |
3269 * +======================+===================================+
3270 * | CLR_TFR | CLEAR |
3271 * +----------------------+-----------------------------------+
3272 * \endrst
3273 *
3274 * @param DMAx DMAx instance
3275 * @retval None.
3276 */
3277 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
3278 {
3279 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3280 }
3281
3282 /**
3283 * @brief Clear Channel 4 transfer complete flag.
3284 *
3285 * \rst
3286 * +----------------------+-----------------------------------+
3287 * | Register | BitsName |
3288 * +======================+===================================+
3289 * | CLR_TFR | CLEAR |
3290 * +----------------------+-----------------------------------+
3291 * \endrst
3292 *
3293 * @param DMAx DMAx instance
3294 * @retval None.
3295 */
3296 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
3297 {
3298 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3299 }
3300
3301 /**
3302 * @brief Clear Channel 5 transfer complete flag.
3303 *
3304 * \rst
3305 * +----------------------+-----------------------------------+
3306 * | Register | BitsName |
3307 * +======================+===================================+
3308 * | CLR_TFR | CLEAR |
3309 * +----------------------+-----------------------------------+
3310 * \endrst
3311 *
3312 * @param DMAx DMAx instance
3313 * @retval None.
3314 */
3315 __STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
3316 {
3317 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3318 }
3319
3320 /**
3321 * @brief Clear Channel 6 transfer complete flag.
3322 *
3323 * \rst
3324 * +----------------------+-----------------------------------+
3325 * | Register | BitsName |
3326 * +======================+===================================+
3327 * | CLR_TFR | CLEAR |
3328 * +----------------------+-----------------------------------+
3329 * \endrst
3330 *
3331 * @param DMAx DMAx instance
3332 * @retval None.
3333 */
3334 __STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
3335 {
3336 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3337 }
3338
3339 /**
3340 * @brief Clear Channel 7 transfer complete flag.
3341 *
3342 * \rst
3343 * +----------------------+-----------------------------------+
3344 * | Register | BitsName |
3345 * +======================+===================================+
3346 * | CLR_TFR | CLEAR |
3347 * +----------------------+-----------------------------------+
3348 * \endrst
3349 *
3350 * @param DMAx DMAx instance
3351 * @retval None.
3352 */
3353 __STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
3354 {
3355 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3356 }
3357
3358 /**
3359 * @brief Clear DMA Channel block complete flag.
3360 *
3361 * \rst
3362 * +----------------------+-----------------------------------+
3363 * | Register | BitsName |
3364 * +======================+===================================+
3365 * | CLR_BLK | CLEAR |
3366 * +----------------------+-----------------------------------+
3367 * \endrst
3368 *
3369 * @param DMAx DMAx instance
3370 * @param channel This parameter can be one of the following values:
3371 * @arg @ref LL_DMA_CHANNEL_0
3372 * @arg @ref LL_DMA_CHANNEL_1
3373 * @arg @ref LL_DMA_CHANNEL_2
3374 * @arg @ref LL_DMA_CHANNEL_3
3375 * @arg @ref LL_DMA_CHANNEL_4
3376 * @arg @ref LL_DMA_CHANNEL_5
3377 * @arg @ref LL_DMA_CHANNEL_6
3378 * @arg @ref LL_DMA_CHANNEL_7
3379 * @retval None.
3380 */
3381 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
3382 {
3383 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3384 }
3385
3386 /**
3387 * @brief Clear Channel 0 Block Complete flag.
3388 *
3389 * \rst
3390 * +----------------------+-----------------------------------+
3391 * | Register | BitsName |
3392 * +======================+===================================+
3393 * | CLR_BLK | CLEAR |
3394 * +----------------------+-----------------------------------+
3395 * \endrst
3396 *
3397 * @param DMAx DMAx instance
3398 * @retval None.
3399 */
3400 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
3401 {
3402 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3403 }
3404
3405 /**
3406 * @brief Clear Channel 1 Block Complete flag.
3407 *
3408 * \rst
3409 * +----------------------+-----------------------------------+
3410 * | Register | BitsName |
3411 * +======================+===================================+
3412 * | CLR_BLK | CLEAR |
3413 * +----------------------+-----------------------------------+
3414 * \endrst
3415 *
3416 * @param DMAx DMAx instance
3417 * @retval None.
3418 */
3419 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
3420 {
3421 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3422 }
3423
3424 /**
3425 * @brief Clear Channel 2 Block Complete flag.
3426 *
3427 * \rst
3428 * +----------------------+-----------------------------------+
3429 * | Register | BitsName |
3430 * +======================+===================================+
3431 * | CLR_BLK | CLEAR |
3432 * +----------------------+-----------------------------------+
3433 * \endrst
3434 *
3435 * @param DMAx DMAx instance
3436 * @retval None.
3437 */
3438 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
3439 {
3440 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3441 }
3442
3443 /**
3444 * @brief Clear Channel 3 Block Complete flag.
3445 *
3446 * \rst
3447 * +----------------------+-----------------------------------+
3448 * | Register | BitsName |
3449 * +======================+===================================+
3450 * | CLR_BLK | CLEAR |
3451 * +----------------------+-----------------------------------+
3452 * \endrst
3453 *
3454 * @param DMAx DMAx instance
3455 * @retval None.
3456 */
3457 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
3458 {
3459 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3460 }
3461
3462 /**
3463 * @brief Clear Channel 4 Block Complete flag.
3464 *
3465 * \rst
3466 * +----------------------+-----------------------------------+
3467 * | Register | BitsName |
3468 * +======================+===================================+
3469 * | CLR_BLK | CLEAR |
3470 * +----------------------+-----------------------------------+
3471 * \endrst
3472 *
3473 * @param DMAx DMAx instance
3474 * @retval None.
3475 */
3476 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
3477 {
3478 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
3479 }
3480
3481 /**
3482 * @brief Clear Channel 5 Block Complete flag.
3483 *
3484 * \rst
3485 * +----------------------+-----------------------------------+
3486 * | Register | BitsName |
3487 * +======================+===================================+
3488 * | CLR_BLK | CLEAR |
3489 * +----------------------+-----------------------------------+
3490 * \endrst
3491 *
3492 * @param DMAx DMAx instance
3493 * @retval None.
3494 */
3495 __STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
3496 {
3497 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
3498 }
3499
3500 /**
3501 * @brief Clear Channel 6 Block Cmplete flag.
3502 *
3503 * \rst
3504 * +----------------------+-----------------------------------+
3505 * | Register | BitsName |
3506 * +======================+===================================+
3507 * | CLR_BLK | CLEAR |
3508 * +----------------------+-----------------------------------+
3509 * \endrst
3510 *
3511 * @param DMAx DMAx instance
3512 * @retval None.
3513 */
3514 __STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
3515 {
3516 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
3517 }
3518
3519 /**
3520 * @brief Clear Channel 7 Block Complete flag.
3521 *
3522 * \rst
3523 * +----------------------+-----------------------------------+
3524 * | Register | BitsName |
3525 * +======================+===================================+
3526 * | CLR_BLK | CLEAR |
3527 * +----------------------+-----------------------------------+
3528 * \endrst
3529 *
3530 * @param DMAx DMAx instance
3531 * @retval None.
3532 */
3533 __STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
3534 {
3535 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
3536 }
3537
3538 /**
3539 * @brief Clear DMA Channel source transaction Complete flag.
3540 *
3541 * \rst
3542 * +----------------------+-----------------------------------+
3543 * | Register | BitsName |
3544 * +======================+===================================+
3545 * | CLR_SRC_TRN | CLEAR |
3546 * +----------------------+-----------------------------------+
3547 * \endrst
3548 *
3549 * @param DMAx DMAx instance
3550 * @param channel This parameter can be one of the following values:
3551 * @arg @ref LL_DMA_CHANNEL_0
3552 * @arg @ref LL_DMA_CHANNEL_1
3553 * @arg @ref LL_DMA_CHANNEL_2
3554 * @arg @ref LL_DMA_CHANNEL_3
3555 * @arg @ref LL_DMA_CHANNEL_4
3556 * @arg @ref LL_DMA_CHANNEL_5
3557 * @arg @ref LL_DMA_CHANNEL_6
3558 * @arg @ref LL_DMA_CHANNEL_7
3559 * @retval None.
3560 */
3561 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
3562 {
3563 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
3564 }
3565
3566 /**
3567 * @brief Clear Channel 0 source transaction Complete flag.
3568 *
3569 * \rst
3570 * +----------------------+-----------------------------------+
3571 * | Register | BitsName |
3572 * +======================+===================================+
3573 * | CLR_SRC_TRN | CLEAR |
3574 * +----------------------+-----------------------------------+
3575 * \endrst
3576 *
3577 * @param DMAx DMAx instance
3578 * @retval None.
3579 */
3580 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
3581 {
3582 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
3583 }
3584
3585 /**
3586 * @brief Clear Channel 1 source transaction Complete flag.
3587 *
3588 * \rst
3589 * +----------------------+-----------------------------------+
3590 * | Register | BitsName |
3591 * +======================+===================================+
3592 * | CLR_SRC_TRN | CLEAR |
3593 * +----------------------+-----------------------------------+
3594 * \endrst
3595 *
3596 * @param DMAx DMAx instance
3597 * @retval None.
3598 */
3599 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
3600 {
3601 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
3602 }
3603
3604 /**
3605 * @brief Clear Channel 2 source transaction Complete flag.
3606 *
3607 * \rst
3608 * +----------------------+-----------------------------------+
3609 * | Register | BitsName |
3610 * +======================+===================================+
3611 * | CLR_SRC_TRN | CLEAR |
3612 * +----------------------+-----------------------------------+
3613 * \endrst
3614 *
3615 * @param DMAx DMAx instance
3616 * @retval None.
3617 */
3618 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
3619 {
3620 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
3621 }
3622
3623 /**
3624 * @brief Clear Channel 3 source transaction Complete flag.
3625 *
3626 * \rst
3627 * +----------------------+-----------------------------------+
3628 * | Register | BitsName |
3629 * +======================+===================================+
3630 * | CLR_SRC_TRN | CLEAR |
3631 * +----------------------+-----------------------------------+
3632 * \endrst
3633 *
3634 * @param DMAx DMAx instance
3635 * @retval None.
3636 */
3637 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
3638 {
3639 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
3640 }
3641
3642 /**
3643 * @brief Clear Channel 4 source transaction Complete flag.
3644 *
3645 * \rst
3646 * +----------------------+-----------------------------------+
3647 * | Register | BitsName |
3648 * +======================+===================================+
3649 * | CLR_SRC_TRN | CLEAR |
3650 * +----------------------+-----------------------------------+
3651 * \endrst
3652 *
3653 * @param DMAx DMAx instance
3654 * @retval None.
3655 */
3656 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
3657 {
3658 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
3659 }
3660
3661 /**
3662 * @brief Clear Channel 5 source transaction Complete flag.
3663 *
3664 * \rst
3665 * +----------------------+-----------------------------------+
3666 * | Register | BitsName |
3667 * +======================+===================================+
3668 * | CLR_SRC_TRN | CLEAR |
3669 * +----------------------+-----------------------------------+
3670 * \endrst
3671 *
3672 * @param DMAx DMAx instance
3673 * @retval None.
3674 */
3675 __STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
3676 {
3677 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
3678 }
3679
3680 /**
3681 * @brief Clear Channel 6 source transaction Complete flag.
3682 *
3683 * \rst
3684 * +----------------------+-----------------------------------+
3685 * | Register | BitsName |
3686 * +======================+===================================+
3687 * | CLR_SRC_TRN | CLEAR |
3688 * +----------------------+-----------------------------------+
3689 * \endrst
3690 *
3691 * @param DMAx DMAx instance
3692 * @retval None.
3693 */
3694 __STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
3695 {
3696 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
3697 }
3698
3699 /**
3700 * @brief Clear Channel 7 source transaction Complete flag.
3701 *
3702 * \rst
3703 * +----------------------+-----------------------------------+
3704 * | Register | BitsName |
3705 * +======================+===================================+
3706 * | CLR_SRC_TRN | CLEAR |
3707 * +----------------------+-----------------------------------+
3708 * \endrst
3709 *
3710 * @param DMAx DMAx instance
3711 * @retval None.
3712 */
3713 __STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
3714 {
3715 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
3716 }
3717
3718 /**
3719 * @brief Clear DMA Channel destination transaction Complete flag.
3720 *
3721 * \rst
3722 * +----------------------+-----------------------------------+
3723 * | Register | BitsName |
3724 * +======================+===================================+
3725 * | CLR_DST_TRN | CLEAR |
3726 * +----------------------+-----------------------------------+
3727 * \endrst
3728 *
3729 * @param DMAx DMAx instance
3730 * @param channel This parameter can be one of the following values:
3731 * @arg @ref LL_DMA_CHANNEL_0
3732 * @arg @ref LL_DMA_CHANNEL_1
3733 * @arg @ref LL_DMA_CHANNEL_2
3734 * @arg @ref LL_DMA_CHANNEL_3
3735 * @arg @ref LL_DMA_CHANNEL_4
3736 * @arg @ref LL_DMA_CHANNEL_5
3737 * @arg @ref LL_DMA_CHANNEL_6
3738 * @arg @ref LL_DMA_CHANNEL_7
3739 * @retval None.
3740 */
3741 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
3742 {
3743 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
3744 }
3745
3746 /**
3747 * @brief Clear Channel 0 destination transaction Complete status.
3748 *
3749 * \rst
3750 * +----------------------+-----------------------------------+
3751 * | Register | BitsName |
3752 * +======================+===================================+
3753 * | CLR_DST_TRN | CLEAR |
3754 * +----------------------+-----------------------------------+
3755 * \endrst
3756 *
3757 * @param DMAx DMAx instance
3758 * @retval None.
3759 */
3760 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
3761 {
3762 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
3763 }
3764
3765 /**
3766 * @brief Clear Channel 1 destination transaction Complete flag.
3767 *
3768 * \rst
3769 * +----------------------+-----------------------------------+
3770 * | Register | BitsName |
3771 * +======================+===================================+
3772 * | CLR_DST_TRN | CLEAR |
3773 * +----------------------+-----------------------------------+
3774 * \endrst
3775 *
3776 * @param DMAx DMAx instance
3777 * @retval None.
3778 */
3779 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
3780 {
3781 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
3782 }
3783
3784 /**
3785 * @brief Clear Channel 2 destination transaction Complete flag.
3786 *
3787 * \rst
3788 * +----------------------+-----------------------------------+
3789 * | Register | BitsName |
3790 * +======================+===================================+
3791 * | CLR_DST_TRN | CLEAR |
3792 * +----------------------+-----------------------------------+
3793 * \endrst
3794 *
3795 * @param DMAx DMAx instance
3796 * @retval None.
3797 */
3798 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
3799 {
3800 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
3801 }
3802
3803 /**
3804 * @brief Clear Channel 3 destination transaction Complete flag.
3805 *
3806 * \rst
3807 * +----------------------+-----------------------------------+
3808 * | Register | BitsName |
3809 * +======================+===================================+
3810 * | CLR_DST_TRN | CLEAR |
3811 * +----------------------+-----------------------------------+
3812 * \endrst
3813 *
3814 * @param DMAx DMAx instance
3815 * @retval None.
3816 */
3817 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
3818 {
3819 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
3820 }
3821
3822 /**
3823 * @brief Clear Channel 4 destination transaction Complete flag.
3824 *
3825 * \rst
3826 * +----------------------+-----------------------------------+
3827 * | Register | BitsName |
3828 * +======================+===================================+
3829 * | CLR_DST_TRN | CLEAR |
3830 * +----------------------+-----------------------------------+
3831 * \endrst
3832 *
3833 * @param DMAx DMAx instance
3834 * @retval None.
3835 */
3836 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
3837 {
3838 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
3839 }
3840
3841 /**
3842 * @brief Clear Channel 5 destination transaction Complete flag.
3843 *
3844 * \rst
3845 * +----------------------+-----------------------------------+
3846 * | Register | BitsName |
3847 * +======================+===================================+
3848 * | CLR_DST_TRN | CLEAR |
3849 * +----------------------+-----------------------------------+
3850 * \endrst
3851 *
3852 * @param DMAx DMAx instance
3853 * @retval None.
3854 */
3855 __STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
3856 {
3857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
3858 }
3859
3860 /**
3861 * @brief Clear Channel 6 destination transaction Complete flag.
3862 *
3863 * \rst
3864 * +----------------------+-----------------------------------+
3865 * | Register | BitsName |
3866 * +======================+===================================+
3867 * | CLR_DST_TRN | CLEAR |
3868 * +----------------------+-----------------------------------+
3869 * \endrst
3870 *
3871 * @param DMAx DMAx instance
3872 * @retval None.
3873 */
3874 __STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
3875 {
3876 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
3877 }
3878
3879 /**
3880 * @brief Clear Channel 7 destination transaction Complete flag.
3881 *
3882 * \rst
3883 * +----------------------+-----------------------------------+
3884 * | Register | BitsName |
3885 * +======================+===================================+
3886 * | CLR_DST_TRN | CLEAR |
3887 * +----------------------+-----------------------------------+
3888 * \endrst
3889 *
3890 * @param DMAx DMAx instance
3891 * @retval None.
3892 */
3893 __STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
3894 {
3895 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
3896 }
3897
3898 /**
3899 * @brief Clear DMA Channel error flag.
3900 *
3901 * \rst
3902 * +----------------------+-----------------------------------+
3903 * | Register | BitsName |
3904 * +======================+===================================+
3905 * | CLR_ERR | CLEAR |
3906 * +----------------------+-----------------------------------+
3907 * \endrst
3908 *
3909 * @param DMAx DMAx instance
3910 * @param channel This parameter can be one of the following values:
3911 * @arg @ref LL_DMA_CHANNEL_0
3912 * @arg @ref LL_DMA_CHANNEL_1
3913 * @arg @ref LL_DMA_CHANNEL_2
3914 * @arg @ref LL_DMA_CHANNEL_3
3915 * @arg @ref LL_DMA_CHANNEL_4
3916 * @arg @ref LL_DMA_CHANNEL_5
3917 * @arg @ref LL_DMA_CHANNEL_6
3918 * @arg @ref LL_DMA_CHANNEL_7
3919 * @retval None.
3920 */
3921 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
3922 {
3923 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
3924 }
3925
3926 /**
3927 * @brief Clear Channel 0 error flag.
3928 *
3929 * \rst
3930 * +----------------------+-----------------------------------+
3931 * | Register | BitsName |
3932 * +======================+===================================+
3933 * | CLR_ERR | CLEAR |
3934 * +----------------------+-----------------------------------+
3935 * \endrst
3936 *
3937 * @param DMAx DMAx instance
3938 * @retval None.
3939 */
3940 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
3941 {
3942 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
3943 }
3944
3945 /**
3946 * @brief Clear Channel 1 error flag.
3947 *
3948 * \rst
3949 * +----------------------+-----------------------------------+
3950 * | Register | BitsName |
3951 * +======================+===================================+
3952 * | CLR_ERR | CLEAR |
3953 * +----------------------+-----------------------------------+
3954 * \endrst
3955 *
3956 * @param DMAx DMAx instance
3957 * @retval None.
3958 */
3959 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
3960 {
3961 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
3962 }
3963
3964 /**
3965 * @brief Clear Channel 2 error flag.
3966 *
3967 * \rst
3968 * +----------------------+-----------------------------------+
3969 * | Register | BitsName |
3970 * +======================+===================================+
3971 * | CLR_ERR | CLEAR |
3972 * +----------------------+-----------------------------------+
3973 * \endrst
3974 *
3975 * @param DMAx DMAx instance
3976 * @retval None.
3977 */
3978 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
3979 {
3980 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3981 }
3982
3983 /**
3984 * @brief Clear Channel 3 error flag.
3985 *
3986 * \rst
3987 * +----------------------+-----------------------------------+
3988 * | Register | BitsName |
3989 * +======================+===================================+
3990 * | CLR_ERR | CLEAR |
3991 * +----------------------+-----------------------------------+
3992 * \endrst
3993 *
3994 * @param DMAx DMAx instance
3995 * @retval None.
3996 */
3997 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
3998 {
3999 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4000 }
4001
4002 /**
4003 * @brief Clear Channel 4 error flag.
4004 *
4005 * \rst
4006 * +----------------------+-----------------------------------+
4007 * | Register | BitsName |
4008 * +======================+===================================+
4009 * | CLR_ERR | CLEAR |
4010 * +----------------------+-----------------------------------+
4011 * \endrst
4012 *
4013 * @param DMAx DMAx instance
4014 * @retval None.
4015 */
4016 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
4017 {
4018 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4019 }
4020
4021 /**
4022 * @brief Clear Channel 5 error flag.
4023 *
4024 * \rst
4025 * +----------------------+-----------------------------------+
4026 * | Register | BitsName |
4027 * +======================+===================================+
4028 * | CLR_ERR | CLEAR |
4029 * +----------------------+-----------------------------------+
4030 * \endrst
4031 *
4032 * @param DMAx DMAx instance
4033 * @retval None.
4034 */
4035 __STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
4036 {
4037 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4038 }
4039
4040 /**
4041 * @brief Clear Channel 6 error flag.
4042 *
4043 * \rst
4044 * +----------------------+-----------------------------------+
4045 * | Register | BitsName |
4046 * +======================+===================================+
4047 * | CLR_ERR | CLEAR |
4048 * +----------------------+-----------------------------------+
4049 * \endrst
4050 *
4051 * @param DMAx DMAx instance
4052 * @retval None.
4053 */
4054 __STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
4055 {
4056 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4057 }
4058
4059 /**
4060 * @brief Clear Channel 7 error flag.
4061 *
4062 * \rst
4063 * +----------------------+-----------------------------------+
4064 * | Register | BitsName |
4065 * +======================+===================================+
4066 * | CLR_ERR | CLEAR |
4067 * +----------------------+-----------------------------------+
4068 * \endrst
4069 *
4070 * @param DMAx DMAx instance
4071 * @retval None.
4072 */
4073 __STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
4074 {
4075 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4076 }
4077
4078 /** @} */
4079
4080 /** @defgroup DMA_LL_EF_IT_Management IT_Management
4081 * @{
4082 */
4083
4084 /**
4085 * @brief Enable Transfer Complete interrupt.
4086 *
4087 * \rst
4088 * +----------------------+-----------------------------------+
4089 * | Register | BitsName |
4090 * +======================+===================================+
4091 * | MASK_TFR | TFR_WE&TFR |
4092 * +----------------------+-----------------------------------+
4093 * \endrst
4094 *
4095 * @param DMAx DMAx instance
4096 * @param channel This parameter can be one of the following values:
4097 * @arg @ref LL_DMA_CHANNEL_0
4098 * @arg @ref LL_DMA_CHANNEL_1
4099 * @arg @ref LL_DMA_CHANNEL_2
4100 * @arg @ref LL_DMA_CHANNEL_3
4101 * @arg @ref LL_DMA_CHANNEL_4
4102 * @arg @ref LL_DMA_CHANNEL_5
4103 * @arg @ref LL_DMA_CHANNEL_6
4104 * @arg @ref LL_DMA_CHANNEL_7
4105 * @retval None
4106 */
4107 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4108 {
4109 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4110 }
4111
4112 /**
4113 * @brief Enable Block Complete interrupt.
4114 *
4115 * \rst
4116 * +----------------------+-----------------------------------+
4117 * | Register | BitsName |
4118 * +======================+===================================+
4119 * | MASK_BLK | BLK_WE&BLK |
4120 * +----------------------+-----------------------------------+
4121 * \endrst
4122 *
4123 * @param DMAx DMAx instance
4124 * @param channel This parameter can be one of the following values:
4125 * @arg @ref LL_DMA_CHANNEL_0
4126 * @arg @ref LL_DMA_CHANNEL_1
4127 * @arg @ref LL_DMA_CHANNEL_2
4128 * @arg @ref LL_DMA_CHANNEL_3
4129 * @arg @ref LL_DMA_CHANNEL_4
4130 * @arg @ref LL_DMA_CHANNEL_5
4131 * @arg @ref LL_DMA_CHANNEL_6
4132 * @arg @ref LL_DMA_CHANNEL_7
4133 * @retval None
4134 */
4135 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4136 {
4137 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4138 }
4139
4140 /**
4141 * @brief Enable source transaction Complete interrupt.
4142 *
4143 * \rst
4144 * +----------------------+-----------------------------------+
4145 * | Register | BitsName |
4146 * +======================+===================================+
4147 * | MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN |
4148 * +----------------------+-----------------------------------+
4149 * \endrst
4150 *
4151 * @param DMAx DMAx instance
4152 * @param channel This parameter can be one of the following values:
4153 * @arg @ref LL_DMA_CHANNEL_0
4154 * @arg @ref LL_DMA_CHANNEL_1
4155 * @arg @ref LL_DMA_CHANNEL_2
4156 * @arg @ref LL_DMA_CHANNEL_3
4157 * @arg @ref LL_DMA_CHANNEL_4
4158 * @arg @ref LL_DMA_CHANNEL_5
4159 * @arg @ref LL_DMA_CHANNEL_6
4160 * @arg @ref LL_DMA_CHANNEL_7
4161 * @retval None
4162 */
4163 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4164 {
4165 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4166 }
4167
4168 /**
4169 * @brief Enable destination transaction Complete interrupt.
4170 *
4171 * \rst
4172 * +----------------------+-----------------------------------+
4173 * | Register | BitsName |
4174 * +======================+===================================+
4175 * | MASK_DST_TRN | DST_TRN_WE&DST_TRN |
4176 * +----------------------+-----------------------------------+
4177 * \endrst
4178 *
4179 * @param DMAx DMAx instance
4180 * @param channel This parameter can be one of the following values:
4181 * @arg @ref LL_DMA_CHANNEL_0
4182 * @arg @ref LL_DMA_CHANNEL_1
4183 * @arg @ref LL_DMA_CHANNEL_2
4184 * @arg @ref LL_DMA_CHANNEL_3
4185 * @arg @ref LL_DMA_CHANNEL_4
4186 * @arg @ref LL_DMA_CHANNEL_5
4187 * @arg @ref LL_DMA_CHANNEL_6
4188 * @arg @ref LL_DMA_CHANNEL_7
4189 * @retval None
4190 */
4191 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4192 {
4193 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4194 }
4195
4196 /**
4197 * @brief Enable error interrupt.
4198 *
4199 * \rst
4200 * +----------------------+-----------------------------------+
4201 * | Register | BitsName |
4202 * +======================+===================================+
4203 * | MASK_ERR | ERR_WE&ERR |
4204 * +----------------------+-----------------------------------+
4205 * \endrst
4206 *
4207 * @param DMAx DMAx instance
4208 * @param channel This parameter can be one of the following values:
4209 * @arg @ref LL_DMA_CHANNEL_0
4210 * @arg @ref LL_DMA_CHANNEL_1
4211 * @arg @ref LL_DMA_CHANNEL_2
4212 * @arg @ref LL_DMA_CHANNEL_3
4213 * @arg @ref LL_DMA_CHANNEL_4
4214 * @arg @ref LL_DMA_CHANNEL_5
4215 * @arg @ref LL_DMA_CHANNEL_6
4216 * @arg @ref LL_DMA_CHANNEL_7
4217 * @retval None
4218 */
4219 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4220 {
4221 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4222 }
4223
4224 /**
4225 * @brief Disable Transfer Complete interrupt.
4226 *
4227 * \rst
4228 * +----------------------+-----------------------------------+
4229 * | Register | BitsName |
4230 * +======================+===================================+
4231 * | MASK_TFR | TFR_WE&TFR |
4232 * +----------------------+-----------------------------------+
4233 * \endrst
4234 *
4235 * @param DMAx DMAx instance
4236 * @param channel This parameter can be one of the following values:
4237 * @arg @ref LL_DMA_CHANNEL_0
4238 * @arg @ref LL_DMA_CHANNEL_1
4239 * @arg @ref LL_DMA_CHANNEL_2
4240 * @arg @ref LL_DMA_CHANNEL_3
4241 * @arg @ref LL_DMA_CHANNEL_4
4242 * @arg @ref LL_DMA_CHANNEL_5
4243 * @arg @ref LL_DMA_CHANNEL_6
4244 * @arg @ref LL_DMA_CHANNEL_7
4245 * @retval None
4246 */
4247 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4248 {
4249 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4250 }
4251
4252 /**
4253 * @brief Disable Block Complete interrupt.
4254 *
4255 * \rst
4256 * +----------------------+-----------------------------------+
4257 * | Register | BitsName |
4258 * +======================+===================================+
4259 * | MASK_BLK | BLK_WE&BLK |
4260 * +----------------------+-----------------------------------+
4261 * \endrst
4262 *
4263 * @param DMAx DMAx instance
4264 * @param channel This parameter can be one of the following values:
4265 * @arg @ref LL_DMA_CHANNEL_0
4266 * @arg @ref LL_DMA_CHANNEL_1
4267 * @arg @ref LL_DMA_CHANNEL_2
4268 * @arg @ref LL_DMA_CHANNEL_3
4269 * @arg @ref LL_DMA_CHANNEL_4
4270 * @arg @ref LL_DMA_CHANNEL_5
4271 * @arg @ref LL_DMA_CHANNEL_6
4272 * @arg @ref LL_DMA_CHANNEL_7
4273 * @retval None
4274 */
4275 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4276 {
4277 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4278 }
4279
4280 /**
4281 * @brief Disable source transaction Complete interrupt.
4282 *
4283 * \rst
4284 * +----------------------+-----------------------------------+
4285 * | Register | BitsName |
4286 * +======================+===================================+
4287 * | MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN |
4288 * +----------------------+-----------------------------------+
4289 * \endrst
4290 *
4291 * @param DMAx DMAx instance
4292 * @param channel This parameter can be one of the following values:
4293 * @arg @ref LL_DMA_CHANNEL_0
4294 * @arg @ref LL_DMA_CHANNEL_1
4295 * @arg @ref LL_DMA_CHANNEL_2
4296 * @arg @ref LL_DMA_CHANNEL_3
4297 * @arg @ref LL_DMA_CHANNEL_4
4298 * @arg @ref LL_DMA_CHANNEL_5
4299 * @arg @ref LL_DMA_CHANNEL_6
4300 * @arg @ref LL_DMA_CHANNEL_7
4301 * @retval None
4302 */
4303 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4304 {
4305 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4306 }
4307
4308 /**
4309 * @brief Disable destination transaction Complete interrupt.
4310 *
4311 * \rst
4312 * +----------------------+-----------------------------------+
4313 * | Register | BitsName |
4314 * +======================+===================================+
4315 * | MASK_DST_TRN | DST_TRN_WE&DST_TRN |
4316 * +----------------------+-----------------------------------+
4317 * \endrst
4318 *
4319 * @param DMAx DMAx instance
4320 * @param channel This parameter can be one of the following values:
4321 * @arg @ref LL_DMA_CHANNEL_0
4322 * @arg @ref LL_DMA_CHANNEL_1
4323 * @arg @ref LL_DMA_CHANNEL_2
4324 * @arg @ref LL_DMA_CHANNEL_3
4325 * @arg @ref LL_DMA_CHANNEL_4
4326 * @arg @ref LL_DMA_CHANNEL_5
4327 * @arg @ref LL_DMA_CHANNEL_6
4328 * @arg @ref LL_DMA_CHANNEL_7
4329 * @retval None
4330 */
4331 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4332 {
4333 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4334 }
4335
4336 /**
4337 * @brief Disable error interrupt.
4338 *
4339 * \rst
4340 * +----------------------+-----------------------------------+
4341 * | Register | BitsName |
4342 * +======================+===================================+
4343 * | MASK_ERR | ERR_WE&ERR |
4344 * +----------------------+-----------------------------------+
4345 * \endrst
4346 *
4347 * @param DMAx DMAx instance
4348 * @param channel This parameter can be one of the following values:
4349 * @arg @ref LL_DMA_CHANNEL_0
4350 * @arg @ref LL_DMA_CHANNEL_1
4351 * @arg @ref LL_DMA_CHANNEL_2
4352 * @arg @ref LL_DMA_CHANNEL_3
4353 * @arg @ref LL_DMA_CHANNEL_4
4354 * @arg @ref LL_DMA_CHANNEL_5
4355 * @arg @ref LL_DMA_CHANNEL_6
4356 * @arg @ref LL_DMA_CHANNEL_7
4357 * @retval None
4358 */
4359 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
4360 {
4361 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4362 }
4363
4364 /**
4365 * @brief Check if DMA Transfer interrupt is enabled or disabled.
4366 *
4367 * \rst
4368 * +----------------------+-----------------------------------+
4369 * | Register | BitsName |
4370 * +======================+===================================+
4371 * | MASK_TFR | TFR |
4372 * +----------------------+-----------------------------------+
4373 * \endrst
4374 *
4375 * @param DMAx DMA instance.
4376 * @param channel This parameter can be one of the following values:
4377 * @arg @ref LL_DMA_CHANNEL_0
4378 * @arg @ref LL_DMA_CHANNEL_1
4379 * @arg @ref LL_DMA_CHANNEL_2
4380 * @arg @ref LL_DMA_CHANNEL_3
4381 * @arg @ref LL_DMA_CHANNEL_4
4382 * @arg @ref LL_DMA_CHANNEL_5
4383 * @arg @ref LL_DMA_CHANNEL_6
4384 * @arg @ref LL_DMA_CHANNEL_7
4385 * @retval State of bit (1 or 0).
4386 */
4387 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
4388 {
4389 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4390 }
4391
4392 /**
4393 * @brief Check if DMA block interrupt is enabled or disabled.
4394 *
4395 * \rst
4396 * +----------------------+-----------------------------------+
4397 * | Register | BitsName |
4398 * +======================+===================================+
4399 * | MASK_BLK | BLK_WE&BLK |
4400 * +----------------------+-----------------------------------+
4401 * \endrst
4402 *
4403 * @param DMAx DMA instance.
4404 * @param channel This parameter can be one of the following values:
4405 * @arg @ref LL_DMA_CHANNEL_0
4406 * @arg @ref LL_DMA_CHANNEL_1
4407 * @arg @ref LL_DMA_CHANNEL_2
4408 * @arg @ref LL_DMA_CHANNEL_3
4409 * @arg @ref LL_DMA_CHANNEL_4
4410 * @arg @ref LL_DMA_CHANNEL_5
4411 * @arg @ref LL_DMA_CHANNEL_6
4412 * @arg @ref LL_DMA_CHANNEL_7
4413 * @retval State of bit (1 or 0).
4414 */
4415 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
4416 {
4417 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4418 }
4419
4420 /**
4421 * @brief Check if DMA source transaction interrupt is enabled or disabled.
4422 *
4423 * \rst
4424 * +----------------------+-----------------------------------+
4425 * | Register | BitsName |
4426 * +======================+===================================+
4427 * | MASK_SRC_TRN | SRC_TRN |
4428 * +----------------------+-----------------------------------+
4429 * \endrst
4430 *
4431 * @param DMAx DMA instance.
4432 * @param channel This parameter can be one of the following values:
4433 * @arg @ref LL_DMA_CHANNEL_0
4434 * @arg @ref LL_DMA_CHANNEL_1
4435 * @arg @ref LL_DMA_CHANNEL_2
4436 * @arg @ref LL_DMA_CHANNEL_3
4437 * @arg @ref LL_DMA_CHANNEL_4
4438 * @arg @ref LL_DMA_CHANNEL_5
4439 * @arg @ref LL_DMA_CHANNEL_6
4440 * @arg @ref LL_DMA_CHANNEL_7
4441 * @retval State of bit (1 or 0).
4442 */
4443 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
4444 {
4445 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4446 }
4447
4448 /**
4449 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
4450 *
4451 * \rst
4452 * +----------------------+-----------------------------------+
4453 * | Register | BitsName |
4454 * +======================+===================================+
4455 * | MASK_DST_TRN | DST_TRN |
4456 * +----------------------+-----------------------------------+
4457 * \endrst
4458 *
4459 * @param DMAx DMA instance.
4460 * @param channel This parameter can be one of the following values:
4461 * @arg @ref LL_DMA_CHANNEL_0
4462 * @arg @ref LL_DMA_CHANNEL_1
4463 * @arg @ref LL_DMA_CHANNEL_2
4464 * @arg @ref LL_DMA_CHANNEL_3
4465 * @arg @ref LL_DMA_CHANNEL_4
4466 * @arg @ref LL_DMA_CHANNEL_5
4467 * @arg @ref LL_DMA_CHANNEL_6
4468 * @arg @ref LL_DMA_CHANNEL_7
4469 * @retval State of bit (1 or 0).
4470 */
4471 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
4472 {
4473 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4474 }
4475
4476 /**
4477 * @brief Check if DMA error interrupt is enabled or disabled.
4478 *
4479 * \rst
4480 * +----------------------+-----------------------------------+
4481 * | Register | BitsName |
4482 * +======================+===================================+
4483 * | MASK_ERR | ERR |
4484 * +----------------------+-----------------------------------+
4485 * \endrst
4486 *
4487 * @param DMAx DMA instance.
4488 * @param channel This parameter can be one of the following values:
4489 * @arg @ref LL_DMA_CHANNEL_0
4490 * @arg @ref LL_DMA_CHANNEL_1
4491 * @arg @ref LL_DMA_CHANNEL_2
4492 * @arg @ref LL_DMA_CHANNEL_3
4493 * @arg @ref LL_DMA_CHANNEL_4
4494 * @arg @ref LL_DMA_CHANNEL_5
4495 * @arg @ref LL_DMA_CHANNEL_6
4496 * @arg @ref LL_DMA_CHANNEL_7
4497 * @retval State of bit (1 or 0).
4498 */
4499 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
4500 {
4501 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4502 }
4503
4504 /**
4505 * @brief Enable DMA channel interrupt.
4506 *
4507 * \rst
4508 * +----------------------+-----------------------------------+
4509 * | Register | BitsName |
4510 * +======================+===================================+
4511 * | CTLL | INI_EN |
4512 * +----------------------+-----------------------------------+
4513 * \endrst
4514 *
4515 * @param DMAx DMA instance.
4516 * @param channel This parameter can be one of the following values:
4517 * @arg @ref LL_DMA_CHANNEL_0
4518 * @arg @ref LL_DMA_CHANNEL_1
4519 * @arg @ref LL_DMA_CHANNEL_2
4520 * @arg @ref LL_DMA_CHANNEL_3
4521 * @arg @ref LL_DMA_CHANNEL_4
4522 * @arg @ref LL_DMA_CHANNEL_5
4523 * @arg @ref LL_DMA_CHANNEL_6
4524 * @arg @ref LL_DMA_CHANNEL_7
4525 * @retval None
4526 */
4527 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
4528 {
4529 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4530 }
4531
4532 /**
4533 * @brief Disable DMA channel interrupt.
4534 *
4535 * \rst
4536 * +----------------------+-----------------------------------+
4537 * | Register | BitsName |
4538 * +======================+===================================+
4539 * | CTLL | INI_EN |
4540 * +----------------------+-----------------------------------+
4541 * \endrst
4542 *
4543 * @param DMAx DMA instance.
4544 * @param channel This parameter can be one of the following values:
4545 * @arg @ref LL_DMA_CHANNEL_0
4546 * @arg @ref LL_DMA_CHANNEL_1
4547 * @arg @ref LL_DMA_CHANNEL_2
4548 * @arg @ref LL_DMA_CHANNEL_3
4549 * @arg @ref LL_DMA_CHANNEL_4
4550 * @arg @ref LL_DMA_CHANNEL_5
4551 * @arg @ref LL_DMA_CHANNEL_6
4552 * @arg @ref LL_DMA_CHANNEL_7
4553 * @retval None
4554 */
4555 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
4556 {
4557 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
4558 }
4559
4560 /** @} */
4561
4562 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
4563 * @{
4564 */
4565
4566 /**
4567 * @brief De-initialize the DMA registers to their default reset values.
4568 * @param DMAx DMAx instance
4569 * @param channel This parameter can be one of the following values:
4570 * @arg @ref LL_DMA_CHANNEL_0
4571 * @arg @ref LL_DMA_CHANNEL_1
4572 * @arg @ref LL_DMA_CHANNEL_2
4573 * @arg @ref LL_DMA_CHANNEL_3
4574 * @arg @ref LL_DMA_CHANNEL_4
4575 * @arg @ref LL_DMA_CHANNEL_5
4576 * @arg @ref LL_DMA_CHANNEL_6
4577 * @arg @ref LL_DMA_CHANNEL_7
4578 * @retval An error_status_t enumeration value:
4579 * - SUCCESS: DMA registers are de-initialized
4580 * - ERROR: DMA registers are not de-initialized
4581 */
4582 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
4583
4584 /**
4585 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
4586 * @param DMAx DMAx instance
4587 * @param channel This parameter can be one of the following values:
4588 * @arg @ref LL_DMA_CHANNEL_0
4589 * @arg @ref LL_DMA_CHANNEL_1
4590 * @arg @ref LL_DMA_CHANNEL_2
4591 * @arg @ref LL_DMA_CHANNEL_3
4592 * @arg @ref LL_DMA_CHANNEL_4
4593 * @arg @ref LL_DMA_CHANNEL_5
4594 * @arg @ref LL_DMA_CHANNEL_6
4595 * @arg @ref LL_DMA_CHANNEL_7
4596 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
4597 * @retval An error_status_t enumeration value:
4598 * - SUCCESS: DMA registers are initialized
4599 * - ERROR: Not applicable
4600 */
4601 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
4602
4603 /**
4604 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
4605 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
4606 * whose fields will be set to default values.
4607 * @retval None
4608 */
4609 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
4610
4611 /** @} */
4612
4613 /** @} */
4614
4615 #endif /* DMA */
4616
4617 #ifdef __cplusplus
4618 }
4619 #endif
4620
4621 #endif /* __GR55xx_LL_DMA_H__ */
4622
4623 /** @} */
4624
4625 /** @} */
4626
4627 /** @} */
ll_dma_clear_flag_err
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3921
ll_dma_get_source_burst_length
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1092
_ll_dma_init::mode
uint32_t mode
Specifies the Single block or Multi-block operation mode.
Definition: gr55xx_ll_dma.h:92
ll_dma_get_mode
__STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
Get DMA mode circular or normal.
Definition: gr55xx_ll_dma.h:777
_ll_dma_init::src_address
uint32_t src_address
Specifies the Source base address for DMA transfer.
Definition: gr55xx_ll_dma.h:78
ll_dma_get_source_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: gr55xx_ll_dma.h:840
ll_dma_get_channel_priority_level
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: gr55xx_ll_dma.h:1228
ll_dma_disable_it_err
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: gr55xx_ll_dma.h:4359
ll_dma_clear_flag_srct3
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3637
ll_dma_is_active_flag_dstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2841
ll_dma_clear_flag_tfr0
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:3220
ll_dma_clear_flag_tfr3
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:3277
ll_dma_clear_flag_blk3
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: gr55xx_ll_dma.h:3457
ll_dma_clear_flag_err7
__STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
Clear Channel 7 error flag.
Definition: gr55xx_ll_dma.h:4073
ll_dma_disable_channel
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: gr55xx_ll_dma.h:454
ll_dma_is_active_flag_tfr4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:2396
ll_dma_is_active_flag_dstt3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2917
ll_dma_clear_flag_dstt3
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3817
ll_dma_is_active_flag_blk0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: gr55xx_ll_dma.h:2500
ll_dma_init
error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
ll_dma_is_active_flag_err0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3040
ll_dma_clear_flag_srct
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3561
ll_dma_disable
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: gr55xx_ll_dma.h:377
ll_dma_is_active_flag_err1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3059
ll_dma_clear_flag_err4
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: gr55xx_ll_dma.h:4016
ll_dma_get_source_width
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: gr55xx_ll_dma.h:966
ll_dma_clear_flag_srct1
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3599
ll_dma_get_source_peripheral
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1662
ll_dma_config_transfer
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: gr55xx_ll_dma.h:642
ll_dma_is_active_flag_srct0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2680
ll_dma_get_destination_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: gr55xx_ll_dma.h:903
ll_dma_set_m2m_dst_address
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1508
ll_dma_deinit
error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
ll_dma_is_empty_fifo
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: gr55xx_ll_dma.h:599
ll_dma_clear_flag_srct4
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3656
ll_dma_disable_it_dstt
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4331
ll_dma_clear_flag_blk1
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: gr55xx_ll_dma.h:3419
ll_dma_clear_flag_tfr
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:3201
ll_dma_disable_it_srct
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4303
ll_dma_set_destination_width
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: gr55xx_ll_dma.h:998
ll_dma_clear_flag_dstt4
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3836
ll_dma_is_enabled_channel
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: gr55xx_ll_dma.h:484
ll_dma_get_m2m_src_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1538
ll_dma_get_destination_burst_length
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1155
ll_dma_clear_flag_blk6
__STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
Clear Channel 6 Block Cmplete flag.
Definition: gr55xx_ll_dma.h:3514
ll_dma_is_active_flag_dstt7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
Indicate the status of Channel 7 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2993
ll_dma_clear_flag_err0
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3940
ll_dma_clear_flag_dstt5
__STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
Clear Channel 5 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3855
ll_dma_clear_flag_err3
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3997
ll_dma_is_enable_it_dstt
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4471
ll_dma_clear_flag_tfr1
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:3239
ll_dma_req_src_burst_transaction
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1850
ll_dma_set_source_peripheral
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1615
ll_dma_set_block_size
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: gr55xx_ll_dma.h:1258
ll_dma_set_source_address
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: gr55xx_ll_dma.h:1361
ll_dma_is_active_flag_rdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: gr55xx_ll_dma.h:2245
ll_dma_is_active_flag_dstt0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2860
ll_dma_get_m2m_dst_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1567
ll_dma_is_active_flag_dstt4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2936
ll_dma_is_active_flag_srct7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
Indicate the status of Channel 7 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2813
ll_dma_config_address
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: gr55xx_ll_dma.h:1326
ll_dma_is_active_flag_tfr5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
Indicate the status of Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:2415
ll_dma_is_active_flag_srct5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
Indicate the status of Channel 5 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2775
ll_dma_req_dst_last_single_transaction
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:2000
ll_dma_disable_it_tfr
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4247
ll_dma_is_active_flag_dstt5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
Indicate the status of Channel 5 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2955
ll_dma_set_destination_increment_mode
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: gr55xx_ll_dma.h:872
ll_dma_is_active_flag_blk1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: gr55xx_ll_dma.h:2519
ll_dma_is_enable_it_blk
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4415
ll_dma_disable_it
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4555
ll_dma_is_active_flag_srct1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2699
_ll_dma_init
LL DMA init Structure definition.
Definition: gr55xx_ll_dma.h:77
ll_dma_clear_flag_dstt6
__STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
Clear Channel 6 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3874
ll_dma_is_active_flag_err3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3097
ll_dma_is_active_flag_err5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
Indicate the status of Channel 5 error flag.
Definition: gr55xx_ll_dma.h:3135
ll_dma_struct_init
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
ll_dma_is_active_flag_tfr1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:2339
ll_dma_get_destination_address
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: gr55xx_ll_dma.h:1446
ll_dma_is_active_flag_err
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3021
ll_dma_req_src_single_transaction
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: gr55xx_ll_dma.h:1821
ll_dma_clear_flag_tfr2
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:3258
ll_dma_is_enable_it_tfr
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4387
ll_dma_is_active_flag_srct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: gr55xx_ll_dma.h:2661
ll_dma_clear_flag_srct0
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3580
ll_dma_is_active_flag_dstt2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2898
ll_dma_is_active_flag_blk2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: gr55xx_ll_dma.h:2538
ll_dma_enable_it_tfr
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:4107
ll_dma_req_dst_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1970
ll_dma_enable_channel
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: gr55xx_ll_dma.h:426
ll_dma_clear_flag_blk7
__STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
Clear Channel 7 Block Complete flag.
Definition: gr55xx_ll_dma.h:3533
ll_dma_set_source_burst_length
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1061
ll_dma_is_active_flag_dstt1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2879
ll_dma_is_active_flag_srct4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2756
ll_dma_is_active_flag_tfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:2301
ll_dma_is_active_flag_srct2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2718
ll_dma_is_active_flag_gsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2095
ll_dma_is_active_flag_err2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3078
ll_dma_is_active_flag_tfr7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
Indicate the status of Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:2453
_ll_dma_init::block_size
uint32_t block_size
Specifies the number of data to transfer, in data unit.
Definition: gr55xx_ll_dma.h:119
ll_dma_get_source_address
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: gr55xx_ll_dma.h:1418
ll_dma_select_handshaking
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: gr55xx_ll_dma.h:1791
ll_dma_is_active_flag_blk7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
Indicate the status of Channel 7 block complete flag.
Definition: gr55xx_ll_dma.h:2633
_ll_dma_init::src_peripheral
uint32_t src_peripheral
Specifies the Source peripheral type.
Definition: gr55xx_ll_dma.h:125
ll_dma_is_active_flag_blk4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: gr55xx_ll_dma.h:2576
ll_dma_clear_flag_tfr5
__STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
Clear Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:3315
ll_dma_set_destination_peripheral
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1710
ll_dma_get_destination_width
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: gr55xx_ll_dma.h:1029
_ll_dma_init::dst_data_width
uint32_t dst_data_width
Specifies the Destination transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:114
ll_dma_is_active_flag_gerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: gr55xx_ll_dma.h:2133
ll_dma_set_source_increment_mode
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: gr55xx_ll_dma.h:809
ll_dma_is_active_flag_gtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: gr55xx_ll_dma.h:2057
ll_dma_set_destination_address
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: gr55xx_ll_dma.h:1390
ll_dma_req_src_last_single_transaction
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:1880
ll_dma_is_active_flag_err7
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
Indicate the status of Channel 7 error flag.
Definition: gr55xx_ll_dma.h:3173
ll_dma_is_active_flag_blk6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
Indicate the status of Channel 6 block complete flag.
Definition: gr55xx_ll_dma.h:2614
ll_dma_clear_flag_err5
__STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
Clear Channel 5 error flag.
Definition: gr55xx_ll_dma.h:4035
ll_dma_resume_channel
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: gr55xx_ll_dma.h:543
ll_dma_clear_flag_dstt0
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: gr55xx_ll_dma.h:3760
_ll_dma_init::src_data_width
uint32_t src_data_width
Specifies the Souce transfer width alignment(byte, half word, word).
Definition: gr55xx_ll_dma.h:109
ll_dma_clear_flag_err2
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3978
ll_dma_set_mode
__STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
Set DMA mode Single block or Multi block.
Definition: gr55xx_ll_dma.h:744
ll_dma_set_m2m_src_address
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1476
ll_dma_is_active_flag_srct6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
Indicate the status of Channel 6 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2794
ll_dma_enable_it_blk
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4135
_ll_dma_init::direction
uint32_t direction
Specifies if the data will be transferred from memory to peripheral, from memory to memory or from pe...
Definition: gr55xx_ll_dma.h:86
ll_dma_clear_flag_tfr6
__STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
Clear Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:3334
ll_dma_clear_flag_dstt
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3741
ll_dma_enable
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: gr55xx_ll_dma.h:354
ll_dma_clear_flag_blk0
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: gr55xx_ll_dma.h:3400
ll_dma_clear_flag_dstt2
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3798
_ll_dma_init::dst_peripheral
uint32_t dst_peripheral
Specifies the Destination peripheral type.
Definition: gr55xx_ll_dma.h:130
ll_dma_disable_it_blk
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:4275
_ll_dma_init::priority
uint32_t priority
Specifies the channel priority level.
Definition: gr55xx_ll_dma.h:135
ll_dma_is_active_flag_err4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: gr55xx_ll_dma.h:3116
ll_dma_is_active_flag_gdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:2114
ll_dma_req_dst_single_transaction
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: gr55xx_ll_dma.h:1941
ll_dma_get_data_transfer_direction
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:709
ll_dma_enable_it_err
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: gr55xx_ll_dma.h:4219
ll_dma_req_dst_last_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:2031
ll_dma_clear_flag_dstt7
__STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
Clear Channel 7 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3893
ll_dma_is_active_flag_err6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
Indicate the status of Channel 6 error flag.
Definition: gr55xx_ll_dma.h:3154
ll_dma_clear_flag_tfr7
__STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
Clear Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:3353
ll_dma_is_active_flag_rerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: gr55xx_ll_dma.h:2273
_ll_dma_init::dst_increment_mode
uint32_t dst_increment_mode
Specifies whether the Destination address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:104
ll_dma_clear_flag_tfr4
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:3296
ll_dma_clear_flag_srct2
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3618
ll_dma_is_enable_it_srct
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4443
_ll_dma_init::dst_address
uint32_t dst_address
Specifies the Destination base address for DMA transfer.
Definition: gr55xx_ll_dma.h:82
ll_dma_clear_flag_srct6
__STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
Clear Channel 6 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3694
ll_dma_clear_flag_err6
__STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
Clear Channel 6 error flag.
Definition: gr55xx_ll_dma.h:4054
ll_dma_clear_flag_srct5
__STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
Clear Channel 5 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3675
ll_dma_is_active_flag_tfr2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:2358
ll_dma_is_active_flag_tfr6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
Indicate the status of Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:2434
ll_dma_is_enable
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: gr55xx_ll_dma.h:396
ll_dma_get_destination_peripheral
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1757
ll_dma_clear_flag_blk2
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: gr55xx_ll_dma.h:3438
ll_dma_set_destination_burst_length
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1124
ll_dma_req_src_last_burst_transaction
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1911
ll_dma_enable_it_dstt
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4191
_ll_dma_init::src_increment_mode
uint32_t src_increment_mode
Specifies whether the Source address is incremented or decrement or not.
Definition: gr55xx_ll_dma.h:99
ll_dma_set_data_transfer_direction
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:677
ll_dma_is_active_flag_tfr0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:2320
ll_dma_clear_flag_srct7
__STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
Clear Channel 7 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3713
ll_dma_is_active_flag_tfr3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:2377
ll_dma_is_suspended
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: gr55xx_ll_dma.h:571
ll_dma_init_t
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
ll_dma_clear_flag_blk5
__STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
Clear Channel 5 Block Complete flag.
Definition: gr55xx_ll_dma.h:3495
ll_dma_set_source_width
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: gr55xx_ll_dma.h:935
ll_dma_is_active_flag_rsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: gr55xx_ll_dma.h:2217
ll_dma_clear_flag_blk4
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: gr55xx_ll_dma.h:3476
ll_dma_is_active_flag_blk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:2481
ll_dma_is_active_flag_rtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: gr55xx_ll_dma.h:2161
ll_dma_is_active_flag_dstt6
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
Indicate the status of Channel 6 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2974
ll_dma_suspend_channel
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: gr55xx_ll_dma.h:514
ll_dma_clear_flag_dstt1
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3779
ll_dma_clear_flag_blk
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:3381
ll_dma_is_active_flag_blk5
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
Indicate the status of Channel 5 block complete flag.
Definition: gr55xx_ll_dma.h:2595
ll_dma_enable_it
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:4527
ll_dma_is_active_flag_blk3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: gr55xx_ll_dma.h:2557
ll_dma_is_active_flag_rblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: gr55xx_ll_dma.h:2189
ll_dma_set_channel_priority_level
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: gr55xx_ll_dma.h:1192
ll_dma_get_block_size
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: gr55xx_ll_dma.h:1288
ll_dma_is_active_flag_gblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: gr55xx_ll_dma.h:2076
ll_dma_enable_it_srct
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:4163
ll_dma_is_enable_it_err
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:4499
ll_dma_clear_flag_err1
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3959
ll_dma_is_active_flag_srct3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2737