app_qspi.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file app_qspi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of QSPI app library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup APP_DRIVER APP DRIVER
43 * @{
44 */
45
46 /** @defgroup APP_QSPI QSPI
47 * @brief QSPI APP module driver.
48 * @{
49 */
50
51
52 #ifndef _APP_QSPI_H_
53 #define _APP_QSPI_H_
54
55 #include "app_drv_config.h"
56 #if (APP_DRIVER_CHIP_TYPE != APP_DRIVER_GR5405) && (APP_DRIVER_CHIP_TYPE != APP_DRIVER_GR5332X)
57 #include "gr55xx_hal.h"
58 #endif
59
60 #include "app_io.h"
61 #include "app_dma.h"
62 #include "app_drv_error.h"
63 #include "app_drv_config.h"
64 #include "stdbool.h"
65 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
66 #include "app_qspi_user_config.h"
67 #endif
68 #ifdef __cplusplus
69 extern "C" {
70 #endif
71
72 #ifdef HAL_QSPI_MODULE_ENABLED
73
74 /**
75 * @defgroup APP_QSPI_MACRO Defines
76 * @{
77 */
78
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup APP_QSPI_Exported_Constants QSPI Exported Constants
81 * @{
82 */
83
84 /**
85 * @brief APP_QSPI_PIN Qspi pin defines
86 */
87 #define APP_QSPI_PIN_ENABLE 1 /**< QSPI pin enable */
88 #define APP_QSPI_PIN_DISABLE 0 /**< QSPI pin disable */
89
90 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
91 /**
92 * @brief APP_MAX_XFER MAX_XREF Defines
93 */
94 #define QSPI_MAX_XFER_SIZE_ONCE (0xFFFCu) /**< max xfer beat in every qspi xfer */
95 #define DMA_MAX_XFER_SIZE_ONCE (4095u) /**< max xfer beat in every dma xfer */
96
97 //#define APP_STORAGE_RAM_ID 0xf /**< Special ID to handle RAM Source */
98 #endif
99
100 #ifndef QSPI_SMART_CS_ENABLE
101 /**
102 * @brief QSPI_SMART_CS_ENABLE smart cs enable defines. NOTE: If QSPI_DATA_MODE_SPI, enable smart cs
103 */
104 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
105 #define QSPI_SMART_CS_ENABLE 1 /**< CS pin is controlled by software */
106 #else
107 #define QSPI_SMART_CS_ENABLE 0 /**< CS pin is controlled by hardware */
108 #endif
109 #endif
110
111 #if QSPI_SMART_CS_ENABLE
112 /**
113 * @brief QSPI_SMART_CS_LOW Pull down QSPI CS.
114 */
115 #define QSPI_SMART_CS_LOW(id) \
116 do { \
117 if(p_qspi_env[id]->p_pin_cfg->cs.enable == APP_QSPI_PIN_ENABLE) \
118 { \
119 app_io_write_pin(p_qspi_env[id]->p_pin_cfg->cs.type, \
120 p_qspi_env[id]->p_pin_cfg->cs.pin, \
121 APP_IO_PIN_RESET); \
122 } \
123 } while(0)
124
125 /**
126 * @brief QSPI_SMART_CS_HIGH Pull up QSPI CS.
127 */
128 #define QSPI_SMART_CS_HIGH(id) \
129 do { \
130 if(p_qspi_env[id]->p_pin_cfg->cs.enable == APP_QSPI_PIN_ENABLE) \
131 { \
132 app_io_write_pin(p_qspi_env[id]->p_pin_cfg->cs.type, \
133 p_qspi_env[id]->p_pin_cfg->cs.pin, \
134 APP_IO_PIN_SET); \
135 } \
136 } while(0)
137 #else
138 #define QSPI_SMART_CS_LOW(id)
139 #define QSPI_SMART_CS_HIGH(id)
140 #endif /* QSPI_SMART_CS_ENABLE */
141
142 /** @} */
143
144 /** @} */
145
146
147 /** @addtogroup APP_QSPI_ENUM Enumerations
148 * @{
149 */
150
151 /**
152 * @brief QSPI module Enumerations definition
153 */
154 typedef enum
155 {
156 APP_QSPI_ID_0, /**< QSPI module 0 */
157 APP_QSPI_ID_1, /**< QSPI module 1 */
158 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
159 APP_QSPI_ID_2, /**< QSPI module 2 */
160 #endif
161 APP_QSPI_ID_MAX, /**< Only for check parameter, not used as input parameters. */
162
163 APP_STORAGE_RAM_ID = 0xf,
164 } app_qspi_id_t;
165
166 /**
167 * @brief APP QSPI Event Type
168 */
169 typedef enum
170 {
171 APP_QSPI_EVT_ERROR, /**< Error reported by QSPI peripheral. */
172 APP_QSPI_EVT_TX_CPLT, /**< Requested TX transfer completed. */
173 APP_QSPI_EVT_RX_DATA, /**< Requested RX transfer completed. */
174 APP_QSPI_EVT_ABORT, /**< Abort reported by QSPI peripheral. */
175 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
176 APP_QSPI_EVT_ASYNC_WR_SCRN_CPLT, /**< ASYNC-Write Quad Screen Complete */
177 APP_QSPI_EVT_ASYNC_WR_SCRN_FAIL, /**< ASYNC-Write Quad Screen Fail */
178 #endif
179 } app_qspi_evt_type_t;
180
181 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
182 /**
183 * @brief QSPI Memory-Mapped Endian Mode
184 */
185 typedef enum {
186 APP_QSPI_MMAP_ENDIAN_MODE_0 = 0, /**< MMAP Endian Mode 0 */
187 APP_QSPI_MMAP_ENDIAN_MODE_1, /**< MMAP Endian Mode 1 */
188 APP_QSPI_MMAP_ENDIAN_MODE_2, /**< MMAP Endian Mode 2 */
189 } app_qspi_mmap_endian_mode_e;
190
191 /**
192 * @brief QSPI Device supporting Memory-Mapped Mode
193 */
194 typedef enum {
195 APP_QSPI_DEVICE_UNSET = 0, /**< UnSet Device */
196 APP_QSPI_DEVICE_FLASH = 1, /**< Flash Device */
197 APP_QSPI_DEVICE_PSRAM = 2, /**< PSRAM Device */
198 } app_qspi_device_e;
199
200 /**
201 * @brief Define PSRAM's Read Command for Memory-Mapped Mode
202 */
203 typedef enum {
204 PSRAM_MMAP_CMD_QREAD_0BH = 0x00, /**< 0BH in Quad */
205 PSRAM_MMAP_CMD_QREAD_EBH = 0x01, /**< EBH in Quad */
206 PSRAM_MMAP_CMD_READ_MAX
207 } app_qspi_psram_mmap_rd_cmd_e;
208
209 /**
210 * @brief Define PSRAM's Write Command for Memory-Mapped Mode
211 */
212 typedef enum {
213 PSRAM_MMAP_CMD_QWRITE_02H = 0x00, /**< 02H in Quad */
214 PSRAM_MMAP_CMD_QWRITE_38H = 0x01, /**< 38H in Quad */
215 PSRAM_MMAP_CMD_WRITE_MAX
216 } app_qspi_psram_mmap_wr_cmd_e;
217
218 /**
219 * @brief Define Flash's Read Command for Memory-Mapped Mode
220 */
221 typedef enum {
222 FLASH_MMAP_CMD_DREAD_3BH = 0x00, /**< 3BH in Dual */
223 FLASH_MMAP_CMD_2READ_BBH = 0x01, /**< BBH in 2Read */
224 FLASH_MMAP_CMD_2READ_BBH_SIOO = 0x02, /**< BBH in 2Read with SIOO mode */
225
226 FLASH_MMAP_CMD_QREAD_6BH = 0x03, /**< 6BH in QRead */
227 FLASH_MMAP_CMD_4READ_EBH = 0x04, /**< EBH in 4Read */
228 FLASH_MMAP_CMD_4READ_EBH_SIOO = 0x05, /**< EBH in 4Read with SIOO mode */
229 FLASH_MMAP_CMD_READ_MAX,
230 } app_qspi_flash_mmap_rd_cmd_e;
231
232 /**
233 * @brief APP QSPI interface type when drawing screen
234 */
235 typedef enum {
236 DRAW_TYPE_IF_NONE = 0x00,
237 DRAW_TYPE_IF_DUAL_SCREEN,
238 DRAW_TYPE_IF_VERI_LINKED_SCREEN,
239 } app_qspi_draw_screen_interface_type_e;
240
241 /**
242 * @brief Define Pin Groups for QSPI
243 */
244 typedef enum {
245
246 QSPI0_PIN_GROUP_0 = 0x00, /**< QSPI0 Pinmux Group */
247 /* CS : GPIO_26.MUX0 */
248 /* CLK : GPIO_21.MUX0 */
249 /* IO0 : GPIO_22.MUX0 */
250 /* IO1 : GPIO_23.MUX0 */
251 /* IO2 : GPIO_24.MUX0 */
252 /* IO3 : GPIO_25.MUX0 */
253
254 QSPI1_PIN_GROUP_0 = 0x01, /**< QSPI1 Pinmux Group 0 */
255 /* CS : GPIO_10.MUX0 */
256 /* CLK : GPIO_15.MUX0 */
257 /* IO0 : GPIO_11.MUX0 */
258 /* IO1 : GPIO_12.MUX0 */
259 /* IO2 : GPIO_13.MUX0 */
260 /* IO3 : GPIO_14.MUX0 */
261
262 QSPI2_PIN_GROUP_0 = 0x02, /**< QSPI2 Pinmux Group 0 */
263 /* CS : GPIO_27.MUX0 */
264 /* CLK : GPIO_16.MUX0 */
265 /* IO0 : GPIO_17.MUX0 */
266 /* IO1 : GPIO_18.MUX0 */
267 /* IO2 : GPIO_19.MUX0 */
268 /* IO3 : GPIO_20.MUX0 */
269 QSPIx_PIN_GROUP_MAX,
270 } qspi_pins_group_e;
271
272 /**
273 * @brief Define BLIT Mode By DMA
274 */
275 typedef enum {
276 BLIT_BY_DMA_SG = 0, /**< need enable BLIT_IMAGE_FEATURE_SUPPORT */
277 BLIT_BY_DMA_LLP = 1, /**< need enable PSRAM_LLP_FEATURE_SUPPORT */
278 } blit_xfer_type_e;
279
280 /** @} */
281
282 /** @addtogroup APP_QSPI_STRUCTURES Structures
283 * @{
284 */
285
286 /**
287 * @brief QSPI memory-mapped configuration Structures
288 */
289 typedef struct {
290 app_qspi_device_e dev_type; /**< Specifies the device type of QSPI */
291 app_qspi_psram_mmap_wr_cmd_e psram_wr; /**< Specifies the write command for PSRAM, Flash does not support this */
292 union {
293 app_qspi_flash_mmap_rd_cmd_e flash_rd; /**< Read command for flash device */
294 app_qspi_psram_mmap_rd_cmd_e psram_rd; /**< Read command for psram device */
295 } rd; /**< Specifies read command by real device */
296 void * set; /**< Reserved */
297 } app_qspi_mmap_device_t;
298 #endif
299
300 /**
301 * @brief QSPI IO configuration Structures
302 */
303 typedef struct
304 {
305 app_io_type_t type; /**< Specifies the type of QSPI IO. */
306 app_io_mux_t mux; /**< Specifies the Peripheral to be connected to the selected pins. */
307 uint32_t pin; /**< Specifies the IO pins to be configured.
308 This parameter can be any value of @ref GR5xxx_pins. */
309 app_io_mode_t mode; /**< Specifies the IO Mode for pins. */
310 app_io_pull_t pull; /**< Specifies the Pull-up or Pull-Down activation for the selected pins. */
311 uint8_t enable; /**< Enable or disable the pin. */
312 } app_qspi_pin_t;
313
314 /**
315 * @brief QSPI configuration Structures
316 */
317 typedef struct
318 {
319 app_qspi_pin_t cs; /**< Set the configuration of QSPI CS pin. */
320 app_qspi_pin_t clk; /**< Set the configuration of QSPI CLK pin. */
321 app_qspi_pin_t io_0; /**< Set the configuration of QSPI IO0 pin. */
322 app_qspi_pin_t io_1; /**< Set the configuration of QSPI IO1 pin. */
323 app_qspi_pin_t io_2; /**< Set the configuration of QSPI IO2 pin. */
324 app_qspi_pin_t io_3; /**< Set the configuration of QSPI IO3 pin. */
325 } app_qspi_pin_cfg_t;
326
327 /**
328 * @brief QSPI DMA configuration structure definition
329 */
330 typedef struct
331 {
332 dma_regs_t * dma_instance; /**< Specifies the dma instance of QSPI. */
333 dma_channel_t dma_channel; /**< Specifies the dma channel of QSPI. */
334 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
335 uint32_t wait_timeout_ms; /**< Specifies timeout time of polling and dead wait, ms. */
336 uint32_t extend; /**< Specifies extend segment, to use */
337 #endif
338 } app_qspi_dma_cfg_t;
339 /** @} */
340
341 /** @addtogroup APP_QSPI_TYPEDEFS Type Definitions
342 * @{
343 */
344
345 /**
346 * @brief QSPI command structure definition
347 */
348 typedef qspi_command_t app_qspi_command_t;
349 /** @} */
350
351 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
352 /** @addtogroup APP_QSPI_STRUCTURES Structures
353 * @{
354 */
355 typedef struct
356 {
357 uint32_t instruction; /**< Specifies the Instruction to be sent.
358 This parameter can be a value (8-bit) between 0x00 and 0xFF. */
359
360 uint32_t leading_address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
361 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
362
363 uint32_t ongoing_address; /**< Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize).
364 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF. */
365
366 uint32_t instruction_size; /**< Specifies the Instruction Size.
367 This parameter can be a value of @ref QSPI_Instruction_Size. */
368
369 uint32_t address_size; /**< Specifies the Address Size.
370 This parameter can be a value of @ref QSPI_Address_Size. */
371
372 uint32_t dummy_cycles; /**< Specifies the Number of Dummy Cycles.
373 This parameter can be a number between 0 and 31. */
374
375 uint32_t data_size; /**< Specifies the QSPI address width.
376 This parameter can be a value of @ref QSPI_Data_Size. */
377
378 uint32_t instruction_address_mode; /**< Specifies the Instruction and Address Mode.
379 This parameter can be a value of @ref QSPI_Inst_Addr_Mode. */
380
381 uint32_t data_mode; /**< Specifies the Data Mode (used for dummy cycles and data phases).
382 This parameter can be a value of @ref QSPI_Data_Mode. */
383
384 bool is_one_take_cs; /**< Sent all data in one take CS or in multiple independent CS */
385
386 } app_qspi_screen_command_t;
387 /** @} */
388 #endif
389
390 /** @addtogroup APP_QSPI_STRUCTURES Structures
391 * @{
392 */
393 /**
394 * @brief QSPI event structure definition
395 */
396 typedef struct
397 {
398 app_qspi_evt_type_t type; /**< Type of event. */
399 union
400 {
401 uint32_t error_code; /**< QSPI Error code . */
402 uint16_t size; /**< QSPI transmitted/received counter. */
403 } data; /**< Event data. */
404 } app_qspi_evt_t;
405
406 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
407 /**
408 * @brief Screen Info. structure definition
409 */
410 typedef struct {
411 unsigned int scrn_pixel_stride; /**< screen pixel stride, such as 390 */
412 unsigned int scrn_pixel_width; /**< screen pixel width, such as 390, width must be less or equal than stride */
413 unsigned int scrn_pixel_height; /**< screen pixel height, such as 390 */
414 unsigned int scrn_pixel_depth; /**< pixel depth, unit: byte, such as 2 */
415 } app_qspi_screen_info_t;
416
417
418 /**
419 * @brief Scroll-Screen structure definition
420 */
421 typedef struct {
422 uint32_t first_frame_start_address; /**< if scroll the screen horizontally : first stands for left image, second stands for right image */
423 uint32_t second_frame_start_address; /**< if scroll the screen vertically : first stands for up image, second stands for down image */
424 uint32_t scroll_coordinate; /**< scroll to where , must be even number, belongs to [0, SCREEN_PIXEL_WIDTH] */
425 bool is_horizontal_scroll; /**< true : screen horizontally ; false : screen vertically */
426 } app_qspi_screen_scroll_t;
427
428 /**
429 * @brief Vertical Scroll-Screen Linked List Structure
430 */
431 typedef struct _screen_veri_link_scroll_t {
432 uint32_t frame_ahb_start_address; /**< Start AHB address for current frame */
433 uint32_t frame_offset_lines; /**< Offset lines for current frame */
434 uint32_t frame_draw_lines; /**< Drawing lines (start from offset line) for current frame */
435 struct _screen_veri_link_scroll_t * next; /**< Linked to next node, if empty, Set NULL */
436 } app_qspi_screen_veri_link_scroll_t;
437
438 /**
439 * @brief One block of screen Structure
440 */
441 typedef struct {
442 uint32_t frame_ahb_start_address; /**< Start AHB address for current block */
443 uint32_t frame_offset_lines; /**< Offset lines for current block */
444 uint32_t frame_draw_lines; /**< Drawing lines (start from offset line) for current block */
445 } app_qspi_screen_block_t;
446
447 /**
448 * @brief Dual Screen (HOR/VER) Scroll Structure, just used for inner driver
449 */
450 typedef struct {
451 app_qspi_screen_scroll_t scroll_config; /**< Start AHB address for current frame */
452 uint32_t image_1_ahb_address; /**< Record first frame starting AHB address */
453 uint32_t image_2_ahb_address; /**< Record second frame starting AHB address */
454 uint32_t this_send_lines; /**< Record current sent lines */
455 uint32_t total_sent_lines; /**< Record total sent lines already */
456 uint32_t sent_line_order; /**< Record current line order */
457 } dual_screen_scroll_t;
458
459 /**
460 * @brief Vertical Linked List Screen-Scroll Structure, just used for inner driver
461 */
462 typedef struct {
463 app_qspi_screen_veri_link_scroll_t vl_scroll; /**< Start AHB address for current frame */
464 app_qspi_screen_veri_link_scroll_t * p_cur_scroll; /**< Record current linked node */
465 uint32_t total_sent_lines; /**< Record total sent lines */
466 } veri_linked_screen_scroll_t;
467
468 /**
469 * @brief Async Draw Screen Structure, just used for inner driver
470 */
471 typedef struct {
472 app_qspi_draw_screen_interface_type_e if_type; /**< drawing interface type */
473 app_qspi_id_t screen_id; /**< Specify the Screen ID */
474 app_qspi_id_t storage_id; /**< Specify the Memory ID */
475 uint32_t llp_cfg_right_shift_bit; /**< Record the llp shift bit configure */
476 uint32_t llp_cfg_ctrl_low; /**< Record the llp control bits configure */
477 app_qspi_screen_info_t screen_info; /**< Record the basic screen info */
478 app_qspi_screen_command_t qspi_screen_command; /**< Record the basic screen command */
479 union {
480 dual_screen_scroll_t dual_ss; /**< info for dual screen-scroll */
481 veri_linked_screen_scroll_t veri_linked_ss; /**< info for veri linked screen-scroll */
482 } ss; /**< union record */
483 } app_qspi_async_draw_screen_info_t;
484
485
486 /**
487 * @brief Blit Image structure definition
488 */
489 typedef struct {
490 uint32_t src_img_address; /**< source address, just offset in storage device */
491 uint32_t src_img_w; /**< pixel width of source image */
492 uint32_t src_img_h; /**< pixel height of source image */
493 uint32_t src_img_x; /**< x-coordinate of source image, left-top point is Coordinate origin */
494 uint32_t src_img_x_delta; /**< blit image width in pixel, do not multiple pixel depth */
495 uint32_t src_img_y; /**< y-coordinate of source image, left-top point is Coordinate origin */
496 uint32_t src_img_y_delta; /**< blit image height in pixel, do not multiple pixel depth */
497 uint32_t dst_buff_address; /**< destination buffer address */
498 uint32_t dst_buff_width; /**< pixel width of destination buffer */
499 uint32_t dst_buff_height; /**< pixel height of destination buffer */
500 uint32_t dst_buff_x; /**< x-coordinate of destination buffer, left-top point is Coordinate origin */
501 uint32_t dst_buff_y; /**< y-coordinate of destination buffer, left-top point is Coordinate origin */
502 uint32_t pixel_depth; /**< pixel depth in byte */
503 } blit_image_config_t;
504 #endif
505 /** @} */
506
507 /** @addtogroup APP_QSPI_TYPEDEFS Type Definitions
508 * @{
509 */
510
511 /**
512 * @brief QSPI event callback definition
513 */
514 typedef void (*app_qspi_evt_handler_t)(app_qspi_evt_t *p_evt);
515 /** @} */
516
517 /** @addtogroup APP_QSPI_ENUM Enumerations
518 * @{
519 */
520 /**@brief App qspi state types. */
521 typedef enum
522 {
523 APP_QSPI_INVALID = 0,
524 APP_QSPI_ACTIVITY,
525 #ifdef APP_DRIVER_WAKEUP_CALL_FUN
526 APP_QSPI_SLEEP,
527 #endif
528 } app_qspi_state_t;
529
530 /**@brief App qspi dma_state types. */
531 typedef enum
532 {
533 APP_QSPI_DMA_INVALID = 0,
534 APP_QSPI_DMA_ACTIVITY,
535 } app_qspi_dma_state_t;
536
537 /** @} */
538
539 /** @addtogroup APP_QSPI_STRUCTURES Structures
540 * @{
541 */
542
543 /**
544 * @brief QSPI device structure definition
545 */
546 typedef struct {
547 qspi_handle_t handle; /**< QSPI handle Structure. */
548 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
549 app_qspi_dma_cfg_t dma_cfg; /**< QSPI DMA configuration structure. */
550 #endif
551 app_qspi_pin_cfg_t *p_pin_cfg; /**< QSPI configuration Structures. */
552 dma_id_t dma_id; /**< DMA id. */
553 app_qspi_state_t qspi_state; /**< App qspi state types. */
554 app_qspi_dma_state_t qspi_dma_state; /**< App qspi dma_state types. */
555 volatile bool start_flag; /**< start flag. */
556 app_qspi_evt_handler_t evt_handler; /**< QSPI event callback. */
557 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
558 app_qspi_mmap_device_t mounted_mmap_device; /**< QSPI memory-mapped configuration Structures. */
559
560 volatile uint8_t mmap_endian_mode; /**< mmap endian mode. */
561 volatile bool is_mmap_inited; /**< mmap inited. */
562 volatile bool is_mmap_prefetch_en; /**< mmap prefetch. */
563 #endif
564 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
565 volatile bool is_used_dma; /**< used dma. */
566 volatile bool is_dma_mode_m2m; /**< dma mode. */
567 #endif
568 volatile bool is_rx_done; /**< rx done. */
569 volatile bool is_tx_done; /**< tx done. */
570 volatile bool is_xfer_err; /**< xfer err. */
571 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
572 volatile bool is_dma_done; /**< dma done. */
573 volatile bool is_async_write_screen; /**< async write screen. */
574 #endif
575 }qspi_env_t;
576
577 /**
578 * @brief QSPI parameters structure definition
579 */
580 typedef struct
581 {
582 app_qspi_id_t id; /**< specified QSPI module ID. */
583 app_qspi_pin_cfg_t pin_cfg; /**< the pin configuration information for the specified QSPI module. */
584 app_qspi_dma_cfg_t dma_cfg; /**< QSPI DMA configuration. */
585 qspi_init_t init; /**< QSPI communication parameters. */
586 qspi_env_t qspi_env; /**< QSPI device structure definition. */
587 } app_qspi_params_t;
588 /** @} */
589
590
591 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
592 /** @addtogroup HAL_APP_QSPI_DRIVER_CONSTANTS Constants
593 * @{
594 */
595
596 /**
597 * @brief The Reference to pin groups define
598 */
599 extern const app_qspi_pin_cfg_t g_qspi_pin_groups[QSPIx_PIN_GROUP_MAX];
600
601 /** @} */
602 #endif
603
604
605 /* Exported functions --------------------------------------------------------*/
606 /** @addtogroup HAL_APP_QSPI_DRIVER_FUNCTIONS Functions
607 * @{
608 */
609 /**
610 ****************************************************************************************
611 * @brief Initialize the APP QSPI DRIVER according to the specified parameters
612 * in the app_qspi_params_t and app_qspi_evt_handler_t.
613 * @note If interrupt mode is set, you can use blocking mode. Conversely, if blocking mode
614 * is set, you can't use interrupt mode.
615 *
616 * @param[in] p_params: Pointer to app_qspi_params_t parameter which contains the
617 * configuration information for the specified QSPI module.
618 * @param[in] evt_handler: QSPI user callback function.
619 *
620 * @return Result of initialization.
621 ****************************************************************************************
622 */
623 uint16_t app_qspi_init(app_qspi_params_t *p_params, app_qspi_evt_handler_t evt_handler);
624
625 /**
626 ****************************************************************************************
627 * @brief De-initialize the APP QSPI DRIVER peripheral.
628 *
629 * @param[in] id: De-initialize for a specific ID.
630 *
631 * @return Result of De-initialization.
632 ****************************************************************************************
633 */
634 uint16_t app_qspi_deinit(app_qspi_id_t id);
635
636 /**
637 ****************************************************************************************
638 * @brief Abort qspi communication with Interrupt.
639 *
640 * @param[in] id: QSPI module ID.
641 *
642 * @return Result of operation.
643 ****************************************************************************************
644 */
645 uint16_t app_qspi_abort(app_qspi_id_t id);
646
647 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
648 /**
649 ****************************************************************************************
650 * @brief Config the memory mapped mode (also called XIP mode) and Active the mode
651 *
652 * @param[in] id : QSPI module ID.
653 * @param[in] dev: device config for mmapped mode
654 *
655 * @return true/false
656 ****************************************************************************************
657 */
658 bool app_qspi_config_memory_mappped(app_qspi_id_t id, app_qspi_mmap_device_t dev);
659
660 /**
661 ****************************************************************************************
662 * @brief Active or Deactive memory mapped mode (also called XIP mode)
663 *
664 * @param[in] id : QSPI module ID.
665 * @param[in] is_active: true - Active the mode; false - Deactive the mode
666 *
667 * @return true/false
668 ****************************************************************************************
669 */
670 bool app_qspi_active_memory_mappped(app_qspi_id_t id, bool is_active);
671 #endif
672
673 /**
674 ****************************************************************************************
675 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
676 * @note This function is used only in Indirect Read Mode.
677 * @param[in] id: which QSPI module want to receive.
678 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
679 * @param[out] p_data: Pointer to data buffer
680 * @param[in] timeout: Timeout duration
681 *
682 * @return Result of operation.
683 ****************************************************************************************
684 */
685 uint16_t app_qspi_command_receive_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
686
687 /**
688 ****************************************************************************************
689 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
690 * @note This function is used only in Indirect Read Mode.
691 * @param[in] id: which QSPI module want to receive.
692 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
693 * @param[out] p_data: Pointer to data buffer
694 *
695 * @return Result of operation.
696 ****************************************************************************************
697 */
698 uint16_t app_qspi_command_receive_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data);
699
700 /**
701 ****************************************************************************************
702 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
703 * @note This function is used only in Indirect Read Mode.
704 * @param[in] id: which QSPI module want to transmit.
705 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
706 * @param[out] p_data: Pointer to data buffer
707 * @param[in] timeout: Timeout duration
708 *
709 * @return Result of operation.
710 ****************************************************************************************
711 */
712 uint16_t app_qspi_command_transmit_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout);
713
714 /**
715 ****************************************************************************************
716 * @brief Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mode with Interrupt.
717 * @note This function is used only in Indirect Read Mode.
718 * @param[in] id: which QSPI module want to transmit.
719 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
720 * @param[out] p_data: Pointer to data buffer
721 *
722 * @return Result of operation.
723 ****************************************************************************************
724 */
725 uint16_t app_qspi_command_transmit_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data);
726
727 /**
728 ****************************************************************************************
729 * @brief Transmit only instruction in blocking mode.
730 * @note This function is used only in Indirect Write Mode.
731 * @param[in] id: which QSPI module want to transmit command.
732 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
733 * @param[in] timeout: Timeout duration
734 *
735 * @return Result of operation.
736 ****************************************************************************************
737 */
738 uint16_t app_qspi_command_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint32_t timeout);
739
740 /**
741 ****************************************************************************************
742 * @brief Transmit instruction in non-blocking mode with Interrupt.
743 * @note This function is used only in Indirect Write Mode.
744 * @param[in] id: which QSPI module want to transmit command.
745 * @param[in] p_cmd: Pointer to a app_qspi_command_t structure that contains the instruction and address for data transfer.
746 *
747 * @return Result of operation.
748 ****************************************************************************************
749 */
750 uint16_t app_qspi_command_async(app_qspi_id_t id, app_qspi_command_t *p_cmd);
751
752 /**
753 ****************************************************************************************
754 * @brief Transmit data without command, support std/dual/quad mode
755 *
756 * @param[in] id : QSPI module ID.
757 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
758 * @ref QSPI_DATA_MODE_DUALSPI
759 * @ref QSPI_DATA_MODE_QUADSPI
760 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
761 * @ref QSPI_DATASIZE_16_BITS
762 * @ref QSPI_DATASIZE_32_BITS
763 * @param[in] p_data : data Pointer to transmit
764 * @param[in] length : byte length of data
765 * @param[in] timeout: Timeout duration
766 *
767 * @return true/false
768 ****************************************************************************************
769 */
770 uint16_t app_qspi_transmit_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout);
771
772 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
773 /**
774 ****************************************************************************************
775 * @brief Transmit an amount of data in blocking mode with standard SPI.
776 * @note This function is used only in Indirect Write Mode.
777 * @param[in] id: which QSPI module want to transmit.
778 * @param[in] p_data: Pointer to data buffer
779 * @param[in] length: Amount of data to be sent in bytes
780 * @param[in] timeout: Timeout duration
781 *
782 * @return Result of operation.
783 ****************************************************************************************
784 */
785 uint16_t app_qspi_transmit_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout);
786 #endif
787
788 /**
789 ****************************************************************************************
790 * @brief Transmit data without command, support std/dual/quad mode
791 *
792 * @param[in] id : QSPI module ID.
793 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
794 * @ref QSPI_DATA_MODE_DUALSPI
795 * @ref QSPI_DATA_MODE_QUADSPI
796 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
797 * @ref QSPI_DATASIZE_16_BITS
798 * @ref QSPI_DATASIZE_32_BITS
799 * @param[in] p_data : data Pointer to transmit
800 * @param[in] length : byte length of data
801 *
802 * @return true/false
803 ****************************************************************************************
804 */
805 uint16_t app_qspi_transmit_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length);
806
807 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
808 /**
809 ****************************************************************************************
810 * @brief Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
811 * @note This function is used only in Indirect Write Mode.
812 * @param[in] id: which QSPI module want to transmit.
813 * @param[in] p_data: Pointer to data buffer
814 * @param[in] length: Amount of data to be sent in bytes
815 *
816 * @return Result of operation.
817 ****************************************************************************************
818 */
819 uint16_t app_qspi_transmit_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length);
820 #endif
821
822 /**
823 ****************************************************************************************
824 * @brief Receive data without command, support std/dual/quad mode
825 *
826 * @param[in] id : QSPI module ID.
827 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
828 * @ref QSPI_DATA_MODE_DUALSPI
829 * @ref QSPI_DATA_MODE_QUADSPI
830 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
831 * @ref QSPI_DATASIZE_16_BITS
832 * @ref QSPI_DATASIZE_32_BITS
833 * @param[in] p_data : data Pointer to transmit
834 * @param[in] length : byte length of data
835 * @param[in] timeout: Timeout duration
836 *
837 * @return true/false
838 ****************************************************************************************
839 */
840 uint16_t app_qspi_receive_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout);
841
842 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
843 /**
844 ****************************************************************************************
845 * @brief Receive an amount of data in blocking mode with standard SPI.
846 * @note This function is used only in Indirect Read Mode.
847 * @param[in] id: which QSPI module want to receive.
848 * @param[out] p_data: Pointer to data buffer
849 * @param[in] length: Amount of data to be received in bytes
850 * @param[in] timeout: Timeout duration
851 *
852 * @return Result of operation.
853 ****************************************************************************************
854 */
855 uint16_t app_qspi_receive_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout);
856 #endif
857
858 /**
859 ****************************************************************************************
860 * @brief Receive data without command, support std/dual/quad mode
861 *
862 * @param[in] id : QSPI module ID.
863 * @param[in] qspi_mode : @ref QSPI_DATA_MODE_SPI
864 * @ref QSPI_DATA_MODE_DUALSPI
865 * @ref QSPI_DATA_MODE_QUADSPI
866 * @param[in] data_width :@ref QSPI_DATASIZE_08_BITS
867 * @ref QSPI_DATASIZE_16_BITS
868 * @ref QSPI_DATASIZE_32_BITS
869 * @param[in] p_data : data Pointer to transmit
870 * @param[in] length : byte length of data
871 *
872 * @return true/false
873 ****************************************************************************************
874 */
875 uint16_t app_qspi_receive_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length);
876
877 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
878 /**
879 ****************************************************************************************
880 * @brief Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
881 * @note This function is used only in Indirect Read Mode.
882 * @param[in] id: which QSPI module want to receive.
883 * @param[out] p_data: Pointer to data buffer
884 * @param[in] length: Amount of data to be received in bytes
885 *
886 * @return Result of operation.
887 ****************************************************************************************
888 */
889 uint16_t app_qspi_receive_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length);
890 #endif
891
892 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5526X) || (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR5525X)
893 /**
894 ****************************************************************************************
895 * @brief Set Data Endian Mode to Read in Memory mapped Mode(XIP Mode)
896 *
897 * @param[in] id : QSPI module ID.
898 * @param[in] mode : endian mode
899 * @return true/false
900 ****************************************************************************************
901 */
902 bool app_qspi_mmap_set_endian_mode(app_qspi_id_t id, app_qspi_mmap_endian_mode_e mode);
903
904 /**
905 ****************************************************************************************
906 * @brief Read U8 Data in Memory mapped Mode(XIP Mode), can be used in flash/psram device
907 *
908 * @param[in] id : QSPI module ID.
909 * @param[in] address : the address of device connected to QSPI, start from 0x000000
910 * @return the read data
911 ****************************************************************************************
912 */
913 uint8_t app_qspi_mmap_read_u8(app_qspi_id_t id, uint32_t address) ;
914
915 /**
916 ****************************************************************************************
917 * @brief Read U16 Data in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
918 *
919 * @param[in] id : QSPI module ID.
920 * @param[in] address : the address of device connected to QSPI, start from 0x000000
921 * @return the read data
922 ****************************************************************************************
923 */
924 uint16_t app_qspi_mmap_read_u16(app_qspi_id_t id, uint32_t address);
925
926 /**
927 ****************************************************************************************
928 * @brief Read U32 Data in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
929 *
930 * @param[in] id : QSPI module ID.
931 * @param[in] address : the address of device connected to QSPI, start from 0x000000
932 * @return the read data
933 ****************************************************************************************
934 */
935 uint32_t app_qspi_mmap_read_u32(app_qspi_id_t id, uint32_t address);
936
937 /**
938 ****************************************************************************************
939 * @brief Read data block in Memory mapped Mode(XIP Mode), The Data is ordered by the order in flash/psram device
940 *
941 * @param[in] id : QSPI module ID.
942 * @param[in] address : the address of device connected to QSPI, start from 0x000000
943 * @param[in] buffer : memory pointer to save the read data
944 * @param[in] length : the read length in byte
945 * @return true/false
946 ****************************************************************************************
947 */
948 bool app_qspi_mmap_read_block(app_qspi_id_t id, uint32_t address, uint8_t * buffer, uint32_t length);
949
950 /**
951 ****************************************************************************************
952 * @brief Return the XIP Base Address of QSPI Instance.
953 *
954 * @param[in] id: QSPI module ID.
955 *
956 * @return The XIP base address.
957 ****************************************************************************************
958 */
959 uint32_t app_qspi_get_xip_base_address(app_qspi_id_t id);
960
961 #endif
962
963 #if (APP_DRIVER_CHIP_TYPE == APP_DRIVER_GR551X)
964 /**
965 ****************************************************************************************
966 * @brief Transmit an amount of data in QPI mode (Async Mode).
967 * @param[in] id: Which QSPI module want to Transmit.
968 * @param[in] data_width: Just support @ref QSPI_DATASIZE_08_BITS @ref QSPI_DATASIZE_16_BITS @ref QSPI_DATASIZE_32_BITS
969 * @param[in] p_data: Pointer to data buffer
970 * @param[in] length: Amount of data to be transmitted in bytes
971 *
972 * @return Result of operation.
973 ****************************************************************************************
974 */
975 uint16_t app_qspi_transmit_in_qpi_async(app_qspi_id_t id, uint32_t data_width, uint8_t *p_data, uint32_t length);
976 #endif
977
978 /**
979 ****************************************************************************************
980 * @brief Return the QSPI handle.
981 *
982 * @param[in] id: QSPI module ID.
983 *
984 * @return Pointer to the specified ID's QSPI handle.
985 ****************************************************************************************
986 */
987 qspi_handle_t *app_qspi_get_handle(app_qspi_id_t id);
988
989 /** @} */
990
991 #endif
992
993 #ifdef __cplusplus
994 }
995 #endif
996
997 #endif
998
999 /** @} */
1000
1001 /** @} */
1002
1003 /** @} */
app_qspi_command_receive_sync
uint16_t app_qspi_command_receive_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
app_qspi_command_t
qspi_command_t app_qspi_command_t
QSPI command structure definition.
Definition: app_qspi.h:348
app_qspi_evt_t::size
uint16_t size
QSPI transmitted/received counter.
Definition: app_qspi.h:402
app_qspi_get_handle
qspi_handle_t * app_qspi_get_handle(app_qspi_id_t id)
Return the QSPI handle.
app_qspi_pin_t::pull
app_io_pull_t pull
Specifies the Pull-up or Pull-Down activation for the selected pins.
Definition: app_qspi.h:310
qspi_env_t::handle
qspi_handle_t handle
QSPI handle Structure.
Definition: app_qspi.h:547
app_qspi_params_t::id
app_qspi_id_t id
specified QSPI module ID.
Definition: app_qspi.h:582
APP_QSPI_ID_1
@ APP_QSPI_ID_1
QSPI module 1.
Definition: app_qspi.h:157
qspi_env_t::qspi_dma_state
app_qspi_dma_state_t qspi_dma_state
App qspi dma_state types.
Definition: app_qspi.h:554
app_qspi_transmit_sync_ex
uint16_t app_qspi_transmit_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit data without command, support std/dual/quad mode.
app_qspi_transmit_async
uint16_t app_qspi_transmit_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
qspi_env_t
QSPI device structure definition.
Definition: app_qspi.h:546
app_qspi_pin_cfg_t::io_3
app_qspi_pin_t io_3
Set the configuration of QSPI IO3 pin.
Definition: app_qspi.h:324
app_qspi_pin_t
QSPI IO configuration Structures.
Definition: app_qspi.h:304
app_qspi_command_transmit_async
uint16_t app_qspi_command_transmit_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
app_qspi_state_t
app_qspi_state_t
App qspi state types.
Definition: app_qspi.h:522
APP_QSPI_ID_0
@ APP_QSPI_ID_0
QSPI module 0.
Definition: app_qspi.h:156
app_qspi_params_t::qspi_env
qspi_env_t qspi_env
QSPI device structure definition.
Definition: app_qspi.h:586
app_qspi_evt_t
QSPI event structure definition.
Definition: app_qspi.h:397
app_io_pull_t
app_io_pull_t
GPIO pull Enumerations definition.
Definition: app_io.h:183
app_io_type_t
app_io_type_t
GPIO type Enumerations definition.
Definition: app_io.h:147
app_qspi_deinit
uint16_t app_qspi_deinit(app_qspi_id_t id)
De-initialize the APP QSPI DRIVER peripheral.
_qspi_init_t
QSPI init Structure definition.
Definition: gr55xx_hal_qspi.h:103
APP_QSPI_EVT_ERROR
@ APP_QSPI_EVT_ERROR
Error reported by QSPI peripheral.
Definition: app_qspi.h:171
app_qspi_receive_sync_ex
uint16_t app_qspi_receive_sync_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive data without command, support std/dual/quad mode.
qspi_env_t::is_tx_done
volatile bool is_tx_done
tx done.
Definition: app_qspi.h:569
app_qspi_pin_cfg_t::cs
app_qspi_pin_t cs
Set the configuration of QSPI CS pin.
Definition: app_qspi.h:319
app_qspi_evt_t::error_code
uint32_t error_code
QSPI Error code .
Definition: app_qspi.h:401
_qspi_command_t
QSPI command Structure definition.
Definition: gr55xx_hal_qspi.h:166
app_qspi_pin_t::mux
app_io_mux_t mux
Specifies the Peripheral to be connected to the selected pins.
Definition: app_qspi.h:306
app_io_mode_t
app_io_mode_t
GPIO mode Enumerations definition.
Definition: app_io.h:163
APP_QSPI_EVT_RX_DATA
@ APP_QSPI_EVT_RX_DATA
Requested RX transfer completed.
Definition: app_qspi.h:173
qspi_env_t::is_rx_done
volatile bool is_rx_done
rx done.
Definition: app_qspi.h:568
app_qspi_id_t
app_qspi_id_t
QSPI module Enumerations definition.
Definition: app_qspi.h:155
app_qspi_dma_cfg_t
QSPI DMA configuration structure definition.
Definition: app_qspi.h:331
app_io.h
Header file containing functions prototypes of GPIO app library.
app_qspi_abort
uint16_t app_qspi_abort(app_qspi_id_t id)
Abort qspi communication with Interrupt.
app_qspi_pin_cfg_t
QSPI configuration Structures.
Definition: app_qspi.h:318
app_qspi_evt_handler_t
void(* app_qspi_evt_handler_t)(app_qspi_evt_t *p_evt)
QSPI event callback definition.
Definition: app_qspi.h:514
app_qspi_command_receive_async
uint16_t app_qspi_command_receive_async(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
app_qspi_command_sync
uint16_t app_qspi_command_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
app_qspi_pin_t::pin
uint32_t pin
Specifies the IO pins to be configured.
Definition: app_qspi.h:307
APP_QSPI_DMA_INVALID
@ APP_QSPI_DMA_INVALID
Definition: app_qspi.h:533
app_qspi_dma_state_t
app_qspi_dma_state_t
App qspi dma_state types.
Definition: app_qspi.h:532
qspi_env_t::dma_id
dma_id_t dma_id
DMA id.
Definition: app_qspi.h:552
APP_QSPI_EVT_ABORT
@ APP_QSPI_EVT_ABORT
Abort reported by QSPI peripheral.
Definition: app_qspi.h:174
app_qspi_receive_async_ex
uint16_t app_qspi_receive_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length)
Receive data without command, support std/dual/quad mode.
app_qspi_transmit_async_ex
uint16_t app_qspi_transmit_async_ex(app_qspi_id_t id, uint32_t qspi_mode, uint32_t data_width, uint8_t *p_data, uint32_t length)
Transmit data without command, support std/dual/quad mode.
app_qspi_user_config.h
app_qspi_pin_t::enable
uint8_t enable
Enable or disable the pin.
Definition: app_qspi.h:311
app_qspi_receive_sync
uint16_t app_qspi_receive_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
APP_QSPI_ACTIVITY
@ APP_QSPI_ACTIVITY
Definition: app_qspi.h:524
app_qspi_pin_cfg_t::io_1
app_qspi_pin_t io_1
Set the configuration of QSPI IO1 pin.
Definition: app_qspi.h:322
APP_QSPI_EVT_TX_CPLT
@ APP_QSPI_EVT_TX_CPLT
Requested TX transfer completed.
Definition: app_qspi.h:172
app_qspi_params_t::init
qspi_init_t init
QSPI communication parameters.
Definition: app_qspi.h:585
APP_STORAGE_RAM_ID
@ APP_STORAGE_RAM_ID
Definition: app_qspi.h:163
qspi_env_t::p_pin_cfg
app_qspi_pin_cfg_t * p_pin_cfg
QSPI configuration Structures.
Definition: app_qspi.h:551
app_qspi_params_t::pin_cfg
app_qspi_pin_cfg_t pin_cfg
the pin configuration information for the specified QSPI module.
Definition: app_qspi.h:583
qspi_env_t::qspi_state
app_qspi_state_t qspi_state
App qspi state types.
Definition: app_qspi.h:553
app_dma.h
Header file containing functions prototypes of DMA app library.
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
app_qspi_command_async
uint16_t app_qspi_command_async(app_qspi_id_t id, app_qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
app_qspi_receive_async
uint16_t app_qspi_receive_async(app_qspi_id_t id, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
app_qspi_transmit_in_qpi_async
uint16_t app_qspi_transmit_in_qpi_async(app_qspi_id_t id, uint32_t data_width, uint8_t *p_data, uint32_t length)
Transmit an amount of data in QPI mode (Async Mode).
app_qspi_pin_cfg_t::clk
app_qspi_pin_t clk
Set the configuration of QSPI CLK pin.
Definition: app_qspi.h:320
APP_QSPI_ID_MAX
@ APP_QSPI_ID_MAX
Only for check parameter, not used as input parameters.
Definition: app_qspi.h:161
app_qspi_evt_type_t
app_qspi_evt_type_t
APP QSPI Event Type.
Definition: app_qspi.h:170
app_qspi_params_t::dma_cfg
app_qspi_dma_cfg_t dma_cfg
QSPI DMA configuration.
Definition: app_qspi.h:584
app_qspi_dma_cfg_t::dma_instance
dma_regs_t * dma_instance
Specifies the dma instance of QSPI.
Definition: app_qspi.h:332
app_io_mux_t
app_io_mux_t
GPIO mux Enumerations definition.
Definition: app_io.h:255
qspi_env_t::evt_handler
app_qspi_evt_handler_t evt_handler
QSPI event callback.
Definition: app_qspi.h:556
APP_QSPI_DMA_ACTIVITY
@ APP_QSPI_DMA_ACTIVITY
Definition: app_qspi.h:534
app_qspi_evt_t::type
app_qspi_evt_type_t type
Type of event.
Definition: app_qspi.h:398
app_qspi_pin_t::mode
app_io_mode_t mode
Specifies the IO Mode for pins.
Definition: app_qspi.h:309
app_qspi_transmit_sync
uint16_t app_qspi_transmit_sync(app_qspi_id_t id, uint8_t *p_data, uint32_t length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
app_qspi_pin_cfg_t::io_2
app_qspi_pin_t io_2
Set the configuration of QSPI IO2 pin.
Definition: app_qspi.h:323
app_drv_error.h
Header file of app driver error code.
app_drv_config.h
Header file of app driver config code.
app_qspi_pin_t::type
app_io_type_t type
Specifies the type of QSPI IO.
Definition: app_qspi.h:305
app_qspi_init
uint16_t app_qspi_init(app_qspi_params_t *p_params, app_qspi_evt_handler_t evt_handler)
Initialize the APP QSPI DRIVER according to the specified parameters in the app_qspi_params_t and app...
_qspi_handle
QSPI handle Structure definition.
Definition: gr55xx_hal_qspi.h:123
qspi_env_t::is_xfer_err
volatile bool is_xfer_err
xfer err.
Definition: app_qspi.h:570
app_qspi_command_transmit_sync
uint16_t app_qspi_command_transmit_sync(app_qspi_id_t id, app_qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
app_qspi_params_t
QSPI parameters structure definition.
Definition: app_qspi.h:581
dma_id_t
int16_t dma_id_t
DMA id definition.
Definition: app_dma.h:98
app_qspi_pin_cfg_t::io_0
app_qspi_pin_t io_0
Set the configuration of QSPI IO0 pin.
Definition: app_qspi.h:321
app_qspi_dma_cfg_t::dma_channel
dma_channel_t dma_channel
Specifies the dma channel of QSPI.
Definition: app_qspi.h:333
qspi_env_t::start_flag
volatile bool start_flag
start flag.
Definition: app_qspi.h:555
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: gr55xx_hal_dma.h:93
APP_QSPI_INVALID
@ APP_QSPI_INVALID
Definition: app_qspi.h:523