- At R&D firm engaged in mixed signal ASIC design, develop new UVM agents, scoreboards & tests to verify complex Mixed signal ASIC & FPGA RTL design.
- Create test sequences & mixed signal behavior models to predict expected performance & accelerate design cycles.
- Create & run verification regression scripts to ensure that a IC modification has not impaired functionality.
- Generate functional & code coverage reports containing metrics to assess design quality.
- Generate UVC (universal verification) components & scoreboards to test whether IC model is correctly processing variable stimuli.
- Generate System Verilog Assertions to validate design behavior.
- Run gate level simulations.
- Create low power verification models.
Goodix Technology Inc 133 Technology Dr #200 Irvine CA 92618
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