Stock Code:603160

招贤纳士banner

Recruitment

Recruitment Life at Goodix Voices from Goodix

Senior VLSI Design Engineer

Job Description:

- At R&D firm engaged in SOC RTL design & implementation. 

- Propose efficient architectures & implementations to optimize chip area & power consumption. 

- Perform block & chip level design & simulation using Verilog/System Verilog. Generate stimulus w/ C/C++. 

- Use modern ASIC design flow to perform duties. Perform synthesis constraint generation w/TCL for Field Programmable Gate Array (FPGA) & ASICs. 

- Perform Static Timing Analysis (STA) on digital circuits. 

-  Assist in testing system functionality & performance on FPGA in lab environment using logic analyzer & oscilloscopes. 


Location:

Goodix Technology Inc, 133 Technology Dr #200, Irvine CA 92618


Employee Activity

The annual domestic and international scenic spots and historical tourism activities enable employees to enjoy the great rivers of the motherland and the localities while relaxing.

More

 

BackContact Us

 

扫描关注

打开微信,点击底部的“发现”,使用“扫一扫”即可关注

×