Macros | |
| #define | QSPI_CLOCK_MODE_0 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_1EDGE) |
| #define | QSPI_CLOCK_MODE_1 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_2EDGE) |
| #define | QSPI_CLOCK_MODE_2 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_1EDGE) |
| #define | QSPI_CLOCK_MODE_3 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_2EDGE) |
| #define QSPI_CLOCK_MODE_0 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_1EDGE) |
Inactive state of CLK is low; CLK toggles at the start of the first data bit
| #define QSPI_CLOCK_MODE_1 (LL_SSI_SCPOL_LOW | LL_SSI_SCPHA_2EDGE) |
Inactive state of CLK is low; CLK toggles in the middle of the first data bit
| #define QSPI_CLOCK_MODE_2 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_1EDGE) |
Inactive state of CLK is high; CLK toggles at the start of the first data bit
| #define QSPI_CLOCK_MODE_3 (LL_SSI_SCPOL_HIGH | LL_SSI_SCPHA_2EDGE) |
Inactive state of CLK is high; CLK toggles in the middle of the first data bit