Functions | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_cmd (xqspi_regs_t *XQSPIx, uint32_t cmd) |
| Set read command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_cmd (xqspi_regs_t *XQSPIx) |
| Get read command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_xip_hp (xqspi_regs_t *XQSPIx) |
| Enable high performance mode. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_xip_hp (xqspi_regs_t *XQSPIx) |
| Disable high performance mode. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_xip_hp (xqspi_regs_t *XQSPIx) |
| Check if high performance mode is enabled. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_ss (xqspi_regs_t *XQSPIx, uint32_t ss) |
| Set slave select. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_ss (xqspi_regs_t *XQSPIx) |
| Get slave select. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_cpha (xqspi_regs_t *XQSPIx, uint32_t cpha) |
| Set clock phase. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_cpha (xqspi_regs_t *XQSPIx) |
| Get clock phase. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_cpol (xqspi_regs_t *XQSPIx, uint32_t cpol) |
| Set clock polarity. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_cpol (xqspi_regs_t *XQSPIx) |
| Get clock polarity. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_addr_size (xqspi_regs_t *XQSPIx, uint32_t size) |
| Set address bytes in command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_addr_size (xqspi_regs_t *XQSPIx) |
| Get address bytes in command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_endian (xqspi_regs_t *XQSPIx, uint32_t endian) |
| Set endian in reading data. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_endian (xqspi_regs_t *XQSPIx) |
| Get endian in reading data. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_hp_cmd (xqspi_regs_t *XQSPIx, uint32_t cmd) |
| Set high performance command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_hp_cmd (xqspi_regs_t *XQSPIx) |
| Get high performance command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_dummycycles (xqspi_regs_t *XQSPIx, uint32_t cycles) |
| Set dummy cycles in command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_dummycycles (xqspi_regs_t *XQSPIx) |
| Get dummy cycles in command. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_set_xip_dummy_hp (xqspi_regs_t *XQSPIx, uint32_t cycles) |
| Set dummy cycles in high performance end. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_dummy_hp (xqspi_regs_t *XQSPIx) |
| Get dummy cycles in high performance end. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_xip (xqspi_regs_t *XQSPIx) |
| Enable XIP mode. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_xip (xqspi_regs_t *XQSPIx) |
| Disable XIP mode. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_xip (xqspi_regs_t *XQSPIx) |
| Check if XIP mode is enabled. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_xip_flag (xqspi_regs_t *XQSPIx) |
| Get XIP status. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_is_enabled_xip_it (xqspi_regs_t *XQSPIx) |
| Check if XIP interrupt is enabled. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_flag_xip_it (xqspi_regs_t *XQSPIx) |
| Get XIP interrupt flag. More... | |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t | ll_xqspi_get_req_xip_it (xqspi_regs_t *XQSPIx) |
| Get XIP interrupt request. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_enable_xip_it (xqspi_regs_t *XQSPIx) |
| Set XIP interrupt enable. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void | ll_xqspi_disable_xip_it (xqspi_regs_t *XQSPIx) |
| Set XIP interrupt disable. More... | |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip | ( | xqspi_regs_t * | XQSPIx | ) |
Disable XIP mode.
| Register | BitsName |
|---|---|
| CTRL3 | EN_REQ |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp | ( | xqspi_regs_t * | XQSPIx | ) |
Disable high performance mode.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_HPEN |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it | ( | xqspi_regs_t * | XQSPIx | ) |
Set XIP interrupt disable.
| Register | BitsName |
|---|---|
| INTCLR | INT_CLR |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip | ( | xqspi_regs_t * | XQSPIx | ) |
Enable XIP mode.
| Register | BitsName |
|---|---|
| CTRL3 | EN_REQ |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp | ( | xqspi_regs_t * | XQSPIx | ) |
Enable high performance mode.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_HPEN |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it | ( | xqspi_regs_t * | XQSPIx | ) |
Set XIP interrupt enable.
| Register | BitsName |
|---|---|
| INTSET | INT_SET |
| XQSPIx | XQSPI instance |
| None |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it | ( | xqspi_regs_t * | XQSPIx | ) |
Get XIP interrupt flag.
| Register | BitsName |
|---|---|
| INTSTAT | INT_STAT |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 1 |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it | ( | xqspi_regs_t * | XQSPIx | ) |
Get XIP interrupt request.
| Register | BitsName |
|---|---|
| INTREQ | INT_REQ |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 1 |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size | ( | xqspi_regs_t * | XQSPIx | ) |
Get address bytes in command.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_ADDR4 |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd | ( | xqspi_regs_t * | XQSPIx | ) |
Get read command.
| Register | BitsName |
|---|---|
| CTRL0 | CFG_CMD |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha | ( | xqspi_regs_t * | XQSPIx | ) |
Get clock phase.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_CPHA |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol | ( | xqspi_regs_t * | XQSPIx | ) |
Get clock polarity.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_CPOL |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp | ( | xqspi_regs_t * | XQSPIx | ) |
Get dummy cycles in high performance end.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_ENDDUMMY |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 3. |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles | ( | xqspi_regs_t * | XQSPIx | ) |
Get dummy cycles in command.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_DUMMYCYCLES |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 0xF. |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian | ( | xqspi_regs_t * | XQSPIx | ) |
Get endian in reading data.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_LE32 |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag | ( | xqspi_regs_t * | XQSPIx | ) |
Get XIP status.
| Register | BitsName |
|---|---|
| STAT | EN_OUT |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 1 |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd | ( | xqspi_regs_t * | XQSPIx | ) |
Get high performance command.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_HPMODE |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 0xFF. |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss | ( | xqspi_regs_t * | XQSPIx | ) |
Get slave select.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_SS |
| XQSPIx | XQSPI instance |
| Returned | Value can be one of the following values: |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip | ( | xqspi_regs_t * | XQSPIx | ) |
Check if XIP mode is enabled.
| Register | BitsName |
|---|---|
| CTRL3 | EN_REQ |
| XQSPIx | XQSPI instance |
| State | of bit (1 or 0). |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp | ( | xqspi_regs_t * | XQSPIx | ) |
Check if high performance mode is enabled.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_HPEN |
| XQSPIx | XQSPI instance |
| State | of bit (1 or 0). |
| SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it | ( | xqspi_regs_t * | XQSPIx | ) |
Check if XIP interrupt is enabled.
| Register | BitsName |
|---|---|
| INTEN | INT_EN |
| XQSPIx | XQSPI instance |
| Returned | Value can between: 0 ~ 1 |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | size | ||
| ) |
Set address bytes in command.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_ADDR4 |
| XQSPIx | XQSPI instance |
| size | This parameter can be one or more of the following values: |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cmd | ||
| ) |
Set read command.
| Register | BitsName |
|---|---|
| CTRL0 | CFG_CMD |
| XQSPIx | XQSPI instance |
| cmd | This parameter can be one of the following values: |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cpha | ||
| ) |
Set clock phase.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_CPHA |
| XQSPIx | XQSPI instance |
| cpha | This parameter can be one or more of the following values: |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cpol | ||
| ) |
Set clock polarity.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_CPOL |
| XQSPIx | XQSPI instance |
| cpol | This parameter can be one or more of the following values: |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cycles | ||
| ) |
Set dummy cycles in high performance end.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_ENDDUMMY |
| XQSPIx | XQSPI instance |
| cycles | This parameter can between: 0 ~ 3. |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cycles | ||
| ) |
Set dummy cycles in command.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_DUMMYCYCLES |
| XQSPIx | XQSPI instance |
| cycles | This parameter can between: 0 ~ 0xF. |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | endian | ||
| ) |
Set endian in reading data.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_LE32 |
| XQSPIx | XQSPI instance |
| endian | This parameter can be one or more of the following values: |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | cmd | ||
| ) |
Set high performance command.
| Register | BitsName |
|---|---|
| CTRL2 | CFG_HPMODE |
| XQSPIx | XQSPI instance |
| cmd | This value is specified by different QSPI FLASH memory vendor to enter into its status register to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF. |
| None |
| SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss | ( | xqspi_regs_t * | XQSPIx, |
| uint32_t | ss | ||
| ) |
Set slave select.
| Register | BitsName |
|---|---|
| CTRL1 | CFG_SS |
| XQSPIx | XQSPI instance |
| ss | This parameter can be one or more of the following values: |
| None |