Go to the documentation of this file.
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
159 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
160 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
161 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
162 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
163 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
164 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
165 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
166 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
167 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
173 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
174 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
175 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
176 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
183 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U)
184 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC
185 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST
186 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST)
192 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
193 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
194 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
200 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
201 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
202 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
208 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
209 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
210 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
211 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
212 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
213 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
219 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
220 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
221 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
222 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
223 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
224 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
230 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
231 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
232 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
238 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
239 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
240 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
246 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
247 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
248 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
249 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
250 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
251 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
252 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
253 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
259 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
260 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
266 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
267 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
273 #define LL_DMA_PERIPH_SPIM_TX ((uint32_t)0x00000000U)
274 #define LL_DMA_PERIPH_SPIM_RX ((uint32_t)0x00000001U)
275 #define LL_DMA_PERIPH_SPIS_TX ((uint32_t)0x00000002U)
276 #define LL_DMA_PERIPH_SPIS_RX ((uint32_t)0x00000003U)
277 #define LL_DMA_PERIPH_QSPI0_TX ((uint32_t)0x00000004U)
278 #define LL_DMA_PERIPH_QSPI0_RX ((uint32_t)0x00000005U)
279 #define LL_DMA_PERIPH_I2C0_TX ((uint32_t)0x00000006U)
280 #define LL_DMA_PERIPH_I2C0_RX ((uint32_t)0x00000007U)
281 #define LL_DMA_PERIPH_I2C1_TX ((uint32_t)0x00000008U)
282 #define LL_DMA_PERIPH_I2C1_RX ((uint32_t)0x00000009U)
283 #define LL_DMA_PERIPH_I2S_S_TX ((uint32_t)0x00000008U)
284 #define LL_DMA_PERIPH_I2S_S_RX ((uint32_t)0x00000009U)
285 #define LL_DMA_PERIPH_UART0_TX ((uint32_t)0x0000000AU)
286 #define LL_DMA_PERIPH_UART0_RX ((uint32_t)0x0000000BU)
287 #define LL_DMA_PERIPH_QSPI1_TX ((uint32_t)0x0000000CU)
288 #define LL_DMA_PERIPH_QSPI1_RX ((uint32_t)0x0000000DU)
289 #define LL_DMA_PERIPH_I2S_M_TX ((uint32_t)0x0000000CU)
290 #define LL_DMA_PERIPH_I2S_M_RX ((uint32_t)0x0000000DU)
291 #define LL_DMA_PERIPH_SNSADC ((uint32_t)0x0000000EU)
292 #define LL_DMA_PERIPH_MEM ((uint32_t)0x0000000FU)
313 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
321 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
352 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
371 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
386 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
412 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
436 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
462 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
488 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
513 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
537 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
561 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
600 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
601 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC,
631 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
659 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
688 __STATIC_INLINE
void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
690 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
719 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
747 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
774 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
802 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
829 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
857 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
884 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
912 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
939 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
967 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
994 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1022 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1049 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1082 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1114 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1140 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1166 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1200 uint32_t src_address,
1201 uint32_t dst_address,
1204 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1205 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1206 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1231 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1256 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1280 return READ_REG(DMAx->CHANNEL[channel].SAR);
1304 return READ_REG(DMAx->CHANNEL[channel].DAR);
1330 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1331 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1358 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1359 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1384 return READ_REG(DMAx->CHANNEL[channel].SAR);
1409 return READ_REG(DMAx->CHANNEL[channel].DAR);
1453 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1496 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1540 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1583 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos;
1613 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1614 src_handshaking | dst_handshaking);
1639 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1640 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1664 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1690 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1691 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1692 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1717 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1718 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1743 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1744 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1768 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1794 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1795 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1796 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1821 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1822 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1843 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1858 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1873 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1888 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1903 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1927 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
1951 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
1975 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
1999 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2023 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2047 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2062 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2077 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2092 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2107 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2122 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
2152 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
2167 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
2191 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2206 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2221 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2236 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2251 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2266 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2281 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
2296 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
2311 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
2335 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2350 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2365 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2380 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2395 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2410 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2425 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
2440 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
2455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
2479 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2494 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2509 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2524 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2539 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2554 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2569 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
2584 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
2599 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
2623 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
2638 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
2653 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
2668 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
2683 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
2698 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
2713 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
2728 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
2743 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
2767 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2782 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2797 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2812 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
2827 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
2842 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
2857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
2872 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
2887 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
2911 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
2926 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
2941 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
2956 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
2971 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
2986 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
3001 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
3016 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
3031 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
3055 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
3070 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
3085 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
3100 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
3115 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
3130 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
3145 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
3160 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
3175 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
3199 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
3214 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
3229 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
3244 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
3259 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
3274 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
3289 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
3304 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
3319 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
3343 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
3358 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
3373 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
3388 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
3403 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
3418 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
3433 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
3448 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
3463 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
3493 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3517 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3541 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3565 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3589 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3613 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3637 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3661 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3685 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3709 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3733 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3757 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
3781 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
3805 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
3829 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
3853 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3877 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: gr55xx_ll_dma.h:3341
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: gr55xx_ll_dma.h:992
uint32_t mode
Definition: gr55xx_ll_dma.h:92
__STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
Get DMA mode circular or normal.
Definition: gr55xx_ll_dma.h:717
uint32_t src_address
Definition: gr55xx_ll_dma.h:78
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: gr55xx_ll_dma.h:772
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: gr55xx_ll_dma.h:1112
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: gr55xx_ll_dma.h:3707
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3113
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2477
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:2780
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:2825
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: gr55xx_ll_dma.h:2969
__STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
Clear Channel 7 error flag.
Definition: gr55xx_ll_dma.h:3461
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: gr55xx_ll_dma.h:434
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:2120
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2537
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3257
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: gr55xx_ll_dma.h:2204
error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: gr55xx_ll_dma.h:2636
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3053
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: gr55xx_ll_dma.h:369
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: gr55xx_ll_dma.h:2651
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: gr55xx_ll_dma.h:3416
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: gr55xx_ll_dma.h:882
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3083
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1494
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: gr55xx_ll_dma.h:598
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2348
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: gr55xx_ll_dma.h:827
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1356
error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: gr55xx_ll_dma.h:559
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3128
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3683
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: gr55xx_ll_dma.h:2939
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:2765
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3659
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: gr55xx_ll_dma.h:910
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3272
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: gr55xx_ll_dma.h:460
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1382
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1047
__STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
Clear Channel 6 Block Cmplete flag.
Definition: gr55xx_ll_dma.h:3014
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
Indicate the status of Channel 7 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2597
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: gr55xx_ll_dma.h:3356
__STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
Clear Channel 5 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3287
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: gr55xx_ll_dma.h:3401
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3803
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:2795
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1662
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1451
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: gr55xx_ll_dma.h:1138
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: gr55xx_ll_dma.h:1229
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: gr55xx_ll_dma.h:1997
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2492
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: gr55xx_ll_dma.h:1407
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2552
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
Indicate the status of Channel 7 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2453
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: gr55xx_ll_dma.h:1198
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
Indicate the status of Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:2135
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
Indicate the status of Channel 5 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2423
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:1792
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:3611
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
Indicate the status of Channel 5 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2567
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: gr55xx_ll_dma.h:800
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: gr55xx_ll_dma.h:2219
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3755
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:3875
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2363
LL DMA init Structure definition.
Definition: gr55xx_ll_dma.h:77
__STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
Clear Channel 6 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3302
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: gr55xx_ll_dma.h:2681
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
Indicate the status of Channel 5 error flag.
Definition: gr55xx_ll_dma.h:2711
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: gr55xx_ll_dma.h:2075
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: gr55xx_ll_dma.h:1302
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: gr55xx_ll_dma.h:2621
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: gr55xx_ll_dma.h:1637
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:2810
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3731
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: gr55xx_ll_dma.h:2333
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3068
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2522
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: gr55xx_ll_dma.h:2234
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: gr55xx_ll_dma.h:3491
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1766
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: gr55xx_ll_dma.h:410
__STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
Clear Channel 7 Block Complete flag.
Definition: gr55xx_ll_dma.h:3029
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: gr55xx_ll_dma.h:965
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2507
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2408
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: gr55xx_ll_dma.h:2045
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2378
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:1871
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: gr55xx_ll_dma.h:2666
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
Indicate the status of Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:2165
uint32_t block_size
Definition: gr55xx_ll_dma.h:119
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: gr55xx_ll_dma.h:1278
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: gr55xx_ll_dma.h:1611
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
Indicate the status of Channel 7 block complete flag.
Definition: gr55xx_ll_dma.h:2309
uint32_t src_peripheral
Definition: gr55xx_ll_dma.h:125
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: gr55xx_ll_dma.h:2264
__STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
Clear Channel 5 transfer complete flag.
Definition: gr55xx_ll_dma.h:2855
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1538
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: gr55xx_ll_dma.h:937
uint32_t dst_data_width
Definition: gr55xx_ll_dma.h:114
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: gr55xx_ll_dma.h:1901
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: gr55xx_ll_dma.h:745
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: gr55xx_ll_dma.h:1841
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: gr55xx_ll_dma.h:1254
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: gr55xx_ll_dma.h:1688
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
Indicate the status of Channel 7 error flag.
Definition: gr55xx_ll_dma.h:2741
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
Indicate the status of Channel 6 block complete flag.
Definition: gr55xx_ll_dma.h:2294
__STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
Clear Channel 5 error flag.
Definition: gr55xx_ll_dma.h:3431
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: gr55xx_ll_dma.h:511
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: gr55xx_ll_dma.h:3212
uint32_t src_data_width
Definition: gr55xx_ll_dma.h:109
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: gr55xx_ll_dma.h:3386
__STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
Set DMA mode Single block or Multi block.
Definition: gr55xx_ll_dma.h:688
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: gr55xx_ll_dma.h:1328
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
Indicate the status of Channel 6 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2438
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:3515
uint32_t direction
Definition: gr55xx_ll_dma.h:86
__STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
Clear Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:2870
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3197
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: gr55xx_ll_dma.h:350
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: gr55xx_ll_dma.h:2924
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3242
uint32_t dst_peripheral
Definition: gr55xx_ll_dma.h:130
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: gr55xx_ll_dma.h:3635
uint32_t priority
Definition: gr55xx_ll_dma.h:135
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: gr55xx_ll_dma.h:2696
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: gr55xx_ll_dma.h:1886
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: gr55xx_ll_dma.h:1741
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:657
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: gr55xx_ll_dma.h:3587
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1819
__STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
Clear Channel 7 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3317
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
Indicate the status of Channel 6 error flag.
Definition: gr55xx_ll_dma.h:2726
__STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
Clear Channel 7 transfer complete flag.
Definition: gr55xx_ll_dma.h:2885
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: gr55xx_ll_dma.h:2021
uint32_t dst_increment_mode
Definition: gr55xx_ll_dma.h:104
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: gr55xx_ll_dma.h:2840
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3098
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3779
uint32_t dst_address
Definition: gr55xx_ll_dma.h:82
__STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
Clear Channel 6 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3158
__STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
Clear Channel 6 error flag.
Definition: gr55xx_ll_dma.h:3446
__STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
Clear Channel 5 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3143
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: gr55xx_ll_dma.h:2090
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
Indicate the status of Channel 6 transfer complete flag.
Definition: gr55xx_ll_dma.h:2150
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: gr55xx_ll_dma.h:384
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: gr55xx_ll_dma.h:1581
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: gr55xx_ll_dma.h:2954
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: gr55xx_ll_dma.h:1020
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: gr55xx_ll_dma.h:1715
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3563
uint32_t src_increment_mode
Definition: gr55xx_ll_dma.h:99
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: gr55xx_ll_dma.h:629
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: gr55xx_ll_dma.h:2060
__STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
Clear Channel 7 source transaction Complete flag.
Definition: gr55xx_ll_dma.h:3173
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: gr55xx_ll_dma.h:2105
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: gr55xx_ll_dma.h:535
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
__STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
Clear Channel 5 Block Complete flag.
Definition: gr55xx_ll_dma.h:2999
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: gr55xx_ll_dma.h:855
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: gr55xx_ll_dma.h:1973
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: gr55xx_ll_dma.h:2984
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:2189
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: gr55xx_ll_dma.h:1925
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
Indicate the status of Channel 6 destination transaction complete flag.
Definition: gr55xx_ll_dma.h:2582
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: gr55xx_ll_dma.h:486
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: gr55xx_ll_dma.h:3227
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: gr55xx_ll_dma.h:2909
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
Indicate the status of Channel 5 block complete flag.
Definition: gr55xx_ll_dma.h:2279
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: gr55xx_ll_dma.h:3851
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: gr55xx_ll_dma.h:2249
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: gr55xx_ll_dma.h:1949
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: gr55xx_ll_dma.h:1080
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: gr55xx_ll_dma.h:1164
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: gr55xx_ll_dma.h:1856
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: gr55xx_ll_dma.h:3539
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: gr55xx_ll_dma.h:3827
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: gr55xx_ll_dma.h:3371
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: gr55xx_ll_dma.h:2393