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52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
114 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK
115 #define LL_CGC_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK
116 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK
117 #define LL_CGC_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK
118 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK
119 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK
120 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK
121 #define LL_CGC_WFI_DMA_HCLK MCU_SUB_WFI_DMA_HCLK
122 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK
123 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK
124 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK
125 #define LL_CGC_WFI_I2S_S_HCLK MCU_SUB_WFI_I2S_S_HCLK
127 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x00000FFFU)
133 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK
134 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK
135 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK
137 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U)
143 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK
144 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK
146 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U)
153 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK
154 #define LL_CGC_FRC_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK
155 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK
156 #define LL_CGC_FRC_PWM_HCLK MCU_SUB_FORCE_PWM_HCLK
157 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK
158 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK
159 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK
160 #define LL_CGC_FRC_DMA_HCLK MCU_SUB_FORCE_DMA_HCLK
161 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK
162 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK
163 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK
164 #define LL_CGC_FRC_I2S_S_HCLK MCU_SUB_FORCE_I2S_S_HCLK
166 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000FFFU)
172 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK
173 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK
174 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK
176 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U)
182 #define LL_CGC_FRC_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK
183 #define LL_CGC_FRC_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK
184 #define LL_CGC_FRC_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK
185 #define LL_CGC_FRC_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK
186 #define LL_CGC_FRC_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK
187 #define LL_CGC_FRC_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK
188 #define LL_CGC_FRC_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK
189 #define LL_CGC_FRC_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK
190 #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK
191 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK
192 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK
194 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x0001FF00U)
195 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x0A01FF00U)
216 #define LL_CGC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
224 #define LL_CGC_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
245 #define LL_CGC_DEFAULT_CONFIG \
247 .wfi_clk0 = ~LL_CGC_WFI_ALL_HCLK0, \
248 .wfi_clk1 = ~LL_CGC_WFI_ALL_HCLK1, \
249 .wfi_clk2 = ~LL_CGC_WFI_ALL_HCLK2, \
250 .force_clk0 = ~LL_CGC_FRC_ALL_HCLK0, \
251 .force_clk1 = ~LL_CGC_FRC_ALL_HCLK1, \
252 .force_clk2 = ~LL_CGC_FRC_ALL_HCLK2, \
306 WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], clk_mask);
344 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0]);
365 GLOBAL_EXCEPTION_DISABLE();
366 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1, clk_mask);
367 GLOBAL_EXCEPTION_ENABLE();
386 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1);
404 GLOBAL_EXCEPTION_DISABLE();
405 MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2, clk_mask);
406 GLOBAL_EXCEPTION_ENABLE();
423 return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2);
462 WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], clk_mask);
500 return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1]);
521 GLOBAL_EXCEPTION_DISABLE();
522 MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1, clk_mask);
523 GLOBAL_EXCEPTION_ENABLE();
542 return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1);
579 GLOBAL_EXCEPTION_DISABLE();
580 MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2, clk_mask);
581 GLOBAL_EXCEPTION_ENABLE();
617 return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2);
631 GLOBAL_EXCEPTION_DISABLE();
632 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
633 GLOBAL_EXCEPTION_ENABLE();
647 GLOBAL_EXCEPTION_DISABLE();
648 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
649 GLOBAL_EXCEPTION_ENABLE();
663 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK) == (MCU_SUB_WFI_SECU_HCLK));
677 GLOBAL_EXCEPTION_DISABLE();
678 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
679 GLOBAL_EXCEPTION_ENABLE();
693 GLOBAL_EXCEPTION_DISABLE();
694 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
695 GLOBAL_EXCEPTION_ENABLE();
709 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK) == (MCU_SUB_WFI_SIM_HCLK));
723 GLOBAL_EXCEPTION_DISABLE();
724 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
725 GLOBAL_EXCEPTION_ENABLE();
739 GLOBAL_EXCEPTION_DISABLE();
740 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
741 GLOBAL_EXCEPTION_ENABLE();
755 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK) == (MCU_SUB_WFI_HTB_HCLK));
769 GLOBAL_EXCEPTION_DISABLE();
770 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
771 GLOBAL_EXCEPTION_ENABLE();
785 GLOBAL_EXCEPTION_DISABLE();
786 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
787 GLOBAL_EXCEPTION_ENABLE();
801 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK) == (MCU_SUB_WFI_PWM_HCLK));
815 GLOBAL_EXCEPTION_DISABLE();
816 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
817 GLOBAL_EXCEPTION_ENABLE();
831 GLOBAL_EXCEPTION_DISABLE();
832 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
833 GLOBAL_EXCEPTION_ENABLE();
847 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK) == (MCU_SUB_WFI_ROM_HCLK));
861 GLOBAL_EXCEPTION_DISABLE();
862 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
863 GLOBAL_EXCEPTION_ENABLE();
877 GLOBAL_EXCEPTION_DISABLE();
878 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
879 GLOBAL_EXCEPTION_ENABLE();
893 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK) == (MCU_SUB_WFI_SNSADC_HCLK));
907 GLOBAL_EXCEPTION_DISABLE();
908 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
909 GLOBAL_EXCEPTION_ENABLE();
923 GLOBAL_EXCEPTION_DISABLE();
924 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
925 GLOBAL_EXCEPTION_ENABLE();
939 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK) == (MCU_SUB_WFI_GPIO_HCLK));
953 GLOBAL_EXCEPTION_DISABLE();
954 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
955 GLOBAL_EXCEPTION_ENABLE();
969 GLOBAL_EXCEPTION_DISABLE();
970 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
971 GLOBAL_EXCEPTION_ENABLE();
985 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK) == (MCU_SUB_WFI_DMA_HCLK));
999 GLOBAL_EXCEPTION_DISABLE();
1000 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1001 GLOBAL_EXCEPTION_ENABLE();
1015 GLOBAL_EXCEPTION_DISABLE();
1016 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1017 GLOBAL_EXCEPTION_ENABLE();
1031 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK) == (MCU_SUB_WFI_BLE_BRG_HCLK));
1045 GLOBAL_EXCEPTION_DISABLE();
1046 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1047 GLOBAL_EXCEPTION_ENABLE();
1061 GLOBAL_EXCEPTION_DISABLE();
1062 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1063 GLOBAL_EXCEPTION_ENABLE();
1077 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK) == (MCU_SUB_WFI_APB_SUB_HCLK));
1091 GLOBAL_EXCEPTION_DISABLE();
1092 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1093 GLOBAL_EXCEPTION_ENABLE();
1107 GLOBAL_EXCEPTION_DISABLE();
1108 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1109 GLOBAL_EXCEPTION_ENABLE();
1124 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK) == (MCU_SUB_WFI_SERIAL_HCLK));
1138 GLOBAL_EXCEPTION_DISABLE();
1139 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1140 GLOBAL_EXCEPTION_ENABLE();
1154 GLOBAL_EXCEPTION_DISABLE();
1155 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1156 GLOBAL_EXCEPTION_ENABLE();
1170 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK) == (MCU_SUB_WFI_I2S_S_HCLK));
1184 GLOBAL_EXCEPTION_DISABLE();
1185 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1186 GLOBAL_EXCEPTION_ENABLE();
1200 GLOBAL_EXCEPTION_DISABLE();
1201 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1202 GLOBAL_EXCEPTION_ENABLE();
1216 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK) == (MCU_SUB_WFI_AON_MCUSUB_HCLK));
1230 GLOBAL_EXCEPTION_DISABLE();
1231 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1232 GLOBAL_EXCEPTION_ENABLE();
1246 GLOBAL_EXCEPTION_DISABLE();
1247 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1248 GLOBAL_EXCEPTION_ENABLE();
1262 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK) == (MCU_SUB_WFI_XF_XQSPI_HCLK));
1276 GLOBAL_EXCEPTION_DISABLE();
1277 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1278 GLOBAL_EXCEPTION_ENABLE();
1292 GLOBAL_EXCEPTION_DISABLE();
1293 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1294 GLOBAL_EXCEPTION_ENABLE();
1308 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK) == (MCU_SUB_WFI_SRAM_HCLK));
1322 GLOBAL_EXCEPTION_DISABLE();
1323 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1324 GLOBAL_EXCEPTION_ENABLE();
1338 GLOBAL_EXCEPTION_DISABLE();
1340 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1342 GLOBAL_EXCEPTION_ENABLE();
1357 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK) == (MCU_SUB_WFI_SECU_DIV4_PCLK));
1371 GLOBAL_EXCEPTION_DISABLE();
1373 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1375 GLOBAL_EXCEPTION_ENABLE();
1389 GLOBAL_EXCEPTION_DISABLE();
1391 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1393 GLOBAL_EXCEPTION_ENABLE();
1407 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK) == (MCU_SUB_WFI_XQSPI_DIV4_PCLK));
1421 GLOBAL_EXCEPTION_DISABLE();
1423 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1425 GLOBAL_EXCEPTION_ENABLE();
1439 GLOBAL_EXCEPTION_DISABLE();
1441 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1443 GLOBAL_EXCEPTION_ENABLE();
1457 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK) == (MCU_SUB_FORCE_SECU_HCLK));
1471 GLOBAL_EXCEPTION_DISABLE();
1473 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1475 GLOBAL_EXCEPTION_ENABLE();
1489 GLOBAL_EXCEPTION_DISABLE();
1491 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1493 GLOBAL_EXCEPTION_ENABLE();
1507 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK) == (MCU_SUB_FORCE_SIM_HCLK));
1521 GLOBAL_EXCEPTION_DISABLE();
1523 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1525 GLOBAL_EXCEPTION_ENABLE();
1539 GLOBAL_EXCEPTION_DISABLE();
1541 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1543 GLOBAL_EXCEPTION_ENABLE();
1557 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK) == (MCU_SUB_FORCE_HTB_HCLK));
1571 GLOBAL_EXCEPTION_DISABLE();
1573 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1575 GLOBAL_EXCEPTION_ENABLE();
1589 GLOBAL_EXCEPTION_DISABLE();
1591 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1593 GLOBAL_EXCEPTION_ENABLE();
1607 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK) == (MCU_SUB_FORCE_PWM_HCLK));
1621 GLOBAL_EXCEPTION_DISABLE();
1623 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1625 GLOBAL_EXCEPTION_ENABLE();
1639 GLOBAL_EXCEPTION_DISABLE();
1641 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1643 GLOBAL_EXCEPTION_ENABLE();
1657 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK) == (MCU_SUB_FORCE_ROM_HCLK));
1671 GLOBAL_EXCEPTION_DISABLE();
1673 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1675 GLOBAL_EXCEPTION_ENABLE();
1689 GLOBAL_EXCEPTION_DISABLE();
1691 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1693 GLOBAL_EXCEPTION_ENABLE();
1707 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK) == (MCU_SUB_FORCE_SNSADC_HCLK));
1721 GLOBAL_EXCEPTION_DISABLE();
1723 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1725 GLOBAL_EXCEPTION_ENABLE();
1739 GLOBAL_EXCEPTION_DISABLE();
1741 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1743 GLOBAL_EXCEPTION_ENABLE();
1757 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK) == (MCU_SUB_FORCE_GPIO_HCLK));
1771 GLOBAL_EXCEPTION_DISABLE();
1773 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1775 GLOBAL_EXCEPTION_ENABLE();
1789 GLOBAL_EXCEPTION_DISABLE();
1791 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1793 GLOBAL_EXCEPTION_ENABLE();
1807 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK) == (MCU_SUB_FORCE_DMA_HCLK));
1821 GLOBAL_EXCEPTION_DISABLE();
1823 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1825 GLOBAL_EXCEPTION_ENABLE();
1839 GLOBAL_EXCEPTION_DISABLE();
1841 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1843 GLOBAL_EXCEPTION_ENABLE();
1857 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK) == (MCU_SUB_FORCE_BLE_BRG_HCLK));
1871 GLOBAL_EXCEPTION_DISABLE();
1873 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1875 GLOBAL_EXCEPTION_ENABLE();
1889 GLOBAL_EXCEPTION_DISABLE();
1891 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1893 GLOBAL_EXCEPTION_ENABLE();
1907 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK) == (MCU_SUB_FORCE_APB_SUB_HCLK));
1921 GLOBAL_EXCEPTION_DISABLE();
1923 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1925 GLOBAL_EXCEPTION_ENABLE();
1939 GLOBAL_EXCEPTION_DISABLE();
1941 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1943 GLOBAL_EXCEPTION_ENABLE();
1957 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK) == (MCU_SUB_FORCE_SERIAL_HCLK));
1971 GLOBAL_EXCEPTION_DISABLE();
1973 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1975 GLOBAL_EXCEPTION_ENABLE();
1989 GLOBAL_EXCEPTION_DISABLE();
1991 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1993 GLOBAL_EXCEPTION_ENABLE();
2007 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK) == (MCU_SUB_FORCE_I2S_S_HCLK));
2021 GLOBAL_EXCEPTION_DISABLE();
2023 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2025 GLOBAL_EXCEPTION_ENABLE();
2039 GLOBAL_EXCEPTION_DISABLE();
2041 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2043 GLOBAL_EXCEPTION_ENABLE();
2057 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK) == (MCU_SUB_FORCE_AON_MCUSUB_HCLK));
2071 GLOBAL_EXCEPTION_DISABLE();
2073 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2075 GLOBAL_EXCEPTION_ENABLE();
2089 GLOBAL_EXCEPTION_DISABLE();
2091 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2093 GLOBAL_EXCEPTION_ENABLE();
2107 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK) == (MCU_SUB_FORCE_XF_XQSPI_HCLK));
2121 GLOBAL_EXCEPTION_DISABLE();
2123 SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2125 GLOBAL_EXCEPTION_ENABLE();
2139 GLOBAL_EXCEPTION_DISABLE();
2141 CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2143 GLOBAL_EXCEPTION_ENABLE();
2157 return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK) == (MCU_SUB_FORCE_SRAM_HCLK));
2171 GLOBAL_EXCEPTION_DISABLE();
2173 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2175 GLOBAL_EXCEPTION_ENABLE();
2189 GLOBAL_EXCEPTION_DISABLE();
2191 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2193 GLOBAL_EXCEPTION_ENABLE();
2207 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK) == (MCU_SUB_FORCE_UART0_HCLK));
2221 GLOBAL_EXCEPTION_DISABLE();
2223 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2225 GLOBAL_EXCEPTION_ENABLE();
2239 GLOBAL_EXCEPTION_DISABLE();
2241 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2243 GLOBAL_EXCEPTION_ENABLE();
2257 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK) == (MCU_SUB_FORCE_UART1_HCLK));
2271 GLOBAL_EXCEPTION_DISABLE();
2273 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2275 GLOBAL_EXCEPTION_ENABLE();
2289 GLOBAL_EXCEPTION_DISABLE();
2291 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2293 GLOBAL_EXCEPTION_ENABLE();
2307 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK) == (MCU_SUB_FORCE_I2C0_HCLK));
2321 GLOBAL_EXCEPTION_DISABLE();
2323 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2325 GLOBAL_EXCEPTION_ENABLE();
2339 GLOBAL_EXCEPTION_DISABLE();
2341 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2343 GLOBAL_EXCEPTION_ENABLE();
2357 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK) == (MCU_SUB_FORCE_I2C1_HCLK));
2371 GLOBAL_EXCEPTION_DISABLE();
2373 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2375 GLOBAL_EXCEPTION_ENABLE();
2389 GLOBAL_EXCEPTION_DISABLE();
2391 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2393 GLOBAL_EXCEPTION_ENABLE();
2407 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK) == (MCU_SUB_FORCE_SPIM_HCLK));
2421 GLOBAL_EXCEPTION_DISABLE();
2423 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2425 GLOBAL_EXCEPTION_ENABLE();
2439 GLOBAL_EXCEPTION_DISABLE();
2441 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2443 GLOBAL_EXCEPTION_ENABLE();
2457 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK) == (MCU_SUB_FORCE_SPIS_HCLK));
2471 GLOBAL_EXCEPTION_DISABLE();
2473 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2475 GLOBAL_EXCEPTION_ENABLE();
2489 GLOBAL_EXCEPTION_DISABLE();
2491 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2493 GLOBAL_EXCEPTION_ENABLE();
2507 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK) == (MCU_SUB_FORCE_QSPI0_HCLK));
2521 GLOBAL_EXCEPTION_DISABLE();
2523 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2525 GLOBAL_EXCEPTION_ENABLE();
2539 GLOBAL_EXCEPTION_DISABLE();
2541 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2543 GLOBAL_EXCEPTION_ENABLE();
2557 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK) == (MCU_SUB_FORCE_QSPI1_HCLK));
2571 GLOBAL_EXCEPTION_DISABLE();
2573 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2575 GLOBAL_EXCEPTION_ENABLE();
2589 GLOBAL_EXCEPTION_DISABLE();
2591 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2593 GLOBAL_EXCEPTION_ENABLE();
2607 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK) == (MCU_SUB_FORCE_I2S_HCLK));
2621 GLOBAL_EXCEPTION_DISABLE();
2623 SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2625 GLOBAL_EXCEPTION_ENABLE();
2639 GLOBAL_EXCEPTION_DISABLE();
2641 CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2643 GLOBAL_EXCEPTION_ENABLE();
2657 return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK) == (MCU_SUB_FORCE_SECU_DIV4_PCLK));
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr55xx_ll_cgc.h:460
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:983
__STATIC_INLINE void ll_cgc_disable_force_off_dma_hclk(void)
Disabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1787
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1887
__STATIC_INLINE void ll_cgc_enable_wfi_off_i2s_s_hclk(void)
Enable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1136
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:875
uint32_t wfi_clk2
Definition: gr55xx_ll_cgc.h:84
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:767
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:721
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1737
uint32_t wfi_clk1
Definition: gr55xx_ll_cgc.h:81
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/DMA/B...
Definition: gr55xx_ll_cgc.h:498
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:783
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1198
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2269
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1437
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:937
__STATIC_INLINE void ll_cgc_enable_force_off_pwm_hclk(void)
Enabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1569
struct _ll_cgc_init_t ll_cgc_init_t
LL CGC init Structure definition.
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:2055
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1182
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2587
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1306
uint32_t force_clk0
Definition: gr55xx_ll_cgc.h:87
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1013
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1919
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1214
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:891
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:799
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:2155
error_status_t ll_cgc_deinit(void)
De-initialize CGC registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:540
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2087
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:691
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2137
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:2255
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1555
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2005
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2319
__STATIC_INLINE void ll_cgc_enable_force_off_dma_hclk(void)
Enabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1769
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2387
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2419
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1819
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2305
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1637
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1669
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm_hclk(void)
Indicate whether the clock for PWM is forced to close.
Definition: gr55xx_ll_cgc.h:1605
__STATIC_INLINE void ll_cgc_disable_force_off_pwm_hclk(void)
Disabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1587
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:967
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1105
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1405
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2505
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2355
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_i2s_s_hclk(void)
Indicate whether the I2S slave automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1168
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2555
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2105
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1228
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:661
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr55xx_ll_cgc.h:342
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2069
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1755
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO...
Definition: gr55xx_ll_cgc.h:304
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:845
__STATIC_INLINE void ll_cgc_disable_wfi_off_i2s_s_hclk(void)
Disable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1152
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:629
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:859
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2369
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1687
__STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
Enabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1469
__STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
Disabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1487
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/...
Definition: gr55xx_ll_cgc.h:615
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2637
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2337
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1869
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:921
uint32_t wfi_clk0
Definition: gr55xx_ll_cgc.h:78
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1122
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2287
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:905
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2437
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr55xx_ll_cgc.h:402
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:363
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:519
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2487
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1387
uint32_t force_clk1
Definition: gr55xx_ll_cgc.h:90
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1987
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1905
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1059
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1837
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1089
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1290
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:421
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2019
error_status_t ll_cgc_init(ll_cgc_init_t *p_cgc_init)
Initialize CGC registers according to the specified. parameters in p_cgc_init.
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1955
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2037
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2519
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:737
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2469
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1029
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:2205
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1043
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:384
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2169
uint32_t force_clk2
Definition: gr55xx_ll_cgc.h:93
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2219
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1619
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:707
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
Indicate whether the clock for SIM is forced to close.
Definition: gr55xx_ll_cgc.h:1505
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1719
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:951
LL CGC init Structure definition.
Definition: gr55xx_ll_cgc.h:77
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1537
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:997
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1855
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2119
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1075
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1244
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/SPIM_HCLK...
Definition: gr55xx_ll_cgc.h:577
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1260
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1369
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2619
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1355
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1969
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2237
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:753
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1419
void ll_cgc_struct_init(ll_cgc_init_t *p_cgc_init)
Set each field of a ll_cgc_init_t type structure to default value.
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1336
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1320
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2405
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1655
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2605
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:645
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:813
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2537
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2569
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1519
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2455
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:675
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2187
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1937
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1455
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:829
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1705
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma_hclk(void)
Indicate whether the clock for DMA is forced to close.
Definition: gr55xx_ll_cgc.h:1805
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:2655
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1274