Macros

#define DMA_REQUEST_SPIM_TX   LL_DMA_PERIPH_SPIM_TX
 
#define DMA_REQUEST_SPIM_RX   LL_DMA_PERIPH_SPIM_RX
 
#define DMA_REQUEST_SPIS_TX   LL_DMA_PERIPH_SPIS_TX
 
#define DMA_REQUEST_SPIS_RX   LL_DMA_PERIPH_SPIS_RX
 
#define DMA_REQUEST_QSPI0_TX   LL_DMA_PERIPH_QSPI0_TX
 
#define DMA_REQUEST_QSPI0_RX   LL_DMA_PERIPH_QSPI0_RX
 
#define DMA_REQUEST_I2C0_TX   LL_DMA_PERIPH_I2C0_TX
 
#define DMA_REQUEST_I2C0_RX   LL_DMA_PERIPH_I2C0_RX
 
#define DMA_REQUEST_I2C1_TX   LL_DMA_PERIPH_I2C1_TX
 
#define DMA_REQUEST_I2C1_RX   LL_DMA_PERIPH_I2C1_RX
 
#define DMA_REQUEST_I2S_S_TX   LL_DMA_PERIPH_I2S_S_TX
 
#define DMA_REQUEST_I2S_S_RX   LL_DMA_PERIPH_I2S_S_RX
 
#define DMA_REQUEST_UART0_TX   LL_DMA_PERIPH_UART0_TX
 
#define DMA_REQUEST_UART0_RX   LL_DMA_PERIPH_UART0_RX
 
#define DMA_REQUEST_QSPI1_TX   LL_DMA_PERIPH_QSPI1_TX
 
#define DMA_REQUEST_QSPI1_RX   LL_DMA_PERIPH_QSPI1_RX
 
#define DMA_REQUEST_I2S_M_TX   LL_DMA_PERIPH_I2S_M_TX
 
#define DMA_REQUEST_I2S_M_RX   LL_DMA_PERIPH_I2S_M_RX
 
#define DMA_REQUEST_SNSADC   LL_DMA_PERIPH_SNSADC
 
#define DMA_REQUEST_MEM   LL_DMA_PERIPH_MEM
 

Detailed Description

Macro Definition Documentation

◆ DMA_REQUEST_I2C0_RX

#define DMA_REQUEST_I2C0_RX   LL_DMA_PERIPH_I2C0_RX

DMA I2C0 receive request

◆ DMA_REQUEST_I2C0_TX

#define DMA_REQUEST_I2C0_TX   LL_DMA_PERIPH_I2C0_TX

DMA I2C0 transmit request

◆ DMA_REQUEST_I2C1_RX

#define DMA_REQUEST_I2C1_RX   LL_DMA_PERIPH_I2C1_RX

DMA I2C1 receive request

◆ DMA_REQUEST_I2C1_TX

#define DMA_REQUEST_I2C1_TX   LL_DMA_PERIPH_I2C1_TX

DMA I2C1 transmit request

◆ DMA_REQUEST_I2S_M_RX

#define DMA_REQUEST_I2S_M_RX   LL_DMA_PERIPH_I2S_M_RX

DMA I2S_M receive request

◆ DMA_REQUEST_I2S_M_TX

#define DMA_REQUEST_I2S_M_TX   LL_DMA_PERIPH_I2S_M_TX

DMA I2S_M transmit request

◆ DMA_REQUEST_I2S_S_RX

#define DMA_REQUEST_I2S_S_RX   LL_DMA_PERIPH_I2S_S_RX

DMA I2S_S receive request

◆ DMA_REQUEST_I2S_S_TX

#define DMA_REQUEST_I2S_S_TX   LL_DMA_PERIPH_I2S_S_TX

DMA I2S_S transmit request

◆ DMA_REQUEST_MEM

#define DMA_REQUEST_MEM   LL_DMA_PERIPH_MEM

DMA Memory request

◆ DMA_REQUEST_QSPI0_RX

#define DMA_REQUEST_QSPI0_RX   LL_DMA_PERIPH_QSPI0_RX

DMA QSPI0 receive request

◆ DMA_REQUEST_QSPI0_TX

#define DMA_REQUEST_QSPI0_TX   LL_DMA_PERIPH_QSPI0_TX

DMA QSPI0 transmit request

◆ DMA_REQUEST_QSPI1_RX

#define DMA_REQUEST_QSPI1_RX   LL_DMA_PERIPH_QSPI1_RX

DMA QSPI1 receive request

◆ DMA_REQUEST_QSPI1_TX

#define DMA_REQUEST_QSPI1_TX   LL_DMA_PERIPH_QSPI1_TX

DMA QSPI1 transmit request

◆ DMA_REQUEST_SNSADC

#define DMA_REQUEST_SNSADC   LL_DMA_PERIPH_SNSADC

DMA SenseADC request

◆ DMA_REQUEST_SPIM_RX

#define DMA_REQUEST_SPIM_RX   LL_DMA_PERIPH_SPIM_RX

DMA SPIM receive request

◆ DMA_REQUEST_SPIM_TX

#define DMA_REQUEST_SPIM_TX   LL_DMA_PERIPH_SPIM_TX

DMA SPIM transmit request

◆ DMA_REQUEST_SPIS_RX

#define DMA_REQUEST_SPIS_RX   LL_DMA_PERIPH_SPIS_RX

DMA SPIS receive request

◆ DMA_REQUEST_SPIS_TX

#define DMA_REQUEST_SPIS_TX   LL_DMA_PERIPH_SPIS_TX

DMA SPIS transmit request

◆ DMA_REQUEST_UART0_RX

#define DMA_REQUEST_UART0_RX   LL_DMA_PERIPH_UART0_RX

DMA UART0 receive request

◆ DMA_REQUEST_UART0_TX

#define DMA_REQUEST_UART0_TX   LL_DMA_PERIPH_UART0_TX

DMA UART0 transmit request