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52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
121 #define LL_MSIO_PIN_0 ((uint32_t)0x01U)
122 #define LL_MSIO_PIN_1 ((uint32_t)0x02U)
123 #define LL_MSIO_PIN_2 ((uint32_t)0x04U)
124 #define LL_MSIO_PIN_3 ((uint32_t)0x08U)
125 #define LL_MSIO_PIN_4 ((uint32_t)0x10U)
126 #define LL_MSIO_PIN_ALL ((uint32_t)0x1FU)
132 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U)
133 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U)
134 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U)
135 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U)
141 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U)
142 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U)
148 #define LL_MSIO_PULL_NO ((uint32_t)0x0U)
149 #define LL_MSIO_PULL_UP ((uint32_t)0x1U)
150 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U)
156 #define LL_MSIO_MUX_0 ((uint32_t)0x0U)
157 #define LL_MSIO_MUX_1 ((uint32_t)0x1U)
158 #define LL_MSIO_MUX_2 ((uint32_t)0x2U)
159 #define LL_MSIO_MUX_3 ((uint32_t)0x3U)
160 #define LL_MSIO_MUX_4 ((uint32_t)0x4U)
161 #define LL_MSIO_MUX_5 ((uint32_t)0x5U)
162 #define LL_MSIO_MUX_6 ((uint32_t)0x6U)
163 #define LL_MSIO_MUX_7 ((uint32_t)0x7U)
184 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
192 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
213 #define LL_MSIO_DEFAULT_CONFIG \
215 .pin = LL_MSIO_PIN_ALL, \
216 .direction = LL_MSIO_DIRECTION_INPUT, \
217 .mode = LL_MSIO_MODE_DIGITAL, \
218 .pull = LL_MSIO_PULL_DOWN, \
219 .mux = LL_MSIO_MUX_7, \
260 uint32_t oe_mask = (pin_mask << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
261 uint32_t ie_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
265 MODIFY_REG(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask), (direction !=
LL_MSIO_DIRECTION_INPUT) ? ie_mask : oe_mask);
267 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
270 SET_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
297 uint32_t oe_mask = (pin << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
298 uint32_t ie_mask = (pin << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
299 uint32_t mask = READ_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
300 if (mask == (ie_mask | oe_mask))
332 uint32_t ae_mask = (pin_mask << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
334 GLOBAL_EXCEPTION_DISABLE();
335 MODIFY_REG(AON->MSIO_PAD_CFG_1, ae_mask, ae_n);
336 GLOBAL_EXCEPTION_ENABLE();
360 uint32_t ae_mask = (pin << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
389 uint32_t rtype_mask = (pin_mask << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
391 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
392 GLOBAL_EXCEPTION_DISABLE();
393 MODIFY_REG(AON->MSIO_PAD_CFG_1, rtype_mask, rtype);
394 GLOBAL_EXCEPTION_ENABLE();
398 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
424 if (READ_BITS(AON->MSIO_PAD_CFG_0, (pin << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N))
430 uint32_t rtype_mask = (pin << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
464 uint32_t pos = POSITION_VAL(pin) << 2;
467 GLOBAL_EXCEPTION_DISABLE();
468 CLEAR_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
469 GLOBAL_EXCEPTION_ENABLE();
473 MODIFY_REG(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos, mux << pos);
474 GLOBAL_EXCEPTION_DISABLE();
475 SET_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
476 GLOBAL_EXCEPTION_ENABLE();
506 if(READ_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos))
508 uint32_t pos = POSITION_VAL(pin) << 2;
509 return (READ_BITS(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos) >> pos);
534 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, MCU_SUB_MSIO_REG0_MSIO_C));
555 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, pin_mask) == pin_mask);
570 MODIFY_REG(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN, (port_value << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
584 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN) >> AON_MSIO_PAD_CFG_0_IN_Pos);
605 pin_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN;
606 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, pin_mask) == pin_mask);
627 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
648 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
669 WRITE_REG(AON->MSIO_PAD_CFG_0, (READ_REG(AON->MSIO_PAD_CFG_0) ^ ((pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN)));
uint32_t mux
Definition: gr55xx_ll_msio.h:96
__STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
Set several MSIO pins to input/output direction.
Definition: gr55xx_ll_msio.h:258
__STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
Return gpio direction for a MSIO pin.
Definition: gr55xx_ll_msio.h:295
#define LL_MSIO_MODE_ANALOG
Definition: gr55xx_ll_msio.h:141
#define LL_MSIO_MODE_DIGITAL
Definition: gr55xx_ll_msio.h:142
__STATIC_INLINE uint32_t ll_msio_read_input_port(void)
Return full input data register value of MSIO.
Definition: gr55xx_ll_msio.h:532
#define LL_MSIO_PULL_DOWN
Definition: gr55xx_ll_msio.h:150
__STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified MSIO pins.
Definition: gr55xx_ll_msio.h:667
__STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several MSIO pins to analog/digital mode.
Definition: gr55xx_ll_msio.h:330
struct _ll_msio_init ll_msio_init_t
LL MSIO init Structure definition.
__STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:422
__STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
Return gpio mode for a MSIO pin.
Definition: gr55xx_ll_msio.h:358
uint32_t mode
Definition: gr55xx_ll_msio.h:86
#define LL_MSIO_PULL_NO
Definition: gr55xx_ll_msio.h:148
__STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
Set specified MSIO pins to low level.
Definition: gr55xx_ll_msio.h:646
__STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
Set specified MSIO pins to high level.
Definition: gr55xx_ll_msio.h:625
#define LL_MSIO_MUX_7
Definition: gr55xx_ll_msio.h:163
#define LL_MSIO_DIRECTION_INOUT
Definition: gr55xx_ll_msio.h:135
#define LL_MSIO_DIRECTION_INPUT
Definition: gr55xx_ll_msio.h:133
__STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:504
__STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:385
uint32_t direction
Definition: gr55xx_ll_msio.h:81
__STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
Write output data register of MSIO.
Definition: gr55xx_ll_msio.h:568
__STATIC_INLINE uint32_t ll_msio_read_output_port(void)
Return full output data register value of MSIO.
Definition: gr55xx_ll_msio.h:582
error_status_t ll_msio_init(ll_msio_init_t *p_msio_init)
Initialize MSIO registers according to the specified. parameters in p_msio_init.
void ll_msio_struct_init(ll_msio_init_t *p_msio_init)
Set each field of a ll_msio_init_t type structure to default value.
#define LL_MSIO_DIRECTION_OUTPUT
Definition: gr55xx_ll_msio.h:134
#define LL_MSIO_PULL_UP
Definition: gr55xx_ll_msio.h:149
error_status_t ll_msio_deinit(void)
De-initialize MSIO registers (Registers restored to their default values).
LL MSIO init Structure definition.
Definition: gr55xx_ll_msio.h:77
uint32_t pin
Definition: gr55xx_ll_msio.h:78
__STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:553
uint32_t pull
Definition: gr55xx_ll_msio.h:91
__STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:603
#define LL_MSIO_DIRECTION_NONE
Definition: gr55xx_ll_msio.h:132
__STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:462