Macros | |
| #define | XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE) |
| #define | XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE) |
| #define | XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE) |
| #define | XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE) |
| #define XQSPI_CLOCK_MODE_0 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_1EDGE) |
Inactive state of CLK is low, CLK toggles at the start of first data bit
| #define XQSPI_CLOCK_MODE_1 ((LL_XQSPI_SCPOL_LOW << 1) | LL_XQSPI_SCPHA_2EDGE) |
Inactive state of CLK is low, CLK toggles in the middle of first data bit
| #define XQSPI_CLOCK_MODE_2 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_1EDGE) |
Inactive state of CLK is high, CLK toggles at the start of first data bit
| #define XQSPI_CLOCK_MODE_3 ((LL_XQSPI_SCPOL_HIGH << 1) | LL_XQSPI_SCPHA_2EDGE) |
Inactive state of CLK is high, CLK toggles in the middle of first data bit