Macros | |
| #define | LL_CGC_FRC_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK |
| #define | LL_CGC_FRC_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK |
| #define | LL_CGC_FRC_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK |
| #define | LL_CGC_FRC_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK |
| #define | LL_CGC_FRC_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK |
| #define | LL_CGC_FRC_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK |
| #define | LL_CGC_FRC_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK |
| #define | LL_CGC_FRC_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK |
| #define | LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK |
| #define | LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK |
| #define | LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK |
| #define | LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x0001FF00U) |
| #define | LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x0A01FF00U) |
| #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x0A01FF00U) |
All clock group 2
| #define LL_CGC_FRC_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK |
Hclk for i2c0
| #define LL_CGC_FRC_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK |
Hclk for i2c1
| #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK |
Hclk for i2s
| #define LL_CGC_FRC_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK |
Hclk for qspi0
| #define LL_CGC_FRC_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK |
Hclk for qspi1
| #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK |
Div4 clk for security blocks
| #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x0001FF00U) |
Hclk for serial blocks
| #define LL_CGC_FRC_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK |
Hclk for spim
| #define LL_CGC_FRC_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK |
Hclk for spis
| #define LL_CGC_FRC_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK |
Hclk for uart0
| #define LL_CGC_FRC_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK |
Hclk for uart1
| #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK |
Div4 clk for xf qspi