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52 #ifndef __GR55XX_LL_COMP_H__
53 #define __GR55XX_LL_COMP_H__
112 #define LL_COMP_INPUT_SRC_IO0 (0UL << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
113 #define LL_COMP_INPUT_SRC_IO1 (1UL << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
114 #define LL_COMP_INPUT_SRC_IO2 (2UL << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
115 #define LL_COMP_INPUT_SRC_IO3 (3UL << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
116 #define LL_COMP_INPUT_SRC_IO4 (4UL << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
122 #define LL_COMP_REF_SRC_IO0 (0UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
123 #define LL_COMP_REF_SRC_IO1 (1UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
124 #define LL_COMP_REF_SRC_IO2 (2UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
125 #define LL_COMP_REF_SRC_IO3 (3UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
126 #define LL_COMP_REF_SRC_IO4 (4UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
127 #define LL_COMP_REF_SRC_VBAT (6UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
128 #define LL_COMP_REF_SRC_VREF (7UL << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
149 #define LL_COMP_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
157 #define LL_COMP_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
178 #define LL_COMP_DEFAULT_CONFIG \
180 .channel_p = LL_COMP_CHANNEL_IO0, \
181 .channel_n = LL_COMP_CHANNEL_IO1, \
209 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP);
210 SET_BITS(AON->RF_REG_10, AON_RF_REG_10_WAKE_COMP_EN_Msk);
224 CLEAR_BITS(AON->RF_REG_10, AON_RF_REG_10_WAKE_COMP_EN_Msk);
225 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP);
245 MODIFY_REG(AON->RF_REG_10, AON_RF_REG_10_CHANNEL_SEL_P_Msk, source);
267 MODIFY_REG(AON->RF_REG_10, AON_RF_REG_10_CHANNEL_SEL_N_Msk, source);
283 MODIFY_REG(AON->RF_REG_10, AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Msk, level << AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Pos);
299 MODIFY_REG(AON->RF_REG_10, AON_RF_REG_10_COMP_REF_CTRL_LV_Msk, level << AON_RF_REG_10_COMP_REF_CTRL_LV_Pos);
313 return (READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_PMU_MSIO_COMP) == AON_SLP_EVENT_PMU_MSIO_COMP);
327 GLOBAL_EXCEPTION_DISABLE();
328 CLEAR_BITS(AON->SLP_EVENT, AON_SLP_EVENT_PMU_MSIO_COMP);
329 GLOBAL_EXCEPTION_ENABLE();
uint32_t ref_source
Definition: gr55xx_ll_comp.h:83
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_comp_is_active_flag_it(void)
Indicate if the COMP Interrupt Flag is set or not.
Definition: gr55xx_ll_comp.h:311
struct _ll_comp_init ll_comp_init_t
LL COMP init Structure definition.
uint32_t input_source
Definition: gr55xx_ll_comp.h:78
LL COMP init Structure definition.
Definition: gr55xx_ll_comp.h:77
__STATIC_INLINE void ll_comp_set_vref_lvl(uint32_t level)
Set VREF control level.
Definition: gr55xx_ll_comp.h:297
__STATIC_INLINE void ll_comp_disable(void)
Disable COMP module.
Definition: gr55xx_ll_comp.h:222
error_status_t ll_comp_deinit(void)
De-initialize COMP registers (Registers restored to their default values).
error_status_t ll_comp_init(ll_comp_init_t *p_comp_init)
Initialize COMP registers according to the specified. parameters in p_comp_init.
__STATIC_INLINE void ll_comp_enable(void)
Enable COMP module.
Definition: gr55xx_ll_comp.h:207
void ll_comp_struct_init(ll_comp_init_t *p_comp_init)
Set each field of a ll_comp_init_t type structure to default value.
__STATIC_INLINE void ll_comp_set_vbatt_lvl(uint32_t level)
Set VBATT control level.
Definition: gr55xx_ll_comp.h:281
__STATIC_INLINE void ll_comp_set_ref_src(uint32_t source)
Set channel of COMP reference source.
Definition: gr55xx_ll_comp.h:265
SECTION_RAM_CODE __STATIC_INLINE void ll_comp_clear_flag_it(void)
Clear Interrupt Status flag for COMP.
Definition: gr55xx_ll_comp.h:325
uint32_t ref_value
Definition: gr55xx_ll_comp.h:87
__STATIC_INLINE void ll_comp_set_input_src(uint32_t source)
Set channel of COMP input source.
Definition: gr55xx_ll_comp.h:243