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52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
62 #if defined (UART0) || defined (UART1)
121 #define LL_UART_LSR_OE UART_LSR_OE
122 #define LL_UART_LSR_PE UART_LSR_PE
123 #define LL_UART_LSR_FE UART_LSR_FE
124 #define LL_UART_LSR_BI UART_LSR_BI
125 #define LL_UART_LSR_THRE UART_LSR_THRE
126 #define LL_UART_LSR_TEMT UART_LSR_TEMT
127 #define LL_UART_LSR_RFE UART_LSR_RFE
129 #define LL_UART_IIR_MS UART_IIR_IID_MS
130 #define LL_UART_IIR_NIP UART_IIR_IID_NIP
131 #define LL_UART_IIR_THRE UART_IIR_IID_THRE
132 #define LL_UART_IIR_RDA UART_IIR_IID_RDA
133 #define LL_UART_IIR_RLS UART_IIR_IID_RLS
134 #define LL_UART_IIR_CTO UART_IIR_IID_CTO
136 #define LL_UART_USR_RFF UART_USR_RFF
137 #define LL_UART_USR_RFNE UART_USR_RFNE
138 #define LL_UART_USR_TFE UART_USR_TFE
139 #define LL_UART_USR_TFNF UART_USR_TFNF
146 #define LL_UART_IER_MS UART_IER_EDSSI
147 #define LL_UART_IER_RLS UART_IER_ERLS
148 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME)
149 #define LL_UART_IER_RDA UART_IER_ERBFI
155 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE
156 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD
157 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN
158 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0
159 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1
165 #define LL_UART_DATABITS_5B UART_LCR_DLS_5
166 #define LL_UART_DATABITS_6B UART_LCR_DLS_6
167 #define LL_UART_DATABITS_7B UART_LCR_DLS_7
168 #define LL_UART_DATABITS_8B UART_LCR_DLS_8
174 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1
175 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5
176 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2
182 #define LL_UART_HWCONTROL_NONE 0x00000000U
183 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS)
189 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U
190 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U
191 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U
192 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U
198 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U
199 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U
200 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U
201 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U
207 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U
208 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U
214 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U
215 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U
225 #define LL_UART_DEFAULT_CONFIG \
227 .baud_rate = 9600U, \
228 .data_bits = LL_UART_DATABITS_8B, \
229 .stop_bits = LL_UART_STOPBITS_1, \
230 .parity = LL_UART_PARITY_NONE, \
231 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
253 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
261 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
276 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
285 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
323 register uint32_t uartdiv =
__LL_UART_DIV(peripheral_clock, baud_rate);
325 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
326 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
327 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
328 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
329 WRITE_REG(UARTx->DLF,
__LL_UART_DLF(peripheral_clock, baud_rate));
351 register uint32_t uartdiv = 0x0U;
352 register uint32_t baud = 0x0U;
354 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
355 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
356 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
358 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
360 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
388 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
411 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
437 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
459 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
489 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
515 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
563 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
587 WRITE_REG(UARTx->SRTS, pin_state);
610 return (uint32_t)(READ_REG(UARTx->SRTS));
632 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
651 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
675 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
697 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
716 WRITE_REG(UARTx->SBCR, 0x1U);
735 WRITE_REG(UARTx->SBCR, 0x0U);
754 return READ_REG(UARTx->SBCR);
773 WRITE_REG(UARTx->SFE, 0x1U);
792 WRITE_REG(UARTx->SFE, 0x0U);
811 return READ_REG(UARTx->SFE);
835 WRITE_REG(UARTx->STET, threshold);
858 return (uint32_t)(READ_REG(UARTx->STET));
882 WRITE_REG(UARTx->SRT, threshold);
905 return (uint32_t)(READ_REG(UARTx->SRT));
924 return (uint32_t)(READ_REG(UARTx->TFL));
943 return (uint32_t)(READ_REG(UARTx->RFL));
962 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
981 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
1003 WRITE_REG(UARTx->SRR, UART_SRR_UR);
1028 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1047 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1067 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1086 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1105 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1124 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1144 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1163 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1182 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1201 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1221 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1241 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1269 SET_BITS(UARTx->DLH_IER.IER, mask);
1297 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1325 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1365 return ((uint32_t)READ_REG(UARTx->LSR));
1389 __IO uint32_t tmpreg;
1390 tmpreg = READ_REG(UARTx->LSR);
1410 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1429 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1448 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1467 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1495 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1522 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1547 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1567 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
LL UART init Structure definition.
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
error_status_t ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.