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52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
62 #if defined (SPIM) || defined (SPIS) || defined (QSPI0) || defined (QSPI1)
205 #define LL_SSI_SR_DCOL SSI_STAT_DCOL
206 #define LL_SSI_SR_TXE SSI_STAT_TXE
207 #define LL_SSI_SR_RFF SSI_STAT_RFF
208 #define LL_SSI_SR_RFNE SSI_STAT_RFNE
209 #define LL_SSI_SR_TFE SSI_STAT_TFE
210 #define LL_SSI_SR_TFNF SSI_STAT_TFNF
211 #define LL_SSI_SR_BUSY SSI_STAT_BUSY
218 #define LL_SSI_IM_MST SSI_INTMASK_MSTIM
219 #define LL_SSI_IM_RXF SSI_INTMASK_RXFIM
220 #define LL_SSI_IM_RXO SSI_INTMASK_RXOIM
221 #define LL_SSI_IM_RXU SSI_INTMASK_RXUIM
222 #define LL_SSI_IM_TXO SSI_INTMASK_TXOIM
223 #define LL_SSI_IM_TXE SSI_INTMASK_TXEIM
225 #define LL_SSI_IS_MST SSI_INTSTAT_MSTIS
226 #define LL_SSI_IS_RXF SSI_INTSTAT_RXFIS
227 #define LL_SSI_IS_RXO SSI_INTSTAT_RXOIS
228 #define LL_SSI_IS_RXU SSI_INTSTAT_RXUIS
229 #define LL_SSI_IS_TXO SSI_INTSTAT_TXOIS
230 #define LL_SSI_IS_TXE SSI_INTSTAT_TXEIS
232 #define LL_SSI_RIS_MST SSI_RAW_INTSTAT_MSTIR
233 #define LL_SSI_RIS_RXF SSI_RAW_INTSTAT_RXFIR
234 #define LL_SSI_RIS_RXO SSI_RAW_INTSTAT_RXOIR
235 #define LL_SSI_RIS_RXU SSI_RAW_INTSTAT_RXUIR
236 #define LL_SSI_RIS_TXO SSI_RAW_INTSTAT_TXOIR
237 #define LL_SSI_RIS_TXE SSI_RAW_INTSTAT_TXEIR
243 #define LL_SSI_FRF_SPI 0x00000000UL
244 #define LL_SSI_FRF_DUALSPI (1UL << SSI_CTRL0_SPIFRF_Pos)
245 #define LL_SSI_FRF_QUADSPI (2UL << SSI_CTRL0_SPIFRF_Pos)
251 #define LL_SSI_DATASIZE_4BIT (3UL << SSI_CTRL0_DFS32_Pos)
252 #define LL_SSI_DATASIZE_5BIT (4UL << SSI_CTRL0_DFS32_Pos)
253 #define LL_SSI_DATASIZE_6BIT (5UL << SSI_CTRL0_DFS32_Pos)
254 #define LL_SSI_DATASIZE_7BIT (6UL << SSI_CTRL0_DFS32_Pos)
255 #define LL_SSI_DATASIZE_8BIT (7UL << SSI_CTRL0_DFS32_Pos)
256 #define LL_SSI_DATASIZE_9BIT (8UL << SSI_CTRL0_DFS32_Pos)
257 #define LL_SSI_DATASIZE_10BIT (9UL << SSI_CTRL0_DFS32_Pos)
258 #define LL_SSI_DATASIZE_11BIT (10UL << SSI_CTRL0_DFS32_Pos)
259 #define LL_SSI_DATASIZE_12BIT (11UL << SSI_CTRL0_DFS32_Pos)
260 #define LL_SSI_DATASIZE_13BIT (12UL << SSI_CTRL0_DFS32_Pos)
261 #define LL_SSI_DATASIZE_14BIT (13UL << SSI_CTRL0_DFS32_Pos)
262 #define LL_SSI_DATASIZE_15BIT (14UL << SSI_CTRL0_DFS32_Pos)
263 #define LL_SSI_DATASIZE_16BIT (15UL << SSI_CTRL0_DFS32_Pos)
264 #define LL_SSI_DATASIZE_17BIT (16UL << SSI_CTRL0_DFS32_Pos)
265 #define LL_SSI_DATASIZE_18BIT (17UL << SSI_CTRL0_DFS32_Pos)
266 #define LL_SSI_DATASIZE_19BIT (18UL << SSI_CTRL0_DFS32_Pos)
267 #define LL_SSI_DATASIZE_20BIT (19UL << SSI_CTRL0_DFS32_Pos)
268 #define LL_SSI_DATASIZE_21BIT (20UL << SSI_CTRL0_DFS32_Pos)
269 #define LL_SSI_DATASIZE_22BIT (21UL << SSI_CTRL0_DFS32_Pos)
270 #define LL_SSI_DATASIZE_23BIT (22UL << SSI_CTRL0_DFS32_Pos)
271 #define LL_SSI_DATASIZE_24BIT (23UL << SSI_CTRL0_DFS32_Pos)
272 #define LL_SSI_DATASIZE_25BIT (24UL << SSI_CTRL0_DFS32_Pos)
273 #define LL_SSI_DATASIZE_26BIT (25UL << SSI_CTRL0_DFS32_Pos)
274 #define LL_SSI_DATASIZE_27BIT (26UL << SSI_CTRL0_DFS32_Pos)
275 #define LL_SSI_DATASIZE_28BIT (27UL << SSI_CTRL0_DFS32_Pos)
276 #define LL_SSI_DATASIZE_29BIT (28UL << SSI_CTRL0_DFS32_Pos)
277 #define LL_SSI_DATASIZE_30BIT (29UL << SSI_CTRL0_DFS32_Pos)
278 #define LL_SSI_DATASIZE_31BIT (30UL << SSI_CTRL0_DFS32_Pos)
279 #define LL_SSI_DATASIZE_32BIT (31UL << SSI_CTRL0_DFS32_Pos)
285 #define LL_SSI_MW_CMDSIZE_1BIT 0x00000000UL
286 #define LL_SSI_MW_CMDSIZE_2BIT (1UL << SSI_CTRL0_CFS_Pos)
287 #define LL_SSI_MW_CMDSIZE_3BIT (2UL << SSI_CTRL0_CFS_Pos)
288 #define LL_SSI_MW_CMDSIZE_4BIT (3UL << SSI_CTRL0_CFS_Pos)
289 #define LL_SSI_MW_CMDSIZE_5BIT (4UL << SSI_CTRL0_CFS_Pos)
290 #define LL_SSI_MW_CMDSIZE_6BIT (5UL << SSI_CTRL0_CFS_Pos)
291 #define LL_SSI_MW_CMDSIZE_7BIT (6UL << SSI_CTRL0_CFS_Pos)
292 #define LL_SSI_MW_CMDSIZE_8BIT (7UL << SSI_CTRL0_CFS_Pos)
293 #define LL_SSI_MW_CMDSIZE_9BIT (8UL << SSI_CTRL0_CFS_Pos)
294 #define LL_SSI_MW_CMDSIZE_10BIT (9UL << SSI_CTRL0_CFS_Pos)
295 #define LL_SSI_MW_CMDSIZE_11BIT (10UL << SSI_CTRL0_CFS_Pos)
296 #define LL_SSI_MW_CMDSIZE_12BIT (11UL << SSI_CTRL0_CFS_Pos)
297 #define LL_SSI_MW_CMDSIZE_13BIT (12UL << SSI_CTRL0_CFS_Pos)
298 #define LL_SSI_MW_CMDSIZE_14BIT (13UL << SSI_CTRL0_CFS_Pos)
299 #define LL_SSI_MW_CMDSIZE_15BIT (14UL << SSI_CTRL0_CFS_Pos)
300 #define LL_SSI_MW_CMDSIZE_16BIT (15UL << SSI_CTRL0_CFS_Pos)
306 #define LL_SSI_NORMAL_MODE 0x00000000UL
307 #define LL_SSI_TEST_MODE (1UL << SSI_CTRL0_SRL_Pos)
313 #define LL_SSI_SLAVE_OUTDIS 0x00000000UL
314 #define LL_SSI_SLAVE_OUTEN (1UL << SSI_CTRL0_SLVOE_Pos)
320 #define LL_SSI_FULL_DUPLEX 0x00000000UL
321 #define LL_SSI_SIMPLEX_TX (1UL << SSI_CTRL0_TMOD_Pos)
322 #define LL_SSI_SIMPLEX_RX (2UL << SSI_CTRL0_TMOD_Pos)
323 #define LL_SSI_READ_EEPROM (3UL << SSI_CTRL0_TMOD_Pos)
329 #define LL_SSI_SCPHA_1EDGE 0x00000000UL
330 #define LL_SSI_SCPHA_2EDGE (1UL << SSI_CTRL0_SCPHA_Pos)
336 #define LL_SSI_SCPOL_LOW 0x00000000UL
337 #define LL_SSI_SCPOL_HIGH (1UL << SSI_CTRL0_SCPOL_Pos)
343 #define LL_SSI_PROTOCOL_MOTOROLA 0x00000000UL
344 #define LL_SSI_PROTOCOL_TI (1UL << SSI_CTRL0_FRF_Pos)
345 #define LL_SSI_PROTOCOL_MICROWIRE (2UL << SSI_CTRL0_FRF_Pos)
351 #define LL_SSI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL
352 #define LL_SSI_MICROWIRE_HANDSHAKE_EN (1UL << SSI_MWC_MHS_Pos)
354 #define LL_SSI_MICROWIRE_RX 0x00000000UL
355 #define LL_SSI_MICROWIRE_TX (1UL << SSI_MWC_MDD_Pos)
357 #define LL_SSI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL
358 #define LL_SSI_MICROWIRE_SEQUENTIAL (1UL << SSI_MWC_MWMOD_Pos)
364 #define LL_SSI_SLAVE1 SSI_SE_SLAVE1
365 #define LL_SSI_SLAVE0 SSI_SE_SLAVE0
371 #define LL_SSI_DMA_TX_DIS 0x00000000UL
372 #define LL_SSI_DMA_TX_EN SSI_DMAC_TDMAE
374 #define LL_SSI_DMA_RX_DIS 0x00000000UL
375 #define LL_SSI_DMA_RX_EN SSI_DMAC_RDMAE
381 #define LL_SSI_INSTSIZE_0BIT 0x00000000UL
382 #define LL_SSI_INSTSIZE_4BIT (1UL << SSI_SCTRL0_INSTL_Pos)
383 #define LL_SSI_INSTSIZE_8BIT (2UL << SSI_SCTRL0_INSTL_Pos)
384 #define LL_SSI_INSTSIZE_16BIT (3UL << SSI_SCTRL0_INSTL_Pos)
390 #define LL_SSI_ADDRSIZE_0BIT 0x00000000UL
391 #define LL_SSI_ADDRSIZE_4BIT (1UL << SSI_SCTRL0_ADDRL_Pos)
392 #define LL_SSI_ADDRSIZE_8BIT (2UL << SSI_SCTRL0_ADDRL_Pos)
393 #define LL_SSI_ADDRSIZE_12BIT (3UL << SSI_SCTRL0_ADDRL_Pos)
394 #define LL_SSI_ADDRSIZE_16BIT (4UL << SSI_SCTRL0_ADDRL_Pos)
395 #define LL_SSI_ADDRSIZE_20BIT (5UL << SSI_SCTRL0_ADDRL_Pos)
396 #define LL_SSI_ADDRSIZE_24BIT (6UL << SSI_SCTRL0_ADDRL_Pos)
397 #define LL_SSI_ADDRSIZE_28BIT (7UL << SSI_SCTRL0_ADDRL_Pos)
398 #define LL_SSI_ADDRSIZE_32BIT (8UL << SSI_SCTRL0_ADDRL_Pos)
399 #define LL_SSI_ADDRSIZE_36BIT (9UL << SSI_SCTRL0_ADDRL_Pos)
400 #define LL_SSI_ADDRSIZE_40BIT (10UL << SSI_SCTRL0_ADDRL_Pos)
401 #define LL_SSI_ADDRSIZE_44BIT (11UL << SSI_SCTRL0_ADDRL_Pos)
402 #define LL_SSI_ADDRSIZE_48BIT (12UL << SSI_SCTRL0_ADDRL_Pos)
403 #define LL_SSI_ADDRSIZE_52BIT (13UL << SSI_SCTRL0_ADDRL_Pos)
404 #define LL_SSI_ADDRSIZE_56BIT (14UL << SSI_SCTRL0_ADDRL_Pos)
405 #define LL_SSI_ADDRSIZE_60BIT (15UL << SSI_SCTRL0_ADDRL_Pos)
411 #define LL_SSI_INST_ADDR_ALL_IN_SPI 0x00000000UL
412 #define LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << SSI_SCTRL0_TRANSTYPE_Pos)
413 #define LL_SSI_INST_ADDR_ALL_IN_SPIFRF (2UL << SSI_SCTRL0_TRANSTYPE_Pos)
423 #define LL_SPIM_DEFAULT_CONFIG \
425 .transfer_direction = LL_SSI_FULL_DUPLEX, \
426 .data_size = LL_SSI_DATASIZE_8BIT, \
427 .clock_polarity = LL_SSI_SCPOL_LOW, \
428 .clock_phase = LL_SSI_SCPHA_1EDGE, \
429 .slave_select = LL_SSI_SLAVE0, \
430 .baud_rate = SystemCoreClock / 2000000, \
436 #define LL_SPIS_DEFAULT_CONFIG \
438 .data_size = LL_SSI_DATASIZE_8BIT, \
439 .clock_polarity = LL_SSI_SCPOL_LOW, \
440 .clock_phase = LL_SSI_SCPHA_1EDGE, \
446 #define LL_QSPI_DEFAULT_CONFIG \
448 .transfer_direction = LL_SSI_SIMPLEX_TX, \
449 .instruction_size = LL_SSI_INSTSIZE_8BIT, \
450 .address_size = LL_SSI_ADDRSIZE_24BIT, \
451 .inst_addr_transfer_format = LL_SSI_INST_ADDR_ALL_IN_SPI,\
453 .data_size = LL_SSI_DATASIZE_8BIT, \
454 .clock_polarity = LL_SSI_SCPOL_LOW, \
455 .clock_phase = LL_SSI_SCPHA_1EDGE, \
456 .baud_rate = SystemCoreClock / 1000000, \
457 .rx_sample_delay = 0, \
479 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
487 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
521 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
541 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
561 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN) == (SSI_CTRL0_SSTEN));
585 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SPIFRF, frf);
608 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SPIFRF));
657 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_DFS32, size);
705 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_DFS32));
742 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_CFS, size);
778 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_CFS));
797 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
816 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
835 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SRL) == (SSI_CTRL0_SRL));
854 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
873 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
892 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE) != (SSI_CTRL0_SLVOE));
916 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_TMOD, transfer_direction);
939 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_TMOD));
963 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPOL, clock_polarity);
984 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPOL));
1008 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPHA, clock_phase);
1029 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPHA));
1053 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_FRF, standard);
1075 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_FRF));
1098 MODIFY_REG(SPIx->CTRL1, SSI_CTRL1_NDF, size);
1120 return (uint32_t)(READ_BITS(SPIx->CTRL1, SSI_CTRL1_NDF));
1139 SET_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1159 CLEAR_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1178 return (READ_BITS(SPIx->SSI_EN, SSI_SSIEN_EN) == (SSI_SSIEN_EN));
1197 SET_BITS(SPIx->MWC, SSI_MWC_MHS);
1216 CLEAR_BITS(SPIx->MWC, SSI_MWC_MHS);
1235 return (READ_BITS(SPIx->MWC, SSI_MWC_MHS) == (SSI_MWC_MHS));
1258 MODIFY_REG(SPIx->MWC, SSI_MWC_MDD, transfer_direction);
1280 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MDD));
1303 MODIFY_REG(SPIx->MWC, SSI_MWC_MWMOD, transfer_mode);
1325 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MWMOD));
1348 SET_BITS(SPIx->SE, ss);
1371 CLEAR_BITS(SPIx->SE, ss);
1394 return (READ_BITS(SPIx->SE, ss) == ss);
1415 WRITE_REG(SPIx->BAUD, baud_rate);
1434 return (uint32_t)(READ_BITS(SPIx->BAUD, SSI_BAUD_SCKDIV));
1454 WRITE_REG(SPIx->TX_FTL, threshold);
1473 return (uint32_t)(READ_BITS(SPIx->TX_FTL, SSI_TXFTL_TFT));
1493 WRITE_REG(SPIx->RX_FTL, threshold);
1512 return (uint32_t)(READ_BITS(SPIx->RX_FTL, SSI_RXFTL_RFT));
1531 return (uint32_t)(READ_BITS(SPIx->TX_FL, SSI_TXFL_TXTFL));
1550 return (uint32_t)(READ_BITS(SPIx->RX_FL, SSI_RXFL_RXTFL));
1569 return (uint32_t)(READ_BITS(SPIx->ID, SSI_IDCODE_ID));
1588 return (uint32_t)(READ_BITS(SPIx->VERSION_ID, SSI_COMP_VERSION));
1621 SET_BITS(SPIx->INTMASK, mask);
1648 CLEAR_BITS(SPIx->INTMASK, mask);
1674 return (READ_BITS(SPIx->INTMASK, mask) == mask);
1706 return (uint32_t)(READ_REG(SPIx->STAT));
1745 return (READ_BITS(SPIx->STAT, flag) == (flag));
1770 return (uint32_t)(READ_REG(SPIx->INTSTAT));
1801 return (READ_BITS(SPIx->INTSTAT, flag) == flag);
1826 return (uint32_t)(READ_REG(SPIx->RAW_INTSTAT));
1846 __IOM uint32_t tmpreg;
1847 tmpreg = SPIx->TXOIC;
1868 __IOM uint32_t tmpreg;
1869 tmpreg = SPIx->RXOIC;
1890 __IOM uint32_t tmpreg;
1891 tmpreg = SPIx->RXUIC;
1912 __IOM uint32_t tmpreg;
1913 tmpreg = SPIx->MSTIC;
1934 __IOM uint32_t tmpreg;
1935 tmpreg = SPIx->INTCLR;
1961 SET_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1980 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1999 return (READ_BITS(SPIx->DMAC, SSI_DMAC_TDMAE) == (SSI_DMAC_TDMAE));
2018 SET_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
2037 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
2056 return (READ_BITS(SPIx->DMAC, SSI_DMAC_RDMAE) == (SSI_DMAC_RDMAE));
2076 WRITE_REG(SPIx->DMA_TDL, threshold);
2095 return (uint32_t)(READ_BITS(SPIx->DMA_TDL, SSI_DMATDL_DMATDL));
2115 WRITE_REG(SPIx->DMA_RDL, threshold);
2134 return (uint32_t)(READ_BITS(SPIx->DMA_RDL, SSI_DMARDL_DMARDL));
2160 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
2180 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
2200 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
2219 return (uint8_t)(READ_REG(SPIx->DATA));
2238 return (uint16_t)(READ_REG(SPIx->DATA));
2257 return (uint32_t)(READ_REG(SPIx->DATA));
2278 WRITE_REG(SPIx->RX_SAMPLE_DLY, delay);
2298 return (uint32_t)(READ_REG(SPIx->RX_SAMPLE_DLY));
2319 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES, wait_cycles << SSI_SCTRL0_WAITCYCLES_Pos);
2339 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES) >> SSI_SCTRL0_WAITCYCLES_Pos);
2364 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL, size);
2388 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL));
2425 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL, size);
2461 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL));
2485 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE, format);
2508 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE));
__STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
Disable slave select toggle.
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
Get transfer mode in Microwire mode.
error_status_t ll_spis_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
Enable Handshake in Microwire mode.
error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
__STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
Disable Handshake in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
SPIS init structures definition.
__STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
Get number of wait cycles in Dual/Quad SPI mode.
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
uint32_t instruction_size
__STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
Clear all error flag.
__STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
Get data frame format for transmitting/receiving the data.
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
Get Rx sample delay.
LL SPIM init structures definition.
__STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
__STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
Enable slave select toggle.
__STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
Get FIFO reception Level.
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
__STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
__STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
uint32_t inst_addr_transfer_format
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
Check if DMA Rx is enabled.
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
__STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
Disable SPI test mode.
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
Get baud rate prescaler.
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
Check if slave output is enabled.
__STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode.
__STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
Get SPI status.
__STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
Get the number of data frames to be continuously received.
__STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
Set frame data size.
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
__STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
__STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
QSPI init structures definition.
uint32_t transfer_direction
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
__STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
Enable DMA Tx.
__STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
__STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
Disable DMA Rx.
error_status_t ll_qspi_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
Get ID code.
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode instruction length in bits.
__STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
Enable SPI peripheral.
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
__STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
Read 32-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
__STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
Enable SPI test mode.
__STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
Disable slave select.
__STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
Get SPI raw interrupt flags.
__STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
Get clock polarity.
__STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
__STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
__STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
__STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
Get serial protocol used.
__STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
__STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
__STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
Get frame data size.
__STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
Get SPI interrupt flags.
__STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
__STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
Clear multi-master error flag.
__STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
Check active flag.
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
Check if SPI test mode is enabled.
uint32_t transfer_direction
__STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
Get IP version.
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
Check if slave select toggle is enabled.
__STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
__STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
__STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
__STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
Enable DMA Rx.
error_status_t ll_spim_deinit(ssi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
__STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
Clear receive FIFO underflow error flag.
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
Enable slave select.
__STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
Disable slave output.
__STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
Enable slave output.
__STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
Get Dual/Quad SPI mode address length in bits.
error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
__STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
Get clock phase.