51 #ifndef __GR55XX_LL_HMAC_H__
52 #define __GR55XX_LL_HMAC_H__
101 #define LL_HMAC_FLAG_DATAREADY_SHA HMAC_STATUS_DATAREADY_SHA
102 #define LL_HMAC_FLAG_DATAREADY_HMAC HMAC_STATUS_DATAREADY_HMAC
103 #define LL_HMAC_FLAG_DMA_MESSAGEDONE HMAC_STATUS_MESSAGEDONE_DMA
104 #define LL_HMAC_FLAG_DMA_DONE HMAC_STATUS_TRANSDONE_DMA
105 #define LL_HMAC_FLAG_DMA_ERR HMAC_STATUS_TRANSERR_DMA
106 #define LL_HMAC_FLAG_KEY_VALID HMAC_STATUS_KEYVALID
112 #define LL_HMAC_HASH_STANDARD 0x00000000U
113 #define LL_HMAC_HASH_USER (1UL << HMAC_CONFIG_ENABLE_USERHASH)
119 #define LL_HMAC_CALCULATETYPE_HMAC 0x00000000U
120 #define LL_HMAC_CALCULATETYPE_SHA (1UL << HMAC_CONFIG_CALCTYPE_Pos)
126 #define LL_HMAC_KEYTYPE_MCU 0x00000000U
127 #define LL_HMAC_KEYTYPE_AHB (1UL << HMAC_CONFIG_KEYTYPE_Pos)
128 #define LL_HMAC_KEYTYPE_KRAM (2UL << HMAC_CONFIG_KEYTYPE_Pos)
134 #define LL_HMAC_DMA_TRANSIZE_MIN (1)
135 #define LL_HMAC_DMA_TRANSIZE_MAX (512)
156 #define LL_HMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
164 #define LL_HMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
197 SET_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE);
216 CLEAR_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE);
235 return (READ_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE) == (HMAC_CTRL_ENABLE));
254 SET_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA);
273 CLEAR_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA);
292 return (READ_BITS(HMACx->CTRL, HMAC_CTRL_START_DMA) == (HMAC_CTRL_START_DMA));
311 SET_BITS(HMACx->CTRL, HMAC_CTRL_ENABLE_RKEY);
330 SET_BITS(HMACx->CTRL, HMAC_CTRL_LASTTRANSFER);
349 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH);
368 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH);
387 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_ENABLE_USERHASH) == (HMAC_CONFIG_ENABLE_USERHASH));
406 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN);
425 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN);
444 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_ENDIAN) == (HMAC_CONFIG_ENDIAN));
467 MODIFY_REG(HMACx->CONFIG, HMAC_CONFIG_KEYTYPE, type);
489 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_KEYTYPE));
508 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE);
527 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE);
546 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_CALCTYPE) == (HMAC_CONFIG_CALCTYPE));
565 SET_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE);
584 CLEAR_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE);
603 return (READ_BITS(HMACx->CONFIG, HMAC_CONFIG_PRIVATE) == (HMAC_CONFIG_PRIVATE));
628 SET_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE);
647 CLEAR_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE);
666 return (READ_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_ENABLE) == (HMAC_INTERRUPT_ENABLE));
691 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_DATAREADY_SHA) == HMAC_STATUS_DATAREADY_SHA);
710 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_DATAREADY_HMAC) == HMAC_STATUS_DATAREADY_HMAC);
729 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_MESSAGEDONE_DMA) == HMAC_STATUS_MESSAGEDONE_DMA);
748 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_TRANSDONE_DMA) == HMAC_STATUS_TRANSDONE_DMA);
767 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_TRANSERR_DMA) == HMAC_STATUS_TRANSERR_DMA);
786 return (READ_BITS(HMACx->STATUS, HMAC_STATUS_KEYVALID) == HMAC_STATUS_KEYVALID);
805 return (READ_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_DONE) == HMAC_INTERRUPT_DONE);
824 CLEAR_BITS(HMACx->INTERRUPT, HMAC_INTERRUPT_DONE);
850 MODIFY_REG(HMACx->TRAN_SIZE, HMAC_TRANSIZE, (block << 6) - 1);
869 return ((READ_BITS(HMACx->TRAN_SIZE, HMAC_TRANSIZE) + 1) >> 6);
889 WRITE_REG(HMACx->RSTART_ADDR, address);
908 return (READ_REG(HMACx->RSTART_ADDR));
928 WRITE_REG(HMACx->WSTART_ADDR, address);
947 return (READ_REG(HMACx->WSTART_ADDR));
973 WRITE_REG(HMACx->USER_HASH[0], hash);
993 WRITE_REG(HMACx->USER_HASH[1], hash);
1013 WRITE_REG(HMACx->USER_HASH[2], hash);
1033 WRITE_REG(HMACx->USER_HASH[3], hash);
1053 WRITE_REG(HMACx->USER_HASH[4], hash);
1073 WRITE_REG(HMACx->USER_HASH[5], hash);
1093 WRITE_REG(HMACx->USER_HASH[6], hash);
1113 WRITE_REG(HMACx->USER_HASH[7], hash);
1132 return (READ_REG(HMACx->FIFO_OUT));
1152 WRITE_REG(HMACx->MESSAGE_FIFO, data);
1172 WRITE_REG(HMACx->KEY[0], key);
1192 WRITE_REG(HMACx->KEY[1], key);
1212 WRITE_REG(HMACx->KEY[2], key);
1232 WRITE_REG(HMACx->KEY[3], key);
1252 WRITE_REG(HMACx->KEY[4], key);
1272 WRITE_REG(HMACx->KEY[5], key);
1292 WRITE_REG(HMACx->KEY[6], key);
1312 WRITE_REG(HMACx->KEY[7], key);
1332 WRITE_REG(HMACx->KEY_ADDR, address);
1351 return (READ_REG(HMACx->KEY_ADDR));
1371 WRITE_REG(HMACx->KPORT_MASK, mask);