gr55xx_ll_efuse.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_efuse.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of eFuse LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_EFUSE EFUSE
47 * @brief eFuse LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_EFUSE_H__
53 #define __GR55xx_LL_EFUSE_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (EFUSE)
63
64 /**
65 * @defgroup EFUSE_LL_MACRO Defines
66 * @{
67 */
68
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup EFUSE_LL_Exported_Constants EFUSE Exported Constants
71 * @{
72 */
73
74 /** @defgroup EFUSE_LL_EC_OPERATION EFUSE Operation Defines
75 * @brief Operation defines which can be used with LL_EFUSE_WriteReg function
76 * @{
77 */
78 #define LL_EFUSE_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM /**< Read fwkay and rootkey from eFuse, and write to keyram */
79 #define LL_EFUSE_READ_TRIM EFUSE_OPER_READ_TRIM /**< Read analog trim from eFuse */
80 #define LL_EFUSE_CRC_CHECK EFUSE_OPER_CRC_CHECK /**< Read the special eFuse addr, and calculate CRC value */
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK /**< Read the whole eFuse value, and check this value with 0 */
82 #define LL_EFUSE_TEST_READ EFUSE_OPER_RD_TEST_MODE /**< Read eFuse test mode from eFuse */
83 /** @} */
84
85 /** @defgroup EFUSE_LL_EC_GET_FLAG Get Flags Defines
86 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
87 * @{
88 */
89 #define LL_EFUSE_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY /**< Write keyram operation is in processing */
90 #define LL_EFUSE_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE /**< Read trim from eFuse has done */
91 #define LL_EFUSE_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE /**< eFuse CRC check done */
92 #define LL_EFUSE_CRC_CHECK_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS /**< CRC check success */
93 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE /**< eFuse initial value check done */
94 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS /**< eFuse initial value check success */
95 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE /**< eFuse one word write done */
96 #define LL_EFUSE_TEST_DONE EFUSE_STATUS_TEST_MODE_DONE /**< Read from eFuse has done in test mode */
97 /** @} */
98
99 /** @defgroup EFUSE_LL_EC_GET_CTL_FLAG Get Power Controller Flags Defines
100 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
101 * @{
102 */
103 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE /**< eFuse power enable done */
104 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE /**< eFuse power disable done */
105 /** @} */
106
107 /** @} */
108
109 /* Exported macro ------------------------------------------------------------*/
110 /** @defgroup EFUSE_LL_Exported_Macros EFUSE Exported Macros
111 * @{
112 */
113
114 /** @defgroup EFUSE_LL_EM_WRITE_READ Common Write and read registers Macros
115 * @{
116 */
117
118 /**
119 * @brief Write a value in eFuse register
120 * @param __instance__ eFuse instance
121 * @param __REG__ Register to be written
122 * @param __VALUE__ Value to be written in the register
123 * @retval None
124 */
125 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
126
127 /**
128 * @brief Read a value in eFuse register
129 * @param __instance__ eFuse instance
130 * @param __REG__ Register to be read
131 * @retval Register value
132 */
133 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
134
135 /** @} */
136
137 /** @} */
138
139 /** @} */
140
141 /* Exported functions --------------------------------------------------------*/
142 /** @defgroup EFUSE_LL_DRIVER_FUNCTIONS Functions
143 * @{
144 */
145
146 /** @defgroup EFUSE_LL_EF_Configuration Configuration functions
147 * @{
148 */
149
150 /**
151 * @brief Set eFuse program time
152 *
153 * \rst
154 * +----------------------+-----------------------------------+
155 * | Register | BitsName |
156 * +======================+===================================+
157 * | TPGM | TIME |
158 * +----------------------+-----------------------------------+
159 * \endrst
160 *
161 * @param EFUSEx eFuse instance
162 * @param time This parameter can be one of the following values: 0 ~ 0xFFF
163 * @retval None
164 */
165 __STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
166 {
167 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
168 }
169
170 /**
171 * @brief Get eFuse program time
172 *
173 * \rst
174 * +----------------------+-----------------------------------+
175 * | Register | BitsName |
176 * +======================+===================================+
177 * | TPGM | TIME |
178 * +----------------------+-----------------------------------+
179 * \endrst
180 *
181 * @param EFUSEx eFuse instance
182 * @retval Returned value can be one of the following values: 0 ~ 0xFFF
183 */
184 __STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
185 {
186 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
187 }
188
189 /**
190 * @brief Enable read address through APB bus be a main address or backup address
191 *
192 * \rst
193 * +----------------------+-----------------------------------+
194 * | Register | BitsName |
195 * +======================+===================================+
196 * | TPGM | MAIN_OR_BACKUP |
197 * +----------------------+-----------------------------------+
198 * \endrst
199 *
200 * @param EFUSEx eFuse instance
201 * @retval None
202 */
203 __STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
204 {
205 SET_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
206 }
207
208 /**
209 * @brief Disable read address through APB bus be a main address or backup address
210 *
211 * \rst
212 * +----------------------+-----------------------------------+
213 * | Register | BitsName |
214 * +======================+===================================+
215 * | TPGM | MAIN_OR_BACKUP |
216 * +----------------------+-----------------------------------+
217 * \endrst
218 *
219 * @param EFUSEx eFuse instance
220 * @retval None
221 */
222 __STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
223 {
224 CLEAR_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
225 }
226
227 /**
228 * @brief Check if read address through APB bus be a main address or backup address is enabled
229 *
230 * \rst
231 * +----------------------+-----------------------------------+
232 * | Register | BitsName |
233 * +======================+===================================+
234 * | TPGM | MAIN_OR_BACKUP |
235 * +----------------------+-----------------------------------+
236 * \endrst
237 *
238 * @param EFUSEx eFuse instance
239 * @retval State of bit (1 or 0).
240 */
241 __STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
242 {
243 return (READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP) == (EFUSE_TPGM_MAIN_OR_BACKUP));
244 }
245
246 /**
247 * @brief Set CRC check length
248 *
249 * \rst
250 * +----------------------+-----------------------------------+
251 * | Register | BitsName |
252 * +======================+===================================+
253 * | TPGM | CRC_CHECK_LEN |
254 * +----------------------+-----------------------------------+
255 * \endrst
256 *
257 * @param EFUSEx eFuse instance
258 * @param length This parameter can be one of the following values: 1 ~ 60
259 * @retval None
260 */
261 __STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
262 {
263 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN, length << EFUSE_TPGM_CRC_CHECK_LEN_Pos);
264 }
265
266 /**
267 * @brief Get CRC check length
268 *
269 * \rst
270 * +----------------------+-----------------------------------+
271 * | Register | BitsName |
272 * +======================+===================================+
273 * | TPGM | CRC_CHECK_LEN |
274 * +----------------------+-----------------------------------+
275 * \endrst
276 *
277 * @param EFUSEx eFuse instance
278 * @retval Returned value can be one of the following values: 1 ~ 60
279 */
280 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
281 {
282 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN) >> EFUSE_TPGM_CRC_CHECK_LEN_Pos);
283 }
284
285 /**
286 * @brief Set the interval number of clk cycles between two bit fuse
287 *
288 * \rst
289 * +----------------------+-----------------------------------+
290 * | Register | BitsName |
291 * +======================+===================================+
292 * | TPGM | WRITE_INTERVAL |
293 * +----------------------+-----------------------------------+
294 * \endrst
295 *
296 * @param EFUSEx eFuse instance
297 * @param interval This parameter can be one of the following values: 0 ~ 0xFF
298 * @retval None
299 */
300 __STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
301 {
302 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
303 }
304
305 /**
306 * @brief Get the interval number of clk cycles between two bit fuse
307 *
308 * \rst
309 * +----------------------+-----------------------------------+
310 * | Register | BitsName |
311 * +======================+===================================+
312 * | TPGM | WRITE_INTERVAL |
313 * +----------------------+-----------------------------------+
314 * \endrst
315 *
316 * @param EFUSEx eFuse instance
317 * @retval Returned value can be one of the following values: 0 ~ 0xFF
318 */
319 __STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
320 {
321 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
322 }
323
324 /**
325 * @brief Enable eFuse PGENB sigal
326 *
327 * \rst
328 * +----------------------+-----------------------------------+
329 * | Register | BitsName |
330 * +======================+===================================+
331 * | PGENB | PGENB_SIG |
332 * +----------------------+-----------------------------------+
333 * \endrst
334 *
335 * @param EFUSEx eFuse instance
336 * @retval None
337 */
338 __STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
339 {
340 SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
341 }
342
343 /**
344 * @brief Disable eFuse PGENB sigal
345 *
346 * \rst
347 * +----------------------+-----------------------------------+
348 * | Register | BitsName |
349 * +======================+===================================+
350 * | PGENB | PGENB_SIG |
351 * +----------------------+-----------------------------------+
352 * \endrst
353 *
354 * @param EFUSEx eFuse instance
355 * @retval None
356 */
357 __STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
358 {
359 CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
360 }
361
362 /**
363 * @brief Check if eFuse PGENB sigal is enabled
364 *
365 * \rst
366 * +----------------------+-----------------------------------+
367 * | Register | BitsName |
368 * +======================+===================================+
369 * | PGENB | PGENB_SIG |
370 * +----------------------+-----------------------------------+
371 * \endrst
372 *
373 * @param EFUSEx eFuse instance
374 * @retval State of bit (1 or 0).
375 */
376 __STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
377 {
378 return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
379 }
380
381 /**
382 * @brief Get test mode
383 * @note This bit should be read only.
384 *
385 * \rst
386 * +----------------------+-----------------------------------+
387 * | Register | BitsName |
388 * +======================+===================================+
389 * | TEST_MODE | TEST_MODE |
390 * +----------------------+-----------------------------------+
391 * \endrst
392 *
393 * @param EFUSEx eFuse instance
394 * @retval Returned value can be one of the following values: 0xFFFF
395 */
396 __STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
397 {
398 return (uint32_t)(READ_BITS(EFUSEx->TEST_MODE, EFUSE_TEST_MODE));
399 }
400
401 /**
402 * @brief Set eFuse operation mode
403 *
404 * \rst
405 * +----------------------+-----------------------------------+
406 * | Register | BitsName |
407 * +======================+===================================+
408 * | OPERATION | WRITE_KEYRAM |
409 * +----------------------+-----------------------------------+
410 * \endrst
411 * OPERATION | INIT_CHECK
412 * OPERATION | CRC_CHECK
413 * OPERATION | READ_TRIM
414 * OPERATION | RD_TEST_MODE
415 *
416 * @param EFUSEx eFuse instance
417 * @param mode This parameter can be one of the following values:
418 * @arg @ref LL_EFUSE_WRITE_KEYRAM
419 * @arg @ref LL_EFUSE_READ_TRIM
420 * @arg @ref LL_EFUSE_CRC_CHECK
421 * @arg @ref LL_EFUSE_INIT_CHECK
422 * @arg @ref LL_EFUSE_TEST_READ
423 * @retval None
424 */
425 __STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
426 {
427 WRITE_REG(EFUSEx->OPERATION, mode);
428 }
429
430 /**
431 * @brief Check active flag
432 *
433 * \rst
434 * +----------------------+-----------------------------------+
435 * | Register | BitsName |
436 * +======================+===================================+
437 * | STAT | WRITE_KEYRAM_BUSY |
438 * +----------------------+-----------------------------------+
439 * \endrst
440 * STAT | READ_TRIM_DONE
441 * STAT | TRIM_CRC_SUCCESS
442 * STAT | INIT_DONE
443 * STAT | INIT_SUCCESS
444 * STAT | CRC_CHECK_DONE
445 * STAT | WRITE_DONE
446 * STAT | TEST_MODE_DONE
447 *
448 * @param EFUSEx eFuse instance
449 * @param flag This parameter can be one of the following values:
450 * @arg @ref LL_EFUSE_WRITE_KEYRAM_BUSY
451 * @arg @ref LL_EFUSE_READ_TRIM_DONE
452 * @arg @ref LL_EFUSE_CRC_CHECK_DONE
453 * @arg @ref LL_EFUSE_CRC_CHECK_SUCCESS
454 * @arg @ref LL_EFUSE_INIT_CHECK_DONE
455 * @arg @ref LL_EFUSE_INIT_CHECK_SUCCESS
456 * @arg @ref LL_EFUSE_WRITE_DONE
457 * @arg @ref LL_EFUSE_TEST_DONE
458 * @retval State of bit (1 or 0).
459 */
460 __STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
461 {
462 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
463 }
464
465 /**
466 * @brief Set key mask
467 *
468 * \rst
469 * +----------------------+-----------------------------------+
470 * | Register | BitsName |
471 * +======================+===================================+
472 * | KEY_MASK | KEY_MASK |
473 * +----------------------+-----------------------------------+
474 * \endrst
475 *
476 * @param EFUSEx eFuse instance
477 * @param mask Key mask
478 * @retval None
479 */
480 __STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
481 {
482 WRITE_REG(EFUSEx->KEY_MASK, mask);
483 }
484
485 /**
486 * @brief Get key mask
487 *
488 * \rst
489 * +----------------------+-----------------------------------+
490 * | Register | BitsName |
491 * +======================+===================================+
492 * | KEY_MASK | KEY_MASK |
493 * +----------------------+-----------------------------------+
494 * \endrst
495 *
496 * @param EFUSEx eFuse instance
497 * @retval None
498 */
499 __STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
500 {
501 return (uint32_t)(READ_REG(EFUSEx->KEY_MASK));
502 }
503
504 /**
505 * @brief Set CRC check start address
506 * @note The address must be a main info address.
507 *
508 * \rst
509 * +----------------------+-----------------------------------+
510 * | Register | BitsName |
511 * +======================+===================================+
512 * | CRC_ADDR | START_CHECK_ADDR |
513 * +----------------------+-----------------------------------+
514 * \endrst
515 *
516 * @param EFUSEx eFuse instance
517 * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
518 * @retval None
519 */
520 __STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
521 {
522 WRITE_REG(EFUSEx->CRC_ADDR, address);
523 }
524
525 /**
526 * @brief Get CRC check start address
527 *
528 * \rst
529 * +----------------------+-----------------------------------+
530 * | Register | BitsName |
531 * +======================+===================================+
532 * | CRC_ADDR | START_CHECK_ADDR |
533 * +----------------------+-----------------------------------+
534 * \endrst
535 *
536 * @param EFUSEx eFuse instance
537 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
538 */
539 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
540 {
541 return (uint32_t)(READ_REG(EFUSEx->CRC_ADDR));
542 }
543
544 /**
545 * @brief Get CRC check results
546 *
547 * \rst
548 * +----------------------+-----------------------------------+
549 * | Register | BitsName |
550 * +======================+===================================+
551 * | CRC_OUTPUT | OUTPUT_VALUE |
552 * +----------------------+-----------------------------------+
553 * \endrst
554 *
555 * @param EFUSEx eFuse instance
556 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
557 */
558 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
559 {
560 return (uint32_t)(READ_REG(EFUSEx->CRC_OUTPUT));
561 }
562
563 /**
564 * @brief Set read trim start address
565 * @note The address must be a main info address.
566 *
567 * \rst
568 * +----------------------+-----------------------------------+
569 * | Register | BitsName |
570 * +======================+===================================+
571 * | TRIM_ADDR | START_ADDR |
572 * +----------------------+-----------------------------------+
573 * \endrst
574 *
575 * @param EFUSEx eFuse instance
576 * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
577 * @retval None
578 */
579 __STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
580 {
581 WRITE_REG(EFUSEx->TRIM_ADDR, address);
582 }
583
584 /**
585 * @brief Get read trim start address
586 *
587 * \rst
588 * +----------------------+-----------------------------------+
589 * | Register | BitsName |
590 * +======================+===================================+
591 * | TRIM_ADDR | START_ADDR |
592 * +----------------------+-----------------------------------+
593 * \endrst
594 *
595 * @param EFUSEx eFuse instance
596 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
597 */
598 __STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
599 {
600 return (uint32_t)(READ_REG(EFUSEx->TRIM_ADDR));
601 }
602
603 /**
604 * @brief Set read trim length
605 *
606 * \rst
607 * +----------------------+-----------------------------------+
608 * | Register | BitsName |
609 * +======================+===================================+
610 * | TRIM_LEN | LENGTH |
611 * +----------------------+-----------------------------------+
612 * \endrst
613 *
614 * @param EFUSEx eFuse instance
615 * @param length This parameter can be one of the following values: 1 ~ 14
616 * @retval None
617 */
618 __STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
619 {
620 WRITE_REG(EFUSEx->TRIM_LEN, length & EFUSE_TRIM_LENGTH);
621 }
622
623 /**
624 * @brief Get read trim length
625 *
626 * \rst
627 * +----------------------+-----------------------------------+
628 * | Register | BitsName |
629 * +======================+===================================+
630 * | TRIM_LEN | LENGTH |
631 * +----------------------+-----------------------------------+
632 * \endrst
633 *
634 * @param EFUSEx eFuse instance
635 * @retval Returned value can be one of the following values: 1 ~ 14
636 */
637 __STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
638 {
639 return (uint32_t)(READ_REG(EFUSEx->TRIM_LEN) & EFUSE_TRIM_LENGTH);
640 }
641
642 /**
643 * @brief Get trim value
644 *
645 * \rst
646 * +----------------------+-----------------------------------+
647 * | Register | BitsName |
648 * +======================+===================================+
649 * | TRIM[n] | TRIM |
650 * +----------------------+-----------------------------------+
651 * \endrst
652 *
653 * @param EFUSEx eFuse instance
654 * @param indx index of trim value registers: 0 ~ 13
655 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
656 */
657 __STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
658 {
659 return (uint32_t)(READ_REG(EFUSEx->TRIM[indx]));
660 }
661
662 /**
663 * @brief eFuse v1.1 power on.
664 *
665 * \rst
666 * +----------------------+-----------------------------------+
667 * | Register | BitsName |
668 * +======================+===================================+
669 * | TPGM | CRC_CHECK_LEN |
670 * +----------------------+-----------------------------------+
671 * \endrst
672 *
673 * @retval None
674 */
675 __STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
676 {
677 SET_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
678 }
679
680 /**
681 * @brief eFuse v1.1 power off.
682 *
683 * \rst
684 * +----------------------+-----------------------------------+
685 * | Register | BitsName |
686 * +======================+===================================+
687 * | TPGM | CRC_CHECK_LEN |
688 * +----------------------+-----------------------------------+
689 * \endrst
690 *
691 * @retval None
692 */
693 __STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
694 {
695 CLEAR_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
696 }
697
698 /**
699 * @brief Set Efulse power controller timing pararmeter.
700 *
701 * Register |BitsName
702 * ----------|--------
703 * PWR_DELTA| PWR_DELTA_0
704 * PWR_DELTA| PWR_DELTA_1
705 * PWR_DELTA| PWR_DELTA_2
706 *
707 * @retval None
708 */
709 __STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
710 {
711 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[0], vddq_0 + (vddq_1 << 16));
712 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[1], vddq_2);
713 }
714
715 /**
716 * @brief Power sequencer begin.
717 *
718 * Register |BitsName
719 * -----------|--------
720 * PWR_CTRL0 | CTRL_ENABLE
721 * PWR_CTRL0 | SEQR_BEGIN
722 *
723 * @retval None
724 */
725 __STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
726 {
727 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_BGN | MCU_SUB_EFUSE_PWR_CTL0_EN);
728 }
729
730 /**
731 * @brief Power sequencer begin.
732 *
733 * Register |BitsName
734 * -----------|--------
735 * PWR_CTRL0 | CTRL_ENABLE
736 * PWR_CTRL0 | SEQR_STOP
737 *
738 * @retval None
739 */
740 __STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
741 {
742 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_STP | MCU_SUB_EFUSE_PWR_CTL0_EN);
743 }
744
745 /**
746 * @brief Power sequencer begin.
747 *
748 * Register |BitsName
749 * --------- -|--------
750 * PWR_CTRL0 | CTRL_ENABLE
751 * PWR_CTRL0 | SEQR_BEGIN
752 * PWR_CTRL0 | SEQR_STOP
753 *
754 * @retval None
755 */
756 __STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
757 {
758 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], 0);
759 }
760
761 /**
762 * @brief Check power controller active flag
763 *
764 * \rst
765 * +----------------------+-----------------------------------+
766 * | Register | BitsName |
767 * +======================+===================================+
768 * | PWR_CTRL1 | EN_DONE |
769 * +----------------------+-----------------------------------+
770 * \endrst
771 * PWR_CTRL1 | DIS_DONE
772 *
773 * @param EFUSEx eFuse instance
774 * @param flag This parameter can be one of the following values:
775 * @arg @ref LL_EFUSE_PWR_CTL_EN_DONE
776 * @arg @ref LL_EFUSE_PWR_CTL_DIS_DONE
777 * @retval State of bit (1 or 0).
778 */
779 __STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
780 {
781 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL[1], flag) == (flag));
782 }
783
784
785
786 /** @} */
787
788 /** @} */
789
790 #endif /* EFUSE */
791
792 #ifdef __cplusplus
793 }
794 #endif
795
796 #endif /* __GR55xx_LL_EFUSE_H__ */
797
798 /** @} */
799
800 /** @} */
801
802 /** @} */
ll_efuse_disable_controller_power
__STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:756
ll_efuse_get_trim_value
__STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
Get trim value.
Definition: gr55xx_ll_efuse.h:657
ll_efuse_get_crc_check_addr
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
Get CRC check start address.
Definition: gr55xx_ll_efuse.h:539
ll_efuse_get_trim_addr
__STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
Get read trim start address.
Definition: gr55xx_ll_efuse.h:598
ll_efuse_enable_controller_power_begin
__STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:725
ll_efuse_set_crc_check_addr
__STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set CRC check start address.
Definition: gr55xx_ll_efuse.h:520
ll_efuse_get_test_mode
__STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
Get test mode.
Definition: gr55xx_ll_efuse.h:396
ll_efuse_set_trim_length
__STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
Set read trim length.
Definition: gr55xx_ll_efuse.h:618
ll_efuse_disable_main_backup
__STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
Disable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:222
ll_efuse_get_trim_length
__STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
Get read trim length.
Definition: gr55xx_ll_efuse.h:637
ll_efuse_set_key_mask
__STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
Set key mask.
Definition: gr55xx_ll_efuse.h:480
ll_efuse_disable_pgenb
__STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
Disable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:357
ll_efuse_is_enabled_main_backup
__STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
Check if read address through APB bus be a main address or backup address is enabled.
Definition: gr55xx_ll_efuse.h:241
ll_efuse_set_crc_check_len
__STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
Set CRC check length.
Definition: gr55xx_ll_efuse.h:261
ll_efuse_enable_power
__STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power on.
Definition: gr55xx_ll_efuse.h:675
ll_efuse_enable_controller_power_stop
__STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
Power sequencer begin.
Definition: gr55xx_ll_efuse.h:740
ll_efuse_get_key_mask
__STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
Get key mask.
Definition: gr55xx_ll_efuse.h:499
ll_efuse_is_enabled_pgenb
__STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
Check if eFuse PGENB sigal is enabled.
Definition: gr55xx_ll_efuse.h:376
ll_efuse_get_interval
__STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
Get the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:319
ll_efuse_get_crc_check_result
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
Get CRC check results.
Definition: gr55xx_ll_efuse.h:558
ll_efuse_set_tpro
__STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
Set eFuse program time.
Definition: gr55xx_ll_efuse.h:165
ll_efuse_set_trim_addr
__STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
Set read trim start address.
Definition: gr55xx_ll_efuse.h:579
ll_efuse_is_active_flag
__STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check active flag.
Definition: gr55xx_ll_efuse.h:460
ll_efuse_set_operation
__STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
Set eFuse operation mode.
Definition: gr55xx_ll_efuse.h:425
ll_efuse_is_controller_power_flag
__STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check power controller active flag.
Definition: gr55xx_ll_efuse.h:779
ll_efuse_enable_main_backup
__STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
Enable read address through APB bus be a main address or backup address.
Definition: gr55xx_ll_efuse.h:203
ll_efuse_disable_power
__STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power off.
Definition: gr55xx_ll_efuse.h:693
ll_efuse_set_controller_power_timing
__STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
Set Efulse power controller timing pararmeter.
Definition: gr55xx_ll_efuse.h:709
ll_efuse_set_interval
__STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
Set the interval number of clk cycles between two bit fuse.
Definition: gr55xx_ll_efuse.h:300
ll_efuse_enable_pgenb
__STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
Enable eFuse PGENB sigal.
Definition: gr55xx_ll_efuse.h:338
ll_efuse_get_crc_check_len
__STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
Get CRC check length.
Definition: gr55xx_ll_efuse.h:280
ll_efuse_get_tpro
__STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
Get eFuse program time.
Definition: gr55xx_ll_efuse.h:184