gr55xx_ll_msio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief MSIO pad Enumerations definition
75 */
76 typedef enum
77 {
78 MSIOA = 0x00, /**< MSIO_A_PAD */
79 } msio_pad_t;
80
81 /**
82 * @brief LL MSIO init Structure definition
83 */
84 typedef struct _ll_msio_init
85 {
86 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
87 This parameter can be any value of @ref MSIO_LL_EC_PIN */
88
89 uint32_t direction; /**< Specifies the direction for the selected pins.
90 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
91
92 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_direction(). */
93
94 uint32_t mode; /**< Specifies the operating mode for the selected pins.
95 This parameter can be a value of @ref MSIO_LL_EC_MODE.
96
97 MSIO HW MSIO_InitStructuration can be modified afterwards using unitary function @ref ll_msio_set_pin_mode(). */
98
99 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
100 This parameter can be a value of @ref MSIO_LL_EC_PULL.
101
102 MSIO HW configuration can be modified afterwards using unitary function @ref ll_msio_set_pin_pull().*/
103
104 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
105 This parameter can be a value of @ref MSIO_LL_EC_MUX.
106
107 GPIO HW MSIO_InitStructuration can be modified afterwards using unitary function
108 @ref ll_msio_set_pin_mux(). */
109
110 } ll_msio_init_t;
111
112 /** @} */
113
114 /** @} */
115
116 /**
117 * @defgroup MSIO_LL_MACRO Defines
118 * @{
119 */
120
121 /* Exported constants --------------------------------------------------------*/
122 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
123 * @{
124 */
125
126 /** @defgroup MSIO_LL_EC_PIN PIN
127 * @{
128 */
129 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
130 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
131 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
132 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
133 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
134 #define LL_MSIO_PIN_ALL ((uint32_t)0x1FU) /**< Select all pins */
135 /** @} */
136
137 /** @defgroup MSIO_LL_EC_DIRECTION Direction
138 * @{
139 */
140 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
141 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
142 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
143 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
144 /** @} */
145
146 /** @defgroup MSIO_LL_EC_MODE Mode
147 * @{
148 */
149 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U) /**< Select analog mode */
150 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U) /**< Enable digital mode */
151 /** @} */
152
153 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
154 * @{
155 */
156 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
157 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
158 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
159 /** @} */
160
161 /** @defgroup MSIO_LL_EC_MUX Alternate Function
162 * @{
163 */
164 #define LL_MSIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
165 #define LL_MSIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
166 #define LL_MSIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
167 #define LL_MSIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
168 #define LL_MSIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
169 #define LL_MSIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
170 #define LL_MSIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
171 #define LL_MSIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
172 /** @} */
173
174 /** @} */
175
176 /* Exported macro ------------------------------------------------------------*/
177 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
178 * @{
179 */
180
181 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
182 * @{
183 */
184
185 /**
186 * @brief Write a value in MSIO register
187 * @param __instance__ MSIO instance
188 * @param __REG__ Register to be written
189 * @param __VALUE__ Value to be written in the register
190 * @retval None
191 */
192 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
193
194 /**
195 * @brief Read a value in MSIO register
196 * @param __instance__ MSIO instance
197 * @param __REG__ Register to be read
198 * @retval Register value
199 */
200 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
201
202 /** @} */
203
204 /** @} */
205
206 /* Private types -------------------------------------------------------------*/
207 /* Private variables ---------------------------------------------------------*/
208 /* Private constants ---------------------------------------------------------*/
209 /* Private macros ------------------------------------------------------------*/
210 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
211 * @{
212 */
213
214 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
215 * @{
216 */
217
218 /**
219 * @brief LL MSIO InitStrcut default configuartion
220 */
221 #define LL_MSIO_DEFAULT_CONFIG \
222 { \
223 .pin = LL_MSIO_PIN_ALL, \
224 .direction = LL_MSIO_DIRECTION_INPUT, \
225 .mode = LL_MSIO_MODE_DIGITAL, \
226 .pull = LL_MSIO_PULL_DOWN, \
227 .mux = LL_MSIO_MUX_7, \
228 }
229 /** @} */
230
231 /** @} */
232
233 /** @} */
234
235 /* Exported functions --------------------------------------------------------*/
236 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
237 * @{
238 */
239
240 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
241 * @{
242 */
243
244 /**
245 * @brief Set several MSIO pins to input/output direction.
246 *
247 * \rst
248 * +----------------------+-----------------------------------+
249 * | Register | BitsName |
250 * +======================+===================================+
251 * | MSIO_PAD_CFG_0 | OE_N |
252 * +----------------------+-----------------------------------+
253 * \endrst
254 * MSIO_PAD_CFG_0 | IE_N
255 *
256 * @param pin_mask This parameter can be a combination of the following values:
257 * @arg @ref LL_MSIO_PIN_0
258 * @arg @ref LL_MSIO_PIN_1
259 * @arg @ref LL_MSIO_PIN_2
260 * @arg @ref LL_MSIO_PIN_3
261 * @arg @ref LL_MSIO_PIN_4
262 * @arg @ref LL_MSIO_PIN_ALL
263 * @param direction This parameter can be one of the following values:
264 * @arg @ref LL_MSIO_DIRECTION_NONE
265 * @arg @ref LL_MSIO_DIRECTION_INPUT
266 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
267 * @arg @ref LL_MSIO_DIRECTION_INOUT
268 * @retval None
269 */
270 __STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
271 {
272 uint32_t oe_mask = (pin_mask << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
273 uint32_t ie_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
274 if (direction != LL_MSIO_DIRECTION_NONE)
275 {
276 if (direction != LL_MSIO_DIRECTION_INOUT)
277 MODIFY_REG(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask), (direction != LL_MSIO_DIRECTION_INPUT) ? ie_mask : oe_mask);
278 else
279 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
280 }
281 else
282 SET_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
283 }
284
285 /**
286 * @brief Return gpio direction for a MSIO pin.
287 * @note I/O direction can be Input direction, General purpose output.
288 * @note Warning: only one pin can be passed as parameter.
289 *
290 * \rst
291 * +----------------------+-----------------------------------+
292 * | Register | BitsName |
293 * +======================+===================================+
294 * | MSIO_PAD_CFG_0 | OE_N |
295 * +----------------------+-----------------------------------+
296 * \endrst
297 * MSIO_PAD_CFG_0 | IE_N
298 *
299 * @param pin This parameter can be one of the following values:
300 * @arg @ref LL_MSIO_PIN_0
301 * @arg @ref LL_MSIO_PIN_1
302 * @arg @ref LL_MSIO_PIN_2
303 * @arg @ref LL_MSIO_PIN_3
304 * @arg @ref LL_MSIO_PIN_4
305 * @retval Returned value can be one of the following values:
306 * @arg @ref LL_MSIO_DIRECTION_NONE
307 * @arg @ref LL_MSIO_DIRECTION_INPUT
308 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
309 * @arg @ref LL_MSIO_DIRECTION_INOUT
310 */
311 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
312 {
313 uint32_t oe_mask = (pin << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
314 uint32_t ie_mask = (pin << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
315 uint32_t mask = READ_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
316 if (mask == (ie_mask | oe_mask))
317 return LL_MSIO_DIRECTION_NONE;
318 else
319 {
320 if (mask == 0)
321 return LL_MSIO_DIRECTION_INOUT;
322 else
323 return ((mask == ie_mask) ? LL_MSIO_DIRECTION_OUTPUT : LL_MSIO_DIRECTION_INPUT);
324 }
325 }
326
327 /**
328 * @brief Set several MSIO pins to analog/digital mode.
329 *
330 * \rst
331 * +----------------------+-----------------------------------+
332 * | Register | BitsName |
333 * +======================+===================================+
334 * | MSIO_PAD_CFG_1 | AE_N |
335 * +----------------------+-----------------------------------+
336 * \endrst
337 *
338 * @param pin_mask This parameter can be a combination of the following values:
339 * @arg @ref LL_MSIO_PIN_0
340 * @arg @ref LL_MSIO_PIN_1
341 * @arg @ref LL_MSIO_PIN_2
342 * @arg @ref LL_MSIO_PIN_3
343 * @arg @ref LL_MSIO_PIN_4
344 * @arg @ref LL_MSIO_PIN_ALL
345 * @param mode This parameter can be one of the following values:
346 * @arg @ref LL_MSIO_MODE_ANALOG
347 * @arg @ref LL_MSIO_MODE_DIGITAL
348 * @retval None
349 */
350 __STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
351 {
352 uint32_t ae_mask = (pin_mask << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
353 uint32_t ae_n = (mode != LL_MSIO_MODE_DIGITAL) ? 0U : ae_mask;
354 GLOBAL_EXCEPTION_DISABLE();
355 MODIFY_REG(AON->MSIO_PAD_CFG_1, ae_mask, ae_n);
356 GLOBAL_EXCEPTION_ENABLE();
357 }
358
359 /**
360 * @brief Return gpio mode for a MSIO pin.
361 * @note I/O mode can be analog or digital.
362 * @note Warning: only one pin can be passed as parameter.
363 *
364 * \rst
365 * +----------------------+-----------------------------------+
366 * | Register | BitsName |
367 * +======================+===================================+
368 * | MSIO_PAD_CFG_1 | AE_N |
369 * +----------------------+-----------------------------------+
370 * \endrst
371 *
372 * @param pin This parameter can be one of the following values:
373 * @arg @ref LL_MSIO_PIN_0
374 * @arg @ref LL_MSIO_PIN_1
375 * @arg @ref LL_MSIO_PIN_2
376 * @arg @ref LL_MSIO_PIN_3
377 * @arg @ref LL_MSIO_PIN_4
378 * @retval Returned value can be one of the following values:
379 * @arg @ref LL_MSIO_MODE_ANALOG
380 * @arg @ref LL_MSIO_MODE_DIGITAL
381 */
382 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
383 {
384 uint32_t ae_mask = (pin << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
385 return ((READ_BITS(AON->MSIO_PAD_CFG_1, ae_mask) == ae_mask) ? LL_MSIO_MODE_DIGITAL : LL_MSIO_MODE_ANALOG);
386 }
387
388 /**
389 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
390 *
391 * \rst
392 * +----------------------+-----------------------------------+
393 * | Register | BitsName |
394 * +======================+===================================+
395 * | MSIO_PAD_CFG_0 | RE_N |
396 * +----------------------+-----------------------------------+
397 * \endrst
398 * MSIO_PAD_CFG_1 | RTYPE
399 *
400 * @param pin_mask This parameter can be a combination of the following values:
401 * @arg @ref LL_MSIO_PIN_0
402 * @arg @ref LL_MSIO_PIN_1
403 * @arg @ref LL_MSIO_PIN_2
404 * @arg @ref LL_MSIO_PIN_3
405 * @arg @ref LL_MSIO_PIN_4
406 * @arg @ref LL_MSIO_PIN_ALL
407 * @param pull This parameter can be one of the following values:
408 * @arg @ref LL_MSIO_PULL_NO
409 * @arg @ref LL_MSIO_PULL_UP
410 * @arg @ref LL_MSIO_PULL_DOWN
411 * @retval None
412 */
413 __STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
414 {
415 if (pull != LL_MSIO_PULL_NO)
416 {
417 uint32_t rtype_mask = (pin_mask << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
418 uint32_t rtype = (pull != LL_MSIO_PULL_UP) ? 0U : rtype_mask;
419 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
420 GLOBAL_EXCEPTION_DISABLE();
421 MODIFY_REG(AON->MSIO_PAD_CFG_1, rtype_mask, rtype);
422 GLOBAL_EXCEPTION_ENABLE();
423 }
424 else
425 {
426 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
427 }
428 }
429
430 /**
431 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
432 * @note Warning: only one pin can be passed as parameter.
433 *
434 * \rst
435 * +----------------------+-----------------------------------+
436 * | Register | BitsName |
437 * +======================+===================================+
438 * | MSIO_PAD_CFG_0 | RE_N |
439 * +----------------------+-----------------------------------+
440 * \endrst
441 * MSIO_PAD_CFG_1 | RTYPE
442 *
443 * @param pin This parameter can be one of the following values:
444 * @arg @ref LL_MSIO_PIN_0
445 * @arg @ref LL_MSIO_PIN_1
446 * @arg @ref LL_MSIO_PIN_2
447 * @arg @ref LL_MSIO_PIN_3
448 * @arg @ref LL_MSIO_PIN_4
449 * @retval Returned value can be one of the following values:
450 * @arg @ref LL_MSIO_PULL_NO
451 * @arg @ref LL_MSIO_PULL_UP
452 * @arg @ref LL_MSIO_PULL_DOWN
453 */
454 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
455 {
456 if (READ_BITS(AON->MSIO_PAD_CFG_0, (pin << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N))
457 {
458 return LL_MSIO_PULL_NO;
459 }
460 else
461 {
462 uint32_t rtype_mask = (pin << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
463 return ((READ_BITS(AON->MSIO_PAD_CFG_1, rtype_mask) != RESET) ? LL_MSIO_PULL_UP : LL_MSIO_PULL_DOWN);
464 }
465 }
466
467 /**
468 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
469 * @note Possible values are from AF0 to AF7 depending on target.
470 * @note Warning: only one pin can be passed as parameter.
471 *
472 * \rst
473 * +----------------------+-----------------------------------+
474 * | Register | BitsName |
475 * +======================+===================================+
476 * | MSIO_PAD_MUX_CTL | CTL_00_04 |
477 * +----------------------+-----------------------------------+
478 * \endrst
479 * MSIO_PAD_CFG_1 | MCU_OVR
480 *
481 * @param pin This parameter can be one of the following values:
482 * @arg @ref LL_MSIO_PIN_0
483 * @arg @ref LL_MSIO_PIN_1
484 * @arg @ref LL_MSIO_PIN_2
485 * @arg @ref LL_MSIO_PIN_3
486 * @arg @ref LL_MSIO_PIN_4
487 * @param mux This parameter can be one of the following values:
488 * @arg @ref LL_MSIO_MUX_0
489 * @arg @ref LL_MSIO_MUX_1
490 * @arg @ref LL_MSIO_MUX_2
491 * @arg @ref LL_MSIO_MUX_3
492 * @arg @ref LL_MSIO_MUX_4
493 * @arg @ref LL_MSIO_MUX_5
494 * @arg @ref LL_MSIO_MUX_6
495 * @arg @ref LL_MSIO_MUX_7
496 * @retval None
497 */
498 __STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
499 {
500 uint32_t pos = POSITION_VAL(pin) << 2;
501 if(LL_MSIO_MUX_7 == mux)
502 {
503 GLOBAL_EXCEPTION_DISABLE();
504 CLEAR_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
505 GLOBAL_EXCEPTION_ENABLE();
506 }
507 else
508 {
509 MODIFY_REG(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos, mux << pos);
510 GLOBAL_EXCEPTION_DISABLE();
511 SET_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
512 GLOBAL_EXCEPTION_ENABLE();
513 }
514 }
515
516 /**
517 * @brief Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
518 *
519 * \rst
520 * +----------------------+-----------------------------------+
521 * | Register | BitsName |
522 * +======================+===================================+
523 * | MSIO_PAD_MUX_CTL | CTL_00_04 |
524 * +----------------------+-----------------------------------+
525 * \endrst
526 * MSIO_PAD_CFG_1 | MCU_OVR
527 *
528 * @param pin This parameter can be one of the following values:
529 * @arg @ref LL_MSIO_PIN_0
530 * @arg @ref LL_MSIO_PIN_1
531 * @arg @ref LL_MSIO_PIN_2
532 * @arg @ref LL_MSIO_PIN_3
533 * @arg @ref LL_MSIO_PIN_4
534 * @retval Returned value can be one of the following values:
535 * @arg @ref LL_MSIO_MUX_0
536 * @arg @ref LL_MSIO_MUX_1
537 * @arg @ref LL_MSIO_MUX_2
538 * @arg @ref LL_MSIO_MUX_3
539 * @arg @ref LL_MSIO_MUX_4
540 * @arg @ref LL_MSIO_MUX_5
541 * @arg @ref LL_MSIO_MUX_6
542 * @arg @ref LL_MSIO_MUX_7
543 */
544 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
545 {
546 if(READ_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos))
547 {
548 uint32_t pos = POSITION_VAL(pin) << 2;
549 return (READ_BITS(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos) >> pos);
550 }
551 else
552 {
553 return LL_MSIO_MUX_7;
554 }
555 }
556
557 /** @} */
558
559 /** @defgroup MSIO_LL_EF_Data_Access Data Access
560 * @{
561 */
562
563 /**
564 * @brief Return full input data register value of MSIO.
565 *
566 * \rst
567 * +----------------------+-----------------------------------+
568 * | Register | BitsName |
569 * +======================+===================================+
570 * | MSIO_REG0 | MSIO_C |
571 * +----------------------+-----------------------------------+
572 * \endrst
573 *
574 * @retval Input data register value of port
575 */
576 __STATIC_INLINE uint32_t ll_msio_read_input_port(void)
577 {
578 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, MCU_SUB_MSIO_REG0_MSIO_C));
579 }
580
581 /**
582 * @brief Return if input data level of several MSIO pins is high or low.
583 *
584 * \rst
585 * +----------------------+-----------------------------------+
586 * | Register | BitsName |
587 * +======================+===================================+
588 * | MSIO_REG0 | MSIO_C |
589 * +----------------------+-----------------------------------+
590 * \endrst
591 *
592 * @param pin_mask This parameter can be a combination of the following values:
593 * @arg @ref LL_MSIO_PIN_0
594 * @arg @ref LL_MSIO_PIN_1
595 * @arg @ref LL_MSIO_PIN_2
596 * @arg @ref LL_MSIO_PIN_3
597 * @arg @ref LL_MSIO_PIN_4
598 * @arg @ref LL_MSIO_PIN_ALL
599 * @retval State of bit (1 or 0).
600 */
601 __STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
602 {
603 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, pin_mask) == pin_mask);
604 }
605
606 /**
607 * @brief Write output data register of MSIO.
608 *
609 * \rst
610 * +----------------------+-----------------------------------+
611 * | Register | BitsName |
612 * +======================+===================================+
613 * | MSIO_PAD_CFG_0 | IN |
614 * +----------------------+-----------------------------------+
615 * \endrst
616 *
617 * @param port_value Level value for each pin of the port
618 * @retval None
619 */
620 __STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
621 {
622 MODIFY_REG(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN, (port_value << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
623 }
624
625 /**
626 * @brief Return full output data register value of MSIO.
627 *
628 * \rst
629 * +----------------------+-----------------------------------+
630 * | Register | BitsName |
631 * +======================+===================================+
632 * | MSIO_PAD_CFG_0 | IN |
633 * +----------------------+-----------------------------------+
634 * \endrst
635 *
636 * @retval Output data register value of port
637 */
638 __STATIC_INLINE uint32_t ll_msio_read_output_port(void)
639 {
640 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN) >> AON_MSIO_PAD_CFG_0_IN_Pos);
641 }
642
643 /**
644 * @brief Return if input data level of several MSIO pins is high or low.
645 *
646 * \rst
647 * +----------------------+-----------------------------------+
648 * | Register | BitsName |
649 * +======================+===================================+
650 * | MSIO_PAD_CFG_0 | IN |
651 * +----------------------+-----------------------------------+
652 * \endrst
653 *
654 * @param pin_mask This parameter can be a combination of the following values:
655 * @arg @ref LL_MSIO_PIN_0
656 * @arg @ref LL_MSIO_PIN_1
657 * @arg @ref LL_MSIO_PIN_2
658 * @arg @ref LL_MSIO_PIN_3
659 * @arg @ref LL_MSIO_PIN_4
660 * @arg @ref LL_MSIO_PIN_ALL
661 * @retval State of bit (1 or 0).
662 */
663 __STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
664 {
665 pin_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN;
666 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, pin_mask) == pin_mask);
667 }
668
669 /**
670 * @brief Set specified MSIO pins to high level
671 *
672 * \rst
673 * +----------------------+-----------------------------------+
674 * | Register | BitsName |
675 * +======================+===================================+
676 * | MSIO_PAD_CFG_0 | IN |
677 * +----------------------+-----------------------------------+
678 * \endrst
679 *
680 * @param pin_mask This parameter can be a combination of the following values:
681 * @arg @ref LL_MSIO_PIN_0
682 * @arg @ref LL_MSIO_PIN_1
683 * @arg @ref LL_MSIO_PIN_2
684 * @arg @ref LL_MSIO_PIN_3
685 * @arg @ref LL_MSIO_PIN_4
686 * @arg @ref LL_MSIO_PIN_ALL
687 * @retval None
688 */
689 __STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
690 {
691 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
692 }
693
694 /**
695 * @brief Set specified MSIO pins to low level.
696 *
697 * \rst
698 * +----------------------+-----------------------------------+
699 * | Register | BitsName |
700 * +======================+===================================+
701 * | MSIO_PAD_CFG_0 | IN |
702 * +----------------------+-----------------------------------+
703 * \endrst
704 *
705 * @param pin_mask This parameter can be a combination of the following values:
706 * @arg @ref LL_MSIO_PIN_0
707 * @arg @ref LL_MSIO_PIN_1
708 * @arg @ref LL_MSIO_PIN_2
709 * @arg @ref LL_MSIO_PIN_3
710 * @arg @ref LL_MSIO_PIN_4
711 * @arg @ref LL_MSIO_PIN_ALL
712 * @retval None
713 */
714 __STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
715 {
716 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
717 }
718
719 /**
720 * @brief Toggle data value of specified MSIO pins.
721 *
722 * \rst
723 * +----------------------+-----------------------------------+
724 * | Register | BitsName |
725 * +======================+===================================+
726 * | MSIO_PAD_CFG_0 | IN |
727 * +----------------------+-----------------------------------+
728 * \endrst
729 *
730 * @param pin_mask This parameter can be a combination of the following values:
731 * @arg @ref LL_MSIO_PIN_0
732 * @arg @ref LL_MSIO_PIN_1
733 * @arg @ref LL_MSIO_PIN_2
734 * @arg @ref LL_MSIO_PIN_3
735 * @arg @ref LL_MSIO_PIN_4
736 * @arg @ref LL_MSIO_PIN_ALL
737 * @retval None
738 */
739 __STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
740 {
741 WRITE_REG(AON->MSIO_PAD_CFG_0, (READ_REG(AON->MSIO_PAD_CFG_0) ^ ((pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN)));
742 }
743
744 /** @} */
745
746 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
747 * @{
748 */
749
750 /**
751 * @brief De-initialize MSIO registers (Registers restored to their default values).
752 * @retval An error_status_t enumeration value:
753 * - SUCCESS: MSIO registers are de-initialized
754 * - ERROR: MSIO registers are not de-initialized
755 */
756 error_status_t ll_msio_deinit(void);
757
758 /**
759 * @brief Initialize MSIO registers according to the specified.
760 * parameters in p_msio_init.
761 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
762 * information for the specified MSIO peripheral.
763 * @retval An error_status_t enumeration value:
764 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
765 * - ERROR: Problem occurred during MSIO Registers initialization
766 */
767 error_status_t ll_msio_init(ll_msio_init_t *p_msio_init);
768
769 /**
770 * @brief Set each field of a @ref ll_msio_init_t type structure to default value.
771 * @param p_msio_init Pointer to a @ref ll_msio_init_t structure
772 * whose fields will be set to default values.
773 * @retval None
774 */
775 void ll_msio_struct_init(ll_msio_init_t *p_msio_init);
776
777 /** @} */
778
779 /** @} */
780
781 #endif /* AON */
782
783 #ifdef __cplusplus
784 }
785 #endif
786
787 #endif /* __GR55XX_LL_MSIO_H__ */
788
789 /** @} */
790
791 /** @} */
792
793 /** @} */
_ll_msio_init::mux
uint32_t mux
Definition: gr55xx_ll_msio.h:104
ll_msio_set_pin_direction
__STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
Set several MSIO pins to input/output direction.
Definition: gr55xx_ll_msio.h:270
ll_msio_get_pin_direction
__STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
Return gpio direction for a MSIO pin.
Definition: gr55xx_ll_msio.h:311
LL_MSIO_MODE_ANALOG
#define LL_MSIO_MODE_ANALOG
Definition: gr55xx_ll_msio.h:149
LL_MSIO_MODE_DIGITAL
#define LL_MSIO_MODE_DIGITAL
Definition: gr55xx_ll_msio.h:150
ll_msio_read_input_port
__STATIC_INLINE uint32_t ll_msio_read_input_port(void)
Return full input data register value of MSIO.
Definition: gr55xx_ll_msio.h:576
LL_MSIO_PULL_DOWN
#define LL_MSIO_PULL_DOWN
Definition: gr55xx_ll_msio.h:158
ll_msio_toggle_pin
__STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified MSIO pins.
Definition: gr55xx_ll_msio.h:739
ll_msio_set_pin_mode
__STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several MSIO pins to analog/digital mode.
Definition: gr55xx_ll_msio.h:350
ll_msio_init_t
struct _ll_msio_init ll_msio_init_t
LL MSIO init Structure definition.
ll_msio_get_pin_pull
__STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:454
ll_msio_get_pin_mode
__STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
Return gpio mode for a MSIO pin.
Definition: gr55xx_ll_msio.h:382
_ll_msio_init::mode
uint32_t mode
Definition: gr55xx_ll_msio.h:94
LL_MSIO_PULL_NO
#define LL_MSIO_PULL_NO
Definition: gr55xx_ll_msio.h:156
ll_msio_reset_output_pin
__STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
Set specified MSIO pins to low level.
Definition: gr55xx_ll_msio.h:714
ll_msio_set_output_pin
__STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
Set specified MSIO pins to high level.
Definition: gr55xx_ll_msio.h:689
LL_MSIO_MUX_7
#define LL_MSIO_MUX_7
Definition: gr55xx_ll_msio.h:171
LL_MSIO_DIRECTION_INOUT
#define LL_MSIO_DIRECTION_INOUT
Definition: gr55xx_ll_msio.h:143
LL_MSIO_DIRECTION_INPUT
#define LL_MSIO_DIRECTION_INPUT
Definition: gr55xx_ll_msio.h:141
ll_msio_get_pin_mux
__STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:544
msio_pad_t
msio_pad_t
MSIO pad Enumerations definition.
Definition: gr55xx_ll_msio.h:77
ll_msio_set_pin_pull
__STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated MSIO pin.
Definition: gr55xx_ll_msio.h:413
_ll_msio_init::direction
uint32_t direction
Definition: gr55xx_ll_msio.h:89
ll_msio_write_output_port
__STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
Write output data register of MSIO.
Definition: gr55xx_ll_msio.h:620
ll_msio_read_output_port
__STATIC_INLINE uint32_t ll_msio_read_output_port(void)
Return full output data register value of MSIO.
Definition: gr55xx_ll_msio.h:638
ll_msio_init
error_status_t ll_msio_init(ll_msio_init_t *p_msio_init)
Initialize MSIO registers according to the specified. parameters in p_msio_init.
ll_msio_struct_init
void ll_msio_struct_init(ll_msio_init_t *p_msio_init)
Set each field of a ll_msio_init_t type structure to default value.
LL_MSIO_DIRECTION_OUTPUT
#define LL_MSIO_DIRECTION_OUTPUT
Definition: gr55xx_ll_msio.h:142
LL_MSIO_PULL_UP
#define LL_MSIO_PULL_UP
Definition: gr55xx_ll_msio.h:157
ll_msio_deinit
error_status_t ll_msio_deinit(void)
De-initialize MSIO registers (Registers restored to their default values).
MSIOA
@ MSIOA
Definition: gr55xx_ll_msio.h:78
_ll_msio_init
LL MSIO init Structure definition.
Definition: gr55xx_ll_msio.h:85
_ll_msio_init::pin
uint32_t pin
Definition: gr55xx_ll_msio.h:86
ll_msio_is_input_pin_set
__STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:601
_ll_msio_init::pull
uint32_t pull
Definition: gr55xx_ll_msio.h:99
ll_msio_is_output_pin_set
__STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several MSIO pins is high or low.
Definition: gr55xx_ll_msio.h:663
LL_MSIO_DIRECTION_NONE
#define LL_MSIO_DIRECTION_NONE
Definition: gr55xx_ll_msio.h:140
ll_msio_set_pin_mux
__STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
Definition: gr55xx_ll_msio.h:498