gr55xx_ll_cgc.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_cgc.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of CGC LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_CGC CGC
47  * @brief CGC LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 #if defined(MCU_SUB)
63 
64 /** @defgroup CGC_LL_STRUCTURES Structures
65  * @{
66  */
67 
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup CGC_LL_ES_INIT CGC Exported init structures
70  * @{
71  */
72 
73 /**
74  * @brief LL CGC init Structure definition
75  */
76 typedef struct _ll_cgc_init_t
77 {
78  uint32_t wfi_clk0; /**< Specifies the block that automatically closes the clock.
79  This parameter can be a combination of @ref CGC_LL_EC_WFI_CLK0. */
80 
81  uint32_t wfi_clk1; /**< Specifies the block that automatically closes the clock.
82  This parameter can be a combination of @ref CGC_LL_EC_WFI_CLK1. */
83 
84  uint32_t wfi_clk2; /**< Specifies the block that automatically closes the clock.
85  This parameter can be a combination of @ref CGC_LL_EC_WFI_CLK2. */
86 
87  uint32_t force_clk0; /**< Specifies the blocks for forced turn off clock.
88  This parameter can be a combination of @ref CGC_LL_EC_FRC_CLK0. */
89 
90  uint32_t force_clk1; /**< Specifies the blocks for forced turn off clock.
91  This parameter can be a combination of @ref CGC_LL_EC_FRC_CLK1. */
92 
93  uint32_t force_clk2; /**< Specifies the blocks for forced turn off clock.
94  This parameter can be a combination of @ref CGC_LL_EC_FRC_CLK2. */
96 
97 /** @} */
98 
99 /** @} */
100 
101 /**
102  * @defgroup CGC_LL_MACRO Defines
103  * @{
104  */
105 
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup CGC_LL_Exported_Constants CGC Exported Constants
108  * @{
109  */
110 
111 /** @defgroup CGC_LL_EC_WFI_CLK0 Block0 Clock During WFI
112  * @{
113  */
114 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK /**< Hclk for all security blocks */
115 #define LL_CGC_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK /**< Hclk for sim card interface */
116 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK /**< Hclk for hopping table */
117 #define LL_CGC_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK /**< Hclk for PWM */
118 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK /**< Hclk for ROM */
119 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK /**< Hclk for sense ADC */
120 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK /**< Hclk for GPIOs */
121 #define LL_CGC_WFI_DMA_HCLK MCU_SUB_WFI_DMA_HCLK /**< Hclk for DMA engine */
122 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
123 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK /**< Hclk for APB subsystem */
124 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK /**< Hclk for serial blocks */
125 #define LL_CGC_WFI_I2S_S_HCLK MCU_SUB_WFI_I2S_S_HCLK /**< Hclk for I2S slave */
126 
127 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x00000FFFU) /**< All clock group 0 */
128 /** @} */
129 
130 /** @defgroup CGC_LL_EC_WFI_CLK1 Block1 Clock During WFI
131  * @{
132  */
133 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
134 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK /**< Hclk for cache top */
135 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK /**< Hclk for SRAMs */
136 
137 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U) /**< All clock group 1 */
138 /** @} */
139 
140 /** @defgroup CGC_LL_EC_WFI_CLK2 Block2 Clock During WFI
141  * @{
142  */
143 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK /**< Div4 clk for security blocks */
144 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
145 
146 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U) /**< All clock group 2 */
147 /** @} */
148 
149 
150 /** @defgroup CGC_LL_EC_FRC_CLK0 Force Clock OFF
151  * @{
152  */
153 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK /**< Hclk for all security blocks */
154 #define LL_CGC_FRC_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK /**< Hclk for sim card interface */
155 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK /**< Hclk for hopping table */
156 #define LL_CGC_FRC_PWM_HCLK MCU_SUB_FORCE_PWM_HCLK /**< Hclk for PWM */
157 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK /**< Hclk for ROM */
158 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK /**< Hclk for sense ADC */
159 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK /**< Hclk for GPIOs */
160 #define LL_CGC_FRC_DMA_HCLK MCU_SUB_FORCE_DMA_HCLK /**< Hclk for DMA engine */
161 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
162 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK /**< Hclk for APB subsystem */
163 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK /**< Hclk for serial blocks */
164 #define LL_CGC_FRC_I2S_S_HCLK MCU_SUB_FORCE_I2S_S_HCLK /**< Hclk for I2S slave */
165 
166 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000FFFU) /**< All clock group 0 */
167 /** @} */
168 
169 /** @defgroup CGC_LL_EC_FRC_CLK1 Force Clock OFF
170  * @{
171  */
172 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
173 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK /**< Hclk for cache top */
174 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK /**< Hclk for SRAMs */
175 
176 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U) /**< All clock group 1 */
177 /** @} */
178 
179 /** @defgroup CGC_LL_EC_FRC_CLK2 Force Clock OFF
180  * @{
181  */
182 #define LL_CGC_FRC_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK /**< Hclk for uart0 */
183 #define LL_CGC_FRC_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK /**< Hclk for uart1 */
184 #define LL_CGC_FRC_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK /**< Hclk for i2c0 */
185 #define LL_CGC_FRC_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK /**< Hclk for i2c1 */
186 #define LL_CGC_FRC_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK /**< Hclk for spim */
187 #define LL_CGC_FRC_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK /**< Hclk for spis */
188 #define LL_CGC_FRC_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK /**< Hclk for qspi0 */
189 #define LL_CGC_FRC_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK /**< Hclk for qspi1 */
190 #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK /**< Hclk for i2s */
191 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK /**< Div4 clk for security blocks */
192 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
193 
194 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x0001FF00U) /**< Hclk for serial blocks */
195 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0x0A01FF00U) /**< All clock group 2 */
196 /** @} */
197 
198 /** @} */
199 
200 /* Exported macro ------------------------------------------------------------*/
201 /** @defgroup CGC_LL_Exported_Macros CGC Exported Macros
202  * @{
203  */
204 
205 /** @defgroup CGC_LL_EM_WRITE_READ Common Write and read registers Macros
206  * @{
207  */
208 
209 /**
210  * @brief Write a value in CGC register
211  * @param __instance__ CGC instance
212  * @param __REG__ Register to be written
213  * @param __VALUE__ Value to be written in the register
214  * @retval None
215  */
216 #define LL_CGC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
217 
218 /**
219  * @brief Read a value in CGC register
220  * @param __instance__ CGC instance
221  * @param __REG__ Register to be read
222  * @retval Register value
223  */
224 #define LL_CGC_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
225 
226 /** @} */
227 
228 /** @} */
229 
230 /* Private types -------------------------------------------------------------*/
231 /* Private variables ---------------------------------------------------------*/
232 /* Private constants ---------------------------------------------------------*/
233 /* Private macros ------------------------------------------------------------*/
234 /** @defgroup CGC_LL_Private_Macros CGC Private Macros
235  * @{
236  */
237 
238 /** @defgroup CGC_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
239  * @{
240  */
241 
242 /**
243  * @brief LL CGC InitStrcut default configuartion
244  */
245 #define LL_CGC_DEFAULT_CONFIG \
246 { \
247  .wfi_clk0 = ~LL_CGC_WFI_ALL_HCLK0, \
248  .wfi_clk1 = ~LL_CGC_WFI_ALL_HCLK1, \
249  .wfi_clk2 = ~LL_CGC_WFI_ALL_HCLK2, \
250  .force_clk0 = ~LL_CGC_FRC_ALL_HCLK0, \
251  .force_clk1 = ~LL_CGC_FRC_ALL_HCLK1, \
252  .force_clk2 = ~LL_CGC_FRC_ALL_HCLK2, \
253 }
254 /** @} */
255 
256 /** @} */
257 
258 /** @} */
259 
260 
261 /* Exported functions --------------------------------------------------------*/
262 /** @defgroup CGC_LL_DRIVER_FUNCTIONS Functions
263  * @{
264  */
265 
266 /** @defgroup CGC_LL_EF_CLK_Configuration Clock Configuration
267  * @{
268  */
269 
270 /**
271  * @brief Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/
272  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
273  *
274  * Register | BitsName
275  * ----------|--------
276  * CG_CTRL_0 | SECU_HCLK
277  * CG_CTRL_0 | SIM_HCLK
278  * CG_CTRL_0 | HTB_HCLK
279  * CG_CTRL_0 | PWM_HCLK
280  * CG_CTRL_0 | ROM_HCLK
281  * CG_CTRL_0 | SNSADC_HCLK
282  * CG_CTRL_0 | GPIO_HCLK
283  * CG_CTRL_0 | DMA_HCLK
284  * CG_CTRL_0 | BLE_BRG_HCLK
285  * CG_CTRL_0 | APB_SUB_HCLK
286  * CG_CTRL_0 | SERIAL_HCLK
287  * CG_CTRL_0 | I2S_S_HCLK
288  *
289  * @param clk_mask This parameter can be a combination of the following values:
290  * @arg @ref LL_CGC_WFI_SECU_HCLK
291  * @arg @ref LL_CGC_WFI_SIM_HCLK
292  * @arg @ref LL_CGC_WFI_HTB_HCLK
293  * @arg @ref LL_CGC_WFI_PWM_HCLK
294  * @arg @ref LL_CGC_WFI_ROM_HCLK
295  * @arg @ref LL_CGC_WFI_SNSADC_HCLK
296  * @arg @ref LL_CGC_WFI_GPIO_HCLK
297  * @arg @ref LL_CGC_WFI_DMA_HCLK
298  * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
299  * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
300  * @arg @ref LL_CGC_WFI_SERIAL_HCLK
301  * @arg @ref LL_CGC_WFI_I2S_S_HCLK
302  * @retval None
303  */
304 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
305 {
306  WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], clk_mask);
307 }
308 
309 /**
310  * @brief Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/
311  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
312  *
313  * Register | BitsName
314  * ----------|--------
315  * CG_CTRL_0 | SECU_HCLK
316  * CG_CTRL_0 | SIM_HCLK
317  * CG_CTRL_0 | HTB_HCLK
318  * CG_CTRL_0 | PWM_HCLK
319  * CG_CTRL_0 | ROM_HCLK
320  * CG_CTRL_0 | SNSADC_HCLK
321  * CG_CTRL_0 | GPIO_HCLK
322  * CG_CTRL_0 | DMA_HCLK
323  * CG_CTRL_0 | BLE_BRG_HCLK
324  * CG_CTRL_0 | APB_SUB_HCLK
325  * CG_CTRL_0 | SERIAL_HCLK
326  * CG_CTRL_0 | I2S_S_HCLK
327  *
328  * @retval Returned value can be a combination of the following values:
329  * @arg @ref LL_CGC_WFI_SECU_HCLK
330  * @arg @ref LL_CGC_WFI_SIM_HCLK
331  * @arg @ref LL_CGC_WFI_HTB_HCLK
332  * @arg @ref LL_CGC_WFI_PWM_HCLK
333  * @arg @ref LL_CGC_WFI_ROM_HCLK
334  * @arg @ref LL_CGC_WFI_SNSADC_HCLK
335  * @arg @ref LL_CGC_WFI_GPIO_HCLK
336  * @arg @ref LL_CGC_WFI_DMA_HCLK
337  * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
338  * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
339  * @arg @ref LL_CGC_WFI_SERIAL_HCLK
340  * @arg @ref LL_CGC_WFI_I2S_S_HCLK
341  */
342 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
343 {
344  return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[0]);
345 }
346 
347 
348 /**
349  * @brief Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
350  *
351  * Register | BitsName
352  * ----------|--------
353  * CG_CTRL_2 | AON_MCUSUB_HCLK
354  * CG_CTRL_2 | XF_XQSPI_HCLK
355  * CG_CTRL_2 | SRAM_HCLK
356  *
357  * @param clk_mask This parameter can be a combination of the following values:
358  * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
359  * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
360  * @arg @ref LL_CGC_WFI_SRAM_HCLK
361  * @retval None
362  */
363 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
364 {
365  GLOBAL_EXCEPTION_DISABLE();
366  MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1, clk_mask);
367  GLOBAL_EXCEPTION_ENABLE();
368 }
369 
370 /**
371  * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
372  *
373  * Register | BitsName
374  * ----------|--------
375  * CG_CTRL_2 | AON_MCUSUB_HCLK
376  * CG_CTRL_2 | XF_XQSPI_HCLK
377  * CG_CTRL_2 | SRAM_HCLK
378  *
379  * @retval Returned value can be a combination of the following values:
380  * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
381  * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
382  * @arg @ref LL_CGC_WFI_SRAM_HCLK
383  */
384 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
385 {
386  return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_MSK_HCLK_1);
387 }
388 
389 /**
390  * @brief Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
391  *
392  * Register | BitsName
393  * ----------|--------
394  * PERIPH_GC | SECU_DIV4_PCLK
395  * PERIPH_GC | XQSPI_DIV4_PCLK
396  *
397  * @param clk_mask This parameter can be a combination of the following values:
398  * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
399  * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
400  * @retval None
401  */
402 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
403 {
404  GLOBAL_EXCEPTION_DISABLE();
405  MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2, clk_mask);
406  GLOBAL_EXCEPTION_ENABLE();
407 }
408 
409 /**
410  * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
411  *
412  * Register | BitsName
413  * ----------|--------
414  * PERIPH_GC | SECU_DIV4_PCLK
415  * PERIPH_GC | XQSPI_DIV4_PCLK
416  *
417  * @retval Returned value can be a combination of the following values:
418  * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
419  * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
420  */
421 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
422 {
423  return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_MSK_HCLK_2);
424 }
425 
426 /**
427  * @brief Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/
428  * DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
429  *
430  * Register | BitsName
431  * ----------|--------
432  * CG_CTRL_1 | SECU_HCLK
433  * CG_CTRL_1 | SIM_HCLK
434  * CG_CTRL_1 | HTB_HCLK
435  * CG_CTRL_1 | PWM_HCLK
436  * CG_CTRL_1 | ROM_HCLK
437  * CG_CTRL_1 | SNSADC_HCLK
438  * CG_CTRL_1 | GPIO_HCLK
439  * CG_CTRL_1 | DMA_HCLK
440  * CG_CTRL_1 | BLE_BRG_HCLK
441  * CG_CTRL_1 | APB_SUB_HCLK
442  * CG_CTRL_1 | SERIAL_HCLK
443  * CG_CTRL_1 | I2S_S_HCLK
444  *
445  * @param clk_mask This parameter can be a combination of the following values:
446  * @arg @ref LL_CGC_FRC_SECU_HCLK
447  * @arg @ref LL_CGC_FRC_SIM_HCLK
448  * @arg @ref LL_CGC_FRC_HTB_HCLK
449  * @arg @ref LL_CGC_FRC_PWM_HCLK
450  * @arg @ref LL_CGC_FRC_ROM_HCLK
451  * @arg @ref LL_CGC_FRC_SNSADC_HCLK
452  * @arg @ref LL_CGC_FRC_GPIO_HCLK
453  * @arg @ref LL_CGC_FRC_DMA_HCLK
454  * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
455  * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
456  * @arg @ref LL_CGC_FRC_SERIAL_HCLK
457  * @arg @ref LL_CGC_FRC_I2S_S_HCLK
458  * @retval None
459  */
460 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
461 {
462  WRITE_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], clk_mask);
463 }
464 
465 /**
466  * @brief Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/PWM/
467  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
468  *
469  * Register | BitsName
470  * ----------|--------
471  * CG_CTRL_1 | SECU_HCLK
472  * CG_CTRL_1 | SIM_HCLK
473  * CG_CTRL_1 | HTB_HCLK
474  * CG_CTRL_1 | PWM_HCLK
475  * CG_CTRL_1 | ROM_HCLK
476  * CG_CTRL_1 | SNSADC_HCLK
477  * CG_CTRL_1 | GPIO_HCLK
478  * CG_CTRL_1 | DMA_HCLK
479  * CG_CTRL_1 | BLE_BRG_HCLK
480  * CG_CTRL_1 | APB_SUB_HCLK
481  * CG_CTRL_1 | SERIAL_HCLK
482  * CG_CTRL_1 | I2S_S_HCLK
483  *
484  * @retval Returned value can be a combination of the following values:
485  * @arg @ref LL_CGC_FRC_SECU_HCLK
486  * @arg @ref LL_CGC_FRC_SIM_HCLK
487  * @arg @ref LL_CGC_FRC_HTB_HCLK
488  * @arg @ref LL_CGC_FRC_PWM_HCLK
489  * @arg @ref LL_CGC_FRC_ROM_HCLK
490  * @arg @ref LL_CGC_FRC_SNSADC_HCLK
491  * @arg @ref LL_CGC_FRC_GPIO_HCLK
492  * @arg @ref LL_CGC_FRC_DMA_HCLK
493  * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
494  * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
495  * @arg @ref LL_CGC_FRC_SERIAL_HCLK
496  * @arg @ref LL_CGC_FRC_I2S_S_HCLK
497  */
498 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
499 {
500  return READ_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[1]);
501 }
502 
503 
504 /**
505  * @brief Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
506  *
507  * Register | BitsName
508  * ----------|--------
509  * CG_CTRL_2 | AON_MCUSUB_HCLK
510  * CG_CTRL_2 | XF_XQSPI_HCLK
511  * CG_CTRL_2 | SRAM_HCLK
512  *
513  * @param clk_mask This parameter can be a combination of the following values:
514  * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
515  * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
516  * @arg @ref LL_CGC_FRC_SRAM_HCLK
517  * @retval None
518  */
519 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
520 {
521  GLOBAL_EXCEPTION_DISABLE();
522  MODIFY_REG(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1, clk_mask);
523  GLOBAL_EXCEPTION_ENABLE();
524 }
525 
526 /**
527  * @brief Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
528  *
529  * Register | BitsName
530  * ----------|--------
531  * CG_CTRL_2 | AON_MCUSUB_HCLK
532  * CG_CTRL_2 | XF_XQSPI_HCLK
533  * CG_CTRL_2 | SRAM_HCLK
534  *
535  * @retval Returned value can be a combination of the following values:
536  * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
537  * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
538  * @arg @ref LL_CGC_FRC_SRAM_HCLK
539  */
540 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
541 {
542  return READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_MSK_HCLK_1);
543 }
544 
545 /**
546  * @brief Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/
547  * I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK)
548  *
549  * Register | BitsName
550  * ----------|--------
551  * PERIPH_GC | UART0_HCLK
552  * PERIPH_GC | UART1_HCLK
553  * PERIPH_GC | I2C0_HCLK
554  * PERIPH_GC | I2C1_HCLK
555  * PERIPH_GC | SPIM_HCLK
556  * PERIPH_GC | SPIS_HCLK
557  * PERIPH_GC | QSPI0_HCLK
558  * PERIPH_GC | QSPI1_HCLK
559  * PERIPH_GC | I2S_HCLK
560  * PERIPH_GC | SECU_DIV4_PCLK
561  * PERIPH_GC | XQSPI_DIV4_PCLK
562  *
563  * @param clk_mask This parameter can be a combination of the following values:
564  * @arg @ref LL_CGC_FRC_UART0_HCLK
565  * @arg @ref LL_CGC_FRC_UART1_HCLK
566  * @arg @ref LL_CGC_FRC_I2C0_HCLK
567  * @arg @ref LL_CGC_FRC_I2C1_HCLK
568  * @arg @ref LL_CGC_FRC_SPIM_HCLK
569  * @arg @ref LL_CGC_FRC_SPIS_HCLK
570  * @arg @ref LL_CGC_FRC_QSPI0_HCLK
571  * @arg @ref LL_CGC_FRC_QSPI1_HCLK
572  * @arg @ref LL_CGC_FRC_I2S_HCLK
573  * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
574  * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
575  * @retval None
576  */
577 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
578 {
579  GLOBAL_EXCEPTION_DISABLE();
580  MODIFY_REG(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2, clk_mask);
581  GLOBAL_EXCEPTION_ENABLE();
582 }
583 
584 /**
585  * @brief Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/
586  * I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK)
587  *
588  * Register | BitsName
589  * ----------|--------
590  * PERIPH_GC | UART0_HCLK
591  * PERIPH_GC | UART1_HCLK
592  * PERIPH_GC | I2C0_HCLK
593  * PERIPH_GC | I2C1_HCLK
594  * PERIPH_GC | SPIM_HCLK
595  * PERIPH_GC | SPIS_HCLK
596  * PERIPH_GC | QSPI0_HCLK
597  * PERIPH_GC | QSPI1_HCLK
598  * PERIPH_GC | I2S_HCLK
599  * PERIPH_GC | SECU_DIV4_PCLK
600  * PERIPH_GC | XQSPI_DIV4_PCLK
601  *
602  * @retval Returned value can be a combination of the following values:
603  * @arg @ref LL_CGC_FRC_UART0_HCLK
604  * @arg @ref LL_CGC_FRC_UART1_HCLK
605  * @arg @ref LL_CGC_FRC_I2C0_HCLK
606  * @arg @ref LL_CGC_FRC_I2C1_HCLK
607  * @arg @ref LL_CGC_FRC_SPIM_HCLK
608  * @arg @ref LL_CGC_FRC_SPIS_HCLK
609  * @arg @ref LL_CGC_FRC_QSPI0_HCLK
610  * @arg @ref LL_CGC_FRC_QSPI1_HCLK
611  * @arg @ref LL_CGC_FRC_I2S_HCLK
612  * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
613  * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
614  */
615 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
616 {
617  return READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_MSK_HCLK_2);
618 }
619 
620 /**
621  * @brief Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
622  *
623  * Register | BitsName
624  * ----------|--------
625  * CG_CTRL_0 | SECU_HCLK
626  *
627  * @retval None
628  */
629 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
630 {
631  GLOBAL_EXCEPTION_DISABLE();
632  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
633  GLOBAL_EXCEPTION_ENABLE();
634 }
635 
636 /**
637  * @brief Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
638  *
639  * Register | BitsName
640  * ----------|--------
641  * CG_CTRL_0 | SECU_HCLK
642  *
643  * @retval None
644  */
645 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
646 {
647  GLOBAL_EXCEPTION_DISABLE();
648  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK);
649  GLOBAL_EXCEPTION_ENABLE();
650 }
651 
652 /**
653  * @brief Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is enabled.
654  *
655  * Register | BitsName
656  * ----------|--------
657  * CG_CTRL_0 | SECU_HCLK
658  *
659  * @retval State of bit (1 or 0).
660  */
661 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
662 {
663  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK) == (MCU_SUB_WFI_SECU_HCLK));
664 }
665 
666 /**
667  * @brief Enable SIM automatic turn off clock during WFI
668  *
669  * Register | BitsName
670  * ----------|--------
671  * CG_CTRL_0 | SIM_HCLK
672  *
673  * @retval None
674  */
675 __STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
676 {
677  GLOBAL_EXCEPTION_DISABLE();
678  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
679  GLOBAL_EXCEPTION_ENABLE();
680 }
681 
682 /**
683  * @brief Disable SIM automatic turn off clock during WFI
684  *
685  * Register | BitsName
686  * ----------|--------
687  * CG_CTRL_0 | SIM_HCLK
688  *
689  * @retval None
690  */
691 __STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
692 {
693  GLOBAL_EXCEPTION_DISABLE();
694  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK);
695  GLOBAL_EXCEPTION_ENABLE();
696 }
697 
698 /**
699  * @brief Indicate whether the SIM automatic turn off clock is enabled.
700  *
701  * Register | BitsName
702  * ----------|--------
703  * CG_CTRL_0 | SIM_HCLK
704  *
705  * @retval State of bit (1 or 0).
706  */
707 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
708 {
709  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK) == (MCU_SUB_WFI_SIM_HCLK));
710 }
711 
712 /**
713  * @brief Enable Hopping Table automatic turn off clock during WFI
714  *
715  * Register | BitsName
716  * ----------|--------
717  * CG_CTRL_0 | HTB_HCLK
718  *
719  * @retval None
720  */
721 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
722 {
723  GLOBAL_EXCEPTION_DISABLE();
724  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
725  GLOBAL_EXCEPTION_ENABLE();
726 }
727 
728 /**
729  * @brief Disable Hopping Table automatic turn off clock during WFI
730  *
731  * Register | BitsName
732  * ----------|--------
733  * CG_CTRL_0 | HTB_HCLK
734  *
735  * @retval None
736  */
737 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
738 {
739  GLOBAL_EXCEPTION_DISABLE();
740  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK);
741  GLOBAL_EXCEPTION_ENABLE();
742 }
743 
744 /**
745  * @brief Indicate whether the Hopping Table automatic turn off clock is enabled.
746  *
747  * Register | BitsName
748  * ----------|--------
749  * CG_CTRL_0 | HTB_HCLK
750  *
751  * @retval State of bit (1 or 0).
752  */
753 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
754 {
755  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK) == (MCU_SUB_WFI_HTB_HCLK));
756 }
757 
758 /**
759  * @brief Enable PWM automatic turn off clock during WFI
760  *
761  * Register | BitsName
762  * ----------|--------
763  * CG_CTRL_0 | PWM_HCLK
764  *
765  * @retval None
766  */
767 __STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
768 {
769  GLOBAL_EXCEPTION_DISABLE();
770  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
771  GLOBAL_EXCEPTION_ENABLE();
772 }
773 
774 /**
775  * @brief Disable PWM automatic turn off clock during WFI
776  *
777  * Register | BitsName
778  * ----------|--------
779  * CG_CTRL_0 | PWM_HCLK
780  *
781  * @retval None
782  */
783 __STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
784 {
785  GLOBAL_EXCEPTION_DISABLE();
786  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK);
787  GLOBAL_EXCEPTION_ENABLE();
788 }
789 
790 /**
791  * @brief Indicate whether the PWM automatic turn off clock is enabled.
792  *
793  * Register | BitsName
794  * ----------|--------
795  * CG_CTRL_0 | PWM_HCLK
796  *
797  * @retval State of bit (1 or 0).
798  */
799 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
800 {
801  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK) == (MCU_SUB_WFI_PWM_HCLK));
802 }
803 
804 /**
805  * @brief Enable ROM automatic turn off clock during WFI
806  *
807  * Register | BitsName
808  * ----------|--------
809  * CG_CTRL_0 | ROM_HCLK
810  *
811  * @retval None
812  */
813 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
814 {
815  GLOBAL_EXCEPTION_DISABLE();
816  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
817  GLOBAL_EXCEPTION_ENABLE();
818 }
819 
820 /**
821  * @brief Disable ROM automatic turn off clock during WFI
822  *
823  * Register | BitsName
824  * ----------|--------
825  * CG_CTRL_0 | ROM_HCLK
826  *
827  * @retval None
828  */
829 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
830 {
831  GLOBAL_EXCEPTION_DISABLE();
832  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK);
833  GLOBAL_EXCEPTION_ENABLE();
834 }
835 
836 /**
837  * @brief Indicate whether the ROM automatic turn off clock is enabled.
838  *
839  * Register | BitsName
840  * ----------|--------
841  * CG_CTRL_0 | ROM_HCLK
842  *
843  * @retval State of bit (1 or 0).
844  */
845 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
846 {
847  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK) == (MCU_SUB_WFI_ROM_HCLK));
848 }
849 
850 /**
851  * @brief Enable SNSADC automatic turn off clock during WFI
852  *
853  * Register | BitsName
854  * ----------|--------
855  * CG_CTRL_0 | SNSADC_HCLK
856  *
857  * @retval None
858  */
859 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
860 {
861  GLOBAL_EXCEPTION_DISABLE();
862  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
863  GLOBAL_EXCEPTION_ENABLE();
864 }
865 
866 /**
867  * @brief Disable SNSADC automatic turn off clock during WFI
868  *
869  * Register | BitsName
870  * ----------|--------
871  * CG_CTRL_0 | SNSADC_HCLK
872  *
873  * @retval None
874  */
875 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
876 {
877  GLOBAL_EXCEPTION_DISABLE();
878  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK);
879  GLOBAL_EXCEPTION_ENABLE();
880 }
881 
882 /**
883  * @brief Indicate whether the SNSADC automatic turn off clock is enabled.
884  *
885  * Register | BitsName
886  * ----------|--------
887  * CG_CTRL_0 | SNSADC_HCLK
888  *
889  * @retval State of bit (1 or 0).
890  */
891 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
892 {
893  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK) == (MCU_SUB_WFI_SNSADC_HCLK));
894 }
895 
896 /**
897  * @brief Enable GPIO automatic turn off clock during WFI
898  *
899  * Register | BitsName
900  * ----------|--------
901  * CG_CTRL_0 | GPIO_HCLK
902  *
903  * @retval None
904  */
905 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
906 {
907  GLOBAL_EXCEPTION_DISABLE();
908  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
909  GLOBAL_EXCEPTION_ENABLE();
910 }
911 
912 /**
913  * @brief Disable GPIO automatic turn off clock during WFI
914  *
915  * Register | BitsName
916  * ----------|--------
917  * CG_CTRL_0 | GPIO_HCLK
918  *
919  * @retval None
920  */
921 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
922 {
923  GLOBAL_EXCEPTION_DISABLE();
924  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK);
925  GLOBAL_EXCEPTION_ENABLE();
926 }
927 
928 /**
929  * @brief Indicate whether the GPIO automatic turn off clock is enabled.
930  *
931  * Register | BitsName
932  * ----------|--------
933  * CG_CTRL_0 | GPIO_HCLK
934  *
935  * @retval State of bit (1 or 0).
936  */
937 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
938 {
939  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK) == (MCU_SUB_WFI_GPIO_HCLK));
940 }
941 
942 /**
943  * @brief Enable DMA automatic turn off clock during WFI
944  *
945  * Register | BitsName
946  * ----------|--------
947  * CG_CTRL_0 | DMA_HCLK
948  *
949  * @retval None
950  */
951 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
952 {
953  GLOBAL_EXCEPTION_DISABLE();
954  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
955  GLOBAL_EXCEPTION_ENABLE();
956 }
957 
958 /**
959  * @brief Disable DMA automatic turn off clock during WFI
960  *
961  * Register | BitsName
962  * ----------|--------
963  * CG_CTRL_0 | DMA_HCLK
964  *
965  * @retval None
966  */
967 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
968 {
969  GLOBAL_EXCEPTION_DISABLE();
970  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK);
971  GLOBAL_EXCEPTION_ENABLE();
972 }
973 
974 /**
975  * @brief Indicate whether the DMA automatic turn off clock is enabled.
976  *
977  * Register | BitsName
978  * ----------|--------
979  * CG_CTRL_0 | DMA_HCLK
980  *
981  * @retval State of bit (1 or 0).
982  */
983 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
984 {
985  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK) == (MCU_SUB_WFI_DMA_HCLK));
986 }
987 
988 /**
989  * @brief Enable BLE Bridge automatic turn off clock during WFI
990  *
991  * Register | BitsName
992  * ----------|--------
993  * CG_CTRL_0 | BLE_BRG_HCLK
994  *
995  * @retval None
996  */
997 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
998 {
999  GLOBAL_EXCEPTION_DISABLE();
1000  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1001  GLOBAL_EXCEPTION_ENABLE();
1002 }
1003 
1004 /**
1005  * @brief Disable BLE Bridge automatic turn off clock during WFI
1006  *
1007  * Register | BitsName
1008  * ----------|--------
1009  * CG_CTRL_0 | BLE_BRG_HCLK
1010  *
1011  * @retval None
1012  */
1013 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1014 {
1015  GLOBAL_EXCEPTION_DISABLE();
1016  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK);
1017  GLOBAL_EXCEPTION_ENABLE();
1018 }
1019 
1020 /**
1021  * @brief Indicate whether the BLE Bridge automatic turn off clock is enabled.
1022  *
1023  * Register | BitsName
1024  * ----------|--------
1025  * CG_CTRL_0 | BLE_BRG_HCLK
1026  *
1027  * @retval State of bit (1 or 0).
1028  */
1029 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1030 {
1031  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK) == (MCU_SUB_WFI_BLE_BRG_HCLK));
1032 }
1033 
1034 /**
1035  * @brief Enable APB Subsystem automatic turn off clock during WFI
1036  *
1037  * Register | BitsName
1038  * ----------|--------
1039  * CG_CTRL_0 | APB_SUB_HCLK
1040  *
1041  * @retval None
1042  */
1043 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1044 {
1045  GLOBAL_EXCEPTION_DISABLE();
1046  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1047  GLOBAL_EXCEPTION_ENABLE();
1048 }
1049 
1050 /**
1051  * @brief Disable APB Subsystem automatic turn off clock during WFI
1052  *
1053  * Register | BitsName
1054  * ----------|--------
1055  * CG_CTRL_0 | APB_SUB_HCLK
1056  *
1057  * @retval None
1058  */
1059 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1060 {
1061  GLOBAL_EXCEPTION_DISABLE();
1062  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK);
1063  GLOBAL_EXCEPTION_ENABLE();
1064 }
1065 
1066 /**
1067  * @brief Indicate whether the APB Subsystem automatic turn off clock is enabled.
1068  *
1069  * Register | BitsName
1070  * ----------|--------
1071  * CG_CTRL_0 | APB_SUB_HCLK
1072  *
1073  * @retval State of bit (1 or 0).
1074  */
1075 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1076 {
1077  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK) == (MCU_SUB_WFI_APB_SUB_HCLK));
1078 }
1079 
1080 /**
1081  * @brief Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1082  *
1083  * Register | BitsName
1084  * ----------|--------
1085  * CG_CTRL_0 | SERIAL_HCLK
1086  *
1087  * @retval None
1088  */
1089 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1090 {
1091  GLOBAL_EXCEPTION_DISABLE();
1092  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1093  GLOBAL_EXCEPTION_ENABLE();
1094 }
1095 
1096 /**
1097  * @brief Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1098  *
1099  * Register | BitsName
1100  * ----------|--------
1101  * CG_CTRL_0 | SERIAL_HCLK
1102  *
1103  * @retval None
1104  */
1105 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1106 {
1107  GLOBAL_EXCEPTION_DISABLE();
1108  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK);
1109  GLOBAL_EXCEPTION_ENABLE();
1110 }
1111 
1112 /**
1113  * @brief Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off
1114  * clock is enabled.
1115  *
1116  * Register | BitsName
1117  * ----------|--------
1118  * CG_CTRL_0 | SERIAL_HCLK
1119  *
1120  * @retval State of bit (1 or 0).
1121  */
1122 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1123 {
1124  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK) == (MCU_SUB_WFI_SERIAL_HCLK));
1125 }
1126 
1127 /**
1128  * @brief Enable I2S slave automatic turn off clock during WFI
1129  *
1130  * Register | BitsName
1131  * ----------|--------
1132  * CG_CTRL_0 | I2S_S_HCLK
1133  *
1134  * @retval None
1135  */
1136 __STATIC_INLINE void ll_cgc_enable_wfi_off_i2s_s_hclk(void)
1137 {
1138  GLOBAL_EXCEPTION_DISABLE();
1139  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1140  GLOBAL_EXCEPTION_ENABLE();
1141 }
1142 
1143 /**
1144  * @brief Disable I2S slave automatic turn off clock during WFI
1145  *
1146  * Register | BitsName
1147  * ----------|--------
1148  * CG_CTRL_0 | I2S_S_HCLK
1149  *
1150  * @retval None
1151  */
1152 __STATIC_INLINE void ll_cgc_disable_wfi_off_i2s_s_hclk(void)
1153 {
1154  GLOBAL_EXCEPTION_DISABLE();
1155  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK);
1156  GLOBAL_EXCEPTION_ENABLE();
1157 }
1158 
1159 /**
1160  * @brief Indicate whether the I2S slave automatic turn off clock is enabled.
1161  *
1162  * Register | BitsName
1163  * ----------|--------
1164  * CG_CTRL_0 | I2S_S_HCLK
1165  *
1166  * @retval State of bit (1 or 0).
1167  */
1168 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_i2s_s_hclk(void)
1169 {
1170  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_I2S_S_HCLK) == (MCU_SUB_WFI_I2S_S_HCLK));
1171 }
1172 
1173 /**
1174  * @brief Enable AON_MUCSUB automatic turn off clock during WFI
1175  *
1176  * Register | BitsName
1177  * ----------|--------
1178  * CG_CTRL_2 | AON_MCUSUB_HCLK
1179  *
1180  * @retval None
1181  */
1182 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1183 {
1184  GLOBAL_EXCEPTION_DISABLE();
1185  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1186  GLOBAL_EXCEPTION_ENABLE();
1187 }
1188 
1189 /**
1190  * @brief Disable AON_MUCSUB automatic turn off clock during WFI
1191  *
1192  * Register | BitsName
1193  * ----------|--------
1194  * CG_CTRL_2 | AON_MCUSUB_HCLK
1195  *
1196  * @retval None
1197  */
1198 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1199 {
1200  GLOBAL_EXCEPTION_DISABLE();
1201  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK);
1202  GLOBAL_EXCEPTION_ENABLE();
1203 }
1204 
1205 /**
1206  * @brief Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
1207  *
1208  * Register | BitsName
1209  * ----------|--------
1210  * CG_CTRL_2 | AON_MCUSUB_HCLK
1211  *
1212  * @retval State of bit (1 or 0).
1213  */
1214 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1215 {
1216  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK) == (MCU_SUB_WFI_AON_MCUSUB_HCLK));
1217 }
1218 
1219 /**
1220  * @brief Enable XQSPI automatic turn off clock during WFI
1221  *
1222  * Register | BitsName
1223  * ----------|--------
1224  * CG_CTRL_2 | XF_XQSPI_HCLK
1225  *
1226  * @retval None
1227  */
1228 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1229 {
1230  GLOBAL_EXCEPTION_DISABLE();
1231  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1232  GLOBAL_EXCEPTION_ENABLE();
1233 }
1234 
1235 /**
1236  * @brief Disable XQSPI automatic turn off clock during WFI
1237  *
1238  * Register | BitsName
1239  * ----------|--------
1240  * CG_CTRL_2 | XF_XQSPI_HCLK
1241  *
1242  * @retval None
1243  */
1244 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1245 {
1246  GLOBAL_EXCEPTION_DISABLE();
1247  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK);
1248  GLOBAL_EXCEPTION_ENABLE();
1249 }
1250 
1251 /**
1252  * @brief Indicate whether the XQSPI automatic turn off clock is enabled.
1253  *
1254  * Register | BitsName
1255  * ----------|--------
1256  * CG_CTRL_2 | XF_XQSPI_HCLK
1257  *
1258  * @retval State of bit (1 or 0).
1259  */
1260 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1261 {
1262  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK) == (MCU_SUB_WFI_XF_XQSPI_HCLK));
1263 }
1264 
1265 /**
1266  * @brief Enable SRAM automatic turn off clock during WFI
1267  *
1268  * Register | BitsName
1269  * ----------|--------
1270  * CG_CTRL_2 | SRAM_HCLK
1271  *
1272  * @retval None
1273  */
1274 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1275 {
1276  GLOBAL_EXCEPTION_DISABLE();
1277  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1278  GLOBAL_EXCEPTION_ENABLE();
1279 }
1280 
1281 /**
1282  * @brief Disable SRAM automatic turn off clock during WFI
1283  *
1284  * Register | BitsName
1285  * ----------|--------
1286  * CG_CTRL_2 | SRAM_HCLK
1287  *
1288  * @retval None
1289  */
1290 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1291 {
1292  GLOBAL_EXCEPTION_DISABLE();
1293  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK);
1294  GLOBAL_EXCEPTION_ENABLE();
1295 }
1296 
1297 /**
1298  * @brief Indicate whether the SRAM automatic turn off clock is enabled.
1299  *
1300  * Register | BitsName
1301  * ----------|--------
1302  * CG_CTRL_2 | SRAM_HCLK
1303  *
1304  * @retval State of bit (1 or 0).
1305  */
1306 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1307 {
1308  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK) == (MCU_SUB_WFI_SRAM_HCLK));
1309 }
1310 
1311 /**
1312  * @brief Enable security blocks automatic turn off div4 clock during WFI
1313  *
1314  * Register | BitsName
1315  * ----------|--------
1316  * PERIPH_GC | SECU_DIV4_PCLK
1317  *
1318  * @retval None
1319  */
1320 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1321 {
1322  GLOBAL_EXCEPTION_DISABLE();
1323  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1324  GLOBAL_EXCEPTION_ENABLE();
1325 }
1326 
1327 /**
1328  * @brief Disable security blocks automatic turn off div4 clock during WFI
1329  *
1330  * Register | BitsName
1331  * ----------|--------
1332  * PERIPH_GC | SECU_DIV4_PCLK
1333  *
1334  * @retval None
1335  */
1336 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1337 {
1338  GLOBAL_EXCEPTION_DISABLE();
1339 
1340  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK);
1341 
1342  GLOBAL_EXCEPTION_ENABLE();
1343 }
1344 
1345 /**
1346  * @brief Indicate whether the security blocks automatic turn off div4
1347  * clock is enabled.
1348  *
1349  * Register | BitsName
1350  * ----------|--------
1351  * PERIPH_GC | SECU_DIV4_PCLK
1352  *
1353  * @retval State of bit (1 or 0).
1354  */
1355 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1356 {
1357  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_SECU_DIV4_PCLK) == (MCU_SUB_WFI_SECU_DIV4_PCLK));
1358 }
1359 
1360 /**
1361  * @brief Enable XQSPI automatic turn off div4 clock during WFI
1362  *
1363  * Register | BitsName
1364  * ----------|--------
1365  * PERIPH_GC | XQSPI_DIV4_PCLK
1366  *
1367  * @retval None
1368  */
1369 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1370 {
1371  GLOBAL_EXCEPTION_DISABLE();
1372 
1373  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1374 
1375  GLOBAL_EXCEPTION_ENABLE();
1376 }
1377 
1378 /**
1379  * @brief Disable XQSPI automatic turn off div4 clock during WFI
1380  *
1381  * Register | BitsName
1382  * ----------|--------
1383  * PERIPH_GC | XQSPI_DIV4_PCLK
1384  *
1385  * @retval None
1386  */
1387 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1388 {
1389  GLOBAL_EXCEPTION_DISABLE();
1390 
1391  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK);
1392 
1393  GLOBAL_EXCEPTION_ENABLE();
1394 }
1395 
1396 /**
1397  * @brief Indicate whether the XQSPI automatic turn off div4 clock is enabled.
1398  *
1399  * Register | BitsName
1400  * ----------|--------
1401  * PERIPH_GC | XQSPI_DIV4_PCLK
1402  *
1403  * @retval State of bit (1 or 0).
1404  */
1405 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1406 {
1407  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_WFI_XQSPI_DIV4_PCLK) == (MCU_SUB_WFI_XQSPI_DIV4_PCLK));
1408 }
1409 
1410 /**
1411  * @brief Enabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1412  *
1413  * Register | BitsName
1414  * ----------|--------
1415  * CG_CTRL_1 | SECU_HCLK
1416  *
1417  * @retval None
1418  */
1419 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1420 {
1421  GLOBAL_EXCEPTION_DISABLE();
1422 
1423  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1424 
1425  GLOBAL_EXCEPTION_ENABLE();
1426 }
1427 
1428 /**
1429  * @brief Disabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1430  *
1431  * Register | BitsName
1432  * ----------|--------
1433  * CG_CTRL_1 | SECU_HCLK
1434  *
1435  * @retval None
1436  */
1437 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1438 {
1439  GLOBAL_EXCEPTION_DISABLE();
1440 
1441  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK);
1442 
1443  GLOBAL_EXCEPTION_ENABLE();
1444 }
1445 
1446 /**
1447  * @brief Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
1448  *
1449  * Register | BitsName
1450  * ----------|--------
1451  * CG_CTRL_1 | SECU_HCLK
1452  *
1453  * @retval State of bit (1 or 0).
1454  */
1455 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1456 {
1457  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK) == (MCU_SUB_FORCE_SECU_HCLK));
1458 }
1459 
1460 /**
1461  * @brief Enabling force to turn off the clock for SIM.
1462  *
1463  * Register | BitsName
1464  * ----------|--------
1465  * CG_CTRL_1 | SIM_HCLK
1466  *
1467  * @retval None
1468  */
1469 __STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
1470 {
1471  GLOBAL_EXCEPTION_DISABLE();
1472 
1473  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1474 
1475  GLOBAL_EXCEPTION_ENABLE();
1476 }
1477 
1478 /**
1479  * @brief Disabling force to turn off the clock for SIM.
1480  *
1481  * Register | BitsName
1482  * ----------|--------
1483  * CG_CTRL_1 | SIM_HCLK
1484  *
1485  * @retval None
1486  */
1487 __STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
1488 {
1489  GLOBAL_EXCEPTION_DISABLE();
1490 
1491  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK);
1492 
1493  GLOBAL_EXCEPTION_ENABLE();
1494 }
1495 
1496 /**
1497  * @brief Indicate whether the clock for SIM is forced to close.
1498  *
1499  * Register | BitsName
1500  * ----------|--------
1501  * CG_CTRL_1 | SIM_HCLK
1502  *
1503  * @retval State of bit (1 or 0).
1504  */
1505 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
1506 {
1507  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK) == (MCU_SUB_FORCE_SIM_HCLK));
1508 }
1509 
1510 /**
1511  * @brief Enabling force to turn off the clock for Hopping Table.
1512  *
1513  * Register | BitsName
1514  * ----------|--------
1515  * CG_CTRL_1 | HTB_HCLK
1516  *
1517  * @retval None
1518  */
1519 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1520 {
1521  GLOBAL_EXCEPTION_DISABLE();
1522 
1523  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1524 
1525  GLOBAL_EXCEPTION_ENABLE();
1526 }
1527 
1528 /**
1529  * @brief Disabling force to turn off the clock for Hopping Table.
1530  *
1531  * Register | BitsName
1532  * ----------|--------
1533  * CG_CTRL_1 | HTB_HCLK
1534  *
1535  * @retval None
1536  */
1537 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1538 {
1539  GLOBAL_EXCEPTION_DISABLE();
1540 
1541  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK);
1542 
1543  GLOBAL_EXCEPTION_ENABLE();
1544 }
1545 
1546 /**
1547  * @brief Indicate whether the clock for Hopping Table is forced to close.
1548  *
1549  * Register | BitsName
1550  * ----------|--------
1551  * CG_CTRL_1 | HTB_HCLK
1552  *
1553  * @retval State of bit (1 or 0).
1554  */
1555 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1556 {
1557  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK) == (MCU_SUB_FORCE_HTB_HCLK));
1558 }
1559 
1560 /**
1561  * @brief Enabling force to turn off the clock for PWM.
1562  *
1563  * Register | BitsName
1564  * ----------|--------
1565  * CG_CTRL_1 | PWM_HCLK
1566  *
1567  * @retval None
1568  */
1569 __STATIC_INLINE void ll_cgc_enable_force_off_pwm_hclk(void)
1570 {
1571  GLOBAL_EXCEPTION_DISABLE();
1572 
1573  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1574 
1575  GLOBAL_EXCEPTION_ENABLE();
1576 }
1577 
1578 /**
1579  * @brief Disabling force to turn off the clock for PWM.
1580  *
1581  * Register | BitsName
1582  * ----------|--------
1583  * CG_CTRL_1 | PWM_HCLK
1584  *
1585  * @retval None
1586  */
1587 __STATIC_INLINE void ll_cgc_disable_force_off_pwm_hclk(void)
1588 {
1589  GLOBAL_EXCEPTION_DISABLE();
1590 
1591  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK);
1592 
1593  GLOBAL_EXCEPTION_ENABLE();
1594 }
1595 
1596 /**
1597  * @brief Indicate whether the clock for PWM is forced to close.
1598  *
1599  * Register | BitsName
1600  * ----------|--------
1601  * CG_CTRL_1 | PWM_HCLK
1602  *
1603  * @retval State of bit (1 or 0).
1604  */
1605 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm_hclk(void)
1606 {
1607  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_PWM_HCLK) == (MCU_SUB_FORCE_PWM_HCLK));
1608 }
1609 
1610 /**
1611  * @brief Enabling force to turn off the clock for ROM.
1612  *
1613  * Register | BitsName
1614  * ----------|--------
1615  * CG_CTRL_1 | ROM_HCLK
1616  *
1617  * @retval None
1618  */
1619 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1620 {
1621  GLOBAL_EXCEPTION_DISABLE();
1622 
1623  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1624 
1625  GLOBAL_EXCEPTION_ENABLE();
1626 }
1627 
1628 /**
1629  * @brief Disabling force to turn off the clock for ROM.
1630  *
1631  * Register | BitsName
1632  * ----------|--------
1633  * CG_CTRL_1 | ROM_HCLK
1634  *
1635  * @retval None
1636  */
1637 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1638 {
1639  GLOBAL_EXCEPTION_DISABLE();
1640 
1641  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK);
1642 
1643  GLOBAL_EXCEPTION_ENABLE();
1644 }
1645 
1646 /**
1647  * @brief Indicate whether the clock for ROM is forced to close.
1648  *
1649  * Register | BitsName
1650  * ----------|--------
1651  * CG_CTRL_1 | ROM_HCLK
1652  *
1653  * @retval State of bit (1 or 0).
1654  */
1655 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1656 {
1657  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK) == (MCU_SUB_FORCE_ROM_HCLK));
1658 }
1659 
1660 /**
1661  * @brief Enabling force to turn off the clock for SNSADC.
1662  *
1663  * Register | BitsName
1664  * ----------|--------
1665  * CG_CTRL_1 | SNSADC_HCLK
1666  *
1667  * @retval None
1668  */
1669 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1670 {
1671  GLOBAL_EXCEPTION_DISABLE();
1672 
1673  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1674 
1675  GLOBAL_EXCEPTION_ENABLE();
1676 }
1677 
1678 /**
1679  * @brief Disabling force to turn off the clock for SNSADC.
1680  *
1681  * Register | BitsName
1682  * ----------|--------
1683  * CG_CTRL_1 | SNSADC_HCLK
1684  *
1685  * @retval None
1686  */
1687 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1688 {
1689  GLOBAL_EXCEPTION_DISABLE();
1690 
1691  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK);
1692 
1693  GLOBAL_EXCEPTION_ENABLE();
1694 }
1695 
1696 /**
1697  * @brief Indicate whether the clock for SNSADC is forced to close.
1698  *
1699  * Register | BitsName
1700  * ----------|--------
1701  * CG_CTRL_1 | SNSADC_HCLK
1702  *
1703  * @retval State of bit (1 or 0).
1704  */
1705 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1706 {
1707  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK) == (MCU_SUB_FORCE_SNSADC_HCLK));
1708 }
1709 
1710 /**
1711  * @brief Enabling force to turn off the clock for GPIO.
1712  *
1713  * Register | BitsName
1714  * ----------|--------
1715  * CG_CTRL_1 | GPIO_HCLK
1716  *
1717  * @retval None
1718  */
1719 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1720 {
1721  GLOBAL_EXCEPTION_DISABLE();
1722 
1723  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1724 
1725  GLOBAL_EXCEPTION_ENABLE();
1726 }
1727 
1728 /**
1729  * @brief Disabling force to turn off the clock for GPIO.
1730  *
1731  * Register | BitsName
1732  * ----------|--------
1733  * CG_CTRL_1 | GPIO_HCLK
1734  *
1735  * @retval None
1736  */
1737 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1738 {
1739  GLOBAL_EXCEPTION_DISABLE();
1740 
1741  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK);
1742 
1743  GLOBAL_EXCEPTION_ENABLE();
1744 }
1745 
1746 /**
1747  * @brief Indicate whether the clock for GPIO is forced to close.
1748  *
1749  * Register | BitsName
1750  * ----------|--------
1751  * CG_CTRL_1 | GPIO_HCLK
1752  *
1753  * @retval State of bit (1 or 0).
1754  */
1755 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1756 {
1757  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK) == (MCU_SUB_FORCE_GPIO_HCLK));
1758 }
1759 
1760 /**
1761  * @brief Enabling force to turn off the clock for DMA.
1762  *
1763  * Register | BitsName
1764  * ----------|--------
1765  * CG_CTRL_1 | DMA_HCLK
1766  *
1767  * @retval None
1768  */
1769 __STATIC_INLINE void ll_cgc_enable_force_off_dma_hclk(void)
1770 {
1771  GLOBAL_EXCEPTION_DISABLE();
1772 
1773  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1774 
1775  GLOBAL_EXCEPTION_ENABLE();
1776 }
1777 
1778 /**
1779  * @brief Disabling force to turn off the clock for DMA.
1780  *
1781  * Register | BitsName
1782  * ----------|--------
1783  * CG_CTRL_1 | DMA_HCLK
1784  *
1785  * @retval None
1786  */
1787 __STATIC_INLINE void ll_cgc_disable_force_off_dma_hclk(void)
1788 {
1789  GLOBAL_EXCEPTION_DISABLE();
1790 
1791  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK);
1792 
1793  GLOBAL_EXCEPTION_ENABLE();
1794 }
1795 
1796 /**
1797  * @brief Indicate whether the clock for DMA is forced to close.
1798  *
1799  * Register | BitsName
1800  * ----------|--------
1801  * CG_CTRL_1 | DMA_HCLK
1802  *
1803  * @retval State of bit (1 or 0).
1804  */
1805 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma_hclk(void)
1806 {
1807  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_DMA_HCLK) == (MCU_SUB_FORCE_DMA_HCLK));
1808 }
1809 
1810 /**
1811  * @brief Enabling force to turn off the clock for BLE Bridge.
1812  *
1813  * Register | BitsName
1814  * ----------|--------
1815  * CG_CTRL_1 | BLE_BRG_HCLK
1816  *
1817  * @retval None
1818  */
1819 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1820 {
1821  GLOBAL_EXCEPTION_DISABLE();
1822 
1823  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1824 
1825  GLOBAL_EXCEPTION_ENABLE();
1826 }
1827 
1828 /**
1829  * @brief Disabling force to turn off the clock for BLE Bridge.
1830  *
1831  * Register | BitsName
1832  * ----------|--------
1833  * CG_CTRL_1 | BLE_BRG_HCLK
1834  *
1835  * @retval None
1836  */
1837 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1838 {
1839  GLOBAL_EXCEPTION_DISABLE();
1840 
1841  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK);
1842 
1843  GLOBAL_EXCEPTION_ENABLE();
1844 }
1845 
1846 /**
1847  * @brief Indicate whether the clock for BLE Bridge is forced to close.
1848  *
1849  * Register | BitsName
1850  * ----------|--------
1851  * CG_CTRL_1 | BLE_BRG_HCLK
1852  *
1853  * @retval State of bit (1 or 0).
1854  */
1855 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1856 {
1857  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK) == (MCU_SUB_FORCE_BLE_BRG_HCLK));
1858 }
1859 
1860 /**
1861  * @brief Enabling force to turn off the clock for APB Subsystem.
1862  *
1863  * Register | BitsName
1864  * ----------|--------
1865  * CG_CTRL_1 | APB_SUB_HCLK
1866  *
1867  * @retval None
1868  */
1869 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1870 {
1871  GLOBAL_EXCEPTION_DISABLE();
1872 
1873  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1874 
1875  GLOBAL_EXCEPTION_ENABLE();
1876 }
1877 
1878 /**
1879  * @brief Disabling force to turn off the clock for APB Subsystem.
1880  *
1881  * Register | BitsName
1882  * ----------|--------
1883  * CG_CTRL_1 | APB_SUB_HCLK
1884  *
1885  * @retval None
1886  */
1887 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1888 {
1889  GLOBAL_EXCEPTION_DISABLE();
1890 
1891  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK);
1892 
1893  GLOBAL_EXCEPTION_ENABLE();
1894 }
1895 
1896 /**
1897  * @brief Indicate whether the clock for APB Subsystem is forced to close.
1898  *
1899  * Register | BitsName
1900  * ----------|--------
1901  * CG_CTRL_1 | APB_SUB_HCLK
1902  *
1903  * @retval State of bit (1 or 0).
1904  */
1905 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1906 {
1907  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK) == (MCU_SUB_FORCE_APB_SUB_HCLK));
1908 }
1909 
1910 /**
1911  * @brief Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1912  *
1913  * Register | BitsName
1914  * ----------|--------
1915  * CG_CTRL_1 | SERIAL_HCLK
1916  *
1917  * @retval None
1918  */
1919 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1920 {
1921  GLOBAL_EXCEPTION_DISABLE();
1922 
1923  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1924 
1925  GLOBAL_EXCEPTION_ENABLE();
1926 }
1927 
1928 /**
1929  * @brief Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1930  *
1931  * Register | BitsName
1932  * ----------|--------
1933  * CG_CTRL_1 | SERIAL_HCLK
1934  *
1935  * @retval None
1936  */
1937 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1938 {
1939  GLOBAL_EXCEPTION_DISABLE();
1940 
1941  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK);
1942 
1943  GLOBAL_EXCEPTION_ENABLE();
1944 }
1945 
1946 /**
1947  * @brief Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
1948  *
1949  * Register | BitsName
1950  * ----------|--------
1951  * CG_CTRL_1 | SERIAL_HCLK
1952  *
1953  * @retval State of bit (1 or 0).
1954  */
1955 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1956 {
1957  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK) == (MCU_SUB_FORCE_SERIAL_HCLK));
1958 }
1959 
1960 /**
1961  * @brief Enabling force to turn off the clock for I2S slave.
1962  *
1963  * Register | BitsName
1964  * ----------|--------
1965  * CG_CTRL_1 | I2S_S_HCLK
1966  *
1967  * @retval None
1968  */
1969 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_hclk(void)
1970 {
1971  GLOBAL_EXCEPTION_DISABLE();
1972 
1973  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1974 
1975  GLOBAL_EXCEPTION_ENABLE();
1976 }
1977 
1978 /**
1979  * @brief Disabling force to turn off the clock for I2S slave.
1980  *
1981  * Register | BitsName
1982  * ----------|--------
1983  * CG_CTRL_1 | I2S_S_HCLK
1984  *
1985  * @retval None
1986  */
1987 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_hclk(void)
1988 {
1989  GLOBAL_EXCEPTION_DISABLE();
1990 
1991  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK);
1992 
1993  GLOBAL_EXCEPTION_ENABLE();
1994 }
1995 
1996 /**
1997  * @brief Indicate whether the clock for I2S slave is forced to close.
1998  *
1999  * Register | BitsName
2000  * ----------|--------
2001  * CG_CTRL_1 | I2S_S_HCLK
2002  *
2003  * @retval State of bit (1 or 0).
2004  */
2005 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_hclk(void)
2006 {
2007  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_I2S_S_HCLK) == (MCU_SUB_FORCE_I2S_S_HCLK));
2008 }
2009 
2010 /**
2011  * @brief Enabling force to turn off the clock for AON_MUCSUB.
2012  *
2013  * Register | BitsName
2014  * ----------|--------
2015  * CG_CTRL_2 | AON_MCUSUB_HCLK
2016  *
2017  * @retval None
2018  */
2020 {
2021  GLOBAL_EXCEPTION_DISABLE();
2022 
2023  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2024 
2025  GLOBAL_EXCEPTION_ENABLE();
2026 }
2027 
2028 /**
2029  * @brief Disabling force to turn off the clock for AON_MUCSUB.
2030  *
2031  * Register | BitsName
2032  * ----------|--------
2033  * CG_CTRL_2 | AON_MCUSUB_HCLK
2034  *
2035  * @retval None
2036  */
2038 {
2039  GLOBAL_EXCEPTION_DISABLE();
2040 
2041  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK);
2042 
2043  GLOBAL_EXCEPTION_ENABLE();
2044 }
2045 
2046 /**
2047  * @brief Indicate whether the clock for AON_MUCSUB is forced to close.
2048  *
2049  * Register | BitsName
2050  * ----------|--------
2051  * CG_CTRL_2 | AON_MCUSUB_HCLK
2052  *
2053  * @retval State of bit (1 or 0).
2054  */
2055 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
2056 {
2057  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK) == (MCU_SUB_FORCE_AON_MCUSUB_HCLK));
2058 }
2059 
2060 /**
2061  * @brief Enabling force to turn off the clock for XQSPI.
2062  *
2063  * Register | BitsName
2064  * ----------|--------
2065  * CG_CTRL_2 | XF_XQSPI_HCLK
2066  *
2067  * @retval None
2068  */
2069 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
2070 {
2071  GLOBAL_EXCEPTION_DISABLE();
2072 
2073  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2074 
2075  GLOBAL_EXCEPTION_ENABLE();
2076 }
2077 
2078 /**
2079  * @brief Disabling force to turn off the clock for XQSPI.
2080  *
2081  * Register | BitsName
2082  * ----------|--------
2083  * CG_CTRL_2 | XF_XQSPI_HCLK
2084  *
2085  * @retval None
2086  */
2087 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
2088 {
2089  GLOBAL_EXCEPTION_DISABLE();
2090 
2091  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK);
2092 
2093  GLOBAL_EXCEPTION_ENABLE();
2094 }
2095 
2096 /**
2097  * @brief Indicate whether the clock for XQSPI is forced to close.
2098  *
2099  * Register | BitsName
2100  * ----------|--------
2101  * CG_CTRL_2 | XF_XQSPI_HCLK
2102  *
2103  * @retval State of bit (1 or 0).
2104  */
2105 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
2106 {
2107  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK) == (MCU_SUB_FORCE_XF_XQSPI_HCLK));
2108 }
2109 
2110 /**
2111  * @brief Enabling force to turn off the clock for SRAM.
2112  *
2113  * Register | BitsName
2114  * ----------|--------
2115  * CG_CTRL_2 | SRAM_HCLK
2116  *
2117  * @retval None
2118  */
2119 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
2120 {
2121  GLOBAL_EXCEPTION_DISABLE();
2122 
2123  SET_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2124 
2125  GLOBAL_EXCEPTION_ENABLE();
2126 }
2127 
2128 /**
2129  * @brief Disabling force to turn off the clock for SRAM.
2130  *
2131  * Register | BitsName
2132  * ----------|--------
2133  * CG_CTRL_2 | SRAM_HCLK
2134  *
2135  * @retval None
2136  */
2137 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
2138 {
2139  GLOBAL_EXCEPTION_DISABLE();
2140 
2141  CLEAR_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK);
2142 
2143  GLOBAL_EXCEPTION_ENABLE();
2144 }
2145 
2146 /**
2147  * @brief Indicate whether the clock for SRAM is forced to close.
2148  *
2149  * Register | BitsName
2150  * ----------|--------
2151  * CG_CTRL_2 | SRAM_HCLK
2152  *
2153  * @retval State of bit (1 or 0).
2154  */
2155 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
2156 {
2157  return (READ_BITS(MCU_SUB->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK) == (MCU_SUB_FORCE_SRAM_HCLK));
2158 }
2159 
2160 /**
2161  * @brief Enabling force to turn off the clock for UART0.
2162  *
2163  * Register | BitsName
2164  * ----------|--------
2165  * PERIPH_GC | UART0_HCLK
2166  *
2167  * @retval None
2168  */
2169 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
2170 {
2171  GLOBAL_EXCEPTION_DISABLE();
2172 
2173  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2174 
2175  GLOBAL_EXCEPTION_ENABLE();
2176 }
2177 
2178 /**
2179  * @brief Disabling force to turn off the clock for UART0.
2180  *
2181  * Register | BitsName
2182  * ----------|--------
2183  * PERIPH_GC | UART0_HCLK
2184  *
2185  * @retval None
2186  */
2187 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
2188 {
2189  GLOBAL_EXCEPTION_DISABLE();
2190 
2191  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK);
2192 
2193  GLOBAL_EXCEPTION_ENABLE();
2194 }
2195 
2196 /**
2197  * @brief Indicate whether the clock for UART0 is forced to close.
2198  *
2199  * Register | BitsName
2200  * ----------|--------
2201  * PERIPH_GC | UART0_HCLK
2202  *
2203  * @retval State of bit (1 or 0).
2204  */
2205 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
2206 {
2207  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART0_HCLK) == (MCU_SUB_FORCE_UART0_HCLK));
2208 }
2209 
2210 /**
2211  * @brief Enabling force to turn off the clock for UART1.
2212  *
2213  * Register | BitsName
2214  * ----------|--------
2215  * PERIPH_GC | UART1_HCLK
2216  *
2217  * @retval None
2218  */
2219 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
2220 {
2221  GLOBAL_EXCEPTION_DISABLE();
2222 
2223  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2224 
2225  GLOBAL_EXCEPTION_ENABLE();
2226 }
2227 
2228 /**
2229  * @brief Disabling force to turn off the clock for UART1.
2230  *
2231  * Register | BitsName
2232  * ----------|--------
2233  * PERIPH_GC | UART1_HCLK
2234  *
2235  * @retval None
2236  */
2237 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
2238 {
2239  GLOBAL_EXCEPTION_DISABLE();
2240 
2241  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK);
2242 
2243  GLOBAL_EXCEPTION_ENABLE();
2244 }
2245 
2246 /**
2247  * @brief Indicate whether the clock for UART1 is forced to close.
2248  *
2249  * Register | BitsName
2250  * ----------|--------
2251  * PERIPH_GC | UART1_HCLK
2252  *
2253  * @retval State of bit (1 or 0).
2254  */
2255 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
2256 {
2257  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_UART1_HCLK) == (MCU_SUB_FORCE_UART1_HCLK));
2258 }
2259 
2260 /**
2261  * @brief Enabling force to turn off the clock for I2C0.
2262  *
2263  * Register | BitsName
2264  * ----------|--------
2265  * PERIPH_GC | I2C0_HCLK
2266  *
2267  * @retval None
2268  */
2269 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2270 {
2271  GLOBAL_EXCEPTION_DISABLE();
2272 
2273  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2274 
2275  GLOBAL_EXCEPTION_ENABLE();
2276 }
2277 
2278 /**
2279  * @brief Disabling force to turn off the clock for I2C0.
2280  *
2281  * Register | BitsName
2282  * ----------|--------
2283  * PERIPH_GC | I2C0_HCLK
2284  *
2285  * @retval None
2286  */
2287 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2288 {
2289  GLOBAL_EXCEPTION_DISABLE();
2290 
2291  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK);
2292 
2293  GLOBAL_EXCEPTION_ENABLE();
2294 }
2295 
2296 /**
2297  * @brief Indicate whether the clock for I2C0 is forced to close.
2298  *
2299  * Register | BitsName
2300  * ----------|--------
2301  * PERIPH_GC | I2C0_HCLK
2302  *
2303  * @retval State of bit (1 or 0).
2304  */
2305 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2306 {
2307  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C0_HCLK) == (MCU_SUB_FORCE_I2C0_HCLK));
2308 }
2309 
2310 /**
2311  * @brief Enabling force to turn off the clock for I2C1.
2312  *
2313  * Register | BitsName
2314  * ----------|--------
2315  * PERIPH_GC | I2C1_HCLK
2316  *
2317  * @retval None
2318  */
2319 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2320 {
2321  GLOBAL_EXCEPTION_DISABLE();
2322 
2323  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2324 
2325  GLOBAL_EXCEPTION_ENABLE();
2326 }
2327 
2328 /**
2329  * @brief Disabling force to turn off the clock for I2C1.
2330  *
2331  * Register | BitsName
2332  * ----------|--------
2333  * PERIPH_GC | I2C1_HCLK
2334  *
2335  * @retval None
2336  */
2337 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2338 {
2339  GLOBAL_EXCEPTION_DISABLE();
2340 
2341  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK);
2342 
2343  GLOBAL_EXCEPTION_ENABLE();
2344 }
2345 
2346 /**
2347  * @brief Indicate whether the clock for I2C1 is forced to close.
2348  *
2349  * Register | BitsName
2350  * ----------|--------
2351  * PERIPH_GC | I2C1_HCLK
2352  *
2353  * @retval State of bit (1 or 0).
2354  */
2355 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2356 {
2357  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2C1_HCLK) == (MCU_SUB_FORCE_I2C1_HCLK));
2358 }
2359 
2360 /**
2361  * @brief Enabling force to turn off the clock for SPIM.
2362  *
2363  * Register | BitsName
2364  * ----------|--------
2365  * PERIPH_GC | SPIM_HCLK
2366  *
2367  * @retval None
2368  */
2369 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2370 {
2371  GLOBAL_EXCEPTION_DISABLE();
2372 
2373  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2374 
2375  GLOBAL_EXCEPTION_ENABLE();
2376 }
2377 
2378 /**
2379  * @brief Disabling force to turn off the clock for SPIM.
2380  *
2381  * Register | BitsName
2382  * ----------|--------
2383  * PERIPH_GC | SPIM_HCLK
2384  *
2385  * @retval None
2386  */
2387 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2388 {
2389  GLOBAL_EXCEPTION_DISABLE();
2390 
2391  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK);
2392 
2393  GLOBAL_EXCEPTION_ENABLE();
2394 }
2395 
2396 /**
2397  * @brief Indicate whether the clock for SPIM is forced to close.
2398  *
2399  * Register | BitsName
2400  * ----------|--------
2401  * PERIPH_GC | SPIM_HCLK
2402  *
2403  * @retval State of bit (1 or 0).
2404  */
2405 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2406 {
2407  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIM_HCLK) == (MCU_SUB_FORCE_SPIM_HCLK));
2408 }
2409 
2410 /**
2411  * @brief Enabling force to turn off the clock for SPIS.
2412  *
2413  * Register | BitsName
2414  * ----------|--------
2415  * PERIPH_GC | SPIS_HCLK
2416  *
2417  * @retval None
2418  */
2419 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2420 {
2421  GLOBAL_EXCEPTION_DISABLE();
2422 
2423  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2424 
2425  GLOBAL_EXCEPTION_ENABLE();
2426 }
2427 
2428 /**
2429  * @brief Disabling force to turn off the clock for SPIS.
2430  *
2431  * Register | BitsName
2432  * ----------|--------
2433  * PERIPH_GC | SPIS_HCLK
2434  *
2435  * @retval None
2436  */
2437 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2438 {
2439  GLOBAL_EXCEPTION_DISABLE();
2440 
2441  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK);
2442 
2443  GLOBAL_EXCEPTION_ENABLE();
2444 }
2445 
2446 /**
2447  * @brief Indicate whether the clock for SPIS is forced to close.
2448  *
2449  * Register | BitsName
2450  * ----------|--------
2451  * PERIPH_GC | SPIS_HCLK
2452  *
2453  * @retval State of bit (1 or 0).
2454  */
2455 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2456 {
2457  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SPIS_HCLK) == (MCU_SUB_FORCE_SPIS_HCLK));
2458 }
2459 
2460 /**
2461  * @brief Enabling force to turn off the clock for QSPI0.
2462  *
2463  * Register | BitsName
2464  * ----------|--------
2465  * PERIPH_GC | QSPI0_HCLK
2466  *
2467  * @retval None
2468  */
2469 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2470 {
2471  GLOBAL_EXCEPTION_DISABLE();
2472 
2473  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2474 
2475  GLOBAL_EXCEPTION_ENABLE();
2476 }
2477 
2478 /**
2479  * @brief Disabling force to turn off the clock for QSPI0.
2480  *
2481  * Register | BitsName
2482  * ----------|--------
2483  * PERIPH_GC | QSPI0_HCLK
2484  *
2485  * @retval None
2486  */
2487 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2488 {
2489  GLOBAL_EXCEPTION_DISABLE();
2490 
2491  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK);
2492 
2493  GLOBAL_EXCEPTION_ENABLE();
2494 }
2495 
2496 /**
2497  * @brief Indicate whether the clock for QSPI0 is forced to close.
2498  *
2499  * Register | BitsName
2500  * ----------|--------
2501  * PERIPH_GC | QSPI0_HCLK
2502  *
2503  * @retval State of bit (1 or 0).
2504  */
2505 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2506 {
2507  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI0_HCLK) == (MCU_SUB_FORCE_QSPI0_HCLK));
2508 }
2509 
2510 /**
2511  * @brief Enabling force to turn off the clock for QSPI1.
2512  *
2513  * Register | BitsName
2514  * ----------|--------
2515  * PERIPH_GC | QSPI1_HCLK
2516  *
2517  * @retval None
2518  */
2519 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2520 {
2521  GLOBAL_EXCEPTION_DISABLE();
2522 
2523  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2524 
2525  GLOBAL_EXCEPTION_ENABLE();
2526 }
2527 
2528 /**
2529  * @brief Disabling force to turn off the clock for QSPI1.
2530  *
2531  * Register | BitsName
2532  * ----------|--------
2533  * PERIPH_GC | QSPI1_HCLK
2534  *
2535  * @retval None
2536  */
2537 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2538 {
2539  GLOBAL_EXCEPTION_DISABLE();
2540 
2541  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK);
2542 
2543  GLOBAL_EXCEPTION_ENABLE();
2544 }
2545 
2546 /**
2547  * @brief Indicate whether the clock for QSPI1 is forced to close.
2548  *
2549  * Register | BitsName
2550  * ----------|--------
2551  * PERIPH_GC | QSPI1_HCLK
2552  *
2553  * @retval State of bit (1 or 0).
2554  */
2555 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2556 {
2557  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_QSPI1_HCLK) == (MCU_SUB_FORCE_QSPI1_HCLK));
2558 }
2559 
2560 /**
2561  * @brief Enabling force to turn off the clock for I2S master.
2562  *
2563  * Register | BitsName
2564  * ----------|--------
2565  * PERIPH_GC | I2S_HCLK
2566  *
2567  * @retval None
2568  */
2569 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2570 {
2571  GLOBAL_EXCEPTION_DISABLE();
2572 
2573  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2574 
2575  GLOBAL_EXCEPTION_ENABLE();
2576 }
2577 
2578 /**
2579  * @brief Disabling force to turn off the clock for I2S master.
2580  *
2581  * Register | BitsName
2582  * ----------|--------
2583  * PERIPH_GC | I2S_HCLK
2584  *
2585  * @retval None
2586  */
2587 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2588 {
2589  GLOBAL_EXCEPTION_DISABLE();
2590 
2591  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK);
2592 
2593  GLOBAL_EXCEPTION_ENABLE();
2594 }
2595 
2596 /**
2597  * @brief Indicate whether the clock for I2S master is forced to close.
2598  *
2599  * Register | BitsName
2600  * ----------|--------
2601  * PERIPH_GC | I2S_HCLK
2602  *
2603  * @retval State of bit (1 or 0).
2604  */
2605 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2606 {
2607  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_I2S_HCLK) == (MCU_SUB_FORCE_I2S_HCLK));
2608 }
2609 
2610 /**
2611  * @brief Enabling force to turn off the div4 clock for security blocks.
2612  *
2613  * Register | BitsName
2614  * ----------|--------
2615  * PERIPH_GC | I2S_HCLK
2616  *
2617  * @retval None
2618  */
2619 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
2620 {
2621  GLOBAL_EXCEPTION_DISABLE();
2622 
2623  SET_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2624 
2625  GLOBAL_EXCEPTION_ENABLE();
2626 }
2627 
2628 /**
2629  * @brief Disabling force to turn off the div4 clock for security blocks.
2630  *
2631  * Register | BitsName
2632  * ----------|--------
2633  * PERIPH_GC | I2S_HCLK
2634  *
2635  * @retval None
2636  */
2638 {
2639  GLOBAL_EXCEPTION_DISABLE();
2640 
2641  CLEAR_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK);
2642 
2643  GLOBAL_EXCEPTION_ENABLE();
2644 }
2645 
2646 /**
2647  * @brief Indicate whether the div4 clock for security blocks is forced to close.
2648  *
2649  * Register | BitsName
2650  * ----------|--------
2651  * PERIPH_GC | I2S_HCLK
2652  *
2653  * @retval State of bit (1 or 0).
2654  */
2655 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
2656 {
2657  return (READ_BITS(MCU_SUB->MCU_PERIPH_CG, MCU_SUB_FORCE_SECU_DIV4_PCLK) == (MCU_SUB_FORCE_SECU_DIV4_PCLK));
2658 }
2659 
2660 
2661 /** @} */
2662 
2663 /** @defgroup CGC_LL_EF_Init Initialization and de-initialization functions
2664  * @{
2665  */
2666 
2667 /**
2668  * @brief De-initialize CGC registers (Registers restored to their default values).
2669  * @retval An error_status_t enumeration value:
2670  * - SUCCESS: CGC registers are de-initialized
2671  * - ERROR: CGC registers are not de-initialized
2672  */
2673 error_status_t ll_cgc_deinit(void);
2674 
2675 /**
2676  * @brief Initialize CGC registers according to the specified.
2677  * parameters in p_cgc_init.
2678  * @param p_cgc_init Pointer to a ll_cgc_init_t structure that contains the configuration
2679  * information for the specified CGC register.
2680  * @retval An error_status_t enumeration value:
2681  * - SUCCESS: CGC registers are initialized according to p_cgc_init content
2682  * - ERROR: Problem occurred during CGC Registers initialization
2683  */
2684 error_status_t ll_cgc_init(ll_cgc_init_t *p_cgc_init);
2685 
2686 /**
2687  * @brief Set each field of a @ref ll_cgc_init_t type structure to default value.
2688  * @param p_cgc_init Pointer to a @ref ll_cgc_init_t structure
2689  * whose fields will be set to default values.
2690  * @retval None
2691  */
2693 
2694 /** @} */
2695 
2696 /** @} */
2697 
2698 
2699 #endif /* CGC */
2700 
2701 #ifdef __cplusplus
2702 }
2703 #endif
2704 
2705 #endif /* __GR55XX_LL_CGC_H__ */
2706 
2707 /** @} */
2708 
2709 /** @} */
2710 
2711 /** @} */
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr55xx_ll_cgc.h:460
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:983
ll_cgc_disable_force_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma_hclk(void)
Disabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1787
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1887
ll_cgc_enable_wfi_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_i2s_s_hclk(void)
Enable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1136
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:875
_ll_cgc_init_t::wfi_clk2
uint32_t wfi_clk2
Definition: gr55xx_ll_cgc.h:84
ll_cgc_enable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:767
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:721
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1737
_ll_cgc_init_t::wfi_clk1
uint32_t wfi_clk1
Definition: gr55xx_ll_cgc.h:81
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/DMA/B...
Definition: gr55xx_ll_cgc.h:498
ll_cgc_disable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:783
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1198
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2269
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1437
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:937
ll_cgc_enable_force_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm_hclk(void)
Enabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1569
ll_cgc_init_t
struct _ll_cgc_init_t ll_cgc_init_t
LL CGC init Structure definition.
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:2055
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1182
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2587
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1306
_ll_cgc_init_t::force_clk0
uint32_t force_clk0
Definition: gr55xx_ll_cgc.h:87
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1013
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1919
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1214
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:891
ll_cgc_is_enabled_wfi_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:799
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:2155
ll_cgc_deinit
error_status_t ll_cgc_deinit(void)
De-initialize CGC registers (Registers restored to their default values).
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:540
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2087
ll_cgc_disable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:691
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2137
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:2255
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1555
ll_cgc_is_enabled_force_off_i2s_s_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2005
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2319
ll_cgc_enable_force_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma_hclk(void)
Enabling force to turn off the clock for DMA.
Definition: gr55xx_ll_cgc.h:1769
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2387
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2419
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1819
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2305
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1637
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1669
ll_cgc_is_enabled_force_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm_hclk(void)
Indicate whether the clock for PWM is forced to close.
Definition: gr55xx_ll_cgc.h:1605
ll_cgc_disable_force_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm_hclk(void)
Disabling force to turn off the clock for PWM.
Definition: gr55xx_ll_cgc.h:1587
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:967
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1105
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1405
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2505
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2355
ll_cgc_is_enabled_wfi_off_i2s_s_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_i2s_s_hclk(void)
Indicate whether the I2S slave automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1168
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2555
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2105
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1228
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:661
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr55xx_ll_cgc.h:342
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2069
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1755
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO...
Definition: gr55xx_ll_cgc.h:304
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:845
ll_cgc_disable_wfi_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_i2s_s_hclk(void)
Disable I2S slave automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1152
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:629
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:859
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2369
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1687
ll_cgc_enable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
Enabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1469
ll_cgc_disable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
Disabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1487
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/...
Definition: gr55xx_ll_cgc.h:615
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2637
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2337
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1869
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:921
_ll_cgc_init_t::wfi_clk0
uint32_t wfi_clk0
Definition: gr55xx_ll_cgc.h:78
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1122
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2287
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:905
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2437
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr55xx_ll_cgc.h:402
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:363
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:519
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2487
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1387
_ll_cgc_init_t::force_clk1
uint32_t force_clk1
Definition: gr55xx_ll_cgc.h:90
ll_cgc_disable_force_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1987
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1905
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1059
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1837
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1089
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1290
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:421
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2019
ll_cgc_init
error_status_t ll_cgc_init(ll_cgc_init_t *p_cgc_init)
Initialize CGC registers according to the specified. parameters in p_cgc_init.
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1955
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2037
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2519
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:737
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2469
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1029
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:2205
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1043
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:384
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2169
_ll_cgc_init_t::force_clk2
uint32_t force_clk2
Definition: gr55xx_ll_cgc.h:93
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2219
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1619
ll_cgc_is_enabled_wfi_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:707
ll_cgc_is_enabled_force_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
Indicate whether the clock for SIM is forced to close.
Definition: gr55xx_ll_cgc.h:1505
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1719
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:951
_ll_cgc_init_t
LL CGC init Structure definition.
Definition: gr55xx_ll_cgc.h:77
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1537
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:997
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1855
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2119
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1075
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1244
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/I2C0_HCLK/ I2C1_HCLK/SPIM_HCLK...
Definition: gr55xx_ll_cgc.h:577
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1260
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1369
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:2619
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1355
ll_cgc_enable_force_off_i2s_s_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:1969
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2237
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:753
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1419
ll_cgc_struct_init
void ll_cgc_struct_init(ll_cgc_init_t *p_cgc_init)
Set each field of a ll_cgc_init_t type structure to default value.
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1336
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1320
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2405
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1655
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2605
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:645
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:813
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2537
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2569
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1519
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2455
ll_cgc_enable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:675
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2187
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1937
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1455
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:829
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1705
ll_cgc_is_enabled_force_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma_hclk(void)
Indicate whether the clock for DMA is forced to close.
Definition: gr55xx_ll_cgc.h:1805
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:2655
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1274