gr55xx_ll_aes.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aes.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AES LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AES AES
47 * @brief AES LL module driver.
48 * @{
49 */
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "gr55xx.h"
60
61 #if defined (AES)
62
63 /** @defgroup AES_LL_STRUCTURES Structures
64 * @{
65 */
66
67 /* Exported types ------------------------------------------------------------*/
68 /** @defgroup AES_LL_ES_INIT AES Exported Init structures
69 * @{
70 */
71
72 /**
73 * @brief LL AES Init Structure definition
74 */
75 typedef struct _ll_aes_init
76 {
77 uint32_t key_size; /**< 128, 192 or 256-bit key length.
78 This parameter can be a value of @ref AES_LL_EC_KEY_SIZE */
79
80 uint32_t *p_key; /**< Encryption/Decryption Key */
81
82 uint32_t *p_init_vector; /**< Initialization Vector used for CBC modes */
83
84 uint32_t *p_seed; /**< Random seeds */
85
86 } ll_aes_init_t;
87
88 /** @} */
89
90 /** @} */
91
92 /**
93 * @defgroup AES_LL_MACRO Defines
94 * @{
95 */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup AES_LL_Exported_Constants AES Exported Constants
99 * @{
100 */
101
102 /** @defgroup AES_LL_EC_GET_FLAG Get Flag Defines
103 * @brief Flag definitions which can be used with LL_AES_ReadReg function
104 * @{
105 */
106 #define LL_AES_FLAG_DATAREADY AES_STATUS_READY /**< AES result data out ready */
107 #define LL_AES_FLAG_DMA_DONE AES_STATUS_TRANSDONE /**< AES dma transfer done */
108 #define LL_AES_FLAG_DMA_ERR AES_STATUS_TRANSERR /**< AES dma transfer error */
109 #define LL_AES_FLAG_KEY_VALID AES_STATUS_KEYVALID /**< AES has fetched key */
110 /** @} */
111
112 /** @defgroup AES_LL_EC_KEY_SIZE Key Size
113 * @{
114 */
115 #define LL_AES_KEY_SIZE_128 0x00000000U /**< 128 bits */
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CONFIG_KEYMODE_Pos) /**< 192 bits */
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CONFIG_KEYMODE_Pos) /**< 256 bits */
118 /** @} */
119
120 /** @defgroup AES_LL_EC_OPERATION_MODE Operation Mode
121 * @{
122 */
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U /**< Electronic codebook (ECB) mode */
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CONFIG_OPMODE_Pos) /**< Cipher block chaining (CBC) mode */
125 /** @} */
126
127 /** @defgroup AES_LL_EC_KEY_TYPE Key Type
128 * @{
129 */
130 #define LL_AES_KEYTYPE_MCU 0x00000000U /**< MCU */
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CONFIG_KEYTYPE_Pos) /**< AHB master */
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CONFIG_KEYTYPE_Pos) /**< Key Port */
133 /** @} */
134
135 /** @defgroup AES_LL_EC_TRANSFER_SIZE Transfer Size
136 * @{
137 */
138 #define LL_AES_DMA_TRANSIZE_MIN (1) /**< Min size = 1 block */
139 #define LL_AES_DMA_TRANSIZE_MAX (2048) /**< Max size = 2048 blocks */
140 /** @} */
141
142 /** @} */
143
144 /* Exported macro ------------------------------------------------------------*/
145 /** @defgroup AES_LL_Exported_Macros AES Exported Macros
146 * @{
147 */
148
149 /** @defgroup AES_LL_EM_WRITE_READ Common Write and read registers Macros
150 * @{
151 */
152
153 /**
154 * @brief Write a value in AES register
155 * @param __INSTANCE__ AES Instance
156 * @param __REG__ Register to be written
157 * @param __VALUE__ Value to be written in the register
158 * @retval None
159 */
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
161
162 /**
163 * @brief Read a value in AES register
164 * @param __INSTANCE__ AES Instance
165 * @param __REG__ Register to be read
166 * @retval Register value
167 */
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
169
170 /** @} */
171
172 /** @} */
173
174 /** @} */
175
176 /* Exported functions --------------------------------------------------------*/
177 /** @defgroup AES_LL_DRIVER_FUNCTIONS Functions
178 * @{
179 */
180
181 /** @defgroup AES_LL_EF_Configuration Configuration functions
182 * @{
183 */
184
185 /**
186 * @brief Enable AES.
187 *
188 * \rst
189 * +----------------------+-----------------------------+
190 * | Register | BitsName |
191 * +======================+=============================+
192 * | CTRL | ENABLE |
193 * +----------------------+-----------------------------+
194 * \endrst
195 *
196 * @param AESx AES instance
197 * @retval None
198 */
199 __STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
200 {
201 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE);
202 }
203
204 /**
205 * @brief Disable AES.
206 *
207 * \rst
208 * +----------------------+-----------------------------+
209 * | Register | BitsName |
210 * +======================+=============================+
211 * | CTRL | ENABLE |
212 * +----------------------+-----------------------------+
213 * \endrst
214 *
215 * @param AESx AES instance
216 * @retval None
217 */
218 __STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
219 {
220 CLEAR_BITS(AESx->CTRL, AES_CTRL_ENABLE);
221 }
222
223 /**
224 * @brief Indicate whether the AES is enabled.
225 *
226 * \rst
227 * +----------------------+-----------------------------+
228 * | Register | BitsName |
229 * +======================+=============================+
230 * | CTRL | ENABLE |
231 * +----------------------+-----------------------------+
232 * \endrst
233 *
234 * @param AESx AES instance
235 * @retval State of bit (1 or 0).
236 */
237 __STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
238 {
239 return (READ_BITS(AESx->CTRL, AES_CTRL_ENABLE) == (AES_CTRL_ENABLE));
240 }
241
242 /**
243 * @brief Enable AES start in MCU mode.
244 *
245 * \rst
246 * +----------------------+-----------------------------+
247 * | Register | BitsName |
248 * +======================+=============================+
249 * | CTRL | START_NORMAL |
250 * +----------------------+-----------------------------+
251 * \endrst
252 *
253 * @param AESx AES instance
254 * @retval None
255 */
256 __STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
257 {
258 SET_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
259 }
260
261 /**
262 * @brief Disable AES start in MCU mode.
263 *
264 * \rst
265 * +----------------------+-----------------------------+
266 * | Register | BitsName |
267 * +======================+=============================+
268 * | CTRL | START_NORMAL |
269 * +----------------------+-----------------------------+
270 * \endrst
271 *
272 * @param AESx AES instance
273 * @retval None
274 */
275 __STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
276 {
277 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
278 }
279
280 /**
281 * @brief Indicate whether the AES start in MCU mode is enabled.
282 *
283 * \rst
284 * +----------------------+-----------------------------+
285 * | Register | BitsName |
286 * +======================+=============================+
287 * | CTRL | START_NORMAL |
288 * +----------------------+-----------------------------+
289 * \endrst
290 *
291 * @param AESx AES instance
292 * @retval State of bit (1 or 0).
293 */
294 __STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
295 {
296 return (READ_BITS(AESx->CTRL, AES_CTRL_START_NORMAL) == (AES_CTRL_START_NORMAL));
297 }
298
299 /**
300 * @brief Enable AES DMA mode.
301 *
302 * \rst
303 * +----------------------+-----------------------------+
304 * | Register | BitsName |
305 * +======================+=============================+
306 * | CTRL | START_DMA |
307 * +----------------------+-----------------------------+
308 * \endrst
309 *
310 * @param AESx AES instance
311 * @retval None
312 */
313 __STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
314 {
315 SET_BITS(AESx->CTRL, AES_CTRL_START_DMA);
316 }
317
318 /**
319 * @brief Disable AES DMA mode.
320 *
321 * \rst
322 * +----------------------+-----------------------------+
323 * | Register | BitsName |
324 * +======================+=============================+
325 * | CTRL | START_DMA |
326 * +----------------------+-----------------------------+
327 * \endrst
328 *
329 * @param AESx AES instance
330 * @retval None
331 */
332 __STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
333 {
334 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_DMA);
335 }
336
337 /**
338 * @brief Indicate whether the AES DMA mode is enabled.
339 *
340 * \rst
341 * +----------------------+-----------------------------+
342 * | Register | BitsName |
343 * +======================+=============================+
344 * | CTRL | START_DMA |
345 * +----------------------+-----------------------------+
346 * \endrst
347 *
348 * @param AESx AES instance
349 * @retval State of bit (1 or 0).
350 */
351 __STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
352 {
353 return (READ_BITS(AESx->CTRL, AES_CTRL_START_DMA) == (AES_CTRL_START_DMA));
354 }
355
356 /**
357 * @brief Enable fetch key through AHB/key port.
358 *
359 * \rst
360 * +----------------------+-----------------------------+
361 * | Register | BitsName |
362 * +======================+=============================+
363 * | CTRL | ENABLE_RKEY |
364 * +----------------------+-----------------------------+
365 * \endrst
366 *
367 * @param AESx AES instance
368 * @retval None
369 */
370 __STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
371 {
372 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE_RKEY);
373 }
374
375 /**
376 * @brief Set AES key size.
377 *
378 * \rst
379 * +----------------------+-----------------------------+
380 * | Register | BitsName |
381 * +======================+=============================+
382 * | CONFIG | KEYMODE |
383 * +----------------------+-----------------------------+
384 * \endrst
385 *
386 * @param AESx AES instance
387 * @param size This parameter can be one of the following values:
388 * @arg @ref LL_AES_KEY_SIZE_128
389 * @arg @ref LL_AES_KEY_SIZE_192
390 * @arg @ref LL_AES_KEY_SIZE_256
391 * @retval None
392 */
393 __STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
394 {
395 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYMODE, size);
396 }
397
398 /**
399 * @brief Get AES key size.
400 *
401 * \rst
402 * +----------------------+-----------------------------+
403 * | Register | BitsName |
404 * +======================+=============================+
405 * | CONFIG | KEYMODE |
406 * +----------------------+-----------------------------+
407 * \endrst
408 *
409 * @param AESx AES instance
410 * @retval Returned value can be one of the following values:
411 * @arg @ref LL_AES_KEY_SIZE_128
412 * @arg @ref LL_AES_KEY_SIZE_192
413 * @arg @ref LL_AES_KEY_SIZE_256
414 */
415 __STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
416 {
417 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYMODE));
418 }
419
420 /**
421 * @brief Enable AES full mask.
422 *
423 * \rst
424 * +----------------------+-----------------------------+
425 * | Register | BitsName |
426 * +======================+=============================+
427 * | CONFIG | ENABLE_FULLMASK |
428 * +----------------------+-----------------------------+
429 * \endrst
430 *
431 * @param AESx AES instance
432 * @retval None
433 */
434 __STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
435 {
436 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
437 }
438
439 /**
440 * @brief Disable AES full mask.
441 *
442 * \rst
443 * +----------------------+-----------------------------+
444 * | Register | BitsName |
445 * +======================+=============================+
446 * | CONFIG | ENABLE_FULLMASK |
447 * +----------------------+-----------------------------+
448 * \endrst
449 *
450 * @param AESx AES instance
451 * @retval None
452 */
453 __STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
454 {
455 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
456 }
457
458 /**
459 * @brief Indicate whether the AES full mask is enabled.
460 *
461 * \rst
462 * +----------------------+-----------------------------+
463 * | Register | BitsName |
464 * +======================+=============================+
465 * | CONFIG | ENABLE_FULLMASK |
466 * +----------------------+-----------------------------+
467 * \endrst
468 *
469 * @param AESx AES instance
470 * @retval State of bit (1 or 0).
471 */
472 __STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
473 {
474 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK) == (AES_CONFIG_ENABLE_FULLMASK));
475 }
476
477 /**
478 * @brief Enable AES encryption mode.
479 *
480 * \rst
481 * +----------------------+-----------------------------+
482 * | Register | BitsName |
483 * +======================+=============================+
484 * | CONFIG | ENABLE_ENCRYPTION |
485 * +----------------------+-----------------------------+
486 * \endrst
487 *
488 * @param AESx AES instance
489 * @retval None
490 */
491 __STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
492 {
493 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
494 }
495
496 /**
497 * @brief Disable AES encryption mode.
498 *
499 * \rst
500 * +----------------------+-----------------------------+
501 * | Register | BitsName |
502 * +======================+=============================+
503 * | CONFIG | ENABLE_ENCRYPTION |
504 * +----------------------+-----------------------------+
505 * \endrst
506 *
507 * @param AESx AES instance
508 * @retval None
509 */
510 __STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
511 {
512 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
513 }
514
515 /**
516 * @brief Indicate whether the AES encryption mode is enabled.
517 *
518 * \rst
519 * +----------------------+-----------------------------+
520 * | Register | BitsName |
521 * +======================+=============================+
522 * | CONFIG | ENABLE_ENCRYPTION |
523 * +----------------------+-----------------------------+
524 * \endrst
525 *
526 * @param AESx AES instance
527 * @retval State of bit (1 or 0).
528 */
529 __STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
530 {
531 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION) == (AES_CONFIG_ENABLE_ENCRYPTION));
532 }
533
534 /**
535 * @brief Set AES to load seed for LFSR.
536 *
537 * \rst
538 * +----------------------+-----------------------------+
539 * | Register | BitsName |
540 * +======================+=============================+
541 * | CONFIG | LOADSEED |
542 * +----------------------+-----------------------------+
543 * \endrst
544 *
545 * @param AESx AES instance
546 * @retval None
547 */
548 __STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
549 {
550 SET_BITS(AESx->CONFIG, AES_CONFIG_LOADSEED);
551 }
552
553 /**
554 * @brief Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
555 *
556 * \rst
557 * +----------------------+-----------------------------+
558 * | Register | BitsName |
559 * +======================+=============================+
560 * | CONFIG | FIRSTBLOCK |
561 * +----------------------+-----------------------------+
562 * \endrst
563 *
564 * @param AESx AES instance
565 * @retval None
566 */
567 __STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
568 {
569 SET_BITS(AESx->CONFIG, AES_CONFIG_FIRSTBLOCK);
570 }
571
572 /**
573 * @brief Enable AES in little endian.
574 *
575 * \rst
576 * +----------------------+-----------------------------+
577 * | Register | BitsName |
578 * +======================+=============================+
579 * | CONFIG | ENDIAN |
580 * +----------------------+-----------------------------+
581 * \endrst
582 *
583 * @param AESx AES instance
584 * @retval None
585 */
586 __STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
587 {
588 SET_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
589 }
590
591 /**
592 * @brief Disable AES in little endian.
593 *
594 * \rst
595 * +----------------------+-----------------------------+
596 * | Register | BitsName |
597 * +======================+=============================+
598 * | CONFIG | ENDIAN |
599 * +----------------------+-----------------------------+
600 * \endrst
601 *
602 * @param AESx AES instance
603 * @retval None
604 */
605 __STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
606 {
607 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
608 }
609
610 /**
611 * @brief Indicate whether the AES is in little endian.
612 *
613 * \rst
614 * +----------------------+-----------------------------+
615 * | Register | BitsName |
616 * +======================+=============================+
617 * | CONFIG | ENDIAN |
618 * +----------------------+-----------------------------+
619 * \endrst
620 *
621 * @param AESx AES instance
622 * @retval State of bit (1 or 0).
623 */
624 __STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
625 {
626 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN) == (AES_CONFIG_ENDIAN));
627 }
628
629 /**
630 * @brief Set AES operation mode.
631 *
632 * \rst
633 * +----------------------+-----------------------------+
634 * | Register | BitsName |
635 * +======================+=============================+
636 * | CONFIG | OPMODE |
637 * +----------------------+-----------------------------+
638 * \endrst
639 *
640 * @param AESx AES instance
641 * @param mode This parameter can be one of the following values:
642 * @arg @ref LL_AES_OPERATION_MODE_ECB
643 * @arg @ref LL_AES_OPERATION_MODE_CBC
644 * @retval None
645 */
646 __STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
647 {
648 MODIFY_REG(AESx->CONFIG, AES_CONFIG_OPMODE, mode);
649 }
650
651 /**
652 * @brief Get AES operation mode.
653 *
654 * \rst
655 * +----------------------+-----------------------------+
656 * | Register | BitsName |
657 * +======================+=============================+
658 * | CONFIG | OPMODE |
659 * +----------------------+-----------------------------+
660 * \endrst
661 *
662 * @param AESx AES instance
663 * @retval Returned value can be one of the following values:
664 * @arg @ref LL_AES_OPERATION_MODE_ECB
665 * @arg @ref LL_AES_OPERATION_MODE_CBC
666 */
667 __STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
668 {
669 return (READ_BITS(AESx->CONFIG, AES_CONFIG_OPMODE));
670 }
671
672 /**
673 * @brief Set ways to obtain AES key.
674 *
675 * \rst
676 * +----------------------+-----------------------------+
677 * | Register | BitsName |
678 * +======================+=============================+
679 * | CONFIG | KEYTYPE |
680 * +----------------------+-----------------------------+
681 * \endrst
682 *
683 * @param AESx AES instance
684 * @param Type This parameter can be one of the following values:
685 * @arg @ref LL_AES_KEYTYPE_MCU
686 * @arg @ref LL_AES_KEYTYPE_AHB
687 * @arg @ref LL_AES_KEYTYPE_KRAM
688 * @retval None
689 */
690 __STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
691 {
692 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYTYPE, Type);
693 }
694
695 /**
696 * @brief Get ways to obtain AES key.
697 *
698 * \rst
699 * +----------------------+-----------------------------+
700 * | Register | BitsName |
701 * +======================+=============================+
702 * | CONFIG | KEYTYPE |
703 * +----------------------+-----------------------------+
704 * \endrst
705 *
706 * @param AESx AES instance
707 * @retval Returned value can be one of the following values:
708 * @arg @ref LL_AES_KEYTYPE_MCU
709 * @arg @ref LL_AES_KEYTYPE_AHB
710 * @arg @ref LL_AES_KEYTYPE_KRAM
711 */
712 __STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
713 {
714 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYTYPE));
715 }
716
717 /** @} */
718
719 /** @defgroup AES_LL_EF_IT_Management IT_Management
720 * @{
721 */
722
723 /**
724 * @brief Enable AES the done interrupt.
725 *
726 * \rst
727 * +----------------------+-----------------------------+
728 * | Register | BitsName |
729 * +======================+=============================+
730 * | INTERRUPT | ENABLE |
731 * +----------------------+-----------------------------+
732 * \endrst
733 *
734 * @param AESx AES instance
735 * @retval None
736 */
737 __STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
738 {
739 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
740 }
741
742 /**
743 * @brief Disable AES the done interrupt.
744 *
745 * \rst
746 * +----------------------+-----------------------------+
747 * | Register | BitsName |
748 * +======================+=============================+
749 * | INTERRUPT | ENABLE |
750 * +----------------------+-----------------------------+
751 * \endrst
752 *
753 * @param AESx AES instance
754 * @retval None
755 */
756 __STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
757 {
758 CLEAR_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
759 }
760
761 /**
762 * @brief Indicate whether the done interrupt is enabled.
763 *
764 * \rst
765 * +----------------------+-----------------------------+
766 * | Register | BitsName |
767 * +======================+=============================+
768 * | INTERRUPT | ENABLE |
769 * +----------------------+-----------------------------+
770 * \endrst
771 *
772 * @param AESx AES instance
773 * @retval State of bit (1 or 0).
774 */
775 __STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
776 {
777 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE) == (AES_INTERRUPT_ENABLE));
778 }
779
780 /** @} */
781
782 /** @defgroup AES_LL_EF_FLAG_Management FLAG_Management
783 * @{
784 */
785
786 /**
787 * @brief Indicate whether the ready flag is set.
788 *
789 * \rst
790 * +----------------------+-----------------------------+
791 * | Register | BitsName |
792 * +======================+=============================+
793 * | STATUS | READY |
794 * +----------------------+-----------------------------+
795 * \endrst
796 *
797 * @param AESx AES instance
798 * @retval State of bit (1 or 0).
799 */
800 __STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
801 {
802 return (READ_BITS(AESx->STATUS, AES_STATUS_READY) == AES_STATUS_READY);
803 }
804
805 /**
806 * @brief Indicate whether the DMA transfer done flag is set.
807 *
808 * \rst
809 * +----------------------+-----------------------------+
810 * | Register | BitsName |
811 * +======================+=============================+
812 * | STATUS | TRANSDONE |
813 * +----------------------+-----------------------------+
814 * \endrst
815 *
816 * @param AESx AES instance
817 * @retval State of bit (1 or 0).
818 */
819 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
820 {
821 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSDONE) == AES_STATUS_TRANSDONE);
822 }
823
824 /**
825 * @brief Indicate whether the DMA transfer error flag is set.
826 *
827 * \rst
828 * +----------------------+-----------------------------+
829 * | Register | BitsName |
830 * +======================+=============================+
831 * | STATUS | TRANSERR |
832 * +----------------------+-----------------------------+
833 * \endrst
834 *
835 * @param AESx AES instance
836 * @retval State of bit (1 or 0).
837 */
838 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
839 {
840 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSERR) == AES_STATUS_TRANSERR);
841 }
842
843 /**
844 * @brief Indicate whether the key valid flag is set.
845 *
846 * \rst
847 * +----------------------+-----------------------------+
848 * | Register | BitsName |
849 * +======================+=============================+
850 * | STATUS | KEYVALID |
851 * +----------------------+-----------------------------+
852 * \endrst
853 *
854 * @param AESx AES instance
855 * @retval State of bit (1 or 0).
856 */
857 __STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
858 {
859 return (READ_BITS(AESx->STATUS, AES_STATUS_KEYVALID) == AES_STATUS_KEYVALID);
860 }
861
862 /**
863 * @brief Indicate whether the done interrupt flag is set.
864 *
865 * \rst
866 * +----------------------+-----------------------------+
867 * | Register | BitsName |
868 * +======================+=============================+
869 * | INTERRUPT | DONE |
870 * +----------------------+-----------------------------+
871 * \endrst
872 *
873 * @param AESx AES instance
874 * @retval State of bit (1 or 0).
875 */
876 __STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
877 {
878 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE) == AES_INTERRUPT_DONE);
879 }
880
881 /**
882 * @brief Clear the done interrupt flag.
883 *
884 * \rst
885 * +----------------------+-----------------------------+
886 * | Register | BitsName |
887 * +======================+=============================+
888 * | INTERRUPT | DONE |
889 * +----------------------+-----------------------------+
890 * \endrst
891 *
892 * @param AESx AES instance
893 * @retval None
894 */
895 __STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
896 {
897 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE);
898 }
899
900 /** @} */
901
902 /** @defgroup AES_LL_EF_DMA_Management DMA_Management
903 * @{
904 */
905
906 /**
907 * @brief Set AES transfer blocks in DMA mode.
908 *
909 * \rst
910 * +----------------------+-----------------------------+
911 * | Register | BitsName |
912 * +======================+=============================+
913 * | TRAN_SIZE | TRAN_SIZE |
914 * +----------------------+-----------------------------+
915 * \endrst
916 *
917 * @param AESx AES instance
918 * @param block This parameter can be one of the following values: 1 ~ 2048.
919 * @retval None
920 */
921 __STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
922 {
923 MODIFY_REG(AESx->TRAN_SIZE, AES_TRAN_SIZE, (block << 4) - 1);
924 }
925
926 /**
927 * @brief Get AES transfer blocks in DMA mode.
928 *
929 * \rst
930 * +----------------------+-----------------------------+
931 * | Register | BitsName |
932 * +======================+=============================+
933 * | TRAN_SIZE | TRAN_SIZE |
934 * +----------------------+-----------------------------+
935 * \endrst
936 *
937 * @param AESx AES instance
938 * @retval Return value between 1 and 2048.
939 */
940 __STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
941 {
942 return ((READ_BITS(AESx->TRAN_SIZE, AES_TRAN_SIZE) + 1) >> 4);
943 }
944
945 /**
946 * @brief Set AES read address of RAM in DMA mode.
947 * @note This read address of RAM requires 4 byte alignment.
948 *
949 * \rst
950 * +----------------------+-----------------------------+
951 * | Register | BitsName |
952 * +======================+=============================+
953 * | RSTART_ADDR | RSTART_ADDR |
954 * +----------------------+-----------------------------+
955 * \endrst
956 *
957 * @param AESx AES instance
958 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
959 * @retval None
960 */
961 __STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
962 {
963 WRITE_REG(AESx->RSTART_ADDR, address);
964 }
965
966 /**
967 * @brief Get AES read address of RAM in DMA mode.
968 *
969 * \rst
970 * +----------------------+-----------------------------+
971 * | Register | BitsName |
972 * +======================+=============================+
973 * | RSTART_ADDR | RSTART_ADDR |
974 * +----------------------+-----------------------------+
975 * \endrst
976 *
977 * @param AESx AES instance
978 * @retval Returned value is the read address in RAM.
979 */
980 __STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
981 {
982 return (READ_REG(AESx->RSTART_ADDR));
983 }
984
985 /**
986 * @brief Set AES write address of RAM in DMA mode.
987 * @note This write address of RAM requires 4 byte alignment.
988 *
989 * \rst
990 * +----------------------+-----------------------------+
991 * | Register | BitsName |
992 * +======================+=============================+
993 * | WSTART_ADDR | WSTART_ADDR |
994 * +----------------------+-----------------------------+
995 * \endrst
996 *
997 * @param AESx AES instance
998 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
999 * @retval None
1000 */
1001 __STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
1002 {
1003 WRITE_REG(AESx->WSTART_ADDR, address);
1004 }
1005
1006 /**
1007 * @brief Get AES write address of RAM in DMA mode.
1008 *
1009 * \rst
1010 * +----------------------+-----------------------------+
1011 * | Register | BitsName |
1012 * +======================+=============================+
1013 * | WSTART_ADDR | WSTART_ADDR |
1014 * +----------------------+-----------------------------+
1015 * \endrst
1016 *
1017 * @param AESx AES instance
1018 * @retval Returned value is the wrute address in RAM
1019 */
1020 __STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
1021 {
1022 return (READ_REG(AESx->WSTART_ADDR));
1023 }
1024
1025 /** @} */
1026
1027 /** @defgroup AES_LL_EF_Data_Management Data_Management
1028 * @{
1029 */
1030
1031 /**
1032 * @brief Set AES key address in memory.
1033 *
1034 * \rst
1035 * +----------------------+-----------------------------+
1036 * | Register | BitsName |
1037 * +======================+=============================+
1038 * | KEY_ADDR | KEY_ADDR |
1039 * +----------------------+-----------------------------+
1040 * \endrst
1041 *
1042 * @param AESx AES instance
1043 * @param address This parameter can be one of the address in RAM
1044 * @retval None
1045 */
1046 __STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
1047 {
1048 WRITE_REG(AESx->KEY_ADDR, address);
1049 }
1050
1051 /**
1052 * @brief Get AES key address in memory.
1053 *
1054 * \rst
1055 * +----------------------+-----------------------------+
1056 * | Register | BitsName |
1057 * +======================+=============================+
1058 * | KEY_ADDR | KEY_ADDR |
1059 * +----------------------+-----------------------------+
1060 * \endrst
1061 *
1062 * @param AESx AES instance
1063 * @retval Returned value is the key address in RAM.
1064 */
1065 __STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
1066 {
1067 return (READ_REG(AESx->KEY_ADDR));
1068 }
1069
1070 /**
1071 * @brief Get AES output data[127:96].
1072 *
1073 * \rst
1074 * +----------------------+-----------------------------+
1075 * | Register | BitsName |
1076 * +======================+=============================+
1077 * | DATA_OUT[0] | DATA_OUT |
1078 * +----------------------+-----------------------------+
1079 * \endrst
1080 *
1081 * @param AESx AES instance
1082 * @retval Output Data[127:96]
1083 */
1084 __STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
1085 {
1086 return (READ_REG(AESx->DATA_OUT[0]));
1087 }
1088
1089 /**
1090 * @brief Get AES output data[95:64].
1091 *
1092 * \rst
1093 * +----------------------+-----------------------------+
1094 * | Register | BitsName |
1095 * +======================+=============================+
1096 * | DATA_OUT[1] | DATA_OUT |
1097 * +----------------------+-----------------------------+
1098 * \endrst
1099 *
1100 * @param AESx AES instance
1101 * @retval Output Data[95:64]
1102 */
1103 __STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
1104 {
1105 return (READ_REG(AESx->DATA_OUT[1]));
1106 }
1107
1108 /**
1109 * @brief Get AES output data[63:32].
1110 *
1111 * \rst
1112 * +----------------------+-----------------------------+
1113 * | Register | BitsName |
1114 * +======================+=============================+
1115 * | DATA_OUT[2] | DATA_OUT |
1116 * +----------------------+-----------------------------+
1117 * \endrst
1118 *
1119 * @param AESx AES instance
1120 * @retval Output Data[63:32]
1121 */
1122 __STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
1123 {
1124 return (READ_REG(AESx->DATA_OUT[2]));
1125 }
1126
1127 /**
1128 * @brief Get AES output data[31:0].
1129 *
1130 * \rst
1131 * +----------------------+-----------------------------+
1132 * | Register | BitsName |
1133 * +======================+=============================+
1134 * | DATA_OUT[3] | DATA_OUT |
1135 * +----------------------+-----------------------------+
1136 * \endrst
1137 *
1138 * @param AESx AES instance
1139 * @retval Output Data[31:0]
1140 */
1141 __STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
1142 {
1143 return (READ_REG(AESx->DATA_OUT[3]));
1144 }
1145
1146 /**
1147 * @brief Set AES key[255:224].
1148 *
1149 * \rst
1150 * +----------------------+-----------------------------+
1151 * | Register | BitsName |
1152 * +======================+=============================+
1153 * | KEY[0] | KEY |
1154 * +----------------------+-----------------------------+
1155 * \endrst
1156 *
1157 * @param AESx AES instance
1158 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1159 * @retval None
1160 */
1161 __STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
1162 {
1163 WRITE_REG(AESx->KEY[0], key);
1164 }
1165
1166 /**
1167 * @brief Set AES key[223:192].
1168 *
1169 * \rst
1170 * +----------------------+-----------------------------+
1171 * | Register | BitsName |
1172 * +======================+=============================+
1173 * | KEY[1] | KEY |
1174 * +----------------------+-----------------------------+
1175 * \endrst
1176 *
1177 * @param AESx AES instance
1178 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1179 * @retval None
1180 */
1181 __STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
1182 {
1183 WRITE_REG(AESx->KEY[1], key);
1184 }
1185
1186 /**
1187 * @brief Set AES key[191:160].
1188 *
1189 * \rst
1190 * +----------------------+-----------------------------+
1191 * | Register | BitsName |
1192 * +======================+=============================+
1193 * | KEY[2] | KEY |
1194 * +----------------------+-----------------------------+
1195 * \endrst
1196 *
1197 * @param AESx AES instance
1198 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1199 * @retval None
1200 */
1201 __STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
1202 {
1203 WRITE_REG(AESx->KEY[2], key);
1204 }
1205
1206 /**
1207 * @brief Set AES key[159:128].
1208 *
1209 * \rst
1210 * +----------------------+-----------------------------+
1211 * | Register | BitsName |
1212 * +======================+=============================+
1213 * | KEY[3] | KEY |
1214 * +----------------------+-----------------------------+
1215 * \endrst
1216 *
1217 * @param AESx AES instance
1218 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1219 * @retval None
1220 */
1221 __STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
1222 {
1223 WRITE_REG(AESx->KEY[3], key);
1224 }
1225
1226 /**
1227 * @brief Set AES key[127:96].
1228 *
1229 * \rst
1230 * +----------------------+-----------------------------+
1231 * | Register | BitsName |
1232 * +======================+=============================+
1233 * | KEY[4] | KEY |
1234 * +----------------------+-----------------------------+
1235 * \endrst
1236 *
1237 * @param AESx AES instance
1238 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1239 * @retval None
1240 */
1241 __STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
1242 {
1243 WRITE_REG(AESx->KEY[4], key);
1244 }
1245
1246 /**
1247 * @brief Set AES key[95:64].
1248 *
1249 * \rst
1250 * +----------------------+-----------------------------+
1251 * | Register | BitsName |
1252 * +======================+=============================+
1253 * | KEY[5] | KEY |
1254 * +----------------------+-----------------------------+
1255 * \endrst
1256 *
1257 * @param AESx AES instance
1258 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1259 * @retval None
1260 */
1261 __STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
1262 {
1263 WRITE_REG(AESx->KEY[5], key);
1264 }
1265
1266 /**
1267 * @brief Set AES key[63:32].
1268 *
1269 * \rst
1270 * +----------------------+-----------------------------+
1271 * | Register | BitsName |
1272 * +======================+=============================+
1273 * | KEY[6] | KEY |
1274 * +----------------------+-----------------------------+
1275 * \endrst
1276 *
1277 * @param AESx AES instance
1278 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1279 * @retval None
1280 */
1281 __STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
1282 {
1283 WRITE_REG(AESx->KEY[6], key);
1284 }
1285
1286 /**
1287 * @brief Set AES key[31:0].
1288 *
1289 * \rst
1290 * +----------------------+-----------------------------+
1291 * | Register | BitsName |
1292 * +======================+=============================+
1293 * | KEY[7] | KEY |
1294 * +----------------------+-----------------------------+
1295 * \endrst
1296 *
1297 * @param AESx AES instance
1298 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1299 * @retval None
1300 */
1301 __STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
1302 {
1303 WRITE_REG(AESx->KEY[7], key);
1304 }
1305
1306 /**
1307 * @brief Set AES input seed.
1308 *
1309 * \rst
1310 * +----------------------+-----------------------------+
1311 * | Register | BitsName |
1312 * +======================+=============================+
1313 * | SEED_IN | SEED_IN |
1314 * +----------------------+-----------------------------+
1315 * \endrst
1316 *
1317 * @param AESx AES instance
1318 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1319 * @retval None
1320 */
1321 __STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
1322 {
1323 WRITE_REG(AESx->SEED_IN, seed);
1324 }
1325
1326 /**
1327 * @brief Get AES input seed.
1328 *
1329 * \rst
1330 * +----------------------+-----------------------------+
1331 * | Register | BitsName |
1332 * +======================+=============================+
1333 * | SEED_IN | SEED_IN |
1334 * +----------------------+-----------------------------+
1335 * \endrst
1336 *
1337 * @param AESx AES instance
1338 * @retval Returned value is the input seed.
1339 */
1340 __STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
1341 {
1342 return (READ_REG(AESx->SEED_IN));
1343 }
1344
1345 /**
1346 * @brief Set AES output seed.
1347 *
1348 * \rst
1349 * +----------------------+-----------------------------+
1350 * | Register | BitsName |
1351 * +======================+=============================+
1352 * | SEED_OUT | SEED_OUT |
1353 * +----------------------+-----------------------------+
1354 * \endrst
1355 *
1356 * @param AESx AES instance
1357 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1358 * @retval None
1359 */
1360 __STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
1361 {
1362 WRITE_REG(AESx->SEED_OUT, seed);
1363 }
1364
1365 /**
1366 * @brief Get AES output seed.
1367 *
1368 * \rst
1369 * +----------------------+-----------------------------+
1370 * | Register | BitsName |
1371 * +======================+=============================+
1372 * | SEED_OUT | SEED_OUT |
1373 * +----------------------+-----------------------------+
1374 * \endrst
1375 *
1376 * @param AESx AES instance
1377 * @retval Returned value is the output seed.
1378 */
1379 __STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
1380 {
1381 return (READ_REG(AESx->SEED_OUT));
1382 }
1383
1384 /**
1385 * @brief Set sbox input data's mask.
1386 *
1387 * \rst
1388 * +----------------------+-----------------------------+
1389 * | Register | BitsName |
1390 * +======================+=============================+
1391 * | SEED_IMASK | SEED_IMASK |
1392 * +----------------------+-----------------------------+
1393 * \endrst
1394 *
1395 * @param AESx AES instance
1396 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1397 * @retval None
1398 */
1399 __STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
1400 {
1401 WRITE_REG(AESx->SEED_IMASK, mask);
1402 }
1403
1404 /**
1405 * @brief Get sbox input data's mask.
1406 *
1407 * \rst
1408 * +----------------------+-----------------------------+
1409 * | Register | BitsName |
1410 * +======================+=============================+
1411 * | SEED_IMASK | SEED_IMASK |
1412 * +----------------------+-----------------------------+
1413 * \endrst
1414 *
1415 * @param AESx AES instance
1416 * @retval Returned value is the input data's mask.
1417 */
1418 __STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
1419 {
1420 return (READ_REG(AESx->SEED_IMASK));
1421 }
1422
1423 /**
1424 * @brief Set sbox output data's mask.
1425 *
1426 * \rst
1427 * +----------------------+-----------------------------+
1428 * | Register | BitsName |
1429 * +======================+=============================+
1430 * | SEED_OSBOX | SEED_OSBOX |
1431 * +----------------------+-----------------------------+
1432 * \endrst
1433 *
1434 * @param AESx AES instance
1435 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1436 * @retval None
1437 */
1438 __STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
1439 {
1440 WRITE_REG(AESx->SEED_OSBOX, mask);
1441 }
1442
1443 /**
1444 * @brief Get sbox output data's mask.
1445 *
1446 * \rst
1447 * +----------------------+-----------------------------+
1448 * | Register | BitsName |
1449 * +======================+=============================+
1450 * | SEED_OSBOX | SEED_OSBOX |
1451 * +----------------------+-----------------------------+
1452 * \endrst
1453 *
1454 * @param AESx AES instance
1455 * @retval Returned value is the output data's mask.
1456 */
1457 __STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
1458 {
1459 return (READ_REG(AESx->SEED_OSBOX));
1460 }
1461
1462 /**
1463 * @brief Set AES initialization vector[127:96].
1464 *
1465 * \rst
1466 * +----------------------+-----------------------------+
1467 * | Register | BitsName |
1468 * +======================+=============================+
1469 * | VECTOR_INIT[0] | VECTOR_INIT |
1470 * +----------------------+-----------------------------+
1471 * \endrst
1472 *
1473 * @param AESx AES instance
1474 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1475 * @retval None
1476 */
1477 __STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
1478 {
1479 WRITE_REG(AESx->VECTOR_INIT[0], vector);
1480 }
1481
1482 /**
1483 * @brief Set AES initialization vector[95:64].
1484 *
1485 * \rst
1486 * +----------------------+-----------------------------+
1487 * | Register | BitsName |
1488 * +======================+=============================+
1489 * | VECTOR_INIT[1] | VECTOR_INIT |
1490 * +----------------------+-----------------------------+
1491 * \endrst
1492 *
1493 * @param AESx AES instance
1494 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1495 * @retval None
1496 */
1497 __STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
1498 {
1499 WRITE_REG(AESx->VECTOR_INIT[1], vector);
1500 }
1501
1502 /**
1503 * @brief Set AES initialization vector[63:32].
1504 *
1505 * \rst
1506 * +----------------------+-----------------------------+
1507 * | Register | BitsName |
1508 * +======================+=============================+
1509 * | VECTOR_INIT[2] | VECTOR_INIT |
1510 * +----------------------+-----------------------------+
1511 * \endrst
1512 *
1513 * @param AESx AES instance
1514 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1515 * @retval None
1516 */
1517 __STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
1518 {
1519 WRITE_REG(AESx->VECTOR_INIT[2], vector);
1520 }
1521
1522 /**
1523 * @brief Set AES initialization vector[31:0].
1524 *
1525 * \rst
1526 * +----------------------+-----------------------------+
1527 * | Register | BitsName |
1528 * +======================+=============================+
1529 * | VECTOR_INIT[3] | VECTOR_INIT |
1530 * +----------------------+-----------------------------+
1531 * \endrst
1532 *
1533 * @param AESx AES instance
1534 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1535 * @retval None
1536 */
1537 __STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
1538 {
1539 WRITE_REG(AESx->VECTOR_INIT[3], vector);
1540 }
1541
1542 /**
1543 * @brief Set AES input data[127:96].
1544 *
1545 * \rst
1546 * +----------------------+-----------------------------+
1547 * | Register | BitsName |
1548 * +======================+=============================+
1549 * | DATA_IN[0] | DATA_IN |
1550 * +----------------------+-----------------------------+
1551 * \endrst
1552 *
1553 * @param AESx AES instance
1554 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1555 * @retval None
1556 */
1557 __STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
1558 {
1559 WRITE_REG(AESx->DATA_IN[0], data);
1560 }
1561
1562 /**
1563 * @brief Set AES input data[95:64].
1564 *
1565 * \rst
1566 * +----------------------+-----------------------------+
1567 * | Register | BitsName |
1568 * +======================+=============================+
1569 * | DATA_IN[1] | DATA_IN |
1570 * +----------------------+-----------------------------+
1571 * \endrst
1572 *
1573 * @param AESx AES instance
1574 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1575 * @retval None
1576 */
1577 __STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
1578 {
1579 WRITE_REG(AESx->DATA_IN[1], data);
1580 }
1581
1582 /**
1583 * @brief Set AES input data[63:32].
1584 *
1585 * \rst
1586 * +----------------------+-----------------------------+
1587 * | Register | BitsName |
1588 * +======================+=============================+
1589 * | DATA_IN[2] | DATA_IN |
1590 * +----------------------+-----------------------------+
1591 * \endrst
1592 *
1593 * @param AESx AES instance
1594 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1595 * @retval None
1596 */
1597 __STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
1598 {
1599 WRITE_REG(AESx->DATA_IN[2], data);
1600 }
1601
1602 /**
1603 * @brief Set AES input data[31:0].
1604 *
1605 * \rst
1606 * +----------------------+-----------------------------+
1607 * | Register | BitsName |
1608 * +======================+=============================+
1609 * | DATA_IN[3] | DATA_IN |
1610 * +----------------------+-----------------------------+
1611 * \endrst
1612 *
1613 * @param AESx AES instance
1614 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1615 * @retval None
1616 */
1617 __STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
1618 {
1619 WRITE_REG(AESx->DATA_IN[3], data);
1620 }
1621
1622 /**
1623 * @brief Set AES fetch key port mask.
1624 *
1625 * \rst
1626 * +----------------------+-----------------------------+
1627 * | Register | BitsName |
1628 * +======================+=============================+
1629 * | KPORT_MASK | KPORT_MASK |
1630 * +----------------------+-----------------------------+
1631 * \endrst
1632 *
1633 * @param AESx AES instance
1634 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1635 * @retval None
1636 */
1637 __STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
1638 {
1639 WRITE_REG(AESx->KPORT_MASK, mask);
1640 }
1641
1642 /** @} */
1643
1644 /** @defgroup AES_LL_EF_Init Initialization and de-initialization functions
1645 * @{
1646 */
1647
1648 /**
1649 * @brief De-initialize AES registers (Registers restored to their default values).
1650 * @param AESx AES Instance
1651 * @retval An error_status_t enumeration value:
1652 * - SUCCESS: AES registers are de-initialized
1653 * - ERROR: AES registers are not de-initialized
1654 */
1655 error_status_t ll_aes_deinit(aes_regs_t *AESx);
1656
1657 /**
1658 * @brief Initialize AES registers according to the specified
1659 * parameters in p_aes_init.
1660 * @param AESx AES Instance
1661 * @param p_aes_init Pointer to a ll_aes_init_t structure that contains the configuration
1662 * information for the specified AES peripheral.
1663 * @retval An error_status_t enumeration value:
1664 * - SUCCESS: AES registers are initialized according to p_aes_init content
1665 * - ERROR: Problem occurred during AES Registers initialization
1666 */
1667 error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init);
1668
1669 /**
1670 * @brief Set each field of a @ref ll_aes_init_t type structure to default value.
1671 * @param p_aes_init Pointer to a @ref ll_aes_init_t structure
1672 * whose fields will be set to default values.
1673 * @retval None
1674 */
1675 void ll_aes_struct_init(ll_aes_init_t *p_aes_init);
1676
1677 /** @} */
1678
1679 /** @} */
1680
1681 #endif /* AES */
1682
1683 #ifdef __cplusplus
1684 }
1685 #endif
1686
1687 #endif /* __GR55XX_LL_AES_H__ */
1688
1689 /** @} */
1690
1691 /** @} */
1692
1693 /** @} */
ll_aes_enable_read_key
__STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
Enable fetch key through AHB/key port.
Definition: gr55xx_ll_aes.h:370
ll_aes_enable_encryption
__STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
Enable AES encryption mode.
Definition: gr55xx_ll_aes.h:491
ll_aes_disable_encryption
__STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
Disable AES encryption mode.
Definition: gr55xx_ll_aes.h:510
ll_aes_set_vector_127_96
__STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[127:96].
Definition: gr55xx_ll_aes.h:1477
_ll_aes_init::p_key
uint32_t * p_key
Definition: gr55xx_ll_aes.h:80
ll_aes_disable_start
__STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
Disable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:275
ll_aes_get_data_63_32
__STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
Get AES output data[63:32].
Definition: gr55xx_ll_aes.h:1122
ll_aes_get_data_127_96
__STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
Get AES output data[127:96].
Definition: gr55xx_ll_aes.h:1084
ll_aes_set_key_type
__STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
Set ways to obtain AES key.
Definition: gr55xx_ll_aes.h:690
ll_aes_disable
__STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
Disable AES.
Definition: gr55xx_ll_aes.h:218
ll_aes_set_data_63_32
__STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
Set AES input data[63:32].
Definition: gr55xx_ll_aes.h:1597
ll_aes_set_key_95_64
__STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
Set AES key[95:64].
Definition: gr55xx_ll_aes.h:1261
ll_aes_init_t
struct _ll_aes_init ll_aes_init_t
LL AES Init Structure definition.
ll_aes_get_data_95_64
__STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
Get AES output data[95:64].
Definition: gr55xx_ll_aes.h:1103
ll_aes_get_dma_write_address
__STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
Get AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:1020
ll_aes_is_action_flag_dma_error
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
Indicate whether the DMA transfer error flag is set.
Definition: gr55xx_ll_aes.h:838
ll_aes_set_operation_mode
__STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
Set AES operation mode.
Definition: gr55xx_ll_aes.h:646
ll_aes_set_key_31_0
__STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
Set AES key[31:0].
Definition: gr55xx_ll_aes.h:1301
ll_aes_is_enabled_it_done
__STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt is enabled.
Definition: gr55xx_ll_aes.h:775
ll_aes_set_vector_63_32
__STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[63:32].
Definition: gr55xx_ll_aes.h:1517
ll_aes_set_vector_31_0
__STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[31:0].
Definition: gr55xx_ll_aes.h:1537
ll_aes_is_action_flag_ready
__STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
Indicate whether the ready flag is set.
Definition: gr55xx_ll_aes.h:800
ll_aes_is_enabled_full_mask
__STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
Indicate whether the AES full mask is enabled.
Definition: gr55xx_ll_aes.h:472
ll_aes_set_seed_in
__STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
Set AES input seed.
Definition: gr55xx_ll_aes.h:1321
ll_aes_enable_full_mask
__STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
Enable AES full mask.
Definition: gr55xx_ll_aes.h:434
ll_aes_deinit
error_status_t ll_aes_deinit(aes_regs_t *AESx)
De-initialize AES registers (Registers restored to their default values).
_ll_aes_init
LL AES Init Structure definition.
Definition: gr55xx_ll_aes.h:76
ll_aes_disable_dma_start
__STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
Disable AES DMA mode.
Definition: gr55xx_ll_aes.h:332
ll_aes_is_enabled_little_endian
__STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
Indicate whether the AES is in little endian.
Definition: gr55xx_ll_aes.h:624
ll_aes_enable_start
__STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
Enable AES start in MCU mode.
Definition: gr55xx_ll_aes.h:256
_ll_aes_init::p_init_vector
uint32_t * p_init_vector
Definition: gr55xx_ll_aes.h:82
ll_aes_set_key_191_160
__STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
Set AES key[191:160].
Definition: gr55xx_ll_aes.h:1201
ll_aes_set_dma_write_address
__STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
Set AES write address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:1001
ll_aes_get_key_size
__STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
Get AES key size.
Definition: gr55xx_ll_aes.h:415
ll_aes_get_seed_Imask
__STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
Get sbox input data's mask.
Definition: gr55xx_ll_aes.h:1418
ll_aes_init
error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init)
Initialize AES registers according to the specified parameters in p_aes_init.
ll_aes_is_action_flag_dma_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
Indicate whether the DMA transfer done flag is set.
Definition: gr55xx_ll_aes.h:819
ll_aes_set_first_block
__STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
Definition: gr55xx_ll_aes.h:567
ll_aes_get_key_type
__STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
Get ways to obtain AES key.
Definition: gr55xx_ll_aes.h:712
ll_aes_set_data_95_64
__STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
Set AES input data[95:64].
Definition: gr55xx_ll_aes.h:1577
ll_aes_is_action_flag_it_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt flag is set.
Definition: gr55xx_ll_aes.h:876
ll_aes_set_data_127_96
__STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
Set AES input data[127:96].
Definition: gr55xx_ll_aes.h:1557
ll_aes_set_key_63_32
__STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
Set AES key[63:32].
Definition: gr55xx_ll_aes.h:1281
ll_aes_set_key_address
__STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
Set AES key address in memory.
Definition: gr55xx_ll_aes.h:1046
ll_aes_disable_little_endian
__STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
Disable AES in little endian.
Definition: gr55xx_ll_aes.h:605
ll_aes_is_enabled_encryption
__STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
Indicate whether the AES encryption mode is enabled.
Definition: gr55xx_ll_aes.h:529
ll_aes_set_vector_95_64
__STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[95:64].
Definition: gr55xx_ll_aes.h:1497
ll_aes_set_key_159_128
__STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
Set AES key[159:128].
Definition: gr55xx_ll_aes.h:1221
ll_aes_get_dma_read_address
__STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
Get AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:980
ll_aes_is_action_flag_key_valid
__STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
Indicate whether the key valid flag is set.
Definition: gr55xx_ll_aes.h:857
ll_aes_get_seed_out
__STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
Get AES output seed.
Definition: gr55xx_ll_aes.h:1379
ll_aes_get_seed_Osbox
__STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
Get sbox output data's mask.
Definition: gr55xx_ll_aes.h:1457
ll_aes_struct_init
void ll_aes_struct_init(ll_aes_init_t *p_aes_init)
Set each field of a ll_aes_init_t type structure to default value.
ll_aes_disable_it_done
__STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
Disable AES the done interrupt.
Definition: gr55xx_ll_aes.h:756
ll_aes_enable_little_endian
__STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
Enable AES in little endian.
Definition: gr55xx_ll_aes.h:586
ll_aes_set_dma_read_address
__STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
Set AES read address of RAM in DMA mode.
Definition: gr55xx_ll_aes.h:961
ll_aes_enable_it_done
__STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
Enable AES the done interrupt.
Definition: gr55xx_ll_aes.h:737
ll_aes_set_seed_out
__STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
Set AES output seed.
Definition: gr55xx_ll_aes.h:1360
_ll_aes_init::key_size
uint32_t key_size
Definition: gr55xx_ll_aes.h:77
ll_aes_set_data_31_0
__STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
Set AES input data[31:0].
Definition: gr55xx_ll_aes.h:1617
ll_aes_get_operation_mode
__STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
Get AES operation mode.
Definition: gr55xx_ll_aes.h:667
ll_aes_get_key_address
__STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
Get AES key address in memory.
Definition: gr55xx_ll_aes.h:1065
ll_aes_set_seed_Imask
__STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
Set sbox input data's mask.
Definition: gr55xx_ll_aes.h:1399
ll_aes_get_data_31_0
__STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
Get AES output data[31:0].
Definition: gr55xx_ll_aes.h:1141
ll_aes_disable_full_mask
__STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
Disable AES full mask.
Definition: gr55xx_ll_aes.h:453
ll_aes_set_key_255_224
__STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
Set AES key[255:224].
Definition: gr55xx_ll_aes.h:1161
ll_aes_is_enabled_dma_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
Indicate whether the AES DMA mode is enabled.
Definition: gr55xx_ll_aes.h:351
ll_aes_set_dma_transfer_block
__STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
Set AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:921
ll_aes_set_key_port_mask
__STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
Set AES fetch key port mask.
Definition: gr55xx_ll_aes.h:1637
ll_aes_get_seed_in
__STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
Get AES input seed.
Definition: gr55xx_ll_aes.h:1340
ll_aes_clear_flag_it_done
__STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
Clear the done interrupt flag.
Definition: gr55xx_ll_aes.h:895
ll_aes_enable_dma_start
__STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
Enable AES DMA mode.
Definition: gr55xx_ll_aes.h:313
ll_aes_set_seed_Osbox
__STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
Set sbox output data's mask.
Definition: gr55xx_ll_aes.h:1438
ll_aes_enable
__STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
Enable AES.
Definition: gr55xx_ll_aes.h:199
ll_aes_set_key_127_96
__STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
Set AES key[127:96].
Definition: gr55xx_ll_aes.h:1241
ll_aes_set_load_seed
__STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
Set AES to load seed for LFSR.
Definition: gr55xx_ll_aes.h:548
ll_aes_is_enabled_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
Indicate whether the AES start in MCU mode is enabled.
Definition: gr55xx_ll_aes.h:294
ll_aes_is_enabled
__STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
Indicate whether the AES is enabled.
Definition: gr55xx_ll_aes.h:237
ll_aes_set_key_223_192
__STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
Set AES key[223:192].
Definition: gr55xx_ll_aes.h:1181
ll_aes_set_key_size
__STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
Set AES key size.
Definition: gr55xx_ll_aes.h:393
_ll_aes_init::p_seed
uint32_t * p_seed
Definition: gr55xx_ll_aes.h:84
ll_aes_get_dma_transfer_block
__STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
Get AES transfer blocks in DMA mode.
Definition: gr55xx_ll_aes.h:940