51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
106 #define LL_AES_FLAG_DATAREADY AES_STATUS_READY
107 #define LL_AES_FLAG_DMA_DONE AES_STATUS_TRANSDONE
108 #define LL_AES_FLAG_DMA_ERR AES_STATUS_TRANSERR
109 #define LL_AES_FLAG_KEY_VALID AES_STATUS_KEYVALID
115 #define LL_AES_KEY_SIZE_128 0x00000000U
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CONFIG_KEYMODE_Pos)
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CONFIG_KEYMODE_Pos)
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CONFIG_OPMODE_Pos)
130 #define LL_AES_KEYTYPE_MCU 0x00000000U
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CONFIG_KEYTYPE_Pos)
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CONFIG_KEYTYPE_Pos)
138 #define LL_AES_DMA_TRANSIZE_MIN (1)
139 #define LL_AES_DMA_TRANSIZE_MAX (2048)
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
201 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE);
220 CLEAR_BITS(AESx->CTRL, AES_CTRL_ENABLE);
239 return (READ_BITS(AESx->CTRL, AES_CTRL_ENABLE) == (AES_CTRL_ENABLE));
258 SET_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
277 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
296 return (READ_BITS(AESx->CTRL, AES_CTRL_START_NORMAL) == (AES_CTRL_START_NORMAL));
315 SET_BITS(AESx->CTRL, AES_CTRL_START_DMA);
334 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_DMA);
353 return (READ_BITS(AESx->CTRL, AES_CTRL_START_DMA) == (AES_CTRL_START_DMA));
372 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE_RKEY);
395 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYMODE, size);
417 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYMODE));
436 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
455 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
474 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK) == (AES_CONFIG_ENABLE_FULLMASK));
493 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
512 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
531 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION) == (AES_CONFIG_ENABLE_ENCRYPTION));
550 SET_BITS(AESx->CONFIG, AES_CONFIG_LOADSEED);
569 SET_BITS(AESx->CONFIG, AES_CONFIG_FIRSTBLOCK);
588 SET_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
607 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
626 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN) == (AES_CONFIG_ENDIAN));
648 MODIFY_REG(AESx->CONFIG, AES_CONFIG_OPMODE, mode);
669 return (READ_BITS(AESx->CONFIG, AES_CONFIG_OPMODE));
692 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYTYPE, Type);
714 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYTYPE));
739 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
758 CLEAR_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
777 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE) == (AES_INTERRUPT_ENABLE));
802 return (READ_BITS(AESx->STATUS, AES_STATUS_READY) == AES_STATUS_READY);
821 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSDONE) == AES_STATUS_TRANSDONE);
840 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSERR) == AES_STATUS_TRANSERR);
859 return (READ_BITS(AESx->STATUS, AES_STATUS_KEYVALID) == AES_STATUS_KEYVALID);
878 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE) == AES_INTERRUPT_DONE);
897 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE);
923 MODIFY_REG(AESx->TRAN_SIZE, AES_TRAN_SIZE, (block << 4) - 1);
942 return ((READ_BITS(AESx->TRAN_SIZE, AES_TRAN_SIZE) + 1) >> 4);
963 WRITE_REG(AESx->RSTART_ADDR, address);
982 return (READ_REG(AESx->RSTART_ADDR));
1003 WRITE_REG(AESx->WSTART_ADDR, address);
1022 return (READ_REG(AESx->WSTART_ADDR));
1048 WRITE_REG(AESx->KEY_ADDR, address);
1067 return (READ_REG(AESx->KEY_ADDR));
1086 return (READ_REG(AESx->DATA_OUT[0]));
1105 return (READ_REG(AESx->DATA_OUT[1]));
1124 return (READ_REG(AESx->DATA_OUT[2]));
1143 return (READ_REG(AESx->DATA_OUT[3]));
1163 WRITE_REG(AESx->KEY[0], key);
1183 WRITE_REG(AESx->KEY[1], key);
1203 WRITE_REG(AESx->KEY[2], key);
1223 WRITE_REG(AESx->KEY[3], key);
1243 WRITE_REG(AESx->KEY[4], key);
1263 WRITE_REG(AESx->KEY[5], key);
1283 WRITE_REG(AESx->KEY[6], key);
1303 WRITE_REG(AESx->KEY[7], key);
1323 WRITE_REG(AESx->SEED_IN, seed);
1342 return (READ_REG(AESx->SEED_IN));
1362 WRITE_REG(AESx->SEED_OUT, seed);
1381 return (READ_REG(AESx->SEED_OUT));
1401 WRITE_REG(AESx->SEED_IMASK, mask);
1420 return (READ_REG(AESx->SEED_IMASK));
1440 WRITE_REG(AESx->SEED_OSBOX, mask);
1459 return (READ_REG(AESx->SEED_OSBOX));
1479 WRITE_REG(AESx->VECTOR_INIT[0], vector);
1499 WRITE_REG(AESx->VECTOR_INIT[1], vector);
1519 WRITE_REG(AESx->VECTOR_INIT[2], vector);
1539 WRITE_REG(AESx->VECTOR_INIT[3], vector);
1559 WRITE_REG(AESx->DATA_IN[0], data);
1579 WRITE_REG(AESx->DATA_IN[1], data);
1599 WRITE_REG(AESx->DATA_IN[2], data);
1619 WRITE_REG(AESx->DATA_IN[3], data);
1639 WRITE_REG(AESx->KPORT_MASK, mask);