52 #ifndef __GR55XX_LL_BOD_H_
53 #define __GR55XX_LL_BOD_H_
110 #define LL_BOD_ENABLE 0x1
111 #define LL_BOD_DISABLE 0x0
117 #define LL_BOD2_ENABLE 0x1
118 #define LL_BOD2_DISABLE 0x0
124 #define LL_BOD_STATIC_ENABLE (0x1)
125 #define LL_BOD_STATIC_DISABLE (0x0)
131 #define LL_BOD2_LEVEL_0 0x0
132 #define LL_BOD2_LEVEL_1 0x1
133 #define LL_BOD2_LEVEL_2 0x2
134 #define LL_BOD2_LEVEL_3 0x3
135 #define LL_BOD2_LEVEL_4 0x4
136 #define LL_BOD2_LEVEL_5 0x5
137 #define LL_BOD2_LEVEL_6 0x6
138 #define LL_BOD2_LEVEL_7 0x7
158 SET_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD_EN);
171 CLEAR_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD_EN);
184 SET_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD2_EN);
197 CLEAR_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD2_EN);
210 MODIFY_REG(AON->RF_REG_3, AON_RF_REG_3_BOD_LVL_CTRL_LV, (lvl_ctrl_lv << AON_RF_REG_3_BOD_LVL_CTRL_LV_Pos));
222 SET_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD_STATIC_LV_EN);
234 CLEAR_BITS(AON->RF_REG_3, AON_RF_REG_3_BOD_STATIC_LV_EN);
248 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE);
262 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE);
276 return (uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_PMU_BOD_FEDGE) == AON_SLP_EVENT_PMU_BOD_FEDGE);
290 GLOBAL_EXCEPTION_DISABLE();
291 WRITE_REG(AON->SLP_EVENT, ~AON_SLP_EVENT_PMU_BOD_FEDGE);
292 GLOBAL_EXCEPTION_ENABLE();