gr55xx_ll_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_GPIO GPIO
47 * @brief GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_GPIO_H__
53 #define __GR55XX_LL_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined (GPIO0) || defined (GPIO1)
63
64 /** @defgroup GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup GPIO_LL_ES_INIT GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL GPIO init configuration definition
75 */
76 typedef struct _ll_gpio_init
77 {
78 uint32_t pin; /*!< Specifies the GPIO pins to be GPIO_InitStructured.
79 This parameter can be any value of @ref GPIO_LL_EC_PIN */
80
81 uint32_t mode; /*!< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref GPIO_LL_EC_MODE.
83
84 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_mode(). */
85
86 uint32_t pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref GPIO_LL_EC_PULL.
88
89 GPIO HW configuration can be modified afterwards using unitary function @ref ll_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref GPIO_LL_EC_MUX.
93
94 GPIO HW GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_gpio_set_mux_pin_0_7() and ll_gpio_set_mux_pin_8_15(). */
96
97 uint32_t trigger; /*!< Specifies the trigger signal active edge.
98 This parameter can be a value of @ref GPIO_LL_EC_TRIGGER. */
99
100 } ll_gpio_init_t;
101
102 /** @} */
103
104 /** @} */
105
106 /**
107 * @defgroup GPIO_LL_MACRO Defines
108 * @{
109 */
110
111 /* Exported constants --------------------------------------------------------*/
112 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
113 * @{
114 */
115
116 /** @defgroup GPIO_LL_EC_PIN PIN
117 * @{
118 */
119 #define LL_GPIO_PIN_0 ((uint32_t)0x0001U) /*!< Select pin 0 */
120 #define LL_GPIO_PIN_1 ((uint32_t)0x0002U) /*!< Select pin 1 */
121 #define LL_GPIO_PIN_2 ((uint32_t)0x0004U) /*!< Select pin 2 */
122 #define LL_GPIO_PIN_3 ((uint32_t)0x0008U) /*!< Select pin 3 */
123 #define LL_GPIO_PIN_4 ((uint32_t)0x0010U) /*!< Select pin 4 */
124 #define LL_GPIO_PIN_5 ((uint32_t)0x0020U) /*!< Select pin 5 */
125 #define LL_GPIO_PIN_6 ((uint32_t)0x0040U) /*!< Select pin 6 */
126 #define LL_GPIO_PIN_7 ((uint32_t)0x0080U) /*!< Select pin 7 */
127 #define LL_GPIO_PIN_8 ((uint32_t)0x0100U) /*!< Select pin 8 */
128 #define LL_GPIO_PIN_9 ((uint32_t)0x0200U) /*!< Select pin 9 */
129 #define LL_GPIO_PIN_10 ((uint32_t)0x0400U) /*!< Select pin 10 */
130 #define LL_GPIO_PIN_11 ((uint32_t)0x0800U) /*!< Select pin 11 */
131 #define LL_GPIO_PIN_12 ((uint32_t)0x1000U) /*!< Select pin 12 */
132 #define LL_GPIO_PIN_13 ((uint32_t)0x2000U) /*!< Select pin 13 */
133 #define LL_GPIO_PIN_14 ((uint32_t)0x4000U) /*!< Select pin 14 */
134 #define LL_GPIO_PIN_15 ((uint32_t)0x8000U) /*!< Select pin 15 */
135 #define LL_GPIO_PIN_ALL ((uint32_t)0xFFFFU) /*!< Select all pins */
136 /** @} */
137
138 /** @defgroup GPIO_LL_EC_MODE Mode
139 * @{
140 */
141 #define LL_GPIO_MODE_INPUT ((uint32_t)0x0U) /*!< Select input mode */
142 #define LL_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /*!< Select output mode */
143 #define LL_GPIO_MODE_MUX ((uint32_t)0x2U) /*!< Select mux peripheral mode */
144 /** @} */
145
146 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
147 * @{
148 */
149 #define LL_GPIO_PULL_NO LL_GPIO_RE_N /*!< Select I/O no pull */
150 #define LL_GPIO_PULL_UP LL_GPIO_RTYP /*!< Select I/O pull up */
151 #define LL_GPIO_PULL_DOWN ((uint32_t)0x0U) /*!< Select I/O pull down */
152 /** @} */
153
154 /** @defgroup GPIO_LL_EC_MUX Alternate Function
155 * @{
156 */
157 #define LL_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
158 #define LL_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
159 #define LL_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
160 #define LL_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
161 #define LL_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
162 #define LL_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
163 #define LL_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
164 #define LL_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
165 #define LL_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
166 /** @} */
167
168 /** @defgroup GPIO_LL_EC_TRIGGER Interrupt Trigger
169 * @{
170 */
171 #define LL_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /*!< No Trigger Mode */
172 #define LL_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /*!< Trigger Rising Mode */
173 #define LL_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /*!< Trigger Falling Mode */
174 #define LL_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /*!< Trigger High Mode */
175 #define LL_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /*!< Trigger Low Mode */
176 /** @} */
177
178 /** @defgroup GPIO_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
179 * @{
180 */
181
182 /**
183 * @brief LL GPIO InitStrcut default configuartion
184 */
185 #define LL_GPIO_DEFAULT_CONFIG \
186 { \
187 .pin = LL_GPIO_PIN_ALL, \
188 .mode = LL_GPIO_MODE_INPUT, \
189 .pull = LL_GPIO_PULL_DOWN, \
190 .mux = LL_GPIO_MUX_7, \
191 .trigger = LL_GPIO_TRIGGER_NONE, \
192 }
193 /** @} */
194
195 /** @} */
196
197 /* Exported macro ------------------------------------------------------------*/
198 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
199 * @{
200 */
201
202 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
203 * @{
204 */
205
206 /**
207 * @brief Write a value in GPIO register
208 * @param __instance__ GPIO instance
209 * @param __REG__ Register to be written
210 * @param __VALUE__ Value to be written in the register
211 * @retval None
212 */
213 #define LL_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
214
215 /**
216 * @brief Read a value in GPIO register
217 * @param __instance__ GPIO instance
218 * @param __REG__ Register to be read
219 * @retval Register value
220 */
221 #define LL_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
222
223 /** @} */
224
225 /** @} */
226
227 /* Private types -------------------------------------------------------------*/
228 /* Private variables ---------------------------------------------------------*/
229 /* Private constants ---------------------------------------------------------*/
230 /* Private macros ------------------------------------------------------------*/
231 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
232 * @{
233 */
234
235 /** @brief Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
236 * @param __GPIOx__ This parameter can be one of the following values:
237 * @arg GPIO0
238 * @arg GPIO1
239 * @retval none
240 */
241 #define LL_GPIO_GET_RESISTOR_POS(__GPIOx__) (((__GPIOx__) == GPIO0) ? 0 : 16)
242
243 /** @brief Get mux control register address of specified GPIO instance.
244 * @param __GPIOx__ This parameter can be one of the following values:
245 * @arg GPIO0
246 * @arg GPIO1
247 * @retval none
248 */
249 #define LL_GPIO_GET_REG_MUX_CTRL_0_7( __GPIOx__) \
250 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL0_7) : &(MCU_SUB->DPAD_MUX_CTL16_23))
251
252 /** @brief Get mux control register address of specified GPIO instance.
253 * @param __GPIOx__ This parameter can be one of the following values:
254 * @arg GPIO0
255 * @arg GPIO1
256 * @retval none
257 */
258 #define LL_GPIO_GET_REG_MUX_CTRL_8_15( __GPIOx__) \
259 (((__GPIOx__) == GPIO0) ? &(MCU_SUB->DPAD_MUX_CTL8_15) : &(MCU_SUB->DPAD_MUX_CTL24_31))
260
261 /** @defgroup GPIO_LL_PM_RESISTOR Resistor Enable
262 * @{
263 */
264 #define LL_GPIO_RE_N_Pos 0 /**< Resistor Enable bits position */
265 #define LL_GPIO_RE_N_Msk (0x1U << LL_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
266 #define LL_GPIO_RE_N LL_GPIO_RE_N_Msk /**< Resistor Enable bits */
267 /** @} */
268
269 /** @defgroup GPIO_LL_PM_RESISTOR_TYPE Resistor Type
270 * @{
271 */
272 #define LL_GPIO_RTYP_Pos 1 /**< Resistor Type bits position */
273 #define LL_GPIO_RTYP_Msk (0x1U << LL_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
274 #define LL_GPIO_RTYP LL_GPIO_RTYP_Msk /**< Resistor Type bits */
275 /** @} */
276
277 /** @} */
278
279 /** @} */
280
281 /* Exported functions --------------------------------------------------------*/
282 /** @defgroup GPIO_LL_DRIVER_FUNCTIONS Functions
283 * @{
284 */
285
286 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
287 * @{
288 */
289
290 /**
291 * @brief Set several pins to input/output mode on dedicated port.
292 *
293 * \rst
294 * +----------------------+-----------------------------------+
295 * | Register | BitsName |
296 * +======================+===================================+
297 * | OUTENSET | OUTENSET |
298 * +----------------------+-----------------------------------+
299 * \endrst
300 * OUTENCLR | OUTENCLR
301 *
302 * @param GPIOx GPIO Port
303 * @param pin_mask This parameter can be a combination of the following values:
304 * @arg @ref LL_GPIO_PIN_0
305 * @arg @ref LL_GPIO_PIN_1
306 * @arg @ref LL_GPIO_PIN_2
307 * @arg @ref LL_GPIO_PIN_3
308 * @arg @ref LL_GPIO_PIN_4
309 * @arg @ref LL_GPIO_PIN_5
310 * @arg @ref LL_GPIO_PIN_6
311 * @arg @ref LL_GPIO_PIN_7
312 * @arg @ref LL_GPIO_PIN_8
313 * @arg @ref LL_GPIO_PIN_9
314 * @arg @ref LL_GPIO_PIN_10
315 * @arg @ref LL_GPIO_PIN_11
316 * @arg @ref LL_GPIO_PIN_12
317 * @arg @ref LL_GPIO_PIN_13
318 * @arg @ref LL_GPIO_PIN_14
319 * @arg @ref LL_GPIO_PIN_15
320 * @arg @ref LL_GPIO_PIN_ALL
321 * @param mode This parameter can be one of the following values:
322 * @arg @ref LL_GPIO_MODE_INPUT
323 * @arg @ref LL_GPIO_MODE_OUTPUT
324 * @retval None
325 */
326 __STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
327 {
328 if (mode == LL_GPIO_MODE_OUTPUT)
329 {
330 WRITE_REG(GPIOx->OUTENSET, pin_mask);
331 }
332 else if(mode == LL_GPIO_MODE_INPUT)
333 {
334 WRITE_REG(GPIOx->OUTENCLR, pin_mask);
335 }
336 }
337
338 /**
339 * @brief Return gpio mode for a dedicated pin on dedicated port.
340 * @note I/O mode can be Input mode, General purpose output.
341 * @note Warning: only one pin can be passed as parameter.
342 *
343 * \rst
344 * +----------------------+-----------------------------------+
345 * | Register | BitsName |
346 * +======================+===================================+
347 * | OUTENSET | OUTENSET |
348 * +----------------------+-----------------------------------+
349 * \endrst
350 *
351 * @param GPIOx GPIO Port
352 * @param pin This parameter can be one of the following values:
353 * @arg @ref LL_GPIO_PIN_0
354 * @arg @ref LL_GPIO_PIN_1
355 * @arg @ref LL_GPIO_PIN_2
356 * @arg @ref LL_GPIO_PIN_3
357 * @arg @ref LL_GPIO_PIN_4
358 * @arg @ref LL_GPIO_PIN_5
359 * @arg @ref LL_GPIO_PIN_6
360 * @arg @ref LL_GPIO_PIN_7
361 * @arg @ref LL_GPIO_PIN_8
362 * @arg @ref LL_GPIO_PIN_9
363 * @arg @ref LL_GPIO_PIN_10
364 * @arg @ref LL_GPIO_PIN_11
365 * @arg @ref LL_GPIO_PIN_12
366 * @arg @ref LL_GPIO_PIN_13
367 * @arg @ref LL_GPIO_PIN_14
368 * @arg @ref LL_GPIO_PIN_15
369 * @retval Returned value can be one of the following values:
370 * @arg @ref LL_GPIO_MODE_INPUT
371 * @arg @ref LL_GPIO_MODE_OUTPUT
372 */
373 __STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
374 {
375 return (uint32_t)(READ_BITS(GPIOx->OUTENSET, pin) != RESET);
376 }
377
378 /**
379 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
380 *
381 * \rst
382 * +----------------------+-----------------------------------+
383 * | Register | BitsName |
384 * +======================+===================================+
385 * | DPAD_RE_N_BUS | RE_N |
386 * +----------------------+-----------------------------------+
387 * \endrst
388 * DPAD_RTYP_BUS | RTYP
389 *
390 * @param GPIOx GPIO Port
391 * @param pin_mask This parameter can be a combination of the following values:
392 * @arg @ref LL_GPIO_PIN_0
393 * @arg @ref LL_GPIO_PIN_1
394 * @arg @ref LL_GPIO_PIN_2
395 * @arg @ref LL_GPIO_PIN_3
396 * @arg @ref LL_GPIO_PIN_4
397 * @arg @ref LL_GPIO_PIN_5
398 * @arg @ref LL_GPIO_PIN_6
399 * @arg @ref LL_GPIO_PIN_7
400 * @arg @ref LL_GPIO_PIN_8
401 * @arg @ref LL_GPIO_PIN_9
402 * @arg @ref LL_GPIO_PIN_10
403 * @arg @ref LL_GPIO_PIN_11
404 * @arg @ref LL_GPIO_PIN_12
405 * @arg @ref LL_GPIO_PIN_13
406 * @arg @ref LL_GPIO_PIN_14
407 * @arg @ref LL_GPIO_PIN_15
408 * @param pull This parameter can be one of the following values:
409 * @arg @ref LL_GPIO_PULL_NO
410 * @arg @ref LL_GPIO_PULL_UP
411 * @arg @ref LL_GPIO_PULL_DOWN
412 * @retval None
413 */
414 __STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
415 {
416 /* Get pin mask in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
417 pin_mask <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
418 MODIFY_REG(MCU_SUB->DPAD_RTYP_BUS, pin_mask, (pull == LL_GPIO_PULL_UP) ? pin_mask : 0x0000U);
419 MODIFY_REG(MCU_SUB->DPAD_RE_N_BUS, pin_mask, (pull == LL_GPIO_PULL_NO) ? pin_mask : 0x0000U);
420 }
421
422 /**
423 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
424 * @note Warning: only one pin can be passed as parameter.
425 *
426 * \rst
427 * +----------------------+-----------------------------------+
428 * | Register | BitsName |
429 * +======================+===================================+
430 * | DPAD_RE_N_BUS | RE_N |
431 * +----------------------+-----------------------------------+
432 * \endrst
433 * DPAD_RTYP_BUS | RTYP
434 *
435 * @param GPIOx GPIO Port
436 * @param pin This parameter can be one of the following values:
437 * @arg @ref LL_GPIO_PIN_0
438 * @arg @ref LL_GPIO_PIN_1
439 * @arg @ref LL_GPIO_PIN_2
440 * @arg @ref LL_GPIO_PIN_3
441 * @arg @ref LL_GPIO_PIN_4
442 * @arg @ref LL_GPIO_PIN_5
443 * @arg @ref LL_GPIO_PIN_6
444 * @arg @ref LL_GPIO_PIN_7
445 * @arg @ref LL_GPIO_PIN_8
446 * @arg @ref LL_GPIO_PIN_9
447 * @arg @ref LL_GPIO_PIN_10
448 * @arg @ref LL_GPIO_PIN_11
449 * @arg @ref LL_GPIO_PIN_12
450 * @arg @ref LL_GPIO_PIN_13
451 * @arg @ref LL_GPIO_PIN_14
452 * @arg @ref LL_GPIO_PIN_15
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_GPIO_PULL_NO
455 * @arg @ref LL_GPIO_PULL_UP
456 * @arg @ref LL_GPIO_PULL_DOWN
457 */
458 __STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
459 {
460 /* Get pin position in resitor related registers, GPIO0:0~15, GPIO1:16~31 */
461 pin <<= LL_GPIO_GET_RESISTOR_POS(GPIOx);
462 return ((READ_BITS(MCU_SUB->DPAD_RE_N_BUS, pin) != RESET) ? LL_GPIO_PULL_NO :
463 ((READ_BITS(MCU_SUB->DPAD_RTYP_BUS, pin) != RESET) ? LL_GPIO_PULL_UP : LL_GPIO_PULL_DOWN));
464 }
465
466 /**
467 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
468 * @note Possible values are from AF0 to AF15 depending on target.
469 * @note Warning: only one pin can be passed as parameter.
470 *
471 * \rst
472 * +----------------------+-----------------------------------+
473 * | Register | BitsName |
474 * +======================+===================================+
475 * | DPAD_MUX_CTRL0_7 | CTRL0_7 |
476 * +----------------------+-----------------------------------+
477 * \endrst
478 * DPAD_MUX_CTRL16_23 | CTRL16_23
479 *
480 * @param GPIOx GPIO Port
481 * @param pin This parameter can be one of the following values:
482 * @arg @ref LL_GPIO_PIN_0
483 * @arg @ref LL_GPIO_PIN_1
484 * @arg @ref LL_GPIO_PIN_2
485 * @arg @ref LL_GPIO_PIN_3
486 * @arg @ref LL_GPIO_PIN_4
487 * @arg @ref LL_GPIO_PIN_5
488 * @arg @ref LL_GPIO_PIN_6
489 * @arg @ref LL_GPIO_PIN_7
490 * @param mux This parameter can be one of the following values:
491 * @arg @ref LL_GPIO_MUX_0
492 * @arg @ref LL_GPIO_MUX_1
493 * @arg @ref LL_GPIO_MUX_2
494 * @arg @ref LL_GPIO_MUX_3
495 * @arg @ref LL_GPIO_MUX_4
496 * @arg @ref LL_GPIO_MUX_5
497 * @arg @ref LL_GPIO_MUX_6
498 * @arg @ref LL_GPIO_MUX_7
499 * @arg @ref LL_GPIO_MUX_8
500 * @retval None
501 */
502 __STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
503 {
504 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
505 uint32_t pos = POSITION_VAL(pin) << 2;
506 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
507 }
508
509 /**
510 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
511 *
512 * \rst
513 * +----------------------+-----------------------------------+
514 * | Register | BitsName |
515 * +======================+===================================+
516 * | DPAD_MUX_CTRL0_7 | CTRL0_7 |
517 * +----------------------+-----------------------------------+
518 * \endrst
519 * DPAD_MUX_CTRL16_23 | CTRL16_23
520 *
521 * @param GPIOx GPIO Port
522 * @param pin This parameter can be one of the following values:
523 * @arg @ref LL_GPIO_PIN_0
524 * @arg @ref LL_GPIO_PIN_1
525 * @arg @ref LL_GPIO_PIN_2
526 * @arg @ref LL_GPIO_PIN_3
527 * @arg @ref LL_GPIO_PIN_4
528 * @arg @ref LL_GPIO_PIN_5
529 * @arg @ref LL_GPIO_PIN_6
530 * @arg @ref LL_GPIO_PIN_7
531 * @retval Returned value can be one of the following values:
532 * @arg @ref LL_GPIO_MUX_0
533 * @arg @ref LL_GPIO_MUX_1
534 * @arg @ref LL_GPIO_MUX_2
535 * @arg @ref LL_GPIO_MUX_3
536 * @arg @ref LL_GPIO_MUX_4
537 * @arg @ref LL_GPIO_MUX_5
538 * @arg @ref LL_GPIO_MUX_6
539 * @arg @ref LL_GPIO_MUX_7
540 * @arg @ref LL_GPIO_MUX_8
541 */
542 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
543 {
544 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_0_7(GPIOx);
545 uint32_t pos = POSITION_VAL(pin) << 2;
546 return (READ_BITS(*pReg, 0xF << pos) >> pos);
547 }
548
549 /**
550 * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
551 * @note Possible values are from AF0 to AF15 depending on target.
552 * @note Warning: only one pin can be passed as parameter.
553 *
554 * \rst
555 * +----------------------+-----------------------------------+
556 * | Register | BitsName |
557 * +======================+===================================+
558 * | DPAD_MUX_CTRL8_15 | CTRL8_15 |
559 * +----------------------+-----------------------------------+
560 * \endrst
561 * DPAD_MUX_CTRL24_31 | CTRL24_31
562 *
563 * @param GPIOx GPIO Port
564 * @param pin This parameter can be one of the following values:
565 * @arg @ref LL_GPIO_PIN_8
566 * @arg @ref LL_GPIO_PIN_9
567 * @arg @ref LL_GPIO_PIN_10
568 * @arg @ref LL_GPIO_PIN_11
569 * @arg @ref LL_GPIO_PIN_12
570 * @arg @ref LL_GPIO_PIN_13
571 * @arg @ref LL_GPIO_PIN_14
572 * @arg @ref LL_GPIO_PIN_15
573 * @param mux This parameter can be one of the following values:
574 * @arg @ref LL_GPIO_MUX_0
575 * @arg @ref LL_GPIO_MUX_1
576 * @arg @ref LL_GPIO_MUX_2
577 * @arg @ref LL_GPIO_MUX_3
578 * @arg @ref LL_GPIO_MUX_4
579 * @arg @ref LL_GPIO_MUX_5
580 * @arg @ref LL_GPIO_MUX_6
581 * @arg @ref LL_GPIO_MUX_7
582 * @arg @ref LL_GPIO_MUX_8
583 * @retval None
584 */
585 __STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
586 {
587 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
588 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
589 MODIFY_REG(*pReg, 0xF << pos, mux << pos);
590 }
591
592 /**
593 * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
594 * @note Possible values are from AF0 to AF15 depending on target.
595 *
596 * \rst
597 * +----------------------+-----------------------------------+
598 * | Register | BitsName |
599 * +======================+===================================+
600 * | DPAD_MUX_CTRL8_15 | CTRL8_15 |
601 * +----------------------+-----------------------------------+
602 * \endrst
603 * DPAD_MUX_CTRL24_31 | CTRL24_31
604 *
605 * @param GPIOx GPIO Port
606 * @param pin This parameter can be one of the following values:
607 * @arg @ref LL_GPIO_PIN_8
608 * @arg @ref LL_GPIO_PIN_9
609 * @arg @ref LL_GPIO_PIN_10
610 * @arg @ref LL_GPIO_PIN_11
611 * @arg @ref LL_GPIO_PIN_12
612 * @arg @ref LL_GPIO_PIN_13
613 * @arg @ref LL_GPIO_PIN_14
614 * @arg @ref LL_GPIO_PIN_15
615 * @retval Returned value can be one of the following values:
616 * @arg @ref LL_GPIO_MUX_0
617 * @arg @ref LL_GPIO_MUX_1
618 * @arg @ref LL_GPIO_MUX_2
619 * @arg @ref LL_GPIO_MUX_3
620 * @arg @ref LL_GPIO_MUX_4
621 * @arg @ref LL_GPIO_MUX_5
622 * @arg @ref LL_GPIO_MUX_6
623 * @arg @ref LL_GPIO_MUX_7
624 * @arg @ref LL_GPIO_MUX_8
625 */
626 __STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
627 {
628 volatile uint32_t *pReg = LL_GPIO_GET_REG_MUX_CTRL_8_15(GPIOx);
629 uint32_t pos = POSITION_VAL(pin >> 8) << 2;
630 return (READ_BITS(*pReg, 0xF << pos) >> pos);
631 }
632
633 /** @} */
634
635 /** @defgroup GPIO_LL_EF_Data_Access Data Access
636 * @{
637 */
638
639 /**
640 * @brief Return full input data register value for a dedicated port.
641 *
642 * \rst
643 * +----------------------+-----------------------------------+
644 * | Register | BitsName |
645 * +======================+===================================+
646 * | DATA | DATA |
647 * +----------------------+-----------------------------------+
648 * \endrst
649 *
650 * @param GPIOx GPIO Port
651 * @retval Input data register value of port
652 */
653 __STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
654 {
655 return (uint32_t)(READ_REG(GPIOx->DATA));
656 }
657
658 /**
659 * @brief Return if input data level for several pins of dedicated port is high or low.
660 *
661 * \rst
662 * +----------------------+-----------------------------------+
663 * | Register | BitsName |
664 * +======================+===================================+
665 * | DATA | DATA |
666 * +----------------------+-----------------------------------+
667 * \endrst
668 *
669 * @param GPIOx GPIO Port
670 * @param pin_mask This parameter can be a combination of the following values:
671 * @arg @ref LL_GPIO_PIN_0
672 * @arg @ref LL_GPIO_PIN_1
673 * @arg @ref LL_GPIO_PIN_2
674 * @arg @ref LL_GPIO_PIN_3
675 * @arg @ref LL_GPIO_PIN_4
676 * @arg @ref LL_GPIO_PIN_5
677 * @arg @ref LL_GPIO_PIN_6
678 * @arg @ref LL_GPIO_PIN_7
679 * @arg @ref LL_GPIO_PIN_8
680 * @arg @ref LL_GPIO_PIN_9
681 * @arg @ref LL_GPIO_PIN_10
682 * @arg @ref LL_GPIO_PIN_11
683 * @arg @ref LL_GPIO_PIN_12
684 * @arg @ref LL_GPIO_PIN_13
685 * @arg @ref LL_GPIO_PIN_14
686 * @arg @ref LL_GPIO_PIN_15
687 * @arg @ref LL_GPIO_PIN_ALL
688 * @retval State of bit (1 or 0).
689 */
690 __STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
691 {
692 return (READ_BITS(GPIOx->DATA, pin_mask) == (pin_mask));
693 }
694
695 /**
696 * @brief Write output data register for the port.
697 *
698 * \rst
699 * +----------------------+-----------------------------------+
700 * | Register | BitsName |
701 * +======================+===================================+
702 * | DATAOUT | DATAOUT |
703 * +----------------------+-----------------------------------+
704 * \endrst
705 *
706 * @param GPIOx GPIO Port
707 * @param port_value Level value for each pin of the port
708 * @retval None
709 */
710 __STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
711 {
712 WRITE_REG(GPIOx->DATAOUT, port_value);
713 }
714
715 /**
716 * @brief Return full output data register value for a dedicated port.
717 *
718 * \rst
719 * +----------------------+-----------------------------------+
720 * | Register | BitsName |
721 * +======================+===================================+
722 * | DATAOUT | DATAOUT |
723 * +----------------------+-----------------------------------+
724 * \endrst
725 *
726 * @param GPIOx GPIO Port
727 * @retval Output data register value of port
728 */
729 __STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
730 {
731 return (uint32_t)(READ_REG(GPIOx->DATAOUT));
732 }
733
734 /**
735 * @brief Return if input data level for several pins of dedicated port is high or low.
736 *
737 * \rst
738 * +----------------------+-----------------------------------+
739 * | Register | BitsName |
740 * +======================+===================================+
741 * | DATAOUT | DATAOUT |
742 * +----------------------+-----------------------------------+
743 * \endrst
744 *
745 * @param GPIOx GPIO Port
746 * @param pin_mask This parameter can be a combination of the following values:
747 * @arg @ref LL_GPIO_PIN_0
748 * @arg @ref LL_GPIO_PIN_1
749 * @arg @ref LL_GPIO_PIN_2
750 * @arg @ref LL_GPIO_PIN_3
751 * @arg @ref LL_GPIO_PIN_4
752 * @arg @ref LL_GPIO_PIN_5
753 * @arg @ref LL_GPIO_PIN_6
754 * @arg @ref LL_GPIO_PIN_7
755 * @arg @ref LL_GPIO_PIN_8
756 * @arg @ref LL_GPIO_PIN_9
757 * @arg @ref LL_GPIO_PIN_10
758 * @arg @ref LL_GPIO_PIN_11
759 * @arg @ref LL_GPIO_PIN_12
760 * @arg @ref LL_GPIO_PIN_13
761 * @arg @ref LL_GPIO_PIN_14
762 * @arg @ref LL_GPIO_PIN_15
763 * @arg @ref LL_GPIO_PIN_ALL
764 * @retval State of bit (1 or 0).
765 */
766 __STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
767 {
768 return (READ_BITS(GPIOx->DATAOUT, pin_mask) == (pin_mask));
769 }
770
771 /**
772 * @brief Set several pins to high level on dedicated gpio port.
773 *
774 * \rst
775 * +----------------------+-----------------------------------+
776 * | Register | BitsName |
777 * +======================+===================================+
778 * | DATAOUT | DATAOUT |
779 * +----------------------+-----------------------------------+
780 * \endrst
781 *
782 * @param GPIOx GPIO Port
783 * @param pin_mask This parameter can be a combination of the following values:
784 * @arg @ref LL_GPIO_PIN_0
785 * @arg @ref LL_GPIO_PIN_1
786 * @arg @ref LL_GPIO_PIN_2
787 * @arg @ref LL_GPIO_PIN_3
788 * @arg @ref LL_GPIO_PIN_4
789 * @arg @ref LL_GPIO_PIN_5
790 * @arg @ref LL_GPIO_PIN_6
791 * @arg @ref LL_GPIO_PIN_7
792 * @arg @ref LL_GPIO_PIN_8
793 * @arg @ref LL_GPIO_PIN_9
794 * @arg @ref LL_GPIO_PIN_10
795 * @arg @ref LL_GPIO_PIN_11
796 * @arg @ref LL_GPIO_PIN_12
797 * @arg @ref LL_GPIO_PIN_13
798 * @arg @ref LL_GPIO_PIN_14
799 * @arg @ref LL_GPIO_PIN_15
800 * @arg @ref LL_GPIO_PIN_ALL
801 * @retval None
802 */
803 __STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
804 {
805 #ifdef USE_GPIO_MASK_REGISTER
806 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], pin_mask & GPIO_MASKLOWBYTE_DATA);
807 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> GPIO_MASKHIGHBYTE_DATA_Pos)],
808 pin_mask & GPIO_MASKHIGHBYTE_DATA);
809 #else
810 SET_BITS(GPIOx->DATAOUT, pin_mask);
811 #endif
812 }
813
814 /**
815 * @brief Set several pins to low level on dedicated gpio port.
816 *
817 * \rst
818 * +----------------------+-----------------------------------+
819 * | Register | BitsName |
820 * +======================+===================================+
821 * | DATAOUT | DATAOUT |
822 * +----------------------+-----------------------------------+
823 * \endrst
824 *
825 * @param GPIOx GPIO Port
826 * @param pin_mask This parameter can be a combination of the following values:
827 * @arg @ref LL_GPIO_PIN_0
828 * @arg @ref LL_GPIO_PIN_1
829 * @arg @ref LL_GPIO_PIN_2
830 * @arg @ref LL_GPIO_PIN_3
831 * @arg @ref LL_GPIO_PIN_4
832 * @arg @ref LL_GPIO_PIN_5
833 * @arg @ref LL_GPIO_PIN_6
834 * @arg @ref LL_GPIO_PIN_7
835 * @arg @ref LL_GPIO_PIN_8
836 * @arg @ref LL_GPIO_PIN_9
837 * @arg @ref LL_GPIO_PIN_10
838 * @arg @ref LL_GPIO_PIN_11
839 * @arg @ref LL_GPIO_PIN_12
840 * @arg @ref LL_GPIO_PIN_13
841 * @arg @ref LL_GPIO_PIN_14
842 * @arg @ref LL_GPIO_PIN_15
843 * @arg @ref LL_GPIO_PIN_ALL
844 * @retval None
845 */
846 __STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
847 {
848 #ifdef USE_GPIO_MASK_REGISTER
849 WRITE_REG(GPIOx->MASKLOWBYTE[(uint8_t)pin_mask], 0x0000U);
850 WRITE_REG(GPIOx->MASKHIGHBYTE[(uint8_t)(pin_mask >> 8)], 0x0000U);
851 #else
852 CLEAR_BITS(GPIOx->DATAOUT, pin_mask);
853 #endif
854 }
855
856 /**
857 * @brief Toggle data value for several pin of dedicated port.
858 *
859 * \rst
860 * +----------------------+-----------------------------------+
861 * | Register | BitsName |
862 * +======================+===================================+
863 * | DATAOUT | DATAOUT |
864 * +----------------------+-----------------------------------+
865 * \endrst
866 *
867 * @param GPIOx GPIO Port
868 * @param pin_mask This parameter can be a combination of the following values:
869 * @arg @ref LL_GPIO_PIN_0
870 * @arg @ref LL_GPIO_PIN_1
871 * @arg @ref LL_GPIO_PIN_2
872 * @arg @ref LL_GPIO_PIN_3
873 * @arg @ref LL_GPIO_PIN_4
874 * @arg @ref LL_GPIO_PIN_5
875 * @arg @ref LL_GPIO_PIN_6
876 * @arg @ref LL_GPIO_PIN_7
877 * @arg @ref LL_GPIO_PIN_8
878 * @arg @ref LL_GPIO_PIN_9
879 * @arg @ref LL_GPIO_PIN_10
880 * @arg @ref LL_GPIO_PIN_11
881 * @arg @ref LL_GPIO_PIN_12
882 * @arg @ref LL_GPIO_PIN_13
883 * @arg @ref LL_GPIO_PIN_14
884 * @arg @ref LL_GPIO_PIN_15
885 * @arg @ref LL_GPIO_PIN_ALL
886 * @retval None
887 */
888 __STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
889 {
890 WRITE_REG(GPIOx->DATAOUT, READ_REG(GPIOx->DATAOUT) ^ pin_mask);
891 }
892
893 /** @} */
894
895 /** @defgroup GPIO_LL_EF_IT_Management IT_Management
896 * @{
897 */
898
899 /**
900 * @brief Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
901 * @note
902 *
903 * \rst
904 * +----------------------+-----------------------------------+
905 * | Register | BitsName |
906 * +======================+===================================+
907 * | INTPOLCLR | INTPOLCLR |
908 * +----------------------+-----------------------------------+
909 * \endrst
910 * INTTYPESET | INTTYPESET
911 *
912 * @param GPIOx GPIO instance.
913 * @param pin_mask This parameter can be a combination of the following values:
914 * @arg @ref LL_GPIO_PIN_0
915 * @arg @ref LL_GPIO_PIN_1
916 * @arg @ref LL_GPIO_PIN_2
917 * @arg @ref LL_GPIO_PIN_3
918 * @arg @ref LL_GPIO_PIN_4
919 * @arg @ref LL_GPIO_PIN_5
920 * @arg @ref LL_GPIO_PIN_6
921 * @arg @ref LL_GPIO_PIN_7
922 * @arg @ref LL_GPIO_PIN_8
923 * @arg @ref LL_GPIO_PIN_9
924 * @arg @ref LL_GPIO_PIN_10
925 * @arg @ref LL_GPIO_PIN_11
926 * @arg @ref LL_GPIO_PIN_12
927 * @arg @ref LL_GPIO_PIN_13
928 * @arg @ref LL_GPIO_PIN_14
929 * @arg @ref LL_GPIO_PIN_15
930 * @arg @ref LL_GPIO_PIN_ALL
931 * @retval None
932 */
933 __STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
934 {
935 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
936 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
937 }
938
939 /**
940 * @brief Check if falling edge trigger is enabled for pins in the range of 0 to 15.
941 * @note
942 *
943 * \rst
944 * +----------------------+-----------------------------------+
945 * | Register | BitsName |
946 * +======================+===================================+
947 * | INTPOLCLR | INTPOLCLR |
948 * +----------------------+-----------------------------------+
949 * \endrst
950 * INTTYPESET | INTTYPESET
951 *
952 * @param GPIOx GPIO instance.
953 * @param pin_mask This parameter can be a combination of the following values:
954 * @arg @ref LL_GPIO_PIN_0
955 * @arg @ref LL_GPIO_PIN_1
956 * @arg @ref LL_GPIO_PIN_2
957 * @arg @ref LL_GPIO_PIN_3
958 * @arg @ref LL_GPIO_PIN_4
959 * @arg @ref LL_GPIO_PIN_5
960 * @arg @ref LL_GPIO_PIN_6
961 * @arg @ref LL_GPIO_PIN_7
962 * @arg @ref LL_GPIO_PIN_8
963 * @arg @ref LL_GPIO_PIN_9
964 * @arg @ref LL_GPIO_PIN_10
965 * @arg @ref LL_GPIO_PIN_11
966 * @arg @ref LL_GPIO_PIN_12
967 * @arg @ref LL_GPIO_PIN_13
968 * @arg @ref LL_GPIO_PIN_14
969 * @arg @ref LL_GPIO_PIN_15
970 * @arg @ref LL_GPIO_PIN_ALL
971 * @retval State of bit (1 or 0).
972 */
973 __STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
974 {
975 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
976 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
977 }
978
979 /**
980 * @brief Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
981 * @note
982 *
983 * \rst
984 * +----------------------+-----------------------------------+
985 * | Register | BitsName |
986 * +======================+===================================+
987 * | INTPOLSET | INTPOLSET |
988 * +----------------------+-----------------------------------+
989 * \endrst
990 * INTTYPESET | INTTYPESET
991 *
992 * @param GPIOx GPIO instance.
993 * @param pin_mask This parameter can be a combination of the following values:
994 * @arg @ref LL_GPIO_PIN_0
995 * @arg @ref LL_GPIO_PIN_1
996 * @arg @ref LL_GPIO_PIN_2
997 * @arg @ref LL_GPIO_PIN_3
998 * @arg @ref LL_GPIO_PIN_4
999 * @arg @ref LL_GPIO_PIN_5
1000 * @arg @ref LL_GPIO_PIN_6
1001 * @arg @ref LL_GPIO_PIN_7
1002 * @arg @ref LL_GPIO_PIN_8
1003 * @arg @ref LL_GPIO_PIN_9
1004 * @arg @ref LL_GPIO_PIN_10
1005 * @arg @ref LL_GPIO_PIN_11
1006 * @arg @ref LL_GPIO_PIN_12
1007 * @arg @ref LL_GPIO_PIN_13
1008 * @arg @ref LL_GPIO_PIN_14
1009 * @arg @ref LL_GPIO_PIN_15
1010 * @arg @ref LL_GPIO_PIN_ALL
1011 * @retval None
1012 */
1013 __STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1014 {
1015 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1016 WRITE_REG(GPIOx->INTTYPESET, pin_mask);
1017 }
1018
1019 /**
1020 * @brief Check if rising edge trigger is enabled for pins in the range of 0 to 15.
1021 * @note
1022 *
1023 * \rst
1024 * +----------------------+-----------------------------------+
1025 * | Register | BitsName |
1026 * +======================+===================================+
1027 * | INTPOLSET | INTPOLSET |
1028 * +----------------------+-----------------------------------+
1029 * \endrst
1030 * INTTYPESET | INTTYPESET
1031 *
1032 * @param GPIOx GPIO instance.
1033 * @param pin_mask This parameter can be a combination of the following values:
1034 * @arg @ref LL_GPIO_PIN_0
1035 * @arg @ref LL_GPIO_PIN_1
1036 * @arg @ref LL_GPIO_PIN_2
1037 * @arg @ref LL_GPIO_PIN_3
1038 * @arg @ref LL_GPIO_PIN_4
1039 * @arg @ref LL_GPIO_PIN_5
1040 * @arg @ref LL_GPIO_PIN_6
1041 * @arg @ref LL_GPIO_PIN_7
1042 * @arg @ref LL_GPIO_PIN_8
1043 * @arg @ref LL_GPIO_PIN_9
1044 * @arg @ref LL_GPIO_PIN_10
1045 * @arg @ref LL_GPIO_PIN_11
1046 * @arg @ref LL_GPIO_PIN_12
1047 * @arg @ref LL_GPIO_PIN_13
1048 * @arg @ref LL_GPIO_PIN_14
1049 * @arg @ref LL_GPIO_PIN_15
1050 * @arg @ref LL_GPIO_PIN_ALL
1051 * @note Please check each device line mapping for GPIO Line availability
1052 * @retval State of bit (1 or 0).
1053 */
1054 __STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1055 {
1056 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
1057 (READ_BITS(GPIOx->INTTYPESET, pin_mask) == (pin_mask)));
1058 }
1059
1060 /**
1061 * @brief Enable GPIO High Level Trigger for pins in the range of 0 to 15.
1062 * @note
1063 *
1064 * \rst
1065 * +----------------------+-----------------------------------+
1066 * | Register | BitsName |
1067 * +======================+===================================+
1068 * | INTPOLSET | INTPOLSET |
1069 * +----------------------+-----------------------------------+
1070 * \endrst
1071 * INTTYPECLR | INTTYPECLR
1072 *
1073 * @param GPIOx GPIO instance.
1074 * @param pin_mask This parameter can be a combination of the following values:
1075 * @arg @ref LL_GPIO_PIN_0
1076 * @arg @ref LL_GPIO_PIN_1
1077 * @arg @ref LL_GPIO_PIN_2
1078 * @arg @ref LL_GPIO_PIN_3
1079 * @arg @ref LL_GPIO_PIN_4
1080 * @arg @ref LL_GPIO_PIN_5
1081 * @arg @ref LL_GPIO_PIN_6
1082 * @arg @ref LL_GPIO_PIN_7
1083 * @arg @ref LL_GPIO_PIN_8
1084 * @arg @ref LL_GPIO_PIN_9
1085 * @arg @ref LL_GPIO_PIN_10
1086 * @arg @ref LL_GPIO_PIN_11
1087 * @arg @ref LL_GPIO_PIN_12
1088 * @arg @ref LL_GPIO_PIN_13
1089 * @arg @ref LL_GPIO_PIN_14
1090 * @arg @ref LL_GPIO_PIN_15
1091 * @arg @ref LL_GPIO_PIN_ALL
1092 * @retval None
1093 */
1094 __STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1095 {
1096 WRITE_REG(GPIOx->INTPOLSET, pin_mask);
1097 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1098 }
1099
1100 /**
1101 * @brief Check if high level trigger is enabled for pins in the range of 0 to 15.
1102 * @note
1103 *
1104 * \rst
1105 * +----------------------+-----------------------------------+
1106 * | Register | BitsName |
1107 * +======================+===================================+
1108 * | INTPOLSET | INTPOLSET |
1109 * +----------------------+-----------------------------------+
1110 * \endrst
1111 * INTTYPECLR | INTTYPECLR
1112 *
1113 * @param GPIOx GPIO instance.
1114 * @param pin_mask This parameter can be a combination of the following values:
1115 * @arg @ref LL_GPIO_PIN_0
1116 * @arg @ref LL_GPIO_PIN_1
1117 * @arg @ref LL_GPIO_PIN_2
1118 * @arg @ref LL_GPIO_PIN_3
1119 * @arg @ref LL_GPIO_PIN_4
1120 * @arg @ref LL_GPIO_PIN_5
1121 * @arg @ref LL_GPIO_PIN_6
1122 * @arg @ref LL_GPIO_PIN_7
1123 * @arg @ref LL_GPIO_PIN_8
1124 * @arg @ref LL_GPIO_PIN_9
1125 * @arg @ref LL_GPIO_PIN_10
1126 * @arg @ref LL_GPIO_PIN_11
1127 * @arg @ref LL_GPIO_PIN_12
1128 * @arg @ref LL_GPIO_PIN_13
1129 * @arg @ref LL_GPIO_PIN_14
1130 * @arg @ref LL_GPIO_PIN_15
1131 * @arg @ref LL_GPIO_PIN_ALL
1132 * @retval State of bit (1 or 0).
1133 */
1134 __STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1135 {
1136 return ((READ_BITS(GPIOx->INTPOLSET, pin_mask) == (pin_mask)) &&
1137 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1138 }
1139
1140 /**
1141 * @brief Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
1142 * @note
1143 *
1144 * \rst
1145 * +----------------------+-----------------------------------+
1146 * | Register | BitsName |
1147 * +======================+===================================+
1148 * | INTPOLCLR | INTPOLCLR |
1149 * +----------------------+-----------------------------------+
1150 * \endrst
1151 * INTTYPECLR | INTTYPECLR
1152 *
1153 * @param GPIOx GPIO instance.
1154 * @param pin_mask This parameter can be a combination of the following values:
1155 * @arg @ref LL_GPIO_PIN_0
1156 * @arg @ref LL_GPIO_PIN_1
1157 * @arg @ref LL_GPIO_PIN_2
1158 * @arg @ref LL_GPIO_PIN_3
1159 * @arg @ref LL_GPIO_PIN_4
1160 * @arg @ref LL_GPIO_PIN_5
1161 * @arg @ref LL_GPIO_PIN_6
1162 * @arg @ref LL_GPIO_PIN_7
1163 * @arg @ref LL_GPIO_PIN_8
1164 * @arg @ref LL_GPIO_PIN_9
1165 * @arg @ref LL_GPIO_PIN_10
1166 * @arg @ref LL_GPIO_PIN_11
1167 * @arg @ref LL_GPIO_PIN_12
1168 * @arg @ref LL_GPIO_PIN_13
1169 * @arg @ref LL_GPIO_PIN_14
1170 * @arg @ref LL_GPIO_PIN_15
1171 * @arg @ref LL_GPIO_PIN_ALL
1172 * @retval None
1173 */
1174 __STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1175 {
1176 WRITE_REG(GPIOx->INTPOLCLR, pin_mask);
1177 WRITE_REG(GPIOx->INTTYPECLR, pin_mask);
1178 }
1179
1180 /**
1181 * @brief Check if low level trigger is enabled for pins in the range of 0 to 15
1182 * @note
1183 *
1184 * \rst
1185 * +----------------------+-----------------------------------+
1186 * | Register | BitsName |
1187 * +======================+===================================+
1188 * | INTPOLCLR | INTPOLCLR |
1189 * +----------------------+-----------------------------------+
1190 * \endrst
1191 * INTTYPECLR | INTTYPECLR
1192 *
1193 * @param GPIOx GPIO instance.
1194 * @param pin_mask This parameter can be a combination of the following values:
1195 * @arg @ref LL_GPIO_PIN_0
1196 * @arg @ref LL_GPIO_PIN_1
1197 * @arg @ref LL_GPIO_PIN_2
1198 * @arg @ref LL_GPIO_PIN_3
1199 * @arg @ref LL_GPIO_PIN_4
1200 * @arg @ref LL_GPIO_PIN_5
1201 * @arg @ref LL_GPIO_PIN_6
1202 * @arg @ref LL_GPIO_PIN_7
1203 * @arg @ref LL_GPIO_PIN_8
1204 * @arg @ref LL_GPIO_PIN_9
1205 * @arg @ref LL_GPIO_PIN_10
1206 * @arg @ref LL_GPIO_PIN_11
1207 * @arg @ref LL_GPIO_PIN_12
1208 * @arg @ref LL_GPIO_PIN_13
1209 * @arg @ref LL_GPIO_PIN_14
1210 * @arg @ref LL_GPIO_PIN_15
1211 * @arg @ref LL_GPIO_PIN_ALL
1212 * @retval State of bit (1 or 0).
1213 */
1214 __STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
1215 {
1216 return ((READ_BITS(GPIOx->INTPOLCLR, pin_mask) == (pin_mask)) &&
1217 (READ_BITS(GPIOx->INTTYPECLR, pin_mask) == (pin_mask)));
1218 }
1219
1220 /**
1221 * @brief Enable GPIO interrupts for pins in the range of 0 to 15.
1222 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1223 *
1224 * \rst
1225 * +----------------------+-----------------------------------+
1226 * | Register | BitsName |
1227 * +======================+===================================+
1228 * | INTENSET | INTENSET |
1229 * +----------------------+-----------------------------------+
1230 * \endrst
1231 *
1232 * @param GPIOx GPIO instance.
1233 * @param pin_mask This parameter can be a combination of the following values:
1234 * @arg @ref LL_GPIO_PIN_0
1235 * @arg @ref LL_GPIO_PIN_1
1236 * @arg @ref LL_GPIO_PIN_2
1237 * @arg @ref LL_GPIO_PIN_3
1238 * @arg @ref LL_GPIO_PIN_4
1239 * @arg @ref LL_GPIO_PIN_5
1240 * @arg @ref LL_GPIO_PIN_6
1241 * @arg @ref LL_GPIO_PIN_7
1242 * @arg @ref LL_GPIO_PIN_8
1243 * @arg @ref LL_GPIO_PIN_9
1244 * @arg @ref LL_GPIO_PIN_10
1245 * @arg @ref LL_GPIO_PIN_11
1246 * @arg @ref LL_GPIO_PIN_12
1247 * @arg @ref LL_GPIO_PIN_13
1248 * @arg @ref LL_GPIO_PIN_14
1249 * @arg @ref LL_GPIO_PIN_15
1250 * @arg @ref LL_GPIO_PIN_ALL
1251 * @retval None
1252 */
1253 __STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1254 {
1255 WRITE_REG(GPIOx->INTENSET, pin_mask);
1256 }
1257
1258 /**
1259 * @brief Disable GPIO interrupts for pins in the range of 0 to 15.
1260 * @note @ref GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1261 *
1262 * \rst
1263 * +----------------------+-----------------------------------+
1264 * | Register | BitsName |
1265 * +======================+===================================+
1266 * | INTENCLR | INTENCLR |
1267 * +----------------------+-----------------------------------+
1268 * \endrst
1269 *
1270 * @param GPIOx GPIO instance.
1271 * @param pin_mask This parameter can be a combination of the following values:
1272 * @arg @ref LL_GPIO_PIN_0
1273 * @arg @ref LL_GPIO_PIN_1
1274 * @arg @ref LL_GPIO_PIN_2
1275 * @arg @ref LL_GPIO_PIN_3
1276 * @arg @ref LL_GPIO_PIN_4
1277 * @arg @ref LL_GPIO_PIN_5
1278 * @arg @ref LL_GPIO_PIN_6
1279 * @arg @ref LL_GPIO_PIN_7
1280 * @arg @ref LL_GPIO_PIN_8
1281 * @arg @ref LL_GPIO_PIN_9
1282 * @arg @ref LL_GPIO_PIN_10
1283 * @arg @ref LL_GPIO_PIN_11
1284 * @arg @ref LL_GPIO_PIN_12
1285 * @arg @ref LL_GPIO_PIN_13
1286 * @arg @ref LL_GPIO_PIN_14
1287 * @arg @ref LL_GPIO_PIN_15
1288 * @arg @ref LL_GPIO_PIN_ALL
1289 * @retval None
1290 */
1291 __STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1292 {
1293 WRITE_REG(GPIOx->INTENCLR, pin_mask);
1294 }
1295
1296 /**
1297 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1298 *
1299 * \rst
1300 * +----------------------+-----------------------------------+
1301 * | Register | BitsName |
1302 * +======================+===================================+
1303 * | INTENSET | INTENSET |
1304 * +----------------------+-----------------------------------+
1305 * \endrst
1306 *
1307 * @param GPIOx GPIO instance.
1308 * @param pin_mask This parameter can be a combination of the following values:
1309 * @arg @ref LL_GPIO_PIN_0
1310 * @arg @ref LL_GPIO_PIN_1
1311 * @arg @ref LL_GPIO_PIN_2
1312 * @arg @ref LL_GPIO_PIN_3
1313 * @arg @ref LL_GPIO_PIN_4
1314 * @arg @ref LL_GPIO_PIN_5
1315 * @arg @ref LL_GPIO_PIN_6
1316 * @arg @ref LL_GPIO_PIN_7
1317 * @arg @ref LL_GPIO_PIN_8
1318 * @arg @ref LL_GPIO_PIN_9
1319 * @arg @ref LL_GPIO_PIN_10
1320 * @arg @ref LL_GPIO_PIN_11
1321 * @arg @ref LL_GPIO_PIN_12
1322 * @arg @ref LL_GPIO_PIN_13
1323 * @arg @ref LL_GPIO_PIN_14
1324 * @arg @ref LL_GPIO_PIN_15
1325 * @arg @ref LL_GPIO_PIN_ALL
1326 * @retval State of bit (1 or 0).
1327 */
1328 __STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1329 {
1330 return (READ_BITS(GPIOx->INTENSET, pin_mask) == (pin_mask));
1331 }
1332
1333 /** @} */
1334
1335 /** @defgroup GPIO_LL_EF_Flag_Management Flag_Management
1336 * @{
1337 */
1338
1339 /**
1340 * @brief Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15
1341 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1342 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1343 *
1344 * \rst
1345 * +----------------------+-----------------------------------+
1346 * | Register | BitsName |
1347 * +======================+===================================+
1348 * | INTSTATUS | INTSTATUS |
1349 * +----------------------+-----------------------------------+
1350 * \endrst
1351 *
1352 * @param GPIOx GPIO instance.
1353 * @param pin_mask This parameter can be a combination of the following values:
1354 * @arg @ref LL_GPIO_PIN_0
1355 * @arg @ref LL_GPIO_PIN_1
1356 * @arg @ref LL_GPIO_PIN_2
1357 * @arg @ref LL_GPIO_PIN_3
1358 * @arg @ref LL_GPIO_PIN_4
1359 * @arg @ref LL_GPIO_PIN_5
1360 * @arg @ref LL_GPIO_PIN_6
1361 * @arg @ref LL_GPIO_PIN_7
1362 * @arg @ref LL_GPIO_PIN_8
1363 * @arg @ref LL_GPIO_PIN_9
1364 * @arg @ref LL_GPIO_PIN_10
1365 * @arg @ref LL_GPIO_PIN_11
1366 * @arg @ref LL_GPIO_PIN_12
1367 * @arg @ref LL_GPIO_PIN_13
1368 * @arg @ref LL_GPIO_PIN_14
1369 * @arg @ref LL_GPIO_PIN_15
1370 * @arg @ref LL_GPIO_PIN_ALL
1371 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1372 */
1373 __STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1374 {
1375 return (uint32_t)(READ_BITS(GPIOx->INTSTAT, pin_mask));
1376 }
1377
1378 /**
1379 * @brief Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
1380 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1381 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1382 *
1383 * \rst
1384 * +----------------------+-----------------------------------+
1385 * | Register | BitsName |
1386 * +======================+===================================+
1387 * | INTSTATUS | INTSTATUS |
1388 * +----------------------+-----------------------------------+
1389 * \endrst
1390 *
1391 * @param GPIOx GPIO instance.
1392 * @param pin_mask This parameter can be a combination of the following values:
1393 * @arg @ref LL_GPIO_PIN_0
1394 * @arg @ref LL_GPIO_PIN_1
1395 * @arg @ref LL_GPIO_PIN_2
1396 * @arg @ref LL_GPIO_PIN_3
1397 * @arg @ref LL_GPIO_PIN_4
1398 * @arg @ref LL_GPIO_PIN_5
1399 * @arg @ref LL_GPIO_PIN_6
1400 * @arg @ref LL_GPIO_PIN_7
1401 * @arg @ref LL_GPIO_PIN_8
1402 * @arg @ref LL_GPIO_PIN_9
1403 * @arg @ref LL_GPIO_PIN_10
1404 * @arg @ref LL_GPIO_PIN_11
1405 * @arg @ref LL_GPIO_PIN_12
1406 * @arg @ref LL_GPIO_PIN_13
1407 * @arg @ref LL_GPIO_PIN_14
1408 * @arg @ref LL_GPIO_PIN_15
1409 * @arg @ref LL_GPIO_PIN_ALL
1410 * @retval State of bit (1 or 0).
1411 */
1412 __STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1413 {
1414 return (READ_BITS(GPIOx->INTSTAT, pin_mask) == pin_mask);
1415 }
1416
1417 /**
1418 * @brief Clear Interrupt Status flag for pins in the range of 0 to 15.
1419 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1420 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1421 *
1422 * \rst
1423 * +----------------------+-----------------------------------+
1424 * | Register | BitsName |
1425 * +======================+===================================+
1426 * | INTSTATUS | INTSTATUS |
1427 * +----------------------+-----------------------------------+
1428 * \endrst
1429 *
1430 * @param GPIOx GPIO instance.
1431 * @param pin_mask This parameter can be a combination of the following values:
1432 * @arg @ref LL_GPIO_PIN_0
1433 * @arg @ref LL_GPIO_PIN_1
1434 * @arg @ref LL_GPIO_PIN_2
1435 * @arg @ref LL_GPIO_PIN_3
1436 * @arg @ref LL_GPIO_PIN_4
1437 * @arg @ref LL_GPIO_PIN_5
1438 * @arg @ref LL_GPIO_PIN_6
1439 * @arg @ref LL_GPIO_PIN_7
1440 * @arg @ref LL_GPIO_PIN_8
1441 * @arg @ref LL_GPIO_PIN_9
1442 * @arg @ref LL_GPIO_PIN_10
1443 * @arg @ref LL_GPIO_PIN_11
1444 * @arg @ref LL_GPIO_PIN_12
1445 * @arg @ref LL_GPIO_PIN_13
1446 * @arg @ref LL_GPIO_PIN_14
1447 * @arg @ref LL_GPIO_PIN_15
1448 * @arg @ref LL_GPIO_PIN_ALL
1449 * @retval None
1450 */
1451 __STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
1452 {
1453 WRITE_REG(GPIOx->INTSTAT, pin_mask);
1454 }
1455
1456 /** @} */
1457
1458 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
1459 * @{
1460 */
1461
1462 /**
1463 * @brief De-initialize GPIO registers (Registers restored to their default values).
1464 * @param GPIOx GPIO instance.
1465 * @retval An error_status_t enumeration value:
1466 * - SUCCESS: GPIO registers are de-initialized
1467 * - ERROR: GPIO registers are not de-initialized
1468 */
1469 error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx);
1470
1471 /**
1472 * @brief Initialize GPIO registers according to the specified
1473 * parameters in p_gpio_init.
1474 * @param GPIOx GPIO instance.
1475 * @param p_gpio_init Pointer to a ll_gpio_init_t structure that contains the configuration
1476 * information for the specified GPIO peripheral.
1477 * @retval An error_status_t enumeration value:
1478 * - SUCCESS: GPIO registers are initialized according to p_gpio_init content
1479 * - ERROR: Problem occurred during GPIO Registers initialization
1480 */
1481 error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init);
1482
1483 /**
1484 * @brief Set each field of a @ref ll_gpio_init_t type structure to default value.
1485 * @param p_gpio_init Pointer to a @ref ll_gpio_init_t structure
1486 * whose fields will be set to default values.
1487 * @retval None
1488 */
1489 void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init);
1490
1491 /** @} */
1492
1493 /** @} */
1494
1495 #endif /* defined (GPIO0) || defined (GPIO1) */
1496
1497 #ifdef __cplusplus
1498 }
1499 #endif
1500
1501 #endif /* __GR55xx_LL_GPIO_H__ */
1502
1503 /** @} */
1504
1505 /** @} */
1506
1507 /** @} */
ll_gpio_read_input_port
__STATIC_INLINE uint32_t ll_gpio_read_input_port(gpio_regs_t *GPIOx)
Return full input data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:653
_ll_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_gpio.h:78
ll_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:542
ll_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if low level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1214
LL_GPIO_GET_RESISTOR_POS
#define LL_GPIO_GET_RESISTOR_POS(__GPIOx__)
Get the starting position of the specified GPIO instance in related pull-up/pull-down register.
Definition: gr55xx_ll_gpio.h:241
LL_GPIO_PULL_NO
#define LL_GPIO_PULL_NO
Definition: gr55xx_ll_gpio.h:149
ll_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_output_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:766
ll_gpio_enable_high_trigger
__STATIC_INLINE void ll_gpio_enable_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO High Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1094
ll_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_gpio_is_enabled_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_gpio.h:1328
_ll_gpio_init
LL GPIO init configuration definition.
Definition: gr55xx_ll_gpio.h:77
ll_gpio_init_t
struct _ll_gpio_init ll_gpio_init_t
LL GPIO init configuration definition.
ll_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if rising edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1054
ll_gpio_set_mux_pin_8_15
__STATIC_INLINE void ll_gpio_set_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:585
LL_GPIO_PULL_UP
#define LL_GPIO_PULL_UP
Definition: gr55xx_ll_gpio.h:150
_ll_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_gpio.h:91
_ll_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_gpio.h:97
ll_gpio_read_output_port
__STATIC_INLINE uint32_t ll_gpio_read_output_port(gpio_regs_t *GPIOx)
Return full output data register value for a dedicated port.
Definition: gr55xx_ll_gpio.h:729
ll_gpio_set_output_pin
__STATIC_INLINE void ll_gpio_set_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to high level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:803
ll_gpio_enable_rising_trigger
__STATIC_INLINE void ll_gpio_enable_rising_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Rising Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1013
ll_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_gpio_is_active_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Indicates if the GPIO Interrupt Flag is set or not for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1412
ll_gpio_enable_it
__STATIC_INLINE void ll_gpio_enable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1253
ll_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_gpio_get_pin_mode(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio mode for a dedicated pin on dedicated port.
Definition: gr55xx_ll_gpio.h:373
ll_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_gpio_get_pin_pull(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:458
LL_GPIO_GET_REG_MUX_CTRL_0_7
#define LL_GPIO_GET_REG_MUX_CTRL_0_7(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:249
ll_gpio_reset_output_pin
__STATIC_INLINE void ll_gpio_reset_output_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Set several pins to low level on dedicated gpio port.
Definition: gr55xx_ll_gpio.h:846
ll_gpio_deinit
error_status_t ll_gpio_deinit(gpio_regs_t *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
LL_GPIO_PULL_DOWN
#define LL_GPIO_PULL_DOWN
Definition: gr55xx_ll_gpio.h:151
ll_gpio_toggle_pin
__STATIC_INLINE void ll_gpio_toggle_pin(gpio_regs_t *GPIOx, uint32_t pin_mask)
Toggle data value for several pin of dedicated port.
Definition: gr55xx_ll_gpio.h:888
ll_gpio_write_output_port
__STATIC_INLINE void ll_gpio_write_output_port(gpio_regs_t *GPIOx, uint32_t port_value)
Write output data register for the port.
Definition: gr55xx_ll_gpio.h:710
ll_gpio_init
error_status_t ll_gpio_init(gpio_regs_t *GPIOx, ll_gpio_init_t *p_gpio_init)
Initialize GPIO registers according to the specified parameters in p_gpio_init.
LL_GPIO_MODE_INPUT
#define LL_GPIO_MODE_INPUT
Definition: gr55xx_ll_gpio.h:141
ll_gpio_enable_low_trigger
__STATIC_INLINE void ll_gpio_enable_low_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Low Level Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1174
_ll_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_gpio.h:81
ll_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_gpio_set_mux_pin_0_7(gpio_regs_t *GPIOx, uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_gpio.h:502
LL_GPIO_MODE_OUTPUT
#define LL_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_gpio.h:142
ll_gpio_set_pin_mode
__STATIC_INLINE void ll_gpio_set_pin_mode(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t mode)
Set several pins to input/output mode on dedicated port.
Definition: gr55xx_ll_gpio.h:326
ll_gpio_get_mux_pin_8_15
__STATIC_INLINE uint32_t ll_gpio_get_mux_pin_8_15(gpio_regs_t *GPIOx, uint32_t pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
Definition: gr55xx_ll_gpio.h:626
ll_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_gpio_is_input_pin_set(gpio_regs_t *GPIOx, uint32_t pin_mask)
Return if input data level for several pins of dedicated port is high or low.
Definition: gr55xx_ll_gpio.h:690
ll_gpio_struct_init
void ll_gpio_struct_init(ll_gpio_init_t *p_gpio_init)
Set each field of a ll_gpio_init_t type structure to default value.
_ll_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_gpio.h:86
ll_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_gpio_read_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Read GPIO Interrupt Combination Flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1373
ll_gpio_enable_falling_trigger
__STATIC_INLINE void ll_gpio_enable_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Enable GPIO Falling Edge Trigger for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:933
ll_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_high_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if high level trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1134
LL_GPIO_GET_REG_MUX_CTRL_8_15
#define LL_GPIO_GET_REG_MUX_CTRL_8_15(__GPIOx__)
Get mux control register address of specified GPIO instance.
Definition: gr55xx_ll_gpio.h:258
ll_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_gpio_is_enabled_falling_trigger(gpio_regs_t *GPIOx, uint32_t pin_mask)
Check if falling edge trigger is enabled for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:973
ll_gpio_disable_it
__STATIC_INLINE void ll_gpio_disable_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Disable GPIO interrupts for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1291
ll_gpio_set_pin_pull
__STATIC_INLINE void ll_gpio_set_pin_pull(gpio_regs_t *GPIOx, uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
Definition: gr55xx_ll_gpio.h:414
ll_gpio_clear_flag_it
__STATIC_INLINE void ll_gpio_clear_flag_it(gpio_regs_t *GPIOx, uint32_t pin_mask)
Clear Interrupt Status flag for pins in the range of 0 to 15.
Definition: gr55xx_ll_gpio.h:1451