gr55xx_ll_aon_gpio.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61
62 #if defined(AON)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init
77 {
78 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
79 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
80
81 uint32_t mode; /**< Specifies the operating mode for the selected pins.
82 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
83
84 AON_GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_mode(). */
85
86 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
87 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
88
89 AON_GPIO HW configuration can be modified afterwards using unitary function @ref ll_aon_gpio_set_pin_pull().*/
90
91 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
92 This parameter can be a value of @ref AON_GPIO_LL_EC_MUX.
93
94 GPIO HW AON_GPIO_InitStructuration can be modified afterwards using unitary function
95 @ref ll_aon_gpio_set_mux_pin_0_7(). */
96
97 uint32_t trigger; /**< Specifies the trigger signal active edge.
98 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
99 } ll_aon_gpio_init_t;
100
101 /** @} */
102
103 /** @} */
104
105 /**
106 * @defgroup AON_GPIO_LL_MACRO Defines
107 * @{
108 */
109
110 /* Exported constants --------------------------------------------------------*/
111 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
112 * @{
113 */
114
115 /** @defgroup AON_GPIO_LL_EC_PIN PIN
116 * @{
117 */
118 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
119 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
120 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
121 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
122 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
123 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
124 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
125 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
126 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
127 /** @} */
128
129 /** @defgroup AON_GPIO_LL_EC_MODE Mode
130 * @{
131 */
132 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U) /**< Select input mode */
133 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /**< Select output mode */
134 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U) /**< Select mux peripheral mode */
135 /** @} */
136
137 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
138 * @{
139 */
140 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N /**< Select I/O no pull */
141 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP /**< Select I/O pull up */
142 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U) /**< Select I/O pull down */
143 /** @} */
144
145 /** @defgroup AON_GPIO_LL_EC_MUX Alternate Function
146 * @{
147 */
148 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
149 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
150 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
151 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
152 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
153 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
154 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
155 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
156 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
157 /** @} */
158
159
160 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
161 * @{
162 */
163 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
164 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
165 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
166 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
167 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
168 /** @} */
169
170 /** @} */
171
172 /* Exported macro ------------------------------------------------------------*/
173 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
174 * @{
175 */
176
177 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
178 * @{
179 */
180
181 /**
182 * @brief Write a value in AON_GPIO register
183 * @param __instance__ AON_GPIO instance
184 * @param __REG__ Register to be written
185 * @param __VALUE__ Value to be written in the register
186 * @retval None
187 */
188 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
189
190 /**
191 * @brief Read a value in AON_GPIO register
192 * @param __instance__ AON_GPIO instance
193 * @param __REG__ Register to be read
194 * @retval Register value
195 */
196 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
197
198 /** @} */
199
200 /** @} */
201
202 /* Private types -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private constants ---------------------------------------------------------*/
205 /* Private macros ------------------------------------------------------------*/
206 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
207 * @{
208 */
209
210 /** @defgroup AON_GPIO_LL_PM_RESISTOR Resistor Enable
211 * @{
212 */
213 #define LL_AON_GPIO_RE_N_Pos AON_PAD_CTL0_GPO_RE_N_Pos /**< Resistor Enable bits position */
214 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
215 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk /**< Resistor Enable bits */
216 /** @} */
217
218 /** @defgroup AON_GPIO_LL_PM_RESISTOR_TYPE Resistor Type
219 * @{
220 */
221 #define LL_AON_GPIO_RTYP_Pos AON_PAD_CTL0_GPO_RTYPE_Pos /**< Resistor Type bits position */
222 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
223 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk /**< Resistor Type bits */
224 /** @} */
225
226 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
227 * @{
228 */
229
230 /**
231 * @brief LL AON_GPIO InitStrcut default configuartion
232 */
233 #define LL_AON_GPIO_DEFAULT_CONFIG \
234 { \
235 .pin = LL_AON_GPIO_PIN_ALL, \
236 .mode = LL_AON_GPIO_MODE_INPUT, \
237 .pull = LL_AON_GPIO_PULL_DOWN, \
238 .mux = LL_AON_GPIO_MUX_7, \
239 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
240 }
241 /** @} */
242
243 /** @} */
244
245 /** @} */
246
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
249 * @{
250 */
251
252 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
253 * @{
254 */
255
256 /**
257 * @brief Set several AON_GPIO pins to input/output mode.
258 *
259 * \rst
260 * +----------------------+-----------------------------------+
261 * | Register | BitsName |
262 * +======================+===================================+
263 * | AON_PAD_CTL1 | AON_GPO_OE_N |
264 * +----------------------+-----------------------------------+
265 * \endrst
266 *
267 * @param pin_mask This parameter can be a combination of the following values:
268 * @arg @ref LL_AON_GPIO_PIN_0
269 * @arg @ref LL_AON_GPIO_PIN_1
270 * @arg @ref LL_AON_GPIO_PIN_2
271 * @arg @ref LL_AON_GPIO_PIN_3
272 * @arg @ref LL_AON_GPIO_PIN_4
273 * @arg @ref LL_AON_GPIO_PIN_5
274 * @arg @ref LL_AON_GPIO_PIN_6
275 * @arg @ref LL_AON_GPIO_PIN_7
276 * @arg @ref LL_AON_GPIO_PIN_ALL
277 * @param mode This parameter can be one of the following values:
278 * @arg @ref LL_AON_GPIO_MODE_INPUT
279 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
280 * @retval None
281 */
282 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
283 {
284 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
285 GLOBAL_EXCEPTION_DISABLE();
286 MODIFY_REG(AON->AON_PAD_CTL1, pin_mask, (mode == LL_AON_GPIO_MODE_INPUT) ? pin_mask : 0);
287 GLOBAL_EXCEPTION_ENABLE();
288 }
289
290 /**
291 * @brief Return gpio mode for a AON_GPIO pin.
292 * @note I/O mode can be Input mode. General purpose output.
293 * @note Warning: only one pin can be passed as parameter.
294 *
295 * \rst
296 * +----------------------+-----------------------------------+
297 * | Register | BitsName |
298 * +======================+===================================+
299 * | AON_PAD_CTL1 | AON_GPO_OE_N |
300 * +----------------------+-----------------------------------+
301 * \endrst
302 *
303 * @param pin This parameter can be one of the following values:
304 * @arg @ref LL_AON_GPIO_PIN_0
305 * @arg @ref LL_AON_GPIO_PIN_1
306 * @arg @ref LL_AON_GPIO_PIN_2
307 * @arg @ref LL_AON_GPIO_PIN_3
308 * @arg @ref LL_AON_GPIO_PIN_4
309 * @arg @ref LL_AON_GPIO_PIN_5
310 * @arg @ref LL_AON_GPIO_PIN_6
311 * @arg @ref LL_AON_GPIO_PIN_7
312 * @retval Returned value can be one of the following values:
313 * @arg @ref LL_AON_GPIO_MODE_INPUT
314 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
315 */
316 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
317 {
318 pin = (pin << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
319 return ((uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin) == LL_AON_GPIO_MODE_INPUT) ?
320 LL_AON_GPIO_MODE_OUTPUT : LL_AON_GPIO_MODE_INPUT);
321 }
322
323 /**
324 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
325 * @note Warning: only one pin can be passed as parameter.
326 *
327 * \rst
328 * +----------------------+-----------------------------------+
329 * | Register | BitsName |
330 * +======================+===================================+
331 * | AON_PAD_CTL0 | GPO_RE_N |
332 * +----------------------+-----------------------------------+
333 * \endrst
334 * AON_PAD_CTL0 | GPO_RTYPE
335 *
336 * @param pin_mask This parameter can be a combination of the following values:
337 * @arg @ref LL_AON_GPIO_PIN_0
338 * @arg @ref LL_AON_GPIO_PIN_1
339 * @arg @ref LL_AON_GPIO_PIN_2
340 * @arg @ref LL_AON_GPIO_PIN_3
341 * @arg @ref LL_AON_GPIO_PIN_4
342 * @arg @ref LL_AON_GPIO_PIN_5
343 * @arg @ref LL_AON_GPIO_PIN_6
344 * @arg @ref LL_AON_GPIO_PIN_7
345 * @arg @ref LL_AON_GPIO_PIN_ALL
346 * @param pull This parameter can be one of the following values:
347 * @arg @ref LL_AON_GPIO_PULL_NO
348 * @arg @ref LL_AON_GPIO_PULL_UP
349 * @arg @ref LL_AON_GPIO_PULL_DOWN
350 * @retval None
351 */
352 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
353 {
354 uint32_t RTypeMask = (pin_mask << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
355 uint32_t REnMask = (pin_mask << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
356 uint32_t RType = (pull == LL_AON_GPIO_PULL_UP) ? RTypeMask : 0x0000U;
357 uint32_t REn = (pull == LL_AON_GPIO_PULL_NO) ? REnMask : 0x0000U;
358 MODIFY_REG(AON->AON_PAD_CTL0, REnMask | RTypeMask, REn | RType);
359 }
360
361 /**
362 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
363 * @note Warning: only one pin can be passed as parameter.
364 *
365 * \rst
366 * +----------------------+-----------------------------------+
367 * | Register | BitsName |
368 * +======================+===================================+
369 * | AON_PAD_CTL0 | GPO_RE_N |
370 * +----------------------+-----------------------------------+
371 * \endrst
372 * AON_PAD_CTL0 | GPO_RTYPE
373 *
374 * @param pin This parameter can be one of the following values:
375 * @arg @ref LL_AON_GPIO_PIN_0
376 * @arg @ref LL_AON_GPIO_PIN_1
377 * @arg @ref LL_AON_GPIO_PIN_2
378 * @arg @ref LL_AON_GPIO_PIN_3
379 * @arg @ref LL_AON_GPIO_PIN_4
380 * @arg @ref LL_AON_GPIO_PIN_5
381 * @arg @ref LL_AON_GPIO_PIN_6
382 * @arg @ref LL_AON_GPIO_PIN_7
383 * @retval Returned value can be one of the following values:
384 * @arg @ref LL_AON_GPIO_PULL_NO
385 * @arg @ref LL_AON_GPIO_PULL_UP
386 * @arg @ref LL_AON_GPIO_PULL_DOWN
387 */
388 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
389 {
390 uint32_t RTypeMask = (pin << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
391 uint32_t REnMask = (pin << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
392 //return (READ_BITS(AON->AON_PAD_CTL0, REnMask | RTypeMask) >> POSITION_VAL(Pin));
393 return ((READ_BITS(AON->AON_PAD_CTL0, REnMask) != RESET) ? LL_AON_GPIO_PULL_NO :
394 ((READ_BITS(AON->AON_PAD_CTL0, RTypeMask) != RESET) ? LL_AON_GPIO_PULL_UP : LL_AON_GPIO_PULL_DOWN));
395 }
396
397 /**
398 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
399 * @note Possible values are from AF0 to AF15 depending on target.
400 * @note Warning: only one pin can be passed as parameter.
401 *
402 * \rst
403 * +----------------------+-----------------------------------+
404 * | Register | BitsName |
405 * +======================+===================================+
406 * | AON_PAD_MUX_CTRL | CTRL0_7 |
407 * +----------------------+-----------------------------------+
408 * \endrst
409 * AON_PAD_CTL_0 | MCU_OVR
410 *
411 * @param pin This parameter can be one of the following values:
412 * @arg @ref LL_AON_GPIO_PIN_0
413 * @arg @ref LL_AON_GPIO_PIN_1
414 * @arg @ref LL_AON_GPIO_PIN_2
415 * @arg @ref LL_AON_GPIO_PIN_3
416 * @arg @ref LL_AON_GPIO_PIN_4
417 * @arg @ref LL_AON_GPIO_PIN_5
418 * @arg @ref LL_AON_GPIO_PIN_6
419 * @arg @ref LL_AON_GPIO_PIN_7
420 * @param mux This parameter can be one of the following values:
421 * @arg @ref LL_AON_GPIO_MUX_0
422 * @arg @ref LL_AON_GPIO_MUX_1
423 * @arg @ref LL_AON_GPIO_MUX_2
424 * @arg @ref LL_AON_GPIO_MUX_3
425 * @arg @ref LL_AON_GPIO_MUX_4
426 * @arg @ref LL_AON_GPIO_MUX_5
427 * @arg @ref LL_AON_GPIO_MUX_6
428 * @arg @ref LL_AON_GPIO_MUX_7
429 * @arg @ref LL_AON_GPIO_MUX_8
430 * @retval None
431 */
432 __STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
433 {
434 uint32_t pos = POSITION_VAL(pin) << 2;
435 if(LL_AON_GPIO_MUX_7 == mux)
436 {
437 CLEAR_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
438 }
439 else
440 {
441 MODIFY_REG(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
442 SET_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
443 }
444 }
445
446 /**
447 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
448 *
449 * \rst
450 * +----------------------+-----------------------------------+
451 * | Register | BitsName |
452 * +======================+===================================+
453 * | AON_PAD_MUX_CTRL | CTRL0_7 |
454 * +----------------------+-----------------------------------+
455 * \endrst
456 * AON_PAD_CTL_0 | MCU_OVR
457 *
458 * @param pin This parameter can be one of the following values:
459 * @arg @ref LL_AON_GPIO_PIN_0
460 * @arg @ref LL_AON_GPIO_PIN_1
461 * @arg @ref LL_AON_GPIO_PIN_2
462 * @arg @ref LL_AON_GPIO_PIN_3
463 * @arg @ref LL_AON_GPIO_PIN_4
464 * @arg @ref LL_AON_GPIO_PIN_5
465 * @arg @ref LL_AON_GPIO_PIN_6
466 * @arg @ref LL_AON_GPIO_PIN_7
467 * @retval Returned value can be one of the following values:
468 * @arg @ref LL_AON_GPIO_MUX_0
469 * @arg @ref LL_AON_GPIO_MUX_1
470 * @arg @ref LL_AON_GPIO_MUX_2
471 * @arg @ref LL_AON_GPIO_MUX_3
472 * @arg @ref LL_AON_GPIO_MUX_4
473 * @arg @ref LL_AON_GPIO_MUX_5
474 * @arg @ref LL_AON_GPIO_MUX_6
475 * @arg @ref LL_AON_GPIO_MUX_7
476 * @arg @ref LL_AON_GPIO_MUX_8
477 */
478 __STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
479 {
480 if(READ_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos))
481 {
482 uint32_t pos = POSITION_VAL(pin) << 2;
483 return (READ_BITS(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
484 }
485 else
486 {
487 return LL_AON_GPIO_MUX_7;
488 }
489 }
490
491 /**
492 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
493 *
494 * \rst
495 * +----------------------+-----------------------------------+
496 * | Register | BitsName |
497 * +======================+===================================+
498 * | PWR_RET01 | XO_2MHZ_ENA |
499 * +----------------------+-----------------------------------+
500 * \endrst
501 *
502 * @retval None
503 */
504 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
505 {
506 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
507 }
508
509 /**
510 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
511 *
512 * \rst
513 * +----------------------+-----------------------------------+
514 * | Register | BitsName |
515 * +======================+===================================+
516 * | PWR_RET01 | XO_2MHZ_ENA |
517 * +----------------------+-----------------------------------+
518 * \endrst
519 *
520 * @retval None
521 */
522 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
523 {
524 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
525 }
526
527 /**
528 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
529 *
530 * \rst
531 * +----------------------+-----------------------------------+
532 * | Register | BitsName |
533 * +======================+===================================+
534 * | PWR_RET01 | XO_2MHZ_ENA |
535 * +----------------------+-----------------------------------+
536 * \endrst
537 *
538 * @retval None
539 */
540 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
541 {
542 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA) == AON_PWR_REG01_XO_2MHZ_ENA);
543 }
544
545 /** @} */
546
547 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
548 * @{
549 */
550
551 /**
552 * @brief Return full input data register value of AON_GPIO.
553 *
554 * \rst
555 * +----------------------+-----------------------------------+
556 * | Register | BitsName |
557 * +======================+===================================+
558 * | AON_PAD_CTL1 | O_AON_GPI |
559 * +----------------------+-----------------------------------+
560 * \endrst
561 *
562 * @retval Input data register value of port
563 */
564 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
565 {
566 return (uint32_t)(READ_BITS(GPIO2->DATA, GPIO_DATA));
567 }
568
569 /**
570 * @brief Return if input data level of several AON_GPIO pins is high or low.
571 *
572 * \rst
573 * +----------------------+-----------------------------------+
574 * | Register | BitsName |
575 * +======================+===================================+
576 * | AON_PAD_CTL1 | O_AON_GPI |
577 * +----------------------+-----------------------------------+
578 * \endrst
579 *
580 * @param pin_mask This parameter can be a combination of the following values:
581 * @arg @ref LL_AON_GPIO_PIN_0
582 * @arg @ref LL_AON_GPIO_PIN_1
583 * @arg @ref LL_AON_GPIO_PIN_2
584 * @arg @ref LL_AON_GPIO_PIN_3
585 * @arg @ref LL_AON_GPIO_PIN_4
586 * @arg @ref LL_AON_GPIO_PIN_5
587 * @arg @ref LL_AON_GPIO_PIN_6
588 * @arg @ref LL_AON_GPIO_PIN_7
589 * @arg @ref LL_AON_GPIO_PIN_ALL
590 * @retval State of bit (1 or 0).
591 */
592 __STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
593 {
594 return (uint32_t)(READ_BITS(GPIO2->DATA, pin_mask) == pin_mask);
595 }
596
597 /**
598 * @brief Write output data register of AON_GPIO.
599 *
600 * \rst
601 * +----------------------+-----------------------------------+
602 * | Register | BitsName |
603 * +======================+===================================+
604 * | AON_PAD_CTL1 | AON_GPO |
605 * +----------------------+-----------------------------------+
606 * \endrst
607 *
608 * @param port_value Level value for each pin of the port
609 * @retval None
610 */
611 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
612 {
613 GLOBAL_EXCEPTION_DISABLE();
614 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO, (port_value << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
615 GLOBAL_EXCEPTION_ENABLE();
616 }
617
618 /**
619 * @brief Return full output data register value of AON_GPIO.
620 *
621 * \rst
622 * +----------------------+-----------------------------------+
623 * | Register | BitsName |
624 * +======================+===================================+
625 * | AON_PAD_CTL1 | AON_GPO |
626 * +----------------------+-----------------------------------+
627 * \endrst
628 *
629 * @retval Output data register value of port
630 */
631 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
632 {
633 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO) >> AON_PAD_CTL1_AON_GPO_Pos);
634 }
635
636 /**
637 * @brief Return if input data level of several AON_GPIO pins is high or low.
638 *
639 * \rst
640 * +----------------------+-----------------------------------+
641 * | Register | BitsName |
642 * +======================+===================================+
643 * | AON_PAD_CTL1 | AON_GPO |
644 * +----------------------+-----------------------------------+
645 * \endrst
646 *
647 * @param pin_mask This parameter can be a combination of the following values:
648 * @arg @ref LL_AON_GPIO_PIN_0
649 * @arg @ref LL_AON_GPIO_PIN_1
650 * @arg @ref LL_AON_GPIO_PIN_2
651 * @arg @ref LL_AON_GPIO_PIN_3
652 * @arg @ref LL_AON_GPIO_PIN_4
653 * @arg @ref LL_AON_GPIO_PIN_5
654 * @arg @ref LL_AON_GPIO_PIN_6
655 * @arg @ref LL_AON_GPIO_PIN_7
656 * @arg @ref LL_AON_GPIO_PIN_ALL
657 * @retval State of bit (1 or 0).
658 */
659 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
660 {
661 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO;
662 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin_mask) == pin_mask);
663 }
664
665 /**
666 * @brief Set specified AON_GPIO pins to high level
667 *
668 * \rst
669 * +----------------------+-----------------------------------+
670 * | Register | BitsName |
671 * +======================+===================================+
672 * | AON_PAD_CTL1 | AON_GPO |
673 * +----------------------+-----------------------------------+
674 * \endrst
675 *
676 * @param pin_mask This parameter can be a combination of the following values:
677 * @arg @ref LL_AON_GPIO_PIN_0
678 * @arg @ref LL_AON_GPIO_PIN_1
679 * @arg @ref LL_AON_GPIO_PIN_2
680 * @arg @ref LL_AON_GPIO_PIN_3
681 * @arg @ref LL_AON_GPIO_PIN_4
682 * @arg @ref LL_AON_GPIO_PIN_5
683 * @arg @ref LL_AON_GPIO_PIN_6
684 * @arg @ref LL_AON_GPIO_PIN_7
685 * @arg @ref LL_AON_GPIO_PIN_ALL
686 * @retval None
687 */
688 __STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
689 {
690 GLOBAL_EXCEPTION_DISABLE();
691 SET_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
692 GLOBAL_EXCEPTION_ENABLE();
693 }
694
695 /**
696 * @brief Set specified AON_GPIO pins to low level.
697 *
698 * \rst
699 * +----------------------+-----------------------------------+
700 * | Register | BitsName |
701 * +======================+===================================+
702 * | AON_PAD_CTL1 | AON_GPO |
703 * +----------------------+-----------------------------------+
704 * \endrst
705 *
706 * @param pin_mask This parameter can be a combination of the following values:
707 * @arg @ref LL_AON_GPIO_PIN_0
708 * @arg @ref LL_AON_GPIO_PIN_1
709 * @arg @ref LL_AON_GPIO_PIN_2
710 * @arg @ref LL_AON_GPIO_PIN_3
711 * @arg @ref LL_AON_GPIO_PIN_4
712 * @arg @ref LL_AON_GPIO_PIN_5
713 * @arg @ref LL_AON_GPIO_PIN_6
714 * @arg @ref LL_AON_GPIO_PIN_7
715 * @arg @ref LL_AON_GPIO_PIN_ALL
716 * @retval None
717 */
718 __STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
719 {
720 GLOBAL_EXCEPTION_DISABLE();
721 CLEAR_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
722 GLOBAL_EXCEPTION_ENABLE();
723 }
724
725 /**
726 * @brief Toggle data value of specified AON_GPIO pins.
727 *
728 * \rst
729 * +----------------------+-----------------------------------+
730 * | Register | BitsName |
731 * +======================+===================================+
732 * | AON_PAD_CTL1 | AON_GPO |
733 * +----------------------+-----------------------------------+
734 * \endrst
735 *
736 * @param pin_mask This parameter can be a combination of the following values:
737 * @arg @ref LL_AON_GPIO_PIN_0
738 * @arg @ref LL_AON_GPIO_PIN_1
739 * @arg @ref LL_AON_GPIO_PIN_2
740 * @arg @ref LL_AON_GPIO_PIN_3
741 * @arg @ref LL_AON_GPIO_PIN_4
742 * @arg @ref LL_AON_GPIO_PIN_5
743 * @arg @ref LL_AON_GPIO_PIN_6
744 * @arg @ref LL_AON_GPIO_PIN_7
745 * @arg @ref LL_AON_GPIO_PIN_ALL
746 * @retval None
747 */
748 __STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
749 {
750 GLOBAL_EXCEPTION_DISABLE();
751 WRITE_REG(AON->AON_PAD_CTL1, (READ_REG(AON->AON_PAD_CTL1) ^ ((pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO)));
752 GLOBAL_EXCEPTION_ENABLE();
753 }
754
755 /** @} */
756
757 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
758 * @{
759 */
760
761 /**
762 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
763 *
764 * \rst
765 * +----------------------+-----------------------------------+
766 * | Register | BitsName |
767 * +======================+===================================+
768 * | INTPOLCLR | INTPOLCLR |
769 * +----------------------+-----------------------------------+
770 * \endrst
771 * INTTYPESET | INTTYPESET
772 *
773 * @param pin_mask This parameter can be a combination of the following values:
774 * @arg @ref LL_AON_GPIO_PIN_0
775 * @arg @ref LL_AON_GPIO_PIN_1
776 * @arg @ref LL_AON_GPIO_PIN_2
777 * @arg @ref LL_AON_GPIO_PIN_3
778 * @arg @ref LL_AON_GPIO_PIN_4
779 * @arg @ref LL_AON_GPIO_PIN_5
780 * @arg @ref LL_AON_GPIO_PIN_6
781 * @arg @ref LL_AON_GPIO_PIN_7
782 * @arg @ref LL_AON_GPIO_PIN_ALL
783 * @retval None
784 */
785 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
786 {
787 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
788 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
789 }
790
791 /**
792 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
793 *
794 * \rst
795 * +----------------------+-----------------------------------+
796 * | Register | BitsName |
797 * +======================+===================================+
798 * | INTPOLCLR | INTPOLCLR |
799 * +----------------------+-----------------------------------+
800 * \endrst
801 * INTTYPESET | INTTYPESET
802 *
803 * @param pin_mask This parameter can be a combination of the following values:
804 * @arg @ref LL_AON_GPIO_PIN_0
805 * @arg @ref LL_AON_GPIO_PIN_1
806 * @arg @ref LL_AON_GPIO_PIN_2
807 * @arg @ref LL_AON_GPIO_PIN_3
808 * @arg @ref LL_AON_GPIO_PIN_4
809 * @arg @ref LL_AON_GPIO_PIN_5
810 * @arg @ref LL_AON_GPIO_PIN_6
811 * @arg @ref LL_AON_GPIO_PIN_7
812 * @arg @ref LL_AON_GPIO_PIN_ALL
813 * @retval State of bit (1 or 0).
814 */
815 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
816 {
817 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
818 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
819 }
820
821 /**
822 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
823 *
824 * \rst
825 * +----------------------+-----------------------------------+
826 * | Register | BitsName |
827 * +======================+===================================+
828 * | INTPOLSET | INTPOLSET |
829 * +----------------------+-----------------------------------+
830 * \endrst
831 * INTTYPESET | INTTYPESET
832 *
833 * @param pin_mask This parameter can be a combination of the following values:
834 * @arg @ref LL_AON_GPIO_PIN_0
835 * @arg @ref LL_AON_GPIO_PIN_1
836 * @arg @ref LL_AON_GPIO_PIN_2
837 * @arg @ref LL_AON_GPIO_PIN_3
838 * @arg @ref LL_AON_GPIO_PIN_4
839 * @arg @ref LL_AON_GPIO_PIN_5
840 * @arg @ref LL_AON_GPIO_PIN_6
841 * @arg @ref LL_AON_GPIO_PIN_7
842 * @arg @ref LL_AON_GPIO_PIN_ALL
843 * @retval None
844 */
845 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
846 {
847 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
848 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
849 }
850
851 /**
852 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
853 * @note Please check each device line mapping for AON_GPIO Line availability
854 *
855 * \rst
856 * +----------------------+-----------------------------------+
857 * | Register | BitsName |
858 * +======================+===================================+
859 * | INTPOLSET | INTPOLSET |
860 * +----------------------+-----------------------------------+
861 * \endrst
862 * INTTYPESET | INTTYPESET
863 *
864 * @param pin_mask This parameter can be a combination of the following values:
865 * @arg @ref LL_AON_GPIO_PIN_0
866 * @arg @ref LL_AON_GPIO_PIN_1
867 * @arg @ref LL_AON_GPIO_PIN_2
868 * @arg @ref LL_AON_GPIO_PIN_3
869 * @arg @ref LL_AON_GPIO_PIN_4
870 * @arg @ref LL_AON_GPIO_PIN_5
871 * @arg @ref LL_AON_GPIO_PIN_6
872 * @arg @ref LL_AON_GPIO_PIN_7
873 * @arg @ref LL_AON_GPIO_PIN_ALL
874 * @retval State of bit (1 or 0).
875 */
876 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
877 {
878 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
879 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
880 }
881
882 /**
883 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
884 *
885 * \rst
886 * +----------------------+-----------------------------------+
887 * | Register | BitsName |
888 * +======================+===================================+
889 * | INTPOLSET | INTPOLSET |
890 * +----------------------+-----------------------------------+
891 * \endrst
892 * INTTYPECLR | INTTYPECLR
893 *
894 * @param pin_mask This parameter can be a combination of the following values:
895 * @arg @ref LL_AON_GPIO_PIN_0
896 * @arg @ref LL_AON_GPIO_PIN_1
897 * @arg @ref LL_AON_GPIO_PIN_2
898 * @arg @ref LL_AON_GPIO_PIN_3
899 * @arg @ref LL_AON_GPIO_PIN_4
900 * @arg @ref LL_AON_GPIO_PIN_5
901 * @arg @ref LL_AON_GPIO_PIN_6
902 * @arg @ref LL_AON_GPIO_PIN_7
903 * @arg @ref LL_AON_GPIO_PIN_ALL
904 * @retval None
905 */
906 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
907 {
908 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
909 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
910 }
911
912 /**
913 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
914 *
915 * \rst
916 * +----------------------+-----------------------------------+
917 * | Register | BitsName |
918 * +======================+===================================+
919 * | INTPOLSET | INTPOLSET |
920 * +----------------------+-----------------------------------+
921 * \endrst
922 * INTTYPECLR | INTTYPECLR
923 *
924 * @param pin_mask This parameter can be a combination of the following values:
925 * @arg @ref LL_AON_GPIO_PIN_0
926 * @arg @ref LL_AON_GPIO_PIN_1
927 * @arg @ref LL_AON_GPIO_PIN_2
928 * @arg @ref LL_AON_GPIO_PIN_3
929 * @arg @ref LL_AON_GPIO_PIN_4
930 * @arg @ref LL_AON_GPIO_PIN_5
931 * @arg @ref LL_AON_GPIO_PIN_6
932 * @arg @ref LL_AON_GPIO_PIN_7
933 * @arg @ref LL_AON_GPIO_PIN_ALL
934 * @retval State of bit (1 or 0).
935 */
936 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
937 {
938 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
939 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
940 }
941
942 /**
943 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
944 *
945 * \rst
946 * +----------------------+-----------------------------------+
947 * | Register | BitsName |
948 * +======================+===================================+
949 * | INTPOLCLR | INTPOLCLR |
950 * +----------------------+-----------------------------------+
951 * \endrst
952 * INTTYPECLR | INTTYPECLR
953 *
954 * @param pin_mask This parameter can be a combination of the following values:
955 * @arg @ref LL_AON_GPIO_PIN_0
956 * @arg @ref LL_AON_GPIO_PIN_1
957 * @arg @ref LL_AON_GPIO_PIN_2
958 * @arg @ref LL_AON_GPIO_PIN_3
959 * @arg @ref LL_AON_GPIO_PIN_4
960 * @arg @ref LL_AON_GPIO_PIN_5
961 * @arg @ref LL_AON_GPIO_PIN_6
962 * @arg @ref LL_AON_GPIO_PIN_7
963 * @arg @ref LL_AON_GPIO_PIN_ALL
964 * @retval None
965 */
966 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
967 {
968 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
969 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
970 }
971
972 /**
973 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
974 *
975 * \rst
976 * +----------------------+-----------------------------------+
977 * | Register | BitsName |
978 * +======================+===================================+
979 * | INTPOLCLR | INTPOLCLR |
980 * +----------------------+-----------------------------------+
981 * \endrst
982 * INTTYPECLR | INTTYPECLR
983 *
984 * @param pin_mask This parameter can be a combination of the following values:
985 * @arg @ref LL_AON_GPIO_PIN_0
986 * @arg @ref LL_AON_GPIO_PIN_1
987 * @arg @ref LL_AON_GPIO_PIN_2
988 * @arg @ref LL_AON_GPIO_PIN_3
989 * @arg @ref LL_AON_GPIO_PIN_4
990 * @arg @ref LL_AON_GPIO_PIN_5
991 * @arg @ref LL_AON_GPIO_PIN_6
992 * @arg @ref LL_AON_GPIO_PIN_7
993 * @arg @ref LL_AON_GPIO_PIN_ALL
994 * @retval State of bit (1 or 0).
995 */
996 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
997 {
998 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
999 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
1000 }
1001
1002 /**
1003 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
1004 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1005 *
1006 * \rst
1007 * +----------------------+-----------------------------------+
1008 * | Register | BitsName |
1009 * +======================+===================================+
1010 * | INTENSET | INTENSET |
1011 * +----------------------+-----------------------------------+
1012 * \endrst
1013 *
1014 * @param pin_mask This parameter can be a combination of the following values:
1015 * @arg @ref LL_AON_GPIO_PIN_0
1016 * @arg @ref LL_AON_GPIO_PIN_1
1017 * @arg @ref LL_AON_GPIO_PIN_2
1018 * @arg @ref LL_AON_GPIO_PIN_3
1019 * @arg @ref LL_AON_GPIO_PIN_4
1020 * @arg @ref LL_AON_GPIO_PIN_5
1021 * @arg @ref LL_AON_GPIO_PIN_6
1022 * @arg @ref LL_AON_GPIO_PIN_7
1023 * @arg @ref LL_AON_GPIO_PIN_ALL
1024 * @retval None
1025 */
1026 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
1027 {
1028 WRITE_REG(GPIO2->INTENSET, pin_mask);
1029 }
1030
1031 /**
1032 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
1033 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
1034 *
1035 * \rst
1036 * +----------------------+-----------------------------------+
1037 * | Register | BitsName |
1038 * +======================+===================================+
1039 * | INTENCLR | INTENCLR |
1040 * +----------------------+-----------------------------------+
1041 * \endrst
1042 *
1043 * @param pin_mask This parameter can be a combination of the following values:
1044 * @arg @ref LL_AON_GPIO_PIN_0
1045 * @arg @ref LL_AON_GPIO_PIN_1
1046 * @arg @ref LL_AON_GPIO_PIN_2
1047 * @arg @ref LL_AON_GPIO_PIN_3
1048 * @arg @ref LL_AON_GPIO_PIN_4
1049 * @arg @ref LL_AON_GPIO_PIN_5
1050 * @arg @ref LL_AON_GPIO_PIN_6
1051 * @arg @ref LL_AON_GPIO_PIN_7
1052 * @arg @ref LL_AON_GPIO_PIN_ALL
1053 * @retval None
1054 */
1055 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
1056 {
1057 WRITE_REG(GPIO2->INTENCLR, pin_mask);
1058 }
1059
1060 /**
1061 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
1062 *
1063 * \rst
1064 * +----------------------+-----------------------------------+
1065 * | Register | BitsName |
1066 * +======================+===================================+
1067 * | INTENSET | INTENSET |
1068 * +----------------------+-----------------------------------+
1069 * \endrst
1070 *
1071 * @param pin_mask This parameter can be a combination of the following values:
1072 * @arg @ref LL_AON_GPIO_PIN_0
1073 * @arg @ref LL_AON_GPIO_PIN_1
1074 * @arg @ref LL_AON_GPIO_PIN_2
1075 * @arg @ref LL_AON_GPIO_PIN_3
1076 * @arg @ref LL_AON_GPIO_PIN_4
1077 * @arg @ref LL_AON_GPIO_PIN_5
1078 * @arg @ref LL_AON_GPIO_PIN_6
1079 * @arg @ref LL_AON_GPIO_PIN_7
1080 * @arg @ref LL_AON_GPIO_PIN_ALL
1081 * @retval State of bit (1 or 0).
1082 */
1083 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1084 {
1085 return (READ_BITS(GPIO2->INTENSET, pin_mask) == (pin_mask));
1086 }
1087
1088 /** @} */
1089
1090 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
1091 * @{
1092 */
1093
1094 /**
1095 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
1096 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1097 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1098 *
1099 * \rst
1100 * +----------------------+-----------------------------------+
1101 * | Register | BitsName |
1102 * +======================+===================================+
1103 * | INTSTATUS | INTSTATUS |
1104 * +----------------------+-----------------------------------+
1105 * \endrst
1106 *
1107 * @param pin_mask This parameter can be a combination of the following values:
1108 * @arg @ref LL_AON_GPIO_PIN_0
1109 * @arg @ref LL_AON_GPIO_PIN_1
1110 * @arg @ref LL_AON_GPIO_PIN_2
1111 * @arg @ref LL_AON_GPIO_PIN_3
1112 * @arg @ref LL_AON_GPIO_PIN_4
1113 * @arg @ref LL_AON_GPIO_PIN_5
1114 * @arg @ref LL_AON_GPIO_PIN_6
1115 * @arg @ref LL_AON_GPIO_PIN_7
1116 * @arg @ref LL_AON_GPIO_PIN_ALL
1117 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1118 */
1119 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1120 {
1121 uint32_t ext2 = READ_BITS(GPIO2->INTSTAT, pin_mask);
1122 uint32_t wkup = (READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1123 pin_mask & READ_BITS(AON->EXT_WKUP_CTL, LL_AON_GPIO_PIN_ALL);
1124 return (uint32_t)(ext2 | wkup);
1125 }
1126
1127 /**
1128 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1129 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1130 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1131 *
1132 * \rst
1133 * +----------------------+-----------------------------------+
1134 * | Register | BitsName |
1135 * +======================+===================================+
1136 * | INTSTATUS | INTSTATUS |
1137 * +----------------------+-----------------------------------+
1138 * \endrst
1139 *
1140 * @param pin_mask This parameter can be a combination of the following values:
1141 * @arg @ref LL_AON_GPIO_PIN_0
1142 * @arg @ref LL_AON_GPIO_PIN_1
1143 * @arg @ref LL_AON_GPIO_PIN_2
1144 * @arg @ref LL_AON_GPIO_PIN_3
1145 * @arg @ref LL_AON_GPIO_PIN_4
1146 * @arg @ref LL_AON_GPIO_PIN_5
1147 * @arg @ref LL_AON_GPIO_PIN_6
1148 * @arg @ref LL_AON_GPIO_PIN_7
1149 * @arg @ref LL_AON_GPIO_PIN_ALL
1150 * @retval State of bit (1 or 0).
1151 */
1152 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1153 {
1154 return (READ_BITS(GPIO2->INTSTAT, pin_mask) == pin_mask);
1155 }
1156
1157 /**
1158 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1159 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1160 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1161 *
1162 * \rst
1163 * +----------------------+-----------------------------------+
1164 * | Register | BitsName |
1165 * +======================+===================================+
1166 * | INTSTATUS | INTSTATUS |
1167 * +----------------------+-----------------------------------+
1168 * \endrst
1169 *
1170 * @param pin_mask This parameter can be a combination of the following values:
1171 * @arg @ref LL_AON_GPIO_PIN_0
1172 * @arg @ref LL_AON_GPIO_PIN_1
1173 * @arg @ref LL_AON_GPIO_PIN_2
1174 * @arg @ref LL_AON_GPIO_PIN_3
1175 * @arg @ref LL_AON_GPIO_PIN_4
1176 * @arg @ref LL_AON_GPIO_PIN_5
1177 * @arg @ref LL_AON_GPIO_PIN_6
1178 * @arg @ref LL_AON_GPIO_PIN_7
1179 * @arg @ref LL_AON_GPIO_PIN_ALL
1180 * @retval None
1181 */
1182 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1183 {
1184 WRITE_REG(GPIO2->INTSTAT, pin_mask);
1185 }
1186
1187 /** @} */
1188
1189 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1190 * @{
1191 */
1192
1193 /**
1194 * @brief De-initialize AON_GPIO registers (Registers restored to their default values).
1195 * @retval An error_status_t enumeration value:
1196 * - SUCCESS: AON_GPIO registers are de-initialized
1197 * - ERROR: AON_GPIO registers are not de-initialized
1198 */
1199 error_status_t ll_aon_gpio_deinit(void);
1200
1201 /**
1202 * @brief Initialize AON_GPIO registers according to the specified.
1203 * parameters in p_aon_gpio_init.
1204 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1205 * information for the specified AON_GPIO peripheral.
1206 * @retval An error_status_t enumeration value:
1207 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1208 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1209 */
1210 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1211
1212 /**
1213 * @brief Set each field of a @ref ll_aon_gpio_init_t type structure to default value.
1214 * @param p_aon_gpio_init Pointer to a @ref ll_aon_gpio_init_t structure
1215 * whose fields will be set to default values.
1216 * @retval None
1217 */
1218 void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1219
1220 /** @} */
1221
1222 /** @} */
1223
1224 #endif /* AON */
1225
1226 #ifdef __cplusplus
1227 }
1228 #endif
1229
1230 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1231
1232 /** @} */
1233
1234 /** @} */
1235
1236 /** @} */
LL_AON_GPIO_PULL_UP
#define LL_AON_GPIO_PULL_UP
Definition: gr55xx_ll_aon_gpio.h:141
LL_AON_GPIO_PIN_ALL
#define LL_AON_GPIO_PIN_ALL
Definition: gr55xx_ll_aon_gpio.h:126
_ll_aon_gpio_init::pull
uint32_t pull
Definition: gr55xx_ll_aon_gpio.h:86
ll_aon_gpio_disable_it
__STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
Disable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1055
ll_aon_gpio_is_enabled_xo_2mhz_output
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:540
ll_aon_gpio_set_pin_pull
__STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:352
ll_aon_gpio_clear_flag_it
__STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
Clear Interrupt Status flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1182
ll_aon_gpio_struct_init
void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Set each field of a ll_aon_gpio_init_t type structure to default value.
ll_aon_gpio_is_enabled_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
Check if the Interrupt of specified GPIO pins is enabled or disabled.
Definition: gr55xx_ll_aon_gpio.h:1083
ll_aon_gpio_is_output_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:659
ll_aon_gpio_reset_output_pin
__STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to low level.
Definition: gr55xx_ll_aon_gpio.h:718
ll_aon_gpio_is_active_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1152
ll_aon_gpio_get_pin_pull
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:388
ll_aon_gpio_write_output_port
__STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
Write output data register of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:611
LL_AON_GPIO_MODE_OUTPUT
#define LL_AON_GPIO_MODE_OUTPUT
Definition: gr55xx_ll_aon_gpio.h:133
ll_aon_gpio_is_input_pin_set
__STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
Return if input data level of several AON_GPIO pins is high or low.
Definition: gr55xx_ll_aon_gpio.h:592
ll_aon_gpio_set_mux_pin_0_7
__STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:432
ll_aon_gpio_enable_low_trigger
__STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:966
LL_AON_GPIO_PULL_DOWN
#define LL_AON_GPIO_PULL_DOWN
Definition: gr55xx_ll_aon_gpio.h:142
ll_aon_gpio_get_pin_mode
__STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
Return gpio mode for a AON_GPIO pin.
Definition: gr55xx_ll_aon_gpio.h:316
ll_aon_gpio_enable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
Enable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:504
LL_AON_GPIO_MODE_INPUT
#define LL_AON_GPIO_MODE_INPUT
Definition: gr55xx_ll_aon_gpio.h:132
_ll_aon_gpio_init::mode
uint32_t mode
Definition: gr55xx_ll_aon_gpio.h:81
ll_aon_gpio_disable_xo_2mhz_output
__STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
Disable Xo_2MHz output on AON_GPIO_PIN5.
Definition: gr55xx_ll_aon_gpio.h:522
ll_aon_gpio_toggle_pin
__STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
Toggle data value of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:748
ll_aon_gpio_enable_falling_trigger
__STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:785
_ll_aon_gpio_init::trigger
uint32_t trigger
Definition: gr55xx_ll_aon_gpio.h:97
_ll_aon_gpio_init::mux
uint32_t mux
Definition: gr55xx_ll_aon_gpio.h:91
ll_aon_gpio_get_mux_pin_0_7
__STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
Definition: gr55xx_ll_aon_gpio.h:478
LL_AON_GPIO_MUX_7
#define LL_AON_GPIO_MUX_7
Definition: gr55xx_ll_aon_gpio.h:155
ll_aon_gpio_set_output_pin
__STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
Set specified AON_GPIO pins to high level.
Definition: gr55xx_ll_aon_gpio.h:688
_ll_aon_gpio_init
LL AON_GPIO init Structure definition.
Definition: gr55xx_ll_aon_gpio.h:77
ll_aon_gpio_deinit
error_status_t ll_aon_gpio_deinit(void)
De-initialize AON_GPIO registers (Registers restored to their default values).
ll_aon_gpio_enable_high_trigger
__STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:906
_ll_aon_gpio_init::pin
uint32_t pin
Definition: gr55xx_ll_aon_gpio.h:78
ll_aon_gpio_read_input_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
Return full input data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:564
ll_aon_gpio_init
error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init)
Initialize AON_GPIO registers according to the specified. parameters in p_aon_gpio_init.
LL_AON_GPIO_PULL_NO
#define LL_AON_GPIO_PULL_NO
Definition: gr55xx_ll_aon_gpio.h:140
ll_aon_gpio_read_output_port
__STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
Return full output data register value of AON_GPIO.
Definition: gr55xx_ll_aon_gpio.h:631
ll_aon_gpio_is_enabled_high_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
Check if high level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:936
ll_aon_gpio_set_pin_mode
__STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
Set several AON_GPIO pins to input/output mode.
Definition: gr55xx_ll_aon_gpio.h:282
ll_aon_gpio_is_enabled_falling_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
Check if falling edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:815
ll_aon_gpio_read_flag_it
__STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1119
ll_aon_gpio_init_t
struct _ll_aon_gpio_init ll_aon_gpio_init_t
LL AON_GPIO init Structure definition.
ll_aon_gpio_enable_it
__STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
Enable AON_GPIO interrupts of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:1026
ll_aon_gpio_is_enabled_low_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
Check if low level trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:996
ll_aon_gpio_enable_rising_trigger
__STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:845
ll_aon_gpio_is_enabled_rising_trigger
__STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
Check if rising edge trigger is enabled of specified AON_GPIO pins.
Definition: gr55xx_ll_aon_gpio.h:876