gr55xx_ll_pwm.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef __GR55XX_LL_PWM_H__
52 #define __GR55XX_LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr55xx.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /** @defgroup PWM_LL_STRUCTURES Structures
63 * @{
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
68 * @{
69 */
70
71 /**
72 * @brief LL PWM Output Channel init Structure definition.
73 */
74 typedef struct _ll_pwm_channel_init_t
75 {
76 uint8_t duty; /**< Specifies the duty in PWM output mode.
77 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.
78
79 This feature can be modified afterwards using unitary function ll_pwm_set_compare_xn()
80 where X can be (A, B, C) and n can be (0, 1).*/
81
82 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
83 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
84
85 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
86 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
87
88 } ll_pwm_channel_init_t;
89
90 /**
91 * @brief LL PWM init Structure definition.
92 */
93 typedef struct _ll_pwm_init_t
94 {
95 uint32_t mode; /**< Specifies the PWM output mode.
96 This parameter can be a value of @ref PWM_LL_EC_MODE.
97
98 This feature can be modified afterwards using unitary function @ref ll_pwm_set_mode().*/
99
100 uint32_t align; /**< Specifies the PWM alignment pulses.
101 This parameter can be a value of @ref PWM_LL_EC_ALIGN.*/
102
103 uint32_t prescaler; /**< Specifies the prescaler value which will be used configure PWM output frequency.
104 This parameter must be a number ranges between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
105 This parameter should be larger than 128.
106
107 This feature can be modified afterwards using unitary function @ref ll_pwm_set_prescaler().*/
108
109 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
110 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
111 This parameter is recommended to be larger than 128*prescaler to guarantee an ideal breath effect.
112
113 This feature can be modified afterwards using unitary function @ref ll_pwm_set_breath_prescaler().*/
114
115 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
116 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFF.
117
118 This feature can be modified afterwards using unitary function @ref ll_pwm_set_hold_prescaler().*/
119
120 ll_pwm_channel_init_t channel_a; /**< Specifies the configuration of channelA.
121 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
122
123 ll_pwm_channel_init_t channel_b; /**< Specifies the configuration of channelB.
124 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
125
126 ll_pwm_channel_init_t channel_c; /**< Specifies the configuration of channelC.
127 This parameter can be a value of @ref ll_pwm_channel_init_t.*/
128
129 } ll_pwm_init_t;
130
131 /** @} */
132
133 /** @} */
134
135 /**
136 * @defgroup PWM_LL_MACRO Defines
137 * @{
138 */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
142 * @{
143 */
144
145 /** @defgroup PWM_LL_EC_MODE PWM mode
146 * @{
147 */
148 #define LL_PWM_FLICKER_MODE (0x00000000U) /**< PWM flicker mode */
149 #define LL_PWM_BREATH_MODE PWM_MODE_BREATHEN /**< PWM breath mode */
150 /** @} */
151
152 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
153 * @{
154 */
155 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
156 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
157 /** @} */
158
159 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
160 * @{
161 */
162 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
163 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
164 /** @} */
165
166 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
167 * @{
168 */
169 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
170 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
171 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
172 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
173 /** @} */
174
175 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
176 * @{
177 */
178 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
179 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
180 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
181 /** @} */
182
183 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
184 * @{
185 */
186
187 /**
188 * @brief LL PWM Channel InitStrcut default configuartion
189 */
190 #define LL_PWM_CHANNEL_DEFAULT_CONFIG \
191 { \
192 .duty = 50, \
193 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
194 }
195
196 /**
197 * @brief LL PWM InitStrcut default configuartion
198 */
199 #define LL_PWM_DEFAULT_CONFIG \
200 { \
201 .mode = LL_PWM_FLICKER_MODE, \
202 .align = LL_PWM_EDGE_ALIGNED, \
203 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
204 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
205 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
206 .channel_a = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
207 .channel_b = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
208 .channel_c = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
209 }
210
211 /** @} */
212
213 /** @} */
214
215 /* Exported macro ------------------------------------------------------------*/
216 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
217 * @{
218 */
219
220 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
221 * @{
222 */
223
224 /**
225 * @brief Write a value in PWM register
226 * @param __instance__ PWM instance
227 * @param __REG__ Register to be written
228 * @param __VALUE__ Value to be written in the register
229 * @retval None
230 */
231 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
232
233 /**
234 * @brief Read a value in PWM register
235 * @param __instance__ PWM instance
236 * @param __REG__ Register to be read
237 * @retval Register value
238 */
239 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
240
241 /** @} */
242
243 /** @} */
244
245 /** @} */
246
247 /* Exported functions --------------------------------------------------------*/
248 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
249 * @{
250 */
251
252 /** @defgroup PWM_LL_EF_Configuration Configuration functions
253 * @{
254 */
255
256 /**
257 * @brief Enable PWM.
258 *
259 * \rst
260 * +----------------------+-----------------------------------+
261 * | Register | BitsName |
262 * +======================+===================================+
263 * | MODE | EN |
264 * +----------------------+-----------------------------------+
265 * \endrst
266 *
267 * @param PWMx PWM instance
268 * @retval None
269 */
270 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
271 {
272 SET_BITS(PWMx->MODE, PWM_MODE_EN);
273 }
274
275 /**
276 * @brief Disable PWM.
277 *
278 * \rst
279 * +----------------------+-----------------------------------+
280 * | Register | BitsName |
281 * +======================+===================================+
282 * | MODE | EN |
283 * +----------------------+-----------------------------------+
284 * \endrst
285 *
286 * @param PWMx PWM instance
287 * @retval None
288 */
289 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
290 {
291 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
292 }
293
294 /**
295 * @brief Indicate whether the PWM is enabled.
296 *
297 * \rst
298 * +----------------------+-----------------------------------+
299 * | Register | BitsName |
300 * +======================+===================================+
301 * | MODE | EN |
302 * +----------------------+-----------------------------------+
303 * \endrst
304 *
305 * @param PWMx PWM instance
306 * @retval State of bit (1 or 0).
307 */
308 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
309 {
310 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
311 }
312
313 /**
314 * @brief Enable PWM pause.
315 *
316 * \rst
317 * +----------------------+-----------------------------------+
318 * | Register | BitsName |
319 * +======================+===================================+
320 * | MODE | PAUSE |
321 * +----------------------+-----------------------------------+
322 * \endrst
323 *
324 * @param PWMx PWM instance
325 * @retval None
326 */
327 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
328 {
329 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
330 }
331
332 /**
333 * @brief Disable PWM pause.
334 *
335 * \rst
336 * +----------------------+-----------------------------------+
337 * | Register | BitsName |
338 * +======================+===================================+
339 * | MODE | PAUSE |
340 * +----------------------+-----------------------------------+
341 * \endrst
342 *
343 * @param PWMx PWM instance
344 * @retval None
345 */
346 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
347 {
348 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
349 }
350
351 /**
352 * @brief Indicate whether the PWM pause is enabled.
353 *
354 * \rst
355 * +----------------------+-----------------------------------+
356 * | Register | BitsName |
357 * +======================+===================================+
358 * | MODE | PAUSE |
359 * +----------------------+-----------------------------------+
360 * \endrst
361 *
362 * @param PWMx PWM instance
363 * @retval State of bit (1 or 0).
364 */
365 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
366 {
367 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
368 }
369
370 /**
371 * @brief Set PWM mode.
372 *
373 * \rst
374 * +----------------------+-----------------------------------+
375 * | Register | BitsName |
376 * +======================+===================================+
377 * | MODE | BREATHEN |
378 * +----------------------+-----------------------------------+
379 * \endrst
380 *
381 * @param PWMx PWM instance
382 * @param mode This parameter can be one of the following values:
383 * @arg @ref LL_PWM_FLICKER_MODE
384 * @arg @ref LL_PWM_BREATH_MODE
385 * @retval None
386 */
387 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
388 {
389 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, mode);
390 }
391
392 /**
393 * @brief Get PWM mode.
394 *
395 * \rst
396 * +----------------------+-----------------------------------+
397 * | Register | BitsName |
398 * +======================+===================================+
399 * | MODE | BREATHEN |
400 * +----------------------+-----------------------------------+
401 * \endrst
402 *
403 * @param PWMx PWM instance
404 * @retval Return value can be one of the following values:
405 * @arg @ref LL_PWM_FLICKER_MODE
406 * @arg @ref LL_PWM_BREATH_MODE
407 */
408 __STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
409 {
410 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN));
411 }
412
413 /**
414 * @brief Enable positive drive mode in channelA.
415 *
416 * \rst
417 * +----------------------+-----------------------------------+
418 * | Register | BitsName |
419 * +======================+===================================+
420 * | MODE | DPENA |
421 * +----------------------+-----------------------------------+
422 * \endrst
423 *
424 * @param PWMx PWM instance
425 * @retval None
426 */
427 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
428 {
429 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
430 }
431
432 /**
433 * @brief Disable positive drive mode in channelA.
434 *
435 * \rst
436 * +----------------------+-----------------------------------+
437 * | Register | BitsName |
438 * +======================+===================================+
439 * | MODE | DPENA |
440 * +----------------------+-----------------------------------+
441 * \endrst
442 *
443 * @param PWMx PWM instance
444 * @retval None
445 */
446 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
447 {
448 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
449 }
450
451 /**
452 * @brief Indicate whether the positive drive mode in channelA is enabled.
453 *
454 * \rst
455 * +----------------------+-----------------------------------+
456 * | Register | BitsName |
457 * +======================+===================================+
458 * | MODE | DPENA |
459 * +----------------------+-----------------------------------+
460 * \endrst
461 *
462 * @param PWMx PWM instance
463 * @retval State of bit (1 or 0).
464 */
465 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
466 {
467 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
468 }
469
470 /**
471 * @brief Enable positive drive mode in channelB.
472 *
473 * \rst
474 * +----------------------+-----------------------------------+
475 * | Register | BitsName |
476 * +======================+===================================+
477 * | MODE | DPENB |
478 * +----------------------+-----------------------------------+
479 * \endrst
480 *
481 * @param PWMx PWM instance
482 * @retval None
483 */
484 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
485 {
486 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
487 }
488
489 /**
490 * @brief Disable positive drive mode in channelB.
491 *
492 * \rst
493 * +----------------------+-----------------------------------+
494 * | Register | BitsName |
495 * +======================+===================================+
496 * | MODE | DPENB |
497 * +----------------------+-----------------------------------+
498 * \endrst
499 *
500 * @param PWMx PWM instance
501 * @retval None
502 */
503 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
504 {
505 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
506 }
507
508 /**
509 * @brief Indicate whether the positive drive mode in channelB is enabled.
510 *
511 * \rst
512 * +----------------------+-----------------------------------+
513 * | Register | BitsName |
514 * +======================+===================================+
515 * | MODE | DPENB |
516 * +----------------------+-----------------------------------+
517 * \endrst
518 *
519 * @param PWMx PWM instance
520 * @retval State of bit (1 or 0).
521 */
522 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
523 {
524 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
525 }
526
527 /**
528 * @brief Enable positive drive mode in channelC.
529 *
530 * \rst
531 * +----------------------+-----------------------------------+
532 * | Register | BitsName |
533 * +======================+===================================+
534 * | MODE | DPENC |
535 * +----------------------+-----------------------------------+
536 * \endrst
537 *
538 * @param PWMx PWM instance
539 * @retval None
540 */
541 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
542 {
543 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
544 }
545
546 /**
547 * @brief Disable positive drive mode in channelC.
548 *
549 * \rst
550 * +----------------------+-----------------------------------+
551 * | Register | BitsName |
552 * +======================+===================================+
553 * | MODE | DPENC |
554 * +----------------------+-----------------------------------+
555 * \endrst
556 *
557 * @param PWMx PWM instance
558 * @retval None
559 */
560 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
561 {
562 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
563 }
564
565 /**
566 * @brief Indicate whether the positive drive mode in channelC is enabled.
567 *
568 * \rst
569 * +----------------------+-----------------------------------+
570 * | Register | BitsName |
571 * +======================+===================================+
572 * | MODE | DPENC |
573 * +----------------------+-----------------------------------+
574 * \endrst
575 *
576 * @param PWMx PWM instance
577 * @retval State of bit (1 or 0).
578 */
579 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
580 {
581 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
582 }
583
584 /**
585 * @brief Check update active flag
586 *
587 * \rst
588 * +----------------------+-----------------------------------+
589 * | Register | BitsName |
590 * +======================+===================================+
591 * | UPDATE | SAG |
592 * +----------------------+-----------------------------------+
593 * \endrst
594 *
595 * @param PWMx PWM instance
596 * @retval State of bit (1 or 0).
597 */
598 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
599 {
600 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
601 }
602
603 /**
604 * @brief Enable update all parameters.
605 *
606 * \rst
607 * +----------------------+-----------------------------------+
608 * | Register | BitsName |
609 * +======================+===================================+
610 * | UPDATE | SA |
611 * +----------------------+-----------------------------------+
612 * \endrst
613 *
614 * @param PWMx PWM instance
615 * @retval None
616 */
617 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
618 {
619 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
620 }
621
622 /**
623 * @brief Disable update all parameters.
624 *
625 * \rst
626 * +----------------------+-----------------------------------+
627 * | Register | BitsName |
628 * +======================+===================================+
629 * | UPDATE | SA |
630 * +----------------------+-----------------------------------+
631 * \endrst
632 *
633 * @param PWMx PWM instance
634 * @retval None
635 */
636 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
637 {
638 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
639 }
640
641 /**
642 * @brief Indicate whether the update all parameters is enabled.
643 *
644 * \rst
645 * +----------------------+-----------------------------------+
646 * | Register | BitsName |
647 * +======================+===================================+
648 * | UPDATE | SA |
649 * +----------------------+-----------------------------------+
650 * \endrst
651 *
652 * @param PWMx PWM instance
653 * @retval State of bit (1 or 0).
654 */
655 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
656 {
657 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
658 }
659
660 /**
661 * @brief Enable update period.
662 *
663 * \rst
664 * +----------------------+-----------------------------------+
665 * | Register | BitsName |
666 * +======================+===================================+
667 * | UPDATE | SSPRD |
668 * +----------------------+-----------------------------------+
669 * \endrst
670 *
671 * @param PWMx PWM instance
672 * @retval None
673 */
674 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
675 {
676 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
677 }
678
679 /**
680 * @brief Disable update period.
681 *
682 * \rst
683 * +----------------------+-----------------------------------+
684 * | Register | BitsName |
685 * +======================+===================================+
686 * | UPDATE | SSPRD |
687 * +----------------------+-----------------------------------+
688 * \endrst
689 *
690 * @param PWMx PWM instance
691 * @retval None
692 */
693 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
694 {
695 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
696 }
697
698 /**
699 * @brief Indicate whether the update period is enabled.
700 *
701 * \rst
702 * +----------------------+-----------------------------------+
703 * | Register | BitsName |
704 * +======================+===================================+
705 * | UPDATE | SSPRD |
706 * +----------------------+-----------------------------------+
707 * \endrst
708 *
709 * @param PWMx PWM instance
710 * @retval State of bit (1 or 0).
711 */
712 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
713 {
714 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
715 }
716
717 /**
718 * @brief Enable update compareA0.
719 *
720 * \rst
721 * +----------------------+-----------------------------------+
722 * | Register | BitsName |
723 * +======================+===================================+
724 * | UPDATE | SSCMPA0 |
725 * +----------------------+-----------------------------------+
726 * \endrst
727 *
728 * @param PWMx PWM instance
729 * @retval None
730 */
731 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
732 {
733 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
734 }
735
736 /**
737 * @brief Disable update compareA0.
738 *
739 * \rst
740 * +----------------------+-----------------------------------+
741 * | Register | BitsName |
742 * +======================+===================================+
743 * | UPDATE | SSCMPA0 |
744 * +----------------------+-----------------------------------+
745 * \endrst
746 *
747 * @param PWMx PWM instance
748 * @retval None
749 */
750 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
751 {
752 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
753 }
754
755 /**
756 * @brief Indicate whether the update compareA0 is enabled.
757 *
758 * \rst
759 * +----------------------+-----------------------------------+
760 * | Register | BitsName |
761 * +======================+===================================+
762 * | UPDATE | SSCMPA0 |
763 * +----------------------+-----------------------------------+
764 * \endrst
765 *
766 * @param PWMx PWM instance
767 * @retval State of bit (1 or 0).
768 */
769 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
770 {
771 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
772 }
773
774 /**
775 * @brief Enable update compareA1.
776 *
777 * \rst
778 * +----------------------+-----------------------------------+
779 * | Register | BitsName |
780 * +======================+===================================+
781 * | UPDATE | SSCMPA1 |
782 * +----------------------+-----------------------------------+
783 * \endrst
784 *
785 * @param PWMx PWM instance
786 * @retval None
787 */
788 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
789 {
790 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
791 }
792
793 /**
794 * @brief Disable update compareA1.
795 *
796 * \rst
797 * +----------------------+-----------------------------------+
798 * | Register | BitsName |
799 * +======================+===================================+
800 * | UPDATE | SSCMPA1 |
801 * +----------------------+-----------------------------------+
802 * \endrst
803 *
804 * @param PWMx PWM instance
805 * @retval None
806 */
807 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
808 {
809 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
810 }
811
812 /**
813 * @brief Indicate whether the update compareA1 is enabled.
814 *
815 * \rst
816 * +----------------------+-----------------------------------+
817 * | Register | BitsName |
818 * +======================+===================================+
819 * | UPDATE | SSCMPA1 |
820 * +----------------------+-----------------------------------+
821 * \endrst
822 *
823 * @param PWMx PWM instance
824 * @retval State of bit (1 or 0).
825 */
826 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
827 {
828 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
829 }
830
831 /**
832 * @brief Enable update compareB0.
833 *
834 * \rst
835 * +----------------------+-----------------------------------+
836 * | Register | BitsName |
837 * +======================+===================================+
838 * | UPDATE | SSCMPB0 |
839 * +----------------------+-----------------------------------+
840 * \endrst
841 *
842 * @param PWMx PWM instance
843 * @retval None
844 */
845 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
846 {
847 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
848 }
849
850 /**
851 * @brief Disable update compareB0.
852 *
853 * \rst
854 * +----------------------+-----------------------------------+
855 * | Register | BitsName |
856 * +======================+===================================+
857 * | UPDATE | SSCMPB0 |
858 * +----------------------+-----------------------------------+
859 * \endrst
860 *
861 * @param PWMx PWM instance
862 * @retval None
863 */
864 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
865 {
866 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
867 }
868
869 /**
870 * @brief Indicate whether the update compareB0 is enabled.
871 *
872 * \rst
873 * +----------------------+-----------------------------------+
874 * | Register | BitsName |
875 * +======================+===================================+
876 * | UPDATE | SSCMPB0 |
877 * +----------------------+-----------------------------------+
878 * \endrst
879 *
880 * @param PWMx PWM instance
881 * @retval State of bit (1 or 0).
882 */
883 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
884 {
885 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
886 }
887
888 /**
889 * @brief Enable update compareB1.
890 *
891 * \rst
892 * +----------------------+-----------------------------------+
893 * | Register | BitsName |
894 * +======================+===================================+
895 * | UPDATE | SSCMPB1 |
896 * +----------------------+-----------------------------------+
897 * \endrst
898 *
899 * @param PWMx PWM instance
900 * @retval None
901 */
902 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
903 {
904 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
905 }
906
907 /**
908 * @brief Disable update compareB1.
909 *
910 * \rst
911 * +----------------------+-----------------------------------+
912 * | Register | BitsName |
913 * +======================+===================================+
914 * | UPDATE | SSCMPB1 |
915 * +----------------------+-----------------------------------+
916 * \endrst
917 *
918 * @param PWMx PWM instance
919 * @retval None
920 */
921 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
922 {
923 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
924 }
925
926 /**
927 * @brief Indicate whether the update compareB1 is enabled.
928 *
929 * \rst
930 * +----------------------+-----------------------------------+
931 * | Register | BitsName |
932 * +======================+===================================+
933 * | UPDATE | SSCMPB1 |
934 * +----------------------+-----------------------------------+
935 * \endrst
936 *
937 * @param PWMx PWM instance
938 * @retval State of bit (1 or 0).
939 */
940 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
941 {
942 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
943 }
944
945 /**
946 * @brief Enable update compareC0.
947 *
948 * \rst
949 * +----------------------+-----------------------------------+
950 * | Register | BitsName |
951 * +======================+===================================+
952 * | UPDATE | SSCMPC0 |
953 * +----------------------+-----------------------------------+
954 * \endrst
955 *
956 * @param PWMx PWM instance
957 * @retval None
958 */
959 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
960 {
961 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
962 }
963
964 /**
965 * @brief Disable update compareC0.
966 *
967 * \rst
968 * +----------------------+-----------------------------------+
969 * | Register | BitsName |
970 * +======================+===================================+
971 * | UPDATE | SSCMPC0 |
972 * +----------------------+-----------------------------------+
973 * \endrst
974 *
975 * @param PWMx PWM instance
976 * @retval None
977 */
978 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
979 {
980 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
981 }
982
983 /**
984 * @brief Indicate whether the update compareC0 is enabled.
985 *
986 * \rst
987 * +----------------------+-----------------------------------+
988 * | Register | BitsName |
989 * +======================+===================================+
990 * | UPDATE | SSCMPC0 |
991 * +----------------------+-----------------------------------+
992 * \endrst
993 *
994 * @param PWMx PWM instance
995 * @retval State of bit (1 or 0).
996 */
997 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
998 {
999 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
1000 }
1001
1002 /**
1003 * @brief Enable update compareC1.
1004 *
1005 * \rst
1006 * +----------------------+-----------------------------------+
1007 * | Register | BitsName |
1008 * +======================+===================================+
1009 * | UPDATE | SSCMPC1 |
1010 * +----------------------+-----------------------------------+
1011 * \endrst
1012 *
1013 * @param PWMx PWM instance
1014 * @retval None
1015 */
1016 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
1017 {
1018 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1019 }
1020
1021 /**
1022 * @brief Disable update compareC1.
1023 *
1024 * \rst
1025 * +----------------------+-----------------------------------+
1026 * | Register | BitsName |
1027 * +======================+===================================+
1028 * | UPDATE | SSCMPC1 |
1029 * +----------------------+-----------------------------------+
1030 * \endrst
1031 *
1032 * @param PWMx PWM instance
1033 * @retval None
1034 */
1035 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
1036 {
1037 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1038 }
1039
1040 /**
1041 * @brief Indicate whether the update compareC1 is enabled.
1042 *
1043 * \rst
1044 * +----------------------+-----------------------------------+
1045 * | Register | BitsName |
1046 * +======================+===================================+
1047 * | UPDATE | SSCMPC1 |
1048 * +----------------------+-----------------------------------+
1049 * \endrst
1050 *
1051 * @param PWMx PWM instance
1052 * @retval State of bit (1 or 0).
1053 */
1054 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
1055 {
1056 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
1057 }
1058
1059 /**
1060 * @brief Enable update pause.
1061 *
1062 * \rst
1063 * +----------------------+-----------------------------------+
1064 * | Register | BitsName |
1065 * +======================+===================================+
1066 * | UPDATE | SSPAUSE |
1067 * +----------------------+-----------------------------------+
1068 * \endrst
1069 *
1070 * @param PWMx PWM instance
1071 * @retval None
1072 */
1073 __STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
1074 {
1075 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
1076 }
1077
1078 /**
1079 * @brief Disable update pause.
1080 *
1081 * \rst
1082 * +----------------------+-----------------------------------+
1083 * | Register | BitsName |
1084 * +======================+===================================+
1085 * | UPDATE | SSPAUSE |
1086 * +----------------------+-----------------------------------+
1087 * \endrst
1088 *
1089 * @param PWMx PWM instance
1090 * @retval None
1091 */
1092 __STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
1093 {
1094 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
1095 }
1096
1097 /**
1098 * @brief Indicate whether the update pause is enabled.
1099 *
1100 * \rst
1101 * +----------------------+-----------------------------------+
1102 * | Register | BitsName |
1103 * +======================+===================================+
1104 * | UPDATE | SSPAUSE |
1105 * +----------------------+-----------------------------------+
1106 * \endrst
1107 *
1108 * @param PWMx PWM instance
1109 * @retval State of bit (1 or 0).
1110 */
1111 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
1112 {
1113 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE) == (PWM_UPDATE_SSPAUSE));
1114 }
1115
1116 /**
1117 * @brief Enable update breath period.
1118 *
1119 * \rst
1120 * +----------------------+-----------------------------------+
1121 * | Register | BitsName |
1122 * +======================+===================================+
1123 * | UPDATE | SSBRPRD |
1124 * +----------------------+-----------------------------------+
1125 * \endrst
1126 *
1127 * @param PWMx PWM instance
1128 * @retval None
1129 */
1130 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
1131 {
1132 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1133 }
1134
1135 /**
1136 * @brief Disable update breath period.
1137 *
1138 * \rst
1139 * +----------------------+-----------------------------------+
1140 * | Register | BitsName |
1141 * +======================+===================================+
1142 * | UPDATE | SSBRPRD |
1143 * +----------------------+-----------------------------------+
1144 * \endrst
1145 *
1146 * @param PWMx PWM instance
1147 * @retval None
1148 */
1149 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
1150 {
1151 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1152 }
1153
1154 /**
1155 * @brief Indicate whether the update breath period is enabled.
1156 *
1157 * \rst
1158 * +----------------------+-----------------------------------+
1159 * | Register | BitsName |
1160 * +======================+===================================+
1161 * | UPDATE | SSBRPRD |
1162 * +----------------------+-----------------------------------+
1163 * \endrst
1164 *
1165 * @param PWMx PWM instance
1166 * @retval State of bit (1 or 0).
1167 */
1168 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
1169 {
1170 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
1171 }
1172
1173 /**
1174 * @brief Enable update hold period.
1175 *
1176 * \rst
1177 * +----------------------+-----------------------------------+
1178 * | Register | BitsName |
1179 * +======================+===================================+
1180 * | UPDATE | SSHOLD |
1181 * +----------------------+-----------------------------------+
1182 * \endrst
1183 *
1184 * @param PWMx PWM instance
1185 * @retval None
1186 */
1187 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
1188 {
1189 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1190 }
1191
1192 /**
1193 * @brief Disable update hold period.
1194 *
1195 * \rst
1196 * +----------------------+-----------------------------------+
1197 * | Register | BitsName |
1198 * +======================+===================================+
1199 * | UPDATE | SSHOLD |
1200 * +----------------------+-----------------------------------+
1201 * \endrst
1202 *
1203 * @param PWMx PWM instance
1204 * @retval None
1205 */
1206 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1207 {
1208 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1209 }
1210
1211 /**
1212 * @brief Indicate whether the update hold period is enabled.
1213 *
1214 * \rst
1215 * +----------------------+-----------------------------------+
1216 * | Register | BitsName |
1217 * +======================+===================================+
1218 * | UPDATE | SSHOLD |
1219 * +----------------------+-----------------------------------+
1220 * \endrst
1221 *
1222 * @param PWMx PWM instance
1223 * @retval State of bit (1 or 0).
1224 */
1225 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1226 {
1227 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1228 }
1229
1230 /**
1231 * @brief Enable update active event.
1232 *
1233 * \rst
1234 * +----------------------+-----------------------------------+
1235 * | Register | BitsName |
1236 * +======================+===================================+
1237 * | UPDATE | SSAQCTRL |
1238 * +----------------------+-----------------------------------+
1239 * \endrst
1240 *
1241 * @param PWMx PWM instance
1242 * @retval None
1243 */
1244 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1245 {
1246 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1247 }
1248
1249 /**
1250 * @brief Disable update active event.
1251 *
1252 * \rst
1253 * +----------------------+-----------------------------------+
1254 * | Register | BitsName |
1255 * +======================+===================================+
1256 * | UPDATE | SSAQCTRL |
1257 * +----------------------+-----------------------------------+
1258 * \endrst
1259 *
1260 * @param PWMx PWM instance
1261 * @retval None
1262 */
1263 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1264 {
1265 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1266 }
1267
1268 /**
1269 * @brief Indicate whether the update active event is enabled.
1270 *
1271 * \rst
1272 * +----------------------+-----------------------------------+
1273 * | Register | BitsName |
1274 * +======================+===================================+
1275 * | UPDATE | SSAQCTRL |
1276 * +----------------------+-----------------------------------+
1277 * \endrst
1278 *
1279 * @param PWMx PWM instance
1280 * @retval State of bit (1 or 0).
1281 */
1282 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1283 {
1284 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1285 }
1286
1287 /**
1288 * @brief Set the PWM prescaler.
1289 *
1290 * \rst
1291 * +----------------------+-----------------------------------+
1292 * | Register | BitsName |
1293 * +======================+===================================+
1294 * | PRD | PRD |
1295 * +----------------------+-----------------------------------+
1296 * \endrst
1297 *
1298 * @param PWMx PWM instance
1299 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1300 * @retval None
1301 */
1302 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1303 {
1304 WRITE_REG(PWMx->PRD, prescaler);
1305 }
1306
1307 /**
1308 * @brief Get the PWM prescaler.
1309 *
1310 * \rst
1311 * +----------------------+-----------------------------------+
1312 * | Register | BitsName |
1313 * +======================+===================================+
1314 * | PRD | PRD |
1315 * +----------------------+-----------------------------------+
1316 * \endrst
1317 *
1318 * @param PWMx PWM instance
1319 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1320 */
1321 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1322 {
1323 return (READ_REG(PWMx->PRD));
1324 }
1325
1326 /**
1327 * @brief Set the PWM compare counter A0.
1328 *
1329 * \rst
1330 * +----------------------+-----------------------------------+
1331 * | Register | BitsName |
1332 * +======================+===================================+
1333 * | CMPA0 | CMPA0 |
1334 * +----------------------+-----------------------------------+
1335 * \endrst
1336 *
1337 * @param PWMx PWM instance
1338 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1339 * @retval None
1340 */
1341 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1342 {
1343 WRITE_REG(PWMx->CMPA0, compare);
1344 }
1345
1346 /**
1347 * @brief Get the PWM compare counter A0.
1348 *
1349 * \rst
1350 * +----------------------+-----------------------------------+
1351 * | Register | BitsName |
1352 * +======================+===================================+
1353 * | CMPA0 | CMPA0 |
1354 * +----------------------+-----------------------------------+
1355 * \endrst
1356 *
1357 * @param PWMx PWM instance
1358 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1359 */
1360 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1361 {
1362 return (READ_REG(PWMx->CMPA0));
1363 }
1364
1365 /**
1366 * @brief Set the PWM compare counter A1.
1367 *
1368 * \rst
1369 * +----------------------+-----------------------------------+
1370 * | Register | BitsName |
1371 * +======================+===================================+
1372 * | CMPA1 | CMPA1 |
1373 * +----------------------+-----------------------------------+
1374 * \endrst
1375 *
1376 * @param PWMx PWM instance
1377 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1378 * @retval None
1379 */
1380 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1381 {
1382 WRITE_REG(PWMx->CMPA1, compare);
1383 }
1384
1385 /**
1386 * @brief Get the PWM compare counter A1.
1387 *
1388 * \rst
1389 * +----------------------+-----------------------------------+
1390 * | Register | BitsName |
1391 * +======================+===================================+
1392 * | CMPA1 | CMPA1 |
1393 * +----------------------+-----------------------------------+
1394 * \endrst
1395 *
1396 * @param PWMx PWM instance
1397 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1398 */
1399 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1400 {
1401 return (READ_REG(PWMx->CMPA1));
1402 }
1403
1404 /**
1405 * @brief Set the PWM compare counter B0.
1406 *
1407 * \rst
1408 * +----------------------+-----------------------------------+
1409 * | Register | BitsName |
1410 * +======================+===================================+
1411 * | CMPB0 | CMPB0 |
1412 * +----------------------+-----------------------------------+
1413 * \endrst
1414 *
1415 * @param PWMx PWM instance
1416 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1417 * @retval None
1418 */
1419 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1420 {
1421 WRITE_REG(PWMx->CMPB0, compare);
1422 }
1423
1424 /**
1425 * @brief Get the PWM compare counter B0.
1426 *
1427 * \rst
1428 * +----------------------+-----------------------------------+
1429 * | Register | BitsName |
1430 * +======================+===================================+
1431 * | CMPB0 | CMPB0 |
1432 * +----------------------+-----------------------------------+
1433 * \endrst
1434 *
1435 * @param PWMx PWM instance
1436 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1437 */
1438 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1439 {
1440 return (READ_REG(PWMx->CMPB0));
1441 }
1442
1443 /**
1444 * @brief Set the PWM compare counter B1.
1445 *
1446 * \rst
1447 * +----------------------+-----------------------------------+
1448 * | Register | BitsName |
1449 * +======================+===================================+
1450 * | CMPB1 | CMPB1 |
1451 * +----------------------+-----------------------------------+
1452 * \endrst
1453 *
1454 * @param PWMx PWM instance
1455 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1456 * @retval None
1457 */
1458 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1459 {
1460 WRITE_REG(PWMx->CMPB1, compare);
1461 }
1462
1463 /**
1464 * @brief Get the PWM compare counter B1.
1465 *
1466 * \rst
1467 * +----------------------+-----------------------------------+
1468 * | Register | BitsName |
1469 * +======================+===================================+
1470 * | CMPB1 | CMPB1 |
1471 * +----------------------+-----------------------------------+
1472 * \endrst
1473 *
1474 * @param PWMx PWM instance
1475 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1476 */
1477 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1478 {
1479 return (READ_REG(PWMx->CMPB1));
1480 }
1481
1482 /**
1483 * @brief Set the PWM compare counter C0.
1484 *
1485 * \rst
1486 * +----------------------+-----------------------------------+
1487 * | Register | BitsName |
1488 * +======================+===================================+
1489 * | CMPC0 | CMPC0 |
1490 * +----------------------+-----------------------------------+
1491 * \endrst
1492 *
1493 * @param PWMx PWM instance
1494 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1495 * @retval None
1496 */
1497 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1498 {
1499 WRITE_REG(PWMx->CMPC0, compare);
1500 }
1501
1502 /**
1503 * @brief Get the PWM compare counter C0.
1504 *
1505 * \rst
1506 * +----------------------+-----------------------------------+
1507 * | Register | BitsName |
1508 * +======================+===================================+
1509 * | CMPC0 | CMPC0 |
1510 * +----------------------+-----------------------------------+
1511 * \endrst
1512 *
1513 * @param PWMx PWM instance
1514 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1515 */
1516 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1517 {
1518 return (READ_REG(PWMx->CMPC0));
1519 }
1520
1521 /**
1522 * @brief Set the PWM compare counter C1.
1523 *
1524 * \rst
1525 * +----------------------+-----------------------------------+
1526 * | Register | BitsName |
1527 * +======================+===================================+
1528 * | CMPC1 | CMPC1 |
1529 * +----------------------+-----------------------------------+
1530 * \endrst
1531 *
1532 * @param PWMx PWM instance
1533 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1534 * @retval None
1535 */
1536 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1537 {
1538 WRITE_REG(PWMx->CMPC1, compare);
1539 }
1540
1541 /**
1542 * @brief Get the PWM compare counter C1.
1543 *
1544 * \rst
1545 * +----------------------+-----------------------------------+
1546 * | Register | BitsName |
1547 * +======================+===================================+
1548 * | CMPC1 | CMPC1 |
1549 * +----------------------+-----------------------------------+
1550 * \endrst
1551 *
1552 * @param PWMx PWM instance
1553 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1554 */
1555 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1556 {
1557 return (READ_REG(PWMx->CMPC1));
1558 }
1559
1560 /**
1561 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1562 *
1563 * \rst
1564 * +----------------------+-----------------------------------+
1565 * | Register | BitsName |
1566 * +======================+===================================+
1567 * | AQCTRL | A0 |
1568 * +----------------------+-----------------------------------+
1569 * \endrst
1570 *
1571 * @param PWMx PWM instance
1572 * @param action_event This parameter can be one of the following values:
1573 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1574 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1575 * @arg @ref LL_PWM_ACTIONEVENT_SET
1576 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1577 * @retval None
1578 */
1579 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1580 {
1581 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1582 }
1583
1584 /**
1585 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1586 *
1587 * \rst
1588 * +----------------------+-----------------------------------+
1589 * | Register | BitsName |
1590 * +======================+===================================+
1591 * | AQCTRL | A0 |
1592 * +----------------------+-----------------------------------+
1593 * \endrst
1594 *
1595 * @param PWMx PWM instance
1596 * @retval Return value can be one of the following values:
1597 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1598 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1599 * @arg @ref LL_PWM_ACTIONEVENT_SET
1600 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1601 */
1602 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1603 {
1604 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1605 }
1606
1607 /**
1608 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1609 *
1610 * \rst
1611 * +----------------------+-----------------------------------+
1612 * | Register | BitsName |
1613 * +======================+===================================+
1614 * | AQCTRL | A1 |
1615 * +----------------------+-----------------------------------+
1616 * \endrst
1617 *
1618 * @param PWMx PWM instance
1619 * @param action_event This parameter can be one of the following values:
1620 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1621 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1622 * @arg @ref LL_PWM_ACTIONEVENT_SET
1623 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1624 * @retval None
1625 */
1626 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1627 {
1628 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1629 }
1630
1631 /**
1632 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1633 *
1634 * \rst
1635 * +----------------------+-----------------------------------+
1636 * | Register | BitsName |
1637 * +======================+===================================+
1638 * | AQCTRL | A1 |
1639 * +----------------------+-----------------------------------+
1640 * \endrst
1641 *
1642 * @param PWMx PWM instance
1643 * @retval Return value can be one of the following values:
1644 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1645 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1646 * @arg @ref LL_PWM_ACTIONEVENT_SET
1647 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1648 */
1649 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1650 {
1651 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1652 }
1653
1654 /**
1655 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1656 *
1657 * \rst
1658 * +----------------------+-----------------------------------+
1659 * | Register | BitsName |
1660 * +======================+===================================+
1661 * | AQCTRL | B0 |
1662 * +----------------------+-----------------------------------+
1663 * \endrst
1664 *
1665 * @param PWMx PWM instance
1666 * @param action_event This parameter can be one of the following values:
1667 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1668 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1669 * @arg @ref LL_PWM_ACTIONEVENT_SET
1670 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1671 * @retval None
1672 */
1673 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1674 {
1675 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1676 }
1677
1678 /**
1679 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1680 *
1681 * \rst
1682 * +----------------------+-----------------------------------+
1683 * | Register | BitsName |
1684 * +======================+===================================+
1685 * | AQCTRL | B0 |
1686 * +----------------------+-----------------------------------+
1687 * \endrst
1688 *
1689 * @param PWMx PWM instance
1690 * @retval Return value can be one of the following values:
1691 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1692 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1693 * @arg @ref LL_PWM_ACTIONEVENT_SET
1694 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1695 */
1696 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1697 {
1698 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1699 }
1700
1701 /**
1702 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1703 *
1704 * \rst
1705 * +----------------------+-----------------------------------+
1706 * | Register | BitsName |
1707 * +======================+===================================+
1708 * | AQCTRL | B1 |
1709 * +----------------------+-----------------------------------+
1710 * \endrst
1711 *
1712 * @param PWMx PWM instance
1713 * @param action_event This parameter can be one of the following values:
1714 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1715 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1716 * @arg @ref LL_PWM_ACTIONEVENT_SET
1717 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1718 * @retval None
1719 */
1720 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1721 {
1722 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1723 }
1724
1725 /**
1726 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1727 *
1728 * \rst
1729 * +----------------------+-----------------------------------+
1730 * | Register | BitsName |
1731 * +======================+===================================+
1732 * | AQCTRL | B1 |
1733 * +----------------------+-----------------------------------+
1734 * \endrst
1735 *
1736 * @param PWMx PWM instance
1737 * @retval Return value can be one of the following values:
1738 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1739 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1740 * @arg @ref LL_PWM_ACTIONEVENT_SET
1741 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1742 */
1743 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1744 {
1745 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1746 }
1747
1748 /**
1749 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1750 *
1751 * \rst
1752 * +----------------------+-----------------------------------+
1753 * | Register | BitsName |
1754 * +======================+===================================+
1755 * | AQCTRL | C0 |
1756 * +----------------------+-----------------------------------+
1757 * \endrst
1758 *
1759 * @param PWMx PWM instance
1760 * @param action_event This parameter can be one of the following values:
1761 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1762 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1763 * @arg @ref LL_PWM_ACTIONEVENT_SET
1764 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1765 * @retval None
1766 */
1767 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1768 {
1769 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1770 }
1771
1772 /**
1773 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1774 *
1775 * \rst
1776 * +----------------------+-----------------------------------+
1777 * | Register | BitsName |
1778 * +======================+===================================+
1779 * | AQCTRL | C0 |
1780 * +----------------------+-----------------------------------+
1781 * \endrst
1782 *
1783 * @param PWMx PWM instance
1784 * @retval Return value can be one of the following values:
1785 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1786 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1787 * @arg @ref LL_PWM_ACTIONEVENT_SET
1788 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1789 */
1790 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1791 {
1792 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1793 }
1794
1795 /**
1796 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1797 *
1798 * \rst
1799 * +----------------------+-----------------------------------+
1800 * | Register | BitsName |
1801 * +======================+===================================+
1802 * | AQCTRL | C1 |
1803 * +----------------------+-----------------------------------+
1804 * \endrst
1805 *
1806 * @param PWMx PWM instance
1807 * @param action_event This parameter can be one of the following values:
1808 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1809 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1810 * @arg @ref LL_PWM_ACTIONEVENT_SET
1811 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1812 * @retval None
1813 */
1814 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1815 {
1816 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1817 }
1818
1819 /**
1820 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1821 *
1822 * \rst
1823 * +----------------------+-----------------------------------+
1824 * | Register | BitsName |
1825 * +======================+===================================+
1826 * | AQCTRL | C1 |
1827 * +----------------------+-----------------------------------+
1828 * \endrst
1829 *
1830 * @param PWMx PWM instance
1831 * @retval Return value can be one of the following values:
1832 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1833 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1834 * @arg @ref LL_PWM_ACTIONEVENT_SET
1835 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1836 */
1837 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1838 {
1839 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1840 }
1841
1842 /**
1843 * @brief Set the breath prescaler in breath mode.
1844 *
1845 * \rst
1846 * +----------------------+-----------------------------------+
1847 * | Register | BitsName |
1848 * +======================+===================================+
1849 * | BRPRD | BRPRD |
1850 * +----------------------+-----------------------------------+
1851 * \endrst
1852 *
1853 * @param PWMx PWM instance
1854 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1855 * @retval None
1856 */
1857 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1858 {
1859 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1860 }
1861
1862 /**
1863 * @brief Get the breath prescaler in breath mode.
1864 *
1865 * \rst
1866 * +----------------------+-----------------------------------+
1867 * | Register | BitsName |
1868 * +======================+===================================+
1869 * | BRPRD | BRPRD |
1870 * +----------------------+-----------------------------------+
1871 * \endrst
1872 *
1873 * @param PWMx PWM instance
1874 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1875 */
1876 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1877 {
1878 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1879 }
1880
1881 /**
1882 * @brief Set the hold prescaler in breath mode.
1883 *
1884 * \rst
1885 * +----------------------+-----------------------------------+
1886 * | Register | BitsName |
1887 * +======================+===================================+
1888 * | HOLD | HOLD |
1889 * +----------------------+-----------------------------------+
1890 * \endrst
1891 *
1892 * @param PWMx PWM instance
1893 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1894 * @retval None
1895 */
1896 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1897 {
1898 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1899 }
1900
1901 /**
1902 * @brief Get the hold prescaler in breath mode.
1903 *
1904 * \rst
1905 * +----------------------+-----------------------------------+
1906 * | Register | BitsName |
1907 * +======================+===================================+
1908 * | HOLD | HOLD |
1909 * +----------------------+-----------------------------------+
1910 * \endrst
1911 *
1912 * @param PWMx PWM instance
1913 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1914 */
1915 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1916 {
1917 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1918 }
1919
1920 /** @} */
1921
1922 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
1923 * @{
1924 */
1925
1926 /**
1927 * @brief De-initialize PWM registers (Registers restored to their default values).
1928 * @param PWMx PWM instance
1929 * @retval An error_status_t enumeration value:
1930 * - SUCCESS: PWM registers are de-initialized
1931 * - ERROR: PWM registers are not de-initialized
1932 */
1933 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
1934
1935 /**
1936 * @brief Initialize PWM registers according to the specified
1937 * parameters in PWM_InitStruct.
1938 * @param PWMx PWM instance
1939 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
1940 * information for the specified PWM peripheral.
1941 * @retval An error_status_t enumeration value:
1942 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
1943 * - ERROR: Problem occurred during PWM Registers initialization
1944 */
1945 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
1946
1947 /**
1948 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
1949 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
1950 * whose fields will be set to default values.
1951 * @retval None
1952 */
1953 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
1954
1955 /** @} */
1956
1957 /** @} */
1958
1959 #endif /* PWM0 || PWM1 */
1960
1961 #ifdef __cplusplus
1962 }
1963 #endif
1964
1965 #endif /* __GR55XX_LL_PWM_H__ */
1966
1967 /** @} */
1968
1969 /** @} */
1970
1971 /** @} */
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: gr55xx_ll_pwm.h:1035
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: gr55xx_ll_pwm.h:522
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1497
_ll_pwm_init_t::channel_c
ll_pwm_channel_init_t channel_c
Definition: gr55xx_ll_pwm.h:126
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1673
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: gr55xx_ll_pwm.h:1516
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1536
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1341
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1837
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: gr55xx_ll_pwm.h:94
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: gr55xx_ll_pwm.h:1263
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: gr55xx_ll_pwm.h:864
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: gr55xx_ll_pwm.h:617
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1321
ll_pwm_init
error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: gr55xx_ll_pwm.h:1360
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1876
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: gr55xx_ll_pwm.h:1206
ll_pwm_deinit
error_status_t ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
_ll_pwm_channel_init_t::drive_polarity
uint8_t drive_polarity
Definition: gr55xx_ll_pwm.h:82
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: gr55xx_ll_pwm.h:940
_ll_pwm_init_t::bprescaler
uint32_t bprescaler
Definition: gr55xx_ll_pwm.h:109
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: gr55xx_ll_pwm.h:1244
ll_pwm_enable_update_pause
__STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
Enable update pause.
Definition: gr55xx_ll_pwm.h:1073
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1579
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1380
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1477
ll_pwm_get_mode
__STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: gr55xx_ll_pwm.h:408
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: gr55xx_ll_pwm.h:655
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1720
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: gr55xx_ll_pwm.h:308
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: gr55xx_ll_pwm.h:978
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: gr55xx_ll_pwm.h:1696
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: gr55xx_ll_pwm.h:807
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: gr55xx_ll_pwm.h:327
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: gr55xx_ll_pwm.h:1282
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: gr55xx_ll_pwm.h:769
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: gr55xx_ll_pwm.h:883
_ll_pwm_init_t::mode
uint32_t mode
Definition: gr55xx_ll_pwm.h:95
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1438
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: gr55xx_ll_pwm.h:674
_ll_pwm_init_t::hprescaler
uint32_t hprescaler
Definition: gr55xx_ll_pwm.h:115
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: gr55xx_ll_pwm.h:1187
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1857
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: gr55xx_ll_pwm.h:365
_ll_pwm_init_t::channel_b
ll_pwm_channel_init_t channel_b
Definition: gr55xx_ll_pwm.h:123
ll_pwm_disable_update_pause
__STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
Disable update pause.
Definition: gr55xx_ll_pwm.h:1092
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: gr55xx_ll_pwm.h:1016
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: gr55xx_ll_pwm.h:921
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: gr55xx_ll_pwm.h:346
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: gr55xx_ll_pwm.h:465
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: gr55xx_ll_pwm.h:1814
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: gr55xx_ll_pwm.h:1399
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: gr55xx_ll_pwm.h:712
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: gr55xx_ll_pwm.h:1168
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: gr55xx_ll_pwm.h:845
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: gr55xx_ll_pwm.h:902
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: gr55xx_ll_pwm.h:693
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1915
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: gr55xx_ll_pwm.h:750
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: gr55xx_ll_pwm.h:1130
_ll_pwm_init_t::align
uint32_t align
Definition: gr55xx_ll_pwm.h:100
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: gr55xx_ll_pwm.h:731
ll_pwm_channel_init_t
struct _ll_pwm_channel_init_t ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: gr55xx_ll_pwm.h:1225
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1649
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: gr55xx_ll_pwm.h:636
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: gr55xx_ll_pwm.h:598
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: gr55xx_ll_pwm.h:1896
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: gr55xx_ll_pwm.h:997
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:560
_ll_pwm_init_t::channel_a
ll_pwm_channel_init_t channel_a
Definition: gr55xx_ll_pwm.h:120
_ll_pwm_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: gr55xx_ll_pwm.h:75
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: gr55xx_ll_pwm.h:1458
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: gr55xx_ll_pwm.h:1054
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:484
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: gr55xx_ll_pwm.h:270
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: gr55xx_ll_pwm.h:503
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: gr55xx_ll_pwm.h:289
_ll_pwm_init_t::prescaler
uint32_t prescaler
Definition: gr55xx_ll_pwm.h:103
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: gr55xx_ll_pwm.h:1419
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:446
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1767
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: gr55xx_ll_pwm.h:541
ll_pwm_is_enabled_update_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
Indicate whether the update pause is enabled.
Definition: gr55xx_ll_pwm.h:1111
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: gr55xx_ll_pwm.h:1626
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: gr55xx_ll_pwm.h:1555
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: gr55xx_ll_pwm.h:1149
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: gr55xx_ll_pwm.h:1602
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: gr55xx_ll_pwm.h:788
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: gr55xx_ll_pwm.h:1302
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: gr55xx_ll_pwm.h:1743
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: gr55xx_ll_pwm.h:959
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: gr55xx_ll_pwm.h:579
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
Set PWM mode.
Definition: gr55xx_ll_pwm.h:387
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: gr55xx_ll_pwm.h:826
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: gr55xx_ll_pwm.h:1790
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: gr55xx_ll_pwm.h:427
_ll_pwm_channel_init_t::duty
uint8_t duty
Definition: gr55xx_ll_pwm.h:76