Collaboration diagram for DUAL TIMER Prescaler Division:Macros | |
| #define | DUAL_TIMER_PRESCALER_DIV0 LL_DUAL_TIMER_PRESCALER_DIV0 |
| 0 stage of prescale, clock is divided by 1. More... | |
| #define | DUAL_TIMER_PRESCALER_DIV16 LL_DUAL_TIMER_PRESCALER_DIV16 |
| 4 stages of prescale, clock is divided by 16. More... | |
| #define | DUAL_TIMER_PRESCALER_DIV256 LL_DUAL_TIMER_PRESCALER_DIV256 |
| 8 stages of prescale, clock is divided by 256. More... | |
| #define DUAL_TIMER_PRESCALER_DIV0 LL_DUAL_TIMER_PRESCALER_DIV0 |
| #define DUAL_TIMER_PRESCALER_DIV16 LL_DUAL_TIMER_PRESCALER_DIV16 |
| #define DUAL_TIMER_PRESCALER_DIV256 LL_DUAL_TIMER_PRESCALER_DIV256 |
8 stages of prescale, clock is divided by 256.
Definition at line 170 of file gr55xx_hal_dual_tim.h.