52 #ifndef __GR55XX_LL_BOD_H_
53 #define __GR55XX_LL_BOD_H_
107 #define LL_BOD_ENABLE 0x1
108 #define LL_BOD_DISABLE 0x0
114 #define LL_BOD2_ENABLE 0x1
115 #define LL_BOD2_DISABLE 0x0
121 #define LL_BOD2_LEVEL_0 0x0
122 #define LL_BOD2_LEVEL_1 0x1
123 #define LL_BOD2_LEVEL_2 0x2
124 #define LL_BOD2_LEVEL_3 0x3
125 #define LL_BOD2_LEVEL_4 0x4
126 #define LL_BOD2_LEVEL_5 0x5
127 #define LL_BOD2_LEVEL_6 0x6
128 #define LL_BOD2_LEVEL_7 0x7
129 #define LL_BOD2_LEVEL_8 0x8
130 #define LL_BOD2_LEVEL_9 0x9
131 #define LL_BOD2_LEVEL_10 0xA
132 #define LL_BOD2_LEVEL_11 0xB
133 #define LL_BOD2_LEVEL_12 0xC
134 #define LL_BOD2_LEVEL_13 0xD
135 #define LL_BOD2_LEVEL_14 0xE
136 #define LL_BOD2_LEVEL_15 0xF
156 #if defined(BIT_BAND_SUPPORT)
157 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 1;
159 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
173 #if defined(BIT_BAND_SUPPORT)
174 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 0;
176 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
190 #if defined(BIT_BAND_SUPPORT)
191 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 1;
193 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
207 #if defined(BIT_BAND_SUPPORT)
208 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 0;
210 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
224 #if defined(BIT_BAND_SUPPORT)
225 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos) = (lvl_ctrl_lv & 0x01);
226 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+1) = ((lvl_ctrl_lv>>1) & 0x01);
227 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+2) = ((lvl_ctrl_lv>>2) & 0x01);
228 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+3) = ((lvl_ctrl_lv>>3) & 0x01);
230 MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV, (lvl_ctrl_lv << AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos));
243 #if defined(BIT_BAND_SUPPORT)
244 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 1;
246 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
259 #if defined(BIT_BAND_SUPPORT)
260 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 0;
262 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
277 SET_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
291 CLEAR_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
306 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD) == AON_CTL_AON_IRQ_PMU_BOD);
320 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD);
334 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_PMU_BOD) == AON_CTL_SLP_EVENT_PMU_BOD);
348 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_PMU_BOD);