gr55xx_ll_aon_pmu.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_aon_pmu.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of PMU LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_PMU AON_PMU
47  * @brief PMU LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_PMU_H_
53 #define __GR55XX_LL_PMU_H_
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal.h"
61 
62 /** @defgroup LL_PMU_DRIVER_FUNCTIONS Functions
63  * @{
64  */
65 /**
66  * @brief Enable the RTC
67  *
68  * Register|BitsName
69  * --------|--------
70  * RF_REG_0 | RTC_EN
71  *
72  * @retval None
73  *
74  */
75 __STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
76 {
77  SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
78 }
79 
80 /**
81  * @brief Disable the RTC
82  *
83  * Register|BitsName
84  * --------|--------
85  * RF_REG_0 | RTC_EN
86  *
87  */
88 __STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
89 {
90  CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
91 }
92 
93 /**
94  * @brief Set RTC GM
95  *
96  * Register|BitsName
97  * --------|--------
98  * RF_REG_0 | EN
99  *
100  * @param value: The rtc gm value.
101  *
102  */
103 __STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
104 {
105  MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_GM, (value << AON_PMU_RF_REG_0_RTC_GM_Pos));
106 }
107 
108 /**
109  * @brief Set lv,default is set to 1.8V,LSB = 8.5mv
110  *
111  * Register|BitsName
112  * --------|--------
113  * RF_REG_0 | EN
114  *
115  * @param value: The io ldo vout value.
116  *
117  */
118 __STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
119 {
120  MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1, (value << AON_PMU_RF_REG_0_IO_LDO_REG1_Pos));
121 }
122 
123 /**
124  * @brief Set retention level
125  *
126  * Register|BitsName
127  * --------|--------
128  * RF_REG_0 | ctrl_ret
129  *
130  * @param value: The retention level value.
131  *
132  */
133 __STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
134 {
135  MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET, (value << AON_PMU_RF_REG_0_CTRL_RET_Pos));
136 }
137 
138 /**
139  * @brief Get retention level
140  *
141  * Register|BitsName
142  * --------|--------
143  * RF_REG_0 | ctrl_ret
144  *
145  * @retval The current retention level.
146  *
147  */
148 __STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
149 {
150  return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_CTRL_RET) >> AON_PMU_RF_REG_0_CTRL_RET_Pos);
151 }
152 
153 /**
154  * @brief Set dcdc the ton value
155  *
156  * Register|BitsName
157  * --------|--------
158  * RF_REG_1 | TON
159  *
160  * @param value: The dcdc ton value.
161  *
162  */
163 __STATIC_INLINE void ll_aon_pmu_set_dcdc_ton(uint32_t value)
164 {
165  MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_TON, (value << AON_PMU_RF_REG_1_TON_Pos));
166 }
167 
168 /**
169  * @brief Get dcdc the ton value
170  *
171  * Register|BitsName
172  * --------|--------
173  * RF_REG_1 | TON
174  *
175  * @retval The dcdc ton value.
176  *
177  */
178 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_ton(void)
179 {
180  return (READ_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_TON) >> AON_PMU_RF_REG_1_TON_Pos);
181 }
182 
183 /**
184  * @brief Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
185  *
186  * Register|BitsName
187  * --------|--------
188  * RF_REG_4 | AON_PMU_RF_REG_4_DCDC_VREF
189  *
190  * @param value: the dcdc vreg value.
191  *
192  */
193 __STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
194 {
195  MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DCDC_VREF, (value << AON_PMU_RF_REG_4_DCDC_VREF_Pos));
196 }
197 
198 /**
199  * @brief Get dcdc vreg
200  *
201  * Register|BitsName
202  * --------|--------
203  * RF_REG_4 | AON_PMU_RF_REG_4_DCDC_VREF
204  *
205  * @retval The dcdc vreg value.
206  *
207  */
208 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
209 {
210  return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DCDC_VREF) >> AON_PMU_RF_REG_4_DCDC_VREF_Pos);
211 }
212 
213 /**
214  * @brief Set dcdc reg_sel_aon_pmu_dcore_vref, default from AON.
215  *
216  * Register|BitsName
217  * --------|--------
218  * PMU_DCORE_VREF | REG_SEL_AON_PMU_DCORE_VREF
219  *
220  * @param sel: the dcore vref source control.
221  *
222  */
223 __STATIC_INLINE void ll_aon_pmu_set_dcore_sel(uint8_t sel)
224 {
225  MODIFY_REG(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_SEL, (sel << AON_PMU_DCORE_VREF_REG_SEL_Pos));
226 }
227 
228 
229 /**
230  * @brief Enable the io ldo bypass
231  *
232  * Register|BitsName
233  * --------|--------
234  * RF_REG_3 | BYPASS_EN
235  *
236  */
237 __STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
238 {
239  SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_IO_LDO_BYPASS);
240 }
241 
242 /**
243  * @brief Disable the io ldo bypass
244  *
245  * Register|BitsName
246  * --------|--------
247  * RF_REG_3 | BYPASS_EN
248  *
249  */
250 __STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
251 {
252  CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_IO_LDO_BYPASS);
253 }
254 
255 
256 /**
257  * @brief Enable the dig ldo bleed
258  *
259  * Register|BitsName
260  * --------|--------
261  * RF_REG_4 | EN
262  *
263  */
264 __STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
265 {
266  SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
267 }
268 
269 /**
270  * @brief Disable the dig ldo bleed
271  *
272  * Register|BitsName
273  * --------|--------
274  * RF_REG_4 | EN
275  *
276  */
277 __STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
278 {
279  CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
280 }
281 
282 /**
283  * @brief Set dig ldo out
284  *
285  * Register|BitsName
286  * --------|--------
287  * PMU_DCORE_VREF | DIG_LDO_OUT
288  *
289  * @param value: The dig ldo out value.
290  *
291  */
292 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
293 {
294  MODIFY_REG(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_DIG_OUT, (value << AON_PMU_DCORE_VREF_REG_DIG_OUT_Pos));
295 }
296 
297 /**
298  * @brief Get dig ldo out value
299  *
300  * Register|BitsName
301  * --------|--------
302  * PMU_DCORE_VREF | DIG_LDO_OUT
303  *
304  *
305  */
306 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
307 {
308  return (READ_BITS(AON_PMU->PMU_DCORE_VREF, AON_PMU_DCORE_VREF_REG_DIG_OUT) >> AON_PMU_DCORE_VREF_REG_DIG_OUT_Pos);
309 }
310 
311 /**
312  * @brief Enable the dig ldo bypass
313  *
314  * Register|BitsName
315  * --------|--------
316  * RF_REG_4 | BYPASS_EN
317  *
318  */
319 __STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
320 {
321  SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
322 }
323 
324 /**
325  * @brief Disable the dig ldo bypass
326  *
327  * Register|BitsName
328  * --------|--------
329  * RF_REG_4 | BYPASS_EN
330  *
331  */
332 __STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
333 {
334  CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN);
335 }
336 
337 /**
338  * @brief Set the dig ldo bypass
339  *
340  * Register|BitsName
341  * --------|--------
342  * RF_REG_4 | BYPASS_EN
343  *
344  */
345 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
346 {
347  MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN, (enable << AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos));
348 }
349 
350 /**
351  * @brief Get the dig ldo bypass
352  *
353  * Register|BitsName
354  * --------|--------
355  * RF_REG_4 | BYPASS_EN
356  *
357  * @retval The dig ldo bypass enable value.
358  *
359  */
360 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
361 {
362  return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN) >> AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos);
363 }
364 
365 /**
366  * @brief Set clk period
367  *
368  * Register|BitsName
369  * --------|--------
370  * RF_REG_4 | CLK_PERIOD
371  *
372  * @param value: The clock period value.
373  * @retval None
374  *
375  */
376 __STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
377 {
378  MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CLK_PERIOD, (value << AON_PMU_RF_REG_4_CLK_PERIOD_Pos));
379 }
380 
381 /**
382  * @brief Get clk period
383  *
384  * Register|BitsName
385  * --------|--------
386  * RF_REG_4 | CLK_PERIOD
387  *
388  * @retval The clock period value.
389  *
390  */
391 __STATIC_INLINE uint32_t ll_aon_pmu_get_clk_period(void)
392 {
393  return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_CLK_PERIOD) >> AON_PMU_RF_REG_4_CLK_PERIOD_Pos);
394 }
395 
396 /**
397  * @brief Enables clock injection from XO to ring oscillator.
398  *
399  * Register|BitsName
400  * --------|--------
401  * RF_REG_1 | EN_INJ_ON
402  *
403  * @retval None
404  *
405  */
406 __STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
407 {
408  SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_EN_INJ_ON);
409 }
410 
411 /**
412  * @brief Disables clock injection from XO to ring oscillator.
413  *
414  * Register|BitsName
415  * --------|--------
416  * RF_REG_1 | EN_INJ_ON
417  *
418  * @retval None
419  *
420  */
421 __STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
422 {
423  CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_EN_INJ_ON);
424 }
425 
426 /**
427  * @brief Enable the dcdc ton startup
428  *
429  * Register|BitsName
430  * --------|--------
431  * DCDC_LDO_REG_0 | TON_STARTUP
432  *
433  */
434 __STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
435 {
436  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TON_STARTUP);
437 }
438 
439 /**
440  * @brief Enable clock detection override
441  *
442  * Register|BitsName
443  * --------|--------
444  * DCDC_LDO_REG_0 | CLK_DET_OVR
445  *
446  * @retval None
447  *
448  */
449 __STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr(void)
450 {
451  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR);
452 }
453 
454 /**
455  * @brief Disable clock detection override
456  *
457  * Register|BitsName
458  * --------|--------
459  * DCDC_LDO_REG_0 | CLK_DET_OVR
460  *
461  * @retval None
462  *
463  */
464 __STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr(void)
465 {
466  CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR);
467 }
468 
469 
470 /**
471  * @brief Enable clock detection override source as XO
472  *
473  * Register|BitsName
474  * --------|--------
475  * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
476  *
477  * @retval None
478  *
479  */
480 __STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr_src_xo(void)
481 {
482  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC);
483 }
484 
485 /**
486  * @brief Disable clock detection override source XO ---- means set as RING
487  *
488  * Register|BitsName
489  * --------|--------
490  * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
491  *
492  * @retval None
493  *
494  */
495 __STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr_src_xo(void)
496 {
497  CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC);
498 }
499 
500 /**
501  * @brief Set clock detection override source
502  *
503  * Register|BitsName
504  * --------|--------
505  * DCDC_LDO_REG_0 | CLK_DET_OVR_SRC
506  *
507  * @param value: the clock detection override source value.
508  * @retval None
509  *
510  */
511 __STATIC_INLINE void ll_aon_pmu_set_clk_det_ovr_src(uint32_t value)
512 {
513  MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC, (value << AON_PMU_DCDC_LDO_REG0_CLK_DET_OVR_SRC_Pos));
514 }
515 
516 
517 /**
518  * @brief Enable use_xo
519  *
520  * Register|BitsName
521  * --------|--------
522  * DCDC_LDO_REG_0 | USE_XO
523  *
524  * @retval None
525  *
526  */
527 __STATIC_INLINE void ll_aon_pmu_enable_use_xo(void)
528 {
529  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_USE_XO);
530 }
531 
532 /**
533  * @brief Disable use_xo
534  *
535  * Register|BitsName
536  * --------|--------
537  * DCDC_LDO_REG_0 | USE_XO
538  *
539  * @retval None
540  *
541  */
542 __STATIC_INLINE void ll_aon_pmu_disable_use_xo(void)
543 {
544  CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_USE_XO);
545 }
546 
547 
548 /**
549  * @brief Enable the digital io ldo.
550  *
551  * Register|BitsName
552  * --------|--------
553  * DCDC_LDO_REG_0 | EN_DIG_IO_LDO
554  *
555  * @retval None
556  *
557  */
558 __STATIC_INLINE void ll_aon_pmu_enable_dig_io_ldo(void)
559 {
560  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_EN_DIG_IO_LDO);
561 }
562 
563 /**
564  * @brief Disable the tristate ldo.
565  *
566  * Register|BitsName
567  * --------|--------
568  * DCDC_LDO_REG_0 | TRISTATE_LD
569  *
570  * @retval None
571  *
572  */
573 __STATIC_INLINE void ll_aon_pmu_disable_tristate_ldo(void)
574 {
575  CLEAR_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TRISTATE_LDO);
576 }
577 
578 /**
579  * @brief Disable the tristate analog ldo.
580  *
581  * Register|BitsName
582  * --------|--------
583  * DCDC_LDO_REG_0 | TRISTATE_ANA_IO_LDO
584  *
585  * @retval None
586  *
587  */
588 __STATIC_INLINE void ll_aon_pmu_enable_tristate_ana_io_ldo(void)
589 {
590  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_TRISTATE_ANA_IO_LDO);
591 }
592 
593 /**
594  * @brief Set ldo control_override.
595  *
596  * Register|BitsName
597  * --------|--------
598  * DCDC_LDO_REG_0 | REG0_LDO_CTRL_OV
599  *
600  * @retval None
601  *
602  */
603 __STATIC_INLINE void ll_aon_pmu_set_ldo_control_override(void)
604 {
605  SET_BITS(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_LDO_CTRL_OV);
606 }
607 
608 /**
609  * @brief Set boost step.
610  *
611  * Register|BitsName
612  * --------|--------
613  * DCDC_LDO_REG_0 | BOOST_STEP
614  *
615  * @param value: The boost step value.
616  * @retval None
617  *
618  */
619 __STATIC_INLINE void ll_aon_pmu_set_boost_step(uint32_t value)
620 {
621  MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_BOOST_STEP, (value << AON_PMU_DCDC_LDO_REG0_BOOST_STEP_Pos));
622 }
623 
624 /**
625  * @brief Set digital io ldo divider.
626  *
627  * Register|BitsName
628  * --------|--------
629  * DCDC_LDO_REG_0 | CLK_DIV_SEL
630  *
631  * @param value: The dig ldo div value.
632  * @retval None
633  *
634  */
635 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_div(uint32_t value)
636 {
637  MODIFY_REG(AON_PMU->DCDC_LDO_REG_0, AON_PMU_DCDC_LDO_REG0_CLK_DIV_SEL, (value << AON_PMU_DCDC_LDO_REG0_CLK_DIV_SEL_Pos));
638 }
639 
640 /**
641  * @brief Set the rtc cur cap
642  *
643  * Register|BitsName
644  * --------|--------
645  * RC_RTC_REG_0 | RTC_CAP
646  *
647  * @param value: The rtc current cap value.
648  *
649  */
650 __STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
651 {
652  MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CS, (value << AON_PMU_RC_RTC_REG0_RTC_CS_Pos));
653 }
654 /**
655  * @brief Set the rtc on MSIO A6/7 en pad sw
656  *
657  * Register|BitsName
658  * --------|--------
659  * RC_RTC_REG_0 | EN_PAD_SW
660  *
661  *
662  */
663 __STATIC_INLINE void ll_aon_pmu_enable_pad_sw(void)
664 {
665  SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_EN_PAD_SW);
666 }
667 
668 
669 /**
670  * @brief Set clock detection option
671  *
672  * Register|BitsName
673  * --------|--------
674  * RC_RTC_REG_0 | CLK_DET_OPT
675  *
676  * @param value: clock detection option value, 0: use clk_det, 1: use glitch free MUX.
677  * @retval None
678  *
679  */
680 __STATIC_INLINE void ll_aon_pmu_set_clk_det_opt(uint32_t value)
681 {
682  MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_CLK_DET_OPT, (value << AON_PMU_RC_RTC_REG0_CLK_DET_OPT_Pos));
683 }
684 
685 /**
686  * @brief Set the rtc cur cap
687  *
688  * Register|BitsName
689  * --------|--------
690  * RC_RTC_REG_0 | RTC_CAP
691  *
692  * @param value: The rtc current cap value.
693  *
694  */
695 __STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
696 {
697  MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP, (value << AON_PMU_RC_RTC_REG0_RTC_CAP_Pos));
698 }
699 
700 /**
701  * @brief Get the rtc cur cap
702  *
703  * Register|BitsName
704  * --------|--------
705  * RC_RTC_REG_0 | RTC_CAP
706  *
707  * @retval The rtc current cap value.
708  *
709  */
710 __STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
711 {
712  return (READ_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP) >> AON_PMU_RC_RTC_REG0_RTC_CAP_Pos);
713 }
714 
715 /**
716  * @brief Enable the RCOSC
717  *
718  * Register|BitsName
719  * --------|--------
720  * RC_RTC_REG_0 | RCOSC
721  *
722  */
723 __STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
724 {
725  SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
726 }
727 
728 /**
729  * @brief Disable the RCOSC
730  *
731  * Register|BitsName
732  * --------|--------
733  * RC_RTC_REG_0 | RCOSC
734  *
735  */
736 __STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
737 {
738  CLEAR_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
739 }
740 
741 /**
742  * @brief enable the ret ldo
743  *
744  * Register|BitsName
745  * --------|--------
746  * RET_LDO_REG | RET_LDO_EN
747  *
748  */
749 __STATIC_INLINE void ll_aon_pmu_enable_ret_ldo(void)
750 {
751  SET_BITS(AON_PMU->RET_LDO, AON_PMU_RET_LDO_EN);
752 }
753 
754 /**
755  * @brief modify ret ldo ctrl level
756  *
757  * Register|BitsName
758  * --------|--------
759  * RET_LDO_REG | RET_LDO_CTRL_5_1
760  *
761  */
762 __STATIC_INLINE void ll_aon_pmu_set_ret_ldo_ctrl_lvl(uint32_t value)
763 {
764  MODIFY_REG(AON_PMU->RET_LDO, AON_PMU_RET_LDO_OUT, (value << AON_PMU_RET_LDO_OUT_Pos));
765 }
766 
767 /**
768  * @brief modify lpd active
769  *
770  * Register|BitsName
771  * --------|--------
772  * PMU_LPD_CFG | LPD_VAON_ACTIVE
773  *
774  */
775 __STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
776 {
777  MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_ACTIVE, (value << AON_PMU_LPD_VAON_ACTIVE_Pos));
778 }
779 
780 /**
781  * @brief Get lpd active value
782  *
783  * Register|BitsName
784  * --------|--------
785  * PMU_LPD_CFG | LPD_VAON_ACTIVE
786  *
787  * @retval The current lpd active value.
788  *
789  */
790 __STATIC_INLINE uint32_t ll_aon_pmu_get_lpd_active(void)
791 {
792  return (READ_BITS(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_ACTIVE) >> AON_PMU_LPD_VAON_ACTIVE_Pos);
793 }
794 
795 /**
796  * @brief modify lpd sleep
797  *
798  * Register|BitsName
799  * --------|--------
800  * PMU_LPD_CFG | LPD_VAON_SLEEP
801  *
802  */
803 __STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
804 {
805  MODIFY_REG(AON_PMU->PMU_LPD_CFG, AON_PMU_LPD_VAON_SLEEP, (value << AON_PMU_LPD_VAON_SLEEP_Pos));
806 }
807 /**
808  * @brief modify ton on
809  *
810  * Register|BitsName
811  * --------|--------
812  * PMU_TON_CFG | AON_PMU_TON_CTRL_ON
813  *
814  */
815 __STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
816 {
817  MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_ON, (value << AON_PMU_TON_CTRL_ON_Pos));
818 }
819 /**
820  * @brief modify ton off
821  *
822  * Register|BitsName
823  * --------|--------
824  * PMU_TON_CFG | AON_PMU_TON_CTRL_OFF
825  *
826  */
827 __STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
828 {
829  MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_OFF, (value << AON_PMU_TON_CTRL_OFF_Pos));
830 }
831 /**
832  * @brief set rng freq
833  *
834  * Register|BitsName
835  * --------|--------
836  * RF_REG0 | AON_PMU_RF_REG_0_RNG_FREQ_CONT
837  *
838  */
839 __STATIC_INLINE void ll_aon_pmu_set_rng_req(uint32_t value)
840 {
841  MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_FREQ_CONT, (value << AON_PMU_RF_REG_0_RNG_FREQ_CONT_Pos));
842 }
843 /**
844  * @brief set rng freq
845  *
846  * Register|BitsName
847  * --------|--------
848  * RF_REG0 | AON_PMU_RF_REG_0_RNG_FREQ_CONT
849  *
850  */
851 __STATIC_INLINE void ll_aon_pmu_set_rng_freq_bump_enable(void)
852 {
853  SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RNG_FREQ_BUMP);
854 }
855 /**
856  * @brief Enable short aon digcore
857  *
858  * Register|BitsName
859  * --------|--------
860  * RF_REG2 | SHORT_AON_DIGCORE
861  *
862  * @retval None
863  *
864  */
865 __STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
866 {
867  SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_SHORT_AON_DIGCORE);
868 }
869 
870 /**
871  * @brief Disable short aon digcore
872  *
873  * Register|BitsName
874  * --------|--------
875  * RF_REG2 | SHORT_AON_DIGCORE
876  *
877  * @retval None
878  *
879  */
880 __STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
881 {
882  CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_SHORT_AON_DIGCORE);
883 }
884 /** @} */
885 
886 #endif
887 
888 /** @} */
889 
890 /** @} */
891 
892 /** @} */
ll_aon_pmu_enable_clk_det_ovr_src_xo
__STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr_src_xo(void)
Enable clock detection override source as XO.
Definition: gr55xx_ll_aon_pmu.h:480
ll_aon_pmu_disable_clk_inject
__STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
Disables clock injection from XO to ring oscillator.
Definition: gr55xx_ll_aon_pmu.h:421
ll_aon_pmu_set_clk_det_ovr_src
__STATIC_INLINE void ll_aon_pmu_set_clk_det_ovr_src(uint32_t value)
Set clock detection override source.
Definition: gr55xx_ll_aon_pmu.h:511
ll_aon_pmu_disable_clk_det_ovr_src_xo
__STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr_src_xo(void)
Disable clock detection override source XO —- means set as RING.
Definition: gr55xx_ll_aon_pmu.h:495
ll_aon_pmu_set_clk_det_opt
__STATIC_INLINE void ll_aon_pmu_set_clk_det_opt(uint32_t value)
Set clock detection option.
Definition: gr55xx_ll_aon_pmu.h:680
ll_aon_pmu_set_dig_ldo_div
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_div(uint32_t value)
Set digital io ldo divider.
Definition: gr55xx_ll_aon_pmu.h:635
ll_aon_pmu_set_clk_period
__STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
Set clk period.
Definition: gr55xx_ll_aon_pmu.h:376
ll_aon_pmu_enable_pad_sw
__STATIC_INLINE void ll_aon_pmu_enable_pad_sw(void)
Set the rtc on MSIO A6/7 en pad sw.
Definition: gr55xx_ll_aon_pmu.h:663
ll_aon_pmu_set_lpd_active
__STATIC_FORCEINLINE void ll_aon_pmu_set_lpd_active(uint32_t value)
modify lpd active
Definition: gr55xx_ll_aon_pmu.h:775
ll_aon_pmu_enable_clk_det_ovr
__STATIC_INLINE void ll_aon_pmu_enable_clk_det_ovr(void)
Enable clock detection override.
Definition: gr55xx_ll_aon_pmu.h:449
ll_aon_pmu_set_retention_level
__STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
Set retention level.
Definition: gr55xx_ll_aon_pmu.h:133
ll_aon_pmu_get_retention_level
__STATIC_INLINE uint32_t ll_aon_pmu_get_retention_level(void)
Get retention level.
Definition: gr55xx_ll_aon_pmu.h:148
ll_aon_pmu_get_lpd_active
__STATIC_INLINE uint32_t ll_aon_pmu_get_lpd_active(void)
Get lpd active value.
Definition: gr55xx_ll_aon_pmu.h:790
ll_aon_pmu_enable_ton_startup_overide
__STATIC_INLINE void ll_aon_pmu_enable_ton_startup_overide(void)
Enable the dcdc ton startup.
Definition: gr55xx_ll_aon_pmu.h:434
ll_aon_pmu_enable_bleed
__STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
Enable the dig ldo bleed.
Definition: gr55xx_ll_aon_pmu.h:264
ll_aon_pmu_set_dcore_sel
__STATIC_INLINE void ll_aon_pmu_set_dcore_sel(uint8_t sel)
Set dcdc reg_sel_aon_pmu_dcore_vref, default from AON.
Definition: gr55xx_ll_aon_pmu.h:223
ll_aon_pmu_set_ldo_control_override
__STATIC_INLINE void ll_aon_pmu_set_ldo_control_override(void)
Set ldo control_override.
Definition: gr55xx_ll_aon_pmu.h:603
ll_aon_pmu_disable_rcosc
__STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
Disable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:736
ll_aon_pmu_set_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
modify ton on
Definition: gr55xx_ll_aon_pmu.h:815
ll_aon_pmu_disable_clk_det_ovr
__STATIC_INLINE void ll_aon_pmu_disable_clk_det_ovr(void)
Disable clock detection override.
Definition: gr55xx_ll_aon_pmu.h:464
ll_aon_pmu_disable_tristate_ldo
__STATIC_INLINE void ll_aon_pmu_disable_tristate_ldo(void)
Disable the tristate ldo.
Definition: gr55xx_ll_aon_pmu.h:573
ll_aon_pmu_set_rtc_cs
__STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:650
ll_aon_pmu_set_lpd_sleep
__STATIC_INLINE void ll_aon_pmu_set_lpd_sleep(uint32_t value)
modify lpd sleep
Definition: gr55xx_ll_aon_pmu.h:803
ll_aon_pmu_enable_rtc
__STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
Enable the RTC.
Definition: gr55xx_ll_aon_pmu.h:75
ll_aon_pmu_disable_use_xo
__STATIC_INLINE void ll_aon_pmu_disable_use_xo(void)
Disable use_xo.
Definition: gr55xx_ll_aon_pmu.h:542
ll_aon_pmu_disable_bleed
__STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
Disable the dig ldo bleed.
Definition: gr55xx_ll_aon_pmu.h:277
ll_aon_pmu_enable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
Enable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:237
ll_aon_pmu_get_dcdc_ton
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_ton(void)
Get dcdc the ton value.
Definition: gr55xx_ll_aon_pmu.h:178
ll_aon_pmu_enable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_dig_ldo_bypass(void)
Enable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:319
ll_aon_pmu_set_ret_ldo_ctrl_lvl
__STATIC_INLINE void ll_aon_pmu_set_ret_ldo_ctrl_lvl(uint32_t value)
modify ret ldo ctrl level
Definition: gr55xx_ll_aon_pmu.h:762
ll_aon_pmu_enable_rcosc
__STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
Enable the RCOSC.
Definition: gr55xx_ll_aon_pmu.h:723
ll_aon_pmu_set_rng_freq_bump_enable
__STATIC_INLINE void ll_aon_pmu_set_rng_freq_bump_enable(void)
set rng freq
Definition: gr55xx_ll_aon_pmu.h:851
ll_aon_pmu_enable_ret_ldo
__STATIC_INLINE void ll_aon_pmu_enable_ret_ldo(void)
enable the ret ldo
Definition: gr55xx_ll_aon_pmu.h:749
ll_aon_pmu_set_rtc_gm
__STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
Set RTC GM.
Definition: gr55xx_ll_aon_pmu.h:103
ll_aon_pmu_set_dcdc_ton
__STATIC_INLINE void ll_aon_pmu_set_dcdc_ton(uint32_t value)
Set dcdc the ton value.
Definition: gr55xx_ll_aon_pmu.h:163
ll_aon_pmu_disable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_disable_short_aon_digcore(void)
Disable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:880
ll_aon_pmu_set_dig_ldo_out
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out(uint32_t value)
Set dig ldo out.
Definition: gr55xx_ll_aon_pmu.h:292
ll_aon_pmu_get_dig_ldo_out
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out(void)
Get dig ldo out value.
Definition: gr55xx_ll_aon_pmu.h:306
ll_aon_pmu_disable_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_dig_ldo_bypass(void)
Disable the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:332
ll_aon_pmu_set_rtc_cap
__STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
Set the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:695
ll_aon_pmu_disable_rtc
__STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
Disable the RTC.
Definition: gr55xx_ll_aon_pmu.h:88
gr55xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_aon_pmu_enable_short_aon_digcore
__STATIC_FORCEINLINE void ll_aon_pmu_enable_short_aon_digcore(void)
Enable short aon digcore.
Definition: gr55xx_ll_aon_pmu.h:865
ll_aon_pmu_get_rtc_cap
__STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
Get the rtc cur cap.
Definition: gr55xx_ll_aon_pmu.h:710
ll_aon_pmu_set_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
Set the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:345
ll_aon_pmu_set_non_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
modify ton off
Definition: gr55xx_ll_aon_pmu.h:827
ll_aon_pmu_set_rng_req
__STATIC_INLINE void ll_aon_pmu_set_rng_req(uint32_t value)
set rng freq
Definition: gr55xx_ll_aon_pmu.h:839
ll_aon_pmu_set_boost_step
__STATIC_INLINE void ll_aon_pmu_set_boost_step(uint32_t value)
Set boost step.
Definition: gr55xx_ll_aon_pmu.h:619
ll_aon_pmu_get_clk_period
__STATIC_INLINE uint32_t ll_aon_pmu_get_clk_period(void)
Get clk period.
Definition: gr55xx_ll_aon_pmu.h:391
ll_aon_pmu_enable_dig_io_ldo
__STATIC_INLINE void ll_aon_pmu_enable_dig_io_ldo(void)
Enable the digital io ldo.
Definition: gr55xx_ll_aon_pmu.h:558
ll_aon_pmu_set_io_ldo_vout
__STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
Set lv,default is set to 1.8V,LSB = 8.5mv.
Definition: gr55xx_ll_aon_pmu.h:118
ll_aon_pmu_disable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
Disable the io ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:250
ll_aon_pmu_enable_use_xo
__STATIC_INLINE void ll_aon_pmu_enable_use_xo(void)
Enable use_xo.
Definition: gr55xx_ll_aon_pmu.h:527
ll_aon_pmu_enable_clk_inject
__STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
Enables clock injection from XO to ring oscillator.
Definition: gr55xx_ll_aon_pmu.h:406
ll_aon_pmu_enable_tristate_ana_io_ldo
__STATIC_INLINE void ll_aon_pmu_enable_tristate_ana_io_ldo(void)
Disable the tristate analog ldo.
Definition: gr55xx_ll_aon_pmu.h:588
ll_aon_pmu_get_dig_ldo_bypass
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
Get the dig ldo bypass.
Definition: gr55xx_ll_aon_pmu.h:360
ll_aon_pmu_get_dcdc_vreg
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
Get dcdc vreg.
Definition: gr55xx_ll_aon_pmu.h:208
ll_aon_pmu_set_dcdc_vreg
__STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
Definition: gr55xx_ll_aon_pmu.h:193