52 #ifndef __GR55XX_LL_AON_WDT_H__
53 #define __GR55XX_LL_AON_WDT_H__
71 #define LL_AON_WD_TIMER_CLK_SEL_RNG (0x0U << AON_WDT_CLK_SEL_Pos)
72 #define LL_AON_WD_TIMER_CLK_SEL_XO (0x1U << AON_WDT_CLK_SEL_Pos)
73 #define LL_AON_WD_TIMER_CLK_SEL_RNG2 (0x2U << AON_WDT_CLK_SEL_Pos)
74 #define LL_AON_WD_TIMER_CLK_SEL_RTC (0x3U << AON_WDT_CLK_SEL_Pos)
86 #define AON_WDT_REG_READ (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN | \
87 AON_WDT_CFG0_ALARM_EN))
111 WRITE_REG(AON_WDT->CFG0,AON_WDT_CFG0_CFG | AON_WDT_CFG0_EN |
AON_WDT_REG_READ);
124 MODIFY_REG(AON_WDT->CFG0, 0xFFFFFFFF, AON_WDT_CFG0_CFG);
138 return (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN) == (AON_WDT_CFG0_EN));
156 MODIFY_REG(AON_WDT->CLK, AON_WDT_CLK_SEL, value);
174 return (READ_BITS(AON_WDT->CLK, AON_WDT_CLK_SEL));
188 WRITE_REG(AON_WDT->TIMER_W, counter);
202 return (uint32_t)READ_BITS(AON_WDT->TIMER_W, AON_WDT_TIMER_W_VAL);
216 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
231 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_TIMER_SET |
AON_WDT_REG_READ);
246 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
263 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
280 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
281 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_SET |
AON_WDT_REG_READ);
297 return (uint32_t)(READ_BITS(AON_WDT->ALARM_W, AON_WDT_ALARM_W_VAL));
311 return (uint32_t)(READ_BITS(AON_WDT->ALARM_R, AON_WDT_ALARM_R_VAL));
325 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_BUSY) == (AON_WDT_STAT_BUSY));
339 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_EN |
AON_WDT_REG_READ);
353 WRITE_REG(AON_WDT->CFG0, (
AON_WDT_REG_READ & (~AON_WDT_CFG0_ALARM_EN)) | AON_WDT_CFG0_CFG);
367 return (uint32_t)(READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_ALARM_EN) == AON_WDT_CFG0_ALARM_EN);
388 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_STAT) == (AON_WDT_STAT_STAT));
404 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_AON_WDT) == AON_CTL_AON_IRQ_AON_WDT);
418 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_AON_WDT);
434 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_AON_WDT) == AON_CTL_SLP_EVENT_AON_WDT);
448 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_AON_WDT);
458 WRITE_REG(AON_WDT->LOCK, 0x15CC5A51 << 1);
468 WRITE_REG(AON_WDT->LOCK, 0 << 1);