52 #ifndef __GR55XX_LL_COMP_H__
53 #define __GR55XX_LL_COMP_H__
120 #define LL_COMP_INPUT_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
121 #define LL_COMP_INPUT_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
122 #define LL_COMP_INPUT_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
123 #define LL_COMP_INPUT_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
124 #define LL_COMP_INPUT_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
125 #define LL_COMP_INPUT_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
126 #define LL_COMP_INPUT_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
127 #define LL_COMP_INPUT_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
129 #define LL_COMP_INPUT_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
130 #define LL_COMP_INPUT_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
137 #define LL_COMP_REF_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
138 #define LL_COMP_REF_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
139 #define LL_COMP_REF_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
140 #define LL_COMP_REF_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
141 #define LL_COMP_REF_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
142 #define LL_COMP_REF_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
143 #define LL_COMP_REF_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
144 #define LL_COMP_REF_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
146 #define LL_COMP_REF_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
147 #define LL_COMP_REF_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
153 #define LL_COMP_HYST_POSITIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_HYST_Pos )
154 #define LL_COMP_HYST_NEGATIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_HYST_Pos )
161 #define LL_COMP_WAKEUP_EDGE_BOTH ( 0UL )
162 #define LL_COMP_WAKEUP_EDGE_FALLING ( 1UL )
163 #define LL_COMP_WAKEUP_EDGE_RISING ( 2UL )
185 #define LL_COMP_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
193 #define LL_COMP_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
214 #define LL_COMP_DEFAULT_CONFIG \
216 .channel_p = LL_COMP_CHANNEL_IO0, \
217 .channel_n = LL_COMP_CHANNEL_IO1, \
245 SET_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
259 CLEAR_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
284 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Msk, source);
309 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Msk, source);
325 SET_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_VBAT_EN_Msk);
326 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_LV_Pos);
342 SET_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_VREF_EN_Msk);
343 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_COMP_REF_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_COMP_REF_CTRL_LV_Pos);
356 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_ICOMP_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_ICOMP_CTRL_LV_Pos);
370 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_CASCRES_HALF_CTRL_Msk, level <<AON_PMU_COMP_REG_1_COMP_CASCRES_HALF_CTRL_Pos);
387 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_HYST , hyst);
404 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_HYST , hyst);
418 SET_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CLK_COMP_EN_Msk);
432 CLEAR_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CLK_COMP_EN_Msk);
446 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 1;
460 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 0;
474 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE) == AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE);
488 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 1;
502 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 0;
516 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL) == AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL);
530 return (READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_CMP_RISE) == AON_CTL_SLP_EVENT_CMP_RISE);
544 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_CMP_RISE);
558 return (READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_CMP_FALL) == AON_CTL_SLP_EVENT_CMP_FALL);
572 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_CMP_FALL);
586 MODIFY_REG(AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE, cycle << AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);
600 return (uint32_t)(READ_BITS(AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Msk) >> AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);