Defines

Macros

#define HAL_GDC_REG_MODE   (0x00U)
 
#define HAL_GDC_REG_CLKCTRL   (0x04U)
 
#define HAL_GDC_REG_PLAY   (0x10U)
 
#define HAL_GDC_REG_CLKCTRL_CG   (0x1a8U)
 
#define HAL_GDC_REG_BGCOLOR   (0x08U)
 
#define HAL_GDC_REG_RESXY   (0x0cU)
 
#define HAL_GDC_REG_FRONTPORCHXY   (0x14U)
 
#define HAL_GDC_REG_BLANKINGXY   (0x18U)
 
#define HAL_GDC_REG_BACKPORCHXY   (0x1cU)
 
#define HAL_GDC_REG_CURSORXY   (0x20U)
 
#define HAL_GDC_REG_STARTXY   (0x24U)
 
#define HAL_GDC_REG_DBIB_CFG   (0x28U)
 
#define HAL_GDC_REG_GPIO   (0x2cU)
 
#define HAL_GDC_REG_LAYER0_MODE   (0x30U)
 
#define HAL_GDC_REG_LAYER0_STARTXY   (0x34U)
 
#define HAL_GDC_REG_LAYER0_SIZEXY   (0x38U)
 
#define HAL_GDC_REG_LAYER0_BASEADDR   (0x3cU)
 
#define HAL_GDC_REG_LAYER0_STRIDE   (0x40U)
 
#define HAL_GDC_REG_LAYER0_RESXY   (0x44U)
 
#define HAL_GDC_REG_LAYER0_SCALEX   (0x48U)
 
#define HAL_GDC_REG_LAYER0_SCALEY   (0x4cU)
 
#define HAL_GDC_REG_LAYER1_MODE   (0x50U)
 
#define HAL_GDC_REG_LAYER1_STARTXY   (0x54U)
 
#define HAL_GDC_REG_LAYER1_SIZEXY   (0x58U)
 
#define HAL_GDC_REG_LAYER1_BASEADDR   (0x5cU)
 
#define HAL_GDC_REG_LAYER1_STRIDE   (0x60U)
 
#define HAL_GDC_REG_LAYER1_RESXY   (0x64U)
 
#define HAL_GDC_REG_LAYER1_SCALEX   (0x68U)
 
#define HAL_GDC_REG_LAYER1_SCALEY   (0x6cU)
 
#define HAL_GDC_REG_LAYER2_MODE   (0x70U)
 
#define HAL_GDC_REG_LAYER2_STARTXY   (0x74U)
 
#define HAL_GDC_REG_LAYER2_SIZEXY   (0x78U)
 
#define HAL_GDC_REG_LAYER2_BASEADDR   (0x7cU)
 
#define HAL_GDC_REG_LAYER2_STRIDE   (0x80U)
 
#define HAL_GDC_REG_LAYER2_RESXY   (0x84U)
 
#define HAL_GDC_REG_LAYER2_SCALEX   (0x88U)
 
#define HAL_GDC_REG_LAYER2_SCALEY   (0x8cU)
 
#define HAL_GDC_REG_LAYER3_MODE   (0x90U)
 
#define HAL_GDC_REG_LAYER3_STARTXY   (0x94U)
 
#define HAL_GDC_REG_LAYER3_SIZEXY   (0x98U)
 
#define HAL_GDC_REG_LAYER3_BASEADDR   (0x9cU)
 
#define HAL_GDC_REG_LAYER3_STRIDE   (0xa0U)
 
#define HAL_GDC_REG_LAYER3_RESXY   (0xa4U)
 
#define HAL_GDC_REG_LAYER3_SCALEX   (0xa8U)
 
#define HAL_GDC_REG_LAYER3_SCALEY   (0xacU)
 
#define HAL_GDC_REG_LAYER0_UBASE   (0xd0U)
 
#define HAL_GDC_REG_LAYER0_VBASE   (0xd4U)
 
#define HAL_GDC_REG_LAYER0_UVSTRIDE   (0xd8U)
 
#define HAL_GDC_REG_LAYER1_UBASE   (0xdcU)
 
#define HAL_GDC_REG_LAYER1_VBASE   (0xe0U)
 
#define HAL_GDC_REG_LAYER1_UVSTRIDE   (0xe4U)
 
#define HAL_GDC_REG_LAYER2_UBASE   (0x188U)
 
#define HAL_GDC_REG_LAYER2_VBASE   (0x18cU)
 
#define HAL_GDC_REG_LAYER2_UVSTRIDE   (0x190U)
 
#define HAL_GDC_REG_LAYER3_UBASE   (0x194U)
 
#define HAL_GDC_REG_LAYER3_VBASE   (0x198U)
 
#define HAL_GDC_REG_LAYER3_UVSTRIDE   (0x19cU)
 
#define HAL_GDC_REG_DBIB_CMD   (0xe8U)
 
#define HAL_GDC_REG_DBIB_RDAT   (0xecU)
 
#define HAL_GDC_REG_CONFIG   (0xf0U)
 
#define HAL_GDC_REG_IDREG   (0xf4U)
 
#define HAL_GDC_REG_INTERRUPT   (0xf8U)
 
#define HAL_GDC_REG_STATUS   (0xfcU)
 
#define HAL_GDC_REG_COLMOD   (0x100U)
 
#define HAL_GDC_REG_CRC   (0x184U)
 
#define HAL_GDC_REG_FORMAT_CTRL   (0x1a0U)
 
#define HAL_GDC_REG_FORMAT_CTRL2   (0x1a4U)
 
#define HAL_GDC_REG_FORMAT_CTRL3   (0x1acU)
 
#define HAL_GDC_REG_PALETTE   (0x400U)
 
#define HAL_GDC_REG_CURSOR_IMAGE   (0x800U)
 
#define HAL_GDC_REG_CURSOR_LUT   (0xA00U)
 
#define HAL_GDC_REG_GAMMALUT_0   (0x1000U)
 
#define HAL_GDC_REG_GAMMALUT_1   (0x1400U)
 
#define HAL_GDC_REG_GAMMALUT_2   (0x1800U)
 
#define HAL_GDC_REG_GAMMALUT_3   (0x1c00U)
 
#define HAL_GDC_REG_LAYER_MODE(i)   (0x030 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_STARTXY(i)   (0x034 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_SIZEXY(i)   (0x038 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_BASEADDR(i)   (0x03c + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_STRIDE(i)   (0x040 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_RESXY(i)   (0x044 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_SCALEX(i)   (0x048 + 0x20*(i))
 
#define HAL_GDC_REG_LAYER_SCALEY(i)   (0x04c + 0x20*(i))
 
#define HAL_GDC_REG_GAMMALUT(i)   (0x1000+ 0x400*(i))
 

Detailed Description

Macro Definition Documentation

◆ HAL_GDC_REG_BACKPORCHXY

#define HAL_GDC_REG_BACKPORCHXY   (0x1cU)

This register specifies the X and Y back porch.

Definition at line 29 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_BGCOLOR

#define HAL_GDC_REG_BGCOLOR   (0x08U)

This register specifies the main background color

Definition at line 25 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_BLANKINGXY

#define HAL_GDC_REG_BLANKINGXY   (0x18U)

This register specifies the X and Y blanking period.

Definition at line 28 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CLKCTRL

#define HAL_GDC_REG_CLKCTRL   (0x04U)

This register specifies the clock division.

Definition at line 22 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CLKCTRL_CG

#define HAL_GDC_REG_CLKCTRL_CG   (0x1a8U)

This register specifies the clock control of DC..

Definition at line 24 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_COLMOD

#define HAL_GDC_REG_COLMOD   (0x100U)

This register specifies the color mode of DC.

Definition at line 90 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CONFIG

#define HAL_GDC_REG_CONFIG   (0xf0U)

This register specifies the configuration of DC.

Definition at line 86 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CRC

#define HAL_GDC_REG_CRC   (0x184U)

This register specifies the CRC check of DC.

Definition at line 91 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CURSOR_IMAGE

#define HAL_GDC_REG_CURSOR_IMAGE   (0x800U)

This register specifies the cursor image.

Definition at line 97 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CURSOR_LUT

#define HAL_GDC_REG_CURSOR_LUT   (0xA00U)

This register specifies the lut of cursor

Definition at line 98 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_CURSORXY

#define HAL_GDC_REG_CURSORXY   (0x20U)

This register specifies the cursor's start X and Y coordinates

Definition at line 30 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_DBIB_CFG

#define HAL_GDC_REG_DBIB_CFG   (0x28U)

This register specifies the configuration of the interface.

Definition at line 32 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_DBIB_CMD

#define HAL_GDC_REG_DBIB_CMD   (0xe8U)

This register specifies the CMD to SPI interface.

Definition at line 84 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_DBIB_RDAT

#define HAL_GDC_REG_DBIB_RDAT   (0xecU)

This register specifies the read data by SPI interface.

Definition at line 85 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_FORMAT_CTRL

#define HAL_GDC_REG_FORMAT_CTRL   (0x1a0U)

This register specifies the format control of DC.

Definition at line 93 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_FORMAT_CTRL2

#define HAL_GDC_REG_FORMAT_CTRL2   (0x1a4U)

This register specifies the format control of DC.

Definition at line 94 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_FORMAT_CTRL3

#define HAL_GDC_REG_FORMAT_CTRL3   (0x1acU)

This register specifies the format control of DC.

Definition at line 95 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_FRONTPORCHXY

#define HAL_GDC_REG_FRONTPORCHXY   (0x14U)

This register specifies the X and Y front porch.

Definition at line 27 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GAMMALUT

#define HAL_GDC_REG_GAMMALUT (   i)    (0x1000+ 0x400*(i))

This register specifies the gammaluti.

Definition at line 112 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GAMMALUT_0

#define HAL_GDC_REG_GAMMALUT_0   (0x1000U)

This register specifies the gammalut of layer0.

Definition at line 99 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GAMMALUT_1

#define HAL_GDC_REG_GAMMALUT_1   (0x1400U)

This register specifies the gammalut of layer1.

Definition at line 100 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GAMMALUT_2

#define HAL_GDC_REG_GAMMALUT_2   (0x1800U)

This register specifies the gammalut of layer2.

Definition at line 101 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GAMMALUT_3

#define HAL_GDC_REG_GAMMALUT_3   (0x1c00U)

This register specifies the gammalut of layer3.

Definition at line 102 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_GPIO

#define HAL_GDC_REG_GPIO   (0x2cU)

This register specifies the general Purpose

Definition at line 33 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_IDREG

#define HAL_GDC_REG_IDREG   (0xf4U)

This register specifies the ID of DC.

Definition at line 87 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_INTERRUPT

#define HAL_GDC_REG_INTERRUPT   (0xf8U)

This register specifies the interrupt of DC.

Definition at line 88 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_BASEADDR

#define HAL_GDC_REG_LAYER0_BASEADDR   (0x3cU)

This register specifies the start address of the framebuffer.

Definition at line 38 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_MODE

#define HAL_GDC_REG_LAYER0_MODE   (0x30U)

This register specifies the mode of layer0.

Definition at line 35 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_RESXY

#define HAL_GDC_REG_LAYER0_RESXY   (0x44U)

This register specifies the resolution of the layer0.

Definition at line 40 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_SCALEX

#define HAL_GDC_REG_LAYER0_SCALEX   (0x48U)

This register specifies the scale-x of the layer0.

Definition at line 41 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_SCALEY

#define HAL_GDC_REG_LAYER0_SCALEY   (0x4cU)

This register specifies the scale-y of the layer0.

Definition at line 42 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_SIZEXY

#define HAL_GDC_REG_LAYER0_SIZEXY   (0x38U)

This register specifies the size of the layer0.

Definition at line 37 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_STARTXY

#define HAL_GDC_REG_LAYER0_STARTXY   (0x34U)

This register specifies the start position of the layer0.

Definition at line 36 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_STRIDE

#define HAL_GDC_REG_LAYER0_STRIDE   (0x40U)

This register specifies the stride of the layer0.

Definition at line 39 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_UBASE

#define HAL_GDC_REG_LAYER0_UBASE   (0xd0U)

This register specifies the start address of the U chroma for layer 0 YUV planar format

Definition at line 71 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_UVSTRIDE

#define HAL_GDC_REG_LAYER0_UVSTRIDE   (0xd8U)

This register specifies the start address of the V chroma for layer 0 YUV planar format

Definition at line 73 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER0_VBASE

#define HAL_GDC_REG_LAYER0_VBASE   (0xd4U)

This register specifies the start address of the V chroma for layer 0 YUV planar format

Definition at line 72 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_BASEADDR

#define HAL_GDC_REG_LAYER1_BASEADDR   (0x5cU)

This register specifies the start address of the framebuffer.

Definition at line 47 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_MODE

#define HAL_GDC_REG_LAYER1_MODE   (0x50U)

This register specifies the mode of layer1.

Definition at line 44 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_RESXY

#define HAL_GDC_REG_LAYER1_RESXY   (0x64U)

This register specifies the resolution of the layer1.

Definition at line 49 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_SCALEX

#define HAL_GDC_REG_LAYER1_SCALEX   (0x68U)

This register specifies the scale-x of the layer1.

Definition at line 50 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_SCALEY

#define HAL_GDC_REG_LAYER1_SCALEY   (0x6cU)

This register specifies the scale-y of the layer1.

Definition at line 51 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_SIZEXY

#define HAL_GDC_REG_LAYER1_SIZEXY   (0x58U)

This register specifies the size of the layer1.

Definition at line 46 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_STARTXY

#define HAL_GDC_REG_LAYER1_STARTXY   (0x54U)

This register specifies the start position of the layer1.

Definition at line 45 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_STRIDE

#define HAL_GDC_REG_LAYER1_STRIDE   (0x60U)

This register specifies the stride of the layer1.

Definition at line 48 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_UBASE

#define HAL_GDC_REG_LAYER1_UBASE   (0xdcU)

This register specifies the start address of the U chroma for layer 1 YUV planar format

Definition at line 74 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_UVSTRIDE

#define HAL_GDC_REG_LAYER1_UVSTRIDE   (0xe4U)

This register specifies the start address of the V chroma for layer 1 YUV planar format

Definition at line 76 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER1_VBASE

#define HAL_GDC_REG_LAYER1_VBASE   (0xe0U)

This register specifies the start address of the V chroma for layer 1 YUV planar format

Definition at line 75 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_BASEADDR

#define HAL_GDC_REG_LAYER2_BASEADDR   (0x7cU)

This register specifies the start address of the framebuffer.

Definition at line 56 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_MODE

#define HAL_GDC_REG_LAYER2_MODE   (0x70U)

This register specifies the mode of layer2.

Definition at line 53 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_RESXY

#define HAL_GDC_REG_LAYER2_RESXY   (0x84U)

This register specifies the resolution of the layer2.

Definition at line 58 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_SCALEX

#define HAL_GDC_REG_LAYER2_SCALEX   (0x88U)

This register specifies the scale-x of the layer2.

Definition at line 59 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_SCALEY

#define HAL_GDC_REG_LAYER2_SCALEY   (0x8cU)

This register specifies the scale-y of the layer2.

Definition at line 60 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_SIZEXY

#define HAL_GDC_REG_LAYER2_SIZEXY   (0x78U)

This register specifies the size of the layer2.

Definition at line 55 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_STARTXY

#define HAL_GDC_REG_LAYER2_STARTXY   (0x74U)

This register specifies the start position of the layer2.

Definition at line 54 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_STRIDE

#define HAL_GDC_REG_LAYER2_STRIDE   (0x80U)

This register specifies the stride of the layer2.

Definition at line 57 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_UBASE

#define HAL_GDC_REG_LAYER2_UBASE   (0x188U)

This register specifies the start address of the U chroma for layer 2 YUV planar format

Definition at line 77 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_UVSTRIDE

#define HAL_GDC_REG_LAYER2_UVSTRIDE   (0x190U)

This register specifies the start address of the V chroma for layer 2 YUV planar format

Definition at line 79 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER2_VBASE

#define HAL_GDC_REG_LAYER2_VBASE   (0x18cU)

This register specifies the start address of the V chroma for layer 2 YUV planar format

Definition at line 78 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_BASEADDR

#define HAL_GDC_REG_LAYER3_BASEADDR   (0x9cU)

This register specifies the start address of the framebuffer.

Definition at line 65 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_MODE

#define HAL_GDC_REG_LAYER3_MODE   (0x90U)

This register specifies the mode of layer3.

Definition at line 62 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_RESXY

#define HAL_GDC_REG_LAYER3_RESXY   (0xa4U)

This register specifies the resolution of the layer3.

Definition at line 67 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_SCALEX

#define HAL_GDC_REG_LAYER3_SCALEX   (0xa8U)

This register specifies the scale-x of the layer3.

Definition at line 68 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_SCALEY

#define HAL_GDC_REG_LAYER3_SCALEY   (0xacU)

This register specifies the scale-y of the layer3.

Definition at line 69 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_SIZEXY

#define HAL_GDC_REG_LAYER3_SIZEXY   (0x98U)

This register specifies the size of the layer3.

Definition at line 64 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_STARTXY

#define HAL_GDC_REG_LAYER3_STARTXY   (0x94U)

This register specifies the start position of the layer3.

Definition at line 63 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_STRIDE

#define HAL_GDC_REG_LAYER3_STRIDE   (0xa0U)

This register specifies the stride of the layer3.

Definition at line 66 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_UBASE

#define HAL_GDC_REG_LAYER3_UBASE   (0x194U)

This register specifies the start address of the U chroma for layer 3 YUV planar format

Definition at line 80 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_UVSTRIDE

#define HAL_GDC_REG_LAYER3_UVSTRIDE   (0x19cU)

This register specifies the start address of the V chroma for layer 3 YUV planar format

Definition at line 82 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER3_VBASE

#define HAL_GDC_REG_LAYER3_VBASE   (0x198U)

This register specifies the start address of the V chroma for layer 3 YUV planar format

Definition at line 81 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_BASEADDR

#define HAL_GDC_REG_LAYER_BASEADDR (   i)    (0x03c + 0x20*(i))

This register specifies the start address of the framebuffer.

Definition at line 107 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_MODE

#define HAL_GDC_REG_LAYER_MODE (   i)    (0x030 + 0x20*(i))

This register specifies the mode of layeri.

Definition at line 104 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_RESXY

#define HAL_GDC_REG_LAYER_RESXY (   i)    (0x044 + 0x20*(i))

This register specifies the resolution of the layeri.

Definition at line 109 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_SCALEX

#define HAL_GDC_REG_LAYER_SCALEX (   i)    (0x048 + 0x20*(i))

This register specifies the scale-x of the layeri.

Definition at line 110 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_SCALEY

#define HAL_GDC_REG_LAYER_SCALEY (   i)    (0x04c + 0x20*(i))

This register specifies the scale-y of the layeri.

Definition at line 111 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_SIZEXY

#define HAL_GDC_REG_LAYER_SIZEXY (   i)    (0x038 + 0x20*(i))

This register specifies the size of the layeri.

Definition at line 106 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_STARTXY

#define HAL_GDC_REG_LAYER_STARTXY (   i)    (0x034 + 0x20*(i))

This register specifies the start position of the layeri.

Definition at line 105 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_LAYER_STRIDE

#define HAL_GDC_REG_LAYER_STRIDE (   i)    (0x040 + 0x20*(i))

This register specifies the stride of the layeri.

Definition at line 108 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_MODE

#define HAL_GDC_REG_MODE   (0x00U)

This register specifies the general control.

Definition at line 21 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_PALETTE

#define HAL_GDC_REG_PALETTE   (0x400U)

This register global palette/gamma correction memory region

Definition at line 96 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_PLAY

#define HAL_GDC_REG_PLAY   (0x10U)

This register sequence the trigger the DC.

Definition at line 23 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_RESXY

#define HAL_GDC_REG_RESXY   (0x0cU)

This register specifies the main X and Y resolutions.

Definition at line 26 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_STARTXY

#define HAL_GDC_REG_STARTXY   (0x24U)

This register specifies the start position of the first frame.

Definition at line 31 of file hal_gdc_regs.h.

◆ HAL_GDC_REG_STATUS

#define HAL_GDC_REG_STATUS   (0xfcU)

This register specifies the status of DC.

Definition at line 89 of file hal_gdc_regs.h.