52 #ifndef __GR55xx_LL_SLEEP_TIMER_H__
53 #define __GR55xx_LL_SLEEP_TIMER_H__
75 #define SLP_TIMER_CFG0_CNT_SLP_ONLY (0x1U << SLP_TIMER_CFG0_COUNT_MODE_Pos)
76 #define SLP_TIMER_CFG0_CNT_ANY_CONDITION (0x0U << SLP_TIMER_CFG0_COUNT_MODE_Pos)
77 #define SLP_TIMER_CFG0_SINGLE_MODE (0x1U << SLP_TIMER_CFG0_MODE_Pos)
78 #define SLP_TIMER_CFG0_AUTO_RELOAD (0x0U << SLP_TIMER_CFG0_MODE_Pos)
79 #define LL_SLEEP_TIMER_SINGLE_MODE_0 (SLP_TIMER_CFG0_SINGLE_MODE | SLP_TIMER_CFG0_CNT_SLP_ONLY)
80 #define LL_SLEEP_TIMER_SINGLE_MODE_1 (SLP_TIMER_CFG0_SINGLE_MODE | SLP_TIMER_CFG0_CNT_ANY_CONDITION)
81 #define LL_SLEEP_TIMER_AUTO_MODE (SLP_TIMER_CFG0_AUTO_RELOAD | SLP_TIMER_CFG0_CNT_ANY_CONDITION)
86 #define LL_SLEEP_TIMER_CLK_SEL_RNG_OSC (0x0U << SLP_TIMER_CLK_SEL_Pos)
87 #define LL_SLEEP_TIMER_CLK_SEL_XO (0x1U << SLP_TIMER_CLK_SEL_Pos)
88 #define LL_SLEEP_TIMER_CLK_SEL_RNG2_OSC (0x2U << SLP_TIMER_CLK_SEL_Pos)
89 #define LL_SLEEP_TIMER_CLK_SEL_RTC_OSC (0x3U << SLP_TIMER_CLK_SEL_Pos)
116 MODIFY_REG(SLP_TIMER->CLK, SLP_TIMER_CLK_SEL, value);
133 return (READ_BITS(SLP_TIMER->CLK, SLP_TIMER_CLK_SEL));
148 WRITE_REG(SLP_TIMER->TIMER_W, value);
162 return READ_REG(SLP_TIMER->TIMER_W);
176 return READ_REG(SLP_TIMER->TIMER_R);
190 return (uint32_t)(READ_BITS(SLP_TIMER->STAT, SLP_TIMER_STAT_STAT) == SLP_TIMER_STAT_STAT);
204 return (uint32_t)(READ_BITS(SLP_TIMER->STAT, SLP_TIMER_STAT_BUSY) == SLP_TIMER_STAT_BUSY);
219 WRITE_REG(SLP_TIMER->CFG0, SLP_TIMER_CFG0_EN | SLP_TIMER_CFG0_VAL_SET | mode | SLP_TIMER_CFG0_CFG);
232 MODIFY_REG(SLP_TIMER->CFG0, SLP_TIMER_CFG0_EN, SLP_TIMER_CFG0_CFG);
246 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_SLP_TIMER);