gr55xx_ll_cgc.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_cgc.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of CGC LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_CGC CGC
47  * @brief CGC LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_CGC_H__
53 #define __GR55XX_LL_CGC_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 #if defined(MCU_SUB) || defined(MCU_RET)
63 /**
64  * @defgroup LL_CGC_MACRO Defines
65  * @{
66  */
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup LL_CGC_Exported_Constants CGC Exported Constants
69  * @{
70  */
71 /** @defgroup LL_CGC_EC_WFI_CLK0 Block0 Clock During WFI
72  * @{
73  */
74 #define LL_CGC_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK /**< Hclk for all security blocks */
75 #define LL_CGC_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK /**< Hclk for sim card interface */
76 #define LL_CGC_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK /**< Hclk for hopping table */
77 #define LL_CGC_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK /**< Hclk for PWM */
78 #define LL_CGC_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK /**< Hclk for ROM */
79 #define LL_CGC_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK /**< Hclk for sense ADC */
80 #define LL_CGC_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK /**< Hclk for GPIOs */
81 #define LL_CGC_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
82 #define LL_CGC_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK /**< Hclk for APB subsystem */
83 #define LL_CGC_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK /**< Hclk for serial blocks */
84 #define LL_CGC_WFI_ALL_HCLK0 ((uint32_t)0x000007FFU) /**< All clock group 0 */
85 
86 /** @} */
87 
88 /** @defgroup LL_CGC_EC_WFI_CLK1 Block1 Clock During WFI
89  * @{
90  */
91 #define LL_CGC_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
92 #define LL_CGC_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK /**< Hclk for cache top */
93 #define LL_CGC_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK /**< Hclk for SRAMs */
94 
95 #define LL_CGC_WFI_ALL_HCLK1 ((uint32_t)0x00000007U) /**< All clock group 1 */
96 /** @} */
97 
98 /** @defgroup LL_CGC_EC_WFI_CLK2 Block2 Clock During WFI
99  * @{
100  */
101 #define LL_CGC_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK /**< Div4 clk for security blocks */
102 #define LL_CGC_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
103 
104 #define LL_CGC_WFI_ALL_HCLK2 ((uint32_t)0x05000000U) /**< All clock group 2 */
105 /** @} */
106 
107 
108 /** @defgroup LL_CGC_EC_FRC_CLK0 Block0 Clock During FRC
109  * @{
110  */
111 #define LL_CGC_FRC_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK /**< Hclk for all security blocks */
112 #define LL_CGC_FRC_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK /**< Hclk for sim card interface */
113 #define LL_CGC_FRC_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK /**< Hclk for hopping table */
114 #define LL_CGC_FRC_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK /**< Hclk for ROM */
115 #define LL_CGC_FRC_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK /**< Hclk for sense ADC */
116 #define LL_CGC_FRC_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK /**< Hclk for GPIOs */
117 #define LL_CGC_FRC_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK /**< Hclk for BLE MCU bridge */
118 #define LL_CGC_FRC_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK /**< Hclk for APB subsystem */
119 #define LL_CGC_FRC_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK /**< Hclk for serial blocks */
120 #define LL_CGC_FRC_ALL_HCLK0 ((uint32_t)0x00000777U) /**< All clock group 0 */
121 /** @} */
122 
123 /** @defgroup LL_CGC_EC_FRC_CLK1 Block1 Clock During FRC
124  * @{
125  */
126 #define LL_CGC_FRC_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK /**< Hclk for Always-on register */
127 #define LL_CGC_FRC_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK /**< Hclk for cache top */
128 #define LL_CGC_FRC_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK /**< Hclk for SRAMs */
129 
130 #define LL_CGC_FRC_ALL_HCLK1 ((uint32_t)0x00070000U) /**< All clock group 1 */
131 /** @} */
132 
133 /** @defgroup LL_CGC_EC_FRC_CLK2 Block2 Clock During FRC
134  * @{
135  */
136 #define LL_CGC_FRC_UART0_PCLK MCU_SUB_FORCE_UART0_PCLK /**< Pclk for uart0 */
137 #define LL_CGC_FRC_UART1_PCLK MCU_SUB_FORCE_UART1_PCLK /**< Pclk for uart1 */
138 #define LL_CGC_FRC_UART2_PCLK MCU_SUB_FORCE_UART2_PCLK /**< Pclk for uart2 */
139 #define LL_CGC_FRC_UART3_PCLK MCU_SUB_FORCE_UART3_PCLK /**< Pclk for uart3 */
140 #define LL_CGC_FRC_UART4_PCLK MCU_SUB_FORCE_UART4_PCLK /**< Pclk for uart4 */
141 #define LL_CGC_FRC_UART5_PCLK MCU_SUB_FORCE_UART5_PCLK /**< Pclk for uart5 */
142 #define LL_CGC_FRC_I2C0_PCLK MCU_SUB_FORCE_I2C0_PCLK /**< Hclk for i2c0 */
143 #define LL_CGC_FRC_I2C1_PCLK MCU_SUB_FORCE_I2C1_PCLK /**< Hclk for i2c1 */
144 #define LL_CGC_FRC_I2C2_PCLK MCU_SUB_FORCE_I2C2_PCLK /**< Hclk for i2c2 */
145 #define LL_CGC_FRC_I2C3_PCLK MCU_SUB_FORCE_I2C3_PCLK /**< Hclk for i2c3 */
146 #define LL_CGC_FRC_I2C4_PCLK MCU_SUB_FORCE_I2C4_PCLK /**< Hclk for i2c4 */
147 #define LL_CGC_FRC_I2C5_PCLK MCU_SUB_FORCE_I2C5_PCLK /**< Hclk for i2c5 */
148 #define LL_CGC_FRC_QSPI0_PCLK MCU_SUB_FORCE_QSPI0_PCLK /**< Hclk for qspi0 */
149 #define LL_CGC_FRC_QSPI1_PCLK MCU_SUB_FORCE_QSPI1_PCLK /**< Hclk for qspi1 */
150 #define LL_CGC_FRC_QSPI2_PCLK MCU_SUB_FORCE_QSPI2_PCLK /**< Hclk for qspi2 */
151 #define LL_CGC_FRC_SPI_M_PCLK MCU_SUB_FORCE_SPI_M_PCLK /**< Hclk for spim */
152 #define LL_CGC_FRC_SPI_S_PCLK MCU_SUB_FORCE_SPI_S_PCLK /**< Hclk for spis */
153 #define LL_CGC_FRC_I2S_HCLK MCU_SUB_FORCE_I2S_PCLK /**< Hclk for i2s */
154 #define LL_CGC_FRC_I2S_S_PCLK MCU_SUB_FORCE_I2S_S_PCLK /**< Hclk for i2ss */
155 #define LL_CGC_FRC_DSPI_PCLK MCU_SUB_FORCE_DSPI_PCLK /**< Hclk for dspi */
156 #define LL_CGC_FRC_PDM_PCLK MCU_SUB_FORCE_PDM_PCLK /**< Hclk for pdm */
157 #define LL_CGC_FRC_PWM_0_PCLK MCU_SUB_FORCE_PWM_0_PCLK /**< Pclk for PWM0 */
158 #define LL_CGC_FRC_PWM_1_PCLK MCU_SUB_FORCE_PWM_1_PCLK /**< Pclk for PWM1 */
159 #define LL_CGC_FRC_VTTBL_PCLK MCU_SUB_FORCE_VTTBL_PCLK /**< Pclk for VTTBL */
160 #define LL_CGC_FRC_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK /**< Div4 clk for security blocksi */
161 #define LL_CGC_FRC_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK /**< Div4 clk for xf qspi */
162 
163 #define LL_CGC_FRC_SERIALS_HCLK2 ((uint32_t)0x705E0FFFUL) /**< Hclk for serial blocks */
164 #define LL_CGC_FRC_ALL_HCLK2 ((uint32_t)0xFF7FCFFFUL) /**< All clock group 2 */
165 /** @} */
166 
167 /** @defgroup LL_CGC_PERIPH_CG_LP_EN Low Power Feature
168  * @{
169  */
170 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN /**< Enable AHB2APB ASYNC low-power feature */
171 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB2APB_SYNC_EN MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN /**< Enable AHB2APB SYNC low-power feature */
172 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_EN MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN /**< Enable qspim low-power feature */
173 #define LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN /**< Enable AHB bus low-power feature */
174 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN /**< Enable i2c sclk low-power feature */
175 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN /**< Enable spis sclk low-power feature */
176 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN /**< Enable spim sclk low-power feature */
177 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN /**< Enable i2s master low-power feature */
178 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN /**< Enable uart pclk low-power feature */
179 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN /**< Enable uart sclk low-power feature */
180 
181 #define LL_CGC_MCU_PERIPH_CG_LP ((uint32_t)0x00000F3FUL) /**< All Low Power Feature */
182 /** @} */
183 
184 /** @defgroup LL_CGC_SUBSYS_PERI_CLK_SLP_OFF Peripherals Off During WFI/WFE
185  * @brief Turn the peripherals off during WFI/WFE
186  * @{
187  */
188 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 /**< Turn the uart0 off during WFI/WFE */
189 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 /**< Turn the uart1 off during WFI/WFE */
190 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 /**< Turn the uart2 off during WFI/WFE */
191 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 /**< Turn the uart3 off during WFI/WFE */
192 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_4_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART4 /**< Turn the uart4 off during WFI/WFE */
193 #define LL_CGC_MCU_PERIPH_CG_LP_EN_UART_5_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_UART5 /**< Turn the uart5 off during WFI/WFE */
194 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM /**< Turn the i2s_m off during WFI/WFE */
195 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS /**< Turn the i2s_s off during WFI/WFE */
196 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_M_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM /**< Turn the spi_m off during WFI/WFE */
197 #define LL_CGC_MCU_PERIPH_CG_LP_EN_SPI_S_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS /**< Turn the spi_s off during WFI/WFE */
198 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 /**< Turn the pwm0 off during WFI/WFE */
199 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PWM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 /**< Turn the pwm1 off during WFI/WFE */
200 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 /**< Turn the qspim0 off during WFI/WFE */
201 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 /**< Turn the qspim1 off during WFI/WFE */
202 #define LL_CGC_MCU_PERIPH_CG_LP_EN_QSPIM_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 /**< Turn the qspim2 off during WFI/WFE */
203 #define LL_CGC_MCU_PERIPH_CG_LP_EN_DSPI_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI /**< Turn the dspi off during WFI/WFE */
204 #define LL_CGC_MCU_PERIPH_CG_LP_EN_PDM_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_PDM /**< Turn the pdm off during WFI/WFE */
205 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_0_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 /**< Turn the i2c0 off during WFI/WFE */
206 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_1_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 /**< Turn the i2c1 off during WFI/WFE */
207 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_2_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 /**< Turn the i2c0 off during WFI/WFE */
208 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_3_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 /**< Turn the i2c1 off during WFI/WFE */
209 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_4_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4 /**< Turn the i2c0 off during WFI/WFE */
210 #define LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5 /**< Turn the i2c1 off during WFI/WFE */
211 
212 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_OFF ((uint32_t)0x01FC3FFFUL) /**< Serial blocks */
213 #define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL ((uint32_t)0x03FFFF3FUL) /**< Serial blocks */
214 
215 /** @} */
216 
217 /** @defgroup LL_CGC_SUBSYS_SECU_CLK_CTRL Individual Block's Clock Control
218  * @brief Individual block's clock control inside security system
219  * @{
220  */
221 #define LL_CGC_MCU_FRC_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF /**< Force individual aes's clock control */
222 #define LL_CGC_MCU_SLP_AES_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF /**< Individual aes's clock control */
223 #define LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF /**< Force individual hmac's clock control */
224 #define LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF /**< Individual hmac's clock control */
225 #define LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF /**< Force individual pkc's clock control */
226 #define LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF /**< Individual pkc's clock control */
227 #define LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF /**< Force individual present's clock control */
228 #define LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF /**< Individual present's clock control */
229 #define LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF /**< Force individual ramkey's clock control */
230 #define LL_CGC_MCU_SLP_RAMKEY_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF /**< Individual ramkey's clock control */
231 #define LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF /**< Force individual rng's clock control */
232 #define LL_CGC_MCU_SLP_RNG_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF /**< Individual rng's clock control */
233 #define LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF /**< Force individual efuse's clock control */
234 #define LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF /**< Individual efuse's clock control */
235 
236 #define LL_CGC_MCU_SECU_FRC_OFF_HCLK ((uint32_t)0x00001555U) /**< Hclk for security clock */
237 #define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK ((uint32_t)0x00002AAAU) /**< Hclk for security clock WFI/WFE */
238 
239 #define LL_CGC_MCU_SECU_FRC_OFF_ALL (LL_CGC_MCU_SECU_FRC_OFF_HCLK |\
240  LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK) /**< Hclk for security clock */
241 
242 #define LL_CGC_MCU_MISC_CLK_DEFAULT ((uint32_t)0x0000003BU) /**< Hclk for msic default clock */
243 
244 #define LL_CGC_MCU_MISC_CLK ((uint32_t)0x0000003FU) /**< Hclk for msic all clock */
245 
246 #define LL_CGC_MCU_MISC_DMA_CLK ((uint32_t)0x00000038U) /**< Hclk for msic dma clock */
247 
248 /** @} */
249 
250 /** @defgroup LL_CGC_SUBSYS_DEFAULT_CLK Default System Clock Specify
251  * @brief Specify the default system clock when the system is initialized
252  * @{
253  */
254 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0 (LL_CGC_WFI_SECU_HCLK |\
255  LL_CGC_WFI_SIM_HCLK |\
256  LL_CGC_WFI_PWM_HCLK |\
257  LL_CGC_WFI_SNSADC_HCLK |\
258  LL_CGC_WFI_GPIO_HCLK |\
259  LL_CGC_WFI_BLE_BRG_HCLK |\
260  LL_CGC_WFI_SERIAL_HCLK) /**< Hclk0 for the system default clock WFI/WFE */
261 
262 #define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1 (LL_CGC_WFI_AON_MCUSUB_HCLK |\
263  LL_CGC_WFI_XF_XQSPI_HCLK |\
264  LL_CGC_WFI_SRAM_HCLK) /**< Hclk1 for the system default clock WFI/WFE */
265 
266 
267 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK (LL_CGC_FRC_SECU_HCLK |\
268  LL_CGC_FRC_SIM_HCLK |\
269  LL_CGC_FRC_SNSADC_HCLK |\
270  LL_CGC_FRC_SERIAL_HCLK) /**< Hclk for the system default clock */
271 
272 #define LL_CGC_MCU_SUBSYS_DEFAULT_CLK1 (MCU_SUB_FORCE_SECU_DIV4_PCLK) /**< Hclk for the system default clock */
273 
274 
275 #define LL_CGC_MCU_PERIPH_CG_DEFAULT (LL_CGC_FRC_UART0_PCLK |\
276  LL_CGC_FRC_UART1_PCLK |\
277  LL_CGC_FRC_UART2_PCLK |\
278  LL_CGC_FRC_UART3_PCLK |\
279  LL_CGC_FRC_UART4_PCLK |\
280  LL_CGC_FRC_UART5_PCLK |\
281  LL_CGC_FRC_I2C0_PCLK |\
282  LL_CGC_FRC_I2C1_PCLK |\
283  LL_CGC_FRC_I2C2_PCLK |\
284  LL_CGC_FRC_I2C3_PCLK |\
285  LL_CGC_FRC_I2C4_PCLK |\
286  LL_CGC_FRC_I2C5_PCLK |\
287  LL_CGC_FRC_QSPI0_PCLK |\
288  LL_CGC_FRC_QSPI1_PCLK |\
289  LL_CGC_FRC_QSPI2_PCLK |\
290  LL_CGC_FRC_SPI_M_PCLK |\
291  LL_CGC_FRC_SPI_S_PCLK |\
292  LL_CGC_FRC_I2S_HCLK |\
293  LL_CGC_FRC_I2S_S_PCLK |\
294  LL_CGC_FRC_DSPI_PCLK |\
295  LL_CGC_FRC_PDM_PCLK |\
296  LL_CGC_FRC_PWM_0_PCLK |\
297  LL_CGC_FRC_PWM_1_PCLK) /**< pclk for the system default periph clock */
298 
299 #define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT (MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
300  MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
301  MCU_SUB_PERIPH_CLK_SLP_OFF_UART2 |\
302  MCU_SUB_PERIPH_CLK_SLP_OFF_UART3 |\
303  MCU_SUB_PERIPH_CLK_SLP_OFF_UART4 |\
304  MCU_SUB_PERIPH_CLK_SLP_OFF_UART5 |\
305  MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM |\
306  MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS |\
307  MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
308  MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
309  MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
310  MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
311  MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0 |\
312  MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1 |\
313  MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2 |\
314  MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI |\
315  MCU_SUB_PERIPH_CLK_SLP_OFF_PDM |\
316  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
317  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1 |\
318  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2 |\
319  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3 |\
320  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4 |\
321  MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5) /**< pclk for the system default periph wfi clock */
322 
323 #define CGC_CLOCK_ENABLE (1) /**< Bit segment address enable */
324 #define CGC_CLOCK_DISABLE (0) /**< Bit segment address disable */
325 
326 #if defined(BIT_BAND_SUPPORT)
327 
328 #define BIT_SEGMENT_VALUE BIT_ADDR /**< Bit segment address value manipulation */
329 
330 #else
331 
332 #define BIT_BAND(addr, bitnum) (((addr) & 0xF0000000) + 0x2000000 + (((addr) & 0xFFFFF) << 5) + ((bitnum) << 2)) /**< Bit segment address calculation */
333 #define MEMORY_ADDR(addr) (*((volatile uint32_t *)(addr))) /**< Bit segment address type conversion */
334 #define BIT_SEGMENT_VALUE(addr, bitnum) MEMORY_ADDR(BIT_BAND(addr, bitnum)) /**< Bit segment address value manipulation */
335 
336 #endif
337 
338 /** @} */
339 
340 /** @} */
341 
342 /** @} */
343 
344 /* Private types -------------------------------------------------------------*/
345 /* Private variables ---------------------------------------------------------*/
346 /* Private constants ---------------------------------------------------------*/
347 /* Private macros ------------------------------------------------------------*/
348 /* Exported functions --------------------------------------------------------*/
349 /** @defgroup LL_CGC_DRIVER_FUNCTIONS Functions
350  * @{
351  */
352 
353 /**
354  * @brief Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/
355  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
356  *
357  * Register | BitsName
358  * ----------|--------
359  * CG_CTRL_0 | SECU_HCLK
360  * CG_CTRL_0 | SIM_HCLK
361  * CG_CTRL_0 | HTB_HCLK
362  * CG_CTRL_0 | PWM_HCLK
363  * CG_CTRL_0 | ROM_HCLK
364  * CG_CTRL_0 | SNSADC_HCLK
365  * CG_CTRL_0 | GPIO_HCLK
366  * CG_CTRL_0 | BLE_BRG_HCLK
367  * CG_CTRL_0 | APB_SUB_HCLK
368  * CG_CTRL_0 | SERIAL_HCLK
369  *
370  * @param clk_mask This parameter can be a combination of the following values:
371  * @arg @ref LL_CGC_WFI_SECU_HCLK
372  * @arg @ref LL_CGC_WFI_SIM_HCLK
373  * @arg @ref LL_CGC_WFI_HTB_HCLK
374  * @arg @ref LL_CGC_WFI_PWM_HCLK
375  * @arg @ref LL_CGC_WFI_ROM_HCLK
376  * @arg @ref LL_CGC_WFI_SNSADC_HCLK
377  * @arg @ref LL_CGC_WFI_GPIO_HCLK
378  * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
379  * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
380  * @arg @ref LL_CGC_WFI_SERIAL_HCLK
381  * @retval None
382  */
383 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
384 {
385  MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0], LL_CGC_WFI_ALL_HCLK0, clk_mask);
386 }
387 
388 /**
389  * @brief Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/
390  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
391  *
392  * Register | BitsName
393  * ----------|--------
394  * CG_CTRL_0 | SECU_HCLK
395  * CG_CTRL_0 | SIM_HCLK
396  * CG_CTRL_0 | HTB_HCLK
397  * CG_CTRL_0 | PWM_HCLK
398  * CG_CTRL_0 | ROM_HCLK
399  * CG_CTRL_0 | SNSADC_HCLK
400  * CG_CTRL_0 | GPIO_HCLK
401  * CG_CTRL_0 | BLE_BRG_HCLK
402  * CG_CTRL_0 | APB_SUB_HCLK
403  * CG_CTRL_0 | SERIAL_HCLK
404  *
405  * @retval Returned value can be a combination of the following values:
406  * @arg @ref LL_CGC_WFI_SECU_HCLK
407  * @arg @ref LL_CGC_WFI_SIM_HCLK
408  * @arg @ref LL_CGC_WFI_HTB_HCLK
409  * @arg @ref LL_CGC_WFI_PWM_HCLK
410  * @arg @ref LL_CGC_WFI_ROM_HCLK
411  * @arg @ref LL_CGC_WFI_SNSADC_HCLK
412  * @arg @ref LL_CGC_WFI_GPIO_HCLK
413  * @arg @ref LL_CGC_WFI_BLE_BRG_HCLK
414  * @arg @ref LL_CGC_WFI_APB_SUB_HCLK
415  * @arg @ref LL_CGC_WFI_SERIAL_HCLK
416  */
417 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
418 {
419  return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[0]);
420 }
421 
422 /**
423  * @brief Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
424  *
425  * Register | BitsName
426  * ----------|--------
427  * CG_CTRL_2 | AON_MCUSUB_HCLK
428  * CG_CTRL_2 | XF_XQSPI_HCLK
429  * CG_CTRL_2 | SRAM_HCLK
430  *
431  * @param clk_mask This parameter can be a combination of the following values:
432  * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
433  * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
434  * @arg @ref LL_CGC_WFI_SRAM_HCLK
435  * @retval None
436  */
437 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
438 {
439  MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1, clk_mask);
440 }
441 
442 /**
443  * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
444  *
445  * Register | BitsName
446  * ----------|--------
447  * CG_CTRL_2 | AON_MCUSUB_HCLK
448  * CG_CTRL_2 | XF_XQSPI_HCLK
449  * CG_CTRL_2 | SRAM_HCLK
450  *
451  * @retval Returned value can be a combination of the following values:
452  * @arg @ref LL_CGC_WFI_AON_MCUSUB_HCLK
453  * @arg @ref LL_CGC_WFI_XF_XQSPI_HCLK
454  * @arg @ref LL_CGC_WFI_SRAM_HCLK
455  */
456 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
457 {
458  return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_WFI_ALL_HCLK1);
459 }
460 
461 /**
462  * @brief Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
463  *
464  * Register | BitsName
465  * ----------|--------
466  * PERIPH_GC | SECU_DIV4_PCLK
467  * PERIPH_GC | XQSPI_DIV4_PCLK
468  *
469  * @param clk_mask This parameter can be a combination of the following values:
470  * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
471  * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
472  * @retval None
473  */
474 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
475 {
476  MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2, clk_mask);
477 }
478 
479 /**
480  * @brief Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
481  *
482  * Register | BitsName
483  * ----------|--------
484  * PERIPH_GC | SECU_DIV4_PCLK
485  * PERIPH_GC | XQSPI_DIV4_PCLK
486  *
487  * @retval Returned value can be a combination of the following values:
488  * @arg @ref LL_CGC_WFI_SECU_DIV4_PCLK
489  * @arg @ref LL_CGC_WFI_XQSPI_DIV4_PCLK
490  */
491 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
492 {
493  return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_WFI_ALL_HCLK2);
494 }
495 
496 /**
497  * @brief Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI.etc)
498  *
499  * Register | BitsName
500  * ----------|--------
501  * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
502  * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
503  *
504  * @param clk_mask This parameter can be a combination of the following values:
505  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
506  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
507  * .....
508  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF
509  * @retval None
510  */
511 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
512 {
513  MODIFY_REG(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL, clk_mask);
514 }
515 
516 /**
517  * @brief Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI.etc)
518  *
519  * Register | BitsName
520  * ----------|--------
521  * PERIPH_GC | UART0 - UART5/I2C0 - I2C5
522  * PERIPH_GC | I2SM/I2SS/SPIM/SPIS/PWM0/PWM1//QSPIM0/QSPIM1/QSPIM2/DSPI/PDM
523  *
524  * @retval Returned value can be a combination of the following values:
525  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_0_SLP_OFF
526  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_1_SLP_OFF
527  * .....
528  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_5_SLP_OFF
529  */
530 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
531 {
532  return READ_BITS(MCU_RET->MCU_PERIPH_CLK_SLP_OFF, LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL);
533 }
534 
535 /**
536  * @brief Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
537  *
538  * Register | BitsName
539  * ----------|--------
540  * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
541  *
542  * @param clk_mask This parameter can be a combination of the following values:
543  * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
544  * .....
545  * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
546  * @retval None
547  */
548 __STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
549 {
550  MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
551 }
552 
553 /**
554  * @brief Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
555  *
556  * Register | BitsName
557  * ----------|--------
558  * PERIPH_GC | AES/HMAC/PKC/RNG/EFUSE
559  *
560  * @retval Returned value can be a combination of the following values:
561  * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
562  * .....
563  * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
564  */
565 __STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
566 {
567  return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
568 }
569 
570 /**
571  * @brief Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/
572  * DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
573  *
574  * Register | BitsName
575  * ----------|--------
576  * CG_CTRL_1 | SECU_HCLK
577  * CG_CTRL_1 | SIM_HCLK
578  * CG_CTRL_1 | HTB_HCLK
579  * CG_CTRL_1 | ROM_HCLK
580  * CG_CTRL_1 | SNSADC_HCLK
581  * CG_CTRL_1 | GPIO_HCLK
582  * CG_CTRL_1 | BLE_BRG_HCLK
583  * CG_CTRL_1 | APB_SUB_HCLK
584  * CG_CTRL_1 | SERIAL_HCLK
585  *
586  * @param clk_mask This parameter can be a combination of the following values:
587  * @arg @ref LL_CGC_FRC_SECU_HCLK
588  * @arg @ref LL_CGC_FRC_SIM_HCLK
589  * @arg @ref LL_CGC_FRC_HTB_HCLK
590  * @arg @ref LL_CGC_FRC_ROM_HCLK
591  * @arg @ref LL_CGC_FRC_SNSADC_HCLK
592  * @arg @ref LL_CGC_FRC_GPIO_HCLK
593  * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
594  * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
595  * @arg @ref LL_CGC_FRC_SERIAL_HCLK
596  * @retval None
597  */
598 __STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
599 {
600  MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1], LL_CGC_FRC_ALL_HCLK0, clk_mask);
601 }
602 
603 /**
604  * @brief Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/
605  * ROM/SNSADC/GPIO/DMA/BLE_BRG/APB_SUB/SERIAL/I2S)
606  *
607  * Register | BitsName
608  * ----------|--------
609  * CG_CTRL_1 | SECU_HCLK
610  * CG_CTRL_1 | SIM_HCLK
611  * CG_CTRL_1 | HTB_HCLK
612  * CG_CTRL_1 | ROM_HCLK
613  * CG_CTRL_1 | SNSADC_HCLK
614  * CG_CTRL_1 | GPIO_HCLK
615  * CG_CTRL_1 | BLE_BRG_HCLK
616  * CG_CTRL_1 | APB_SUB_HCLK
617  * CG_CTRL_1 | SERIAL_HCLK
618  *
619  * @retval Returned value can be a combination of the following values:
620  * @arg @ref LL_CGC_FRC_SECU_HCLK
621  * @arg @ref LL_CGC_FRC_SIM_HCLK
622  * @arg @ref LL_CGC_FRC_HTB_HCLK
623  * @arg @ref LL_CGC_FRC_ROM_HCLK
624  * @arg @ref LL_CGC_FRC_SNSADC_HCLK
625  * @arg @ref LL_CGC_FRC_GPIO_HCLK
626  * @arg @ref LL_CGC_FRC_BLE_BRG_HCLK
627  * @arg @ref LL_CGC_FRC_APB_SUB_HCLK
628  * @arg @ref LL_CGC_FRC_SERIAL_HCLK
629  */
630 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
631 {
632  return READ_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[1]);
633 }
634 
635 /**
636  * @brief Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
637  *
638  * Register | BitsName
639  * ----------|--------
640  * CG_CTRL_2 | AON_MCUSUB_HCLK
641  * CG_CTRL_2 | XF_XQSPI_HCLK
642  * CG_CTRL_2 | SRAM_HCLK
643  *
644  * @param clk_mask This parameter can be a combination of the following values:
645  * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
646  * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
647  * @arg @ref LL_CGC_FRC_SRAM_HCLK
648  * @retval None
649  */
650 __STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
651 {
652  MODIFY_REG(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1, clk_mask);
653 }
654 
655 /**
656  * @brief Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
657  *
658  * Register | BitsName
659  * ----------|--------
660  * CG_CTRL_2 | AON_MCUSUB_HCLK
661  * CG_CTRL_2 | XF_XQSPI_HCLK
662  * CG_CTRL_2 | SRAM_HCLK
663  *
664  * @retval Returned value can be a combination of the following values:
665  * @arg @ref LL_CGC_FRC_AON_MCUSUB_HCLK
666  * @arg @ref LL_CGC_FRC_XF_XQSPI_HCLK
667  * @arg @ref LL_CGC_FRC_SRAM_HCLK
668  */
669 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
670 {
671  return READ_BITS(MCU_RET->MCU_SUBSYS_CG_CTRL[2], LL_CGC_FRC_ALL_HCLK1);
672 }
673 
674 /**
675  * @brief Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
676  * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
677  *
678  * Register | BitsName
679  * ----------|--------
680  * PERIPH_GC | UART0_PCLK
681  * PERIPH_GC | UART1_PCLK
682  * PERIPH_GC | UART2_PCLK
683  * PERIPH_GC | UART3_PCLK
684  * PERIPH_GC | UART4_PCLK
685  * PERIPH_GC | UART5_PCLK
686  * PERIPH_GC | I2C0_PCLK
687  * PERIPH_GC | I2C1_PCLK
688  * PERIPH_GC | I2C2_PCLK
689  * PERIPH_GC | I2C3_PCLK
690  * PERIPH_GC | I2C4_PCLK
691  * PERIPH_GC | I2C5_PCLK
692  * PERIPH_GC | QSPI0_PCLK
693  * PERIPH_GC | QSPI1_PCLK
694  * PERIPH_GC | QSPI2_PCLK
695  * PERIPH_GC | SPIM_PCLK
696  * PERIPH_GC | SPIS_PCLK
697  * PERIPH_GC | I2S_HCLK
698  * PERIPH_GC | I2S_S_PCLK
699  * PERIPH_GC | DSPI_PCLK
700  * PERIPH_GC | PDM_PCLK
701  * PERIPH_GC | PWM_0_PCLK
702  * PERIPH_GC | PWM_1_PCLK
703  * PERIPH_GC | VTTBL_PCLK
704  * PERIPH_GC | SECU_DIV4_PCLK
705  * PERIPH_GC | XQSPI_DIV4_PCLK
706  * PERIPH_GC | SERIALS_HCLK2
707  *
708  * @param clk_mask This parameter can be a combination of the following values:
709  * @arg @ref LL_CGC_FRC_UART0_PCLK
710  * @arg @ref LL_CGC_FRC_UART1_PCLK
711  * @arg @ref LL_CGC_FRC_UART2_PCLK
712  * @arg @ref LL_CGC_FRC_UART3_PCLK
713  * @arg @ref LL_CGC_FRC_UART4_PCLK
714  * @arg @ref LL_CGC_FRC_UART5_PCLK
715  * @arg @ref LL_CGC_FRC_I2C0_PCLK
716  * @arg @ref LL_CGC_FRC_I2C1_PCLK
717  * @arg @ref LL_CGC_FRC_I2C2_PCLK
718  * @arg @ref LL_CGC_FRC_I2C3_PCLK
719  * @arg @ref LL_CGC_FRC_I2C4_PCLK
720  * @arg @ref LL_CGC_FRC_I2C5_PCLK
721  * @arg @ref LL_CGC_FRC_QSPI0_PCLK
722  * @arg @ref LL_CGC_FRC_QSPI1_PCLK
723  * @arg @ref LL_CGC_FRC_QSPI2_PCLK
724  * @arg @ref LL_CGC_FRC_SPI_M_PCLK
725  * @arg @ref LL_CGC_FRC_SPI_S_PCLK
726  * @arg @ref LL_CGC_FRC_I2S_HCLK
727  * @arg @ref LL_CGC_FRC_I2S_S_PCLK
728  * @arg @ref LL_CGC_FRC_DSPI_PCLK
729  * @arg @ref LL_CGC_FRC_PDM_PCLK
730  * @arg @ref LL_CGC_FRC_PWM_0_PCLK
731  * @arg @ref LL_CGC_FRC_PWM_1_PCLK
732  * @arg @ref LL_CGC_FRC_VTTBL_PCLK
733  * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
734  * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
735  * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
736  * @retval None
737  */
738 __STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
739 {
740  MODIFY_REG(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2, clk_mask);
741 }
742 
743 
744 /**
745  * @brief Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HCLK/UART5_HCLK/
746  * I2C0_HCLK/I2C1_HCLK/SPIM_HCLK/SPIS_HCLK/QSPI0_HCLK/QSPI1_HCLK/I2S_HCLK/SECU_DIV4_PCLK/XQSPI_DIV4_PCLK/PWM0/PWM1)
747  *
748  * Register | BitsName
749  * ----------|--------
750  * PERIPH_GC | UART0_PCLK
751  * PERIPH_GC | UART1_PCLK
752  * PERIPH_GC | UART2_PCLK
753  * PERIPH_GC | UART3_PCLK
754  * PERIPH_GC | UART4_PCLK
755  * PERIPH_GC | UART5_PCLK
756  * PERIPH_GC | I2C0_PCLK
757  * PERIPH_GC | I2C1_PCLK
758  * PERIPH_GC | I2C2_PCLK
759  * PERIPH_GC | I2C3_PCLK
760  * PERIPH_GC | I2C4_PCLK
761  * PERIPH_GC | I2C5_PCLK
762  * PERIPH_GC | QSPI0_PCLK
763  * PERIPH_GC | QSPI1_PCLK
764  * PERIPH_GC | QSPI2_PCLK
765  * PERIPH_GC | SPIM_PCLK
766  * PERIPH_GC | SPIS_PCLK
767  * PERIPH_GC | I2S_HCLK
768  * PERIPH_GC | I2S_S_PCLK
769  * PERIPH_GC | DSPI_PCLK
770  * PERIPH_GC | PDM_PCLK
771  * PERIPH_GC | PWM_0_PCLK
772  * PERIPH_GC | PWM_1_PCLK
773  * PERIPH_GC | VTTBL_PCLK
774  * PERIPH_GC | SECU_DIV4_PCLK
775  * PERIPH_GC | XQSPI_DIV4_PCLK
776  * PERIPH_GC | SERIALS_HCLK2
777  *
778  * @retval Returned value can be a combination of the following values:
779  * @arg @ref LL_CGC_FRC_UART0_PCLK
780  * @arg @ref LL_CGC_FRC_UART1_PCLK
781  * @arg @ref LL_CGC_FRC_UART2_PCLK
782  * @arg @ref LL_CGC_FRC_UART3_PCLK
783  * @arg @ref LL_CGC_FRC_UART4_PCLK
784  * @arg @ref LL_CGC_FRC_UART5_PCLK
785  * @arg @ref LL_CGC_FRC_I2C0_PCLK
786  * @arg @ref LL_CGC_FRC_I2C1_PCLK
787  * @arg @ref LL_CGC_FRC_I2C2_PCLK
788  * @arg @ref LL_CGC_FRC_I2C3_PCLK
789  * @arg @ref LL_CGC_FRC_I2C4_PCLK
790  * @arg @ref LL_CGC_FRC_I2C5_PCLK
791  * @arg @ref LL_CGC_FRC_QSPI0_PCLK
792  * @arg @ref LL_CGC_FRC_QSPI1_PCLK
793  * @arg @ref LL_CGC_FRC_QSPI2_PCLK
794  * @arg @ref LL_CGC_FRC_SPI_M_PCLK
795  * @arg @ref LL_CGC_FRC_SPI_S_PCLK
796  * @arg @ref LL_CGC_FRC_I2S_HCLK
797  * @arg @ref LL_CGC_FRC_I2S_S_PCLK
798  * @arg @ref LL_CGC_FRC_DSPI_PCLK
799  * @arg @ref LL_CGC_FRC_PDM_PCLK
800  * @arg @ref LL_CGC_FRC_PWM_0_PCLK
801  * @arg @ref LL_CGC_FRC_PWM_1_PCLK
802  * @arg @ref LL_CGC_FRC_VTTBL_PCLK
803  * @arg @ref LL_CGC_FRC_SECU_DIV4_PCLK
804  * @arg @ref LL_CGC_FRC_XQSPI_DIV4_PCLK
805  * @arg @ref LL_CGC_FRC_SERIALS_HCLK2
806  */
807 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
808 {
809  return READ_BITS(MCU_RET->MCU_PERIPH_PCLK_OFF, LL_CGC_FRC_ALL_HCLK2);
810 }
811 
812 /**
813  * @brief Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
814  *
815  * Register | BitsName
816  * ----------|--------
817  * PERIPH_GC | AES/HMAC/PKC/PRESENT/RAMKEY/RNG/EFUSE
818  *
819  * @param clk_mask This parameter can be a combination of the following values:
820  * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
821  * .....
822  * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
823  * @retval None
824  */
825 __STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
826 {
827  MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
828 }
829 
830 /**
831  * @brief Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
832  *
833  * Register | BitsName
834  * ----------|--------
835  * PERIPH_GC | AES/HMAC/PKC/PRESENT/RAMKEY/RNG/EFUSE
836  *
837  * @retval Returned value can be a combination of the following values:
838  * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
839  * .....
840  * @arg @ref LL_CGC_MCU_SLP_EFUSE_HCLK_OFF_EN
841  */
842 __STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
843 {
844  return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
845 }
846 
847 
848 /**
849  * @brief Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
850  *
851  * Register | BitsName
852  * ----------|--------
853  * CG_CTRL_0 | SECU_HCLK
854  *
855  * @retval None
856  */
857 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
858 {
859  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
860 }
861 
862 /**
863  * @brief Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI
864  *
865  * Register | BitsName
866  * ----------|--------
867  * CG_CTRL_0 | SECU_HCLK
868  *
869  * @retval None
870  */
871 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
872 {
873  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
874 }
875 
876 /**
877  * @brief Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is enabled.
878  *
879  * Register | BitsName
880  * ----------|--------
881  * CG_CTRL_0 | SECU_HCLK
882  *
883  * @retval State of bit (1 or 0).
884  */
885 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
886 {
887  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
888 }
889 
890 /**
891  * @brief Enable SIM automatic turn off clock during WFI
892  *
893  * Register | BitsName
894  * ----------|--------
895  * CG_CTRL_0 | SIM_HCLK
896  *
897  * @retval None
898  */
899 __STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
900 {
901  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) = CGC_CLOCK_ENABLE;
902 }
903 
904 /**
905  * @brief Disable SIM automatic turn off clock during WFI
906  *
907  * Register | BitsName
908  * ----------|--------
909  * CG_CTRL_0 | SIM_HCLK
910  *
911  * @retval None
912  */
913 __STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
914 {
915  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) = CGC_CLOCK_DISABLE;
916 }
917 
918 /**
919  * @brief Indicate whether the SIM automatic turn off clock is enabled.
920  *
921  * Register | BitsName
922  * ----------|--------
923  * CG_CTRL_0 | SIM_HCLK
924  *
925  * @retval State of bit (1 or 0).
926  */
927 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
928 {
929  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SIM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
930 }
931 
932 /**
933  * @brief Enable Hopping Table automatic turn off clock during WFI
934  *
935  * Register | BitsName
936  * ----------|--------
937  * CG_CTRL_0 | HTB_HCLK
938  *
939  * @retval None
940  */
941 __STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
942 {
943  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
944 }
945 
946 /**
947  * @brief Disable Hopping Table automatic turn off clock during WFI
948  *
949  * Register | BitsName
950  * ----------|--------
951  * CG_CTRL_0 | HTB_HCLK
952  *
953  * @retval None
954  */
955 __STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
956 {
957  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
958 }
959 
960 /**
961  * @brief Indicate whether the Hopping Table automatic turn off clock is enabled.
962  *
963  * Register | BitsName
964  * ----------|--------
965  * CG_CTRL_0 | HTB_HCLK
966  *
967  * @retval State of bit (1 or 0).
968  */
969 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
970 {
971  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
972 }
973 
974 /**
975  * @brief Enable PWM automatic turn off clock during WFI
976  *
977  * Register | BitsName
978  * ----------|--------
979  * CG_CTRL_0 | PWM_HCLK
980  *
981  * @retval None
982  */
983 __STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
984 {
985  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) = CGC_CLOCK_ENABLE;
986 }
987 
988 /**
989  * @brief Disable PWM automatic turn off clock during WFI
990  *
991  * Register | BitsName
992  * ----------|--------
993  * CG_CTRL_0 | PWM_HCLK
994  *
995  * @retval None
996  */
997 __STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
998 {
999  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1000 }
1001 
1002 /**
1003  * @brief Indicate whether the PWM automatic turn off clock is enabled.
1004  *
1005  * Register | BitsName
1006  * ----------|--------
1007  * CG_CTRL_0 | PWM_HCLK
1008  *
1009  * @retval State of bit (1 or 0).
1010  */
1011 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
1012 {
1013  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_PWM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1014 }
1015 
1016 /**
1017  * @brief Enable ROM automatic turn off clock during WFI
1018  *
1019  * Register | BitsName
1020  * ----------|--------
1021  * CG_CTRL_0 | ROM_HCLK
1022  *
1023  * @retval None
1024  */
1025 __STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
1026 {
1027  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1028 }
1029 
1030 /**
1031  * @brief Disable ROM automatic turn off clock during WFI
1032  *
1033  * Register | BitsName
1034  * ----------|--------
1035  * CG_CTRL_0 | ROM_HCLK
1036  *
1037  * @retval None
1038  */
1039 __STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
1040 {
1041  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1042 }
1043 
1044 /**
1045  * @brief Indicate whether the ROM automatic turn off clock is enabled.
1046  *
1047  * Register | BitsName
1048  * ----------|--------
1049  * CG_CTRL_0 | ROM_HCLK
1050  *
1051  * @retval State of bit (1 or 0).
1052  */
1053 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
1054 {
1055  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1056 }
1057 
1058 /**
1059  * @brief Enable SNSADC automatic turn off clock during WFI
1060  *
1061  * Register | BitsName
1062  * ----------|--------
1063  * CG_CTRL_0 | SNSADC_HCLK
1064  *
1065  * @retval None
1066  */
1067 __STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
1068 {
1069  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1070 }
1071 
1072 /**
1073  * @brief Disable SNSADC automatic turn off clock during WFI
1074  *
1075  * Register | BitsName
1076  * ----------|--------
1077  * CG_CTRL_0 | SNSADC_HCLK
1078  *
1079  * @retval None
1080  */
1081 __STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
1082 {
1083  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1084 }
1085 
1086 /**
1087  * @brief Indicate whether the SNSADC automatic turn off clock is enabled.
1088  *
1089  * Register | BitsName
1090  * ----------|--------
1091  * CG_CTRL_0 | SNSADC_HCLK
1092  *
1093  * @retval State of bit (1 or 0).
1094  */
1095 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
1096 {
1097  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1098 }
1099 
1100 /**
1101  * @brief Enable GPIO automatic turn off clock during WFI
1102  *
1103  * Register | BitsName
1104  * ----------|--------
1105  * CG_CTRL_0 | GPIO_HCLK
1106  *
1107  * @retval None
1108  */
1109 __STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
1110 {
1111  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1112 }
1113 
1114 /**
1115  * @brief Disable GPIO automatic turn off clock during WFI
1116  *
1117  * Register | BitsName
1118  * ----------|--------
1119  * CG_CTRL_0 | GPIO_HCLK
1120  *
1121  * @retval None
1122  */
1123 __STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
1124 {
1125  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1126 }
1127 
1128 /**
1129  * @brief Indicate whether the GPIO automatic turn off clock is enabled.
1130  *
1131  * Register | BitsName
1132  * ----------|--------
1133  * CG_CTRL_0 | GPIO_HCLK
1134  *
1135  * @retval State of bit (1 or 0).
1136  */
1137 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
1138 {
1139  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1140 }
1141 
1142 /**
1143  * @brief Enable DMA automatic turn off clock during WFI
1144  *
1145  * Register | BitsName
1146  * ----------|--------
1147  * CG_CTRL_0 | DMA_HCLK
1148  *
1149  * @retval None
1150  */
1151 __STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
1152 {
1153  // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_ENABLE;
1154 }
1155 
1156 /**
1157  * @brief Disable DMA automatic turn off clock during WFI
1158  *
1159  * Register | BitsName
1160  * ----------|--------
1161  * CG_CTRL_0 | DMA_HCLK
1162  *
1163  * @retval None
1164  */
1165 __STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
1166 {
1167  // BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) = CGC_CLOCK_DISABLE;
1168 }
1169 
1170 /**
1171  * @brief Indicate whether the DMA automatic turn off clock is enabled.
1172  *
1173  * Register | BitsName
1174  * ----------|--------
1175  * CG_CTRL_0 | DMA_HCLK
1176  *
1177  * @retval State of bit (1 or 0).
1178  */
1179 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
1180 {
1181  // return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_DMA_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1182  return 0;
1183 }
1184 
1185 /**
1186  * @brief Enable BLE Bridge automatic turn off clock during WFI
1187  *
1188  * Register | BitsName
1189  * ----------|--------
1190  * CG_CTRL_0 | BLE_BRG_HCLK
1191  *
1192  * @retval None
1193  */
1194 __STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
1195 {
1196  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1197 }
1198 
1199 /**
1200  * @brief Disable BLE Bridge automatic turn off clock during WFI
1201  *
1202  * Register | BitsName
1203  * ----------|--------
1204  * CG_CTRL_0 | BLE_BRG_HCLK
1205  *
1206  * @retval None
1207  */
1208 __STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
1209 {
1210  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1211 }
1212 
1213 /**
1214  * @brief Indicate whether the BLE Bridge automatic turn off clock is enabled.
1215  *
1216  * Register | BitsName
1217  * ----------|--------
1218  * CG_CTRL_0 | BLE_BRG_HCLK
1219  *
1220  * @retval State of bit (1 or 0).
1221  */
1222 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
1223 {
1224  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1225 }
1226 
1227 /**
1228  * @brief Enable APB Subsystem automatic turn off clock during WFI
1229  *
1230  * Register | BitsName
1231  * ----------|--------
1232  * CG_CTRL_0 | APB_SUB_HCLK
1233  *
1234  * @retval None
1235  */
1236 __STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
1237 {
1238  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1239 }
1240 
1241 /**
1242  * @brief Disable APB Subsystem automatic turn off clock during WFI
1243  *
1244  * Register | BitsName
1245  * ----------|--------
1246  * CG_CTRL_0 | APB_SUB_HCLK
1247  *
1248  * @retval None
1249  */
1250 __STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
1251 {
1252  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1253 }
1254 
1255 /**
1256  * @brief Indicate whether the APB Subsystem automatic turn off clock is enabled.
1257  *
1258  * Register | BitsName
1259  * ----------|--------
1260  * CG_CTRL_0 | APB_SUB_HCLK
1261  *
1262  * @retval State of bit (1 or 0).
1263  */
1264 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
1265 {
1266  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1267 }
1268 
1269 /**
1270  * @brief Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1271  *
1272  * Register | BitsName
1273  * ----------|--------
1274  * CG_CTRL_0 | SERIAL_HCLK
1275  *
1276  * @retval None
1277  */
1278 __STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
1279 {
1280  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1281 }
1282 
1283 /**
1284  * @brief Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI
1285  *
1286  * Register | BitsName
1287  * ----------|--------
1288  * CG_CTRL_0 | SERIAL_HCLK
1289  *
1290  * @retval None
1291  */
1292 __STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
1293 {
1294  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1295 }
1296 
1297 /**
1298  * @brief Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off
1299  * clock is enabled.
1300  *
1301  * Register | BitsName
1302  * ----------|--------
1303  * CG_CTRL_0 | SERIAL_HCLK
1304  *
1305  * @retval State of bit (1 or 0).
1306  */
1307 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
1308 {
1309  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1310 }
1311 
1312 /**
1313  * @brief Enable USB automatic turn off clock during WFI
1314  *
1315  * Register | BitsName
1316  * ----------|--------
1317  * CG_CTRL_0 | USB_HCLK
1318  *
1319  * @retval None
1320  */
1321 __STATIC_INLINE void ll_cgc_enable_wfi_off_usb_hclk(void)
1322 {
1323  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1324 }
1325 
1326 /**
1327  * @brief Disable USB automatic turn off clock during WFI
1328  *
1329  * Register | BitsName
1330  * ----------|--------
1331  * CG_CTRL_0 | USB_HCLK
1332  *
1333  * @retval None
1334  */
1335 __STATIC_INLINE void ll_cgc_disable_wfi_off_usb_hclk(void)
1336 {
1337  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1338 }
1339 
1340 /**
1341  * @brief Indicate whether the USB automatic turn off
1342  * clock is enabled.
1343  *
1344  * Register | BitsName
1345  * ----------|--------
1346  * CG_CTRL_0 | USB_HCLK
1347  *
1348  * @retval State of bit (1 or 0).
1349  */
1350 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_usb_hclk(void)
1351 {
1352  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[0], MCU_SUB_WFI_USB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1353 }
1354 
1355 /**
1356  * @brief Enable AON_MUCSUB automatic turn off clock during WFI
1357  *
1358  * Register | BitsName
1359  * ----------|--------
1360  * CG_CTRL_2 | AON_MCUSUB_HCLK
1361  *
1362  * @retval None
1363  */
1364 __STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
1365 {
1366  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1367 }
1368 
1369 /**
1370  * @brief Disable AON_MUCSUB automatic turn off clock during WFI
1371  *
1372  * Register | BitsName
1373  * ----------|--------
1374  * CG_CTRL_2 | AON_MCUSUB_HCLK
1375  *
1376  * @retval None
1377  */
1378 __STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
1379 {
1380  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1381 }
1382 
1383 /**
1384  * @brief Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
1385  *
1386  * Register | BitsName
1387  * ----------|--------
1388  * CG_CTRL_2 | AON_MCUSUB_HCLK
1389  *
1390  * @retval State of bit (1 or 0).
1391  */
1392 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
1393 {
1394  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1395 }
1396 
1397 /**
1398  * @brief Enable XQSPI automatic turn off clock during WFI
1399  *
1400  * Register | BitsName
1401  * ----------|--------
1402  * CG_CTRL_2 | XF_XQSPI_HCLK
1403  *
1404  * @retval None
1405  */
1406 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
1407 {
1408  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
1409 }
1410 
1411 /**
1412  * @brief Disable XQSPI automatic turn off clock during WFI
1413  *
1414  * Register | BitsName
1415  * ----------|--------
1416  * CG_CTRL_2 | XF_XQSPI_HCLK
1417  *
1418  * @retval None
1419  */
1420 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
1421 {
1422  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
1423 }
1424 
1425 /**
1426  * @brief Indicate whether the XQSPI automatic turn off clock is enabled.
1427  *
1428  * Register | BitsName
1429  * ----------|--------
1430  * CG_CTRL_2 | XF_XQSPI_HCLK
1431  *
1432  * @retval State of bit (1 or 0).
1433  */
1434 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
1435 {
1436  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1437 }
1438 
1439 /**
1440  * @brief Enable SRAM automatic turn off clock during WFI
1441  *
1442  * Register | BitsName
1443  * ----------|--------
1444  * CG_CTRL_2 | SRAM_HCLK
1445  *
1446  * @retval None
1447  */
1448 __STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
1449 {
1450  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1451 }
1452 
1453 /**
1454  * @brief Disable SRAM automatic turn off clock during WFI
1455  *
1456  * Register | BitsName
1457  * ----------|--------
1458  * CG_CTRL_2 | SRAM_HCLK
1459  *
1460  * @retval None
1461  */
1462 __STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
1463 {
1464  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1465 }
1466 
1467 /**
1468  * @brief Indicate whether the SRAM automatic turn off clock is enabled.
1469  *
1470  * Register | BitsName
1471  * ----------|--------
1472  * CG_CTRL_2 | SRAM_HCLK
1473  *
1474  * @retval State of bit (1 or 0).
1475  */
1476 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
1477 {
1478  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_WFI_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1479 }
1480 
1481 /**
1482  * @brief Enable security blocks automatic turn off div4 clock during WFI
1483  *
1484  * Register | BitsName
1485  * ----------|--------
1486  * PERIPH_GC | SECU_DIV4_PCLK
1487  *
1488  * @retval None
1489  */
1490 __STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
1491 {
1492  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1493 }
1494 
1495 /**
1496  * @brief Disable security blocks automatic turn off div4 clock during WFI
1497  *
1498  * Register | BitsName
1499  * ----------|--------
1500  * PERIPH_GC | SECU_DIV4_PCLK
1501  *
1502  * @retval None
1503  */
1504 __STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
1505 {
1506  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1507 }
1508 
1509 /**
1510  * @brief Indicate whether the security blocks automatic turn off div4
1511  * clock is enabled.
1512  *
1513  * Register | BitsName
1514  * ----------|--------
1515  * PERIPH_GC | SECU_DIV4_PCLK
1516  *
1517  * @retval State of bit (1 or 0).
1518  */
1519 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
1520 {
1521  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1522 }
1523 
1524 /**
1525  * @brief Enable XQSPI automatic turn off div4 clock during WFI
1526  *
1527  * Register | BitsName
1528  * ----------|--------
1529  * PERIPH_GC | XQSPI_DIV4_PCLK
1530  *
1531  * @retval None
1532  */
1533 __STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
1534 {
1535  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
1536 }
1537 
1538 /**
1539  * @brief Disable XQSPI automatic turn off div4 clock during WFI
1540  *
1541  * Register | BitsName
1542  * ----------|--------
1543  * PERIPH_GC | XQSPI_DIV4_PCLK
1544  *
1545  * @retval None
1546  */
1547 __STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
1548 {
1549  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
1550 }
1551 
1552 /**
1553  * @brief Indicate whether the XQSPI automatic turn off div4 clock is enabled.
1554  *
1555  * Register | BitsName
1556  * ----------|--------
1557  * PERIPH_GC | XQSPI_DIV4_PCLK
1558  *
1559  * @retval State of bit (1 or 0).
1560  */
1561 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
1562 {
1563  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
1564 }
1565 
1566 /**
1567  * @brief Enabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1568  *
1569  * Register | BitsName
1570  * ----------|--------
1571  * CG_CTRL_1 | SECU_HCLK
1572  *
1573  * @retval None
1574  */
1575 __STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
1576 {
1577  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_ENABLE;
1578 }
1579 
1580 /**
1581  * @brief Disabling force to turn off the clock for security blocks(including AES, PKC, Present, HMAC).
1582  *
1583  * Register | BitsName
1584  * ----------|--------
1585  * CG_CTRL_1 | SECU_HCLK
1586  *
1587  * @retval None
1588  */
1589 __STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
1590 {
1591  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) = CGC_CLOCK_DISABLE;
1592 }
1593 
1594 /**
1595  * @brief Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
1596  *
1597  * Register | BitsName
1598  * ----------|--------
1599  * CG_CTRL_1 | SECU_HCLK
1600  *
1601  * @retval State of bit (1 or 0).
1602  */
1603 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
1604 {
1605  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SECU_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1606 }
1607 
1608 /**
1609  * @brief Enabling force to turn off the clock for SIM.
1610  *
1611  * Register | BitsName
1612  * ----------|--------
1613  * CG_CTRL_1 | SIM_HCLK
1614  *
1615  * @retval None
1616  */
1617 __STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
1618 {
1619  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1620 }
1621 
1622 /**
1623  * @brief Disabling force to turn off the clock for SIM.
1624  *
1625  * Register | BitsName
1626  * ----------|--------
1627  * CG_CTRL_1 | SIM_HCLK
1628  *
1629  * @retval None
1630  */
1631 __STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
1632 {
1633  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1634 }
1635 
1636 /**
1637  * @brief Indicate whether the clock for SIM is forced to close.
1638  *
1639  * Register | BitsName
1640  * ----------|--------
1641  * CG_CTRL_1 | SIM_HCLK
1642  *
1643  * @retval State of bit (1 or 0).
1644  */
1645 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
1646 {
1647  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SIM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1648 }
1649 
1650 /**
1651  * @brief Enabling force to turn off the clock for Hopping Table.
1652  *
1653  * Register | BitsName
1654  * ----------|--------
1655  * CG_CTRL_1 | HTB_HCLK
1656  *
1657  * @retval None
1658  */
1659 __STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
1660 {
1661  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1662 }
1663 
1664 /**
1665  * @brief Disabling force to turn off the clock for Hopping Table.
1666  *
1667  * Register | BitsName
1668  * ----------|--------
1669  * CG_CTRL_1 | HTB_HCLK
1670  *
1671  * @retval None
1672  */
1673 __STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
1674 {
1675  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1676 }
1677 
1678 /**
1679  * @brief Indicate whether the clock for Hopping Table is forced to close.
1680  *
1681  * Register | BitsName
1682  * ----------|--------
1683  * CG_CTRL_1 | HTB_HCLK
1684  *
1685  * @retval State of bit (1 or 0).
1686  */
1687 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
1688 {
1689  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_HTB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1690 }
1691 
1692 /**
1693  * @brief Enabling force to turn off the clock for ROM.
1694  *
1695  * Register | BitsName
1696  * ----------|--------
1697  * CG_CTRL_1 | ROM_HCLK
1698  *
1699  * @retval None
1700  */
1701 __STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
1702 {
1703  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_ENABLE;
1704 }
1705 
1706 /**
1707  * @brief Disabling force to turn off the clock for ROM.
1708  *
1709  * Register | BitsName
1710  * ----------|--------
1711  * CG_CTRL_1 | ROM_HCLK
1712  *
1713  * @retval None
1714  */
1715 __STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
1716 {
1717  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) = CGC_CLOCK_DISABLE;
1718 }
1719 
1720 /**
1721  * @brief Indicate whether the clock for ROM is forced to close.
1722  *
1723  * Register | BitsName
1724  * ----------|--------
1725  * CG_CTRL_1 | ROM_HCLK
1726  *
1727  * @retval State of bit (1 or 0).
1728  */
1729 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
1730 {
1731  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_ROM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1732 }
1733 
1734 /**
1735  * @brief Enabling force to turn off the clock for SNSADC.
1736  *
1737  * Register | BitsName
1738  * ----------|--------
1739  * CG_CTRL_1 | SNSADC_HCLK
1740  *
1741  * @retval None
1742  */
1743 __STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
1744 {
1745  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_ENABLE;
1746 }
1747 
1748 /**
1749  * @brief Disabling force to turn off the clock for SNSADC.
1750  *
1751  * Register | BitsName
1752  * ----------|--------
1753  * CG_CTRL_1 | SNSADC_HCLK
1754  *
1755  * @retval None
1756  */
1757 __STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
1758 {
1759  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) = CGC_CLOCK_DISABLE;
1760 }
1761 
1762 /**
1763  * @brief Indicate whether the clock for SNSADC is forced to close.
1764  *
1765  * Register | BitsName
1766  * ----------|--------
1767  * CG_CTRL_1 | SNSADC_HCLK
1768  *
1769  * @retval State of bit (1 or 0).
1770  */
1771 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
1772 {
1773  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SNSADC_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1774 }
1775 
1776 /**
1777  * @brief Enabling force to turn off the clock for GPIO.
1778  *
1779  * Register | BitsName
1780  * ----------|--------
1781  * CG_CTRL_1 | GPIO_HCLK
1782  *
1783  * @retval None
1784  */
1785 __STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
1786 {
1787  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_ENABLE;
1788 }
1789 
1790 /**
1791  * @brief Disabling force to turn off the clock for GPIO.
1792  *
1793  * Register | BitsName
1794  * ----------|--------
1795  * CG_CTRL_1 | GPIO_HCLK
1796  *
1797  * @retval None
1798  */
1799 __STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
1800 {
1801  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) = CGC_CLOCK_DISABLE;
1802 }
1803 
1804 /**
1805  * @brief Indicate whether the clock for GPIO is forced to close.
1806  *
1807  * Register | BitsName
1808  * ----------|--------
1809  * CG_CTRL_1 | GPIO_HCLK
1810  *
1811  * @retval State of bit (1 or 0).
1812  */
1813 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
1814 {
1815  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_GPIO_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1816 }
1817 
1818 /**
1819  * @brief Enabling force to turn off the clock for BLE Bridge.
1820  *
1821  * Register | BitsName
1822  * ----------|--------
1823  * CG_CTRL_1 | BLE_BRG_HCLK
1824  *
1825  * @retval None
1826  */
1827 __STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
1828 {
1829  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_ENABLE;
1830 }
1831 
1832 /**
1833  * @brief Disabling force to turn off the clock for BLE Bridge.
1834  *
1835  * Register | BitsName
1836  * ----------|--------
1837  * CG_CTRL_1 | BLE_BRG_HCLK
1838  *
1839  * @retval None
1840  */
1841 __STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
1842 {
1843  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) = CGC_CLOCK_DISABLE;
1844 }
1845 
1846 /**
1847  * @brief Indicate whether the clock for BLE Bridge is forced to close.
1848  *
1849  * Register | BitsName
1850  * ----------|--------
1851  * CG_CTRL_1 | BLE_BRG_HCLK
1852  *
1853  * @retval State of bit (1 or 0).
1854  */
1855 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
1856 {
1857  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_BLE_BRG_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1858 }
1859 
1860 /**
1861  * @brief Enabling force to turn off the clock for APB Subsystem.
1862  *
1863  * Register | BitsName
1864  * ----------|--------
1865  * CG_CTRL_1 | APB_SUB_HCLK
1866  *
1867  * @retval None
1868  */
1869 __STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
1870 {
1871  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1872 }
1873 
1874 /**
1875  * @brief Disabling force to turn off the clock for APB Subsystem.
1876  *
1877  * Register | BitsName
1878  * ----------|--------
1879  * CG_CTRL_1 | APB_SUB_HCLK
1880  *
1881  * @retval None
1882  */
1883 __STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
1884 {
1885  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1886 }
1887 
1888 /**
1889  * @brief Indicate whether the clock for APB Subsystem is forced to close.
1890  *
1891  * Register | BitsName
1892  * ----------|--------
1893  * CG_CTRL_1 | APB_SUB_HCLK
1894  *
1895  * @retval State of bit (1 or 0).
1896  */
1897 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
1898 {
1899  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_APB_SUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1900 }
1901 
1902 /**
1903  * @brief Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1904  *
1905  * Register | BitsName
1906  * ----------|--------
1907  * CG_CTRL_1 | SERIAL_HCLK
1908  *
1909  * @retval None
1910  */
1911 __STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
1912 {
1913  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_ENABLE;
1914 }
1915 
1916 /**
1917  * @brief Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI).
1918  *
1919  * Register | BitsName
1920  * ----------|--------
1921  * CG_CTRL_1 | SERIAL_HCLK
1922  *
1923  * @retval None
1924  */
1925 __STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
1926 {
1927  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) = CGC_CLOCK_DISABLE;
1928 }
1929 
1930 /**
1931  * @brief Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
1932  *
1933  * Register | BitsName
1934  * ----------|--------
1935  * CG_CTRL_1 | SERIAL_HCLK
1936  *
1937  * @retval State of bit (1 or 0).
1938  */
1939 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
1940 {
1941  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_SERIAL_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1942 }
1943 
1944 /**
1945  * @brief Enabling force to turn off the clock for USB.
1946  *
1947  * Register | BitsName
1948  * ----------|--------
1949  * CG_CTRL_1 | USB_HCLK
1950  *
1951  * @retval None
1952  */
1953 __STATIC_INLINE void ll_cgc_enable_force_off_usb_hclk(void)
1954 {
1955  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1956 }
1957 
1958 /**
1959  * @brief Disabling force to turn off the clock for USB.
1960  *
1961  * Register | BitsName
1962  * ----------|--------
1963  * CG_CTRL_1 | USB_HCLK
1964  *
1965  * @retval None
1966  */
1967 __STATIC_INLINE void ll_cgc_disable_force_off_usb_hclk(void)
1968 {
1969  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) = CGC_CLOCK_DISABLE;
1970 }
1971 
1972 /**
1973  * @brief Indicate whether the clock for USB is forced to close.
1974  *
1975  * Register | BitsName
1976  * ----------|--------
1977  * CG_CTRL_1 | USB_HCLK
1978  *
1979  * @retval State of bit (1 or 0).
1980  */
1981 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_usb_hclk(void)
1982 {
1983  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[1], MCU_SUB_FORCE_USB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
1984 }
1985 
1986 /**
1987  * @brief Enabling force to turn off the clock for AON_MUCSUB.
1988  *
1989  * Register | BitsName
1990  * ----------|--------
1991  * CG_CTRL_2 | AON_MCUSUB_HCLK
1992  *
1993  * @retval None
1994  */
1996 {
1997  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_ENABLE;
1998 }
1999 
2000 /**
2001  * @brief Disabling force to turn off the clock for AON_MUCSUB.
2002  *
2003  * Register | BitsName
2004  * ----------|--------
2005  * CG_CTRL_2 | AON_MCUSUB_HCLK
2006  *
2007  * @retval None
2008  */
2010 {
2011  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) = CGC_CLOCK_DISABLE;
2012 }
2013 
2014 /**
2015  * @brief Indicate whether the clock for AON_MUCSUB is forced to close.
2016  *
2017  * Register | BitsName
2018  * ----------|--------
2019  * CG_CTRL_2 | AON_MCUSUB_HCLK
2020  *
2021  * @retval State of bit (1 or 0).
2022  */
2023 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
2024 {
2025  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2026 }
2027 
2028 /**
2029  * @brief Enabling force to turn off the clock for XQSPI.
2030  *
2031  * Register | BitsName
2032  * ----------|--------
2033  * CG_CTRL_2 | XF_XQSPI_HCLK
2034  *
2035  * @retval None
2036  */
2037 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
2038 {
2039  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_ENABLE;
2040 }
2041 
2042 /**
2043  * @brief Disabling force to turn off the clock for XQSPI.
2044  *
2045  * Register | BitsName
2046  * ----------|--------
2047  * CG_CTRL_2 | XF_XQSPI_HCLK
2048  *
2049  * @retval None
2050  */
2051 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
2052 {
2053  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) = CGC_CLOCK_DISABLE;
2054 }
2055 
2056 /**
2057  * @brief Indicate whether the clock for XQSPI is forced to close.
2058  *
2059  * Register | BitsName
2060  * ----------|--------
2061  * CG_CTRL_2 | XF_XQSPI_HCLK
2062  *
2063  * @retval State of bit (1 or 0).
2064  */
2065 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
2066 {
2067  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2068 }
2069 
2070 /**
2071  * @brief Enabling force to turn off the clock for SRAM.
2072  *
2073  * Register | BitsName
2074  * ----------|--------
2075  * CG_CTRL_2 | SRAM_HCLK
2076  *
2077  * @retval None
2078  */
2079 __STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
2080 {
2081  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_ENABLE;
2082 }
2083 
2084 /**
2085  * @brief Disabling force to turn off the clock for SRAM.
2086  *
2087  * Register | BitsName
2088  * ----------|--------
2089  * CG_CTRL_2 | SRAM_HCLK
2090  *
2091  * @retval None
2092  */
2093 __STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
2094 {
2095  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) = CGC_CLOCK_DISABLE;
2096 }
2097 
2098 /**
2099  * @brief Indicate whether the clock for SRAM is forced to close.
2100  *
2101  * Register | BitsName
2102  * ----------|--------
2103  * CG_CTRL_2 | SRAM_HCLK
2104  *
2105  * @retval State of bit (1 or 0).
2106  */
2107 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
2108 {
2109  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_SUBSYS_CG_CTRL[2], MCU_SUB_FORCE_SRAM_HCLK_Pos) == (CGC_CLOCK_ENABLE));
2110 }
2111 
2112 /**
2113  * @brief Enabling force to turn off the clock for UART0.
2114  *
2115  * Register | BitsName
2116  * ----------|--------
2117  * PERIPH_GC | UART0_HCLK
2118  *
2119  * @retval None
2120  */
2121 __STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
2122 {
2123  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2124 }
2125 
2126 /**
2127  * @brief Disabling force to turn off the clock for UART0.
2128  *
2129  * Register | BitsName
2130  * ----------|--------
2131  * PERIPH_GC | UART0_HCLK
2132  *
2133  * @retval None
2134  */
2135 __STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
2136 {
2137  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2138 }
2139 
2140 /**
2141  * @brief Indicate whether the clock for UART0 is forced to close.
2142  *
2143  * Register | BitsName
2144  * ----------|--------
2145  * PERIPH_GC | UART0_HCLK
2146  *
2147  * @retval State of bit (1 or 0).
2148  */
2149 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
2150 {
2151  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2152 }
2153 
2154 /**
2155  * @brief Enabling force to turn off the clock for UART1.
2156  *
2157  * Register | BitsName
2158  * ----------|--------
2159  * PERIPH_GC | UART1_HCLK
2160  *
2161  * @retval None
2162  */
2163 __STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
2164 {
2165  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2166 }
2167 
2168 /**
2169  * @brief Disabling force to turn off the clock for UART1.
2170  *
2171  * Register | BitsName
2172  * ----------|--------
2173  * PERIPH_GC | UART1_HCLK
2174  *
2175  * @retval None
2176  */
2177 __STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
2178 {
2179  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2180 }
2181 
2182 /**
2183  * @brief Indicate whether the clock for UART1 is forced to close.
2184  *
2185  * Register | BitsName
2186  * ----------|--------
2187  * PERIPH_GC | UART1_HCLK
2188  *
2189  * @retval State of bit (1 or 0).
2190  */
2191 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
2192 {
2193  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2194 }
2195 
2196 /**
2197  * @brief Enabling force to turn off the clock for UART2.
2198  *
2199  * Register | BitsName
2200  * ----------|--------
2201  * PERIPH_GC | UART2_HCLK
2202  *
2203  * @retval None
2204  */
2205 __STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
2206 {
2207  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2208 }
2209 
2210 /**
2211  * @brief Disabling force to turn off the clock for UART2.
2212  *
2213  * Register | BitsName
2214  * ----------|--------
2215  * PERIPH_GC | UART2_HCLK
2216  *
2217  * @retval None
2218  */
2219 __STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
2220 {
2221  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2222 }
2223 
2224 /**
2225  * @brief Indicate whether the clock for UART2 is forced to close.
2226  *
2227  * Register | BitsName
2228  * ----------|--------
2229  * PERIPH_GC | UART2_HCLK
2230  *
2231  * @retval State of bit (1 or 0).
2232  */
2233 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
2234 {
2235  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2236 }
2237 
2238 /**
2239  * @brief Enabling force to turn off the clock for UART3.
2240  *
2241  * Register | BitsName
2242  * ----------|--------
2243  * PERIPH_GC | UART3_HCLK
2244  *
2245  * @retval None
2246  */
2247 __STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
2248 {
2249  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_ENABLE;
2250 }
2251 
2252 /**
2253  * @brief Disabling force to turn off the clock for UART3.
2254  *
2255  * Register | BitsName
2256  * ----------|--------
2257  * PERIPH_GC | UART3_HCLK
2258  *
2259  * @retval None
2260  */
2261 __STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
2262 {
2263  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) = CGC_CLOCK_DISABLE;
2264 }
2265 
2266 /**
2267  * @brief Indicate whether the clock for UART3 is forced to close.
2268  *
2269  * Register | BitsName
2270  * ----------|--------
2271  * PERIPH_GC | UART3_HCLK
2272  *
2273  * @retval State of bit (1 or 0).
2274  */
2275 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
2276 {
2277  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2278 }
2279 
2280 /**
2281  * @brief Enabling force to turn off the clock for UART4.
2282  *
2283  * Register | BitsName
2284  * ----------|--------
2285  * PERIPH_GC | UART4_HCLK
2286  *
2287  * @retval None
2288  */
2289 __STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
2290 {
2291  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2292 }
2293 
2294 /**
2295  * @brief Disabling force to turn off the clock for UART4.
2296  *
2297  * Register | BitsName
2298  * ----------|--------
2299  * PERIPH_GC | UART4_HCLK
2300  *
2301  * @retval None
2302  */
2303 __STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
2304 {
2305  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2306 }
2307 
2308 /**
2309  * @brief Indicate whether the clock for UART4 is forced to close.
2310  *
2311  * Register | BitsName
2312  * ----------|--------
2313  * PERIPH_GC | UART4_HCLK
2314  *
2315  * @retval State of bit (1 or 0).
2316  */
2317 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
2318 {
2319  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2320 }
2321 
2322 /**
2323  * @brief Enabling force to turn off the clock for UART5.
2324  *
2325  * Register | BitsName
2326  * ----------|--------
2327  * PERIPH_GC | UART5_HCLK
2328  *
2329  * @retval None
2330  */
2331 __STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
2332 {
2333  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) = CGC_CLOCK_ENABLE;
2334 }
2335 
2336 /**
2337  * @brief Disabling force to turn off the clock for UART5.
2338  *
2339  * Register | BitsName
2340  * ----------|--------
2341  * PERIPH_GC | UART5_HCLK
2342  *
2343  * @retval None
2344  */
2345 __STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
2346 {
2347  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) = CGC_CLOCK_DISABLE;
2348 }
2349 
2350 /**
2351  * @brief Indicate whether the clock for UART5 is forced to close.
2352  *
2353  * Register | BitsName
2354  * ----------|--------
2355  * PERIPH_GC | UART5_HCLK
2356  *
2357  * @retval State of bit (1 or 0).
2358  */
2359 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
2360 {
2361  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_UART5_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2362 }
2363 
2364 /**
2365  * @brief Enabling force to turn off the clock for I2C0.
2366  *
2367  * Register | BitsName
2368  * ----------|--------
2369  * PERIPH_GC | I2C0_HCLK
2370  *
2371  * @retval None
2372  */
2373 __STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
2374 {
2375  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2376 }
2377 
2378 /**
2379  * @brief Disabling force to turn off the clock for I2C0.
2380  *
2381  * Register | BitsName
2382  * ----------|--------
2383  * PERIPH_GC | I2C0_HCLK
2384  *
2385  * @retval None
2386  */
2387 __STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
2388 {
2389  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2390 }
2391 
2392 /**
2393  * @brief Indicate whether the clock for I2C0 is forced to close.
2394  *
2395  * Register | BitsName
2396  * ----------|--------
2397  * PERIPH_GC | I2C0_HCLK
2398  *
2399  * @retval State of bit (1 or 0).
2400  */
2401 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
2402 {
2403  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2404 }
2405 
2406 /**
2407  * @brief Enabling force to turn off the clock for I2C1.
2408  *
2409  * Register | BitsName
2410  * ----------|--------
2411  * PERIPH_GC | I2C1_HCLK
2412  *
2413  * @retval None
2414  */
2415 __STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
2416 {
2417  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2418 }
2419 
2420 /**
2421  * @brief Disabling force to turn off the clock for I2C1.
2422  *
2423  * Register | BitsName
2424  * ----------|--------
2425  * PERIPH_GC | I2C1_HCLK
2426  *
2427  * @retval None
2428  */
2429 __STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
2430 {
2431  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2432 }
2433 
2434 /**
2435  * @brief Indicate whether the clock for I2C1 is forced to close.
2436  *
2437  * Register | BitsName
2438  * ----------|--------
2439  * PERIPH_GC | I2C1_HCLK
2440  *
2441  * @retval State of bit (1 or 0).
2442  */
2443 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
2444 {
2445  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2446 }
2447 
2448 /**
2449  * @brief Enabling force to turn off the clock for I2C2.
2450  *
2451  * Register | BitsName
2452  * ----------|--------
2453  * PERIPH_GC | I2C2_HCLK
2454  *
2455  * @retval None
2456  */
2457 __STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
2458 {
2459  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2460 }
2461 
2462 /**
2463  * @brief Disabling force to turn off the clock for I2C2.
2464  *
2465  * Register | BitsName
2466  * ----------|--------
2467  * PERIPH_GC | I2C2_HCLK
2468  *
2469  * @retval None
2470  */
2471 __STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
2472 {
2473  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2474 }
2475 
2476 /**
2477  * @brief Indicate whether the clock for I2C2 is forced to close.
2478  *
2479  * Register | BitsName
2480  * ----------|--------
2481  * PERIPH_GC | I2C2_HCLK
2482  *
2483  * @retval State of bit (1 or 0).
2484  */
2485 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
2486 {
2487  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2488 }
2489 
2490 /**
2491  * @brief Enabling force to turn off the clock for I2C3.
2492  *
2493  * Register | BitsName
2494  * ----------|--------
2495  * PERIPH_GC | I2C3_HCLK
2496  *
2497  * @retval None
2498  */
2499 __STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
2500 {
2501  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_ENABLE;
2502 }
2503 
2504 /**
2505  * @brief Disabling force to turn off the clock for I2C3.
2506  *
2507  * Register | BitsName
2508  * ----------|--------
2509  * PERIPH_GC | I2C3_HCLK
2510  *
2511  * @retval None
2512  */
2513 __STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
2514 {
2515  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) = CGC_CLOCK_DISABLE;
2516 }
2517 
2518 /**
2519  * @brief Indicate whether the clock for I2C3 is forced to close.
2520  *
2521  * Register | BitsName
2522  * ----------|--------
2523  * PERIPH_GC | I2C3_HCLK
2524  *
2525  * @retval State of bit (1 or 0).
2526  */
2527 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
2528 {
2529  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C3_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2530 }
2531 
2532 /**
2533  * @brief Enabling force to turn off the clock for I2C4.
2534  *
2535  * Register | BitsName
2536  * ----------|--------
2537  * PERIPH_GC | I2C4_HCLK
2538  *
2539  * @retval None
2540  */
2541 __STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
2542 {
2543  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) = CGC_CLOCK_ENABLE;
2544 }
2545 
2546 /**
2547  * @brief Disabling force to turn off the clock for I2C4.
2548  *
2549  * Register | BitsName
2550  * ----------|--------
2551  * PERIPH_GC | I2C4_HCLK
2552  *
2553  * @retval None
2554  */
2555 __STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
2556 {
2557  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) = CGC_CLOCK_DISABLE;
2558 }
2559 
2560 /**
2561  * @brief Indicate whether the clock for I2C4 is forced to close.
2562  *
2563  * Register | BitsName
2564  * ----------|--------
2565  * PERIPH_GC | I2C4_HCLK
2566  *
2567  * @retval State of bit (1 or 0).
2568  */
2569 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
2570 {
2571  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2572 }
2573 
2574 /**
2575  * @brief Enabling force to turn off the clock for I2C5.
2576  *
2577  * Register | BitsName
2578  * ----------|--------
2579  * PERIPH_GC | I2C5_HCLK
2580  *
2581  * @retval None
2582  */
2583 __STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
2584 {
2585  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) = CGC_CLOCK_ENABLE;
2586 }
2587 
2588 /**
2589  * @brief Disabling force to turn off the clock for I2C5.
2590  *
2591  * Register | BitsName
2592  * ----------|--------
2593  * PERIPH_GC | I2C5_HCLK
2594  *
2595  * @retval None
2596  */
2597 __STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
2598 {
2599  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) = CGC_CLOCK_DISABLE;
2600 }
2601 
2602 /**
2603  * @brief Indicate whether the clock for I2C5 is forced to close.
2604  *
2605  * Register | BitsName
2606  * ----------|--------
2607  * PERIPH_GC | I2C5_HCLK
2608  *
2609  * @retval State of bit (1 or 0).
2610  */
2611 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
2612 {
2613  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2C5_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2614 }
2615 
2616 /**
2617  * @brief Enabling force to turn off the clock for SPIM.
2618  *
2619  * Register | BitsName
2620  * ----------|--------
2621  * PERIPH_GC | SPIM_HCLK
2622  *
2623  * @retval None
2624  */
2625 __STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
2626 {
2627  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_ENABLE;
2628 }
2629 
2630 /**
2631  * @brief Disabling force to turn off the clock for SPIM.
2632  *
2633  * Register | BitsName
2634  * ----------|--------
2635  * PERIPH_GC | SPIM_HCLK
2636  *
2637  * @retval None
2638  */
2639 __STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
2640 {
2641  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) = CGC_CLOCK_DISABLE;
2642 }
2643 
2644 /**
2645  * @brief Indicate whether the clock for SPIM is forced to close.
2646  *
2647  * Register | BitsName
2648  * ----------|--------
2649  * PERIPH_GC | SPIM_HCLK
2650  *
2651  * @retval State of bit (1 or 0).
2652  */
2653 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
2654 {
2655  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_M_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2656 }
2657 
2658 /**
2659  * @brief Enabling force to turn off the clock for SPIS.
2660  *
2661  * Register | BitsName
2662  * ----------|--------
2663  * PERIPH_GC | SPIS_HCLK
2664  *
2665  * @retval None
2666  */
2667 __STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
2668 {
2669  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2670 }
2671 
2672 /**
2673  * @brief Disabling force to turn off the clock for SPIS.
2674  *
2675  * Register | BitsName
2676  * ----------|--------
2677  * PERIPH_GC | SPIS_HCLK
2678  *
2679  * @retval None
2680  */
2681 __STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
2682 {
2683  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2684 }
2685 
2686 /**
2687  * @brief Indicate whether the clock for SPIS is forced to close.
2688  *
2689  * Register | BitsName
2690  * ----------|--------
2691  * PERIPH_GC | SPIS_HCLK
2692  *
2693  * @retval State of bit (1 or 0).
2694  */
2695 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
2696 {
2697  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SPI_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2698 }
2699 
2700 /**
2701  * @brief Enabling force to turn off the clock for QSPI0.
2702  *
2703  * Register | BitsName
2704  * ----------|--------
2705  * PERIPH_GC | QSPI0_HCLK
2706  *
2707  * @retval None
2708  */
2709 __STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
2710 {
2711  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_ENABLE;
2712 }
2713 
2714 /**
2715  * @brief Disabling force to turn off the clock for QSPI0.
2716  *
2717  * Register | BitsName
2718  * ----------|--------
2719  * PERIPH_GC | QSPI0_HCLK
2720  *
2721  * @retval None
2722  */
2723 __STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
2724 {
2725  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) = CGC_CLOCK_DISABLE;
2726 }
2727 
2728 /**
2729  * @brief Indicate whether the clock for QSPI0 is forced to close.
2730  *
2731  * Register | BitsName
2732  * ----------|--------
2733  * PERIPH_GC | QSPI0_HCLK
2734  *
2735  * @retval State of bit (1 or 0).
2736  */
2737 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
2738 {
2739  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2740 }
2741 
2742 /**
2743  * @brief Enabling force to turn off the clock for QSPI1.
2744  *
2745  * Register | BitsName
2746  * ----------|--------
2747  * PERIPH_GC | QSPI1_HCLK
2748  *
2749  * @retval None
2750  */
2751 __STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
2752 {
2753  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_ENABLE;
2754 }
2755 
2756 /**
2757  * @brief Disabling force to turn off the clock for QSPI1.
2758  *
2759  * Register | BitsName
2760  * ----------|--------
2761  * PERIPH_GC | QSPI1_HCLK
2762  *
2763  * @retval None
2764  */
2765 __STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
2766 {
2767  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) = CGC_CLOCK_DISABLE;
2768 }
2769 
2770 /**
2771  * @brief Indicate whether the clock for QSPI1 is forced to close.
2772  *
2773  * Register | BitsName
2774  * ----------|--------
2775  * PERIPH_GC | QSPI1_HCLK
2776  *
2777  * @retval State of bit (1 or 0).
2778  */
2779 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
2780 {
2781  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2782 }
2783 
2784 /**
2785  * @brief Enabling force to turn off the clock for QSPI2.
2786  *
2787  * Register | BitsName
2788  * ----------|--------
2789  * PERIPH_GC | QSPI2_HCLK
2790  *
2791  * @retval None
2792  */
2793 __STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
2794 {
2795  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_ENABLE;
2796 }
2797 
2798 /**
2799  * @brief Disabling force to turn off the clock for QSPI2.
2800  *
2801  * Register | BitsName
2802  * ----------|--------
2803  * PERIPH_GC | QSPI2_HCLK
2804  *
2805  * @retval None
2806  */
2807 __STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
2808 {
2809  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) = CGC_CLOCK_DISABLE;
2810 }
2811 
2812 /**
2813  * @brief Indicate whether the clock for QSPI2 is forced to close.
2814  *
2815  * Register | BitsName
2816  * ----------|--------
2817  * PERIPH_GC | QSPI2_HCLK
2818  *
2819  * @retval State of bit (1 or 0).
2820  */
2821 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
2822 {
2823  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_QSPI2_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2824 }
2825 
2826 
2827 /**
2828  * @brief Enabling force to turn off the clock for I2S master.
2829  *
2830  * Register | BitsName
2831  * ----------|--------
2832  * PERIPH_GC | I2S_HCLK
2833  *
2834  * @retval None
2835  */
2836 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
2837 {
2838  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2839 }
2840 
2841 /**
2842  * @brief Disabling force to turn off the clock for I2S master.
2843  *
2844  * Register | BitsName
2845  * ----------|--------
2846  * PERIPH_GC | I2S_HCLK
2847  *
2848  * @retval None
2849  */
2850 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
2851 {
2852  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2853 }
2854 
2855 /**
2856  * @brief Indicate whether the clock for I2S master is forced to close.
2857  *
2858  * Register | BitsName
2859  * ----------|--------
2860  * PERIPH_GC | I2S_HCLK
2861  *
2862  * @retval State of bit (1 or 0).
2863  */
2864 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
2865 {
2866  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2867 }
2868 
2869 /**
2870  * @brief Enabling force to turn off the clock for I2S slave.
2871  *
2872  * Register | BitsName
2873  * ----------|--------
2874  * PERIPH_GC | I2S_S_PCLK
2875  *
2876  * @retval None
2877  */
2878 __STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
2879 {
2880  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_ENABLE;
2881 }
2882 
2883 /**
2884  * @brief Disabling force to turn off the clock for I2S slave.
2885  *
2886  * Register | BitsName
2887  * ----------|--------
2888  * PERIPH_GC | I2S_S_PCLK
2889  *
2890  * @retval None
2891  */
2892 __STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
2893 {
2894  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) = CGC_CLOCK_DISABLE;
2895 }
2896 
2897 /**
2898  * @brief Indicate whether the clock for I2S slave is forced to close.
2899  *
2900  * Register | BitsName
2901  * ----------|--------
2902  * PERIPH_GC | I2S_S_PCLK
2903  *
2904  * @retval State of bit (1 or 0).
2905  */
2906 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
2907 {
2908  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_I2S_S_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2909 }
2910 
2911 /**
2912  * @brief Enabling force to turn off the clock for DSPI slave.
2913  *
2914  * Register | BitsName
2915  * ----------|--------
2916  * PERIPH_GC | DSPI_PCLK
2917  *
2918  * @retval None
2919  */
2920 __STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
2921 {
2922  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_ENABLE;
2923 }
2924 
2925 /**
2926  * @brief Disabling force to turn off the clock for DSPI slave.
2927  *
2928  * Register | BitsName
2929  * ----------|--------
2930  * PERIPH_GC | DSPI_PCLK
2931  *
2932  * @retval None
2933  */
2934 __STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
2935 {
2936  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) = CGC_CLOCK_DISABLE;
2937 }
2938 
2939 /**
2940  * @brief Indicate whether the clock for DSPI is forced to close.
2941  *
2942  * Register | BitsName
2943  * ----------|--------
2944  * PERIPH_GC | DSPI_PCLK
2945  *
2946  * @retval State of bit (1 or 0).
2947  */
2948 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
2949 {
2950  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_DSPI_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2951 }
2952 
2953 /**
2954  * @brief Enabling force to turn off the clock for PDM slave.
2955  *
2956  * Register | BitsName
2957  * ----------|--------
2958  * PERIPH_GC | PDM_PCLK
2959  *
2960  * @retval None
2961  */
2962 __STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
2963 {
2964  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_ENABLE;
2965 }
2966 
2967 /**
2968  * @brief Disabling force to turn off the clock for PDM slave.
2969  *
2970  * Register | BitsName
2971  * ----------|--------
2972  * PERIPH_GC | PDM_PCLK
2973  *
2974  * @retval None
2975  */
2976 __STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
2977 {
2978  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) = CGC_CLOCK_DISABLE;
2979 }
2980 
2981 /**
2982  * @brief Indicate whether the clock for PDM is forced to close.
2983  *
2984  * Register | BitsName
2985  * ----------|--------
2986  * PERIPH_GC | PDM_PCLK
2987  *
2988  * @retval State of bit (1 or 0).
2989  */
2990 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
2991 {
2992  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PDM_PCLK_Pos) == (CGC_CLOCK_ENABLE));
2993 }
2994 
2995 /**
2996  * @brief Enabling force to turn off the div4 clock for security blocks.
2997  *
2998  * Register | BitsName
2999  * ----------|--------
3000  * PERIPH_GC | I2S_HCLK
3001  *
3002  * @retval None
3003  */
3004 __STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
3005 {
3006  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
3007 }
3008 
3009 /**
3010  * @brief Disabling force to turn off the div4 clock for security blocks.
3011  *
3012  * Register | BitsName
3013  * ----------|--------
3014  * PERIPH_GC | I2S_HCLK
3015  *
3016  * @retval None
3017  */
3019 {
3020  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
3021 }
3022 
3023 /**
3024  * @brief Indicate whether the div4 clock for security blocks is forced to close.
3025  *
3026  * Register | BitsName
3027  * ----------|--------
3028  * PERIPH_GC | I2S_HCLK
3029  *
3030  * @retval State of bit (1 or 0).
3031  */
3032 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
3033 {
3034  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3035 }
3036 /**
3037  * @brief Enabling force to turn off the div4 clock for xf qspi blocks.
3038  *
3039  * Register | BitsName
3040  * ----------|--------
3041  * PERIPH_GC | XQSPI_HCLK
3042  *
3043  * @retval None
3044  */
3046 {
3047  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_ENABLE;
3048 }
3049 
3050 /**
3051  * @brief Disabling force to turn off the div4 clock for xf qspi blocks.
3052  *
3053  * Register | BitsName
3054  * ----------|--------
3055  * PERIPH_GC | XQSPI_HCLK
3056  *
3057  * @retval None
3058  */
3060 {
3061  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) = CGC_CLOCK_DISABLE;
3062 }
3063 
3064 /**
3065  * @brief Indicate whether the div4 clock for xf qspi blocks is forced to close.
3066  *
3067  * Register | BitsName
3068  * ----------|--------
3069  * PERIPH_GC | XQSPI_HCLK
3070  *
3071  * @retval State of bit (1 or 0).
3072  */
3074 {
3075  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3076 }
3077 
3078 /**
3079  * @brief Enabling force to turn off the clock for PWM0.
3080  *
3081  * Register | BitsName
3082  * ----------|--------
3083  * PERIPH_GC | PWM0_PCLK
3084  *
3085  * @retval None
3086  */
3087 __STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
3088 {
3089  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_ENABLE;
3090 }
3091 
3092 /**
3093  * @brief Disabling force to turn off the clock for PWM0.
3094  *
3095  * Register | BitsName
3096  * ----------|--------
3097  * PERIPH_GC | PWM0_PCLK
3098  *
3099  * @retval None
3100  */
3101 __STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
3102 {
3103  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) = CGC_CLOCK_DISABLE;
3104 }
3105 
3106 /**
3107  * @brief Indicate whether the clock for PWM0 is forced to close.
3108  *
3109  * Register | BitsName
3110  * ----------|--------
3111  * PERIPH_GC | PWM0_PCLK
3112  *
3113  * @retval State of bit (1 or 0).
3114  */
3115 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
3116 {
3117  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_0_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3118 }
3119 
3120 /**
3121  * @brief Enabling force to turn off the clock for PWM1.
3122  *
3123  * Register | BitsName
3124  * ----------|--------
3125  * PERIPH_GC | PWM1_PCLK
3126  *
3127  * @retval None
3128  */
3129 __STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
3130 {
3131  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_ENABLE;
3132 }
3133 
3134 /**
3135  * @brief Disabling force to turn off the clock for PWM1.
3136  *
3137  * Register | BitsName
3138  * ----------|--------
3139  * PERIPH_GC | PWM1_PCLK
3140  *
3141  * @retval None
3142  */
3143 __STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
3144 {
3145  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) = CGC_CLOCK_DISABLE;
3146 }
3147 
3148 /**
3149  * @brief Indicate whether the clock for PWM1 is forced to close.
3150  *
3151  * Register | BitsName
3152  * ----------|--------
3153  * PERIPH_GC | PWM1_PCLK
3154  *
3155  * @retval State of bit (1 or 0).
3156  */
3157 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
3158 {
3159  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_PWM_1_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3160 }
3161 
3162 /**
3163  * @brief Enabling force to turn off the clock for VTTBL.
3164  *
3165  * Register | BitsName
3166  * ----------|--------
3167  * PERIPH_GC | VTTBL_PCLK
3168  *
3169  * @retval None
3170  */
3171 __STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
3172 {
3173  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_ENABLE;
3174 }
3175 
3176 /**
3177  * @brief Disabling force to turn off the clock for VTTBL.
3178  *
3179  * Register | BitsName
3180  * ----------|--------
3181  * PERIPH_GC | VTTBL_PCLK
3182  *
3183  * @retval None
3184  */
3185 __STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
3186 {
3187  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) = CGC_CLOCK_DISABLE;
3188 }
3189 
3190 /**
3191  * @brief Indicate whether the clock for VTTBL is forced to close.
3192  *
3193  * Register | BitsName
3194  * ----------|--------
3195  * PERIPH_GC | VTTBL_PCLK
3196  *
3197  * @retval State of bit (1 or 0).
3198  */
3199 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
3200 {
3201  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_PCLK_OFF, MCU_SUB_FORCE_VTTBL_PCLK_Pos) == (CGC_CLOCK_ENABLE));
3202 }
3203 
3204 /**
3205  * @brief Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
3206  *
3207  * Register | BitsName
3208  * ---------|--------
3209  * CG_LP_EN | UART_LP_SCLK
3210  * CG_LP_EN | UART_LP_PCLK
3211  * CG_LP_EN | I2S_LP
3212  * CG_LP_EN | SPIM_LP_SCLK
3213  * CG_LP_EN | SPIS_LP_SCLK
3214  * CG_LP_EN | I2C_LP_SCLK
3215  * CG_LP_EN | AHB_BUS_LP
3216  *
3217  * @param clk_mask This parameter can be a combination of the following values:
3218  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
3219  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
3220  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
3221  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
3222  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
3223  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
3224  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
3225  * @retval None
3226  */
3227 __STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
3228 {
3229  WRITE_REG(MCU_RET->MCU_PERIPH_CG_LP_EN, clk_mask);
3230 }
3231 
3232 /**
3233  * @brief Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
3234  *
3235  * Register | BitsName
3236  * ---------|--------
3237  * CG_LP_EN | UART_LP_SCLK
3238  * CG_LP_EN | UART_LP_PCLK
3239  * CG_LP_EN | I2S_LP
3240  * CG_LP_EN | SPIM_LP_SCLK
3241  * CG_LP_EN | SPIS_LP_SCLK
3242  * CG_LP_EN | I2C_LP_SCLK
3243  * CG_LP_EN | AHB_BUS_LP
3244  *
3245  * @retval Returned value can be a combination of the following values:
3246  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_AHB_BUS_LP_EN
3247  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN
3248  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN
3249  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN
3250  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_I2S_LP_EN
3251  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_PCLK_EN
3252  * @arg @ref LL_CGC_MCU_PERIPH_CG_LP_EN_UART_LP_SCLK_EN
3253  */
3254 __STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
3255 {
3256  return READ_REG(MCU_RET->MCU_PERIPH_CG_LP_EN);
3257 }
3258 
3259 /**
3260  * @brief Enable uart sclk low-power feature
3261  *
3262  * Register | BitsName
3263  * ---------|--------
3264  * CG_LP_EN | UART_LP_SCLK
3265  *
3266  * @retval None
3267  */
3268 __STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
3269 {
3270  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3271 }
3272 
3273 /**
3274  * @brief Disable uart sclk low-power feature
3275  *
3276  * Register | BitsName
3277  * ---------|--------
3278  * CG_LP_EN | UART_LP_SCLK
3279  *
3280  * @retval None
3281  */
3282 __STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
3283 {
3284  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3285 }
3286 
3287 /**
3288  * @brief Indicate whether the uart sclk low-power is enabled.
3289  *
3290  * Register | BitsName
3291  * ---------|--------
3292  * CG_LP_EN | UART_LP_SCLK
3293  *
3294  * @retval State of bit (1 or 0).
3295  */
3296 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
3297 {
3298  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3299 }
3300 
3301 /**
3302  * @brief Enable uart pclk low-power feature
3303  *
3304  * Register | BitsName
3305  * ---------|--------
3306  * CG_LP_EN | UART_LP_PCLK
3307  *
3308  * @retval None
3309  */
3310 __STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
3311 {
3312  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3313 }
3314 
3315 /**
3316  * @brief Disable uart pclk low-power feature
3317  *
3318  * Register | BitsName
3319  * ---------|--------
3320  * CG_LP_EN | UART_LP_PCLK
3321  *
3322  * @retval None
3323  */
3324 __STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
3325 {
3326  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3327 }
3328 
3329 /**
3330  * @brief Indicate whether the uart pclk low-power is enabled.
3331  *
3332  * Register | BitsName
3333  * ---------|--------
3334  * CG_LP_EN | UART_LP_PCLK
3335  *
3336  * @retval State of bit (1 or 0).
3337  */
3338 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
3339 {
3340  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_UART_LP_PCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3341 }
3342 
3343 /**
3344  * @brief Enable i2s low-power feature
3345  *
3346  * Register | BitsName
3347  * ---------|--------
3348  * CG_LP_EN | I2S_LP
3349  *
3350  * @retval None
3351  */
3352 __STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
3353 {
3354  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3355 }
3356 
3357 /**
3358  * @brief Disable i2s low-power feature
3359  *
3360  * Register | BitsName
3361  * ---------|--------
3362  * CG_LP_EN | I2S_LP
3363  *
3364  * @retval None
3365  */
3366 __STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
3367 {
3368  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3369 }
3370 
3371 /**
3372  * @brief Indicate whether the i2s low-power is enabled.
3373  *
3374  * Register | BitsName
3375  * ---------|--------
3376  * CG_LP_EN | I2S_LP
3377  *
3378  * @retval State of bit (1 or 0).
3379  */
3380 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
3381 {
3382  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2S_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3383 }
3384 
3385 /**
3386  * @brief Enable spim sclk low-power feature
3387  *
3388  * Register | BitsName
3389  * ---------|--------
3390  * CG_LP_EN | SPIM_LP_SCLK
3391  *
3392  * @retval None
3393  */
3394 __STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
3395 {
3396  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3397 }
3398 
3399 /**
3400  * @brief Disable spim sclk low-power feature
3401  *
3402  * Register | BitsName
3403  * ---------|--------
3404  * CG_LP_EN | SPIM_LP_SCLK
3405  *
3406  * @retval None
3407  */
3408 __STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
3409 {
3410  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3411 }
3412 
3413 /**
3414  * @brief Indicate whether the spim sclk low-power is enabled.
3415  *
3416  * Register | BitsName
3417  * ---------|--------
3418  * CG_LP_EN | SPIM_LP_SCLK
3419  *
3420  * @retval State of bit (1 or 0).
3421  */
3422 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
3423 {
3424  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIM_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3425 }
3426 
3427 /**
3428  * @brief Enable spis sclk low-power feature
3429  *
3430  * Register | BitsName
3431  * ---------|--------
3432  * CG_LP_EN | SPIS_LP_SCLK
3433  *
3434  * @retval None
3435  */
3436 __STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
3437 {
3438  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3439 }
3440 
3441 /**
3442  * @brief Disable spis sclk low-power feature
3443  *
3444  * Register | BitsName
3445  * ---------|--------
3446  * CG_LP_EN | SPIS_LP_SCLK
3447  *
3448  * @retval None
3449  */
3450 __STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
3451 {
3452  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3453 }
3454 
3455 /**
3456  * @brief Indicate whether the spis sclk low-power is enabled.
3457  *
3458  * Register | BitsName
3459  * ---------|--------
3460  * CG_LP_EN | SPIS_LP_SCLK
3461  *
3462  * @retval State of bit (1 or 0).
3463  */
3464 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
3465 {
3466  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_SPIS_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3467 }
3468 
3469 /**
3470  * @brief Enable i2c sclk low-power feature
3471  *
3472  * Register | BitsName
3473  * ---------|--------
3474  * CG_LP_EN | I2C_LP_SCLK
3475  *
3476  * @retval None
3477  */
3478 __STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
3479 {
3480  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_ENABLE;
3481 }
3482 
3483 /**
3484  * @brief Disable i2c sclk low-power feature
3485  *
3486  * Register | BitsName
3487  * ---------|--------
3488  * CG_LP_EN | I2C_LP_SCLK
3489  *
3490  * @retval None
3491  */
3492 __STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
3493 {
3494  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) = CGC_CLOCK_DISABLE;
3495 }
3496 
3497 /**
3498  * @brief Indicate whether the i2c sclk low-power is enabled.
3499  *
3500  * Register | BitsName
3501  * ---------|--------
3502  * CG_LP_EN | I2C_LP_SCLK
3503  *
3504  * @retval State of bit (1 or 0).
3505  */
3506 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
3507 {
3508  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_I2C_LP_SCLK_EN_Pos) == (CGC_CLOCK_ENABLE));
3509 }
3510 
3511 /**
3512  * @brief Enable ahb bus low-power feature
3513  *
3514  * Register | BitsName
3515  * ---------|--------
3516  * CG_LP_EN | AHB_BUS_LP
3517  *
3518  * @retval None
3519  */
3520 __STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
3521 {
3522  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_ENABLE;
3523 }
3524 
3525 /**
3526  * @brief Disable ahb bus low-power feature
3527  *
3528  * Register | BitsName
3529  * ---------|--------
3530  * CG_LP_EN | AHB_BUS_LP
3531  *
3532  * @retval None
3533  */
3534 __STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
3535 {
3536  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) = CGC_CLOCK_DISABLE;
3537 }
3538 
3539 /**
3540  * @brief Indicate whether the ahb bus low-power is enabled.
3541  *
3542  * Register | BitsName
3543  * ---------|--------
3544  * CG_LP_EN | AHB_BUS_LP
3545  *
3546  * @retval State of bit (1 or 0).
3547  */
3548 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
3549 {
3550  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_AHB_BUS_LP_EN_Pos) == (CGC_CLOCK_ENABLE));
3551 }
3552 
3553 /**
3554  * @brief Enable QSPIM low-power feature
3555  *
3556  * Register | BitsName
3557  * ---------|--------
3558  * CG_LP_EN | QSPIM_LP
3559  *
3560  * @retval None
3561  */
3562 __STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
3563 {
3564  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_ENABLE;
3565 }
3566 
3567 /**
3568  * @brief Disable QSPIM low-power feature
3569  *
3570  * Register | BitsName
3571  * ---------|--------
3572  * CG_LP_EN | QSPIM_LP
3573  *
3574  * @retval None
3575  */
3576 __STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
3577 {
3578  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) = CGC_CLOCK_DISABLE;
3579 }
3580 
3581 /**
3582  * @brief Indicate whether the QSPIM low-power is enabled.
3583  *
3584  * Register | BitsName
3585  * ---------|--------
3586  * CG_LP_EN | QSPIM_LP
3587  *
3588  * @retval State of bit (1 or 0).
3589  */
3590 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
3591 {
3592  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_EN_QSPIM_EN_Pos) == (CGC_CLOCK_ENABLE));
3593 }
3594 
3595 /**
3596  * @brief Enable AHB2APB bus low-power feature
3597  *
3598  * Register | BitsName
3599  * ---------|--------
3600  * CG_LP_EN | AHB2APB_BUS_LP
3601  *
3602  * @retval None
3603  */
3605 {
3606  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3607 }
3608 
3609 /**
3610  * @brief Disable AHB2APB bus low-power feature
3611  *
3612  * Register | BitsName
3613  * ---------|--------
3614  * CG_LP_EN | AHB2APB_BUS_LP
3615  *
3616  * @retval None
3617  */
3619 {
3620  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3621 }
3622 
3623 /**
3624  * @brief Indicate whether the AHB2APB bus low-power is enabled.
3625  *
3626  * Register | BitsName
3627  * ---------|--------
3628  * CG_LP_EN | AHB2APB_BUS_LP
3629  *
3630  * @retval State of bit (1 or 0).
3631  */
3632 __STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
3633 {
3634  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_SYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3635 }
3636 
3637 /**
3638  * @brief Enable ahb bus low-power feature
3639  *
3640  * Register | BitsName
3641  * ---------|--------
3642  * CG_LP_EN | AHB_BUS_LP
3643  *
3644  * @retval None
3645  */
3647 {
3648  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_ENABLE;
3649 }
3650 
3651 /**
3652  * @brief Disable ahb bus low-power feature
3653  *
3654  * Register | BitsName
3655  * ---------|--------
3656  * CG_LP_EN | AHB_BUS_LP
3657  *
3658  * @retval None
3659  */
3661 {
3662  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) = CGC_CLOCK_DISABLE;
3663 }
3664 
3665 /**
3666  * @brief Indicate whether the ahb bus low-power is enabled.
3667  *
3668  * Register | BitsName
3669  * ---------|--------
3670  * CG_LP_EN | AHB_BUS_LP
3671  *
3672  * @retval State of bit (1 or 0).
3673  */
3675 {
3676  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CG_LP_EN, MCU_SUB_PERIPH_CG_LP_AHB2APB_ASYNC_EN_Pos) == (CGC_CLOCK_ENABLE));
3677 }
3678 
3679 /**
3680  * @brief Enable turn UART0 off during WFI/WFE
3681  *
3682  * Register | BitsName
3683  * ---------|--------
3684  * CLK_SLP_OFF | UART0_SLP
3685  *
3686  * @retval None
3687  */
3688 __STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
3689 {
3690  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_ENABLE;
3691 }
3692 
3693 /**
3694  * @brief Disable turn UART0 off during WFI/WFE
3695  *
3696  * Register | BitsName
3697  * ---------|--------
3698  * CLK_SLP_OFF | UART0_SLP
3699  *
3700  * @retval None
3701  */
3702 __STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
3703 {
3704  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) = CGC_CLOCK_DISABLE;
3705 }
3706 
3707 /**
3708  * @brief Indicate whether turn UART0 off during WFI/WFE is enabled.
3709  *
3710  * Register | BitsName
3711  * ---------|--------
3712  * CLK_SLP_OFF | UART0_SLP
3713  *
3714  * @retval State of bit (1 or 0).
3715  */
3716 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
3717 {
3718  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART0_Pos) == (CGC_CLOCK_ENABLE));
3719 }
3720 
3721 /**
3722  * @brief Enable turn UART1 off during WFI/WFE
3723  *
3724  * Register | BitsName
3725  * ---------|--------
3726  * CLK_SLP_OFF | UART1_SLP
3727  *
3728  * @retval None
3729  */
3730 __STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
3731 {
3732  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_ENABLE;
3733 }
3734 
3735 /**
3736  * @brief Disable turn UART1 off during WFI/WFE
3737  *
3738  * Register | BitsName
3739  * ---------|--------
3740  * CLK_SLP_OFF | UART1_SLP
3741  *
3742  * @retval None
3743  */
3744 __STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
3745 {
3746  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) = CGC_CLOCK_DISABLE;
3747 }
3748 
3749 /**
3750  * @brief Indicate whether turn UART1 off during WFI/WFE is enabled.
3751  *
3752  * Register | BitsName
3753  * ---------|--------
3754  * CLK_SLP_OFF | UART1_SLP
3755  *
3756  * @retval State of bit (1 or 0).
3757  */
3758 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
3759 {
3760  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART1_Pos) == (CGC_CLOCK_ENABLE));
3761 }
3762 
3763 /**
3764  * @brief Enable turn UART2 off during WFI/WFE
3765  *
3766  * Register | BitsName
3767  * ---------|--------
3768  * CLK_SLP_OFF | UART2_SLP
3769  *
3770  * @retval None
3771  */
3772 __STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
3773 {
3774  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_ENABLE;
3775 }
3776 
3777 /**
3778  * @brief Disable turn UART2 off during WFI/WFE
3779  *
3780  * Register | BitsName
3781  * ---------|--------
3782  * CLK_SLP_OFF | UART2_SLP
3783  *
3784  * @retval None
3785  */
3786 __STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
3787 {
3788  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) = CGC_CLOCK_DISABLE;
3789 }
3790 
3791 /**
3792  * @brief Indicate whether turn UART2 off during WFI/WFE is enabled.
3793  *
3794  * Register | BitsName
3795  * ---------|--------
3796  * CLK_SLP_OFF | UART2_SLP
3797  *
3798  * @retval State of bit (1 or 0).
3799  */
3800 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
3801 {
3802  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART2_Pos) == (CGC_CLOCK_ENABLE));
3803 }
3804 
3805 /**
3806  * @brief Enable turn UART3 off during WFI/WFE
3807  *
3808  * Register | BitsName
3809  * ---------|--------
3810  * CLK_SLP_OFF | UART3_SLP
3811  *
3812  * @retval None
3813  */
3814 __STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
3815 {
3816  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_ENABLE;
3817 }
3818 
3819 /**
3820  * @brief Disable turn UART3 off during WFI/WFE
3821  *
3822  * Register | BitsName
3823  * ---------|--------
3824  * CLK_SLP_OFF | UART3_SLP
3825  *
3826  * @retval None
3827  */
3828 __STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
3829 {
3830  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) = CGC_CLOCK_DISABLE;
3831 }
3832 
3833 /**
3834  * @brief Indicate whether turn UART3 off during WFI/WFE is enabled.
3835  *
3836  * Register | BitsName
3837  * ---------|--------
3838  * CLK_SLP_OFF | UART3_SLP
3839  *
3840  * @retval State of bit (1 or 0).
3841  */
3842 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
3843 {
3844  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART3_Pos) == (CGC_CLOCK_ENABLE));
3845 }
3846 
3847 /**
3848  * @brief Enable turn UART4 off during WFI/WFE
3849  *
3850  * Register | BitsName
3851  * ---------|--------
3852  * CLK_SLP_OFF | UART4_SLP
3853  *
3854  * @retval None
3855  */
3856 __STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
3857 {
3858  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) = CGC_CLOCK_ENABLE;
3859 }
3860 
3861 /**
3862  * @brief Disable turn UART4 off during WFI/WFE
3863  *
3864  * Register | BitsName
3865  * ---------|--------
3866  * CLK_SLP_OFF | UART4_SLP
3867  *
3868  * @retval None
3869  */
3870 __STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
3871 {
3872  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) = CGC_CLOCK_DISABLE;
3873 }
3874 
3875 /**
3876  * @brief Indicate whether turn UART4 off during WFI/WFE is enabled.
3877  *
3878  * Register | BitsName
3879  * ---------|--------
3880  * CLK_SLP_OFF | UART4_SLP
3881  *
3882  * @retval State of bit (1 or 0).
3883  */
3884 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
3885 {
3886  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART4_Pos) == (CGC_CLOCK_ENABLE));
3887 }
3888 
3889 /**
3890  * @brief Enable turn UART5 off during WFI/WFE
3891  *
3892  * Register | BitsName
3893  * ---------|--------
3894  * CLK_SLP_OFF | UART5_SLP
3895  *
3896  * @retval None
3897  */
3898 __STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
3899 {
3900  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) = CGC_CLOCK_ENABLE;
3901 }
3902 
3903 /**
3904  * @brief Disable turn UART5 off during WFI/WFE
3905  *
3906  * Register | BitsName
3907  * ---------|--------
3908  * CLK_SLP_OFF | UART5_SLP
3909  *
3910  * @retval None
3911  */
3912 __STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
3913 {
3914  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) = CGC_CLOCK_DISABLE;
3915 }
3916 
3917 /**
3918  * @brief Indicate whether turn UART5 off during WFI/WFE is enabled.
3919  *
3920  * Register | BitsName
3921  * ---------|--------
3922  * CLK_SLP_OFF | UART5_SLP
3923  *
3924  * @retval State of bit (1 or 0).
3925  */
3926 __STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
3927 {
3928  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_UART5_Pos) == (CGC_CLOCK_ENABLE));
3929 }
3930 
3931 /**
3932  * @brief Enable turn I2C0 off during WFI/WFE
3933  *
3934  * Register | BitsName
3935  * ---------|--------
3936  * CLK_SLP_OFF | I2C0_SLP
3937  *
3938  * @retval None
3939  */
3940 __STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
3941 {
3942  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_ENABLE;
3943 }
3944 
3945 /**
3946  * @brief Disable turn I2C0 off during WFI/WFE
3947  *
3948  * Register | BitsName
3949  * ---------|--------
3950  * CLK_SLP_OFF | I2C0_SLP
3951  *
3952  * @retval None
3953  */
3954 __STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
3955 {
3956  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) = CGC_CLOCK_DISABLE;
3957 }
3958 
3959 /**
3960  * @brief Indicate whether turn I2C0 off during WFI/WFE is enabled.
3961  *
3962  * Register | BitsName
3963  * ---------|--------
3964  * CLK_SLP_OFF | I2C0_SLP
3965  *
3966  * @retval State of bit (1 or 0).
3967  */
3968 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
3969 {
3970  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0_Pos) == (CGC_CLOCK_ENABLE));
3971 }
3972 
3973 /**
3974  * @brief Enable turn I2C1 off during WFI/WFE
3975  *
3976  * Register | BitsName
3977  * ---------|--------
3978  * CLK_SLP_OFF | I2C1_SLP
3979  *
3980  * @retval None
3981  */
3982 __STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
3983 {
3984  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_ENABLE;
3985 }
3986 
3987 /**
3988  * @brief Disable turn I2C1 off during WFI/WFE
3989  *
3990  * Register | BitsName
3991  * ---------|--------
3992  * CLK_SLP_OFF | I2C1_SLP
3993  *
3994  * @retval None
3995  */
3996 __STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
3997 {
3998  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) = CGC_CLOCK_DISABLE;
3999 }
4000 
4001 /**
4002  * @brief Indicate whether turn I2C1 off during WFI/WFE is enabled.
4003  *
4004  * Register | BitsName
4005  * ---------|--------
4006  * CLK_SLP_OFF | I2C1_SLP
4007  *
4008  * @retval State of bit (1 or 0).
4009  */
4010 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
4011 {
4012  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1_Pos) == (CGC_CLOCK_ENABLE));
4013 }
4014 
4015 /**
4016  * @brief Enable turn I2C2 off during WFI/WFE
4017  *
4018  * Register | BitsName
4019  * ---------|--------
4020  * CLK_SLP_OFF | I2C2_SLP
4021  *
4022  * @retval None
4023  */
4024 __STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
4025 {
4026  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_ENABLE;
4027 }
4028 
4029 /**
4030  * @brief Disable turn I2C2 off during WFI/WFE
4031  *
4032  * Register | BitsName
4033  * ---------|--------
4034  * CLK_SLP_OFF | I2C2_SLP
4035  *
4036  * @retval None
4037  */
4038 __STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
4039 {
4040  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) = CGC_CLOCK_DISABLE;
4041 }
4042 
4043 /**
4044  * @brief Indicate whether turn I2C2 off during WFI/WFE is enabled.
4045  *
4046  * Register | BitsName
4047  * ---------|--------
4048  * CLK_SLP_OFF | I2C2_SLP
4049  *
4050  * @retval State of bit (1 or 0).
4051  */
4052 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
4053 {
4054  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C2_Pos) == (CGC_CLOCK_ENABLE));
4055 }
4056 
4057 /**
4058  * @brief Enable turn I2C3 off during WFI/WFE
4059  *
4060  * Register | BitsName
4061  * ---------|--------
4062  * CLK_SLP_OFF | I2C3_SLP
4063  *
4064  * @retval None
4065  */
4066 __STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
4067 {
4068  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_ENABLE;
4069 }
4070 
4071 /**
4072  * @brief Disable turn I2C3 off during WFI/WFE
4073  *
4074  * Register | BitsName
4075  * ---------|--------
4076  * CLK_SLP_OFF | I2C3_SLP
4077  *
4078  * @retval None
4079  */
4080 __STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
4081 {
4082  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) = CGC_CLOCK_DISABLE;
4083 }
4084 
4085 /**
4086  * @brief Indicate whether turn I2C3 off during WFI/WFE is enabled.
4087  *
4088  * Register | BitsName
4089  * ---------|--------
4090  * CLK_SLP_OFF | I2C3_SLP
4091  *
4092  * @retval State of bit (1 or 0).
4093  */
4094 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
4095 {
4096  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C3_Pos) == (CGC_CLOCK_ENABLE));
4097 }
4098 
4099 /**
4100  * @brief Enable turn I2C4 off during WFI/WFE
4101  *
4102  * Register | BitsName
4103  * ---------|--------
4104  * CLK_SLP_OFF | I2C4_SLP
4105  *
4106  * @retval None
4107  */
4108 __STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
4109 {
4110  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) = CGC_CLOCK_ENABLE;
4111 }
4112 
4113 /**
4114  * @brief Disable turn I2C4 off during WFI/WFE
4115  *
4116  * Register | BitsName
4117  * ---------|--------
4118  * CLK_SLP_OFF | I2C4_SLP
4119  *
4120  * @retval None
4121  */
4122 __STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
4123 {
4124  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) = CGC_CLOCK_DISABLE;
4125 }
4126 
4127 /**
4128  * @brief Indicate whether turn I2C4 off during WFI/WFE is enabled.
4129  *
4130  * Register | BitsName
4131  * ---------|--------
4132  * CLK_SLP_OFF | I2C4_SLP
4133  *
4134  * @retval State of bit (1 or 0).
4135  */
4136 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
4137 {
4138  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C4_Pos) == (CGC_CLOCK_ENABLE));
4139 }
4140 
4141 /**
4142  * @brief Enable turn I2C5 off during WFI/WFE
4143  *
4144  * Register | BitsName
4145  * ---------|--------
4146  * CLK_SLP_OFF | I2C5_SLP
4147  *
4148  * @retval None
4149  */
4150 __STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
4151 {
4152  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) = CGC_CLOCK_ENABLE;
4153 }
4154 
4155 /**
4156  * @brief Disable turn I2C5 off during WFI/WFE
4157  *
4158  * Register | BitsName
4159  * ---------|--------
4160  * CLK_SLP_OFF | I2C5_SLP
4161  *
4162  * @retval None
4163  */
4164 __STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
4165 {
4166  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) = CGC_CLOCK_DISABLE;
4167 }
4168 
4169 /**
4170  * @brief Indicate whether turn I2C5 off during WFI/WFE is enabled.
4171  *
4172  * Register | BitsName
4173  * ---------|--------
4174  * CLK_SLP_OFF | I2C5_SLP
4175  *
4176  * @retval State of bit (1 or 0).
4177  */
4178 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
4179 {
4180  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2C5_Pos) == (CGC_CLOCK_ENABLE));
4181 }
4182 
4183 /**
4184  * @brief Enable turn I2S_M off during WFI/WFE
4185  *
4186  * Register | BitsName
4187  * ---------|--------
4188  * CLK_SLP_OFF | I2SM_SLP
4189  *
4190  * @retval None
4191  */
4192 __STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
4193 {
4194  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_ENABLE;
4195 }
4196 
4197 /**
4198  * @brief Disable turn I2S_M off during WFI/WFE
4199  *
4200  * Register | BitsName
4201  * ---------|--------
4202  * CLK_SLP_OFF | I2SM_SLP
4203  *
4204  * @retval None
4205  */
4206 __STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
4207 {
4208  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) = CGC_CLOCK_DISABLE;
4209 }
4210 
4211 /**
4212  * @brief Indicate whether turn I2S_M off during WFI/WFE is enabled.
4213  *
4214  * Register | BitsName
4215  * ---------|--------
4216  * CLK_SLP_OFF | I2SM_SLP
4217  *
4218  * @retval State of bit (1 or 0).
4219  */
4220 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
4221 {
4222  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SM_Pos) == (CGC_CLOCK_ENABLE));
4223 }
4224 
4225 /**
4226  * @brief Enable turn I2S_S off during WFI/WFE
4227  *
4228  * Register | BitsName
4229  * ---------|--------
4230  * CLK_SLP_OFF | I2SS_SLP
4231  *
4232  * @retval None
4233  */
4234 __STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
4235 {
4236  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_ENABLE;
4237 }
4238 
4239 /**
4240  * @brief Disable turn I2S_S off during WFI/WFE
4241  *
4242  * Register | BitsName
4243  * ---------|--------
4244  * CLK_SLP_OFF | I2SS_SLP
4245  *
4246  * @retval None
4247  */
4248 __STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
4249 {
4250  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) = CGC_CLOCK_DISABLE;
4251 }
4252 
4253 /**
4254  * @brief Indicate whether turn I2S_S off during WFI/WFE is enabled.
4255  *
4256  * Register | BitsName
4257  * ---------|--------
4258  * CLK_SLP_OFF | I2SS_SLP
4259  *
4260  * @retval State of bit (1 or 0).
4261  */
4262 __STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
4263 {
4264  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_I2SS_Pos) == (CGC_CLOCK_ENABLE));
4265 }
4266 
4267 /**
4268  * @brief Enable turn SPI_M off during WFI/WFE
4269  *
4270  * Register | BitsName
4271  * ---------|--------
4272  * CLK_SLP_OFF | SPIM_SLP
4273  *
4274  * @retval None
4275  */
4276 __STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
4277 {
4278  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_ENABLE;
4279 }
4280 
4281 /**
4282  * @brief Disable turn SPI_M off during WFI/WFE
4283  *
4284  * Register | BitsName
4285  * ---------|--------
4286  * CLK_SLP_OFF | SPIM_SLP
4287  *
4288  * @retval None
4289  */
4290 __STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
4291 {
4292  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) = CGC_CLOCK_DISABLE;
4293 }
4294 
4295 /**
4296  * @brief Indicate whether turn SPI_M off during WFI/WFE is enabled.
4297  *
4298  * Register | BitsName
4299  * ---------|--------
4300  * CLK_SLP_OFF | SPIM_SLP
4301  *
4302  * @retval State of bit (1 or 0).
4303  */
4304 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
4305 {
4306  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM_Pos) == (CGC_CLOCK_ENABLE));
4307 }
4308 
4309 /**
4310  * @brief Enable turn SPI_S off during WFI/WFE
4311  *
4312  * Register | BitsName
4313  * ---------|--------
4314  * CLK_SLP_OFF | SPIS_SLP
4315  *
4316  * @retval None
4317  */
4318 __STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
4319 {
4320  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_ENABLE;
4321 }
4322 
4323 /**
4324  * @brief Disable turn SPI_S off during WFI/WFE
4325  *
4326  * Register | BitsName
4327  * ---------|--------
4328  * CLK_SLP_OFF | SPIS_SLP
4329  *
4330  * @retval None
4331  */
4332 __STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
4333 {
4334  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) = CGC_CLOCK_DISABLE;
4335 }
4336 
4337 /**
4338  * @brief Indicate whether turn SPI_S off during WFI/WFE is enabled.
4339  *
4340  * Register | BitsName
4341  * ---------|--------
4342  * CLK_SLP_OFF | SPIS_SLP
4343  *
4344  * @retval State of bit (1 or 0).
4345  */
4346 __STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
4347 {
4348  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS_Pos) == (CGC_CLOCK_ENABLE));
4349 }
4350 
4351 /**
4352  * @brief Enable turn pwm0 off during WFI/WFE
4353  *
4354  * Register | BitsName
4355  * ---------|--------
4356  * CLK_SLP_OFF | PWM0_SLP
4357  *
4358  * @retval None
4359  */
4360 __STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
4361 {
4362  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_ENABLE;
4363 }
4364 
4365 /**
4366  * @brief Disable turn pwm0 off during WFI/WFE
4367  *
4368  * Register | BitsName
4369  * ---------|--------
4370  * CLK_SLP_OFF | PWM0_SLP
4371  *
4372  * @retval None
4373  */
4374 __STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
4375 {
4376  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) = CGC_CLOCK_DISABLE;
4377 }
4378 
4379 /**
4380  * @brief Indicate whether turn pwm0 off during WFI/WFE is enabled.
4381  *
4382  * Register | BitsName
4383  * ---------|--------
4384  * CLK_SLP_OFF | PWM0_SLP
4385  *
4386  * @retval State of bit (1 or 0).
4387  */
4388 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
4389 {
4390  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0_Pos) == (CGC_CLOCK_ENABLE));
4391 }
4392 
4393 /**
4394  * @brief Enable turn pwm1 off during WFI/WFE
4395  *
4396  * Register | BitsName
4397  * ---------|--------
4398  * CLK_SLP_OFF | PWM1_SLP
4399  *
4400  * @retval None
4401  */
4402 __STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
4403 {
4404  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_ENABLE;
4405 }
4406 
4407 /**
4408  * @brief Disable turn pwm1 off during WFI/WFE
4409  *
4410  * Register | BitsName
4411  * ---------|--------
4412  * CLK_SLP_OFF | PWM1_SLP
4413  *
4414  * @retval None
4415  */
4416 __STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
4417 {
4418  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) = CGC_CLOCK_DISABLE;
4419 }
4420 
4421 /**
4422  * @brief Indicate whether turn pwm1 off during WFI/WFE is enabled.
4423  *
4424  * Register | BitsName
4425  * ---------|--------
4426  * CLK_SLP_OFF | PWM1_SLP
4427  *
4428  * @retval State of bit (1 or 0).
4429  */
4430 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
4431 {
4432  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1_Pos) == (CGC_CLOCK_ENABLE));
4433 }
4434 
4435 /**
4436  * @brief Enable turn QSPIM0 off during WFI/WFE
4437  *
4438  * Register | BitsName
4439  * ---------|--------
4440  * CLK_SLP_OFF | QSPIM0_SLP
4441  *
4442  * @retval None
4443  */
4444 __STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
4445 {
4446  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_ENABLE;
4447 }
4448 
4449 /**
4450  * @brief Disable turn QSPIM0 off during WFI/WFE
4451  *
4452  * Register | BitsName
4453  * ---------|--------
4454  * CLK_SLP_OFF | QSPIM0_SLP
4455  *
4456  * @retval None
4457  */
4458 __STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
4459 {
4460  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) = CGC_CLOCK_DISABLE;
4461 }
4462 
4463 /**
4464  * @brief Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
4465  *
4466  * Register | BitsName
4467  * ---------|--------
4468  * CLK_SLP_OFF | QSPIM0_SLP
4469  *
4470  * @retval State of bit (1 or 0).
4471  */
4472 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
4473 {
4474  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM0_Pos) == (CGC_CLOCK_ENABLE));
4475 }
4476 
4477 /**
4478  * @brief Enable turn QSPIM1 off during WFI/WFE
4479  *
4480  * Register | BitsName
4481  * ---------|--------
4482  * CLK_SLP_OFF | QSPIM1_SLP
4483  *
4484  * @retval None
4485  */
4486 __STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
4487 {
4488  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_ENABLE;
4489 }
4490 
4491 /**
4492  * @brief Disable turn QSPIM1 off during WFI/WFE
4493  *
4494  * Register | BitsName
4495  * ---------|--------
4496  * CLK_SLP_OFF | QSPIM1_SLP
4497  *
4498  * @retval None
4499  */
4500 __STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
4501 {
4502  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) = CGC_CLOCK_DISABLE;
4503 }
4504 
4505 /**
4506  * @brief Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
4507  *
4508  * Register | BitsName
4509  * ---------|--------
4510  * CLK_SLP_OFF | QSPIM1_SLP
4511  *
4512  * @retval State of bit (1 or 0).
4513  */
4514 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
4515 {
4516  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM1_Pos) == (CGC_CLOCK_ENABLE));
4517 }
4518 
4519 /**
4520  * @brief Enable turn QSPIM2 off during WFI/WFE
4521  *
4522  * Register | BitsName
4523  * ---------|--------
4524  * CLK_SLP_OFF | QSPIM2_SLP
4525  *
4526  * @retval None
4527  */
4528 __STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
4529 {
4530  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_ENABLE;
4531 }
4532 
4533 /**
4534  * @brief Disable turn QSPIM2 off during WFI/WFE
4535  *
4536  * Register | BitsName
4537  * ---------|--------
4538  * CLK_SLP_OFF | QSPIM2_SLP
4539  *
4540  * @retval None
4541  */
4542 __STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
4543 {
4544  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) = CGC_CLOCK_DISABLE;
4545 }
4546 
4547 /**
4548  * @brief Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
4549  *
4550  * Register | BitsName
4551  * ---------|--------
4552  * CLK_SLP_OFF | QSPIM2_SLP
4553  *
4554  * @retval State of bit (1 or 0).
4555  */
4556 __STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
4557 {
4558  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_QSPIM2_Pos) == (CGC_CLOCK_ENABLE));
4559 }
4560 
4561 /**
4562  * @brief Enable turn DSPI off during WFI/WFE
4563  *
4564  * Register | BitsName
4565  * ---------|--------
4566  * CLK_SLP_OFF | DSPI_SLP
4567  *
4568  * @retval None
4569  */
4570 __STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
4571 {
4572  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_ENABLE;
4573 }
4574 
4575 /**
4576  * @brief Disable turn DSPI off during WFI/WFE
4577  *
4578  * Register | BitsName
4579  * ---------|--------
4580  * CLK_SLP_OFF | DSPI_SLP
4581  *
4582  * @retval None
4583  */
4584 __STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
4585 {
4586  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) = CGC_CLOCK_DISABLE;
4587 }
4588 
4589 /**
4590  * @brief Indicate whether turn DSPI off during WFI/WFE is enabled.
4591  *
4592  * Register | BitsName
4593  * ---------|--------
4594  * CLK_SLP_OFF | DSPI_SLP
4595  *
4596  * @retval State of bit (1 or 0).
4597  */
4598 __STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
4599 {
4600  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_DSPI_Pos) == (CGC_CLOCK_ENABLE));
4601 }
4602 
4603 /**
4604  * @brief Enable turn PDM off during WFI/WFE
4605  *
4606  * Register | BitsName
4607  * ---------|--------
4608  * CLK_SLP_OFF | PDM_SLP
4609  *
4610  * @retval None
4611  */
4612 __STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
4613 {
4614  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_ENABLE;
4615 }
4616 
4617 /**
4618  * @brief Disable turn PDM off during WFI/WFE
4619  *
4620  * Register | BitsName
4621  * ---------|--------
4622  * CLK_SLP_OFF | PDM_SLP
4623  *
4624  * @retval None
4625  */
4626 __STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
4627 {
4628  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) = CGC_CLOCK_DISABLE;
4629 }
4630 
4631 /**
4632  * @brief Indicate whether turn PDM off during WFI/WFE is enabled.
4633  *
4634  * Register | BitsName
4635  * ---------|--------
4636  * CLK_SLP_OFF | PDM_SLP
4637  *
4638  * @retval State of bit (1 or 0).
4639  */
4640 __STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
4641 {
4642  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_PERIPH_CLK_SLP_OFF, MCU_SUB_PERIPH_CLK_SLP_OFF_PDM_Pos) == (CGC_CLOCK_ENABLE));
4643 }
4644 
4645 /**
4646  * @brief Individual block's clock control inside security system which was forced to turn off (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4647  *
4648  * Register | BitsName
4649  * ----------|--------
4650  * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4651  * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4652  * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4653  * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4654  * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4655  * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4656  * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4657  *
4658  * @param clk_mask This parameter can be a combination of the following values:
4659  * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4660  * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4661  * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4662  * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4663  * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4664  * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4665  * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4666  * @retval None
4667  */
4668 __STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
4669 {
4670  MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK, clk_mask);
4671 }
4672 
4673 /**
4674  * @brief Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4675  *
4676  * Register | BitsName
4677  * ----------|--------
4678  * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4679  * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4680  * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4681  * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4682  * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4683  * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4684  * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
4685  *
4686  * @retval Returned value can be a combination of the following values:
4687  * @arg @ref LL_CGC_MCU_FRC_AES_HCLK_OFF_EN
4688  * @arg @ref LL_CGC_MCU_FRC_HMAC_HCLK_OFF_EN
4689  * @arg @ref LL_CGC_MCU_FRC_PKC_HCLK_OFF_EN
4690  * @arg @ref LL_CGC_MCU_FRC_PRESENT_HCLK_OFF_EN
4691  * @arg @ref LL_CGC_MCU_FRC_RAMKEY_HCLK_OFF_EN
4692  * @arg @ref LL_CGC_MCU_FRC_RNG_HCLK_OFF_EN
4693  * @arg @ref LL_CGC_MCU_FRC_EFUSE_HCLK_OFF_EN
4694  */
4695 __STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
4696 {
4697  return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_HCLK);
4698 }
4699 
4700 /**
4701  * @brief Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4702  *
4703  * Register | BitsName
4704  * ----------|--------
4705  * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4706  * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4707  * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4708  * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4709  *
4710  * @param clk_mask This parameter can be a combination of the following values:
4711  * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4712  * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4713  * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4714  * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4715  * @retval None
4716  */
4717 __STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
4718 {
4719  MODIFY_REG(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK, clk_mask);
4720 }
4721 
4722 /**
4723  * @brief Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMKAY/RNG/EFUSE)
4724  *
4725  * Register | BitsName
4726  * ----------|--------
4727  * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
4728  * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
4729  * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
4730  * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
4731  *
4732  * @retval Returned value can be a combination of the following values:
4733  * @arg @ref LL_CGC_MCU_SLP_AES_HCLK_OFF_EN
4734  * @arg @ref LL_CGC_MCU_SLP_HMAC_HCLK_OFF_EN
4735  * @arg @ref LL_CGC_MCU_SLP_PKC_HCLK_OFF_EN
4736  * @arg @ref LL_CGC_MCU_SLP_PRESENT_HCLK_OFF_EN
4737  */
4738 __STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
4739 {
4740  return READ_BITS(MCU_RET->SECU_CLK_CTRL, LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK);
4741 }
4742 
4743 /**
4744  * @brief Enabling force to turn off the clock for AES.
4745  *
4746  * Register | BitsName
4747  * ----------|--------
4748  * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4749  *
4750  * @retval None
4751  */
4752 __STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
4753 {
4754  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4755 }
4756 
4757 /**
4758  * @brief Disabling force to turn off the clock for AES.
4759  *
4760  * Register | BitsName
4761  * ----------|--------
4762  * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4763  *
4764  * @retval None
4765  */
4766 __STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
4767 {
4768  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4769 }
4770 
4771 /**
4772  * @brief Indicate whether the clock for AES is forced to close.
4773  *
4774  * Register | BitsName
4775  * ----------|--------
4776  * SECU_CLK_CTRL | AES_HCLK_FRC_OFF
4777  *
4778  * @retval State of bit (1 or 0).
4779  */
4780 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
4781 {
4782  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4783 }
4784 
4785 /**
4786  * @brief Enabling force to turn off the clock for HMAC.
4787  *
4788  * Register | BitsName
4789  * ----------|--------
4790  * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4791  *
4792  * @retval None
4793  */
4794 __STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
4795 {
4796  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4797 }
4798 
4799 /**
4800  * @brief Disabling force to turn off the clock for HMAC.
4801  *
4802  * Register | BitsName
4803  * ----------|--------
4804  * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4805  *
4806  * @retval None
4807  */
4808 __STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
4809 {
4810  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4811 }
4812 
4813 /**
4814  * @brief Indicate whether the clock for HMAC is forced to close.
4815  *
4816  * Register | BitsName
4817  * ----------|--------
4818  * SECU_CLK_CTRL | HMAC_HCLK_FRC_OFF
4819  *
4820  * @retval State of bit (1 or 0).
4821  */
4822 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
4823 {
4824  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4825 }
4826 
4827 /**
4828  * @brief Enabling force to turn off the clock for PKC.
4829  *
4830  * Register | BitsName
4831  * ----------|--------
4832  * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4833  *
4834  * @retval None
4835  */
4836 __STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
4837 {
4838  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4839 }
4840 
4841 /**
4842  * @brief Disabling force to turn off the clock for PKC.
4843  *
4844  * Register | BitsName
4845  * ----------|--------
4846  * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4847  *
4848  * @retval None
4849  */
4850 __STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
4851 {
4852  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4853 }
4854 
4855 /**
4856  * @brief Indicate whether the clock for PKC is forced to close.
4857  *
4858  * Register | BitsName
4859  * ----------|--------
4860  * SECU_CLK_CTRL | PKC_HCLK_FRC_OFF
4861  *
4862  * @retval State of bit (1 or 0).
4863  */
4864 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
4865 {
4866  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4867 }
4868 
4869 /**
4870  * @brief Enabling force to turn off the clock for PRESENT.
4871  *
4872  * Register | BitsName
4873  * ----------|--------
4874  * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4875  *
4876  * @retval None
4877  */
4878 __STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
4879 {
4880  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4881 }
4882 
4883 /**
4884  * @brief Disabling force to turn off the clock for PRESENT.
4885  *
4886  * Register | BitsName
4887  * ----------|--------
4888  * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4889  *
4890  * @retval None
4891  */
4892 __STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
4893 {
4894  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4895 }
4896 
4897 /**
4898  * @brief Indicate whether the clock for PRESENT is forced to close.
4899  *
4900  * Register | BitsName
4901  * ----------|--------
4902  * SECU_CLK_CTRL | PRESENT_HCLK_FRC_OFF
4903  *
4904  * @retval State of bit (1 or 0).
4905  */
4906 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
4907 {
4908  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4909 }
4910 
4911 /**
4912  * @brief Enabling force to turn off the clock for RAMKEY.
4913  *
4914  * Register | BitsName
4915  * ----------|--------
4916  * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4917  *
4918  * @retval None
4919  */
4920 __STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
4921 {
4922  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4923 }
4924 
4925 /**
4926  * @brief Disabling force to turn off the clock for RAMKEY.
4927  *
4928  * Register | BitsName
4929  * ----------|--------
4930  * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4931  *
4932  * @retval None
4933  */
4934 __STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
4935 {
4936  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4937 }
4938 
4939 /**
4940  * @brief Indicate whether the clock for RAMKEY is forced to close.
4941  *
4942  * Register | BitsName
4943  * ----------|--------
4944  * SECU_CLK_CTRL | RAMKEY_HCLK_FRC_OFF
4945  *
4946  * @retval State of bit (1 or 0).
4947  */
4948 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
4949 {
4950  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4951 }
4952 
4953 
4954 /**
4955  * @brief Enabling force to turn off the clock for RNG.
4956  *
4957  * Register | BitsName
4958  * ----------|--------
4959  * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4960  *
4961  * @retval None
4962  */
4963 __STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
4964 {
4965  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
4966 }
4967 
4968 /**
4969  * @brief Disabling force to turn off the clock for RNG.
4970  *
4971  * Register | BitsName
4972  * ----------|--------
4973  * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4974  *
4975  * @retval None
4976  */
4977 __STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
4978 {
4979  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
4980 }
4981 
4982 /**
4983  * @brief Indicate whether the clock for RNG is forced to close.
4984  *
4985  * Register | BitsName
4986  * ----------|--------
4987  * SECU_CLK_CTRL | RNG_HCLK_FRC_OFF
4988  *
4989  * @retval State of bit (1 or 0).
4990  */
4991 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
4992 {
4993  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
4994 }
4995 
4996 /**
4997  * @brief Enabling force to turn off the clock for EFUSE.
4998  *
4999  * Register | BitsName
5000  * ----------|--------
5001  * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5002  *
5003  * @retval None
5004  */
5005 __STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
5006 {
5007  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_ENABLE;
5008 }
5009 
5010 /**
5011  * @brief Disabling force to turn off the clock for EFUSE.
5012  *
5013  * Register | BitsName
5014  * ----------|--------
5015  * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5016  *
5017  * @retval None
5018  */
5019 __STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
5020 {
5021  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) = CGC_CLOCK_DISABLE;
5022 }
5023 
5024 /**
5025  * @brief Indicate whether the clock for EFUSE is forced to close.
5026  *
5027  * Register | BitsName
5028  * ----------|--------
5029  * SECU_CLK_CTRL | EFUSE_HCLK_FRC_OFF
5030  *
5031  * @retval State of bit (1 or 0).
5032  */
5033 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
5034 {
5035  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_FORCE_OFF_Pos) == (CGC_CLOCK_ENABLE));
5036 }
5037 
5038 /**
5039  * @brief Enable AES automatic turn off clock during WFI/WFE
5040  *
5041  * Register | BitsName
5042  * ----------|--------
5043  * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5044  *
5045  * @retval None
5046  */
5047 __STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
5048 {
5049  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5050 }
5051 
5052 /**
5053  * @brief Disable AES automatic turn off clock during WFI/WFE
5054  *
5055  * Register | BitsName
5056  * ----------|--------
5057  * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5058  *
5059  * @retval None
5060  */
5061 __STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
5062 {
5063  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5064 }
5065 
5066 /**
5067  * @brief Indicate whether the AES automatic turn off clock is enabled.
5068  *
5069  * Register | BitsName
5070  * ----------|--------
5071  * SECU_CLK_CTRL | AES_HCLK_SLP_OFF
5072  *
5073  * @retval State of bit (1 or 0).
5074  */
5075 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
5076 {
5077  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_AES_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5078 }
5079 
5080 /**
5081  * @brief Enable HMAC automatic turn off clock during WFI/WFE
5082  *
5083  * Register | BitsName
5084  * ----------|--------
5085  * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5086  *
5087  * @retval None
5088  */
5089 __STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
5090 {
5091  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5092 }
5093 
5094 /**
5095  * @brief Disable HMAC automatic turn off clock during WFI/WFE
5096  *
5097  * Register | BitsName
5098  * ----------|--------
5099  * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5100  *
5101  * @retval None
5102  */
5103 __STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
5104 {
5105  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5106 }
5107 
5108 /**
5109  * @brief Indicate whether the HMAC automatic turn off clock is enabled.
5110  *
5111  * Register | BitsName
5112  * ----------|--------
5113  * SECU_CLK_CTRL | HMAC_HCLK_SLP_OFF
5114  *
5115  * @retval State of bit (1 or 0).
5116  */
5117 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
5118 {
5119  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_HMAC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5120 }
5121 
5122 /**
5123  * @brief Enable PKC automatic turn off clock during WFI/WFE
5124  *
5125  * Register | BitsName
5126  * ----------|--------
5127  * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5128  *
5129  * @retval None
5130  */
5131 __STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
5132 {
5133  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5134 }
5135 
5136 /**
5137  * @brief Disable PKC automatic turn off clock during WFI/WFE
5138  *
5139  * Register | BitsName
5140  * ----------|--------
5141  * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5142  *
5143  * @retval None
5144  */
5145 __STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
5146 {
5147  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5148 }
5149 
5150 /**
5151  * @brief Indicate whether the PKC automatic turn off clock is enabled.
5152  *
5153  * Register | BitsName
5154  * ----------|--------
5155  * SECU_CLK_CTRL | PKC_HCLK_SLP_OFF
5156  *
5157  * @retval State of bit (1 or 0).
5158  */
5159 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
5160 {
5161  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PKC_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5162 }
5163 
5164 /**
5165  * @brief Enable PRESENT automatic turn off clock during WFI/WFE
5166  *
5167  * Register | BitsName
5168  * ----------|--------
5169  * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5170  *
5171  * @retval None
5172  */
5173 __STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
5174 {
5175  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5176 }
5177 
5178 /**
5179  * @brief Disable PRESENT automatic turn off clock during WFI/WFE
5180  *
5181  * Register | BitsName
5182  * ----------|--------
5183  * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5184  *
5185  * @retval None
5186  */
5187 __STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
5188 {
5189  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5190 }
5191 
5192 /**
5193  * @brief Indicate whether the PRESENT automatic turn off clock is enabled.
5194  *
5195  * Register | BitsName
5196  * ----------|--------
5197  * SECU_CLK_CTRL | PRESENT_HCLK_SLP_OFF
5198  *
5199  * @retval State of bit (1 or 0).
5200  */
5201 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
5202 {
5203  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_PRESENT_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5204 }
5205 
5206 /**
5207  * @brief Enable RAMKEY automatic turn off clock during WFI/WFE
5208  *
5209  * Register | BitsName
5210  * ----------|--------
5211  * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5212  *
5213  * @retval None
5214  */
5215 __STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
5216 {
5217  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5218 }
5219 
5220 /**
5221  * @brief Disable RAMKEY automatic turn off clock during WFI/WFE
5222  *
5223  * Register | BitsName
5224  * ----------|--------
5225  * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5226  *
5227  * @retval None
5228  */
5229 __STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
5230 {
5231  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5232 }
5233 
5234 /**
5235  * @brief Indicate whether the RAMKEY automatic turn off clock is enabled.
5236  *
5237  * Register | BitsName
5238  * ----------|--------
5239  * SECU_CLK_CTRL | RAMKEY_HCLK_SLP_OFF
5240  *
5241  * @retval State of bit (1 or 0).
5242  */
5243 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
5244 {
5245  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RAMKEY_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5246 }
5247 
5248 /**
5249  * @brief Enable RNG automatic turn off clock during WFI/WFE
5250  *
5251  * Register | BitsName
5252  * ----------|--------
5253  * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5254  *
5255  * @retval None
5256  */
5257 __STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
5258 {
5259  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5260 }
5261 
5262 /**
5263  * @brief Disable RNG automatic turn off clock during WFI/WFE
5264  *
5265  * Register | BitsName
5266  * ----------|--------
5267  * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5268  *
5269  * @retval None
5270  */
5271 __STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
5272 {
5273  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5274 }
5275 
5276 /**
5277  * @brief Indicate whether the RNG automatic turn off clock is enabled.
5278  *
5279  * Register | BitsName
5280  * ----------|--------
5281  * SECU_CLK_CTRL | RNG_HCLK_SLP_OFF
5282  *
5283  * @retval State of bit (1 or 0).
5284  */
5285 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
5286 {
5287  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_RNG_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5288 }
5289 
5290 /**
5291  * @brief Enable EFUSE automatic turn off clock during WFI/WFE
5292  *
5293  * Register | BitsName
5294  * ----------|--------
5295  * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5296  *
5297  * @retval None
5298  */
5299 __STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
5300 {
5301  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_ENABLE;
5302 }
5303 
5304 /**
5305  * @brief Disable EFUSE automatic turn off clock during WFI/WFE
5306  *
5307  * Register | BitsName
5308  * ----------|--------
5309  * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5310  *
5311  * @retval None
5312  */
5313 __STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
5314 {
5315  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) = CGC_CLOCK_DISABLE;
5316 }
5317 
5318 /**
5319  * @brief Indicate whether the EFUSE automatic turn off clock is enabled.
5320  *
5321  * Register | BitsName
5322  * ----------|--------
5323  * SECU_CLK_CTRL | EFUSE_HCLK_SLP_OFF
5324  *
5325  * @retval State of bit (1 or 0).
5326  */
5327 __STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
5328 {
5329  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->SECU_CLK_CTRL, MCU_SUB_SECU_CLK_CTRL_EFUSE_HCLK_SLP_OFF_Pos) == (CGC_CLOCK_ENABLE));
5330 }
5331 
5332 /**
5333  * @brief Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
5334  *
5335  * Register | BitsName
5336  * ----------|--------
5337  * MCU_MISC_CLK | GPADC/XQSPI/DMA0/DMA1/DMA2
5338  *
5339  * @retval None
5340  */
5341 __STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
5342 {
5343  MODIFY_REG(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK, clk_mask);
5344 }
5345 
5346 /**
5347  * @brief Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
5348  *
5349  * Register | BitsName
5350  * ----------|--------
5351  * MCU_MISC_CLK | GPADC/XQSPI/DMA0/DMA1/DMA2
5352  */
5353 __STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
5354 {
5355  return READ_BITS(MCU_RET->MCU_MISC_CLK, LL_CGC_MCU_MISC_CLK);
5356 }
5357 
5358 /**
5359  * @brief Enable XQSPI SCK CLK turn off
5360  *
5361  * Register | BitsName
5362  * ----------|--------
5363  * MCU_MISC_CLK |XQSPI SCK CLK_OFF
5364  *
5365  * @retval None
5366  */
5367 __STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
5368 {
5369  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_ENABLE;
5370 }
5371 
5372 /**
5373  * @brief Disable XQSPI SCK CLK turn off
5374  *
5375  * Register | BitsName
5376  * ----------|--------
5377  * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5378  *
5379  * @retval None
5380  */
5381 __STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
5382 {
5383  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) = CGC_CLOCK_DISABLE;
5384 }
5385 
5386 /**
5387  * @brief Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
5388  *
5389  * Register | BitsName
5390  * ----------|--------
5391  * MCU_MISC_CLK | XQSPI SCK CLK_OFF
5392  *
5393  * @retval State of bit (1 or 0).
5394  */
5395 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
5396 {
5397  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_XQSPI_SCK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5398 }
5399 
5400 /**
5401  * @brief Enable DMA0 turn off
5402  *
5403  * Register | BitsName
5404  * ----------|--------
5405  * MCU_MISC_CLK |DMA0_OFF
5406  *
5407  * @retval None
5408  */
5409 __STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
5410 {
5411  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5412 }
5413 
5414 /**
5415  * @brief Disable DMA0 turn off
5416  *
5417  * Register | BitsName
5418  * ----------|--------
5419  * MCU_MISC_CLK | DMA0_OFF
5420  *
5421  * @retval None
5422  */
5423 __STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
5424 {
5425  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5426 }
5427 
5428 /**
5429  * @brief Indicate whether the DMA0 automatic turn off clock is enabled.
5430  *
5431  * Register | BitsName
5432  * ----------|--------
5433  * MCU_MISC_CLK | DMA0_OFF
5434  *
5435  * @retval State of bit (1 or 0).
5436  */
5437 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
5438 {
5439  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA0_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5440 }
5441 
5442 /**
5443  * @brief Enable DMA1 turn off
5444  *
5445  * Register | BitsName
5446  * ----------|--------
5447  * MCU_MISC_CLK |DMA1_OFF
5448  *
5449  * @retval None
5450  */
5451 __STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
5452 {
5453  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5454 }
5455 
5456 /**
5457  * @brief Disable DMA1 turn off
5458  *
5459  * Register | BitsName
5460  * ----------|--------
5461  * MCU_MISC_CLK | DMA1_OFF
5462  *
5463  * @retval None
5464  */
5465 __STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
5466 {
5467  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5468 }
5469 
5470 /**
5471  * @brief Indicate whether the DMA1 automatic turn off clock is enabled.
5472  *
5473  * Register | BitsName
5474  * ----------|--------
5475  * MCU_MISC_CLK | DMA1_OFF
5476  *
5477  * @retval State of bit (1 or 0).
5478  */
5479 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
5480 {
5481  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA1_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5482 }
5483 
5484 /**
5485  * @brief Enable DMA2 turn off
5486  *
5487  * Register | BitsName
5488  * ----------|--------
5489  * MCU_MISC_CLK |DMA2_OFF
5490  *
5491  * @retval None
5492  */
5493 __STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
5494 {
5495  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_ENABLE;
5496 }
5497 
5498 /**
5499  * @brief Disable DMA2 turn off
5500  *
5501  * Register | BitsName
5502  * ----------|--------
5503  * MCU_MISC_CLK | DMA2_OFF
5504  *
5505  * @retval None
5506  */
5507 __STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
5508 {
5509  BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) = CGC_CLOCK_DISABLE;
5510 }
5511 
5512 /**
5513  * @brief Indicate whether the DMA2 automatic turn off clock is enabled.
5514  *
5515  * Register | BitsName
5516  * ----------|--------
5517  * MCU_MISC_CLK | DMA2_OFF
5518  *
5519  * @retval State of bit (1 or 0).
5520  */
5521 __STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
5522 {
5523  return (BIT_SEGMENT_VALUE((uint32_t)&MCU_RET->MCU_MISC_CLK, MCU_SUB_CLK_CTRL_DMA2_HCLK_OFF_Pos) == (CGC_CLOCK_ENABLE));
5524 }
5525 
5526 /** @} */
5527 
5528 #endif /* CGC */
5529 
5530 #ifdef __cplusplus
5531 }
5532 #endif
5533 
5534 #endif /* __GR55XX_LL_CGC_H__ */
5535 
5536 /** @} */
5537 
5538 /** @} */
5539 
5540 /** @} */
ll_cgc_enable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_m_slp_wfi(void)
Enable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4192
ll_cgc_set_force_off_hclk_1
__STATIC_INLINE void ll_cgc_set_force_off_hclk_1(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:650
ll_cgc_is_enabled_force_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_htb_hclk(void)
Indicate whether the clock for Hopping Table is forced to close.
Definition: gr55xx_ll_cgc.h:1687
ll_cgc_enable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aes_hclk(void)
Enabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4752
ll_cgc_is_enabled_force_off_uart4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart4_hclk(void)
Indicate whether the clock for UART4 is forced to close.
Definition: gr55xx_ll_cgc.h:2317
ll_cgc_is_enabled_force_off_i2c4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c4_hclk(void)
Indicate whether the clock for I2C4 is forced to close.
Definition: gr55xx_ll_cgc.h:2569
ll_cgc_is_enabled_force_off_uart5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart5_hclk(void)
Indicate whether the clock for UART5 is forced to close.
Definition: gr55xx_ll_cgc.h:2359
ll_cgc_enable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_efuse_hclk(void)
Enabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:5005
ll_cgc_disable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dspi_hclk(void)
Disabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2934
ll_cgc_is_enabled_force_off_i2c5_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c5_hclk(void)
Indicate whether the clock for I2C5 is forced to close.
Definition: gr55xx_ll_cgc.h:2611
ll_cgc_enable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rng_hclk(void)
Enabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:4963
ll_cgc_is_enabled_force_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ramkey_hclk(void)
Indicate whether the clock for RAMKEY is forced to close.
Definition: gr55xx_ll_cgc.h:4948
ll_cgc_is_enabled_wfi_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pkc_hclk(void)
Indicate whether the PKC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5159
ll_cgc_disable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_gpio_hclk(void)
Disabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1799
ll_cgc_disable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pkc_hclk(void)
Disabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4850
ll_cgc_disable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart0_slp_wfi(void)
Disable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3702
ll_cgc_enable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c3_hclk(void)
Enabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2499
ll_cgc_disable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pwm_hclk(void)
Disable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:997
ll_cgc_is_enabled_i2c_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c_sclk_low_power(void)
Indicate whether the i2c sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3506
ll_cgc_is_enabled_force_off_i2c1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c1_hclk(void)
Indicate whether the clock for I2C1 is forced to close.
Definition: gr55xx_ll_cgc.h:2443
ll_cgc_is_enabled_force_off_i2c0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c0_hclk(void)
Indicate whether the clock for I2C0 is forced to close.
Definition: gr55xx_ll_cgc.h:2401
ll_cgc_is_enabled_spi_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_m_slp_wfi(void)
Indicate whether turn SPI_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4304
ll_cgc_disable_force_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_efuse_hclk(void)
Disabling force to turn off the clock for EFUSE.
Definition: gr55xx_ll_cgc.h:5019
ll_cgc_disable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c2_slp_wfi(void)
Disable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4038
ll_cgc_is_enabled_uart1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart1_slp_wfi(void)
Indicate whether turn UART1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3758
ll_cgc_enable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma1_hclk(void)
Enable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:5451
BIT_SEGMENT_VALUE
#define BIT_SEGMENT_VALUE
Definition: gr55xx_ll_cgc.h:328
ll_cgc_enable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_serial_hclk(void)
Enable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1278
ll_cgc_disable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ble_brg_hclk(void)
Disable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1208
ll_cgc_disable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_pkc_hclk(void)
Disable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5145
ll_cgc_enable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_snsadc_hclk(void)
Enable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1067
LL_CGC_WFI_ALL_HCLK2
#define LL_CGC_WFI_ALL_HCLK2
Definition: gr55xx_ll_cgc.h:104
ll_cgc_enable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart3_slp_wfi(void)
Enable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3814
ll_cgc_set_force_off_hclk_2
__STATIC_INLINE void ll_cgc_set_force_off_hclk_2(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK/UART4_HC...
Definition: gr55xx_ll_cgc.h:738
ll_cgc_disable_force_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aes_hclk(void)
Disabling force to turn off the clock for AES.
Definition: gr55xx_ll_cgc.h:4766
ll_cgc_enable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_snsadc_hclk(void)
Enabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1743
ll_cgc_enable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_div4_hclk(void)
Enable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1490
ll_cgc_enable_wfi_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pkc_hclk(void)
Enable PKC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5131
ll_cgc_disable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c3_slp_wfi(void)
Disable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4080
ll_cgc_enable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_xf_xqspi_div4_pclk(void)
Enabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:3045
ll_cgc_is_enabled_wfi_off_pwm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_pwm_hclk(void)
Indicate whether the PWM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1011
ll_cgc_enable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3520
ll_cgc_is_enabled_force_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_efuse_hclk(void)
Indicate whether the clock for EFUSE is forced to close.
Definition: gr55xx_ll_cgc.h:5033
ll_cgc_is_enabled_i2c2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c2_slp_wfi(void)
Indicate whether turn I2C2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4052
ll_cgc_is_enabled_force_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_hmac_hclk(void)
Indicate whether the clock for HMAC is forced to close.
Definition: gr55xx_ll_cgc.h:4822
ll_cgc_is_enabled_wfi_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sram_hclk(void)
Indicate whether the SRAM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1476
ll_cgc_disable_force_off_dma1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma1_hclk(void)
Disable DMA1 turn off.
Definition: gr55xx_ll_cgc.h:5465
ll_cgc_is_enabled_force_off_i2c2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c2_hclk(void)
Indicate whether the clock for I2C2 is forced to close.
Definition: gr55xx_ll_cgc.h:2485
ll_cgc_enable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c0_slp_wfi(void)
Enable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3940
ll_cgc_enable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_i2c_sclk_low_power(void)
Enable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3478
ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xf_xqspi_div4_pclk(void)
Indicate whether the div4 clock for xf qspi blocks is forced to close.
Definition: gr55xx_ll_cgc.h:3073
ll_cgc_enable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sim_hclk(void)
Enable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:899
ll_cgc_disable_wfi_off_usb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_usb_hclk(void)
Disable USB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1335
ll_cgc_enable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sim_hclk(void)
Enabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1617
ll_cgc_enable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm0_slp_wfi(void)
Enable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4360
ll_cgc_disable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_hclk(void)
Disable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:871
ll_cgc_disable_force_off_i2c3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c3_hclk(void)
Disabling force to turn off the clock for I2C3.
Definition: gr55xx_ll_cgc.h:2513
ll_cgc_disable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart2_hclk(void)
Disabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:2219
ll_cgc_disable_qspim_low_power
__STATIC_INLINE void ll_cgc_disable_qspim_low_power(void)
Disable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3576
ll_cgc_disable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pdm_slp_wfi(void)
Disable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4626
ll_cgc_enable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_s_slp_wfi(void)
Enable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4318
ll_cgc_is_enabled_wfi_off_usb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_usb_hclk(void)
Indicate whether the USB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1350
ll_cgc_is_enabled_force_off_pwm0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm0_hclk(void)
Indicate whether the clock for PWM0 is forced to close.
Definition: gr55xx_ll_cgc.h:3115
ll_cgc_get_mcu_periph_low_power
__STATIC_INLINE uint32_t ll_cgc_get_mcu_periph_low_power(void)
Return to clock blocks that has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr55xx_ll_cgc.h:3254
ll_cgc_disable_force_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_snsadc_hclk(void)
Disabling force to turn off the clock for SNSADC.
Definition: gr55xx_ll_cgc.h:1757
ll_cgc_enable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart2_slp_wfi(void)
Enable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3772
ll_cgc_is_enabled_force_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aes_hclk(void)
Indicate whether the clock for AES is forced to close.
Definition: gr55xx_ll_cgc.h:4780
ll_cgc_enable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_sram_hclk(void)
Enable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1448
ll_cgc_is_enabled_force_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_ble_brg_hclk(void)
Indicate whether the clock for BLE Bridge is forced to close.
Definition: gr55xx_ll_cgc.h:1855
ll_cgc_is_enabled_wfi_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_snsadc_hclk(void)
Indicate whether the SNSADC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1095
ll_cgc_set_mcu_periph_low_power
__STATIC_INLINE void ll_cgc_set_mcu_periph_low_power(uint32_t clk_mask)
Some peripherals has low power feature. (Include: UART/I2S/SPIM/SPIS/I2C/AHB BUS)
Definition: gr55xx_ll_cgc.h:3227
ll_cgc_is_enabled_force_off_qspi1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi1_hclk(void)
Indicate whether the clock for QSPI1 is forced to close.
Definition: gr55xx_ll_cgc.h:2779
ll_cgc_is_enabled_wfi_off_hmac_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_hmac_hclk(void)
Indicate whether the HMAC automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5117
ll_cgc_is_enabled_force_off_uart3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart3_hclk(void)
Indicate whether the clock for UART3 is forced to close.
Definition: gr55xx_ll_cgc.h:2275
ll_cgc_enable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart5_slp_wfi(void)
Enable turn UART5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3898
ll_cgc_is_enabled_ahb2apb_async_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_async_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3674
ll_cgc_enable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_sync_bus_low_power(void)
Enable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3604
ll_cgc_disable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_async_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3660
ll_cgc_get_wfi_off_hclk_4
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_4(void)
Return to clock blocks that is turned off during WFI.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:565
ll_cgc_disable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi1_hclk(void)
Disabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2765
ll_cgc_is_enabled_uart_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_sclk_low_power(void)
Indicate whether the uart sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3296
ll_cgc_is_enabled_i2s_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_low_power(void)
Indicate whether the i2s low-power is enabled.
Definition: gr55xx_ll_cgc.h:3380
ll_cgc_get_force_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_2(void)
Return to clock blocks that was forcibly closed.(Include: UART0_HCLK/UART1_HCLK/UART2_HCLK/UART3_HCLK...
Definition: gr55xx_ll_cgc.h:807
ll_cgc_is_enabled_wfi_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_hclk(void)
Indicate whether the XQSPI automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1434
ll_cgc_is_enabled_force_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_apb_sub_hclk(void)
Indicate whether the clock for APB Subsystem is forced to close.
Definition: gr55xx_ll_cgc.h:1897
ll_cgc_disable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart5_hclk(void)
Disabling force to turn off the clock for UART5.
Definition: gr55xx_ll_cgc.h:2345
ll_cgc_enable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_sck(void)
Enable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:5367
ll_cgc_is_enabled_force_off_vttbl_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_vttbl_hclk(void)
Indicate whether the clock for VTTBL is forced to close.
Definition: gr55xx_ll_cgc.h:3199
ll_cgc_enable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi2_hclk(void)
Enabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2793
LL_CGC_FRC_ALL_HCLK0
#define LL_CGC_FRC_ALL_HCLK0
Definition: gr55xx_ll_cgc.h:120
ll_cgc_disable_i2s_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_m_slp_wfi(void)
Disable turn I2S_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4206
ll_cgc_disable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aes_hclk(void)
Disable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5061
ll_cgc_is_enabled_qspim1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim1_slp_wfi(void)
Indicate whether turn QSPIM1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4514
ll_cgc_enable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c5_hclk(void)
Enabling force to turn off the clock for I2C5.
Definition: gr55xx_ll_cgc.h:2583
ll_cgc_disable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart0_hclk(void)
Disabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2135
ll_cgc_set_wfi_off_hclk_1
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_1(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:437
ll_cgc_enable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_sclk_low_power(void)
Enable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3268
ll_cgc_enable_i2c3_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c3_slp_wfi(void)
Enable turn I2C3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4066
ll_cgc_enable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c0_hclk(void)
Enabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2373
ll_cgc_set_wfi_off_hclk_3
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: UART/DSPI.I2C/QSPI....
Definition: gr55xx_ll_cgc.h:511
ll_cgc_enable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_enable_uart_pclk_low_power(void)
Enable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:3310
CGC_CLOCK_ENABLE
#define CGC_CLOCK_ENABLE
Definition: gr55xx_ll_cgc.h:323
ll_cgc_get_wfi_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_1(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:456
ll_cgc_enable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pdm_hclk(void)
Enabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2962
ll_cgc_is_enabled_i2c0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c0_slp_wfi(void)
Indicate whether turn I2C0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3968
ll_cgc_disable_i2c_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_i2c_sclk_low_power(void)
Disable i2c sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3492
ll_cgc_enable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_rom_hclk(void)
Enabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1701
ll_cgc_set_force_off_hclk_0
__STATIC_INLINE void ll_cgc_set_force_off_hclk_0(uint32_t clk_mask)
Some peripherals force turn off clock. (Include: Security/SIM/HTB/PWM/ROM/SNSADC/GPIO/ DMA/BLE_BRG/AP...
Definition: gr55xx_ll_cgc.h:598
ll_cgc_is_enabled_qspim_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim_low_power(void)
Indicate whether the QSPIM low-power is enabled.
Definition: gr55xx_ll_cgc.h:3590
ll_cgc_disable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_m_slp_wfi(void)
Disable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4290
ll_cgc_disable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spim_sclk_low_power(void)
Disable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3408
ll_cgc_is_enabled_force_off_dma0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma0_hclk(void)
Indicate whether the DMA0 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5437
ll_cgc_disable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma0_hclk(void)
Disable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:5423
ll_cgc_enable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim0_slp_wfi(void)
Enable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4444
ll_cgc_disable_force_off_qspi2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi2_hclk(void)
Disabling force to turn off the clock for QSPI2.
Definition: gr55xx_ll_cgc.h:2807
ll_cgc_is_enabled_force_off_qspi2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi2_hclk(void)
Indicate whether the clock for QSPI2 is forced to close.
Definition: gr55xx_ll_cgc.h:2821
ll_cgc_disable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c4_slp_wfi(void)
Disable turn I2C4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4122
ll_cgc_is_enabled_uart_pclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart_pclk_low_power(void)
Indicate whether the uart pclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3338
ll_cgc_is_enabled_force_off_xqspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_hclk(void)
Indicate whether the clock for XQSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2065
ll_cgc_is_enabled_force_off_pkc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pkc_hclk(void)
Indicate whether the clock for PKC is forced to close.
Definition: gr55xx_ll_cgc.h:4864
ll_cgc_disable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_serial_hclk(void)
Disabling force to turn off the clock for serial blocks(including I2C, UART, QSPI,...
Definition: gr55xx_ll_cgc.h:1925
ll_cgc_enable_i2c4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c4_slp_wfi(void)
Enable turn I2C4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4108
ll_cgc_is_enabled_wfi_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_gpio_hclk(void)
Indicate whether the GPIO automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1137
ll_cgc_is_enabled_force_off_gpio_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_gpio_hclk(void)
Indicate whether the clock for GPIO is forced to close.
Definition: gr55xx_ll_cgc.h:1813
ll_cgc_disable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c1_slp_wfi(void)
Disable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3996
ll_cgc_is_enabled_wfi_off_dma_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_dma_hclk(void)
Indicate whether the DMA automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1179
ll_cgc_enable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_present_hclk(void)
Enable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5173
ll_cgc_disable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ble_brg_hclk(void)
Disabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1841
ll_cgc_disable_force_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rom_hclk(void)
Disabling force to turn off the clock for ROM.
Definition: gr55xx_ll_cgc.h:1715
ll_cgc_disable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_gpio_hclk(void)
Disable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1123
ll_cgc_disable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart4_slp_wfi(void)
Disable turn UART4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3870
ll_cgc_is_enabled_wfi_off_ble_brg_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ble_brg_hclk(void)
Indicate whether the BLE Bridge automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1222
ll_cgc_enable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c4_hclk(void)
Enabling force to turn off the clock for I2C4.
Definition: gr55xx_ll_cgc.h:2541
ll_cgc_disable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_m_hclk(void)
Disabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2850
ll_cgc_is_enabled_force_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rng_hclk(void)
Indicate whether the clock for RNG is forced to close.
Definition: gr55xx_ll_cgc.h:4991
ll_cgc_disable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_htb_hclk(void)
Disable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:955
ll_cgc_get_wfi_off_hclk_2
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_2(void)
Return to clock blocks that is turned off during WFI.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:491
ll_cgc_enable_wfi_off_usb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_usb_hclk(void)
Enable USB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1321
ll_cgc_disable_i2s_low_power
__STATIC_INLINE void ll_cgc_disable_i2s_low_power(void)
Disable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:3366
ll_cgc_disable_wfi_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sim_hclk(void)
Disable SIM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:913
ll_cgc_disable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rng_hclk(void)
Disable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5271
ll_cgc_disable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm1_slp_wfi(void)
Disable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4416
ll_cgc_is_enabled_force_off_pdm_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pdm_hclk(void)
Indicate whether the clock for PDM is forced to close.
Definition: gr55xx_ll_cgc.h:2990
ll_cgc_disable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_apb_sub_hclk(void)
Disabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1883
ll_cgc_enable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_efuse_hclk(void)
Enable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5299
ll_cgc_is_enabled_force_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_rom_hclk(void)
Indicate whether the clock for ROM is forced to close.
Definition: gr55xx_ll_cgc.h:1729
ll_cgc_is_enabled_force_off_uart2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart2_hclk(void)
Indicate whether the clock for UART2 is forced to close.
Definition: gr55xx_ll_cgc.h:2233
ll_cgc_is_enabled_force_off_i2s_s_p_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_s_p_hclk(void)
Indicate whether the clock for I2S slave is forced to close.
Definition: gr55xx_ll_cgc.h:2906
ll_cgc_is_enabled_ahb2apb_sync_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb2apb_sync_bus_low_power(void)
Indicate whether the AHB2APB bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3632
ll_cgc_enable_wfi_off_pwm_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_pwm_hclk(void)
Enable PWM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:983
ll_cgc_enable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c2_hclk(void)
Enabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2457
ll_cgc_disable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm0_hclk(void)
Disabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:3101
LL_CGC_MCU_SECU_FRC_OFF_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_HCLK
Definition: gr55xx_ll_cgc.h:236
ll_cgc_disable_force_off_xf_xqspi_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_xf_xqspi_div4_pclk(void)
Disabling force to turn off the div4 clock for xf qspi blocks.
Definition: gr55xx_ll_cgc.h:3059
ll_cgc_is_enabled_force_off_sram_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sram_hclk(void)
Indicate whether the clock for SRAM is forced to close.
Definition: gr55xx_ll_cgc.h:2107
ll_cgc_disable_force_off_rng_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_rng_hclk(void)
Disabling force to turn off the clock for RNG.
Definition: gr55xx_ll_cgc.h:4977
ll_cgc_disable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_div4_hclk(void)
Disable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1547
ll_cgc_enable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2s_s_slp_wfi(void)
Enable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4234
ll_cgc_disable_force_off_i2c4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c4_hclk(void)
Disabling force to turn off the clock for I2C4.
Definition: gr55xx_ll_cgc.h:2555
ll_cgc_is_enabled_force_off_pwm1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_pwm1_hclk(void)
Indicate whether the clock for PWM1 is forced to close.
Definition: gr55xx_ll_cgc.h:3157
ll_cgc_is_enabled_force_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_aon_mcusub_hclk(void)
Indicate whether the clock for AON_MUCSUB is forced to close.
Definition: gr55xx_ll_cgc.h:2023
ll_cgc_is_enabled_uart3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart3_slp_wfi(void)
Indicate whether turn UART3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3842
ll_cgc_is_enabled_spis_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spis_sclk_low_power(void)
Indicate whether the spis sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3464
ll_cgc_is_enabled_force_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_hclk(void)
Indicate whether the clock for security blocks(including AES, PKC, Present, HMAC) is forced to close.
Definition: gr55xx_ll_cgc.h:1603
ll_cgc_is_enabled_force_off_dspi_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dspi_hclk(void)
Indicate whether the clock for DSPI is forced to close.
Definition: gr55xx_ll_cgc.h:2948
ll_cgc_get_slp_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_slp_off_secu(void)
Return to security clock blocks that is turned off during WFI/WFE.(Include: AES/HMAC/PKC/PRESENT/RAMK...
Definition: gr55xx_ll_cgc.h:4738
ll_cgc_is_enabled_force_off_xqspi_sck
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_xqspi_sck(void)
Indicate whether the XQSPI SCK CLK automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5395
ll_cgc_disable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_aon_mcusub_hclk(void)
Disable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1378
ll_cgc_disable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_rom_hclk(void)
Disable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1039
ll_cgc_set_misc_clk
__STATIC_INLINE void ll_cgc_set_misc_clk(uint32_t clk_mask)
Some MISC_CLK blocks turn off clock. (Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
Definition: gr55xx_ll_cgc.h:5341
ll_cgc_disable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2s_s_p_hclk(void)
Disabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2892
ll_cgc_is_enabled_force_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_sim_hclk(void)
Indicate whether the clock for SIM is forced to close.
Definition: gr55xx_ll_cgc.h:1645
LL_CGC_FRC_ALL_HCLK2
#define LL_CGC_FRC_ALL_HCLK2
Definition: gr55xx_ll_cgc.h:164
ll_cgc_is_enabled_wfi_off_apb_sub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_apb_sub_hclk(void)
Indicate whether the APB Subsystem automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1264
LL_CGC_MCU_MISC_CLK
#define LL_CGC_MCU_MISC_CLK
Definition: gr55xx_ll_cgc.h:244
ll_cgc_enable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_hclk(void)
Enabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1575
ll_cgc_disable_ahb_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb_bus_low_power(void)
Disable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3534
ll_cgc_disable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_xqspi_hclk(void)
Disable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1420
LL_CGC_WFI_ALL_HCLK0
#define LL_CGC_WFI_ALL_HCLK0
Definition: gr55xx_ll_cgc.h:84
ll_cgc_disable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c5_slp_wfi(void)
Disable turn I2C5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4164
ll_cgc_disable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart1_hclk(void)
Disabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2177
LL_CGC_WFI_ALL_HCLK1
#define LL_CGC_WFI_ALL_HCLK1
Definition: gr55xx_ll_cgc.h:95
ll_cgc_enable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_hmac_hclk(void)
Enabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4794
ll_cgc_enable_pdm_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pdm_slp_wfi(void)
Enable turn PDM off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4612
ll_cgc_disable_wfi_off_serial_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_serial_hclk(void)
Disable serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1292
ll_cgc_disable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart4_hclk(void)
Disabling force to turn off the clock for UART4.
Definition: gr55xx_ll_cgc.h:2303
ll_cgc_is_enabled_wfi_off_aes_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aes_hclk(void)
Indicate whether the AES automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5075
ll_cgc_disable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_hmac_hclk(void)
Disable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5103
ll_cgc_disable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spis_hclk(void)
Disabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2681
ll_cgc_enable_wfi_off_xqspi_div4_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_div4_hclk(void)
Enable XQSPI automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1533
ll_cgc_disable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_div4_pclk(void)
Disabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:3018
ll_cgc_disable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_htb_hclk(void)
Disabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1673
ll_cgc_enable_force_off_dma0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma0_hclk(void)
Enable DMA0 turn off.
Definition: gr55xx_ll_cgc.h:5409
ll_cgc_disable_qspim0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim0_slp_wfi(void)
Disable turn QSPIM0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4458
ll_cgc_enable_uart0_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart0_slp_wfi(void)
Enable turn UART0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3688
ll_cgc_is_enabled_uart2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart2_slp_wfi(void)
Indicate whether turn UART2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3800
ll_cgc_enable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_sram_hclk(void)
Enabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2079
ll_cgc_enable_force_off_usb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_usb_hclk(void)
Enabling force to turn off the clock for USB.
Definition: gr55xx_ll_cgc.h:1953
ll_cgc_get_force_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_3(void)
Return to clock blocks that is turned off.(Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:842
ll_cgc_disable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim1_slp_wfi(void)
Disable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4500
ll_cgc_is_enabled_force_off_spim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spim_hclk(void)
Indicate whether the clock for SPIM is forced to close.
Definition: gr55xx_ll_cgc.h:2653
ll_cgc_is_enabled_wfi_off_htb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_htb_hclk(void)
Indicate whether the Hopping Table automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:969
ll_cgc_enable_force_off_i2s_s_p_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_s_p_hclk(void)
Enabling force to turn off the clock for I2S slave.
Definition: gr55xx_ll_cgc.h:2878
ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_xqspi_div4_hclk(void)
Indicate whether the XQSPI automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1561
ll_cgc_is_enabled_spi_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spi_s_slp_wfi(void)
Indicate whether turn SPI_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4346
ll_cgc_disable_force_off_pdm_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pdm_hclk(void)
Disabling force to turn off the clock for PDM slave.
Definition: gr55xx_ll_cgc.h:2976
ll_cgc_disable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart1_slp_wfi(void)
Disable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3744
ll_cgc_disable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_uart3_hclk(void)
Disabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:2261
ll_cgc_enable_spim_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spim_sclk_low_power(void)
Enable spim sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3394
ll_cgc_is_enabled_qspim0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim0_slp_wfi(void)
Indicate whether turn QSPIM0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4472
ll_cgc_enable_force_off_secu_div4_pclk
__STATIC_INLINE void ll_cgc_enable_force_off_secu_div4_pclk(void)
Enabling force to turn off the div4 clock for security blocks.
Definition: gr55xx_ll_cgc.h:3004
ll_cgc_is_enabled_wfi_off_ramkey_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_ramkey_hclk(void)
Indicate whether the RAMKEY automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5243
ll_cgc_disable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_vttbl_hclk(void)
Disabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:3185
ll_cgc_disable_wfi_off_secu_div4_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_secu_div4_hclk(void)
Disable security blocks automatic turn off div4 clock during WFI.
Definition: gr55xx_ll_cgc.h:1504
ll_cgc_enable_force_off_uart0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart0_hclk(void)
Enabling force to turn off the clock for UART0.
Definition: gr55xx_ll_cgc.h:2121
ll_cgc_disable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_pwm1_hclk(void)
Disabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:3143
ll_cgc_is_enabled_force_off_snsadc_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_snsadc_hclk(void)
Indicate whether the clock for SNSADC is forced to close.
Definition: gr55xx_ll_cgc.h:1771
ll_cgc_disable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_apb_sub_hclk(void)
Disable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1250
ll_cgc_enable_wfi_off_rom_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rom_hclk(void)
Enable ROM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1025
ll_cgc_is_enabled_force_off_spis_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_spis_hclk(void)
Indicate whether the clock for SPIS is forced to close.
Definition: gr55xx_ll_cgc.h:2695
ll_cgc_is_enabled_wfi_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_serial_hclk(void)
Indicate whether the serial blocks(including I2C, UART, QSPI, I2S, SPI) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:1307
ll_cgc_is_enabled_pwm1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm1_slp_wfi(void)
Indicate whether turn pwm1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4430
ll_cgc_enable_force_off_qspi1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi1_hclk(void)
Enabling force to turn off the clock for QSPI1.
Definition: gr55xx_ll_cgc.h:2751
ll_cgc_enable_ahb2apb_async_bus_low_power
__STATIC_INLINE void ll_cgc_enable_ahb2apb_async_bus_low_power(void)
Enable ahb bus low-power feature.
Definition: gr55xx_ll_cgc.h:3646
ll_cgc_disable_wfi_off_snsadc_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_snsadc_hclk(void)
Disable SNSADC automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1081
ll_cgc_disable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_ramkey_hclk(void)
Disable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5229
ll_cgc_enable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_enable_dspi_slp_wfi(void)
Enable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4570
ll_cgc_get_force_off_secu
__STATIC_INLINE uint32_t ll_cgc_get_force_off_secu(void)
Return to clock blocks that was forcibly closed inside security system.(Include: AES/HMAC/PKC/PRESENT...
Definition: gr55xx_ll_cgc.h:4695
ll_cgc_is_enabled_wfi_off_efuse_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_efuse_hclk(void)
Indicate whether the EFUSE automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5327
ll_cgc_enable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spim_hclk(void)
Enabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2625
ll_cgc_enable_force_off_pwm0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm0_hclk(void)
Enabling force to turn off the clock for PWM0.
Definition: gr55xx_ll_cgc.h:3087
ll_cgc_disable_force_off_i2c2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c2_hclk(void)
Disabling force to turn off the clock for I2C2.
Definition: gr55xx_ll_cgc.h:2471
ll_cgc_disable_wfi_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_present_hclk(void)
Disable PRESENT automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5187
ll_cgc_get_force_off_hclk_1
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_1(void)
Return to clock blocks that was forcibly closed.(Include: AON_MCUSUB/XF_XQSPI/SRAM)
Definition: gr55xx_ll_cgc.h:669
ll_cgc_enable_wfi_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aon_mcusub_hclk(void)
Enable AON_MUCSUB automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1364
ll_cgc_enable_wfi_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ramkey_hclk(void)
Enable RAMKEY automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5215
ll_cgc_set_wfi_off_hclk_4
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_4(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:548
ll_cgc_enable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_present_hclk(void)
Enabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4878
ll_cgc_enable_spi_m_slp_wfi
__STATIC_INLINE void ll_cgc_enable_spi_m_slp_wfi(void)
Enable turn SPI_M off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4276
ll_cgc_disable_uart_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_sclk_low_power(void)
Disable uart sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3282
CGC_CLOCK_DISABLE
#define CGC_CLOCK_DISABLE
Definition: gr55xx_ll_cgc.h:324
ll_cgc_enable_force_off_uart2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart2_hclk(void)
Enabling force to turn off the clock for UART2.
Definition: gr55xx_ll_cgc.h:2205
ll_cgc_disable_uart2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart2_slp_wfi(void)
Disable turn UART2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3786
ll_cgc_enable_i2c5_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c5_slp_wfi(void)
Enable turn I2C5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4150
ll_cgc_enable_uart4_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart4_slp_wfi(void)
Enable turn UART4 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3856
ll_cgc_is_enabled_force_off_qspi0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_qspi0_hclk(void)
Indicate whether the clock for QSPI0 is forced to close.
Definition: gr55xx_ll_cgc.h:2737
ll_cgc_enable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ramkey_hclk(void)
Enabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4920
ll_cgc_is_enabled_dspi_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_dspi_slp_wfi(void)
Indicate whether turn DSPI off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4598
ll_cgc_enable_force_off_pwm1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pwm1_hclk(void)
Enabling force to turn off the clock for PWM1.
Definition: gr55xx_ll_cgc.h:3129
ll_cgc_disable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_hclk(void)
Disabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2051
ll_cgc_is_enabled_uart0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart0_slp_wfi(void)
Indicate whether turn UART0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3716
ll_cgc_enable_qspim1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim1_slp_wfi(void)
Enable turn QSPIM1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4486
ll_cgc_enable_force_off_spis_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_spis_hclk(void)
Enabling force to turn off the clock for SPIS.
Definition: gr55xx_ll_cgc.h:2667
ll_cgc_is_enabled_i2c4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c4_slp_wfi(void)
Indicate whether turn I2C4 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4136
ll_cgc_enable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2c1_hclk(void)
Enabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2415
ll_cgc_enable_force_off_uart3_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart3_hclk(void)
Enabling force to turn off the clock for UART3.
Definition: gr55xx_ll_cgc.h:2247
ll_cgc_disable_uart_pclk_low_power
__STATIC_INLINE void ll_cgc_disable_uart_pclk_low_power(void)
Disable uart pclk low-power feature.
Definition: gr55xx_ll_cgc.h:3324
ll_cgc_disable_force_off_i2c0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c0_hclk(void)
Disabling force to turn off the clock for I2C0.
Definition: gr55xx_ll_cgc.h:2387
ll_cgc_is_enabled_force_off_serial_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_serial_hclk(void)
Indicate whether the clock for serial blocks(including I2C, UART, QSPI, I2S, SPI) is forced to close.
Definition: gr55xx_ll_cgc.h:1939
ll_cgc_enable_force_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_xqspi_hclk(void)
Enabling force to turn off the clock for XQSPI.
Definition: gr55xx_ll_cgc.h:2037
ll_cgc_enable_uart1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_uart1_slp_wfi(void)
Enable turn UART1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3730
ll_cgc_is_enabled_force_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_present_hclk(void)
Indicate whether the clock for PRESENT is forced to close.
Definition: gr55xx_ll_cgc.h:4906
ll_cgc_get_force_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_force_off_hclk_0(void)
Return to clock blocks that was forcibly closed.(Include: Security/SIM/HTB/ ROM/SNSADC/GPIO/DMA/BLE_B...
Definition: gr55xx_ll_cgc.h:630
ll_cgc_disable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_aon_mcusub_hclk(void)
Disabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:2009
ll_cgc_is_enabled_force_off_secu_div4_pclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_secu_div4_pclk(void)
Indicate whether the div4 clock for security blocks is forced to close.
Definition: gr55xx_ll_cgc.h:3032
ll_cgc_is_enabled_force_off_dma2_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma2_hclk(void)
Indicate whether the DMA2 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5521
ll_cgc_is_enabled_uart5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart5_slp_wfi(void)
Indicate whether turn UART5 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3926
ll_cgc_disable_force_off_ramkey_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_ramkey_hclk(void)
Disabling force to turn off the clock for RAMKEY.
Definition: gr55xx_ll_cgc.h:4934
ll_cgc_disable_force_off_sim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sim_hclk(void)
Disabling force to turn off the clock for SIM.
Definition: gr55xx_ll_cgc.h:1631
ll_cgc_is_enabled_qspim2_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_qspim2_slp_wfi(void)
Indicate whether turn QSPIM2 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4556
ll_cgc_enable_wfi_off_hmac_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_hmac_hclk(void)
Enable HMAC automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5089
ll_cgc_enable_wfi_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_apb_sub_hclk(void)
Enable APB Subsystem automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1236
ll_cgc_disable_uart3_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart3_slp_wfi(void)
Disable turn UART3 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3828
ll_cgc_is_enabled_i2c3_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c3_slp_wfi(void)
Indicate whether turn I2C3 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4094
ll_cgc_disable_force_off_spim_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_spim_hclk(void)
Disabling force to turn off the clock for SPIM.
Definition: gr55xx_ll_cgc.h:2639
ll_cgc_enable_force_off_uart1_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart1_hclk(void)
Enabling force to turn off the clock for UART1.
Definition: gr55xx_ll_cgc.h:2163
ll_cgc_is_enabled_force_off_usb_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_usb_hclk(void)
Indicate whether the clock for USB is forced to close.
Definition: gr55xx_ll_cgc.h:1981
ll_cgc_enable_i2s_low_power
__STATIC_INLINE void ll_cgc_enable_i2s_low_power(void)
Enable i2s low-power feature.
Definition: gr55xx_ll_cgc.h:3352
ll_cgc_enable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dma2_hclk(void)
Enable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:5493
ll_cgc_enable_wfi_off_aes_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_aes_hclk(void)
Enable AES automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5047
ll_cgc_disable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_disable_qspim2_slp_wfi(void)
Disable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4542
ll_cgc_enable_i2c2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c2_slp_wfi(void)
Enable turn I2C2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4024
ll_cgc_enable_force_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_gpio_hclk(void)
Enabling force to turn off the clock for GPIO.
Definition: gr55xx_ll_cgc.h:1785
ll_cgc_is_enabled_spim_sclk_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_spim_sclk_low_power(void)
Indicate whether the spim sclk low-power is enabled.
Definition: gr55xx_ll_cgc.h:3422
ll_cgc_disable_force_off_present_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_present_hclk(void)
Disabling force to turn off the clock for PRESENT.
Definition: gr55xx_ll_cgc.h:4892
ll_cgc_disable_force_off_i2c1_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c1_hclk(void)
Disabling force to turn off the clock for I2C1.
Definition: gr55xx_ll_cgc.h:2429
ll_cgc_enable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_dma_hclk(void)
Enable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1151
ll_cgc_disable_wfi_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_sram_hclk(void)
Disable SRAM automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1462
ll_cgc_disable_wfi_off_dma_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_dma_hclk(void)
Disable DMA automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1165
ll_cgc_is_enabled_force_off_dma1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_dma1_hclk(void)
Indicate whether the DMA1 automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5479
ll_cgc_set_slp_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_slp_off_hclk_secu(uint32_t clk_mask)
Some security blocks automatic turn off clock during WFI/WFE. (Include: AES/HMAC/PKC/PRESENT/RAMKAY/R...
Definition: gr55xx_ll_cgc.h:4717
ll_cgc_set_wfi_off_hclk_0
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_0(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO...
Definition: gr55xx_ll_cgc.h:383
ll_cgc_enable_force_off_i2s_m_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_i2s_m_hclk(void)
Enabling force to turn off the clock for I2S master.
Definition: gr55xx_ll_cgc.h:2836
ll_cgc_is_enabled_uart4_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_uart4_slp_wfi(void)
Indicate whether turn UART4 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:3884
ll_cgc_is_enabled_ahb_bus_low_power
__STATIC_INLINE uint32_t ll_cgc_is_enabled_ahb_bus_low_power(void)
Indicate whether the ahb bus low-power is enabled.
Definition: gr55xx_ll_cgc.h:3548
ll_cgc_disable_force_off_sram_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_sram_hclk(void)
Disabling force to turn off the clock for SRAM.
Definition: gr55xx_ll_cgc.h:2093
ll_cgc_disable_force_off_hmac_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_hmac_hclk(void)
Disabling force to turn off the clock for HMAC.
Definition: gr55xx_ll_cgc.h:4808
ll_cgc_enable_force_off_dspi_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_dspi_hclk(void)
Enabling force to turn off the clock for DSPI slave.
Definition: gr55xx_ll_cgc.h:2920
ll_cgc_is_enabled_force_off_uart0_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart0_hclk(void)
Indicate whether the clock for UART0 is forced to close.
Definition: gr55xx_ll_cgc.h:2149
ll_cgc_is_enabled_wfi_off_present_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_present_hclk(void)
Indicate whether the PRESENT automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5201
ll_cgc_enable_force_off_serial_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_serial_hclk(void)
Enabling force to turn off the clock for serial blocks(including I2C, UART, QSPI, I2S,...
Definition: gr55xx_ll_cgc.h:1911
ll_cgc_enable_force_off_aon_mcusub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_aon_mcusub_hclk(void)
Enabling force to turn off the clock for AON_MUCSUB.
Definition: gr55xx_ll_cgc.h:1995
ll_cgc_is_enabled_i2s_s_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_s_slp_wfi(void)
Indicate whether turn I2S_S off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4262
ll_cgc_enable_wfi_off_gpio_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_gpio_hclk(void)
Enable GPIO automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1109
ll_cgc_is_enabled_i2s_m_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2s_m_slp_wfi(void)
Indicate whether turn I2S_M off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4220
ll_cgc_disable_wfi_off_efuse_hclk
__STATIC_INLINE void ll_cgc_disable_wfi_off_efuse_hclk(void)
Disable EFUSE automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5313
ll_cgc_enable_wfi_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_ble_brg_hclk(void)
Enable BLE Bridge automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1194
ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_aon_mcusub_hclk(void)
Indicate whether the AON_MUCSUB automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1392
ll_cgc_enable_force_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_htb_hclk(void)
Enabling force to turn off the clock for Hopping Table.
Definition: gr55xx_ll_cgc.h:1659
ll_cgc_get_wfi_off_hclk_3
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_3(void)
Return to clock blocks that is turned off during WFI.(Include: UART/DSPI.I2C/QSPI....
Definition: gr55xx_ll_cgc.h:530
ll_cgc_is_enabled_pdm_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pdm_slp_wfi(void)
Indicate whether turn PDM off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4640
ll_cgc_enable_i2c1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_i2c1_slp_wfi(void)
Enable turn I2C1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3982
ll_cgc_enable_force_off_pkc_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_pkc_hclk(void)
Enabling force to turn off the clock for PKC.
Definition: gr55xx_ll_cgc.h:4836
ll_cgc_is_enabled_force_off_i2c3_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2c3_hclk(void)
Indicate whether the clock for I2C3 is forced to close.
Definition: gr55xx_ll_cgc.h:2527
ll_cgc_disable_force_off_usb_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_usb_hclk(void)
Disabling force to turn off the clock for USB.
Definition: gr55xx_ll_cgc.h:1967
ll_cgc_enable_force_off_ble_brg_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_ble_brg_hclk(void)
Enabling force to turn off the clock for BLE Bridge.
Definition: gr55xx_ll_cgc.h:1827
ll_cgc_is_enabled_wfi_off_secu_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_hclk(void)
Indicate whether the security blocks(including AES, PKC, Present, HMAC) automatic turn off clock is e...
Definition: gr55xx_ll_cgc.h:885
ll_cgc_enable_qspim_low_power
__STATIC_INLINE void ll_cgc_enable_qspim_low_power(void)
Enable QSPIM low-power feature.
Definition: gr55xx_ll_cgc.h:3562
ll_cgc_enable_force_off_apb_sub_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_apb_sub_hclk(void)
Enabling force to turn off the clock for APB Subsystem.
Definition: gr55xx_ll_cgc.h:1869
ll_cgc_is_enabled_wfi_off_sim_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_sim_hclk(void)
Indicate whether the SIM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:927
ll_cgc_enable_wfi_off_secu_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_secu_hclk(void)
Enable security blocks(including AES, PKC, Present, HMAC) automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:857
ll_cgc_enable_pwm1_slp_wfi
__STATIC_INLINE void ll_cgc_enable_pwm1_slp_wfi(void)
Enable turn pwm1 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4402
LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
#define LL_CGC_MCU_SECU_FRC_OFF_WFI_HCLK
Definition: gr55xx_ll_cgc.h:237
ll_cgc_enable_force_off_uart4_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart4_hclk(void)
Enabling force to turn off the clock for UART4.
Definition: gr55xx_ll_cgc.h:2289
ll_cgc_is_enabled_i2c5_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c5_slp_wfi(void)
Indicate whether turn I2C5 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4178
ll_cgc_disable_spi_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_spi_s_slp_wfi(void)
Disable turn SPI_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4332
ll_cgc_disable_i2s_s_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2s_s_slp_wfi(void)
Disable turn I2S_S off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4248
ll_cgc_disable_ahb2apb_sync_bus_low_power
__STATIC_INLINE void ll_cgc_disable_ahb2apb_sync_bus_low_power(void)
Disable AHB2APB bus low-power feature.
Definition: gr55xx_ll_cgc.h:3618
ll_cgc_enable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_enable_spis_sclk_low_power(void)
Enable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3436
ll_cgc_disable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_qspi0_hclk(void)
Disabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2723
ll_cgc_is_enabled_wfi_off_rom_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rom_hclk(void)
Indicate whether the ROM automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:1053
ll_cgc_enable_force_off_vttbl_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_vttbl_hclk(void)
Enabling force to turn off the clock for VTTBL.
Definition: gr55xx_ll_cgc.h:3171
ll_cgc_enable_qspim2_slp_wfi
__STATIC_INLINE void ll_cgc_enable_qspim2_slp_wfi(void)
Enable turn QSPIM2 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4528
ll_cgc_enable_wfi_off_rng_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_rng_hclk(void)
Enable RNG automatic turn off clock during WFI/WFE.
Definition: gr55xx_ll_cgc.h:5257
ll_cgc_disable_force_off_secu_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_secu_hclk(void)
Disabling force to turn off the clock for security blocks(including AES, PKC, Present,...
Definition: gr55xx_ll_cgc.h:1589
ll_cgc_disable_i2c0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_i2c0_slp_wfi(void)
Disable turn I2C0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3954
ll_cgc_is_enabled_force_off_i2s_m_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_i2s_m_hclk(void)
Indicate whether the clock for I2S master is forced to close.
Definition: gr55xx_ll_cgc.h:2864
LL_CGC_FRC_ALL_HCLK1
#define LL_CGC_FRC_ALL_HCLK1
Definition: gr55xx_ll_cgc.h:130
ll_cgc_set_force_off_hclk_secu
__STATIC_INLINE void ll_cgc_set_force_off_hclk_secu(uint32_t clk_mask)
Individual block's clock control inside security system which was forced to turn off (Include: AES/HM...
Definition: gr55xx_ll_cgc.h:4668
ll_cgc_is_enabled_pwm0_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_pwm0_slp_wfi(void)
Indicate whether turn pwm0 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4388
ll_cgc_is_enabled_wfi_off_secu_div4_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_secu_div4_hclk(void)
Indicate whether the security blocks automatic turn off div4 clock is enabled.
Definition: gr55xx_ll_cgc.h:1519
ll_cgc_disable_spis_sclk_low_power
__STATIC_INLINE void ll_cgc_disable_spis_sclk_low_power(void)
Disable spis sclk low-power feature.
Definition: gr55xx_ll_cgc.h:3450
ll_cgc_enable_wfi_off_xqspi_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_xqspi_hclk(void)
Enable XQSPI automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:1406
ll_cgc_set_force_off_hclk_3
__STATIC_INLINE void ll_cgc_set_force_off_hclk_3(uint32_t clk_mask)
Some peripherals automatic turn off clock. (Include: AES/HMAC/PKC/RNG.etc)
Definition: gr55xx_ll_cgc.h:825
ll_cgc_is_enabled_i2c1_slp_wfi
__STATIC_INLINE uint32_t ll_cgc_is_enabled_i2c1_slp_wfi(void)
Indicate whether turn I2C1 off during WFI/WFE is enabled.
Definition: gr55xx_ll_cgc.h:4010
ll_cgc_set_wfi_off_hclk_2
__STATIC_INLINE void ll_cgc_set_wfi_off_hclk_2(uint32_t clk_mask)
Some peripherals automatic turn off clock during WFI. (Include: SECU_DIV4/XQSPI_DIV4)
Definition: gr55xx_ll_cgc.h:474
ll_cgc_disable_uart5_slp_wfi
__STATIC_INLINE void ll_cgc_disable_uart5_slp_wfi(void)
Disable turn UART5 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:3912
ll_cgc_enable_force_off_qspi0_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_qspi0_hclk(void)
Enabling force to turn off the clock for QSPI0.
Definition: gr55xx_ll_cgc.h:2709
ll_cgc_disable_force_off_xqspi_sck
__STATIC_INLINE void ll_cgc_disable_force_off_xqspi_sck(void)
Disable XQSPI SCK CLK turn off.
Definition: gr55xx_ll_cgc.h:5381
ll_cgc_enable_wfi_off_htb_hclk
__STATIC_INLINE void ll_cgc_enable_wfi_off_htb_hclk(void)
Enable Hopping Table automatic turn off clock during WFI.
Definition: gr55xx_ll_cgc.h:941
ll_cgc_enable_force_off_uart5_hclk
__STATIC_INLINE void ll_cgc_enable_force_off_uart5_hclk(void)
Enabling force to turn off the clock for UART5.
Definition: gr55xx_ll_cgc.h:2331
ll_cgc_disable_force_off_i2c5_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_i2c5_hclk(void)
Disabling force to turn off the clock for I2C5.
Definition: gr55xx_ll_cgc.h:2597
ll_cgc_disable_dspi_slp_wfi
__STATIC_INLINE void ll_cgc_disable_dspi_slp_wfi(void)
Disable turn DSPI off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4584
ll_cgc_is_enabled_wfi_off_rng_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_wfi_off_rng_hclk(void)
Indicate whether the RNG automatic turn off clock is enabled.
Definition: gr55xx_ll_cgc.h:5285
ll_cgc_get_misc_clk
__STATIC_INLINE uint32_t ll_cgc_get_misc_clk(void)
Return to MISC_CLK clock blocks that is turned off.(Include: GPADC/XQSPI/DMA0/DMA1/DMA2)
Definition: gr55xx_ll_cgc.h:5353
ll_cgc_is_enabled_force_off_uart1_hclk
__STATIC_INLINE uint32_t ll_cgc_is_enabled_force_off_uart1_hclk(void)
Indicate whether the clock for UART1 is forced to close.
Definition: gr55xx_ll_cgc.h:2191
ll_cgc_disable_pwm0_slp_wfi
__STATIC_INLINE void ll_cgc_disable_pwm0_slp_wfi(void)
Disable turn pwm0 off during WFI/WFE.
Definition: gr55xx_ll_cgc.h:4374
ll_cgc_disable_force_off_dma2_hclk
__STATIC_INLINE void ll_cgc_disable_force_off_dma2_hclk(void)
Disable DMA2 turn off.
Definition: gr55xx_ll_cgc.h:5507
LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
#define LL_CGC_MCU_PERIPH_SERIALS_SLP_ALL
Definition: gr55xx_ll_cgc.h:213
ll_cgc_get_wfi_off_hclk_0
__STATIC_INLINE uint32_t ll_cgc_get_wfi_off_hclk_0(void)
Return to clock blocks that is turned off during WFI.(Include: Security/SIM/HTB/PWM/ ROM/SNSADC/GPIO/...
Definition: gr55xx_ll_cgc.h:417