52 #ifndef __GR55xx_LL_OSPI_X_H__
53 #define __GR55xx_LL_OSPI_X_H__
128 #define LL_OSPI_X_TCEM_TIME_IGNORE_DISABLE 0x00
129 #define LL_OSPI_X_TCEM_TIME_IGNORE_ENABLE 0x01
136 #define LL_OSPI_X_TXHS_TIME_IGNORE_DISABLE 0x00
137 #define LL_OSPI_X_TXHS_TIME_IGNORE_ENABLE 0x01
144 #define LL_OSPI_X_ACCESS_TYPE_MEMORY_ARRAY 0x00
145 #define LL_OSPI_X_ACCESS_TYPE_MODE_REGISTER 0x01
152 #define LL_OSPI_X_TXDPD_TIME_IGNORE_DISABLE 0x00
153 #define LL_OSPI_X_TXDPD_TIME_IGNORE_ENABLE 0x01
160 #define LL_OSPI_X_READ_PREFETCH_DISABLE 0x00
161 #define LL_OSPI_X_READ_PREFETCH_ENABLE 0x01
168 #define LL_OSPI_X_INTERRUPT_DISABLE 0x00
169 #define LL_OSPI_X_INTERRUPT_ENABLE 0x01
176 #define LL_OSPI_X_MEM_PAGE_SIZE_64Bytes 0x06
177 #define LL_OSPI_X_MEM_PAGE_SIZE_128Bytes 0x07
178 #define LL_OSPI_X_MEM_PAGE_SIZE_256Bytes 0x08
179 #define LL_OSPI_X_MEM_PAGE_SIZE_512Bytes 0x09
180 #define LL_OSPI_X_MEM_PAGE_SIZE_1024Bytes 0x0A
181 #define LL_OSPI_X_MEM_PAGE_SIZE_2048Bytes 0x0B
182 #define LL_OSPI_X_MEM_PAGE_SIZE_4096Bytes 0x0C
198 MODIFY_REG(OSPIx->MEM_BASE_ADDR, OSPI_X_MEM_BASE_ADDR, base_address << OSPI_X_MEM_BASE_ADDR_POS);
209 return (uint32_t)(READ_BITS(OSPIx->MEM_BASE_ADDR, OSPI_X_MEM_BASE_ADDR) >> OSPI_X_MEM_BASE_ADDR_POS);
221 MODIFY_REG(OSPIx->MEM_TOP_ADDR, OSPI_X_MEM_TOP_ADDR, top_address << OSPI_X_MEM_TOP_ADDR_POS);
232 return (uint32_t)(READ_BITS(OSPIx->MEM_TOP_ADDR, OSPI_X_MEM_TOP_ADDR) >> OSPI_X_MEM_TOP_ADDR_POS);
244 MODIFY_REG(OSPIx->GLOBAL_RESET, OSPI_X_TRST_CNT, trst_cnt << OSPI_X_TRST_CNT_POS);
255 return (uint32_t)(READ_BITS(OSPIx->GLOBAL_RESET, OSPI_X_TRST_CNT) >> OSPI_X_TRST_CNT_POS);
266 MODIFY_REG(OSPIx->GLOBAL_RESET, OSPI_X_GLOBAL_RST_EN, 1 << OSPI_X_GLOBAL_RST_EN_POS);
278 MODIFY_REG(OSPIx->ACCESS_TYPE, OSPI_X_ACCESS_TYPE, access_type << OSPI_X_ACCESS_TYPE_POS);
289 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TYPE, OSPI_X_ACCESS_TYPE) >> OSPI_X_ACCESS_TYPE_POS);
301 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_IGNORE, is_ignore << OSPI_X_TCEM_IGNORE_POS);
312 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_IGNORE) >> OSPI_X_TCEM_IGNORE_POS);
324 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_CNT, tcem_cnt << OSPI_X_TCEM_CNT_POS);
335 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCEM_CNT) >> OSPI_X_TCEM_CNT_POS);
347 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TRC_CNT, trc_cnt << OSPI_X_TRC_CNT_POS);
358 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TRC_CNT) >> OSPI_X_TRC_CNT_POS);
370 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_TCPH_CNT, tcph_cnt << OSPI_X_TCPH_CNT_POS);
381 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_TCPH_CNT) >> OSPI_X_TCPH_CNT_POS);
393 MODIFY_REG(OSPIx->ACCESS_TIMING, OSPI_X_MEM_PAGE_SIZE, mem_page_size << OSPI_X_MEM_PAGE_SIZE_POS);
404 return (uint32_t)(READ_BITS(OSPIx->ACCESS_TIMING, OSPI_X_MEM_PAGE_SIZE) >> OSPI_X_MEM_PAGE_SIZE_POS);
415 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_DPD_ENTRY, 0x01 << OSPI_X_DPD_ENTRY_POS);
426 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_DPD_EXIT, 0x01 << OSPI_X_DPD_EXIT_POS);
438 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_TIME_IGNORE, is_ignore << OSPI_X_TXDPD_TIME_IGNORE_POS);
449 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_TIME_IGNORE) >> OSPI_X_TXDPD_TIME_IGNORE_POS);
461 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_CNT, txdpd_cnt << OSPI_X_TXDPD_CNT_POS);
472 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXDPD_CNT) >> OSPI_X_TXDPD_CNT_POS);
484 MODIFY_REG(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXPDPD_CNT, txpdpd_cnt << OSPI_X_DPD_EXIT_CYCLE_CNT_POS);
495 return (uint32_t)(READ_BITS(OSPIx->DEEP_DOWN_CNTRL, OSPI_X_TXPDPD_CNT) >> OSPI_X_DPD_EXIT_CYCLE_CNT_POS);
506 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_ENTRY, 0x01 << OSPI_X_HS_ENTRY_POS);
517 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT, 0x01 << OSPI_X_HS_EXIT_POS);
529 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_TIME_IGNORE, is_ignore << OSPI_X_TXHS_TIME_IGNORE_POS);
540 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_TIME_IGNORE) >> OSPI_X_TXHS_TIME_IGNORE_POS);
552 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_CNT, txhs_count << OSPI_X_TXHS_CNT_POS);
563 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_TXHS_CNT) >> OSPI_X_TXHS_CNT_POS);
575 MODIFY_REG(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT_CYCLE_CNT, txphs_count << OSPI_X_HS_EXIT_CYCLE_CNT_POS);
586 return (uint32_t)(READ_BITS(OSPIx->HALF_SLP_CNTRL, OSPI_X_HS_EXIT_CYCLE_CNT) >> OSPI_X_HS_EXIT_CYCLE_CNT_POS);
598 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_GLOBAL_RST_IE, intr << OSPI_X_GLOBAL_RST_IE_POS);
609 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_GLOBAL_RST_IE) == OSPI_X_GLOBAL_RST_IE) ? 1 : 0;
621 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_ENTRY_IE, intr << OSPI_X_HS_ENTRY_IE_POS);
632 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_ENTRY_IE) == OSPI_X_HS_ENTRY_IE) ? 1 : 0;
644 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_EXIT_IE, intr << OSPI_X_HS_EXIT_IE_POS);
655 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_HS_EXIT_IE) == OSPI_X_HS_EXIT_IE) ? 1 : 0;
667 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_ENTRY_IE, intr << OSPI_X_DPD_ENTRY_IE_POS);
678 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_ENTRY_IE) == OSPI_X_DPD_ENTRY_IE) ? 1 : 0;
690 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_EXIT_IE, intr << OSPI_X_DPD_EXIT_IE_POS);
701 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DPD_EXIT_IE) == OSPI_X_DPD_EXIT_IE) ? 1 : 0;
713 MODIFY_REG(OSPIx->INTERRUPT_CNTRL, OSPI_X_DQS_TIMEOUT_IE, intr << OSPI_X_DQS_TIMEOUT_IE_POS);
724 return (READ_BITS(OSPIx->INTERRUPT_CNTRL, OSPI_X_DQS_TIMEOUT_IE) == OSPI_X_DQS_TIMEOUT_IE) ? 1 : 0;
735 uint32_t status = OSPIx->XFER_STATUS;
736 return ((status & 0x01) > 0 ? 1 : 0);
747 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_HS_ENTRY_DONE) == OSPI_X_HS_ENTRY_DONE) ? 1 : 0;
758 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_HS_EXIT_DONE) == OSPI_X_HS_EXIT_DONE) ? 1 : 0;
769 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DPD_ENTRY_DONE) == OSPI_X_DPD_ENTRY_DONE) ? 1 : 0;
780 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DPD_EXIT_DONE) == OSPI_X_DPD_EXIT_DONE) ? 1 : 0;
791 return (READ_BITS(OSPIx->XFER_STATUS, OSPI_X_DQS_NON_TOGGLE_ERR) == OSPI_X_DQS_NON_TOGGLE_ERR) ? 1 : 0;
803 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_RD, cmd << OSPI_X_CMD_SYNC_RD_POS);
814 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_RD) >> OSPI_X_CMD_SYNC_RD_POS);
826 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_WR, cmd << OSPI_X_CMD_SYNC_WR_POS);
837 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_SYNC_WR) >> OSPI_X_CMD_SYNC_WR_POS);
849 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_RD, cmd << OSPI_X_CMD_BURST_RD_POS);
860 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_RD) >> OSPI_X_CMD_BURST_RD_POS);
872 MODIFY_REG(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_WR, cmd << OSPI_X_CMD_BURST_WR_POS);
883 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_1, OSPI_X_CMD_BURST_WR) >> OSPI_X_CMD_BURST_WR_POS);
895 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_RD, cmd << OSPI_X_CMD_REG_RD_POS);
906 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_RD) >> OSPI_X_CMD_REG_RD_POS);
918 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_WR, cmd << OSPI_X_CMD_REG_WR_POS);
929 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_REG_WR) >> OSPI_X_CMD_REG_WR_POS);
941 MODIFY_REG(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_GLOBAL_RST, cmd << OSPI_X_CMD_GLOBAL_RST_POS);
952 return (uint32_t)(READ_BITS(OSPIx->CMD_CNTRL_2, OSPI_X_CMD_GLOBAL_RST) >> OSPI_X_CMD_GLOBAL_RST_POS);
964 timeout_clk = (timeout_clk > 31) ? 31 : timeout_clk;
965 MODIFY_REG(OSPIx->DQS_TIMEOUT, OSPI_X_DQS_NON_TGL_TIMEOUT, timeout_clk << OSPI_X_DQS_NON_TGL_TIMEOUT_POS);
976 return (uint32_t)(READ_BITS(OSPIx->DQS_TIMEOUT, OSPI_X_DQS_NON_TGL_TIMEOUT) >> OSPI_X_DQS_NON_TGL_TIMEOUT_POS);
988 MODIFY_REG(OSPIx->READ_PREFETCH, OSPI_X_RD_DATA_PREFETCH, is_prefetch << OSPI_X_RD_DATA_PREFETCH_POS);
999 return (READ_BITS(OSPIx->READ_PREFETCH, OSPI_X_RD_DATA_PREFETCH) == OSPI_X_RD_DATA_PREFETCH) ? 1 : 0;
1011 MODIFY_REG(OSPIx->PHY_CNTRL_0, 0xFF, phy_delay);
1022 return READ_BITS(OSPIx->PHY_CNTRL_0, 0xFF);
1032 return OSPI0_XIP_BASE;