52 #ifndef __GR55XX_LL_RTC_H__
53 #define __GR55XX_LL_RTC_H__
73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U)
74 #define LL_RTC_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos)
75 #define LL_RTC_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos)
76 #define LL_RTC_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos)
77 #define LL_RTC_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos)
78 #define LL_RTC_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos)
79 #define LL_RTC_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos)
80 #define LL_RTC_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos)
86 #define LL_RTC_TIMER_CLK_SEL_RNG (0x0U << RTC_CLK_SEL_Pos)
87 #define LL_RTC_TIMER_CLK_SEL_XO (0x1U << RTC_CLK_SEL_Pos)
88 #define LL_RTC_TIMER_CLK_SEL_RNG2 (0x2U << RTC_CLK_SEL_Pos)
89 #define LL_RTC_TIMER_CLK_SEL_RTC (0x3U << RTC_CLK_SEL_Pos)
95 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U)
96 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U)
104 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
105 RTC_CFG0_ALARM_EN | \
138 MODIFY_REG(RTCx->CLK, RTC_CLK_SEL, value);
156 return (READ_BITS(RTCx->CLK, RTC_CLK_SEL));
170 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
184 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
198 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
212 WRITE_REG(RTCx->TIMER_W, counter);
227 WRITE_REG(RTCx->TIMER_W, start_value);
228 SET_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
233 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
263 WRITE_REG(RTCx->ALARM_W, alarm_value);
264 SET_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
278 WRITE_REG(RTCx->TICK_W, tick);
279 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
280 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET);
294 return (uint32_t)READ_REG(RTCx->TIMER_W);
308 return (uint32_t)READ_REG(RTCx->TIMER_R);
322 return (uint32_t)READ_REG(RTCx->ALARM_W);
336 return (uint32_t)READ_REG(RTCx->ALARM_R);
341 return (uint32_t)READ_REG(RTCx->TICK_W);
346 return (uint32_t)READ_REG(RTCx->TICK_R);
361 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
375 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
389 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
404 SET_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
409 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
433 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
447 WRITE_REG(RTCx->ALARM_W, value);
448 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET);
453 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
467 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
481 CLEAR_BITS(RTCx->CFG0,RTC_CFG0_ALARM_SET | RTC_CFG0_ALARM_EN);
482 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
496 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
510 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
511 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
525 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
526 SET_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
546 CLEAR_BITS(RTCx->CFG0,((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
550 SET_BITS(RTCx->CFG0,(tick_mode << RTC_CFG0_TICK_MDOE_Pos));
564 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
577 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
578 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
591 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
605 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
606 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
620 WRITE_REG(RTCx->TICK_W, tick_reload);
621 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET);
634 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
635 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN);
648 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
662 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
676 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
690 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
712 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
728 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
744 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
758 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
772 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
787 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
794 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
796 else if(RTCx == RTC1)
798 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
806 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
808 else if(RTCx == RTC1)
810 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
827 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
829 else if(RTCx == RTC1)
831 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
848 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
850 else if(RTCx == RTC1)
852 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);