gr55xx_hal_cortex.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_hal_cortex.h
5  * @author BLE Driver Team
6  * @brief Header file of CORTEX HAL module.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup HAL_DRIVER HAL Driver
43  * @{
44  */
45 
46 /** @defgroup HAL_CORTEX CORTEX
47  * @brief CORTEX HAL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_CORTEX_H__
53 #define __GR55xx_HAL_CORTEX_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx_hal_def.h"
61 
62 /* Exported types ------------------------------------------------------------*/
63 
64 /** @addtogroup HAL_CORTEX_STRUCTURES Structures
65  * @{
66  */
67 
68 #if (__MPU_PRESENT == 1U)
69 
70 /** @defgroup CORTEX_MPU_Region_Configuration MPU Region Configuration
71  * @{
72  */
73 
74 /**
75  * @brief MPU Region initialization structure
76  */
77 typedef struct _mpu_region_init_t
78 {
79  uint8_t enable; /**< Specifies the status of the region.
80  This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
81 
82  uint8_t number; /**< Specifies the number of the region to protect.
83  This parameter can be a value of @ref CORTEX_MPU_Region_Number */
84 
85  uint32_t base_address; /**< Specifies the base address of the region to protect. */
86 
87  uint8_t size; /**< Specifies the size of the region to protect.
88  This parameter can be a value of @ref CORTEX_MPU_Region_Size */
89 
90  uint8_t subregion_disable; /**< Specifies the number of the subregion protection to disable.
91  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
92 
93  uint8_t type_tex_field; /**< Specifies the TEX field level.
94  This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
95 
96  uint8_t access_permission; /**< Specifies the region access permission type.
97  This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
98 
99  uint8_t disable_exec; /**< Specifies the instruction access status.
100  This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
101 
102  uint8_t is_shareable; /**< Specifies the shareability status of the protected region.
103  This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
104 
105  uint8_t is_cacheable; /**< Specifies the cacheable status of the region protected.
106  This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
107 
108  uint8_t is_bufferable; /**< Specifies the bufferable status of the protected region.
109  This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
110 
112 
113 /** @} */
114 
115 #endif /* __MPU_PRESENT */
116 
117 /** @} */
118 
119 
120 /**
121  * @defgroup HAL_CORTEX_MACRO Defines
122  * @{
123  */
124 
125 /* Exported constants --------------------------------------------------------*/
126 
127 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
128  * @{
129  */
130 
131 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
132  * @{
133  */
134 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /**< 0 bit for pre-emption priority,
135  8 bits for subpriority */
136 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /**< 1 bit for pre-emption priority,
137  7 bits for subpriority */
138 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /**< 2 bits for pre-emption priority,
139  6 bits for subpriority */
140 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /**< 3 bits for pre-emption priority,
141  5 bits for subpriority */
142 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /**< 4 bits for pre-emption priority,
143  4 bits for subpriority */
144 #define NVIC_PRIORITYGROUP_5 (0x00000002U) /**< 5 bits for pre-emption priority,
145  3 bits for subpriority */
146 #define NVIC_PRIORITYGROUP_6 (0x00000001U) /**< 6 bits for pre-emption priority,
147  2 bits for subpriority */
148 #define NVIC_PRIORITYGROUP_7 (0x00000000U) /**< 7 bits for pre-emption priority,
149  1 bit for subpriority */
150 /** @} */
151 
152 #if (__MPU_PRESENT == 1U)
153 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
154  * @{
155  */
156 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) /**< HFNMIENA disable, PRIVDEFENA disable */
157 #define MPU_HARDFAULT_NMI (0x00000002U) /**< HFNMIENA enable, PRIVDEFENA disable */
158 #define MPU_PRIVILEGED_DEFAULT (0x00000004U) /**< HFNMIENA disable, PRIVDEFENA enable */
159 #define MPU_HFNMI_PRIVDEF (0x00000006U) /**< HFNMIENA enable, PRIVDEFENA enable */
160 /** @} */
161 
162 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
163  * @{
164  */
165 #define MPU_REGION_ENABLE ((uint8_t)0x01U) /**< MPU Region Enable */
166 #define MPU_REGION_DISABLE ((uint8_t)0x00U) /**< MPU Region Disable */
167 /** @} */
168 
169 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
170  * @{
171  */
172 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) /**< MPU Instruction Access Enable */
173 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /**< MPU Instruction Access Disable */
174 /** @} */
175 
176 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
177  * @{
178  */
179 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) /**< MPU Instruction Access Shareable */
180 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Shareable */
181 /** @} */
182 
183 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
184  * @{
185  */
186 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) /**< MPU Instruction Access Cacheable */
187 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Cacheable */
188 /** @} */
189 
190 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
191  * @{
192  */
193 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) /**< MPU Instruction Access Bufferable */
194 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Bufferable */
195 /** @} */
196 
197 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
198  * @{
199  */
200 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U) /**< MPU TEX Level 0 */
201 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U) /**< MPU TEX Level 1 */
202 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /**< MPU TEX Level 2 */
203 /** @} */
204 
205 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
206  * @{
207  */
208 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) /**< MPU Region Size 32B */
209 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) /**< MPU Region Size 64B */
210 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) /**< MPU Region Size 128B */
211 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) /**< MPU Region Size 256B */
212 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) /**< MPU Region Size 512B */
213 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /**< MPU Region Size 1KB */
214 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /**< MPU Region Size 2KB */
215 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /**< MPU Region Size 4KB */
216 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /**< MPU Region Size 8KB */
217 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /**< MPU Region Size 16KB */
218 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /**< MPU Region Size 32KB */
219 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /**< MPU Region Size 64KB */
220 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /**< MPU Region Size 128KB */
221 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /**< MPU Region Size 256KB */
222 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /**< MPU Region Size 512KB */
223 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /**< MPU Region Size 1MB */
224 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /**< MPU Region Size 2MB */
225 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /**< MPU Region Size 4MB */
226 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /**< MPU Region Size 8MB */
227 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /**< MPU Region Size 16MB */
228 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /**< MPU Region Size 32MB */
229 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /**< MPU Region Size 64MB */
230 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /**< MPU Region Size 128MB */
231 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /**< MPU Region Size 256MB */
232 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /**< MPU Region Size 512MB */
233 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /**< MPU Region Size 1GB */
234 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /**< MPU Region Size 2GB */
235 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /**< MPU Region Size 4GB */
236 /** @} */
237 
238 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
239  * @{
240  */
241 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) /**< All accesses generate a permission fault */
242 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) /**< Access from privileged software only */
243 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) /**< Writes by unprivileged software generate a permission fault */
244 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) /**< Full access */
245 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) /**< Reads by privileged software only */
246 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /**< Read only, by privileged or unprivileged software */
247 /** @} */
248 
249 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
250  * @{
251  */
252 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) /**< MPU Region Number 0 */
253 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) /**< MPU Region Number 1 */
254 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) /**< MPU Region Number 2 */
255 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) /**< MPU Region Number 3 */
256 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) /**< MPU Region Number 4 */
257 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) /**< MPU Region Number 5 */
258 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) /**< MPU Region Number 6 */
259 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /**< MPU Region Number 7 */
260 /** @} */
261 #endif /* __MPU_PRESENT */
262 
263 /** @} */
264 
265 /* Exported Macros -----------------------------------------------------------*/
266 /* Private types -------------------------------------------------------------*/
267 /* Private variables ---------------------------------------------------------*/
268 /* Private constants ---------------------------------------------------------*/
269 
270 /* Private macros ------------------------------------------------------------*/
271 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
272  * @{
273  */
274 
275 /**
276  * @brief Check if NVIC priority group is valid.
277  * @param __GROUP__ NVIC priority group.
278  * @retval SET (__GROUP__ is valid)
279  * @retval RESET (__GROUP__ is invalid)
280  */
281 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
282  ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
283  ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
284  ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
285  ((__GROUP__) == NVIC_PRIORITYGROUP_4) || \
286  ((__GROUP__) == NVIC_PRIORITYGROUP_5) || \
287  ((__GROUP__) == NVIC_PRIORITYGROUP_6) || \
288  ((__GROUP__) == NVIC_PRIORITYGROUP_7))
289 
290 /**
291  * @brief Check if NVIC priority group is valid.
292  * @param __PRIORITY__ NVIC priority group.
293  * @retval SET (__PRIORITY__ is valid)
294  * @retval RESET (__PRIORITY__ is invalid)
295  */
296 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x80U)
297 
298 /**
299  * @brief Check if NVIC sub priority is valid.
300  * @param __PRIORITY__ NVIC sub priority.
301  * @retval SET (__PRIORITY__ is valid)
302  * @retval RESET (__PRIORITY__ is invalid)
303  */
304 #define IS_NVIC_SUB_PRIORITY(__PRIORITY__) ((__PRIORITY__) <= 0xFFU)
305 
306 /**
307  * @brief Check if NVIC deivce IRQ is valid.
308  * @param __IRQ__ NVIC device IRQ.
309  * @retval SET (__IRQ__ is valid)
310  * @retval RESET (__IRQ__ is invalid)
311  */
312 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) >= 0x00)
313 
314 #if (__MPU_PRESENT == 1U)
315 
316 /**
317  * @brief Check if MPU enable state is valid.
318  * @param __STATE__ Enable state.
319  * @retval SET (__STATE__ is valid)
320  * @retval RESET (__STATE__ is not invalid)
321  */
322 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
323  ((__STATE__) == MPU_REGION_DISABLE))
324 
325 /**
326  * @brief Check if MPU instruction access state is valid.
327  * @param __STATE__ MPU instruction access state.
328  * @retval SET (__STATE__ is valid)
329  * @retval RESET (__STATE__ is not invalid)
330  */
331 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
332  ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
333 
334 /**
335  * @brief Check if MPU access shareable state is valid.
336  * @param __STATE__ MPU access shareable state.
337  * @retval SET (__STATE__ is valid)
338  * @retval RESET (__STATE__ is not invalid)
339  */
340 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \
341  ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
342 
343 /**
344  * @brief Check if MPU access cacheable state is valid.
345  * @param __STATE__ MPU access cacheable state.
346  * @retval SET (__STATE__ is valid)
347  * @retval RESET (__STATE__ is not invalid)
348  */
349 #define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \
350  ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE))
351 
352 /**
353  * @brief Check if MPU access bufferable state is valid.
354  * @param __STATE__ MPU access bufferable state.
355  * @retval SET (__STATE__ is valid)
356  * @retval RESET (__STATE__ is not invalid)
357  */
358 #define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \
359  ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE))
360 
361 /**
362  * @brief Check if MPU Tex level is valid.
363  * @param __TYPE__ MPU Tex level.
364  * @retval SET (__TYPE__ is valid)
365  * @retval RESET (__TYPE__ is invalid)
366  */
367 #define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \
368  ((__TYPE__) == MPU_TEX_LEVEL1) || \
369  ((__TYPE__) == MPU_TEX_LEVEL2))
370 
371 /**
372  * @brief Check if MPU region permission attribute type is valid.
373  * @param __TYPE__ MPU region permission attribute type.
374  * @retval SET (__TYPE__ is valid)
375  * @retval RESET (__TYPE__ is invalid)
376  */
377 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \
378  ((__TYPE__) == MPU_REGION_PRIV_RW) || \
379  ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \
380  ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \
381  ((__TYPE__) == MPU_REGION_PRIV_RO) || \
382  ((__TYPE__) == MPU_REGION_PRIV_RO_URO))
383 
384 /**
385  * @brief Check if MPU region number is valid.
386  * @param __NUMBER__ MPU region number.
387  * @retval SET (__NUMBER__ is valid)
388  * @retval RESET (__NUMBER__ is invalid)
389  */
390 #define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
391  ((__NUMBER__) == MPU_REGION_NUMBER1) || \
392  ((__NUMBER__) == MPU_REGION_NUMBER2) || \
393  ((__NUMBER__) == MPU_REGION_NUMBER3) || \
394  ((__NUMBER__) == MPU_REGION_NUMBER4) || \
395  ((__NUMBER__) == MPU_REGION_NUMBER5) || \
396  ((__NUMBER__) == MPU_REGION_NUMBER6) || \
397  ((__NUMBER__) == MPU_REGION_NUMBER7))
398 
399 /**
400  * @brief Check if MPU region size is valid.
401  * @param __SIZE__ MPU region size.
402  * @retval SET (__SIZE__ is valid)
403  * @retval RESET (__SIZE__ is invalid)
404  */
405 #define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \
406  ((__SIZE__) == MPU_REGION_SIZE_64B) || \
407  ((__SIZE__) == MPU_REGION_SIZE_128B) || \
408  ((__SIZE__) == MPU_REGION_SIZE_256B) || \
409  ((__SIZE__) == MPU_REGION_SIZE_512B) || \
410  ((__SIZE__) == MPU_REGION_SIZE_1KB) || \
411  ((__SIZE__) == MPU_REGION_SIZE_2KB) || \
412  ((__SIZE__) == MPU_REGION_SIZE_4KB) || \
413  ((__SIZE__) == MPU_REGION_SIZE_8KB) || \
414  ((__SIZE__) == MPU_REGION_SIZE_16KB) || \
415  ((__SIZE__) == MPU_REGION_SIZE_32KB) || \
416  ((__SIZE__) == MPU_REGION_SIZE_64KB) || \
417  ((__SIZE__) == MPU_REGION_SIZE_128KB) || \
418  ((__SIZE__) == MPU_REGION_SIZE_256KB) || \
419  ((__SIZE__) == MPU_REGION_SIZE_512KB) || \
420  ((__SIZE__) == MPU_REGION_SIZE_1MB) || \
421  ((__SIZE__) == MPU_REGION_SIZE_2MB) || \
422  ((__SIZE__) == MPU_REGION_SIZE_4MB) || \
423  ((__SIZE__) == MPU_REGION_SIZE_8MB) || \
424  ((__SIZE__) == MPU_REGION_SIZE_16MB) || \
425  ((__SIZE__) == MPU_REGION_SIZE_32MB) || \
426  ((__SIZE__) == MPU_REGION_SIZE_64MB) || \
427  ((__SIZE__) == MPU_REGION_SIZE_128MB) || \
428  ((__SIZE__) == MPU_REGION_SIZE_256MB) || \
429  ((__SIZE__) == MPU_REGION_SIZE_512MB) || \
430  ((__SIZE__) == MPU_REGION_SIZE_1GB) || \
431  ((__SIZE__) == MPU_REGION_SIZE_2GB) || \
432  ((__SIZE__) == MPU_REGION_SIZE_4GB))
433 
434 
435 /**
436  * @brief Check if MPU sub region is valid.
437  * @param __SUBREGION__ MPU sub region.
438  * @retval SET (__SUBREGION__ is valid)
439  * @retval RESET (__SUBREGION__ is invalid)
440  */
441 #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)
442 #endif /* __MPU_PRESENT */
443 
444 /** @} */
445 
446 /** @} */
447 
448 /* Exported functions --------------------------------------------------------*/
449 /** @addtogroup HAL_CORTEX_DRIVER_FUNCTIONS Functions
450  * @{
451  */
452 
453 /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
454  * @brief Initialization and Configuration functions.
455  *
456 @verbatim
457  ==============================================================================
458  ##### Initialization and de-initialization functions #####
459  ==============================================================================
460  [..]
461  This section provides the CORTEX HAL driver functions allowing to configure Interrupts
462  Systick functionalities
463 
464 @endverbatim
465  * @{
466  */
467 
468 /**
469  ****************************************************************************************
470  * @brief Set the priority grouping field (pre-emption priority and subpriority)
471  * using the required unlock sequence.
472  *
473  * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
474  * The pending IRQ priority will be managed only by the subpriority.
475  *
476  * @param[in] priority_group: The priority grouping bits length.
477  * This parameter can be one of the following values:
478  * @arg @ref NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
479  * 8 bits for subpriority
480  * @arg @ref NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
481  * 7 bits for subpriority
482  * @arg @ref NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
483  * 6 bits for subpriority
484  * @arg @ref NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
485  * 5 bits for subpriority
486  * @arg @ref NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
487  * 4 bits for subpriority
488  * @arg @ref NVIC_PRIORITYGROUP_5 5 bits for pre-emption priority,
489  * 3 bits for subpriority
490  * @arg @ref NVIC_PRIORITYGROUP_6 6 bits for pre-emption priority,
491  * 2 bits for subpriority
492  * @arg @ref NVIC_PRIORITYGROUP_7 7 bits for pre-emption priority,
493  * 1 bit for subpriority
494  ****************************************************************************************
495  */
496 void hal_nvic_set_priority_grouping(uint32_t priority_group);
497 
498 /**
499  ****************************************************************************************
500  * @brief Set the priority of an interrupt.
501  *
502  * @param[in] IRQn: External interrupt number.
503  * This parameter can be an enumerator of IRQn_Type enumeration
504  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
505  * @param[in] preempt_priority: The pre-emption priority for the IRQn channel.
506  * This parameter can be a value between 0 and 127 as described in the table CORTEX_NVIC_Priority_Table.
507  * A lower priority value indicates a higher priority
508  * @param[in] sub_priority: The subpriority level for the IRQ channel.
509  * This parameter can be a value between 0 and 255 as described in the table CORTEX_NVIC_Priority_Table.
510  * A lower priority value indicates a higher priority.
511  ****************************************************************************************
512  */
513 void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority);
514 
515 /**
516  ****************************************************************************************
517  * @brief Enable a device specific interrupt in the NVIC interrupt controller.
518  *
519  * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
520  * function should be called before.
521  *
522  * @param[in] IRQn: External interrupt number.
523  * This parameter can be an enumerator of IRQn_Type enumeration
524  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
525  ****************************************************************************************
526  */
527 void hal_nvic_enable_irq(IRQn_Type IRQn);
528 
529 /**
530  ****************************************************************************************
531  * @brief Disable a device specific interrupt in the NVIC interrupt controller.
532  *
533  * @param[in] IRQn: External interrupt number.
534  * This parameter can be an enumerator of IRQn_Type enumeration
535  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
536  ****************************************************************************************
537  */
538 void hal_nvic_disable_irq(IRQn_Type IRQn);
539 
540 /**
541  ****************************************************************************************
542  * @brief Initiate a system reset request to reset the MCU.
543  ****************************************************************************************
544  */
546 
547 
548 /**
549  ****************************************************************************************
550  * @brief Initialize the System Timer and its interrupt, and start the System Tick Timer.
551  * Counter is in free running mode to generate periodic interrupts.
552  *
553  * @param[in] ticks_number: Specifies the number of ticks between two interrupts.
554  *
555  * @retval status
556  * - 0 Function succeeded.
557  * - 1 Function failed.
558  ****************************************************************************************
559  */
560 uint32_t hal_systick_config(uint32_t ticks_number);
561 
562 /** @} */
563 
564 /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
565  * @brief Cortex control functions.
566  *
567 @verbatim
568  ==============================================================================
569  ##### Peripheral Control functions #####
570  ==============================================================================
571  [..]
572  This subsection provides a set of functions allowing to control the CORTEX
573  (NVIC, SYSTICK, MPU) functionalities.
574 
575 
576 @endverbatim
577  * @{
578  */
579 
580 #if (__MPU_PRESENT == 1U)
581 /**
582  ****************************************************************************************
583  * @brief Initialize and configures the Region and the memory to be protected.
584  *
585  * @param[in] p_mpu_init: Pointer to a mpu_region_init_t structure that contains
586  * the initialization and configuration information.
587  ****************************************************************************************
588  */
590 #endif /* __MPU_PRESENT */
591 
592 /**
593  ****************************************************************************************
594  * @brief Get the priority grouping field from the NVIC Interrupt Controller.
595  *
596  * @return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
597  ****************************************************************************************
598  */
600 
601 /**
602  ****************************************************************************************
603  * @brief Get the priority of an interrupt.
604  *
605  * @param[in] IRQn: External interrupt number.
606  * This parameter can be an enumerator of IRQn_Type enumeration.
607  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
608  * @param[in] priority_group: The priority grouping bits length.
609  * This parameter can be one of the following values:
610  * @arg @ref NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
611  * 8 bits for subpriority
612  * @arg @ref NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
613  * 7 bits for subpriority
614  * @arg @ref NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
615  * 6 bits for subpriority
616  * @arg @ref NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
617  * 5 bits for subpriority
618  * @arg @ref NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
619  * 4 bits for subpriority
620  * @arg @ref NVIC_PRIORITYGROUP_5 5 bits for pre-emption priority,
621  * 3 bits for subpriority
622  * @arg @ref NVIC_PRIORITYGROUP_6 6 bits for pre-emption priority,
623  * 2 bits for subpriority
624  * @arg @ref NVIC_PRIORITYGROUP_7 7 bits for pre-emption priority,
625  * 1 bit for subpriority
626  * @param[in] p_preempt_priority: Pointer on the Preemptive priority value (starting from 0).
627  * @param[in] p_sub_priority: Pointer on the Subpriority value (starting from 0).
628  ****************************************************************************************
629  */
630 void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority);
631 
632 /**
633  ****************************************************************************************
634  * @brief Set Pending bit of an external interrupt.
635  *
636  * @param[in] IRQn: External interrupt number.
637  * This parameter can be an enumerator of IRQn_Type enumeration
638  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
639  ****************************************************************************************
640  */
641 void hal_nvic_set_pending_irq(IRQn_Type IRQn);
642 
643 /**
644  ****************************************************************************************
645  * @brief Get Pending Interrupt (reads the pending register in the NVIC
646  * and returns the pending bit for the specified interrupt).
647  *
648  * @param[in] IRQn: External interrupt number.
649  * This parameter can be an enumerator of IRQn_Type enumeration
650  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
651  *
652  * @return status
653  * - 0 Interrupt status is not pending.
654  * - 1 Interrupt status is pending.
655  ****************************************************************************************
656  */
657 uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn);
658 
659 /**
660  ****************************************************************************************
661  * @brief Clear the pending bit of an external interrupt.
662  *
663  * @param[in] IRQn: External interrupt number.
664  * This parameter can be an enumerator of IRQn_Type enumeration
665  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
666  ****************************************************************************************
667  */
668 void hal_nvic_clear_pending_irq(IRQn_Type IRQn);
669 
670 /**
671  ****************************************************************************************
672  * @brief Get active interrupt (reads the active register in NVIC and returns the active bit).
673  *
674  * @param[in] IRQn: External interrupt number.
675  * This parameter can be an enumerator of IRQn_Type enumeration
676  * (For the complete GR55xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (gr55xxxx.h))
677  *
678  * @return status
679  * - 0 Interrupt status is not pending.
680  * - 1 Interrupt status is pending.
681  ****************************************************************************************
682  */
683 uint32_t hal_nvic_get_active(IRQn_Type IRQn);
684 
685 /** @} */
686 
687 /* Private functions ---------------------------------------------------------*/
688 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
689  * @brief CORTEX private functions
690  * @{
691  */
692 
693 #if (__MPU_PRESENT == 1U)
694 
695 /**
696  ****************************************************************************************
697  * @brief Disables the MPU and clears the HFNMIENA bit (ARM recommendation)
698  ****************************************************************************************
699  */
700 void hal_mpu_disable(void);
701 
702 /**
703  ****************************************************************************************
704  * @brief Enable the MPU
705  *
706  * @param[in] mpu_control: Specifies the control mode of the MPU during hard fault,
707  * NMI, FAULTMASK and privileged access to the default memory.
708  * This parameter can be one of the following values:
709  * @arg @ref MPU_HFNMI_PRIVDEF_NONE
710  * @arg @ref MPU_HARDFAULT_NMI
711  * @arg @ref MPU_PRIVILEGED_DEFAULT
712  * @arg @ref MPU_HFNMI_PRIVDEF
713  ****************************************************************************************
714  */
715 void hal_mpu_enable(uint32_t mpu_control);
716 
717 #endif /* __MPU_PRESENT */
718 
719 /** @} */
720 
721 /** @} */
722 
723 #ifdef __cplusplus
724 }
725 #endif
726 
727 #endif /* __GR55xx_HAL_CORTEX_H__ */
728 
729 /** @} */
730 
731 /** @} */
732 
733 /** @} */
_mpu_region_init_t::type_tex_field
uint8_t type_tex_field
Definition: gr55xx_hal_cortex.h:93
hal_mpu_config_region
void hal_mpu_config_region(mpu_region_init_t *p_mpu_init)
Initialize and configures the Region and the memory to be protected.
hal_nvic_system_reset
void hal_nvic_system_reset(void)
Initiate a system reset request to reset the MCU.
hal_nvic_get_priority
void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority)
Get the priority of an interrupt.
_mpu_region_init_t::is_bufferable
uint8_t is_bufferable
Definition: gr55xx_hal_cortex.h:108
_mpu_region_init_t::is_shareable
uint8_t is_shareable
Definition: gr55xx_hal_cortex.h:102
_mpu_region_init_t::access_permission
uint8_t access_permission
Definition: gr55xx_hal_cortex.h:96
hal_mpu_disable
void hal_mpu_disable(void)
Disables the MPU and clears the HFNMIENA bit (ARM recommendation)
hal_mpu_enable
void hal_mpu_enable(uint32_t mpu_control)
Enable the MPU.
mpu_region_init_t
struct _mpu_region_init_t mpu_region_init_t
MPU Region initialization structure.
_mpu_region_init_t::disable_exec
uint8_t disable_exec
Definition: gr55xx_hal_cortex.h:99
_mpu_region_init_t
MPU Region initialization structure.
Definition: gr55xx_hal_cortex.h:78
_mpu_region_init_t::size
uint8_t size
Definition: gr55xx_hal_cortex.h:87
hal_nvic_enable_irq
void hal_nvic_enable_irq(IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
hal_nvic_set_pending_irq
void hal_nvic_set_pending_irq(IRQn_Type IRQn)
Set Pending bit of an external interrupt.
hal_nvic_set_priority
void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority)
Set the priority of an interrupt.
hal_nvic_get_priority_grouping
uint32_t hal_nvic_get_priority_grouping(void)
Get the priority grouping field from the NVIC Interrupt Controller.
_mpu_region_init_t::enable
uint8_t enable
Definition: gr55xx_hal_cortex.h:79
hal_nvic_get_active
uint32_t hal_nvic_get_active(IRQn_Type IRQn)
Get active interrupt (reads the active register in NVIC and returns the active bit).
_mpu_region_init_t::is_cacheable
uint8_t is_cacheable
Definition: gr55xx_hal_cortex.h:105
_mpu_region_init_t::number
uint8_t number
Definition: gr55xx_hal_cortex.h:82
hal_nvic_clear_pending_irq
void hal_nvic_clear_pending_irq(IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
hal_systick_config
uint32_t hal_systick_config(uint32_t ticks_number)
Initialize the System Timer and its interrupt, and start the System Tick Timer. Counter is in free ru...
hal_nvic_get_pending_irq
uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn)
Get Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the spe...
_mpu_region_init_t::base_address
uint32_t base_address
Definition: gr55xx_hal_cortex.h:85
_mpu_region_init_t::subregion_disable
uint8_t subregion_disable
Definition: gr55xx_hal_cortex.h:90
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_nvic_set_priority_grouping
void hal_nvic_set_priority_grouping(uint32_t priority_group)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequ...
hal_nvic_disable_irq
void hal_nvic_disable_irq(IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.