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52 #ifndef __GR55xx_LL_QSPI_H__
53 #define __GR55xx_LL_QSPI_H__
62 #if defined (QSPI0) || defined (QSPI1) || defined (QSPI2)
283 #define LL_QSPI_MAX_FIFO_DEPTH (32u)
285 #define LL_QSPI0_REG_RX_FIFO_DEPTH (16u)
286 #define LL_QSPI0_REG_TX_FIFO_DEPTH (16u)
287 #define LL_QSPI0_XIP_RX_FIFO_DEPTH (32u)
288 #define LL_QSPI0_XIP_TX_FIFO_DEPTH (16u)
290 #define LL_QSPI1_REG_RX_FIFO_DEPTH (32u)
291 #define LL_QSPI1_REG_TX_FIFO_DEPTH (32u)
292 #define LL_QSPI1_XIP_RX_FIFO_DEPTH (32u)
293 #define LL_QSPI1_XIP_TX_FIFO_DEPTH (32u)
295 #define LL_QSPI2_REG_RX_FIFO_DEPTH (16u)
296 #define LL_QSPI2_REG_TX_FIFO_DEPTH (32u)
297 #define LL_QSPI2_XIP_RX_FIFO_DEPTH (16u)
298 #define LL_QSPI2_XIP_TX_FIFO_DEPTH (16u)
305 #define LL_QSPI_SR_DCOL QSPI_STAT_DCOL
306 #define LL_QSPI_SR_TXE QSPI_STAT_TXE
307 #define LL_QSPI_SR_RFF QSPI_STAT_RFF
308 #define LL_QSPI_SR_RFNE QSPI_STAT_RFNE
309 #define LL_QSPI_SR_TFE QSPI_STAT_TFE
310 #define LL_QSPI_SR_TFNF QSPI_STAT_TFNF
311 #define LL_QSPI_SR_BUSY QSPI_STAT_BUSY
318 #define LL_QSPI_IM_SPITE QSPI_INTMASK_SPITEIM
319 #define LL_QSPI_IM_TXU QSPI_INTMASK_TXUIM
320 #define LL_QSPI_IM_XRXO QSPI_INTMASK_XRXOIM
321 #define LL_QSPI_IM_MST QSPI_INTMASK_MSTIM
322 #define LL_QSPI_IM_RXF QSPI_INTMASK_RXFIM
323 #define LL_QSPI_IM_RXO QSPI_INTMASK_RXOIM
324 #define LL_QSPI_IM_RXU QSPI_INTMASK_RXUIM
325 #define LL_QSPI_IM_TXO QSPI_INTMASK_TXOIM
326 #define LL_QSPI_IM_TXE QSPI_INTMASK_TXEIM
327 #define LL_QSPI_IM_ALL (LL_QSPI_IM_SPITE| \
337 #define LL_QSPI_IS_SPITE QSPI_INTMASK_SPITEIS
338 #define LL_QSPI_IS_TXU QSPI_INTMASK_TXUIS
339 #define LL_QSPI_IS_XRXO QSPI_INTSTAT_XRXOIS
340 #define LL_QSPI_IS_MST QSPI_INTSTAT_MSTIS
341 #define LL_QSPI_IS_RXF QSPI_INTSTAT_RXFIS
342 #define LL_QSPI_IS_RXO QSPI_INTSTAT_RXOIS
343 #define LL_QSPI_IS_RXU QSPI_INTSTAT_RXUIS
344 #define LL_QSPI_IS_TXO QSPI_INTSTAT_TXOIS
345 #define LL_QSPI_IS_TXE QSPI_INTSTAT_TXEIS
346 #define LL_QSPI_IS_ALL (LL_QSPI_IS_SPITE| \
356 #define LL_QSPI_RIS_SPITE QSPI_RAW_INTMASK_SPITEIR
357 #define LL_QSPI_RIS_TXU QSPI_RAW_INTMASK_TXUIIR
358 #define LL_QSPI_RIS_XRXO QSPI_RAW_INTSTAT_XRXOIR
359 #define LL_QSPI_RIS_MST QSPI_RAW_INTSTAT_MSTIR
360 #define LL_QSPI_RIS_RXF QSPI_RAW_INTSTAT_RXFIR
361 #define LL_QSPI_RIS_RXO QSPI_RAW_INTSTAT_RXOIR
362 #define LL_QSPI_RIS_RXU QSPI_RAW_INTSTAT_RXUIR
363 #define LL_QSPI_RIS_TXO QSPI_RAW_INTSTAT_TXOIR
364 #define LL_QSPI_RIS_TXE QSPI_RAW_INTSTAT_TXEIR
365 #define LL_QSPI_RIS_ALL (LL_QSPI_RIS_SPITE| \
380 #define LL_QSPI_FRF_SPI 0x00000000UL
381 #define LL_QSPI_FRF_DUALSPI (1UL << QSPI_CTRL0_SPIFRF_Pos)
382 #define LL_QSPI_FRF_QUADSPI (2UL << QSPI_CTRL0_SPIFRF_Pos)
388 #define LL_QSPI_DATASIZE_4BIT (3UL << QSPI_CTRL0_DFS32_Pos)
389 #define LL_QSPI_DATASIZE_5BIT (4UL << QSPI_CTRL0_DFS32_Pos)
390 #define LL_QSPI_DATASIZE_6BIT (5UL << QSPI_CTRL0_DFS32_Pos)
391 #define LL_QSPI_DATASIZE_7BIT (6UL << QSPI_CTRL0_DFS32_Pos)
392 #define LL_QSPI_DATASIZE_8BIT (7UL << QSPI_CTRL0_DFS32_Pos)
393 #define LL_QSPI_DATASIZE_9BIT (8UL << QSPI_CTRL0_DFS32_Pos)
394 #define LL_QSPI_DATASIZE_10BIT (9UL << QSPI_CTRL0_DFS32_Pos)
395 #define LL_QSPI_DATASIZE_11BIT (10UL << QSPI_CTRL0_DFS32_Pos)
396 #define LL_QSPI_DATASIZE_12BIT (11UL << QSPI_CTRL0_DFS32_Pos)
397 #define LL_QSPI_DATASIZE_13BIT (12UL << QSPI_CTRL0_DFS32_Pos)
398 #define LL_QSPI_DATASIZE_14BIT (13UL << QSPI_CTRL0_DFS32_Pos)
399 #define LL_QSPI_DATASIZE_15BIT (14UL << QSPI_CTRL0_DFS32_Pos)
400 #define LL_QSPI_DATASIZE_16BIT (15UL << QSPI_CTRL0_DFS32_Pos)
401 #define LL_QSPI_DATASIZE_17BIT (16UL << QSPI_CTRL0_DFS32_Pos)
402 #define LL_QSPI_DATASIZE_18BIT (17UL << QSPI_CTRL0_DFS32_Pos)
403 #define LL_QSPI_DATASIZE_19BIT (18UL << QSPI_CTRL0_DFS32_Pos)
404 #define LL_QSPI_DATASIZE_20BIT (19UL << QSPI_CTRL0_DFS32_Pos)
405 #define LL_QSPI_DATASIZE_21BIT (20UL << QSPI_CTRL0_DFS32_Pos)
406 #define LL_QSPI_DATASIZE_22BIT (21UL << QSPI_CTRL0_DFS32_Pos)
407 #define LL_QSPI_DATASIZE_23BIT (22UL << QSPI_CTRL0_DFS32_Pos)
408 #define LL_QSPI_DATASIZE_24BIT (23UL << QSPI_CTRL0_DFS32_Pos)
409 #define LL_QSPI_DATASIZE_25BIT (24UL << QSPI_CTRL0_DFS32_Pos)
410 #define LL_QSPI_DATASIZE_26BIT (25UL << QSPI_CTRL0_DFS32_Pos)
411 #define LL_QSPI_DATASIZE_27BIT (26UL << QSPI_CTRL0_DFS32_Pos)
412 #define LL_QSPI_DATASIZE_28BIT (27UL << QSPI_CTRL0_DFS32_Pos)
413 #define LL_QSPI_DATASIZE_29BIT (28UL << QSPI_CTRL0_DFS32_Pos)
414 #define LL_QSPI_DATASIZE_30BIT (29UL << QSPI_CTRL0_DFS32_Pos)
415 #define LL_QSPI_DATASIZE_31BIT (30UL << QSPI_CTRL0_DFS32_Pos)
416 #define LL_QSPI_DATASIZE_32BIT (31UL << QSPI_CTRL0_DFS32_Pos)
422 #define LL_QSPI_MW_CMDSIZE_1BIT 0x00000000UL
423 #define LL_QSPI_MW_CMDSIZE_2BIT (1UL << QSPI_CTRL0_CFS_Pos)
424 #define LL_QSPI_MW_CMDSIZE_3BIT (2UL << QSPI_CTRL0_CFS_Pos)
425 #define LL_QSPI_MW_CMDSIZE_4BIT (3UL << QSPI_CTRL0_CFS_Pos)
426 #define LL_QSPI_MW_CMDSIZE_5BIT (4UL << QSPI_CTRL0_CFS_Pos)
427 #define LL_QSPI_MW_CMDSIZE_6BIT (5UL << QSPI_CTRL0_CFS_Pos)
428 #define LL_QSPI_MW_CMDSIZE_7BIT (6UL << QSPI_CTRL0_CFS_Pos)
429 #define LL_QSPI_MW_CMDSIZE_8BIT (7UL << QSPI_CTRL0_CFS_Pos)
430 #define LL_QSPI_MW_CMDSIZE_9BIT (8UL << QSPI_CTRL0_CFS_Pos)
431 #define LL_QSPI_MW_CMDSIZE_10BIT (9UL << QSPI_CTRL0_CFS_Pos)
432 #define LL_QSPI_MW_CMDSIZE_11BIT (10UL << QSPI_CTRL0_CFS_Pos)
433 #define LL_QSPI_MW_CMDSIZE_12BIT (11UL << QSPI_CTRL0_CFS_Pos)
434 #define LL_QSPI_MW_CMDSIZE_13BIT (12UL << QSPI_CTRL0_CFS_Pos)
435 #define LL_QSPI_MW_CMDSIZE_14BIT (13UL << QSPI_CTRL0_CFS_Pos)
436 #define LL_QSPI_MW_CMDSIZE_15BIT (14UL << QSPI_CTRL0_CFS_Pos)
437 #define LL_QSPI_MW_CMDSIZE_16BIT (15UL << QSPI_CTRL0_CFS_Pos)
443 #define LL_QSPI_NORMAL_MODE 0x00000000UL
444 #define LL_QSPI_TEST_MODE (1UL << QSPI_CTRL0_SRL_Pos)
450 #define LL_QSPI_SLAVE_OUTDIS 0x00000000UL
451 #define LL_QSPI_SLAVE_OUTEN (1UL << QSPI_CTRL0_SLVOE_Pos)
457 #define LL_QSPI_FULL_DUPLEX 0x00000000UL
458 #define LL_QSPI_SIMPLEX_TX (1UL << QSPI_CTRL0_TMOD_Pos)
459 #define LL_QSPI_SIMPLEX_RX (2UL << QSPI_CTRL0_TMOD_Pos)
460 #define LL_QSPI_READ_EEPROM (3UL << QSPI_CTRL0_TMOD_Pos)
466 #define LL_QSPI_SCPHA_1EDGE 0x00000000UL
467 #define LL_QSPI_SCPHA_2EDGE (1UL << QSPI_CTRL0_SCPHA_Pos)
473 #define LL_QSPI_SCPOL_LOW 0x00000000UL
474 #define LL_QSPI_SCPOL_HIGH (1UL << QSPI_CTRL0_SCPOL_Pos)
480 #define LL_QSPI_PROTOCOL_MOTOROLA 0x00000000UL
481 #define LL_QSPI_PROTOCOL_TI (1UL << QSPI_CTRL0_FRF_Pos)
482 #define LL_QSPI_PROTOCOL_MICROWIRE (2UL << QSPI_CTRL0_FRF_Pos)
488 #define LL_QSPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL
489 #define LL_QSPI_MICROWIRE_HANDSHAKE_EN (1UL << QSPI_MWC_MHS_Pos)
491 #define LL_QSPI_MICROWIRE_RX 0x00000000UL
492 #define LL_QSPI_MICROWIRE_TX (1UL << QSPI_MWC_MDD_Pos)
494 #define LL_QSPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL
495 #define LL_QSPI_MICROWIRE_SEQUENTIAL (1UL << QSPI_MWC_MWMOD_Pos)
501 #define LL_QSPI_SLAVE1 QSPI_SE_SLAVE1
502 #define LL_QSPI_SLAVE0 QSPI_SE_SLAVE0
508 #define LL_QSPI_DMA_TX_DIS 0x00000000UL
509 #define LL_QSPI_DMA_TX_EN QSPI_DMAC_TDMAE
511 #define LL_QSPI_DMA_RX_DIS 0x00000000UL
512 #define LL_QSPI_DMA_RX_EN QSPI_DMAC_RDMAE
518 #define LL_QSPI_INSTSIZE_0BIT 0x00000000UL
519 #define LL_QSPI_INSTSIZE_4BIT (1UL << QSPI_SCTRL0_INSTL_Pos)
520 #define LL_QSPI_INSTSIZE_8BIT (2UL << QSPI_SCTRL0_INSTL_Pos)
521 #define LL_QSPI_INSTSIZE_16BIT (3UL << QSPI_SCTRL0_INSTL_Pos)
527 #define LL_QSPI_ADDRSIZE_0BIT 0x00000000UL
528 #define LL_QSPI_ADDRSIZE_4BIT (1UL << QSPI_SCTRL0_ADDRL_Pos)
529 #define LL_QSPI_ADDRSIZE_8BIT (2UL << QSPI_SCTRL0_ADDRL_Pos)
530 #define LL_QSPI_ADDRSIZE_12BIT (3UL << QSPI_SCTRL0_ADDRL_Pos)
531 #define LL_QSPI_ADDRSIZE_16BIT (4UL << QSPI_SCTRL0_ADDRL_Pos)
532 #define LL_QSPI_ADDRSIZE_20BIT (5UL << QSPI_SCTRL0_ADDRL_Pos)
533 #define LL_QSPI_ADDRSIZE_24BIT (6UL << QSPI_SCTRL0_ADDRL_Pos)
534 #define LL_QSPI_ADDRSIZE_28BIT (7UL << QSPI_SCTRL0_ADDRL_Pos)
535 #define LL_QSPI_ADDRSIZE_32BIT (8UL << QSPI_SCTRL0_ADDRL_Pos)
536 #define LL_QSPI_ADDRSIZE_36BIT (9UL << QSPI_SCTRL0_ADDRL_Pos)
537 #define LL_QSPI_ADDRSIZE_40BIT (10UL << QSPI_SCTRL0_ADDRL_Pos)
538 #define LL_QSPI_ADDRSIZE_44BIT (11UL << QSPI_SCTRL0_ADDRL_Pos)
539 #define LL_QSPI_ADDRSIZE_48BIT (12UL << QSPI_SCTRL0_ADDRL_Pos)
540 #define LL_QSPI_ADDRSIZE_52BIT (13UL << QSPI_SCTRL0_ADDRL_Pos)
541 #define LL_QSPI_ADDRSIZE_56BIT (14UL << QSPI_SCTRL0_ADDRL_Pos)
542 #define LL_QSPI_ADDRSIZE_60BIT (15UL << QSPI_SCTRL0_ADDRL_Pos)
548 #define LL_QSPI_RX_SAMPLE_POSITIVE_EDGE (0U)
549 #define LL_QSPI_RX_SAMPLE_NEGATIVE_EDGE (1U)
555 #define LL_QSPI_INST_ADDR_ALL_IN_SPI 0x00000000UL
556 #define LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << QSPI_SCTRL0_TRANSTYPE_Pos)
557 #define LL_QSPI_INST_ADDR_ALL_IN_SPIFRF (2UL << QSPI_SCTRL0_TRANSTYPE_Pos)
565 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 0u
566 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 1u
567 #define LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 2u
574 #define LL_QSPI_CONCURRENT_XIP_SLAVE0 QSPI_XIP_SLAVE0_EN
581 #define LL_QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_DATASIZE_8BIT
582 #define LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_DATASIZE_16BIT
583 #define LL_QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_DATASIZE_32BIT
590 #define LL_QSPI_CONCURRENT_XIP_MBL_2 0x0
591 #define LL_QSPI_CONCURRENT_XIP_MBL_4 0x1
592 #define LL_QSPI_CONCURRENT_XIP_MBL_8 0x2
593 #define LL_QSPI_CONCURRENT_XIP_MBL_16 0x3
600 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT 0x0
601 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT 0x1
602 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT 0x2
603 #define LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT 0x3
610 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT 0x0
611 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT 0x1
612 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT 0x2
613 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT 0x3
614 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT 0x4
615 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT 0x5
616 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT 0x6
617 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT 0x7
618 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT 0x8
619 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT 0x9
620 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT 0xA
621 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT 0xB
622 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT 0xC
623 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT 0xD
624 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT 0xE
625 #define LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT 0xF
632 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI 0x0
633 #define LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF 0x1
634 #define LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF 0x2
641 #define LL_QSPI_CONCURRENT_XIP_FRF_RSVD 0x0
642 #define LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI 0x1
643 #define LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI 0x2
644 #define LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI 0x3
650 #define LL_QSPI_CLK_STRETCH_ENABLE 1u
651 #define LL_QSPI_CLK_STRETCH_DISABLE 0u
657 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE 1u
658 #define LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE 0u
664 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE 1u
665 #define LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE 0u
671 #define LL_QSPI_CONCURRENT_XIP_INST_ENABLE 1u
672 #define LL_QSPI_CONCURRENT_XIP_INST_DISABLE 0u
678 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE 1u
679 #define LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE 0u
685 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE 1u
686 #define LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE 0u
692 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS 0u
693 #define LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS 1u
704 #define LL_QSPI_DEFAULT_CONFIG \
706 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
707 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
708 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
709 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
711 .data_size = LL_QSPI_DATASIZE_8BIT, \
712 .clock_polarity = LL_QSPI_SCPOL_LOW, \
713 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
714 .baud_rate = SystemCoreClock / 1000000, \
715 .rx_sample_delay = 0, \
720 #define LL_CONC_QSPI_DEFAULT_CONFIG \
722 .baud_rate = SystemCoreClock / 1000000, \
723 .clock_polarity = LL_QSPI_SCPOL_LOW, \
724 .clock_phase = LL_QSPI_SCPHA_1EDGE, \
725 .data_size = LL_QSPI_DATASIZE_8BIT, \
726 .clock_stretch_en = LL_QSPI_CLK_STRETCH_DISABLE, \
727 .transfer_direction = LL_QSPI_SIMPLEX_RX, \
728 .instruction_size = LL_QSPI_INSTSIZE_8BIT, \
729 .address_size = LL_QSPI_ADDRSIZE_24BIT, \
730 .inst_addr_transfer_format = LL_QSPI_INST_ADDR_ALL_IN_SPI, \
732 .rx_sample_delay = 0, \
734 .tx_start_fifo_threshold = 0, \
735 .tx_fifo_threshold = 0, \
736 .rx_fifo_threshold = 0, \
737 .dma_tx_fifo_level = 0, \
738 .dma_rx_fifo_level = 0, \
740 .x_prefetch_en = LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE, \
741 .x_continous_xfer_en = LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE, \
742 .x_continous_xfer_toc = 0x00, \
743 .x_dfs_hardcode_en = LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE, \
744 .x_mode_bits_en = LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE, \
745 .x_mode_bits_length = LL_QSPI_CONCURRENT_XIP_MBL_8, \
746 .x_mode_bits_data = 0x00, \
747 .x_instruction_en = LL_QSPI_CONCURRENT_XIP_INST_DISABLE, \
748 .x_instruction_size = LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT, \
749 .x_instruction = 0x00, \
750 .x_address_size = LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT,\
751 .x_inst_addr_transfer_format = LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF, \
752 .x_dummy_cycles = 0x00, \
753 .x_data_frame_format = LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI, \
776 #define LL_QSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
784 #define LL_QSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
814 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
830 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN);
846 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SSTEN) == (QSPI_CTRL0_SSTEN));
866 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF, frf);
885 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SPIFRF));
930 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_DFS32, size);
974 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DFS32));
1007 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_CFS, size);
1039 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_CFS));
1054 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1069 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL);
1084 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SRL) == (QSPI_CTRL0_SRL));
1099 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1114 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE);
1129 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SLVOE) != (QSPI_CTRL0_SLVOE));
1149 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_TMOD, transfer_direction);
1168 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_TMOD));
1188 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPOL, clock_polarity);
1205 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPOL));
1225 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_SCPHA, clock_phase);
1242 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_SCPHA));
1262 MODIFY_REG(QSPIx->CTRL0, QSPI_CTRL0_FRF, standard);
1280 return (uint32_t)(READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_FRF));
1299 MODIFY_REG(QSPIx->CTRL1, QSPI_CTRL1_NDF, size);
1302 #define ll_qspi_set_xfer_size ll_qspi_set_receive_size
1319 return (uint32_t)(READ_BITS(QSPIx->CTRL1, QSPI_CTRL1_NDF));
1334 SET_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1350 CLEAR_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN);
1365 return (READ_BITS(QSPIx->QSPI_EN, QSPI_SSI_EN) == (QSPI_SSI_EN));
1380 SET_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1395 CLEAR_BITS(QSPIx->MWC, QSPI_MWC_MHS);
1410 return (READ_BITS(QSPIx->MWC, QSPI_MWC_MHS) == (QSPI_MWC_MHS));
1429 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MDD, transfer_direction);
1447 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MDD));
1466 MODIFY_REG(QSPIx->MWC, QSPI_MWC_MWMOD, transfer_mode);
1484 return (uint32_t)(READ_BITS(QSPIx->MWC, QSPI_MWC_MWMOD));
1503 SET_BITS(QSPIx->SE, ss);
1522 CLEAR_BITS(QSPIx->SE, ss);
1541 return (READ_BITS(QSPIx->SE, ss) == ss);
1558 WRITE_REG(QSPIx->BAUD, baud_rate & QSPI_BAUD_SCKDIV);
1573 return (uint32_t)(READ_BITS(QSPIx->BAUD, QSPI_BAUD_SCKDIV));
1589 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTHR_TFT, threshold << QSPI_TXFTHR_TFT_Pos);
1604 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTHR_TFT) >> QSPI_TXFTHR_TFT_Pos);
1620 MODIFY_REG(QSPIx->TX_FTL, QSPI_TXFTL_TFT, threshold << QSPI_TXFTL_TFT_Pos);
1635 return (uint32_t)(READ_BITS(QSPIx->TX_FTL, QSPI_TXFTL_TFT) >> QSPI_TXFTL_TFT_Pos);
1651 WRITE_REG(QSPIx->RX_FTL, threshold);
1666 return (uint32_t)(READ_BITS(QSPIx->RX_FTL, QSPI_RXFTL_RFT));
1681 return (uint32_t)(READ_BITS(QSPIx->TX_FL, QSPI_TXFL_TXTFL));
1696 return (uint32_t)(READ_BITS(QSPIx->RX_FL, QSPI_RXFL_RXTFL));
1711 return (uint32_t)(READ_BITS(QSPIx->ID, QSPI_IDCODE_ID));
1726 return (uint32_t)(READ_BITS(QSPIx->VERSION_ID, QSPI_COMP_VERSION));
1758 SET_BITS(QSPIx->INTMASK, mask);
1784 CLEAR_BITS(QSPIx->INTMASK, mask);
1809 return (READ_BITS(QSPIx->INTMASK, mask) == mask);
1837 return (uint32_t)(READ_REG(QSPIx->STAT));
1866 return (READ_BITS(QSPIx->STAT, flag) == (flag));
1890 return (uint32_t)(READ_REG(QSPIx->INTSTAT));
1920 return (READ_BITS(QSPIx->INTSTAT, flag) == flag);
1944 return (uint32_t)(READ_REG(QSPIx->RAW_INTSTAT));
1960 __IOM uint32_t tmpreg;
1961 tmpreg = QSPIx->TXOIC;
1978 __IOM uint32_t tmpreg;
1979 tmpreg = QSPIx->RXOIC;
1996 __IOM uint32_t tmpreg;
1997 tmpreg = QSPIx->RXUIC;
2014 __IOM uint32_t tmpreg;
2015 tmpreg = QSPIx->MSTIC;
2032 __IOM uint32_t tmpreg;
2033 tmpreg = QSPIx->XIP_RXOICR;
2050 __IOM uint32_t tmpreg;
2051 tmpreg = QSPIx->INTCLR;
2073 SET_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2088 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE);
2103 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_TDMAE) == (QSPI_DMAC_TDMAE));
2118 SET_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2133 CLEAR_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE);
2148 return (READ_BITS(QSPIx->DMAC, QSPI_DMAC_RDMAE) == (QSPI_DMAC_RDMAE));
2164 WRITE_REG(QSPIx->DMA_TDL, threshold);
2179 return (uint32_t)(READ_BITS(QSPIx->DMA_TDL, QSPI_DMATDL_DMATDL));
2195 WRITE_REG(QSPIx->DMA_RDL, threshold);
2210 return (uint32_t)(READ_BITS(QSPIx->DMA_RDL, QSPI_DMARDL_DMARDL));
2232 *((__IOM uint8_t *)&QSPIx->DATA) = tx_data;
2248 *((__IOM uint16_t *)&QSPIx->DATA) = tx_data;
2264 *((__IOM uint32_t *)&QSPIx->DATA) = tx_data;
2279 return (uint8_t)(READ_REG(QSPIx->DATA));
2294 return (uint16_t)(READ_REG(QSPIx->DATA));
2309 return (uint32_t)(READ_REG(QSPIx->DATA));
2326 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE, edge << QSPI_RX_SAMPLE_EDGE_Pos);
2342 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLE_EDGE) >> QSPI_RX_SAMPLE_EDGE_Pos);
2359 MODIFY_REG(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY, delay);
2375 return (uint32_t)(READ_BITS(QSPIx->RX_SAMPLE_DLY, QSPI_RX_SAMPLEDLY));
2391 SET_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2407 CLEAR_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN);
2423 return (READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_CLK_STRETCH_EN) == (QSPI_SCTRL0_CLK_STRETCH_EN));
2440 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES, wait_cycles << QSPI_SCTRL0_WAITCYCLES_Pos);
2456 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_WAITCYCLES) >> QSPI_SCTRL0_WAITCYCLES_Pos);
2477 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL, size);
2497 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_INSTL));
2530 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL, size);
2562 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_ADDRL));
2582 MODIFY_REG(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE, format);
2601 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL0, QSPI_SCTRL0_TRANSTYPE));
2619 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2635 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN);
2651 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_MD_BIT_EN) == (QSPI_XCTRL_MD_BIT_EN));
2671 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL, mbl << QSPI_XCTRL_XIP_MBL_Pos);
2690 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_MBL) >> QSPI_XCTRL_XIP_MBL_Pos);
2707 MODIFY_REG(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS, mode << QSPI_XIP_MODE_BITS_Pos);
2723 return (uint32_t)(READ_BITS(QSPIx->XIP_MODE_BITS, QSPI_XIP_MODE_BITS) >> QSPI_XIP_MODE_BITS_Pos);
2740 MODIFY_REG(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST, inst << QSPI_XIP_INCR_INST_Pos);
2756 return (uint32_t)(READ_BITS(QSPIx->XIP_INCR_INST, QSPI_XIP_INCR_INST) >> QSPI_XIP_INCR_INST_Pos);
2773 MODIFY_REG(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST, inst << QSPI_XIP_WRAP_INST_Pos);
2789 return (uint32_t)(READ_BITS(QSPIx->XIP_WRAP_INST, QSPI_XIP_WRAP_INST) >> QSPI_XIP_WRAP_INST_Pos);
2806 SET_BITS(QSPIx->XIP_SER, ss);
2823 CLEAR_BITS(QSPIx->XIP_SER, ss);
2840 return (READ_BITS(QSPIx->XIP_SER, ss) == ss);
2857 MODIFY_REG(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT, xtoc << QSPI_XIP_TOCNT_Pos);
2873 return (uint32_t)(READ_BITS(QSPIx->XIP_CNT_TIME_OUT, QSPI_XIP_TOCNT) >> QSPI_XIP_TOCNT_Pos);
2889 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2905 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN);
2921 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_XIP_PREFETCH_EN) == (QSPI_XCTRL_XIP_PREFETCH_EN));
2937 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2953 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN);
2969 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_CONT_XFER_EN) == (QSPI_XCTRL_CONT_XFER_EN));
2985 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
3001 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN);
3017 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INST_EN) == (QSPI_XCTRL_INST_EN));
3037 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL, inst_size << QSPI_XCTRL_INSTL_Pos);
3056 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_INSTL) >> QSPI_XCTRL_INSTL_Pos);
3073 SET_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3089 CLEAR_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC);
3105 return (READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_DFS_HC) == (QSPI_XCTRL_DFS_HC));
3122 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES, wait_cycles << QSPI_XCTRL_WAITCYCLES_Pos);
3138 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_WAITCYCLES) >> QSPI_XCTRL_WAITCYCLES_Pos);
3171 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL, addr_size << QSPI_XCTRL_ADDRL_Pos);
3202 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_ADDRL) >> QSPI_XCTRL_ADDRL_Pos);
3222 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE, format << QSPI_XCTRL_TRANSTYPE_Pos);
3240 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_TRANSTYPE) >> QSPI_XCTRL_TRANSTYPE_Pos);
3261 MODIFY_REG(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF, format << QSPI_XCTRL_FRF_Pos);
3281 return (uint32_t)(READ_BITS(QSPIx->XIP_CTRL, QSPI_XCTRL_FRF) >> QSPI_XCTRL_FRF_Pos);
3346 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3348 MODIFY_REG(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which), mode << which);
3370 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_ENDIAN_MODE_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_ENDIAN_MODE_Pos : MCU_SUB_QSPI_M_XIP_M2_ENDIAN_MODE_Pos) ;
3372 return (READ_BITS(MCU_SUB->QSPI_M_XIP, MCU_SUB_QSPI_M_XIP_ENDIAN_ORDER & (0x3 << which)) >> which );
3390 SET_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3406 CLEAR_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN);
3421 return (READ_BITS(QSPIx->CTRL0, QSPI_CTRL0_DWS_EN) == (QSPI_CTRL0_DWS_EN));
3437 __IOM uint32_t tmpreg;
3438 tmpreg = QSPIx->SPI_TEIC;
3456 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS, max_ws << QSPI_SCTRL1_MAX_WS_Pos);
3472 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_MAX_WS) >> QSPI_SCTRL1_MAX_WS_Pos);
3489 MODIFY_REG(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS, dyn_ws << QSPI_SCTRL1_DYN_WS_Pos);
3506 return (uint32_t)(READ_BITS(QSPIx->SPI_CTRL1, QSPI_SCTRL1_DYN_WS) >> QSPI_SCTRL1_DYN_WS_Pos);
3523 MODIFY_REG(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST, inst << QSPI_XIP_WR_INCR_INST_Pos);
3539 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_INCR_INST, QSPI_XIP_WR_INCR_INST) >> QSPI_XIP_WR_INCR_INST_Pos);
3556 MODIFY_REG(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST, inst << QSPI_XIP_WR_WRAP_INST_Pos);
3572 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_WRAP_INST, QSPI_XIP_WR_WRAP_INST) >> QSPI_XIP_WR_WRAP_INST_Pos);
3590 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES, wait_cycles << QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3606 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_WAITCYCLES) >> QSPI_XIP_WR_CTRL_WAITCYCLES_Pos);
3627 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL, inst_size << QSPI_XIP_WR_CTRL_INSTL_Pos);
3646 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_INSTL) >> QSPI_XIP_WR_CTRL_INSTL_Pos);
3673 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL, addr_size << QSPI_XIP_WR_CTRL_ADDRL_Pos);
3697 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_ADDRL) >> QSPI_XIP_WR_CTRL_ADDRL_Pos);
3717 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE, format << QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3735 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_TRANSTYPE) >> QSPI_XIP_WR_CTRL_TRANSTYPE_Pos);
3756 MODIFY_REG(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF, format << QSPI_XIP_WR_CTRL_FRF_Pos);
3776 return (uint32_t)(READ_BITS(QSPIx->XIP_WR_CTRL, QSPI_XIP_WR_CTRL_FRF) >> QSPI_XIP_WR_CTRL_FRF_Pos);
3795 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 0);
3812 MODIFY_REG(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN, 1);
3829 return (READ_BITS(MCU_SUB->QSPI_M_HRESP_DBG, MCU_SUB_QSPI_M_HRESP_ERR_MASK_EN) == (0));
3848 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3851 MODIFY_REG(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which, (baudrate*delay) << which);
3869 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_SETUP_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_SETUP_DLY_Pos : MCU_SUB_QSPI_M2_CS_SETUP_DLY_Pos) ;
3876 return (READ_BITS(MCU_SUB->QSPI_M_CS_SETUP_DLY, 0xFF << which) >> which)/baudrate;
3895 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ((QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3898 MODIFY_REG(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which, (baudrate*delay) << which);
3916 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M0_CS_RELEASE_DLY_Pos : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M1_CS_RELEASE_DLY_Pos : MCU_SUB_QSPI_M2_CS_RELEASE_DLY_Pos) ;
3923 return (READ_BITS(MCU_SUB->QSPI_M_CS_RELEASE_DLY, 0xFF << which) >> which)/baudrate;
3940 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3941 SET_BITS(MCU_SUB->QSPI_M_XIP, which);
3958 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3959 CLEAR_BITS(MCU_SUB->QSPI_M_XIP, which);
3976 uint32_t which = (QSPIx == QSPI0) ? MCU_SUB_QSPI_M_XIP_M0_DYNAMIC_LE_EN : ( (QSPIx == QSPI1) ? MCU_SUB_QSPI_M_XIP_M1_DYNAMIC_LE_EN : MCU_SUB_QSPI_M_XIP_M2_DYNAMIC_LE_EN) ;
3977 return (READ_BITS(MCU_SUB->QSPI_M_XIP, which) == (which));
3988 if(QSPI0 == QSPIx) {
3990 }
else if(QSPI1 == QSPIx) {
4005 if(QSPI0 == QSPIx) {
4007 }
else if(QSPI1 == QSPIx) {
4022 if(QSPI0 == QSPIx) {
4024 }
else if(QSPI1 == QSPIx) {
4039 if(QSPI0 == QSPIx) {
4041 }
else if(QSPI1 == QSPIx) {
4056 if(QSPI0 == QSPIx) {
4057 return QSPI0_XIP_BASE;
4058 }
else if(QSPI1 == QSPIx) {
4059 return QSPI1_XIP_BASE;
4061 return QSPI2_XIP_BASE;
#define LL_QSPI0_XIP_RX_FIFO_DEPTH
__STATIC_INLINE void ll_qspi_set_cs_release_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Release Delay for QSPI.
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_prefetch(qspi_regs_t *QSPIx)
Disable the pre-fetch feature for concurrent xip mode.
__STATIC_INLINE uint32_t ll_qspi_get_receive_size(qspi_regs_t *QSPIx)
Get the number of data frames to be continuously received.
__STATIC_INLINE void ll_qspi_transmit_data32(qspi_regs_t *QSPIx, uint32_t tx_data)
Write 32-Bits in the data register.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_slave_out(qspi_regs_t *QSPIx)
Check if slave output is enabled.
__STATIC_INLINE void ll_qspi_enable_micro_handshake(qspi_regs_t *QSPIx)
Enable Handshake in Microwire mode.
__STATIC_INLINE uint32_t ll_qspi_is_active_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check active flag.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Enable the hardcoded DFS feature for concurrent xip mode.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip mode.
error_status_t ll_qspi_memorymapped(qspi_regs_t *QSPIx, ll_qspi_memorymapped_init_t *p_qspi_mmap_init)
Configure the qspi to memorymapped.
__STATIC_INLINE uint32_t ll_qspi_get_standard(qspi_regs_t *QSPIx)
Get serial protocol used.
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_delay(qspi_regs_t *QSPIx)
Get Rx sample delay.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_prefetch(qspi_regs_t *QSPIx)
check if the pre-fetch feature is enabled or not for concurrent xip mode
__STATIC_INLINE void ll_qspi_concurrent_set_xip_toc(qspi_regs_t *QSPIx, uint32_t xtoc)
Set time out count for continuous transfer for xip mode.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_clk_stretch(qspi_regs_t *QSPIx)
Check if the clock stretch feature is enabled or not for Enhanced SPI.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_data(qspi_regs_t *QSPIx, uint32_t mode)
set the mode phase (sent after address phase) value in xip mode
__STATIC_INLINE void ll_qspi_set_standard(qspi_regs_t *QSPIx, uint32_t standard)
Set serial protocol used.
#define LL_QSPI1_XIP_TX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip write mode.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip mode.
__STATIC_INLINE void ll_qspi_transmit_data16(qspi_regs_t *QSPIx, uint16_t tx_data)
Write 16-Bits in the data register.
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable the slave in xip mode.
__STATIC_INLINE void ll_qspi_disable_hresp_err_debug_mode(void)
Disable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens.
__STATIC_INLINE void ll_qspi_enable_dws(qspi_regs_t *QSPIx)
Enable dynamic of wait states for QSPI peripheral.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip mode.
uint32_t instruction_size
__STATIC_INLINE uint32_t ll_qspi_receive_data32(qspi_regs_t *QSPIx)
Read 32-Bits in the data register.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_it(qspi_regs_t *QSPIx, uint32_t mask)
Check if interrupt is enabled.
__STATIC_INLINE void ll_qspi_enable_ss_toggle(qspi_regs_t *QSPIx)
Enable slave select toggle.
__STATIC_INLINE void ll_qspi_disable_test_mode(qspi_regs_t *QSPIx)
Disable SPI test mode.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_instruction_size(qspi_regs_t *QSPIx)
Get the instruction size for concurrent xip write mode.
#define LL_QSPI0_REG_RX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_get_rx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t ll_qspi_is_enabled(qspi_regs_t *QSPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void ll_qspi_set_receive_size(qspi_regs_t *QSPIx, uint32_t size)
Set the number of data frames to be continuously received.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip write mode.
@ LL_QSPI_MEMORYMAPPED_MODE_READ_WRITE
__STATIC_INLINE uint32_t ll_qspi_get_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
get the value for dynamic wait state
__STATIC_INLINE void ll_qspi_enable(qspi_regs_t *QSPIx)
Enable SPI peripheral.
__STATIC_INLINE uint32_t ll_qspi_get_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode.
uint32_t ll_qspi_is_enabled_xip(qspi_regs_t *QSPIx)
Check if qspi xip mode is enabled.
#define LL_QSPI2_REG_RX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_get_clock_polarity(qspi_regs_t *QSPIx)
Get clock polarity.
__STATIC_INLINE void ll_qspi_set_cs_setup_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set CS Setup Delay for QSPI.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction in xip mode
__STATIC_INLINE void ll_qspi_enable_hresp_err_debug_mode(void)
Enable the AHB Response Error Debug for all QSPI Modules. if violation, hardfault happens.
uint32_t inst_addr_transfer_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip write mode.
__STATIC_INLINE uint32_t ll_qspi_get_xip_base_address(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
__STATIC_INLINE uint32_t ll_qspi_get_max_wait_cycles(qspi_regs_t *QSPIx)
get the max wait cycles per transaction for dynamic wait state
@ LL_QSPI_MEMORYMAPPED_MODE_READ_ONLY
uint32_t x_wr_dummy_cycles
__STATIC_INLINE void ll_qspi_enable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable slave select.
__STATIC_INLINE void ll_qspi_set_tx_start_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TX transfer start.
__STATIC_INLINE void ll_qspi_clear_flag_all(qspi_regs_t *QSPIx)
Clear all error(txo,rxu,rxo,mst) flag.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip write mode.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Check if the hardcoded DFS feature is enabled or not for concurrent xip mode.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_micro_handshake(qspi_regs_t *QSPIx)
Check if Handshake in Microwire mode is enabled.
uint32_t x_wr_address_size
__STATIC_INLINE uint32_t ll_qspi_get_status(qspi_regs_t *QSPIx)
Get SPI status.
void ll_qspi_disable_xip(qspi_regs_t *QSPIx)
Disable qspi xip mode.
__STATIC_INLINE uint32_t ll_qspi_get_baud_rate_prescaler(qspi_regs_t *QSPIx)
Get baud rate prescaler.
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_dfs_hardcode(qspi_regs_t *QSPIx)
Disable the hardcoded DFS feature for concurrent xip mode.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip write mode.
__STATIC_INLINE void ll_qspi_set_dma_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
__STATIC_INLINE void ll_qspi_enable_dma_req_rx(qspi_regs_t *QSPIx)
Enable DMA Rx.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_mode_bits(qspi_regs_t *QSPIx)
Check if the mode bits phase is enabled or not for concurrent xip mode.
__STATIC_INLINE void ll_qspi_disable_salve_out(qspi_regs_t *QSPIx)
Disable slave output.
__STATIC_INLINE void ll_qspi_set_frame_format(qspi_regs_t *QSPIx, uint32_t frf)
Set data frame format for transmitting/receiving the data.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip mode.
uint32_t x_dfs_hardcode_en
__STATIC_INLINE void ll_qspi_set_data_size(qspi_regs_t *QSPIx, uint32_t size)
Set frame data size.
__STATIC_INLINE uint32_t ll_qspi_get_cs_release_delay(qspi_regs_t *QSPIx)
Get CS Release Delay for QSPI.
__STATIC_INLINE uint32_t ll_qspi_get_clock_phase(qspi_regs_t *QSPIx)
Get clock phase.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction for write in xip mode
__STATIC_INLINE void ll_qspi_set_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set the wait(also called dummy) cycles for concurrent xip mode.
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_instruction(qspi_regs_t *QSPIx)
Disable the instruction phase for concurrent xip mode.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction for write in xip mode
QSPI init structures definition.
#define LL_QSPI1_REG_RX_FIFO_DEPTH
__STATIC_INLINE void ll_qspi_clear_flag_xrxo(qspi_regs_t *QSPIx)
Clear XIP receive FIFO overflow flag.
__STATIC_INLINE void ll_qspi_set_wait_cycles(qspi_regs_t *QSPIx, uint32_t wait_cycles)
Set number of wait cycles in Dual/Quad SPI mode.
__STATIC_INLINE void ll_qspi_set_dynamic_wait_state(qspi_regs_t *QSPIx, uint32_t dyn_ws)
set the value for dynamic wait state
__STATIC_INLINE void ll_qspi_disable_micro_handshake(qspi_regs_t *QSPIx)
Disable Handshake in Microwire mode.
__STATIC_INLINE void ll_qspi_set_add_inst_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set Dual/Quad SPI mode address and instruction transfer format.
__STATIC_INLINE void ll_qspi_set_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void ll_qspi_disable_clk_stretch(qspi_regs_t *QSPIx)
Disable the clock stretch feature for Enhanced SPI.
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an TXE event.
__STATIC_INLINE void ll_qspi_clear_flag_mst(qspi_regs_t *QSPIx)
Clear multi-master error flag.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wrap_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-wrap transfer instruction in xip mode
__STATIC_INLINE uint32_t ll_qspi_get_cs_setup_delay(qspi_regs_t *QSPIx)
Get CS Setup Delay for QSPI.
__STATIC_INLINE uint32_t ll_qspi_get_frame_format(qspi_regs_t *QSPIx)
Get data frame format for transmitting/receiving the data.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_rx(qspi_regs_t *QSPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_mode_bits(qspi_regs_t *QSPIx)
Enable the mode bits phase for concurrent xip mode.
uint32_t x_wr_data_frame_format
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Disable the continuous transfer feature for concurrent xip mode.
__STATIC_INLINE uint32_t ll_qspi_get_address_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address length in bits.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_instruction(qspi_regs_t *QSPIx)
Enable the instruction phase for concurrent xip mode.
uint32_t x_data_frame_format
__STATIC_INLINE void ll_qspi_concurrent_set_xip_address_size(qspi_regs_t *QSPIx, uint32_t addr_size)
Set the address size for concurrent xip mode.
#define LL_QSPI2_REG_TX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_get_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode address and instruction transfer format.
__STATIC_INLINE void ll_qspi_enable_it(qspi_regs_t *QSPIx, uint32_t mask)
Enable interrupt.
__STATIC_INLINE void ll_qspi_enable_slave_out(qspi_regs_t *QSPIx)
Enable slave output.
__STATIC_INLINE void ll_qspi_disable_dma_req_tx(qspi_regs_t *QSPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t ll_qspi_get_dma_rx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_addr_inst_transfer_format(qspi_regs_t *QSPIx)
Get the transfer format of inst & address for concurrent xip write mode.
__STATIC_INLINE uint8_t ll_qspi_receive_data8(qspi_regs_t *QSPIx)
Read 8-Bits in the data register.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_inst_addr_transfer_format(qspi_regs_t *QSPIx, uint32_t format)
Set the transfer format of inst & address for concurrent xip write mode.
__STATIC_INLINE uint32_t ll_qspi_get_id_code(qspi_regs_t *QSPIx)
Get ID code.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_continuous_xfer(qspi_regs_t *QSPIx)
Check if the continuous transfer feature is enabled or not for concurrent xip mode.
uint32_t x_mode_bits_data
__STATIC_INLINE void ll_qspi_disable_xip_dynamic_le(qspi_regs_t *QSPIx)
Disable qspi xip dynamic little-endian mode.
__STATIC_INLINE void ll_qspi_disable_dma_req_rx(qspi_regs_t *QSPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dws(qspi_regs_t *QSPIx)
Check if dynamic of wait states for QSPI peripheral is enabled.
__STATIC_INLINE void ll_qspi_enable_dma_req_tx(qspi_regs_t *QSPIx)
Enable DMA Tx.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_mode_bits_length(qspi_regs_t *QSPIx, uint32_t mbl)
Set the length of mode bits phase for concurrent xip mode.
__STATIC_INLINE void ll_qspi_enable_xip_dynamic_le(qspi_regs_t *QSPIx)
Enable qspi xip dynamic little-endian mode.
uint32_t x_continous_xfer_toc
__STATIC_INLINE uint32_t ll_qspi_get_xip_endian_mode(qspi_regs_t *QSPIx)
Get xip's endian mode.
uint32_t x_wr_instruction_size
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_address_size(qspi_regs_t *QSPIx)
Get the address size for concurrent xip mode.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Enable the slave in xip mode.
__STATIC_INLINE uint32_t ll_qspi_get_raw_if_flag(qspi_regs_t *QSPIx)
Get SPI raw interrupt flags.
__STATIC_INLINE void ll_qspi_set_tx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip write mode.
#define LL_QSPI0_XIP_TX_FIFO_DEPTH
__STATIC_INLINE void ll_qspi_concurrent_set_xip_frame_format(qspi_regs_t *QSPIx, uint32_t format)
Set the QSPI frame format for concurrent xip mode.
__STATIC_INLINE void ll_qspi_disable_ss(qspi_regs_t *QSPIx, uint32_t ss)
Disable slave select.
struct _ll_qspi_memorymapped_read_init_t ll_qspi_memorymapped_read_init_t
__STATIC_INLINE uint32_t ll_qspi_get_version(qspi_regs_t *QSPIx)
Get IP version.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction for write in xip mode
__STATIC_INLINE void ll_qspi_set_clock_polarity(qspi_regs_t *QSPIx, uint32_t clock_polarity)
Set clock polarity.
uint32_t x_instruction_size
__STATIC_INLINE void ll_qspi_concurrent_disable_xip_mode_bits(qspi_regs_t *QSPIx)
Disable the mode bits phase for concurrent xip mode.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_toc(qspi_regs_t *QSPIx)
Get time out count for continuous transfer for xip mode.
error_status_t ll_qspi_deinit(qspi_regs_t *QSPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_data(qspi_regs_t *QSPIx)
get the mode phase (sent after address phase) value in xip mode
__STATIC_INLINE void ll_qspi_concurrent_set_xip_wr_instruction_size(qspi_regs_t *QSPIx, uint32_t inst_size)
Set the instruction size for concurrent xip write mode.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_instruction(qspi_regs_t *QSPIx)
Check if the instruction phase is enabled or not for concurrent xip mode.
ll_qspi_memorymapped_write_init_t wr
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of XIP Mode.
__STATIC_INLINE uint32_t ll_qspi_get_dma_tx_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_prefetch(qspi_regs_t *QSPIx)
Enable the pre-fetch feature for concurrent xip mode.
__STATIC_INLINE void ll_qspi_set_max_wait_cycles(qspi_regs_t *QSPIx, uint32_t max_ws)
set the max wait cycles per transaction for dynamic wait state
__STATIC_INLINE void ll_qspi_set_xip_endian_mode(qspi_regs_t *QSPIx, uint32_t mode)
Set xip's endian mode.
__STATIC_INLINE void ll_qspi_set_control_frame_size(qspi_regs_t *QSPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
uint32_t transfer_direction
__STATIC_INLINE uint32_t ll_qspi_get_control_frame_size(qspi_regs_t *QSPIx)
Get the length of the control word for the Microwire frame format.
__STATIC_INLINE uint32_t ll_qspi_get_wait_cycles(qspi_regs_t *QSPIx)
Get number of wait cycles in Dual/Quad SPI mode.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_test_mode(qspi_regs_t *QSPIx)
Check if SPI test mode is enabled.
__STATIC_INLINE uint32_t ll_qspi_is_it_flag(qspi_regs_t *QSPIx, uint32_t flag)
Check interrupt flag.
__STATIC_INLINE uint16_t ll_qspi_receive_data16(qspi_regs_t *QSPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void ll_qspi_transmit_data8(qspi_regs_t *QSPIx, uint8_t tx_data)
Write 8-Bits in the data register.
__STATIC_INLINE uint32_t ll_qspi_get_rx_sample_edge(qspi_regs_t *QSPIx)
Get the RX sample edge.
error_status_t ll_qspi_init(qspi_regs_t *QSPIx, ll_qspi_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in SPI_InitStruct.
__STATIC_INLINE uint32_t ll_qspi_concurrent_is_enabled_xip_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if the slave is enabled or not for concurrent xip mode.
uint32_t x_mode_bits_length
__STATIC_INLINE uint32_t ll_qspi_get_tx_fifo_level(qspi_regs_t *QSPIx)
Get FIFO Transmission Level.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_xip_dynamic_le(qspi_regs_t *QSPIx)
Check if qspi xip dynamic little-endian mode is enabled.
__STATIC_INLINE void ll_qspi_disable_dws(qspi_regs_t *QSPIx)
Disable dynamic of wait states for QSPI peripheral.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wr_wrap_inst(qspi_regs_t *QSPIx)
get the ahb-wrap transfer instruction for write in xip mode
struct _ll_qspi_memorymapped_write_init_t ll_qspi_memorymapped_write_init_t
uint32_t x_instruction_en
#define LL_QSPI2_XIP_TX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss(qspi_regs_t *QSPIx, uint32_t ss)
Check if slave select is enabled.
__STATIC_INLINE void ll_qspi_set_rx_sample_delay(qspi_regs_t *QSPIx, uint32_t delay)
Set Rx sample delay.
uint32_t x_wr_inst_addr_transfer_format
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_mode(qspi_regs_t *QSPIx)
Get transfer mode in Microwire mode.
__STATIC_INLINE void ll_qspi_concurrent_set_xip_incr_inst(qspi_regs_t *QSPIx, uint32_t inst)
set the ahb-incr transfer instruction in xip mode
__STATIC_INLINE void ll_qspi_clear_flag_rxo(qspi_regs_t *QSPIx)
Clear receive FIFO overflow error flag.
__STATIC_INLINE uint32_t ll_qspi_get_micro_transfer_direction(qspi_regs_t *QSPIx)
Get transfer direction mode in Microwire mode.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_dma_req_tx(qspi_regs_t *QSPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_incr_inst(qspi_regs_t *QSPIx)
get the ahb-incr transfer instruction in xip mode
__STATIC_INLINE void ll_qspi_set_micro_transfer_direction(qspi_regs_t *QSPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
__STATIC_INLINE void ll_qspi_clear_flag_txo(qspi_regs_t *QSPIx)
Clear transmit FIFO overflow error flag.
__STATIC_INLINE uint32_t ll_qspi_get_instruction_size(qspi_regs_t *QSPIx)
Get Dual/Quad SPI mode instruction length in bits.
#define LL_QSPI1_REG_TX_FIFO_DEPTH
__STATIC_INLINE void ll_qspi_enable_clk_stretch(qspi_regs_t *QSPIx)
Enable the clock stretch feature for Enhanced SPI.
__STATIC_INLINE void ll_qspi_set_instruction_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode instruction length in bits.
uint32_t x_continous_xfer_en
ll_qspi_memorymapped_mode_e
__STATIC_INLINE void ll_qspi_enable_test_mode(qspi_regs_t *QSPIx)
Enable SPI test mode.
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_rx_fifo_depth(qspi_regs_t *QSPIx)
Get Receive FIFO Depth Of Register Mode.
void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init)
Set each field of a ll_qspi_init_t type structure to default value.
__STATIC_INLINE void ll_qspi_clear_flag_spite(qspi_regs_t *QSPIx)
Clear QSPI Transmit Error interrupt.
__STATIC_INLINE void ll_qspi_set_micro_transfer_mode(qspi_regs_t *QSPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
uint32_t x_inst_addr_transfer_format
__STATIC_INLINE uint32_t ll_qspi_get_reg_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of Register Mode.
__STATIC_INLINE void ll_qspi_set_clock_phase(qspi_regs_t *QSPIx, uint32_t clock_phase)
Set clock phase.
__STATIC_INLINE uint32_t ll_qspi_is_hresp_err_debug_mode_enabled(void)
Check if the AHB Response Error Debug is enabled for all QSPI Modules.
ll_qspi_memorymapped_mode_e rw_mode
__STATIC_INLINE void ll_qspi_set_address_size(qspi_regs_t *QSPIx, uint32_t size)
Set Dual/Quad SPI mode address length in bits.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_mode_bits_length(qspi_regs_t *QSPIx)
Get the length of mode bits phase for concurrent xip mode.
ll_qspi_memorymapped_read_init_t rd
__STATIC_INLINE uint32_t ll_qspi_get_xip_mode_tx_fifo_depth(qspi_regs_t *QSPIx)
Get Transmit FIFO Depth Of XIP Mode.
__STATIC_INLINE uint32_t ll_qspi_is_enabled_ss_toggle(qspi_regs_t *QSPIx)
Check if slave select toggle is enabled.
__STATIC_INLINE void ll_qspi_disable_ss_toggle(qspi_regs_t *QSPIx)
Disable slave select toggle.
struct _ll_qspi_init_t ll_qspi_init_t
QSPI init structures definition.
__STATIC_INLINE void ll_qspi_set_baud_rate_prescaler(qspi_regs_t *QSPIx, uint32_t baud_rate)
Set baud rate prescaler.
__STATIC_INLINE void ll_qspi_set_dma_rx_fifo_threshold(qspi_regs_t *QSPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
__STATIC_INLINE void ll_qspi_disable_it(qspi_regs_t *QSPIx, uint32_t mask)
Disable interrupt.
__STATIC_INLINE uint32_t ll_qspi_get_data_size(qspi_regs_t *QSPIx)
Get frame data size.
void ll_qspi_enable_xip(qspi_regs_t *QSPIx)
Enable qspi xip mode.
__STATIC_INLINE void ll_qspi_set_rx_sample_edge(qspi_regs_t *QSPIx, uint32_t edge)
Set the RX sample edge.
struct _ll_qspi_memorymapped_init_t ll_qspi_memorymapped_init_t
uint32_t x_wr_instruction
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_frame_format(qspi_regs_t *QSPIx)
Get the QSPI frame format for concurrent xip mode.
#define LL_QSPI1_XIP_RX_FIFO_DEPTH
#define LL_QSPI0_REG_TX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_get_it_flag(qspi_regs_t *QSPIx)
Get SPI interrupt flags.
#define LL_QSPI2_XIP_RX_FIFO_DEPTH
__STATIC_INLINE uint32_t ll_qspi_get_tx_start_fifo_threshold(qspi_regs_t *QSPIx)
Get threshold of TX transfer start.
__STATIC_INLINE void ll_qspi_disable(qspi_regs_t *QSPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t ll_qspi_concurrent_get_xip_wait_cycles(qspi_regs_t *QSPIx)
Get the wait(also called dummy) cycles for concurrent xip mode.
__STATIC_INLINE void ll_qspi_concurrent_enable_xip_continuous_xfer(qspi_regs_t *QSPIx)
Enable the continuous transfer feature for concurrent xip mode.
__STATIC_INLINE void ll_qspi_clear_flag_rxu(qspi_regs_t *QSPIx)
Clear receive FIFO underflow error flag.