gr55xx_hal_gpio_ex.h
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/**
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****************************************************************************************
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*
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* @file gr55xx_hal_gpio_ex.h
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* @author BLE Driver Team
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* @brief Header file containing extended macro of GPIO HAL library.
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*
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****************************************************************************************
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* @attention
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#####Copyright (c) 2019 GOODIX
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of GOODIX nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************************
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*/
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/** @addtogroup PERIPHERAL Peripheral Driver
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* @{
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*/
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/** @addtogroup HAL_DRIVER HAL Driver
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* @{
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*/
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/** @defgroup HAL_GPIOEx GPIOEx
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* @brief GPIOEx HAL module driver.
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* @{
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __GR55xx_HAL_GPIO_EX_H__
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#define __GR55xx_HAL_GPIO_EX_H__
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "
gr55xx_hal_def.h
"
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#include "
gr55xx_ll_gpio.h
"
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/* Exported types ------------------------------------------------------------*/
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/**
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* @defgroup HAL_GPIOEX_MACRO Defines
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* @{
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
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* @{
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*/
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/** @defgroup GPIOEx_Mux_Mode GPIOEx Mux Mode definition
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* @{
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*/
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#define GPIO_MUX_0 LL_GPIO_MUX_0
/**< GPIO Mux mode 0 */
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#define GPIO_MUX_1 LL_GPIO_MUX_1
/**< GPIO Mux mode 1 */
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#define GPIO_MUX_2 LL_GPIO_MUX_2
/**< GPIO Mux mode 2 */
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#define GPIO_MUX_3 LL_GPIO_MUX_3
/**< GPIO Mux mode 3 */
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#define GPIO_MUX_4 LL_GPIO_MUX_4
/**< GPIO Mux mode 4 */
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#define GPIO_MUX_5 LL_GPIO_MUX_5
/**< GPIO Mux mode 5 */
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#define GPIO_MUX_6 LL_GPIO_MUX_6
/**< GPIO Mux mode 6 */
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#define GPIO_MUX_7 LL_GPIO_MUX_7
/**< GPIO Mux mode 7 */
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#define GPIO_MUX_8 LL_GPIO_MUX_8
/**< GPIO Mux mode 8 */
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/** @} */
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/** @defgroup GPIOEx_Mux_Function_Selection GPIOEx Mux function selection
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* @{
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*/
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#if defined (GR552xx)
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/*---------------------------------- GR552xx ------------------------------*/
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/** @defgroup GPIOEx_Common_Selection GPIO PIN common MUX selection(Available for all GPIO pins)
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* @{
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*/
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#define GPIO_PIN_MUX_TESTBUS GPIO_MUX_8
/**< GPIO PIN x Mux Select TESTBUS */
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#define GPIO_PIN_MUX_GPIO GPIO_MUX_7
/**< GPIO PIN x Mux Select GPIO */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN0_Mux_Selection GPIO0_PIN0 MUX selection
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* @{
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*/
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#define GPIO0_PIN0_MUX_SWD_CLK GPIO_MUX_0
/**< GPIO0_PIN0 Mux Select SWD_CLK */
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#define GPIO0_PIN0_MUX_I2C1_SCL GPIO_MUX_1
/**< GPIO0_PIN0 Mux Select I2C1_SCL */
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#define GPIO0_PIN0_MUX_UART0_TX GPIO_MUX_2
/**< GPIO0_PIN0 Mux Select UART0_TX */
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#define GPIO0_PIN0_MUX_UART1_CTS GPIO_MUX_3
/**< GPIO0_PIN0 Mux Select UART1_CTS */
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#define GPIO0_PIN0_MUX_PWM1_C GPIO_MUX_4
/**< GPIO0_PIN0 Mux Select PWM1_C */
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#define GPIO0_PIN0_MUX_PWM0_C GPIO_MUX_5
/**< GPIO0_PIN0 Mux Select PWM0_C */
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#define GPIO0_PIN0_MUX_PDM_CLKO GPIO_MUX_6
/**< GPIO0_PIN0 Mux Select PDM_CLKO */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN1_Mux_Selection GPIO0_PIN1 MUX selection
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* @{
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*/
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#define GPIO0_PIN1_MUX_SWD_IO GPIO_MUX_0
/**< GPIO0_PIN1 Mux Select SWD_IO */
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#define GPIO0_PIN1_MUX_I2C1_SDA GPIO_MUX_1
/**< GPIO0_PIN1 Mux Select I2C1_SDA */
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#define GPIO0_PIN1_MUX_UART0_RX GPIO_MUX_2
/**< GPIO0_PIN1 Mux Select UART0_RX */
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#define GPIO0_PIN1_MUX_UART1_RTS GPIO_MUX_3
/**< GPIO0_PIN1 Mux Select UART1_RTS */
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#define GPIO0_PIN1_MUX_PWM1_B GPIO_MUX_4
/**< GPIO0_PIN1 Mux Select PWM1_B */
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#define GPIO0_PIN1_MUX_PWM0_B GPIO_MUX_5
/**< GPIO0_PIN1 Mux Select PWM0_B */
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#define GPIO0_PIN1_MUX_PDM_DI GPIO_MUX_6
/**< GPIO0_PIN1 Mux Select PDM_DI */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN2_Mux_Selection GPIO0_PIN2 MUX selection
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* @{
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*/
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#define GPIO0_PIN2_MUX_I2C0_SCL GPIO_MUX_0
/**< GPIO0_PIN2 Mux Select I2C0_SCL */
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#define GPIO0_PIN2_MUX_PDM_CLKO GPIO_MUX_1
/**< GPIO0_PIN2 Mux Select PDM_CLKO */
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#define GPIO0_PIN2_MUX_UART0_CTS GPIO_MUX_2
/**< GPIO0_PIN2 Mux Select UART0_CTS */
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#define GPIO0_PIN2_MUX_UART1_TX GPIO_MUX_3
/**< GPIO0_PIN2 Mux Select UART1_TX */
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#define GPIO0_PIN2_MUX_PWM1_A GPIO_MUX_4
/**< GPIO0_PIN2 Mux Select PWM1_A */
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#define GPIO0_PIN2_MUX_PWM0_A GPIO_MUX_5
/**< GPIO0_PIN2 Mux Select PWM0_A */
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#define GPIO0_PIN2_MUX_ISO_SYNC1_P GPIO_MUX_6
/**< GPIO0_PIN2 Mux Select ISO_SYNC1_P */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN3_Mux_Selection GPIO0_PIN3 MUX selection
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* @{
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*/
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#define GPIO0_PIN3_MUX_I2C0_SDA GPIO_MUX_0
/**< GPIO0_PIN3 Mux Select I2C0_SDA */
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#define GPIO0_PIN3_MUX_PDM_DI GPIO_MUX_1
/**< GPIO0_PIN3 Mux Select PDM_DI */
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#define GPIO0_PIN3_MUX_UART0_RTS GPIO_MUX_2
/**< GPIO0_PIN3 Mux Select UART0_RTS */
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#define GPIO0_PIN3_MUX_UART1_RX GPIO_MUX_3
/**< GPIO0_PIN3 Mux Select UART1_RX */
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#define GPIO0_PIN3_MUX_FERP_GPIO_TRIG GPIO_MUX_4
/**< GPIO0_PIN3 Mux Select FERP_GPIO_TRIG */
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#define GPIO0_PIN3_MUX_SWO GPIO_MUX_5
/**< GPIO0_PIN3 Mux Select SWO */
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#define GPIO0_PIN3_MUX_ISO_SYNC0_P GPIO_MUX_6
/**< GPIO0_PIN3 Mux Select ISO_SYNC0_P */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN4_Mux_Selection GPIO0_PIN4 MUX selection
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* @{
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*/
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#define GPIO0_PIN4_MUX_I2C4_SCL GPIO_MUX_0
/**< GPIO0_PIN4 Mux Select I2C4_SCL */
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#define GPIO0_PIN4_MUX_SPI_M_CLK GPIO_MUX_1
/**< GPIO0_PIN4 Mux Select SPI_M_CLK */
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#define GPIO0_PIN4_MUX_PWM0_A GPIO_MUX_2
/**< GPIO0_PIN4 Mux Select PWM0_A */
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#define GPIO0_PIN4_MUX_UART3_TX GPIO_MUX_3
/**< GPIO0_PIN4 Mux Select UART3_TX */
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#define GPIO0_PIN4_MUX_PDM_CLKO GPIO_MUX_4
/**< GPIO0_PIN4 Mux Select PDM_CLKO */
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#define GPIO0_PIN4_MUX_DF_ANT_SWITCH_SEL_0 GPIO_MUX_5
/**< GPIO0_PIN4 Mux Select DF_ANT_SWITCH_SEL_0 */
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#define GPIO0_PIN4_MUX_UART2_CTS GPIO_MUX_6
/**< GPIO0_PIN4 Mux Select UART2_CTS */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN5_Mux_Selection GPIO0_PIN5 MUX selection
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* @{
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*/
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#define GPIO0_PIN5_MUX_I2C4_SDA GPIO_MUX_0
/**< GPIO0_PIN5 Mux Select I2C4_SDA */
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#define GPIO0_PIN5_MUX_SPI_M_MOSI GPIO_MUX_1
/**< GPIO0_PIN5 Mux Select SPI_M_MOSI */
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#define GPIO0_PIN5_MUX_PWM0_B GPIO_MUX_2
/**< GPIO0_PIN5 Mux Select PWM0_B */
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#define GPIO0_PIN5_MUX_UART3_RX GPIO_MUX_3
/**< GPIO0_PIN5 Mux Select UART3_RX */
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#define GPIO0_PIN5_MUX_PDM_DI GPIO_MUX_4
/**< GPIO0_PIN5 Mux Select PDM_DI */
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#define GPIO0_PIN5_MUX_DF_ANT_SWITCH_SEL_1 GPIO_MUX_5
/**< GPIO0_PIN5 Mux Select DF_ANT_SWITCH_SEL_1 */
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#define GPIO0_PIN5_MUX_UART2_RTS GPIO_MUX_6
/**< GPIO0_PIN5 Mux Select UART2_RTS */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN6_Mux_Selection GPIO0_PIN6 MUX selection
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* @{
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*/
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#define GPIO0_PIN6_MUX_I2C3_SCL GPIO_MUX_0
/**< GPIO0_PIN6 Mux Select I2C3_SCL */
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#define GPIO0_PIN6_MUX_SPI_M_MISO GPIO_MUX_1
/**< GPIO0_PIN6 Mux Select SPI_M_MISO */
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#define GPIO0_PIN6_MUX_PWM0_C GPIO_MUX_2
/**< GPIO0_PIN6 Mux Select PWM0_C */
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#define GPIO0_PIN6_MUX_I2S_WS GPIO_MUX_3
/**< GPIO0_PIN6 Mux Select I2S_WS */
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#define GPIO0_PIN6_MUX_ISO_SYNC1_P GPIO_MUX_4
/**< GPIO0_PIN6 Mux Select ISO_SYNC1_P */
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#define GPIO0_PIN6_MUX_SPI_S_CLK GPIO_MUX_5
/**< GPIO0_PIN6 Mux Select SPI_S_CLK */
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#define GPIO0_PIN6_MUX_SIM_PRESENCE GPIO_MUX_6
/**< GPIO0_PIN6 Mux Select SIM_PRESENCE */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN7_Mux_Selection GPIO0_PIN7 MUX selection
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* @{
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*/
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#define GPIO0_PIN7_MUX_I2C3_SDA GPIO_MUX_0
/**< GPIO0_PIN7 Mux Select I2C3_SDA */
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#define GPIO0_PIN7_MUX_SPI_M_CS0_N GPIO_MUX_1
/**< GPIO0_PIN7 Mux Select SPI_M_CS0_N */
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#define GPIO0_PIN7_MUX_PWM1_A GPIO_MUX_2
/**< GPIO0_PIN7 Mux Select PWM1_A */
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#define GPIO0_PIN7_MUX_I2S_TX_SDO GPIO_MUX_3
/**< GPIO0_PIN7 Mux Select I2S_TX_SDO */
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#define GPIO0_PIN7_MUX_ISO_SYNC0_P GPIO_MUX_4
/**< GPIO0_PIN7 Mux Select ISO_SYNC0_P */
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#define GPIO0_PIN7_MUX_SPI_S_MISO GPIO_MUX_5
/**< GPIO0_PIN7 Mux Select SPI_S_MISO */
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#define GPIO0_PIN7_MUX_SIM_RST_N GPIO_MUX_6
/**< GPIO0_PIN7 Mux Select SIM_RST_N */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN8_Mux_Selection GPIO0_PIN8 MUX selection
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* @{
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*/
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#define GPIO0_PIN8_MUX_I2C5_SCL GPIO_MUX_0
/**< GPIO0_PIN8 Mux Select I2C5_SCL */
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#define GPIO0_PIN8_MUX_UART2_TX GPIO_MUX_1
/**< GPIO0_PIN8 Mux Select UART2_TX */
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#define GPIO0_PIN8_MUX_PWM1_B GPIO_MUX_2
/**< GPIO0_PIN8 Mux Select PWM1_B */
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#define GPIO0_PIN8_MUX_I2S_RX_SDI GPIO_MUX_3
/**< GPIO0_PIN8 Mux Select I2S_RX_SDI */
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#define GPIO0_PIN8_MUX_UART3_CTS GPIO_MUX_4
/**< GPIO0_PIN8 Mux Select UART3_CTS */
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#define GPIO0_PIN8_MUX_SPI_S_MOSI GPIO_MUX_5
/**< GPIO0_PIN8 Mux Select SPI_S_MOSI */
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#define GPIO0_PIN8_MUX_SIM_IO GPIO_MUX_6
/**< GPIO0_PIN8 Mux Select SIM_IO */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN9_Mux_Selection GPIO0_PIN9 MUX selection
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* @{
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*/
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#define GPIO0_PIN9_MUX_I2C5_SDA GPIO_MUX_0
/**< GPIO0_PIN9 Mux Select I2C5_SDA */
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#define GPIO0_PIN9_MUX_UART2_RX GPIO_MUX_1
/**< GPIO0_PIN9 Mux Select UART2_RX */
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#define GPIO0_PIN9_MUX_PWM1_C GPIO_MUX_2
/**< GPIO0_PIN9 Mux Select PWM1_C */
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#define GPIO0_PIN9_MUX_I2S_SCLK GPIO_MUX_3
/**< GPIO0_PIN9 Mux Select I2S_SCLK */
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#define GPIO0_PIN9_MUX_UART3_RTS GPIO_MUX_4
/**< GPIO0_PIN9 Mux Select UART3_RTS */
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#define GPIO0_PIN9_MUX_SPI_S_CS_N GPIO_MUX_5
/**< GPIO0_PIN9 Mux Select SPI_S_CS_N */
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#define GPIO0_PIN9_MUX_SIM_CLK GPIO_MUX_6
/**< GPIO0_PIN9 Mux Select SIM_CLK */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN10_Mux_Selection GPIO0_PIN10 MUX selection
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* @{
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*/
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#define GPIO0_PIN10_MUX_QSPI_M1_CS_N GPIO_MUX_0
/**< GPIO0_PIN10 Mux Select QSPI_M1_CS_N */
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#define GPIO0_PIN10_MUX_I2S_S_WS GPIO_MUX_1
/**< GPIO0_PIN10 Mux Select I2S_S_WS */
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#define GPIO0_PIN10_MUX_SPI_M_CS0_N GPIO_MUX_2
/**< GPIO0_PIN10 Mux Select SPI_M_CS0_N */
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#define GPIO0_PIN10_MUX_UART4_CTS GPIO_MUX_3
/**< GPIO0_PIN10 Mux Select UART4_CTS */
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#define GPIO0_PIN10_MUX_UART5_RX GPIO_MUX_4
/**< GPIO0_PIN10 Mux Select UART5_RX */
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#define GPIO0_PIN10_MUX_PWM1_A GPIO_MUX_5
/**< GPIO0_PIN10 Mux Select PWM1_A */
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#define GPIO0_PIN10_MUX_SPI_S_MOSI GPIO_MUX_6
/**< GPIO0_PIN10 Mux Select SPI_S_MOSI */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN11_Mux_Selection GPIO0_PIN11 MUX selection
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* @{
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*/
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#define GPIO0_PIN11_MUX_QSPI_M1_IO_3 GPIO_MUX_0
/**< GPIO0_PIN11 Mux Select QSPI_M1_IO_3 */
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#define GPIO0_PIN11_MUX_I2S_S_TX_SDO GPIO_MUX_1
/**< GPIO0_PIN11 Mux Select I2S_S_TX_SDO */
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#define GPIO0_PIN11_MUX_I2C3_SCL GPIO_MUX_2
/**< GPIO0_PIN11 Mux Select I2C3_SCL */
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#define GPIO0_PIN11_MUX_UART4_RTS GPIO_MUX_3
/**< GPIO0_PIN11 Mux Select UART4_RTS */
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#define GPIO0_PIN11_MUX_UART5_TX GPIO_MUX_4
/**< GPIO0_PIN11 Mux Select UART5_TX */
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#define GPIO0_PIN11_MUX_PWM1_B GPIO_MUX_5
/**< GPIO0_PIN11 Mux Select PWM1_B */
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#define GPIO0_PIN11_MUX_SPI_S_CLK GPIO_MUX_6
/**< GPIO0_PIN11 Mux Select SPI_S_CLK */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN12_Mux_Selection GPIO0_PIN12 MUX selection
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* @{
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*/
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#define GPIO0_PIN12_MUX_QSPI_M1_IO_2 GPIO_MUX_0
/**< GPIO0_PIN12 Mux Select QSPI_M1_IO_2 */
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#define GPIO0_PIN12_MUX_I2S_S_RX_SDI GPIO_MUX_1
/**< GPIO0_PIN12 Mux Select I2S_S_RX_SDI */
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#define GPIO0_PIN12_MUX_I2C3_SDA GPIO_MUX_2
/**< GPIO0_PIN12 Mux Select I2C3_SDA */
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#define GPIO0_PIN12_MUX_UART4_TX GPIO_MUX_3
/**< GPIO0_PIN12 Mux Select UART4_TX */
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#define GPIO0_PIN12_MUX_UART5_CTS GPIO_MUX_4
/**< GPIO0_PIN12 Mux Select UART5_CTS */
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#define GPIO0_PIN12_MUX_PWM1_C GPIO_MUX_5
/**< GPIO0_PIN12 Mux Select PWM1_C */
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#define GPIO0_PIN12_MUX_SPI_S_MISO GPIO_MUX_6
/**< GPIO0_PIN12 Mux Select SPI_S_MISO */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN13_Mux_Selection GPIO0_PIN13 MUX selection
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* @{
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*/
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#define GPIO0_PIN13_MUX_QSPI_M1_IO_1 GPIO_MUX_0
/**< GPIO0_PIN13 Mux Select QSPI_M1_IO_1 */
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#define GPIO0_PIN13_MUX_I2S_S_SCLK GPIO_MUX_1
/**< GPIO0_PIN13 Mux Select I2S_S_SCLK */
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#define GPIO0_PIN13_MUX_SPI_M_MISO GPIO_MUX_2
/**< GPIO0_PIN13 Mux Select SPI_M_MISO */
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#define GPIO0_PIN13_MUX_UART4_RX GPIO_MUX_3
/**< GPIO0_PIN13 Mux Select UART4_RX */
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#define GPIO0_PIN13_MUX_UART5_RTS GPIO_MUX_4
/**< GPIO0_PIN13 Mux Select UART5_RTS */
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#define GPIO0_PIN13_MUX_FERP_GPIO_TRIG GPIO_MUX_5
/**< GPIO0_PIN13 Mux Select FERP_GPIO_TRIG */
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#define GPIO0_PIN13_MUX_SPI_S_CS_N GPIO_MUX_6
/**< GPIO0_PIN13 Mux Select SPI_S_CS_N */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN14_Mux_Selection GPIO0_PIN14 MUX selection
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* @{
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*/
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#define GPIO0_PIN14_MUX_QSPI_M1_IO_0 GPIO_MUX_0
/**< GPIO0_PIN14 Mux Select QSPI_M1_IO_0 */
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#define GPIO0_PIN14_MUX_I2C5_SCL GPIO_MUX_1
/**< GPIO0_PIN14 Mux Select I2C5_SCL */
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#define GPIO0_PIN14_MUX_SPI_M_MOSI GPIO_MUX_2
/**< GPIO0_PIN14 Mux Select SPI_M_MOSI */
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#define GPIO0_PIN14_MUX_PDM_CLKO GPIO_MUX_3
/**< GPIO0_PIN14 Mux Select PDM_CLKO */
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#define GPIO0_PIN14_MUX_DF_ANT_SWITCH_SEL_2 GPIO_MUX_4
/**< GPIO0_PIN14 Mux Select DF_ANT_SWITCH_SEL_2 */
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#define GPIO0_PIN14_MUX_UART0_TX GPIO_MUX_5
/**< GPIO0_PIN14 Mux Select UART0_TX */
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#define GPIO0_PIN14_MUX_ISO_SYNC1_P GPIO_MUX_6
/**< GPIO0_PIN14 Mux Select ISO_SYNC1_P */
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/** @} */
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/** @defgroup GPIOEx_GPIO0_PIN15_Mux_Selection GPIO0_PIN15 MUX selection
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* @{
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*/
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#define GPIO0_PIN15_MUX_QSPI_M1_CLK GPIO_MUX_0
/**< GPIO0_PIN15 Mux Select QSPI_M1_CLK */
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#define GPIO0_PIN15_MUX_I2C5_SDA GPIO_MUX_1
/**< GPIO0_PIN15 Mux Select I2C5_SDA */
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#define GPIO0_PIN15_MUX_SPI_M_CLK GPIO_MUX_2
/**< GPIO0_PIN15 Mux Select SPI_M_CLK */
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#define GPIO0_PIN15_MUX_PDM_DI GPIO_MUX_3
/**< GPIO0_PIN15 Mux Select PDM_DI */
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#define GPIO0_PIN15_MUX_DF_ANT_SWITCH_SEL_3 GPIO_MUX_4
/**< GPIO0_PIN15 Mux Select DF_ANT_SWITCH_SEL_3 */
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#define GPIO0_PIN15_MUX_UART0_RX GPIO_MUX_5
/**< GPIO0_PIN15 Mux Select UART0_RX */
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#define GPIO0_PIN15_MUX_ISO_SYNC0_P GPIO_MUX_6
/**< GPIO0_PIN15 Mux Select ISO_SYNC0_P */
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/** @} */
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/** @defgroup GPIOEx_GPIO1_PIN0_Mux_Selection GPIO1_PIN0 MUX selection
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* @{
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*/
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#define GPIO1_PIN0_MUX_QSPI_M2_CLK GPIO_MUX_0
/**< GPIO1_PIN0 Mux Select QSPI_M2_CLK */
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#define GPIO1_PIN0_MUX_DC_CLK GPIO_MUX_1
/**< GPIO1_PIN0 Mux Select DC_CLK */
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#define GPIO1_PIN0_MUX_DSPI_SCK GPIO_MUX_2
/**< GPIO1_PIN0 Mux Select DSPI_SCK */
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#define GPIO1_PIN0_MUX_SPI_M_CLK GPIO_MUX_3
/**< GPIO1_PIN0 Mux Select SPI_M_CLK */
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#define GPIO1_PIN0_MUX_UART4_TX GPIO_MUX_4
/**< GPIO1_PIN0 Mux Select UART4_TX */
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#define GPIO1_PIN0_MUX_PWM0_C GPIO_MUX_5
/**< GPIO1_PIN0 Mux Select PWM0_C */
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#define GPIO1_PIN0_MUX_I2C0_SCL GPIO_MUX_6
/**< GPIO1_PIN0 Mux Select I2C0_SCL */
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/** @} */
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/** @defgroup GPIOEx_GPIO1_PIN1_Mux_Selection GPIO1_PIN1 MUX selection
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* @{
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*/
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#define GPIO1_PIN1_MUX_QSPI_M2_IO_0 GPIO_MUX_0
/**< GPIO1_PIN1 Mux Select QSPI_M2_IO_0 */
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#define GPIO1_PIN1_MUX_DC_IO_0 GPIO_MUX_1
/**< GPIO1_PIN1 Mux Select DC_IO_0 */
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#define GPIO1_PIN1_MUX_DSPI_MOSI GPIO_MUX_2
/**< GPIO1_PIN1 Mux Select DSPI_MOSI */
318
#define GPIO1_PIN1_MUX_SPI_M_MOSI GPIO_MUX_3
/**< GPIO1_PIN1 Mux Select SPI_M_MOSI */
319
#define GPIO1_PIN1_MUX_UART2_TX GPIO_MUX_4
/**< GPIO1_PIN1 Mux Select UART2_TX */
320
#define GPIO1_PIN1_MUX_UART3_CTS GPIO_MUX_5
/**< GPIO1_PIN1 Mux Select UART3_CTS */
321
#define GPIO1_PIN1_MUX_I2C0_SDA GPIO_MUX_6
/**< GPIO1_PIN1 Mux Select I2C0_SDA */
322
/** @} */
323
324
/** @defgroup GPIOEx_GPIO1_PIN2_Mux_Selection GPIO1_PIN2 MUX selection
325
* @{
326
*/
327
#define GPIO1_PIN2_MUX_QSPI_M2_IO_1 GPIO_MUX_0
/**< GPIO1_PIN2 Mux Select QSPI_M2_IO_1 */
328
#define GPIO1_PIN2_MUX_DC_IO_1 GPIO_MUX_1
/**< GPIO1_PIN2 Mux Select DC_IO_1 */
329
#define GPIO1_PIN2_MUX_DSPI_MISO GPIO_MUX_2
/**< GPIO1_PIN2 Mux Select DSPI_MISO */
330
#define GPIO1_PIN2_MUX_SPI_M_MISO GPIO_MUX_3
/**< GPIO1_PIN2 Mux Select SPI_M_MISO */
331
#define GPIO1_PIN2_MUX_UART2_RX GPIO_MUX_4
/**< GPIO1_PIN2 Mux Select UART2_RX */
332
#define GPIO1_PIN2_MUX_UART3_RTS GPIO_MUX_5
/**< GPIO1_PIN2 Mux Select UART3_RTS */
333
#define GPIO1_PIN2_MUX_PWM1_A GPIO_MUX_6
/**< GPIO1_PIN2 Mux Select PWM1_A */
334
/** @} */
335
336
/** @defgroup GPIOEx_GPIO1_PIN3_Mux_Selection GPIO1_PIN3 MUX selection
337
* @{
338
*/
339
#define GPIO1_PIN3_MUX_QSPI_M2_IO_2 GPIO_MUX_0
/**< GPIO1_PIN3 Mux Select QSPI_M2_IO_2 */
340
#define GPIO1_PIN3_MUX_DC_IO_2 GPIO_MUX_1
/**< GPIO1_PIN3 Mux Select DC_IO_2 */
341
#define GPIO1_PIN3_MUX_DSPI_DCX GPIO_MUX_2
/**< GPIO1_PIN3 Mux Select DSPI_DCX */
342
#define GPIO1_PIN3_MUX_SPI_M_CS0_N GPIO_MUX_3
/**< GPIO1_PIN3 Mux Select SPI_M_CS0_N */
343
#define GPIO1_PIN3_MUX_UART2_CTS GPIO_MUX_4
/**< GPIO1_PIN3 Mux Select UART2_CTS */
344
#define GPIO1_PIN3_MUX_UART3_TX GPIO_MUX_5
/**< GPIO1_PIN3 Mux Select UART3_TX */
345
#define GPIO1_PIN3_MUX_PWM1_B GPIO_MUX_6
/**< GPIO1_PIN3 Mux Select PWM1_B */
346
/** @} */
347
348
/** @defgroup GPIOEx_GPIO1_PIN4_Mux_Selection GPIO1_PIN4 MUX selection
349
* @{
350
*/
351
#define GPIO1_PIN4_MUX_QSPI_M2_IO_3 GPIO_MUX_0
/**< GPIO1_PIN4 Mux Select QSPI_M2_IO_3 */
352
#define GPIO1_PIN4_MUX_DC_IO_3 GPIO_MUX_1
/**< GPIO1_PIN4 Mux Select DC_IO_3 */
353
#define GPIO1_PIN4_MUX_DSPI_CSS GPIO_MUX_2
/**< GPIO1_PIN4 Mux Select DSPI_CSS */
354
#define GPIO1_PIN4_MUX_SPI_M_CS1_N GPIO_MUX_3
/**< GPIO1_PIN4 Mux Select SPI_M_CS1_N */
355
#define GPIO1_PIN4_MUX_UART2_RTS GPIO_MUX_4
/**< GPIO1_PIN4 Mux Select UART2_RTS */
356
#define GPIO1_PIN4_MUX_UART3_RX GPIO_MUX_5
/**< GPIO1_PIN4 Mux Select UART3_RX */
357
#define GPIO1_PIN4_MUX_PWM1_C GPIO_MUX_6
/**< GPIO1_PIN4 Mux Select PWM1_C */
358
/** @} */
359
360
/** @defgroup GPIOEx_GPIO1_PIN5_Mux_Selection GPIO1_PIN5 MUX selection
361
* @{
362
*/
363
#define GPIO1_PIN5_MUX_QSPI_M0_CLK GPIO_MUX_0
/**< GPIO1_PIN5 Mux Select QSPI_M0_CLK */
364
#define GPIO1_PIN5_MUX_SPI_M_CLK GPIO_MUX_1
/**< GPIO1_PIN5 Mux Select SPI_M_CLK */
365
#define GPIO1_PIN5_MUX_SIM_CLK GPIO_MUX_2
/**< GPIO1_PIN5 Mux Select SIM_CLK */
366
#define GPIO1_PIN5_MUX_I2S_SCLK GPIO_MUX_3
/**< GPIO1_PIN5 Mux Select I2S_SCLK */
367
#define GPIO1_PIN5_MUX_I2S_S_SCLK GPIO_MUX_4
/**< GPIO1_PIN5 Mux Select I2S_S_SCLK */
368
#define GPIO1_PIN5_MUX_SPI_S_CLK GPIO_MUX_5
/**< GPIO1_PIN5 Mux Select SPI_S_CLK */
369
#define GPIO1_PIN5_MUX_I2C3_SCL GPIO_MUX_6
/**< GPIO1_PIN5 Mux Select I2C3_SCL */
370
/** @} */
371
372
/** @defgroup GPIOEx_GPIO1_PIN6_Mux_Selection GPIO1_PIN6 MUX selection
373
* @{
374
*/
375
#define GPIO1_PIN6_MUX_QSPI_M0_IO_0 GPIO_MUX_0
/**< GPIO1_PIN6 Mux Select QSPI_M0_IO_0 */
376
#define GPIO1_PIN6_MUX_SPI_M_MOSI GPIO_MUX_1
/**< GPIO1_PIN6 Mux Select SPI_M_MOSI */
377
#define GPIO1_PIN6_MUX_SIM_IO GPIO_MUX_2
/**< GPIO1_PIN6 Mux Select SIM_IO */
378
#define GPIO1_PIN6_MUX_I2S_RX_SDI GPIO_MUX_3
/**< GPIO1_PIN6 Mux Select I2S_RX_SDI */
379
#define GPIO1_PIN6_MUX_I2S_S_TX_SDO GPIO_MUX_4
/**< GPIO1_PIN6 Mux Select I2S_S_TX_SDO */
380
#define GPIO1_PIN6_MUX_SPI_S_MISO GPIO_MUX_5
/**< GPIO1_PIN6 Mux Select SPI_S_MISO */
381
#define GPIO1_PIN6_MUX_I2C3_SDA GPIO_MUX_6
/**< GPIO1_PIN6 Mux Select I2C3_SDA */
382
/** @} */
383
384
/** @defgroup GPIOEx_GPIO1_PIN7_Mux_Selection GPIO1_PIN7 MUX selection
385
* @{
386
*/
387
#define GPIO1_PIN7_MUX_QSPI_M0_IO_1 GPIO_MUX_0
/**< GPIO1_PIN7 Mux Select QSPI_M0_IO_1 */
388
#define GPIO1_PIN7_MUX_SPI_M_MISO GPIO_MUX_1
/**< GPIO1_PIN7 Mux Select SPI_M_MISO */
389
#define GPIO1_PIN7_MUX_SIM_RST_N GPIO_MUX_2
/**< GPIO1_PIN7 Mux Select SIM_RST_N */
390
#define GPIO1_PIN7_MUX_I2S_TX_SDO GPIO_MUX_3
/**< GPIO1_PIN7 Mux Select I2S_TX_SDO */
391
#define GPIO1_PIN7_MUX_I2S_S_RX_SDI GPIO_MUX_4
/**< GPIO1_PIN7 Mux Select I2S_S_RX_SDI */
392
#define GPIO1_PIN7_MUX_SPI_S_MOSI GPIO_MUX_5
/**< GPIO1_PIN7 Mux Select SPI_S_MOSI */
393
#define GPIO1_PIN7_MUX_I2C2_SCL GPIO_MUX_6
/**< GPIO1_PIN7 Mux Select I2C2_SCL */
394
/** @} */
395
396
/** @defgroup GPIOEx_GPIO1_PIN8_Mux_Selection GPIO1_PIN8 MUX selection
397
* @{
398
*/
399
#define GPIO1_PIN8_MUX_QSPI_M0_IO_2 GPIO_MUX_0
/**< GPIO1_PIN8 Mux Select QSPI_M0_IO_2 */
400
#define GPIO1_PIN8_MUX_SPI_M_CS0_N GPIO_MUX_1
/**< GPIO1_PIN8 Mux Select SPI_M_CS0_N */
401
#define GPIO1_PIN8_MUX_SIM_PRESENCE GPIO_MUX_2
/**< GPIO1_PIN8 Mux Select SIM_PRESENCE */
402
#define GPIO1_PIN8_MUX_I2S_WS GPIO_MUX_3
/**< GPIO1_PIN8 Mux Select I2S_WS */
403
#define GPIO1_PIN8_MUX_I2S_S_WS GPIO_MUX_4
/**< GPIO1_PIN8 Mux Select I2S_S_WS */
404
#define GPIO1_PIN8_MUX_SPI_S_CS_N GPIO_MUX_5
/**< GPIO1_PIN8 Mux Select SPI_S_CS_N */
405
#define GPIO1_PIN8_MUX_I2C2_SDA GPIO_MUX_6
/**< GPIO1_PIN8 Mux Select I2C2_SDA */
406
/** @} */
407
408
/** @defgroup GPIOEx_GPIO1_PIN9_Mux_Selection GPIO1_PIN9 MUX selection
409
* @{
410
*/
411
#define GPIO1_PIN9_MUX_QSPI_M0_IO_3 GPIO_MUX_0
/**< GPIO1_PIN9 Mux Select QSPI_M0_IO_3 */
412
#define GPIO1_PIN9_MUX_SPI_M_CS1_N GPIO_MUX_1
/**< GPIO1_PIN9 Mux Select SPI_M_CS1_N */
413
#define GPIO1_PIN9_MUX_FERP_GPIO_TRIG GPIO_MUX_2
/**< GPIO1_PIN9 Mux Select FERP_GPIO_TRIG */
414
#define GPIO1_PIN9_MUX_UART4_RX GPIO_MUX_3
/**< GPIO1_PIN9 Mux Select UART4_RX */
415
#define GPIO1_PIN9_MUX_I2C3_SCL GPIO_MUX_4
/**< GPIO1_PIN9 Mux Select I2C3_SCL */
416
#define GPIO1_PIN9_MUX_I2C1_SCL GPIO_MUX_5
/**< GPIO1_PIN9 Mux Select I2C1_SCL */
417
#define GPIO1_PIN9_MUX_PWM0_A GPIO_MUX_6
/**< GPIO1_PIN9 Mux Select PWM0_A */
418
/** @} */
419
420
/** @defgroup GPIOEx_GPIO1_PIN10_Mux_Selection GPIO1_PIN10 MUX selection
421
* @{
422
*/
423
#define GPIO1_PIN10_MUX_QSPI_M0_CS_N GPIO_MUX_0
/**< GPIO1_PIN10 Mux Select QSPI_M0_CS_N */
424
#define GPIO1_PIN10_MUX_SPI_M_CS0_N GPIO_MUX_1
/**< GPIO1_PIN10 Mux Select SPI_M_CS0_N */
425
#define GPIO1_PIN10_MUX_UART0_CTS GPIO_MUX_2
/**< GPIO1_PIN10 Mux Select UART0_CTS */
426
#define GPIO1_PIN10_MUX_SPI_M_CLK GPIO_MUX_3
/**< GPIO1_PIN10 Mux Select SPI_M_CLK */
427
#define GPIO1_PIN10_MUX_I2C3_SDA GPIO_MUX_4
/**< GPIO1_PIN10 Mux Select I2C3_SDA */
428
#define GPIO1_PIN10_MUX_I2C1_SDA GPIO_MUX_5
/**< GPIO1_PIN10 Mux Select I2C1_SDA */
429
#define GPIO1_PIN10_MUX_PWM0_B GPIO_MUX_6
/**< GPIO1_PIN10 Mux Select PWM0_B */
430
/** @} */
431
432
/** @defgroup GPIOEx_GPIO1_PIN11_Mux_Selection GPIO1_PIN11 MUX selection
433
* @{
434
*/
435
#define GPIO1_PIN11_MUX_QSPI_M2_CS_N GPIO_MUX_0
/**< GPIO1_PIN11 Mux Select QSPI_M2_CS_N */
436
#define GPIO1_PIN11_MUX_DC_CS_N GPIO_MUX_1
/**< GPIO1_PIN11 Mux Select DC_CS_N */
437
#define GPIO1_PIN11_MUX_UART0_RTS GPIO_MUX_2
/**< GPIO1_PIN11 Mux Select UART0_RTS */
438
#define GPIO1_PIN11_MUX_SPI_M_MOSI GPIO_MUX_3
/**< GPIO1_PIN11 Mux Select SPI_M_MOSI */
439
#define GPIO1_PIN11_MUX_I2C2_SCL GPIO_MUX_4
/**< GPIO1_PIN11 Mux Select I2C2_SCL */
440
#define GPIO1_PIN11_MUX_I2C0_SCL GPIO_MUX_5
/**< GPIO1_PIN11 Mux Select I2C0_SCL */
441
#define GPIO1_PIN11_MUX_PWM0_C GPIO_MUX_6
/**< GPIO1_PIN11 Mux Select PWM0_C */
442
/** @} */
443
444
/** @defgroup GPIOEx_GPIO1_PIN12_Mux_Selection GPIO1_PIN12 MUX selection
445
* @{
446
*/
447
#define GPIO1_PIN12_MUX_PDM_CLKO GPIO_MUX_0
/**< GPIO1_PIN12 Mux Select PDM_CLKO */
448
#define GPIO1_PIN12_MUX_ISO_SYNC1_P GPIO_MUX_1
/**< GPIO1_PIN12 Mux Select ISO_SYNC1_P */
449
#define GPIO1_PIN12_MUX_UART0_TX GPIO_MUX_2
/**< GPIO1_PIN12 Mux Select UART0_TX */
450
#define GPIO1_PIN12_MUX_SPI_M_MISO GPIO_MUX_3
/**< GPIO1_PIN12 Mux Select SPI_M_MISO */
451
#define GPIO1_PIN12_MUX_I2C2_SDA GPIO_MUX_4
/**< GPIO1_PIN12 Mux Select I2C2_SDA */
452
#define GPIO1_PIN12_MUX_I2C0_SDA GPIO_MUX_5
/**< GPIO1_PIN12 Mux Select I2C0_SDA */
453
#define GPIO1_PIN12_MUX_SPI_M_CLK GPIO_MUX_6
/**< GPIO1_PIN12 Mux Select SPI_M_CLK */
454
/** @} */
455
456
/** @defgroup GPIOEx_GPIO1_PIN13_Mux_Selection GPIO1_PIN13 MUX selection
457
* @{
458
*/
459
#define GPIO1_PIN13_MUX_PDM_DI GPIO_MUX_0
/**< GPIO1_PIN13 Mux Select PDM_DI */
460
#define GPIO1_PIN13_MUX_ISO_SYNC0_P GPIO_MUX_1
/**< GPIO1_PIN13 Mux Select ISO_SYNC0_P */
461
#define GPIO1_PIN13_MUX_UART0_RX GPIO_MUX_2
/**< GPIO1_PIN13 Mux Select UART0_RX */
462
#define GPIO1_PIN13_MUX_SPI_M_CS0_N GPIO_MUX_3
/**< GPIO1_PIN13 Mux Select SPI_M_CS0_N */
463
#define GPIO1_PIN13_MUX_FERP_GPIO_TRIG GPIO_MUX_4
/**< GPIO1_PIN13 Mux Select FERP_GPIO_TRIG */
464
#define GPIO1_PIN13_MUX_DC_DCX GPIO_MUX_5
/**< GPIO1_PIN13 Mux Select DC_DCX */
465
#define GPIO1_PIN13_MUX_SPI_M_MOSI GPIO_MUX_6
/**< GPIO1_PIN13 Mux Select SPI_M_MOSI */
466
/** @} */
467
468
/** @defgroup GPIOEx_GPIO1_PIN14_Mux_Selection GPIO1_PIN14 MUX selection
469
* @{
470
*/
471
#define GPIO1_PIN14_MUX_SPI_S_MOSI GPIO_MUX_0
/**< GPIO1_PIN14 Mux Select SPI_S_MOSI */
472
#define GPIO1_PIN14_MUX_I2S_SCLK GPIO_MUX_1
/**< GPIO1_PIN14 Mux Select I2S_SCLK */
473
#define GPIO1_PIN14_MUX_I2S_S_WS GPIO_MUX_2
/**< GPIO1_PIN14 Mux Select I2S_S_WS */
474
#define GPIO1_PIN14_MUX_I2C1_SCL GPIO_MUX_3
/**< GPIO1_PIN14 Mux Select I2C1_SCL */
475
#define GPIO1_PIN14_MUX_UART1_CTS GPIO_MUX_4
/**< GPIO1_PIN14 Mux Select UART1_CTS */
476
#define GPIO1_PIN14_MUX_I2C5_SCL GPIO_MUX_5
/**< GPIO1_PIN14 Mux Select I2C5_SCL */
477
#define GPIO1_PIN14_MUX_SPI_M_MISO GPIO_MUX_6
/**< GPIO1_PIN14 Mux Select SPI_M_MISO */
478
/** @} */
479
480
/** @defgroup GPIOEx_GPIO1_PIN15_Mux_Selection GPIO1_PIN15 MUX selection
481
* @{
482
*/
483
#define GPIO1_PIN15_MUX_SPI_S_CLK GPIO_MUX_0
/**< GPIO1_PIN15 Mux Select SPI_S_CLK */
484
#define GPIO1_PIN15_MUX_I2S_RX_SDI GPIO_MUX_1
/**< GPIO1_PIN15 Mux Select I2S_RX_SDI */
485
#define GPIO1_PIN15_MUX_I2S_S_TX_SDO GPIO_MUX_2
/**< GPIO1_PIN15 Mux Select I2S_S_TX_SDO */
486
#define GPIO1_PIN15_MUX_I2C1_SDA GPIO_MUX_3
/**< GPIO1_PIN15 Mux Select I2C1_SDA */
487
#define GPIO1_PIN15_MUX_UART1_RTS GPIO_MUX_4
/**< GPIO1_PIN15 Mux Select UART1_RTS */
488
#define GPIO1_PIN15_MUX_I2C5_SDA GPIO_MUX_5
/**< GPIO1_PIN15 Mux Select I2C5_SDA */
489
#define GPIO1_PIN15_MUX_SPI_M_CS0_N GPIO_MUX_6
/**< GPIO1_PIN15 Mux Select SPI_M_CS0_N */
490
/** @} */
491
492
/** @defgroup GPIOEx_GPIO2_PIN0_Mux_Selection GPIO2_PIN0 MUX selection
493
* @{
494
*/
495
#define GPIO2_PIN0_MUX_SPI_S_MISO GPIO_MUX_0
/**< GPIO2_PIN0 Mux Select SPI_S_MISO */
496
#define GPIO2_PIN0_MUX_I2S_TX_SDO GPIO_MUX_1
/**< GPIO2_PIN0 Mux Select I2S_TX_SDO */
497
#define GPIO2_PIN0_MUX_I2S_S_RX_SDI GPIO_MUX_2
/**< GPIO2_PIN0 Mux Select I2S_S_RX_SDI */
498
#define GPIO2_PIN0_MUX_PDM_CLKO GPIO_MUX_3
/**< GPIO2_PIN0 Mux Select PDM_CLKO */
499
#define GPIO2_PIN0_MUX_UART1_TX GPIO_MUX_4
/**< GPIO2_PIN0 Mux Select UART1_TX */
500
#define GPIO2_PIN0_MUX_PWM0_B GPIO_MUX_5
/**< GPIO2_PIN0 Mux Select PWM0_B */
501
#define GPIO2_PIN0_MUX_I2C0_SCL GPIO_MUX_6
/**< GPIO2_PIN0 Mux Select I2C0_SCL */
502
/** @} */
503
504
/** @defgroup GPIOEx_GPIO2_PIN1_Mux_Selection GPIO2_PIN1 MUX selection
505
* @{
506
*/
507
#define GPIO2_PIN1_MUX_SPI_S_CS_N GPIO_MUX_0
/**< GPIO2_PIN1 Mux Select SPI_S_CS_N */
508
#define GPIO2_PIN1_MUX_I2S_WS GPIO_MUX_1
/**< GPIO2_PIN1 Mux Select I2S_WS */
509
#define GPIO2_PIN1_MUX_I2S_S_SCLK GPIO_MUX_2
/**< GPIO2_PIN1 Mux Select I2S_S_SCLK */
510
#define GPIO2_PIN1_MUX_PDM_DI GPIO_MUX_3
/**< GPIO2_PIN1 Mux Select PDM_DI */
511
#define GPIO2_PIN1_MUX_UART1_RX GPIO_MUX_4
/**< GPIO2_PIN1 Mux Select UART1_RX */
512
#define GPIO2_PIN1_MUX_PWM0_A GPIO_MUX_5
/**< GPIO2_PIN1 Mux Select PWM0_A */
513
#define GPIO2_PIN1_MUX_I2C0_SDA GPIO_MUX_6
/**< GPIO2_PIN1 Mux Select I2C0_SDA */
514
/** @} */
515
516
/**
517
* @brief Check if GPIO Mux mode is valid.
518
* @param __MUX__ GPIO mux mode.
519
* @retval SET (__ACTION__ is valid) or RESET (__ACTION__ is invalid)
520
*/
521
#define IS_GPIO_MUX(__MUX__) (((__MUX__) <= GPIO_MUX_8))
522
523
/*------------------------------------------------------------------------------------------*/
524
#endif
/* GR552xx */
525
526
527
528
/** @} */
529
530
/** @} */
531
532
/* Exported macro ------------------------------------------------------------*/
533
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
534
* @{
535
*/
536
537
#ifdef __cplusplus
538
}
539
#endif
540
541
#endif
/* __GR55xx_HAL_GPIO_EX_H__ */
542
543
/** @} */
544
/** @} */
545
546
/** @} */
547
548
/** @} */
549
550
/** @} */
gr55xx_ll_gpio.h
Header file containing functions prototypes of GPIO LL library.
gr55xx_hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.