52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
62 #if defined(AON_IO) || defined(MCU_RET)
120 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U)
121 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U)
122 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U)
123 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U)
124 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U)
125 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U)
126 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U)
127 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U)
128 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU)
134 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U)
135 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U)
136 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U)
142 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N
143 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP
144 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U)
150 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U)
151 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U)
152 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U)
153 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U)
154 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U)
155 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U)
156 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U)
157 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U)
158 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U)
165 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U)
166 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U)
167 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U)
168 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U)
169 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U)
170 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U)
177 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U)
178 #define LL_CLK_RNG_OSC_2MHZ ((uint32_t)0x01U)
179 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U)
180 #define LL_CLK_RTC_CLK ((uint32_t)0x03U)
202 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
210 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
226 #define LL_AON_GPIO_RE_N_Pos AON_IO_AON_PAD_CTRL0_R_EN_POS
227 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos)
228 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk
234 #define LL_AON_GPIO_RTYP_Pos AON_IO_AON_PAD_CTRL0_R_TYPE_POS
235 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos)
236 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk
246 #define LL_AON_GPIO_DEFAULT_CONFIG \
248 .pin = LL_AON_GPIO_PIN_ALL, \
249 .mode = LL_AON_GPIO_MODE_INPUT, \
250 .pull = LL_AON_GPIO_PULL_DOWN, \
251 .mux = LL_AON_GPIO_MUX_7, \
252 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
293 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_EN_POS) & AON_IO_AON_PAD_CTRL1_OUT_EN;
321 pin = (pin << AON_IO_AON_PAD_CTRL1_OUT_EN_POS) & AON_IO_AON_PAD_CTRL1_OUT_EN;
322 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin) == pin) ?
353 uint32_t RTypeMask = (pin_mask << AON_IO_AON_PAD_CTRL0_R_TYPE_POS) & AON_IO_AON_PAD_CTRL0_R_TYPE;
354 uint32_t REnMask = (pin_mask << AON_IO_AON_PAD_CTRL0_R_EN_POS) & AON_IO_AON_PAD_CTRL0_R_EN;
357 MODIFY_REG(AON_IO->AON_PAD_CTRL0, REnMask | RTypeMask, REn | RType);
385 uint32_t RTypeMask = (pin << AON_IO_AON_PAD_CTRL0_R_TYPE_POS) & AON_IO_AON_PAD_CTRL0_R_TYPE;
386 uint32_t REnMask = (pin << AON_IO_AON_PAD_CTRL0_R_EN_POS) & AON_IO_AON_PAD_CTRL0_R_EN;
424 uint32_t pos = POSITION_VAL(pin) << 2;
427 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
431 MODIFY_REG(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
432 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
466 if(READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
468 uint32_t pos = POSITION_VAL(pin) << 2;
469 return (READ_BITS(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
493 MODIFY_REG(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
494 AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_CTL_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
508 CLEAR_BITS(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN);
522 return (READ_BITS(AON_CTL->AON_PAD_CLK, AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_CTL_AON_PAD_CLK_AON_GPIO4_OUT_EN);
536 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
550 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
564 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
584 uint32_t pin_mask = (
LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
585 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) >> AON_IO_AON_PAD_CTRL1_IN_VAL_POS);
609 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_IN_VAL_POS) & AON_IO_AON_PAD_CTRL1_IN_VAL;
610 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
634 pin_mask = (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL;
635 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, pin_mask) == pin_mask);
649 MODIFY_REG(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL, (port_value << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
663 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL1, AON_IO_AON_PAD_CTRL1_OUT_VAL) >> AON_IO_AON_PAD_CTRL1_OUT_VAL_POS);
688 SET_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
712 CLEAR_BITS(AON_IO->AON_PAD_CTRL1, (pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL);
736 WRITE_REG(AON_IO->AON_PAD_CTRL1, (READ_REG(AON_IO->AON_PAD_CTRL1)
737 ^ ((pin_mask << AON_IO_AON_PAD_CTRL1_OUT_VAL_POS) & AON_IO_AON_PAD_CTRL1_OUT_VAL)));
768 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
769 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
770 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
771 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
772 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
773 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
798 uint32_t invert = ((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
799 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
800 uint32_t edge_type = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
801 return (invert && edge_en && edge_type);
826 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
827 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
828 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
829 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
830 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
831 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
857 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
858 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
859 uint32_t edge_type = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
860 return (invert && edge_en && edge_type);
885 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
886 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
887 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
888 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
913 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
914 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
915 return (invert && edge_en );
940 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
941 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
942 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
943 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
968 uint32_t invert = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
969 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
970 return (invert && edge_en);
995 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
996 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
997 SET_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en | both);
1022 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1023 uint32_t edge_both = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1024 return ( edge_en && edge_both);
1049 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1074 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1098 return ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1120 return (READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1152 return (READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1178 return ((READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1204 CLEAR_BITS(AON_IO->EXT_WAKEUP_STAT, pin_mask);
1220 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1234 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);