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10 #ifndef HAL_GDC_REGS_H__
11 #define HAL_GDC_REGS_H__
21 #define HAL_GDC_REG_MODE (0x00U)
22 #define HAL_GDC_REG_CLKCTRL (0x04U)
23 #define HAL_GDC_REG_PLAY (0x10U)
24 #define HAL_GDC_REG_CLKCTRL_CG (0x1a8U)
25 #define HAL_GDC_REG_BGCOLOR (0x08U)
26 #define HAL_GDC_REG_RESXY (0x0cU)
27 #define HAL_GDC_REG_FRONTPORCHXY (0x14U)
28 #define HAL_GDC_REG_BLANKINGXY (0x18U)
29 #define HAL_GDC_REG_BACKPORCHXY (0x1cU)
30 #define HAL_GDC_REG_CURSORXY (0x20U)
31 #define HAL_GDC_REG_STARTXY (0x24U)
32 #define HAL_GDC_REG_DBIB_CFG (0x28U)
33 #define HAL_GDC_REG_GPIO (0x2cU)
35 #define HAL_GDC_REG_LAYER0_MODE (0x30U)
36 #define HAL_GDC_REG_LAYER0_STARTXY (0x34U)
37 #define HAL_GDC_REG_LAYER0_SIZEXY (0x38U)
38 #define HAL_GDC_REG_LAYER0_BASEADDR (0x3cU)
39 #define HAL_GDC_REG_LAYER0_STRIDE (0x40U)
40 #define HAL_GDC_REG_LAYER0_RESXY (0x44U)
41 #define HAL_GDC_REG_LAYER0_SCALEX (0x48U)
42 #define HAL_GDC_REG_LAYER0_SCALEY (0x4cU)
44 #define HAL_GDC_REG_LAYER1_MODE (0x50U)
45 #define HAL_GDC_REG_LAYER1_STARTXY (0x54U)
46 #define HAL_GDC_REG_LAYER1_SIZEXY (0x58U)
47 #define HAL_GDC_REG_LAYER1_BASEADDR (0x5cU)
48 #define HAL_GDC_REG_LAYER1_STRIDE (0x60U)
49 #define HAL_GDC_REG_LAYER1_RESXY (0x64U)
50 #define HAL_GDC_REG_LAYER1_SCALEX (0x68U)
51 #define HAL_GDC_REG_LAYER1_SCALEY (0x6cU)
53 #define HAL_GDC_REG_LAYER2_MODE (0x70U)
54 #define HAL_GDC_REG_LAYER2_STARTXY (0x74U)
55 #define HAL_GDC_REG_LAYER2_SIZEXY (0x78U)
56 #define HAL_GDC_REG_LAYER2_BASEADDR (0x7cU)
57 #define HAL_GDC_REG_LAYER2_STRIDE (0x80U)
58 #define HAL_GDC_REG_LAYER2_RESXY (0x84U)
59 #define HAL_GDC_REG_LAYER2_SCALEX (0x88U)
60 #define HAL_GDC_REG_LAYER2_SCALEY (0x8cU)
62 #define HAL_GDC_REG_LAYER3_MODE (0x90U)
63 #define HAL_GDC_REG_LAYER3_STARTXY (0x94U)
64 #define HAL_GDC_REG_LAYER3_SIZEXY (0x98U)
65 #define HAL_GDC_REG_LAYER3_BASEADDR (0x9cU)
66 #define HAL_GDC_REG_LAYER3_STRIDE (0xa0U)
67 #define HAL_GDC_REG_LAYER3_RESXY (0xa4U)
68 #define HAL_GDC_REG_LAYER3_SCALEX (0xa8U)
69 #define HAL_GDC_REG_LAYER3_SCALEY (0xacU)
71 #define HAL_GDC_REG_LAYER0_UBASE (0xd0U)
72 #define HAL_GDC_REG_LAYER0_VBASE (0xd4U)
73 #define HAL_GDC_REG_LAYER0_UVSTRIDE (0xd8U)
74 #define HAL_GDC_REG_LAYER1_UBASE (0xdcU)
75 #define HAL_GDC_REG_LAYER1_VBASE (0xe0U)
76 #define HAL_GDC_REG_LAYER1_UVSTRIDE (0xe4U)
77 #define HAL_GDC_REG_LAYER2_UBASE (0x188U)
78 #define HAL_GDC_REG_LAYER2_VBASE (0x18cU)
79 #define HAL_GDC_REG_LAYER2_UVSTRIDE (0x190U)
80 #define HAL_GDC_REG_LAYER3_UBASE (0x194U)
81 #define HAL_GDC_REG_LAYER3_VBASE (0x198U)
82 #define HAL_GDC_REG_LAYER3_UVSTRIDE (0x19cU)
84 #define HAL_GDC_REG_DBIB_CMD (0xe8U)
85 #define HAL_GDC_REG_DBIB_RDAT (0xecU)
86 #define HAL_GDC_REG_CONFIG (0xf0U)
87 #define HAL_GDC_REG_IDREG (0xf4U)
88 #define HAL_GDC_REG_INTERRUPT (0xf8U)
89 #define HAL_GDC_REG_STATUS (0xfcU)
90 #define HAL_GDC_REG_COLMOD (0x100U)
91 #define HAL_GDC_REG_CRC (0x184U)
93 #define HAL_GDC_REG_FORMAT_CTRL (0x1a0U)
94 #define HAL_GDC_REG_FORMAT_CTRL2 (0x1a4U)
95 #define HAL_GDC_REG_FORMAT_CTRL3 (0x1acU)
96 #define HAL_GDC_REG_PALETTE (0x400U)
97 #define HAL_GDC_REG_CURSOR_IMAGE (0x800U)
98 #define HAL_GDC_REG_CURSOR_LUT (0xA00U)
99 #define HAL_GDC_REG_GAMMALUT_0 (0x1000U)
100 #define HAL_GDC_REG_GAMMALUT_1 (0x1400U)
101 #define HAL_GDC_REG_GAMMALUT_2 (0x1800U)
102 #define HAL_GDC_REG_GAMMALUT_3 (0x1c00U)
104 #define HAL_GDC_REG_LAYER_MODE(i) (0x030 + 0x20*(i))
105 #define HAL_GDC_REG_LAYER_STARTXY(i) (0x034 + 0x20*(i))
106 #define HAL_GDC_REG_LAYER_SIZEXY(i) (0x038 + 0x20*(i))
107 #define HAL_GDC_REG_LAYER_BASEADDR(i) (0x03c + 0x20*(i))
108 #define HAL_GDC_REG_LAYER_STRIDE(i) (0x040 + 0x20*(i))
109 #define HAL_GDC_REG_LAYER_RESXY(i) (0x044 + 0x20*(i))
110 #define HAL_GDC_REG_LAYER_SCALEX(i) (0x048 + 0x20*(i))
111 #define HAL_GDC_REG_LAYER_SCALEY(i) (0x04c + 0x20*(i))
112 #define HAL_GDC_REG_GAMMALUT(i) (0x1000+ 0x400*(i))