52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
62 #if defined (DMA) || defined (DMA0) || defined (DMA1)
158 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
159 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
160 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
161 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
162 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
163 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
164 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
165 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
166 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
172 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
173 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
174 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
175 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
182 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U)
183 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC
184 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST
185 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST)
191 #define LL_DMA_LLP_DST_ENABLE DMA_CTLL_LLP_DST_EN_ENABLE
192 #define LL_DMA_LLP_DST_DISABLE DMA_CTLL_LLP_DST_EN_DISABLE
198 #define LL_DMA_LLP_SRC_ENABLE DMA_CTLL_LLP_SRC_EN_ENABLE
199 #define LL_DMA_LLP_SRC_DISABLE DMA_CTLL_LLP_SRC_EN_DISABLE
205 #define LL_DMA_SRC_STAT_UPDATE_ENABLE DMA_CFGH_SS_UPD_ENABLE
206 #define LL_DMA_SRC_STAT_UPDATE_DISABLE DMA_CFGH_SS_UPD_DISABLE
212 #define LL_DMA_DST_STAT_UPDATE_ENABLE DMA_CFGH_DS_UPD_ENABLE
213 #define LL_DMA_DST_STAT_UPDATE_DISABLE DMA_CFGH_DS_UPD_DISABLE
219 #define LL_DMA_DST_SCATTER_ENABLE DMA_CTLL_DST_SCATTER_EN_ENABLE
220 #define LL_DMA_DST_SCATTER_DISABLE DMA_CTLL_DST_SCATTER_EN_DISABLE
226 #define LL_DMA_SRC_GATHER_ENABLE DMA_CTLL_SRC_GATHER_EN_ENABLE
227 #define LL_DMA_SRC_GATHER_DISABLE DMA_CTLL_SRC_GATHER_EN_DISABLE
234 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
235 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
236 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
242 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
243 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
244 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
250 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
251 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
252 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
253 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
254 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
255 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
261 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
262 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
263 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
264 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
265 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
266 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
272 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
273 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
274 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
280 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
281 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
282 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
288 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
289 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
290 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
291 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
292 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
293 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
294 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
295 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
301 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
302 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
308 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
309 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
316 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU)
319 #define LL_DMA0_PERIPH_QSPI0_TX ((uint32_t)0x00000000U)
320 #define LL_DMA0_PERIPH_QSPI0_RX ((uint32_t)0x00000001U)
321 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U)
322 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U)
323 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U)
324 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U)
325 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U)
326 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U)
327 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U)
328 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U)
329 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU)
330 #define LL_DMA0_PERIPH_OSPI_TX ((uint32_t)0x0000000CU)
331 #define LL_DMA0_PERIPH_OSPI_RX ((uint32_t)0x0000000DU)
332 #define LL_DMA0_PERIPH_UART2_TX ((uint32_t)0x0000000EU)
333 #define LL_DMA0_PERIPH_UART2_RX ((uint32_t)0x0000000FU)
336 #define LL_DMA0_PERIPH_I2C2_TX ((uint32_t)0x00000012U)
337 #define LL_DMA0_PERIPH_I2C2_RX ((uint32_t)0x00000013U)
338 #define LL_DMA0_PERIPH_UART3_TX ((uint32_t)0x00000014U)
339 #define LL_DMA0_PERIPH_UART3_RX ((uint32_t)0x00000015U)
340 #define LL_DMA0_PERIPH_I2C5_TX ((uint32_t)0x00000016U)
341 #define LL_DMA0_PERIPH_I2C5_RX ((uint32_t)0x00000017U)
342 #define LL_DMA0_PERIPH_I2C4_TX ((uint32_t)0x00000018U)
343 #define LL_DMA0_PERIPH_I2C4_RX ((uint32_t)0x00000019U)
344 #define LL_DMA0_PERIPH_UART4_TX ((uint32_t)0x0000001AU)
345 #define LL_DMA0_PERIPH_UART4_RX ((uint32_t)0x0000001BU)
346 #define LL_DMA0_PERIPH_QSPI1_TX ((uint32_t)0x0000001CU)
347 #define LL_DMA0_PERIPH_QSPI1_RX ((uint32_t)0x0000001DU)
348 #define LL_DMA0_PERIPH_I2C3_TX ((uint32_t)0x0000001EU)
349 #define LL_DMA0_PERIPH_I2C3_RX ((uint32_t)0x0000001FU)
352 #define LL_DMA1_PERIPH_MEM ((uint32_t)0x00000009U)
355 #define LL_DMA1_PERIPH_OSPI_TX ((uint32_t)0x00000000U)
356 #define LL_DMA1_PERIPH_OSPI_RX ((uint32_t)0x00000001U)
357 #define LL_DMA1_PERIPH_QSPI2_TX ((uint32_t)0x00000002U)
358 #define LL_DMA1_PERIPH_QSPI2_RX ((uint32_t)0x00000003U)
359 #define LL_DMA1_PERIPH_I2S_M_TX ((uint32_t)0x00000004U)
360 #define LL_DMA1_PERIPH_I2S_M_RX ((uint32_t)0x00000005U)
361 #define LL_DMA1_PERIPH_I2S_S_TX ((uint32_t)0x00000006U)
362 #define LL_DMA1_PERIPH_I2S_S_RX ((uint32_t)0x00000007U)
363 #define LL_DMA1_PERIPH_PDM_TX ((uint32_t)0x00000008U)
364 #define LL_DMA1_PERIPH_QSPI1_TX ((uint32_t)0x0000000AU)
365 #define LL_DMA1_PERIPH_QSPI1_RX ((uint32_t)0x0000000BU)
367 #define LL_DMA1_PERIPH_I2C0_TX ((uint32_t)0x0000000CU)
368 #define LL_DMA1_PERIPH_I2C0_RX ((uint32_t)0x0000000DU)
369 #define LL_DMA1_PERIPH_I2C1_TX ((uint32_t)0x0000000EU)
370 #define LL_DMA1_PERIPH_I2C1_RX ((uint32_t)0x0000000FU)
373 #define LL_DMA1_PERIPH_SPIM_TX ((uint32_t)0x00000010U)
374 #define LL_DMA1_PERIPH_SPIM_RX ((uint32_t)0x00000011U)
375 #define LL_DMA1_PERIPH_DSPIM_TX ((uint32_t)0x00000012U)
376 #define LL_DMA1_PERIPH_DSPIM_RX ((uint32_t)0x00000013U)
377 #define LL_DMA1_PERIPH_QSPI1_TX_2 ((uint32_t)0x00000014U)
378 #define LL_DMA1_PERIPH_QSPI1_RX_2 ((uint32_t)0x00000015U)
379 #define LL_DMA1_PERIPH_UART3_TX ((uint32_t)0x00000016U)
380 #define LL_DMA1_PERIPH_UART3_RX ((uint32_t)0x00000017U)
381 #define LL_DMA1_PERIPH_UART4_TX ((uint32_t)0x00000018U)
382 #define LL_DMA1_PERIPH_UART4_RX ((uint32_t)0x00000019U)
383 #define LL_DMA1_PERIPH_UART5_TX ((uint32_t)0x0000001AU)
384 #define LL_DMA1_PERIPH_UART5_RX ((uint32_t)0x0000001BU)
385 #define LL_DMA1_PERIPH_UART0_TX ((uint32_t)0x0000001EU)
386 #define LL_DMA1_PERIPH_UART0_RX ((uint32_t)0x0000001FU)
408 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
416 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
447 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
466 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
481 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
507 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
531 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
557 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
583 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
608 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
632 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
656 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
695 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
696 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
725 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
753 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
782 __STATIC_INLINE
void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
784 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
813 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
839 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
865 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
891 MODIFY_REG(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT, sstat);
917 return READ_BITS(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT);
943 MODIFY_REG(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT, dstat);
968 return READ_BITS(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT);
994 MODIFY_REG(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR, sstatar);
1019 return READ_BITS(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR);
1045 MODIFY_REG(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR, dstatar);
1070 return READ_BITS(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR);
1096 MODIFY_REG(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC, llp_loc);
1121 return READ_BITS(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC);
1148 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN, llp_dst_en);
1174 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN);
1201 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN, llp_src_en);
1227 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN);
1254 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN, dst_scatter_en);
1280 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN);
1307 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN, src_gather_en);
1333 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN);
1361 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
1388 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
1416 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
1443 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
1471 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
1498 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
1526 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1553 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1581 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1608 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1636 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1663 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1696 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1728 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1754 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1780 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1814 uint32_t src_address,
1815 uint32_t dst_address,
1818 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1819 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1820 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1845 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1870 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1894 return READ_REG(DMAx->CHANNEL[channel].SAR);
1918 return READ_REG(DMAx->CHANNEL[channel].DAR);
1944 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1945 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1972 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1973 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1998 return READ_REG(DMAx->CHANNEL[channel].SAR);
2023 return READ_REG(DMAx->CHANNEL[channel].DAR);
2250 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
2273 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
2356 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
2379 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
2409 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
2410 src_handshaking | dst_handshaking);
2436 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI, src_gather_sgi << DMA_SGR_SGI_Pos );
2461 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI) >> DMA_SGR_SGI_Pos);
2487 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC, src_gather_sgc << DMA_SGR_SGC_Pos );
2512 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC) >> DMA_SGR_SGC_Pos);
2538 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI, dst_scatter_dsi << DMA_DSR_DSI_Pos );
2563 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI) >> DMA_DSR_DSI_Pos);
2589 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC, dst_scatter_dsc << DMA_DSR_DSC_Pos );
2614 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC) >> DMA_DSR_DSC_Pos);
2639 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2640 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2664 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2690 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2691 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2692 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2717 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2718 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2743 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2744 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2768 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2794 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2795 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2796 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2821 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2822 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2843 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2858 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2873 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2888 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2903 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2927 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2951 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2975 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2999 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
3023 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
3047 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
3062 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
3077 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
3092 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
3107 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
3122 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
3137 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
3152 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
3167 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
3191 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
3206 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
3221 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
3236 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
3251 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
3266 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
3281 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
3296 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
3311 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
3335 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
3350 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
3365 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
3380 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
3395 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
3410 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
3425 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
3440 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
3455 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
3479 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
3494 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
3509 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
3524 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
3539 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
3554 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
3569 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
3584 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
3599 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
3623 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3638 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3653 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3668 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3683 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3698 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3713 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3728 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3743 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3767 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3782 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3797 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3812 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3827 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3842 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3857 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3872 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3887 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3911 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3926 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3941 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3956 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3971 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3986 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
4001 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
4016 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
4031 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
4055 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
4070 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
4085 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
4100 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
4115 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
4130 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
4145 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
4160 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
4175 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
4199 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
4214 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
4229 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
4244 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
4259 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
4274 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
4289 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
4304 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
4319 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
4343 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
4358 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
4373 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
4388 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
4403 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4418 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4433 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4448 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4463 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4493 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4517 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4541 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4565 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4589 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4613 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4637 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4661 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4685 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4709 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4733 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4757 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4781 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4805 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4829 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4853 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4877 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
4901 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
4964 error_status_t
ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral);