Macros | |
#define | MIPICFG_DBI_EN (1U<<31U) |
#define | MIPICFG_FRC_CSX_0 (1U<<30U) |
#define | MIPICFG_FRC_CSX_1 ((1U<<30U)|(1U<<29U)) |
#define | MIPICFG_SPI_CSX_V (1U<<29U) |
#define | MIPICFG_DIS_TE (1U<<28U) |
#define | MIPICFG_SPIDC_DQSPI (1U<<27U) |
#define | MIPICFG_RSTN_DBI_SPI (1U<<26U) |
#define | MIPICFG_RESX (1U<<25U) |
#define | MIPICFG_DMA (1U<<24U) |
#define | MIPICFG_SPI3 (1U<<23U) |
#define | MIPICFG_SPI4 (1U<<22U) |
#define | MIPICFG_GPI ((1U<<23U)|(1U<<22U)) |
#define | MIPICFG_EN_STALL (1U<<21U) |
#define | MIPICFG_SPI_CPHA (1U<<20U) |
#define | MIPICFG_SPI_CPOL (1U<<19U) |
#define | MIPICFG_SPI_JDI (1U<<18U) |
#define | MIPICFG_EN_DVALID (1U<<18U) |
#define | MIPICFG_SPI_HOLD (1U<<17U) |
#define | MIPICFG_INV_ADDR (1U<<16U) |
#define | MIPICFG_SCAN_ADDR (1U<<15U) |
#define | MIPICFG_PIXCLK_OUT_EN (1U<<14U) |
#define | MIPICFG_EXT_CTRL (1U<<13U) |
#define | MIPICFG_BLANKING_EN (1U<<12U) |
#define | MIPICFG_DSPI_SPIX (1U<<11U) |
#define | MIPICFG_QSPI (1U<<10U) |
#define | MIPICFG_QSPI_DDR ((1U<<10U)|(1U<<9U)) |
#define | MIPICFG_DSPI (1U<< 9U) |
#define | MIPICFG_SPI (0U<< 9U) |
#define | MIPICFG_NULL (0x00U) |
#define MIPICFG_BLANKING_EN (1U<<12U) |
Enables horizontal blanking
Definition at line 46 of file hal_gdc_mipi.h.
#define MIPICFG_DBI_EN (1U<<31U) |
Enables MIPI DBI/SPI interface
Definition at line 24 of file hal_gdc_mipi.h.
#define MIPICFG_DIS_TE (1U<<28U) |
Disables Input Tearing Signal
Definition at line 28 of file hal_gdc_mipi.h.
#define MIPICFG_DMA (1U<<24U) |
(unused) Enables pixel data from DMA
Definition at line 32 of file hal_gdc_mipi.h.
#define MIPICFG_DSPI (1U<< 9U) |
Enables DSPI
Definition at line 50 of file hal_gdc_mipi.h.
#define MIPICFG_DSPI_SPIX (1U<<11U) |
Enables DSPI sub-pixel transaction
Definition at line 47 of file hal_gdc_mipi.h.
#define MIPICFG_EN_DVALID (1U<<18U) |
Enables read using external data valid signal
Definition at line 40 of file hal_gdc_mipi.h.
#define MIPICFG_EN_STALL (1U<<21U) |
Enables back-pressure from dbi_stall_i signal
Definition at line 36 of file hal_gdc_mipi.h.
#define MIPICFG_EXT_CTRL (1U<<13U) |
Enables external control signals
Definition at line 45 of file hal_gdc_mipi.h.
#define MIPICFG_FRC_CSX_0 (1U<<30U) |
Enables CSX force value
Definition at line 25 of file hal_gdc_mipi.h.
#define MIPICFG_FRC_CSX_1 ((1U<<30U)|(1U<<29U)) |
Force CSX to 1
Definition at line 26 of file hal_gdc_mipi.h.
#define MIPICFG_GPI ((1U<<23U)|(1U<<22U)) |
Enables Generic Packet Interface
Definition at line 35 of file hal_gdc_mipi.h.
#define MIPICFG_INV_ADDR (1U<<16U) |
Inverts scanline address
Definition at line 42 of file hal_gdc_mipi.h.
#define MIPICFG_NULL (0x00U) |
MIPI CFG NULL
Definition at line 52 of file hal_gdc_mipi.h.
#define MIPICFG_PIXCLK_OUT_EN (1U<<14U) |
Redirects pixel generation clock to the output
Definition at line 44 of file hal_gdc_mipi.h.
#define MIPICFG_QSPI (1U<<10U) |
Enables QSPI
Definition at line 48 of file hal_gdc_mipi.h.
#define MIPICFG_QSPI_DDR ((1U<<10U)|(1U<<9U)) |
Enables QSPI DDR
Definition at line 49 of file hal_gdc_mipi.h.
#define MIPICFG_RESX (1U<<25U) |
Controls MIPI DBI Type-B RESX output signal
Definition at line 31 of file hal_gdc_mipi.h.
#define MIPICFG_RSTN_DBI_SPI (1U<<26U) |
DBI/SPI interfaces clear
Definition at line 30 of file hal_gdc_mipi.h.
#define MIPICFG_SCAN_ADDR (1U<<15U) |
Scan address used as header of each line
Definition at line 43 of file hal_gdc_mipi.h.
#define MIPICFG_SPI (0U<< 9U) |
Enables SPI
Definition at line 51 of file hal_gdc_mipi.h.
#define MIPICFG_SPI3 (1U<<23U) |
Enables SPI 3-wire interface
Definition at line 33 of file hal_gdc_mipi.h.
#define MIPICFG_SPI4 (1U<<22U) |
Enables SPI 4-wire interface
Definition at line 34 of file hal_gdc_mipi.h.
#define MIPICFG_SPI_CPHA (1U<<20U) |
Sets SPI Clock Phase
Definition at line 37 of file hal_gdc_mipi.h.
#define MIPICFG_SPI_CPOL (1U<<19U) |
Sets SPI Clock Polarity
Definition at line 38 of file hal_gdc_mipi.h.
#define MIPICFG_SPI_CSX_V (1U<<29U) |
CSX active high/low
Definition at line 27 of file hal_gdc_mipi.h.
#define MIPICFG_SPI_HOLD (1U<<17U) |
Binds scanline address with pixel data
Definition at line 41 of file hal_gdc_mipi.h.
#define MIPICFG_SPI_JDI (1U<<18U) |
– reserved –
Definition at line 39 of file hal_gdc_mipi.h.
#define MIPICFG_SPIDC_DQSPI (1U<<27U) |
Enables the usage of SPI_DC wire as SPI_SD1
Definition at line 29 of file hal_gdc_mipi.h.