52 #ifndef __GR55XX_LL_ADC_H__
53 #define __GR55XX_LL_ADC_H__
128 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos)
129 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos)
130 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos)
131 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos)
132 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos)
133 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos)
134 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos)
135 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos)
142 #define LL_ADC_REF_VALUE_0P8 (0x3UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
143 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
144 #define LL_ADC_REF_VALUE_1P6 (0xAUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
145 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
151 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos)
152 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL)
158 #define LL_ADC_INPUT_SRC_IO0 (0UL)
159 #define LL_ADC_INPUT_SRC_IO1 (1UL)
160 #define LL_ADC_INPUT_SRC_IO2 (2UL)
161 #define LL_ADC_INPUT_SRC_IO3 (3UL)
162 #define LL_ADC_INPUT_SRC_IO4 (4UL)
163 #define LL_ADC_INPUT_SRC_IO5 (5UL)
164 #define LL_ADC_INPUT_SRC_IO6 (6UL)
165 #define LL_ADC_INPUT_SRC_IO7 (7UL)
166 #define LL_ADC_INPUT_SRC_TMP (13UL)
167 #define LL_ADC_INPUT_SRC_BAT (14UL)
168 #define LL_ADC_INPUT_SRC_REF (15UL)
176 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL)
177 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
178 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
179 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
180 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
202 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
210 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
232 #define LL_ADC_DEFAULT_CONFIG \
234 .channel_p = LL_ADC_INPUT_SRC_IO0, \
235 .channel_n = LL_ADC_INPUT_SRC_IO1, \
236 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
237 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
238 .ref_value = LL_ADC_REF_VALUE_1P2, \
239 .clock = LL_ADC_CLK_16M \
242 #define LL_ADC_DEFAULT_CONFIG \
244 .channel_p = LL_ADC_INPUT_SRC_IO0, \
245 .channel_n = LL_ADC_INPUT_SRC_IO1, \
246 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
247 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
248 .ref_value = LL_ADC_REF_VALUE_1P2, \
249 .clock = LL_ADC_CLK_16 \
279 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
295 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
311 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
327 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
343 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
367 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
390 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
411 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
431 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
447 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
463 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
479 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
495 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
511 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
527 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
546 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
564 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk) >> AON_PMU_SNSADC_CFG_SINGLE_EN_Pos);
582 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
598 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
614 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
632 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
648 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
672 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
695 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
719 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
742 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
758 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
774 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
790 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
812 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
833 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
852 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
868 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
890 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
905 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
919 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
934 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
950 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
967 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
982 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
996 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
1010 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
1024 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
1038 CLEAR_BITS(MCU_SUB->SENSE_ADC_RET_TKN_SW, MCU_SUB_SNSADC_RET_TKN_SW_RELEASE_Msk);
1052 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);