52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
62 #if defined (AON_CTL) && defined (AON_IO)
76 #define LL_PWR_WKUP_COND_EXT AON_CTL_MCU_WAKEUP_CTRL_EXT
77 #define LL_PWR_WKUP_COND_TIMER AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER
78 #define LL_PWR_WKUP_COND_BLE AON_CTL_MCU_WAKEUP_CTRL_SMS_OSC
79 #define LL_PWR_WKUP_COND_CLDR AON_CTL_MCU_WAKEUP_CTRL_RTC0
80 #define LL_PWR_WKUP_COND_CLDR_TICK AON_CTL_MCU_WAKEUP_CTRL_RTC1
81 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_CTL_MCU_WAKEUP_CTRL_PMU_BOD
82 #define LL_PWR_WKUP_COND_AUSB AON_CTL_MCU_WAKEUP_CTRL_USB_ATTACH
83 #define LL_PWR_WKUP_COND_DUSB AON_CTL_MCU_WAKEUP_CTRL_USB_DETACH
84 #define LL_PWR_WKUP_COND_BLE_IRQ AON_CTL_MCU_WAKEUP_CTRL_BLE_IRQ
85 #define LL_PWR_WKUP_COND_AON_WDT AON_CTL_MCU_WAKEUP_CTRL_AON_WDT
86 #define LL_PWR_WKUP_COND_COMP AON_CTL_MCU_WAKEUP_CTRL_PMU_COMP
87 #define LL_PWR_WKUP_COND_ALL (0xFFFU << AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER_Pos)
95 #define LL_PWR_WKUP_EVENT_BLE AON_CTL_SLP_EVENT_SMS_OSC
96 #define LL_PWR_WKUP_EVENT_TIMER AON_CTL_SLP_EVENT_SLP_TIMER
97 #define LL_PWR_WKUP_EVENT_EXT AON_CTL_SLP_EVENT_EXT
98 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_CTL_SLP_EVENT_PMU_BOD
99 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_CTL_SLP_EVENT_PMU_MSIO
100 #define LL_PWR_WKUP_EVENT_WDT AON_CTL_SLP_EVENT_AON_WDT
101 #define LL_PWR_WKUP_EVENT_CLDR AON_CTL_SLP_EVENT_RTC0
102 #define LL_PWR_WKUP_EVENT_AUSB AON_CTL_SLP_EVENT_USB_ATTACH
103 #define LL_PWR_WKUP_EVENT_DUSB AON_CTL_SLP_EVENT_USB_DETACH
104 #define LL_PWR_WKUP_EVENT_CLDR_TICK AON_CTL_SLP_EVENT_RTC1
105 #define LL_PWR_WKUP_EVENT_BLE_IRQ AON_CTL_SLP_EVENT_BLE_IRQ
106 #define LL_PWR_WKUP_EVENT_ALL (0xFFFU << AON_CTL_SLP_EVENT_SLP_TIMER_Pos)
112 #define LL_PWR_DPAD_LE_OFF (0x00000000U)
113 #define LL_PWR_DPAD_LE_ON (0x00000001U)
152 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
178 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
248 WRITE_REG(SLP_TIMER->TIMER_W, value);
262 return READ_REG(SLP_TIMER->TIMER_R);
278 SET_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
293 CLEAR_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
307 return (READ_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ) == AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
328 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_SLEEP, (sleep << AON_PWR_DPAD_LE_CTRL_SLEEP_Pos));
329 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_WAKEUP, (wakeup << AON_PWR_DPAD_LE_CTRL_WAKEUP_Pos));
351 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
366 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
380 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N) == 0x0U));
397 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
412 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
426 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_RST_N_RD) == 0x0U));
441 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
442 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
443 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
458 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
459 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
460 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
475 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN) == AON_PWR_COMM_TIMER_PWR_CTRL_EN));
490 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
491 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
506 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
507 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
522 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD) == AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD));
536 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
551 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
565 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN));
579 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
594 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
608 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN));
623 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
638 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
652 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON));
668 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ);
683 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ));
698 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
713 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
727 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
742 WRITE_REG(AON_CTL->COMM_TIMER_CFG0, time);
756 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG0));
770 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_STAT));
791 WRITE_REG(AON_CTL->COMM_TIMER_CFG1, (twext << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWEXT_Pos) |
792 (twosc << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos) |
793 (twrm << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWRM_Pos));
809 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1));
819 return ((((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1) & AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Msk)) >> AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos);
849 return ((uint32_t)(READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) >> AON_IO_EXT_WAKEUP_STAT_STAT_POS));
873 WRITE_REG(AON_IO->EXT_WAKEUP_STAT, ~(wakeup_pin << AON_IO_EXT_WAKEUP_STAT_STAT_POS));
915 return (READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT);
930 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
931 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
946 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DCDC, (value << AON_PWR_A_TIMING_CTRL0_DCDC_Pos));
961 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DIG_LDO, (value << AON_PWR_A_TIMING_CTRL0_DIG_LDO_Pos));
977 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_FAST_LDO, (value << AON_PWR_A_TIMING_CTRL1_FAST_LDO_Pos));
992 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_HF_OSC, (value << AON_PWR_A_TIMING_CTRL1_HF_OSC_Pos));
1007 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL_LOCK, (value << AON_PWR_A_TIMING_CTRL2_PLL_LOCK_Pos));
1022 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL, (value << AON_PWR_A_TIMING_CTRL2_PLL_Pos));
1037 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_PWR_SWITCH, (value << AON_PWR_A_TIMING_CTRL3_PWR_SWITCH_Pos));
1052 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_XO, (value << AON_PWR_A_TIMING_CTRL3_XO_Pos));
1067 MODIFY_REG(AON_PWR->A_TIMING_CTRL4, AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH, (value << AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH_Pos));
1081 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_MCU_PWR_TYPE);
1095 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_DCDC_OFF);
1109 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_LDO_OFF);
1123 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1136 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);