gr55xx_ll_bod.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr55xx_ll_bod.h
5  * @author BLE Driver Team
6  * @brief Header file containing functions prototypes of CALENDAR LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_BOD BOD
47  * @brief BOD LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_BOD_H_
53 #define __GR55XX_LL_BOD_H_
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr55xx.h"
61 
62 /** @defgroup BOD_LL_STRUCTURES Structures
63  * @{
64  */
65 
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup BOD_LL_ES_INIT BOD Exported init structures
68  * @{
69  */
70 
71 /**
72  * @brief LL BOD init Structure definition
73  */
74 typedef struct _ll_bod_init
75 {
76  uint8_t bod_en; /**< Specifies the bod enable.
77 
78  This parament can be modified afterwards using unitary function @ref ll_bod_enable() and ll_bod_disable(). */
79 
80  uint8_t bod2_en; /**< Specifies the bod2 enable.
81 
82  This parament can be modified afterwards using unitary function @ref ll_bod2_enable() and ll_bod2_disable().. */
83 
84  uint8_t bod2_lvl; /**< Specifies the bod2 level.
85  This parameter can be a value of ADC_LL_EC_INPUT_MODE.
86 
87  This parament can be modified afterwards using unitary function @ref ll_bod2_lvl_ctrl_lv_set(). */
89 
90 /** @} */
91 
92 /** @} */
93 
94 /**
95  * @defgroup BOD_LL_MACRO Defines
96  * @{
97  */
98 
99 /* Exported constants --------------------------------------------------------*/
100 /** @defgroup BOD_LL_Exported_Constants BOD Exported Constants
101  * @{
102  */
103 
104 /** @defgroup BOD_LL_ENABLE BOD ENABLE
105  * @{
106  */
107 #define LL_BOD_ENABLE 0x1 /**< BOD enable */
108 #define LL_BOD_DISABLE 0x0 /**< BOD disable */
109 /** @} */
110 
111 /** @defgroup BOD2_LL_ENABLE BOD2 ENABLE
112  * @{
113  */
114 #define LL_BOD2_ENABLE 0x1 /**< BOD2 enable */
115 #define LL_BOD2_DISABLE 0x0 /**< BOD2 disable */
116 /** @} */
117 
118 /** @defgroup BOD2_LL_LEVEL BOD2 LVEVL
119  * @{
120  */
121 #define LL_BOD2_LEVEL_0 0x0 /**< BOD2 Level 0 */
122 #define LL_BOD2_LEVEL_1 0x1 /**< BOD2 Level 1 */
123 #define LL_BOD2_LEVEL_2 0x2 /**< BOD2 Level 2 */
124 #define LL_BOD2_LEVEL_3 0x3 /**< BOD2 Level 3 */
125 #define LL_BOD2_LEVEL_4 0x4 /**< BOD2 Level 4 */
126 #define LL_BOD2_LEVEL_5 0x5 /**< BOD2 Level 5 */
127 #define LL_BOD2_LEVEL_6 0x6 /**< BOD2 Level 6 */
128 #define LL_BOD2_LEVEL_7 0x7 /**< BOD2 Level 7 */
129 #define LL_BOD2_LEVEL_8 0x8 /**< BOD2 Level 8 */
130 #define LL_BOD2_LEVEL_9 0x9 /**< BOD2 Level 9 */
131 #define LL_BOD2_LEVEL_10 0xA /**< BOD2 Level 10 */
132 #define LL_BOD2_LEVEL_11 0xB /**< BOD2 Level 11 */
133 #define LL_BOD2_LEVEL_12 0xC /**< BOD2 Level 12 */
134 #define LL_BOD2_LEVEL_13 0xD /**< BOD2 Level 13 */
135 #define LL_BOD2_LEVEL_14 0xE /**< BOD2 Level 14 */
136 #define LL_BOD2_LEVEL_15 0xF /**< BOD2 Level 15 */
137 /** @} */
138 
139 /** @} */
140 
141 /** @} */
142 
143 /** @defgroup BOD_LL_DRIVER_FUNCTIONS Functions
144  * @{
145  */
146 /**
147  * @brief Enable the bod
148  *
149  * Register|BitsName
150  * --------|--------
151  * RF_REG_3 | bod_en_lv
152  *
153  */
154 __STATIC_INLINE void ll_bod_enable(void)
155 {
156 #if defined(BIT_BAND_SUPPORT)
157  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 1;
158 #else
159  SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
160 #endif
161 }
162 
163 /**
164  * @brief Disable the bod
165  *
166  * Register|BitsName
167  * --------|--------
168  * RF_REG_3 | bod_en_lv
169  *
170  */
171 __STATIC_INLINE void ll_bod_disable(void)
172 {
173 #if defined(BIT_BAND_SUPPORT)
174  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 0;
175 #else
176  CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
177 #endif
178 }
179 
180 /**
181  * @brief Enable the bod2
182  *
183  * Register|BitsName
184  * --------|--------
185  * RF_REG_3 | bod2_en_lv
186  *
187  */
188 __STATIC_INLINE void ll_bod2_enable(void)
189 {
190 #if defined(BIT_BAND_SUPPORT)
191  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 1;
192 #else
193  SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
194 #endif
195 }
196 
197 /**
198  * @brief Disable the bod2
199  *
200  * Register|BitsName
201  * --------|--------
202  * RF_REG_3 | bod2_en_lv
203  *
204  */
205 __STATIC_INLINE void ll_bod2_disable(void)
206 {
207 #if defined(BIT_BAND_SUPPORT)
208  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 0;
209 #else
210  CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
211 #endif
212 }
213 
214 /**
215  * @brief Set bod control level
216  *
217  * Register|BitsName
218  * --------|--------
219  * RF_REG_3 | bod_lvl_ctrl_lv_3_0
220  * @param lvl_ctrl_lv: 0x0 ~ 0xF
221  */
222 __STATIC_INLINE void ll_bod2_lvl_ctrl_lv_set(uint8_t lvl_ctrl_lv)
223 {
224 #if defined(BIT_BAND_SUPPORT)
225  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos) = (lvl_ctrl_lv & 0x01);
226  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+1) = ((lvl_ctrl_lv>>1) & 0x01);
227  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+2) = ((lvl_ctrl_lv>>2) & 0x01);
228  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+3) = ((lvl_ctrl_lv>>3) & 0x01);
229 #else
230  MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV, (lvl_ctrl_lv << AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos));
231 #endif
232 }
233 
234 /**
235  * @brief enable bod static lv
236  *
237  * Register|BitsName
238  * --------|--------
239  * RF_REG_3 | bod_static_lv
240  */
241 __STATIC_INLINE void ll_bod_static_lv_enable(void)
242 {
243 #if defined(BIT_BAND_SUPPORT)
244  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 1;
245 #else
246  SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
247 #endif
248 }
249 
250 /**
251  * @brief disable bod static lv
252  *
253  * Register|BitsName
254  * --------|--------
255  * RF_REG_3 | bod_static_lv
256  */
257 __STATIC_INLINE void ll_bod_static_lv_disable(void)
258 {
259 #if defined(BIT_BAND_SUPPORT)
260  BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 0;
261 #else
262  CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
263 #endif
264 }
265 
266 /**
267  * @brief enable BOD FEDGE Event.
268  *
269  * Register|BitsName
270  * --------|--------
271  * AON_IRQ | PMU_BOD_FEDGE
272  *
273  * @retval State of bit (1 or 0).
274  */
275 __STATIC_INLINE void ll_bod_enable_fedge(void)
276 {
277  SET_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
278 }
279 
280 /**
281  * @brief disable BOD FEDGE Event.
282  *
283  * Register|BitsName
284  * --------|--------
285  * AON_IRQ | PMU_BOD_FEDGE
286  *
287  * @retval State of bit (1 or 0).
288  */
289 __STATIC_INLINE void ll_bod_disable_fedge(void)
290 {
291  CLEAR_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
292 }
293 
294 
295 /**
296  * @brief Indicate if the BOD REDGE Event Flag is set or not.
297  *
298  * Register|BitsName
299  * --------|--------
300  * AON_IRQ | PMU_BOD_REDGE
301  *
302  * @retval State of bit (1 or 0).
303  */
304 __STATIC_INLINE uint32_t ll_bod_is_active_flag_fedge(void)
305 {
306  return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD) == AON_CTL_AON_IRQ_PMU_BOD);
307 }
308 
309 /**
310  * @brief Clear Interrupt Status flag.
311  *
312  * Register|BitsName
313  * --------|--------
314  * AON_IRQ| PMU_BOD_REDGE
315  *
316  * @retval None
317  */
318 __STATIC_INLINE void ll_bod_clear_flag_fedge(void)
319 {
320  WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD);
321 }
322 
323 /**
324  * @brief Indicate if the BOD FEDGE Event Flag is set or not.
325  *
326  * Register|BitsName
327  * --------|--------
328  * SLP_EVENT | SLP_EVENT_BOD
329  *
330  * @retval State of bit (1 or 0).
331  */
332 __STATIC_INLINE uint32_t ll_bod_is_active_flag_redge(void)
333 {
334  return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_PMU_BOD) == AON_CTL_SLP_EVENT_PMU_BOD);
335 }
336 
337 /**
338  * @brief Clear Interrupt Status flag.
339  *
340  * Register|BitsName
341  * --------|--------
342  * SLP_EVENT| SLP_EVENT_BOD
343  *
344  * @retval None
345  */
346 __STATIC_INLINE void ll_bod_clear_flag_redge(void)
347 {
348  WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_PMU_BOD);
349 }
350 
351 /**
352  * @brief De-initialize the BOD registers to their default reset values.
353  * @retval An error_status_t enumeration value:
354  * - SUCCESS: PDM registers are de-initialized
355  * - ERROR: PDM registers are not de-initialized
356  */
357 error_status_t ll_bod_deinit(void);
358 
359 /**
360  * @brief Initialize the BOD registers according to the specified parameters in p_bod_init.
361  * @param p_bod_init pointer to a @ref ll_bod_init_t structure.
362  * @retval An error_status_t enumeration value:
363  * - SUCCESS: BOD registers are initialized
364  * - ERROR: Not applicable
365  */
366 error_status_t ll_bod_init(ll_bod_init_t *p_bod_init);
367 
368 /**
369  * @brief Set each field of a @ref ll_bod_init_t type structure to default value.
370  * @param p_bod_init Pointer to a @ref ll_bod_init_t structure
371  * whose fields will be set to default values.
372  * @retval None
373  */
375 /** @} */
376 #endif
377 /** @} */
378 
379 /** @} */
380 
381 /** @} */
ll_bod_static_lv_disable
__STATIC_INLINE void ll_bod_static_lv_disable(void)
disable bod static lv
Definition: gr55xx_ll_bod.h:257
ll_bod_is_active_flag_redge
__STATIC_INLINE uint32_t ll_bod_is_active_flag_redge(void)
Indicate if the BOD FEDGE Event Flag is set or not.
Definition: gr55xx_ll_bod.h:332
_ll_bod_init
LL BOD init Structure definition.
Definition: gr55xx_ll_bod.h:75
ll_bod_enable
__STATIC_INLINE void ll_bod_enable(void)
Enable the bod.
Definition: gr55xx_ll_bod.h:154
ll_bod2_disable
__STATIC_INLINE void ll_bod2_disable(void)
Disable the bod2.
Definition: gr55xx_ll_bod.h:205
_ll_bod_init::bod2_en
uint8_t bod2_en
Definition: gr55xx_ll_bod.h:80
ll_bod_init_t
struct _ll_bod_init ll_bod_init_t
LL BOD init Structure definition.
_ll_bod_init::bod_en
uint8_t bod_en
Definition: gr55xx_ll_bod.h:76
ll_bod_disable_fedge
__STATIC_INLINE void ll_bod_disable_fedge(void)
disable BOD FEDGE Event.
Definition: gr55xx_ll_bod.h:289
ll_bod_clear_flag_fedge
__STATIC_INLINE void ll_bod_clear_flag_fedge(void)
Clear Interrupt Status flag.
Definition: gr55xx_ll_bod.h:318
ll_bod2_lvl_ctrl_lv_set
__STATIC_INLINE void ll_bod2_lvl_ctrl_lv_set(uint8_t lvl_ctrl_lv)
Set bod control level.
Definition: gr55xx_ll_bod.h:222
ll_bod_static_lv_enable
__STATIC_INLINE void ll_bod_static_lv_enable(void)
enable bod static lv
Definition: gr55xx_ll_bod.h:241
ll_bod_struct_init
void ll_bod_struct_init(ll_bod_init_t *p_bod_init)
Set each field of a ll_bod_init_t type structure to default value.
ll_bod_is_active_flag_fedge
__STATIC_INLINE uint32_t ll_bod_is_active_flag_fedge(void)
Indicate if the BOD REDGE Event Flag is set or not.
Definition: gr55xx_ll_bod.h:304
ll_bod_clear_flag_redge
__STATIC_INLINE void ll_bod_clear_flag_redge(void)
Clear Interrupt Status flag.
Definition: gr55xx_ll_bod.h:346
ll_bod_init
error_status_t ll_bod_init(ll_bod_init_t *p_bod_init)
Initialize the BOD registers according to the specified parameters in p_bod_init.
ll_bod_deinit
error_status_t ll_bod_deinit(void)
De-initialize the BOD registers to their default reset values.
_ll_bod_init::bod2_lvl
uint8_t bod2_lvl
Definition: gr55xx_ll_bod.h:84
ll_bod_disable
__STATIC_INLINE void ll_bod_disable(void)
Disable the bod.
Definition: gr55xx_ll_bod.h:171
ll_bod2_enable
__STATIC_INLINE void ll_bod2_enable(void)
Enable the bod2.
Definition: gr55xx_ll_bod.h:188
ll_bod_enable_fedge
__STATIC_INLINE void ll_bod_enable_fedge(void)
enable BOD FEDGE Event.
Definition: gr55xx_ll_bod.h:275