52 #ifndef __GR55xx_LL_PDM_H__
53 #define __GR55xx_LL_PDM_H__
109 #define LL_PDM_SAMPLE_RATE_15_625K PDM_CLK_SAMPLE_RATE_15_625K
110 #define LL_PDM_SAMPLE_RATE_16K PDM_CLK_SAMPLE_RATE_16K
111 #define LL_PDM_SAMPLE_RATE_8K PDM_CLK_SAMPLE_RATE_8K
121 #define LL_PDM_MODE_LEFT ((uint32_t)0x00000000U)
122 #define LL_PDM_MODE_RIGHT ((uint32_t)0x00000001U)
123 #define LL_PDM_MODE_STEREO ((uint32_t)0x00000002U)
129 #define LL_PDM_CLK_ENABLE PDM_CLK_EN_ENABLE
130 #define LL_PDM_CLK_DISABLE PDM_CLK_EN_DISABLE
136 #define LL_PDM_LEFT_RX_ENABLE PDM_EN_L_EN_RX_ENABLE
137 #define LL_PDM_LEFT_RX_DISABLE PDM_EN_L_EN_RX_DISABLE
138 #define LL_PDM_RIGHT_RX_ENABLE PDM_EN_R_EN_RX_ENABLE
139 #define LL_PDM_RIGHT_RX_DISABLE PDM_EN_R_EN_RX_DISABLE
145 #define LL_PDM_LEFT_SAMPLE_DMIC_ENABLE PDM_EN_L_SMP_DMIC_ENABLE
146 #define LL_PDM_LEFT_SAMPLE_DMIC_DISABLE PDM_EN_L_SMP_DMIC_DISABLE
147 #define LL_PDM_RIGHT_SAMPLE_DMIC_ENABLE PDM_EN_R_SMP_DMIC_ENABLE
148 #define LL_PDM_RIGHT_SAMPLE_DMIC_DISABLE PDM_EN_R_SMP_DMIC_DISABLE
154 #define LL_PDM_LEFT_STAGE0_ENABLE PDM_EN_L_EN_STAGE0_ENABLE
155 #define LL_PDM_LEFT_STAGE0_DISABLE PDM_EN_L_EN_STAGE0_DISABLE
156 #define LL_PDM_LEFT_STAGE1_ENABLE PDM_EN_L_EN_STAGE1_ENABLE
157 #define LL_PDM_LEFT_STAGE1_DISABLE PDM_EN_L_EN_STAGE1_DISABLE
158 #define LL_PDM_LEFT_STAGE2_ENABLE PDM_EN_L_EN_STAGE2_ENABLE
159 #define LL_PDM_LEFT_STAGE2_DISABLE PDM_EN_L_EN_STAGE2_DISABLE
160 #define LL_PDM_LEFT_STAGE3_ENABLE PDM_EN_L_EN_STAGE3_ENABLE
161 #define LL_PDM_LEFT_STAGE3_DISABLE PDM_EN_L_EN_STAGE3_DISABLE
162 #define LL_PDM_LEFT_STAGE4_ENABLE PDM_EN_L_EN_STAGE4_ENABLE
163 #define LL_PDM_LEFT_STAGE4_DISABLE PDM_EN_L_EN_STAGE4_DISABLE
164 #define LL_PDM_LEFT_STAGE5_ENABLE PDM_EN_L_EN_STAGE5_ENABLE
165 #define LL_PDM_LEFT_STAGE5_DISABLE PDM_EN_L_EN_STAGE5_DISABLE
166 #define LL_PDM_LEFT_STAGE6_ENABLE PDM_EN_L_EN_STAGE6_ENABLE
167 #define LL_PDM_LEFT_STAGE6_DISABLE PDM_EN_L_EN_STAGE6_DISABLE
168 #define LL_PDM_LEFT_STAGE7_ENABLE PDM_EN_L_EN_STAGE7_ENABLE
169 #define LL_PDM_LEFT_STAGE7_DISABLE PDM_EN_L_EN_STAGE7_DISABLE
170 #define LL_PDM_RIGHT_STAGE0_ENABLE PDM_EN_R_EN_STAGE0_ENABLE
171 #define LL_PDM_RIGHT_STAGE0_DISABLE PDM_EN_R_EN_STAGE0_DISABLE
172 #define LL_PDM_RIGHT_STAGE1_ENABLE PDM_EN_R_EN_STAGE1_ENABLE
173 #define LL_PDM_RIGHT_STAGE1_DISABLE PDM_EN_R_EN_STAGE1_DISABLE
174 #define LL_PDM_RIGHT_STAGE2_ENABLE PDM_EN_R_EN_STAGE2_ENABLE
175 #define LL_PDM_RIGHT_STAGE2_DISABLE PDM_EN_R_EN_STAGE2_DISABLE
176 #define LL_PDM_RIGHT_STAGE3_ENABLE PDM_EN_R_EN_STAGE3_ENABLE
177 #define LL_PDM_RIGHT_STAGE3_DISABLE PDM_EN_R_EN_STAGE3_DISABLE
178 #define LL_PDM_RIGHT_STAGE4_ENABLE PDM_EN_R_EN_STAGE4_ENABLE
179 #define LL_PDM_RIGHT_STAGE4_DISABLE PDM_EN_R_EN_STAGE4_DISABLE
180 #define LL_PDM_RIGHT_STAGE5_ENABLE PDM_EN_R_EN_STAGE5_ENABLE
181 #define LL_PDM_RIGHT_STAGE5_DISABLE PDM_EN_R_EN_STAGE5_DISABLE
182 #define LL_PDM_RIGHT_STAGE6_ENABLE PDM_EN_R_EN_STAGE6_ENABLE
183 #define LL_PDM_RIGHT_STAGE6_DISABLE PDM_EN_R_EN_STAGE6_DISABLE
184 #define LL_PDM_RIGHT_STAGE7_ENABLE PDM_EN_R_EN_STAGE7_ENABLE
185 #define LL_PDM_RIGHT_STAGE7_DISABLE PDM_EN_R_EN_STAGE7_DISABLE
191 #define LL_PDM_LEFT_HPF_ENABLE PDM_EN_L_EN_HPF_ENABLE
192 #define LL_PDM_LEFT_HPF_DISABLE PDM_EN_L_EN_HPF_DISABLE
193 #define LL_PDM_RIGHT_HPF_ENABLE PDM_EN_R_EN_HPF_ENABLE
194 #define LL_PDM_RIGHT_HPF_DISABLE PDM_EN_R_EN_HPF_DISABLE
200 #define LL_PDM_LEFT_HPF_BYPASS_ENABLE PDM_HPF_CFG_L_BYPASS_ENABLE
201 #define LL_PDM_LEFT_HPF_BYPASS_DISABLE PDM_HPF_CFG_L_BYPASS_DISABLE
202 #define LL_PDM_RIGHT_HPF_BYPASS_ENABLE PDM_HPF_CFG_R_BYPASS_ENABLE
203 #define LL_PDM_RIGHT_HPF_BYPASS_DISABLE PDM_HPF_CFG_R_BYPASS_DISABLE
209 #define LL_PDM_LEFT_HPF_CORNER_0_25 PDM_HPF_CFG_L_CORNER_0_25
210 #define LL_PDM_LEFT_HPF_CORNER_1 PDM_HPF_CFG_L_CORNER_1
211 #define LL_PDM_LEFT_HPF_CORNER_4 PDM_HPF_CFG_L_CORNER_4
212 #define LL_PDM_LEFT_HPF_CORNER_16 PDM_HPF_CFG_L_CORNER_16
213 #define LL_PDM_RIGHT_HPF_CORNER_0_25 PDM_HPF_CFG_R_CORNER_0_25
214 #define LL_PDM_RIGHT_HPF_CORNER_1 PDM_HPF_CFG_R_CORNER_1
215 #define LL_PDM_RIGHT_HPF_CORNER_4 PDM_HPF_CFG_R_CORNER_4
216 #define LL_PDM_RIGHT_HPF_CORNER_16 PDM_HPF_CFG_R_CORNER_16
222 #define LL_PDM_LEFT_HPF_FREEZE_ENABLE PDM_HPF_CFG_L_FREEZE_ENABLE
223 #define LL_PDM_LEFT_HPF_FREEZE_DISABLE PDM_HPF_CFG_L_FREEZE_DISABLE
224 #define LL_PDM_RIGHT_HPF_FREEZE_ENABLE PDM_HPF_CFG_R_FREEZE_ENABLE
225 #define LL_PDM_RIGHT_HPF_FREEZE_DISABLE PDM_HPF_CFG_R_FREEZE_DISABLE
245 #define LL_PDM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
253 #define LL_PDM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
335 MODIFY_REG(PDMx->CLK, PDM_CLK_SAMPLE_RATE, sample_rate);
353 return (READ_BITS(PDMx->CLK, PDM_CLK_SAMPLE_RATE));
371 MODIFY_REG(PDMx->CLK_DIV, PDM_CLK_DIV_POSEDGE_EN_PULSE_CFG, (target << PDM_CLK_DIV_POSEDGE_EN_PULSE_CFG_POS));
386 return (READ_BITS(PDMx->CLK_DIV, PDM_CLK_DIV_POSEDGE_EN_PULSE_CFG) >> PDM_CLK_DIV_POSEDGE_EN_PULSE_CFG_POS);
404 MODIFY_REG(PDMx->CLK_DIV, PDM_CLK_DIV_NEGEDGE_EN_PULSE_CFG, (target << PDM_CLK_DIV_NEGEDGE_EN_PULSE_CFG_POS));
419 return (READ_BITS(PDMx->CLK_DIV, PDM_CLK_DIV_NEGEDGE_EN_PULSE_CFG) >> PDM_CLK_DIV_NEGEDGE_EN_PULSE_CFG_POS);
436 MODIFY_REG(PDMx->EN_L, PDM_EN_L_EN_RX | PDM_EN_L_EN_STAGE0 | PDM_EN_L_EN_STAGE1 |\
437 PDM_EN_L_EN_STAGE2 | PDM_EN_L_EN_STAGE3 | PDM_EN_L_EN_STAGE4 |\
438 PDM_EN_L_EN_STAGE5 | PDM_EN_L_EN_STAGE6 | PDM_EN_L_EN_STAGE7 |\
439 PDM_EN_L_SMP_DMIC | PDM_EN_L_EN_HPF, \
440 PDM_EN_L_EN_RX_ENABLE | PDM_EN_L_SMP_DMIC_ENABLE | PDM_EN_L_EN_STAGE0_DISABLE |\
441 PDM_EN_L_EN_STAGE1_DISABLE | PDM_EN_L_EN_STAGE2_ENABLE | PDM_EN_L_EN_STAGE3_ENABLE |\
442 PDM_EN_L_EN_STAGE4_ENABLE | PDM_EN_L_EN_STAGE5_ENABLE | PDM_EN_L_EN_STAGE6_ENABLE |\
443 PDM_EN_L_EN_STAGE7_ENABLE | PDM_EN_L_EN_HPF_ENABLE);
460 MODIFY_REG(PDMx->EN_L, PDM_EN_L_EN_RX | PDM_EN_L_EN_STAGE0 | PDM_EN_L_EN_STAGE1 |\
461 PDM_EN_L_EN_STAGE2 | PDM_EN_L_EN_STAGE3 | PDM_EN_L_EN_STAGE4 |\
462 PDM_EN_L_EN_STAGE5 | PDM_EN_L_EN_STAGE6 | PDM_EN_L_EN_STAGE7 |\
463 PDM_EN_L_SMP_DMIC | PDM_EN_L_EN_HPF, \
464 PDM_EN_L_EN_RX_DISABLE | PDM_EN_L_SMP_DMIC_DISABLE | PDM_EN_L_EN_STAGE0_DISABLE |\
465 PDM_EN_L_EN_STAGE1_DISABLE | PDM_EN_L_EN_STAGE2_DISABLE | PDM_EN_L_EN_STAGE3_DISABLE |\
466 PDM_EN_L_EN_STAGE4_DISABLE | PDM_EN_L_EN_STAGE5_DISABLE | PDM_EN_L_EN_STAGE6_DISABLE |\
467 PDM_EN_L_EN_STAGE7_DISABLE | PDM_EN_L_EN_HPF_DISABLE);
484 MODIFY_REG(PDMx->EN_R, PDM_EN_R_EN_RX | PDM_EN_R_EN_STAGE0 | PDM_EN_R_EN_STAGE1 |\
485 PDM_EN_R_EN_STAGE2 | PDM_EN_R_EN_STAGE3 | PDM_EN_R_EN_STAGE4 |\
486 PDM_EN_R_EN_STAGE5 | PDM_EN_R_EN_STAGE6 | PDM_EN_R_EN_STAGE7 |\
487 PDM_EN_R_SMP_DMIC | PDM_EN_R_EN_HPF, \
488 PDM_EN_R_EN_RX_ENABLE | PDM_EN_R_SMP_DMIC_ENABLE | PDM_EN_R_EN_STAGE0_DISABLE |\
489 PDM_EN_R_EN_STAGE1_DISABLE | PDM_EN_R_EN_STAGE2_ENABLE | PDM_EN_R_EN_STAGE3_ENABLE |\
490 PDM_EN_R_EN_STAGE4_ENABLE | PDM_EN_R_EN_STAGE5_ENABLE | PDM_EN_R_EN_STAGE6_ENABLE |\
491 PDM_EN_R_EN_STAGE7_ENABLE | PDM_EN_R_EN_HPF_ENABLE);
508 MODIFY_REG(PDMx->EN_R, PDM_EN_R_EN_RX | PDM_EN_R_EN_STAGE0 | PDM_EN_R_EN_STAGE1 |\
509 PDM_EN_R_EN_STAGE2 | PDM_EN_R_EN_STAGE3 | PDM_EN_R_EN_STAGE4 |\
510 PDM_EN_R_EN_STAGE5 | PDM_EN_R_EN_STAGE6 | PDM_EN_R_EN_STAGE7 |\
511 PDM_EN_R_SMP_DMIC | PDM_EN_R_EN_HPF, \
512 PDM_EN_R_EN_RX_DISABLE | PDM_EN_R_SMP_DMIC_DISABLE | PDM_EN_R_EN_STAGE0_DISABLE |\
513 PDM_EN_R_EN_STAGE1_DISABLE | PDM_EN_R_EN_STAGE2_DISABLE | PDM_EN_R_EN_STAGE3_DISABLE |\
514 PDM_EN_R_EN_STAGE4_DISABLE | PDM_EN_R_EN_STAGE5_DISABLE | PDM_EN_R_EN_STAGE6_DISABLE |\
515 PDM_EN_R_EN_STAGE7_DISABLE | PDM_EN_R_EN_HPF_DISABLE);
1591 MODIFY_REG(PDMx->IN_CFG_L, PDM_IN_CFG_L_RX_UPSMP, rxd_upsample << PDM_IN_CFG_L_RX_UPSMP_POS);
1608 return READ_BITS(PDMx->IN_CFG_L, PDM_IN_CFG_L_RX_UPSMP >> PDM_IN_CFG_L_RX_UPSMP_POS);
1626 MODIFY_REG(PDMx->IN_CFG_R, PDM_IN_CFG_R_RX_UPSMP, rxd_upsample << PDM_IN_CFG_R_RX_UPSMP_POS);
1643 return READ_BITS(PDMx->IN_CFG_R, PDM_IN_CFG_R_RX_UPSMP >> PDM_IN_CFG_R_RX_UPSMP_POS);
1661 MODIFY_REG(PDMx->IN_CFG_L, PDM_IN_CFG_L_STAGE_INIT, stage_init << PDM_IN_CFG_L_STAGE_INIT_POS);
1678 return (READ_BITS(PDMx->IN_CFG_L, PDM_IN_CFG_L_STAGE_INIT) >> PDM_IN_CFG_L_STAGE_INIT_POS) ;
1696 MODIFY_REG(PDMx->IN_CFG_R, PDM_IN_CFG_R_STAGE_INIT, stage_init << PDM_IN_CFG_R_STAGE_INIT_POS);
1713 return (READ_BITS(PDMx->IN_CFG_R, PDM_IN_CFG_R_STAGE_INIT) >> PDM_IN_CFG_R_STAGE_INIT_POS) ;
1731 MODIFY_REG(PDMx->LPF_CFG_L, PDM_LPF_CFG_L_UPSMP_FACTOR, upsample_factor << PDM_LPF_CFG_L_UPSMP_FACTOR_POS);
1748 return (READ_BITS(PDMx->LPF_CFG_L, PDM_LPF_CFG_L_UPSMP_FACTOR) >> PDM_LPF_CFG_L_UPSMP_FACTOR_POS) ;
1766 MODIFY_REG(PDMx->LPF_CFG_R, PDM_LPF_CFG_R_UPSMP_FACTOR, upsample_factor << PDM_LPF_CFG_R_UPSMP_FACTOR_POS);
1783 return (READ_BITS(PDMx->LPF_CFG_R, PDM_LPF_CFG_R_UPSMP_FACTOR) >> PDM_LPF_CFG_R_UPSMP_FACTOR_POS) ;
1898 MODIFY_REG(PDMx->HPF_CFG_L, PDM_HPF_CFG_L_CORNER, hpf_corner);
1918 return READ_BITS(PDMx->HPF_CFG_L, PDM_HPF_CFG_L_CORNER);
1939 MODIFY_REG(PDMx->HPF_CFG_R, PDM_HPF_CFG_R_CORNER, hpf_corner);
1959 return READ_BITS(PDMx->HPF_CFG_R, PDM_HPF_CFG_R_CORNER);
2071 MODIFY_REG(PDMx->PGA_CFG_L, PDM_PGA_CFG_L_VAL, pga_val << PDM_PGA_CFG_L_VAL_POS);
2088 return (READ_BITS(PDMx->PGA_CFG_L, PDM_PGA_CFG_L_VAL) >> PDM_PGA_CFG_L_VAL_POS);
2106 MODIFY_REG(PDMx->PGA_CFG_R, PDM_PGA_CFG_R_VAL, pga_val << PDM_PGA_CFG_R_VAL_POS);
2123 return (READ_BITS(PDMx->PGA_CFG_R, PDM_PGA_CFG_R_VAL) >> PDM_PGA_CFG_R_VAL_POS);
2140 return (READ_BITS(PDMx->DATA_L, PDM_DATA_L_DATA) >> PDM_DATA_L_DATA_POS);
2157 return (READ_BITS(PDMx->DATA_R, PDM_DATA_R_DATA) >> PDM_DATA_R_DATA_POS);
2175 MODIFY_REG(PDMx->DATA_L, PDM_DATA_L_VALID, (1 << PDM_DATA_L_VALID_POS));
2193 return ((READ_BITS(PDMx->DATA_L, PDM_DATA_L_VALID) >> PDM_DATA_L_VALID_POS) == 1);
2211 MODIFY_REG(PDMx->DATA_R, PDM_DATA_R_VALID, (1 << PDM_DATA_R_VALID_POS));
2229 return ((READ_BITS(PDMx->DATA_R, PDM_DATA_R_VALID) >> PDM_DATA_R_VALID_POS) == 1);
2247 MODIFY_REG(PDMx->DATA_L, PDM_DATA_L_OVER, (1 << PDM_DATA_L_OVER_POS));
2265 return ((READ_BITS(PDMx->DATA_L, PDM_DATA_L_OVER) >> PDM_DATA_L_OVER_POS) == 1);
2283 MODIFY_REG(PDMx->DATA_R, PDM_DATA_R_OVER, (1 << PDM_DATA_R_OVER_POS));
2301 return ((READ_BITS(PDMx->DATA_R, PDM_DATA_R_OVER) >> PDM_DATA_R_OVER_POS) == 1);
2316 MODIFY_REG(PDMx->INT_L, PDM_INT_L_VALID_MASK,(0 << PDM_INT_L_VALID_MASK_POS));
2331 MODIFY_REG(PDMx->INT_L, PDM_INT_L_VALID_MASK,(1 << PDM_INT_L_VALID_MASK_POS));
2346 return ((READ_BITS(PDMx->INT_L, PDM_INT_L_VALID_MASK) >> PDM_INT_L_VALID_MASK_POS) == 0);
2361 MODIFY_REG(PDMx->INT_R, PDM_INT_R_VALID_MASK,(0 << PDM_INT_R_VALID_MASK_POS));
2376 MODIFY_REG(PDMx->INT_R, PDM_INT_R_VALID_MASK,(1 << PDM_INT_R_VALID_MASK_POS));
2391 return ((READ_BITS(PDMx->INT_R, PDM_INT_R_VALID_MASK) >> PDM_INT_R_VALID_MASK_POS) == 0);
2406 MODIFY_REG(PDMx->INT_L, PDM_INT_L_OVER_MASK,(0 << PDM_INT_L_OVER_MASK_POS));
2421 MODIFY_REG(PDMx->INT_L, PDM_INT_L_OVER_MASK,(1 << PDM_INT_L_OVER_MASK_POS));
2436 return ((READ_BITS(PDMx->INT_L, PDM_INT_L_OVER_MASK) >> PDM_INT_L_OVER_MASK_POS) == 0);
2451 MODIFY_REG(PDMx->INT_R, PDM_INT_R_OVER_MASK,(0 << PDM_INT_R_OVER_MASK_POS));
2466 MODIFY_REG(PDMx->INT_R, PDM_INT_R_OVER_MASK,(1 << PDM_INT_R_OVER_MASK_POS));
2481 return ((READ_BITS(PDMx->INT_R, PDM_INT_R_OVER_MASK) >> PDM_INT_R_OVER_MASK_POS) == 0);
2496 MODIFY_REG(PDMx->DATA_L, PDM_DATA_L_VALID_DMA_MASK,PDM_DATA_L_VALID_DMA_MASK_ENABLE);
2511 MODIFY_REG(PDMx->DATA_L, PDM_DATA_L_VALID_DMA_MASK,PDM_DATA_L_VALID_DMA_MASK_DISABLE);
2526 MODIFY_REG(PDMx->DATA_R, PDM_DATA_R_VALID_DMA_MASK,PDM_DATA_R_VALID_DMA_MASK_ENABLE);
2541 MODIFY_REG(PDMx->DATA_R, PDM_DATA_R_VALID_DMA_MASK,PDM_DATA_R_VALID_DMA_MASK_DISABLE);