52 #ifndef __GR55XX_LL_BOD_H_
53 #define __GR55XX_LL_BOD_H_
110 #define LL_BOD_ENABLE 0x1
111 #define LL_BOD_DISABLE 0x0
117 #define LL_BOD2_ENABLE 0x1
118 #define LL_BOD2_DISABLE 0x0
124 #define LL_BOD_STATIC_ENABLE (0x1)
125 #define LL_BOD_STATIC_DISABLE (0x0)
131 #define LL_BOD2_LEVEL_0 0x0
132 #define LL_BOD2_LEVEL_1 0x1
133 #define LL_BOD2_LEVEL_2 0x2
134 #define LL_BOD2_LEVEL_3 0x3
135 #define LL_BOD2_LEVEL_4 0x4
136 #define LL_BOD2_LEVEL_5 0x5
137 #define LL_BOD2_LEVEL_6 0x6
138 #define LL_BOD2_LEVEL_7 0x7
139 #define LL_BOD2_LEVEL_8 0x8
140 #define LL_BOD2_LEVEL_9 0x9
141 #define LL_BOD2_LEVEL_10 0xA
142 #define LL_BOD2_LEVEL_11 0xB
143 #define LL_BOD2_LEVEL_12 0xC
144 #define LL_BOD2_LEVEL_13 0xD
145 #define LL_BOD2_LEVEL_14 0xE
146 #define LL_BOD2_LEVEL_15 0xF
166 #if defined(BIT_BAND_SUPPORT)
167 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 1;
169 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
183 #if defined(BIT_BAND_SUPPORT)
184 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN_Pos) = 0;
186 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
200 #if defined(BIT_BAND_SUPPORT)
201 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 1;
203 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN);
217 #if defined(BIT_BAND_SUPPORT)
218 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_EN_Pos) = 0;
220 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_EN);
234 #if defined(BIT_BAND_SUPPORT)
235 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos) = (lvl_ctrl_lv & 0x01);
236 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+1) = ((lvl_ctrl_lv>>1) & 0x01);
237 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+2) = ((lvl_ctrl_lv>>2) & 0x01);
238 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos+3) = ((lvl_ctrl_lv>>3) & 0x01);
240 MODIFY_REG(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV, (lvl_ctrl_lv << AON_PMU_RF_REG_3_BOD_LVL_CTRL_LV_Pos));
253 #if defined(BIT_BAND_SUPPORT)
254 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 1;
256 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
269 #if defined(BIT_BAND_SUPPORT)
270 BIT_ADDR((uint32_t)&AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_Pos) = 0;
272 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD_STATIC_LV_EN);
287 SET_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
301 CLEAR_BITS(AON_CTL->AON_IRQ_EN, AON_CTL_AON_IRQ_PMU_BOD);
315 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_PMU_BOD) == AON_CTL_AON_IRQ_PMU_BOD);
329 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_PMU_BOD);
343 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_PMU_BOD) == AON_CTL_SLP_EVENT_PMU_BOD);
357 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_PMU_BOD);