52 #ifndef __GR55XX_LL_AON_WDT_H__
53 #define __GR55XX_LL_AON_WDT_H__
69 #define LL_AON_WD_TIMER_CLK_SEL_RNG (0x0U << AON_WDT_CLK_SEL_Pos)
70 #define LL_AON_WD_TIMER_CLK_SEL_XO (0x1U << AON_WDT_CLK_SEL_Pos)
71 #define LL_AON_WD_TIMER_CLK_SEL_RNG2 (0x2U << AON_WDT_CLK_SEL_Pos)
72 #define LL_AON_WD_TIMER_CLK_SEL_RTC (0x3U << AON_WDT_CLK_SEL_Pos)
79 #define AON_WDT_REG_READ (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN | \
80 AON_WDT_CFG0_ALARM_EN))
103 WRITE_REG(AON_WDT->CFG0,AON_WDT_CFG0_CFG | AON_WDT_CFG0_EN |
AON_WDT_REG_READ);
116 MODIFY_REG(AON_WDT->CFG0, 0xFFFFFFFF, AON_WDT_CFG0_CFG);
130 return (READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_EN) == (AON_WDT_CFG0_EN));
148 MODIFY_REG(AON_WDT->CLK, AON_WDT_CLK_SEL, value);
166 return (READ_BITS(AON_WDT->CLK, AON_WDT_CLK_SEL));
180 WRITE_REG(AON_WDT->TIMER_W, counter);
194 return (uint32_t)READ_BITS(AON_WDT->TIMER_W, AON_WDT_TIMER_W_VAL);
208 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
223 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_TIMER_SET |
AON_WDT_REG_READ);
238 return (uint32_t)READ_BITS(AON_WDT->TIMER_R, AON_WDT_TIMER_R_VAL);
255 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
272 WRITE_REG(AON_WDT->ALARM_W, (counter & AON_WDT_ALARM_W_VAL));
273 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_SET |
AON_WDT_REG_READ);
289 return (uint32_t)(READ_BITS(AON_WDT->ALARM_W, AON_WDT_ALARM_W_VAL));
303 return (uint32_t)(READ_BITS(AON_WDT->ALARM_R, AON_WDT_ALARM_R_VAL));
317 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_BUSY) == (AON_WDT_STAT_BUSY));
331 WRITE_REG(AON_WDT->CFG0, AON_WDT_CFG0_CFG | AON_WDT_CFG0_ALARM_EN |
AON_WDT_REG_READ);
345 WRITE_REG(AON_WDT->CFG0, (
AON_WDT_REG_READ & (~AON_WDT_CFG0_ALARM_EN)) | AON_WDT_CFG0_CFG);
359 return (uint32_t)(READ_BITS(AON_WDT->CFG0, AON_WDT_CFG0_ALARM_EN) == AON_WDT_CFG0_ALARM_EN);
380 return (uint32_t)(READ_BITS(AON_WDT->STAT, AON_WDT_STAT_STAT) == (AON_WDT_STAT_STAT));
396 return (uint32_t)(READ_BITS(AON_CTL->AON_IRQ, AON_CTL_AON_IRQ_AON_WDT) == AON_CTL_AON_IRQ_AON_WDT);
410 WRITE_REG(AON_CTL->AON_IRQ, ~AON_CTL_AON_IRQ_AON_WDT);
426 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_AON_WDT) == AON_CTL_SLP_EVENT_AON_WDT);
440 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_AON_WDT);
450 WRITE_REG(AON_WDT->LOCK, 0x15CC5A51 << 1);
460 WRITE_REG(AON_WDT->LOCK, 0 << 1);