52 #ifndef __GR55xx_LL_PWR_H__
53 #define __GR55xx_LL_PWR_H__
62 #if defined(AON_CTL) && defined(AON_IO)
76 #define LL_PWR_WKUP_COND_EXT AON_CTL_MCU_WAKEUP_CTRL_EXT
77 #define LL_PWR_WKUP_COND_TIMER AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER
78 #define LL_PWR_WKUP_COND_BLE AON_CTL_MCU_WAKEUP_CTRL_SMS_OSC
79 #define LL_PWR_WKUP_COND_CLDR AON_CTL_MCU_WAKEUP_CTRL_RTC0
80 #define LL_PWR_WKUP_COND_CLDR_TICK AON_CTL_MCU_WAKEUP_CTRL_RTC1
81 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_CTL_MCU_WAKEUP_CTRL_PMU_BOD
82 #define LL_PWR_WKUP_COND_AUSB AON_CTL_MCU_WAKEUP_CTRL_USB_ATTACH
83 #define LL_PWR_WKUP_COND_DUSB AON_CTL_MCU_WAKEUP_CTRL_USB_DETACH
84 #define LL_PWR_WKUP_COND_BLE_IRQ AON_CTL_MCU_WAKEUP_CTRL_BLE_IRQ
85 #define LL_PWR_WKUP_COND_AON_WDT AON_CTL_MCU_WAKEUP_CTRL_AON_WDT
86 #define LL_PWR_WKUP_COND_COMP AON_CTL_MCU_WAKEUP_CTRL_PMU_COMP
87 #define LL_PWR_WKUP_COND_ALL (0xFFFU << AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER_Pos)
95 #define LL_PWR_WKUP_EVENT_BLE AON_CTL_SLP_EVENT_SMS_OSC
96 #define LL_PWR_WKUP_EVENT_TIMER AON_CTL_SLP_EVENT_SLP_TIMER
97 #define LL_PWR_WKUP_EVENT_EXT AON_CTL_SLP_EVENT_EXT
98 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_CTL_SLP_EVENT_PMU_BOD
99 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_CTL_SLP_EVENT_PMU_MSIO
100 #define LL_PWR_WKUP_EVENT_WDT AON_CTL_SLP_EVENT_AON_WDT
101 #define LL_PWR_WKUP_EVENT_CLDR AON_CTL_SLP_EVENT_RTC0
102 #define LL_PWR_WKUP_EVENT_AUSB AON_CTL_SLP_EVENT_USB_ATTACH
103 #define LL_PWR_WKUP_EVENT_DUSB AON_CTL_SLP_EVENT_USB_DETACH
104 #define LL_PWR_WKUP_EVENT_CLDR_TICK AON_CTL_SLP_EVENT_RTC1
105 #define LL_PWR_WKUP_EVENT_BLE_IRQ AON_CTL_SLP_EVENT_BLE_IRQ
106 #define LL_PWR_WKUP_EVENT_ALL (0xFFFU << AON_CTL_SLP_EVENT_SLP_TIMER_Pos)
118 #define LL_PWR_DPAD_LE_OFF (0x00000000U)
119 #define LL_PWR_DPAD_LE_ON (0x00000001U)
157 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_set_wakeup_condition(uint32_t condition)
159 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
184 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_clear_wakeup_condition(uint32_t condition)
186 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
211 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(
void)
213 return ((uint32_t)READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, LL_PWR_WKUP_COND_ALL));
238 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(
void)
240 return ((uint32_t)READ_BITS(AON_CTL->AON_SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
255 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_set_sleep_timer_value(uint32_t value)
257 WRITE_REG(SLP_TIMER->TIMER_W, value);
269 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_read_value(
void)
271 return READ_REG(SLP_TIMER->TIMER_R);
285 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_smc_wakeup_req(
void)
287 SET_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
300 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_smc_wakeup_req(
void)
302 CLEAR_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
314 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(
void)
316 return (READ_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ) == AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
335 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
337 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_SLEEP, (sleep << AON_PWR_DPAD_LE_CTRL_SLEEP_Pos));
338 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_WAKEUP, (wakeup << AON_PWR_DPAD_LE_CTRL_WAKEUP_Pos));
358 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_timer_reset(
void)
360 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
373 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_timer_reset(
void)
375 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
387 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(
void)
389 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N) == 0x0U));
404 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_core_reset(
void)
406 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
419 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_core_reset(
void)
421 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
433 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(
void)
435 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_RST_N_RD) == 0x0U));
448 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_timer_power(
void)
450 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
451 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
452 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
465 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_timer_power(
void)
467 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
468 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
469 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
482 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(
void)
484 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN) == AON_PWR_COMM_TIMER_PWR_CTRL_EN));
497 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_core_power(
void)
499 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
500 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
513 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_core_power(
void)
515 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
516 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
529 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(
void)
531 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD) == AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD));
543 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_osc_sleep(
void)
545 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
558 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_osc_sleep(
void)
560 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
572 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(
void)
574 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN));
586 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_radio_sleep(
void)
588 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
601 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_radio_sleep(
void)
603 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
615 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(
void)
617 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN));
630 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_core_deep_sleep(
void)
632 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
645 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_core_deep_sleep(
void)
647 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
659 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(
void)
661 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON));
675 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_soft_wakeup_req(
void)
677 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ);
690 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(
void)
692 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ));
705 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_enable_comm_core_ext_wakeup(
void)
707 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
720 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_comm_core_ext_wakeup(
void)
722 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
734 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(
void)
736 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
749 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
751 WRITE_REG(AON_CTL->COMM_TIMER_CFG0, time);
763 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(
void)
765 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG0));
777 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(
void)
779 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_STAT));
798 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
800 WRITE_REG(AON_CTL->COMM_TIMER_CFG1, (twext << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWEXT_Pos) |
801 (twosc << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos) |
802 (twrm << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWRM_Pos));
816 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(
void)
818 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1));
826 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(
void)
828 return ((((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1) & AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Msk)) >> AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos);
856 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(
void)
858 return ((uint32_t)(READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) >> AON_IO_EXT_WAKEUP_STAT_STAT_POS));
880 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
882 WRITE_REG(AON_IO->EXT_WAKEUP_STAT, ~(wakeup_pin << AON_IO_EXT_WAKEUP_STAT_STAT_POS));
907 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_clear_wakeup_event(uint32_t event)
909 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
922 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(
void)
924 return (READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT);
937 SECTION_RAM_CODE __STATIC_INLINE
void ll_pwr_disable_cache_module(
void)
939 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
940 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
953 __STATIC_INLINE
void ll_pwr_set_dcdc_prepare_timing(uint32_t value)
955 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DCDC, (value << AON_PWR_A_TIMING_CTRL0_DCDC_Pos));
968 __STATIC_INLINE
void ll_pwr_set_dig_ldo_prepare_timing(uint32_t value)
970 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DIG_LDO, (value << AON_PWR_A_TIMING_CTRL0_DIG_LDO_Pos));
984 __STATIC_INLINE
void ll_pwr_set_fast_ldo_prepare_timing(uint32_t value)
986 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_FAST_LDO, (value << AON_PWR_A_TIMING_CTRL1_FAST_LDO_Pos));
999 __STATIC_INLINE
void ll_pwr_set_hf_osc_prepare_timing(uint32_t value)
1001 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_HF_OSC, (value << AON_PWR_A_TIMING_CTRL1_HF_OSC_Pos));
1014 __STATIC_INLINE
void ll_pwr_set_pll_lock_timing(uint32_t value)
1016 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL_LOCK, (value << AON_PWR_A_TIMING_CTRL2_PLL_LOCK_Pos));
1029 __STATIC_INLINE
void ll_pwr_set_pll_prepare_timing(uint32_t value)
1031 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL, (value << AON_PWR_A_TIMING_CTRL2_PLL_Pos));
1044 __STATIC_INLINE
void ll_pwr_set_pwr_switch_prepare_timing(uint32_t value)
1046 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_PWR_SWITCH, (value << AON_PWR_A_TIMING_CTRL3_PWR_SWITCH_Pos));
1059 __STATIC_INLINE
void ll_pwr_set_xo_prepare_timing(uint32_t value)
1061 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_XO, (value << AON_PWR_A_TIMING_CTRL3_XO_Pos));
1074 __STATIC_INLINE
void ll_pwr_set_xo_bias_sw_timing(uint32_t value)
1076 MODIFY_REG(AON_PWR->A_TIMING_CTRL4, AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH, (value << AON_PWR_A_TIMING_CTRL4_XO_BIAS_SWITCH_Pos));
1088 __STATIC_INLINE
void ll_pwr_enable_fast_ldo_pwr_mode(
void)
1090 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_MCU_PWR_TYPE);
1102 __STATIC_INLINE
void ll_pwr_turn_on_dcdc_after_wakeup(
void)
1104 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_DCDC_OFF);
1116 __STATIC_INLINE
void ll_pwr_turn_off_fast_ldo_in_regular_boot(
void)
1118 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_FAST_LDO_OFF);
1130 __STATIC_INLINE
void ll_pwr_turn_off_enable_xo_pll_after_dcdc_ready(
void)
1132 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1143 __STATIC_INLINE
void ll_pwr_turn_on_enable_xo_pll_after_dcdc_ready(
void)
1145 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);