52 #ifndef __GR55XX_LL_RTC_H__
53 #define __GR55XX_LL_RTC_H__
73 #define LL_RTC_DIV_NONE ((uint32_t)0x00U)
74 #define LL_RTC_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos)
75 #define LL_RTC_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos)
76 #define LL_RTC_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos)
77 #define LL_RTC_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos)
78 #define LL_RTC_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos)
79 #define LL_RTC_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos)
80 #define LL_RTC_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos)
86 #define LL_RTC_TIMER_CLK_SEL_RNG (0x0U << RTC_CLK_SEL_Pos)
87 #define LL_RTC_TIMER_CLK_SEL_XO (0x1U << RTC_CLK_SEL_Pos)
88 #define LL_RTC_TIMER_CLK_SEL_RNG2 (0x2U << RTC_CLK_SEL_Pos)
89 #define LL_RTC_TIMER_CLK_SEL_RTC (0x3U << RTC_CLK_SEL_Pos)
95 #define LL_RTC_TIMER_TICK_TYPE_SINGLE (0x0U)
96 #define LL_RTC_TIMER_TICK_TYPE_AUTO (0x1U)
102 #define READ_CFG0_CFG(RTCx) (READ_BITS(RTCx->CFG0, RTC_CFG0_EN | \
103 RTC_CFG0_ALARM_EN | \
137 MODIFY_REG(RTCx->CLK, RTC_CLK_SEL, value);
156 return (READ_BITS(RTCx->CLK, RTC_CLK_SEL));
171 WRITE_REG(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN);
186 MODIFY_REG(RTCx->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
201 return (READ_BITS(RTCx->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
217 WRITE_REG(RTCx->TIMER_W, counter);
234 WRITE_REG(RTCx->TIMER_W, start_value);
235 SET_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
250 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TIMER_SET);
283 WRITE_REG(RTCx->ALARM_W, alarm_value);
284 SET_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
300 WRITE_REG(RTCx->TICK_W, tick);
301 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
302 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET);
317 return (uint32_t)READ_REG(RTCx->TIMER_W);
332 return (uint32_t)READ_REG(RTCx->TIMER_R);
347 return (uint32_t)READ_REG(RTCx->ALARM_W);
362 return (uint32_t)READ_REG(RTCx->ALARM_R);
377 return (uint32_t)READ_REG(RTCx->TICK_W);
392 return (uint32_t)READ_REG(RTCx->TICK_R);
408 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
423 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
438 return (uint32_t)(READ_BITS(RTCx->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
454 SET_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
459 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_WRAP_CLR);
483 MODIFY_REG(RTCx->CFG1, RTC_CFG1_DIV, div);
499 WRITE_REG(RTCx->ALARM_W, value);
500 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN | RTC_CFG0_ALARM_SET);
505 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
520 SET_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
535 CLEAR_BITS(RTCx->CFG0,RTC_CFG0_ALARM_SET | RTC_CFG0_ALARM_EN);
536 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
551 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM);
566 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
567 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
582 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
583 SET_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
603 CLEAR_BITS(RTCx->CFG0,((~tick_mode) << RTC_CFG0_TICK_MDOE_Pos));
607 SET_BITS(RTCx->CFG0,(tick_mode << RTC_CFG0_TICK_MDOE_Pos));
623 SET_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
638 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN | RTC_CFG0_TICK_SET);
639 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG);
654 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_TICK);
670 return (uint32_t)((READ_BITS(RTCx->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
671 (READ_BITS(RTCx->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
688 WRITE_REG(RTCx->TICK_W, tick_reload);
689 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN| RTC_CFG0_TICK_SET);
704 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_ALARM_SET);
705 SET_BITS(RTCx->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_EN);
720 CLEAR_BITS(RTCx->CFG0, RTC_CFG0_TICK_SET);
735 SET_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
750 CLEAR_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP);
765 return (uint32_t)(READ_BITS(RTCx->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
788 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
805 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
822 return (uint32_t)(READ_BITS(RTCx->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
837 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_ALARM);
852 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_WRAP);
868 WRITE_REG(RTCx->INT_STAT, RTC_INT_STAT_TICK);
875 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
877 else if(RTCx == RTC1)
879 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
887 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);
889 else if(RTCx == RTC1)
891 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC1);
909 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
911 else if(RTCx == RTC1)
913 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);
931 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC0);
933 else if(RTCx == RTC1)
935 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_RTC1);