52 #ifndef __GR55xx_LL_EFUSE_H__
53 #define __GR55xx_LL_EFUSE_H__
78 #define LL_EFUSE_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM
79 #define LL_EFUSE_READ_TRIM EFUSE_OPER_READ_TRIM
80 #define LL_EFUSE_CRC_CHECK EFUSE_OPER_CRC_CHECK
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK
82 #define LL_EFUSE_TEST_READ EFUSE_OPER_RD_TEST_MODE
89 #define LL_EFUSE_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY
90 #define LL_EFUSE_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE
91 #define LL_EFUSE_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE
92 #define LL_EFUSE_CRC_CHECK_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS
93 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE
94 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS
95 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE
96 #define LL_EFUSE_TEST_DONE EFUSE_STATUS_TEST_MODE_DONE
103 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE
104 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE
125 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
133 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
163 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, ((time << EFUSE_TPGM_TIME_Pos) & EFUSE_TPGM_TIME));
178 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
193 SET_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
208 CLEAR_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
223 return (READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP) == (EFUSE_TPGM_MAIN_OR_BACKUP));
239 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN, length << EFUSE_TPGM_CRC_CHECK_LEN_Pos);
254 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN) >> EFUSE_TPGM_CRC_CHECK_LEN_Pos);
270 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
285 return (uint8_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
301 MODIFY_REG(EFUSEx->PGENB, EFUSE_PGENB_PGMEN_CTRL, (value << EFUSE_PGENB_PGMEN_CTRL_Pos) & EFUSE_PGENB_PGMEN_CTRL);
316 return (uint8_t)(READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_PGMEN_CTRL) >> EFUSE_PGENB_PGMEN_CTRL_Pos);
332 return (uint32_t)(READ_BITS(EFUSEx->TEST_MODE, EFUSE_TEST_MODE));
357 WRITE_REG(EFUSEx->OPERATION, mode);
388 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
404 WRITE_REG(EFUSEx->KEY_MASK, mask);
419 return (uint32_t)(READ_REG(EFUSEx->KEY_MASK));
436 WRITE_REG(EFUSEx->CRC_ADDR, address);
451 return (uint32_t)(READ_REG(EFUSEx->CRC_ADDR));
466 return (uint32_t)(READ_REG(EFUSEx->CRC_OUTPUT));
483 WRITE_REG(EFUSEx->TRIM_ADDR, address);
498 return (uint32_t)(READ_REG(EFUSEx->TRIM_ADDR));
514 WRITE_REG(EFUSEx->TRIM_LEN, length & EFUSE_TRIM_LENGTH);
529 return (uint32_t)(READ_REG(EFUSEx->TRIM_LEN) & EFUSE_TRIM_LENGTH);
545 return (uint32_t)(READ_REG(EFUSEx->TRIM[indx]));
559 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
573 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
589 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN | AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
604 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN | AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
620 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_0, vddq_0 + (vddq_1 << 16));
621 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_1, vddq_2);
636 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_BGN | MCU_SUB_EFUSE_PWR_CTL0_EN);
651 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_STP | MCU_SUB_EFUSE_PWR_CTL0_EN);
667 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL_0, 0);
686 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL_1, flag) == (flag));