52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
62 #if defined(AON_IO) || defined(MCU_RET)
76 typedef struct _ll_aon_gpio_init
116 } ll_aon_gpio_init_t;
134 #define LL_AON_GPIO_MODE_INPUT_POS ((uint32_t)0x0U)
135 #define LL_AON_GPIO_MODE_OUTPUT_POS ((uint32_t)0x1U)
136 #define LL_AON_GPIO_STRENGTH_DS0_MASK ((uint32_t)0x10U)
137 #define LL_AON_GPIO_STRENGTH_DS1_MASK ((uint32_t)0x01U)
138 #define LL_AON_GPIO_STRENGTH_DS0_POS ((uint32_t)0x04U)
139 #define LL_AON_GPIO_STRENGTH_DS1_POS ((uint32_t)0x00U)
145 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U)
146 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U)
147 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U)
148 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U)
149 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U)
150 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U)
151 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U)
152 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U)
153 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU)
159 #define LL_AON_GPIO_MODE_NONE ((uint32_t)0x0U)
160 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x1U)
161 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x2U)
162 #define LL_AON_GPIO_MODE_INOUT ((uint32_t)0x3U)
169 #define LL_AON_GPIO_PULL_NO ((uint32_t)0x0U)
170 #define LL_AON_GPIO_PULL_UP ((uint32_t)0x1U)
171 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x2U)
178 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U)
179 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U)
180 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U)
181 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U)
182 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U)
183 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U)
184 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U)
185 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U)
186 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U)
193 #define LL_AON_GPIO_SPEED_MEDIUM ((uint32_t)0x1U)
194 #define LL_AON_GPIO_SPEED_HIGH ((uint32_t)0x0U)
200 #define LL_AON_GPIO_STRENGTH_LOW ((uint32_t)0x00U)
201 #define LL_AON_GPIO_STRENGTH_MEDIUM ((uint32_t)0x01U)
202 #define LL_AON_GPIO_STRENGTH_HIGH ((uint32_t)0x10U)
203 #define LL_AON_GPIO_STRENGTH_ULTRA ((uint32_t)0x11U)
209 #define LL_AON_GPIO_INPUT_TYPE_CMOS ((uint32_t)0x00U)
210 #define LL_AON_GPIO_INPUT_TYPE_SCHMITT ((uint32_t)0x01U)
216 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U)
217 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U)
218 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U)
219 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U)
220 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U)
221 #define LL_AON_GPIO_TRIGGER_BOTH_EDGE ((uint32_t)0x05U)
228 #define LL_CLK_RNG_OSC_32K ((uint32_t)0x00U)
229 #define LL_CLK_RNG_OSC_2MHZ ((uint32_t)0x01U)
230 #define LL_CLK_RC_OSC_CLK ((uint32_t)0x02U)
231 #define LL_CLK_RTC_CLK ((uint32_t)0x03U)
253 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
261 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
281 #define LL_AON_GPIO_DEFAULT_CONFIG \
283 .pin = LL_AON_GPIO_PIN_ALL, \
284 .mode = LL_AON_GPIO_MODE_INPUT, \
285 .pull = LL_AON_GPIO_PULL_DOWN, \
286 .mux = LL_AON_GPIO_MUX_8, \
287 .speed = LL_AON_GPIO_SPEED_MEDIUM, \
288 .strength = LL_AON_GPIO_STRENGTH_MEDIUM, \
289 .input_type = LL_AON_GPIO_INPUT_TYPE_CMOS, \
290 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
331 SECTION_RAM_CODE __STATIC_INLINE
void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
333 uint32_t ie_mask = (pin_mask << AON_IO_AON_PAD_IE_POS) & AON_IO_AON_PAD_IE;
334 uint32_t oe_mask = (pin_mask << AON_IO_AON_PAD_OE_POS) & AON_IO_AON_PAD_OE;
335 uint32_t ie = ((mode == LL_AON_GPIO_MODE_INPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? ie_mask : 0x0000U;
336 uint32_t oe = ((mode == LL_AON_GPIO_MODE_OUTPUT) || (mode == LL_AON_GPIO_MODE_INOUT)) ? oe_mask : 0x0000U;
337 MODIFY_REG(AON_IO->AON_PAD_CTRL0, ie_mask, ie);
338 MODIFY_REG(AON_IO->AON_PAD_CTRL0, oe_mask, oe);
366 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
368 uint32_t ie_mask = (pin << AON_IO_AON_PAD_IE_POS) & AON_IO_AON_PAD_IE;
369 uint32_t oe_mask = (pin << AON_IO_AON_PAD_OE_POS) & AON_IO_AON_PAD_OE;
370 uint32_t ie = READ_BITS(AON_IO->AON_PAD_CTRL0, ie_mask) >> (POSITION_VAL(pin));
371 uint32_t oe = READ_BITS(AON_IO->AON_PAD_CTRL0, oe_mask) >> (POSITION_VAL(pin));
372 return (((ie >> AON_IO_AON_PAD_IE_POS) << LL_AON_GPIO_MODE_INPUT_POS)
373 | ((oe >> AON_IO_AON_PAD_OE_POS) << LL_AON_GPIO_MODE_OUTPUT_POS));
398 __STATIC_INLINE
void ll_aon_gpio_set_pin_input_type(uint32_t pin_mask, uint32_t type)
400 pin_mask = (pin_mask << AON_IO_AON_PAD_IS_POS) & AON_IO_AON_PAD_IS;
401 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask, (type == LL_AON_GPIO_INPUT_TYPE_SCHMITT) ? pin_mask : 0);
426 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_input_type(uint32_t pin)
428 pin = (pin << AON_IO_AON_PAD_IS_POS) & AON_IO_AON_PAD_IS;
429 return ((uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL2, pin) == pin) ?
430 LL_AON_GPIO_INPUT_TYPE_SCHMITT : LL_AON_GPIO_INPUT_TYPE_CMOS);
458 __STATIC_INLINE
void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
460 uint32_t ps_mask = (pin_mask << AON_IO_AON_PAD_PS_POS) & AON_IO_AON_PAD_PS;
461 uint32_t pe_mask = (pin_mask << AON_IO_AON_PAD_PE_POS) & AON_IO_AON_PAD_PE;
462 uint32_t ps = (pull == LL_AON_GPIO_PULL_UP) ? ps_mask : 0x0000U;
463 uint32_t pe = (pull == LL_AON_GPIO_PULL_NO) ? 0x0000U : pe_mask;
464 MODIFY_REG(AON_IO->AON_PAD_CTRL1, pe_mask | ps_mask, pe | ps);
490 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
492 uint32_t ps_mask = (pin << AON_IO_AON_PAD_PS_POS) & AON_IO_AON_PAD_PS;
493 uint32_t pe_mask = (pin << AON_IO_AON_PAD_PE_POS) & AON_IO_AON_PAD_PE;
494 return ((READ_BITS(AON_IO->AON_PAD_CTRL1, pe_mask) == RESET) ? LL_AON_GPIO_PULL_NO :
495 ((READ_BITS(AON_IO->AON_PAD_CTRL1, ps_mask) == RESET) ? LL_AON_GPIO_PULL_DOWN : LL_AON_GPIO_PULL_UP));
529 __STATIC_INLINE
void ll_aon_gpio_set_pin_mux(uint32_t pin, uint32_t mux)
531 uint32_t pos = POSITION_VAL(pin) << 2;
532 if(LL_AON_GPIO_MUX_8 == mux)
534 CLEAR_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
538 MODIFY_REG(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
539 SET_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS);
571 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mux(uint32_t pin)
573 if(READ_BITS(AON_IO->AON_MCU_OVR, pin << AON_IO_AON_MCU_OVR_OVR_POS))
575 uint32_t pos = POSITION_VAL(pin) << 2;
576 return (READ_BITS(MCU_RET->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
580 return LL_AON_GPIO_MUX_8;
607 __STATIC_INLINE
void ll_aon_gpio_set_pin_speed(uint32_t pin_mask, uint32_t speed)
610 pos = POSITION_VAL(pin_mask);
611 MODIFY_REG(AON_IO->AON_PAD_CTRL1, pin_mask << AON_IO_AON_PAD_SR_POS, speed << pos << AON_IO_AON_PAD_SR_POS);
635 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_speed(uint32_t pin)
638 pos = POSITION_VAL(pin);
639 return (READ_BITS(AON_IO->AON_PAD_CTRL1, pin << AON_IO_AON_PAD_SR_POS) >> AON_IO_AON_PAD_SR_POS >> pos);
669 __STATIC_INLINE
void ll_aon_gpio_set_pin_strength(uint32_t pin_mask, uint32_t strength)
672 pos = POSITION_VAL(pin_mask);
673 uint8_t ds0 = (strength & LL_AON_GPIO_STRENGTH_DS0_MASK) >> LL_AON_GPIO_STRENGTH_DS0_POS;
674 uint8_t ds1 = (strength & LL_AON_GPIO_STRENGTH_DS1_MASK) >> LL_AON_GPIO_STRENGTH_DS1_POS;
675 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS0_POS , ds0 << pos << AON_IO_AON_PAD_DS0_POS);
676 MODIFY_REG(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS1_POS , ds1 << pos << AON_IO_AON_PAD_DS1_POS);
703 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_strength(uint32_t pin_mask)
706 pos = POSITION_VAL(pin_mask);
707 uint8_t ds0 = READ_BITS(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS0_POS ) >> AON_IO_AON_PAD_DS0_POS >> pos;
708 uint8_t ds1 = READ_BITS(AON_IO->AON_PAD_CTRL2, pin_mask << AON_IO_AON_PAD_DS1_POS ) >> AON_IO_AON_PAD_DS1_POS >> pos;
709 return ((ds0 << LL_AON_GPIO_STRENGTH_DS0_POS) | (ds1 << LL_AON_GPIO_STRENGTH_DS1_POS));
725 __STATIC_INLINE
void ll_aon_gpio4_enable_clk_output(uint32_t clk_sel)
727 MODIFY_REG(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL,
728 AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN | (clk_sel<<AON_IO_AON_PAD_CLK_AON_GPIO4_CLK_SEL_Pos));
740 __STATIC_INLINE
void ll_aon_gpio4_disable_clk_output(
void)
742 CLEAR_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
754 __STATIC_INLINE uint32_t ll_aon_gpio4_is_enabled_clk_output(
void)
756 return (READ_BITS(AON_IO->AON_PAD_CLK, AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN) == AON_IO_AON_PAD_CLK_AON_GPIO4_OUT_EN);
768 __STATIC_INLINE
void ll_aon_gpio_enable_xo_2mhz_output(
void)
770 SET_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
782 __STATIC_INLINE
void ll_aon_gpio_disable_xo_2mhz_output(
void)
784 CLEAR_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT);
796 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(
void)
798 return (uint32_t)(READ_BITS(AON_CTL->XO_CTRL, AON_CTL_XO_CTRL_2MHZ_OUT) == AON_CTL_XO_CTRL_2MHZ_OUT);
816 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(
void)
818 uint32_t pin_mask = (LL_AON_GPIO_PIN_ALL << AON_IO_AON_PAD_IN_VAL_POS) & AON_IO_AON_PAD_IN_VAL;
819 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) >> AON_IO_AON_PAD_IN_VAL_POS);
841 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_pin(uint32_t pin_mask)
843 pin_mask = (pin_mask << AON_IO_AON_PAD_IN_VAL_POS) & AON_IO_AON_PAD_IN_VAL;
844 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
866 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_pin(uint32_t pin_mask)
868 pin_mask = (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL;
869 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
881 __STATIC_INLINE
void ll_aon_gpio_write_output_port(uint32_t port_value)
883 MODIFY_REG(AON_IO->AON_PAD_CTRL0, AON_IO_AON_PAD_OUT_VAL, (port_value << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
895 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(
void)
897 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, AON_IO_AON_PAD_OUT_VAL) >> AON_IO_AON_PAD_OUT_VAL_POS);
919 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
921 pin_mask = (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL;
922 return (uint32_t)(READ_BITS(AON_IO->AON_PAD_CTRL0, pin_mask) == pin_mask);
944 SECTION_RAM_CODE __STATIC_INLINE
void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
946 SET_BITS(AON_IO->AON_PAD_CTRL0, (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
968 SECTION_RAM_CODE __STATIC_INLINE
void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
970 CLEAR_BITS(AON_IO->AON_PAD_CTRL0, (pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL);
992 SECTION_RAM_CODE __STATIC_INLINE
void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
994 WRITE_REG(AON_IO->AON_PAD_CTRL0, (READ_REG(AON_IO->AON_PAD_CTRL0)
995 ^ ((pin_mask << AON_IO_AON_PAD_OUT_VAL_POS) & AON_IO_AON_PAD_OUT_VAL)));
1024 __STATIC_INLINE
void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
1026 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1027 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1028 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1029 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1030 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1031 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, both, edge_en | edge_type);
1054 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
1056 uint32_t invert = ((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1057 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1058 uint32_t edge_type = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1059 return (invert && edge_en && edge_type);
1082 __STATIC_INLINE
void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
1084 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1085 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1086 uint32_t edge_type = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE;
1087 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1088 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1089 MODIFY_REG(AON_IO->EXT_WAKEUP_CTRL1, edge_type | both, edge_en);
1113 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
1115 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1116 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1117 uint32_t edge_type = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1118 return (invert && edge_en && edge_type);
1141 __STATIC_INLINE
void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
1143 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1144 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1145 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1146 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
1169 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
1171 uint32_t invert = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT)) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1172 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1173 return (invert && edge_en );
1196 __STATIC_INLINE
void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
1198 uint32_t invert = (pin_mask << AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & AON_IO_EXT_WAKEUP_CTRL0_INVERT;
1199 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1200 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, invert);
1201 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en);
1224 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
1226 uint32_t invert = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_INVERT) >> AON_IO_EXT_WAKEUP_CTRL0_INVERT_POS) & (pin_mask)) == (pin_mask);
1227 uint32_t edge_en = (((~READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN)) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1228 return (invert && edge_en);
1251 __STATIC_INLINE
void ll_aon_gpio_enable_both_trigger(uint32_t pin_mask)
1253 uint32_t edge_en = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN;
1254 uint32_t both = (pin_mask << AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH_POS) & AON_IO_EXT_WAKEUP_CTRL1_EDGE_BOTH;
1255 SET_BITS(AON_IO->EXT_WAKEUP_CTRL1, edge_en | both);
1278 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_both_trigger(uint32_t pin_mask)
1280 uint32_t edge_en = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_EN_POS) & (pin_mask)) == (pin_mask);
1281 uint32_t edge_both = ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL1, AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE) >> AON_IO_EXT_WAKEUP_CTRL1_EDGE_TYPE_POS) & (pin_mask)) == (pin_mask);
1282 return ( edge_en && edge_both);
1305 __STATIC_INLINE
void ll_aon_gpio_enable_it(uint32_t pin_mask)
1307 SET_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1330 SECTION_RAM_CODE __STATIC_INLINE
void ll_aon_gpio_disable_it(uint32_t pin_mask)
1332 CLEAR_BITS(AON_IO->EXT_WAKEUP_CTRL0, pin_mask);
1354 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
1356 return ((READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN) & (pin_mask)) == (pin_mask));
1376 __STATIC_INLINE uint32_t ll_aon_gpio_get_enabled_pin(
void)
1378 return (READ_BITS(AON_IO->EXT_WAKEUP_CTRL0, AON_IO_EXT_WAKEUP_CTRL0_SRC_EN));
1389 __STATIC_INLINE uint32_t ll_aon_gpio_is_enable_wakeup_it(
void)
1391 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_EXT) == (AON_CTL_MCU_WAKEUP_CTRL_EXT));
1420 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1422 return (READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask));
1446 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1448 return ((READ_BITS(AON_IO->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) & (pin_mask)) == (pin_mask));
1472 __STATIC_INLINE
void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1474 CLEAR_BITS(AON_IO->EXT_WAKEUP_STAT, pin_mask);
1488 __STATIC_INLINE uint32_t ll_aon_gpio_read_event_flag_it(
void)
1490 return (uint32_t)(READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_EXT) == AON_CTL_SLP_EVENT_EXT);
1502 __STATIC_INLINE
void ll_aon_gpio_clear_event_flag_it(
void)
1504 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_EXT);
1521 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);