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52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
321 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
322 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
323 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U)
324 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
325 #define HAL_DMA_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
332 #define DMA0_REQUEST_OSPI_TX LL_DMA0_PERIPH_OSPI_TX
333 #define DMA0_REQUEST_OSPI_RX LL_DMA0_PERIPH_OSPI_RX
334 #define DMA0_REQUEST_QSPI0_TX LL_DMA0_PERIPH_QSPI0_TX
335 #define DMA0_REQUEST_QSPI0_RX LL_DMA0_PERIPH_QSPI0_RX
336 #define DMA0_REQUEST_QSPI1_TX LL_DMA0_PERIPH_QSPI1_TX
337 #define DMA0_REQUEST_QSPI1_RX LL_DMA0_PERIPH_QSPI1_RX
338 #define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX
339 #define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX
340 #define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX
341 #define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX
342 #define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX
343 #define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX
344 #define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX
345 #define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX
346 #define DMA0_REQUEST_UART2_TX LL_DMA0_PERIPH_UART2_TX
347 #define DMA0_REQUEST_UART2_RX LL_DMA0_PERIPH_UART2_RX
348 #define DMA0_REQUEST_UART3_TX LL_DMA0_PERIPH_UART3_TX
349 #define DMA0_REQUEST_UART3_RX LL_DMA0_PERIPH_UART3_RX
350 #define DMA0_REQUEST_UART4_TX LL_DMA0_PERIPH_UART4_TX
351 #define DMA0_REQUEST_UART4_RX LL_DMA0_PERIPH_UART4_RX
352 #define DMA0_REQUEST_I2C2_TX LL_DMA0_PERIPH_I2C2_TX
353 #define DMA0_REQUEST_I2C2_RX LL_DMA0_PERIPH_I2C2_RX
354 #define DMA0_REQUEST_I2C3_TX LL_DMA0_PERIPH_I2C3_TX
355 #define DMA0_REQUEST_I2C3_RX LL_DMA0_PERIPH_I2C3_RX
356 #define DMA0_REQUEST_I2C4_TX LL_DMA0_PERIPH_I2C4_TX
357 #define DMA0_REQUEST_I2C4_RX LL_DMA0_PERIPH_I2C4_RX
358 #define DMA0_REQUEST_I2C5_TX LL_DMA0_PERIPH_I2C5_TX
359 #define DMA0_REQUEST_I2C5_RX LL_DMA0_PERIPH_I2C5_RX
360 #define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC
361 #define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM
364 #define DMA1_REQUEST_OSPI_TX LL_DMA1_PERIPH_OSPI_TX
365 #define DMA1_REQUEST_OSPI_RX LL_DMA1_PERIPH_OSPI_RX
366 #define DMA1_REQUEST_QSPI1_TX LL_DMA1_PERIPH_QSPI1_TX
367 #define DMA1_REQUEST_QSPI1_RX LL_DMA1_PERIPH_QSPI1_RX
368 #define DMA1_REQUEST_QSPI2_TX LL_DMA1_PERIPH_QSPI2_TX
369 #define DMA1_REQUEST_QSPI2_RX LL_DMA1_PERIPH_QSPI2_RX
370 #define DMA1_REQUEST_SPIM_TX LL_DMA1_PERIPH_SPIM_TX
371 #define DMA1_REQUEST_SPIM_RX LL_DMA1_PERIPH_SPIM_RX
372 #define DMA1_REQUEST_DSPIM_TX LL_DMA1_PERIPH_DSPIM_TX
373 #define DMA1_REQUEST_DSPIM_RX LL_DMA1_PERIPH_DSPIM_RX
374 #define DMA1_REQUEST_I2S_M_TX LL_DMA1_PERIPH_I2S_M_TX
375 #define DMA1_REQUEST_I2S_M_RX LL_DMA1_PERIPH_I2S_M_RX
376 #define DMA1_REQUEST_I2S_S_TX LL_DMA1_PERIPH_I2S_S_TX
377 #define DMA1_REQUEST_I2S_S_RX LL_DMA1_PERIPH_I2S_S_RX
378 #define DMA1_REQUEST_PDM_TX LL_DMA1_PERIPH_PDM_TX
379 #define DMA1_REQUEST_I2C0_TX LL_DMA1_PERIPH_I2C0_TX
380 #define DMA1_REQUEST_I2C0_RX LL_DMA1_PERIPH_I2C0_RX
381 #define DMA1_REQUEST_I2C1_TX LL_DMA1_PERIPH_I2C1_TX
382 #define DMA1_REQUEST_I2C1_RX LL_DMA1_PERIPH_I2C1_RX
383 #define DMA1_REQUEST_UART0_TX LL_DMA1_PERIPH_UART0_TX
384 #define DMA1_REQUEST_UART0_RX LL_DMA1_PERIPH_UART0_RX
385 #define DMA1_REQUEST_UART3_TX LL_DMA1_PERIPH_UART3_TX
386 #define DMA1_REQUEST_UART3_RX LL_DMA1_PERIPH_UART3_RX
387 #define DMA1_REQUEST_UART4_TX LL_DMA1_PERIPH_UART4_TX
388 #define DMA1_REQUEST_UART4_RX LL_DMA1_PERIPH_UART4_RX
389 #define DMA1_REQUEST_UART5_TX LL_DMA1_PERIPH_UART5_TX
390 #define DMA1_REQUEST_UART5_RX LL_DMA1_PERIPH_UART5_RX
391 #define DMA1_REQUEST_MEM LL_DMA1_PERIPH_MEM
397 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
398 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
399 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
400 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH
406 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT
407 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT
408 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE
414 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT
415 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT
416 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE
422 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE
423 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD
424 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD
430 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE
431 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD
432 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD
438 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK
439 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
446 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0
447 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_1
448 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_2
449 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_3
456 #define DMA_LLP_DST_ENABLE LL_DMA_LLP_DST_ENABLE
457 #define DMA_LLP_DST_DISABLE LL_DMA_LLP_DST_DISABLE
463 #define DMA_LLP_SRC_ENABLE LL_DMA_LLP_SRC_ENABLE
464 #define DMA_LLP_SRC_DISABLE LL_DMA_LLP_SRC_DISABLE
470 #define DMA_DST_SCATTER_ENABLE LL_DMA_DST_SCATTER_ENABLE
471 #define DMA_DST_SCATTER_DISABLE LL_DMA_DST_SCATTER_DISABLE
477 #define DMA_SRC_GATHER_ENABLE LL_DMA_SRC_GATHER_ENABLE
478 #define DMA_SRC_GATHER_DISABLE LL_DMA_SRC_GATHER_DISABLE
492 #define IS_DMA_ALL_P_INSTANCE(__p_instance__) (((__p_instance__) == DMA0) || \
493 ((__p_instance__) == DMA1))
499 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
500 ((__instance__) == DMA_Channel1) || \
501 ((__instance__) == DMA_Channel2) || \
502 ((__instance__) == DMA_Channel3) || \
503 ((__instance__) == DMA_Channel4) || \
504 ((__instance__) == DMA_Channel5))
512 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA0_REQUEST_QSPI0_TX) || \
513 ((__REQUEST__) == DMA0_REQUEST_QSPI0_RX) || \
514 ((__REQUEST__) == DMA0_REQUEST_SPIM_TX) || \
515 ((__REQUEST__) == DMA0_REQUEST_SPIM_RX) || \
516 ((__REQUEST__) == DMA0_REQUEST_SPIS_TX) || \
517 ((__REQUEST__) == DMA0_REQUEST_SPIS_RX) || \
518 ((__REQUEST__) == DMA0_REQUEST_UART0_TX) || \
519 ((__REQUEST__) == DMA0_REQUEST_UART0_RX) || \
520 ((__REQUEST__) == DMA0_REQUEST_UART1_TX) || \
521 ((__REQUEST__) == DMA0_REQUEST_UART1_RX) || \
522 ((__REQUEST__) == DMA0_REQUEST_SNSADC) || \
523 ((__REQUEST__) == DMA0_REQUEST_QSPI1_TX) || \
524 ((__REQUEST__) == DMA0_REQUEST_QSPI1_RX) || \
525 ((__REQUEST__) == DMA0_REQUEST_MEM) || \
526 ((__REQUEST__) == DMA1_REQUEST_QSPI1_TX) || \
527 ((__REQUEST__) == DMA1_REQUEST_QSPI1_RX) || \
528 ((__REQUEST__) == DMA1_REQUEST_QSPI2_TX) || \
529 ((__REQUEST__) == DMA1_REQUEST_QSPI2_RX) || \
530 ((__REQUEST__) == DMA1_REQUEST_SPIM_TX) || \
531 ((__REQUEST__) == DMA1_REQUEST_SPIM_RX) || \
532 ((__REQUEST__) == DMA1_REQUEST_DSPIM_TX) || \
533 ((__REQUEST__) == DMA1_REQUEST_DSPIM_RX) || \
534 ((__REQUEST__) == DMA1_REQUEST_I2S_M_TX) || \
535 ((__REQUEST__) == DMA1_REQUEST_I2S_M_RX) || \
536 ((__REQUEST__) == DMA1_REQUEST_I2S_S_TX) || \
537 ((__REQUEST__) == DMA1_REQUEST_I2S_S_RX) || \
538 ((__REQUEST__) == DMA1_REQUEST_PDM_TX) || \
539 ((__REQUEST__) == DMA1_REQUEST_GPADC) || \
540 ((__REQUEST__) == DMA1_REQUEST_I2C0_TX) || \
541 ((__REQUEST__) == DMA1_REQUEST_I2C0_RX) || \
542 ((__REQUEST__) == DMA1_REQUEST_I2C1_TX) || \
543 ((__REQUEST__) == DMA1_REQUEST_I2C1_RX) || \
544 ((__REQUEST__) == DMA1_REQUEST_MEM))
550 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
551 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
552 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
553 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
559 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) <= 0xFFF))
565 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
566 ((__STATE__) == DMA_SRC_DECREMENT) || \
567 ((__STATE__) == DMA_SRC_NO_CHANGE))
573 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
574 ((__STATE__) == DMA_DST_DECREMENT) || \
575 ((__STATE__) == DMA_DST_NO_CHANGE))
581 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
582 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
583 ((__SIZE__) == DMA_SDATAALIGN_WORD))
589 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
590 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
591 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
597 #define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_NORMAL ) || \
598 ((__MODE__) == DMA_CIRCULAR))
604 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
605 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
606 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
607 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
613 #define IS_DMA_SRC_GATHER_EN(__VALUE__) (((__VALUE__) == DMA_SRC_GATHER_DISABLE) || \
614 ((__VALUE__) == DMA_SRC_GATHER_ENABLE))
620 #define IS_DMA_DST_SCATTER_EN(__VALUE__) (((__VALUE__) == DMA_DST_SCATTER_DISABLE) || \
621 ((__VALUE__) == DMA_DST_SCATTER_ENABLE))
627 #define IS_DMA_LLP_SRC_EN(__VALUE__) (((__VALUE__) ==DMA_LLP_SRC_DISABLE) || \
628 ((__VALUE__) ==DMA_LLP_SRC_ENABLE))
634 #define IS_DMA_LLP_DST_EN(__VALUE__) (((__VALUE__) ==DMA_LLP_DST_DISABLE) || \
635 ((__VALUE__) ==DMA_LLP_DST_ENABLE))
hal_lock_t
HAL Lock structures definition.
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA Configuration Structure definition.
hal_status_t hal_dma_start_sg_llp_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer with Channel Disabled.
uint32_t llp_dst_writeback
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
HAL DMA State Enumerations definition.
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Enabled.
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
LL DMA sg and llp config definition.
struct dma_sg_llp_config dma_sg_llp_config_t
LL DMA sg and llp config definition.
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
Header file containing functions prototypes of DMA LL library.
@ HAL_DMA_XFER_ABORT_CB_ID
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
struct dma_block_config * head_lli
LL DMA scatter config definition.
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep. This function must be used in conjun...
__IO hal_dma_state_t state
struct dma_block_config * p_lli
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
void(* xfer_error_callback)(struct _dma_handle *p_dma)
void dma_set_renew_flag(dma_handle_t *p_dma)
set the flag if DMAn has been used before sleep
hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Diabled.
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
struct _dma_init dma_init_t
DMA Configuration Structure definition.
hal_status_t hal_dma_start_sg_llp(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer.
struct dma_scatter_config dma_scatter_config_t
LL DMA scatter config definition.
uint32_t llp_src_writeback
hal_status_t
HAL Status structures definition.
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
struct dma_gather_config dma_gather_config_t
LL DMA gather config definition.
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
uint32_t dst_data_alignment
LL DMA llp config definition.
struct dma_block_config dma_block_config_t
LL DMA block definition.
struct dma_llp_config dma_llp_config_t
LL DMA llp config definition.
LL DMA gather config definition.
hal_status_t hal_dma_start_sg_llp_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_sg_llp_config_t *sg_llp_config)
Start the DMA Transfer with Channel Enabled.
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
@ HAL_DMA_XFER_ERROR_CB_ID
dma_gather_config_t gather_config
void dma_resume_before_using(dma_handle_t *p_dma, bool init_flag)
resume dma regs before using if just waked up from sleep /only need to clear sleep_flag if on initial...
dma_llp_config_t llp_config
dma_scatter_config_t scatter_config
uint32_t src_data_alignment
DMA handle Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
HAL DMA Channel Enumerations definition.