52 #ifndef __GR55XX_LL_CALENDAR_H__
53 #define __GR55XX_LL_CALENDAR_H__
73 #define LL_CALENDAR_DIV_NONE ((uint32_t)0x00U)
74 #define LL_CALENDAR_DIV_2 ((uint32_t)0x01U << RTC_CFG1_DIV_Pos)
75 #define LL_CALENDAR_DIV_4 ((uint32_t)0x02U << RTC_CFG1_DIV_Pos)
76 #define LL_CALENDAR_DIV_8 ((uint32_t)0x03U << RTC_CFG1_DIV_Pos)
77 #define LL_CALENDAR_DIV_16 ((uint32_t)0x04U << RTC_CFG1_DIV_Pos)
78 #define LL_CALENDAR_DIV_32 ((uint32_t)0x05U << RTC_CFG1_DIV_Pos)
79 #define LL_CALENDAR_DIV_64 ((uint32_t)0x06U << RTC_CFG1_DIV_Pos)
80 #define LL_CALENDAR_DIV_128 ((uint32_t)0x07U << RTC_CFG1_DIV_Pos)
86 #define LL_CLDR_TIMER_CLK_SEL_RNG (0x0U << RTC_CLK_SEL_Pos)
87 #define LL_CLDR_TIMER_CLK_SEL_XO (0x1U << RTC_CLK_SEL_Pos)
88 #define LL_CLDR_TIMER_CLK_SEL_RNG2 (0x2U << RTC_CLK_SEL_Pos)
89 #define LL_CLDR_TIMER_CLK_SEL_RTC (0x3U << RTC_CLK_SEL_Pos)
97 #define LL_CLDR_TIMER_TICK (0x0U)
104 #define LL_CLDR_TIMER_TICK_TYPE_SINGLE (0x0U)
105 #define LL_CLDR_TIMER_TICK_TYPE_AUTO (0x1U)
111 #define CLDR_REG_READ (READ_BITS(CALENDAR->CFG0, RTC_CFG0_EN | \
112 RTC_CFG0_ALARM_EN | \
142 MODIFY_REG(CALENDAR->CLK, RTC_CLK_SEL, value);
160 return (READ_BITS(CALENDAR->CLK, RTC_CLK_SEL));
174 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_EN |
CLDR_REG_READ);
188 MODIFY_REG(CALENDAR->CFG0, 0xFFFFFFFF, RTC_CFG0_CFG);
202 return (READ_BITS(CALENDAR->CFG0, RTC_CFG0_EN) == RTC_CFG0_EN);
216 WRITE_REG(CALENDAR->TIMER_W, counter);
231 WRITE_REG(CALENDAR->TIMER_W, counter);
232 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_TIMER_SET |
CLDR_REG_READ);
246 WRITE_REG(CALENDAR->ALARM_W, alarm);
261 WRITE_REG(CALENDAR->ALARM_W, alarm);
262 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_SET |
CLDR_REG_READ);
276 return (uint32_t)READ_REG(CALENDAR->TIMER_W);
290 return (uint32_t)READ_REG(CALENDAR->TIMER_R);
304 return (uint32_t)READ_REG(CALENDAR->ALARM_W);
318 return (uint32_t)READ_REG(CALENDAR->ALARM_R);
333 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_WRAP_CNT) >> RTC_STAT_WRAP_CNT_Pos);
347 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_BUSY) == RTC_STAT_BUSY);
361 return (uint32_t)(READ_BITS(CALENDAR->STAT, RTC_STAT_STAT) == RTC_STAT_STAT);
376 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_WRAP_CLR |
CLDR_REG_READ);
399 MODIFY_REG(CALENDAR->CFG1, RTC_CFG1_DIV, div);
413 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_ALARM_EN |
CLDR_REG_READ);
427 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM);
441 WRITE_REG(CALENDAR->CFG0, (
CLDR_REG_READ & (~RTC_CFG0_ALARM_EN)) | RTC_CFG0_CFG);
455 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM);
469 return (uint32_t)((READ_BITS(CALENDAR->CFG0, RTC_CFG0_ALARM_EN) == RTC_CFG0_ALARM_EN) &&
470 (READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_ALARM) == RTC_INT_EN_ALARM));
490 WRITE_REG(CALENDAR->CFG0, (RTC_CFG0_CFG | RTC_CFG0_TICK_EN | (tick_mode << RTC_CFG0_TICK_MDOE_Pos) | (
CLDR_REG_READ & (~(1 << RTC_CFG0_TICK_MDOE_Pos)))));
507 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK);
524 WRITE_REG(CALENDAR->CFG0, (
CLDR_REG_READ & (~RTC_CFG0_TICK_EN)) | RTC_CFG0_CFG);
541 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK);
559 return (uint32_t)((READ_BITS(CALENDAR->CFG0, RTC_CFG0_TICK_EN) == RTC_CFG0_TICK_EN) &&
560 (READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_TICK) == RTC_INT_EN_TICK));
579 WRITE_REG(CALENDAR->TICK_W, counter);
580 WRITE_REG(CALENDAR->CFG0, RTC_CFG0_CFG | RTC_CFG0_TICK_SET |
CLDR_REG_READ);
594 SET_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP);
608 CLEAR_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP);
622 return (uint32_t)(READ_BITS(CALENDAR->INT_EN, RTC_INT_EN_WRAP) == RTC_INT_EN_WRAP);
644 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_ALARM) == RTC_INT_STAT_ALARM);
660 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_WRAP) == RTC_INT_STAT_WRAP);
680 return (uint32_t)(READ_BITS(CALENDAR->INT_STAT, RTC_INT_STAT_TICK) == RTC_INT_STAT_TICK);
694 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_ALARM);
708 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_WRAP);
726 WRITE_REG(CALENDAR->INT_STAT, RTC_INT_STAT_TICK);
736 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_RTC0);