Go to the documentation of this file. 1 #ifndef __GR55XX_EFUSE_LAYOUT_H__
2 #define __GR55XX_EFUSE_LAYOUT_H__
7 #define EFUSE_BT_ADDR_SIZE (6)
8 #define EFUSE_CHIP_UID_SIZE (16)
9 #define EFUSE_CHIP_ID_SIZE (6)
10 #define EFUSE_PRODUCT_ID_SIZE (2)
11 #define FW_PUBLIC_KEY_HASH_SIZE (16)
12 #define ROOT_PUBLIC_KEY_HASH_SIZE (16)
14 #define ECC_KEY_SIZE (32)
15 #define FW_KEY_SIZE (32)
16 #define HMAC_KEY_SIZE (32)
17 #define DATA_KEY_SIZE (32)
19 #define EFUSE_TRIM_PATTERN (0x4744)
21 #define EFUSE_IO_LDO_SEL_MASK (0x01)
22 #define EFUSE_IO_LDO_BYPASS_MASK (0x02)
126 uint8_t user_section[32];
efuse_ctrl_section_t backup_ctrl_section
#define EFUSE_CHIP_UID_SIZE
uint32_t enc_boot_system_clk
uint8_t chip_uid[EFUSE_CHIP_UID_SIZE]
#define EFUSE_PRODUCT_ID_SIZE
efuse_ctrl_section_t main_ctrl_section
#define EFUSE_CHIP_ID_SIZE
#define FW_PUBLIC_KEY_HASH_SIZE
efuse_key_section_t main_key_section
uint32_t memory_power_size
efuse_sadc_trim_t sadc_trim
uint8_t bt_addr[EFUSE_BT_ADDR_SIZE]
efuse_trim1_t efuse_trim1
#define EFUSE_BT_ADDR_SIZE
#define ROOT_PUBLIC_KEY_HASH_SIZE
efuse_trim0_t efuse_trim0
uint32_t enc_boot_xip_read_cmd
uint8_t lp_gain_offset_2m
uint32_t enc_boot_flash_clk
efuse_comp_trim_t comp_trim
efuse_key_section_t backup_key_section
uint32_t isp_jlink_bypass
efuse_exflash_timing_t flash_timing