52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
62 #if defined (I2S_M) || defined (I2S_S)
131 #define LL_I2S_STATUS_TXFO I2S_INT_STAT_TX_FIFO_OVER
132 #define LL_I2S_STATUS_TXFE I2S_INT_STAT_TX_FIFO_EMPTY
133 #define LL_I2S_STATUS_RXFO I2S_INT_STAT_RX_FIFO_OVER
134 #define LL_I2S_STATUS_RXDA I2S_INT_STAT_RX_DATA_AVL
141 #define LL_I2S_INT_TXFO I2S_INT_MASK_TX_FOM
142 #define LL_I2S_INT_TXFE I2S_INT_MASK_TX_FEM
143 #define LL_I2S_INT_RXFO I2S_INT_MASK_RX_FOM
144 #define LL_I2S_INT_RXDA I2S_INT_MASK_RX_DAM
150 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL)
151 #define LL_I2S_CLOCK_SRC_64M (1UL << 18)
152 #define LL_I2S_CLOCK_SRC_32M (2UL << 18)
158 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL)
159 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RX_CFG_WORD_LEN_POS)
160 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RX_CFG_WORD_LEN_POS)
161 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RX_CFG_WORD_LEN_POS)
162 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RX_CFG_WORD_LEN_POS)
163 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RX_CFG_WORD_LEN_POS)
169 #define LL_I2S_SIMPLEX_TX (1UL)
170 #define LL_I2S_SIMPLEX_RX (2UL)
171 #define LL_I2S_FULL_DUPLEX (3UL)
177 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL)
178 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
179 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
180 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
181 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
182 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
183 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
184 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
185 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
186 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
187 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
188 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
189 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
190 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
191 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
192 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RX_FIFO_CFG_RX_FIFO_TL_POS)
198 #define LL_I2S_WS_CYCLES_16 (0x00000000UL)
199 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_SCLK_CFG_WS_SCLK_POS)
200 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_SCLK_CFG_WS_SCLK_POS)
206 #define LL_I2S_SCLKG_NONE (0x00000000UL)
207 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_SCLK_CFG_SCLK_GAT_POS)
208 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_SCLK_CFG_SCLK_GAT_POS)
209 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_SCLK_CFG_SCLK_GAT_POS)
210 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_SCLK_CFG_SCLK_GAT_POS)
216 #define LL_I2S_RESOLUTION_12BIT (0UL)
217 #define LL_I2S_RESOLUTION_16BIT (1UL)
218 #define LL_I2S_RESOLUTION_20BIT (2UL)
219 #define LL_I2S_RESOLUTION_24BIT (3UL)
220 #define LL_I2S_RESOLUTION_32BIT (4UL)
226 #define LL_I2S_CHANNEL_NUM_1 (0UL)
227 #define LL_I2S_CHANNEL_NUM_2 (1UL)
228 #define LL_I2S_CHANNEL_NUM_3 (2UL)
229 #define LL_I2S_CHANNEL_NUM_4 (3UL)
235 #define LL_I2S_FIFO_DEPTH_2 (0UL)
236 #define LL_I2S_FIFO_DEPTH_4 (1UL)
237 #define LL_I2S_FIFO_DEPTH_8 (2UL)
238 #define LL_I2S_FIFO_DEPTH_16 (3UL)
244 #define LL_I2S_APB_WIDTH_8BIT (0UL)
245 #define LL_I2S_APB_WIDTH_16BIT (1UL)
246 #define LL_I2S_APB_WIDTH_32BIT (2UL)
256 #define LL_I2S_DEFAULT_CONFIG \
258 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
259 .txdata_size = LL_I2S_DATASIZE_16BIT, \
260 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
261 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
262 .clock_source = LL_I2S_CLOCK_SRC_32M, \
263 .audio_freq = 48000 \
286 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
294 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
323 SET_BITS(I2Sx->EN, I2S_EN_I2S_EN);
338 CLEAR_BITS(I2Sx->EN, I2S_EN_I2S_EN);
353 return (READ_BITS(I2Sx->EN, I2S_EN_I2S_EN) == (I2S_EN_I2S_EN));
368 SET_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN);
383 CLEAR_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN);
398 return (READ_BITS(I2Sx->RX_EN, I2S_RX_EN_RX_EN) == (I2S_RX_EN_RX_EN));
413 SET_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN);
428 CLEAR_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN);
443 return (READ_BITS(I2Sx->TX_EN, I2S_TX_EN_TX_EN) == (I2S_TX_EN_TX_EN));
458 SET_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN);
473 CLEAR_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN);
488 return (READ_BITS(I2Sx->CLK_EN, I2S_CLK_EN_CLK_EN) == (I2S_CLK_EN_CLK_EN));
508 MODIFY_REG(I2Sx->SCLK_CFG, I2S_SCLK_CFG_WS_SCLK, cycles);
526 return (uint32_t)(READ_BITS(I2Sx->SCLK_CFG, I2S_SCLK_CFG_WS_SCLK));
547 MODIFY_REG(I2Sx->SCLK_CFG, I2S_SCLK_CFG_SCLK_GAT, cycles);
567 return (uint32_t)(READ_BITS(I2Sx->SCLK_CFG, I2S_SCLK_CFG_SCLK_GAT));
582 WRITE_REG(I2Sx->RX_FIFO_RST, I2S_RX_FIFO_RST_RX_FIFO_RST);
597 WRITE_REG(I2Sx->TX_FIFO_RST, I2S_TX_FIFO_RST_TX_FIFO_RST);
612 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
626 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
640 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
654 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
668 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
686 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
702 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
716 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN);
730 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN);
744 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN) == (MCU_SUB_I2S_CLK_CFG_SRC_CLK_EN));
765 return (uint32_t)(READ_REG(I2Sx->LEFT_BUF));
780 return (uint32_t)(READ_REG(I2Sx->RIGHT_BUF));
796 WRITE_REG(I2Sx->LEFT_BUF, data);
812 WRITE_REG(I2Sx->RIGHT_BUF, data);
827 SET_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN);
842 CLEAR_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN);
857 return (READ_BITS(I2Sx->RX_CH_EN, I2S_RX_CH_EN_RX_CH_EN) == (I2S_RX_CH_EN_RX_CH_EN));
872 SET_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN);
887 CLEAR_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN);
902 return (READ_BITS(I2Sx->TX_CH_EN, I2S_TX_CH_EN_TX_CH_EN) == (I2S_TX_CH_EN_TX_CH_EN));
925 MODIFY_REG(I2Sx->RX_CFG, I2S_RX_CFG_WORD_LEN, size);
946 return (uint32_t)(READ_BITS(I2Sx->RX_CFG, I2S_RX_CFG_WORD_LEN));
969 MODIFY_REG(I2Sx->TX_CFG, I2S_TX_CFG_WORD_LEN, size);
990 return (uint32_t)(READ_BITS(I2Sx->TX_CFG, I2S_TX_CFG_WORD_LEN));
1012 return (uint32_t)(READ_BITS(I2Sx->INT_STAT, I2S_INT_STAT_TX_FIFO_OVER | I2S_INT_STAT_TX_FIFO_EMPTY | \
1013 I2S_INT_STAT_RX_FIFO_OVER | I2S_INT_STAT_RX_DATA_AVL));
1037 return (uint32_t)(READ_BITS(I2Sx->INT_STAT, flag) == flag);
1060 CLEAR_BITS(I2Sx->INT_MASK, mask);
1083 SET_BITS(I2Sx->INT_MASK, mask);
1106 return ((READ_BITS(I2Sx->INT_MASK, mask) ^ (mask)) == (mask));
1121 return (READ_BITS(I2Sx->RX_OVER, I2S_RX_OVER_RX_CLR_FDO));
1136 return (READ_BITS(I2Sx->TX_OVER, I2S_TX_OVER_TX_CLR_FDO));
1168 WRITE_REG(I2Sx->RX_FIFO_CFG, threshold);
1199 return (uint32_t)(READ_BITS(I2Sx->RX_FIFO_CFG, I2S_RX_FIFO_CFG_RX_FIFO_TL));
1231 WRITE_REG(I2Sx->TX_FIFO_CFG, threshold);
1262 return (uint32_t)(READ_BITS(I2Sx->TX_FIFO_CFG, I2S_TX_FIFO_CFG_TX_FIFO_TL));
1277 WRITE_REG(I2Sx->RX_FIFO_FLUSH, I2S_RX_FIFO_FLUSH_RX_FIFO_RST);
1292 WRITE_REG(I2Sx->TX_FIFO_FLUSH, I2S_TX_FIFO_FLUSH_TX_FIFO_RST);
1314 WRITE_REG(I2Sx->RST_RX_DMA, I2S_RST_RX_DMA_RST_RX_DMA);
1330 WRITE_REG(I2Sx->RST_TX_DMA, I2S_RST_TX_DMA_RST_TX_DMA);
1348 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1350 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1367 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1369 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1386 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET) == MCU_SUB_I2S_DMA_MODE_SET);
1388 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET) == MCU_SUB_I2S_DMA_MODE_S_SET);
1405 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1407 SET_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1424 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET);
1426 CLEAR_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET);
1444 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_SET) == MCU_SUB_I2S_DMA_MODE_SET);
1446 return (READ_BITS(MCU_SUB->I2S_DMA_MODE, MCU_SUB_I2S_DMA_MODE_S_SET) == MCU_SUB_I2S_DMA_MODE_S_SET);