Macros | |
#define | QSPI_CLOCK_MODE_0 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_1EDGE) |
#define | QSPI_CLOCK_MODE_1 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_2EDGE) |
#define | QSPI_CLOCK_MODE_2 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_1EDGE) |
#define | QSPI_CLOCK_MODE_3 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_2EDGE) |
#define QSPI_CLOCK_MODE_0 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_1EDGE) |
Inactive state of CLK is low; CLK toggles at the start of the first data bit
Definition at line 424 of file gr55xx_hal_qspi.h.
#define QSPI_CLOCK_MODE_1 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_2EDGE) |
Inactive state of CLK is low; CLK toggles in the middle of the first data bit
Definition at line 425 of file gr55xx_hal_qspi.h.
#define QSPI_CLOCK_MODE_2 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_1EDGE) |
Inactive state of CLK is high; CLK toggles at the start of the first data bit
Definition at line 426 of file gr55xx_hal_qspi.h.
#define QSPI_CLOCK_MODE_3 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_2EDGE) |
Inactive state of CLK is high; CLK toggles in the middle of the first data bit
Definition at line 427 of file gr55xx_hal_qspi.h.