51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
106 #define LL_AES_FLAG_DATAREADY AES_STAT_READY
107 #define LL_AES_FLAG_DMA_DONE AES_STAT_DMA_XFE_CPLT
108 #define LL_AES_FLAG_DMA_ERR AES_STAT_DMA_XFE_ERR
109 #define LL_AES_FLAG_KEY_VALID AES_STAT_KEY_STAT
115 #define LL_AES_KEY_SIZE_128 0x00000000U
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CFG_KEY_MODE_POS)
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CFG_KEY_MODE_POS)
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CFG_OPT_MODE_POS)
130 #define LL_AES_KEYTYPE_MCU 0x00000000U
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CFG_KEY_TYPE_POS)
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CFG_KEY_TYPE_POS)
138 #define LL_AES_DMA_TRANSIZE_MIN (1)
139 #define LL_AES_DMA_TRANSIZE_MAX (2048)
160 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
168 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
197 SET_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
212 CLEAR_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
227 return (READ_BITS(AESx->CTRL, AES_CTRL_MODULE_EN) == (AES_CTRL_MODULE_EN));
242 SET_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
257 CLEAR_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
272 return (READ_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN) == (AES_CTRL_MCU_MODE_EN));
287 SET_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
302 CLEAR_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
317 return (READ_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN) == (AES_CTRL_DMA_MODE_EN));
332 SET_BITS(AESx->CTRL, AES_CTRL_FKEY_EN);
351 MODIFY_REG(AESx->CFG, AES_CFG_KEY_MODE, size);
369 return (READ_BITS(AESx->CFG, AES_CFG_KEY_MODE));
384 SET_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
399 CLEAR_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
414 return (READ_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN) == (AES_CFG_FULL_MASK_EN));
429 SET_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
444 CLEAR_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
459 return (READ_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL) == (AES_CFG_DEC_ENC_SEL));
474 SET_BITS(AESx->CFG, AES_CFG_LOAD_SEED);
489 SET_BITS(AESx->CFG, AES_CFG_FIRST_BLK);
504 SET_BITS(AESx->CFG, AES_CFG_ENDIAN);
519 CLEAR_BITS(AESx->CFG, AES_CFG_ENDIAN);
534 return (READ_BITS(AESx->CFG, AES_CFG_ENDIAN) == (AES_CFG_ENDIAN));
552 MODIFY_REG(AESx->CFG, AES_CFG_OPT_MODE, mode);
569 return (READ_BITS(AESx->CFG, AES_CFG_OPT_MODE));
588 MODIFY_REG(AESx->CFG, AES_CFG_KEY_TYPE, Type);
606 return (READ_BITS(AESx->CFG, AES_CFG_KEY_TYPE));
627 SET_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
642 CLEAR_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
657 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_EN) == (AES_INT_CPLT_INT_EN));
678 return (READ_BITS(AESx->STAT, AES_STAT_READY) == AES_STAT_READY);
693 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_CPLT) == AES_STAT_DMA_XFE_CPLT);
708 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_ERR) == AES_STAT_DMA_XFE_ERR);
723 return (READ_BITS(AESx->STAT, AES_STAT_KEY_STAT) == AES_STAT_KEY_STAT);
738 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG) == AES_INT_CPLT_INT_FLAG);
753 SET_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG);
775 MODIFY_REG(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE, (block << 4) - 1);
790 return ((READ_BITS(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE) + 1) >> 4);
807 WRITE_REG(AESx->RD_START_ADDR, address);
822 return (READ_REG(AESx->RD_START_ADDR));
839 WRITE_REG(AESx->WR_START_ADDR, address);
854 return (READ_REG(AESx->WR_START_ADDR));
876 WRITE_REG(AESx->KEY_ADDR, address);
891 return (READ_REG(AESx->KEY_ADDR));
906 return (READ_REG(AESx->DATA_OUT0));
921 return (READ_REG(AESx->DATA_OUT1));
936 return (READ_REG(AESx->DATA_OUT2));
951 return (READ_REG(AESx->DATA_OUT3));
967 WRITE_REG(AESx->KEY0, key);
983 WRITE_REG(AESx->KEY1, key);
999 WRITE_REG(AESx->KEY2, key);
1015 WRITE_REG(AESx->KEY3, key);
1031 WRITE_REG(AESx->KEY4, key);
1047 WRITE_REG(AESx->KEY5, key);
1063 WRITE_REG(AESx->KEY6, key);
1079 WRITE_REG(AESx->KEY7, key);
1095 WRITE_REG(AESx->INIT_SSI, seed);
1110 return (READ_REG(AESx->INIT_SSI));
1126 WRITE_REG(AESx->INIT_SSO, seed);
1141 return (READ_REG(AESx->INIT_SSO));
1157 WRITE_REG(AESx->MASK_SSI, mask);
1172 return (READ_REG(AESx->MASK_SSI));
1188 WRITE_REG(AESx->MASK_SSO, mask);
1203 return (READ_REG(AESx->MASK_SSO));
1219 WRITE_REG(AESx->INIT_V0, vector);
1235 WRITE_REG(AESx->INIT_V1, vector);
1251 WRITE_REG(AESx->INIT_V2, vector);
1267 WRITE_REG(AESx->INIT_V3, vector);
1283 WRITE_REG(AESx->DATA_IN0, data);
1299 WRITE_REG(AESx->DATA_IN1, data);
1315 WRITE_REG(AESx->DATA_IN2, data);
1331 WRITE_REG(AESx->DATA_IN3, data);
1347 WRITE_REG(AESx->KEYPORT_MASK, mask);