52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
62 #if defined (DMA) || defined (DMA0) || defined (DMA1)
158 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U)
159 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
160 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
161 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
162 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
163 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
164 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
165 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
166 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
172 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M
173 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P
174 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M
175 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P
182 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U)
183 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC
184 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST
185 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST)
191 #define LL_DMA_LLP_DST_ENABLE DMA_CTLL_LLP_DST_EN_ENABLE
192 #define LL_DMA_LLP_DST_DISABLE DMA_CTLL_LLP_DST_EN_DISABLE
198 #define LL_DMA_LLP_SRC_ENABLE DMA_CTLL_LLP_SRC_EN_ENABLE
199 #define LL_DMA_LLP_SRC_DISABLE DMA_CTLL_LLP_SRC_EN_DISABLE
205 #define LL_DMA_SRC_STAT_UPDATE_ENABLE DMA_CFGH_SS_UPD_ENABLE
206 #define LL_DMA_SRC_STAT_UPDATE_DISABLE DMA_CFGH_SS_UPD_DISABLE
212 #define LL_DMA_DST_STAT_UPDATE_ENABLE DMA_CFGH_DS_UPD_ENABLE
213 #define LL_DMA_DST_STAT_UPDATE_DISABLE DMA_CFGH_DS_UPD_DISABLE
219 #define LL_DMA_DST_SCATTER_ENABLE DMA_CTLL_DST_SCATTER_EN_ENABLE
220 #define LL_DMA_DST_SCATTER_DISABLE DMA_CTLL_DST_SCATTER_EN_DISABLE
226 #define LL_DMA_SRC_GATHER_ENABLE DMA_CTLL_SRC_GATHER_EN_ENABLE
227 #define LL_DMA_SRC_GATHER_DISABLE DMA_CTLL_SRC_GATHER_EN_DISABLE
234 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC
235 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC
236 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO
242 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC
243 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC
244 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO
250 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1
251 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4
252 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8
253 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16
254 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32
255 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64
261 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1
262 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4
263 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8
264 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16
265 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32
266 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64
272 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8
273 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16
274 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32
280 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8
281 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16
282 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32
288 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0
289 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1
290 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2
291 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3
292 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4
293 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5
294 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6
295 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7
301 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U)
302 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC
308 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U)
309 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST
316 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU)
319 #define LL_DMA0_PERIPH_QSPI0_TX ((uint32_t)0x00000000U)
320 #define LL_DMA0_PERIPH_QSPI0_RX ((uint32_t)0x00000001U)
321 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U)
322 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U)
323 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U)
324 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U)
325 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U)
326 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U)
327 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U)
328 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U)
329 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU)
330 #define LL_DMA0_PERIPH_OSPI_TX ((uint32_t)0x0000000CU)
331 #define LL_DMA0_PERIPH_OSPI_RX ((uint32_t)0x0000000DU)
332 #define LL_DMA0_PERIPH_UART2_TX ((uint32_t)0x0000000EU)
333 #define LL_DMA0_PERIPH_UART2_RX ((uint32_t)0x0000000FU)
336 #define LL_DMA0_PERIPH_I2C2_TX ((uint32_t)0x00000012U)
337 #define LL_DMA0_PERIPH_I2C2_RX ((uint32_t)0x00000013U)
338 #define LL_DMA0_PERIPH_UART3_TX ((uint32_t)0x00000014U)
339 #define LL_DMA0_PERIPH_UART3_RX ((uint32_t)0x00000015U)
340 #define LL_DMA0_PERIPH_I2C5_TX ((uint32_t)0x00000016U)
341 #define LL_DMA0_PERIPH_I2C5_RX ((uint32_t)0x00000017U)
342 #define LL_DMA0_PERIPH_I2C4_TX ((uint32_t)0x00000018U)
343 #define LL_DMA0_PERIPH_I2C4_RX ((uint32_t)0x00000019U)
344 #define LL_DMA0_PERIPH_UART4_TX ((uint32_t)0x0000001AU)
345 #define LL_DMA0_PERIPH_UART4_RX ((uint32_t)0x0000001BU)
346 #define LL_DMA0_PERIPH_QSPI1_TX ((uint32_t)0x0000001CU)
347 #define LL_DMA0_PERIPH_QSPI1_RX ((uint32_t)0x0000001DU)
348 #define LL_DMA0_PERIPH_I2C3_TX ((uint32_t)0x0000001EU)
349 #define LL_DMA0_PERIPH_I2C3_RX ((uint32_t)0x0000001FU)
352 #define LL_DMA1_PERIPH_MEM ((uint32_t)0x00000009U)
355 #define LL_DMA1_PERIPH_OSPI_TX ((uint32_t)0x00000000U)
356 #define LL_DMA1_PERIPH_OSPI_RX ((uint32_t)0x00000001U)
357 #define LL_DMA1_PERIPH_QSPI2_TX ((uint32_t)0x00000002U)
358 #define LL_DMA1_PERIPH_QSPI2_RX ((uint32_t)0x00000003U)
359 #define LL_DMA1_PERIPH_I2S_M_TX ((uint32_t)0x00000004U)
360 #define LL_DMA1_PERIPH_I2S_M_RX ((uint32_t)0x00000005U)
361 #define LL_DMA1_PERIPH_I2S_S_TX ((uint32_t)0x00000006U)
362 #define LL_DMA1_PERIPH_I2S_S_RX ((uint32_t)0x00000007U)
363 #define LL_DMA1_PERIPH_PDM_TX ((uint32_t)0x00000008U)
364 #define LL_DMA1_PERIPH_QSPI1_TX ((uint32_t)0x0000000AU)
365 #define LL_DMA1_PERIPH_QSPI1_RX ((uint32_t)0x0000000BU)
366 #define LL_DMA1_PERIPH_I2C0_TX ((uint32_t)0x0000000CU)
367 #define LL_DMA1_PERIPH_I2C0_RX ((uint32_t)0x0000000DU)
368 #define LL_DMA1_PERIPH_I2C1_TX ((uint32_t)0x0000000EU)
369 #define LL_DMA1_PERIPH_I2C1_RX ((uint32_t)0x0000000FU)
372 #define LL_DMA1_PERIPH_SPIM_TX ((uint32_t)0x00000010U)
373 #define LL_DMA1_PERIPH_SPIM_RX ((uint32_t)0x00000011U)
374 #define LL_DMA1_PERIPH_DSPIM_TX ((uint32_t)0x00000012U)
375 #define LL_DMA1_PERIPH_DSPIM_RX ((uint32_t)0x00000013U)
376 #define LL_DMA1_PERIPH_QSPI1_TX_2 ((uint32_t)0x00000014U)
377 #define LL_DMA1_PERIPH_QSPI1_RX_2 ((uint32_t)0x00000015U)
378 #define LL_DMA1_PERIPH_UART3_TX ((uint32_t)0x00000016U)
379 #define LL_DMA1_PERIPH_UART3_RX ((uint32_t)0x00000017U)
380 #define LL_DMA1_PERIPH_UART4_TX ((uint32_t)0x00000018U)
381 #define LL_DMA1_PERIPH_UART4_RX ((uint32_t)0x00000019U)
382 #define LL_DMA1_PERIPH_UART5_TX ((uint32_t)0x0000001AU)
383 #define LL_DMA1_PERIPH_UART5_RX ((uint32_t)0x0000001BU)
384 #define LL_DMA1_PERIPH_UART0_TX ((uint32_t)0x0000001EU)
385 #define LL_DMA1_PERIPH_UART0_RX ((uint32_t)0x0000001FU)
407 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
415 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
446 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
465 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
480 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
506 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
530 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
556 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
582 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
607 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
631 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
655 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
694 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
695 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
724 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
752 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
781 __STATIC_INLINE
void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
783 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
812 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
838 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
864 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
890 MODIFY_REG(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT, sstat);
916 return READ_BITS(DMAx->CHANNEL[channel].SSTAT, DMA_SSTAT_SSTAT);
942 MODIFY_REG(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT, dstat);
967 return READ_BITS(DMAx->CHANNEL[channel].DSTAT, DMA_DSTAT_DSTAT);
993 MODIFY_REG(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR, sstatar);
1018 return READ_BITS(DMAx->CHANNEL[channel].SSTATAR, DMA_SSTATAR_SSTATAR);
1044 MODIFY_REG(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR, dstatar);
1069 return READ_BITS(DMAx->CHANNEL[channel].DSTATAR, DMA_DSTATAR_DSTATAR);
1095 MODIFY_REG(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC, llp_loc);
1120 return READ_BITS(DMAx->CHANNEL[channel].LLP, DMA_LLP_LOC);
1147 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN, llp_dst_en);
1173 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_DST_EN);
1200 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN, llp_src_en);
1226 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_LLP_SRC_EN);
1253 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN, dst_scatter_en);
1279 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_SCATTER_EN);
1306 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN, src_gather_en);
1332 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_GATHER_EN);
1360 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
1387 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
1415 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
1442 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
1470 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
1497 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
1525 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
1552 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
1580 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
1607 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1635 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1662 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1695 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1727 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1753 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1779 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1813 uint32_t src_address,
1814 uint32_t dst_address,
1817 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1818 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1819 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1844 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1869 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1893 return READ_REG(DMAx->CHANNEL[channel].SAR);
1917 return READ_REG(DMAx->CHANNEL[channel].DAR);
1943 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1944 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1971 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1972 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1997 return READ_REG(DMAx->CHANNEL[channel].SAR);
2022 return READ_REG(DMAx->CHANNEL[channel].DAR);
2252 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
2275 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
2361 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
2384 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
2414 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
2415 src_handshaking | dst_handshaking);
2441 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI, src_gather_sgi << DMA_SGR_SGI_Pos );
2466 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGI) >> DMA_SGR_SGI_Pos);
2492 MODIFY_REG(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC, src_gather_sgc << DMA_SGR_SGC_Pos );
2517 return (READ_BITS(DMAx->CHANNEL[channel].SGR, DMA_SGR_SGC) >> DMA_SGR_SGC_Pos);
2543 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI, dst_scatter_dsi << DMA_DSR_DSI_Pos );
2568 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSI) >> DMA_DSR_DSI_Pos);
2594 MODIFY_REG(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC, dst_scatter_dsc << DMA_DSR_DSC_Pos );
2619 return (READ_BITS(DMAx->CHANNEL[channel].DSR, DMA_DSR_DSC) >> DMA_DSR_DSC_Pos);
2644 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2645 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2669 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2695 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
2696 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2697 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2722 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
2723 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
2748 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2749 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2773 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2799 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
2800 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2801 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2826 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
2827 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
2848 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
2863 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
2878 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
2893 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
2908 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
2932 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
2956 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2980 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
3004 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
3028 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
3052 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
3067 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
3082 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
3097 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
3112 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
3127 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
3142 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 5)) == (1 << 5));
3157 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 6)) == (1 << 6));
3172 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 7)) == (1 << 7));
3196 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
3211 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
3226 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
3241 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
3256 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
3271 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
3286 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 5)) == (1 << 5));
3301 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 6)) == (1 << 6));
3316 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 7)) == (1 << 7));
3340 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
3355 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
3370 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
3385 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
3400 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
3415 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
3430 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 5)) == (1 << 5));
3445 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 6)) == (1 << 6));
3460 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 7)) == (1 << 7));
3484 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
3499 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
3514 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
3529 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
3544 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
3559 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
3574 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 5)) == (1 << 5));
3589 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 6)) == (1 << 6));
3604 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 7)) == (1 << 7));
3628 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
3643 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
3658 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
3673 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
3688 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
3703 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
3718 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 5)) == (1 << 5));
3733 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 6)) == (1 << 6));
3748 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 7)) == (1 << 7));
3772 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
3787 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
3802 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
3817 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
3832 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
3847 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
3862 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 5));
3877 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 6));
3892 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 7));
3916 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
3931 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
3946 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
3961 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
3976 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
3991 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
4006 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 5));
4021 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 6));
4036 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 7));
4060 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
4075 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
4090 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
4105 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
4120 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
4135 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
4150 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 5));
4165 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 6));
4180 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 7));
4204 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
4219 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
4234 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
4249 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
4264 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
4279 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
4294 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 5));
4309 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 6));
4324 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 7));
4348 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
4363 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
4378 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
4393 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
4408 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
4423 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
4438 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 5));
4453 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 6));
4468 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 7));
4498 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
4522 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
4546 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
4570 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
4594 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
4618 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
4642 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
4666 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
4690 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
4714 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
4738 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
4762 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
4786 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
4810 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
4834 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
4858 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
4882 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
4906 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
4969 error_status_t
ll_dma_hs_choice(dma_regs_t *DMAx, uint32_t src_peripheral, uint32_t dst_peripheral);