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52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
62 #if defined (SPIM) || defined (SPIS)
152 #define LL_SPI_SR_DCOL SPI_STAT_DATA_COLN_ERR
153 #define LL_SPI_SR_TXE SPI_STAT_TX_ERR
154 #define LL_SPI_SR_RFF SPI_STAT_RX_FIFO_FULL
155 #define LL_SPI_SR_RFNE SPI_STAT_RX_FIFO_NE
156 #define LL_SPI_SR_TFE SPI_STAT_TX_FIFO_EMPTY
157 #define LL_SPI_SR_TFNF SPI_STAT_TX_FIFO_NF
158 #define LL_SPI_SR_BUSY SPI_STAT_SSI_BUSY
165 #define LL_SPI_IM_MST SPI_INT_MASK_MULTI_M_CIM
166 #define LL_SPI_IM_RXF SPI_INT_MASK_RX_FIFO_FIM
167 #define LL_SPI_IM_RXO SPI_INT_MASK_RX_FIFO_OIM
168 #define LL_SPI_IM_RXU SPI_INT_MASK_RX_FIFO_UIM
169 #define LL_SPI_IM_TXO SPI_INT_MASK_TX_FIFO_OIM
170 #define LL_SPI_IM_TXE SPI_INT_MASK_TX_FIFO_EIM
172 #define LL_SPI_IS_MST SPI_INT_STAT_MULTI_M_CIS
173 #define LL_SPI_IS_RXF SPI_INT_STAT_RX_FIFO_FIS
174 #define LL_SPI_IS_RXO SPI_INT_STAT_RX_FIFO_OIS
175 #define LL_SPI_IS_RXU SPI_INT_STAT_RX_FIFO_UIS
176 #define LL_SPI_IS_TXO SPI_INT_STAT_TX_FIFO_OIS
177 #define LL_SPI_IS_TXE SPI_INT_STAT_TX_FIFO_EIS
179 #define LL_SPI_RIS_MST SPI_RAW_INT_STAT_MULTI_M_CRIS
180 #define LL_SPI_RIS_RXF SPI_RAW_INT_STAT_RX_FIFO_FRIS
181 #define LL_SPI_RIS_RXO SPI_RAW_INT_STAT_RX_FIFO_ORIS
182 #define LL_SPI_RIS_RXU SPI_RAW_INT_STAT_RX_FIFO_URIS
183 #define LL_SPI_RIS_TXO SPI_RAW_INT_STAT_TX_FIFO_ORIS
184 #define LL_SPI_RIS_TXE SPI_RAW_INT_STAT_TX_FIFO_ERIS
190 #define LL_SPI_DATASIZE_4BIT (3UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
191 #define LL_SPI_DATASIZE_5BIT (4UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
192 #define LL_SPI_DATASIZE_6BIT (5UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
193 #define LL_SPI_DATASIZE_7BIT (6UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
194 #define LL_SPI_DATASIZE_8BIT (7UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
195 #define LL_SPI_DATASIZE_9BIT (8UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
196 #define LL_SPI_DATASIZE_10BIT (9UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
197 #define LL_SPI_DATASIZE_11BIT (10UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
198 #define LL_SPI_DATASIZE_12BIT (11UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
199 #define LL_SPI_DATASIZE_13BIT (12UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
200 #define LL_SPI_DATASIZE_14BIT (13UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
201 #define LL_SPI_DATASIZE_15BIT (14UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
202 #define LL_SPI_DATASIZE_16BIT (15UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
203 #define LL_SPI_DATASIZE_17BIT (16UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
204 #define LL_SPI_DATASIZE_18BIT (17UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
205 #define LL_SPI_DATASIZE_19BIT (18UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
206 #define LL_SPI_DATASIZE_20BIT (19UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
207 #define LL_SPI_DATASIZE_21BIT (20UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
208 #define LL_SPI_DATASIZE_22BIT (21UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
209 #define LL_SPI_DATASIZE_23BIT (22UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
210 #define LL_SPI_DATASIZE_24BIT (23UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
211 #define LL_SPI_DATASIZE_25BIT (24UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
212 #define LL_SPI_DATASIZE_26BIT (25UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
213 #define LL_SPI_DATASIZE_27BIT (26UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
214 #define LL_SPI_DATASIZE_28BIT (27UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
215 #define LL_SPI_DATASIZE_29BIT (28UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
216 #define LL_SPI_DATASIZE_30BIT (29UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
217 #define LL_SPI_DATASIZE_31BIT (30UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
218 #define LL_SPI_DATASIZE_32BIT (31UL << SPI_CTRL0_DATA_FRAME_SIZE_POS)
224 #define LL_SPI_MW_CMDSIZE_1BIT 0x00000000UL
225 #define LL_SPI_MW_CMDSIZE_2BIT (1UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
226 #define LL_SPI_MW_CMDSIZE_3BIT (2UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
227 #define LL_SPI_MW_CMDSIZE_4BIT (3UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
228 #define LL_SPI_MW_CMDSIZE_5BIT (4UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
229 #define LL_SPI_MW_CMDSIZE_6BIT (5UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
230 #define LL_SPI_MW_CMDSIZE_7BIT (6UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
231 #define LL_SPI_MW_CMDSIZE_8BIT (7UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
232 #define LL_SPI_MW_CMDSIZE_9BIT (8UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
233 #define LL_SPI_MW_CMDSIZE_10BIT (9UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
234 #define LL_SPI_MW_CMDSIZE_11BIT (10UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
235 #define LL_SPI_MW_CMDSIZE_12BIT (11UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
236 #define LL_SPI_MW_CMDSIZE_13BIT (12UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
237 #define LL_SPI_MW_CMDSIZE_14BIT (13UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
238 #define LL_SPI_MW_CMDSIZE_15BIT (14UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
239 #define LL_SPI_MW_CMDSIZE_16BIT (15UL << SPI_CTRL0_CTRL_FRAME_SIZE_POS)
245 #define LL_SPI_NORMAL_MODE 0x00000000UL
246 #define LL_SPI_TEST_MODE (1UL << SPI_CTRL0_SHIFT_REG_LOOP_POS)
252 #define LL_SPI_SLAVE_OUTDIS 0x00000000UL
253 #define LL_SPI_SLAVE_OUTEN (1UL << SPI_CTRL0_S_OUT_EN_POS)
259 #define LL_SPI_FULL_DUPLEX 0x00000000UL
260 #define LL_SPI_SIMPLEX_TX (1UL << SPI_CTRL0_XFE_MODE_POS)
261 #define LL_SPI_SIMPLEX_RX (2UL << SPI_CTRL0_XFE_MODE_POS)
262 #define LL_SPI_READ_EEPROM (3UL << SPI_CTRL0_XFE_MODE_POS)
268 #define LL_SPI_SCPHA_1EDGE 0x00000000UL
269 #define LL_SPI_SCPHA_2EDGE (1UL << SPI_CTRL0_SERIAL_CLK_PHASE_POS)
275 #define LL_SPI_SCPOL_LOW 0x00000000UL
276 #define LL_SPI_SCPOL_HIGH (1UL << SPI_CTRL0_SERIAL_CLK_POL_POS)
282 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000UL
283 #define LL_SPI_PROTOCOL_TI (1UL << SPI_CTRL0_FRAME_FORMAT_POS)
284 #define LL_SPI_PROTOCOL_MICROWIRE (2UL << SPI_CTRL0_FRAME_FORMAT_POS)
290 #define LL_SPI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL
291 #define LL_SPI_MICROWIRE_HANDSHAKE_EN (1UL << SPI_MW_CTRL_MW_HSG_POS)
293 #define LL_SPI_MICROWIRE_RX 0x00000000UL
294 #define LL_SPI_MICROWIRE_TX (1UL << SPI_MW_CTRL_MW_DIR_DW_POS)
296 #define LL_SPI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL
297 #define LL_SPI_MICROWIRE_SEQUENTIAL (1UL << SPI_MW_CTRL_MW_XFE_MODE_POS)
303 #define LL_SPI_SLAVE1 SPI_SLA_S1_SEL_EN
304 #define LL_SPI_SLAVE0 SPI_SLA_S0_SEL_EN
310 #define LL_SPI_DMA_TX_DIS 0x00000000UL
311 #define LL_SPI_DMA_TX_EN SPI_DMA_CTRL_TX_DMA_EN
313 #define LL_SPI_DMA_RX_DIS 0x00000000UL
314 #define LL_SPI_DMA_RX_EN SPI_DMA_CTRL_RX_DMA_EN
320 #define LL_SPI_M_FIFO_DEPTH (16u)
321 #define LL_SPI_S_FIFO_DEPTH (16u)
327 #define LL_SPIM_DEFAULT_CONFIG \
329 .transfer_direction = LL_SPI_FULL_DUPLEX, \
330 .data_size = LL_SPI_DATASIZE_8BIT, \
331 .clock_polarity = LL_SPI_SCPOL_LOW, \
332 .clock_phase = LL_SPI_SCPHA_1EDGE, \
333 .slave_select = LL_SPI_SLAVE0, \
334 .baud_rate = SystemCoreClock / 2000000, \
335 .rx_sample_delay = 0, \
341 #define LL_SPIS_DEFAULT_CONFIG \
343 .data_size = LL_SPI_DATASIZE_8BIT, \
344 .clock_polarity = LL_SPI_SCPOL_LOW, \
345 .clock_phase = LL_SPI_SCPHA_1EDGE, \
365 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
373 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
403 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
419 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN);
435 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_ST_EN) == (SPI_CTRL0_S_ST_EN));
480 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE, size);
524 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_DATA_FRAME_SIZE));
557 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE, size);
589 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_CTRL_FRAME_SIZE));
604 SET_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
619 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP);
634 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_SHIFT_REG_LOOP) == (SPI_CTRL0_SHIFT_REG_LOOP));
649 CLEAR_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
664 SET_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN);
679 return (READ_BITS(SPIx->CTRL0, SPI_CTRL0_S_OUT_EN) != (SPI_CTRL0_S_OUT_EN));
699 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_XFE_MODE, transfer_direction);
718 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_XFE_MODE));
738 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL, clock_polarity);
755 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_POL));
775 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE, clock_phase);
792 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_SERIAL_CLK_PHASE));
812 MODIFY_REG(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT, standard);
830 return (uint32_t)(READ_BITS(SPIx->CTRL0, SPI_CTRL0_FRAME_FORMAT));
849 MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME, size);
867 return (uint32_t)(READ_BITS(SPIx->CTRL1, SPI_CTRL1_NUM_DATA_FRAME));
882 SET_BITS(SPIx->SSI_EN, SPI_SSI_EN);
898 CLEAR_BITS(SPIx->SSI_EN, SPI_SSI_EN);
913 return (READ_BITS(SPIx->SSI_EN, SPI_SSI_EN) == (SPI_SSI_EN));
928 SET_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
943 CLEAR_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG);
958 return (READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_HSG) == (SPI_MW_CTRL_MW_HSG));
977 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW, transfer_direction);
995 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_DIR_DW));
1014 MODIFY_REG(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE, transfer_mode);
1032 return (uint32_t)(READ_BITS(SPIx->MW_CTRL, SPI_MW_CTRL_MW_XFE_MODE));
1051 SET_BITS(SPIx->S_EN, ss);
1070 CLEAR_BITS(SPIx->S_EN, ss);
1089 return (READ_BITS(SPIx->S_EN, ss) == ss);
1106 WRITE_REG(SPIx->BAUD, baud_rate);
1121 return (uint32_t)(READ_BITS(SPIx->BAUD, SPI_BAUD_CLK_DIV));
1137 WRITE_REG(SPIx->TX_FIFO_TL, threshold);
1152 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_TL, SPI_TX_FIFO_TL_TX_FIFO_THD));
1168 WRITE_REG(SPIx->RX_FIFO_TL, threshold);
1183 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_TL, SPI_RX_FIFO_TL_RX_FIFO_THD));
1198 return (uint32_t)(READ_BITS(SPIx->TX_FIFO_LEVEL, SPI_TX_FIFO_LEVEL_TX_FIFO_LEVEL));
1213 return (uint32_t)(READ_BITS(SPIx->RX_FIFO_LEVEL, SPI_RX_FIFO_LEVEL_RX_FIFO_LEVEL));
1242 SET_BITS(SPIx->INT_MASK, mask);
1265 CLEAR_BITS(SPIx->INT_MASK, mask);
1287 return (READ_BITS(SPIx->INT_MASK, mask) == mask);
1315 return (uint32_t)(READ_REG(SPIx->STAT));
1344 return (READ_BITS(SPIx->STAT, flag) == (flag));
1365 return (uint32_t)(READ_REG(SPIx->INT_STAT));
1392 return (READ_BITS(SPIx->INT_STAT, flag) == flag);
1413 return (uint32_t)(READ_REG(SPIx->RAW_INT_STAT));
1429 __IOM uint32_t tmpreg;
1430 tmpreg = SPIx->TX_FIFO_OIC;
1447 __IOM uint32_t tmpreg;
1448 tmpreg = SPIx->RX_FIFO_OIC;
1465 __IOM uint32_t tmpreg;
1466 tmpreg = SPIx->RX_FIFO_UIC;
1483 __IOM uint32_t tmpreg;
1484 tmpreg = SPIx->MULTI_M_IC;
1501 __IOM uint32_t tmpreg;
1502 tmpreg = SPIx->INT_CLR;
1524 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1539 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN);
1554 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_TX_DMA_EN) == (SPI_DMA_CTRL_TX_DMA_EN));
1569 SET_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1584 CLEAR_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN);
1599 return (READ_BITS(SPIx->DMA_CTRL, SPI_DMA_CTRL_RX_DMA_EN) == (SPI_DMA_CTRL_RX_DMA_EN));
1615 WRITE_REG(SPIx->DMA_TX_DL, threshold);
1630 return (uint32_t)(READ_BITS(SPIx->DMA_TX_DL, SPI_DMA_TX_DL_DMA_TX_DL));
1646 WRITE_REG(SPIx->DMA_RX_DL, threshold);
1661 return (uint32_t)(READ_BITS(SPIx->DMA_RX_DL, SPI_DMA_RX_DL_DMA_RX_DL));
1683 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1699 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1715 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1730 return (uint8_t)(READ_REG(SPIx->DATA));
1745 return (uint16_t)(READ_REG(SPIx->DATA));
1760 return (uint32_t)(READ_REG(SPIx->DATA));
1777 MODIFY_REG(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY, delay);
1793 return (uint32_t)(READ_BITS(SPIx->RX_SAMPLE_DLY, SPI_RX_SAMPLEDLY));
__STATIC_INLINE void ll_spi_enable_dma_req_rx(spi_regs_t *SPIx)
Enable DMA Rx.
__STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(spi_regs_t *SPIx)
Check if SPI test mode is enabled.
__STATIC_INLINE void ll_spi_set_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an TXE event.
__STATIC_INLINE void ll_spi_transmit_data8(spi_regs_t *SPIx, uint8_t tx_data)
Write 8-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(spi_regs_t *SPIx)
Get Rx sample delay.
__STATIC_INLINE void ll_spi_disable_dma_req_rx(spi_regs_t *SPIx)
Disable DMA Rx.
SPIS init structures definition.
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an TXE event.
__STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an DMA Rx request event.
void ll_spim_struct_init(ll_spim_init_t *p_spi_init)
Set each field of a ll_spim_init_t type structure to default value.
__STATIC_INLINE void ll_spi_enable_ss(spi_regs_t *SPIx, uint32_t ss)
Enable slave select.
error_status_t ll_spis_init(spi_regs_t *SPIx, ll_spis_init_t *p_spi_init)
Initialize SSI registers according to the specified parameters in p_spi_init.
__STATIC_INLINE void ll_spi_enable_ss_toggle(spi_regs_t *SPIx)
Enable slave select toggle.
__STATIC_INLINE void ll_spi_enable_it(spi_regs_t *SPIx, uint32_t mask)
Enable interrupt.
__STATIC_INLINE void ll_spi_enable_test_mode(spi_regs_t *SPIx)
Enable SPI test mode.
__STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of TXFIFO that triggers an DMA Tx request event.
LL SPIM init structures definition.
__STATIC_INLINE void ll_spi_enable_slave_out(spi_regs_t *SPIx)
Enable slave output.
__STATIC_INLINE void ll_spi_set_receive_size(spi_regs_t *SPIx, uint32_t size)
Set the number of data frames to be continuously received.
__STATIC_INLINE void ll_spi_set_rx_sample_delay(spi_regs_t *SPIx, uint32_t delay)
Set Rx sample delay.
__STATIC_INLINE uint32_t ll_spi_is_active_flag(spi_regs_t *SPIx, uint32_t flag)
Check active flag.
error_status_t ll_spim_init(spi_regs_t *SPIx, ll_spim_init_t *p_spi_init)
Initialize SPIM registers according to the specified parameters in p_spi_init.
__STATIC_INLINE void ll_spi_enable(spi_regs_t *SPIx)
Enable SPI peripheral.
void ll_spis_struct_init(ll_spis_init_t *p_spi_init)
Set each field of a ll_spis_init_t type structure to default value.
__STATIC_INLINE void ll_spi_clear_flag_all(spi_regs_t *SPIx)
Clear all error flag.
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void ll_spi_enable_micro_handshake(spi_regs_t *SPIx)
Enable Handshake in Microwire mode.
__STATIC_INLINE void ll_spi_disable_ss_toggle(spi_regs_t *SPIx)
Disable slave select toggle.
__STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(spi_regs_t *SPIx)
Get SPI raw interrupt flags.
__STATIC_INLINE void ll_spi_disable_salve_out(spi_regs_t *SPIx)
Disable slave output.
__STATIC_INLINE uint32_t ll_spi_get_it_flag(spi_regs_t *SPIx)
Get SPI interrupt flags.
__STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an DMA Rx request event.
__STATIC_INLINE void ll_spi_disable(spi_regs_t *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t ll_spi_receive_data32(spi_regs_t *SPIx)
Read 32-Bits in the data register.
__STATIC_INLINE void ll_spi_set_baud_rate_prescaler(spi_regs_t *SPIx, uint32_t baud_rate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(spi_regs_t *SPIx)
Get threshold of TXFIFO that triggers an DMA Tx request event.
struct _ll_spim_init_t ll_spim_init_t
LL SPIM init structures definition.
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(spi_regs_t *SPIx)
Check if Handshake in Microwire mode is enabled.
__STATIC_INLINE uint32_t ll_spi_get_control_frame_size(spi_regs_t *SPIx)
Get the length of the control word for the Microwire frame format.
uint32_t transfer_direction
__STATIC_INLINE void ll_spi_transmit_data16(spi_regs_t *SPIx, uint16_t tx_data)
Write 16-Bits in the data register.
__STATIC_INLINE void ll_spi_set_standard(spi_regs_t *SPIx, uint32_t standard)
Set serial protocol used.
struct _ll_spis_init_t ll_spis_init_t
SPIS init structures definition.
__STATIC_INLINE uint32_t ll_spi_get_status(spi_regs_t *SPIx)
Get SPI status.
__STATIC_INLINE uint32_t ll_spi_get_data_size(spi_regs_t *SPIx)
Get frame data size.
__STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(spi_regs_t *SPIx)
Get transfer mode in Microwire mode.
__STATIC_INLINE void ll_spi_set_clock_polarity(spi_regs_t *SPIx, uint32_t clock_polarity)
Set clock polarity.
__STATIC_INLINE void ll_spi_set_micro_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(spi_regs_t *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(spi_regs_t *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t ll_spi_is_enabled(spi_regs_t *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void ll_spi_set_data_size(spi_regs_t *SPIx, uint32_t size)
Set frame data size.
__STATIC_INLINE void ll_spi_enable_dma_req_tx(spi_regs_t *SPIx)
Enable DMA Tx.
__STATIC_INLINE void ll_spi_disable_ss(spi_regs_t *SPIx, uint32_t ss)
Disable slave select.
__STATIC_INLINE void ll_spi_set_rx_fifo_threshold(spi_regs_t *SPIx, uint32_t threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void ll_spi_disable_micro_handshake(spi_regs_t *SPIx)
Disable Handshake in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_get_receive_size(spi_regs_t *SPIx)
Get the number of data frames to be continuously received.
__STATIC_INLINE uint32_t ll_spi_get_clock_phase(spi_regs_t *SPIx)
Get clock phase.
__STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(spi_regs_t *SPIx)
Get FIFO reception Level.
error_status_t ll_spim_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE void ll_spi_disable_dma_req_tx(spi_regs_t *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(spi_regs_t *SPIx)
Get baud rate prescaler.
__STATIC_INLINE uint16_t ll_spi_receive_data16(spi_regs_t *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(spi_regs_t *SPIx)
Check if slave output is enabled.
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(spi_regs_t *SPIx)
Check if slave select toggle is enabled.
__STATIC_INLINE uint32_t ll_spi_get_standard(spi_regs_t *SPIx)
Get serial protocol used.
__STATIC_INLINE void ll_spi_clear_flag_rxo(spi_regs_t *SPIx)
Clear receive FIFO overflow error flag.
__STATIC_INLINE void ll_spi_clear_flag_txo(spi_regs_t *SPIx)
Clear transmit FIFO overflow error flag.
__STATIC_INLINE void ll_spi_transmit_data32(spi_regs_t *SPIx, uint32_t tx_data)
Write 32-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_get_transfer_direction(spi_regs_t *SPIx)
Get transfer direction mode.
__STATIC_INLINE uint32_t ll_spi_is_it_flag(spi_regs_t *SPIx, uint32_t flag)
Check interrupt flag.
__STATIC_INLINE void ll_spi_set_control_frame_size(spi_regs_t *SPIx, uint32_t size)
Set the length of the control word for the Microwire frame format.
__STATIC_INLINE uint8_t ll_spi_receive_data8(spi_regs_t *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(spi_regs_t *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void ll_spi_set_clock_phase(spi_regs_t *SPIx, uint32_t clock_phase)
Set clock phase.
__STATIC_INLINE void ll_spi_disable_it(spi_regs_t *SPIx, uint32_t mask)
Disable interrupt.
__STATIC_INLINE void ll_spi_set_micro_transfer_mode(spi_regs_t *SPIx, uint32_t transfer_mode)
Set transfer mode in Microwire mode.
__STATIC_INLINE uint32_t ll_spi_is_enabled_ss(spi_regs_t *SPIx, uint32_t ss)
Check if slave select is enabled.
__STATIC_INLINE uint32_t ll_spi_is_enabled_it(spi_regs_t *SPIx, uint32_t mask)
Check if interrupt is enabled.
__STATIC_INLINE void ll_spi_set_transfer_direction(spi_regs_t *SPIx, uint32_t transfer_direction)
Set transfer direction mode.
__STATIC_INLINE void ll_spi_disable_test_mode(spi_regs_t *SPIx)
Disable SPI test mode.
error_status_t ll_spis_deinit(spi_regs_t *SPIx)
De-initialize SSI registers (Registers restored to their default values).
__STATIC_INLINE void ll_spi_clear_flag_mst(spi_regs_t *SPIx)
Clear multi-master error flag.
__STATIC_INLINE uint32_t ll_spi_get_clock_polarity(spi_regs_t *SPIx)
Get clock polarity.
__STATIC_INLINE void ll_spi_clear_flag_rxu(spi_regs_t *SPIx)
Clear receive FIFO underflow error flag.