52 #ifndef __GR55XX_LL_COMP_H__
53 #define __GR55XX_LL_COMP_H__
76 typedef struct _ll_comp_init
78 uint32_t input_source;
121 #define LL_COMP_INPUT_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
122 #define LL_COMP_INPUT_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
123 #define LL_COMP_INPUT_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
124 #define LL_COMP_INPUT_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
125 #define LL_COMP_INPUT_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
126 #define LL_COMP_INPUT_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
127 #define LL_COMP_INPUT_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
128 #define LL_COMP_INPUT_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
130 #define LL_COMP_INPUT_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
131 #define LL_COMP_INPUT_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Pos)
138 #define LL_COMP_REF_SRC_IO0 (0UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
139 #define LL_COMP_REF_SRC_IO1 (1UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
140 #define LL_COMP_REF_SRC_IO2 (2UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
141 #define LL_COMP_REF_SRC_IO3 (3UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
142 #define LL_COMP_REF_SRC_IO4 (4UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
143 #define LL_COMP_REF_SRC_IO5 (5UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
144 #define LL_COMP_REF_SRC_IO6 (6UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
145 #define LL_COMP_REF_SRC_IO7 (7UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
147 #define LL_COMP_REF_SRC_VBAT (9UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
148 #define LL_COMP_REF_SRC_VREF (10UL << AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Pos)
154 #define LL_COMP_HYST_POSITIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_HYST_Pos )
155 #define LL_COMP_HYST_NEGATIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_HYST_Pos )
162 #define LL_COMP_RES_DEGENERATION_POSITIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_RES_DEGENERATION_Pos )
163 #define LL_COMP_RES_DEGENERATION_NEGATIVE (1UL << AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_RES_DEGENERATION_Pos )
169 #define LL_COMP_WAKEUP_EDGE_BOTH ( 0UL )
170 #define LL_COMP_WAKEUP_EDGE_FALLING ( 1UL )
171 #define LL_COMP_WAKEUP_EDGE_RISING ( 2UL )
193 #define LL_COMP_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
201 #define LL_COMP_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
222 #define LL_COMP_DEFAULT_CONFIG \
224 .channel_p = LL_COMP_CHANNEL_IO0, \
225 .channel_n = LL_COMP_CHANNEL_IO1, \
251 __STATIC_INLINE
void ll_comp_enable(
void)
253 SET_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
265 __STATIC_INLINE
void ll_comp_disable(
void)
267 CLEAR_BITS(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_WAKE_COMP_EN_Msk);
290 __STATIC_INLINE
void ll_comp_set_input_src(uint32_t source)
292 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_P_Msk, source);
315 __STATIC_INLINE
void ll_comp_set_ref_src(uint32_t source)
317 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_CHANNEL_SEL_N_Msk, source);
331 __STATIC_INLINE
void ll_comp_set_vbatt_lvl(uint32_t level)
333 SET_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_VBAT_EN_Msk);
334 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_COMP_BATT_LVL_CTRL_LV_Pos);
348 __STATIC_INLINE
void ll_comp_set_vref_lvl(uint32_t level)
350 SET_BITS(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_VREF_EN_Msk);
351 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_COMP_REF_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_COMP_REF_CTRL_LV_Pos);
364 __STATIC_INLINE
void ll_comp_set_current(uint32_t level)
366 MODIFY_REG(AON_PMU->COMP_REG_0, AON_PMU_COMP_REG_0_ICOMP_CTRL_LV_Msk, level << AON_PMU_COMP_REG_0_ICOMP_CTRL_LV_Pos);
380 __STATIC_INLINE
void ll_comp_cascres_half_high(uint32_t level)
382 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_COMP_CASCRES_HALF_CTRL_Msk, level <<AON_PMU_COMP_REG_1_COMP_CASCRES_HALF_CTRL_Pos);
397 __STATIC_INLINE
void ll_comp_positive_hysteresis(uint32_t hyst)
399 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_HYST , hyst);
414 __STATIC_INLINE
void ll_comp_negative_hysteresis(uint32_t hyst)
416 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_HYST , hyst);
431 __STATIC_INLINE
void ll_comp_positive_degeneration(uint32_t res_deg)
433 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_POSITIVE_RES_DEGENERATION , res_deg);
448 __STATIC_INLINE
void ll_comp_negative_degeneration(uint32_t res_deg)
450 MODIFY_REG(AON_PMU->COMP_REG_1, AON_PMU_COMP_REG_1_CHANNEL_NEGATIVE_RES_DEGENERATION , res_deg);
464 __STATIC_INLINE
void ll_comp_set_remove_cycle(uint32_t cycle)
466 MODIFY_REG(AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE, cycle << AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);
478 __STATIC_INLINE uint32_t ll_comp_get_remove_cycle(
void)
480 return (uint32_t)(READ_BITS(AON_CTL->PMU_COMP_GLITCH_REMOVE, AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Msk) >> AON_CTL_PMU_COMP_GLITCH_REMOVE_CYCLE_Pos);
492 __STATIC_INLINE
void ll_comp_enable_rising_wakeup(
void)
494 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 1;
506 __STATIC_INLINE
void ll_comp_disable_rising_wakeup(
void)
508 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE_Pos) = 0;
520 __STATIC_INLINE uint32_t ll_comp_is_enable_rising_wakeup(
void)
522 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE) == AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE);
534 __STATIC_INLINE
void ll_comp_enable_falling_wakeup(
void)
536 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 1;
548 __STATIC_INLINE
void ll_comp_disable_falling_wakeup(
void)
550 BIT_ADDR((uint32_t)&AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL_Pos) = 0;
562 __STATIC_INLINE uint32_t ll_comp_is_enable_falling_wakeup(
void)
564 return (READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL) == AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL);
576 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_comp_is_rising_triger_flag_it(
void)
578 return (READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_CMP_RISE) == AON_CTL_SLP_EVENT_CMP_RISE);
590 SECTION_RAM_CODE __STATIC_INLINE
void ll_comp_clear_rising_triger_flag_it(
void)
592 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_CMP_RISE);
604 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_comp_is_falling_triger_flag_it(
void)
606 return (READ_BITS(AON_CTL->AON_SLP_EVENT, AON_CTL_SLP_EVENT_CMP_FALL) == AON_CTL_SLP_EVENT_CMP_FALL);
618 SECTION_RAM_CODE __STATIC_INLINE
void ll_comp_clear_falling_triger_flag_it(
void)
620 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~AON_CTL_SLP_EVENT_CMP_FALL);
636 error_status_t ll_comp_deinit(
void);
647 error_status_t ll_comp_init(ll_comp_init_t *p_comp_init);
655 void ll_comp_struct_init(ll_comp_init_t *p_comp_init);