52 #ifndef __GR55XX_LL_GPADC_H__
53 #define __GR55XX_LL_GPADC_H__
76 typedef struct _ll_gpadc_init
116 #define LL_GPADC_CTRL0_DEFAULT_VALUE (0x882004ae)//M = 4'he(m+n=32), P = 2'h2(fixed), N = 6'h12(fixed), conv_num = 4'h0, td_t = 8'h20, ts_div = 3'h0, test_mode=1'd1(continu output); clk_inv=1'd0, cali_cap =1'h0, adc_en = 1'h0, conv_sel = 1'h1.
117 #define LL_GPADC_CTRL1_DEFAULT_VALUE (0x0000097b)
118 #define LL_GPADC_CONST_DEFAULT_VALUE (0x10e910e0)
119 #define LL_GPADC_ANA_CTRL_DEFAULT_VALUE (0x00022072)//Vref_pd=0,bypass pga,chp=2,chn=2.
125 #define LL_GPADC_P_INPUT_SRC_VCM (0UL)
126 #define LL_GPADC_P_INPUT_SRC_IO1 (1UL)
127 #define LL_GPADC_P_INPUT_SRC_IO2 (2UL)
128 #define LL_GPADC_P_INPUT_SRC_IO3 (3UL)
129 #define LL_GPADC_P_INPUT_SRC_IO4 (4UL)
130 #define LL_GPADC_P_INPUT_SRC_IO5 (5UL)
131 #define LL_GPADC_P_INPUT_SRC_IO6 (6UL)
132 #define LL_GPADC_P_INPUT_SRC_IO7 (7UL)
138 #define LL_GPADC_N_INPUT_SRC_VCM (0UL)
139 #define LL_GPADC_N_INPUT_SRC_IO0 (1UL)
140 #define LL_GPADC_N_INPUT_SRC_IO1 (2UL)
141 #define LL_GPADC_N_INPUT_SRC_IO2 (3UL)
142 #define LL_GPADC_N_INPUT_SRC_IO3 (4UL)
143 #define LL_GPADC_N_INPUT_SRC_IO4 (5UL)
144 #define LL_GPADC_N_INPUT_SRC_IO5 (6UL)
145 #define LL_GPADC_N_INPUT_SRC_IO6 (7UL)
151 #define LL_GPADC_INPUT_DIFFERENTIAL (0UL)
152 #define LL_GPADC_INPUT_SINGLE (1UL )
158 #define LL_GPADC_VDD_VALUE_1P8 (0UL)
159 #define LL_GPADC_VDD_VALUE_2P3 (5UL)
165 #define LL_GPADC_SPR_1M (0UL)
166 #define LL_GPADC_SPR_500K (1UL)
167 #define LL_GPADC_SPR_250K (2UL)
168 #define LL_GPADC_SPR_125K (3UL)
174 #define LL_GPADC_PGA_MODE_BYPASS (0UL)
175 #define LL_GPADC_PGA_MODE_NORMAL (1UL)
181 #define LL_GPADC_PGA_GAIN_0DB (0UL)
182 #define LL_GPADC_PGA_GAIN_5DB (5UL)
183 #define LL_GPADC_PGA_GAIN_10DB (10UL)
184 #define LL_GPADC_PGA_GAIN_20DB (20UL)
206 #define LL_GPADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
214 #define LL_GPADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
250 __STATIC_INLINE
void ll_gpadc_enable(
void)
252 SET_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk);
264 __STATIC_INLINE
void ll_gpadc_disable(
void)
266 CLEAR_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk);
278 __STATIC_INLINE uint32_t ll_gpadc_is_enabled(
void)
280 return (READ_BITS(GPADC->CTRL0, GPADC_CTRL0_ADC_EN_Msk) == (GPADC_CTRL0_ADC_EN_Msk));
293 __STATIC_INLINE
void ll_gpadc_set_vref_sel(uint32_t vref_sel)
295 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_VREF_SEL_Msk, vref_sel << GPADC_ANA_CTRL_VREF_SEL_POS);
309 __STATIC_INLINE
void ll_gpadc_set_input_para(uint32_t input,uint32_t input_sel)
311 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_ADC_INPUT_Msk, input << GPADC_ANA_CTRL_ADC_INPUT_POS);
312 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_ADC_INPUT_SEL_Msk, input_sel << GPADC_ANA_CTRL_ADC_INPUT_SEL_POS);
325 __STATIC_INLINE
void ll_gpadc_set_cali_sel(uint32_t cali_sel)
327 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CALI_SEL_Msk , cali_sel << GPADC_ANA_CTRL_CALI_SEL_POS);
340 __STATIC_INLINE
void ll_gpadc_set_chp_sel(uint32_t chp_sel)
342 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CH_SEL_P_Msk , chp_sel << GPADC_ANA_CTRL_CH_SEL_P_POS);
355 __STATIC_INLINE
void ll_gpadc_set_chn_sel(uint32_t chn_sel)
357 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_CH_SEL_N_Msk , chn_sel << GPADC_ANA_CTRL_CH_SEL_N_POS);
370 __STATIC_INLINE
void ll_gpadc_set_clk_div(uint32_t div)
372 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_TS_DIV_Msk, div << GPADC_CTRL0_TS_DIV_POS);
385 __STATIC_INLINE
void ll_gpadc_set_data_out_mode(uint32_t mode)
387 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_SAMPLE_MODE_Msk, mode << GPADC_CTRL0_SAMPLE_MODE_POS);
400 __STATIC_INLINE
void ll_gpadc_set_conv_sel(uint32_t conv_sel)
402 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_CONV_SEL_Msk, conv_sel << GPADC_CTRL0_CONV_SEL_POS);
415 __STATIC_INLINE
void ll_gpadc_set_vref_pd(uint32_t pd)
417 MODIFY_REG(GPADC->ANA_CTRL, GPADC_ANA_CTRL_VREF_PD_Msk, pd << GPADC_ANA_CTRL_VREF_PD_POS);
430 __STATIC_INLINE
void ll_gpadc_set_operation_mode(uint32_t mode)
432 MODIFY_REG(GPADC->CTRL0, GPADC_CTRL0_CALI_CAP_Msk, mode << GPADC_CTRL0_CALI_CAP_POS);
444 __STATIC_INLINE
void ll_gpadc_offset_enable(
void)
446 SET_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_EN_Msk);
458 __STATIC_INLINE
void ll_gpadc_offset_disable(
void)
460 CLEAR_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_EN_Msk);
472 __STATIC_INLINE
void ll_gpadc_offset_auto_load_enable(
void)
474 SET_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_AUTO_LOAD_Msk );
486 __STATIC_INLINE
void ll_gpadc_offset_auto_load_disable(
void)
488 CLEAR_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_AUTO_LOAD_Msk );
500 __STATIC_INLINE uint32_t ll_gpadc_get_offset_value(
void)
502 return (uint32_t)(READ_BITS(GPADC->OFFSET, GPADC_OFFSET_OFFSET_VALUE_Msk) >> GPADC_OFFSET_OFFSET_VALUE_POS);
514 __STATIC_INLINE uint32_t ll_gpadc_get_data_p(
void)
516 return (uint32_t)(READ_BITS(GPADC->DATA, GPADC_DATA_DATA_P_Msk) >> GPADC_DATA_DATA_P_POS);
528 __STATIC_INLINE uint32_t ll_gpadc_get_data_n(
void)
530 return (uint32_t)(READ_BITS(GPADC->DATA, GPADC_DATA_DATA_N_Msk) >> GPADC_DATA_DATA_N_POS);
544 __STATIC_INLINE
void ll_gpadc_set_coefx(uint8_t coef_num,uint32_t coef_value)
546 MODIFY_REG(*(&(GPADC->COEF0)+4*coef_num), GPADC_COEF0_COE0_Msk, coef_value << GPADC_COEF0_COE0_POS);
559 __STATIC_INLINE uint32_t ll_gpadc_get_coefx(uint8_t coef_num)
561 return (uint32_t)(READ_BITS(GPADC->COEF0+4*coef_num, GPADC_COEF0_COE0_Msk) >> GPADC_COEF0_COE0_POS);
573 __STATIC_INLINE uint32_t ll_gpadc_read_fifo(
void)
575 return (uint32_t)(READ_REG(GPADC->FIFO_RD));
587 __STATIC_INLINE
void ll_gpadc_set_thresh(uint32_t thresh)
589 MODIFY_REG(GPADC->FIFO_THD, GPADC_FIFO_THD_Msk, (thresh & 0x3F) << GPADC_FIFO_THD_POS);
600 __STATIC_INLINE uint32_t ll_gpadc_is_fifo_notempty(
void)
602 return (uint32_t)(READ_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_VALID) == GPADC_FIFO_STAT_VALID);
613 __STATIC_INLINE uint32_t ll_gpadc_get_fifo_count(
void)
615 return (uint32_t)(READ_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_COUNT) >> GPADC_FIFO_STAT_COUNT_POS);
626 __STATIC_INLINE
void ll_gpadc_flush_fifo(
void)
628 SET_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_FLUSH_Msk);
629 CLEAR_BITS(GPADC->FIFO_STAT, GPADC_FIFO_STAT_FLUSH_Msk);
640 __STATIC_INLINE
void ll_gpadc_set_ldo23(uint32_t value)
642 MODIFY_REG(GPADC->ANA_MBG, GPADC_ANA_MBG_LDO23_SEL_Msk, value << GPADC_ANA_MBG_LDO23_SEL_POS);
653 __STATIC_INLINE
void ll_gpadc_pga_enable(
void)
655 CLEAR_BITS(GPADC->ANA_PGA, GPADC_ANA_PGA_PD_Msk);
666 __STATIC_INLINE
void ll_gpadc_pga_disable(
void)
668 SET_BITS(GPADC->ANA_PGA, GPADC_ANA_PGA_PD_Msk);
679 __STATIC_INLINE
void ll_gpadc_set_gain(uint32_t value)
681 MODIFY_REG(GPADC->ANA_PGA, GPADC_ANA_PGA_GAIN_CTRL_Msk, value << GPADC_ANA_PGA_GAIN_CTRL_POS);
691 error_status_t ll_gpadc_deinit(
void);
702 error_status_t ll_gpadc_init(ll_gpadc_init_t *p_gpadc_init);
710 void ll_gpadc_struct_init(ll_gpadc_init_t *p_gpadc_init);