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#define | LL_CLK_CPLL_S96M_CLK AON_CTL_MCU_CLK_CTRL_SEL_96M |
#define | LL_CLK_CPLL_S64M_CLK AON_CTL_MCU_CLK_CTRL_SEL_64M |
#define | LL_CLK_XO_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_XO_16M |
#define | LL_CLK_CPLL_F48M_CLK AON_CTL_MCU_CLK_CTRL_SEL_48M |
#define | LL_CLK_CPLL_T24M_CLK AON_CTL_MCU_CLK_CTRL_SEL_24M |
#define | LL_CLK_CPLL_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_16M |
#define | LL_CLK_CPLL_T32M_CLK AON_CTL_MCU_CLK_CTRL_SEL_32M |
#define | LL_CLK_AON_CLK_WAKUP_CLK_EN (1 << AON_CTL_AON_CLK_WAKUP_CLK_EN_Pos) |
#define | LL_CLK_AON_CLK_WAKUP_CLK_DIS 0 |
#define LL_CLK_AON_CLK_WAKUP_CLK_DIS 0 |
wakeup clock disable
Definition at line 95 of file gr55xx_ll_clk.h.
#define LL_CLK_AON_CLK_WAKUP_CLK_EN (1 << AON_CTL_AON_CLK_WAKUP_CLK_EN_Pos) |
wakeup clock enable
Definition at line 94 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_F48M_CLK AON_CTL_MCU_CLK_CTRL_SEL_48M |
Select PLL/HF_OSC 48MHz clk as system clock
Definition at line 89 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_16M |
Select PLL/HF_OSC 16MHz clk as system clock
Definition at line 91 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_S64M_CLK AON_CTL_MCU_CLK_CTRL_SEL_64M |
Select PLL/HF_OSC 64MHz clk as system clock
Definition at line 87 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_S96M_CLK AON_CTL_MCU_CLK_CTRL_SEL_96M |
Select PLL/HF_OSC 96MHz clk as system clock
Definition at line 86 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_T24M_CLK AON_CTL_MCU_CLK_CTRL_SEL_24M |
Select PLL/HF_OSC 24MHz clk as system clock
Definition at line 90 of file gr55xx_ll_clk.h.
#define LL_CLK_CPLL_T32M_CLK AON_CTL_MCU_CLK_CTRL_SEL_32M |
Select PLL/HF_OSC 32MHz clk as system clock
Definition at line 92 of file gr55xx_ll_clk.h.
#define LL_CLK_XO_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_XO_16M |
Select XO 16MHz clk as system clock
Definition at line 88 of file gr55xx_ll_clk.h.