52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
158 #define LL_XQSPI_HP_MODE_DIS 0
159 #define LL_XQSPI_HP_MODE_EN 1
165 #define LL_XQSPI_1ST_PREFETCH_DIS XQSPI_RG_1ST_PREFETCH_DIS_Msk
166 #define LL_XQSPI_1ST_PREFETCH_EN 0
172 #define LL_XQSPI_MODE_XIP 0
173 #define LL_XQSPI_MODE_QSPI 1
179 #define LL_XQSPI_XIP_CMD_READ 0x03
180 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B
181 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B
182 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB
183 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B
184 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB
190 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos)
191 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos)
192 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos)
193 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos)
199 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL
200 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4
206 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL
207 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32
213 #define LL_XQSPI_CACHE_DIS 0
214 #define LL_XQSPI_CACHE_EN 1
220 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL
221 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO
227 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL
228 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS
235 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK
236 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL
237 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY
238 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK
239 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL
240 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY
241 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP
248 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk
249 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk
250 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk
251 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk
252 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk
254 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk
255 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk
256 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk
257 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk
258 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk
264 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL
265 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL
266 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL
267 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL
268 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL
274 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL
275 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos)
276 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos)
282 #define LL_XQSPI_QSPI_LSB 0x00000000UL
283 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST
289 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL
290 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
291 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
292 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
293 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
294 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
295 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
296 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
302 #define LL_XQSPI_SCPHA_1EDGE 0
303 #define LL_XQSPI_SCPHA_2EDGE 1
309 #define LL_XQSPI_SCPOL_LOW 0
310 #define LL_XQSPI_SCPOL_HIGH 1
316 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL
317 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos)
318 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos)
319 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos)
320 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos)
326 #define LL_XQSPI_CACHE_DIRECT_MAP_DIS 0
327 #define LL_XQSPI_CACHE_DIRECT_MAP_EN 1
333 #define LL_XQSPI_CACHE_FLUSH_DIS 1
334 #define LL_XQSPI_CACHE_FLUSH_EN 0
341 #define LL_XQSPI_ENABLE_PRESENT 0
342 #define LL_XQSPI_DISABLE_PRESENT 1
348 #define LL_XQSPI_FLASH_WRITE_128BIT 0
349 #define LL_XQSPI_FLASH_WRITE_32BIT 1
359 #define LL_XQSPI_DEFAULT_CONFIG \
361 .mode = LL_XQSPI_MODE_QSPI, \
362 .cache_mode = LL_XQSPI_CACHE_EN, \
363 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
364 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
365 .data_order = LL_XQSPI_QSPI_MSB, \
366 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
367 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
368 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
369 .cache_direct_map_en= LL_XQSPI_CACHE_DIRECT_MAP_DIS, \
370 .cache_flush = LL_XQSPI_CACHE_FLUSH_EN, \
392 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
400 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
430 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
431 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
447 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
448 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
463 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
479 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
480 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
496 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
497 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
512 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN));
528 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
544 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
559 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
574 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_CLK_FORCE_EN, XQSPI_CACHE_CTRL0_CLK_FORCE_EN);
593 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
611 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
630 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
648 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
665 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
680 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
696 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
712 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
727 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
743 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
759 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
775 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
804 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
825 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
841 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
846 SET_BITS(XQSPIx->XIP.SOFT_RST, XQSPI_XIP_SOFT_RST);
862 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
877 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
898 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
917 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
936 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
953 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
972 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
989 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
1008 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
1025 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
1044 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
1061 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
1079 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
1094 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
1115 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1134 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES) >> XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1150 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1165 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1180 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1195 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1211 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1227 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1243 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1259 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1275 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1291 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1307 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1329 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1345 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1361 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1376 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1391 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1406 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1427 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1447 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1468 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1488 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1503 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1518 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1533 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1548 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1563 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1578 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1597 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1614 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1633 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1650 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1668 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1685 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1700 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1715 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1730 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1745 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1760 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1775 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1800 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1823 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1838 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1853 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1868 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1883 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1898 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1913 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1933 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1951 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1973 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1996 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
2012 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2028 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2044 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
2059 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
2074 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
2089 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
2111 SET_BITS(XQSPIx->QSPI.INTEN, mask);
2133 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2154 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2174 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2199 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2221 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2237 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2252 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2268 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2283 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2298 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2316 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2334 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2352 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2369 return READ_REG(XQSPIx->QSPI.BYPASS);
2385 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2401 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2417 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2433 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2449 CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2465 SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2480 SET_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN);
2495 CLEAR_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN);
2509 return (READ_BITS(AON_CTL->FLASH_PSRAM_PAD_PWR, AON_CTL_FLASH_CACHE_PAD_EN) == (AON_CTL_FLASH_CACHE_PAD_EN));
2529 MODIFY_REG(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL, speed);
2548 return (uint32_t)(READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL));
2563 SET_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2578 CLEAR_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2592 return (READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET) == (AON_CTL_FLASH_CACHE_XF_TAG_RET));