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52 #ifndef __GR55xx_HAL_CORTEX_H__
53 #define __GR55xx_HAL_CORTEX_H__
68 #if (__MPU_PRESENT == 1U)
77 typedef struct _mpu_region_init_t
85 uint32_t base_address;
90 uint8_t subregion_disable;
93 uint8_t type_tex_field;
96 uint8_t access_permission;
102 uint8_t is_shareable;
105 uint8_t is_cacheable;
108 uint8_t is_bufferable;
134 #define NVIC_PRIORITYGROUP_0 (0x00000007U)
136 #define NVIC_PRIORITYGROUP_1 (0x00000006U)
138 #define NVIC_PRIORITYGROUP_2 (0x00000005U)
140 #define NVIC_PRIORITYGROUP_3 (0x00000004U)
142 #define NVIC_PRIORITYGROUP_4 (0x00000003U)
144 #define NVIC_PRIORITYGROUP_5 (0x00000002U)
146 #define NVIC_PRIORITYGROUP_6 (0x00000001U)
148 #define NVIC_PRIORITYGROUP_7 (0x00000000U)
152 #if (__MPU_PRESENT == 1U)
156 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
157 #define MPU_HARDFAULT_NMI (0x00000002U)
158 #define MPU_PRIVILEGED_DEFAULT (0x00000004U)
159 #define MPU_HFNMI_PRIVDEF (0x00000006U)
165 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
166 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
172 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
173 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
179 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
180 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
186 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
187 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
193 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
194 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
200 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
201 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
202 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
208 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
209 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
210 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
211 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
212 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
213 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
214 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
215 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
216 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
217 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
218 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
219 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
220 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
221 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
222 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
223 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
224 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
225 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
226 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
227 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
228 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
229 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
230 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
231 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
232 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
233 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
234 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
235 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
241 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
242 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
243 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
244 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
245 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
246 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
252 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
253 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
254 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
255 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
256 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
257 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
258 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
259 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
280 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
281 ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
282 ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
283 ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
284 ((__GROUP__) == NVIC_PRIORITYGROUP_4) || \
285 ((__GROUP__) == NVIC_PRIORITYGROUP_5) || \
286 ((__GROUP__) == NVIC_PRIORITYGROUP_6) || \
287 ((__GROUP__) == NVIC_PRIORITYGROUP_7))
294 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x80U)
301 #define IS_NVIC_SUB_PRIORITY(__PRIORITY__) ((__PRIORITY__) <= 0xFFU)
308 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) >= 0x00)
315 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
316 ((__SOURCE__) == SYSTICK_CLKSOURCE_REFCLK))
318 #if (__MPU_PRESENT == 1U)
325 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
326 ((__STATE__) == MPU_REGION_DISABLE))
333 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
334 ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
341 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \
342 ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
349 #define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \
350 ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE))
357 #define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \
358 ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE))
365 #define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \
366 ((__TYPE__) == MPU_TEX_LEVEL1) || \
367 ((__TYPE__) == MPU_TEX_LEVEL2))
374 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \
375 ((__TYPE__) == MPU_REGION_PRIV_RW) || \
376 ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \
377 ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \
378 ((__TYPE__) == MPU_REGION_PRIV_RO) || \
379 ((__TYPE__) == MPU_REGION_PRIV_RO_URO))
386 #define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
387 ((__NUMBER__) == MPU_REGION_NUMBER1) || \
388 ((__NUMBER__) == MPU_REGION_NUMBER2) || \
389 ((__NUMBER__) == MPU_REGION_NUMBER3) || \
390 ((__NUMBER__) == MPU_REGION_NUMBER4) || \
391 ((__NUMBER__) == MPU_REGION_NUMBER5) || \
392 ((__NUMBER__) == MPU_REGION_NUMBER6) || \
393 ((__NUMBER__) == MPU_REGION_NUMBER7))
400 #define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \
401 ((__SIZE__) == MPU_REGION_SIZE_64B) || \
402 ((__SIZE__) == MPU_REGION_SIZE_128B) || \
403 ((__SIZE__) == MPU_REGION_SIZE_256B) || \
404 ((__SIZE__) == MPU_REGION_SIZE_512B) || \
405 ((__SIZE__) == MPU_REGION_SIZE_1KB) || \
406 ((__SIZE__) == MPU_REGION_SIZE_2KB) || \
407 ((__SIZE__) == MPU_REGION_SIZE_4KB) || \
408 ((__SIZE__) == MPU_REGION_SIZE_8KB) || \
409 ((__SIZE__) == MPU_REGION_SIZE_16KB) || \
410 ((__SIZE__) == MPU_REGION_SIZE_32KB) || \
411 ((__SIZE__) == MPU_REGION_SIZE_64KB) || \
412 ((__SIZE__) == MPU_REGION_SIZE_128KB) || \
413 ((__SIZE__) == MPU_REGION_SIZE_256KB) || \
414 ((__SIZE__) == MPU_REGION_SIZE_512KB) || \
415 ((__SIZE__) == MPU_REGION_SIZE_1MB) || \
416 ((__SIZE__) == MPU_REGION_SIZE_2MB) || \
417 ((__SIZE__) == MPU_REGION_SIZE_4MB) || \
418 ((__SIZE__) == MPU_REGION_SIZE_8MB) || \
419 ((__SIZE__) == MPU_REGION_SIZE_16MB) || \
420 ((__SIZE__) == MPU_REGION_SIZE_32MB) || \
421 ((__SIZE__) == MPU_REGION_SIZE_64MB) || \
422 ((__SIZE__) == MPU_REGION_SIZE_128MB) || \
423 ((__SIZE__) == MPU_REGION_SIZE_256MB) || \
424 ((__SIZE__) == MPU_REGION_SIZE_512MB) || \
425 ((__SIZE__) == MPU_REGION_SIZE_1GB) || \
426 ((__SIZE__) == MPU_REGION_SIZE_2GB) || \
427 ((__SIZE__) == MPU_REGION_SIZE_4GB))
435 #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)
574 #if (__MPU_PRESENT == 1U)
583 void hal_mpu_config_region(mpu_region_init_t *p_mpu_init);
624 void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority);
687 #if (__MPU_PRESENT == 1U)
694 void hal_mpu_disable(
void);
709 void hal_mpu_enable(uint32_t mpu_control);
void hal_nvic_system_reset(void)
Initiate a system reset request to reset the MCU.
void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, uint32_t *p_sub_priority)
Get the priority of an interrupt.
void hal_nvic_enable_irq(IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void hal_nvic_set_pending_irq(IRQn_Type IRQn)
Set Pending bit of an external interrupt.
void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority)
Set the priority of an interrupt.
uint32_t hal_nvic_get_priority_grouping(void)
Get the priority grouping field from the NVIC Interrupt Controller.
uint32_t hal_nvic_get_active(IRQn_Type IRQn)
Get active interrupt (reads the active register in NVIC and returns the active bit).
void hal_nvic_clear_pending_irq(IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t hal_systick_config(uint32_t ticks_number)
Initialize the System Timer and its interrupt, and start the System Tick Timer. Counter is in free ru...
uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn)
Get Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the spe...
This file contains HAL common definitions, enumeration, macros and structures definitions.
void hal_nvic_set_priority_grouping(uint32_t priority_group)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequ...
void hal_nvic_disable_irq(IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.