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52 #ifndef __GR55xx_HAL_QSPI_H__
53 #define __GR55xx_HAL_QSPI_H__
395 #define QSPI_DMA_CRTL_LOW_REGISTER_CFG(src_direction, src_tr_width, dst_tr_width, src_msize, dst_msize, en_gather) \
397 DMA_CTLL_INI_EN | DMA_MEMORY_TO_PERIPH | DMA_LLP_SRC_ENABLE | DMA_LLP_DST_DISABLE | \
398 en_gather | DMA_DST_SCATTER_DISABLE | DMA_DST_NO_CHANGE | \
399 src_direction | src_tr_width | dst_tr_width | src_msize | dst_msize \
407 #define QSPI_MAX_FIFO_DEPTH LL_QSPI_MAX_FIFO_DEPTH
413 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
414 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
415 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
416 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
417 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
424 #define QSPI_CLOCK_MODE_0 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_1EDGE)
425 #define QSPI_CLOCK_MODE_1 (LL_QSPI_SCPOL_LOW | LL_QSPI_SCPHA_2EDGE)
426 #define QSPI_CLOCK_MODE_2 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_1EDGE)
427 #define QSPI_CLOCK_MODE_3 (LL_QSPI_SCPOL_HIGH | LL_QSPI_SCPHA_2EDGE)
435 #define QSPI_DATA_MODE_SPI LL_QSPI_FRF_SPI
436 #define QSPI_DATA_MODE_DUALSPI LL_QSPI_FRF_DUALSPI
437 #define QSPI_DATA_MODE_QUADSPI LL_QSPI_FRF_QUADSPI
445 #define QSPI_INSTSIZE_00_BITS LL_QSPI_INSTSIZE_0BIT
446 #define QSPI_INSTSIZE_04_BITS LL_QSPI_INSTSIZE_4BIT
447 #define QSPI_INSTSIZE_08_BITS LL_QSPI_INSTSIZE_8BIT
448 #define QSPI_INSTSIZE_16_BITS LL_QSPI_INSTSIZE_16BIT
456 #define QSPI_ADDRSIZE_00_BITS LL_QSPI_ADDRSIZE_0BIT
457 #define QSPI_ADDRSIZE_04_BITS LL_QSPI_ADDRSIZE_4BIT
458 #define QSPI_ADDRSIZE_08_BITS LL_QSPI_ADDRSIZE_8BIT
459 #define QSPI_ADDRSIZE_12_BITS LL_QSPI_ADDRSIZE_12BIT
460 #define QSPI_ADDRSIZE_16_BITS LL_QSPI_ADDRSIZE_16BIT
461 #define QSPI_ADDRSIZE_20_BITS LL_QSPI_ADDRSIZE_20BIT
462 #define QSPI_ADDRSIZE_24_BITS LL_QSPI_ADDRSIZE_24BIT
463 #define QSPI_ADDRSIZE_28_BITS LL_QSPI_ADDRSIZE_28BIT
464 #define QSPI_ADDRSIZE_32_BITS LL_QSPI_ADDRSIZE_32BIT
472 #define QSPI_DATASIZE_04_BITS LL_QSPI_DATASIZE_4BIT
473 #define QSPI_DATASIZE_05_BITS LL_QSPI_DATASIZE_5BIT
474 #define QSPI_DATASIZE_06_BITS LL_QSPI_DATASIZE_6BIT
475 #define QSPI_DATASIZE_07_BITS LL_QSPI_DATASIZE_7BIT
476 #define QSPI_DATASIZE_08_BITS LL_QSPI_DATASIZE_8BIT
477 #define QSPI_DATASIZE_09_BITS LL_QSPI_DATASIZE_9BIT
478 #define QSPI_DATASIZE_10_BITS LL_QSPI_DATASIZE_10BIT
479 #define QSPI_DATASIZE_11_BITS LL_QSPI_DATASIZE_11BIT
480 #define QSPI_DATASIZE_12_BITS LL_QSPI_DATASIZE_12BIT
481 #define QSPI_DATASIZE_13_BITS LL_QSPI_DATASIZE_13BIT
482 #define QSPI_DATASIZE_14_BITS LL_QSPI_DATASIZE_14BIT
483 #define QSPI_DATASIZE_15_BITS LL_QSPI_DATASIZE_15BIT
484 #define QSPI_DATASIZE_16_BITS LL_QSPI_DATASIZE_16BIT
485 #define QSPI_DATASIZE_17_BITS LL_QSPI_DATASIZE_17BIT
486 #define QSPI_DATASIZE_18_BITS LL_QSPI_DATASIZE_18BIT
487 #define QSPI_DATASIZE_19_BITS LL_QSPI_DATASIZE_19BIT
488 #define QSPI_DATASIZE_20_BITS LL_QSPI_DATASIZE_20BIT
489 #define QSPI_DATASIZE_21_BITS LL_QSPI_DATASIZE_21BIT
490 #define QSPI_DATASIZE_22_BITS LL_QSPI_DATASIZE_22BIT
491 #define QSPI_DATASIZE_23_BITS LL_QSPI_DATASIZE_23BIT
492 #define QSPI_DATASIZE_24_BITS LL_QSPI_DATASIZE_24BIT
493 #define QSPI_DATASIZE_25_BITS LL_QSPI_DATASIZE_25BIT
494 #define QSPI_DATASIZE_26_BITS LL_QSPI_DATASIZE_26BIT
495 #define QSPI_DATASIZE_27_BITS LL_QSPI_DATASIZE_27BIT
496 #define QSPI_DATASIZE_28_BITS LL_QSPI_DATASIZE_28BIT
497 #define QSPI_DATASIZE_29_BITS LL_QSPI_DATASIZE_29BIT
498 #define QSPI_DATASIZE_30_BITS LL_QSPI_DATASIZE_30BIT
499 #define QSPI_DATASIZE_31_BITS LL_QSPI_DATASIZE_31BIT
500 #define QSPI_DATASIZE_32_BITS LL_QSPI_DATASIZE_32BIT
510 #define QSPI_INST_ADDR_ALL_IN_SPI LL_QSPI_INST_ADDR_ALL_IN_SPI
511 #define QSPI_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_INST_IN_SPI_ADDR_IN_SPIFRF
512 #define QSPI_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_INST_ADDR_ALL_IN_SPIFRF
520 #define QSPI_FLAG_DCOL LL_QSPI_SR_DCOL
521 #define QSPI_FLAG_TXE LL_QSPI_SR_TXE
522 #define QSPI_FLAG_RFF LL_QSPI_SR_RFF
523 #define QSPI_FLAG_RFNE LL_QSPI_SR_RFNE
524 #define QSPI_FLAG_TFE LL_QSPI_SR_TFE
525 #define QSPI_FLAG_TFNF LL_QSPI_SR_TFNF
526 #define QSPI_FLAG_BUSY LL_QSPI_SR_BUSY
534 #define QSPI_IT_TXU LL_QSPI_IS_TXU
535 #define QSPI_IT_XRXO LL_QSPI_IS_XRXO
536 #define QSPI_IT_MST LL_QSPI_IS_MST
537 #define QSPI_IT_RXF LL_QSPI_IS_RXF
538 #define QSPI_IT_RXO LL_QSPI_IS_RXO
539 #define QSPI_IT_RXU LL_QSPI_IS_RXU
540 #define QSPI_IT_TXO LL_QSPI_IS_TXO
541 #define QSPI_IT_TXE LL_QSPI_IS_TXE
542 #define QSPI_IT_ALL LL_QSPI_IS_ALL
549 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)
555 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_0
556 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_1
557 #define QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 LL_QSPI_CONCURRENT_XIP_ENDIAN_MODE_2
563 #define QSPI_CONCURRENT_XIP_SLAVE0 LL_QSPI_CONCURRENT_XIP_SLAVE0
569 #define QSPI_CONCURRENT_XIP_DFS_BYTE LL_QSPI_CONCURRENT_XIP_DFS_BYTE
570 #define QSPI_CONCURRENT_XIP_DFS_HALFWORD LL_QSPI_CONCURRENT_XIP_DFS_HALFWORD
571 #define QSPI_CONCURRENT_XIP_DFS_WORD LL_QSPI_CONCURRENT_XIP_DFS_WORD
577 #define QSPI_CONCURRENT_XIP_MBL_2 LL_QSPI_CONCURRENT_XIP_MBL_2
578 #define QSPI_CONCURRENT_XIP_MBL_4 LL_QSPI_CONCURRENT_XIP_MBL_4
579 #define QSPI_CONCURRENT_XIP_MBL_8 LL_QSPI_CONCURRENT_XIP_MBL_8
580 #define QSPI_CONCURRENT_XIP_MBL_16 LL_QSPI_CONCURRENT_XIP_MBL_16
586 #define QSPI_CONCURRENT_XIP_INSTSIZE_0BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_0BIT
587 #define QSPI_CONCURRENT_XIP_INSTSIZE_4BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_4BIT
588 #define QSPI_CONCURRENT_XIP_INSTSIZE_8BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_8BIT
589 #define QSPI_CONCURRENT_XIP_INSTSIZE_16BIT LL_QSPI_CONCURRENT_XIP_INSTSIZE_16BIT
595 #define QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT
596 #define QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT
597 #define QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT
598 #define QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT
599 #define QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT
600 #define QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT
601 #define QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT
602 #define QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT
603 #define QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT
604 #define QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT
605 #define QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT
606 #define QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT
607 #define QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT
608 #define QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT
609 #define QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT
610 #define QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT LL_QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT
616 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI
617 #define QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF
618 #define QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF LL_QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF
624 #define QSPI_CONCURRENT_XIP_FRF_RSVD LL_QSPI_CONCURRENT_XIP_FRF_RSVD
625 #define QSPI_CONCURRENT_XIP_FRF_DUAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_DUAL_SPI
626 #define QSPI_CONCURRENT_XIP_FRF_QUAD_SPI LL_QSPI_CONCURRENT_XIP_FRF_QUAD_SPI
627 #define QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI LL_QSPI_CONCURRENT_XIP_FRF_OCTAL_SPI
633 #define QSPI_CLK_STRETCH_ENABLE LL_QSPI_CLK_STRETCH_ENABLE
634 #define QSPI_CLK_STRETCH_DISABLE LL_QSPI_CLK_STRETCH_DISABLE
640 #define QSPI_CONCURRENT_XIP_PREFETCH_ENABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_ENABLE
641 #define QSPI_CONCURRENT_XIP_PREFETCH_DISABLE LL_QSPI_CONCURRENT_XIP_PREFETCH_DISABLE
647 #define QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE
648 #define QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE LL_QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE
654 #define QSPI_CONCURRENT_XIP_INST_ENABLE LL_QSPI_CONCURRENT_XIP_INST_ENABLE
655 #define QSPI_CONCURRENT_XIP_INST_DISABLE LL_QSPI_CONCURRENT_XIP_INST_DISABLE
661 #define QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE
662 #define QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE LL_QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE
668 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE
669 #define QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE LL_QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE
675 #define QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS
676 #define QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS LL_QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS
683 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_0 0u
685 #define QSPI_PSRAM_LINKED_BLOCK_DATA_MODE_1 1u
694 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_RECTANGLE 0u
696 #define QSPI_PSRAM_LINKED_BLOCK_DATA_SHAPE_NON_RECTANGLE 1u
710 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->state = HAL_QSPI_STATE_RESET)
717 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
724 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->QSPI_EN, QSPI_SSI_EN)
731 #define __HAL_QSPI_ENABLE_DMATX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
737 #define __HAL_QSPI_ENABLE_DMARX(__HANDLE__) SET_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
744 #define __HAL_QSPI_DISABLE_DMATX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_TDMAE)
751 #define __HAL_QSPI_DISABLE_DMARX(__HANDLE__) CLEAR_BITS((__HANDLE__)->p_instance->DMAC, QSPI_DMAC_RDMAE)
766 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
781 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BITS((__HANDLE__)->p_instance->INTMASK, (__INTERRUPT__))
796 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BITS((__HANDLE__)->p_instance->INTSTAT, (__INTERRUPT__)) == (__INTERRUPT__))
812 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__)) != 0) ? SET : RESET)
828 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) READ_BITS((__HANDLE__)->p_instance->STAT, (__FLAG__))
841 #define IS_QSPI_CLOCK_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
848 #define IS_QSPI_FIFO_THRESHOLD(__THR__) (((__THR__) >= 0) && ((__THR__) <= (QSPI_MAX_FIFO_DEPTH - 1)))
854 #define IS_QSPI_CLOCK_MODE(__CLKMODE__) (((__CLKMODE__) == QSPI_CLOCK_MODE_0) || \
855 ((__CLKMODE__) == QSPI_CLOCK_MODE_1) || \
856 ((__CLKMODE__) == QSPI_CLOCK_MODE_2) || \
857 ((__CLKMODE__) == QSPI_CLOCK_MODE_3))
863 #define IS_QSPI_RX_SAMPLE_DLY(__DLY__) (((__DLY__) >= 0) && ((__DLY__) <= 7))
870 #define IS_QSPI_INSTRUCTION_SIZE(__INST_SIZE__) (((__INST_SIZE__) == QSPI_INSTSIZE_00_BITS) || \
871 ((__INST_SIZE__) == QSPI_INSTSIZE_04_BITS) || \
872 ((__INST_SIZE__) == QSPI_INSTSIZE_08_BITS) || \
873 ((__INST_SIZE__) == QSPI_INSTSIZE_16_BITS))
879 #define IS_QSPI_ADDRESS_SIZE(__ADDR_SIZE__) (((__ADDR_SIZE__) == QSPI_ADDRSIZE_00_BITS) || \
880 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_04_BITS) || \
881 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_08_BITS) || \
882 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_12_BITS) || \
883 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_16_BITS) || \
884 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_20_BITS) || \
885 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_24_BITS) || \
886 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_28_BITS) || \
887 ((__ADDR_SIZE__) == QSPI_ADDRSIZE_32_BITS))
893 #define IS_QSPI_DUMMY_CYCLES(__DCY__) ((__DCY__) <= 31)
899 #define IS_QSPI_INSTADDR_MODE(__MODE__) (((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPI) || \
900 ((__MODE__) == QSPI_INST_IN_SPI_ADDR_IN_SPIFRF) || \
901 ((__MODE__) == QSPI_INST_ADDR_ALL_IN_SPIFRF))
907 #define IS_QSPI_DATA_MODE(__MODE__) (((__MODE__) == QSPI_DATA_MODE_SPI) || \
908 ((__MODE__) == QSPI_DATA_MODE_DUALSPI) || \
909 ((__MODE__) == QSPI_DATA_MODE_QUADSPI))
916 #define IS_QSPI_SUPPORTED_DATA_SIZE(__SIZE__) (((__SIZE__) == QSPI_DATASIZE_08_BITS) || \
917 ((__SIZE__) == QSPI_DATASIZE_16_BITS) || \
918 ((__SIZE__) == QSPI_DATASIZE_32_BITS))
932 #define IS_QSPI_CONC_XIP_SIOO_MODE(_SIOO_) ( (QSPI_CONCURRENT_XIP_INST_SENT_EVERY_ACCESS == (_SIOO_)) || \
933 (QSPI_CONCURRENT_XIP_INST_SENT_ONLY_FIRST_ACCESS == (_SIOO_)) )
939 #define IS_QSPI_CONC_XIP_DFS(_DFS_) ( (QSPI_CONCURRENT_XIP_DFS_BYTE == (_DFS_)) || \
940 (QSPI_CONCURRENT_XIP_DFS_HALFWORD == (_DFS_)) || \
941 (QSPI_CONCURRENT_XIP_DFS_WORD == (_DFS_)) )
947 #define IS_QSPI_CONC_XIP_DFS_HC_EN(_HC_EN_) ( (QSPI_CONCURRENT_XIP_DFS_HARDCODE_ENABLE == (_HC_EN_)) || \
948 (QSPI_CONCURRENT_XIP_DFS_HARDCODE_DISABLE == (_HC_EN_)) )
954 #define IS_QSPI_CONC_XIP_INST_EN(_INST_EN_) ( (QSPI_CONCURRENT_XIP_INST_ENABLE == (_INST_EN_)) || \
955 (QSPI_CONCURRENT_XIP_INST_DISABLE == (_INST_EN_)) )
961 #define IS_QSPI_CONC_XIP_INST_SIZE(_INST_SIZE_) ( (QSPI_CONCURRENT_XIP_INSTSIZE_0BIT == (_INST_SIZE_) ) || \
962 (QSPI_CONCURRENT_XIP_INSTSIZE_4BIT == (_INST_SIZE_) ) || \
963 (QSPI_CONCURRENT_XIP_INSTSIZE_8BIT == (_INST_SIZE_) ) || \
964 (QSPI_CONCURRENT_XIP_INSTSIZE_16BIT == (_INST_SIZE_) ) )
970 #define IS_QSPI_CONC_XIP_INST(_INST_) ((_INST_) <= 0xFFFF )
976 #define IS_QSPI_CONC_XIP_ADDR_SIZE(_ADDR_SIZE_) ( (QSPI_CONCURRENT_XIP_ADDRSIZE_0BIT == (_ADDR_SIZE_) ) || \
977 (QSPI_CONCURRENT_XIP_ADDRSIZE_4BIT == (_ADDR_SIZE_) ) || \
978 (QSPI_CONCURRENT_XIP_ADDRSIZE_8BIT == (_ADDR_SIZE_) ) || \
979 (QSPI_CONCURRENT_XIP_ADDRSIZE_12BIT == (_ADDR_SIZE_) ) || \
980 (QSPI_CONCURRENT_XIP_ADDRSIZE_16BIT == (_ADDR_SIZE_) ) || \
981 (QSPI_CONCURRENT_XIP_ADDRSIZE_20BIT == (_ADDR_SIZE_) ) || \
982 (QSPI_CONCURRENT_XIP_ADDRSIZE_24BIT == (_ADDR_SIZE_) ) || \
983 (QSPI_CONCURRENT_XIP_ADDRSIZE_28BIT == (_ADDR_SIZE_) ) || \
984 (QSPI_CONCURRENT_XIP_ADDRSIZE_32BIT == (_ADDR_SIZE_) ) || \
985 (QSPI_CONCURRENT_XIP_ADDRSIZE_36BIT == (_ADDR_SIZE_) ) || \
986 (QSPI_CONCURRENT_XIP_ADDRSIZE_40BIT == (_ADDR_SIZE_) ) || \
987 (QSPI_CONCURRENT_XIP_ADDRSIZE_44BIT == (_ADDR_SIZE_) ) || \
988 (QSPI_CONCURRENT_XIP_ADDRSIZE_48BIT == (_ADDR_SIZE_) ) || \
989 (QSPI_CONCURRENT_XIP_ADDRSIZE_52BIT == (_ADDR_SIZE_) ) || \
990 (QSPI_CONCURRENT_XIP_ADDRSIZE_56BIT == (_ADDR_SIZE_) ) || \
991 (QSPI_CONCURRENT_XIP_ADDRSIZE_60BIT == (_ADDR_SIZE_) ) )
997 #define IS_QSPI_CONC_INST_ADDR_XFER_FORMAT(_FORMAT_) ( (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPI == (_FORMAT_)) || \
998 (QSPI_CONCURRENT_XIP_INST_IN_SPI_ADDR_IN_SPIFRF == (_FORMAT_)) || \
999 (QSPI_CONCURRENT_XIP_INST_ADDR_ALL_IN_SPIFRF == (_FORMAT_)) )
1005 #define IS_QSPI_CONC_XIP_MODE_BITS_EN(_MD_EN_) ( (QSPI_CONCURRENT_XIP_MODE_BITS_ENABLE == (_MD_EN_) ) || \
1006 (QSPI_CONCURRENT_XIP_MODE_BITS_DISABLE == (_MD_EN_) ))
1012 #define IS_QSPI_CONC_XIP_MODE_BITS_SIZE(_MD_SIZE_) ( (QSPI_CONCURRENT_XIP_MBL_2 == (_MD_SIZE_)) || \
1013 (QSPI_CONCURRENT_XIP_MBL_4 == (_MD_SIZE_)) || \
1014 (QSPI_CONCURRENT_XIP_MBL_8 == (_MD_SIZE_)) || \
1015 (QSPI_CONCURRENT_XIP_MBL_16 == (_MD_SIZE_)) )
1021 #define IS_QSPI_CONC_XIP_MODE_BITS(_MD_BITS_) ( (_MD_BITS_) <= 0xFFFF)
1027 #define IS_QSPI_CONC_XIP_DUMMY_CYCLES(__DCY__) ( (__DCY__) <= 31)
1033 #define IS_QSPI_CONC_XIP_DATA_FRF(_XIP_FRF_) ( (QSPI_CONCURRENT_XIP_FRF_DUAL_SPI == (_XIP_FRF_)) || \
1034 (QSPI_CONCURRENT_XIP_FRF_QUAD_SPI == (_XIP_FRF_)) )
1040 #define IS_QSPI_CONC_XIP_PREFETCH_EN(_PREFETCH_EN_) ( (QSPI_CONCURRENT_XIP_PREFETCH_ENABLE == (_PREFETCH_EN_)) || \
1041 (QSPI_CONCURRENT_XIP_PREFETCH_DISABLE == (_PREFETCH_EN_)) )
1047 #define IS_QSPI_CONC_XIP_CONT_XFER_EN(_CONT_XFER_EN_) ( (QSPI_CONCURRENT_XIP_CONT_XFER_ENABLE == (_CONT_XFER_EN_)) || \
1048 (QSPI_CONCURRENT_XIP_CONT_XFER_DISABLE == (_CONT_XFER_EN_)) )
1054 #define IS_QSPI_CONC_XIP_CONT_XFER_TOC(_TOC_) ( (_TOC_) <= 0xFF)
1060 #define IS_QSPI_CONC_XIP_ENDIAN_MODE(_MODE_) ( (QSPI_CONCURRENT_XIP_ENDIAN_MODE_0 == (_MODE_)) || \
1061 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_1 == (_MODE_)) || \
1062 (QSPI_CONCURRENT_XIP_ENDIAN_MODE_2 == (_MODE_)) )
void(* qspi_msp_deinit)(qspi_handle_t *p_qspi)
__IO uint32_t tx_xfer_size
uint32_t instruction_size
hal_lock_t
HAL Lock structures definition.
enum _qspi_memorymapped_idx_e qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
void(* qspi_rx_cplt_callback)(qspi_handle_t *p_qspi)
uint32_t x_instruction_size
@ HAL_MMAPPED_STATE_ACTIVED
hal_status_t hal_qspi_memorymapped_update(qspi_handle_t *p_qspi, qspi_memorymapped_set_t *mmap_set, uint32_t count)
Used to update memorymapped any parameter quickly.
@ QSPI_MMAPED_IDX_CONT_XFER_TOC
@ HAL_QSPI_STATE_BUSY_MEM_MAPPED
qspi_memorymapped_idx_e mmap_key
struct _qspi_memorymapped_t qspi_memorymapped_t
QSPI memory map Structure definition.
hal_status_t hal_qspi_receive(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length, uint32_t timeout)
Receive an amount of data in blocking mode with standard SPI.
hal_status_t hal_qspi_command_receive(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Receive an amount of data with the specified instruction, address and dummy cycles in blocking mode.
uint32_t instruction_address_mode
uint32_t x_inst_addr_transfer_format
@ QSPI_MMAPED_IDX_EDIAN_MODE
__IO uint32_t rx_xfer_size
uint32_t x_continous_xfer_en
Header file containing functions prototypes of QSPI LL library.
struct _qspi_memorymapped_set_t qspi_memorymapped_set_t
KEY:Value pair to set memorymapped parameter.
__IO hal_qspi_state_t state
void(* qspi_error_callback)(qspi_handle_t *p_qspi)
__IO uint32_t rx_xfer_count
@ QSPI_MMAPED_IDX_ADDR_SIZE
hal_status_t hal_qspi_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI peripheral.
hal_status_t hal_qspi_command_transmit_dma_llp_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config, dma_gather_config_t *p_gather_config)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA L...
QSPI init Structure definition.
void hal_qspi_msp_init(qspi_handle_t *p_qspi)
Initialize the QSPI MSP.
uint32_t x_instruction_en
@ QSPI_MMAPED_IDX_MODE_BITS_SIZE
uint32_t data_block_length
void hal_qspi_set_tcsu(qspi_handle_t *p_qspi, uint32_t delay)
Set the QSPI cs setup & release time value.
QSPI command Structure definition.
hal_status_t hal_qspi_receive_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with DMA.
void(* write_fifo)(struct _qspi_handle *p_qspi)
hal_status_t hal_qspi_init(qspi_handle_t *p_qspi)
Initialize the QSPI according to the specified parameters in the qspi_init_t and initialize the assoc...
@ QSPI_MMAPED_IDX_MODE_BITS_EN
void hal_qspi_msp_deinit(qspi_handle_t *p_qspi)
De-initialize the QSPI MSP.
hal_status_t hal_qspi_command_transmit_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with Inter...
hal_status_t hal_qspi_transmit_dma(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Transmit an amount of data in non-blocking mode at standard SPI with DMA.
uint32_t x_data_frame_format
hal_status_t hal_qspi_suspend_reg(qspi_handle_t *p_qspi)
Suspend some registers related to QSPI configuration before sleep.
hal_status_t hal_qspi_transmit_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length)
Transmit an amount of data in non-blocking mode at standard SPI with Interrupt.
void hal_qspi_tx_cplt_callback(qspi_handle_t *p_qspi)
Tx Transfer completed callback.
hal_status_t hal_qspi_transmit(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t data_length, uint32_t timeout)
Transmit an amount of data in blocking mode with standard SPI.
hal_status_t hal_qspi_command_receive_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
@ QSPI_MMAPED_IDX_PREFETCH_EN
void hal_qspi_abort_cplt_callback(qspi_handle_t *p_qspi)
QSPI Abort Complete callback.
hal_status_t hal_qspi_command_transmit(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t timeout)
Transmit an amount of data with the specified instruction and address in blocking mode.
hal_status_t hal_qspi_memorymapped_active(qspi_handle_t *p_qspi, uint32_t is_sioo_mode)
Active the memory mapped mode from Ready state. users must make sure parameters of mmaped mode hava b...
uint32_t x_inst_addr_transfer_format
void(* qspi_tx_cplt_callback)(qspi_handle_t *p_qspi)
hal_status_t hal_qspi_memorymapped_deactive(qspi_handle_t *p_qspi)
Deactive the memory mapped mode to Ready state it's recommended to use with hal_qspi_memorymapped_act...
void hal_qspi_irq_handler(qspi_handle_t *p_qspi)
Handle QSPI interrupt request.
hal_status_t hal_qspi_abort(qspi_handle_t *p_qspi)
Abort the current transmission.
hal_memorymapped_status_t
HAL Status structures Of memorymapped definition.
uint32_t x_instruction_size
KEY:Value pair to set memorymapped parameter.
HAL_QSPI Callback function definition.
void hal_qspi_rx_cplt_callback(qspi_handle_t *p_qspi)
Rx Transfer completed callback.
@ QSPI_MMAPED_IDX_INST_SIZE
hal_status_t hal_qspi_transmit_dma_llp(qspi_handle_t *p_qspi, dma_llp_config_t *p_llp_config, uint32_t data_mode, uint32_t data_length, uint32_t clock_stretch_enable)
Transmit Multi-Block of data without instruction and address in non-blocking mode with DMA Linked Lis...
struct _qspi_memorymapped_write_t qspi_memorymapped_write_t
QSPI memory map write Structure definition.
@ QSPI_MMAPED_IDX_DATA_FRF
@ QSPI_MMAPED_IDX_INST_VAL
QSPI memory map Structure definition.
QSPI memory map write Structure definition.
hal_status_t hal_qspi_abort_it(qspi_handle_t *p_qspi)
Abort the current transmission (non-blocking function)
@ QSPI_MMAPED_IDX_WAIT_CYCLES
struct _qspi_command_t qspi_command_t
QSPI command Structure definition.
@ HAL_QSPI_STATE_BUSY_INDIRECT_RX
void(* qspi_abort_cplt_callback)(qspi_handle_t *p_qspi)
@ QSPI_MMAPED_IDX_CONT_XFER_EN
hal_status_t hal_qspi_psram_transmit_dma_llp_limited(qspi_handle_t *p_qspi, qspi_psram_command_t *p_cmd, dma_llp_config_t *p_llp_config)
: Used to write PSRAM in high speed mode with dma LLP
hal_status_t
HAL Status structures definition.
hal_status_t hal_qspi_command(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint32_t timeout)
Transmit only instruction in blocking mode.
uint32_t x_continous_xfer_toc
void(* read_fifo)(struct _qspi_handle *p_qspi)
hal_status_t hal_qspi_command_transmit_dma_llp(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_llp_config_t *p_llp_config)
Transmit Multi-Block of data with the specified instruction and address in non-blocking mode with DMA...
@ HAL_MMAPPED_STATE_DEACTIVED
uint32_t x_data_frame_format
@ QSPI_MMAPED_IDX_DFS_HARDCCODE_EN
hal_status_t hal_qspi_resume_reg(qspi_handle_t *p_qspi)
Restore some registers related to QSPI configuration after sleep. This function must be used in conju...
LL DMA llp config definition.
hal_status_t hal_qspi_command_receive_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Receive an amount of data with the specified instruction, address and dummy cycles in non-blocking mo...
_qspi_memorymapped_idx_e
KEY index enum for memorymapped mode, use to modify any parameter quickly.
__IO uint32_t tx_xfer_count
@ HAL_QSPI_STATE_BUSY_INDIRECT_TX
hal_status_t hal_qspi_command_transmit_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA .
void hal_qspi_set_timeout(qspi_handle_t *p_qspi, uint32_t timeout)
Set the QSPI internal process timeout value.
hal_status_t hal_qspi_memorymapped(qspi_handle_t *p_qspi, qspi_memorymapped_t *mmap_cmd, qspi_memorymapped_write_t *mmap_wr_cmd)
Configure the Memory Mapped mode. Called after hal_qspi_init(...)
LL DMA gather config definition.
struct _qspi_handle qspi_handle_t
QSPI handle Structure definition.
hal_status_t hal_qspi_receive_it(qspi_handle_t *p_qspi, uint32_t data_mode, uint32_t data_size, uint8_t *p_data, uint32_t length)
Receive an amount of data in non-blocking mode at standard SPI with Interrupt.
hal_status_t hal_qspi_command_it(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with Interrupt.
struct _qspi_init_t qspi_init_t
QSPI init Structure definition.
struct _hal_qspi_callback hal_qspi_callback_t
HAL_QSPI Callback function definition.
hal_status_t hal_qspi_command_receive_dma_scatter(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, uint8_t *p_data, uint32_t sct_interval, uint32_t sct_count)
Receive an amount of data with the specified instruction and address in non-blocking mode with DMA Sc...
hal_qspi_state_t
HAL QSPI State Enumerations definition.
QSPI command for psram-write Structure definition.
hal_qspi_state_t hal_qspi_get_state(qspi_handle_t *p_qspi)
Return the QSPI handle state.
void(* qspi_msp_init)(qspi_handle_t *p_qspi)
hal_status_t hal_qspi_command_dma(qspi_handle_t *p_qspi, qspi_command_t *p_cmd)
Transmit instruction in non-blocking mode with DMA.
QSPI handle Structure definition.
DMA handle Structure definition.
This file contains HAL common definitions, enumeration, macros and structures definitions.
@ QSPI_MMAPED_IDX_MODE_BITS_VAL
uint32_t hal_qspi_get_error(qspi_handle_t *p_qspi)
Return the QSPI error code.
uint32_t clock_stretch_en
@ HAL_MMAPPED_STATE_ERROR
void hal_qspi_error_callback(qspi_handle_t *p_qspi)
QSPI error callback.
@ QSPI_MMAPED_IDX_INST_ADDR_XFER_FORMAT
uint32_t x_mode_bits_data
hal_memorymapped_status_t hal_qspi_memorymapped_is_actived(qspi_handle_t *p_qspi)
Check whether the memory mapped mode is Actived.
uint32_t x_mode_bits_length
@ QSPI_MMAPED_IDX_INST_EN
hal_status_t hal_qspi_command_transmit_dma_gather(qspi_handle_t *p_qspi, qspi_command_t *p_cmd, dma_gather_config_t *p_gather_config, uint8_t *p_data)
Transmit an amount of data with the specified instruction and address in non-blocking mode with DMA G...