52 #ifndef __GR55XX_LL_ADC_H__
53 #define __GR55XX_LL_ADC_H__
76 typedef struct _ll_adc_init
128 #define LL_ADC_CLK_16M (4UL << MCU_SUB_SNSADC_CLK_WR_Pos)
129 #define LL_ADC_CLK_8M (5UL << MCU_SUB_SNSADC_CLK_WR_Pos)
130 #define LL_ADC_CLK_4M (6UL << MCU_SUB_SNSADC_CLK_WR_Pos)
131 #define LL_ADC_CLK_1M (7UL << MCU_SUB_SNSADC_CLK_WR_Pos)
132 #define LL_ADC_CLK_16K (1UL << MCU_SUB_SNSADC_CLK_WR_Pos)
133 #define LL_ADC_CLK_8K (2UL << MCU_SUB_SNSADC_CLK_WR_Pos)
134 #define LL_ADC_CLK_4K (3UL << MCU_SUB_SNSADC_CLK_WR_Pos)
135 #define LL_ADC_CLK_NONE (0UL << MCU_SUB_SNSADC_CLK_WR_Pos)
142 #define LL_ADC_REF_VALUE_0P8 (0x4UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
143 #define LL_ADC_REF_VALUE_1P2 (0x7UL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
144 #define LL_ADC_REF_VALUE_1P6 (0xBUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
145 #define LL_ADC_REF_VALUE_2P0 (0xFUL << AON_PMU_SNSADC_CFG_REF_VALUE_Pos)
151 #define LL_ADC_INPUT_SINGLE (1UL << AON_PMU_SNSADC_CFG_SINGLE_EN_Pos)
152 #define LL_ADC_INPUT_DIFFERENTIAL (0x00000000UL)
158 #define LL_ADC_INPUT_SRC_IO0 (0UL)
159 #define LL_ADC_INPUT_SRC_IO1 (1UL)
160 #define LL_ADC_INPUT_SRC_IO2 (2UL)
161 #define LL_ADC_INPUT_SRC_IO3 (3UL)
162 #define LL_ADC_INPUT_SRC_IO4 (4UL)
163 #define LL_ADC_INPUT_SRC_IO5 (5UL)
164 #define LL_ADC_INPUT_SRC_IO6 (6UL)
165 #define LL_ADC_INPUT_SRC_IO7 (7UL)
166 #define LL_ADC_INPUT_SRC_TMP (13UL)
167 #define LL_ADC_INPUT_SRC_BAT (14UL)
168 #define LL_ADC_INPUT_SRC_REF (15UL)
176 #define LL_ADC_REF_SRC_BUF_INT (0x00000000UL)
177 #define LL_ADC_REF_SRC_IO0 (3UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
178 #define LL_ADC_REF_SRC_IO1 (4UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
179 #define LL_ADC_REF_SRC_IO2 (5UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
180 #define LL_ADC_REF_SRC_IO3 (6UL << AON_PMU_SNSADC_CFG_REF_SEL_Pos)
187 #define LL_ADC_CFG_REG_DEFAULT (0x0710070AU)
208 #define LL_ADC_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG((__instance__)->__REG__, (__VALUE__))
216 #define LL_ADC_ReadReg(__instance__, __REG__) READ_REG((__instance__)->__REG__)
238 #define LL_ADC_DEFAULT_CONFIG \
240 .channel_p = LL_ADC_INPUT_SRC_IO0, \
241 .channel_n = LL_ADC_INPUT_SRC_IO1, \
242 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
243 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
244 .ref_value = LL_ADC_REF_VALUE_1P2, \
245 .clock = LL_ADC_CLK_16M \
248 #define LL_ADC_DEFAULT_CONFIG \
250 .channel_p = LL_ADC_INPUT_SRC_IO0, \
251 .channel_n = LL_ADC_INPUT_SRC_IO1, \
252 .input_mode = LL_ADC_INPUT_DIFFERENTIAL, \
253 .ref_source = LL_ADC_REF_SRC_BUF_INT, \
254 .ref_value = LL_ADC_REF_VALUE_1P2, \
255 .clock = LL_ADC_CLK_16 \
282 __STATIC_INLINE
void ll_adc_enable(
void)
285 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
298 __STATIC_INLINE
void ll_adc_disable(
void)
301 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk);
314 __STATIC_INLINE uint32_t ll_adc_is_enabled(
void)
317 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_EN_Msk) == (AON_PMU_SNSADC_CFG_EN_Msk));
330 __STATIC_INLINE
void ll_adc_disable_clock(
void)
333 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, MCU_SUB_SNSADC_CLK_NONE);
346 __STATIC_INLINE uint32_t ll_adc_is_enabled_clock(
void)
349 return (READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) != 0);
370 __STATIC_INLINE
void ll_adc_set_clock(uint32_t clk)
373 MODIFY_REG(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_WR, clk);
393 __STATIC_INLINE uint32_t ll_adc_get_clock(
void)
396 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_CLK, MCU_SUB_SNSADC_CLK_RD) >> MCU_SUB_SNSADC_CLK_RD_Pos);
414 __STATIC_INLINE
void ll_adc_set_ref_value(uint32_t value)
417 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk, value);
434 __STATIC_INLINE uint32_t ll_adc_get_ref_value(
void)
437 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_VALUE_Msk) >> AON_PMU_SNSADC_CFG_REF_VALUE_Pos);
450 __STATIC_INLINE
void ll_adc_enable_temp(
void)
453 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
466 __STATIC_INLINE
void ll_adc_disable_temp(
void)
469 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk);
482 __STATIC_INLINE uint32_t ll_adc_is_enabled_temp(
void)
485 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_TEMP_EN_Msk) == (AON_PMU_SNSADC_CFG_TEMP_EN_Msk));
498 __STATIC_INLINE
void ll_adc_enable_vbat(
void)
501 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
514 __STATIC_INLINE
void ll_adc_disable_vbat(
void)
517 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk);
530 __STATIC_INLINE uint32_t ll_adc_is_enabled_vbat(
void)
533 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_VBAT_EN_Msk) == (AON_PMU_SNSADC_CFG_VBAT_EN_Msk));
549 __STATIC_INLINE
void ll_adc_set_input_mode(uint32_t mode)
552 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk, mode);
567 __STATIC_INLINE uint32_t ll_adc_get_input_mode(
void)
570 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_SINGLE_EN_Msk) >> AON_PMU_SNSADC_CFG_SINGLE_EN_Pos);
585 __STATIC_INLINE
void ll_adc_enable_ofs_cal(
void)
588 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
601 __STATIC_INLINE
void ll_adc_disable_ofs_cal(
void)
604 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk);
617 __STATIC_INLINE uint32_t ll_adc_is_enabled_ofs_cal(
void)
620 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk) == (AON_PMU_SNSADC_CFG_OFS_CAL_EN_Msk));
635 __STATIC_INLINE
void ll_adc_set_dynamic_rang(uint32_t rang)
638 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk, (rang & 0x7) << AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
651 __STATIC_INLINE uint32_t ll_adc_get_dynamic_rang(
void)
654 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_DYMAMIC_Msk) >> AON_PMU_SNSADC_CFG_DYMAMIC_Pos);
675 __STATIC_INLINE
void ll_adc_set_channelp(uint32_t source)
678 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk, source << AON_PMU_SNSADC_CFG_CHN_P_Pos);
698 __STATIC_INLINE uint32_t ll_adc_get_channelp(
void)
701 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_P_Msk) >> AON_PMU_SNSADC_CFG_CHN_P_Pos);
722 __STATIC_INLINE
void ll_adc_set_channeln(uint32_t source)
725 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk, source << AON_PMU_SNSADC_CFG_CHN_N_Pos);
745 __STATIC_INLINE uint32_t ll_adc_get_channeln(
void)
748 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_CHN_N_Msk) >> AON_PMU_SNSADC_CFG_CHN_N_Pos);
761 __STATIC_INLINE
void ll_adc_enable_mas_rst(
void)
764 SET_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
777 __STATIC_INLINE
void ll_adc_disable_mas_rst(
void)
780 CLEAR_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk);
793 __STATIC_INLINE uint32_t ll_adc_is_enabled_mas_rst(
void)
796 return (READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_MAS_RST_Msk) == (AON_PMU_SNSADC_CFG_MAS_RST_Msk));
815 __STATIC_INLINE
void ll_adc_set_ref(uint32_t source)
818 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk, source);
836 __STATIC_INLINE uint32_t ll_adc_get_ref(
void)
839 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_SEL_Msk) >> AON_PMU_SNSADC_CFG_REF_SEL_Pos);
855 __STATIC_INLINE
void ll_adc_set_ref_current(uint32_t source)
858 MODIFY_REG(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk, (source & 0x7) << AON_PMU_SNSADC_CFG_REF_HP_Pos);
871 __STATIC_INLINE uint32_t ll_adc_get_ref_current(
void)
874 return (uint32_t)(READ_BITS(AON_PMU->SNSADC_CFG, AON_PMU_SNSADC_CFG_REF_HP_Msk) >> AON_PMU_SNSADC_CFG_REF_HP_Pos);
894 __STATIC_INLINE uint32_t ll_adc_read_fifo(
void)
896 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_FIFO));
909 __STATIC_INLINE
void ll_adc_set_thresh(uint32_t thresh)
911 MODIFY_REG(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH, (thresh & 0x3F) << MCU_SUB_SNSADC_FF_THRESH_Pos);
923 __STATIC_INLINE uint32_t ll_adc_get_thresh(
void)
925 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_THRESH) >> MCU_SUB_SNSADC_FF_THRESH_Pos);
937 __STATIC_INLINE
void ll_adc_enable_dma_req(
void)
940 SET_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
953 __STATIC_INLINE
void ll_adc_disable_dma_req(
void)
956 CLEAR_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk);
970 __STATIC_INLINE uint32_t ll_adc_is_enabled_dma_req(
void)
973 return (READ_BITS(MCU_SUB->SENSE_FF_THRESH, MCU_SUB_SNSADC_FF_DMA_EN_Msk) == (MCU_SUB_SNSADC_FF_DMA_EN_Msk));
986 __STATIC_INLINE uint32_t ll_adc_is_fifo_notempty(
void)
988 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_VAL) == MCU_SUB_SNSADC_STAT_VAL);
1000 __STATIC_INLINE uint32_t ll_adc_get_fifo_count(
void)
1002 return (uint32_t)(READ_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FF_COUNT) >> MCU_SUB_SNSADC_STAT_FF_COUNT_Pos);
1014 __STATIC_INLINE
void ll_adc_flush_fifo(
void)
1016 SET_BITS(MCU_SUB->SENSE_ADC_STAT, MCU_SUB_SNSADC_STAT_FLUSH_Msk);
1028 __STATIC_INLINE uint32_t ll_adc_try_lock_sw_token(
void)
1030 return (uint32_t)(READ_REG(MCU_SUB->SENSE_ADC_GET_TKN_SW) == MCU_SUB_SNSADC_TKN_LOCKED_SW);
1042 __STATIC_INLINE
void ll_adc_release_sw_token(
void)
1044 CLEAR_BITS(MCU_SUB->SENSE_ADC_RET_TKN_SW, MCU_SUB_SNSADC_RET_TKN_SW_RELEASE_Msk);
1056 __STATIC_INLINE uint32_t ll_adc_get_token_state(
void)
1058 return READ_REG(MCU_SUB->SENSE_ADC_TKN_STS);
1073 error_status_t ll_adc_deinit(
void);
1084 error_status_t ll_adc_init(ll_adc_init_t *p_adc_init);
1092 void ll_adc_struct_init(ll_adc_init_t *p_adc_init);