gr533x_ll_pwr.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_LL_PWR_H__
53 #define __GR533x_LL_PWR_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61
62 #if defined(AON_CTL) && defined(AON_IO)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
70 * @{
71 */
72
73 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
74 * @{
75 */
76 #define LL_PWR_WKUP_COND_EXT AON_CTL_MCU_WAKEUP_CTRL_EXT /**< External wakeup: AON_GPIO */
77 #define LL_PWR_WKUP_COND_TIMER AON_CTL_MCU_WAKEUP_CTRL_SLP_TIMER /**< AON Timer wakeup */
78 #define LL_PWR_WKUP_COND_BLE AON_CTL_MCU_WAKEUP_CTRL_SMS_OSC /**< BLE wakeup */
79 #define LL_PWR_WKUP_COND_CLDR AON_CTL_MCU_WAKEUP_CTRL_RTC0 /**< RTC0 wakeup */
80 #define LL_PWR_WKUP_COND_AON_WDT AON_CTL_MCU_WAKEUP_CTRL_AON_WDT /**< AON WDT reahch 0 wakeup */
81 #define LL_PWR_WKUP_COND_COMP_RISE AON_CTL_MCU_WAKEUP_CTRL_COMP_RISE /**< COMP rise wakeup */
82 #define LL_PWR_WKUP_COND_COMP_FALL AON_CTL_MCU_WAKEUP_CTRL_COMP_FALL /**< COMP fall wakeup */
83 #define LL_PWR_WKUP_COND_ALL AON_CTL_WAKEUP_CTRL_SEL /**< All wakeup sources mask */
84
85 /** @} */
86
87 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
88 * @{
89 */
90 #define LL_PWR_WKUP_EVENT_BLE AON_CTL_SLP_EVENT_SMS_OSC /**< BLE Timer wakeup event */
91 #define LL_PWR_WKUP_EVENT_TIMER AON_CTL_SLP_EVENT_SLP_TIMER /**< AON Timer wakeup event */
92 #define LL_PWR_WKUP_EVENT_EXT AON_CTL_SLP_EVENT_EXT /**< External wakeup event: AON_GPIO */
93 #define LL_PWR_WKUP_EVENT_COMP_RISE AON_CTL_SLP_EVENT_COMP_RISE /**< Comparator rise wakeup event */
94 #define LL_PWR_WKUP_EVENT_COMP_FALL AON_CTL_SLP_EVENT_COMP_FALL /**< Comparator fall wakeup event */
95 #define LL_PWR_WKUP_EVENT_WDT AON_CTL_SLP_EVENT_AON_WDT /**< AON WDT Alarm wakeup event */
96 #define LL_PWR_WKUP_EVENT_CLDR AON_CTL_SLP_EVENT_RTC0 /**< RTC0 wakeup event */
97 #define LL_PWR_WKUP_EVENT_ALL AON_CTL_SLP_EVENT_ALL /**< All event mask */
98 /** @} */
99
100 /** @defgroup PWR_LL_EC_AON_IRQ Condition
101 * @{
102 */
103 #define LL_PWR_AON_IRQ_EVT_BLE_PWR_ON AON_CTL_AON_IRQ_BLE_PWR /**< BLE power up done IRQ event */
104 #define LL_PWR_AON_IRQ_EVT_BLE_PWR_DN AON_CTL_AON_IRQ_BLE_PWR_DN /**< BLE power down done IRQ event */
105 #define LL_PWR_AON_IRQ_EVT_BOD_RISE AON_CTL_AON_IRQ_PMU_BOD_RISE /**< BOD rise edge IRQ event */
106 #define LL_PWR_AON_IRQ_EVT_CPLL_DN AON_CTL_AON_IRQ_AONPLL_CHG /**< PLL power on done IRQ event */
107 #define LL_PWR_AON_IRQ_EVT_BOD_FALL AON_CTL_AON_IRQ_PMU_BOD_FALL /**< PMU BOD fall edge IRQ event */
108 #define LL_PWR_AON_IRQ_EVT_BLE_MAC AON_CTL_AON_IRQ_BLE_MAC_IRQ /**< BLE MAC IRQ event */
109 #define LL_PWR_AON_IRQ_EVT_SLP_FAIL AON_CTL_AON_IRQ_SLP_FAIL_IRQ /**< Sleep fail IRQ event */
110 #define LL_PWR_AON_IRQ_EVT_ALL AON_CTL_AON_IRQ_BLE_ALL /**< All IRQ event mask */
111
112 /** @} */
113
114 /** @defgroup PWR_LL_EC_AON_IRQ_EVT Event
115 * @{
116 */
117 #define LL_PWR_AON_IRQ_EN_BLE_PWR_ON AON_CTL_AON_IRQ_EN_BLE_PWR_ON /**< BLE power up done IRQ EN */
118 #define LL_PWR_AON_IRQ_EN_BLE_PWR_DN AON_CTL_AON_IRQ_EN_BLE_PWR_DN /**< BLE power down done IRQ EN */
119 #define LL_PWR_AON_IRQ_EN_BOD_RISE AON_CTL_AON_IRQ_EN_PMU_BOD_RISE /**< BOD rise edge IRQ EN */
120 #define LL_PWR_AON_IRQ_EN_CPLL_DN AON_CTL_AON_IRQ_EN_AONPLL_CHG /**< PLL power on done IRQ EN */
121 #define LL_PWR_AON_IRQ_EN_BOD_FALL AON_CTL_AON_IRQ_EN_PMU_BOD_FALL /**< PMU BOD fall edge IRQ EN */
122 #define LL_PWR_AON_IRQ_EN_BLE_MAC AON_CTL_AON_IRQ_EN_BLE_MAC_IRQ /**< BLE MAC IRQ EN */
123 #define LL_PWR_AON_IRQ_EN_SLP_FAIL AON_CTL_AON_IRQ_EN_SLP_FAIL_IRQ /**< Sleep fail IRQ EN */
124 #define LL_PWR_AON_IRQ_EN_ALL AON_CTL_AON_IRQ_EN_ALL /**< All IRQ EN */
125 /** @} */
126
127
128 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
129 * @{
130 */
131
132 /** @} */
133 /** @} */
134
135 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
136 * @{
137 */
138 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
139 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
140 /** @} */
141
142 /** @} */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
146 * @{
147 */
148
149 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
150 * @{
151 */
152
153 /**
154 * @brief Set the DeepSleep WakeUp Condition
155 *
156 * Register|BitsName
157 * --------|--------
158 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
159 *
160 * @param condition This parameter can be one of the following values:
161 * @arg @ref LL_PWR_WKUP_COND_EXT
162 * @arg @ref LL_PWR_WKUP_COND_TIMER
163 * @arg @ref LL_PWR_WKUP_COND_BLE
164 * @arg @ref LL_PWR_WKUP_COND_CLDR
165 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
166 * @arg @ref LL_PWR_WKUP_COND_COMP_RISE
167 * @arg @ref LL_PWR_WKUP_COND_COMP_FALL
168 * @arg @ref LL_PWR_WKUP_COND_ALL
169 * @retval None
170 */
171 __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
172 {
173 SET_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
174 }
175
176 /**
177 * @brief Clear the DeepSleep WakeUp Condition
178 *
179 * Register|BitsName
180 * --------|--------
181 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
182 *
183 * @param condition This parameter can be one of the following values:
184 * @arg @ref LL_PWR_WKUP_COND_EXT
185 * @arg @ref LL_PWR_WKUP_COND_TIMER
186 * @arg @ref LL_PWR_WKUP_COND_BLE
187 * @arg @ref LL_PWR_WKUP_COND_CLDR
188 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
189 * @arg @ref LL_PWR_WKUP_COND_COMP_RISE
190 * @arg @ref LL_PWR_WKUP_COND_COMP_FALL
191 * @arg @ref LL_PWR_WKUP_COND_ALL
192 * @retval None
193 */
194 __STATIC_INLINE void ll_pwr_clear_wakeup_condition(uint32_t condition)
195 {
196 CLEAR_BITS(AON_CTL->MCU_WAKEUP_CTRL, condition);
197 }
198
199 /**
200 * @brief Get the Selected DeepSleep WakeUp Condition
201 *
202 * Register|BitsName
203 * --------|--------
204 * MCU_WAKEUP_CTRL | MCU_WAKEUP_CTRL
205 *
206 * @retval Returned value can be one of the following values:
207 * @arg @ref LL_PWR_WKUP_COND_EXT
208 * @arg @ref LL_PWR_WKUP_COND_TIMER
209 * @arg @ref LL_PWR_WKUP_COND_BLE
210 * @arg @ref LL_PWR_WKUP_COND_CLDR
211 * @arg @ref LL_PWR_WKUP_COND_AON_WDT
212 * @arg @ref LL_PWR_WKUP_COND_COMP_RISE
213 * @arg @ref LL_PWR_WKUP_COND_COMP_FALL
214 * @arg @ref LL_PWR_WKUP_COND_ALL
215 */
216 __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
217 {
218 return ((uint32_t)READ_BITS(AON_CTL->MCU_WAKEUP_CTRL, LL_PWR_WKUP_COND_ALL));
219 }
220
221 /**
222 * @brief Get the Event that triggered the DeepSleep WakeUp.
223 * @note Only available on GR551xx_B2 and later version
224 *
225 * Register|BitsName
226 * --------|--------
227 * AON_SLP_EVENT | AON_SLP_EVENT
228 *
229 * @retval Returned value can be combination of the following values:
230 * @arg @ref LL_PWR_WKUP_EVENT_BLE
231 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
232 * @arg @ref LL_PWR_WKUP_EVENT_EXT
233 * @arg @ref LL_PWR_WKUP_EVENT_COMP_RISE
234 * @arg @ref LL_PWR_WKUP_EVENT_COMP_FALL
235 * @arg @ref LL_PWR_WKUP_EVENT_WDT
236 * @arg @ref LL_PWR_WKUP_EVENT_CLDR
237 */
238 __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
239 {
240 return ((uint32_t)READ_BITS(AON_CTL->AON_SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
241 }
242
243 /**
244 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
245 * @note After the value was set, use LL_PWR_CMD_32_TIMER_LD command to
246 * load the configuration into Power State Controller.
247 *
248 * Register|BitsName
249 * --------|--------
250 * SLEEP_TIMER_W | SLEEP_TIMER_W
251 *
252 * @param value 32 bits count value loaded into the t32bit_timer
253 * @retval None
254 */
255 __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
256 {
257 WRITE_REG(SLP_TIMER->TIMER_W, value);
258 }
259
260 /**
261 * @brief Read the AON Sleep Timer counter current value.
262 *
263 * Register|BitsName
264 * --------|--------
265 * SLEEP_TIMER_R | PWR_CTL_TIMER_32B
266 *
267 * @retval 32 bit AON Timer Count Value
268 */
269 __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_read_value(void)
270 {
271 return READ_REG(SLP_TIMER->TIMER_R);
272 }
273
274
275 /**
276 * @brief Enable the SMC WakeUp Request.
277 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
278 *
279 * Register|BitsName
280 * --------|--------
281 * BLE_MISC | SMC_WAKEUP_REQ
282 *
283 * @retval None
284 */
285 __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
286 {
287 SET_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
288 }
289
290 /**
291 * @brief Disable the SMC WakeUp Request.
292 * @note This function is used to clear SMC WakeUp Request.
293 *
294 * Register|BitsName
295 * --------|--------
296 * BLE_MISC | SMC_WAKEUP_REQ
297 *
298 * @retval None
299 */
300 __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
301 {
302 CLEAR_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
303 }
304
305 /**
306 * @brief Check if the SMC WakeUp Request was enabled or disabled.
307 *
308 * Register|BitsName
309 * --------|--------
310 * BLE_MISC | SMC_WAKEUP_REQ
311 *
312 * @retval State of bit (1 or 0).
313 */
314 __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
315 {
316 return (READ_BITS(AON_CTL->BLE_MISC, AON_CTL_BLE_MISC_SMC_WAKEUP_REQ) == AON_CTL_BLE_MISC_SMC_WAKEUP_REQ);
317 }
318
319 /**
320 * @brief Set the DPAD LE value during sleep and after wake up.
321 *
322 * Register|BitsName
323 * --------|--------
324 * DPAD_LE_CTRL | DPAD_LE_SLP_VAL
325 * DPAD_LE_CTRL | DPAD_LE_WKUP_VAL
326 *
327 * @param sleep This parameter can be one of the following values:
328 * @arg @ref LL_PWR_DPAD_LE_OFF
329 * @arg @ref LL_PWR_DPAD_LE_ON
330 * @param wakeup This parameter can be one of the following values:
331 * @arg @ref LL_PWR_DPAD_LE_OFF
332 * @arg @ref LL_PWR_DPAD_LE_ON
333 * @retval None
334 */
335 __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
336 {
337 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_SLEEP, (sleep << AON_PWR_DPAD_LE_CTRL_SLEEP_Pos));
338 MODIFY_REG(AON_PWR->DPAD_LE_CTRL, AON_PWR_DPAD_LE_CTRL_WAKEUP, (wakeup << AON_PWR_DPAD_LE_CTRL_WAKEUP_Pos));
339 }
340
341 /** @} */
342
343 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
344 * @{
345 */
346
347 /**
348 * @brief Enable the Communication Timer Reset.
349 * @note Comm timer can be reset when all ble connection were disconnected and
350 * MCU was ready to enter into deepsleep mode.
351 *
352 * Register|BitsName
353 * --------|--------
354 * COMM_CTRL | COMM_TIMER_RST_N
355 *
356 * @retval None
357 */
358 __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
359 {
360 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
361 }
362
363 /**
364 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
365 * @note After powered up, Comm Timer need to enter into running mode.
366 *
367 * Register|BitsName
368 * --------|--------
369 * COMM_CTRL | COMM_TIMER_RST_N
370 *
371 * @retval None
372 */
373 __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
374 {
375 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N);
376 }
377
378 /**
379 * @brief Check if the Communication Timer Reset was enabled or disabled.
380 *
381 * Register|BitsName
382 * --------|--------
383 * COMM_CTRL | COMM_TIMER_RST_N
384 *
385 * @retval State of bit (1 or 0).
386 */
387 __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
388 {
389 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_RST_N) == 0x0U));
390 }
391
392 /**
393 * @brief Enable the Communication Core Reset.
394 * @note Comm Core can be reset when all ble connection were disconnected and
395 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
396 * is 0, the ble is held in reset.
397 *
398 * Register|BitsName
399 * --------|--------
400 * COMM_CTRL | COMM_CORE_RST_N
401 *
402 * @retval None
403 */
404 __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
405 {
406 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
407 }
408
409 /**
410 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
411 * @note After powered up, Comm Core need to enter into running mode.
412 *
413 * Register|BitsName
414 * --------|--------
415 * COMM_CTRL | COMM_CORE_RST_N
416 *
417 * @retval None
418 */
419 __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
420 {
421 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_RST_N);
422 }
423
424 /**
425 * @brief Check if the Communication Core Reset was enabled or disabled.
426 *
427 * Register|BitsName
428 * --------|--------
429 * COMM_CTRL | COMM_CORE_RST_N
430 *
431 * @retval State of bit (1 or 0).
432 */
433 __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
434 {
435 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_RST_N_RD) == 0x0U));
436 }
437
438 /**
439 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
440 *
441 * Register|BitsName
442 * --------|--------
443 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
444 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
445 *
446 * @retval None
447 */
448 __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
449 {
450 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
451 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
452 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
453 }
454
455 /**
456 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
457 *
458 * Register|BitsName
459 * --------|--------
460 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
461 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
462 *
463 * @retval None
464 */
465 __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
466 {
467 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
468 SET_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_ISO_EN);
469 CLEAR_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN);
470 }
471
472 /**
473 * @brief Check if the Communication Timer Power was enabled or disabled.
474 *
475 * Register|BitsName
476 * --------|--------
477 * BLE_PWR_CTL | ISO_EN_PD_COMM_TIMER
478 * BLE_PWR_CTL | PWR_EN_PD_COMM_TIMER
479 *
480 * @retval State of bit (1 or 0).
481 */
482 __STATIC_FORCEINLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
483 {
484 return ((uint32_t)(READ_BITS(AON_PWR->COMM_TIMER_PWR_CTRL, AON_PWR_COMM_TIMER_PWR_CTRL_EN) == AON_PWR_COMM_TIMER_PWR_CTRL_EN));
485 }
486
487 /**
488 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
489 *
490 * Register|BitsName
491 * --------|--------
492 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
493 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
494 *
495 * @retval None
496 */
497 __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
498 {
499 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
500 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
501 }
502
503 /**
504 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
505 *
506 * Register|BitsName
507 * --------|--------
508 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
509 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
510 *
511 * @retval None
512 */
513 __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
514 {
515 SET_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_ISO_EN);
516 CLEAR_BITS(AON_PWR->COMM_CORE_PWR_CTRL_SW, AON_PWR_COMM_CORE_PWR_CTRL_SW_CORE_EN);
517 }
518
519 /**
520 * @brief Check if the Communication Core Power was enabled or disabled.
521 *
522 * Register|BitsName
523 * --------|--------
524 * BLE_PWR_CTL | ISO_EN_PD_COMM_CORE
525 * BLE_PWR_CTL | PWR_EN_PD_COMM_CORE
526 *
527 * @retval None
528 */
529 __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
530 {
531 return ((uint32_t)(READ_BITS(AON_PWR->COMM_CORE_PWR_STAT, AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD) == AON_PWR_COMM_CORE_PWR_STAT_CORE_EN_RD));
532 }
533
534 /**
535 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
536 *
537 * Register|BitsName
538 * --------|--------
539 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
540 *
541 * @retval None
542 */
543 __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
544 {
545 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
546 }
547
548 /**
549 * @brief Disable high frequency crystal oscillator sleep mode.
550 * @note Switch OSC from sleep mode into normal active mode.
551 *
552 * Register|BitsName
553 * --------|--------
554 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
555 *
556 * @retval None
557 */
558 __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
559 {
560 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN);
561 }
562
563 /**
564 * @brief Check if the OSC sleep mode was enabled or disabled.
565 *
566 * Register|BitsName
567 * --------|--------
568 * BLE_PWR_CTL | COMM_DEEPSLCNTL_OSC_SLEEP_EN
569 *
570 * @retval State of bit (1 or 0).
571 */
572 __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
573 {
574 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_OSC_SLEEP_EN));
575 }
576
577 /**
578 * @brief Enable Radio sleep mode, and disable Radio module.
579 *
580 * Register|BitsName
581 * --------|--------
582 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
583 *
584 * @retval None
585 */
586 __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
587 {
588 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
589 }
590
591 /**
592 * @brief Disable Radio sleep mode.
593 * @note Switch Radio from sleep mode into normal active mode.
594 *
595 * Register|BitsName
596 * --------|--------
597 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
598 *
599 * @retval None
600 */
601 __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
602 {
603 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN);
604 }
605
606 /**
607 * @brief Check if the Radio sleep mode was enabled or disabled.
608 *
609 * Register|BitsName
610 * --------|--------
611 * BLE_PWR_CTL | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
612 *
613 * @retval State of bit (1 or 0).
614 */
615 __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
616 {
617 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN) == AON_CTL_COMM_CTRL_DEEPSLCNTL_RADIO_SLEEP_EN));
618 }
619
620 /**
621 * @brief Enable Communication Core Deep Sleep Mode.
622 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
623 *
624 * Register|BitsName
625 * --------|--------
626 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
627 *
628 * @retval None
629 */
630 __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
631 {
632 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
633 }
634
635 /**
636 * @brief Disable Communication Core Deep Sleep Mode.
637 * @note Switch Communication Core from sleep mode into normal active mode.
638 *
639 * Register|BitsName
640 * --------|--------
641 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
642 *
643 * @retval None
644 */
645 __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
646 {
647 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON);
648 }
649
650 /**
651 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
652 *
653 * Register|BitsName
654 * --------|--------
655 * BLE_PWR_CTL | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
656 *
657 * @retval State of bit (1 or 0).
658 */
659 __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
660 {
661 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_ON));
662 }
663
664 /**
665 * @brief Enable Wake Up Request from Software.
666 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
667 * when written with a 1. No action happens if it is written with 0.
668 *
669 * Register|BitsName
670 * --------|--------
671 * BLE_PWR_CTL | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
672 *
673 * @retval None
674 */
675 __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
676 {
677 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ);
678 }
679
680 /**
681 * @brief Check if the Wake Up Request was enabled or disabled.
682 * @note Resets at 0 means request action is performed.
683 *
684 * Register|BitsName
685 * --------|--------
686 * BLE_PWR_CTL | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
687 *
688 * @retval State of bit (1 or 0).
689 */
690 __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
691 {
692 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ) == AON_CTL_COMM_CTRL_DEEPSLCNTL_SOFT_WAKEUP_REQ));
693 }
694
695 /**
696 * @brief Enable Communication Core external wakeup.
697 * @note After this configuration, Communication Core can be woken up by external wake-up
698 *
699 * Register|BitsName
700 * --------|--------
701 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
702 *
703 * @retval None
704 */
705 __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
706 {
707 CLEAR_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
708 }
709
710 /**
711 * @brief Disable Communication Core external wakeup.
712 * @note After this configuration, Communication Core cannot be woken up by external wake-up
713 *
714 * Register|BitsName
715 * --------|--------
716 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
717 *
718 * @retval None
719 */
720 __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
721 {
722 SET_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB);
723 }
724
725 /**
726 * @brief Check if the Communication Core external wakeup was enabled or disabled.
727 *
728 * Register|BitsName
729 * --------|--------
730 * BLE_PWR_CTL | COMM_DEEPSLCNTL_EXTWKUPDSB
731 *
732 * @retval State of bit (1 or 0).
733 */
734 __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
735 {
736 return ((uint32_t)(READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
737 }
738
739 /**
740 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
741 *
742 * Register|BitsName
743 * --------|--------
744 * COMM_TIMER_CFG_0 | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
745 *
746 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
747 * @retval None
748 */
749 __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
750 {
751 WRITE_REG(AON_CTL->COMM_TIMER_CFG0, time);
752 }
753
754 /**
755 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
756 *
757 * Register|BitsName
758 * --------|--------
759 * COMM_TIMER_CFG_0 | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
760 *
761 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
762 */
763 __STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
764 {
765 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG0));
766 }
767
768 /**
769 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
770 *
771 * Register|BitsName
772 * --------|--------
773 * COMM_TMR_REG | DEEPSLDUR
774 *
775 * @retval Sleep duration
776 */
777 __STATIC_FORCEINLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
778 {
779 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_STAT));
780 }
781
782 /**
783 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
784 *
785 * Register|BitsName
786 * --------|--------
787 * COMM_TIMER_CFG_1 | TWEXT
788 * COMM_TIMER_CFG_1 | TWOSC
789 * COMM_TIMER_CFG_1 | TWRM
790 *
791 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
792 * oscillator following an external wake–up request (signal wakeup_req).
793 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
794 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
795 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
796 * @retval None
797 */
798 __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
799 {
800 WRITE_REG(AON_CTL->COMM_TIMER_CFG1, (twext << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWEXT_Pos) |
801 (twosc << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos) |
802 (twrm << AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWRM_Pos));
803 }
804
805 /**
806 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
807 *
808 * Register|BitsName
809 * --------|--------
810 * COMM_TIMER_CFG_1 | TWEXT
811 * COMM_TIMER_CFG_1 | TWOSC
812 * COMM_TIMER_CFG_1 | TWRM
813 *
814 * @retval COMM_TMR_ENBPRESET Register value
815 */
816 __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
817 {
818 return ((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1));
819 }
820
821 /**
822 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
823 *
824 * @retval TWOSC value
825 */
826 __STATIC_FORCEINLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
827 {
828 return ((((uint32_t)READ_REG(AON_CTL->COMM_TIMER_CFG1) & AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Msk)) >> AON_CTL_COMM_TIMER_CFG1_ENBPRESET_TWOSC_Pos);
829 }
830
831 /** @} */
832
833 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
834 * @{
835 */
836
837 /**
838 * @brief Get the External Wake Up Status.
839 * @note 0 means not waked up and 1 means waked up.
840 *
841 * Register|BitsName
842 * --------|--------
843 * EXT_WAKEUP_STAT | EXT_WKUP_STATUS
844 *
845 * @retval Returned value can be a combination of the following values:
846 * LL_PWR_EXTWKUP_PIN0
847 * LL_PWR_EXTWKUP_PIN1
848 * LL_PWR_EXTWKUP_PIN2
849 * LL_PWR_EXTWKUP_PIN3
850 * LL_PWR_EXTWKUP_PIN4
851 * LL_PWR_EXTWKUP_PIN5
852 * LL_PWR_EXTWKUP_PIN6
853 * LL_PWR_EXTWKUP_PIN7
854 * LL_PWR_EXTWKUP_PIN_ALL
855 */
856 __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
857 {
858 return ((uint32_t)(READ_BITS(AON_CTL->EXT_WAKEUP_STAT, AON_IO_EXT_WAKEUP_STAT_STAT) >> AON_IO_EXT_WAKEUP_STAT_STAT_POS));
859 }
860
861 /**
862 * @brief Clear the External Wake Up Status.
863 *
864 * Register|BitsName
865 * --------|--------
866 * EXT_WAKEUP_STAT | EXT_WKUP_STATUS
867 *
868 * @param wakeup_pin This parameter can be a combination of the following values:
869 * LL_PWR_EXTWKUP_PIN0
870 * LL_PWR_EXTWKUP_PIN1
871 * LL_PWR_EXTWKUP_PIN2
872 * LL_PWR_EXTWKUP_PIN3
873 * LL_PWR_EXTWKUP_PIN4
874 * LL_PWR_EXTWKUP_PIN5
875 * LL_PWR_EXTWKUP_PIN6
876 * LL_PWR_EXTWKUP_PIN7
877 * LL_PWR_EXTWKUP_PIN_ALL
878 * @retval None
879 */
880 __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
881 {
882 WRITE_REG(AON_CTL->EXT_WAKEUP_STAT, ~(wakeup_pin << AON_IO_EXT_WAKEUP_STAT_STAT_POS));
883 }
884
885 /**
886 * @brief Clear the Event that triggered the DeepSleep WakeUp.
887 *
888 * Register|BitsName
889 * --------|--------
890 * AON_SLEEP_EVENT | AON_SLEEP_EVENT
891 *
892 * @param event This parameter can be a combination of the following values:
893 * @arg @ref LL_PWR_WKUP_EVENT_BLE
894 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
895 * @arg @ref LL_PWR_WKUP_EVENT_EXT
896 * @arg @ref LL_PWR_WKUP_EVENT_COMP_RISE
897 * @arg @ref LL_PWR_WKUP_EVENT_COMP_FALL
898 * @arg @ref LL_PWR_WKUP_EVENT_WDT
899 * @arg @ref LL_PWR_WKUP_EVENT_CLDR
900 * @retval None
901 */
902 __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
903 {
904 WRITE_REG(AON_CTL->AON_SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
905 }
906
907 /**
908 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
909 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
910 *
911 * Register|BitsName
912 * --------|--------
913 * COMM_CTRL | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT
914 *
915 * @retval State of bit (1 or 0).
916 */
917 __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
918 {
919 return (READ_BITS(AON_CTL->COMM_CTRL, AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_CTL_COMM_CTRL_DEEPSLCNTL_DEEP_SLEEP_STAT);
920 }
921
922 /**
923 * @brief Disable cache function
924 * @note The cache should be closed before chip go to deepsleep.
925 *
926 * Register|BitsName
927 * --------|--------
928 * CACHE.CTRL0 |EN
929 *
930 * @retval None
931 */
932 __STATIC_INLINE void ll_pwr_disable_cache_module(void)
933 {
934 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
935 __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
936 }
937
938 /**
939 * @brief Set DCDC prepare timing.
940 *
941 * Register|BitsName
942 * --------|--------
943 * AON_PWR | DCDC
944 *
945 * @param value setting value.
946 * @retval None
947 */
948 __STATIC_INLINE void ll_pwr_set_dcdc_prepare_timing(uint32_t value)
949 {
950 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DCDC, (value << AON_PWR_A_TIMING_CTRL0_DCDC_Pos));
951 }
952
953 /**
954 * @brief Set digtal LDO prepare timing.
955 *
956 * Register|BitsName
957 * --------|--------
958 * A_TIMING_CTRL0 | DIG_LDO
959 *
960 * @param value setting value.
961 * @retval None
962 */
963 __STATIC_INLINE void ll_pwr_set_dig_ldo_prepare_timing(uint32_t value)
964 {
965 MODIFY_REG(AON_PWR->A_TIMING_CTRL0, AON_PWR_A_TIMING_CTRL0_DIG_LDO, (value << AON_PWR_A_TIMING_CTRL0_DIG_LDO_Pos));
966 }
967
968
969 /**
970 * @brief Set fast LDO prepare timing.
971 *
972 * Register|BitsName
973 * --------|--------
974 * A_TIMING_CTRL1 | FAST_LDO
975 *
976 * @param value setting value.
977 * @retval None
978 */
979 __STATIC_INLINE void ll_pwr_set_fast_ldo_prepare_timing(uint32_t value)
980 {
981 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_FAST_LDO, (value << AON_PWR_A_TIMING_CTRL1_FAST_LDO_Pos));
982 }
983
984 /**
985 * @brief Set HF OSC prepare timing.
986 *
987 * Register|BitsName
988 * --------|--------
989 * A_TIMING_CTRL1 | HF_OSC
990 *
991 * @param value setting value.
992 * @retval None
993 */
994 __STATIC_INLINE void ll_pwr_set_hf_osc_prepare_timing(uint32_t value)
995 {
996 MODIFY_REG(AON_PWR->A_TIMING_CTRL1, AON_PWR_A_TIMING_CTRL1_HF_OSC, (value << AON_PWR_A_TIMING_CTRL1_HF_OSC_Pos));
997 }
998
999 /**
1000 * @brief Set PLL lock prepare timing.
1001 *
1002 * Register|BitsName
1003 * --------|--------
1004 * A_TIMING_CTRL2 | PLL_LOCK
1005 *
1006 * @param value setting value.
1007 * @retval None
1008 */
1009 __STATIC_INLINE void ll_pwr_set_pll_lock_timing(uint32_t value)
1010 {
1011 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL_LOCK, (value << AON_PWR_A_TIMING_CTRL2_PLL_LOCK_Pos));
1012 }
1013
1014 /**
1015 * @brief Set PLL prepare timing.
1016 *
1017 * Register|BitsName
1018 * --------|--------
1019 * A_TIMING_CTRL2 | PLL
1020 *
1021 * @param value setting value.
1022 * @retval None
1023 */
1024 __STATIC_INLINE void ll_pwr_set_pll_prepare_timing(uint32_t value)
1025 {
1026 MODIFY_REG(AON_PWR->A_TIMING_CTRL2, AON_PWR_A_TIMING_CTRL2_PLL, (value << AON_PWR_A_TIMING_CTRL2_PLL_Pos));
1027 }
1028
1029 /**
1030 * @brief Set power switch prepare timing.
1031 *
1032 * Register|BitsName
1033 * --------|--------
1034 * A_TIMING_CTRL3 | PWR_SWITCH
1035 *
1036 * @param value setting value.
1037 * @retval None
1038 */
1039 __STATIC_INLINE void ll_pwr_set_pwr_switch_prepare_timing(uint32_t value)
1040 {
1041 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_PWR_SWITCH, (value << AON_PWR_A_TIMING_CTRL3_PWR_SWITCH_Pos));
1042 }
1043
1044 /**
1045 * @brief Set Set XO prepare timing.
1046 *
1047 * Register|BitsName
1048 * --------|--------
1049 * A_TIMING_CTRL3 | CTRL3_XO
1050 *
1051 * @param value setting value.
1052 * @retval None
1053 */
1054 __STATIC_INLINE void ll_pwr_set_xo_prepare_timing(uint32_t value)
1055 {
1056 MODIFY_REG(AON_PWR->A_TIMING_CTRL3, AON_PWR_A_TIMING_CTRL3_XO, (value << AON_PWR_A_TIMING_CTRL3_XO_Pos));
1057 }
1058
1059 /**
1060 * @brief ll_pwr_set_pwr_mode
1061 *
1062 * Register|BitsName
1063 * --------|--------
1064 * AON_START_CFG | AON_PWR_AON_START_CFG_POWER_MODE
1065 *
1066 * @param value setting value.
1067 * @retval None
1068 */
1069 __STATIC_INLINE void ll_pwr_set_pwr_mode(uint32_t value)
1070 {
1071 MODIFY_REG(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_POWER_MODE,value << AON_PWR_AON_START_CFG_POWER_MODE_Pos);
1072 }
1073
1074
1075 /**
1076 * @brief Turn off enable xo/pll in warm boot.
1077 *
1078 * Register|BitsName
1079 * --------|--------
1080 * AON_START_CFG | AON_PWR_AON_START_CFG_XO_EN_PWR | AON_PWR_AON_START_CFG_PLL_EN_PWR
1081 *
1082 * @retval None
1083 */
1084 __STATIC_INLINE void ll_pwr_turn_off_enable_xo_pll_after_dcdc_ready(void)
1085 {
1086 CLEAR_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1087 }
1088
1089 /**
1090 * @brief Turn on enable xo/pll in srpg.
1091 *
1092 * Register|BitsName
1093 * --------|--------
1094 * AON_START_CFG | AON_PWR_AON_START_CFG_XO_EN_PWR | AON_PWR_AON_START_CFG_PLL_EN_PWR
1095 *
1096 * @retval None
1097 */
1098 __STATIC_INLINE void ll_pwr_turn_on_enable_xo_pll_after_dcdc_ready(void)
1099 {
1100 SET_BITS(AON_PWR->AON_START_CFG, AON_PWR_AON_START_CFG_XO_EN_PWR|AON_PWR_AON_START_CFG_PLL_EN_PWR);
1101 }
1102
1103 /**
1104 * @brief Set the AON IRQ Condition
1105 *
1106 * Register|BitsName
1107 * --------|--------
1108 * AON_IRQ_EN | AON_IRQ_EN
1109 *
1110 * @param condition This parameter can be one of the following values:
1111 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_PWR_ON
1112 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_PWR_DN
1113 * @arg @ref LL_PWR_AON_IRQ_EN_BOD_RISE
1114 * @arg @ref LL_PWR_AON_IRQ_EN_CPLL_DN
1115 * @arg @ref LL_PWR_AON_IRQ_EN_BOD_FALL
1116 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_MAC
1117 * @arg @ref LL_PWR_AON_IRQ_EN_SLP_FAIL
1118 * @arg @ref LL_PWR_AON_IRQ_EN_ALL
1119 * @retval None
1120 */
1121 __STATIC_INLINE void ll_pwr_enable_aon_irq(uint32_t condition)
1122 {
1123 SET_BITS(AON_CTL->AON_IRQ_EN, condition);
1124 }
1125
1126 /**
1127 * @brief clear the AON IRQ Condition
1128 *
1129 * Register|BitsName
1130 * --------|--------
1131 * AON_IRQ_EN | AON_IRQ_EN
1132 *
1133 * @param condition This parameter can be one of the following values:
1134 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_PWR_ON
1135 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_PWR_DN
1136 * @arg @ref LL_PWR_AON_IRQ_EN_BOD_RISE
1137 * @arg @ref LL_PWR_AON_IRQ_EN_CPLL_DN
1138 * @arg @ref LL_PWR_AON_IRQ_EN_BOD_FALL
1139 * @arg @ref LL_PWR_AON_IRQ_EN_BLE_MAC
1140 * @arg @ref LL_PWR_AON_IRQ_EN_SLP_FAIL
1141 * @arg @ref LL_PWR_AON_IRQ_EN_ALL
1142 * @retval None
1143 */
1144 __STATIC_INLINE void ll_pwr_disable_aon_irq(uint32_t condition)
1145 {
1146 CLEAR_BITS(AON_CTL->AON_IRQ_EN, condition);
1147 }
1148
1149 /**
1150 * @brief Clear the AON IRQ EVENT
1151 *
1152 * Register|BitsName
1153 * --------|--------
1154 * AON_IRQ | AON_IRQ
1155 *
1156 * @param condition This parameter can be one of the following values:
1157 * @arg @ref LL_PWR_AON_IRQ_EVT_BLE_PWR_ON
1158 * @arg @ref LL_PWR_AON_IRQ_EVT_BLE_PWR_DN
1159 * @arg @ref LL_PWR_AON_IRQ_EVT_BOD_RISE
1160 * @arg @ref LL_PWR_AON_IRQ_EVT_CPLL_DN
1161 * @arg @ref LL_PWR_AON_IRQ_EVT_BOD_FALL
1162 * @arg @ref LL_PWR_AON_IRQ_EVT_BLE_MAC
1163 * @arg @ref LL_PWR_AON_IRQ_EVT_SLP_FAIL
1164 * @arg @ref LL_PWR_AON_IRQ_EVT_ALL
1165 * @retval None
1166 */
1167 __STATIC_INLINE void ll_pwr_clear_aon_irq_event(uint32_t condition)
1168 {
1169 CLEAR_BITS(AON_CTL->AON_IRQ, condition);
1170 }
1171
1172
1173 /** @} */
1174
1175 /** @} */
1176
1177 #endif /* defined(AON) */
1178
1179 #ifdef __cplusplus
1180 }
1181 #endif
1182
1183 #endif /* __GR533x_LL_PWR_H__ */
1184
1185 /** @} */
1186
1187 /** @} */
1188
1189 /** @} */