gr533x_ll_aon_rf.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file gr533x_ll_aon_rf.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON RF LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_RF AON RF Module Driver
47 * @brief AON_RF LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533X_LL_AON_RF_H_
53 #define __GR533X_LL_AON_RF_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x_hal.h"
61
62 /** @defgroup AON_PMU_LL_DRIVER_FUNCTIONS Functions
63 * @{
64 */
65
66 /**
67 * @brief Enable the test mux 0 tri state
68 *
69 * Register|BitsName
70 * --------|--------
71 * RF5 | TEST_MUX_EN
72 *
73 */
74 __STATIC_INLINE void ll_aon_rf_enable_test_mux(void)
75 {
76 SET_BITS(AON_RF->RF5, AON_RF_RF5_TEST_MUX_EN);
77 }
78
79 /**
80 * @brief Disable the test mux 0 tri state
81 *
82 * Register|BitsName
83 * --------|--------
84 * RF5 | TEST_MUX_EN
85 *
86 */
87 __STATIC_INLINE void ll_aon_rf_disable_test_mux(void)
88 {
89 CLEAR_BITS(AON_RF->RF5, AON_RF_RF5_TEST_MUX_EN);
90 }
91
92 /**
93 * @brief Enable the cpll reset
94 *
95 * Register|BitsName
96 * --------|--------
97 * RF6 | CPLL_CP_EN
98 *
99 */
100 __STATIC_INLINE void ll_aon_rf_enable_cpll_cp_reset(void)
101 {
102 SET_BITS(AON_RF->RF6, AON_RF_RF6_CPLL_CP_EN);
103 }
104
105 /**
106 * @brief Disable the cpll reset
107 *
108 * Register|BitsName
109 * --------|--------
110 * RF6 | CPLL_CP_EN
111 *
112 */
113 __STATIC_INLINE void ll_aon_rf_disable_cpll_cp_reset(void)
114 {
115 CLEAR_BITS(AON_RF->RF6, AON_RF_RF6_CPLL_CP_EN);
116 }
117
118 /**
119 * @brief Enable the cpll drift detection
120 *
121 * Register|BitsName
122 * --------|--------
123 * RF6 | PLL_LOCK_DET_EN
124 *
125 */
126 __STATIC_INLINE void ll_aon_rf_enable_cpll_drift_detection(void)
127 {
128 SET_BITS(AON_RF->RF6, AON_RF_RF6_PLL_LOCK_DET_EN);
129 }
130
131 /**
132 * @brief Disable the cpll drift detection
133 *
134 * Register|BitsName
135 * --------|--------
136 * RF6 | PLL_LOCK_DET_EN
137 *
138 */
139 __STATIC_INLINE void ll_aon_rf_disable_cpll_drift_detection(void)
140 {
141 CLEAR_BITS(AON_RF->RF6, AON_RF_RF6_PLL_LOCK_DET_EN);
142 }
143
144 /**
145 * @brief Set the cpll m div,Pre division before CP (00- no division / 11 divide by 16).
146 *
147 * Register|BitsName
148 * --------|--------
149 * RF6 | CPLL_M_DIV_CTRL
150 *
151 * @param value: The cpll m div value.
152 *
153 */
154 __STATIC_INLINE void ll_aon_rf_set_cpll_m_div(uint32_t value)
155 {
156 MODIFY_REG(AON_RF->RF6, AON_RF_RF6_CPLL_M_DIV_CTRL, (value << AON_RF_RF6_CPLL_M_DIV_CTRL_Pos));
157 }
158
159 /**
160 * @brief Set the cpll drift detection.
161 *
162 * Register|BitsName
163 * --------|--------
164 * RF7 | L_H_THRESHOLD
165 *
166 * @param l_threshold: L Threshold.
167 * @param h_threshold: H Threshold.
168 *
169 */
170 __STATIC_INLINE void ll_aon_rf_set_threshold(uint32_t l_threshold, uint32_t h_threshold)
171 {
172 MODIFY_REG(AON_RF->RF7, AON_RF_RF7_L_H_THRESHOLD, (((h_threshold << 2) | l_threshold) << AON_RF_RF7_L_H_THRESHOLD_Pos));
173 }
174
175
176 /**
177 * @brief Set XO core current programmability.
178 *
179 * Register|BitsName
180 * --------|--------
181 * RF8 | XO_IBIAS_CTRL_4_0
182 *
183 * @param hi_value: hi value
184 * @param lo_value: lo value
185 * @retval None
186 *
187 */
188 __STATIC_INLINE void ll_aon_rf_set_xo_ibias(uint32_t hi_value,uint32_t lo_value)
189 {
190 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_BIAS_HI, (hi_value << AON_RF_XO_BIAS_HI_Pos));
191 MODIFY_REG(AON_RF->RF_XO_BIAS_VAL, AON_RF_XO_BIAS_LO, (lo_value << AON_RF_XO_BIAS_LO_Pos));
192 }
193
194 /**
195 * @brief Set the RF_REG9
196 *
197 * Register|BitsName
198 * --------|--------
199 * RF9 | ALL
200 *
201 * @param value: The RF_REG9 value.
202 *
203 */
204 __STATIC_INLINE void ll_aon_rf_set_rf_reg9(uint32_t value)
205 {
206 WRITE_REG(AON_RF->RF9, value);
207 }
208
209 /**
210 * @brief Get the RF_REG9
211 *
212 * Register|BitsName
213 * --------|--------
214 * RF9 | ALL
215 *
216 * @retval The RF_REG9 value.
217 *
218 */
219 __STATIC_INLINE uint32_t ll_aon_rf_get_rf_reg9(void)
220 {
221 return READ_REG(AON_RF->RF9);
222 }
223
224
225 /**
226 * @brief Set the xo cap value,cload programmability from 50fF to 26pF on each side.
227 *
228 * Register|BitsName
229 * --------|--------
230 * RF9 | XO_CAP
231 *
232 * @param value: The xo cap value.
233 *
234 */
235 __STATIC_INLINE void ll_aon_rf_set_xo_cap(uint32_t value)
236 {
237 MODIFY_REG(AON_RF->RF9, AON_RF_RF9_XO_CAP_CTRL, (value << AON_RF_RF9_XO_CAP_CTRL_Pos));
238 }
239
240 /**
241 * @brief Get the cpll crscde
242 *
243 * Register|BitsName
244 * --------|--------
245 * RF_RD_REG_0 | CPLL_CRSCDE
246 *
247 * @retval cpll crscde.
248 *
249 */
250 __STATIC_INLINE uint32_t ll_aon_rf_get_cpll_crscde(void)
251 {
252 return (READ_BITS(AON_RF->RF_RD_REG_0, AON_RF_RF_RD_REG_0_CPLL_CRSCDE) >> AON_RF_RF_RD_REG_0_CPLL_CRSCDE_Pos);
253 }
254 /**
255 * @brief Set SU enable.
256 *
257 * Register|BitsName
258 * --------|--------
259 * RF8 | SU_ENABLE
260 *
261 *
262 */
263 __STATIC_INLINE void ll_aon_rf_set_su_enable(void)
264 {
265 SET_BITS(AON_RF->RF8, AON_RF_RF8_SU_EN | AON_RF_RF8_SU_NOISE_VCO_EN | AON_RF_RF8_SU_GM_IBOOT_EN);
266 }
267 /**
268 * @brief Set cpll drift irq enable.
269 *
270 * Register|BitsName
271 * --------|--------
272 * CPLL_IRQ_CFG | MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN
273 *
274 *
275 */
276 __STATIC_INLINE void ll_mcu_set_cpll_drift_irq_enable(void)
277 {
278 SET_BITS(MCU_SUB->CPLL_IRQ_CFG, MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN);
279 }
280 /**
281 * @brief Set cpll drift irq disable.
282 *
283 * Register|BitsName
284 * --------|--------
285 * CPLL_IRQ_CFG | MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN
286 *
287 *
288 */
289 __STATIC_INLINE void ll_mcu_set_cpll_drift_irq_disable(void)
290 {
291 CLEAR_BITS(MCU_SUB->CPLL_IRQ_CFG, MCU_SUB_CPLL_IRQ_CFG_DRIFT_IRQ_EN);
292 }
293
294 /** @} */
295 #ifdef __cplusplus
296 }
297 #endif
298
299 #endif
300
301 /** @} */
302 /** @} */
303 /** @} */
304
ll_aon_rf_enable_test_mux
__STATIC_INLINE void ll_aon_rf_enable_test_mux(void)
Enable the test mux 0 tri state.
Definition: gr533x_ll_aon_rf.h:74
ll_aon_rf_set_rf_reg9
__STATIC_INLINE void ll_aon_rf_set_rf_reg9(uint32_t value)
Set the RF_REG9.
Definition: gr533x_ll_aon_rf.h:204
ll_aon_rf_enable_cpll_drift_detection
__STATIC_INLINE void ll_aon_rf_enable_cpll_drift_detection(void)
Enable the cpll drift detection.
Definition: gr533x_ll_aon_rf.h:126
ll_mcu_set_cpll_drift_irq_disable
__STATIC_INLINE void ll_mcu_set_cpll_drift_irq_disable(void)
Set cpll drift irq disable.
Definition: gr533x_ll_aon_rf.h:289
ll_aon_rf_disable_test_mux
__STATIC_INLINE void ll_aon_rf_disable_test_mux(void)
Disable the test mux 0 tri state.
Definition: gr533x_ll_aon_rf.h:87
ll_aon_rf_enable_cpll_cp_reset
__STATIC_INLINE void ll_aon_rf_enable_cpll_cp_reset(void)
Enable the cpll reset.
Definition: gr533x_ll_aon_rf.h:100
ll_aon_rf_set_xo_ibias
__STATIC_INLINE void ll_aon_rf_set_xo_ibias(uint32_t hi_value, uint32_t lo_value)
Set XO core current programmability.
Definition: gr533x_ll_aon_rf.h:188
ll_aon_rf_set_cpll_m_div
__STATIC_INLINE void ll_aon_rf_set_cpll_m_div(uint32_t value)
Set the cpll m div,Pre division before CP (00- no division / 11 divide by 16).
Definition: gr533x_ll_aon_rf.h:154
ll_aon_rf_get_cpll_crscde
__STATIC_INLINE uint32_t ll_aon_rf_get_cpll_crscde(void)
Get the cpll crscde.
Definition: gr533x_ll_aon_rf.h:250
ll_aon_rf_set_su_enable
__STATIC_INLINE void ll_aon_rf_set_su_enable(void)
Set SU enable.
Definition: gr533x_ll_aon_rf.h:263
ll_aon_rf_disable_cpll_drift_detection
__STATIC_INLINE void ll_aon_rf_disable_cpll_drift_detection(void)
Disable the cpll drift detection.
Definition: gr533x_ll_aon_rf.h:139
ll_aon_rf_set_threshold
__STATIC_INLINE void ll_aon_rf_set_threshold(uint32_t l_threshold, uint32_t h_threshold)
Set the cpll drift detection.
Definition: gr533x_ll_aon_rf.h:170
ll_aon_rf_get_rf_reg9
__STATIC_INLINE uint32_t ll_aon_rf_get_rf_reg9(void)
Get the RF_REG9.
Definition: gr533x_ll_aon_rf.h:219
gr533x_hal.h
This file contains all the functions prototypes for the HAL module driver.
ll_aon_rf_set_xo_cap
__STATIC_INLINE void ll_aon_rf_set_xo_cap(uint32_t value)
Set the xo cap value,cload programmability from 50fF to 26pF on each side.
Definition: gr533x_ll_aon_rf.h:235
ll_mcu_set_cpll_drift_irq_enable
__STATIC_INLINE void ll_mcu_set_cpll_drift_irq_enable(void)
Set cpll drift irq enable.
Definition: gr533x_ll_aon_rf.h:276
ll_aon_rf_disable_cpll_cp_reset
__STATIC_INLINE void ll_aon_rf_disable_cpll_cp_reset(void)
Disable the cpll reset.
Definition: gr533x_ll_aon_rf.h:113