ll_aes.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_aes.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AES LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AES AES
47 * @brief AES LL module driver.
48 * @{
49 */
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR5XX_LL_AES_H__
52 #define __GR5XX_LL_AES_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "gr5x.h"
60
61 #if defined (AES)
62
63 /** @defgroup AES_LL_STRUCTURES Structures
64 * @{
65 */
66
67 /* Exported types ------------------------------------------------------------*/
68 /** @defgroup AES_LL_ES_INIT AES Exported Init structures
69 * @{
70 */
71
72 /**
73 * @brief LL AES Init Structure definition
74 */
75 typedef struct _ll_aes_init
76 {
77 uint32_t key_size; /**< 128, 192 or 256-bit key length.
78 This parameter can be a value of @ref AES_LL_EC_KEY_SIZE */
79
80 uint32_t *p_key; /**< Encryption/Decryption Key */
81
82 uint32_t *p_init_vector; /**< Initialization Vector used for CBC modes */
83
84 uint32_t *p_seed; /**< Random seeds */
85
86 } ll_aes_init_t;
87
88 /** @} */
89
90 /** @} */
91
92 /**
93 * @defgroup AES_LL_MACRO Defines
94 * @{
95 */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup AES_LL_Exported_Constants AES Exported Constants
99 * @{
100 */
101
102 /** @defgroup AES_LL_EC_GET_FLAG Get Flag Defines
103 * @brief Flag definitions which can be used with LL_AES_ReadReg function
104 * @{
105 */
106 #define LL_AES_FLAG_DATAREADY AES_STAT_READY /**< AES result data out ready */
107 #define LL_AES_FLAG_DMA_DONE AES_STAT_DMA_XFE_CPLT /**< AES dma transfer done */
108 #define LL_AES_FLAG_DMA_ERR AES_STAT_DMA_XFE_ERR /**< AES dma transfer error */
109 #define LL_AES_FLAG_KEY_VALID AES_STAT_KEY_STAT /**< AES has fetched key */
110 /** @} */
111
112 /** @defgroup AES_LL_EC_KEY_SIZE Key Size
113 * @{
114 */
115 #define LL_AES_KEY_SIZE_128 0x00000000U /**< 128 bits */
116 #define LL_AES_KEY_SIZE_192 (1UL << AES_CFG_KEY_MODE_POS) /**< 192 bits */
117 #define LL_AES_KEY_SIZE_256 (2UL << AES_CFG_KEY_MODE_POS) /**< 256 bits */
118 /** @} */
119
120 /** @defgroup AES_LL_EC_OPERATION_MODE Operation Mode
121 * @{
122 */
123 #define LL_AES_OPERATION_MODE_ECB 0x00000000U /**< Electronic codebook (ECB) mode */
124 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CFG_OPT_MODE_POS) /**< Cipher block chaining (CBC) mode */
125 /** @} */
126
127 /** @defgroup AES_LL_EC_KEY_TYPE Key Type
128 * @{
129 */
130 #define LL_AES_KEYTYPE_MCU 0x00000000U /**< MCU */
131 #define LL_AES_KEYTYPE_AHB (1UL << AES_CFG_KEY_TYPE_POS) /**< AHB master */
132 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CFG_KEY_TYPE_POS) /**< Key Port */
133 /** @} */
134
135 /** @defgroup AES_LL_EC_KEY_MODE Key Mode
136 * @{
137 */
138 #define LL_AES_KEYMODE_NORMAL 0x00000000U /**< Normal Key mode */
139 #define LL_AES_KEYMODE_KEYWRAP (1UL << AES_CFG_KEY_WRAP_POS) /**< Key Wrapping mode */
140 /** @} */
141
142 /** @defgroup AES_LL_EC_TRANSFER_SIZE Transfer Size
143 * @{
144 */
145 #define LL_AES_DMA_TRANSIZE_MIN (1) /**< Min size = 1 block */
146 #define LL_AES_DMA_TRANSIZE_MAX (2048) /**< Max size = 2048 blocks */
147 /** @} */
148
149 /** @defgroup AES_LL_EC_KEYRAM_KEYSLOT Keyram keyslot
150 * @{
151 */
152 #define LL_AES_KEYRAM_KEYSLOT_0 ((uint32_t)0x00000000U) /**< KEYRAM KEYSLOT 0 */
153 #define LL_AES_KEYRAM_KEYSLOT_1 ((uint32_t)0x00000010U) /**< KEYRAM KEYSLOT 1 */
154 #define LL_AES_KEYRAM_KEYSLOT_2 ((uint32_t)0x00000020U) /**< KEYRAM KEYSLOT 2 */
155 #define LL_AES_KEYRAM_KEYSLOT_3 ((uint32_t)0x00000030U) /**< KEYRAM KEYSLOT 3 */
156 #define LL_AES_KEYRAM_KEYSLOT_4 ((uint32_t)0x00000040U) /**< KEYRAM KEYSLOT 4 */
157 #define LL_AES_KEYRAM_KEYSLOT_5 ((uint32_t)0x00000050U) /**< KEYRAM KEYSLOT 5 */
158 #define LL_AES_KEYRAM_KEYSLOT_6 ((uint32_t)0x00000060U) /**< KEYRAM KEYSLOT 6 */
159 #define LL_AES_KEYRAM_KEYSLOT_7 ((uint32_t)0x00000070U) /**< KEYRAM KEYSLOT 7 */
160 #define LL_AES_KEYRAM_KEYSLOT_8 ((uint32_t)0x00000080U) /**< KEYRAM KEYSLOT 8 */
161 #define LL_AES_KEYRAM_KEYSLOT_9 ((uint32_t)0x00000090U) /**< KEYRAM KEYSLOT 9 */
162 #define LL_AES_KEYRAM_KEYSLOT_10 ((uint32_t)0x000000A0U) /**< KEYRAM KEYSLOT 10 */
163 #define LL_AES_KEYRAM_KEYSLOT_11 ((uint32_t)0x000000B0U) /**< KEYRAM KEYSLOT 11 */
164 #define LL_AES_KEYRAM_KEYSLOT_12 ((uint32_t)0x000000C0U) /**< KEYRAM KEYSLOT 12 */
165 #define LL_AES_KEYRAM_KEYSLOT_13 ((uint32_t)0x000000D0U) /**< KEYRAM KEYSLOT 13 */
166 #define LL_AES_KEYRAM_KEYSLOT_14 ((uint32_t)0x000000E0U) /**< KEYRAM KEYSLOT 14 */
167 #define LL_AES_KEYRAM_KEYSLOT_15 ((uint32_t)0x000000F0U) /**< KEYRAM KEYSLOT 15 */
168 /** @} */
169
170 /** @} */
171
172 /* Exported macro ------------------------------------------------------------*/
173 /** @defgroup AES_LL_Exported_Macros AES Exported Macros
174 * @{
175 */
176
177 /** @defgroup AES_LL_EM_WRITE_READ Common Write and read registers Macros
178 * @{
179 */
180
181 /**
182 * @brief Write a value in AES register
183 * @param __INSTANCE__ AES Instance
184 * @param __REG__ Register to be written
185 * @param __VALUE__ Value to be written in the register
186 * @retval None
187 */
188 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
189
190 /**
191 * @brief Read a value in AES register
192 * @param __INSTANCE__ AES Instance
193 * @param __REG__ Register to be read
194 * @retval Register value
195 */
196 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
197
198 /** @} */
199
200 /** @} */
201
202 /** @} */
203
204 /* Exported functions --------------------------------------------------------*/
205 /** @defgroup AES_LL_DRIVER_FUNCTIONS Functions
206 * @{
207 */
208
209 /** @defgroup AES_LL_EF_Configuration Configuration functions
210 * @{
211 */
212
213 /**
214 * @brief Enable AES.
215 *
216 * Register|BitsName
217 * ---------------|---------------
218 * CTRL | MODULE_EN
219 *
220 * @param AESx AES instance
221 * @retval None
222 */
223 __STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
224 {
225 SET_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
226 }
227
228 /**
229 * @brief Disable AES.
230 *
231 * Register|BitsName
232 * ---------------|---------------
233 * CTRL | MODULE_EN
234 *
235 * @param AESx AES instance
236 * @retval None
237 */
238 __STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
239 {
240 CLEAR_BITS(AESx->CTRL, AES_CTRL_MODULE_EN);
241 }
242
243 /**
244 * @brief Indicate whether the AES is enabled.
245 *
246 * Register|BitsName
247 * ---------------|---------------
248 * CTRL | MODULE_EN
249 *
250 * @param AESx AES instance
251 * @retval State of bit (1 or 0).
252 */
253 __STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
254 {
255 return (READ_BITS(AESx->CTRL, AES_CTRL_MODULE_EN) == (AES_CTRL_MODULE_EN));
256 }
257
258 /**
259 * @brief Enable AES start in MCU mode.
260 *
261 * Register|BitsName
262 * ---------------|---------------
263 * CTRL | MCU_MODE_EN
264 *
265 * @param AESx AES instance
266 * @retval None
267 */
268 __STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
269 {
270 SET_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
271 }
272
273 /**
274 * @brief Disable AES start in MCU mode.
275 *
276 * Register|BitsName
277 * ---------------|---------------
278 * CTRL | MCU_MODE_EN
279 *
280 * @param AESx AES instance
281 * @retval None
282 */
283 __STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
284 {
285 CLEAR_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN);
286 }
287
288 /**
289 * @brief Indicate whether the AES start in MCU mode is enabled.
290 *
291 * Register|BitsName
292 * ---------------|---------------
293 * CTRL | MCU_MODE_EN
294 *
295 * @param AESx AES instance
296 * @retval State of bit (1 or 0).
297 */
298 __STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
299 {
300 return (READ_BITS(AESx->CTRL, AES_CTRL_MCU_MODE_EN) == (AES_CTRL_MCU_MODE_EN));
301 }
302
303 /**
304 * @brief Enable AES DMA mode.
305 *
306 * Register|BitsName
307 * ---------------|---------------
308 * CTRL | DMA_MODE_EN
309 *
310 * @param AESx AES instance
311 * @retval None
312 */
313 __STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
314 {
315 SET_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
316 }
317
318 /**
319 * @brief Disable AES DMA mode.
320 *
321 * Register|BitsName
322 * ---------------|---------------
323 * CTRL | DMA_MODE_EN
324 *
325 * @param AESx AES instance
326 * @retval None
327 */
328 __STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
329 {
330 CLEAR_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN);
331 }
332
333 /**
334 * @brief Indicate whether the AES DMA mode is enabled.
335 *
336 * Register|BitsName
337 * ---------------|---------------
338 * CTRL | DMA_MODE_EN
339 *
340 * @param AESx AES instance
341 * @retval State of bit (1 or 0).
342 */
343 __STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
344 {
345 return (READ_BITS(AESx->CTRL, AES_CTRL_DMA_MODE_EN) == (AES_CTRL_DMA_MODE_EN));
346 }
347
348 /**
349 * @brief Enable fetch key through AHB/key port.
350 *
351 * Register|BitsName
352 * ---------------|---------------
353 * CTRL | FKEY_EN
354 *
355 * @param AESx AES instance
356 * @retval None
357 */
358 __STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
359 {
360 SET_BITS(AESx->CTRL, AES_CTRL_FKEY_EN);
361 }
362
363 /**
364 * @brief Set AES key size.
365 *
366 * Register|BitsName
367 * ---------------|---------------
368 * CFG | KEY_MODE
369 *
370 * @param AESx AES instance
371 * @param size This parameter can be one of the following values:
372 * @arg @ref LL_AES_KEY_SIZE_128
373 * @arg @ref LL_AES_KEY_SIZE_192
374 * @arg @ref LL_AES_KEY_SIZE_256
375 * @retval None
376 */
377 __STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
378 {
379 MODIFY_REG(AESx->CFG, AES_CFG_KEY_MODE, size);
380 }
381
382 /**
383 * @brief Get AES key size.
384 *
385 * Register|BitsName
386 * ---------------|---------------
387 * CFG | KEY_MODE
388 *
389 * @param AESx AES instance
390 * @retval Returned value can be one of the following values:
391 * @arg @ref LL_AES_KEY_SIZE_128
392 * @arg @ref LL_AES_KEY_SIZE_192
393 * @arg @ref LL_AES_KEY_SIZE_256
394 */
395 __STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
396 {
397 return (READ_BITS(AESx->CFG, AES_CFG_KEY_MODE));
398 }
399
400 /**
401 * @brief Enable AES full mask.
402 *
403 * Register|BitsName
404 * ---------------|---------------
405 * CFG | FULL_MASK_EN
406 *
407 * @param AESx AES instance
408 * @retval None
409 */
410 __STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
411 {
412 SET_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
413 }
414
415 /**
416 * @brief Disable AES full mask.
417 *
418 * Register|BitsName
419 * ---------------|---------------
420 * CFG | FULL_MASK_EN
421 *
422 * @param AESx AES instance
423 * @retval None
424 */
425 __STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
426 {
427 CLEAR_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN);
428 }
429
430 /**
431 * @brief Indicate whether the AES full mask is enabled.
432 *
433 * Register|BitsName
434 * ---------------|---------------
435 * CFG | FULL_MASK_EN
436 *
437 * @param AESx AES instance
438 * @retval State of bit (1 or 0).
439 */
440 __STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
441 {
442 return (READ_BITS(AESx->CFG, AES_CFG_FULL_MASK_EN) == (AES_CFG_FULL_MASK_EN));
443 }
444
445 /**
446 * @brief Enable AES encryption mode.
447 *
448 * Register|BitsName
449 * ---------------|---------------
450 * CFG | DEC_ENC_SEL
451 *
452 * @param AESx AES instance
453 * @retval None
454 */
455 __STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
456 {
457 SET_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
458 }
459
460 /**
461 * @brief Disable AES encryption mode.
462 *
463 * Register|BitsName
464 * ---------------|---------------
465 * CFG | DEC_ENC_SEL
466 *
467 * @param AESx AES instance
468 * @retval None
469 */
470 __STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
471 {
472 CLEAR_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL);
473 }
474
475 /**
476 * @brief Indicate whether the AES encryption mode is enabled.
477 *
478 * Register|BitsName
479 * ---------------|---------------
480 * CFG | DEC_ENC_SEL
481 *
482 * @param AESx AES instance
483 * @retval State of bit (1 or 0).
484 */
485 __STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
486 {
487 return (READ_BITS(AESx->CFG, AES_CFG_DEC_ENC_SEL) == (AES_CFG_DEC_ENC_SEL));
488 }
489
490 /**
491 * @brief Set AES to load seed for LFSR.
492 *
493 * Register|BitsName
494 * ---------------|---------------
495 * CFG | LOAD_SEED
496 *
497 * @param AESx AES instance
498 * @retval None
499 */
500 __STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
501 {
502 SET_BITS(AESx->CFG, AES_CFG_LOAD_SEED);
503 }
504
505 /**
506 * @brief Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
507 *
508 * Register|BitsName
509 * ---------------|---------------
510 * CFG | FIRST_BLK
511 *
512 * @param AESx AES instance
513 * @retval None
514 */
515 __STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
516 {
517 SET_BITS(AESx->CFG, AES_CFG_FIRST_BLK);
518 }
519
520 /**
521 * @brief Enable AES in little endian.
522 *
523 * Register|BitsName
524 * ---------------|---------------
525 * CFG | ENDIAN
526 *
527 * @param AESx AES instance
528 * @retval None
529 */
530 __STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
531 {
532 SET_BITS(AESx->CFG, AES_CFG_ENDIAN);
533 }
534
535 /**
536 * @brief Disable AES in little endian.
537 *
538 * Register|BitsName
539 * ---------------|---------------
540 * CFG | ENDIAN
541 *
542 * @param AESx AES instance
543 * @retval None
544 */
545 __STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
546 {
547 CLEAR_BITS(AESx->CFG, AES_CFG_ENDIAN);
548 }
549
550 /**
551 * @brief Indicate whether the AES is in little endian.
552 *
553 * Register|BitsName
554 * ---------------|---------------
555 * CFG | ENDIAN
556 *
557 * @param AESx AES instance
558 * @retval State of bit (1 or 0).
559 */
560 __STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
561 {
562 return (READ_BITS(AESx->CFG, AES_CFG_ENDIAN) == (AES_CFG_ENDIAN));
563 }
564
565 /**
566 * @brief Set AES operation mode.
567 *
568 * Register|BitsName
569 * ---------------|---------------
570 * CFG | OPT_MODE
571 *
572 * @param AESx AES instance
573 * @param mode This parameter can be one of the following values:
574 * @arg @ref LL_AES_OPERATION_MODE_ECB
575 * @arg @ref LL_AES_OPERATION_MODE_CBC
576 * @retval None
577 */
578 __STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
579 {
580 MODIFY_REG(AESx->CFG, AES_CFG_OPT_MODE, mode);
581 }
582
583 /**
584 * @brief Get AES operation mode.
585 *
586 * Register|BitsName
587 * ---------------|---------------
588 * CFG | OPT_MODE
589 *
590 * @param AESx AES instance
591 * @retval Returned value can be one of the following values:
592 * @arg @ref LL_AES_OPERATION_MODE_ECB
593 * @arg @ref LL_AES_OPERATION_MODE_CBC
594 */
595 __STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
596 {
597 return (READ_BITS(AESx->CFG, AES_CFG_OPT_MODE));
598 }
599
600 /**
601 * @brief Set ways to obtain AES key.
602 *
603 * Register|BitsName
604 * ---------------|---------------
605 * CFG | KEY_TYPE
606 *
607 * @param AESx AES instance
608 * @param Type This parameter can be one of the following values:
609 * @arg @ref LL_AES_KEYTYPE_MCU
610 * @arg @ref LL_AES_KEYTYPE_AHB
611 * @arg @ref LL_AES_KEYTYPE_KRAM
612 * @retval None
613 */
614 __STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
615 {
616 MODIFY_REG(AESx->CFG, AES_CFG_KEY_TYPE, Type);
617 }
618
619 /**
620 * @brief Get ways to obtain AES key.
621 *
622 * Register|BitsName
623 * ---------------|---------------
624 * CFG | KEY_TYPE
625 *
626 * @param AESx AES instance
627 * @retval Returned value can be one of the following values:
628 * @arg @ref LL_AES_KEYTYPE_MCU
629 * @arg @ref LL_AES_KEYTYPE_AHB
630 * @arg @ref LL_AES_KEYTYPE_KRAM
631 */
632 __STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
633 {
634 return (READ_BITS(AESx->CFG, AES_CFG_KEY_TYPE));
635 }
636
637 /**
638 * @brief Set AES key mode.
639 *
640 * Register|BitsName
641 * ---------------|---------------
642 * CFG | KEY_WRAP
643 *
644 * @param AESx AES instance
645 * @param mode This parameter can be one of the following values:
646 * @arg @ref LL_AES_KEYMODE_NORMAL
647 * @arg @ref LL_AES_KEYMODE_KEYWRAP
648 * @retval None
649 */
650 __STATIC_INLINE void ll_aes_set_key_mode(aes_regs_t *AESx, uint32_t mode)
651 {
652 MODIFY_REG(AESx->CFG, AES_CFG_KEY_WRAP, mode);
653 }
654
655 /**
656 * @brief Get AES key mode.
657 *
658 * Register|BitsName
659 * ---------------|---------------
660 * CFG | KEY_WRAP
661 *
662 * @param AESx AES instance
663 * @retval Returned value can be one of the following values:
664 * @arg @ref LL_AES_KEYMODE_NORMAL
665 * @arg @ref LL_AES_KEYMODE_KEYWRAP
666 */
667 __STATIC_INLINE uint32_t ll_aes_get_key_mode(aes_regs_t *AESx)
668 {
669 return (READ_BITS(AESx->CFG, AES_CFG_KEY_WRAP));
670 }
671
672 /** @} */
673
674 /** @defgroup AES_LL_EF_IT_Management IT_Management
675 * @{
676 */
677
678 /**
679 * @brief Enable AES the done interrupt.
680 *
681 * Register|BitsName
682 * ---------------|---------------
683 * INT | CPLT_INT_EN
684 *
685 * @param AESx AES instance
686 * @retval None
687 */
688 __STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
689 {
690 SET_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
691 }
692
693 /**
694 * @brief Disable AES the done interrupt.
695 *
696 * Register|BitsName
697 * ---------------|---------------
698 * INT | CPLT_INT_EN
699 *
700 * @param AESx AES instance
701 * @retval None
702 */
703 __STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
704 {
705 CLEAR_BITS(AESx->INT, AES_INT_CPLT_INT_EN);
706 }
707
708 /**
709 * @brief Indicate whether the done interrupt is enabled.
710 *
711 * Register|BitsName
712 * ---------------|---------------
713 * INT | CPLT_INT_EN
714 *
715 * @param AESx AES instance
716 * @retval State of bit (1 or 0).
717 */
718 __STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
719 {
720 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_EN) == (AES_INT_CPLT_INT_EN));
721 }
722
723 /** @} */
724
725 /** @defgroup AES_LL_EF_FLAG_Management FLAG_Management
726 * @{
727 */
728
729 /**
730 * @brief Indicate whether the ready flag is set.
731 *
732 * Register|BitsName
733 * ---------------|---------------
734 * STAT | READY
735 *
736 * @param AESx AES instance
737 * @retval State of bit (1 or 0).
738 */
739 __STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
740 {
741 return (READ_BITS(AESx->STAT, AES_STAT_READY) == AES_STAT_READY);
742 }
743
744 /**
745 * @brief Indicate whether the DMA transfer done flag is set.
746 *
747 * Register|BitsName
748 * ---------------|---------------
749 * STAT | DMA_XFE_CPLT
750 *
751 * @param AESx AES instance
752 * @retval State of bit (1 or 0).
753 */
754 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
755 {
756 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_CPLT) == AES_STAT_DMA_XFE_CPLT);
757 }
758
759 /**
760 * @brief Indicate whether the DMA transfer error flag is set.
761 *
762 * Register|BitsName
763 * ---------------|---------------
764 * STAT | DMA_XFE_ERR
765 *
766 * @param AESx AES instance
767 * @retval State of bit (1 or 0).
768 */
769 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
770 {
771 return (READ_BITS(AESx->STAT, AES_STAT_DMA_XFE_ERR) == AES_STAT_DMA_XFE_ERR);
772 }
773
774 /**
775 * @brief Indicate whether the key valid flag is set.
776 *
777 * Register|BitsName
778 * ---------------|---------------
779 * STAT | KEY_STAT
780 *
781 * @param AESx AES instance
782 * @retval State of bit (1 or 0).
783 */
784 __STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
785 {
786 return (READ_BITS(AESx->STAT, AES_STAT_KEY_STAT) == AES_STAT_KEY_STAT);
787 }
788
789 /**
790 * @brief Indicate whether the done interrupt flag is set.
791 *
792 * Register|BitsName
793 * ---------------|---------------
794 * INT | CPLT_INT_FLAG
795 *
796 * @param AESx AES instance
797 * @retval State of bit (1 or 0).
798 */
799 __STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
800 {
801 return (READ_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG) == AES_INT_CPLT_INT_FLAG);
802 }
803
804 /**
805 * @brief Clear the done interrupt flag.
806 *
807 * Register|BitsName
808 * ---------------|---------------
809 * INT | CPLT_INT_FLAG
810 *
811 * @param AESx AES instance
812 * @retval None
813 */
814 __STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
815 {
816 SET_BITS(AESx->INT, AES_INT_CPLT_INT_FLAG);
817 }
818
819 /** @} */
820
821 /** @defgroup AES_LL_EF_DMA_Management DMA_Management
822 * @{
823 */
824
825 /**
826 * @brief Set AES transfer blocks in DMA mode.
827 *
828 * Register|BitsName
829 * ---------------|---------------
830 * XFE_SIZE | SIZE
831 *
832 * @param AESx AES instance
833 * @param block This parameter can be one of the following values: 1 ~ 2048.
834 * @retval None
835 */
836 __STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
837 {
838 MODIFY_REG(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE, (block << 4) - 1);
839 }
840
841 /**
842 * @brief Get AES transfer blocks in DMA mode.
843 *
844 * Register|BitsName
845 * ---------------|---------------
846 * XFE_SIZE | SIZE
847 *
848 * @param AESx AES instance
849 * @retval Return value between 1 and 2048.
850 */
851 __STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
852 {
853 return ((READ_BITS(AESx->XFE_SIZE, AES_XFE_SIZE_SIZE) + 1) >> 4);
854 }
855
856 /**
857 * @brief Set AES read address of RAM in DMA mode.
858 * @note This read address of RAM requires 4 byte alignment.
859 *
860 * Register|BitsName
861 * ---------------|---------------
862 * RD_START_ADDR | ADDR
863 *
864 * @param AESx AES instance
865 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
866 * @retval None
867 */
868 __STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
869 {
870 WRITE_REG(AESx->RD_START_ADDR, address);
871 }
872
873 /**
874 * @brief Get AES read address of RAM in DMA mode.
875 *
876 * Register|BitsName
877 * ---------------|---------------
878 * RD_START_ADDR | ADDR
879 *
880 * @param AESx AES instance
881 * @retval Returned value is the read address in RAM.
882 */
883 __STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
884 {
885 return (READ_REG(AESx->RD_START_ADDR));
886 }
887
888 /**
889 * @brief Set AES write address of RAM in DMA mode.
890 * @note This write address of RAM requires 4 byte alignment.
891 *
892 * Register|BitsName
893 * ---------------|---------------
894 * WR_START_ADDR | ADDR
895 *
896 * @param AESx AES instance
897 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
898 * @retval None
899 */
900 __STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
901 {
902 WRITE_REG(AESx->WR_START_ADDR, address);
903 }
904
905 /**
906 * @brief Get AES write address of RAM in DMA mode.
907 *
908 * Register|BitsName
909 * ---------------|---------------
910 * WR_START_ADDR | ADDR
911 *
912 * @param AESx AES instance
913 * @retval Returned value is the wrute address in RAM
914 */
915 __STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
916 {
917 return (READ_REG(AESx->WR_START_ADDR));
918 }
919
920 /** @} */
921
922 /** @defgroup AES_LL_EF_Data_Management Data_Management
923 * @{
924 */
925
926 /**
927 * @brief Set AES key address in memory.
928 *
929 * Register|BitsName
930 * ---------------|---------------
931 * KEY_ADDR | ADDR
932 *
933 * @param AESx AES instance
934 * @param address This parameter can be one of the address in RAM
935 * @retval None
936 */
937 __STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
938 {
939 WRITE_REG(AESx->KEY_ADDR, address);
940 }
941
942 /**
943 * @brief Get AES key address in memory.
944 *
945 * Register|BitsName
946 * ---------------|---------------
947 * KEY_ADDR | ADDR
948 *
949 * @param AESx AES instance
950 * @retval Returned value is the key address in RAM.
951 */
952 __STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
953 {
954 return (READ_REG(AESx->KEY_ADDR));
955 }
956
957 /**
958 * @brief Get AES output data[127:96].
959 *
960 * Register|BitsName
961 * ---------------|---------------
962 * DATA_OUT0 | DATA
963 *
964 * @param AESx AES instance
965 * @retval Output Data[127:96]
966 */
967 __STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
968 {
969 return (READ_REG(AESx->DATA_OUT0));
970 }
971
972 /**
973 * @brief Get AES output data[95:64].
974 *
975 * Register|BitsName
976 * ---------------|---------------
977 * DATA_OUT1 | DATA
978 *
979 * @param AESx AES instance
980 * @retval Output Data[95:64]
981 */
982 __STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
983 {
984 return (READ_REG(AESx->DATA_OUT1));
985 }
986
987 /**
988 * @brief Get AES output data[63:32].
989 *
990 * Register|BitsName
991 * ---------------|---------------
992 * DATA_OUT2 | DATA
993 *
994 * @param AESx AES instance
995 * @retval Output Data[63:32]
996 */
997 __STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
998 {
999 return (READ_REG(AESx->DATA_OUT2));
1000 }
1001
1002 /**
1003 * @brief Get AES output data[31:0].
1004 *
1005 * Register|BitsName
1006 * ---------------|---------------
1007 * DATA_OUT3 | DATA
1008 *
1009 * @param AESx AES instance
1010 * @retval Output Data[31:0]
1011 */
1012 __STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
1013 {
1014 return (READ_REG(AESx->DATA_OUT3));
1015 }
1016
1017 /**
1018 * @brief Set AES key[255:224].
1019 *
1020 * Register|BitsName
1021 * ---------------|---------------
1022 * KEY0 | KEY
1023 *
1024 * @param AESx AES instance
1025 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1026 * @retval None
1027 */
1028 __STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
1029 {
1030 WRITE_REG(AESx->KEY0, key);
1031 }
1032
1033 /**
1034 * @brief Set AES key[223:192].
1035 *
1036 * Register|BitsName
1037 * ---------------|---------------
1038 * KEY1 | KEY
1039 *
1040 * @param AESx AES instance
1041 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1042 * @retval None
1043 */
1044 __STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
1045 {
1046 WRITE_REG(AESx->KEY1, key);
1047 }
1048
1049 /**
1050 * @brief Set AES key[191:160].
1051 *
1052 * Register|BitsName
1053 * ---------------|---------------
1054 * KEY2 | KEY
1055 *
1056 * @param AESx AES instance
1057 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1058 * @retval None
1059 */
1060 __STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
1061 {
1062 WRITE_REG(AESx->KEY2, key);
1063 }
1064
1065 /**
1066 * @brief Set AES key[159:128].
1067 *
1068 * Register|BitsName
1069 * ---------------|---------------
1070 * KEY3 | KEY
1071 *
1072 * @param AESx AES instance
1073 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1074 * @retval None
1075 */
1076 __STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
1077 {
1078 WRITE_REG(AESx->KEY3, key);
1079 }
1080
1081 /**
1082 * @brief Set AES key[127:96].
1083 *
1084 * Register|BitsName
1085 * ---------------|---------------
1086 * KEY4 | KEY
1087 *
1088 * @param AESx AES instance
1089 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1090 * @retval None
1091 */
1092 __STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
1093 {
1094 WRITE_REG(AESx->KEY4, key);
1095 }
1096
1097 /**
1098 * @brief Set AES key[95:64].
1099 *
1100 * Register|BitsName
1101 * ---------------|---------------
1102 * KEY5 | KEY
1103 *
1104 * @param AESx AES instance
1105 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1106 * @retval None
1107 */
1108 __STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
1109 {
1110 WRITE_REG(AESx->KEY5, key);
1111 }
1112
1113 /**
1114 * @brief Set AES key[63:32].
1115 *
1116 * Register|BitsName
1117 * ---------------|---------------
1118 * KEY6 | KEY
1119 *
1120 * @param AESx AES instance
1121 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1122 * @retval None
1123 */
1124 __STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
1125 {
1126 WRITE_REG(AESx->KEY6, key);
1127 }
1128
1129 /**
1130 * @brief Set AES key[31:0].
1131 *
1132 * Register|BitsName
1133 * ---------------|---------------
1134 * KEY7 | KEY
1135 *
1136 * @param AESx AES instance
1137 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1138 * @retval None
1139 */
1140 __STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
1141 {
1142 WRITE_REG(AESx->KEY7, key);
1143 }
1144
1145 /**
1146 * @brief Set AES input seed.
1147 *
1148 * Register|BitsName
1149 * ---------------|---------------
1150 * INIT_SSI | SEED_IN
1151 *
1152 * @param AESx AES instance
1153 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1154 * @retval None
1155 */
1156 __STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
1157 {
1158 WRITE_REG(AESx->INIT_SSI, seed);
1159 }
1160
1161 /**
1162 * @brief Get AES input seed.
1163 *
1164 * Register|BitsName
1165 * ---------------|---------------
1166 * INIT_SSI | SEED_IN
1167 *
1168 * @param AESx AES instance
1169 * @retval Returned value is the input seed.
1170 */
1171 __STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
1172 {
1173 return (READ_REG(AESx->INIT_SSI));
1174 }
1175
1176 /**
1177 * @brief Set AES output seed.
1178 *
1179 * Register|BitsName
1180 * ---------------|---------------
1181 * INIT_SSO | SEED_OUT
1182 *
1183 * @param AESx AES instance
1184 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1185 * @retval None
1186 */
1187 __STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
1188 {
1189 WRITE_REG(AESx->INIT_SSO, seed);
1190 }
1191
1192 /**
1193 * @brief Get AES output seed.
1194 *
1195 * Register|BitsName
1196 * ---------------|---------------
1197 * INIT_SSO | SEED_OUT
1198 *
1199 * @param AESx AES instance
1200 * @retval Returned value is the output seed.
1201 */
1202 __STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
1203 {
1204 return (READ_REG(AESx->INIT_SSO));
1205 }
1206
1207 /**
1208 * @brief Set sbox input data's mask.
1209 *
1210 * Register|BitsName
1211 * ---------------|---------------
1212 * MASK_SSI | SEED_IMASK
1213 *
1214 * @param AESx AES instance
1215 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1216 * @retval None
1217 */
1218 __STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
1219 {
1220 WRITE_REG(AESx->MASK_SSI, mask);
1221 }
1222
1223 /**
1224 * @brief Get sbox input data's mask.
1225 *
1226 * Register|BitsName
1227 * ---------------|---------------
1228 * MASK_SSI | SEED_IMASK
1229 *
1230 * @param AESx AES instance
1231 * @retval Returned value is the input data's mask.
1232 */
1233 __STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
1234 {
1235 return (READ_REG(AESx->MASK_SSI));
1236 }
1237
1238 /**
1239 * @brief Set sbox output data's mask.
1240 *
1241 * Register|BitsName
1242 * ---------------|---------------
1243 * MASK_SSO | SEED_OSBOX
1244 *
1245 * @param AESx AES instance
1246 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1247 * @retval None
1248 */
1249 __STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
1250 {
1251 WRITE_REG(AESx->MASK_SSO, mask);
1252 }
1253
1254 /**
1255 * @brief Get sbox output data's mask.
1256 *
1257 * Register|BitsName
1258 * ---------------|---------------
1259 * MASK_SSO | SEED_OSBOX
1260 *
1261 * @param AESx AES instance
1262 * @retval Returned value is the output data's mask.
1263 */
1264 __STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
1265 {
1266 return (READ_REG(AESx->MASK_SSO));
1267 }
1268
1269 /**
1270 * @brief Set AES initialization vector[127:96].
1271 *
1272 * Register|BitsName
1273 * ---------------|---------------
1274 * INIT_V0 | VECTOR_INIT
1275 *
1276 * @param AESx AES instance
1277 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1278 * @retval None
1279 */
1280 __STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
1281 {
1282 WRITE_REG(AESx->INIT_V0, vector);
1283 }
1284
1285 /**
1286 * @brief Set AES initialization vector[95:64].
1287 *
1288 * Register|BitsName
1289 * ---------------|---------------
1290 * INIT_V1 | VECTOR_INIT
1291 *
1292 * @param AESx AES instance
1293 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1294 * @retval None
1295 */
1296 __STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
1297 {
1298 WRITE_REG(AESx->INIT_V1, vector);
1299 }
1300
1301 /**
1302 * @brief Set AES initialization vector[63:32].
1303 *
1304 * Register|BitsName
1305 * ---------------|---------------
1306 * INIT_V2 | VECTOR_INIT
1307 *
1308 * @param AESx AES instance
1309 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1310 * @retval None
1311 */
1312 __STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
1313 {
1314 WRITE_REG(AESx->INIT_V2, vector);
1315 }
1316
1317 /**
1318 * @brief Set AES initialization vector[31:0].
1319 *
1320 * Register|BitsName
1321 * ---------------|---------------
1322 * INIT_V3 | VECTOR_INIT
1323 *
1324 * @param AESx AES instance
1325 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1326 * @retval None
1327 */
1328 __STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
1329 {
1330 WRITE_REG(AESx->INIT_V3, vector);
1331 }
1332
1333 /**
1334 * @brief Set AES input data[127:96].
1335 *
1336 * Register|BitsName
1337 * ---------------|---------------
1338 * DATA_IN0 | DATA_IN
1339 *
1340 * @param AESx AES instance
1341 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1342 * @retval None
1343 */
1344 __STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
1345 {
1346 WRITE_REG(AESx->DATA_IN0, data);
1347 }
1348
1349 /**
1350 * @brief Set AES input data[95:64].
1351 *
1352 * Register|BitsName
1353 * ---------------|---------------
1354 * DATA_IN1 | DATA_IN
1355 *
1356 * @param AESx AES instance
1357 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1358 * @retval None
1359 */
1360 __STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
1361 {
1362 WRITE_REG(AESx->DATA_IN1, data);
1363 }
1364
1365 /**
1366 * @brief Set AES input data[63:32].
1367 *
1368 * Register|BitsName
1369 * ---------------|---------------
1370 * DATA_IN2 | DATA_IN
1371 *
1372 * @param AESx AES instance
1373 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1374 * @retval None
1375 */
1376 __STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
1377 {
1378 WRITE_REG(AESx->DATA_IN2, data);
1379 }
1380
1381 /**
1382 * @brief Set AES input data[31:0].
1383 *
1384 * Register|BitsName
1385 * ---------------|---------------
1386 * DATA_IN3 | DATA_IN
1387 *
1388 * @param AESx AES instance
1389 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1390 * @retval None
1391 */
1392 __STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
1393 {
1394 WRITE_REG(AESx->DATA_IN3, data);
1395 }
1396
1397 /**
1398 * @brief Set AES fetch key port mask.
1399 *
1400 * Register|BitsName
1401 * ---------------|---------------
1402 * KEYPORT_MASK | KPORT_MASK
1403 *
1404 * @param AESx AES instance
1405 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1406 * @retval None
1407 */
1408 __STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
1409 {
1410 WRITE_REG(AESx->KEYPORT_MASK, mask);
1411 }
1412
1413 /**
1414 * @brief Set AES keyram offset.
1415 *
1416 * Register|BitsName
1417 * ---------------|---------------
1418 * KEYRAM_OFS | OFFSET
1419 *
1420 * @param AESx AES instance
1421 * @param offset This parameter can be one of the following values:
1422 * @arg @ref LL_AES_KEYRAM_KEYSLOT_3
1423 * @arg @ref LL_AES_KEYRAM_KEYSLOT_4
1424 * @arg @ref LL_AES_KEYRAM_KEYSLOT_5
1425 * @arg @ref LL_AES_KEYRAM_KEYSLOT_6
1426 * @arg @ref LL_AES_KEYRAM_KEYSLOT_7
1427 * @arg @ref LL_AES_KEYRAM_KEYSLOT_8
1428 * @arg @ref LL_AES_KEYRAM_KEYSLOT_9
1429 * @arg @ref LL_AES_KEYRAM_KEYSLOT_10
1430 * @arg @ref LL_AES_KEYRAM_KEYSLOT_11
1431 * @arg @ref LL_AES_KEYRAM_KEYSLOT_12
1432 * @arg @ref LL_AES_KEYRAM_KEYSLOT_13
1433 * @arg @ref LL_AES_KEYRAM_KEYSLOT_14
1434 * @arg @ref LL_AES_KEYRAM_KEYSLOT_15
1435 * @retval None
1436 */
1437 __STATIC_INLINE void ll_aes_set_keyram_offset(aes_regs_t *AESx, uint32_t offset)
1438 {
1439 WRITE_REG(AESx->KEYRAM_OFS, offset);
1440 }
1441
1442 /**
1443 * @brief Get AES keyram offset.
1444 *
1445 * Register|BitsName
1446 * ---------------|---------------
1447 * KEYRAM_OFS | OFFSET
1448 *
1449 * @param AESx AES instance
1450 * @retval Returned value is the offset of keyram.
1451 */
1452 __STATIC_INLINE uint32_t ll_aes_get_keyram_offset(aes_regs_t *AESx)
1453 {
1454 return (READ_REG(AESx->KEYRAM_OFS));
1455 }
1456
1457 /**
1458 * @brief Clear AES CBC first block.
1459 *
1460 * Register|BitsName
1461 * --------|---------------
1462 * CBC_RST | CLR
1463 *
1464 * @param AESx AES instance
1465 * @retval None
1466 */
1467 __STATIC_INLINE void ll_aes_clr_first_block(aes_regs_t *AESx)
1468 {
1469 SET_BITS(AESx->CBC_RST, AES_CBC_RST_CLR);
1470 }
1471
1472 /** @} */
1473
1474 /** @defgroup AES_LL_EF_Init Initialization and de-initialization functions
1475 * @{
1476 */
1477
1478 /**
1479 * @brief De-initialize AES registers (Registers restored to their default values).
1480 * @param AESx AES Instance
1481 * @retval An error_status_t enumeration value:
1482 * - SUCCESS: AES registers are de-initialized
1483 * - ERROR: AES registers are not de-initialized
1484 */
1485 error_status_t ll_aes_deinit(aes_regs_t *AESx);
1486
1487 /**
1488 * @brief Initialize AES registers according to the specified
1489 * parameters in p_aes_init.
1490 * @param AESx AES Instance
1491 * @param p_aes_init Pointer to a ll_aes_init_t structure that contains the configuration
1492 * information for the specified AES peripheral.
1493 * @retval An error_status_t enumeration value:
1494 * - SUCCESS: AES registers are initialized according to p_aes_init content
1495 * - ERROR: Problem occurred during AES Registers initialization
1496 */
1497 error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init);
1498
1499 /**
1500 * @brief Set each field of a @ref ll_aes_init_t type structure to default value.
1501 * @param p_aes_init Pointer to a @ref ll_aes_init_t structure
1502 * whose fields will be set to default values.
1503 * @retval None
1504 */
1505 void ll_aes_struct_init(ll_aes_init_t *p_aes_init);
1506
1507 /** @} */
1508
1509 /** @} */
1510
1511 #endif /* AES */
1512
1513 #ifdef __cplusplus
1514 }
1515 #endif
1516
1517 #endif /* __GR5XX_LL_AES_H__ */
1518
1519 /** @} */
1520
1521 /** @} */
1522
1523 /** @} */
ll_aes_enable_read_key
__STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
Enable fetch key through AHB/key port.
Definition: ll_aes.h:358
ll_aes_enable_encryption
__STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
Enable AES encryption mode.
Definition: ll_aes.h:455
ll_aes_disable_encryption
__STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
Disable AES encryption mode.
Definition: ll_aes.h:470
ll_aes_set_vector_127_96
__STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[127:96].
Definition: ll_aes.h:1280
_ll_aes_init::p_key
uint32_t * p_key
Definition: ll_aes.h:80
ll_aes_disable_start
__STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
Disable AES start in MCU mode.
Definition: ll_aes.h:283
ll_aes_clr_first_block
__STATIC_INLINE void ll_aes_clr_first_block(aes_regs_t *AESx)
Clear AES CBC first block.
Definition: ll_aes.h:1467
ll_aes_get_data_63_32
__STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
Get AES output data[63:32].
Definition: ll_aes.h:997
ll_aes_get_data_127_96
__STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
Get AES output data[127:96].
Definition: ll_aes.h:967
ll_aes_set_key_type
__STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
Set ways to obtain AES key.
Definition: ll_aes.h:614
ll_aes_disable
__STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
Disable AES.
Definition: ll_aes.h:238
ll_aes_set_data_63_32
__STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
Set AES input data[63:32].
Definition: ll_aes.h:1376
ll_aes_set_key_95_64
__STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
Set AES key[95:64].
Definition: ll_aes.h:1108
ll_aes_init_t
struct _ll_aes_init ll_aes_init_t
LL AES Init Structure definition.
ll_aes_get_data_95_64
__STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
Get AES output data[95:64].
Definition: ll_aes.h:982
ll_aes_get_dma_write_address
__STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
Get AES write address of RAM in DMA mode.
Definition: ll_aes.h:915
ll_aes_is_action_flag_dma_error
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
Indicate whether the DMA transfer error flag is set.
Definition: ll_aes.h:769
ll_aes_set_operation_mode
__STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
Set AES operation mode.
Definition: ll_aes.h:578
ll_aes_set_key_31_0
__STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
Set AES key[31:0].
Definition: ll_aes.h:1140
ll_aes_is_enabled_it_done
__STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt is enabled.
Definition: ll_aes.h:718
ll_aes_set_vector_63_32
__STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[63:32].
Definition: ll_aes.h:1312
ll_aes_set_vector_31_0
__STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[31:0].
Definition: ll_aes.h:1328
ll_aes_get_key_mode
__STATIC_INLINE uint32_t ll_aes_get_key_mode(aes_regs_t *AESx)
Get AES key mode.
Definition: ll_aes.h:667
ll_aes_is_action_flag_ready
__STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
Indicate whether the ready flag is set.
Definition: ll_aes.h:739
ll_aes_is_enabled_full_mask
__STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
Indicate whether the AES full mask is enabled.
Definition: ll_aes.h:440
ll_aes_set_seed_in
__STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
Set AES input seed.
Definition: ll_aes.h:1156
ll_aes_enable_full_mask
__STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
Enable AES full mask.
Definition: ll_aes.h:410
ll_aes_get_keyram_offset
__STATIC_INLINE uint32_t ll_aes_get_keyram_offset(aes_regs_t *AESx)
Get AES keyram offset.
Definition: ll_aes.h:1452
ll_aes_deinit
error_status_t ll_aes_deinit(aes_regs_t *AESx)
De-initialize AES registers (Registers restored to their default values).
_ll_aes_init
LL AES Init Structure definition.
Definition: ll_aes.h:76
ll_aes_disable_dma_start
__STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
Disable AES DMA mode.
Definition: ll_aes.h:328
ll_aes_is_enabled_little_endian
__STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
Indicate whether the AES is in little endian.
Definition: ll_aes.h:560
ll_aes_enable_start
__STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
Enable AES start in MCU mode.
Definition: ll_aes.h:268
_ll_aes_init::p_init_vector
uint32_t * p_init_vector
Definition: ll_aes.h:82
ll_aes_set_key_191_160
__STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
Set AES key[191:160].
Definition: ll_aes.h:1060
ll_aes_set_dma_write_address
__STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
Set AES write address of RAM in DMA mode.
Definition: ll_aes.h:900
ll_aes_get_key_size
__STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
Get AES key size.
Definition: ll_aes.h:395
ll_aes_get_seed_Imask
__STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
Get sbox input data's mask.
Definition: ll_aes.h:1233
ll_aes_init
error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init)
Initialize AES registers according to the specified parameters in p_aes_init.
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_aes_is_action_flag_dma_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
Indicate whether the DMA transfer done flag is set.
Definition: ll_aes.h:754
ll_aes_set_first_block
__STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
Definition: ll_aes.h:515
ll_aes_get_key_type
__STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
Get ways to obtain AES key.
Definition: ll_aes.h:632
ll_aes_set_data_95_64
__STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
Set AES input data[95:64].
Definition: ll_aes.h:1360
ll_aes_is_action_flag_it_done
__STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
Indicate whether the done interrupt flag is set.
Definition: ll_aes.h:799
ll_aes_set_data_127_96
__STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
Set AES input data[127:96].
Definition: ll_aes.h:1344
ll_aes_set_key_63_32
__STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
Set AES key[63:32].
Definition: ll_aes.h:1124
ll_aes_set_key_mode
__STATIC_INLINE void ll_aes_set_key_mode(aes_regs_t *AESx, uint32_t mode)
Set AES key mode.
Definition: ll_aes.h:650
ll_aes_set_key_address
__STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
Set AES key address in memory.
Definition: ll_aes.h:937
ll_aes_disable_little_endian
__STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
Disable AES in little endian.
Definition: ll_aes.h:545
ll_aes_is_enabled_encryption
__STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
Indicate whether the AES encryption mode is enabled.
Definition: ll_aes.h:485
ll_aes_set_vector_95_64
__STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
Set AES initialization vector[95:64].
Definition: ll_aes.h:1296
ll_aes_set_key_159_128
__STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
Set AES key[159:128].
Definition: ll_aes.h:1076
ll_aes_get_dma_read_address
__STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
Get AES read address of RAM in DMA mode.
Definition: ll_aes.h:883
ll_aes_is_action_flag_key_valid
__STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
Indicate whether the key valid flag is set.
Definition: ll_aes.h:784
ll_aes_get_seed_out
__STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
Get AES output seed.
Definition: ll_aes.h:1202
ll_aes_get_seed_Osbox
__STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
Get sbox output data's mask.
Definition: ll_aes.h:1264
ll_aes_struct_init
void ll_aes_struct_init(ll_aes_init_t *p_aes_init)
Set each field of a ll_aes_init_t type structure to default value.
ll_aes_disable_it_done
__STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
Disable AES the done interrupt.
Definition: ll_aes.h:703
ll_aes_enable_little_endian
__STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
Enable AES in little endian.
Definition: ll_aes.h:530
ll_aes_set_dma_read_address
__STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
Set AES read address of RAM in DMA mode.
Definition: ll_aes.h:868
ll_aes_enable_it_done
__STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
Enable AES the done interrupt.
Definition: ll_aes.h:688
ll_aes_set_seed_out
__STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
Set AES output seed.
Definition: ll_aes.h:1187
_ll_aes_init::key_size
uint32_t key_size
Definition: ll_aes.h:77
ll_aes_set_data_31_0
__STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
Set AES input data[31:0].
Definition: ll_aes.h:1392
ll_aes_get_operation_mode
__STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
Get AES operation mode.
Definition: ll_aes.h:595
ll_aes_get_key_address
__STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
Get AES key address in memory.
Definition: ll_aes.h:952
ll_aes_set_seed_Imask
__STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
Set sbox input data's mask.
Definition: ll_aes.h:1218
ll_aes_get_data_31_0
__STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
Get AES output data[31:0].
Definition: ll_aes.h:1012
ll_aes_disable_full_mask
__STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
Disable AES full mask.
Definition: ll_aes.h:425
ll_aes_set_key_255_224
__STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
Set AES key[255:224].
Definition: ll_aes.h:1028
ll_aes_is_enabled_dma_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
Indicate whether the AES DMA mode is enabled.
Definition: ll_aes.h:343
ll_aes_set_dma_transfer_block
__STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
Set AES transfer blocks in DMA mode.
Definition: ll_aes.h:836
ll_aes_set_key_port_mask
__STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
Set AES fetch key port mask.
Definition: ll_aes.h:1408
ll_aes_get_seed_in
__STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
Get AES input seed.
Definition: ll_aes.h:1171
ll_aes_clear_flag_it_done
__STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
Clear the done interrupt flag.
Definition: ll_aes.h:814
ll_aes_enable_dma_start
__STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
Enable AES DMA mode.
Definition: ll_aes.h:313
ll_aes_set_seed_Osbox
__STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
Set sbox output data's mask.
Definition: ll_aes.h:1249
ll_aes_enable
__STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
Enable AES.
Definition: ll_aes.h:223
ll_aes_set_key_127_96
__STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
Set AES key[127:96].
Definition: ll_aes.h:1092
ll_aes_set_load_seed
__STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
Set AES to load seed for LFSR.
Definition: ll_aes.h:500
ll_aes_is_enabled_start
__STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
Indicate whether the AES start in MCU mode is enabled.
Definition: ll_aes.h:298
ll_aes_is_enabled
__STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
Indicate whether the AES is enabled.
Definition: ll_aes.h:253
ll_aes_set_keyram_offset
__STATIC_INLINE void ll_aes_set_keyram_offset(aes_regs_t *AESx, uint32_t offset)
Set AES keyram offset.
Definition: ll_aes.h:1437
ll_aes_set_key_223_192
__STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
Set AES key[223:192].
Definition: ll_aes.h:1044
ll_aes_set_key_size
__STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
Set AES key size.
Definition: ll_aes.h:377
_ll_aes_init::p_seed
uint32_t * p_seed
Definition: ll_aes.h:84
ll_aes_get_dma_transfer_block
__STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
Get AES transfer blocks in DMA mode.
Definition: ll_aes.h:851