ll_pwm.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef _LL_PWM_H__
52 #define _LL_PWM_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 #include "gr5x.h"
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /* Exported types ------------------------------------------------------------*/
63 /** @addtogroup LL_PWM_ENUMERATIONS Enumerations
64 * @{
65 */
66
67 /**
68 * @brief LL PWM Mode definition
69 */
70 enum
71 {
72 LL_PWM_FLICKER_MODE = 0x00, /**< Choose PWM Flicker Mode */
73 LL_PWM_BREATH_MODE, /**< Choose PWM Breath Mode */
74 LL_PWM_CODING_MODE, /**< Choose PWM Coding Mode */
75 };
76
77 typedef uint8_t ll_pwm_mode_t;
78
79 /** @} */
80
81 /** @defgroup PWM_LL_STRUCTURES Structures
82 * @{
83 */
84
85 /* Exported types ------------------------------------------------------------*/
86 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
87 * @{
88 */
89
90 /**
91 * @brief LL PWM Output Channel init Structure definition.
92 */
93 typedef struct _ll_pwm_none_coding_channel_init_t
94 {
95 uint8_t duty; /**< Specifies the duty in PWM output mode.
96 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.*/
97
98 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
99 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
100
101 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
102 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
103
104 uint32_t flickerstop_lvl; /**< Specifies the IO level when channel flicker stop.
105 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
106 } ll_pwm_none_coding_channel_init_t;
107
108 /**
109 * @brief LL PWM Output Channel init Structure definition.
110 */
111 typedef struct _ll_pwm_coding_channel_init_t
112 {
113 uint32_t ll_comp0; /**< Specifies current channel first compare value
114 This parameter must be a number ranges between Min_Data=0 and Max_Data=period.*/
115
116 uint32_t ll_comp1; /**< Specifies current channel second compare value
117 This parameter must be a number ranges between Min_Data=0 and Max_Data=period.*/
118
119 uint8_t ll_drive_polarity; /**< Specifies the drive polarity in PWM output mode.
120 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
121 This feature can be modified afterwards using unitary function ll_pwm_enable_positive_drive_channel_x()
122 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C).*/
123
124 uint8_t ll_waiting_time_lvl; /**< Specifies the waiting time level in coding mode.
125 This parameter can be a value of @ref PWM_LL_WAITING_TIME_LVL.*/
126
127 } ll_pwm_coding_channel_init_t;
128
129 /**
130 * @brief LL PWM none coding mode Structure definition.
131 */
132 typedef struct _ll_pwm_none_coding_mode_init_t
133 {
134 uint32_t align; /**< Specifies the PWM alignment pulses.
135 This parameter can be a value of @ref PWM_LL_EC_ALIGN.*/
136
137 uint32_t prescaler; /**< Specifies the prescaler value which will be used configure PWM output frequency.
138 This parameter must be a number ranges between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
139 This parameter should be larger than 128.
140
141 This feature can be modified afterwards using unitary function @ref ll_pwm_set_prescaler().*/
142
143 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in breath mode.
144 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
145 This parameter is recommended to be larger than 128*prescaler to guarantee an ideal breath effect.
146
147 This feature can be modified afterwards using unitary function @ref ll_pwm_set_breath_prescaler().*/
148
149 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
150 This parameter must be a number ranges between Min_Data=0 and Max_Data=0xFFFFFF.
151
152 This feature can be modified afterwards using unitary function @ref ll_pwm_set_hold_prescaler().*/
153
154 uint32_t breathstop_lvl; /**< Specifies the IO level when breath stop.
155 This parameter can be a value of @ref PWM_LL_STOP_LVL.*/
156
157 ll_pwm_none_coding_channel_init_t channel_a; /**< Specifies the configuration of channelA.
158 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
159
160 ll_pwm_none_coding_channel_init_t channel_b; /**< Specifies the configuration of channelB.
161 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
162
163 ll_pwm_none_coding_channel_init_t channel_c; /**< Specifies the configuration of channelC.
164 This parameter can be a value of @ref ll_pwm_none_coding_channel_init_t.*/
165 } ll_pwm_none_coding_mode_init_t;
166
167 /**
168 * @brief LL PWM coding mode Structure definition.
169 */
170 typedef struct _ll_pwm_coding_mode_init_t
171 {
172 uint32_t ll_period; /**< Specifies the period value which will be used configure PWM output frequency in coding mode.
173 This parameter must be a number ranges between Min_Data = 0 and Max_Data = SysCoreCLK.*/
174
175 uint32_t ll_waiting_time; /**< Specifies the waiting time before PWM waveform generation in coding mode.
176 This parameter control PWM waiting time count in the coding mode.*/
177
178 uint8_t ll_data_width_valid; /**< Specifies the coding data valid width in Coding mode.
179 This parameter control coding data valid width = DATA_WIDTH_VALID + 1,
180 DATA_WIDTH_VALID value ranges between Min_Data = 0x0 and Max_Data = 0x1F.*/
181
182 uint8_t ll_coding_channel_select; /**< Specifies the coding channel select all 3 channels or only channel A.
183 This parameter can be a value of @ref PWM_LL_CODING_CHANNEL*/
184
185 ll_pwm_coding_channel_init_t ll_channel_a; /**< Specifies the configuration of channelA in coding mode.
186 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
187
188 ll_pwm_coding_channel_init_t ll_channel_b; /**< Specifies the configuration of channelB in coding mode.
189 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
190
191 ll_pwm_coding_channel_init_t ll_channel_c; /**< Specifies the configuration of channelC in coding mode.
192 This parameter can be a value of @ref ll_pwm_coding_channel_init_t.*/
193 } ll_pwm_coding_mode_init_t;
194
195 /**
196 * @brief LL PWM init Structure definition.
197 */
198 typedef struct _ll_pwm_init_t
199 {
200 ll_pwm_mode_t ll_mode; /**< Specifies the PWM output mode.
201 This parameter can be a value of PWM_LL_EC_MODE.
202
203 This feature can be modified afterwards using unitary function @ref ll_pwm_set_mode().*/
204
205 uint32_t ll_prd_cycles; /**< Specifies the number of period cycle in Flicker mode or Coding mode.
206 This parameter control the number of period cycles, when set to 0 will continuously generate waveform.*/
207
208 ll_pwm_none_coding_mode_init_t none_coding_mode_cfg; /**< Specifies the none coding mode config.
209 This parameter can be a value of @ref ll_pwm_none_coding_mode_init_t.*/
210
211 ll_pwm_coding_mode_init_t coding_mode_cfg; /**< Specifies the coding mode config.
212 This parameter can be a value of @ref ll_pwm_coding_mode_init_t.*/
213
214 } ll_pwm_init_t;
215
216 /** @} */
217
218 /** @} */
219
220 /**
221 * @defgroup PWM_LL_MACRO Defines
222 * @{
223 */
224
225 /* Exported constants --------------------------------------------------------*/
226 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
227 * @{
228 */
229
230 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
231 * @{
232 */
233 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
234 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
235 /** @} */
236
237 /** @defgroup PWM_LL_STOP_LVL PWM stop io level
238 * @{
239 */
240 #define LL_PWM_STOP_LVL_LOW (0x00000000U) /**< PWM stop in low io level */
241 #define LL_PWM_STOP_LVL_HIGH (0x00000001U) /**< PWM stop in high io level */
242 /** @} */
243
244 /** @defgroup PWM_LL_WAITING_TIME_LVL PWM waiting time io level
245 * @{
246 */
247 #define LL_PWM_WAITING_TIME_LVL_LOW (0x00000000U) /**< PWM waiting time io level low */
248 #define LL_PWM_WAITING_TIME_LVL_HIGH (0x00000001U) /**< PWM waiting time io level high */
249 /** @} */
250
251 /** @defgroup PWM_LL_CODING_CHANNEL PWM coding channel select in coding mode
252 * @{
253 */
254 #define LL_PWM_CODING_CHANNEL_ALL (0x00000000U) /**< Select all channels operation in coding mode */
255 #define LL_PWM_CODING_CHANNEL_A (0x00000001U) /**< Select channle A operation in coding mode */
256 /** @} */
257
258 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
259 * @{
260 */
261 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
262 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
263 /** @} */
264
265 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
266 * @{
267 */
268 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
269 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
270 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
271 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
272 /** @} */
273
274 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
275 * @{
276 */
277 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
278 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
279 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
280 /** @} */
281
282 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
283 * @{
284 */
285
286 /**
287 * @brief LL PWM None Coding Channel InitStrcut default configuartion
288 */
289 #define LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG \
290 { \
291 .duty = 50, \
292 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
293 .flickerstop_lvl = LL_PWM_STOP_LVL_LOW, \
294 }
295
296 /**
297 * @brief LL PWM Coding Channel InitStrcut default configuartion
298 */
299 #define LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG \
300 { \
301 .ll_comp0 = 0, \
302 .ll_comp1 = 640, \
303 .ll_drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
304 .ll_waiting_time_lvl = LL_PWM_WAITING_TIME_LVL_LOW, \
305 }
306
307 /**
308 * @brief LL PWM None Coding InitStrcut default configuartion
309 */
310 #define LL_PWM_NONE_CODING_DEFAULT_CONFIG \
311 { \
312 .align = LL_PWM_EDGE_ALIGNED, \
313 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
314 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
315 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
316 .breathstop_lvl = LL_PWM_STOP_LVL_LOW, \
317 .channel_a = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
318 .channel_b = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
319 .channel_c = LL_PWM_NONE_CODING_CHANNEL_DEFAULT_CONFIG, \
320 }
321
322 /**
323 * @brief LL PWM Coding InitStrcut default configuartion
324 */
325 #define LL_PWM_CODING_DEFAULT_CONFIG \
326 { \
327 .ll_period = 640, \
328 .ll_waiting_time = 640, \
329 .ll_data_width_valid = 0x1F, \
330 .ll_coding_channel_select = LL_PWM_CODING_CHANNEL_ALL, \
331 .ll_channel_a = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
332 .ll_channel_b = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
333 .ll_channel_c = LL_PWM_CODING_CHANNEL_DEFAULT_CONFIG, \
334 }
335
336 /**
337 * @brief LL PWM InitStrcut default configuartion
338 */
339 #define LL_PWM_DEFAULT_CONFIG \
340 { \
341 .ll_mode = LL_PWM_FLICKER_MODE, \
342 .ll_prd_cycles = 0x0, \
343 .none_coding_mode_cfg = LL_PWM_NONE_CODING_DEFAULT_CONFIG, \
344 .coding_mode_cfg = LL_PWM_CODING_DEFAULT_CONFIG, \
345 }
346
347 /** @} */
348
349 /** @} */
350
351 /* Exported macro ------------------------------------------------------------*/
352 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
353 * @{
354 */
355
356 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
357 * @{
358 */
359
360 /**
361 * @brief Write a value in PWM register
362 * @param __instance__ PWM instance
363 * @param __REG__ Register to be written
364 * @param __VALUE__ Value to be written in the register
365 * @retval None
366 */
367 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
368
369 /**
370 * @brief Read a value in PWM register
371 * @param __instance__ PWM instance
372 * @param __REG__ Register to be read
373 * @retval Register value
374 */
375 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
376
377 /** @} */
378
379 /** @} */
380
381 /** @} */
382
383 /* Exported functions --------------------------------------------------------*/
384 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
385 * @{
386 */
387
388 /** @defgroup PWM_LL_EF_Configuration Configuration functions
389 * @{
390 */
391
392 /**
393 * @brief Enable PWM.
394 *
395 * Register|BitsName
396 * --------|--------
397 * MODE | EN
398 *
399 * @param PWMx PWM instance
400 * @retval None
401 */
402 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
403 {
404 SET_BITS(PWMx->MODE, PWM_MODE_EN);
405 }
406
407 /**
408 * @brief Disable PWM.
409 *
410 * Register|BitsName
411 * --------|--------
412 * MODE | EN
413 *
414 * @param PWMx PWM instance
415 * @retval None
416 */
417 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
418 {
419 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
420 }
421
422 /**
423 * @brief Indicate whether the PWM is enabled.
424 *
425 * Register|BitsName
426 * --------|--------
427 * MODE | EN
428 *
429 * @param PWMx PWM instance
430 * @retval State of bit (1 or 0).
431 */
432 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
433 {
434 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
435 }
436
437 /**
438 * @brief Enable PWM pause.
439 *
440 * Register|BitsName
441 * --------|--------
442 * MODE | PAUSE
443 *
444 * @param PWMx PWM instance
445 * @retval None
446 */
447 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
448 {
449 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
450 }
451
452 /**
453 * @brief Disable PWM pause.
454 *
455 * Register|BitsName
456 * --------|--------
457 * MODE | PAUSE
458 *
459 * @param PWMx PWM instance
460 * @retval None
461 */
462 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
463 {
464 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
465 }
466
467 /**
468 * @brief Indicate whether the PWM pause is enabled.
469 *
470 * Register|BitsName
471 * --------|--------
472 * MODE | PAUSE
473 *
474 * @param PWMx PWM instance
475 * @retval State of bit (1 or 0).
476 */
477 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
478 {
479 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
480 }
481
482 /**
483 * @brief Set PWM mode.
484 *
485 * Register|BitsName
486 * --------|--------
487 * MODE | BREATHEN and CODINGEN
488 *
489 * @param PWMx PWM instance
490 * @param mode This parameter can be one of the following values:
491 * @arg @ref LL_PWM_FLICKER_MODE
492 * @arg @ref LL_PWM_BREATH_MODE
493 * @arg @ref LL_PWM_CODING_MODE
494 * @retval None
495 */
496 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, ll_pwm_mode_t mode)
497 {
498 if(mode == LL_PWM_CODING_MODE) {
499 #ifdef HAL_PWM_FEATURE_LEGACY
500 if(PWMx == PWM0)
501 #endif
502 MODIFY_REG(PWMx->MODE, PWM_MODE_CODINGEN, 0x1 << PWM_MODE_CODINGEN_POS);
503 } else {
504 CLEAR_BITS(PWMx->MODE, PWM_MODE_CODINGEN);
505 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, (mode == LL_PWM_BREATH_MODE) ?
506 (0x1 << PWM_MODE_BREATHEN_POS) : (0x0 << PWM_MODE_BREATHEN_POS));
507 }
508 }
509
510 /**
511 * @brief Get PWM mode.
512 *
513 * Register|BitsName
514 * --------|--------
515 * MODE | BREATHEN and CODINGEN
516 *
517 * @param PWMx PWM instance
518 * @retval Return value can be one of the following values:
519 * @arg @ref LL_PWM_FLICKER_MODE
520 * @arg @ref LL_PWM_BREATH_MODE
521 * @arg @ref LL_PWM_CODING_MODE
522 */
523 __STATIC_INLINE ll_pwm_mode_t ll_pwm_get_mode(pwm_regs_t *PWMx)
524 {
525 if(READ_BITS(PWMx->MODE, PWM_MODE_CODINGEN) == PWM_MODE_CODINGEN) {
526 return LL_PWM_CODING_MODE;
527 } else {
528 return ((READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN) == PWM_MODE_BREATHEN) ? LL_PWM_BREATH_MODE : LL_PWM_FLICKER_MODE);
529 }
530 }
531
532 /**
533 * @brief Enable positive drive mode in channelA.
534 *
535 * Register|BitsName
536 * --------|--------
537 * MODE | DPENA
538 *
539 * @param PWMx PWM instance
540 * @retval None
541 */
542 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
543 {
544 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
545 }
546
547 /**
548 * @brief Disable positive drive mode in channelA.
549 *
550 * Register|BitsName
551 * --------|--------
552 * MODE | DPENA
553 *
554 * @param PWMx PWM instance
555 * @retval None
556 */
557 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
558 {
559 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
560 }
561
562 /**
563 * @brief Indicate whether the positive drive mode in channelA is enabled.
564 *
565 * Register|BitsName
566 * --------|--------
567 * MODE | DPENA
568 *
569 * @param PWMx PWM instance
570 * @retval State of bit (1 or 0).
571 */
572 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
573 {
574 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
575 }
576
577 /**
578 * @brief Enable positive drive mode in channelB.
579 *
580 * Register|BitsName
581 * --------|--------
582 * MODE | DPENB
583 *
584 * @param PWMx PWM instance
585 * @retval None
586 */
587 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
588 {
589 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
590 }
591
592 /**
593 * @brief Disable positive drive mode in channelB.
594 *
595 * Register|BitsName
596 * --------|--------
597 * MODE | DPENB
598 *
599 * @param PWMx PWM instance
600 * @retval None
601 */
602 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
603 {
604 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
605 }
606
607 /**
608 * @brief Indicate whether the positive drive mode in channelB is enabled.
609 *
610 * Register|BitsName
611 * --------|--------
612 * MODE | DPENB
613 *
614 * @param PWMx PWM instance
615 * @retval State of bit (1 or 0).
616 */
617 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
618 {
619 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
620 }
621
622 /**
623 * @brief Enable positive drive mode in channelC.
624 *
625 * Register|BitsName
626 * --------|--------
627 * MODE | DPENC
628 *
629 * @param PWMx PWM instance
630 * @retval None
631 */
632 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
633 {
634 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
635 }
636
637 /**
638 * @brief Disable positive drive mode in channelC.
639 *
640 * Register|BitsName
641 * --------|--------
642 * MODE | DPENC
643 *
644 * @param PWMx PWM instance
645 * @retval None
646 */
647 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
648 {
649 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
650 }
651
652 /**
653 * @brief Indicate whether the positive drive mode in channelC is enabled.
654 *
655 * Register|BitsName
656 * --------|--------
657 * MODE | DPENC
658 *
659 * @param PWMx PWM instance
660 * @retval State of bit (1 or 0).
661 */
662 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
663 {
664 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
665 }
666
667 /**
668 * @brief Set the channel_a stop level in flicker mode.
669 *
670 * Register|BitsName
671 * --------|--------
672 * MODE | FLICKER_PAUSE_LEVEL_A
673 *
674 * @param PWMx PWM flicker stop level
675 * @param flickerstop_lvl This parameter can be set with 0 or 1.
676 * @retval None
677 */
678 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
679 {
680 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_A_POS);
681 }
682
683 /**
684 * @brief Get the channel_a stop level in flicker mode.
685 *
686 * Register|BitsName
687 * --------|--------
688 * MODE | FLICKER_PAUSE_LEVEL_A
689 *
690 * @param PWMx
691 * @retval Return value of 0 or 1.
692 */
693 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
694 {
695 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_A));
696 }
697
698 /**
699 * @brief Set the channel_b stop level in flicker mode.
700 *
701 * Register|BitsName
702 * --------|--------
703 * MODE | FLICKER_PAUSE_LEVEL_B
704 *
705 * @param PWMx PWM flicker stop level
706 * @param flickerstop_lvl This parameter can be set with 0 or 1.
707 * @retval None
708 */
709 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
710 {
711 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_B_POS);
712 }
713
714 /**
715 * @brief Get the channel_b stop level in flicker mode.
716 *
717 * Register|BitsName
718 * --------|--------
719 * MODE | FLICKER_PAUSE_LEVEL_B
720 *
721 * @param PWMx
722 * @retval Return value of 0 or 1.
723 */
724 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
725 {
726 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_B));
727 }
728
729 /**
730 * @brief Set the channel_c stop level in flicker mode.
731 *
732 * Register|BitsName
733 * --------|--------
734 * MODE | FLICKER_PAUSE_LEVEL_C
735 *
736 * @param PWMx PWM flicker stop level
737 * @param flickerstop_lvl This parameter can be set with 0 or 1.
738 * @retval None
739 */
740 __STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx,uint32_t flickerstop_lvl)
741 {
742 MODIFY_REG(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C, flickerstop_lvl << PWM_MODE_FLICKER_PAUSE_LEVEL_C_POS);
743 }
744
745 /**
746 * @brief Get the channel_c stop level in flicker mode.
747 *
748 * Register|BitsName
749 * --------|--------
750 * MODE | FLICKER_PAUSE_LEVEL_C
751 *
752 * @param PWMx
753 * @retval Return value of 0 or 1.
754 */
755 __STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
756 {
757 return (READ_BITS(PWMx->MODE, PWM_MODE_FLICKER_PAUSE_LEVEL_C));
758 }
759
760 /**
761 * @brief Set the channel_a waiting time level in coding mode.
762 *
763 * Register|BitsName
764 * --------|--------
765 * MODE | WAITING_TIME_LEVEL_A
766 *
767 * @param PWMx
768 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
769 * @retval None
770 */
771 __STATIC_INLINE void ll_pwm_set_waiting_time_level_a(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
772 {
773 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_A_POS);
774 }
775
776 /**
777 * @brief Get the channel_a waiting time level in coding mode.
778 *
779 * Register|BitsName
780 * --------|--------
781 * MODE | WAITING_TIME_LEVEL_A
782 *
783 * @param PWMx
784 * @retval Return value of 0 or 1.
785 */
786 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_a(pwm_regs_t *PWMx)
787 {
788 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_A) == (PWM_MODE_WAITING_TIME_LEVEL_A));
789 }
790
791 /**
792 * @brief Set the channel_b waiting time level in coding mode.
793 *
794 * Register|BitsName
795 * --------|--------
796 * MODE | WAITING_TIME_LEVEL_B
797 *
798 * @param PWMx
799 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
800 * @retval None
801 */
802 __STATIC_INLINE void ll_pwm_set_waiting_time_level_b(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
803 {
804 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_B_POS);
805 }
806
807 /**
808 * @brief Get the channel_b waiting time level in coding mode.
809 *
810 * Register|BitsName
811 * --------|--------
812 * MODE | WAITING_TIME_LEVEL_B
813 *
814 * @param PWMx
815 * @retval Return value of 0 or 1.
816 */
817 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_b(pwm_regs_t *PWMx)
818 {
819 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_B) == (PWM_MODE_WAITING_TIME_LEVEL_B));
820 }
821
822 /**
823 * @brief Set the channel_c waiting time level in coding mode.
824 *
825 * Register|BitsName
826 * --------|--------
827 * MODE | WAITING_TIME_LEVEL_C
828 *
829 * @param PWMx
830 * @param waiting_time_lvl This parameter can be set with LL_PWM_WAITING_TIME_LVL_LOW or LL_PWM_WAITING_TIME_LVL_HIGH.
831 * @retval None
832 */
833 __STATIC_INLINE void ll_pwm_set_waiting_time_level_c(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
834 {
835 MODIFY_REG(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C, waiting_time_lvl << PWM_MODE_WAITING_TIME_LEVEL_C_POS);
836 }
837
838 /**
839 * @brief Get the channel_c waiting time level in coding mode.
840 *
841 * Register|BitsName
842 * --------|--------
843 * MODE | WAITING_TIME_LEVEL_C
844 *
845 * @param PWMx
846 * @retval Return value of 0 or 1.
847 */
848 __STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_c(pwm_regs_t *PWMx)
849 {
850 return (READ_BITS(PWMx->MODE, PWM_MODE_WAITING_TIME_LEVEL_C) == (PWM_MODE_WAITING_TIME_LEVEL_C));
851 }
852
853 /**
854 * @brief Set DMA enable in coding mode.
855 *
856 * Register|BitsName
857 * --------|--------
858 * MODE | DMA_EN
859 *
860 * @param PWMx
861 * @retval None
862 */
863 __STATIC_INLINE void ll_pwm_set_dma_enable(pwm_regs_t *PWMx)
864 {
865 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x1 << PWM_MODE_DMA_EN_POS);
866 }
867
868 /**
869 * @brief Set DMA disable in coding mode.
870 *
871 * Register|BitsName
872 * --------|--------
873 * MODE | DMA_EN
874 *
875 * @param PWMx
876 * @retval None
877 */
878 __STATIC_INLINE void ll_pwm_set_dma_disable(pwm_regs_t *PWMx)
879 {
880 MODIFY_REG(PWMx->MODE, PWM_MODE_DMA_EN, 0x0 << PWM_MODE_DMA_EN_POS);
881 }
882
883 /**
884 * @brief Get DMA enable or disable.
885 *
886 * Register|BitsName
887 * --------|--------
888 * MODE | DMA_EN
889 *
890 * @param PWMx
891 * @retval Return value of 0 or 1.
892 */
893 __STATIC_INLINE uint8_t ll_pwm_get_dma_en(pwm_regs_t *PWMx)
894 {
895 return (READ_BITS(PWMx->MODE, PWM_MODE_DMA_EN) == (PWM_MODE_DMA_EN));
896 }
897
898 /**
899 * @brief Choose 3 channels operation in coding mode or only choose channel A operation in coding mode.
900 *
901 * Register|BitsName
902 * --------|--------
903 * MODE | CODING_CHANNEL_SELECT
904 *
905 * @param PWMx
906 * @param coding_channel This parameter can be set with LL_PWM_CODING_CHANNEL_ALL or LL_PWM_CODING_CHANNEL_A.
907 * @retval None
908 */
909 __STATIC_INLINE void ll_pwm_coding_channel_select(pwm_regs_t *PWMx, uint8_t coding_channel)
910 {
911 MODIFY_REG(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT, coding_channel << PWM_MODE_CODING_CHANNEL_SELECT_POS);
912 }
913
914 /**
915 * @brief Get PWM coding channel.
916 *
917 * Register|BitsName
918 * --------|--------
919 * MODE | CODING_CHANNEL_SELECT
920 *
921 * @param PWMx
922 * @retval Return value of 0 or 1, 0 represents LL_PWM_CODING_CHANNEL_ALL, 1 represents LL_PWM_CODING_CHANNEL_A
923 */
924 __STATIC_INLINE uint8_t ll_pwm_get_coding_channel(pwm_regs_t *PWMx)
925 {
926 return (READ_BITS(PWMx->MODE, PWM_MODE_CODING_CHANNEL_SELECT) == (PWM_MODE_CODING_CHANNEL_SELECT));
927 }
928
929 /**
930 * @brief Check update active flag
931 *
932 * Register|BitsName
933 * --------|--------
934 * UPDATE | SAG
935 *
936 * @param PWMx PWM instance
937 * @retval State of bit (1 or 0).
938 */
939 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
940 {
941 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
942 }
943
944 /**
945 * @brief Enable update all parameters.
946 *
947 * Register|BitsName
948 * --------|--------
949 * UPDATE | SA
950 *
951 * @param PWMx PWM instance
952 * @retval None
953 */
954 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
955 {
956 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
957 }
958
959 /**
960 * @brief Disable update all parameters.
961 *
962 * Register|BitsName
963 * --------|--------
964 * UPDATE | SA
965 *
966 * @param PWMx PWM instance
967 * @retval None
968 */
969 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
970 {
971 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
972 }
973
974 /**
975 * @brief Indicate whether the update all parameters is enabled.
976 *
977 * Register|BitsName
978 * --------|--------
979 * UPDATE | SA
980 *
981 * @param PWMx PWM instance
982 * @retval State of bit (1 or 0).
983 */
984 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
985 {
986 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
987 }
988
989 /**
990 * @brief Enable update period.
991 *
992 * Register|BitsName
993 * --------|--------
994 * UPDATE | SSPRD
995 *
996 * @param PWMx PWM instance
997 * @retval None
998 */
999 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
1000 {
1001 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
1002 }
1003
1004 /**
1005 * @brief Disable update period.
1006 *
1007 * Register|BitsName
1008 * --------|--------
1009 * UPDATE | SSPRD
1010 *
1011 * @param PWMx PWM instance
1012 * @retval None
1013 */
1014 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
1015 {
1016 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
1017 }
1018
1019 /**
1020 * @brief Indicate whether the update period is enabled.
1021 *
1022 * Register|BitsName
1023 * --------|--------
1024 * UPDATE | SSPRD
1025 *
1026 * @param PWMx PWM instance
1027 * @retval State of bit (1 or 0).
1028 */
1029 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
1030 {
1031 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
1032 }
1033
1034 /**
1035 * @brief Enable update compareA0.
1036 *
1037 * Register|BitsName
1038 * --------|--------
1039 * UPDATE | SSCMPA0
1040 *
1041 * @param PWMx PWM instance
1042 * @retval None
1043 */
1044 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
1045 {
1046 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1047 }
1048
1049 /**
1050 * @brief Disable update compareA0.
1051 *
1052 * Register|BitsName
1053 * --------|--------
1054 * UPDATE | SSCMPA0
1055 *
1056 * @param PWMx PWM instance
1057 * @retval None
1058 */
1059 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
1060 {
1061 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
1062 }
1063
1064 /**
1065 * @brief Indicate whether the update compareA0 is enabled.
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * UPDATE | SSCMPA0
1070 *
1071 * @param PWMx PWM instance
1072 * @retval State of bit (1 or 0).
1073 */
1074 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
1075 {
1076 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
1077 }
1078
1079 /**
1080 * @brief Enable update compareA1.
1081 *
1082 * Register|BitsName
1083 * --------|--------
1084 * UPDATE | SSCMPA1
1085 *
1086 * @param PWMx PWM instance
1087 * @retval None
1088 */
1089 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
1090 {
1091 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1092 }
1093
1094 /**
1095 * @brief Disable update compareA1.
1096 *
1097 * Register|BitsName
1098 * --------|--------
1099 * UPDATE | SSCMPA1
1100 *
1101 * @param PWMx PWM instance
1102 * @retval None
1103 */
1104 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
1105 {
1106 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
1107 }
1108
1109 /**
1110 * @brief Indicate whether the update compareA1 is enabled.
1111 *
1112 * Register|BitsName
1113 * --------|--------
1114 * UPDATE | SSCMPA1
1115 *
1116 * @param PWMx PWM instance
1117 * @retval State of bit (1 or 0).
1118 */
1119 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
1120 {
1121 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
1122 }
1123
1124 /**
1125 * @brief Enable update compareB0.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * UPDATE | SSCMPB0
1130 *
1131 * @param PWMx PWM instance
1132 * @retval None
1133 */
1134 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
1135 {
1136 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1137 }
1138
1139 /**
1140 * @brief Disable update compareB0.
1141 *
1142 * Register|BitsName
1143 * --------|--------
1144 * UPDATE | SSCMPB0
1145 *
1146 * @param PWMx PWM instance
1147 * @retval None
1148 */
1149 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
1150 {
1151 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
1152 }
1153
1154 /**
1155 * @brief Indicate whether the update compareB0 is enabled.
1156 *
1157 * Register|BitsName
1158 * --------|--------
1159 * UPDATE | SSCMPB0
1160 *
1161 * @param PWMx PWM instance
1162 * @retval State of bit (1 or 0).
1163 */
1164 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
1165 {
1166 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
1167 }
1168
1169 /**
1170 * @brief Enable update compareB1.
1171 *
1172 * Register|BitsName
1173 * --------|--------
1174 * UPDATE | SSCMPB1
1175 *
1176 * @param PWMx PWM instance
1177 * @retval None
1178 */
1179 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
1180 {
1181 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1182 }
1183
1184 /**
1185 * @brief Disable update compareB1.
1186 *
1187 * Register|BitsName
1188 * --------|--------
1189 * UPDATE | SSCMPB1
1190 *
1191 * @param PWMx PWM instance
1192 * @retval None
1193 */
1194 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
1195 {
1196 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
1197 }
1198
1199 /**
1200 * @brief Indicate whether the update compareB1 is enabled.
1201 *
1202 * Register|BitsName
1203 * --------|--------
1204 * UPDATE | SSCMPB1
1205 *
1206 * @param PWMx PWM instance
1207 * @retval State of bit (1 or 0).
1208 */
1209 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
1210 {
1211 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
1212 }
1213
1214 /**
1215 * @brief Enable update compareC0.
1216 *
1217 * Register|BitsName
1218 * --------|--------
1219 * UPDATE | SSCMPC0
1220 *
1221 * @param PWMx PWM instance
1222 * @retval None
1223 */
1224 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
1225 {
1226 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1227 }
1228
1229 /**
1230 * @brief Disable update compareC0.
1231 *
1232 * Register|BitsName
1233 * --------|--------
1234 * UPDATE | SSCMPC0
1235 *
1236 * @param PWMx PWM instance
1237 * @retval None
1238 */
1239 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
1240 {
1241 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
1242 }
1243
1244 /**
1245 * @brief Indicate whether the update compareC0 is enabled.
1246 *
1247 * Register|BitsName
1248 * --------|--------
1249 * UPDATE | SSCMPC0
1250 *
1251 * @param PWMx PWM instance
1252 * @retval State of bit (1 or 0).
1253 */
1254 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
1255 {
1256 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
1257 }
1258
1259 /**
1260 * @brief Enable update compareC1.
1261 *
1262 * Register|BitsName
1263 * --------|--------
1264 * UPDATE | SSCMPC1
1265 *
1266 * @param PWMx PWM instance
1267 * @retval None
1268 */
1269 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
1270 {
1271 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1272 }
1273
1274 /**
1275 * @brief Disable update compareC1.
1276 *
1277 * Register|BitsName
1278 * --------|--------
1279 * UPDATE | SSCMPC1
1280 *
1281 * @param PWMx PWM instance
1282 * @retval None
1283 */
1284 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
1285 {
1286 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
1287 }
1288
1289 /**
1290 * @brief Indicate whether the update compareC1 is enabled.
1291 *
1292 * Register|BitsName
1293 * --------|--------
1294 * UPDATE | SSCMPC1
1295 *
1296 * @param PWMx PWM instance
1297 * @retval State of bit (1 or 0).
1298 */
1299 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
1300 {
1301 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
1302 }
1303
1304 /**
1305 * @brief Enable update breath period.
1306 *
1307 * Register|BitsName
1308 * --------|--------
1309 * UPDATE | SSBRPRD
1310 *
1311 * @param PWMx PWM instance
1312 * @retval None
1313 */
1314 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
1315 {
1316 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1317 }
1318
1319 /**
1320 * @brief Disable update breath period.
1321 *
1322 * Register|BitsName
1323 * --------|--------
1324 * UPDATE | SSBRPRD
1325 *
1326 * @param PWMx PWM instance
1327 * @retval None
1328 */
1329 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
1330 {
1331 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
1332 }
1333
1334 /**
1335 * @brief Indicate whether the update breath period is enabled.
1336 *
1337 * Register|BitsName
1338 * --------|--------
1339 * UPDATE | SSBRPRD
1340 *
1341 * @param PWMx PWM instance
1342 * @retval State of bit (1 or 0).
1343 */
1344 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
1345 {
1346 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
1347 }
1348
1349 /**
1350 * @brief Enable update hold period.
1351 *
1352 * Register|BitsName
1353 * --------|--------
1354 * UPDATE | SSHOLD
1355 *
1356 * @param PWMx PWM instance
1357 * @retval None
1358 */
1359 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
1360 {
1361 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1362 }
1363
1364 /**
1365 * @brief Disable update hold period.
1366 *
1367 * Register|BitsName
1368 * --------|--------
1369 * UPDATE | SSHOLD
1370 *
1371 * @param PWMx PWM instance
1372 * @retval None
1373 */
1374 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1375 {
1376 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1377 }
1378
1379 /**
1380 * @brief Indicate whether the update hold period is enabled.
1381 *
1382 * Register|BitsName
1383 * --------|--------
1384 * UPDATE | SSHOLD
1385 *
1386 * @param PWMx PWM instance
1387 * @retval State of bit (1 or 0).
1388 */
1389 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1390 {
1391 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1392 }
1393
1394 /**
1395 * @brief Enable update active event.
1396 *
1397 * Register|BitsName
1398 * --------|--------
1399 * UPDATE | SSAQCTRL
1400 *
1401 * @param PWMx PWM instance
1402 * @retval None
1403 */
1404 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1405 {
1406 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1407 }
1408
1409 /**
1410 * @brief Disable update active event.
1411 *
1412 * Register|BitsName
1413 * --------|--------
1414 * UPDATE | SSAQCTRL
1415 *
1416 * @param PWMx PWM instance
1417 * @retval None
1418 */
1419 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1420 {
1421 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1422 }
1423
1424 /**
1425 * @brief Indicate whether the update active event is enabled.
1426 *
1427 * Register|BitsName
1428 * --------|--------
1429 * UPDATE | SSAQCTRL
1430 *
1431 * @param PWMx PWM instance
1432 * @retval State of bit (1 or 0).
1433 */
1434 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1435 {
1436 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1437 }
1438
1439 /**
1440 * @brief Set the PWM prescaler.
1441 *
1442 * Register|BitsName
1443 * --------|--------
1444 * PRD | PRD
1445 *
1446 * @param PWMx PWM instance
1447 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1448 * @retval None
1449 */
1450 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1451 {
1452 WRITE_REG(PWMx->PRD, prescaler);
1453 }
1454
1455 /**
1456 * @brief Get the PWM prescaler.
1457 *
1458 * Register|BitsName
1459 * --------|--------
1460 * PRD | PRD
1461 *
1462 * @param PWMx PWM instance
1463 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1464 */
1465 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1466 {
1467 return (READ_REG(PWMx->PRD));
1468 }
1469
1470 /**
1471 * @brief Set the PWM compare counter A0.
1472 *
1473 * Register|BitsName
1474 * --------|--------
1475 * CMPA0 | CMPA0
1476 *
1477 * @param PWMx PWM instance
1478 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1479 * @retval None
1480 */
1481 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1482 {
1483 WRITE_REG(PWMx->CMPA0, compare);
1484 }
1485
1486 /**
1487 * @brief Get the PWM compare counter A0.
1488 *
1489 * Register|BitsName
1490 * --------|--------
1491 * CMPA0 | CMPA0
1492 *
1493 * @param PWMx PWM instance
1494 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1495 */
1496 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1497 {
1498 return (READ_REG(PWMx->CMPA0));
1499 }
1500
1501 /**
1502 * @brief Set the PWM compare counter A1.
1503 *
1504 * Register|BitsName
1505 * --------|--------
1506 * CMPA1 | CMPA1
1507 *
1508 * @param PWMx PWM instance
1509 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1510 * @retval None
1511 */
1512 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1513 {
1514 WRITE_REG(PWMx->CMPA1, compare);
1515 }
1516
1517 /**
1518 * @brief Get the PWM compare counter A1.
1519 *
1520 * Register|BitsName
1521 * --------|--------
1522 * CMPA1 | CMPA1
1523 *
1524 * @param PWMx PWM instance
1525 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1526 */
1527 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1528 {
1529 return (READ_REG(PWMx->CMPA1));
1530 }
1531
1532 /**
1533 * @brief Set the PWM compare counter B0.
1534 *
1535 * Register|BitsName
1536 * --------|--------
1537 * CMPB0 | CMPB0
1538 *
1539 * @param PWMx PWM instance
1540 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1541 * @retval None
1542 */
1543 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1544 {
1545 WRITE_REG(PWMx->CMPB0, compare);
1546 }
1547
1548 /**
1549 * @brief Get the PWM compare counter B0.
1550 *
1551 * Register|BitsName
1552 * --------|--------
1553 * CMPB0 | CMPB0
1554 *
1555 * @param PWMx PWM instance
1556 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1557 */
1558 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1559 {
1560 return (READ_REG(PWMx->CMPB0));
1561 }
1562
1563 /**
1564 * @brief Set the PWM compare counter B1.
1565 *
1566 * Register|BitsName
1567 * --------|--------
1568 * CMPB1 | CMPB1
1569 *
1570 * @param PWMx PWM instance
1571 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1572 * @retval None
1573 */
1574 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1575 {
1576 WRITE_REG(PWMx->CMPB1, compare);
1577 }
1578
1579 /**
1580 * @brief Get the PWM compare counter B1.
1581 *
1582 * Register|BitsName
1583 * --------|--------
1584 * CMPB1 | CMPB1
1585 *
1586 * @param PWMx PWM instance
1587 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1588 */
1589 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1590 {
1591 return (READ_REG(PWMx->CMPB1));
1592 }
1593
1594 /**
1595 * @brief Set the PWM compare counter C0.
1596 *
1597 * Register|BitsName
1598 * --------|--------
1599 * CMPC0 | CMPC0
1600 *
1601 * @param PWMx PWM instance
1602 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1603 * @retval None
1604 */
1605 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1606 {
1607 WRITE_REG(PWMx->CMPC0, compare);
1608 }
1609
1610 /**
1611 * @brief Get the PWM compare counter C0.
1612 *
1613 * Register|BitsName
1614 * --------|--------
1615 * CMPC0 | CMPC0
1616 *
1617 * @param PWMx PWM instance
1618 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1619 */
1620 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1621 {
1622 return (READ_REG(PWMx->CMPC0));
1623 }
1624
1625 /**
1626 * @brief Set the PWM compare counter C1.
1627 *
1628 * Register|BitsName
1629 * --------|--------
1630 * CMPC1 | CMPC1
1631 *
1632 * @param PWMx PWM instance
1633 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1634 * @retval None
1635 */
1636 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1637 {
1638 WRITE_REG(PWMx->CMPC1, compare);
1639 }
1640
1641 /**
1642 * @brief Get the PWM compare counter C1.
1643 *
1644 * Register|BitsName
1645 * --------|--------
1646 * CMPC1 | CMPC1
1647 *
1648 * @param PWMx PWM instance
1649 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1650 */
1651 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1652 {
1653 return (READ_REG(PWMx->CMPC1));
1654 }
1655
1656 /**
1657 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1658 *
1659 * Register|BitsName
1660 * --------|--------
1661 * AQCTRL | A0
1662 *
1663 * @param PWMx PWM instance
1664 * @param action_event This parameter can be one of the following values:
1665 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1666 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1667 * @arg @ref LL_PWM_ACTIONEVENT_SET
1668 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1669 * @retval None
1670 */
1671 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1672 {
1673 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_POS);
1674 }
1675
1676 /**
1677 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1678 *
1679 * Register|BitsName
1680 * --------|--------
1681 * AQCTRL | A0
1682 *
1683 * @param PWMx PWM instance
1684 * @retval Return value can be one of the following values:
1685 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1686 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1687 * @arg @ref LL_PWM_ACTIONEVENT_SET
1688 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1689 */
1690 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1691 {
1692 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_POS);
1693 }
1694
1695 /**
1696 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1697 *
1698 * Register|BitsName
1699 * --------|--------
1700 * AQCTRL | A1
1701 *
1702 * @param PWMx PWM instance
1703 * @param action_event This parameter can be one of the following values:
1704 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1705 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1706 * @arg @ref LL_PWM_ACTIONEVENT_SET
1707 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1708 * @retval None
1709 */
1710 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1711 {
1712 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_POS);
1713 }
1714
1715 /**
1716 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1717 *
1718 * Register|BitsName
1719 * --------|--------
1720 * AQCTRL | A1
1721 *
1722 * @param PWMx PWM instance
1723 * @retval Return value can be one of the following values:
1724 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1725 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1726 * @arg @ref LL_PWM_ACTIONEVENT_SET
1727 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1728 */
1729 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1730 {
1731 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_POS);
1732 }
1733
1734 /**
1735 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1736 *
1737 * Register|BitsName
1738 * --------|--------
1739 * AQCTRL | B0
1740 *
1741 * @param PWMx PWM instance
1742 * @param action_event This parameter can be one of the following values:
1743 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1744 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1745 * @arg @ref LL_PWM_ACTIONEVENT_SET
1746 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1747 * @retval None
1748 */
1749 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1750 {
1751 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_POS);
1752 }
1753
1754 /**
1755 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1756 *
1757 * Register|BitsName
1758 * --------|--------
1759 * AQCTRL | B0
1760 *
1761 * @param PWMx PWM instance
1762 * @retval Return value can be one of the following values:
1763 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1764 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1765 * @arg @ref LL_PWM_ACTIONEVENT_SET
1766 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1767 */
1768 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1769 {
1770 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_POS);
1771 }
1772
1773 /**
1774 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1775 *
1776 * Register|BitsName
1777 * --------|--------
1778 * AQCTRL | B1
1779 *
1780 * @param PWMx PWM instance
1781 * @param action_event This parameter can be one of the following values:
1782 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1783 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1784 * @arg @ref LL_PWM_ACTIONEVENT_SET
1785 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1786 * @retval None
1787 */
1788 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1789 {
1790 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_POS);
1791 }
1792
1793 /**
1794 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1795 *
1796 * Register|BitsName
1797 * --------|--------
1798 * AQCTRL | B1
1799 *
1800 * @param PWMx PWM instance
1801 * @retval Return value can be one of the following values:
1802 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1803 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1804 * @arg @ref LL_PWM_ACTIONEVENT_SET
1805 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1806 */
1807 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1808 {
1809 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_POS);
1810 }
1811
1812 /**
1813 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1814 *
1815 * Register|BitsName
1816 * --------|--------
1817 * AQCTRL | C0
1818 *
1819 * @param PWMx PWM instance
1820 * @param action_event This parameter can be one of the following values:
1821 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1822 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1823 * @arg @ref LL_PWM_ACTIONEVENT_SET
1824 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1825 * @retval None
1826 */
1827 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1828 {
1829 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_POS);
1830 }
1831
1832 /**
1833 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1834 *
1835 * Register|BitsName
1836 * --------|--------
1837 * AQCTRL | C0
1838 *
1839 * @param PWMx PWM instance
1840 * @retval Return value can be one of the following values:
1841 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1842 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1843 * @arg @ref LL_PWM_ACTIONEVENT_SET
1844 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1845 */
1846 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1847 {
1848 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_POS);
1849 }
1850
1851 /**
1852 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1853 *
1854 * Register|BitsName
1855 * --------|--------
1856 * AQCTRL | C1
1857 *
1858 * @param PWMx PWM instance
1859 * @param action_event This parameter can be one of the following values:
1860 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1861 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1862 * @arg @ref LL_PWM_ACTIONEVENT_SET
1863 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1864 * @retval None
1865 */
1866 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1867 {
1868 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_POS);
1869 }
1870
1871 /**
1872 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1873 *
1874 * Register|BitsName
1875 * --------|--------
1876 * AQCTRL | C1
1877 *
1878 * @param PWMx PWM instance
1879 * @retval Return value can be one of the following values:
1880 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1881 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1882 * @arg @ref LL_PWM_ACTIONEVENT_SET
1883 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1884 */
1885 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1886 {
1887 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_POS);
1888 }
1889
1890 /**
1891 * @brief Set the breath prescaler in breath mode.
1892 *
1893 * Register|BitsName
1894 * --------|--------
1895 * BRPRD | BRPRD
1896 *
1897 * @param PWMx PWM instance
1898 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1899 * @retval None
1900 */
1901 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1902 {
1903 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1904 }
1905
1906 /**
1907 * @brief Get the breath prescaler in breath mode.
1908 *
1909 * Register|BitsName
1910 * --------|--------
1911 * BRPRD | BRPRD
1912 *
1913 * @param PWMx PWM instance
1914 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1915 */
1916 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1917 {
1918 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1919 }
1920
1921 /**
1922 * @brief Set the hold prescaler in breath mode.
1923 *
1924 * Register|BitsName
1925 * --------|--------
1926 * HOLD | HOLD
1927 *
1928 * @param PWMx PWM instance
1929 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1930 * @retval None
1931 */
1932 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1933 {
1934 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1935 }
1936
1937 /**
1938 * @brief Get the hold prescaler in breath mode.
1939 *
1940 * Register|BitsName
1941 * --------|--------
1942 * HOLD | HOLD
1943 *
1944 * @param PWMx PWM instance
1945 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1946 */
1947 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1948 {
1949 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1950 }
1951
1952 /**
1953 * @brief Set the stop level in breath mode.
1954 *
1955 * Register|BitsName
1956 * --------|--------
1957 * MODE | BREATH_PAUSE_LEVEL
1958 *
1959 * @param PWMx PWM breath stop level
1960 * @param breathstop_lvl This parameter can be set with 0 or 1.
1961 * @retval None
1962 */
1963 __STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
1964 {
1965 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL, breathstop_lvl << PWM_MODE_BREATH_PAUSE_LEVEL_POS);
1966 }
1967
1968 /**
1969 * @brief Get the stop level in breath mode.
1970 *
1971 * Register|BitsName
1972 * --------|--------
1973 * MODE | BREATH_PAUSE_LEVEL
1974 *
1975 * @param PWMx PWM breath stop level
1976 * @retval Return value of 0 or 1.
1977 */
1978 __STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
1979 {
1980 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATH_PAUSE_LEVEL));
1981 }
1982
1983 /**
1984 * @brief Set the number of PWM period cycle in flicker mode or coding mode.
1985 *
1986 * Register|BitsName
1987 * --------|--------
1988 * PRD_CYCLES | PRD_CYCLES
1989 *
1990 * @param PWMx
1991 * @param prd_cycles This parameter control the number of period cycles, when set to 0 will continuously generate waveform.
1992 * @retval None.
1993 */
1994 __STATIC_INLINE void ll_pwm_set_prd_cycles(pwm_regs_t *PWMx, uint32_t prd_cycles)
1995 {
1996 WRITE_REG(PWMx->PRD_CYCLES, prd_cycles);
1997 }
1998
1999 /**
2000 * @brief Get the number of PWM period cycle.
2001 *
2002 * Register|BitsName
2003 * --------|--------
2004 * PRD_CYCLES | PRD_CYCLES
2005 *
2006 * @param PWMx
2007 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
2008 */
2009 __STATIC_INLINE uint32_t ll_pwm_get_prd_cycles(pwm_regs_t *PWMx)
2010 {
2011 return (READ_REG(PWMx->PRD_CYCLES));
2012 }
2013
2014 /**
2015 * @brief Set the waiting time count in coding mode.
2016 *
2017 * Register|BitsName
2018 * --------|--------
2019 * WAIT_TIME | WAIT_TIME
2020 *
2021 * @param PWMx
2022 * @param waiting_time This parameter control PWM waiting time in the coding mode.
2023 * @retval None.
2024 */
2025 __STATIC_INLINE void ll_pwm_set_waiting_time(pwm_regs_t *PWMx, uint32_t waiting_time)
2026 {
2027 WRITE_REG(PWMx->WAIT_TIME, waiting_time);
2028 }
2029
2030 /**
2031 * @brief Get the waiting time count.
2032 *
2033 * Register|BitsName
2034 * --------|--------
2035 * WAIT_TIME | WAIT_TIME
2036 *
2037 * @param PWMx
2038 * @retval Return count value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF.
2039 */
2040 __STATIC_INLINE uint32_t ll_pwm_get_waiting_time(pwm_regs_t *PWMx)
2041 {
2042 return (READ_REG(PWMx->WAIT_TIME));
2043 }
2044
2045 /**
2046 * @brief Set the valid coding data width in coding mode.
2047 *
2048 * Register|BitsName
2049 * --------|--------
2050 * DATA_WIDTH_VALID | DATA_WIDTH_VALID
2051 *
2052 * @param PWMx
2053 * @param data_valid_width This parameter control coding data valid width = DATA_WIDTH_VALID + 1,
2054 * DATA_WIDTH_VALID value ranges between Min_Data = 0x0 and Max_Data = 0x1F.
2055 * @retval None.
2056 */
2057 __STATIC_INLINE void ll_pwm_set_data_width_valid(pwm_regs_t *PWMx, uint8_t data_valid_width)
2058 {
2059 MODIFY_REG(PWMx->DATA_WIDTH_VALID, PWM_DATA_WIDTH_VALID, data_valid_width << PWM_DATA_WIDTH_VALID_POS);
2060 }
2061
2062 /**
2063 * @brief Get the valid coding data width.
2064 *
2065 * Register|BitsName
2066 * --------|--------
2067 * DATA_WIDTH_VALID | DATA_WIDTH_VALID
2068 *
2069 * @param PWMx
2070 * @retval Return the valid data width in coding mode
2071 */
2072 __STATIC_INLINE uint8_t ll_pwm_get_data_width_valid(pwm_regs_t *PWMx)
2073 {
2074 return (uint8_t)(READ_REG(PWMx->DATA_WIDTH_VALID) & PWM_DATA_WIDTH_VALID);
2075 }
2076
2077 /**
2078 * @brief Set the PWM coding data in coding mode.
2079 *
2080 * Register|BitsName
2081 * --------|--------
2082 * CODING_DATA | CODING_DATA
2083 *
2084 * @param PWMx
2085 * @param coding_data This parameter control PWM generate waveform by coding data.
2086 * @retval None.
2087 */
2088 __STATIC_INLINE void ll_pwm_set_coding_data(pwm_regs_t *PWMx, uint32_t coding_data)
2089 {
2090 WRITE_REG(PWMx->CODING_DATA, coding_data);
2091 }
2092
2093 /**
2094 * @brief Get the PWM coding data in coding mode.
2095 *
2096 * Register|BitsName
2097 * --------|--------
2098 * CODING_DATA | CODING_DATA
2099 *
2100 * @param PWMx
2101 * @retval Return the coding_data value in coding mode.
2102 */
2103 __STATIC_INLINE uint32_t ll_pwm_get_coding_data(pwm_regs_t *PWMx)
2104 {
2105 return (READ_REG(PWMx->CODING_DATA));
2106 }
2107
2108 /**
2109 * @brief Get pwm coding status
2110 *
2111 * Register|BitsName
2112 * --------|--------
2113 * CODING_STATUS | CODING_STATUS
2114 *
2115 * @param PWMx
2116 * @retval Return the pwm coding status
2117 */
2118 __STATIC_INLINE uint32_t ll_pwm_get_coding_status(pwm_regs_t *PWMx)
2119 {
2120 return (READ_REG(PWMx->CODING_STATUS));
2121 }
2122
2123 /**
2124 * @brief Clear pwma coding error status.
2125 *
2126 * Register|BitsName
2127 * --------|--------
2128 * CLR_CODING_STATUS | CODING_A_ERROR_CLR
2129 *
2130 * @param PWMx
2131 * @retval None.
2132 */
2133 __STATIC_INLINE void ll_pwm_clr_coding_a_error_status(pwm_regs_t *PWMx)
2134 {
2135 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_A_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_A_ERROR_CLR_POS);
2136 }
2137
2138 /**
2139 * @brief Get pwma coding error status
2140 *
2141 * Register|BitsName
2142 * --------|--------
2143 * CODING_STATUS | CODING_A_ERROR
2144 *
2145 * @param PWMx
2146 * @retval Return the pwma coding error status
2147 */
2148 __STATIC_INLINE uint8_t ll_pwm_get_coding_a_error_status(pwm_regs_t *PWMx)
2149 {
2150 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_A_ERROR) == (PWM_CODING_STATUS_CODING_A_ERROR));
2151 }
2152
2153 /**
2154 * @brief Clear pwmb coding error status.
2155 *
2156 * Register|BitsName
2157 * --------|--------
2158 * CLR_CODING_STATUS | CODING_B_ERROR_CLR
2159 *
2160 * @param PWMx
2161 * @retval None.
2162 */
2163 __STATIC_INLINE void ll_pwm_clr_coding_b_error_status(pwm_regs_t *PWMx)
2164 {
2165 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_B_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_B_ERROR_CLR_POS);
2166 }
2167
2168 /**
2169 * @brief Get pwmb coding error status
2170 *
2171 * Register|BitsName
2172 * --------|--------
2173 * CODING_STATUS | CODING_B_ERROR
2174 *
2175 * @param PWMx
2176 * @retval Return the pwmb coding error status
2177 */
2178 __STATIC_INLINE uint8_t ll_pwm_get_coding_b_error_status(pwm_regs_t *PWMx)
2179 {
2180 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_B_ERROR) == (PWM_CODING_STATUS_CODING_B_ERROR));
2181 }
2182
2183 /**
2184 * @brief Clear pwmc coding error status.
2185 *
2186 * Register|BitsName
2187 * --------|--------
2188 * CLR_CODING_STATUS | CODING_C_ERROR_CLR
2189 *
2190 * @param PWMx
2191 * @retval None.
2192 */
2193 __STATIC_INLINE void ll_pwm_clr_coding_c_error_status(pwm_regs_t *PWMx)
2194 {
2195 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_C_ERROR_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_C_ERROR_CLR_POS);
2196 }
2197
2198 /**
2199 * @brief Get pwmc coding error status
2200 *
2201 * Register|BitsName
2202 * --------|--------
2203 * CODING_STATUS | CODING_C_ERROR
2204 *
2205 * @param PWMx
2206 * @retval Return the pwmc coding error status
2207 */
2208 __STATIC_INLINE uint8_t ll_pwm_get_coding_c_error_status(pwm_regs_t *PWMx)
2209 {
2210 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_C_ERROR) == (PWM_CODING_STATUS_CODING_C_ERROR));
2211 }
2212
2213 /**
2214 * @brief Clear coding done status.
2215 *
2216 * Register|BitsName
2217 * --------|--------
2218 * CLR_CODING_STATUS | CODING_DONE_CLR
2219 *
2220 * @param PWMx
2221 * @retval None.
2222 */
2223 __STATIC_INLINE void ll_pwm_clr_coding_done_status(pwm_regs_t *PWMx)
2224 {
2225 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_DONE_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_DONE_CLR_POS);
2226 }
2227
2228 /**
2229 * @brief Get PWM conding done status
2230 *
2231 * Register|BitsName
2232 * --------|--------
2233 * CODING_STATUS | CODING_DONE
2234 *
2235 * @param PWMx
2236 * @retval Return the coding done interrupt status
2237 */
2238 __STATIC_INLINE uint8_t ll_pwm_get_coding_done_status(pwm_regs_t *PWMx)
2239 {
2240 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_DONE) == (PWM_CODING_STATUS_CODING_DONE));
2241 }
2242
2243 /**
2244 * @brief Clear coding load status.
2245 *
2246 * Register|BitsName
2247 * --------|--------
2248 * CLR_CODING_STATUS | CODING_LAOD_CLR
2249 *
2250 * @param PWMx
2251 * @retval None.
2252 */
2253 __STATIC_INLINE void ll_pwm_clr_coding_load_status(pwm_regs_t *PWMx)
2254 {
2255 MODIFY_REG(PWMx->CLR_CODING_STATUS, PWM_CLR_CODING_STATUS_CODING_LOAD_CLR, 0x1 << PWM_CLR_CODING_STATUS_CODING_LOAD_CLR_POS);
2256 }
2257
2258 /**
2259 * @brief Get PWM conding load status
2260 *
2261 * Register|BitsName
2262 * --------|--------
2263 * CODING_STATUS | CODING_LOAD
2264 *
2265 * @param PWMx
2266 * @retval Return the coding load interrupt status
2267 */
2268 __STATIC_INLINE uint8_t ll_pwm_get_coding_load_status(pwm_regs_t *PWMx)
2269 {
2270 return (READ_BITS(PWMx->CODING_STATUS, PWM_CODING_STATUS_CODING_LOAD) == (PWM_CODING_STATUS_CODING_LOAD));
2271 }
2272
2273 /**
2274 * @brief Get the coding data register address used for DMA transfer
2275 *
2276 * Register|BitsName
2277 * --------|--------
2278 * MODE | CODING_DATA
2279 *
2280 * @param PWMx
2281 * @retval Address of coding data register
2282 */
2283 __STATIC_INLINE uint32_t ll_pwm_dma_get_register_address(pwm_regs_t *PWMx)
2284 {
2285 return ((uint32_t) &(PWMx->CODING_DATA));
2286 }
2287
2288 /** @} */
2289
2290 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
2291 * @{
2292 */
2293
2294 /**
2295 * @brief De-initialize PWM registers (Registers restored to their default values).
2296 * @param PWMx PWM instance
2297 * @retval An error_status_t enumeration value:
2298 * - SUCCESS: PWM registers are de-initialized
2299 * - ERROR: PWM registers are not de-initialized
2300 */
2301 void ll_pwm_deinit(pwm_regs_t *PWMx);
2302
2303 /**
2304 * @brief Initialize PWM registers according to the specified
2305 * parameters in PWM_InitStruct.
2306 * @param PWMx PWM instance
2307 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
2308 * information for the specified PWM peripheral.
2309 * @retval An error_status_t enumeration value:
2310 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
2311 * - ERROR: Problem occurred during PWM Registers initialization
2312 */
2313 void ll_pwm_init(pwm_regs_t *PWMx, const ll_pwm_init_t *p_pwm_init);
2314
2315 /**
2316 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
2317 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
2318 * whose fields will be set to default values.
2319 * @retval None
2320 */
2321 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
2322
2323 /** @} */
2324
2325 /** @} */
2326
2327 #endif /* PWM0 || PWM1 */
2328
2329 #ifdef __cplusplus
2330 }
2331 #endif
2332
2333 #endif /* _LL_PWM_H__ */
2334
2335 /** @} */
2336
2337 /** @} */
2338
2339 /** @} */
_ll_pwm_none_coding_channel_init_t::drive_polarity
uint8_t drive_polarity
Definition: ll_pwm.h:98
ll_pwm_disable_update_compare_c1
__STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
Disable update compareC1.
Definition: ll_pwm.h:1284
ll_pwm_is_enabled_positive_drive_channel_b
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelB is enabled.
Definition: ll_pwm.h:617
ll_pwm_set_compare_c0
__STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C0.
Definition: ll_pwm.h:1605
ll_pwm_set_action_event_cmp_b0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: ll_pwm.h:1749
ll_pwm_get_compare_c0
__STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
Get the PWM compare counter C0.
Definition: ll_pwm.h:1620
ll_pwm_set_mode
__STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, ll_pwm_mode_t mode)
Set PWM mode.
Definition: ll_pwm.h:496
_ll_pwm_coding_channel_init_t::ll_comp1
uint32_t ll_comp1
Definition: ll_pwm.h:116
ll_pwm_get_prd_cycles
__STATIC_INLINE uint32_t ll_pwm_get_prd_cycles(pwm_regs_t *PWMx)
Get the number of PWM period cycle.
Definition: ll_pwm.h:2009
ll_pwm_set_compare_c1
__STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter C1.
Definition: ll_pwm.h:1636
ll_pwm_set_compare_a0
__STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A0.
Definition: ll_pwm.h:1481
ll_pwm_get_flicker_stop_level_c
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_c(pwm_regs_t *PWMx)
Get the channel_c stop level in flicker mode.
Definition: ll_pwm.h:755
ll_pwm_get_dma_en
__STATIC_INLINE uint8_t ll_pwm_get_dma_en(pwm_regs_t *PWMx)
Get DMA enable or disable.
Definition: ll_pwm.h:893
ll_pwm_get_action_event_cmp_c1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
Get the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: ll_pwm.h:1885
ll_pwm_get_coding_status
__STATIC_INLINE uint32_t ll_pwm_get_coding_status(pwm_regs_t *PWMx)
Get pwm coding status.
Definition: ll_pwm.h:2118
ll_pwm_dma_get_register_address
__STATIC_INLINE uint32_t ll_pwm_dma_get_register_address(pwm_regs_t *PWMx)
Get the coding data register address used for DMA transfer.
Definition: ll_pwm.h:2283
ll_pwm_set_data_width_valid
__STATIC_INLINE void ll_pwm_set_data_width_valid(pwm_regs_t *PWMx, uint8_t data_valid_width)
Set the valid coding data width in coding mode.
Definition: ll_pwm.h:2057
_ll_pwm_init_t
LL PWM init Structure definition.
Definition: ll_pwm.h:199
_ll_pwm_none_coding_mode_init_t::hprescaler
uint32_t hprescaler
Definition: ll_pwm.h:149
ll_pwm_disable_update_active_event
__STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
Disable update active event.
Definition: ll_pwm.h:1419
ll_pwm_disable_update_compare_b0
__STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
Disable update compareB0.
Definition: ll_pwm.h:1149
ll_pwm_set_dma_disable
__STATIC_INLINE void ll_pwm_set_dma_disable(pwm_regs_t *PWMx)
Set DMA disable in coding mode.
Definition: ll_pwm.h:878
ll_pwm_none_coding_mode_init_t
struct _ll_pwm_none_coding_mode_init_t ll_pwm_none_coding_mode_init_t
LL PWM none coding mode Structure definition.
ll_pwm_get_waiting_time
__STATIC_INLINE uint32_t ll_pwm_get_waiting_time(pwm_regs_t *PWMx)
Get the waiting time count.
Definition: ll_pwm.h:2040
ll_pwm_enable_update_all
__STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
Enable update all parameters.
Definition: ll_pwm.h:954
_ll_pwm_none_coding_mode_init_t::channel_c
ll_pwm_none_coding_channel_init_t channel_c
Definition: ll_pwm.h:163
ll_pwm_get_coding_c_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_c_error_status(pwm_regs_t *PWMx)
Get pwmc coding error status.
Definition: ll_pwm.h:2208
_ll_pwm_init_t::none_coding_mode_cfg
ll_pwm_none_coding_mode_init_t none_coding_mode_cfg
Definition: ll_pwm.h:208
_ll_pwm_init_t::ll_prd_cycles
uint32_t ll_prd_cycles
Definition: ll_pwm.h:205
_ll_pwm_coding_mode_init_t::ll_period
uint32_t ll_period
Definition: ll_pwm.h:172
ll_pwm_get_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
Get the PWM prescaler.
Definition: ll_pwm.h:1465
ll_pwm_get_coding_done_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_done_status(pwm_regs_t *PWMx)
Get PWM conding done status.
Definition: ll_pwm.h:2238
LL_PWM_BREATH_MODE
@ LL_PWM_BREATH_MODE
Definition: ll_pwm.h:73
_ll_pwm_none_coding_channel_init_t::duty
uint8_t duty
Definition: ll_pwm.h:95
ll_pwm_set_waiting_time_level_a
__STATIC_INLINE void ll_pwm_set_waiting_time_level_a(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_a waiting time level in coding mode.
Definition: ll_pwm.h:771
_ll_pwm_none_coding_mode_init_t::breathstop_lvl
uint32_t breathstop_lvl
Definition: ll_pwm.h:154
ll_pwm_get_compare_a0
__STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
Get the PWM compare counter A0.
Definition: ll_pwm.h:1496
ll_pwm_get_breath_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
Get the breath prescaler in breath mode.
Definition: ll_pwm.h:1916
_ll_pwm_init_t::ll_mode
ll_pwm_mode_t ll_mode
Definition: ll_pwm.h:200
_ll_pwm_coding_channel_init_t::ll_drive_polarity
uint8_t ll_drive_polarity
Definition: ll_pwm.h:119
ll_pwm_coding_channel_init_t
struct _ll_pwm_coding_channel_init_t ll_pwm_coding_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_disable_update_hold_period
__STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
Disable update hold period.
Definition: ll_pwm.h:1374
ll_pwm_clr_coding_b_error_status
__STATIC_INLINE void ll_pwm_clr_coding_b_error_status(pwm_regs_t *PWMx)
Clear pwmb coding error status.
Definition: ll_pwm.h:2163
ll_pwm_get_data_width_valid
__STATIC_INLINE uint8_t ll_pwm_get_data_width_valid(pwm_regs_t *PWMx)
Get the valid coding data width.
Definition: ll_pwm.h:2072
_ll_pwm_none_coding_mode_init_t::bprescaler
uint32_t bprescaler
Definition: ll_pwm.h:143
ll_pwm_is_enabled_update_compare_b1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
Indicate whether the update compareB1 is enabled.
Definition: ll_pwm.h:1209
ll_pwm_enable_update_active_event
__STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
Enable update active event.
Definition: ll_pwm.h:1404
_ll_pwm_init_t::coding_mode_cfg
ll_pwm_coding_mode_init_t coding_mode_cfg
Definition: ll_pwm.h:211
ll_pwm_set_action_event_cmp_a0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: ll_pwm.h:1671
ll_pwm_set_compare_a1
__STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter A1.
Definition: ll_pwm.h:1512
ll_pwm_get_mode
__STATIC_INLINE ll_pwm_mode_t ll_pwm_get_mode(pwm_regs_t *PWMx)
Get PWM mode.
Definition: ll_pwm.h:523
ll_pwm_get_compare_b1
__STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
Get the PWM compare counter B1.
Definition: ll_pwm.h:1589
ll_pwm_init
void ll_pwm_init(pwm_regs_t *PWMx, const ll_pwm_init_t *p_pwm_init)
Initialize PWM registers according to the specified parameters in PWM_InitStruct.
ll_pwm_is_enabled_update_all
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
Indicate whether the update all parameters is enabled.
Definition: ll_pwm.h:984
ll_pwm_set_action_event_cmp_b1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: ll_pwm.h:1788
ll_pwm_is_enabled
__STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
Indicate whether the PWM is enabled.
Definition: ll_pwm.h:432
ll_pwm_disable_update_compare_c0
__STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
Disable update compareC0.
Definition: ll_pwm.h:1239
ll_pwm_get_action_event_cmp_b0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
Get the channel B0 action event when PWM counter value reaches compare counter B0.
Definition: ll_pwm.h:1768
ll_pwm_disable_update_compare_a1
__STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
Disable update compareA1.
Definition: ll_pwm.h:1104
ll_pwm_enable_pause
__STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
Enable PWM pause.
Definition: ll_pwm.h:447
ll_pwm_set_coding_data
__STATIC_INLINE void ll_pwm_set_coding_data(pwm_regs_t *PWMx, uint32_t coding_data)
Set the PWM coding data in coding mode.
Definition: ll_pwm.h:2088
ll_pwm_is_enabled_update_active_event
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
Indicate whether the update active event is enabled.
Definition: ll_pwm.h:1434
ll_pwm_is_enabled_update_compare_a0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
Indicate whether the update compareA0 is enabled.
Definition: ll_pwm.h:1074
ll_pwm_is_enabled_update_compare_b0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
Indicate whether the update compareB0 is enabled.
Definition: ll_pwm.h:1164
_ll_pwm_none_coding_mode_init_t
LL PWM none coding mode Structure definition.
Definition: ll_pwm.h:133
ll_pwm_get_compare_b0
__STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
Get the PWM compare counter B0.
Definition: ll_pwm.h:1558
ll_pwm_enable_update_period
__STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
Enable update period.
Definition: ll_pwm.h:999
_ll_pwm_coding_mode_init_t::ll_channel_a
ll_pwm_coding_channel_init_t ll_channel_a
Definition: ll_pwm.h:185
ll_pwm_enable_update_hold_period
__STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
Enable update hold period.
Definition: ll_pwm.h:1359
ll_pwm_set_breath_stop_level
__STATIC_INLINE void ll_pwm_set_breath_stop_level(pwm_regs_t *PWMx, uint32_t breathstop_lvl)
Set the stop level in breath mode.
Definition: ll_pwm.h:1963
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_pwm_set_flicker_stop_level_b
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_b(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_b stop level in flicker mode.
Definition: ll_pwm.h:709
ll_pwm_set_breath_prescaler
__STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
Set the breath prescaler in breath mode.
Definition: ll_pwm.h:1901
ll_pwm_get_breath_stop_level
__STATIC_INLINE uint32_t ll_pwm_get_breath_stop_level(pwm_regs_t *PWMx)
Get the stop level in breath mode.
Definition: ll_pwm.h:1978
ll_pwm_clr_coding_done_status
__STATIC_INLINE void ll_pwm_clr_coding_done_status(pwm_regs_t *PWMx)
Clear coding done status.
Definition: ll_pwm.h:2223
ll_pwm_is_enabled_pause
__STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
Indicate whether the PWM pause is enabled.
Definition: ll_pwm.h:477
_ll_pwm_coding_channel_init_t::ll_waiting_time_lvl
uint8_t ll_waiting_time_lvl
Definition: ll_pwm.h:124
ll_pwm_enable_update_compare_c1
__STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
Enable update compareC1.
Definition: ll_pwm.h:1269
_ll_pwm_coding_channel_init_t::ll_comp0
uint32_t ll_comp0
Definition: ll_pwm.h:113
LL_PWM_FLICKER_MODE
@ LL_PWM_FLICKER_MODE
Definition: ll_pwm.h:72
ll_pwm_disable_update_compare_b1
__STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
Disable update compareB1.
Definition: ll_pwm.h:1194
ll_pwm_disable_pause
__STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
Disable PWM pause.
Definition: ll_pwm.h:462
ll_pwm_get_coding_a_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_a_error_status(pwm_regs_t *PWMx)
Get pwma coding error status.
Definition: ll_pwm.h:2148
_ll_pwm_coding_mode_init_t::ll_coding_channel_select
uint8_t ll_coding_channel_select
Definition: ll_pwm.h:182
ll_pwm_is_enabled_positive_drive_channel_a
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelA is enabled.
Definition: ll_pwm.h:572
ll_pwm_set_action_event_cmp_c1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C1 action event when PWM counter value reaches compare counter C1.
Definition: ll_pwm.h:1866
ll_pwm_get_compare_a1
__STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
Get the PWM compare counter A1.
Definition: ll_pwm.h:1527
ll_pwm_set_prd_cycles
__STATIC_INLINE void ll_pwm_set_prd_cycles(pwm_regs_t *PWMx, uint32_t prd_cycles)
Set the number of PWM period cycle in flicker mode or coding mode.
Definition: ll_pwm.h:1994
ll_pwm_none_coding_channel_init_t
struct _ll_pwm_none_coding_channel_init_t ll_pwm_none_coding_channel_init_t
LL PWM Output Channel init Structure definition.
ll_pwm_get_coding_data
__STATIC_INLINE uint32_t ll_pwm_get_coding_data(pwm_regs_t *PWMx)
Get the PWM coding data in coding mode.
Definition: ll_pwm.h:2103
_ll_pwm_coding_mode_init_t::ll_data_width_valid
uint8_t ll_data_width_valid
Definition: ll_pwm.h:178
ll_pwm_get_coding_load_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_load_status(pwm_regs_t *PWMx)
Get PWM conding load status.
Definition: ll_pwm.h:2268
ll_pwm_is_enabled_update_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
Indicate whether the update period is enabled.
Definition: ll_pwm.h:1029
LL_PWM_CODING_MODE
@ LL_PWM_CODING_MODE
Definition: ll_pwm.h:74
ll_pwm_is_enabled_update_breath_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
Indicate whether the update breath period is enabled.
Definition: ll_pwm.h:1344
ll_pwm_enable_update_compare_b0
__STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
Enable update compareB0.
Definition: ll_pwm.h:1134
ll_pwm_set_waiting_time
__STATIC_INLINE void ll_pwm_set_waiting_time(pwm_regs_t *PWMx, uint32_t waiting_time)
Set the waiting time count in coding mode.
Definition: ll_pwm.h:2025
_ll_pwm_coding_mode_init_t::ll_waiting_time
uint32_t ll_waiting_time
Definition: ll_pwm.h:175
ll_pwm_enable_update_compare_b1
__STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
Enable update compareB1.
Definition: ll_pwm.h:1179
ll_pwm_get_waiting_time_level_b
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_b(pwm_regs_t *PWMx)
Get the channel_b waiting time level in coding mode.
Definition: ll_pwm.h:817
ll_pwm_disable_update_period
__STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
Disable update period.
Definition: ll_pwm.h:1014
ll_pwm_get_hold_prescaler
__STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
Get the hold prescaler in breath mode.
Definition: ll_pwm.h:1947
ll_pwm_disable_update_compare_a0
__STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
Disable update compareA0.
Definition: ll_pwm.h:1059
ll_pwm_set_flicker_stop_level_c
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_c(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_c stop level in flicker mode.
Definition: ll_pwm.h:740
ll_pwm_enable_update_breath_period
__STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
Enable update breath period.
Definition: ll_pwm.h:1314
ll_pwm_enable_update_compare_a0
__STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
Enable update compareA0.
Definition: ll_pwm.h:1044
ll_pwm_is_enabled_update_hold_period
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
Indicate whether the update hold period is enabled.
Definition: ll_pwm.h:1389
ll_pwm_set_waiting_time_level_c
__STATIC_INLINE void ll_pwm_set_waiting_time_level_c(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_c waiting time level in coding mode.
Definition: ll_pwm.h:833
ll_pwm_get_action_event_cmp_a1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
Get the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: ll_pwm.h:1729
ll_pwm_disable_update_all
__STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
Disable update all parameters.
Definition: ll_pwm.h:969
ll_pwm_is_active_flag_update_all
__STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
Check update active flag.
Definition: ll_pwm.h:939
ll_pwm_clr_coding_load_status
__STATIC_INLINE void ll_pwm_clr_coding_load_status(pwm_regs_t *PWMx)
Clear coding load status.
Definition: ll_pwm.h:2253
ll_pwm_set_hold_prescaler
__STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
Set the hold prescaler in breath mode.
Definition: ll_pwm.h:1932
ll_pwm_is_enabled_update_compare_c0
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
Indicate whether the update compareC0 is enabled.
Definition: ll_pwm.h:1254
ll_pwm_disable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
Disable positive drive mode in channelC.
Definition: ll_pwm.h:647
_ll_pwm_coding_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: ll_pwm.h:112
_ll_pwm_none_coding_mode_init_t::channel_a
ll_pwm_none_coding_channel_init_t channel_a
Definition: ll_pwm.h:157
ll_pwm_set_compare_b1
__STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B1.
Definition: ll_pwm.h:1574
ll_pwm_is_enabled_update_compare_c1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
Indicate whether the update compareC1 is enabled.
Definition: ll_pwm.h:1299
_ll_pwm_none_coding_mode_init_t::prescaler
uint32_t prescaler
Definition: ll_pwm.h:137
ll_pwm_enable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
Enable positive drive mode in channelB.
Definition: ll_pwm.h:587
ll_pwm_enable
__STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
Enable PWM.
Definition: ll_pwm.h:402
ll_pwm_disable_positive_drive_channel_b
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
Disable positive drive mode in channelB.
Definition: ll_pwm.h:602
ll_pwm_disable
__STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
Disable PWM.
Definition: ll_pwm.h:417
ll_pwm_get_flicker_stop_level_a
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_a(pwm_regs_t *PWMx)
Get the channel_a stop level in flicker mode.
Definition: ll_pwm.h:693
ll_pwm_set_compare_b0
__STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
Set the PWM compare counter B0.
Definition: ll_pwm.h:1543
ll_pwm_get_waiting_time_level_c
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_c(pwm_regs_t *PWMx)
Get the channel_c waiting time level in coding mode.
Definition: ll_pwm.h:848
ll_pwm_set_flicker_stop_level_a
__STATIC_INLINE void ll_pwm_set_flicker_stop_level_a(pwm_regs_t *PWMx, uint32_t flickerstop_lvl)
Set the channel_a stop level in flicker mode.
Definition: ll_pwm.h:678
ll_pwm_disable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
Disable positive drive mode in channelA.
Definition: ll_pwm.h:557
_ll_pwm_none_coding_channel_init_t::flickerstop_lvl
uint32_t flickerstop_lvl
Definition: ll_pwm.h:104
_ll_pwm_none_coding_channel_init_t
LL PWM Output Channel init Structure definition.
Definition: ll_pwm.h:94
_ll_pwm_coding_mode_init_t
LL PWM coding mode Structure definition.
Definition: ll_pwm.h:171
ll_pwm_set_waiting_time_level_b
__STATIC_INLINE void ll_pwm_set_waiting_time_level_b(pwm_regs_t *PWMx, uint8_t waiting_time_lvl)
Set the channel_b waiting time level in coding mode.
Definition: ll_pwm.h:802
ll_pwm_set_action_event_cmp_c0
__STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: ll_pwm.h:1827
ll_pwm_enable_positive_drive_channel_c
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
Enable positive drive mode in channelC.
Definition: ll_pwm.h:632
ll_pwm_set_action_event_cmp_a1
__STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
Set the channel A1 action event when PWM counter value reaches compare counter A1.
Definition: ll_pwm.h:1710
_ll_pwm_coding_mode_init_t::ll_channel_b
ll_pwm_coding_channel_init_t ll_channel_b
Definition: ll_pwm.h:188
ll_pwm_get_flicker_stop_level_b
__STATIC_INLINE uint32_t ll_pwm_get_flicker_stop_level_b(pwm_regs_t *PWMx)
Get the channel_b stop level in flicker mode.
Definition: ll_pwm.h:724
ll_pwm_init_t
struct _ll_pwm_init_t ll_pwm_init_t
LL PWM init Structure definition.
ll_pwm_struct_init
void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init)
Set each field of a ll_pwm_init_t type structure to default value.
ll_pwm_get_compare_c1
__STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
Get the PWM compare counter C1.
Definition: ll_pwm.h:1651
ll_pwm_get_waiting_time_level_a
__STATIC_INLINE uint8_t ll_pwm_get_waiting_time_level_a(pwm_regs_t *PWMx)
Get the channel_a waiting time level in coding mode.
Definition: ll_pwm.h:786
_ll_pwm_coding_mode_init_t::ll_channel_c
ll_pwm_coding_channel_init_t ll_channel_c
Definition: ll_pwm.h:191
ll_pwm_disable_update_breath_period
__STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
Disable update breath period.
Definition: ll_pwm.h:1329
_ll_pwm_none_coding_mode_init_t::align
uint32_t align
Definition: ll_pwm.h:134
ll_pwm_set_dma_enable
__STATIC_INLINE void ll_pwm_set_dma_enable(pwm_regs_t *PWMx)
Set DMA enable in coding mode.
Definition: ll_pwm.h:863
ll_pwm_clr_coding_c_error_status
__STATIC_INLINE void ll_pwm_clr_coding_c_error_status(pwm_regs_t *PWMx)
Clear pwmc coding error status.
Definition: ll_pwm.h:2193
ll_pwm_get_coding_b_error_status
__STATIC_INLINE uint8_t ll_pwm_get_coding_b_error_status(pwm_regs_t *PWMx)
Get pwmb coding error status.
Definition: ll_pwm.h:2178
ll_pwm_get_action_event_cmp_a0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
Get the channel A0 action event when PWM counter value reaches compare counter A0.
Definition: ll_pwm.h:1690
ll_pwm_enable_update_compare_a1
__STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
Enable update compareA1.
Definition: ll_pwm.h:1089
ll_pwm_set_prescaler
__STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
Set the PWM prescaler.
Definition: ll_pwm.h:1450
_ll_pwm_none_coding_mode_init_t::channel_b
ll_pwm_none_coding_channel_init_t channel_b
Definition: ll_pwm.h:160
ll_pwm_deinit
void ll_pwm_deinit(pwm_regs_t *PWMx)
De-initialize PWM registers (Registers restored to their default values).
ll_pwm_get_action_event_cmp_b1
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
Get the channel B1 action event when PWM counter value reaches compare counter B1.
Definition: ll_pwm.h:1807
ll_pwm_enable_update_compare_c0
__STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
Enable update compareC0.
Definition: ll_pwm.h:1224
ll_pwm_is_enabled_positive_drive_channel_c
__STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
Indicate whether the positive drive mode in channelC is enabled.
Definition: ll_pwm.h:662
ll_pwm_clr_coding_a_error_status
__STATIC_INLINE void ll_pwm_clr_coding_a_error_status(pwm_regs_t *PWMx)
Clear pwma coding error status.
Definition: ll_pwm.h:2133
ll_pwm_coding_channel_select
__STATIC_INLINE void ll_pwm_coding_channel_select(pwm_regs_t *PWMx, uint8_t coding_channel)
Choose 3 channels operation in coding mode or only choose channel A operation in coding mode.
Definition: ll_pwm.h:909
ll_pwm_is_enabled_update_compare_a1
__STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
Indicate whether the update compareA1 is enabled.
Definition: ll_pwm.h:1119
ll_pwm_get_action_event_cmp_c0
__STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
Get the channel C0 action event when PWM counter value reaches compare counter C0.
Definition: ll_pwm.h:1846
ll_pwm_enable_positive_drive_channel_a
__STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
Enable positive drive mode in channelA.
Definition: ll_pwm.h:542
ll_pwm_coding_mode_init_t
struct _ll_pwm_coding_mode_init_t ll_pwm_coding_mode_init_t
LL PWM coding mode Structure definition.
ll_pwm_mode_t
uint8_t ll_pwm_mode_t
Definition: ll_pwm.h:77
ll_pwm_get_coding_channel
__STATIC_INLINE uint8_t ll_pwm_get_coding_channel(pwm_regs_t *PWMx)
Get PWM coding channel.
Definition: ll_pwm.h:924