ll_dma.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef LL_DMA_H
53 #define LL_DMA_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5405.h"
61
62 #if defined (DMA0)
63
64
65 /** @defgroup DMA_LL_STRUCTURES Structures
66 * @{
67 */
68
69 /* Exported types ------------------------------------------------------------*/
70 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
71 * @{
72 */
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init
77 {
78 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
79
80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
81
82 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory or form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
93 This parameter can be a value of @ref DMA_LL_EC_SOURCE
94
95 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_increment_mode(). */
96
97 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
98 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
99
100 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_increment_mode(). */
101
102 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
103 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
104
105 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_width(). */
106
107 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
108 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
109
110 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_width(). */
111
112 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
113 The data unit is equal to the source buffer configuration set in src_data_width parameters.
114 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFF
115
116 This feature can be modified afterwards using unitary function @ref ll_dma_set_block_size(). */
117
118 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
119 This parameter can be a value of @ref DMA_LL_EC_PERIPH
120
121 This feature can be modified afterwards using unitary function @ref ll_dma_set_source_peripheral(). */
122
123 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
124 This parameter can be a value of @ref DMA_LL_EC_PERIPH
125
126 This feature can be modified afterwards using unitary function @ref ll_dma_set_destination_peripheral(). */
127
128 uint32_t priority; /**< Specifies the channel priority level.
129 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
130
131 This feature can be modified afterwards using unitary function @ref ll_dma_set_channel_priority_level(). */
132 } ll_dma_init_t;
133
134 /** @} */
135
136 /** @} */
137
138 /**
139 * @defgroup DMA_LL_MACRO Defines
140 * @{
141 */
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
145 * @{
146 */
147
148 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
149 * @{
150 */
151 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
152 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
153 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
154 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
155 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
156 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all (used only for function @ref ll_dma_deinit(). */
157 /** @} */
158
159 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
160 * @{
161 */
162 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
163 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
164 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
165 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
166 /** @} */
167
168 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
169 * @{
170 */
171 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
172 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
173 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
174 /** @} */
175
176 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
177 * @{
178 */
179 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
180 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
181 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
182 /** @} */
183
184 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
185 * @{
186 */
187 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
188 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
189 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
190 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
191 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
192 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
193 #define LL_DMA_SRC_BURST_LENGTH_128 DMA_CTLL_SRC_MSIZE_128 /**< Source Burst length: 128 words */
194 #define LL_DMA_SRC_BURST_LENGTH_256 DMA_CTLL_SRC_MSIZE_256 /**< Source Burst length: 256 words */
195 /** @} */
196
197 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
198 * @{
199 */
200 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
201 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
202 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
203 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
204 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
205 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
206 #define LL_DMA_DST_BURST_LENGTH_128 DMA_CTLL_DST_MSIZE_128 /**< Destination Burst length: 128 words */
207 #define LL_DMA_DST_BURST_LENGTH_256 DMA_CTLL_DST_MSIZE_256 /**< Destination Burst length: 256 words */
208 /** @} */
209
210 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
211 * @{
212 */
213 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
214 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
215 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
216 /** @} */
217
218 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
219 * @{
220 */
221 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
222 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
223 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
224 /** @} */
225
226 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
227 * @{
228 */
229 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
230 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
231 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
232 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
233 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
234 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
235 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
236 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
237 /** @} */
238
239 /** @defgroup DMA_LL_EC_CHANNEL_LOCK_ENABLE Channel lock enable
240 * @{
241 */
242 #define LL_DMA_LOCK_CH_ENABLE DMA_CFGL_LOCK_CH_ENABLE /**< DMA Channel Lock Enable */
243 #define LL_DMA_LOCK_CH_DSIBALE DMA_CFGL_LOCK_CH_DISABLE /**< DMA Channel Lock DIsable */
244 /** @} */
245
246 /** @defgroup DMA_LL_EC_CHANNEL_LOCK_LEVEL Channel lock level
247 * @{
248 */
249 #define LL_DMA_LOCK_CH_LEVEL_TFR DMA_CFGL_LOCK_CH_L_TFR /**< Over complete DMA transfer */
250 #define LL_DMA_LOCK_CH_LEVEL_BLK DMA_CFGL_LOCK_CH_L_BLK /**< Over complete DMA block transfer */
251 #define LL_DMA_LOCK_CH_LEVEL_TRANS DMA_CFGL_LOCK_CH_L_TRANS /**< Over complete DMA transaction */
252 /** @} */
253
254 /** @defgroup DMA_LL_EC_BUS_LOCK_ENABLE Bus lock enable
255 * @{
256 */
257 #define LL_DMA_LOCK_BUS_ENABLE DMA_CFGL_LOCK_B_ENABLE /**< DMA Bus Lock Enable */
258 #define LL_DMA_LOCK_BUS_DSIBALE DMA_CFGL_LOCK_B_DISABLE /**< DMA Bus Lock DIsable */
259 /** @} */
260
261 /** @defgroup DMA_LL_EC_BUS_LOCK_LEVEL Bus lock level
262 * @{
263 */
264 #define LL_DMA_LOCK_BUS_LEVEL_TFR DMA_CFGL_LOCK_B_L_TFR /**< Over complete DMA transfer */
265 #define LL_DMA_LOCK_BUS_LEVEL_BLK DMA_CFGL_LOCK_B_L_BLK /**< Over complete DMA block transfer */
266 #define LL_DMA_LOCK_BUS_LEVEL_TRANS DMA_CFGL_LOCK_B_L_TRANS /**< Over complete DMA transaction */
267 /** @} */
268
269 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
270 * @{
271 */
272 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
273 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
274 /** @} */
275
276 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
277 * @{
278 */
279 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
280 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
281 /** @} */
282
283 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
284 * @{
285 */
286 /********************************* definition for DMA0 **************************************/
287 #define LL_DMA0_PERIPH_MEM ((uint32_t)0x0000000BU) /**< DMA peripheral type is Memory */
288
289 /********************************* definition for DMA0 HS0 **************************************/
290 #define LL_DMA0_PERIPH_CTE ((uint32_t)0x00000000U) /**< DMA Peripheral type is CTE */
291 #define LL_DMA0_PERIPH_PWM0 ((uint32_t)0x00000001U) /**< DMA Peripheral type is PWM0 */
292 #define LL_DMA0_PERIPH_SPIM_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIM TX */
293 #define LL_DMA0_PERIPH_SPIM_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIM RX */
294 #define LL_DMA0_PERIPH_SPIS_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is SPIS TX */
295 #define LL_DMA0_PERIPH_SPIS_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is SPIS RX */
296 #define LL_DMA0_PERIPH_UART0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is UART0 TX */
297 #define LL_DMA0_PERIPH_UART0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is UART0 RX */
298 #define LL_DMA0_PERIPH_UART1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is UART1 TX */
299 #define LL_DMA0_PERIPH_UART1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is UART1 RX */
300 #define LL_DMA0_PERIPH_SNSADC ((uint32_t)0x0000000AU) /**< DMA peripheral type is SNSADC */
301 #define LL_DMA0_PERIPH_I2C0_TX ((uint32_t)0x0000000CU) /**< DMA peripheral type is I2C0 TX */
302 #define LL_DMA0_PERIPH_I2C0_RX ((uint32_t)0x0000000DU) /**< DMA peripheral type is I2C0 RX */
303 #define LL_DMA0_PERIPH_I2C1_TX ((uint32_t)0x0000000EU) /**< DMA peripheral type is I2C1 TX */
304 #define LL_DMA0_PERIPH_I2C1_RX ((uint32_t)0x0000000FU) /**< DMA peripheral type is I2C1 RX */
305
306 /** @} */
307
308 /** @} */
309
310 /* Exported macro ------------------------------------------------------------*/
311 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
312 * @{
313 */
314
315 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
316 * @{
317 */
318
319 /**
320 * @brief Write a value in DMA register
321 * @param __instance__ DMA instance
322 * @param __REG__ Register to be written
323 * @param __VALUE__ Value to be written in the register
324 * @retval None
325 */
326 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
327
328 /**
329 * @brief Read a value in DMA register
330 * @param __instance__ DMA instance
331 * @param __REG__ Register to be read
332 * @retval Register value
333 */
334 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
335
336 /** @} */
337
338 /** @} */
339
340 /** @} */
341
342 /* Exported functions --------------------------------------------------------*/
343 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
344 * @{
345 */
346
347 /** @defgroup DMA_LL_EF_Configuration Configuration functions
348 * @{
349 */
350
351 /**
352 * @brief Enable DMA Module.
353 * @note This function is used to enable the DMA Module, which must be done before any
354 * channel activity can begin.
355 *
356 * Register|BitsName
357 * --------|--------
358 * CFG_REG | CFG_EN
359 *
360 * @param DMAx DMA instance.
361 * @retval None
362 */
363 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
364 {
365 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
366 }
367
368 /**
369 * @brief Disable DMA Module.
370 * @note If the ll_dma_disable() function is called while any dma channel is still active,
371 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
372 * still active until hardware has terminated all cativity on all channels, at which
373 * point the ll_dma_is_enable() function returns 0.
374 *
375 * Register|BitsName
376 * --------|--------
377 * CFG_REG | CFG_EN
378 *
379 * @param DMAx DMA instance.
380 * @retval None
381 */
382 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
383 {
384 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
385 }
386
387 /**
388 * @brief Check if DMA Module is enabled or disabled.
389 *
390 * Register|BitsName
391 * --------|--------
392 * CFG_REG | CFG_EN
393 *
394 * @param DMAx DMA instance.
395 * @retval State of bit (1 or 0).
396 */
397 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
398 {
399 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
400 }
401
402 /**
403 * @brief Enable DMA channel.
404 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
405 * is ignored and call ll_dma_disable_channel() function will always returns 0.
406 *
407 * Register|BitsName
408 * --------|--------
409 * CH_EN_REG | CH_EN_WE&CH_EN
410 *
411 * @param DMAx DMA instance.
412 * @param channel This parameter can be one of the following values:
413 * @arg @ref LL_DMA_CHANNEL_0
414 * @arg @ref LL_DMA_CHANNEL_1
415 * @arg @ref LL_DMA_CHANNEL_2
416 * @arg @ref LL_DMA_CHANNEL_3
417 * @arg @ref LL_DMA_CHANNEL_4
418 * @retval None
419 */
420 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
421 {
422 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
423 }
424
425 /**
426 * @brief Disable DMA channel.
427 *
428 * Register|BitsName
429 * --------|--------
430 * CH_EN_REG | CH_EN_WE&CH_EN
431 *
432 * @param DMAx DMA instance.
433 * @param channel This parameter can be one of the following values:
434 * @arg @ref LL_DMA_CHANNEL_0
435 * @arg @ref LL_DMA_CHANNEL_1
436 * @arg @ref LL_DMA_CHANNEL_2
437 * @arg @ref LL_DMA_CHANNEL_3
438 * @arg @ref LL_DMA_CHANNEL_4
439 * @retval None
440 */
441 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
442 {
443 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
444 }
445
446 /**
447 * @brief Check if DMA channel is enabled or disabled.
448 * @note Software can therefore poll this function to determine when channel is free
449 * for a new DMA transfer.
450 *
451 * Register|BitsName
452 * --------|--------
453 * CH_EN_REG | CH_EN_WE&CH_EN
454 *
455 * @param DMAx DMA instance.
456 * @param channel This parameter can be one of the following values:
457 * @arg @ref LL_DMA_CHANNEL_0
458 * @arg @ref LL_DMA_CHANNEL_1
459 * @arg @ref LL_DMA_CHANNEL_2
460 * @arg @ref LL_DMA_CHANNEL_3
461 * @arg @ref LL_DMA_CHANNEL_4
462 * @retval State of bit (1 or 0).
463 */
464 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
465 {
466 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
467 }
468
469 /**
470 * @brief Suspend a DMA channel transfer.
471 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
472 * function is called. The function may be called after enabling the DMA channel.
473 *
474 * Register|BitsName
475 * --------|--------
476 * CFGL | CH_SUSP
477 *
478 * @param DMAx DMA instance.
479 * @param channel This parameter can be one of the following values:
480 * @arg @ref LL_DMA_CHANNEL_0
481 * @arg @ref LL_DMA_CHANNEL_1
482 * @arg @ref LL_DMA_CHANNEL_2
483 * @arg @ref LL_DMA_CHANNEL_3
484 * @arg @ref LL_DMA_CHANNEL_4
485 * @retval None
486 */
487 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
488 {
489 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
490 }
491
492 /**
493 * @brief Resume a DMA channel.
494 * @note The function may be called after enabling the DMA channel.
495 *
496 * Register|BitsName
497 * --------|--------
498 * CFGL | CH_SUSP
499 *
500 * @param DMAx DMA instance.
501 * @param channel This parameter can be one of the following values:
502 * @arg @ref LL_DMA_CHANNEL_0
503 * @arg @ref LL_DMA_CHANNEL_1
504 * @arg @ref LL_DMA_CHANNEL_2
505 * @arg @ref LL_DMA_CHANNEL_3
506 * @arg @ref LL_DMA_CHANNEL_4
507 * @retval None
508 */
509 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
510 {
511 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
512 }
513
514 /**
515 * @brief Check if DMA channel is suspended or resumed.
516 *
517 * Register|BitsName
518 * --------|--------
519 * CFGL | CH_SUSP
520 *
521 * @param DMAx DMA instance.
522 * @param channel This parameter can be one of the following values:
523 * @arg @ref LL_DMA_CHANNEL_0
524 * @arg @ref LL_DMA_CHANNEL_1
525 * @arg @ref LL_DMA_CHANNEL_2
526 * @arg @ref LL_DMA_CHANNEL_3
527 * @arg @ref LL_DMA_CHANNEL_4
528 * @retval State of bit (1 or 0).
529 */
530 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
531 {
532 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
533 }
534
535 /**
536 * @brief Check if DMA channel FIFO is empty.
537 *
538 * Register|BitsName
539 * --------|--------
540 * CFGL | FIFO_EMPTY
541 *
542 * @param DMAx DMA instance.
543 * @param channel This parameter can be one of the following values:
544 * @arg @ref LL_DMA_CHANNEL_0
545 * @arg @ref LL_DMA_CHANNEL_1
546 * @arg @ref LL_DMA_CHANNEL_2
547 * @arg @ref LL_DMA_CHANNEL_3
548 * @arg @ref LL_DMA_CHANNEL_4
549 * @retval State of bit (1 or 0).
550 */
551 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
552 {
553 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
554 }
555
556 /**
557 * @brief Configure all parameters link to DMA transfer.
558 *
559 * Register|BitsName
560 * --------|--------
561 * CCR | DIR
562 * CCR | MEM2MEM
563 * CCR | CIRC
564 * CCR | PINC
565 * CCR | MINC
566 * CCR | PSIZE
567 * CCR | MSIZE
568 * CCR | PL
569 *
570 * @param DMAx DMAx instance
571 * @param channel This parameter can be one of the following values:
572 * @arg @ref LL_DMA_CHANNEL_0
573 * @arg @ref LL_DMA_CHANNEL_1
574 * @arg @ref LL_DMA_CHANNEL_2
575 * @arg @ref LL_DMA_CHANNEL_3
576 * @arg @ref LL_DMA_CHANNEL_4
577 * @param configuration This parameter must be a combination of all the following values:
578 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
579 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
580 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
581 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
582 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
583 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
584 * @retval None
585 */
586 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
587 {
588 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH |\
589 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC, configuration);
590 }
591
592 /**
593 * @brief Set Data transfer direction (read from peripheral or from memory).
594 *
595 * Register|BitsName
596 * --------|--------
597 * CTL_LO | TT_FC
598 *
599 * @param DMAx DMAx instance
600 * @param channel This parameter can be one of the following values:
601 * @arg @ref LL_DMA_CHANNEL_0
602 * @arg @ref LL_DMA_CHANNEL_1
603 * @arg @ref LL_DMA_CHANNEL_2
604 * @arg @ref LL_DMA_CHANNEL_3
605 * @arg @ref LL_DMA_CHANNEL_4
606 * @param direction This parameter can be one of the following values:
607 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
608 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
609 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
610 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
611 * @retval None
612 */
613 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
614 {
615 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
616 }
617
618 /**
619 * @brief Get Data transfer direction (read from peripheral or from memory).
620 *
621 * Register|BitsName
622 * --------|--------
623 * CTL_LO | TT_FC
624 *
625 * @param DMAx DMAx instance
626 * @param channel This parameter can be one of the following values:
627 * @arg @ref LL_DMA_CHANNEL_0
628 * @arg @ref LL_DMA_CHANNEL_1
629 * @arg @ref LL_DMA_CHANNEL_2
630 * @arg @ref LL_DMA_CHANNEL_3
631 * @arg @ref LL_DMA_CHANNEL_4
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
634 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
635 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
636 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
637 */
638 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
639 {
640 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
641 }
642
643 /**
644 * @brief Set Source increment mode.
645 *
646 * Register|BitsName
647 * --------|--------
648 * CTL_LO | SINC
649 *
650 * @param DMAx DMAx instance
651 * @param channel This parameter can be one of the following values:
652 * @arg @ref LL_DMA_CHANNEL_0
653 * @arg @ref LL_DMA_CHANNEL_1
654 * @arg @ref LL_DMA_CHANNEL_2
655 * @arg @ref LL_DMA_CHANNEL_3
656 * @arg @ref LL_DMA_CHANNEL_4
657 * @param src_increment_mode This parameter can be one of the following values:
658 * @arg @ref LL_DMA_SRC_INCREMENT
659 * @arg @ref LL_DMA_SRC_DECREMENT
660 * @arg @ref LL_DMA_SRC_NO_CHANGE
661 * @retval None
662 */
663 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
664 {
665 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
666 }
667
668 /**
669 * @brief Get Source increment mode.
670 *
671 * Register|BitsName
672 * --------|--------
673 * CTL_LO | SINC
674 *
675 * @param DMAx DMAx instance
676 * @param channel This parameter can be one of the following values:
677 * @arg @ref LL_DMA_CHANNEL_0
678 * @arg @ref LL_DMA_CHANNEL_1
679 * @arg @ref LL_DMA_CHANNEL_2
680 * @arg @ref LL_DMA_CHANNEL_3
681 * @arg @ref LL_DMA_CHANNEL_4
682 * @retval Returned value can be one of the following values:
683 * @arg @ref LL_DMA_SRC_INCREMENT
684 * @arg @ref LL_DMA_SRC_DECREMENT
685 * @arg @ref LL_DMA_SRC_NO_CHANGE
686 */
687 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
688 {
689 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
690 }
691
692 /**
693 * @brief Set Destination increment mode.
694 *
695 * Register|BitsName
696 * --------|--------
697 * CTL_LO | DINC
698 *
699 * @param DMAx DMAx instance
700 * @param channel This parameter can be one of the following values:
701 * @arg @ref LL_DMA_CHANNEL_0
702 * @arg @ref LL_DMA_CHANNEL_1
703 * @arg @ref LL_DMA_CHANNEL_2
704 * @arg @ref LL_DMA_CHANNEL_3
705 * @arg @ref LL_DMA_CHANNEL_4
706 * @param dst_increment_mode This parameter can be one of the following values:
707 * @arg @ref LL_DMA_DST_INCREMENT
708 * @arg @ref LL_DMA_DST_DECREMENT
709 * @arg @ref LL_DMA_DST_NO_CHANGE
710 * @retval None
711 */
712 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
713 {
714 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
715 }
716
717 /**
718 * @brief Get Destination increment mode.
719 *
720 * Register|BitsName
721 * --------|--------
722 * CTL_LO | DINC
723 *
724 * @param DMAx DMAx instance
725 * @param channel This parameter can be one of the following values:
726 * @arg @ref LL_DMA_CHANNEL_0
727 * @arg @ref LL_DMA_CHANNEL_1
728 * @arg @ref LL_DMA_CHANNEL_2
729 * @arg @ref LL_DMA_CHANNEL_3
730 * @arg @ref LL_DMA_CHANNEL_4
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_DMA_DST_INCREMENT
733 * @arg @ref LL_DMA_DST_DECREMENT
734 * @arg @ref LL_DMA_DST_NO_CHANGE
735 */
736 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
737 {
738 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
739 }
740
741 /**
742 * @brief Set Source transfer width.
743 *
744 * Register|BitsName
745 * --------|--------
746 * CTL_LO | SRC_TR_WIDTH
747 *
748 * @param DMAx DMAx instance
749 * @param channel This parameter can be one of the following values:
750 * @arg @ref LL_DMA_CHANNEL_0
751 * @arg @ref LL_DMA_CHANNEL_1
752 * @arg @ref LL_DMA_CHANNEL_2
753 * @arg @ref LL_DMA_CHANNEL_3
754 * @arg @ref LL_DMA_CHANNEL_4
755 * @param src_width This parameter can be one of the following values:
756 * @arg @ref LL_DMA_SDATAALIGN_BYTE
757 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
758 * @arg @ref LL_DMA_SDATAALIGN_WORD
759 * @retval None
760 */
761 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
762 {
763 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
764 }
765
766 /**
767 * @brief Get Source transfer width.
768 *
769 * Register|BitsName
770 * --------|--------
771 * CTL_LO | SRC_TR_WIDTH
772 *
773 * @param DMAx DMAx instance
774 * @param channel This parameter can be one of the following values:
775 * @arg @ref LL_DMA_CHANNEL_0
776 * @arg @ref LL_DMA_CHANNEL_1
777 * @arg @ref LL_DMA_CHANNEL_2
778 * @arg @ref LL_DMA_CHANNEL_3
779 * @arg @ref LL_DMA_CHANNEL_4
780 * @retval Returned value can be one of the following values:
781 * @arg @ref LL_DMA_SDATAALIGN_BYTE
782 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
783 * @arg @ref LL_DMA_SDATAALIGN_WORD
784 */
785 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
786 {
787 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
788 }
789
790 /**
791 * @brief Set Destination transfer width.
792 *
793 * Register|BitsName
794 * --------|--------
795 * CTL_LO | DST_TR_WIDTH
796 *
797 * @param DMAx DMAx instance
798 * @param channel This parameter can be one of the following values:
799 * @arg @ref LL_DMA_CHANNEL_0
800 * @arg @ref LL_DMA_CHANNEL_1
801 * @arg @ref LL_DMA_CHANNEL_2
802 * @arg @ref LL_DMA_CHANNEL_3
803 * @arg @ref LL_DMA_CHANNEL_4
804 * @param dst_width This parameter can be one of the following values:
805 * @arg @ref LL_DMA_DDATAALIGN_BYTE
806 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
807 * @arg @ref LL_DMA_DDATAALIGN_WORD
808 * @retval None
809 */
810 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
811 {
812 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
813 }
814
815 /**
816 * @brief Get Destination transfer width.
817 *
818 * Register|BitsName
819 * --------|--------
820 * CTL_LO | DST_TR_WIDTH
821 *
822 * @param DMAx DMAx instance
823 * @param channel This parameter can be one of the following values:
824 * @arg @ref LL_DMA_CHANNEL_0
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @retval Returned value can be one of the following values:
830 * @arg @ref LL_DMA_DDATAALIGN_BYTE
831 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
832 * @arg @ref LL_DMA_DDATAALIGN_WORD
833 */
834 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
835 {
836 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
837 }
838
839 /**
840 * @brief Set Source Burst Transaction Length.
841 *
842 * Register|BitsName
843 * --------|--------
844 * CTL_LO | SRC_MSIZE
845 *
846 * @param DMAx DMAx instance
847 * @param channel This parameter can be one of the following values:
848 * @arg @ref LL_DMA_CHANNEL_0
849 * @arg @ref LL_DMA_CHANNEL_1
850 * @arg @ref LL_DMA_CHANNEL_2
851 * @arg @ref LL_DMA_CHANNEL_3
852 * @arg @ref LL_DMA_CHANNEL_4
853 * @param burst_length This parameter can be one of the following values:
854 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
855 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
856 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
857 * @retval None
858 */
859 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
860 {
861 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
862 }
863
864 /**
865 * @brief Get Burst Transaction Length.
866 *
867 * Register|BitsName
868 * --------|--------
869 * CTL_LO | SRC_MSIZE
870 *
871 * @param DMAx DMAx instance
872 * @param channel This parameter can be one of the following values:
873 * @arg @ref LL_DMA_CHANNEL_0
874 * @arg @ref LL_DMA_CHANNEL_1
875 * @arg @ref LL_DMA_CHANNEL_2
876 * @arg @ref LL_DMA_CHANNEL_3
877 * @arg @ref LL_DMA_CHANNEL_4
878 * @retval Returned value can be one of the following values:
879 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
880 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
881 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
882 */
883 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
884 {
885 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
886 }
887
888 /**
889 * @brief Set Destination Burst Transaction Length.
890 *
891 * Register|BitsName
892 * --------|--------
893 * CTL_LO | DST_MSIZE
894 *
895 * @param DMAx DMAx instance
896 * @param channel This parameter can be one of the following values:
897 * @arg @ref LL_DMA_CHANNEL_0
898 * @arg @ref LL_DMA_CHANNEL_1
899 * @arg @ref LL_DMA_CHANNEL_2
900 * @arg @ref LL_DMA_CHANNEL_3
901 * @arg @ref LL_DMA_CHANNEL_4
902 * @param burst_length This parameter can be one of the following values:
903 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
904 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
905 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
906 * @retval None
907 */
908 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
909 {
910 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
911 }
912
913 /**
914 * @brief Get Destination Burst Transaction Length.
915 *
916 * Register|BitsName
917 * --------|--------
918 * CTL_LO | DST_MSIZE
919 *
920 * @param DMAx DMAx instance
921 * @param channel This parameter can be one of the following values:
922 * @arg @ref LL_DMA_CHANNEL_0
923 * @arg @ref LL_DMA_CHANNEL_1
924 * @arg @ref LL_DMA_CHANNEL_2
925 * @arg @ref LL_DMA_CHANNEL_3
926 * @arg @ref LL_DMA_CHANNEL_4
927 * @retval Returned value can be one of the following values:
928 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
929 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
930 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
931 */
932 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
933 {
934 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
935 }
936
937 /**
938 * @brief Set Channel priority level.
939 *
940 * Register|BitsName
941 * --------|--------
942 * CFG_LO | CH_PRIOR
943 *
944 * @param DMAx DMAx instance
945 * @param channel This parameter can be one of the following values:
946 * @arg @ref LL_DMA_CHANNEL_0
947 * @arg @ref LL_DMA_CHANNEL_1
948 * @arg @ref LL_DMA_CHANNEL_2
949 * @arg @ref LL_DMA_CHANNEL_3
950 * @arg @ref LL_DMA_CHANNEL_4
951 * @param priority This parameter can be one of the following values:
952 * @arg @ref LL_DMA_PRIORITY_0
953 * @arg @ref LL_DMA_PRIORITY_1
954 * @arg @ref LL_DMA_PRIORITY_2
955 * @arg @ref LL_DMA_PRIORITY_3
956 * @arg @ref LL_DMA_PRIORITY_4
957 * @retval None
958 */
959 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
960 {
961 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
962 }
963
964 /**
965 * @brief Get Channel priority level.
966 *
967 * Register|BitsName
968 * --------|--------
969 * CFG_LO | CH_PRIOR
970 *
971 * @param DMAx DMAx instance
972 * @param channel This parameter can be one of the following values:
973 * @arg @ref LL_DMA_CHANNEL_0
974 * @arg @ref LL_DMA_CHANNEL_1
975 * @arg @ref LL_DMA_CHANNEL_2
976 * @arg @ref LL_DMA_CHANNEL_3
977 * @arg @ref LL_DMA_CHANNEL_4
978 * @retval Returned value can be one of the following values:
979 * @arg @ref LL_DMA_PRIORITY_0
980 * @arg @ref LL_DMA_PRIORITY_1
981 * @arg @ref LL_DMA_PRIORITY_2
982 * @arg @ref LL_DMA_PRIORITY_3
983 * @arg @ref LL_DMA_PRIORITY_4
984 */
985 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
986 {
987 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
988 }
989
990 /**
991 * @brief Set the block size of a transfer.
992 * @note This action has no effect if channel is enabled.
993 *
994 * Register|BitsName
995 * --------|--------
996 * CTL_HI | BLOCK_TS
997 *
998 * @param DMAx DMAx instance
999 * @param channel This parameter can be one of the following values:
1000 * @arg @ref LL_DMA_CHANNEL_0
1001 * @arg @ref LL_DMA_CHANNEL_1
1002 * @arg @ref LL_DMA_CHANNEL_2
1003 * @arg @ref LL_DMA_CHANNEL_3
1004 * @arg @ref LL_DMA_CHANNEL_4
1005 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1006 * @retval None
1007 */
1008 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1009 {
1010 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1011 }
1012
1013 /**
1014 * @brief Get the block size of a transfer.
1015 * @note Once the channel is enabled, the return value indicate the
1016 * remaining bytes to be transmitted.
1017 *
1018 * Register|BitsName
1019 * --------|--------
1020 * CTL_HI | BLOCK_TS
1021 *
1022 * @param DMAx DMAx instance
1023 * @param channel This parameter can be one of the following values:
1024 * @arg @ref LL_DMA_CHANNEL_0
1025 * @arg @ref LL_DMA_CHANNEL_1
1026 * @arg @ref LL_DMA_CHANNEL_2
1027 * @arg @ref LL_DMA_CHANNEL_3
1028 * @arg @ref LL_DMA_CHANNEL_4
1029 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1030 */
1031 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1032 {
1033 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1034 }
1035
1036 /**
1037 * @brief Configure the Source and Destination addresses.
1038 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1039 *
1040 * Register|BitsName
1041 * --------|--------
1042 * SAR | SAR
1043 * DAR | DAR
1044 * CTL_LO | TT_FC
1045 *
1046 * @param DMAx DMAx instance
1047 * @param channel This parameter can be one of the following values:
1048 * @arg @ref LL_DMA_CHANNEL_0
1049 * @arg @ref LL_DMA_CHANNEL_1
1050 * @arg @ref LL_DMA_CHANNEL_2
1051 * @arg @ref LL_DMA_CHANNEL_3
1052 * @arg @ref LL_DMA_CHANNEL_4
1053 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1054 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1055 * @param direction This parameter can be one of the following values:
1056 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1057 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1058 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1059 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1060 * @retval None
1061 */
1062 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx,
1063 uint32_t channel,
1064 uint32_t src_address,
1065 uint32_t dst_address,
1066 uint32_t direction)
1067 {
1068 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1069 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1070 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1071 }
1072
1073 /**
1074 * @brief Set the Source address.
1075 *
1076 * Register|BitsName
1077 * --------|--------
1078 * SAR | SAR
1079 *
1080 * @param DMAx DMAx instance
1081 * @param channel This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_CHANNEL_0
1083 * @arg @ref LL_DMA_CHANNEL_1
1084 * @arg @ref LL_DMA_CHANNEL_2
1085 * @arg @ref LL_DMA_CHANNEL_3
1086 * @arg @ref LL_DMA_CHANNEL_4
1087 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1088 * @retval None
1089 */
1090 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1091 {
1092 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1093 }
1094
1095 /**
1096 * @brief Set the Destination address.
1097 *
1098 * Register|BitsName
1099 * --------|--------
1100 * DAR | DAR
1101 *
1102 * @param DMAx DMAx instance
1103 * @param channel This parameter can be one of the following values:
1104 * @arg @ref LL_DMA_CHANNEL_0
1105 * @arg @ref LL_DMA_CHANNEL_1
1106 * @arg @ref LL_DMA_CHANNEL_2
1107 * @arg @ref LL_DMA_CHANNEL_3
1108 * @arg @ref LL_DMA_CHANNEL_4
1109 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1110 * @retval None
1111 */
1112 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1113 {
1114 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1115 }
1116
1117 /**
1118 * @brief Get Source address.
1119 *
1120 * Register|BitsName
1121 * --------|--------
1122 * SAR | SAR
1123 *
1124 * @param DMAx DMAx instance
1125 * @param channel This parameter can be one of the following values:
1126 * @arg @ref LL_DMA_CHANNEL_0
1127 * @arg @ref LL_DMA_CHANNEL_1
1128 * @arg @ref LL_DMA_CHANNEL_2
1129 * @arg @ref LL_DMA_CHANNEL_3
1130 * @arg @ref LL_DMA_CHANNEL_4
1131 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1132 */
1133 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1134 {
1135 return READ_REG(DMAx->CHANNEL[channel].SAR);
1136 }
1137
1138 /**
1139 * @brief Get Destination address.
1140 *
1141 * Register|BitsName
1142 * --------|--------
1143 * DAR | DAR
1144 *
1145 * @param DMAx DMAx instance
1146 * @param channel This parameter can be one of the following values:
1147 * @arg @ref LL_DMA_CHANNEL_0
1148 * @arg @ref LL_DMA_CHANNEL_1
1149 * @arg @ref LL_DMA_CHANNEL_2
1150 * @arg @ref LL_DMA_CHANNEL_3
1151 * @arg @ref LL_DMA_CHANNEL_4
1152 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1153 */
1154 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1155 {
1156 return READ_REG(DMAx->CHANNEL[channel].DAR);
1157 }
1158
1159 /**
1160 * @brief Set the Memory to Memory Source address.
1161 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1162 *
1163 * Register|BitsName
1164 * --------|--------
1165 * SAR | SAR
1166 * CTL_LO | TT_FC
1167 * @param DMAx DMAx instance
1168 * @param channel This parameter can be one of the following values:
1169 * @arg @ref LL_DMA_CHANNEL_0
1170 * @arg @ref LL_DMA_CHANNEL_1
1171 * @arg @ref LL_DMA_CHANNEL_2
1172 * @arg @ref LL_DMA_CHANNEL_3
1173 * @arg @ref LL_DMA_CHANNEL_4
1174 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1175 * @retval None
1176 */
1177 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1178 {
1179 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1180 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1181 }
1182
1183 /**
1184 * @brief Set the Memory to Memory Destination address.
1185 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1186 *
1187 * Register|BitsName
1188 * --------|--------
1189 * DAR | DAR
1190 * CTL_LO | TT_FC
1191 *
1192 * @param DMAx DMAx instance
1193 * @param channel This parameter can be one of the following values:
1194 * @arg @ref LL_DMA_CHANNEL_0
1195 * @arg @ref LL_DMA_CHANNEL_1
1196 * @arg @ref LL_DMA_CHANNEL_2
1197 * @arg @ref LL_DMA_CHANNEL_3
1198 * @arg @ref LL_DMA_CHANNEL_4
1199 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1200 * @retval None
1201 */
1202 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1203 {
1204 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1205 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1206 }
1207
1208 /**
1209 * @brief Get the Memory to Memory Source address.
1210 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1211 *
1212 * Register|BitsName
1213 * --------|--------
1214 * SAR | SAR
1215 *
1216 * @param DMAx DMAx instance
1217 * @param channel This parameter can be one of the following values:
1218 * @arg @ref LL_DMA_CHANNEL_0
1219 * @arg @ref LL_DMA_CHANNEL_1
1220 * @arg @ref LL_DMA_CHANNEL_2
1221 * @arg @ref LL_DMA_CHANNEL_3
1222 * @arg @ref LL_DMA_CHANNEL_4
1223 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1224 */
1225 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1226 {
1227 return READ_REG(DMAx->CHANNEL[channel].SAR);
1228 }
1229
1230 /**
1231 * @brief Get the Memory to Memory Destination address.
1232 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1233 *
1234 * Register|BitsName
1235 * --------|--------
1236 * DAR | DAR
1237 *
1238 * @param DMAx DMAx instance
1239 * @param channel This parameter can be one of the following values:
1240 * @arg @ref LL_DMA_CHANNEL_0
1241 * @arg @ref LL_DMA_CHANNEL_1
1242 * @arg @ref LL_DMA_CHANNEL_2
1243 * @arg @ref LL_DMA_CHANNEL_3
1244 * @arg @ref LL_DMA_CHANNEL_4
1245 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1246 */
1247 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
1248 {
1249 return READ_REG(DMAx->CHANNEL[channel].DAR);
1250 }
1251
1252 /**
1253 * @brief Set source peripheral for DMA instance on Channel x.
1254 *
1255 * Register|BitsName
1256 * --------|--------
1257 * CFG_HI | SRC_PER
1258 *
1259 * @param DMAx DMAx instance
1260 * @param channel This parameter can be one of the following values:
1261 * @arg @ref LL_DMA_CHANNEL_0
1262 * @arg @ref LL_DMA_CHANNEL_1
1263 * @arg @ref LL_DMA_CHANNEL_2
1264 * @arg @ref LL_DMA_CHANNEL_3
1265 * @arg @ref LL_DMA_CHANNEL_4
1266 * @param peripheral This parameter can be one of the following values:
1267 * @arg @ref LL_DMA0_PERIPH_CTE
1268 * @arg @ref LL_DMA0_PERIPH_PWM0
1269 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
1270 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
1271 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
1272 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
1273 * @arg @ref LL_DMA0_PERIPH_UART0_TX
1274 * @arg @ref LL_DMA0_PERIPH_UART0_RX
1275 * @arg @ref LL_DMA0_PERIPH_UART1_TX
1276 * @arg @ref LL_DMA0_PERIPH_UART1_RX
1277 * @arg @ref LL_DMA0_PERIPH_SNSADC
1278 * @arg @ref LL_DMA0_PERIPH_I2C0_TX
1279 * @arg @ref LL_DMA0_PERIPH_I2C0_RX
1280 * @arg @ref LL_DMA0_PERIPH_I2C1_TX
1281 * @arg @ref LL_DMA0_PERIPH_I2C1_RX
1282
1283 * @retval None
1284 */
1285 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1286 {
1287 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1288 }
1289
1290 /**
1291 * @brief Get source peripheral for DMA instance on Channel x.
1292 *
1293 * Register|BitsName
1294 * --------|--------
1295 * CFG_HI | SRC_PER
1296 *
1297 * @param DMAx DMAx instance
1298 * @param channel This parameter can be one of the following values:
1299 * @arg @ref LL_DMA_CHANNEL_0
1300 * @arg @ref LL_DMA_CHANNEL_1
1301 * @arg @ref LL_DMA_CHANNEL_2
1302 * @arg @ref LL_DMA_CHANNEL_3
1303 * @arg @ref LL_DMA_CHANNEL_4
1304 * @retval Returned value can be one of the following values:
1305 * @arg @ref LL_DMA0_PERIPH_CTE
1306 * @arg @ref LL_DMA0_PERIPH_PWM0
1307 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
1308 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
1309 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
1310 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
1311 * @arg @ref LL_DMA0_PERIPH_UART0_TX
1312 * @arg @ref LL_DMA0_PERIPH_UART0_RX
1313 * @arg @ref LL_DMA0_PERIPH_UART1_TX
1314 * @arg @ref LL_DMA0_PERIPH_UART1_RX
1315 * @arg @ref LL_DMA0_PERIPH_SNSADC
1316 * @arg @ref LL_DMA0_PERIPH_I2C0_TX
1317 * @arg @ref LL_DMA0_PERIPH_I2C0_RX
1318 * @arg @ref LL_DMA0_PERIPH_I2C1_TX
1319 * @arg @ref LL_DMA0_PERIPH_I2C1_RX
1320 */
1321 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
1322 {
1323 return READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1324 }
1325
1326 /**
1327 * @brief Set destination peripheral for DMA instance on Channel x.
1328 *
1329 * Register|BitsName
1330 * --------|--------
1331 * CFG_HI | DST_PER
1332 *
1333 * @param DMAx DMAx instance
1334 * @param channel This parameter can be one of the following values:
1335 * @arg @ref LL_DMA_CHANNEL_0
1336 * @arg @ref LL_DMA_CHANNEL_1
1337 * @arg @ref LL_DMA_CHANNEL_2
1338 * @arg @ref LL_DMA_CHANNEL_3
1339 * @arg @ref LL_DMA_CHANNEL_4
1340 * @param peripheral This parameter can be one of the following values:
1341 * @arg @ref LL_DMA0_PERIPH_CTE
1342 * @arg @ref LL_DMA0_PERIPH_PWM0
1343 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
1344 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
1345 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
1346 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
1347 * @arg @ref LL_DMA0_PERIPH_UART0_TX
1348 * @arg @ref LL_DMA0_PERIPH_UART0_RX
1349 * @arg @ref LL_DMA0_PERIPH_UART1_TX
1350 * @arg @ref LL_DMA0_PERIPH_UART1_RX
1351 * @arg @ref LL_DMA0_PERIPH_SNSADC
1352 * @arg @ref LL_DMA0_PERIPH_I2C0_TX
1353 * @arg @ref LL_DMA0_PERIPH_I2C0_RX
1354 * @arg @ref LL_DMA0_PERIPH_I2C1_TX
1355 * @arg @ref LL_DMA0_PERIPH_I2C1_RX
1356 * @retval None
1357 */
1358 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1359 {
1360 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1361 }
1362
1363 /**
1364 * @brief Get destination peripheral for DMA instance on Channel x.
1365 *
1366 * Register|BitsName
1367 * --------|--------
1368 * CFG_HI | DST_PER
1369 *
1370 * @param DMAx DMAx instance
1371 * @param channel This parameter can be one of the following values:
1372 * @arg @ref LL_DMA_CHANNEL_0
1373 * @arg @ref LL_DMA_CHANNEL_1
1374 * @arg @ref LL_DMA_CHANNEL_2
1375 * @arg @ref LL_DMA_CHANNEL_3
1376 * @arg @ref LL_DMA_CHANNEL_4
1377 * @retval Returned value can be one of the following values:
1378 * @arg @ref LL_DMA0_PERIPH_CTE
1379 * @arg @ref LL_DMA0_PERIPH_PWM0
1380 * @arg @ref LL_DMA0_PERIPH_SPIM_TX
1381 * @arg @ref LL_DMA0_PERIPH_SPIM_RX
1382 * @arg @ref LL_DMA0_PERIPH_SPIS_TX
1383 * @arg @ref LL_DMA0_PERIPH_SPIS_RX
1384 * @arg @ref LL_DMA0_PERIPH_UART0_TX
1385 * @arg @ref LL_DMA0_PERIPH_UART0_RX
1386 * @arg @ref LL_DMA0_PERIPH_UART1_TX
1387 * @arg @ref LL_DMA0_PERIPH_UART1_RX
1388 * @arg @ref LL_DMA0_PERIPH_SNSADC
1389 * @arg @ref LL_DMA0_PERIPH_I2C0_TX
1390 * @arg @ref LL_DMA0_PERIPH_I2C0_RX
1391 * @arg @ref LL_DMA0_PERIPH_I2C1_TX
1392 * @arg @ref LL_DMA0_PERIPH_I2C1_RX
1393 */
1394 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
1395 {
1396 return (READ_BITS(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos);
1397 }
1398
1399 /**
1400 * @brief Set source and destination source handshaking interface.
1401 *
1402 * Register|BitsName
1403 * --------|--------
1404 * CFG_HI | DST_PER
1405 *
1406 * @param DMAx DMAx instance
1407 * @param channel This parameter can be one of the following values:
1408 * @arg @ref LL_DMA_CHANNEL_0
1409 * @arg @ref LL_DMA_CHANNEL_1
1410 * @arg @ref LL_DMA_CHANNEL_2
1411 * @arg @ref LL_DMA_CHANNEL_3
1412 * @arg @ref LL_DMA_CHANNEL_4
1413 * @param src_handshaking This parameter can be one of the following values:
1414 * @arg @ref LL_DMA_SHANDSHAKING_HW
1415 * @arg @ref LL_DMA_SHANDSHAKING_HW
1416 * @param dst_handshaking This parameter can be one of the following values:
1417 * @arg @ref LL_DMA_DHANDSHAKING_HW
1418 * @arg @ref LL_DMA_DHANDSHAKING_HW
1419 * @retval None
1420 */
1421 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
1422 {
1423 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1424 src_handshaking | dst_handshaking);
1425 }
1426
1427 /**
1428 * @brief Set Maximum AMBA Burst Length.
1429 *
1430 * Register|BitsName
1431 * --------|--------
1432 * CFG_LO | MAX_ABRST
1433 *
1434 * @param DMAx DMAx instance
1435 * @param channel This parameter can be one of the following values:
1436 * @arg @ref LL_DMA_CHANNEL_0
1437 * @arg @ref LL_DMA_CHANNEL_1
1438 * @arg @ref LL_DMA_CHANNEL_2
1439 * @arg @ref LL_DMA_CHANNEL_3
1440 * @arg @ref LL_DMA_CHANNEL_4
1441 * @param beats This parameter can be one of the following values:
1442 Between Min_Data = 0 and Max_Data = 0x3FFU.
1443 * @retval None
1444 */
1445 __STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
1446 {
1447 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST, beats << DMA_CFGL_MAX_ABRST_Pos);
1448 }
1449
1450 /**
1451 * @brief Get source status after each block tranfer completed.
1452 *
1453 * Register|BitsName
1454 * --------|--------
1455 * SSTAT | SSTAT
1456 *
1457 * @param DMAx DMAx instance
1458 * @param channel This parameter can be one of the following values:
1459 * @arg @ref LL_DMA_CHANNEL_0
1460 * @arg @ref LL_DMA_CHANNEL_1
1461 * @arg @ref LL_DMA_CHANNEL_2
1462 * @arg @ref LL_DMA_CHANNEL_3
1463 * @arg @ref LL_DMA_CHANNEL_4
1464 * @retval Returned value can be one of the following values:
1465 Between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
1466 * @retval None
1467 */
1468 __STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
1469 {
1470 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_MAX_ABRST) >> DMA_CFGL_MAX_ABRST_Pos);
1471 }
1472
1473 /**
1474 * @brief Enable channel lock.
1475 *
1476 * Register|BitsName
1477 * --------|--------
1478 * CFG_LO | LOCK_CH
1479 *
1480 * @param DMAx DMAx instance
1481 * @param channel This parameter can be one of the following values:
1482 * @arg @ref LL_DMA_CHANNEL_0
1483 * @arg @ref LL_DMA_CHANNEL_1
1484 * @arg @ref LL_DMA_CHANNEL_2
1485 * @arg @ref LL_DMA_CHANNEL_3
1486 * @arg @ref LL_DMA_CHANNEL_4
1487 * @retval None
1488 */
1489 __STATIC_INLINE void ll_dma_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1490 {
1491 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1492 }
1493
1494 /**
1495 * @brief Disable channel lock.
1496 *
1497 * Register|BitsName
1498 * --------|--------
1499 * CFG_LO | LOCK_CH
1500 *
1501 * @param DMAx DMAx instance
1502 * @param channel This parameter can be one of the following values:
1503 * @arg @ref LL_DMA_CHANNEL_0
1504 * @arg @ref LL_DMA_CHANNEL_1
1505 * @arg @ref LL_DMA_CHANNEL_2
1506 * @arg @ref LL_DMA_CHANNEL_3
1507 * @arg @ref LL_DMA_CHANNEL_4
1508 * @retval None
1509 */
1510 __STATIC_INLINE void ll_dma_disable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1511 {
1512 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH);
1513 }
1514
1515 /**
1516 * @brief CHeck if the channel lock enable.
1517 *
1518 * Register|BitsName
1519 * --------|--------
1520 * CFG_LO | LOCK_CH
1521 *
1522 * @param DMAx DMAx instance
1523 * @param channel This parameter can be one of the following values:
1524 * @arg @ref LL_DMA_CHANNEL_0
1525 * @arg @ref LL_DMA_CHANNEL_1
1526 * @arg @ref LL_DMA_CHANNEL_2
1527 * @arg @ref LL_DMA_CHANNEL_3
1528 * @arg @ref LL_DMA_CHANNEL_4
1529 * @retval None
1530 */
1531 __STATIC_INLINE uint32_t ll_dma_is_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
1532 {
1533 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH) == DMA_CFGL_LOCK_CH);
1534 }
1535
1536 /**
1537 * @brief Enable Bus lock.
1538 *
1539 * Register|BitsName
1540 * --------|--------
1541 * CFG_LO | LOCK_B
1542 *
1543 * @param DMAx DMAx instance
1544 * @param channel This parameter can be one of the following values:
1545 * @arg @ref LL_DMA_CHANNEL_0
1546 * @arg @ref LL_DMA_CHANNEL_1
1547 * @arg @ref LL_DMA_CHANNEL_2
1548 * @arg @ref LL_DMA_CHANNEL_3
1549 * @arg @ref LL_DMA_CHANNEL_4
1550 * @retval None
1551 */
1552 __STATIC_INLINE void ll_dma_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1553 {
1554 SET_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1555 }
1556
1557 /**
1558 * @brief Disable Bus lock.
1559 *
1560 * Register|BitsName
1561 * --------|--------
1562 * CFG_LO | LOCK_B
1563 *
1564 * @param DMAx DMAx instance
1565 * @param channel This parameter can be one of the following values:
1566 * @arg @ref LL_DMA_CHANNEL_0
1567 * @arg @ref LL_DMA_CHANNEL_1
1568 * @arg @ref LL_DMA_CHANNEL_2
1569 * @arg @ref LL_DMA_CHANNEL_3
1570 * @arg @ref LL_DMA_CHANNEL_4
1571 * @retval None
1572 */
1573 __STATIC_INLINE void ll_dma_disable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1574 {
1575 CLEAR_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B);
1576 }
1577
1578 /**
1579 * @brief CHeck if the Bus lock enable.
1580 *
1581 * Register|BitsName
1582 * --------|--------
1583 * CFG_LO | LOCK_B
1584 *
1585 * @param DMAx DMAx instance
1586 * @param channel This parameter can be one of the following values:
1587 * @arg @ref LL_DMA_CHANNEL_0
1588 * @arg @ref LL_DMA_CHANNEL_1
1589 * @arg @ref LL_DMA_CHANNEL_2
1590 * @arg @ref LL_DMA_CHANNEL_3
1591 * @arg @ref LL_DMA_CHANNEL_4
1592 * @retval None
1593 */
1594 __STATIC_INLINE uint32_t ll_dma_is_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
1595 {
1596 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B) == DMA_CFGL_LOCK_B);
1597 }
1598
1599 /**
1600 * @brief Set channel lock level.
1601 *
1602 * Register|BitsName
1603 * --------|--------
1604 * CFG_LO | LOCK_CH
1605 *
1606 * @param DMAx DMAx instance
1607 * @param channel This parameter can be one of the following values:
1608 * @arg @ref LL_DMA_CHANNEL_0
1609 * @arg @ref LL_DMA_CHANNEL_1
1610 * @arg @ref LL_DMA_CHANNEL_2
1611 * @arg @ref LL_DMA_CHANNEL_3
1612 * @arg @ref LL_DMA_CHANNEL_4
1613 * @param lock_level This parameter can be one of the following values:
1614 * @arg @ref LL_DMA_LOCK_CH_LEVEL_TFR
1615 * @arg @ref LL_DMA_LOCK_CH_LEVEL_BLK
1616 * @arg @ref LL_DMA_LOCK_CH_LEVEL_TRANS
1617 * @retval None
1618 */
1619 __STATIC_INLINE void ll_dma_set_channel_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
1620 {
1621 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L, lock_level);
1622 }
1623
1624 /**
1625 * @brief Get channel lock level.
1626 *
1627 * Register|BitsName
1628 * --------|--------
1629 * CFG_LO | LOCK_CH
1630 *
1631 * @param DMAx DMAx instance
1632 * @param channel This parameter can be one of the following values:
1633 * @arg @ref LL_DMA_CHANNEL_0
1634 * @arg @ref LL_DMA_CHANNEL_1
1635 * @arg @ref LL_DMA_CHANNEL_2
1636 * @arg @ref LL_DMA_CHANNEL_3
1637 * @arg @ref LL_DMA_CHANNEL_4
1638 * @retval Returned value can be one of the following values:
1639 * @arg @ref LL_DMA_LOCK_CH_LEVEL_TFR
1640 * @arg @ref LL_DMA_LOCK_CH_LEVEL_BLK
1641 * @arg @ref LL_DMA_LOCK_CH_LEVEL_TRANS
1642 */
1643 __STATIC_INLINE uint32_t ll_dma_get_channel_lock_level(dma_regs_t *DMAx, uint32_t channel)
1644 {
1645 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_CH_L);
1646 }
1647
1648 /**
1649 * @brief Set bus lock level.
1650 *
1651 * Register|BitsName
1652 * --------|--------
1653 * CFG_LO | LOCK_B
1654 *
1655 * @param DMAx DMAx instance
1656 * @param channel This parameter can be one of the following values:
1657 * @arg @ref LL_DMA_CHANNEL_0
1658 * @arg @ref LL_DMA_CHANNEL_1
1659 * @arg @ref LL_DMA_CHANNEL_2
1660 * @arg @ref LL_DMA_CHANNEL_3
1661 * @arg @ref LL_DMA_CHANNEL_4
1662 * @param lock_level This parameter can be one of the following values:
1663 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_TFR
1664 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_BLK
1665 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_TRANS
1666 * @retval None
1667 */
1668 __STATIC_INLINE void ll_dma_set_bus_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
1669 {
1670 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L, lock_level);
1671 }
1672
1673 /**
1674 * @brief Get bus lock level.
1675 *
1676 * Register|BitsName
1677 * --------|--------
1678 * CFG_LO | LOCK_B
1679 *
1680 * @param DMAx DMAx instance
1681 * @param channel This parameter can be one of the following values:
1682 * @arg @ref LL_DMA_CHANNEL_0
1683 * @arg @ref LL_DMA_CHANNEL_1
1684 * @arg @ref LL_DMA_CHANNEL_2
1685 * @arg @ref LL_DMA_CHANNEL_3
1686 * @arg @ref LL_DMA_CHANNEL_4
1687 * @retval Returned value can be one of the following values:
1688 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_TFR
1689 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_BLK
1690 * @arg @ref LL_DMA_LOCK_BUS_LEVEL_TRANS
1691 */
1692 __STATIC_INLINE uint32_t ll_dma_get_bus_lock_level(dma_regs_t *DMAx, uint32_t channel)
1693 {
1694 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_LOCK_B_L);
1695 }
1696
1697 /**
1698 * @brief Source Single Transaction Request.
1699 *
1700 * Register|BitsName
1701 * --------|--------
1702 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1703 * REQ_SRC | SRC_WE&SRC
1704 *
1705 * @param DMAx DMA instance.
1706 * @param channel This parameter can be one of the following values:
1707 * @arg @ref LL_DMA_CHANNEL_0
1708 * @arg @ref LL_DMA_CHANNEL_1
1709 * @arg @ref LL_DMA_CHANNEL_2
1710 * @arg @ref LL_DMA_CHANNEL_3
1711 * @arg @ref LL_DMA_CHANNEL_4
1712 * @retval None
1713 */
1714 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1715 {
1716 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1717 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1718 }
1719
1720 /**
1721 * @brief Source Burst Transaction Request.
1722 *
1723 * Register|BitsName
1724 * --------|--------
1725 * REQ_SRC | SRC_WE&SRC
1726 *
1727 * @param DMAx DMA instance.
1728 * @param channel This parameter can be one of the following values:
1729 * @arg @ref LL_DMA_CHANNEL_0
1730 * @arg @ref LL_DMA_CHANNEL_1
1731 * @arg @ref LL_DMA_CHANNEL_2
1732 * @arg @ref LL_DMA_CHANNEL_3
1733 * @arg @ref LL_DMA_CHANNEL_4
1734 * @retval None
1735 */
1736 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1737 {
1738 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1739 }
1740
1741 /**
1742 * @brief Source Last Single Transaction Request.
1743 *
1744 * Register|BitsName
1745 * --------|--------
1746 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1747 * LST_SRC | LST_SRC_WE&LST_SRC
1748 * REQ_SRC | SRC_WE&SRC
1749 *
1750 * @param DMAx DMA instance.
1751 * @param channel This parameter can be one of the following values:
1752 * @arg @ref LL_DMA_CHANNEL_0
1753 * @arg @ref LL_DMA_CHANNEL_1
1754 * @arg @ref LL_DMA_CHANNEL_2
1755 * @arg @ref LL_DMA_CHANNEL_3
1756 * @arg @ref LL_DMA_CHANNEL_4
1757 * @retval None
1758 */
1759 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1760 {
1761 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1762 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1763 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1764 }
1765
1766 /**
1767 * @brief Source Last Burst Transaction Request.
1768 *
1769 * Register|BitsName
1770 * --------|--------
1771 * LST_SRC | LST_SRC_WE&LST_SRC
1772 * REQ_SRC | SRC_WE&SRC
1773 *
1774 * @param DMAx DMA instance.
1775 * @param channel This parameter can be one of the following values:
1776 * @arg @ref LL_DMA_CHANNEL_0
1777 * @arg @ref LL_DMA_CHANNEL_1
1778 * @arg @ref LL_DMA_CHANNEL_2
1779 * @arg @ref LL_DMA_CHANNEL_3
1780 * @arg @ref LL_DMA_CHANNEL_4
1781 * @retval None
1782 */
1783 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1784 {
1785 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1786 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1787 }
1788
1789 /**
1790 * @brief Destination Single Transaction Request.
1791 *
1792 * Register|BitsName
1793 * --------|--------
1794 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1795 * REQ_DST | DST_WE&DST
1796 *
1797 * @param DMAx DMA instance.
1798 * @param channel This parameter can be one of the following values:
1799 * @arg @ref LL_DMA_CHANNEL_0
1800 * @arg @ref LL_DMA_CHANNEL_1
1801 * @arg @ref LL_DMA_CHANNEL_2
1802 * @arg @ref LL_DMA_CHANNEL_3
1803 * @arg @ref LL_DMA_CHANNEL_4
1804 * @retval None
1805 */
1806 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1807 {
1808 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1809 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1810 }
1811
1812 /**
1813 * @brief Destination Burst Transaction Request.
1814 *
1815 * Register|BitsName
1816 * --------|--------
1817 * REQ_DST | DST_WE&DST
1818 *
1819 * @param DMAx DMA instance.
1820 * @param channel This parameter can be one of the following values:
1821 * @arg @ref LL_DMA_CHANNEL_0
1822 * @arg @ref LL_DMA_CHANNEL_1
1823 * @arg @ref LL_DMA_CHANNEL_2
1824 * @arg @ref LL_DMA_CHANNEL_3
1825 * @arg @ref LL_DMA_CHANNEL_4
1826 * @retval None
1827 */
1828 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1829 {
1830 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1831 }
1832
1833 /**
1834 * @brief Destination Last Single Transaction Request.
1835 *
1836 * Register|BitsName
1837 * --------|--------
1838 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1839 * LST_DST | LST_DST_WE&LST_DST
1840 * REQ_DST | DST_WE&DST
1841 *
1842 * @param DMAx DMA instance.
1843 * @param channel This parameter can be one of the following values:
1844 * @arg @ref LL_DMA_CHANNEL_0
1845 * @arg @ref LL_DMA_CHANNEL_1
1846 * @arg @ref LL_DMA_CHANNEL_2
1847 * @arg @ref LL_DMA_CHANNEL_3
1848 * @arg @ref LL_DMA_CHANNEL_4
1849 * @retval None
1850 */
1851 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1852 {
1853 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1854 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1855 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1856 }
1857
1858 /**
1859 * @brief Destination Last Burst Transaction Request.
1860 *
1861 * Register|BitsName
1862 * --------|--------
1863 * LST_DST | LST_DST_WE&LST_DST
1864 * REQ_DST | DST_WE&DST
1865 *
1866 * @param DMAx DMA instance.
1867 * @param channel This parameter can be one of the following values:
1868 * @arg @ref LL_DMA_CHANNEL_0
1869 * @arg @ref LL_DMA_CHANNEL_1
1870 * @arg @ref LL_DMA_CHANNEL_2
1871 * @arg @ref LL_DMA_CHANNEL_3
1872 * @arg @ref LL_DMA_CHANNEL_4
1873 * @retval None
1874 */
1875 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1876 {
1877 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1878 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1879 }
1880
1881 /** @} */
1882
1883 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1884 * @{
1885 */
1886
1887 /**
1888 * @brief Get DMA Module global transfer complete interrupt status.
1889 *
1890 * Register|BitsName
1891 * --------|--------
1892 * STATUS_INT | TFR
1893 *
1894 * @param DMAx DMAx instance
1895 * @retval State of bit (1 or 0).
1896 */
1897 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
1898 {
1899 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1900 }
1901
1902 /**
1903 * @brief Get DMA Module global block complete interrupt status.
1904 *
1905 * Register|BitsName
1906 * --------|--------
1907 * STATUS_INT | BLOCK
1908 *
1909 * @param DMAx DMAx instance
1910 * @retval State of bit (1 or 0).
1911 */
1912 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
1913 {
1914 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1915 }
1916
1917 /**
1918 * @brief Get DMA Module global source transaction complete interrupt status.
1919 *
1920 * Register|BitsName
1921 * --------|--------
1922 * STATUS_INT | SRCT
1923 *
1924 * @param DMAx DMAx instance
1925 * @retval State of bit (1 or 0).
1926 */
1927 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
1928 {
1929 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1930 }
1931
1932 /**
1933 * @brief Get DMA Module global destination transaction complete interrupt status.
1934 *
1935 * Register|BitsName
1936 * --------|--------
1937 * STATUS_INT | DSTT
1938 *
1939 * @param DMAx DMAx instance
1940 * @retval State of bit (1 or 0).
1941 */
1942 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
1943 {
1944 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1945 }
1946
1947 /**
1948 * @brief Get DMA Module global error interrupt status.
1949 *
1950 * Register|BitsName
1951 * --------|--------
1952 * STATUS_INT | ERR
1953 *
1954 * @param DMAx DMAx instance
1955 * @retval State of bit (1 or 0).
1956 */
1957 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
1958 {
1959 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1960 }
1961
1962 /**
1963 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
1964 *
1965 * Register|BitsName
1966 * --------|--------
1967 * RAW_TFR | RAW
1968 *
1969 * @param DMAx DMAx instance
1970 * @param channel This parameter can be one of the following values:
1971 * @arg @ref LL_DMA_CHANNEL_0
1972 * @arg @ref LL_DMA_CHANNEL_1
1973 * @arg @ref LL_DMA_CHANNEL_2
1974 * @arg @ref LL_DMA_CHANNEL_3
1975 * @arg @ref LL_DMA_CHANNEL_4
1976 * @retval State of bit (1 or 0).
1977 */
1978 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
1979 {
1980 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
1981 }
1982
1983 /**
1984 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
1985 *
1986 * Register|BitsName
1987 * --------|--------
1988 * RAW_BLK | RAW
1989 *
1990 * @param DMAx DMAx instance
1991 * @param channel This parameter can be one of the following values:
1992 * @arg @ref LL_DMA_CHANNEL_0
1993 * @arg @ref LL_DMA_CHANNEL_1
1994 * @arg @ref LL_DMA_CHANNEL_2
1995 * @arg @ref LL_DMA_CHANNEL_3
1996 * @arg @ref LL_DMA_CHANNEL_4
1997 * @retval State of bit (1 or 0).
1998 */
1999 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
2000 {
2001 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[2], (1 << channel)) == (1 << channel));
2002 }
2003
2004 /**
2005 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
2006 *
2007 * Register|BitsName
2008 * --------|--------
2009 * RAW_SRC_TRN | RAW
2010 *
2011 * @param DMAx DMAx instance
2012 * @param channel This parameter can be one of the following values:
2013 * @arg @ref LL_DMA_CHANNEL_0
2014 * @arg @ref LL_DMA_CHANNEL_1
2015 * @arg @ref LL_DMA_CHANNEL_2
2016 * @arg @ref LL_DMA_CHANNEL_3
2017 * @arg @ref LL_DMA_CHANNEL_4
2018 * @retval State of bit (1 or 0).
2019 */
2020 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
2021 {
2022 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[4], (1 << channel)) == (1 << channel));
2023 }
2024
2025 /**
2026 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
2027 *
2028 * Register|BitsName
2029 * --------|--------
2030 * RAW_DST_TRN | RAW
2031 *
2032 * @param DMAx DMAx instance
2033 * @param channel This parameter can be one of the following values:
2034 * @arg @ref LL_DMA_CHANNEL_0
2035 * @arg @ref LL_DMA_CHANNEL_1
2036 * @arg @ref LL_DMA_CHANNEL_2
2037 * @arg @ref LL_DMA_CHANNEL_3
2038 * @arg @ref LL_DMA_CHANNEL_4
2039 * @retval State of bit (1 or 0).
2040 */
2041 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
2042 {
2043 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[6], (1 << channel)) == (1 << channel));
2044 }
2045
2046 /**
2047 * @brief Indicate the Raw Status of IntErr Interrupt flag.
2048 *
2049 * Register|BitsName
2050 * --------|--------
2051 * RAW_ERR | RAW
2052 *
2053 * @param DMAx DMAx instance
2054 * @param channel This parameter can be one of the following values:
2055 * @arg @ref LL_DMA_CHANNEL_0
2056 * @arg @ref LL_DMA_CHANNEL_1
2057 * @arg @ref LL_DMA_CHANNEL_2
2058 * @arg @ref LL_DMA_CHANNEL_3
2059 * @arg @ref LL_DMA_CHANNEL_4
2060 * @retval State of bit (1 or 0).
2061 */
2062 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
2063 {
2064 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[8], (1 << channel)) == (1 << channel));
2065 }
2066
2067 /**
2068 * @brief Indicate the status of DMA Channel transfer complete flag.
2069 *
2070 * Register|BitsName
2071 * --------|--------
2072 * STAT_TFR | STATUS
2073 *
2074 * @param DMAx DMAx instance
2075 * @param channel This parameter can be one of the following values:
2076 * @arg @ref LL_DMA_CHANNEL_0
2077 * @arg @ref LL_DMA_CHANNEL_1
2078 * @arg @ref LL_DMA_CHANNEL_2
2079 * @arg @ref LL_DMA_CHANNEL_3
2080 * @arg @ref LL_DMA_CHANNEL_4
2081 * @retval State of bit (1 or 0).
2082 */
2083 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2084 {
2085 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2086 }
2087
2088 /**
2089 * @brief Indicate the status of Channel 0 transfer complete flag.
2090 *
2091 * Register|BitsName
2092 * --------|--------
2093 * STAT_TFR | STATUS
2094 *
2095 * @param DMAx DMAx instance
2096 * @retval State of bit (1 or 0).
2097 */
2098 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
2099 {
2100 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2101 }
2102
2103 /**
2104 * @brief Indicate the status of Channel 1 transfer complete flag.
2105 *
2106 * Register|BitsName
2107 * --------|--------
2108 * STAT_TFR | STATUS
2109 *
2110 * @param DMAx DMAx instance
2111 * @retval State of bit (1 or 0).
2112 */
2113 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
2114 {
2115 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2116 }
2117
2118 /**
2119 * @brief Indicate the status of Channel 2 transfer complete flag.
2120 *
2121 * Register|BitsName
2122 * --------|--------
2123 * STAT_TFR | STATUS
2124 *
2125 * @param DMAx DMAx instance
2126 * @retval State of bit (1 or 0).
2127 */
2128 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
2129 {
2130 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 2)) == (1 << 2));
2131 }
2132
2133 /**
2134 * @brief Indicate the status of Channel 3 transfer complete flag.
2135 *
2136 * Register|BitsName
2137 * --------|--------
2138 * STAT_TFR | STATUS
2139 *
2140 * @param DMAx DMAx instance
2141 * @retval State of bit (1 or 0).
2142 */
2143 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
2144 {
2145 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 3)) == (1 << 3));
2146 }
2147
2148 /**
2149 * @brief Indicate the status of Channel 4 transfer complete flag.
2150 *
2151 * Register|BitsName
2152 * --------|--------
2153 * STAT_TFR | STATUS
2154 *
2155 * @param DMAx DMAx instance
2156 * @retval State of bit (1 or 0).
2157 */
2158 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
2159 {
2160 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 4)) == (1 << 4));
2161 }
2162
2163
2164 /**
2165 * @brief Indicate the status of DMA Channel block complete flag.
2166 *
2167 * Register|BitsName
2168 * --------|--------
2169 * STAT_BLK | STATUS
2170 *
2171 * @param DMAx DMAx instance
2172 * @param channel This parameter can be one of the following values:
2173 * @arg @ref LL_DMA_CHANNEL_0
2174 * @arg @ref LL_DMA_CHANNEL_1
2175 * @arg @ref LL_DMA_CHANNEL_2
2176 * @arg @ref LL_DMA_CHANNEL_3
2177 * @arg @ref LL_DMA_CHANNEL_4
2178 * @retval State of bit (1 or 0).
2179 */
2180 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2181 {
2182 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << channel)) == (1 << channel));
2183 }
2184
2185 /**
2186 * @brief Indicate the status of Channel 0 block complete flag.
2187 *
2188 * Register|BitsName
2189 * --------|--------
2190 * STAT_BLK | STATUS
2191 *
2192 * @param DMAx DMAx instance
2193 * @retval State of bit (1 or 0).
2194 */
2195 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
2196 {
2197 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 0)) == (1 << 0));
2198 }
2199
2200 /**
2201 * @brief Indicate the status of Channel 1 block complete flag.
2202 *
2203 * Register|BitsName
2204 * --------|--------
2205 * STAT_BLK | STATUS
2206 *
2207 * @param DMAx DMAx instance
2208 * @retval State of bit (1 or 0).
2209 */
2210 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
2211 {
2212 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 1)) == (1 << 1));
2213 }
2214
2215 /**
2216 * @brief Indicate the status of Channel 2 block complete flag.
2217 *
2218 * Register|BitsName
2219 * --------|--------
2220 * STAT_BLK | STATUS
2221 *
2222 * @param DMAx DMAx instance
2223 * @retval State of bit (1 or 0).
2224 */
2225 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
2226 {
2227 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 2)) == (1 << 2));
2228 }
2229
2230 /**
2231 * @brief Indicate the status of Channel 3 block complete flag.
2232 *
2233 * Register|BitsName
2234 * --------|--------
2235 * STAT_BLK | STATUS
2236 *
2237 * @param DMAx DMAx instance
2238 * @retval State of bit (1 or 0).
2239 */
2240 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
2241 {
2242 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 3)) == (1 << 3));
2243 }
2244
2245 /**
2246 * @brief Indicate the status of Channel 4 block complete flag.
2247 *
2248 * Register|BitsName
2249 * --------|--------
2250 * STAT_BLK | STATUS
2251 *
2252 * @param DMAx DMAx instance
2253 * @retval State of bit (1 or 0).
2254 */
2255 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
2256 {
2257 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[2], (1 << 4)) == (1 << 4));
2258 }
2259
2260
2261 /**
2262 * @brief Indicate the status of DMA Channel source transaction complete flag.
2263 *
2264 * Register|BitsName
2265 * --------|--------
2266 * STAT_SRC_TRN | STATUS
2267 *
2268 * @param DMAx DMAx instance
2269 * @param channel This parameter can be one of the following values:
2270 * @arg @ref LL_DMA_CHANNEL_0
2271 * @arg @ref LL_DMA_CHANNEL_1
2272 * @arg @ref LL_DMA_CHANNEL_2
2273 * @arg @ref LL_DMA_CHANNEL_3
2274 * @arg @ref LL_DMA_CHANNEL_4
2275 * @retval State of bit (1 or 0).
2276 */
2277 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2278 {
2279 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << channel)) == (1 << channel));
2280 }
2281
2282 /**
2283 * @brief Indicate the status of Channel 0 source transaction complete flag.
2284 *
2285 * Register|BitsName
2286 * --------|--------
2287 * STAT_SRC_TRN | STATUS
2288 *
2289 * @param DMAx DMAx instance
2290 * @retval State of bit (1 or 0).
2291 */
2292 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
2293 {
2294 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 0)) == (1 << 0));
2295 }
2296
2297 /**
2298 * @brief Indicate the status of Channel 1 source transaction complete flag.
2299 *
2300 * Register|BitsName
2301 * --------|--------
2302 * STAT_SRC_TRN | STATUS
2303 *
2304 * @param DMAx DMAx instance
2305 * @retval State of bit (1 or 0).
2306 */
2307 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
2308 {
2309 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 1)) == (1 << 1));
2310 }
2311
2312 /**
2313 * @brief Indicate the status of Channel 2 source transaction complete flag.
2314 *
2315 * Register|BitsName
2316 * --------|--------
2317 * STAT_SRC_TRN | STATUS
2318 *
2319 * @param DMAx DMAx instance
2320 * @retval State of bit (1 or 0).
2321 */
2322 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
2323 {
2324 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 2)) == (1 << 2));
2325 }
2326
2327 /**
2328 * @brief Indicate the status of Channel 3 source transaction complete flag.
2329 *
2330 * Register|BitsName
2331 * --------|--------
2332 * STAT_SRC_TRN | STATUS
2333 *
2334 * @param DMAx DMAx instance
2335 * @retval State of bit (1 or 0).
2336 */
2337 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
2338 {
2339 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 3)) == (1 << 3));
2340 }
2341
2342 /**
2343 * @brief Indicate the status of Channel 4 source transaction complete flag.
2344 *
2345 * Register|BitsName
2346 * --------|--------
2347 * STAT_SRC_TRN | STATUS
2348 *
2349 * @param DMAx DMAx instance
2350 * @retval State of bit (1 or 0).
2351 */
2352 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
2353 {
2354 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[4], (1 << 4)) == (1 << 4));
2355 }
2356
2357 /**
2358 * @brief Indicate the status of DMA Channel destination transaction complete flag.
2359 *
2360 * Register|BitsName
2361 * --------|--------
2362 * STAT_DST_TRN | STATUS
2363 *
2364 * @param DMAx DMAx instance
2365 * @param channel This parameter can be one of the following values:
2366 * @arg @ref LL_DMA_CHANNEL_0
2367 * @arg @ref LL_DMA_CHANNEL_1
2368 * @arg @ref LL_DMA_CHANNEL_2
2369 * @arg @ref LL_DMA_CHANNEL_3
2370 * @arg @ref LL_DMA_CHANNEL_4
2371 * @retval State of bit (1 or 0).
2372 */
2373 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2374 {
2375 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << channel)) == (1 << channel));
2376 }
2377
2378 /**
2379 * @brief Indicate the status of Channel 0 destination transaction complete flag.
2380 *
2381 * Register|BitsName
2382 * --------|--------
2383 * STAT_DST_TRN | STATUS
2384 *
2385 * @param DMAx DMAx instance
2386 * @retval State of bit (1 or 0).
2387 */
2388 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
2389 {
2390 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 0)) == (1 << 0));
2391 }
2392
2393 /**
2394 * @brief Indicate the status of Channel 1 destination transaction complete flag.
2395 *
2396 * Register|BitsName
2397 * --------|--------
2398 * STAT_DST_TRN | STATUS
2399 *
2400 * @param DMAx DMAx instance
2401 * @retval State of bit (1 or 0).
2402 */
2403 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
2404 {
2405 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 1)) == (1 << 1));
2406 }
2407
2408 /**
2409 * @brief Indicate the status of Channel 2 destination transaction complete flag.
2410 *
2411 * Register|BitsName
2412 * --------|--------
2413 * STAT_DST_TRN | STATUS
2414 *
2415 * @param DMAx DMAx instance
2416 * @retval State of bit (1 or 0).
2417 */
2418 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
2419 {
2420 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 2)) == (1 << 2));
2421 }
2422
2423 /**
2424 * @brief Indicate the status of Channel 3 destination transaction complete flag.
2425 *
2426 * Register|BitsName
2427 * --------|--------
2428 * STAT_DST_TRN | STATUS
2429 *
2430 * @param DMAx DMAx instance
2431 * @retval State of bit (1 or 0).
2432 */
2433 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
2434 {
2435 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 3)) == (1 << 3));
2436 }
2437
2438 /**
2439 * @brief Indicate the status of Channel 4 destination transaction complete flag.
2440 *
2441 * Register|BitsName
2442 * --------|--------
2443 * STAT_DST_TRN | STATUS
2444 *
2445 * @param DMAx DMAx instance
2446 * @retval State of bit (1 or 0).
2447 */
2448 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
2449 {
2450 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[6], (1 << 4)) == (1 << 4));
2451 }
2452
2453 /**
2454 * @brief Indicate the status of DMA Channel error flag.
2455 *
2456 * Register|BitsName
2457 * --------|--------
2458 * STAT_ERR | STATUS
2459 *
2460 * @param DMAx DMAx instance
2461 * @param channel This parameter can be one of the following values:
2462 * @arg @ref LL_DMA_CHANNEL_0
2463 * @arg @ref LL_DMA_CHANNEL_1
2464 * @arg @ref LL_DMA_CHANNEL_2
2465 * @arg @ref LL_DMA_CHANNEL_3
2466 * @arg @ref LL_DMA_CHANNEL_4
2467 * @retval State of bit (1 or 0).
2468 */
2469 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
2470 {
2471 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << channel)) == (1 << channel));
2472 }
2473
2474 /**
2475 * @brief Indicate the status of Channel 0 error flag.
2476 *
2477 * Register|BitsName
2478 * --------|--------
2479 * STAT_ERR | STATUS
2480 *
2481 * @param DMAx DMAx instance
2482 * @retval State of bit (1 or 0).
2483 */
2484 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
2485 {
2486 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 0)) == (1 << 0));
2487 }
2488
2489 /**
2490 * @brief Indicate the status of Channel 1 error flag.
2491 *
2492 * Register|BitsName
2493 * --------|--------
2494 * STAT_ERR | STATUS
2495 *
2496 * @param DMAx DMAx instance
2497 * @retval State of bit (1 or 0).
2498 */
2499 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
2500 {
2501 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 1)) == (1 << 1));
2502 }
2503
2504 /**
2505 * @brief Indicate the status of Channel 2 error flag.
2506 *
2507 * Register|BitsName
2508 * --------|--------
2509 * STAT_ERR | STATUS
2510 *
2511 * @param DMAx DMAx instance
2512 * @retval State of bit (1 or 0).
2513 */
2514 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
2515 {
2516 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 2)) == (1 << 2));
2517 }
2518
2519 /**
2520 * @brief Indicate the status of Channel 3 error flag.
2521 *
2522 * Register|BitsName
2523 * --------|--------
2524 * STAT_ERR | STATUS
2525 *
2526 * @param DMAx DMAx instance
2527 * @retval State of bit (1 or 0).
2528 */
2529 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
2530 {
2531 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 3)) == (1 << 3));
2532 }
2533
2534 /**
2535 * @brief Indicate the status of Channel 4 error flag.
2536 *
2537 * Register|BitsName
2538 * --------|--------
2539 * STAT_ERR | STATUS
2540 *
2541 * @param DMAx DMAx instance
2542 * @retval State of bit (1 or 0).
2543 */
2544 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
2545 {
2546 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[8], (1 << 4)) == (1 << 4));
2547 }
2548
2549 /**
2550 * @brief Clear DMA Channel transfer complete flag.
2551 *
2552 * Register|BitsName
2553 * --------|--------
2554 * CLR_TFR | CLEAR
2555 *
2556 * @param DMAx DMAx instance
2557 * @param channel This parameter can be one of the following values:
2558 * @arg @ref LL_DMA_CHANNEL_0
2559 * @arg @ref LL_DMA_CHANNEL_1
2560 * @arg @ref LL_DMA_CHANNEL_2
2561 * @arg @ref LL_DMA_CHANNEL_3
2562 * @arg @ref LL_DMA_CHANNEL_4
2563 * @retval None.
2564 */
2565 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2566 {
2567 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2568 }
2569
2570 /**
2571 * @brief Clear Channel 0 transfer complete flag.
2572 *
2573 * Register|BitsName
2574 * --------|--------
2575 * CLR_TFR | CLEAR
2576 *
2577 * @param DMAx DMAx instance
2578 * @retval None.
2579 */
2580 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
2581 {
2582 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2583 }
2584
2585 /**
2586 * @brief Clear Channel 1 transfer complete flag.
2587 *
2588 * Register|BitsName
2589 * --------|--------
2590 * CLR_TFR | CLEAR
2591 *
2592 * @param DMAx DMAx instance
2593 * @retval None.
2594 */
2595 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
2596 {
2597 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2598 }
2599
2600 /**
2601 * @brief Clear Channel 2 transfer complete flag.
2602 *
2603 * Register|BitsName
2604 * --------|--------
2605 * CLR_TFR | CLEAR
2606 *
2607 * @param DMAx DMAx instance
2608 * @retval None.
2609 */
2610 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
2611 {
2612 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 2));
2613 }
2614
2615 /**
2616 * @brief Clear Channel 3 transfer complete flag.
2617 *
2618 * Register|BitsName
2619 * --------|--------
2620 * CLR_TFR | CLEAR
2621 *
2622 * @param DMAx DMAx instance
2623 * @retval None.
2624 */
2625 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
2626 {
2627 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 3));
2628 }
2629
2630 /**
2631 * @brief Clear Channel 4 transfer complete flag.
2632 *
2633 * Register|BitsName
2634 * --------|--------
2635 * CLR_TFR | CLEAR
2636 *
2637 * @param DMAx DMAx instance
2638 * @retval None.
2639 */
2640 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
2641 {
2642 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 4));
2643 }
2644
2645 /**
2646 * @brief Clear DMA Channel block complete flag.
2647 *
2648 * Register|BitsName
2649 * --------|--------
2650 * CLR_BLK | CLEAR
2651 *
2652 * @param DMAx DMAx instance
2653 * @param channel This parameter can be one of the following values:
2654 * @arg @ref LL_DMA_CHANNEL_0
2655 * @arg @ref LL_DMA_CHANNEL_1
2656 * @arg @ref LL_DMA_CHANNEL_2
2657 * @arg @ref LL_DMA_CHANNEL_3
2658 * @arg @ref LL_DMA_CHANNEL_4
2659 * @retval None.
2660 */
2661 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2662 {
2663 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << channel));
2664 }
2665
2666 /**
2667 * @brief Clear Channel 0 Block Complete flag.
2668 *
2669 * Register|BitsName
2670 * --------|--------
2671 * CLR_BLK | CLEAR
2672 *
2673 * @param DMAx DMAx instance
2674 * @retval None.
2675 */
2676 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
2677 {
2678 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 0));
2679 }
2680
2681 /**
2682 * @brief Clear Channel 1 Block Complete flag.
2683 *
2684 * Register|BitsName
2685 * --------|--------
2686 * CLR_BLK | CLEAR
2687 *
2688 * @param DMAx DMAx instance
2689 * @retval None.
2690 */
2691 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
2692 {
2693 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 1));
2694 }
2695
2696 /**
2697 * @brief Clear Channel 2 Block Complete flag.
2698 *
2699 * Register|BitsName
2700 * --------|--------
2701 * CLR_BLK | CLEAR
2702 *
2703 * @param DMAx DMAx instance
2704 * @retval None.
2705 */
2706 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
2707 {
2708 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 2));
2709 }
2710
2711 /**
2712 * @brief Clear Channel 3 Block Complete flag.
2713 *
2714 * Register|BitsName
2715 * --------|--------
2716 * CLR_BLK | CLEAR
2717 *
2718 * @param DMAx DMAx instance
2719 * @retval None.
2720 */
2721 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
2722 {
2723 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 3));
2724 }
2725
2726 /**
2727 * @brief Clear Channel 4 Block Complete flag.
2728 *
2729 * Register|BitsName
2730 * --------|--------
2731 * CLR_BLK | CLEAR
2732 *
2733 * @param DMAx DMAx instance
2734 * @retval None.
2735 */
2736 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
2737 {
2738 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[2], (1 << 4));
2739 }
2740
2741 /**
2742 * @brief Clear DMA Channel source transaction Complete flag.
2743 *
2744 * Register|BitsName
2745 * --------|--------
2746 * CLR_SRC_TRN | CLEAR
2747 *
2748 * @param DMAx DMAx instance
2749 * @param channel This parameter can be one of the following values:
2750 * @arg @ref LL_DMA_CHANNEL_0
2751 * @arg @ref LL_DMA_CHANNEL_1
2752 * @arg @ref LL_DMA_CHANNEL_2
2753 * @arg @ref LL_DMA_CHANNEL_3
2754 * @arg @ref LL_DMA_CHANNEL_4
2755 * @retval None.
2756 */
2757 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2758 {
2759 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << channel));
2760 }
2761
2762 /**
2763 * @brief Clear Channel 0 source transaction Complete flag.
2764 *
2765 * Register|BitsName
2766 * --------|--------
2767 * CLR_SRC_TRN | CLEAR
2768 *
2769 * @param DMAx DMAx instance
2770 * @retval None.
2771 */
2772 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
2773 {
2774 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 0));
2775 }
2776
2777 /**
2778 * @brief Clear Channel 1 source transaction Complete flag.
2779 *
2780 * Register|BitsName
2781 * --------|--------
2782 * CLR_SRC_TRN | CLEAR
2783 *
2784 * @param DMAx DMAx instance
2785 * @retval None.
2786 */
2787 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
2788 {
2789 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 1));
2790 }
2791
2792 /**
2793 * @brief Clear Channel 2 source transaction Complete flag.
2794 *
2795 * Register|BitsName
2796 * --------|--------
2797 * CLR_SRC_TRN | CLEAR
2798 *
2799 * @param DMAx DMAx instance
2800 * @retval None.
2801 */
2802 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
2803 {
2804 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 2));
2805 }
2806
2807 /**
2808 * @brief Clear Channel 3 source transaction Complete flag.
2809 *
2810 * Register|BitsName
2811 * --------|--------
2812 * CLR_SRC_TRN | CLEAR
2813 *
2814 * @param DMAx DMAx instance
2815 * @retval None.
2816 */
2817 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
2818 {
2819 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 3));
2820 }
2821
2822 /**
2823 * @brief Clear Channel 4 source transaction Complete flag.
2824 *
2825 * Register|BitsName
2826 * --------|--------
2827 * CLR_SRC_TRN | CLEAR
2828 *
2829 * @param DMAx DMAx instance
2830 * @retval None.
2831 */
2832 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
2833 {
2834 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[4], (1 << 4));
2835 }
2836
2837 /**
2838 * @brief Clear DMA Channel destination transaction Complete flag.
2839 *
2840 * Register|BitsName
2841 * --------|--------
2842 * CLR_DST_TRN | CLEAR
2843 *
2844 * @param DMAx DMAx instance
2845 * @param channel This parameter can be one of the following values:
2846 * @arg @ref LL_DMA_CHANNEL_0
2847 * @arg @ref LL_DMA_CHANNEL_1
2848 * @arg @ref LL_DMA_CHANNEL_2
2849 * @arg @ref LL_DMA_CHANNEL_3
2850 * @arg @ref LL_DMA_CHANNEL_4
2851 * @retval None.
2852 */
2853 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2854 {
2855 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << channel));
2856 }
2857
2858 /**
2859 * @brief Clear Channel 0 destination transaction Complete status.
2860 *
2861 * Register|BitsName
2862 * --------|--------
2863 * CLR_DST_TRN | CLEAR
2864 *
2865 * @param DMAx DMAx instance
2866 * @retval None.
2867 */
2868 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
2869 {
2870 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 0));
2871 }
2872
2873 /**
2874 * @brief Clear Channel 1 destination transaction Complete flag.
2875 *
2876 * Register|BitsName
2877 * --------|--------
2878 * CLR_DST_TRN | CLEAR
2879 *
2880 * @param DMAx DMAx instance
2881 * @retval None.
2882 */
2883 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
2884 {
2885 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 1));
2886 }
2887
2888 /**
2889 * @brief Clear Channel 2 destination transaction Complete flag.
2890 *
2891 * Register|BitsName
2892 * --------|--------
2893 * CLR_DST_TRN | CLEAR
2894 *
2895 * @param DMAx DMAx instance
2896 * @retval None.
2897 */
2898 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
2899 {
2900 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 2));
2901 }
2902
2903 /**
2904 * @brief Clear Channel 3 destination transaction Complete flag.
2905 *
2906 * Register|BitsName
2907 * --------|--------
2908 * CLR_DST_TRN | CLEAR
2909 *
2910 * @param DMAx DMAx instance
2911 * @retval None.
2912 */
2913 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
2914 {
2915 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 3));
2916 }
2917
2918 /**
2919 * @brief Clear Channel 4 destination transaction Complete flag.
2920 *
2921 * Register|BitsName
2922 * --------|--------
2923 * CLR_DST_TRN | CLEAR
2924 *
2925 * @param DMAx DMAx instance
2926 * @retval None.
2927 */
2928 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
2929 {
2930 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[6], (1 << 4));
2931 }
2932
2933 /**
2934 * @brief Clear DMA Channel error flag.
2935 *
2936 * Register|BitsName
2937 * --------|--------
2938 * CLR_ERR | CLEAR
2939 *
2940 * @param DMAx DMAx instance
2941 * @param channel This parameter can be one of the following values:
2942 * @arg @ref LL_DMA_CHANNEL_0
2943 * @arg @ref LL_DMA_CHANNEL_1
2944 * @arg @ref LL_DMA_CHANNEL_2
2945 * @arg @ref LL_DMA_CHANNEL_3
2946 * @arg @ref LL_DMA_CHANNEL_4
2947 * @retval None.
2948 */
2949 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
2950 {
2951 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << channel));
2952 }
2953
2954 /**
2955 * @brief Clear Channel 0 error flag.
2956 *
2957 * Register|BitsName
2958 * --------|--------
2959 * CLR_ERR | CLEAR
2960 *
2961 * @param DMAx DMAx instance
2962 * @retval None.
2963 */
2964 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
2965 {
2966 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 0));
2967 }
2968
2969 /**
2970 * @brief Clear Channel 1 error flag.
2971 *
2972 * Register|BitsName
2973 * --------|--------
2974 * CLR_ERR | CLEAR
2975 *
2976 * @param DMAx DMAx instance
2977 * @retval None.
2978 */
2979 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
2980 {
2981 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 1));
2982 }
2983
2984 /**
2985 * @brief Clear Channel 2 error flag.
2986 *
2987 * Register|BitsName
2988 * --------|--------
2989 * CLR_ERR | CLEAR
2990 *
2991 * @param DMAx DMAx instance
2992 * @retval None.
2993 */
2994 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
2995 {
2996 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 2));
2997 }
2998
2999 /**
3000 * @brief Clear Channel 3 error flag.
3001 *
3002 * Register|BitsName
3003 * --------|--------
3004 * CLR_ERR | CLEAR
3005 *
3006 * @param DMAx DMAx instance
3007 * @retval None.
3008 */
3009 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
3010 {
3011 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 3));
3012 }
3013
3014 /**
3015 * @brief Clear Channel 4 error flag.
3016 *
3017 * Register|BitsName
3018 * --------|--------
3019 * CLR_ERR | CLEAR
3020 *
3021 * @param DMAx DMAx instance
3022 * @retval None.
3023 */
3024 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
3025 {
3026 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[8], (1 << 4));
3027 }
3028
3029 /** @} */
3030
3031 /** @defgroup DMA_LL_EF_IT_Management IT_Management
3032 * @{
3033 */
3034
3035 /**
3036 * @brief Enable Transfer Complete interrupt.
3037 *
3038 * Register|BitsName
3039 * --------|--------
3040 * MASK_TFR | TFR_WE&TFR
3041 *
3042 * @param DMAx DMAx instance
3043 * @param channel This parameter can be one of the following values:
3044 * @arg @ref LL_DMA_CHANNEL_0
3045 * @arg @ref LL_DMA_CHANNEL_1
3046 * @arg @ref LL_DMA_CHANNEL_2
3047 * @arg @ref LL_DMA_CHANNEL_3
3048 * @arg @ref LL_DMA_CHANNEL_4
3049 * @retval None
3050 */
3051 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3052 {
3053 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3054 }
3055
3056 /**
3057 * @brief Enable Block Complete interrupt.
3058 *
3059 * Register|BitsName
3060 * --------|--------
3061 * MASK_BLK | BLK_WE&BLK
3062 *
3063 * @param DMAx DMAx instance
3064 * @param channel This parameter can be one of the following values:
3065 * @arg @ref LL_DMA_CHANNEL_0
3066 * @arg @ref LL_DMA_CHANNEL_1
3067 * @arg @ref LL_DMA_CHANNEL_2
3068 * @arg @ref LL_DMA_CHANNEL_3
3069 * @arg @ref LL_DMA_CHANNEL_4
3070 * @retval None
3071 */
3072 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3073 {
3074 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3075 }
3076
3077 /**
3078 * @brief Enable source transaction Complete interrupt.
3079 *
3080 * Register|BitsName
3081 * --------|--------
3082 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3083 *
3084 * @param DMAx DMAx instance
3085 * @param channel This parameter can be one of the following values:
3086 * @arg @ref LL_DMA_CHANNEL_0
3087 * @arg @ref LL_DMA_CHANNEL_1
3088 * @arg @ref LL_DMA_CHANNEL_2
3089 * @arg @ref LL_DMA_CHANNEL_3
3090 * @arg @ref LL_DMA_CHANNEL_4
3091 * @retval None
3092 */
3093 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3094 {
3095 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3096 }
3097
3098 /**
3099 * @brief Enable destination transaction Complete interrupt.
3100 *
3101 * Register|BitsName
3102 * --------|--------
3103 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3104 *
3105 * @param DMAx DMAx instance
3106 * @param channel This parameter can be one of the following values:
3107 * @arg @ref LL_DMA_CHANNEL_0
3108 * @arg @ref LL_DMA_CHANNEL_1
3109 * @arg @ref LL_DMA_CHANNEL_2
3110 * @arg @ref LL_DMA_CHANNEL_3
3111 * @arg @ref LL_DMA_CHANNEL_4
3112 * @retval None
3113 */
3114 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3115 {
3116 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3117 }
3118
3119 /**
3120 * @brief Enable error interrupt.
3121 *
3122 * Register|BitsName
3123 * --------|--------
3124 * MASK_ERR | ERR_WE&ERR
3125 *
3126 * @param DMAx DMAx instance
3127 * @param channel This parameter can be one of the following values:
3128 * @arg @ref LL_DMA_CHANNEL_0
3129 * @arg @ref LL_DMA_CHANNEL_1
3130 * @arg @ref LL_DMA_CHANNEL_2
3131 * @arg @ref LL_DMA_CHANNEL_3
3132 * @arg @ref LL_DMA_CHANNEL_4
3133 * @retval None
3134 */
3135 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3136 {
3137 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3138 }
3139
3140 /**
3141 * @brief Disable Transfer Complete interrupt.
3142 *
3143 * Register|BitsName
3144 * --------|--------
3145 * MASK_TFR | TFR_WE&TFR
3146 *
3147 * @param DMAx DMAx instance
3148 * @param channel This parameter can be one of the following values:
3149 * @arg @ref LL_DMA_CHANNEL_0
3150 * @arg @ref LL_DMA_CHANNEL_1
3151 * @arg @ref LL_DMA_CHANNEL_2
3152 * @arg @ref LL_DMA_CHANNEL_3
3153 * @arg @ref LL_DMA_CHANNEL_4
3154 * @retval None
3155 */
3156 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3157 {
3158 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3159 }
3160
3161 /**
3162 * @brief Disable Block Complete interrupt.
3163 *
3164 * Register|BitsName
3165 * --------|--------
3166 * MASK_BLK | BLK_WE&BLK
3167 *
3168 * @param DMAx DMAx instance
3169 * @param channel This parameter can be one of the following values:
3170 * @arg @ref LL_DMA_CHANNEL_0
3171 * @arg @ref LL_DMA_CHANNEL_1
3172 * @arg @ref LL_DMA_CHANNEL_2
3173 * @arg @ref LL_DMA_CHANNEL_3
3174 * @arg @ref LL_DMA_CHANNEL_4
3175 * @retval None
3176 */
3177 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3178 {
3179 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3180 }
3181
3182 /**
3183 * @brief Disable source transaction Complete interrupt.
3184 *
3185 * Register|BitsName
3186 * --------|--------
3187 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3188 *
3189 * @param DMAx DMAx instance
3190 * @param channel This parameter can be one of the following values:
3191 * @arg @ref LL_DMA_CHANNEL_0
3192 * @arg @ref LL_DMA_CHANNEL_1
3193 * @arg @ref LL_DMA_CHANNEL_2
3194 * @arg @ref LL_DMA_CHANNEL_3
3195 * @arg @ref LL_DMA_CHANNEL_4
3196 * @retval None
3197 */
3198 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3199 {
3200 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3201 }
3202
3203 /**
3204 * @brief Disable destination transaction Complete interrupt.
3205 *
3206 * Register|BitsName
3207 * --------|--------
3208 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3209 *
3210 * @param DMAx DMAx instance
3211 * @param channel This parameter can be one of the following values:
3212 * @arg @ref LL_DMA_CHANNEL_0
3213 * @arg @ref LL_DMA_CHANNEL_1
3214 * @arg @ref LL_DMA_CHANNEL_2
3215 * @arg @ref LL_DMA_CHANNEL_3
3216 * @arg @ref LL_DMA_CHANNEL_4
3217 * @retval None
3218 */
3219 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3220 {
3221 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3222 }
3223
3224 /**
3225 * @brief Disable error interrupt.
3226 *
3227 * Register|BitsName
3228 * --------|--------
3229 * MASK_ERR | ERR_WE&ERR
3230 *
3231 * @param DMAx DMAx instance
3232 * @param channel This parameter can be one of the following values:
3233 * @arg @ref LL_DMA_CHANNEL_0
3234 * @arg @ref LL_DMA_CHANNEL_1
3235 * @arg @ref LL_DMA_CHANNEL_2
3236 * @arg @ref LL_DMA_CHANNEL_3
3237 * @arg @ref LL_DMA_CHANNEL_4
3238 * @retval None
3239 */
3240 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
3241 {
3242 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3243 }
3244
3245 /**
3246 * @brief Check if DMA Transfer interrupt is enabled or disabled.
3247 *
3248 * Register|BitsName
3249 * --------|--------
3250 * MASK_TFR | TFR
3251 *
3252 * @param DMAx DMA instance.
3253 * @param channel This parameter can be one of the following values:
3254 * @arg @ref LL_DMA_CHANNEL_0
3255 * @arg @ref LL_DMA_CHANNEL_1
3256 * @arg @ref LL_DMA_CHANNEL_2
3257 * @arg @ref LL_DMA_CHANNEL_3
3258 * @arg @ref LL_DMA_CHANNEL_4
3259 * @retval State of bit (1 or 0).
3260 */
3261 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3262 {
3263 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3264 }
3265
3266 /**
3267 * @brief Check if DMA block interrupt is enabled or disabled.
3268 *
3269 * Register|BitsName
3270 * --------|--------
3271 * MASK_BLK | BLK_WE&BLK
3272 *
3273 * @param DMAx DMA instance.
3274 * @param channel This parameter can be one of the following values:
3275 * @arg @ref LL_DMA_CHANNEL_0
3276 * @arg @ref LL_DMA_CHANNEL_1
3277 * @arg @ref LL_DMA_CHANNEL_2
3278 * @arg @ref LL_DMA_CHANNEL_3
3279 * @arg @ref LL_DMA_CHANNEL_4
3280 * @retval State of bit (1 or 0).
3281 */
3282 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3283 {
3284 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[2], (1 << channel)) == (1 << channel));
3285 }
3286
3287 /**
3288 * @brief Check if DMA source transaction interrupt is enabled or disabled.
3289 *
3290 * Register|BitsName
3291 * --------|--------
3292 * MASK_SRC_TRN | SRC_TRN
3293 *
3294 * @param DMAx DMA instance.
3295 * @param channel This parameter can be one of the following values:
3296 * @arg @ref LL_DMA_CHANNEL_0
3297 * @arg @ref LL_DMA_CHANNEL_1
3298 * @arg @ref LL_DMA_CHANNEL_2
3299 * @arg @ref LL_DMA_CHANNEL_3
3300 * @arg @ref LL_DMA_CHANNEL_4
3301 * @retval State of bit (1 or 0).
3302 */
3303 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3304 {
3305 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[4], (1 << channel)) == (1 << channel));
3306 }
3307
3308 /**
3309 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
3310 *
3311 * Register|BitsName
3312 * --------|--------
3313 * MASK_DST_TRN | DST_TRN
3314 *
3315 * @param DMAx DMA instance.
3316 * @param channel This parameter can be one of the following values:
3317 * @arg @ref LL_DMA_CHANNEL_0
3318 * @arg @ref LL_DMA_CHANNEL_1
3319 * @arg @ref LL_DMA_CHANNEL_2
3320 * @arg @ref LL_DMA_CHANNEL_3
3321 * @arg @ref LL_DMA_CHANNEL_4
3322 * @retval State of bit (1 or 0).
3323 */
3324 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3325 {
3326 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[6], (1 << channel)) == (1 << channel));
3327 }
3328
3329 /**
3330 * @brief Check if DMA error interrupt is enabled or disabled.
3331 *
3332 * Register|BitsName
3333 * --------|--------
3334 * MASK_ERR | ERR
3335 *
3336 * @param DMAx DMA instance.
3337 * @param channel This parameter can be one of the following values:
3338 * @arg @ref LL_DMA_CHANNEL_0
3339 * @arg @ref LL_DMA_CHANNEL_1
3340 * @arg @ref LL_DMA_CHANNEL_2
3341 * @arg @ref LL_DMA_CHANNEL_3
3342 * @arg @ref LL_DMA_CHANNEL_4
3343 * @retval State of bit (1 or 0).
3344 */
3345 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3346 {
3347 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[8], (1 << channel)) == (1 << channel));
3348 }
3349
3350 /**
3351 * @brief Enable DMA channel interrupt.
3352 *
3353 * Register|BitsName
3354 * --------|--------
3355 * CTLL | INI_EN
3356 *
3357 * @param DMAx DMA instance.
3358 * @param channel This parameter can be one of the following values:
3359 * @arg @ref LL_DMA_CHANNEL_0
3360 * @arg @ref LL_DMA_CHANNEL_1
3361 * @arg @ref LL_DMA_CHANNEL_2
3362 * @arg @ref LL_DMA_CHANNEL_3
3363 * @arg @ref LL_DMA_CHANNEL_4
3364 * @retval None
3365 */
3366 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
3367 {
3368 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3369 }
3370
3371 /**
3372 * @brief Disable DMA channel interrupt.
3373 *
3374 * Register|BitsName
3375 * --------|--------
3376 * CTLL | INI_EN
3377 *
3378 * @param DMAx DMA instance.
3379 * @param channel This parameter can be one of the following values:
3380 * @arg @ref LL_DMA_CHANNEL_0
3381 * @arg @ref LL_DMA_CHANNEL_1
3382 * @arg @ref LL_DMA_CHANNEL_2
3383 * @arg @ref LL_DMA_CHANNEL_3
3384 * @arg @ref LL_DMA_CHANNEL_4
3385 * @retval None
3386 */
3387 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
3388 {
3389 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
3390 }
3391
3392 /**
3393 * @brief Check if DMA interrupt is enabled or disabled.
3394 *
3395 * Register|BitsName
3396 * --------|--------
3397 * CTL_LO | INT_EN
3398 *
3399 * @param DMAx DMA instance.
3400 * @param channel This parameter can be one of the following values:
3401 * @arg @ref LL_DMA_CHANNEL_0
3402 * @arg @ref LL_DMA_CHANNEL_1
3403 * @arg @ref LL_DMA_CHANNEL_2
3404 * @arg @ref LL_DMA_CHANNEL_3
3405 * @arg @ref LL_DMA_CHANNEL_4
3406 * @retval State of bit (1 or 0).
3407 */
3408 __STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
3409 {
3410 return (READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN) == DMA_CTLL_INI_EN);
3411 }
3412
3413 /** @} */
3414
3415 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3416 * @{
3417 */
3418
3419 /**
3420 * @brief De-initialize the DMA registers to their default reset values.
3421 * @param DMAx DMAx instance
3422 * @param channel This parameter can be one of the following values:
3423 * @arg @ref LL_DMA_CHANNEL_0
3424 * @arg @ref LL_DMA_CHANNEL_1
3425 * @arg @ref LL_DMA_CHANNEL_2
3426 * @arg @ref LL_DMA_CHANNEL_3
3427 * @arg @ref LL_DMA_CHANNEL_4
3428 * @retval An error_status_t enumeration value:
3429 * - SUCCESS: DMA registers are de-initialized
3430 * - ERROR: DMA registers are not de-initialized
3431 */
3432 void ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
3433
3434 /**
3435 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
3436 * @param DMAx DMAx instance
3437 * @param channel This parameter can be one of the following values:
3438 * @arg @ref LL_DMA_CHANNEL_0
3439 * @arg @ref LL_DMA_CHANNEL_1
3440 * @arg @ref LL_DMA_CHANNEL_2
3441 * @arg @ref LL_DMA_CHANNEL_3
3442 * @arg @ref LL_DMA_CHANNEL_4
3443 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
3444 * @retval An error_status_t enumeration value:
3445 * - SUCCESS: DMA registers are initialized
3446 * - ERROR: Not applicable
3447 */
3448 void ll_dma_init(dma_regs_t *DMAx, uint32_t channel, const ll_dma_init_t *p_dma_init);
3449
3450 /**
3451 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
3452 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
3453 * whose fields will be set to default values.
3454 * @retval None
3455 */
3456 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
3457
3458 /** @} */
3459
3460 /** @} */
3461
3462 #endif /* DMA */
3463
3464 #ifdef __cplusplus
3465 }
3466 #endif
3467
3468 #endif /* LL_DMA_H */
3469
3470 /** @} */
3471
3472 /** @} */
3473
3474 /** @} */
ll_dma_clear_flag_err
__STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel error flag.
Definition: ll_dma.h:2949
ll_dma_get_source_burst_length
__STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Burst Transaction Length.
Definition: ll_dma.h:883
_ll_dma_init::src_address
uint32_t src_address
Definition: ll_dma.h:78
ll_dma_get_source_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Source increment mode.
Definition: ll_dma.h:687
ll_dma_get_channel_priority_level
__STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
Get Channel priority level.
Definition: ll_dma.h:985
ll_dma_disable_it_err
__STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
Disable error interrupt.
Definition: ll_dma.h:3240
ll_dma_clear_flag_srct3
__STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
Clear Channel 3 source transaction Complete flag.
Definition: ll_dma.h:2817
ll_dma_is_active_flag_dstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel destination transaction complete flag.
Definition: ll_dma.h:2373
ll_dma_clear_flag_tfr0
__STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
Clear Channel 0 transfer complete flag.
Definition: ll_dma.h:2580
ll_dma_clear_flag_tfr3
__STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
Clear Channel 3 transfer complete flag.
Definition: ll_dma.h:2625
ll_dma_clear_flag_blk3
__STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
Clear Channel 3 Block Complete flag.
Definition: ll_dma.h:2721
ll_dma_disable_channel
__STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel.
Definition: ll_dma.h:441
ll_dma_is_active_flag_tfr4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
Indicate the status of Channel 4 transfer complete flag.
Definition: ll_dma.h:2158
ll_dma_set_max_amba_burst
__STATIC_INLINE void ll_dma_set_max_amba_burst(dma_regs_t *DMAx, uint32_t channel, uint32_t beats)
Set Maximum AMBA Burst Length.
Definition: ll_dma.h:1445
ll_dma_is_active_flag_dstt3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
Indicate the status of Channel 3 destination transaction complete flag.
Definition: ll_dma.h:2433
ll_dma_clear_flag_dstt3
__STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
Clear Channel 3 destination transaction Complete flag.
Definition: ll_dma.h:2913
ll_dma_is_active_flag_blk0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
Indicate the status of Channel 0 block complete flag.
Definition: ll_dma.h:2195
gr5405.h
ll_dma_is_active_flag_err0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
Indicate the status of Channel 0 error flag.
Definition: ll_dma.h:2484
ll_dma_clear_flag_srct
__STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel source transaction Complete flag.
Definition: ll_dma.h:2757
ll_dma_disable
__STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
Disable DMA Module.
Definition: ll_dma.h:382
ll_dma_is_active_flag_err1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
Indicate the status of Channel 1 error flag.
Definition: ll_dma.h:2499
ll_dma_clear_flag_err4
__STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
Clear Channel 4 error flag.
Definition: ll_dma.h:3024
ll_dma_get_source_width
__STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
Get Source transfer width.
Definition: ll_dma.h:785
ll_dma_clear_flag_srct1
__STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
Clear Channel 1 source transaction Complete flag.
Definition: ll_dma.h:2787
ll_dma_get_source_peripheral
__STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get source peripheral for DMA instance on Channel x.
Definition: ll_dma.h:1321
ll_dma_config_transfer
__STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
Configure all parameters link to DMA transfer.
Definition: ll_dma.h:586
ll_dma_is_active_flag_srct0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
Indicate the status of Channel 0 source transaction complete flag.
Definition: ll_dma.h:2292
ll_dma_get_destination_increment_mode
__STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
Get Destination increment mode.
Definition: ll_dma.h:736
ll_dma_set_m2m_dst_address
__STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Destination address.
Definition: ll_dma.h:1202
ll_dma_is_empty_fifo
__STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel FIFO is empty.
Definition: ll_dma.h:551
ll_dma_enable_bus_lock
__STATIC_INLINE void ll_dma_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
Enable Bus lock.
Definition: ll_dma.h:1552
ll_dma_clear_flag_srct4
__STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
Clear Channel 4 source transaction Complete flag.
Definition: ll_dma.h:2832
ll_dma_disable_it_dstt
__STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Disable destination transaction Complete interrupt.
Definition: ll_dma.h:3219
ll_dma_clear_flag_blk1
__STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
Clear Channel 1 Block Complete flag.
Definition: ll_dma.h:2691
ll_dma_get_channel_lock_level
__STATIC_INLINE uint32_t ll_dma_get_channel_lock_level(dma_regs_t *DMAx, uint32_t channel)
Get channel lock level.
Definition: ll_dma.h:1643
ll_dma_clear_flag_tfr
__STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel transfer complete flag.
Definition: ll_dma.h:2565
ll_dma_disable_bus_lock
__STATIC_INLINE void ll_dma_disable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
Disable Bus lock.
Definition: ll_dma.h:1573
ll_dma_disable_it_srct
__STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Disable source transaction Complete interrupt.
Definition: ll_dma.h:3198
ll_dma_set_destination_width
__STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
Set Destination transfer width.
Definition: ll_dma.h:810
ll_dma_clear_flag_dstt4
__STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
Clear Channel 4 destination transaction Complete flag.
Definition: ll_dma.h:2928
ll_dma_is_enabled_channel
__STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is enabled or disabled.
Definition: ll_dma.h:464
ll_dma_get_m2m_src_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Source address.
Definition: ll_dma.h:1225
ll_dma_get_destination_burst_length
__STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
Get Destination Burst Transaction Length.
Definition: ll_dma.h:932
ll_dma_clear_flag_err0
__STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
Clear Channel 0 error flag.
Definition: ll_dma.h:2964
ll_dma_clear_flag_err3
__STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
Clear Channel 3 error flag.
Definition: ll_dma.h:3009
ll_dma_is_enable_it_dstt
__STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Check if DMA destination transaction interrupt is enabled or disabled.
Definition: ll_dma.h:3324
ll_dma_clear_flag_tfr1
__STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
Clear Channel 1 transfer complete flag.
Definition: ll_dma.h:2595
ll_dma_req_src_burst_transaction
__STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Burst Transaction Request.
Definition: ll_dma.h:1736
ll_dma_set_source_peripheral
__STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set source peripheral for DMA instance on Channel x.
Definition: ll_dma.h:1285
ll_dma_set_block_size
__STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
Set the block size of a transfer.
Definition: ll_dma.h:1008
ll_dma_set_source_address
__STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Source address.
Definition: ll_dma.h:1090
ll_dma_is_active_flag_rdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntDstTran Interrupt flag.
Definition: ll_dma.h:2041
ll_dma_is_active_flag_dstt0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
Indicate the status of Channel 0 destination transaction complete flag.
Definition: ll_dma.h:2388
ll_dma_deinit
void ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel)
De-initialize the DMA registers to their default reset values.
ll_dma_get_m2m_dst_address
__STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
Get the Memory to Memory Destination address.
Definition: ll_dma.h:1247
ll_dma_is_active_flag_dstt4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
Indicate the status of Channel 4 destination transaction complete flag.
Definition: ll_dma.h:2448
ll_dma_config_address
__STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address, uint32_t dst_address, uint32_t direction)
Configure the Source and Destination addresses.
Definition: ll_dma.h:1062
ll_dma_req_dst_last_single_transaction
__STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Single Transaction Request.
Definition: ll_dma.h:1851
ll_dma_disable_it_tfr
__STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Disable Transfer Complete interrupt.
Definition: ll_dma.h:3156
ll_dma_set_destination_increment_mode
__STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_increment_mode)
Set Destination increment mode.
Definition: ll_dma.h:712
ll_dma_is_active_flag_blk1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
Indicate the status of Channel 1 block complete flag.
Definition: ll_dma.h:2210
ll_dma_is_enable_it_blk
__STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Check if DMA block interrupt is enabled or disabled.
Definition: ll_dma.h:3282
ll_dma_disable_it
__STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
Disable DMA channel interrupt.
Definition: ll_dma.h:3387
ll_dma_is_active_flag_srct1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
Indicate the status of Channel 1 source transaction complete flag.
Definition: ll_dma.h:2307
_ll_dma_init
LL DMA init Structure definition.
Definition: ll_dma.h:77
ll_dma_is_active_flag_err3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
Indicate the status of Channel 3 error flag.
Definition: ll_dma.h:2529
ll_dma_is_enable_bus_lock
__STATIC_INLINE uint32_t ll_dma_is_enable_bus_lock(dma_regs_t *DMAx, uint32_t channel)
CHeck if the Bus lock enable.
Definition: ll_dma.h:1594
ll_dma_struct_init
void ll_dma_struct_init(ll_dma_init_t *p_dma_init)
Set each field of a ll_dma_init_t type structure to default value.
ll_dma_is_active_flag_tfr1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
Indicate the status of Channel 1 transfer complete flag.
Definition: ll_dma.h:2113
ll_dma_get_destination_address
__STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
Get Destination address.
Definition: ll_dma.h:1154
ll_dma_is_active_flag_err
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel error flag.
Definition: ll_dma.h:2469
ll_dma_req_src_single_transaction
__STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Single Transaction Request.
Definition: ll_dma.h:1714
ll_dma_clear_flag_tfr2
__STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
Clear Channel 2 transfer complete flag.
Definition: ll_dma.h:2610
ll_dma_is_enable_it_tfr
__STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Check if DMA Transfer interrupt is enabled or disabled.
Definition: ll_dma.h:3261
ll_dma_is_active_flag_srct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel source transaction complete flag.
Definition: ll_dma.h:2277
ll_dma_clear_flag_srct0
__STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
Clear Channel 0 source transaction Complete flag.
Definition: ll_dma.h:2772
ll_dma_is_active_flag_dstt2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
Indicate the status of Channel 2 destination transaction complete flag.
Definition: ll_dma.h:2418
ll_dma_is_active_flag_blk2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
Indicate the status of Channel 2 block complete flag.
Definition: ll_dma.h:2225
ll_dma_set_channel_lock_level
__STATIC_INLINE void ll_dma_set_channel_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
Set channel lock level.
Definition: ll_dma.h:1619
ll_dma_enable_it_tfr
__STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
Enable Transfer Complete interrupt.
Definition: ll_dma.h:3051
ll_dma_req_dst_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Burst Transaction Request.
Definition: ll_dma.h:1828
ll_dma_enable_channel
__STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel.
Definition: ll_dma.h:420
ll_dma_set_source_burst_length
__STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Source Burst Transaction Length.
Definition: ll_dma.h:859
ll_dma_is_active_flag_dstt1
__STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
Indicate the status of Channel 1 destination transaction complete flag.
Definition: ll_dma.h:2403
ll_dma_is_active_flag_srct4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
Indicate the status of Channel 4 source transaction complete flag.
Definition: ll_dma.h:2352
ll_dma_is_active_flag_tfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel transfer complete flag.
Definition: ll_dma.h:2083
ll_dma_is_active_flag_srct2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
Indicate the status of Channel 2 source transaction complete flag.
Definition: ll_dma.h:2322
ll_dma_get_max_amba_burst
__STATIC_INLINE uint32_t ll_dma_get_max_amba_burst(dma_regs_t *DMAx, uint32_t channel)
Get source status after each block tranfer completed.
Definition: ll_dma.h:1468
ll_dma_is_active_flag_gsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
Get DMA Module global source transaction complete interrupt status.
Definition: ll_dma.h:1927
ll_dma_enable_channel_lock
__STATIC_INLINE void ll_dma_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
Enable channel lock.
Definition: ll_dma.h:1489
ll_dma_is_active_flag_err2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
Indicate the status of Channel 2 error flag.
Definition: ll_dma.h:2514
_ll_dma_init::block_size
uint32_t block_size
Definition: ll_dma.h:112
ll_dma_get_source_address
__STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
Get Source address.
Definition: ll_dma.h:1133
ll_dma_select_handshaking
__STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel, uint32_t src_handshaking, uint32_t dst_handshaking)
Set source and destination source handshaking interface.
Definition: ll_dma.h:1421
_ll_dma_init::src_peripheral
uint32_t src_peripheral
Definition: ll_dma.h:118
ll_dma_is_active_flag_blk4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
Indicate the status of Channel 4 block complete flag.
Definition: ll_dma.h:2255
ll_dma_set_destination_peripheral
__STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
Set destination peripheral for DMA instance on Channel x.
Definition: ll_dma.h:1358
ll_dma_get_destination_width
__STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
Get Destination transfer width.
Definition: ll_dma.h:834
_ll_dma_init::dst_data_width
uint32_t dst_data_width
Definition: ll_dma.h:107
ll_dma_is_active_flag_gerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
Get DMA Module global error interrupt status.
Definition: ll_dma.h:1957
ll_dma_set_source_increment_mode
__STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
Set Source increment mode.
Definition: ll_dma.h:663
ll_dma_is_active_flag_gtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
Get DMA Module global transfer complete interrupt status.
Definition: ll_dma.h:1897
ll_dma_set_destination_address
__STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Destination address.
Definition: ll_dma.h:1112
ll_dma_is_enable_channel_lock
__STATIC_INLINE uint32_t ll_dma_is_enable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
CHeck if the channel lock enable.
Definition: ll_dma.h:1531
ll_dma_req_src_last_single_transaction
__STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Single Transaction Request.
Definition: ll_dma.h:1759
ll_dma_resume_channel
__STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
Resume a DMA channel.
Definition: ll_dma.h:509
ll_dma_clear_flag_dstt0
__STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
Clear Channel 0 destination transaction Complete status.
Definition: ll_dma.h:2868
_ll_dma_init::src_data_width
uint32_t src_data_width
Definition: ll_dma.h:102
ll_dma_clear_flag_err2
__STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
Clear Channel 2 error flag.
Definition: ll_dma.h:2994
ll_dma_set_m2m_src_address
__STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
Set the Memory to Memory Source address.
Definition: ll_dma.h:1177
ll_dma_enable_it_blk
__STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Enable Block Complete interrupt.
Definition: ll_dma.h:3072
_ll_dma_init::direction
uint32_t direction
Definition: ll_dma.h:86
ll_dma_clear_flag_dstt
__STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel destination transaction Complete flag.
Definition: ll_dma.h:2853
ll_dma_enable
__STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
Enable DMA Module.
Definition: ll_dma.h:363
ll_dma_clear_flag_blk0
__STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
Clear Channel 0 Block Complete flag.
Definition: ll_dma.h:2676
ll_dma_clear_flag_dstt2
__STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
Clear Channel 2 destination transaction Complete flag.
Definition: ll_dma.h:2898
_ll_dma_init::dst_peripheral
uint32_t dst_peripheral
Definition: ll_dma.h:123
ll_dma_disable_it_blk
__STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
Disable Block Complete interrupt.
Definition: ll_dma.h:3177
_ll_dma_init::priority
uint32_t priority
Definition: ll_dma.h:128
ll_dma_is_active_flag_err4
__STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
Indicate the status of Channel 4 error flag.
Definition: ll_dma.h:2544
ll_dma_is_active_flag_gdstt
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
Get DMA Module global destination transaction complete interrupt status.
Definition: ll_dma.h:1942
ll_dma_req_dst_single_transaction
__STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Single Transaction Request.
Definition: ll_dma.h:1806
ll_dma_get_data_transfer_direction
__STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
Get Data transfer direction (read from peripheral or from memory).
Definition: ll_dma.h:638
ll_dma_enable_it_err
__STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Enable error interrupt.
Definition: ll_dma.h:3135
ll_dma_req_dst_last_burst_transaction
__STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Destination Last Burst Transaction Request.
Definition: ll_dma.h:1875
ll_dma_is_active_flag_rerr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntErr Interrupt flag.
Definition: ll_dma.h:2062
_ll_dma_init::dst_increment_mode
uint32_t dst_increment_mode
Definition: ll_dma.h:97
ll_dma_clear_flag_tfr4
__STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
Clear Channel 4 transfer complete flag.
Definition: ll_dma.h:2640
ll_dma_disable_channel_lock
__STATIC_INLINE void ll_dma_disable_channel_lock(dma_regs_t *DMAx, uint32_t channel)
Disable channel lock.
Definition: ll_dma.h:1510
ll_dma_clear_flag_srct2
__STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
Clear Channel 2 source transaction Complete flag.
Definition: ll_dma.h:2802
ll_dma_is_enable_it_srct
__STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Check if DMA source transaction interrupt is enabled or disabled.
Definition: ll_dma.h:3303
_ll_dma_init::dst_address
uint32_t dst_address
Definition: ll_dma.h:82
ll_dma_is_active_flag_tfr2
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
Indicate the status of Channel 2 transfer complete flag.
Definition: ll_dma.h:2128
ll_dma_is_enable
__STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
Check if DMA Module is enabled or disabled.
Definition: ll_dma.h:397
ll_dma_get_destination_peripheral
__STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
Get destination peripheral for DMA instance on Channel x.
Definition: ll_dma.h:1394
ll_dma_clear_flag_blk2
__STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
Clear Channel 2 Block Complete flag.
Definition: ll_dma.h:2706
ll_dma_set_destination_burst_length
__STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
Set Destination Burst Transaction Length.
Definition: ll_dma.h:908
ll_dma_req_src_last_burst_transaction
__STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
Source Last Burst Transaction Request.
Definition: ll_dma.h:1783
ll_dma_enable_it_dstt
__STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
Enable destination transaction Complete interrupt.
Definition: ll_dma.h:3114
_ll_dma_init::src_increment_mode
uint32_t src_increment_mode
Definition: ll_dma.h:92
ll_dma_set_data_transfer_direction
__STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
Set Data transfer direction (read from peripheral or from memory).
Definition: ll_dma.h:613
ll_dma_is_active_flag_tfr0
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
Indicate the status of Channel 0 transfer complete flag.
Definition: ll_dma.h:2098
ll_dma_is_active_flag_tfr3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
Indicate the status of Channel 3 transfer complete flag.
Definition: ll_dma.h:2143
ll_dma_is_suspended
__STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
Check if DMA channel is suspended or resumed.
Definition: ll_dma.h:530
ll_dma_get_bus_lock_level
__STATIC_INLINE uint32_t ll_dma_get_bus_lock_level(dma_regs_t *DMAx, uint32_t channel)
Get bus lock level.
Definition: ll_dma.h:1692
ll_dma_init_t
struct _ll_dma_init ll_dma_init_t
LL DMA init Structure definition.
ll_dma_set_bus_lock_level
__STATIC_INLINE void ll_dma_set_bus_lock_level(dma_regs_t *DMAx, uint32_t channel, uint32_t lock_level)
Set bus lock level.
Definition: ll_dma.h:1668
ll_dma_set_source_width
__STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
Set Source transfer width.
Definition: ll_dma.h:761
ll_dma_is_active_flag_rsrct
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntSrcTran Interrupt flag.
Definition: ll_dma.h:2020
ll_dma_clear_flag_blk4
__STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
Clear Channel 4 Block Complete flag.
Definition: ll_dma.h:2736
ll_dma_is_active_flag_blk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Indicate the status of DMA Channel block complete flag.
Definition: ll_dma.h:2180
ll_dma_is_active_flag_rtfr
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntTfr Interrupt flag.
Definition: ll_dma.h:1978
ll_dma_suspend_channel
__STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
Suspend a DMA channel transfer.
Definition: ll_dma.h:487
ll_dma_clear_flag_dstt1
__STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
Clear Channel 1 destination transaction Complete flag.
Definition: ll_dma.h:2883
ll_dma_clear_flag_blk
__STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
Clear DMA Channel block complete flag.
Definition: ll_dma.h:2661
ll_dma_enable_it
__STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
Enable DMA channel interrupt.
Definition: ll_dma.h:3366
ll_dma_init
void ll_dma_init(dma_regs_t *DMAx, uint32_t channel, const ll_dma_init_t *p_dma_init)
Initialize the DMA registers according to the specified parameters in p_dma_init.
ll_dma_is_active_flag_blk3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
Indicate the status of Channel 3 block complete flag.
Definition: ll_dma.h:2240
ll_dma_is_active_flag_rblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
Indicate the Raw Status of IntBlock Interrupt flag.
Definition: ll_dma.h:1999
ll_dma_set_channel_priority_level
__STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
Set Channel priority level.
Definition: ll_dma.h:959
ll_dma_get_block_size
__STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
Get the block size of a transfer.
Definition: ll_dma.h:1031
ll_dma_is_active_flag_gblk
__STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
Get DMA Module global block complete interrupt status.
Definition: ll_dma.h:1912
ll_dma_enable_it_srct
__STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
Enable source transaction Complete interrupt.
Definition: ll_dma.h:3093
ll_dma_is_enable_it_err
__STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
Check if DMA error interrupt is enabled or disabled.
Definition: ll_dma.h:3345
ll_dma_clear_flag_err1
__STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
Clear Channel 1 error flag.
Definition: ll_dma.h:2979
ll_dma_is_enable_it
__STATIC_INLINE uint32_t ll_dma_is_enable_it(dma_regs_t *DMAx, uint32_t channel)
Check if DMA interrupt is enabled or disabled.
Definition: ll_dma.h:3408
ll_dma_is_active_flag_srct3
__STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
Indicate the status of Channel 3 source transaction complete flag.
Definition: ll_dma.h:2337