ll_uart.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef LL_UART_H
53 #define LL_UART_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5x.h"
61
62 #if defined (UART0) || defined (UART1)
63
64 /** @defgroup UART_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup UART_LL_ES_INIT UART Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL UART init Structure definition
75 */
76 typedef struct _ll_uart_init_t
77 {
78 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
79
80 This feature can be modified afterwards using unitary function @ref ll_uart_set_baud_rate().*/
81
82 uint32_t data_bits; /**< Specifies the number of data bits transmitted or received in a frame.
83 This parameter can be a value of @ref UART_LL_EC_DATABITS.
84
85 This feature can be modified afterwards using unitary function @ref ll_uart_set_data_bits_length().*/
86
87 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
88 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
89
90 This feature can be modified afterwards using unitary function @ref ll_uart_set_stop_bits_length().*/
91
92 uint32_t parity; /**< Specifies the parity mode.
93 This parameter can be a value of @ref UART_LL_EC_PARITY.
94
95 This feature can be modified afterwards using unitary function @ref ll_uart_set_parity().*/
96
97 uint32_t hw_flow_ctrl; /**< Specifies whether the hardware flow control mode is enabled or disabled.
98 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
99
100 This feature can be modified afterwards using unitary function @ref ll_uart_set_hw_flow_ctrl().*/
101 } ll_uart_init_t;
102
103 /** @} */
104
105 /** @} */
106
107 /**
108 * @defgroup UART_LL_MACRO Defines
109 * @{
110 */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
114 * @{
115 */
116
117 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
118 * @brief Flags definitions which can be used with LL_UART_ReadReg function
119 * @{
120 */
121 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
122 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
123 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
124 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
125 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register empty flag */
126 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
127 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
128
129 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
130 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
131 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
132 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
133 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
134 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
135
136 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
137 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
138 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
139 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
140 /** @} */
141
142 /** @defgroup UART_LL_EC_IT IT Defines
143 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
144 * @{
145 */
146 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status Interrupt */
147 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line Status Interrupt */
148 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding Register Empty Interrupt */
149 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available Interrupt and Character Timeout Interrupt */
150 /** @} */
151
152 /** @defgroup UART_LL_EC_PARITY Parity Control
153 * @{
154 */
155 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
156 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and Odd Parity is selected */
157 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and Even Parity is selected */
158 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and Stick Parity 0 is selected */
159 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and Stick Parity 1 is selected */
160 /** @} */
161
162 /** @defgroup UART_LL_EC_DATABITS Data Bits
163 * @{
164 */
165 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit, 5 data bits, n stop bits */
166 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit, 6 data bits, n stop bits */
167 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit, 7 data bits, n stop bits */
168 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit, 8 data bits, n stop bits */
169 /** @} */
170
171 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
172 * @{
173 */
174 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
175 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
176 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
177 /** @} */
178
179 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
180 * @{
181 */
182 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow control disabled */
183 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow control enabled */
184 /** @} */
185
186 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
187 * @{
188 */
189 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
190 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
191 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
192 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
193 /** @} */
194
195 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
196 * @{
197 */
198 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
199 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
200 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
201 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
202 /** @} */
203
204 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
205 * @{
206 */
207 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
208 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
209 /** @} */
210
211 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
212 * @{
213 */
214 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
215 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
216 /** @} */
217
218 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
219 * @{
220 */
221
222 /**
223 * @brief LL UART InitStrcut default configuartion
224 */
225 #define LL_UART_DEFAULT_CONFIG \
226 { \
227 .baud_rate = 9600U, \
228 .data_bits = LL_UART_DATABITS_8B, \
229 .stop_bits = LL_UART_STOPBITS_1, \
230 .parity = LL_UART_PARITY_NONE, \
231 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
232 }
233 /** @} */
234
235 /** @} */
236
237 /* Exported macro ------------------------------------------------------------*/
238 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
239 * @{
240 */
241
242 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
243 * @{
244 */
245
246 /**
247 * @brief Write a value in UART register
248 * @param __instance__ UART instance
249 * @param __REG__ Register to be written
250 * @param __VALUE__ Value to be written in the register
251 * @retval None
252 */
253 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
254
255 /**
256 * @brief Read a value in UART register
257 * @param __instance__ UART instance
258 * @param __REG__ Register to be read
259 * @retval Register value
260 */
261 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
262
263 /** @} */
264
265 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
266 * @{
267 */
268
269 /**
270 * @brief Compute UARTDIV value according to Peripheral Clock and
271 * expected Baud Rate (32 bits value of UARTDIV is returned)
272 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
273 * @param __BAUDRATE__ Baud rate value to achieve
274 * @retval UARTDIV value to be used for DLL,DLH registers
275 */
276 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
277
278 /**
279 * @brief Compute UARTDLF value according to Peripheral Clock and
280 * expected Baud Rate (32 bits value of UARTDLF is returned)
281 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
282 * @param __BAUDRATE__ Baud rate value to achieve
283 * @retval UARTDLF value to be used for DLL,DLH registers
284 */
285 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
286
287 /** @} */
288
289 /** @} */
290
291 /** @} */
292
293 /* Exported functions --------------------------------------------------------*/
294 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
295 * @{
296 */
297
298 /** @defgroup UART_LL_EF_Configuration Configuration functions
299 * @{
300 */
301
302 /**
303 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
304 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
305 * (Baud rate value != 0)
306 *
307 * Register|BitsName
308 * --------|--------
309 * DLL | DLL
310 * DLH | DLH
311 *
312 * @param UARTx UART instance
313 * @param peripheral_clock Peripheral Clock
314 * @param baud_rate Baud Rate
315 * @retval None
316 */
317 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
318 {
319 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
320
321 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
322 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
323 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> 8) & UART_DLH_DLH);
324 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
325 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
326 }
327
328 /**
329 * @brief Return current Baud Rate value
330 * @note In case of non-initialized or invalid value stored in DLL,DLH and DLF register, the value 0 will be returned..
331 *
332 * Register|BitsName
333 * --------|--------
334 * DLL | DLL
335 * DLH | DLH
336 *
337 * @param UARTx UART instance
338 * @param peripheral_clock Peripheral Clock
339 * @retval Baud Rate
340 */
341 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
342 {
343 register uint32_t uartdiv = 0x0U;
344 register uint32_t baud = 0x0U;
345
346 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
347 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << 8);
348 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
349
350 if ((uartdiv != 0) && (UARTx->DLF != 0x0U))
351 {
352 baud = peripheral_clock / (16 * uartdiv + UARTx->DLF);
353 }
354
355 return baud;
356 }
357
358 /**
359 * @brief Set the length of the data bits
360 *
361 * Register|BitsName
362 * --------|--------
363 * LCR | DLS
364 *
365 * @param UARTx UART instance
366 * @param data_bits This parameter can be one of the following values:
367 * @arg @ref LL_UART_DATABITS_5B
368 * @arg @ref LL_UART_DATABITS_6B
369 * @arg @ref LL_UART_DATABITS_7B
370 * @arg @ref LL_UART_DATABITS_8B
371 *
372 * @retval None
373 */
374 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
375 {
376 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
377 }
378
379 /**
380 * @brief Return the length of the data bits
381 *
382 * Register|BitsName
383 * --------|--------
384 * LCR | DLS
385 *
386 * @param UARTx UART instance
387 * @retval Returned value can be one of the following values:
388 * @arg @ref LL_UART_DATABITS_5B
389 * @arg @ref LL_UART_DATABITS_6B
390 * @arg @ref LL_UART_DATABITS_7B
391 * @arg @ref LL_UART_DATABITS_8B
392 */
393 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
394 {
395 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
396 }
397
398 /**
399 * @brief Set the length of the stop bits
400 *
401 * Register|BitsName
402 * --------|--------
403 * LCR | STOP
404 *
405 * @param UARTx UART instance
406 * @param stop_bits This parameter can be one of the following values:
407 * @arg @ref LL_UART_STOPBITS_1
408 * @arg @ref LL_UART_STOPBITS_1_5 (*)
409 * @arg @ref LL_UART_STOPBITS_2 (*)
410 *
411 * (*) STOPBITS_1_5 only valid when DataBits = 5
412 * (*) STOPBITS_2 is invalid when DataBits = 5
413 * @retval None
414 */
415 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
416 {
417 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
418 }
419
420 /**
421 * @brief Retrieve the length of the stop bits
422 *
423 * Register|BitsName
424 * --------|--------
425 * LCR | STOP
426 *
427 * @param UARTx UART instance
428 * @retval Returned value can be one of the following values:
429 * @arg @ref LL_UART_STOPBITS_1
430 * @arg @ref LL_UART_STOPBITS_1_5
431 * @arg @ref LL_UART_STOPBITS_2
432 */
433 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
434 {
435 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
436 }
437
438 /**
439 * @brief Configure Parity.
440 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
441 * When the parity control is enabled (Odd,Even,0,1), computed parity bit is inserted at the MSB position
442 * and parity is checked on the received data.
443 *
444 * Register|BitsName
445 * --------|--------
446 * LCR | SP
447 * LCR | EPS
448 * LCR | PEN
449 *
450 * @param UARTx UART instance
451 * @param parity This parameter can be one of the following values:
452 * @arg @ref LL_UART_PARITY_NONE
453 * @arg @ref LL_UART_PARITY_EVEN
454 * @arg @ref LL_UART_PARITY_ODD
455 * @arg @ref LL_UART_PARITY_SP0
456 * @arg @ref LL_UART_PARITY_SP1
457 * @retval None
458 */
459 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
460 {
461 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
462 }
463
464 /**
465 * @brief Return Parity configuration
466 *
467 * Register|BitsName
468 * --------|--------
469 * LCR | SP
470 * LCR | EPS
471 * LCR | PEN
472 *
473 * @param UARTx UART instance
474 * @retval Returned value can be one of the following values:
475 * @arg @ref LL_UART_PARITY_NONE
476 * @arg @ref LL_UART_PARITY_EVEN
477 * @arg @ref LL_UART_PARITY_ODD
478 * @arg @ref LL_UART_PARITY_SP0
479 * @arg @ref LL_UART_PARITY_SP1
480 */
481 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
482 {
483 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
484 }
485
486 /**
487 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
488 * @note This function call is equivalent to the following function call sequence :
489 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
490 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
491 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
492 *
493 * Register|BitsName
494 * --------|--------
495 * LCR | PS
496 * LCR | EPS
497 * LCR | PEN
498 * LCR | STOP
499 * LCR | DLS
500 *
501 * @param UARTx UART instance
502 * @param data_bits This parameter can be one of the following values:
503 * @arg @ref LL_UART_DATABITS_5B
504 * @arg @ref LL_UART_DATABITS_6B
505 * @arg @ref LL_UART_DATABITS_7B
506 * @arg @ref LL_UART_DATABITS_8B
507 * @param parity This parameter can be one of the following values:
508 * @arg @ref LL_UART_PARITY_NONE
509 * @arg @ref LL_UART_PARITY_EVEN
510 * @arg @ref LL_UART_PARITY_ODD
511 * @arg @ref LL_UART_PARITY_SP0
512 * @arg @ref LL_UART_PARITY_SP1
513 * @param stop_bits This parameter can be one of the following values:
514 * @arg @ref LL_UART_STOPBITS_1
515 * @arg @ref LL_UART_STOPBITS_1_5 (*)
516 * @arg @ref LL_UART_STOPBITS_2 (*)
517 *
518 * (*) STOPBITS_1_5 only valid when DataBits = 5
519 * (*) STOPBITS_2 is invalid when DataBits = 5
520 * @retval None
521 */
522 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx,
523 uint32_t data_bits,
524 uint32_t parity,
525 uint32_t stop_bits)
526 {
527 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
528 }
529
530 /**
531 * @brief Set the break control
532 * @note If set to one, the serial output is forced to the spacing (logic 0) state.
533 *
534 * Register|BitsName
535 * --------|--------
536 * LCR | BC
537 *
538 * @param UARTx UART instance
539 *
540 * @retval None
541 */
542 __STATIC_INLINE void ll_uart_set_bc(uart_regs_t *UARTx)
543 {
544 SET_BITS(UARTx->LCR, UART_LCR_BC);
545 }
546
547 /**
548 * @brief Reset the break control
549 *
550 * Register|BitsName
551 * --------|--------
552 * LCR | BC
553 *
554 * @param UARTx UART instance
555 *
556 * @retval None
557 */
558 __STATIC_INLINE void ll_uart_reset_bc(uart_regs_t *UARTx)
559 {
560 CLEAR_BITS(UARTx->LCR, UART_LCR_BC);
561 }
562
563 /**
564 * @brief Set UART RTS pin state to Active/Inactive
565 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
566 *
567 * Register|BitsName
568 * --------|--------
569 * SRTS | SRTS
570 * MCR | RTS
571 *
572 * @param UARTx UART instance
573 * @param pin_state This parameter can be one of the following values:
574 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
575 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
576 * @retval None
577 */
578 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
579 {
580 WRITE_REG(UARTx->SRTS, pin_state);
581 }
582
583 /**
584 * @brief Get UART RTS pin state
585 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
586 *
587 * Register|BitsName
588 * --------|--------
589 * SRTS | SRTS
590 * MCR | RTS
591 *
592 * @param UARTx UART instance
593 * @retval Returned value can be one of the following values:
594 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
595 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
596 */
597 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
598 {
599 return (uint32_t)(READ_REG(UARTx->SRTS));
600 }
601
602 /**
603 * @brief Get UART CTS pin state
604 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
605 *
606 * Register|BitsName
607 * --------|--------
608 * MSR | CTS
609 *
610 * @param UARTx UART instance
611 * @retval Returned value can be one of the following values:
612 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
613 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
614 */
615 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
616 {
617 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_POS);
618 }
619
620 /**
621 * @brief Indicate if CTS is changed since the last time the MSR was read
622 *
623 * Register|BitsName
624 * --------|--------
625 * MSR | DCTS
626 *
627 * @param UARTx UART instance
628 * @retval State of bit (1 or 0).
629 */
630 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
631 {
632 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_POS);
633 }
634
635 /**
636 * @brief Configure SIR mode enable
637 * @note This function is used to Enable UART SIR mode.
638 *
639 * Register|BitsName
640 * --------|--------
641 * MCR | SIRE
642 *
643 * @param UARTx UART instance
644 * @retval None
645 */
646 __STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
647 {
648 SET_BITS(UARTx->MCR, UART_MCR_SIRE);
649 }
650
651 /**
652 * @brief Configure SIR mode disable
653 * @note This function is used to Disable UART SIR mode.
654 *
655 * Register|BitsName
656 * --------|--------
657 * MCR | SIRE
658 *
659 * @param UARTx UART instance
660 * @retval None
661 */
662 __STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
663 {
664 CLEAR_BITS(UARTx->MCR, UART_MCR_SIRE);
665 }
666
667 /**
668 * @brief Return SIR mode state
669 * @note This function is used to return UART SIR mode state.
670 *
671 * Register|BitsName
672 * --------|--------
673 * MCR | SIRE
674 *
675 * @param UARTx UART instance
676 * @retval State of bit (1 or 0).
677 */
678 __STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
679 {
680 return (READ_BITS(UARTx->MCR, UART_MCR_SIRE) == UART_MCR_SIRE);
681 }
682
683 /**
684 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
685 * @note This function is used to Enable/Disable UART Auto Flow Control.
686 *
687 * Register|BitsName
688 * --------|--------
689 * MCR | AFCE
690 * MCR | RTS
691 *
692 * @param UARTx UART instance
693 * @param hw_flow_ctrl This parameter can be one of the following values:
694 * @arg @ref LL_UART_HWCONTROL_NONE
695 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
696 * @retval None
697 */
698 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
699 {
700 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
701 }
702
703 /**
704 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
705 *
706 * Register|BitsName
707 * --------|--------
708 * MCR | AFCE
709 * MCR | RTS
710 *
711 * @param UARTx UART instance
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_UART_HWCONTROL_NONE
714 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
715 */
716 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
717 {
718 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
719 }
720
721 /**
722 * @brief Enable Break sending
723 *
724 * Register|BitsName
725 * --------|--------
726 * LCR | BC
727 *
728 * @param UARTx UART instance
729 * @retval None
730 */
731 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
732 {
733 WRITE_REG(UARTx->SBCR, 0x1U);
734 }
735
736 /**
737 * @brief Disable Break sending
738 *
739 * Register|BitsName
740 * --------|--------
741 * LCR | BC
742 *
743 * @param UARTx UART instance
744 * @retval None
745 */
746 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
747 {
748 WRITE_REG(UARTx->SBCR, 0x0U);
749 }
750
751 /**
752 * @brief Indicate if Break sending is enabled
753 *
754 * Register|BitsName
755 * --------|--------
756 * LCR | BC
757 *
758 * @param UARTx UART instance
759 * @retval State of bit (1 or 0).
760 */
761 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
762 {
763 return READ_REG(UARTx->SBCR);
764 }
765
766 /**
767 * @brief Enable TX FIFO and RX FIFO
768 *
769 * Register|BitsName
770 * --------|--------
771 * SFE | SFE
772 *
773 * @param UARTx UART instance
774 * @retval None
775 */
776 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
777 {
778 WRITE_REG(UARTx->SFE, 0x1U);
779 }
780
781 /**
782 * @brief Disable TX FIFO and RX FIFO
783 *
784 * Register|BitsName
785 * --------|--------
786 * SFE | SFE
787 *
788 * @param UARTx UART instance
789 * @retval None
790 */
791 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
792 {
793 WRITE_REG(UARTx->SFE, 0x0U);
794 }
795
796 /**
797 * @brief Indicate if TX FIFO and RX FIFO is enabled
798 *
799 * Register|BitsName
800 * --------|--------
801 * SFE | SFE
802 *
803 * @param UARTx UART instance
804 * @retval State of bit (1 or 0).
805 */
806 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
807 {
808 return READ_REG(UARTx->SFE);
809 }
810
811 /**
812 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
813 *
814 * Register|BitsName
815 * --------|--------
816 * STET | STET
817 *
818 * @param UARTx UART instance
819 * @param threshold This parameter can be one of the following values:
820 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
821 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
822 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
823 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
824 * @retval None
825 */
826 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
827 {
828 WRITE_REG(UARTx->STET, threshold);
829 }
830
831 /**
832 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
833 *
834 * Register|BitsName
835 * --------|--------
836 * STET | STET
837 *
838 * @param UARTx UART instance
839 * @retval Returned value can be one of the following values:
840 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
841 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
842 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
843 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
844 */
845 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
846 {
847 return (uint32_t)(READ_REG(UARTx->STET));
848 }
849
850 /**
851 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
852 *
853 * Register|BitsName
854 * --------|--------
855 * SRT | SRT
856 *
857 * @param UARTx UART instance
858 * @param threshold This parameter can be one of the following values:
859 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
860 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
861 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
862 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
863 * @retval None
864 */
865 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
866 {
867 WRITE_REG(UARTx->SRT, threshold);
868 }
869
870 /**
871 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
872 *
873 * Register|BitsName
874 * --------|--------
875 * SRT | SRT
876 *
877 * @param UARTx UART instance
878 * @retval Returned value can be one of the following values:
879 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
880 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
881 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
882 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
883 */
884 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
885 {
886 return (uint32_t)(READ_REG(UARTx->SRT));
887 }
888
889 /**
890 * @brief Get FIFO Transmission Level
891 *
892 * Register|BitsName
893 * --------|--------
894 * TFL | TFL
895 *
896 * @param UARTx UART instance
897 * @retval Returned value can be one of the following values:
898 */
899 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
900 {
901 return (uint32_t)(READ_REG(UARTx->TFL));
902 }
903
904 /**
905 * @brief Get FIFO reception Level
906 *
907 * Register|BitsName
908 * --------|--------
909 * RFL | RFL
910 *
911 * @param UARTx UART instance
912 * @retval Returned value can be one of the following values:
913 */
914 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
915 {
916 return (uint32_t)(READ_REG(UARTx->RFL));
917 }
918
919 /**
920 * @brief Flush Receive FIFO
921 *
922 * Register|BitsName
923 * --------|--------
924 * SRR | RFR
925 *
926 * @param UARTx UART instance
927 * @retval None
928 */
929 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
930 {
931 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
932 }
933
934 /**
935 * @brief Flush Transmit FIFO
936 *
937 * Register|BitsName
938 * --------|--------
939 * SRR | XFR
940 *
941 * @param UARTx UART instance
942 * @retval None
943 */
944 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
945 {
946 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
947 }
948
949 /**
950 * @brief Reset UART
951 * @note This function asynchronously resets the DW_apb_uart and synchronously
952 * removes the reset assertion. For a two clock implementation, both pclk
953 * and sclk domains will be reset.
954 *
955 * Register|BitsName
956 * --------|--------
957 * SRR | UR
958 *
959 * @param UARTx UART instance
960 * @retval None
961 */
962 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
963 {
964 WRITE_REG(UARTx->SRR, UART_SRR_UR);
965 }
966
967 /** @} */
968
969 /** @defgroup UART_LL_EF_IT_Management IT_Management
970 * @{
971 */
972
973 /**
974 * @brief Enable Modem Status Interrupt
975 *
976 * Register|BitsName
977 * --------|--------
978 * IER | EDSSI
979 *
980 * @param UARTx UART instance
981 * @retval None
982 */
983 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
984 {
985 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
986 }
987
988 /**
989 * @brief Enable Receiver Line Status Interrupt
990 *
991 * Register|BitsName
992 * --------|--------
993 * IER | RLS
994 *
995 * @param UARTx UART instance
996 * @retval None
997 */
998 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
999 {
1000 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1001 }
1002
1003 /**
1004 * @brief Enable Transmit Holding Register Empty Interrupt
1005 *
1006 * Register|BitsName
1007 * --------|--------
1008 * IER | PTIME
1009 * IER | ETBEI
1010 *
1011 * @param UARTx UART instance
1012 * @retval None
1013 */
1014 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
1015 {
1016 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1017 }
1018
1019 /**
1020 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
1021 *
1022 * Register|BitsName
1023 * --------|--------
1024 * IER | ERBFI
1025 *
1026 * @param UARTx UART instance
1027 * @retval None
1028 */
1029 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
1030 {
1031 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1032 }
1033
1034 /**
1035 * @brief Disable Modem Status Interrupt
1036 *
1037 * Register|BitsName
1038 * --------|--------
1039 * IER | EDSSI
1040 *
1041 * @param UARTx UART instance
1042 * @retval None
1043 */
1044 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
1045 {
1046 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
1047 }
1048
1049 /**
1050 * @brief Disable Receiver Line Status Interrupt
1051 *
1052 * Register|BitsName
1053 * --------|--------
1054 * IER | RLS
1055 *
1056 * @param UARTx UART instance
1057 * @retval None
1058 */
1059 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
1060 {
1061 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1062 }
1063
1064 /**
1065 * @brief Disable Transmit Holding Register Empty Interrupt
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * IER | PTIME
1070 * IER | ETBEI
1071 *
1072 * @param UARTx UART instance
1073 * @retval None
1074 */
1075 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
1076 {
1077 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1078 }
1079
1080 /**
1081 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1082 *
1083 * Register|BitsName
1084 * --------|--------
1085 * IER | ERBFI
1086 *
1087 * @param UARTx UART instance
1088 * @retval None
1089 */
1090 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1091 {
1092 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1093 }
1094
1095 /**
1096 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1097 *
1098 * Register|BitsName
1099 * --------|--------
1100 * IER | EDSSI
1101 *
1102 * @param UARTx UART instance
1103 * @retval State of bit (1 or 0).
1104 */
1105 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1106 {
1107 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1108 }
1109
1110 /**
1111 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1112 *
1113 * Register|BitsName
1114 * --------|--------
1115 * IER | RLS
1116 *
1117 * @param UARTx UART instance
1118 * @retval State of bit (1 or 0).
1119 */
1120 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1121 {
1122 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1123 }
1124
1125 /**
1126 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1127 *
1128 * Register|BitsName
1129 * --------|--------
1130 * IER | PTIME
1131 * IER | ETBEI
1132 *
1133 * @param UARTx UART instance
1134 * @retval State of bit (1 or 0).
1135 */
1136 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1137 {
1138 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == (UART_IER_PTIME | UART_IER_ETBEI));
1139 }
1140
1141 /**
1142 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1143 * is enabled or disabled.
1144 *
1145 * Register|BitsName
1146 * --------|--------
1147 * IER | ERBFI
1148 *
1149 * @param UARTx UART instance
1150 * @retval State of bit (1 or 0).
1151 */
1152 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1153 {
1154 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1155 }
1156
1157 /**
1158 * @brief Enable the specified UART Interrupt.
1159 *
1160 * Register|BitsName
1161 * --------|--------
1162 * IER | EDSSI
1163 * IER | ERLS
1164 * IER | PTIME
1165 * IER | ETBEI
1166 * IER | ERBFI
1167 *
1168 * @param UARTx UART instance
1169 * @param mask This parameter can be a combination of the following values:
1170 * @arg @ref LL_UART_IER_MS
1171 * @arg @ref LL_UART_IER_RLS
1172 * @arg @ref LL_UART_IER_THRE
1173 * @arg @ref LL_UART_IER_RDA
1174 * @retval None
1175 */
1176 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1177 {
1178 SET_BITS(UARTx->DLH_IER.IER, mask);
1179 }
1180
1181 /**
1182 * @brief Disable the specified UART Interrupt.
1183 *
1184 * Register|BitsName
1185 * --------|--------
1186 * IER | EDSSI
1187 * IER | ERLS
1188 * IER | PTIME
1189 * IER | ETBEI
1190 * IER | ERBFI
1191 *
1192 * @param UARTx UART instance
1193 * @param mask This parameter can be a combination of the following values:
1194 * @arg @ref LL_UART_IER_MS
1195 * @arg @ref LL_UART_IER_RLS
1196 * @arg @ref LL_UART_IER_THRE
1197 * @arg @ref LL_UART_IER_RDA
1198 * @retval None
1199 */
1200 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1201 {
1202 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1203 }
1204
1205 /**
1206 * @brief Check if the specified UART Interrupt is enabled or disabled.
1207 *
1208 * Register|BitsName
1209 * --------|--------
1210 * IER | EDSSI
1211 * IER | ERLS
1212 * IER | PTIME
1213 * IER | ETBEI
1214 * IER | ERBFI
1215 *
1216 * @param UARTx UART instance
1217 * @param mask This parameter can be a combination of the following values:
1218 * @arg @ref LL_UART_IER_MS
1219 * @arg @ref LL_UART_IER_RLS
1220 * @arg @ref LL_UART_IER_THRE
1221 * @arg @ref LL_UART_IER_RDA
1222 * @retval State of bit (1 or 0).
1223 */
1224 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1225 {
1226 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1227 }
1228
1229 /** @} */
1230
1231 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1232 * @{
1233 */
1234
1235 /**
1236 * @brief Get UART Receive Line Status Flag
1237 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1238 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1239 *
1240 * Register|BitsName
1241 * --------|--------
1242 * LSR | OE
1243 * LSR | PE
1244 * LSR | FE
1245 * LSR | BI
1246 * LSR | THRE
1247 * LSR | TEMT
1248 * LSR | RFE
1249 *
1250 * @param UARTx UART instance
1251 * @retval Returned value can be a combination of the following values:
1252 * @arg @ref LL_UART_LSR_OE
1253 * @arg @ref LL_UART_LSR_PE
1254 * @arg @ref LL_UART_LSR_FE
1255 * @arg @ref LL_UART_LSR_BI
1256 * @arg @ref LL_UART_LSR_THRE
1257 * @arg @ref LL_UART_LSR_TEMT
1258 * @arg @ref LL_UART_LSR_RFE
1259 */
1260 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1261 {
1262 return ((uint32_t)READ_REG(UARTx->LSR));
1263 }
1264
1265 /**
1266 * @brief Clear UART Receive Line Status Flag
1267 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1268 *
1269 * Register|BitsName
1270 * --------|--------
1271 * LSR | OE
1272 * LSR | PE
1273 * LSR | FE
1274 * LSR | BI
1275 * LSR | RFE
1276 *
1277 * @param UARTx UART instance
1278 * @retval None
1279 */
1280 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1281 {
1282 __IO uint32_t tmpreg;
1283 tmpreg = READ_REG(UARTx->LSR);
1284 (void) tmpreg;
1285 }
1286
1287 /**
1288 * @brief Check if the UART Receive FIFO Full Flag is set or not
1289 *
1290 * Register|BitsName
1291 * --------|--------
1292 * USR | RFF
1293 *
1294 * @param UARTx UART instance
1295 * @retval State of bit (1 or 0).
1296 */
1297 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1298 {
1299 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1300 }
1301
1302 /**
1303 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1304 *
1305 * Register|BitsName
1306 * --------|--------
1307 * USR | RFNE
1308 *
1309 * @param UARTx UART instance
1310 * @retval State of bit (1 or 0).
1311 */
1312 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1313 {
1314 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1315 }
1316
1317 /**
1318 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1319 *
1320 * Register|BitsName
1321 * --------|--------
1322 * USR | TFE
1323 *
1324 * @param UARTx UART instance
1325 * @retval State of bit (1 or 0).
1326 */
1327 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1328 {
1329 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1330 }
1331
1332 /**
1333 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1334 *
1335 * Register|BitsName
1336 * --------|--------
1337 * USR | TFNF
1338 *
1339 * @param UARTx UART instance
1340 * @retval State of bit (1 or 0).
1341 */
1342 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1343 {
1344 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1345 }
1346
1347 /**
1348 * @brief Get UART interrupt flags
1349 * @note The interrupt flags will be cleared after reading IIR.
1350 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1351 * and No Interrupt Pending Flag will be RESET, read IIR again can get the pended interrupt
1352 *
1353 * Register|BitsName
1354 * --------|--------
1355 * IIR | IID
1356 *
1357 * @param UARTx UART instance
1358 * @retval Returned value can be one or combination of the following values:
1359 * @arg @ref LL_UART_IIR_MS
1360 * @arg @ref LL_UART_IIR_NIP
1361 * @arg @ref LL_UART_IIR_THRE
1362 * @arg @ref LL_UART_IIR_RDA
1363 * @arg @ref LL_UART_IIR_RLS
1364 * @arg @ref LL_UART_IIR_CTO
1365 */
1366 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1367 {
1368 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1369 }
1370
1371 /** @} */
1372
1373 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1374 * @{
1375 */
1376
1377 /**
1378 * @brief Get the data register address used for DMA transfer
1379 * @note The address of data register RBR is the same as the address of THR.
1380 *
1381 * Register|BitsName
1382 * --------|--------
1383 * RBR | RBR
1384 * THR | THR
1385 *
1386 * @param UARTx UART instance
1387 * @retval Address of data register
1388 */
1389 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1390 {
1391 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1392 }
1393
1394 /** @} */
1395
1396 /** @defgroup UART_LL_EF_Data_Management Data_Management
1397 * @{
1398 */
1399
1400 /**
1401 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1402 *
1403 * Register|BitsName
1404 * --------|--------
1405 * RBR | RBR
1406 *
1407 * @param UARTx UART instance
1408 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1409 */
1410 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1411 {
1412 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1413 }
1414
1415 /**
1416 * @brief Clear Receiver Data register
1417 *
1418 * Register|BitsName
1419 * --------|--------
1420 * RBR | RBR
1421 *
1422 * @param UARTx UART instance
1423 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1424 */
1425 __STATIC_INLINE void ll_uart_clear_receive_data8(uart_regs_t *UARTx)
1426 {
1427 READ_REG(UARTx->RBR_DLL_THR.RBR);
1428 }
1429
1430
1431 /**
1432 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1433 *
1434 * Register|BitsName
1435 * --------|--------
1436 * THR | THR
1437 *
1438 * @param UARTx UART instance
1439 * @param value between Min_Data=0x00 and Max_Data=0xFF
1440 * @retval None
1441 */
1442 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1443 {
1444 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1445 }
1446
1447 /** @} */
1448
1449 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1450 * @{
1451 */
1452
1453 /**
1454 * @brief De-initialize UART registers (Registers restored to their default values).
1455 * @param UARTx UART instance
1456
1457 */
1458 void ll_uart_deinit(uart_regs_t *UARTx);
1459
1460 /**
1461 * @brief Initialize UART registers according to the specified
1462 * parameters in p_uart_init.
1463 * @param UARTx UART instance
1464 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1465 * information for the specified UART peripheral.
1466
1467 */
1468 void ll_uart_init(uart_regs_t *UARTx, const ll_uart_init_t *p_uart_init);
1469
1470 /**
1471 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1472 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1473 * whose fields will be set to default values.
1474 * @retval None
1475 */
1476 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1477
1478 /** @} */
1479
1480 /** @} */
1481
1482 #endif /* UART0 || UART1 */
1483
1484 #ifdef __cplusplus
1485 }
1486 #endif
1487
1488 #endif /* LL_UART_H */
1489
1490 /** @} */
1491
1492 /** @} */
1493
1494 /** @} */
ll_uart_is_active_flag_rfne
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
Check if the UART Receive FIFO Not Empty Flag is set or not.
Definition: ll_uart.h:1312
ll_uart_is_enabled_it_ms
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
Check if the UART Modem Status Interrupt is enabled or disabled.
Definition: ll_uart.h:1105
ll_uart_set_rts_pin_state
__STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
Set UART RTS pin state to Active/Inactive.
Definition: ll_uart.h:578
ll_uart_is_enabled_break_sending
__STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
Indicate if Break sending is enabled.
Definition: ll_uart.h:761
ll_uart_disable_it_thre
__STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
Disable Transmit Holding Register Empty Interrupt.
Definition: ll_uart.h:1075
ll_uart_enable_sir
__STATIC_INLINE void ll_uart_enable_sir(uart_regs_t *UARTx)
Configure SIR mode enable.
Definition: ll_uart.h:646
ll_uart_set_stop_bits_length
__STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
Set the length of the stop bits.
Definition: ll_uart.h:415
ll_uart_struct_init
void ll_uart_struct_init(ll_uart_init_t *p_uart_init)
Set each field of a ll_uart_init_t type structure to default value.
ll_uart_reset_bc
__STATIC_INLINE void ll_uart_reset_bc(uart_regs_t *UARTx)
Reset the break control.
Definition: ll_uart.h:558
ll_uart_set_baud_rate
__STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
Configure UART DLF and DLH register for achieving expected Baud Rate value.
Definition: ll_uart.h:317
ll_uart_is_enabled_fifo
__STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
Indicate if TX FIFO and RX FIFO is enabled.
Definition: ll_uart.h:806
ll_uart_enable_it_thre
__STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
Enable Transmit Holding Register Empty Interrupt.
Definition: ll_uart.h:1014
ll_uart_dma_get_register_address
__STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
Get the data register address used for DMA transfer.
Definition: ll_uart.h:1389
ll_uart_enabled_it_ms
__STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
Enable Modem Status Interrupt.
Definition: ll_uart.h:983
ll_uart_set_parity
__STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
Configure Parity.
Definition: ll_uart.h:459
ll_uart_disable_it_rda
__STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
Disable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: ll_uart.h:1090
__LL_UART_DLF
#define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDLF value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDLF ...
Definition: ll_uart.h:285
ll_uart_get_tx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
Get FIFO Transmission Level.
Definition: ll_uart.h:899
_ll_uart_init_t
LL UART init Structure definition.
Definition: ll_uart.h:77
ll_uart_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: ll_uart.h:884
ll_uart_get_rts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
Get UART RTS pin state.
Definition: ll_uart.h:597
ll_uart_enable_it_rls
__STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
Enable Receiver Line Status Interrupt.
Definition: ll_uart.h:998
ll_uart_disable_break_sending
__STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
Disable Break sending.
Definition: ll_uart.h:746
ll_uart_init
void ll_uart_init(uart_regs_t *UARTx, const ll_uart_init_t *p_uart_init)
Initialize UART registers according to the specified parameters in p_uart_init.
ll_uart_is_enabled_it_thre
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
Definition: ll_uart.h:1136
ll_uart_is_active_flag_rff
__STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
Check if the UART Receive FIFO Full Flag is set or not.
Definition: ll_uart.h:1297
ll_uart_enable_it
__STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
Enable the specified UART Interrupt.
Definition: ll_uart.h:1176
ll_uart_get_line_status_flag
__STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
Get UART Receive Line Status Flag.
Definition: ll_uart.h:1260
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_uart_enable_break_sending
__STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
Enable Break sending.
Definition: ll_uart.h:731
ll_uart_deinit
void ll_uart_deinit(uart_regs_t *UARTx)
De-initialize UART registers (Registers restored to their default values).
ll_uart_disable_fifo
__STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
Disable TX FIFO and RX FIFO.
Definition: ll_uart.h:791
ll_uart_clear_receive_data8
__STATIC_INLINE void ll_uart_clear_receive_data8(uart_regs_t *UARTx)
Clear Receiver Data register.
Definition: ll_uart.h:1425
ll_uart_get_data_bits_length
__STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
Return the length of the data bits.
Definition: ll_uart.h:393
ll_uart_get_cts_pin_state
__STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
Get UART CTS pin state.
Definition: ll_uart.h:615
_ll_uart_init_t::data_bits
uint32_t data_bits
Definition: ll_uart.h:82
ll_uart_is_enabled_it_rls
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
Check if the UART Receiver Line Status Interrupt is enabled or disabled.
Definition: ll_uart.h:1120
ll_uart_clear_line_status_flag
__STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
Clear UART Receive Line Status Flag.
Definition: ll_uart.h:1280
ll_uart_enable_it_rda
__STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
Enable Received Data Available Interrupt and Character Timeout Interrupt.
Definition: ll_uart.h:1029
ll_uart_get_baud_rate
__STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
Return current Baud Rate value.
Definition: ll_uart.h:341
_ll_uart_init_t::baud_rate
uint32_t baud_rate
Definition: ll_uart.h:78
ll_uart_is_enabled_it_rda
__STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
Check if the UART Received Data Available Interrupt and Character Timeout Interrupt is enabled or dis...
Definition: ll_uart.h:1152
ll_uart_transmit_data8
__STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
Definition: ll_uart.h:1442
ll_uart_disable_it
__STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
Disable the specified UART Interrupt.
Definition: ll_uart.h:1200
ll_uart_get_hw_flow_ctrl
__STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
Return HW Flow Control configuration (None or Both CTS and RTS)
Definition: ll_uart.h:716
ll_uart_set_hw_flow_ctrl
__STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
Configure HW Flow Control mode (None or Both CTS and RTS)
Definition: ll_uart.h:698
ll_uart_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: ll_uart.h:845
ll_uart_disable_it_ms
__STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
Disable Modem Status Interrupt.
Definition: ll_uart.h:1044
ll_uart_set_rx_fifo_threshold
__STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: ll_uart.h:865
ll_uart_flush_tx_fifo
__STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
Flush Transmit FIFO.
Definition: ll_uart.h:944
ll_uart_receive_data8
__STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
Read Receiver Data register (Receive Data value, 8 bits)
Definition: ll_uart.h:1410
ll_uart_get_parity
__STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
Return Parity configuration.
Definition: ll_uart.h:481
ll_uart_init_t
struct _ll_uart_init_t ll_uart_init_t
LL UART init Structure definition.
ll_uart_reset
__STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
Reset UART.
Definition: ll_uart.h:962
ll_uart_disable_it_rls
__STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
Disable Receiver Line Status Interrupt.
Definition: ll_uart.h:1059
_ll_uart_init_t::stop_bits
uint32_t stop_bits
Definition: ll_uart.h:87
_ll_uart_init_t::parity
uint32_t parity
Definition: ll_uart.h:92
ll_uart_disable_sir
__STATIC_INLINE void ll_uart_disable_sir(uart_regs_t *UARTx)
Configure SIR mode disable.
Definition: ll_uart.h:662
ll_uart_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
Get FIFO reception Level.
Definition: ll_uart.h:914
_ll_uart_init_t::hw_flow_ctrl
uint32_t hw_flow_ctrl
Definition: ll_uart.h:97
ll_uart_is_active_flag_tfe
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Empty Flag is set or not.
Definition: ll_uart.h:1327
ll_uart_config_character
__STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits, uint32_t parity, uint32_t stop_bits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
Definition: ll_uart.h:522
ll_uart_enable_fifo
__STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
Enable TX FIFO and RX FIFO.
Definition: ll_uart.h:776
ll_uart_set_tx_fifo_threshold
__STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
Set threshold of TX FIFO that triggers an THRE interrupt.
Definition: ll_uart.h:826
ll_uart_get_stop_bits_length
__STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
Retrieve the length of the stop bits.
Definition: ll_uart.h:433
ll_uart_is_changed_cts
__STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
Indicate if CTS is changed since the last time the MSR was read.
Definition: ll_uart.h:630
ll_uart_is_enabled_it
__STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
Check if the specified UART Interrupt is enabled or disabled.
Definition: ll_uart.h:1224
ll_uart_is_active_flag_tfnf
__STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
Check if the UART Transmit FIFO Not Full Flag is set or not.
Definition: ll_uart.h:1342
ll_uart_set_bc
__STATIC_INLINE void ll_uart_set_bc(uart_regs_t *UARTx)
Set the break control.
Definition: ll_uart.h:542
ll_uart_is_enabled_sir
__STATIC_INLINE uint32_t ll_uart_is_enabled_sir(uart_regs_t *UARTx)
Return SIR mode state.
Definition: ll_uart.h:678
ll_uart_flush_rx_fifo
__STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
Flush Receive FIFO.
Definition: ll_uart.h:929
__LL_UART_DIV
#define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__)
Compute UARTDIV value according to Peripheral Clock and expected Baud Rate (32 bits value of UARTDIV ...
Definition: ll_uart.h:276
ll_uart_set_data_bits_length
__STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
Set the length of the data bits.
Definition: ll_uart.h:374
ll_uart_get_it_flag
__STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
Get UART interrupt flags.
Definition: ll_uart.h:1366