app_drv_config.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file app_drv_config.h
5 * @author BLE Driver Team
6 * @brief Header file of app driver config code.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup APP_DRIVER APP DRIVER
43 * @{
44 */
45
46 /** @defgroup APP_DRIVER_CONFIG DRIVER CONFIG
47 * @brief APP DRIVER CONFIG
48 * @{
49 */
50
51
52 #ifndef _APP_DRV_CONFIG_H_
53 #define _APP_DRV_CONFIG_H_
54
55 #include "custom_config.h"
56 #include "grx_hal.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 #define APP_DVR_LOG_LVL_NONE (0) /**< None log level define */
62 #define APP_DVR_LOG_LVL_ERR (1) /**< Error log level define */
63 #define APP_DVR_LOG_LVL_WARN (2) /**< Warning log level define */
64 #define APP_DVR_LOG_LVL_INFO (3) /**< Info log level define */
65
66 #ifndef APP_DRV_LOG_LEVEL
67 #define APP_DRV_LOG_LEVEL APP_DVR_LOG_LVL_NONE /**< App driver log level setting */
68 #endif
69 #ifndef APP_DRV_LOG_INTERFACE
70 #define APP_DRV_LOG_INTERFACE printf /**< App driver log interface setting */
71 #endif
72 #ifndef APP_DRV_ASSERT_ENABLE
73 #define APP_DRV_ASSERT_ENABLE 0 /**< App driver assert enable */
74 #endif
75
76 #define APP_DRIVER_GR551X 0x0 /**< APP_DRIVER for GR551X */
77 #define APP_DRIVER_GR5525X 0x1 /**< APP_DRIVER for GR5525X */
78 #define APP_DRIVER_GR5526X 0x2 /**< APP_DRIVER for GR5526X */
79 #define APP_DRIVER_GR5332X 0x3 /**< APP_DRIVER for GR5332X */
80 #define APP_DRIVER_GR5405 0x3 /**< APP_DRIVER for GR5405 */
81
82 #ifdef SOC_GR5515
83 #define APP_DRIVER_CHIP_TYPE APP_DRIVER_GR551X /**< GR5515 chip type*/
84 #define SOC_GPIO_PINS_MAX (32) /**< GR5515 max gpio pins */
85 #define SOC_AON_PINS_MAX (8) /**< GR5515 max aon pins */
86 #elif defined(SOC_GR5X25)
87 #define APP_DRIVER_CHIP_TYPE APP_DRIVER_GR5525X /**< GR5525 chip type*/
88 #define SOC_GPIO_PINS_MAX (32) /**< GR5525 max gpio pins */
89 #define SOC_AON_PINS_MAX (8) /**< GR5525 max aon pins */
90 #elif defined(SOC_GR5526)
91 #define APP_DRIVER_CHIP_TYPE APP_DRIVER_GR5526X /**< GR5526 chip type*/
92 #define SOC_GPIO_PINS_MAX (34) /**< GR5526 max gpio pins */
93 #define SOC_AON_PINS_MAX (8) /**< GR5526 max aon pins */
94 #elif defined(SOC_GR533X)
95 #define APP_DRIVER_CHIP_TYPE APP_DRIVER_GR5332X /**< GR533X chip type*/
96 #define SOC_GPIO_PINS_MAX (14) /**< GR533X max gpio pins */
97 #define SOC_AON_PINS_MAX (8) /**< GR533X max aon pins */
98 #elif defined(SOC_GR5405)
99 #define APP_DRIVER_CHIP_TYPE APP_DRIVER_GR5405 /**< GR5405 chip type*/
100 #define SOC_GPIO_PINS_MAX (14) /**< GR5405 max gpio pins */
101 #define SOC_AON_PINS_MAX (8) /**< GR5405 max aon pins */
102 #elif defined(SOC_GR5410)
103 #define SOC_GPIO_PINS_MAX (14) /**< GR5405 max gpio pins */
104 #define SOC_AON_PINS_MAX (8) /**< GR5405 max aon pins */
105 #endif
106 #if defined(SOC_GR515)
107 #define GPIO_INSTANCE_MAX 2
108 #elif defined(SOC_GR5X25) || defined(SOC_GR5526)
109 #define GPIO_INSTANCE_MAX 3
110 #elif defined(SOC_GR533X) || defined(SOC_GR5405)
111 #define GPIO_INSTANCE_MAX 1
112 #elif defined(SOC_GR5410)
113 #define GPIO_INSTANCE_MAX 2
114 #endif
115
116 #if defined(SOC_GR5410)
117 #define GPIOA_IRQn AON_EXT_IRQn
118 #else
119 #define GPIOA_IRQn EXT0_IRQn
120 #endif
121
122 #if defined(SOC_GR5515) || defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X) || defined(SOC_GR5405)
123 #define APP_IO_AON_GPIO_ENABLE
124 #define APP_IO_MSIO_ENABLE
125 #endif
126 #if defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
127 #define APP_IO_IT_BOTH_EDGE_ENABLE
128 #endif
129 #if defined(SOC_GR5X25) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
130 #define APP_IO_STRENGTH_ENABLE
131 #define APP_IO_SPEED_ENABLE
132 #define APP_IO_INPUT_TYPE_ENABLE
133 #endif
134 #if defined(SOC_GR5515)
135 #define APP_IO_GR551X_LEGACY_ENABLE
136 #endif
137 #if defined(SOC_GR533X) || defined(SOC_GR5405)
138 #define APP_IO_MUX_ARBITRARY_V0
139 #endif
140 #if defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
141 #define APP_IO_MUX APP_IO_MUX_0
142 #elif defined(SOC_GR5X25)
143 #define APP_IO_MUX APP_IO_MUX_8
144 #elif defined(SOC_GR5515) || defined(SOC_GR5526)
145 #define APP_IO_MUX APP_IO_MUX_7
146 #endif
147
148 #if defined(SOC_GR5410)
149 #define APP_IO_GPIO_SUPPORT_ANA_MODE
150 #endif
151
152 #if defined(SOC_GR5515) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
153 #ifndef DMA0
154 #define DMA_INSTANCE_MAX 1
155 #else
156 #define DMA_INSTANCE_MAX 1
157 #endif
158 #elif defined(SOC_GR5526) || defined(SOC_GR5X25)
159 #define DMA_INSTANCE_MAX 2
160 #define APP_DMA_SG_LLP_ENABLE
161 #endif
162 #define DMA_CHANNEL_MAX DMA_Channel_NUM_MAX
163 #if defined(SOC_GR5515) || defined(SOC_GR5X25) || defined(SOC_GR5526)
164 #define APP_DMA_MODE_ENABLE
165 #endif
166 #if defined(SOC_GR5515)
167 #define APP_DMA_GR551X_LEGACY
168 #endif
169
170 #if defined(SOC_GR5410)
171 #ifndef DMA0_IRQn
172 #define DMA0_IRQn DMA_IRQn
173 #endif
174 #ifndef DMA0_REQUEST_MEM
175 #define DMA0_REQUEST_MEM 0
176 #endif
177 #ifndef DMA0_REQUEST_UART0_TX
178 #define DMA0_REQUEST_UART0_TX DMA_REQUEST_UART0_TX
179 #endif
180 #ifndef DMA0_REQUEST_UART0_RX
181 #define DMA0_REQUEST_UART0_RX DMA_REQUEST_UART0_RX
182 #endif
183 #ifndef DMA0_REQUEST_UART1_TX
184 #define DMA0_REQUEST_UART1_TX DMA_REQUEST_UART1_TX
185 #endif
186 #ifndef DMA0_REQUEST_UART1_RX
187 #define DMA0_REQUEST_UART1_RX DMA_REQUEST_UART1_RX
188 #endif
189 #ifndef DMA0_REQUEST_I2C0_TX
190 #define DMA0_REQUEST_I2C0_TX DMA_REQUEST_I2C0_TX
191 #endif
192 #ifndef DMA0_REQUEST_I2C0_RX
193 #define DMA0_REQUEST_I2C0_RX DMA_REQUEST_I2C0_RX
194 #endif
195 #ifndef DMA0_REQUEST_I2C1_TX
196 #define DMA0_REQUEST_I2C1_TX DMA_REQUEST_I2C1_TX
197 #endif
198 #ifndef DMA0_REQUEST_I2C1_RX
199 #define DMA0_REQUEST_I2C1_RX DMA_REQUEST_I2C1_RX
200 #endif
201 #ifndef DMA0_REQUEST_PWM0
202 #define DMA0_REQUEST_PWM0 DMA_REQUEST_PWM0
203 #endif
204 #ifndef DMA0_REQUEST_SPIM0_TX
205 #define DMA0_REQUEST_SPIM0_TX DMA_REQUEST_SPIM0_TX
206 #endif
207 #ifndef DMA0_REQUEST_SPIM0_RX
208 #define DMA0_REQUEST_SPIM0_RX DMA_REQUEST_SPIM0_RX
209 #endif
210 #ifndef DMA0_REQUEST_SPIM1_TX
211 #define DMA0_REQUEST_SPIM1_TX DMA_REQUEST_SPIM1_TX
212 #endif
213 #ifndef DMA0_REQUEST_SPIM1_RX
214 #define DMA0_REQUEST_SPIM1_RX DMA_REQUEST_SPIM1_RX
215 #endif
216 #ifndef DMA0_REQUEST_SPIM2_TX
217 #define DMA0_REQUEST_SPIM2_TX DMA_REQUEST_SPIM2_TX
218 #endif
219 #ifndef DMA0_REQUEST_SPIM2_RX
220 #define DMA0_REQUEST_SPIM2_RX DMA_REQUEST_SPIM2_RX
221 #endif
222 #endif
223
224 #if defined(SOC_GR515)
225 #define UART_INSTANCE_MAX 2
226 #elif defined(SOC_GR5X25)
227 #define UART_INSTANCE_MAX 4
228 #elif defined(SOC_GR5526)
229 #define UART_INSTANCE_MAX 6
230 #elif defined(SOC_GR533X) || defined(SOC_GR5405)
231 #define UART_INSTANCE_MAX 2
232 #elif defined(SOC_GR5410)
233 #define UART_INSTANCE_MAX 2
234 #endif
235 #if defined(SOC_GR515)
236 #define UART1_NO_DMA
237 #endif
238 #if defined(SOC_GR5526)
239 #define UART0_DMA1_REQ_ENABLE
240 #endif
241
242 #if defined(SOC_GR515)
243 #define I2C_INSTANCE_MAX 2
244 #elif defined(SOC_GR5X25)
245 #define I2C_INSTANCE_MAX 4
246 #elif defined(SOC_GR5526)
247 #define I2C_INSTANCE_MAX 6
248 #elif defined(SOC_GR533X) || defined(SOC_GR5405)
249 #define I2C_INSTANCE_MAX 2
250 #elif defined(SOC_GR5410)
251 #define I2C_INSTANCE_MAX 2
252 #endif
253 #if defined(SOC_GR5X25) || defined(SOC_GR5526)
254 #define I2C0_DMA1_REQ_ENABLE
255 #define I2C1_DMA1_REQ_ENABLE
256 #endif
257 #if defined(SOC_GR5515) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
258 #define I2C0_DMA0_REQ_ENABLE
259 #define I2C1_DMA0_REQ_ENABLE
260 #endif
261
262 #if defined(SOC_GR5515)
263 #define APP_I2C_TIMING_API_ENABLE
264 #define APP_I2C_TX_RX_ARBITRARY
265 #define APP_I2C_MEM_CALLBACK_ENABLE
266 #endif
267
268 #if defined(SOC_GR5515)
269 #define APP_SPI_GR551X_LEGACY
270 #endif
271 #if defined(SOC_GR5X25) || defined(SOC_GR5526)
272 #define APP_SPI_DMA_LLP_DISPLAY_ENABLE
273 #define APP_SPI_DMA1_HS_ENABLE
274 #endif
275 #if defined(SOC_GR5526)
276 #define APP_SPI_TX_WITH_IA_32_ENABLE
277 #endif
278 #if defined(SOC_GR5410)
279 #define APP_SPI_NOT_SUPPORT_SLAVE
280 #endif
281
282 #if defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
283 #define APP_TIM_IO_CAPTURE_ENABLE
284 #define APP_DUAL_TIM_IO_ENABLE
285 #endif
286 #if defined(SOC_GR5410)
287 #define APP_DUAL_TIM_IO_MUX_ENABLE
288 #endif
289 #ifndef DUAL_TIMER0_BASE
290 #define DUAL_TIMER0_BASE DUAL_TIM0_BASE
291 #endif
292 #ifndef DUAL_TIMER1_BASE
293 #define DUAL_TIMER1_BASE DUAL_TIM1_BASE
294 #endif
295
296
297 #if defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
298 #define APP_PWM_CODING_ENABLE
299 #endif
300 #if !defined(SOC_GR5515)
301 #define APP_PWM_STOP_SPEC_CH_ENABLE
302 #endif
303
304 #if defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X) || defined(SOC_GR5405)
305 #define APP_RTC_TIME_SYNC_ENABLE
306 #endif
307 #if defined(SOC_GR5X25) || defined(SOC_GR533X) || defined(SOC_GR5405)
308 #define SYSTEM_RTC_SLOW_CLOCK_ENABLE
309 #endif
310 #if defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
311 #if defined(ENV_USE_FREERTOS)
312 #define OS_TICK_BASE_RTC_ENABLE
313 #endif
314 #endif
315 #if (CFG_LPCLK_INTERNAL_EN == 0) || defined(SOC_GR5X25) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
316 #define APP_RTC_WORK_AROUND_DISABLE
317 #endif
318 #if defined(SOC_GR5515)
319 #define APP_RTC_GR551X_LEGACY
320 #endif
321 #if defined(SOC_GR5410)
322 #ifndef CALENDAR_IRQn
323 #define CALENDAR_IRQn RTC_IRQn
324 #endif
325 #define APP_RTC_NO_LL_CALENDAR_DRIVER
326 #endif
327
328 #if defined(SOC_GR5X25) || defined(SOC_GR533X) || defined(SOC_GR5405)
329 #define SYSTEM_SLOW_CLOCK_ENABLE
330 #endif
331
332 #if !defined(SOC_GR5515)
333 #define APP_ADC_VBAT_TEMP_CONV_ENABLE
334 #endif
335 #if defined(SOC_GR5526)
336 #define APP_ADC_CLOCK_START_ENABLE
337 #define APP_ADC_GET_AVG_ENABLE
338 #endif
339 #if defined(SOC_GR5515)
340 #define APP_ADC_INPUT_SRC_GR551X_LEGACY_ENABLE
341 #endif
342
343 #if defined(SOC_GR5515) || defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X) || defined(SOC_GR5405)
344 #define APP_ADC_SNSADC_ENABLE
345 #define APP_ADC_IO_TYPE APP_IO_TYPE_MSIO
346 #define APP_ADC_IO_MUX APP_IO_MUX
347 #endif
348
349 #if defined(SOC_GR5410)
350 #define APP_ADC_GPADC_ENABLE
351 #define APP_ADC_IO_TYPE APP_IO_TYPE_GPIOA
352 #define APP_ADC_IO_MUX APP_IO_MUX_2
353 #endif
354
355 #if defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
356 #define APP_BOD_DEASSERT_ENABLE
357 #endif
358 #if defined(SOC_GR533X) || defined(SOC_GR5405) || defined(SOC_GR5410)
359 #define APP_BOD_AUTO_POWER_BYPASS_ENABLE
360 #endif
361 #if defined(SOC_GR5526)
362 #define APP_BOD_LEVEL_8_15_ENABLE
363 #endif
364
365 #if !defined(SOC_GR5515)
366 #define APP_COMP_EDGE_ENABLE
367 #endif
368 #if defined(SOC_GR5515)
369 #define APP_COMP_WAKE_SOURCE_CFG_ENABLE
370 #endif
371 #if defined(SOC_GR5410)
372 #ifndef COMP_EXT_IRQn
373 #define COMP_EXT_IRQn COMP_IRQn
374 #endif
375 #ifndef COMP_EXT_IRQn
376 #define COMP_EXT_IRQn COMP_IRQn
377 #endif
378 #endif
379 #if defined(SOC_GR5515)
380 #define APP_WDT_GR515_LEGACY
381 #endif
382 #if defined(SOC_GR5410)
383 #define APP_AON_WDT_MULTI_INSTANCE
384 #define AON_WDT_INSTANCE_MAX 2
385 #define APP_AON_WDT_SUPPORT_FREQ_DIV
386 #else
387 #define AON_WDT_INSTANCE_MAX 1
388 #endif
389
390 #if defined(SOC_GR5515)
391 #define APP_PWR_MGMT_HAL_INIT_ENABLE
392 #endif
393 #if defined(SOC_GR5X25) || defined(SOC_GR5526) || defined(SOC_GR533X)
394 #define APP_PWR_MGMT_HAL_REG_ENABLE
395 #define APP_PWR_MGMT_WORD_CHECK_ENABLE
396 #if defined(SOC_GR5X25) || defined(SOC_GR5526)
397 #define APP_PWR_MGMT_WORD_CHECK_EXTRA_ENABLE
398 #endif
399 #endif
400 #if defined(SOC_GR5405) || defined(SOC_GR5410)
401 #define APP_PWR_MGMT_HAL_REG_ENABLE
402 #endif
403
404 #if defined(SOC_GR5410)
405 #define LIN_INSTANCE_MAX 2
406 #endif
407
408 /**
409 * @defgroup APP_DRV_PERIPHERAL_PRIORITY_DEFINE Defines
410 * @{
411 */
412 /**@brief APP driver peripheral priority define. */
413 #ifndef APP_DRIVER_ADC_WAKEUP_PRIORITY
414 #define APP_DRIVER_ADC_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< ADC Wakeup priority High */
415 #endif
416
417 #ifndef APP_DRIVER_AES_WAKEUP_PRIORITY
418 #define APP_DRIVER_AES_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< AES Wakeup priority Mid */
419 #endif
420
421 #ifndef APP_DRIVER_COMP_WAKEUP_PRIORITY
422 #define APP_DRIVER_COMP_WAKEUP_PRIORITY WAKEUP_PRIORITY_LOW /**< COMP Wakeup priority Low */
423 #endif
424
425 #ifndef APP_DRIVER_DUAL_TIM_WAKEUP_PRIORITY
426 #define APP_DRIVER_DUAL_TIM_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< DUAL TIM Wakeup priority Mid */
427 #endif
428
429 #ifndef APP_DRIVER_DMA_WAKEUP_PRIORITY
430 #define APP_DRIVER_DMA_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< DMA Wakeup priority High */
431 #endif
432
433 #ifndef APP_DRIVER_UART_WAKEUP_PRIORITY
434 #define APP_DRIVER_UART_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< Uart Wakeup priority High */
435 #endif
436
437 #ifndef APP_DRIVER_HMAC_WAKEUP_PRIORITY
438 #define APP_DRIVER_HMAC_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< Hmac Wakeup priority Mid */
439 #endif
440
441 #ifndef APP_DRIVER_I2C_WAKEUP_PRIORITY
442 #define APP_DRIVER_I2C_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< I2C Wakeup priority High */
443 #endif
444
445 #ifndef APP_DRIVER_I2S_WAKEUP_PRIORITY
446 #define APP_DRIVER_I2S_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< I2S Wakeup priority High */
447 #endif
448
449 #ifndef APP_DRIVER_QSPI_WAKEUP_PRIORITY
450 #define APP_DRIVER_QSPI_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< QSPI Wakeup priority High */
451 #endif
452
453 #ifndef APP_DRIVER_RNG_WAKEUP_PRIORITY
454 #define APP_DRIVER_RNG_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< RNG Wakeup priority Mid */
455 #endif
456
457 #ifndef APP_DRIVER_SPI_WAKEUP_PRIORITY
458 #define APP_DRIVER_SPI_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< SPI Wakeup priority High */
459 #endif
460
461 #ifndef APP_DRIVER_TIM_WAKEUP_PRIORITY
462 #define APP_DRIVER_TIM_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< TIM Wakeup priority Mid */
463 #endif
464
465 #ifndef APP_DRIVER_PWM_WAKEUP_PRIORITY
466 #define APP_DRIVER_PWM_WAKEUP_PRIORITY WAKEUP_PRIORITY_MID /**< PWM Wakeup priority Mid */
467 #endif
468
469 #ifndef APP_DRIVER_ISO7816_WAKEUP_PRIORITY
470 #define APP_DRIVER_ISO7816_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< ISO7816 Wakeup priority High */
471 #endif
472
473 #ifndef APP_DRIVER_PKC_WAKEUP_PRIORITY
474 #define APP_DRIVER_PKC_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< PKC Wakeup priority High */
475 #endif
476
477 #ifndef APP_DRIVER_DSPI_WAKEUP_PRIORITY
478 #define APP_DRIVER_DSPI_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< DSPI Wakeup priority High */
479 #endif
480
481 #ifndef APP_DRIVER_PDM_WAKEUP_PRIORITY
482 #define APP_DRIVER_PDM_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< PDM Wakeup priority High */
483 #endif
484
485 #ifndef APP_DRIVER_CAN_WAKEUP_PRIORITY
486 #define APP_DRIVER_CAN_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< CAN Wakeup priority High */
487 #endif
488
489 #ifndef APP_DRIVER_LIN_WAKEUP_PRIORITY
490 #define APP_DRIVER_LIN_WAKEUP_PRIORITY WAKEUP_PRIORITY_HIGH /**< LIN Wakeup priority High */
491 #endif
492
493 /**@} */
494
495
496 /**@addtogroup APP_DRV_WAKEUP_PRIORITY_ENUM Enumerations
497 * @{
498 */
499 /**@brief APP driver peripheral wakeup priority define. */
500 typedef enum
501 {
502 WAKEUP_PRIORITY_LOW = 1, /**< Wakeup priority low */
503 WAKEUP_PRIORITY_MID, /**< Wakeup priority mid */
504 WAKEUP_PRIORITY_HIGH /**< Wakeup priority high */
505 } wakeup_priority_t;
506 /** @} */
507
508 #ifndef APP_DRIVER_WAKEUP_CALL_FUN
509 //#define APP_DRIVER_WAKEUP_CALL_FUN
510 #endif
511
512 #ifdef __cplusplus
513 }
514 #endif
515
516 #endif
517
518 /** @} */
519 /** @} */
520 /** @} */
521
WAKEUP_PRIORITY_LOW
@ WAKEUP_PRIORITY_LOW
Definition: app_drv_config.h:502
wakeup_priority_t
wakeup_priority_t
APP driver peripheral wakeup priority define.
Definition: app_drv_config.h:501
WAKEUP_PRIORITY_MID
@ WAKEUP_PRIORITY_MID
Definition: app_drv_config.h:503
grx_hal.h
This file contains all the functions prototypes for the HAL module driver.
WAKEUP_PRIORITY_HIGH
@ WAKEUP_PRIORITY_HIGH
Definition: app_drv_config.h:504