hal_dma.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file hal_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_DMA DMA
47 * @brief DMA HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef HAL_DMA_H
53 #define HAL_DMA_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "ll_dma.h"
61 #include "hal_def.h"
62 #include "hal_pwr_mgmt.h"
63 #include <stdbool.h>
64
65 /* Exported types ------------------------------------------------------------*/
66 /** @addtogroup HAL_DMA_ENUMERATIONS Enumerations
67 * @{
68 */
69
70 /** @defgroup HAL_DMA_state HAL DMA state
71 * @{
72 */
73
74 /**
75 * @brief HAL DMA State Enumerations definition
76 */
77 typedef enum
78 {
79 HAL_DMA_STATE_RESET = 0x00U, /**< DMA not yet initialized or disabled */
80 HAL_DMA_STATE_READY = 0x01U, /**< DMA process success and ready for use */
81 HAL_DMA_STATE_BUSY = 0x02U, /**< DMA process is ongoing */
82 HAL_DMA_STATE_TIMEOUT = 0x03U, /**< DMA timeout state */
83 HAL_DMA_STATE_ERROR = 0x04U, /**< DMA error state */
84 } hal_dma_state_t;
85 /** @} */
86
87 /** @defgroup HAL_DMA_channel HAL DMA channel
88 * @{
89 */
90
91 /**
92 * @brief HAL DMA Channel Enumerations definition
93 */
94 typedef enum
95 {
96 DMA_Channel0 = 0U, /**< Channel 0 */
97 DMA_Channel1 = 1U, /**< Channel 1 */
98 DMA_Channel2 = 2U, /**< Channel 2 */
99 DMA_Channel3 = 3U, /**< Channel 3 */
100 DMA_Channel4 = 4U, /**< Channel 4 */
101 DMA_Channel_NUM_MAX /**< Only for check parameter, not used as input parameters. */
102 } dma_channel_t;
103 /** @} */
104
105 /** @defgroup HAL_DMA_callback_ID HAL DMA callback ID
106 * @{
107 */
108
109 /**
110 * @brief HAL DMA Callback ID Enumerations definition
111 */
112 typedef enum
113 {
114 HAL_DMA_XFER_TFR_CB_ID = 0x00, /**< Full transfer */
115 HAL_DMA_XFER_BLK_CB_ID = 0x01, /**< Block transfer */
116 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /**< Error */
117 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /**< Abort */
118 HAL_DMA_XFER_ALL_CB_ID = 0x04 /**< All */
119 } hal_dma_callback_id_t;
120 /** @} */
121
122 /** @} */
123
124
125 /** @addtogroup HAL_DMA_STRUCTURES Structures
126 * @{
127 */
128
129 /**
130 * @brief DMA LOCK Structure definition
131 */
132 typedef struct _dma_lock_config
133 {
134 uint32_t channel_lock_en; /**< Specifies the dma channel lock enable.
135 This parameter can be a value of @ref DMA_CHANNEL_LOCK_EN */
136
137 uint32_t channel_lock_level; /**< Specifies the dma channel lock level.
138 This parameter can be a value of @ref DMA_CHANNEL_LOCK_LEVEL */
139
140 uint32_t bus_lock_en; /**< Specifies the dma bus lock enable.
141 This parameter can be a value of @ref DMA_BUS_LOCK_EN */
142
143 uint32_t bus_lock_level; /**< Specifies the dma bus lock level.
144 This parameter can be a value of @ref DMA_BUS_LOCK_LEVEL */
145 } dma_lock_config;
146
147 /** @} */
148
149
150 /** @addtogroup HAL_DMA_STRUCTURES Structures
151 * @{
152 */
153
154 /**
155 * @brief DMA Configuration Structure definition
156 */
157 typedef struct _dma_init
158 {
159 uint32_t src_request; /**< Specifies the source request selected for the specified channel.
160 This parameter can be a value of @ref DMA_request */
161
162 uint32_t dst_request; /**< Specifies the destination request selected for the specified channel.
163 This parameter can be a value of @ref DMA_request */
164
165 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
166 from memory to memory or from peripheral to memory.
167 This parameter can be a value of @ref DMA_Data_transfer_direction */
168
169 uint32_t src_increment; /**< Specifies whether the srouce address register should be incremented or decrement or not.
170 This parameter can be a value of @ref DMA_Source_incremented_mode */
171
172 uint32_t dst_increment; /**< Specifies whether the destination address register should be incremented or decrement or not.
173 This parameter can be a value of @ref DMA_Destination_incremented_mode */
174
175 uint32_t src_data_alignment; /**< Specifies the source data width.
176 This parameter can be a value of @ref DMA_Source_data_size */
177
178 uint32_t dst_data_alignment; /**< Specifies the destination data width.
179 This parameter can be a value of @ref DMA_Destination_data_size */
180
181 uint32_t priority; /**< Specifies the software priority for the DMA Channel.
182 This parameter can be a value of @ref DMA_Priority_level */
183 } dma_init_t;
184
185 /** @} */
186
187 /** @addtogroup DMA_handle DMA handle
188 * @{
189 */
190
191 /**
192 * @brief DMA handle Structure definition
193 */
194 typedef struct _dma_handle
195 {
196 dma_regs_t *p_instance; /**< DMA registers base address */
197
198 uint32_t channel; /**< DMA Channel Number */
199
200 dma_init_t init; /**< DMA communication parameters */
201
202 __IO hal_dma_state_t state; /**< DMA transfer state */
203
204 void *p_parent; /**< Parent object state */
205
206 void (* xfer_tfr_callback)(struct _dma_handle *p_dma); /**< DMA transfer complete callback */
207
208 void (* xfer_blk_callback)(struct _dma_handle *p_dma); /**< DMA block complete callback */
209
210 void (* xfer_error_callback)(struct _dma_handle *p_dma); /**< DMA transfer error callback */
211
212 void (* xfer_abort_callback)(struct _dma_handle *p_dma); /**< DMA transfer abort callback */
213
214 __IO uint32_t error_code; /**< DMA Error code */
215
216 uint32_t retention[5]; /**< DMA important register information. */
217 } dma_handle_t;
218
219 /** @} */
220
221 /**
222 * @defgroup HAL_DMA_MACRO Defines
223 * @{
224 */
225
226 /* Exported constants --------------------------------------------------------*/
227 /** @defgroup DMA_Exported_Constants DMA Exported Constants
228 * @{
229 */
230
231 /** @defgroup DMA_Error_Code DMA Error Code
232 * @{
233 */
234 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /**< No error */
235 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /**< Transfer error */
236 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /**< no ongoing transfer */
237 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /**< Timeout error */
238 #define HAL_DMA_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /**< Invalid parameters error */
239 /** @} */
240
241 /** @defgroup DMA_request DMA request definitions
242 * @{
243 */
244 /********************************* definition for DMA0 HS **************************************/
245 #define DMA0_REQUEST_CTE LL_DMA0_PERIPH_CTE /**< DMA CTE transmit request */
246 #define DMA0_REQUEST_PWM0 LL_DMA0_PERIPH_PWM0 /**< DMA PWM0 transmit request */
247 #define DMA0_REQUEST_SPIM_TX LL_DMA0_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
248 #define DMA0_REQUEST_SPIM_RX LL_DMA0_PERIPH_SPIM_RX /**< DMA SPIM RX transmit request */
249 #define DMA0_REQUEST_SPIS_TX LL_DMA0_PERIPH_SPIS_TX /**< DMA SPIS TX transmit request */
250 #define DMA0_REQUEST_SPIS_RX LL_DMA0_PERIPH_SPIS_RX /**< DMA SPIS RX transmit request */
251 #define DMA0_REQUEST_UART0_TX LL_DMA0_PERIPH_UART0_TX /**< DMA UART0 TX transmit request */
252 #define DMA0_REQUEST_UART0_RX LL_DMA0_PERIPH_UART0_RX /**< DMA UART0 RX transmit request */
253 #define DMA0_REQUEST_UART1_TX LL_DMA0_PERIPH_UART1_TX /**< DMA UART1 TX transmit request */
254 #define DMA0_REQUEST_UART1_RX LL_DMA0_PERIPH_UART1_RX /**< DMA UART1 RX transmit request */
255 #define DMA0_REQUEST_SNSADC LL_DMA0_PERIPH_SNSADC /**< DMA SNSADC transmit request */
256 #define DMA0_REQUEST_I2C0_TX LL_DMA0_PERIPH_I2C0_TX /**< DMA peripheral type is I2C0 TX */
257 #define DMA0_REQUEST_I2C0_RX LL_DMA0_PERIPH_I2C0_RX /**< DMA peripheral type is I2C0 RX */
258 #define DMA0_REQUEST_I2C1_TX LL_DMA0_PERIPH_I2C1_TX /**< DMA peripheral type is I2C1 TX */
259 #define DMA0_REQUEST_I2C1_RX LL_DMA0_PERIPH_I2C1_RX /**< DMA peripheral type is I2C1 RX */
260 #define DMA0_REQUEST_MEM LL_DMA0_PERIPH_MEM /**< DMA is Memory transmit request */
261
262 /** @} */
263
264 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
265 * @{
266 */
267 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /**< Memory to memory direction */
268 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /**< Memory to peripheral direction */
269 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /**< Peripheral to memory direction */
270 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH /**< Peripheral to Peripheral direction */
271 /** @} */
272
273 /** @defgroup DMA_Source_incremented_mode DMA Source Incremented Mode
274 * @{
275 */
276 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT /**< Source increment mode */
277 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT /**< Source decrement mode */
278 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE /**< Source no change mode */
279 /** @} */
280
281 /** @defgroup DMA_Destination_incremented_mode DMA Destination Incremented Mode
282 * @{
283 */
284 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT /**< Destination increment mode */
285 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT /**< Destination decrement mode */
286 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE /**< Destination no change mode */
287 /** @} */
288
289 /** @defgroup DMA_Source_data_size DMA Source Data Size Alignment
290 * @{
291 */
292 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE /**< Source data alignment : Byte */
293 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD /**< Source data alignment : HalfWord */
294 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD /**< Source data alignment : Word */
295 /** @} */
296
297 /** @defgroup DMA_Destination_data_size DMA Destination Data Size Alignment
298 * @{
299 */
300 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE /**< Destination data alignment : Byte */
301 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD /**< Destination data alignment : HalfWord */
302 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD /**< Destination data alignment : Word */
303 /** @} */
304
305 /** @} */
306
307 /** @defgroup DMA_Priority_level DMA Priority Level
308 * @{
309 */
310 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0 /**< Priority level : Low */
311 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_1 /**< Priority level : Medium */
312 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_2 /**< Priority level : High */
313 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_3 /**< Priority level : Very High */
314 /** @} */
315
316 /** @defgroup DMA_CHANNEL_LOCK_EN DMA Channel Lock Enable
317 * @{
318 */
319 #define DMA_HAL_CHANNEL_LOCK_ENABLE LL_DMA_LOCK_CH_ENABLE /**< DMA Channel Lock Enable */
320 #define DMA_HAL_CHANNEL_LOCK_DISABLE LL_DMA_LOCK_CH_DISABLE /**< DMA Channel Lock Disable */
321 /** @} */
322
323 /** @defgroup DMA_CHANNEL_LOCK_LEVEL DMA Channel Lock Level
324 * @{
325 */
326 #define DMA_HAL_CHANNEL_LOCK_TFR LL_DMA_LOCK_CH_LEVEL_TFR /**< DMA Channel Lock Over complete DMA transfer */
327 #define DMA_HAL_CHANNEL_LOCK_BLK LL_DMA_LOCK_CH_LEVEL_BLK /**< DMA Channel Lock Over complete DMA block transfer */
328 #define DMA_HAL_CHANNEL_LOCK_TRANS LL_DMA_LOCK_CH_LEVEL_TRANS /**< DMA Channel Lock Over complete DMA transaction */
329 /** @} */
330
331 /** @defgroup DMA_BUS_LOCK_EN DMA Channel Lock Enable
332 * @{
333 */
334 #define DMA_HAL_BUS_LOCK_ENABLE LL_DMA_LOCK_BUS_ENABLE /**< DMA Bus Lock Enable */
335 #define DMA_HAL_BUS_LOCK_DISABLE LL_DMA_LOCK_BUS_DISABLE /**< DMA Bus Lock Disable */
336 /** @} */
337
338 /** @defgroup DMA_BUS_LOCK_LEVEL DMA Bus Lock Level
339 * @{
340 */
341 #define DMA_HAL_BUS_LOCK_TFR LL_DMA_LOCK_BUS_LEVEL_TFR /**< DMA Bus Lock Over complete DMA transfer */
342 #define DMA_HAL_BUS_LOCK_BLK LL_DMA_LOCK_BUS_LEVEL_BLK /**< DMA Bus Lock Over complete DMA block transfer */
343 #define DMA_HAL_BUS_LOCK_TRANS LL_DMA_LOCK_BUS_LEVEL_TRANS /**< DMA Bus Lock Over complete DMA transaction */
344 /** @} */
345
346
347 /* Private macros ------------------------------------------------------------*/
348 /** @defgroup DMA_Private_Macro DMA Private Macros
349 * @{
350 */
351
352 /** @brief Check if DMA instance is valid.
353 * @param __p_instance__ DMA instance.
354 * @retval SET (__p_instance__ is valid) or RESET (__p_instance__ is invalid)
355 */
356 #define IS_DMA_ALL_P_INSTANCE(__p_instance__) (((__p_instance__) == DMA0))
357
358 /** @brief Check if DMA channel instance is valid.
359 * @param __instance__ DMA channel instance.
360 * @retval SET (__instance__ is valid) or RESET (__instance__ is invalid)
361 */
362
363 #define IS_DMA_ALL_INSTANCE(__instance__) (((__instance__) == DMA_Channel0) || \
364 ((__instance__) == DMA_Channel1) || \
365 ((__instance__) == DMA_Channel2) || \
366 ((__instance__) == DMA_Channel3) || \
367 ((__instance__) == DMA_Channel4))
368
369
370
371 /** @brief Check if DMA request is valid.
372 * @param __REQUEST__ DMA request.
373 * @retval SET (__REQUEST__ is valid) or RESET (__REQUEST__ is invalid)
374 */
375
376 #define IS_DMA_ALL_REQUEST(__REQUEST__) (((__REQUEST__) == DMA0_REQUEST_SPIM_TX) || \
377 ((__REQUEST__) == DMA0_REQUEST_SPIM_RX) || \
378 ((__REQUEST__) == DMA0_REQUEST_SPIS_TX) || \
379 ((__REQUEST__) == DMA0_REQUEST_SPIS_RX) || \
380 ((__REQUEST__) == DMA0_REQUEST_UART0_TX) || \
381 ((__REQUEST__) == DMA0_REQUEST_UART0_RX) || \
382 ((__REQUEST__) == DMA0_REQUEST_UART1_TX) || \
383 ((__REQUEST__) == DMA0_REQUEST_UART1_RX) || \
384 ((__REQUEST__) == DMA0_REQUEST_SNSADC) || \
385 ((__REQUEST__) == DMA0_REQUEST_MEM) || \
386 ((__REQUEST__) == DMA0_REQUEST_I2C0_TX) || \
387 ((__REQUEST__) == DMA0_REQUEST_I2C0_RX) || \
388 ((__REQUEST__) == DMA0_REQUEST_I2C1_TX) || \
389 ((__REQUEST__) == DMA0_REQUEST_I2C1_RX))
390
391 /** @brief Check if DMA direction is valid.
392 * @param __DIRECTION__ DMA direction.
393 * @retval SET (__DIRECTION__ is valid) or RESET (__DIRECTION__ is invalid)
394 */
395 #define IS_DMA_DIRECTION(__DIRECTION__) (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
396 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
397 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
398 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH))
399
400 /** @brief Check if DMA buffer size is valid.
401 * @param __SIZE__ DMA buffer size.
402 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
403 */
404 #define IS_DMA_BUFFER_SIZE(__SIZE__) (((__SIZE__) >= 0x1) && ((__SIZE__) <= 0xFFF))
405
406 /** @brief Check if DMA source address increment state is valid.
407 * @param __STATE__ DMA source address increment state.
408 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
409 */
410 #define IS_DMA_SOURCE_INC_STATE(__STATE__) (((__STATE__) == DMA_SRC_INCREMENT) || \
411 ((__STATE__) == DMA_SRC_DECREMENT) || \
412 ((__STATE__) == DMA_SRC_NO_CHANGE))
413
414 /** @brief Check if DMA destination address increment state is valid.
415 * @param __STATE__ DMA destination address increment state.
416 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
417 */
418 #define IS_DMA_DESTINATION_INC_STATE(__STATE__) (((__STATE__) == DMA_DST_INCREMENT) || \
419 ((__STATE__) == DMA_DST_DECREMENT) || \
420 ((__STATE__) == DMA_DST_NO_CHANGE))
421
422 /** @brief Check if DMA source data size is valid.
423 * @param __SIZE__ DMA source data size.
424 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
425 */
426 #define IS_DMA_SOURCE_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
427 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
428 ((__SIZE__) == DMA_SDATAALIGN_WORD))
429
430 /** @brief Check if DMA destination data size is valid.
431 * @param __SIZE__ DMA destination data size.
432 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
433 */
434 #define IS_DMA_DESTINATION_DATA_SIZE(__SIZE__) (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
435 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
436 ((__SIZE__) == DMA_DDATAALIGN_WORD ))
437
438 /** @brief Check if DMA priority is valid.
439 * @param __PRIORITY__ DMA priority.
440 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid)
441 */
442 #define IS_DMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == DMA_PRIORITY_LOW ) || \
443 ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
444 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || \
445 ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH))
446
447 /** @} */
448
449 /** @} */
450
451
452 /* Exported functions --------------------------------------------------------*/
453 /** @addtogroup HAL_DMA_DRIVER_FUNCTIONS Functions
454 * @{
455 */
456
457 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
458 * @brief Initialization and de-initialization functions
459 *
460 @verbatim
461 ===============================================================================
462 ##### Initialization and de-initialization functions #####
463 ===============================================================================
464 [..]
465 This section provides functions allowing to initialize the DMA Channel source
466 and destination addresses, incrementation and data sizes, transfer direction,
467 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
468 [..]
469 The hal_dma_init() function follows the DMA configuration procedures as described in
470 reference manual.
471
472 @endverbatim
473 * @{
474 */
475
476 /**
477 ****************************************************************************************
478 * @brief Initialize the DMA according to the specified
479 * parameters in the dma_init_t and initialize the associated handle.
480 *
481 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
482 *
483 * @retval ::HAL_OK: Operation is OK.
484 * @retval ::HAL_ERROR: Parameter error or operation not supported.
485 * @retval ::HAL_BUSY: Driver is busy.
486 * @retval ::HAL_TIMEOUT: Timeout occurred.
487 ****************************************************************************************
488 */
489 hal_status_t hal_dma_init(dma_handle_t *p_dma);
490
491 /**
492 ****************************************************************************************
493 * @brief De-initialize the DMA peripheral.
494 *
495 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
496 *
497 * @retval ::HAL_OK: Operation is OK.
498 * @retval ::HAL_ERROR: Parameter error or operation not supported.
499 * @retval ::HAL_BUSY: Driver is busy.
500 * @retval ::HAL_TIMEOUT: Timeout occurred.
501 ****************************************************************************************
502 */
503 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
504
505 /** @} */
506
507
508 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
509 * @brief Input and Output operation functions
510 *
511 @verbatim
512 ===============================================================================
513 ##### IO operation functions #####
514 ===============================================================================
515 [..] This section provides functions allowing to:
516 (+) Configure the source, destination address and data length and Start DMA transfer
517 (+) Configure the source, destination address and data length and
518 Start DMA transfer with interrupt
519 (+) Abort DMA transfer
520 (+) Poll for transfer complete
521 (+) Handle DMA interrupt request
522
523 @endverbatim
524 * @{
525 */
526
527 /**
528 ****************************************************************************************
529 * @brief Start the DMA Transfer.
530 *
531 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
532 * @param[in] src_address: The source memory Buffer address
533 * @param[in] dst_address: The destination memory Buffer address
534 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
535 *
536 * @retval ::HAL_OK: Operation is OK.
537 * @retval ::HAL_ERROR: Parameter error or operation not supported.
538 * @retval ::HAL_BUSY: Driver is busy.
539 * @retval ::HAL_TIMEOUT: Timeout occurred.
540 ****************************************************************************************
541 */
542 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
543
544 /**
545 ****************************************************************************************
546 * @brief Start the DMA Transfer whit channel lock and bus lock.
547 *
548 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
549 * @param[in] src_address: The source memory Buffer address
550 * @param[in] dst_address: The destination memory Buffer address
551 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
552 * @param[in] lock_config: The Config of DMA channel and bus lock.
553 *
554 * @retval ::HAL_OK: Operation is OK.
555 * @retval ::HAL_ERROR: Parameter error or operation not supported.
556 * @retval ::HAL_BUSY: Driver is busy.
557 * @retval ::HAL_TIMEOUT: Timeout occurred.
558 ****************************************************************************************
559 */
560 hal_status_t hal_dma_start_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config);
561
562 /**
563 ****************************************************************************************
564 * @brief Start the DMA Transfer with interrupt enabled & Channel Diabled.
565 *
566 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
567 * @param[in] src_address: The source memory Buffer address
568 * @param[in] dst_address: The destination memory Buffer address
569 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
570 *
571 * @retval ::HAL_OK: Operation is OK.
572 * @retval ::HAL_ERROR: Parameter error or operation not supported.
573 * @retval ::HAL_BUSY: Driver is busy.
574 * @retval ::HAL_TIMEOUT: Timeout occurred.
575 ****************************************************************************************
576 */
577 hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
578
579 /**
580 ****************************************************************************************
581 * @brief Start the DMA Transfer with interrupt enabled & Channel Enabled.
582 *
583 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
584 * @param[in] src_address: The source memory Buffer address
585 * @param[in] dst_address: The destination memory Buffer address
586 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
587 *
588 * @retval ::HAL_OK: Operation is OK.
589 * @retval ::HAL_ERROR: Parameter error or operation not supported.
590 * @retval ::HAL_BUSY: Driver is busy.
591 * @retval ::HAL_TIMEOUT: Timeout occurred.
592 ****************************************************************************************
593 */
594 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
595
596 /**
597 ****************************************************************************************
598 * @brief Start the DMA Transfer with interrupt enabled、channel lock and bus lock.
599 *
600 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
601 * @param[in] src_address: The source memory Buffer address
602 * @param[in] dst_address: The destination memory Buffer address
603 * @param[in] data_length: The length of data to be transferred from source to destination, ranging between 0 and 4095.
604 * @param[in] lock_config: The Config of DMA channel and bus lock.
605 *
606 * @retval ::HAL_OK: Operation is OK.
607 * @retval ::HAL_ERROR: Parameter error or operation not supported.
608 * @retval ::HAL_BUSY: Driver is busy.
609 * @retval ::HAL_TIMEOUT: Timeout occurred.
610 ****************************************************************************************
611 */
612 hal_status_t hal_dma_start_it_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config);
613
614 /**
615 ****************************************************************************************
616 * @brief Abort the DMA Transfer.
617 *
618 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
619 *
620 * @retval ::HAL_OK: Operation is OK.
621 * @retval ::HAL_ERROR: Parameter error or operation not supported.
622 * @retval ::HAL_BUSY: Driver is busy.
623 * @retval ::HAL_TIMEOUT: Timeout occurred.
624 ****************************************************************************************
625 */
626 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
627
628 /**
629 ****************************************************************************************
630 * @brief Aborts the DMA Transfer in Interrupt mode.
631 *
632 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
633 *
634 * @retval ::HAL_OK: Operation is OK.
635 * @retval ::HAL_ERROR: Parameter error or operation not supported.
636 * @retval ::HAL_BUSY: Driver is busy.
637 * @retval ::HAL_TIMEOUT: Timeout occurred.
638 ****************************************************************************************
639 */
640 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
641
642 /**
643 ****************************************************************************************
644 * @brief Polling for transfer complete.
645 *
646 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
647 * @param[in] timeout: Timeout duration.
648 *
649 * @retval ::HAL_OK: Operation is OK.
650 * @retval ::HAL_ERROR: Parameter error or operation not supported.
651 * @retval ::HAL_BUSY: Driver is busy.
652 * @retval ::HAL_TIMEOUT: Timeout occurred.
653 ****************************************************************************************
654 */
655 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
656
657 /** @} */
658
659 /** @addtogroup DMA_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
660 * @brief IRQ Handler and Callbacks functions
661 * @{
662 */
663
664 /**
665 ****************************************************************************************
666 * @brief Handle DMA interrupt request.
667 *
668 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
669 ****************************************************************************************
670 */
671 void hal_dma_irq_handler(dma_handle_t *p_dma);
672
673 /**
674 ****************************************************************************************
675 * @brief Register callbacks
676 *
677 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
678 * @param[in] id: User Callback identifer. This parameter can be one of the following values:
679 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
680 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
681 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
682 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
683 * @param[in] callback: Pointer to private callbacsk function which has pointer to a dma_handle_t structure as parameter.
684 *
685 * @retval ::HAL_OK: Operation is OK.
686 * @retval ::HAL_ERROR: Parameter error or operation not supported.
687 * @retval ::HAL_BUSY: Driver is busy.
688 * @retval ::HAL_TIMEOUT: Timeout occurred.
689 ****************************************************************************************
690 */
691 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void (* callback)( dma_handle_t * p_dma));
692
693 /**
694 ****************************************************************************************
695 * @brief UnRegister callbacks
696 *
697 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
698 * @param[in] id: User Callback identifer. This parameter can be a combiantion of the following values:
699 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
700 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
701 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
702 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
703 * @arg @ref HAL_DMA_XFER_ALL_CB_ID
704 *
705 * @retval ::HAL_OK: Operation is OK.
706 * @retval ::HAL_ERROR: Parameter error or operation not supported.
707 * @retval ::HAL_BUSY: Driver is busy.
708 * @retval ::HAL_TIMEOUT: Timeout occurred.
709 ****************************************************************************************
710 */
711 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
712
713 /** @} */
714
715 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
716 * @brief Peripheral State and Errors functions
717 *
718 @verbatim
719 ===============================================================================
720 ##### Peripheral State and Errors functions #####
721 ===============================================================================
722 [..]
723 This subsection provides functions allowing to
724 (+) Check the DMA state
725 (+) Get error code
726
727 @endverbatim
728 * @{
729 */
730
731 /**
732 ****************************************************************************************
733 * @brief Return the DMA hande state.
734 *
735 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
736 *
737 * @retval ::HAL_DMA_STATE_RESET: DMA not yet initialized or disabled.
738 * @retval ::HAL_DMA_STATE_READY: DMA process succeeded and ready for use.
739 * @retval ::HAL_DMA_STATE_BUSY: DMA process is ongoing.
740 * @retval ::HAL_DMA_STATE_TIMEOUT: DMA timeout state.
741 * @retval ::HAL_DMA_STATE_ERROR: DMA error state.
742 ****************************************************************************************
743 */
744 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
745
746 /**
747 ****************************************************************************************
748 * @brief Return the DMA error code.
749 *
750 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration information for the specified DMA Channel.
751 *
752 * @return DMA Error Code
753 ****************************************************************************************
754 */
755 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
756
757 /**
758 ****************************************************************************************
759 * @brief Suspend some registers related to DMA configuration before sleep.
760 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
761 * information for the specified DMA module.
762 * @retval ::HAL_OK: Operation is OK.
763 * @retval ::HAL_ERROR: Parameter error or operation not supported.
764 * @retval ::HAL_BUSY: Driver is busy.
765 * @retval ::HAL_TIMEOUT: Timeout occurred.
766 ****************************************************************************************
767 */
768 void hal_dma_suspend_reg(dma_handle_t *p_dma);
769
770 /**
771 ****************************************************************************************
772 * @brief Restore some registers related to DMA configuration after sleep.
773 * This function must be used in conjunction with the hal_dma_resume_reg().
774 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
775 * information for the specified DMA module.
776 * @retval ::HAL_OK: Operation is OK.
777 * @retval ::HAL_ERROR: Parameter error or operation not supported.
778 * @retval ::HAL_BUSY: Driver is busy.
779 * @retval ::HAL_TIMEOUT: Timeout occurred.
780 ****************************************************************************************
781 */
782 void hal_dma_resume_reg(dma_handle_t *p_dma);
783
784 #ifdef HAL_PM_ENABLE
785 /**
786 ****************************************************************************************
787 * @brief Suspend the register of the specified DMA channel.
788 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
789 * information for the specified DMA module.
790 * @retval ::HAL_PM_ACTIVE: Device is active, not allow sleep.
791 * @retval ::HAL_PM_SLEEP: Allow sleep.
792 ****************************************************************************************
793 */
794 hal_pm_status_t hal_pm_dma_suspend(dma_handle_t *p_dma);
795
796 /**
797 ****************************************************************************************
798 * @brief Resume the register of the specified DMA channel.
799 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
800 * information for the specified DMA module.
801 * @retval ::None
802 ****************************************************************************************
803 */
804 void hal_pm_dma_resume(dma_handle_t *p_dma);
805 #endif /* HAL_PM_ENABLE */
806
807 /**
808 ****************************************************************************************
809 * @brief Suspend the register of the specified DMA channel.
810 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
811 * information for the specified DMA module.
812 * @param[in] channel: dma channel,can be one of the values of dma_channel_t.
813 * @retval ::None
814 ****************************************************************************************
815 */
816 void hal_dma_suspend_channel(dma_handle_t *p_dma, uint32_t channel);
817
818 /**
819 ****************************************************************************************
820 * @brief Resume the register of the specified DMA channel.
821 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
822 * information for the specified DMA module.
823 * @param[in] channel: dma channel,can be one of the values of dma_channel_t.
824 * @retval ::None
825 ****************************************************************************************
826 */
827 void hal_dma_resume_channel(dma_handle_t *p_dma, uint32_t channel);
828
829 /** @} */
830
831 /** @} */
832
833 #ifdef __cplusplus
834 }
835 #endif
836
837 #endif /* HAL_DMA_H */
838
839 /** @} */
840
841 /** @} */
842
843 /** @} */
DMA_Channel4
@ DMA_Channel4
Definition: hal_dma.h:100
HAL_DMA_XFER_TFR_CB_ID
@ HAL_DMA_XFER_TFR_CB_ID
Definition: hal_dma.h:114
_dma_handle::p_instance
dma_regs_t * p_instance
Definition: hal_dma.h:196
hal_dma_get_error
uint32_t hal_dma_get_error(dma_handle_t *p_dma)
Return the DMA error code.
DMA_Channel1
@ DMA_Channel1
Definition: hal_dma.h:97
hal_pm_dma_resume
void hal_pm_dma_resume(dma_handle_t *p_dma)
Resume the register of the specified DMA channel.
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition: hal_dma.h:82
_dma_init
DMA Configuration Structure definition.
Definition: hal_dma.h:158
dma_init_t
struct _dma_init dma_init_t
DMA Configuration Structure definition.
_dma_handle::error_code
__IO uint32_t error_code
Definition: hal_dma.h:214
DMA_Channel0
@ DMA_Channel0
Definition: hal_dma.h:96
hal_pwr_mgmt.h
This file contains all the functions prototypes for the HAL module driver.
dma_handle_t
struct _dma_handle dma_handle_t
DMA handle Structure definition.
hal_dma_state_t
hal_dma_state_t
HAL DMA State Enumerations definition.
Definition: hal_dma.h:78
hal_dma_start_it
hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Enabled.
hal_dma_abort_it
hal_status_t hal_dma_abort_it(dma_handle_t *p_dma)
Aborts the DMA Transfer in Interrupt mode.
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: hal_dma.h:80
_dma_init::dst_increment
uint32_t dst_increment
Definition: hal_dma.h:172
_dma_handle::init
dma_init_t init
Definition: hal_dma.h:200
hal_pm_status_t
hal_pm_status_t
Definition: hal_pwr_mgmt.h:59
hal_dma_start_lock
hal_status_t hal_dma_start_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer whit channel lock and bus lock.
_dma_lock_config::channel_lock_en
uint32_t channel_lock_en
Definition: hal_dma.h:134
DMA_Channel2
@ DMA_Channel2
Definition: hal_dma.h:98
hal_dma_irq_handler
void hal_dma_irq_handler(dma_handle_t *p_dma)
Handle DMA interrupt request.
_dma_handle::xfer_blk_callback
void(* xfer_blk_callback)(struct _dma_handle *p_dma)
Definition: hal_dma.h:208
hal_dma_suspend_channel
void hal_dma_suspend_channel(dma_handle_t *p_dma, uint32_t channel)
Suspend the register of the specified DMA channel.
hal_pm_dma_suspend
hal_pm_status_t hal_pm_dma_suspend(dma_handle_t *p_dma)
Suspend the register of the specified DMA channel.
_dma_handle::retention
uint32_t retention[5]
Definition: hal_dma.h:216
ll_dma.h
Header file containing functions prototypes of DMA LL library.
_dma_init::priority
uint32_t priority
Definition: hal_dma.h:181
hal_dma_suspend_reg
void hal_dma_suspend_reg(dma_handle_t *p_dma)
Suspend some registers related to DMA configuration before sleep.
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: hal_dma.h:117
hal_dma_register_callback
hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id, void(*callback)(dma_handle_t *p_dma))
Register callbacks.
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: hal_dma.h:118
_dma_init::dst_request
uint32_t dst_request
Definition: hal_dma.h:162
hal_dma_poll_for_transfer
hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout)
Polling for transfer complete.
hal_dma_start
hal_status_t hal_dma_start(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer.
_dma_handle::state
__IO hal_dma_state_t state
Definition: hal_dma.h:202
_dma_lock_config::bus_lock_en
uint32_t bus_lock_en
Definition: hal_dma.h:140
hal_dma_init
hal_status_t hal_dma_init(dma_handle_t *p_dma)
Initialize the DMA according to the specified parameters in the dma_init_t and initialize the associa...
_dma_handle::xfer_error_callback
void(* xfer_error_callback)(struct _dma_handle *p_dma)
Definition: hal_dma.h:210
HAL_DMA_XFER_BLK_CB_ID
@ HAL_DMA_XFER_BLK_CB_ID
Definition: hal_dma.h:115
hal_dma_start_it_dc
hal_status_t hal_dma_start_it_dc(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length)
Start the DMA Transfer with interrupt enabled & Channel Diabled.
hal_dma_callback_id_t
hal_dma_callback_id_t
HAL DMA Callback ID Enumerations definition.
Definition: hal_dma.h:113
DMA_Channel3
@ DMA_Channel3
Definition: hal_dma.h:99
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: hal_dma.h:83
hal_status_t
hal_status_t
HAL Status structures definition.
Definition: gr_common.h:140
_dma_handle::xfer_tfr_callback
void(* xfer_tfr_callback)(struct _dma_handle *p_dma)
Definition: hal_dma.h:206
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: hal_dma.h:81
hal_def.h
This file contains HAL common definitions, enumeration, macros and structures definitions.
_dma_handle::xfer_abort_callback
void(* xfer_abort_callback)(struct _dma_handle *p_dma)
Definition: hal_dma.h:212
_dma_init::direction
uint32_t direction
Definition: hal_dma.h:165
_dma_lock_config::channel_lock_level
uint32_t channel_lock_level
Definition: hal_dma.h:137
hal_dma_get_state
hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma)
Return the DMA hande state.
DMA_Channel_NUM_MAX
@ DMA_Channel_NUM_MAX
Definition: hal_dma.h:101
hal_dma_unregister_callback
hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id)
UnRegister callbacks.
_dma_init::dst_data_alignment
uint32_t dst_data_alignment
Definition: hal_dma.h:178
dma_lock_config
struct _dma_lock_config dma_lock_config
DMA LOCK Structure definition.
hal_dma_resume_channel
void hal_dma_resume_channel(dma_handle_t *p_dma, uint32_t channel)
Resume the register of the specified DMA channel.
_dma_lock_config
DMA LOCK Structure definition.
Definition: hal_dma.h:133
_dma_handle::p_parent
void * p_parent
Definition: hal_dma.h:204
hal_dma_resume_reg
void hal_dma_resume_reg(dma_handle_t *p_dma)
Restore some registers related to DMA configuration after sleep. This function must be used in conjun...
hal_dma_abort
hal_status_t hal_dma_abort(dma_handle_t *p_dma)
Abort the DMA Transfer.
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: hal_dma.h:116
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: hal_dma.h:79
_dma_init::src_request
uint32_t src_request
Definition: hal_dma.h:159
_dma_lock_config::bus_lock_level
uint32_t bus_lock_level
Definition: hal_dma.h:143
_dma_handle::channel
uint32_t channel
Definition: hal_dma.h:198
_dma_init::src_data_alignment
uint32_t src_data_alignment
Definition: hal_dma.h:175
_dma_handle
DMA handle Structure definition.
Definition: hal_dma.h:195
hal_dma_deinit
hal_status_t hal_dma_deinit(dma_handle_t *p_dma)
De-initialize the DMA peripheral.
dma_channel_t
dma_channel_t
HAL DMA Channel Enumerations definition.
Definition: hal_dma.h:95
_dma_init::src_increment
uint32_t src_increment
Definition: hal_dma.h:169
hal_dma_start_it_lock
hal_status_t hal_dma_start_it_lock(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length, dma_lock_config *lock_config)
Start the DMA Transfer with interrupt enabled、channel lock and bus lock.