Macros
Specify the default system clock when the system is initialized
Peripheral Driver » LL Driver » CGC » Defines » CGC Exported Constants

## Macros
#define | LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0
#define | LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1
#define | LL_CGC_MCU_SUBSYS_DEFAULT_CLK
#define | LL_CGC_MCU_PERIPH_CG_DEFAULT
#define | LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT
#define | CGC_CLOCK_ENABLE (1)
#define | CGC_CLOCK_DISABLE (0)
#define | BIT_SEGMENT_VALUE BIT_ADDR

## Detailed Description

## Macro Definition Documentation

## ◆ BIT_SEGMENT_VALUE

#define BIT_SEGMENT_VALUE BIT_ADDR

Bit segment address value manipulation

Definition at line 234 of file ll_cgc.h.

## ◆ CGC_CLOCK_DISABLE

#define CGC_CLOCK_DISABLE (0)

Bit segment address disable

Definition at line 232 of file ll_cgc.h.

## ◆ CGC_CLOCK_ENABLE

#define CGC_CLOCK_ENABLE (1)

Bit segment address enable

Definition at line 231 of file ll_cgc.h.

## ◆ LL_CGC_MCU_PERIPH_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_CG_DEFAULT

Value:
(LL_CGC_FRC_UART0_PCLK |\
LL_CGC_FRC_UART1_PCLK |\
LL_CGC_FRC_I2C0_PCLK |\
LL_CGC_FRC_I2C1_PCLK |\
LL_CGC_FRC_SPI_M_PCLK |\
LL_CGC_FRC_SPI_S_PCLK |\
LL_CGC_FRC_PWM_0_PCLK |\
LL_CGC_FRC_PWM_1_PCLK)

pclk for the system default periph clock

Definition at line 218 of file ll_cgc.h.

## ◆ LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT

#define LL_CGC_MCU_PERIPH_SLP_CG_DEFAULT

Value:
(MCU_SUB_PERIPH_CLK_SLP_OFF_UART0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_UART1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIM |\
MCU_SUB_PERIPH_CLK_SLP_OFF_SPIS |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_PWM1 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C0 |\
MCU_SUB_PERIPH_CLK_SLP_OFF_I2C1)

pclk for the system default periph wfi clock

Definition at line 227 of file ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_CLK

#define LL_CGC_MCU_SUBSYS_DEFAULT_CLK

Value:
(LL_CGC_FRC_SECU_HCLK |\
LL_CGC_FRC_SNSADC_HCLK |\
LL_CGC_FRC_SERIAL_HCLK)

Hclk for the system default clock

Definition at line 207 of file ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK0

Value:
(LL_CGC_WFI_SECU_HCLK |\
LL_CGC_WFI_SNSADC_HCLK |\
LL_CGC_WFI_GPIO_HCLK |\
LL_CGC_WFI_BLE_BRG_HCLK |\
LL_CGC_WFI_SERIAL_HCLK)

Hclk0 for the system default clock WFI/WFE

Definition at line 199 of file ll_cgc.h.

## ◆ LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1

#define LL_CGC_MCU_SUBSYS_DEFAULT_WFI_CLK1

Value:
(LL_CGC_WFI_AON_MCUSUB_HCLK |\
LL_CGC_WFI_XF_XQSPI_HCLK)

Hclk1 for the system default clock WFI/WFE

Definition at line 202 of file ll_cgc.h.

LL_CGC_WFI_SECU_HCLK
#define LL_CGC_WFI_SECU_HCLK
Definition: ll_cgc.h:77
LL_CGC_WFI_AON_MCUSUB_HCLK
#define LL_CGC_WFI_AON_MCUSUB_HCLK
Definition: ll_cgc.h:92
LL_CGC_FRC_SECU_HCLK
#define LL_CGC_FRC_SECU_HCLK
Definition: ll_cgc.h:103
LL_CGC_FRC_UART0_PCLK
#define LL_CGC_FRC_UART0_PCLK
Definition: ll_cgc.h:126