ll_clk.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file ll_clk.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of CLOCK LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_CLK LL Clock
47 * @brief CLOCK CALIBRATION LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef _LL_CLK_H_
53 #define _LL_CLK_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5x.h"
61
62 /** @defgroup CLK_SOURCE Clock source
63 * @{
64 */
65 #define LL_CLK_SEL_SOURCE_CPLL_CLK (0UL) /**< Select CPLL clk as the source of the 192MHz clock */
66 #define LL_CLK_SEL_SOURCE_HF_OSC_CLK (1UL) /**< Select hf osc clk as the source of the 192MHz clock */
67 /** @} */
68
69 /** @defgroup SLOW_CLK_SOURCE Slow clock source
70 * @{
71 */
72
73 #define LL_SLOW_CLK_RNG AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RNG /**< Select RNG_OSC clk as the source of the slow clock */
74 #define LL_SLOW_CLK_RC AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RC /**< Select RC_32K clk as the source of the slow clock */
75 #define LL_SLOW_CLK_RTC AON_CTL_MCU_SLOW_CLK_CTRL_SEL_RTC /**< Select RTC_32K clk as the source of the slow clock */
76 /** @} */
77
78 /** @defgroup CLK_SELECT Clock select
79 * @{
80 */
81 #define LL_CLK_CPLL_S64M_CLK AON_CTL_MCU_CLK_CTRL_SEL_64M /**< Select PLL/HF_OSC 64MHz clk as system clock */
82 #define LL_CLK_XO_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_XO_16M /**< Select XO 16MHz clk as system clock */
83 #define LL_CLK_CPLL_S16M_CLK AON_CTL_MCU_CLK_CTRL_SEL_16M /**< Select PLL/HF_OSC 16MHz clk as system clock */
84 #define LL_CLK_CPLL_T32M_CLK AON_CTL_MCU_CLK_CTRL_SEL_32M /**< Select PLL/HF_OSC 32MHz clk as system clock */
85 /** @} */
86
87 /** @defgroup XO_PLL_STATE XO pll state
88 * @{
89 */
90 #define LL_CLK_XO_PLL_PLL_STAT (1UL) /**< Check CPLL STAT */
91 #define LL_CLK_XO_PLL_XO_STAT (2UL) /**< Check XO STAT */
92 #define LL_CLK_XO_PLL_HF_STAT (4UL) /**< Check HF STAT */
93 /** @} */
94
95 /** @defgroup AON_SLOW_CLK_SOURCE AON_SLOW clock source
96 * @{
97 */
98 #define LL_AON_SLOW_CLK_256K (0UL) /**< Select aon slow clk 256k */
99 #define LL_AON_SLOW_CLK_32K (1UL) /**< Select aon slow clk 32k */
100 /** @} */
101
102 /** @defgroup CLK_LL_DRIVER_FUNCTIONS Functions
103 * @{
104 */
105
106 /**
107 * @brief Get system clock.
108 *
109 * Register|BitsName
110 * --------|--------
111 * MCU_CLK_CTRL | CLK_CTRL_SEL
112 *
113 * @retval System clock
114 *
115 */
116 __STATIC_INLINE uint32_t ll_clk_get_sys_clk(void)
117 {
118 return READ_BITS(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL);
119 }
120
121 /**
122 * @brief Set system clock.
123 *
124 * Register|BitsName
125 * --------|--------
126 * MCU_CLK_CTRL | CLK_CTRL_SEL
127 *
128 * @param clk_sel This parameter can be a combination of the following values:
129 * @arg @ref LL_CLK_CPLL_S64M_CLK
130 * @arg @ref LL_CLK_XO_S16M_CLK
131 * @arg @ref LL_CLK_CPLL_S16M_CLK
132 * @arg @ref LL_CLK_CPLL_T32M_CLK
133 * @retval None
134 *
135 */
136 __STATIC_INLINE void ll_clk_set_sys_clk(uint32_t clk_sel)
137 {
138 MODIFY_REG(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SEL, clk_sel);
139 }
140
141 /**
142 * @brief Select clock source.
143 *
144 * Register|BitsName
145 * --------|--------
146 * AON_CLK | CAL_FST_CLK
147 *
148 * @param src_sel This parameter can be a combination of the following values:
149 * @arg @ref LL_CLK_SEL_SOURCE_CPLL_CLK
150 * @arg @ref LL_CLK_SEL_SOURCE_HF_OSC_CLK
151 * @retval None
152 *
153 */
154 __STATIC_INLINE void ll_clk_select_source(uint32_t src_sel)
155 {
156 MODIFY_REG(AON_CTL->AON_CLK, AON_CTL_AON_CLK_CAL_FST_CLK, src_sel);
157 }
158
159 /**
160 * @brief start XO and PLL
161 *
162 * Register|BitsName
163 * --------|--------
164 * AON_PWR | XO_PLL_SET
165 *
166 * @retval void.
167 *
168 */
169 __STATIC_INLINE void ll_clk_start_xo_pll(void)
170 {
171 MODIFY_REG(AON_PWR->XO_PLL_SET, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
172 }
173
174 /**
175 * @brief stop XO and PLL
176 *
177 * Register|BitsName
178 * --------|--------
179 * AON_PWR | XO_PLL_CLR
180 *
181 * @retval void.
182 *
183 */
184 __STATIC_INLINE void ll_clk_stop_xo_pll(void)
185 {
186 MODIFY_REG(AON_PWR->XO_PLL_CLR, AON_PWR_XO_PLL_SET_PLL_SET_Msk | AON_PWR_XO_PLL_SET_XO_SET_Msk, AON_PWR_XO_PLL_SET_PLL_SET | AON_PWR_XO_PLL_SET_XO_SET);
187 }
188
189 /**
190 * @brief Get XO PLL status.
191 *
192 * Register|BitsName
193 * --------|--------
194 * AON_PWR | XO_PLL_STAT
195 *
196 * @retval xo pll status value.
197 *
198 */
199 __STATIC_INLINE uint32_t ll_clk_get_hf_status(void)
200 {
201 return READ_BITS(AON_PWR->XO_PLL_STAT, AON_PWR_XO_PLL_STAT_PLL_STAT |
202 AON_PWR_XO_PLL_STAT_XO_STAT |
203 AON_PWR_XO_PLL_STAT_HF_STAT);
204 }
205
206 /**
207 * @brief Get system slow clock.
208 *
209 * Register|BitsName
210 * --------|--------
211 * MCU_CLK_CTRL | CLK_CTRL_SEL
212 *
213 * @retval System slow clock
214 *
215 */
216 __STATIC_INLINE uint32_t ll_clk_get_sys_slow_clk(void)
217 {
218 return READ_BITS(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_SLOW_CLK_CTRL_SEL);
219 }
220
221 /**
222 * @brief Set system clock.
223 *
224 * Register|BitsName
225 * --------|--------
226 * MCU_CLK_CTRL | CLK_CTRL_SEL
227 *
228 * @param clk_sel This parameter can be a combination of the following values:
229 * @arg @ref LL_SLOW_CLK_RNG
230 * @arg @ref LL_SLOW_CLK_RC
231 * @arg @ref LL_SLOW_CLK_RTC
232 * @retval None
233 *
234 */
235 __STATIC_INLINE void ll_clk_set_sys_slow_clk(uint32_t clk_sel)
236 {
237 MODIFY_REG(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_SLOW_CLK_CTRL_SEL, clk_sel);
238 }
239
240 /**
241 * @brief Set system clock.
242 *
243 * Register|BitsName
244 * --------|--------
245 * MCU_CLK_CTRL | AON_CLK_CTRL_SEL
246 *
247 * @param clk_sel This parameter can be a combination of the following values:
248 * @arg @ref LL_AON_SLOW_CLK_256K
249 * @arg @ref LL_AON_SLOW_CLK_32K
250 * @retval None
251 *
252 */
253 __STATIC_INLINE void ll_clk_set_aon_slow_clk(uint32_t clk_sel)
254 {
255 MODIFY_REG(AON_CTL->MCU_CLK_CTRL, AON_CTL_MCU_CLK_CTRL_SLOW_CLK_SEL, (clk_sel << AON_CTL_MCU_CLK_CTRL_SLOW_CLK_SEL_Pos));
256 }
257
258 /** @} */
259 #ifdef __cplusplus
260 }
261 #endif
262
263 #endif
264
265 /** @} */
266
267 /** @} */
268
269 /** @} */
ll_clk_set_aon_slow_clk
__STATIC_INLINE void ll_clk_set_aon_slow_clk(uint32_t clk_sel)
Set system clock.
Definition: ll_clk.h:253
AON_CTL
#define AON_CTL
Definition: gr5405.h:3
ll_clk_select_source
__STATIC_INLINE void ll_clk_select_source(uint32_t src_sel)
Select clock source.
Definition: ll_clk.h:154
ll_clk_set_sys_slow_clk
__STATIC_INLINE void ll_clk_set_sys_slow_clk(uint32_t clk_sel)
Set system clock.
Definition: ll_clk.h:235
ll_clk_set_sys_clk
__STATIC_INLINE void ll_clk_set_sys_clk(uint32_t clk_sel)
Set system clock.
Definition: ll_clk.h:136
ll_clk_start_xo_pll
__STATIC_INLINE void ll_clk_start_xo_pll(void)
start XO and PLL
Definition: ll_clk.h:169
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_clk_stop_xo_pll
__STATIC_INLINE void ll_clk_stop_xo_pll(void)
stop XO and PLL
Definition: ll_clk.h:184
ll_clk_get_sys_slow_clk
__STATIC_INLINE uint32_t ll_clk_get_sys_slow_clk(void)
Get system slow clock.
Definition: ll_clk.h:216
ll_clk_get_hf_status
__STATIC_INLINE uint32_t ll_clk_get_hf_status(void)
Get XO PLL status.
Definition: ll_clk.h:199
ll_clk_get_sys_clk
__STATIC_INLINE uint32_t ll_clk_get_sys_clk(void)
Get system clock.
Definition: ll_clk.h:116