ll_aon_pmu.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_aon_pmu.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PMU LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PMU PMU LL Module Driver
47 * @brief PMU LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef _LL_PMU_H_
53 #define _LL_PMU_H_
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5x.h"
61
62 /** @defgroup AON_PMU_LL_DRIVER_FUNCTIONS Functions
63 * @{
64 */
65 /**
66 * @brief Enable the RTC
67 *
68 * Register|BitsName
69 * --------|--------
70 * RF_REG_0 | RTC_EN
71 *
72 * @retval None
73 *
74 */
75 __STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
76 {
77 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
78 }
79
80 /**
81 * @brief Disable the RTC
82 *
83 * Register|BitsName
84 * --------|--------
85 * RF_REG_0 | RTC_EN
86 *
87 */
88 __STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
89 {
90 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_EN);
91 }
92
93 /**
94 * @brief Set RTC GM
95 *
96 * Register|BitsName
97 * --------|--------
98 * RF_REG_0 | EN
99 *
100 * @param value: The rtc gm value.
101 *
102 */
103 __STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
104 {
105 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RTC_GM, (value << AON_PMU_RF_REG_0_RTC_GM_Pos));
106 }
107
108 /**
109 * @brief Set lv,default is set to 1.8V,LSB = 8.5mv
110 *
111 * Register|BitsName
112 * --------|--------
113 * RF_REG_0 | EN
114 *
115 * @param value: The io ldo vout value.
116 *
117 */
118 __STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
119 {
120 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_REG1, (value << AON_PMU_RF_REG_0_IO_LDO_REG1_Pos));
121 }
122
123 /**
124 * @brief Set retention level
125 *
126 * Register|BitsName
127 * --------|--------
128 * RF_REG_0 | ctrl_ret
129 *
130 * @param value: The retention level value.
131 *
132 */
133 __STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
134 {
135 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_RET_LDO, (value << AON_PMU_RF_REG_0_RET_LDO_Pos));
136 }
137
138 /**
139 * @brief Set aon ldo value
140 *
141 * Register|BitsName
142 * --------|--------
143 * RF_REG_0 | TON
144 *
145 * @param value: The dcdc ton value.
146 *
147 */
148 __STATIC_INLINE void ll_aon_pmu_set_aon_ldo(uint32_t value)
149 {
150 MODIFY_REG(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_AON_LDO, (value << AON_PMU_RF_REG_0_AON_LDO_Pos));
151 }
152
153 /**
154 * @brief Get aon ldo value
155 *
156 * Register|BitsName
157 * --------|--------
158 * RF_REG_0 | TON
159 *
160 * @retval The dcdc ton value.
161 *
162 */
163 __STATIC_INLINE uint32_t ll_aon_pmu_get_aon_ldo(void)
164 {
165 return (READ_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_AON_LDO) >> AON_PMU_RF_REG_0_AON_LDO_Pos);
166 }
167
168 /**
169 * @brief Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
170 *
171 * Register|BitsName
172 * --------|--------
173 * RF_REG_1 | DCDC_VREG
174 *
175 * @param value: the dcdc vreg value.
176 *
177 */
178 __STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
179 {
180 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VREG, (value << AON_PMU_RF_REG_1_DCDC_VREG_Pos));
181 }
182
183 /**
184 * @brief Get dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
185 *
186 * Register|BitsName
187 * --------|--------
188 * RF_REG_1 | DCDC_VREG
189 *
190 * @retval: the dcdc vreg value.
191 *
192 */
193 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
194 {
195 return (READ_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VREG) >> AON_PMU_RF_REG_1_DCDC_VREG_Pos);
196 }
197
198 /**
199 * @brief Set dcdc voltage step for 18mV.
200 *
201 * Register|BitsName
202 * --------|--------
203 * RF_REG_1 | DCDC_VREG
204 *
205 *
206 */
207 __STATIC_INLINE void ll_aon_pmu_set_dcdc_step_18mV(void)
208 {
209 CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VOLT_STEP);
210 }
211
212 /**
213 * @brief Set dcdc voltage step for 25mV.
214 *
215 * Register|BitsName
216 * --------|--------
217 * RF_REG_1 | DCDC_VREG
218 *
219 *
220 */
221 __STATIC_INLINE void ll_aon_pmu_set_dcdc_step_25mV(void)
222 {
223 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_VOLT_STEP);
224 }
225
226 /**
227 * @brief Set sysldo rg_sysldo_ctrl_vref, vreg defaulted to 1.1V.
228 *
229 * Register|BitsName
230 * --------|--------
231 * FS_REG_1 | RG_SYSLDO_CTRL_VREF
232 *
233 * @param value: the sysldo vreg value.
234 *
235 */
236 __STATIC_INLINE void ll_aon_pmu_set_sysldo_vreg(uint32_t value)
237 {
238 MODIFY_REG(AON_PMU->FS_REG_1, AON_PMU_FS_REG_1_SYSLDO_CODE, (value << AON_PMU_FS_REG_1_SYSLDO_CODE_Pos));
239 }
240
241 /**
242 * @brief Get sysldo rg_sysldo_ctrl_vref, vreg defaulted to 1.1V.
243 *
244 * Register|BitsName
245 * --------|--------
246 * FS_REG_1 | RG_SYSLDO_CTRL_VREF
247 *
248 * @retval: the sysldo vreg value.
249 *
250 */
251 __STATIC_INLINE uint32_t ll_aon_pmu_get_sysldo_vreg(void)
252 {
253 return (READ_BITS(AON_PMU->FS_REG_1, AON_PMU_FS_REG_1_SYSLDO_CODE) >> AON_PMU_FS_REG_1_SYSLDO_CODE_Pos);
254 }
255
256 /**
257 * @brief Enable the io ldo bypass
258 *
259 * Register|BitsName
260 * --------|--------
261 * RF_REG_3 | BYPASS_EN
262 *
263 */
264 __STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
265 {
266 SET_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
267 }
268
269 /**
270 * @brief Disable the io ldo bypass
271 *
272 * Register|BitsName
273 * --------|--------
274 * RF_REG_3 | BYPASS_EN
275 *
276 */
277 __STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
278 {
279 CLEAR_BITS(AON_PMU->RF_REG_0, AON_PMU_RF_REG_0_IO_LDO_BYPASS);
280 }
281
282 /**
283 * @brief Enable the dig ldo bleed
284 *
285 * Register|BitsName
286 * --------|--------
287 * RF_REG_4 | EN
288 *
289 */
290 __STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
291 {
292 SET_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
293 }
294
295 /**
296 * @brief Disable the dig ldo bleed
297 *
298 * Register|BitsName
299 * --------|--------
300 * RF_REG_4 | EN
301 *
302 */
303 __STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
304 {
305 CLEAR_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BLEED_EN);
306 }
307
308 /**
309 * @brief Set the dig ldo bypass
310 *
311 * Register|BitsName
312 * --------|--------
313 * RF_REG_4 | BYPASS_EN
314 *
315 * @param enable: enable pmu set dig lod bypass.
316 *
317 */
318 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
319 {
320 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN, (enable << AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos));
321 }
322
323 /**
324 * @brief Get the dig ldo bypass
325 *
326 * Register|BitsName
327 * --------|--------
328 * RF_REG_4 | BYPASS_EN
329 *
330 * @retval The dig ldo bypass enable value.
331 *
332 */
333 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
334 {
335 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN) >> AON_PMU_RF_REG_4_DIG_LDO_BYPASS_EN_Pos);
336 }
337
338 /**
339 * @brief Set dig ldo out coarse tune
340 *
341 * Register|BitsName
342 * --------|--------
343 * RF_REG_4 | AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE
344 *
345 * @param value: The dig ldo out value.
346 *
347 */
348 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out_coarse_tune(uint32_t value)
349 {
350 MODIFY_REG(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE, (value << AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE_Pos));
351 }
352
353 /**
354 * @brief Get dig ldo out coarse tune
355 *
356 * Register|BitsName
357 * --------|--------
358 * RF_REG_4 | AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE
359 *
360 * @retval: The dig ldo out value.
361 *
362 */
363 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out_coarse_tune(void)
364 {
365 return (READ_BITS(AON_PMU->RF_REG_4, AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE) >> AON_PMU_RF_REG_4_DIG_LDO_COARSE_TUNE_Pos);
366 }
367
368 /**
369 * @brief Set dig ldo out fine tune
370 *
371 * Register|BitsName
372 * --------|--------
373 * PMU_INTF_OVR_VAL_0 | DDVS_CTL_REF
374 *
375 * @param value: The dig ldo out value.
376 *
377 */
378 __STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out_fine_tune(uint32_t value)
379 {
380 MODIFY_REG(AON_PMU->PMU_INTF_OVR_VAL_0, AON_PMU_VAL_AVS_CTL_REF, (value << AON_PMU_VAL_AVS_CTL_REF_Pos) );
381 SET_BITS(AON_PMU->PMU_INTF_OVR_EN_0, AON_PMU_AVS_CTL_REF_EN);
382 }
383
384 /**
385 * @brief Get dig ldo out fine tune
386 *
387 * Register|BitsName
388 * --------|--------
389 * PMU_INTF_OVR_RD0 | DDVS_CTL_REF
390 *
391 * @retval: The dig ldo out value.
392 *
393 */
394 __STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out_fine_tune(void)
395 {
396 return ((AON_PMU->PMU_INTF_OVR_RD0 & AON_PMU_RD_AVS_CTL_REF_Msk) >> AON_PMU_RD_AVS_CTL_REF_Pos);
397 }
398
399 /**
400 * @brief Set clk period
401 *
402 * Register|BitsName
403 * --------|--------
404 * RF_REG_4 | CLK_PERIOD
405 *
406 * @param value: The period of clk.
407 *
408 */
409 __STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
410 {
411 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_CLK_TRIM, (value << AON_PMU_RF_REG_1_BUCK_CLK_TRIM_Pos));
412 }
413
414 /**
415 * @brief Enables clock injection from XO to ring oscillator.
416 *
417 * Register|BitsName
418 * --------|--------
419 * RF_REG_1 | EN_INJ_ON
420 *
421 *
422 */
423 __STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
424 {
425 SET_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_CLK);
426 }
427
428 /**
429 * @brief Disables clock injection from XO to ring oscillator.
430 *
431 * Register|BitsName
432 * --------|--------
433 * RF_REG_1 | EN_INJ_ON
434 *
435 *
436 */
437 __STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
438 {
439 CLEAR_BITS(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_DCDC_CLK);
440 }
441
442 /**
443 * @brief Set the nunber of BUCK`s PMOS driver
444 *
445 * Register|BitsName
446 * --------|--------
447 * RF_REG_1 | rg_buck_pmmosnum_sel<1:0>
448 *
449 * @param value: The nunber of buck pmos driver
450 *
451 */
452 __STATIC_INLINE void ll_aon_pmu_set_buck_pmmosnum_sel(uint32_t value)
453 {
454 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_PMMOSNUM_SEL, (value << AON_PMU_RF_REG_1_BUCK_PMMOSNUM_SEL_Pos));
455 }
456
457 /**
458 * @brief Set the length of driver`s deadtime
459 *
460 * Register|BitsName
461 * --------|--------
462 * RF_REG_1 | rg_buck_pmmosnum_sel<1:0>
463 *
464 * @param value: The length of driver's deadtime
465 *
466 */
467 __STATIC_INLINE void ll_aon_pmu_set_buck_deadtime_sel(uint32_t value)
468 {
469 MODIFY_REG(AON_PMU->RF_REG_1, AON_PMU_RF_REG_1_BUCK_DEADTIME_SEL, (value << AON_PMU_RF_REG_1_BUCK_DEADTIME_SEL_Pos));
470 }
471
472 /**
473 * @brief Set the rtc cur cap
474 *
475 * Register|BitsName
476 * --------|--------
477 * RC_RTC_REG_0 | RTC_CAP
478 *
479 * @param value: The rtc current cap value.
480 *
481 */
482 __STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
483 {
484 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CS, (value << AON_PMU_RC_RTC_REG0_RTC_CS_Pos));
485 }
486
487 /**
488 * @brief Set the rtc cur cap
489 *
490 * Register|BitsName
491 * --------|--------
492 * RC_RTC_REG_0 | RTC_CAP
493 *
494 * @param value: The rtc current cap value.
495 *
496 */
497 __STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
498 {
499 MODIFY_REG(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP, (value << AON_PMU_RC_RTC_REG0_RTC_CAP_Pos));
500 }
501
502 /**
503 * @brief Get the rtc cur cap
504 *
505 * Register|BitsName
506 * --------|--------
507 * RC_RTC_REG_0 | RTC_CAP
508 *
509 * @retval The rtc current cap value.
510 *
511 */
512 __STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
513 {
514 return (READ_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RTC_CAP) >> AON_PMU_RC_RTC_REG0_RTC_CAP_Pos);
515 }
516
517 /**
518 * @brief Enable the RCOSC
519 *
520 * Register|BitsName
521 * --------|--------
522 * RC_RTC_REG_0 | RCOSC
523 *
524 */
525 __STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
526 {
527 SET_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
528 }
529
530 /**
531 * @brief Disable the RCOSC
532 *
533 * Register|BitsName
534 * --------|--------
535 * RC_RTC_REG_0 | RCOSC
536 *
537 */
538 __STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
539 {
540 CLEAR_BITS(AON_PMU->RC_RTC_REG_0, AON_PMU_RC_RTC_REG0_RCOSC);
541 }
542 /**
543 * @brief modify ton on
544 *
545 * Register|BitsName
546 * --------|--------
547 * PMU_TON_CFG | AON_PMU_TON_CTRL_ON
548 *
549 * @param value: The value of tx ton.
550 *
551 */
552 __STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
553 {
554 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_ON, (value << AON_PMU_TON_CTRL_ON_Pos));
555 }
556 /**
557 * @brief modify ton off
558 *
559 * Register|BitsName
560 * --------|--------
561 * PMU_TON_CFG | AON_PMU_TON_CTRL_OFF
562 *
563 * @param value: The value of non tx ton.
564 *
565 */
566 __STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
567 {
568 MODIFY_REG(AON_PMU->PMU_TON_CFG, AON_PMU_TON_CTRL_OFF, (value << AON_PMU_TON_CTRL_OFF_Pos));
569 }
570 /** @} */
571
572 /**
573 * @brief Enable BOD auto power off in deepsleep and power on wakeup
574 *
575 * Register|BitsName
576 * --------|--------
577 * RF_REG_0 | BOD
578 *
579 */
580 __STATIC_INLINE void ll_aon_pmu_enable_bod_auto_power(void)
581 {
582 CLEAR_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
583 }
584
585 /**
586 * @brief Disable BOD auto power off in deepsleep and power on wakeup
587 *
588 * Register|BitsName
589 * --------|--------
590 * RF_REG_0 | BOD
591 *
592 */
593 __STATIC_INLINE void ll_aon_pmu_disable_bod_auto_power(void)
594 {
595 SET_BITS(AON_PMU->RF_REG_3, AON_PMU_RF_REG_3_BOD2_BYPASS);
596 }
597
598 /**
599 * @brief Enable DCDC power
600 *
601 * Register|BitsName
602 * --------|--------
603 * PMU_INTF | DCDC
604 */
605 __STATIC_INLINE void ll_aon_pmu_enable_dcdc(void)
606 {
607 WRITE_REG(AON_PWR->PWR_SET, AON_PWR_PWR_SET_DCDC_SET);
608 }
609
610 /**
611 * @brief Disble DCDC power
612 *
613 * Register|BitsName
614 * --------|--------
615 * PMU_INTF | DCDC
616 */
617 __STATIC_INLINE void ll_aon_pmu_disable_dcdc(void)
618 {
619 WRITE_REG(AON_PWR->PWR_CLR, AON_PWR_PWR_CLR_DCDC_CLR);
620 }
621
622 /**
623 * @brief Get the DCDC enable status
624 *
625 * Register|BitsName
626 * --------|--------
627 * PWR_STS | sts_dcdc_avl
628 *
629 * @retval The dcdc available status, 1: available, 0: not available
630 *
631 */
632 __STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_available_status(void)
633 {
634 return (READ_BITS(AON_PWR->PWR_STAT, AON_PWR_PWR_STAT_DCDC_AVL) >> AON_PWR_PWR_STAT_DCDC_AVL_Pos);
635 }
636
637
638 /**
639 * @brief Enable SYSLDO power
640 *
641 * Register|BitsName
642 * --------|--------
643 * PMU_INTF | SYSLDO
644 */
645 __STATIC_INLINE void ll_aon_pmu_enable_sysldo(void)
646 {
647 WRITE_REG(AON_PWR->PWR_SET, AON_PWR_PWR_SET_FAST_LDO_SET);
648 }
649
650 /**
651 * @brief Disable SYSLDO power
652 *
653 * Register|BitsName
654 * --------|--------
655 * PMU_INTF | DCDC
656 */
657 __STATIC_INLINE void ll_aon_pmu_disable_sysldo(void)
658 {
659 WRITE_REG(AON_PWR->PWR_CLR, AON_PWR_PWR_CLR_FAST_LDO_CLR);
660 }
661
662 /**
663 * @brief Get the SYSLDO enable status
664 *
665 * Register|BitsName
666 * --------|--------
667 * PWR_STS | sts_dig_ldo_avl
668 *
669 * @retval The sysldo available status, 1: available, 0: not available
670 *
671 */
672 __STATIC_INLINE uint32_t ll_aon_pmu_get_sysldo_available_status(void)
673 {
674 return (READ_BITS(AON_PWR->PWR_STAT, AON_PWR_PWR_STAT_FAST_LDO_AVL) >> AON_PWR_PWR_STAT_FAST_LDO_AVL_Pos);
675 }
676
677 #ifdef __cplusplus
678 }
679 #endif
680
681 #endif
682
683 /** @} */
684
685 /** @} */
686
687 /** @} */
ll_aon_pmu_set_dig_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_bypass(bool enable)
Set the dig ldo bypass.
Definition: ll_aon_pmu.h:318
ll_aon_pmu_set_dig_ldo_out_coarse_tune
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out_coarse_tune(uint32_t value)
Set dig ldo out coarse tune.
Definition: ll_aon_pmu.h:348
ll_aon_pmu_disable_dcdc
__STATIC_INLINE void ll_aon_pmu_disable_dcdc(void)
Disble DCDC power.
Definition: ll_aon_pmu.h:617
ll_aon_pmu_set_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_tx_ton_val(uint32_t value)
modify ton on
Definition: ll_aon_pmu.h:552
ll_aon_pmu_get_dig_ldo_bypass
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_bypass(void)
Get the dig ldo bypass.
Definition: ll_aon_pmu.h:333
ll_aon_pmu_get_dig_ldo_out_coarse_tune
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out_coarse_tune(void)
Get dig ldo out coarse tune.
Definition: ll_aon_pmu.h:363
ll_aon_pmu_set_clk_period
__STATIC_INLINE void ll_aon_pmu_set_clk_period(uint32_t value)
Set clk period.
Definition: ll_aon_pmu.h:409
ll_aon_pmu_set_dcdc_step_18mV
__STATIC_INLINE void ll_aon_pmu_set_dcdc_step_18mV(void)
Set dcdc voltage step for 18mV.
Definition: ll_aon_pmu.h:207
ll_aon_pmu_disable_sysldo
__STATIC_INLINE void ll_aon_pmu_disable_sysldo(void)
Disable SYSLDO power.
Definition: ll_aon_pmu.h:657
ll_aon_pmu_set_rtc_cs
__STATIC_INLINE void ll_aon_pmu_set_rtc_cs(uint32_t value)
Set the rtc cur cap.
Definition: ll_aon_pmu.h:482
ll_aon_pmu_set_non_tx_ton_val
__STATIC_INLINE void ll_aon_pmu_set_non_tx_ton_val(uint32_t value)
modify ton off
Definition: ll_aon_pmu.h:566
ll_aon_pmu_set_dcdc_step_25mV
__STATIC_INLINE void ll_aon_pmu_set_dcdc_step_25mV(void)
Set dcdc voltage step for 25mV.
Definition: ll_aon_pmu.h:221
ll_aon_pmu_enable_clk_inject
__STATIC_INLINE void ll_aon_pmu_enable_clk_inject(void)
Enables clock injection from XO to ring oscillator.
Definition: ll_aon_pmu.h:423
ll_aon_pmu_disable_rtc
__STATIC_INLINE void ll_aon_pmu_disable_rtc(void)
Disable the RTC.
Definition: ll_aon_pmu.h:88
ll_aon_pmu_set_buck_pmmosnum_sel
__STATIC_INLINE void ll_aon_pmu_set_buck_pmmosnum_sel(uint32_t value)
Set the nunber of BUCK`s PMOS driver.
Definition: ll_aon_pmu.h:452
ll_aon_pmu_set_rtc_gm
__STATIC_INLINE void ll_aon_pmu_set_rtc_gm(uint32_t value)
Set RTC GM.
Definition: ll_aon_pmu.h:103
ll_aon_pmu_set_retention_level
__STATIC_INLINE void ll_aon_pmu_set_retention_level(uint32_t value)
Set retention level.
Definition: ll_aon_pmu.h:133
ll_aon_pmu_set_sysldo_vreg
__STATIC_INLINE void ll_aon_pmu_set_sysldo_vreg(uint32_t value)
Set sysldo rg_sysldo_ctrl_vref, vreg defaulted to 1.1V.
Definition: ll_aon_pmu.h:236
ll_aon_pmu_get_sysldo_available_status
__STATIC_INLINE uint32_t ll_aon_pmu_get_sysldo_available_status(void)
Get the SYSLDO enable status.
Definition: ll_aon_pmu.h:672
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_aon_pmu_disable_clk_inject
__STATIC_INLINE void ll_aon_pmu_disable_clk_inject(void)
Disables clock injection from XO to ring oscillator.
Definition: ll_aon_pmu.h:437
ll_aon_pmu_set_buck_deadtime_sel
__STATIC_INLINE void ll_aon_pmu_set_buck_deadtime_sel(uint32_t value)
Set the length of driver`s deadtime.
Definition: ll_aon_pmu.h:467
ll_aon_pmu_disable_bleed
__STATIC_INLINE void ll_aon_pmu_disable_bleed(void)
Disable the dig ldo bleed.
Definition: ll_aon_pmu.h:303
ll_aon_pmu_disable_bod_auto_power
__STATIC_INLINE void ll_aon_pmu_disable_bod_auto_power(void)
Disable BOD auto power off in deepsleep and power on wakeup.
Definition: ll_aon_pmu.h:593
ll_aon_pmu_get_aon_ldo
__STATIC_INLINE uint32_t ll_aon_pmu_get_aon_ldo(void)
Get aon ldo value.
Definition: ll_aon_pmu.h:163
ll_aon_pmu_disable_rcosc
__STATIC_INLINE void ll_aon_pmu_disable_rcosc(void)
Disable the RCOSC.
Definition: ll_aon_pmu.h:538
ll_aon_pmu_enable_rtc
__STATIC_INLINE void ll_aon_pmu_enable_rtc(void)
Enable the RTC.
Definition: ll_aon_pmu.h:75
ll_aon_pmu_enable_bleed
__STATIC_INLINE void ll_aon_pmu_enable_bleed(void)
Enable the dig ldo bleed.
Definition: ll_aon_pmu.h:290
ll_aon_pmu_set_aon_ldo
__STATIC_INLINE void ll_aon_pmu_set_aon_ldo(uint32_t value)
Set aon ldo value.
Definition: ll_aon_pmu.h:148
ll_aon_pmu_enable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_enable_io_ldo_bypass(void)
Enable the io ldo bypass.
Definition: ll_aon_pmu.h:264
ll_aon_pmu_get_dig_ldo_out_fine_tune
__STATIC_INLINE uint32_t ll_aon_pmu_get_dig_ldo_out_fine_tune(void)
Get dig ldo out fine tune.
Definition: ll_aon_pmu.h:394
ll_aon_pmu_set_rtc_cap
__STATIC_INLINE void ll_aon_pmu_set_rtc_cap(uint32_t value)
Set the rtc cur cap.
Definition: ll_aon_pmu.h:497
ll_aon_pmu_get_sysldo_vreg
__STATIC_INLINE uint32_t ll_aon_pmu_get_sysldo_vreg(void)
Get sysldo rg_sysldo_ctrl_vref, vreg defaulted to 1.1V.
Definition: ll_aon_pmu.h:251
ll_aon_pmu_set_dcdc_vreg
__STATIC_INLINE void ll_aon_pmu_set_dcdc_vreg(uint32_t value)
Set dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
Definition: ll_aon_pmu.h:178
ll_aon_pmu_enable_bod_auto_power
__STATIC_INLINE void ll_aon_pmu_enable_bod_auto_power(void)
Enable BOD auto power off in deepsleep and power on wakeup.
Definition: ll_aon_pmu.h:580
ll_aon_pmu_get_dcdc_available_status
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_available_status(void)
Get the DCDC enable status.
Definition: ll_aon_pmu.h:632
ll_aon_pmu_enable_rcosc
__STATIC_INLINE void ll_aon_pmu_enable_rcosc(void)
Enable the RCOSC.
Definition: ll_aon_pmu.h:525
ll_aon_pmu_enable_sysldo
__STATIC_INLINE void ll_aon_pmu_enable_sysldo(void)
Enable SYSLDO power.
Definition: ll_aon_pmu.h:645
ll_aon_pmu_get_dcdc_vreg
__STATIC_INLINE uint32_t ll_aon_pmu_get_dcdc_vreg(void)
Get dcdc ref_cntrl_b_lv_3_0,vreg defaulted to 1.1V.
Definition: ll_aon_pmu.h:193
ll_aon_pmu_set_dig_ldo_out_fine_tune
__STATIC_INLINE void ll_aon_pmu_set_dig_ldo_out_fine_tune(uint32_t value)
Set dig ldo out fine tune.
Definition: ll_aon_pmu.h:378
ll_aon_pmu_set_io_ldo_vout
__STATIC_INLINE void ll_aon_pmu_set_io_ldo_vout(uint32_t value)
Set lv,default is set to 1.8V,LSB = 8.5mv.
Definition: ll_aon_pmu.h:118
ll_aon_pmu_disable_io_ldo_bypass
__STATIC_INLINE void ll_aon_pmu_disable_io_ldo_bypass(void)
Disable the io ldo bypass.
Definition: ll_aon_pmu.h:277
ll_aon_pmu_enable_dcdc
__STATIC_INLINE void ll_aon_pmu_enable_dcdc(void)
Enable DCDC power.
Definition: ll_aon_pmu.h:605
ll_aon_pmu_get_rtc_cap
__STATIC_INLINE uint32_t ll_aon_pmu_get_rtc_cap(void)
Get the rtc cur cap.
Definition: ll_aon_pmu.h:512