ll_i2c.h
Go to the documentation of this file.
1 /**
2 ****************************************************************************************
3 *
4 * @file ll_i2c.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2C LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2C I2C
47 * @brief I2C LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef ___LL_I2C_H__
53 #define ___LL_I2C_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5x.h"
61
62 #if defined (I2C0) || defined (I2C1)
63
64 /** @defgroup I2C_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2C_LL_ES_INIT I2C Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2C init Structure definition
75 */
76 typedef struct _ll_i2c_init
77 {
78 uint32_t speed; /**< Specifies the transfer speed. See @ref I2C_LL_EC_SPEED. */
79
80 uint32_t own_address; /**< Specifies the device own address.
81 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
82
83 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
84
85 uint32_t own_addr_size; /**< Specifies the device own address 1 size (7-bit or 10-bit).
86 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS
87
88 This feature can be modified afterwards using unitary function @ref ll_i2c_set_own_address(). */
89 } ll_i2c_init_t;
90
91 /** @} */
92
93 /** @} */
94
95 /**
96 * @defgroup I2C_LL_MACRO Defines
97 * @{
98 */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
102 * @{
103 */
104
105 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
106 * @brief Flags definitions which can be used with LL_I2C_ReadReg function
107 * @{
108 */
109 #define LL_I2C_INTR_STAT_SCL_STUCK_AT_LOW I2C_RAW_INT_STAT_SCL_STUCKLOW /**< SCL_STUCK_AT_LOW interrupt flag */
110 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_RAW_INT_STAT_M_HOLD /**< MST_ON_HOLD interrupt flag */
111 #define LL_I2C_INTR_STAT_RESTART_DET I2C_RAW_INT_STAT_RESTART_DET /**< RESTART_DET interrupt flag */
112 #define LL_I2C_INTR_STAT_GEN_CALL I2C_RAW_INT_STAT_GEN_CALL /**< GEN_CALL interrupt flag */
113 #define LL_I2C_INTR_STAT_START_DET I2C_RAW_INT_STAT_START_DET /**< START_DET interrupt flag */
114 #define LL_I2C_INTR_STAT_STOP_DET I2C_RAW_INT_STAT_STOP_DET /**< STOP_DET interrupt flag */
115 #define LL_I2C_INTR_STAT_ACTIVITY I2C_RAW_INT_STAT_ACTIVITY /**< ACTIVITY interrupt flag */
116 #define LL_I2C_INTR_STAT_RX_DONE I2C_RAW_INT_STAT_RX_DONE /**< RX_DONE interrupt flag */
117 #define LL_I2C_INTR_STAT_TX_ABRT I2C_RAW_INT_STAT_TX_ABORT /**< TX_ABRT interrupt flag */
118 #define LL_I2C_INTR_STAT_RD_REQ I2C_RAW_INT_STAT_RD_REQ /**< RD_REQ interrupt flag */
119 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_RAW_INT_STAT_TX_EMPTY /**< TX_EMPTY interrupt flag */
120 #define LL_I2C_INTR_STAT_TX_OVER I2C_RAW_INT_STAT_TX_OVER /**< TX_OVER interrupt flag */
121 #define LL_I2C_INTR_STAT_RX_FULL I2C_RAW_INT_STAT_RX_FULL /**< RX_FULL interrupt flag */
122 #define LL_I2C_INTR_STAT_RX_OVER I2C_RAW_INT_STAT_RX_OVER /**< RX_OVER interrupt flag */
123 #define LL_I2C_INTR_STAT_RX_UNDER I2C_RAW_INT_STAT_RX_UNDER /**< RX_UNDER interrupt flag */
124
125 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABORT_SRC_TX_FLUSH_CNT /**< Indcates the number of TX FOFO data command */
126 #define LL_I2C_ABRT_SDA_STUCK_AT_LOW I2C_TX_ABORT_SRC_ABORT_SDA_STUCK /**< The SDA stuck at low detected by master */
127 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABORT_SRC_ABORT_USER_ABORT /**< Transfer abort detected by master */
128 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABORT_SRC_ABORT_SLVRD_INTX /**< Slave trying to transmit to remote master in read mode */
129 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABORT_SRC_ABORT_S_ARBLOST /**< Slave lost arbitration to remote master */
130 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABORT_SRC_ABORT_SLVFLUSH_TXFIFO /**< Slave flushes existing data in TX-FIFO upon getting read command */
131 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABORT_SRC_ABORT_LOST /**< Master or Slave Transmitter lost arbitration */
132 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABORT_SRC_ABORT_MASTER_DIS /**< User intitating master operation when MASTER disabled */
133 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABORT_SRC_ABORT_10B_RD_NORSTR /**< Master trying to read in 10-Bit addressing mode when RESTART disabled */
134 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABORT_SRC_ABORT_SBYTE_NORSTRT /**< User trying to send START byte when RESTART disabled */
135 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABORT_SRC_ABORT_HS_NORSTRT /**< User trying to swidth Master to HS mode when RESTART disabled */
136 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABORT_SRC_ABORT_SBYTE_ACKDET /**< ACK detected for START byte */
137 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABORT_SRC_ABORT_HS_ACKDET /**< HS Master code is ACKed in HS Mode */
138 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABORT_SRC_ABORT_GCALL_RD /**< GCALL is followed by read from bus */
139 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABORT_SRC_ABORT_GCALL_NOACK /**< GCALL is not ACKed by any slave */
140 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABORT_SRC_ABORT_TX_NOACK /**< Transmitted data is not ACKed by addressed slave */
141 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABORT_SRC_ABORT_10B2_NOACK /**< Byte 2 of 10-Bit Address is not ACKed by any slave */
142 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABORT_SRC_ABORT_10B1_NOACK /**< Byte 1 of 10-Bit Address is not ACKed by any slave */
143 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABORT_SRC_ABORT_7B_NOACK /**< 7Bit Address is not ACKed by any slave */
144 /** @} */
145
146 /** @defgroup I2C_LL_EC_IT IT Defines
147 * @brief Interrupt definitions which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
148 * @{
149 */
150 #define LL_I2C_INTR_MASK_SCL_STUCK_AT_LOW I2C_INT_MASK_MASK_SCL_STUCKLOW /**< SCL_STUCK_AT_LOW interrupt flag */
151 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INT_MASK_MASK_M_HOLD /**< MST_ON_HOLD interrupt */
152 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INT_MASK_MASK_RESTART_DET /**< RESTART_DET interrupt */
153 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INT_MASK_MASK_GEN_CALL /**< GEN_CALL interrupt */
154 #define LL_I2C_INTR_MASK_START_DET I2C_INT_MASK_MASK_START_DET /**< START_DET interrupt */
155 #define LL_I2C_INTR_MASK_STOP_DET I2C_INT_MASK_MASK_STOP_DET /**< STOP_DET interrupt */
156 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INT_MASK_MASK_ACTIVITY /**< ACTIVITY interrupt */
157 #define LL_I2C_INTR_MASK_RX_DONE I2C_INT_MASK_MASK_RX_DONE /**< RX_DONE interrupt */
158 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INT_MASK_MASK_TX_ABORT /**< TX_ABRT interrupt */
159 #define LL_I2C_INTR_MASK_RD_REQ I2C_INT_MASK_MASK_RD_REQ /**< RD_REQ interrupt */
160 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INT_MASK_MASK_TX_EMPTY /**< TX_EMPTY interrupt */
161 #define LL_I2C_INTR_MASK_TX_OVER I2C_INT_MASK_MASK_TX_OVER /**< TX_OVER interrupt */
162 #define LL_I2C_INTR_MASK_RX_FULL I2C_INT_MASK_MASK_RX_FULL /**< RX_FULL interrupt */
163 #define LL_I2C_INTR_MASK_RX_OVER I2C_INT_MASK_MASK_RX_OVER /**< RX_OVER interrupt */
164 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INT_MASK_MASK_RX_UNDER /**< RX_UNDER interrupt */
165
166 #define LL_I2C_INTR_MASK_ALL 0x00007FFFU /**< All interrupt */
167 /** @} */
168
169 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
170 * @{
171 */
172 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /**< Master operates in 7-bit addressing mode. */
173 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CTRL_ADDR_BIT_M /**< Master operates in 10-bit addressing mode.*/
174 /** @} */
175
176 /** @defgroup I2C_LL_EC_OWNADDRESS Own Address Length
177 * @{
178 */
179 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U /**< Own address 1 is a 7-bit address. */
180 #define LL_I2C_OWNADDRESS_10BIT I2C_CTRL_ADDR_BIT_S /**< Own address 1 is a 10-bit address.*/
181 /** @} */
182
183
184 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
185 * @{
186 */
187 #define LL_I2C_CMD_SLV_NONE 0x00000000U /**< Slave No command. */
188 #define LL_I2C_CMD_MST_WRITE 0x00000000U /**< Master write command. */
189 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD /**< Master read command. */
190 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP /**< Master issue STOP after this command. */
191 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART /**< Master issue RESTART before this command. */
192 /** @} */
193
194 /** @defgroup I2C_LL_EC_SPEED_MODE Transfer Speed Mode
195 * @{
196 */
197 #define LL_I2C_SPEED_MODE_STANDARD (0x1UL << I2C_CTRL_SPEED_POS) /**< Standard Speed mode(0 to 100 Kb/s) of operation. */
198 #define LL_I2C_SPEED_MODE_FAST (0x2UL << I2C_CTRL_SPEED_POS) /**< Fast (400 Kb/s) or Fast Plus mode (1000 Kb/s) of operation. */
199 #define LL_I2C_SPEED_MODE_HIGH (0x3UL << I2C_CTRL_SPEED_POS) /**< High Speed mode (3.4 Mb/s) of operation. */
200 /** @} */
201
202 /** @defgroup I2C_LL_EC_SPEED Transfer Speed
203 * @{
204 */
205 #define LL_I2C_SPEED_100K (100000U) /**< Standard Speed. */
206 #define LL_I2C_SPEED_400K (400000U) /**< Fast Speed. */
207 #define LL_I2C_SPEED_1000K (1000000U) /**< Fast Plus Speed. */
208 #define LL_I2C_SPEED_2000K (2000000U) /**< High Speed. */
209 /** @} */
210
211 /** @defgroup I2C_LL_EC_TX_FIFO_TH TX FIFO Threshold
212 * @{
213 */
214 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
215 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U /**< 1 character in TX FIFO */
216 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U /**< 2 characters in TX FIFO */
217 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U /**< 3 characters in TX FIFO */
218 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U /**< 4 characters in TX FIFO */
219 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U /**< 5 characters in TX FIFO */
220 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U /**< 6 characters in TX FIFO */
221 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U /**< 7 characters in TX FIFO */
222 #define LL_I2C_TX_FIFO_TH_CHAR_8 0x00000008U /**< 9 character in TX FIFO */
223 #define LL_I2C_TX_FIFO_TH_CHAR_9 0x00000009U /**< 9 characters in TX FIFO */
224 #define LL_I2C_TX_FIFO_TH_CHAR_10 0x0000000AU /**< 10 characters in TX FIFO */
225 #define LL_I2C_TX_FIFO_TH_CHAR_11 0x0000000BU /**< 11 characters in TX FIFO */
226 #define LL_I2C_TX_FIFO_TH_CHAR_12 0x0000000CU /**< 12 characters in TX FIFO */
227 #define LL_I2C_TX_FIFO_TH_CHAR_13 0x0000000DU /**< 13 characters in TX FIFO */
228 #define LL_I2C_TX_FIFO_TH_CHAR_14 0x0000000EU /**< 14 characters in TX FIFO */
229 #define LL_I2C_TX_FIFO_TH_CHAR_15 0x0000000FU /**< 15 character in TX FIFO */
230 #define LL_I2C_TX_FIFO_TH_CHAR_16 0x00000010U /**< 16 characters in TX FIFO */
231 #define LL_I2C_TX_FIFO_TH_CHAR_17 0x00000011U /**< 17 characters in TX FIFO */
232 #define LL_I2C_TX_FIFO_TH_CHAR_18 0x00000012U /**< 18 characters in TX FIFO */
233 #define LL_I2C_TX_FIFO_TH_CHAR_19 0x00000013U /**< 19 characters in TX FIFO */
234 #define LL_I2C_TX_FIFO_TH_CHAR_20 0x00000014U /**< 20 characters in TX FIFO */
235 #define LL_I2C_TX_FIFO_TH_CHAR_21 0x00000015U /**< 21 characters in TX FIFO */
236 #define LL_I2C_TX_FIFO_TH_CHAR_22 0x00000016U /**< 22 character in TX FIFO */
237 #define LL_I2C_TX_FIFO_TH_CHAR_23 0x00000017U /**< 23 characters in TX FIFO */
238 #define LL_I2C_TX_FIFO_TH_CHAR_24 0x00000018U /**< 24 characters in TX FIFO */
239 #define LL_I2C_TX_FIFO_TH_CHAR_25 0x00000019U /**< 25 characters in TX FIFO */
240 #define LL_I2C_TX_FIFO_TH_CHAR_26 0x0000001AU /**< 26 characters in TX FIFO */
241 #define LL_I2C_TX_FIFO_TH_CHAR_27 0x0000001BU /**< 27 characters in TX FIFO */
242 #define LL_I2C_TX_FIFO_TH_CHAR_28 0x0000001CU /**< 28 characters in TX FIFO */
243 #define LL_I2C_TX_FIFO_TH_CHAR_29 0x0000001DU /**< 29 characters in TX FIFO */
244 #define LL_I2C_TX_FIFO_TH_CHAR_30 0x0000001EU /**< 30 characters in TX FIFO */
245 #define LL_I2C_TX_FIFO_TH_CHAR_31 0x0000001FU /**< 31 characters in TX FIFO */
246 #define LL_I2C_TX_FIFO_TH_CHAR_32 0x00000020U /**< 32 characters in TX FIFO */
247
248 /** @} */
249
250 /** @defgroup I2C_LL_EC_RX_FIFO_TH RX FIFO Threshold
251 * @{
252 */
253 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
254 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in RX FIFO */
255 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U /**< 3 characters in RX FIFO */
256 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U /**< 4 characters in RX FIFO */
257 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U /**< 5 characters in RX FIFO */
258 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U /**< 6 characters in RX FIFO */
259 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U /**< 7 characters in RX FIFO */
260 #define LL_I2C_RX_FIFO_TH_CHAR_8 0x00000007U /**< 8 character in RX FIFO */
261 #define LL_I2C_RX_FIFO_TH_CHAR_9 0x00000008U /**< 9 characters in RX FIFO */
262 #define LL_I2C_RX_FIFO_TH_CHAR_10 0x00000009U /**< 10 characters in RX FIFO */
263 #define LL_I2C_RX_FIFO_TH_CHAR_11 0x0000000AU /**< 11 characters in RX FIFO */
264 #define LL_I2C_RX_FIFO_TH_CHAR_12 0x0000000BU /**< 12 characters in RX FIFO */
265 #define LL_I2C_RX_FIFO_TH_CHAR_13 0x0000000CU /**< 13 characters in RX FIFO */
266 #define LL_I2C_RX_FIFO_TH_CHAR_14 0x0000000DU /**< 14 characters in RX FIFO */
267 #define LL_I2C_RX_FIFO_TH_CHAR_15 0x0000000EU /**< 15 character in RX FIFO */
268 #define LL_I2C_RX_FIFO_TH_CHAR_16 0x0000000FU /**< 16 characters in RX FIFO */
269 #define LL_I2C_RX_FIFO_TH_CHAR_17 0x00000010U /**< 17 characters in RX FIFO */
270 #define LL_I2C_RX_FIFO_TH_CHAR_18 0x00000011U /**< 18 characters in RX FIFO */
271 #define LL_I2C_RX_FIFO_TH_CHAR_19 0x00000012U /**< 19 characters in RX FIFO */
272 #define LL_I2C_RX_FIFO_TH_CHAR_20 0x00000013U /**< 20 characters in RX FIFO */
273 #define LL_I2C_RX_FIFO_TH_CHAR_21 0x00000014U /**< 21 characters in RX FIFO */
274 #define LL_I2C_RX_FIFO_TH_CHAR_22 0x00000015U /**< 22 character in RX FIFO */
275 #define LL_I2C_RX_FIFO_TH_CHAR_23 0x00000016U /**< 23 characters in RX FIFO */
276 #define LL_I2C_RX_FIFO_TH_CHAR_24 0x00000017U /**< 24 characters in RX FIFO */
277 #define LL_I2C_RX_FIFO_TH_CHAR_25 0x00000018U /**< 25 characters in RX FIFO */
278 #define LL_I2C_RX_FIFO_TH_CHAR_26 0x00000019U /**< 26 characters in RX FIFO */
279 #define LL_I2C_RX_FIFO_TH_CHAR_27 0x0000001AU /**< 27 characters in RX FIFO */
280 #define LL_I2C_RX_FIFO_TH_CHAR_28 0x0000001BU /**< 28 characters in RX FIFO */
281 #define LL_I2C_RX_FIFO_TH_CHAR_29 0x0000001CU /**< 29 character in RX FIFO */
282 #define LL_I2C_RX_FIFO_TH_CHAR_30 0x0000001DU /**< 30 characters in RX FIFO */
283 #define LL_I2C_RX_FIFO_TH_CHAR_31 0x0000001EU /**< 31 characters in RX FIFO */
284 #define LL_I2C_RX_FIFO_TH_CHAR_32 0x0000001FU /**< 32 characters in RX FIFO */
285 #define LL_I2C_RX_FIFO_TH_FULL 0x00000020U /**< RX FIFO full */
286 /** @} */
287
288 /** @defgroup I2C_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
289 * @{
290 */
291
292 /**
293 * @brief LL I2C InitStrcut default configuartion
294 */
295 #define LL_I2C_DEFAULT_CONFIG \
296 { \
297 .speed = LL_I2C_SPEED_400K, \
298 .own_address = 0x55U, \
299 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
300 }
301 /** @} */
302
303 /** @} */
304
305 /* Exported macro ------------------------------------------------------------*/
306 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
307 * @{
308 */
309
310 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
311 * @{
312 */
313
314 /**
315 * @brief Write a value in I2C register
316 * @param __instance__ I2C instance
317 * @param __REG__ Register to be written
318 * @param __VALUE__ Value to be written in the register
319 * @retval None.
320 */
321 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
322
323 /**
324 * @brief Read a value in I2C register
325 * @param __instance__ I2C instance
326 * @param __REG__ Register to be read
327 * @retval Register value
328 */
329 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
330 /** @} */
331
332 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
333 * @{
334 */
335
336 /**
337 * @brief Compute CLK_SSL_CNT value according to Peripheral Clock and expected Speed.
338 * @param __PERIPHCLK__ Peripheral Clock frequency used for I2C instance
339 * @param __SPEED__ Speed value to achieve
340 * @retval CLK_SSL_CNT value to be used for XS_SCL_HCNT, XS_SCL_LCNT registers where X can be (S, F, H)
341 */
342 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
343
344 /**
345 * @brief Get Speed Mode according to expected Speed.
346 * @param __SPEED__ Speed value to achieve
347 * @retval Returned value can be one of the following values:
348 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
349 * @arg @ref LL_I2C_SPEED_MODE_FAST
350 * @arg @ref LL_I2C_SPEED_MODE_HIGH
351 */
352 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
353 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : LL_I2C_SPEED_MODE_HIGH))
354 /** @} */
355
356 /** @} */
357
358 /** @} */
359
360 /* Private types -------------------------------------------------------------*/
361 /* Private variables ---------------------------------------------------------*/
362 /* Private constants ---------------------------------------------------------*/
363 /* Private macros ------------------------------------------------------------*/
364
365 /* Exported functions --------------------------------------------------------*/
366 /** @defgroup I2C_LL_DRIVER_FUNCTIONS Functions
367 * @{
368 */
369
370 /** @defgroup I2C_LL_EF_Configuration Configuration
371 * @{
372 */
373
374 /**
375 * @brief Enable I2C peripheral (ENABLE = 1).
376 *
377 * Register|BitsName
378 * ---------------|---------------
379 * EN | ACTIVITY
380 *
381 * @param I2Cx I2C instance.
382 * @retval None.
383 */
384 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
385 {
386 SET_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
387 }
388
389 /**
390 * @brief Disable I2C peripheral (ENABLE = 0).
391 * @note When ENABLE = 0, the TX FIFO and RX FIFO get flushed.
392 * Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state.
393 * If the module is transmitting, it stops as well as deletes the contents of the transmit buffer
394 * after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops
395 * the current transfer at the end of the current byte and does not acknowledge the transfer..
396 *
397 * Register|BitsName
398 * ---------------|---------------
399 * EN | ACTIVITY
400 *
401 * @param I2Cx I2C instance.
402 * @retval None.
403 */
404 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
405 {
406 CLEAR_BITS(I2Cx->EN, I2C_EN_ACTIVITY);
407 }
408
409 /**
410 * @brief Check if the I2C peripheral is enabled or disabled.
411 *
412 * Register|BitsName
413 * ---------------|---------------
414 * STAT | STAT_EN
415 *
416 * @param I2Cx I2C instance.
417 * @retval State of bit (1 or 0).
418 */
419 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
420 {
421 return (READ_BITS(I2Cx->STAT, I2C_EN_STAT_EN) == (I2C_EN_STAT_EN));
422 }
423
424 /**
425 * @brief Enable I2C master mode.
426 *
427 * Register|BitsName
428 * ---------------|---------------
429 * CTRL | MASTER_ENABLE
430 * CTRL | SLAVE_DISABLE
431 * @param I2Cx I2C instance.
432 * @retval None.
433 */
434 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
435 {
436 SET_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
437 }
438
439 /**
440 * @brief Disable I2C master mode and enable slave mode.
441 *
442 * Register|BitsName
443 * ---------------|---------------
444 * CTRL | MASTER_ENABLE
445 * CTRL | SLAVE_DISABLE
446 * @param I2Cx I2C instance.
447 * @retval None.
448 */
449 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
450 {
451 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS);
452 }
453
454 /**
455 * @brief Check if I2C master mode is enabled or disabled.
456 *
457 * Register|BitsName
458 * ---------------|---------------
459 * CTRL | MASTER_ENABLE
460 * CTRL | SLAVE_DISABLE
461 *
462 * @param I2Cx I2C instance.
463 * @retval State of bit (1 or 0).
464 */
465 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
466 {
467 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_M_MODE | I2C_CTRL_S_DIS) == (I2C_CTRL_M_MODE | I2C_CTRL_S_DIS));
468 }
469
470 /**
471 * @brief Enable General Call(slave mode).
472 * @note When enabled, the Address 0x00 is ACKed.
473 *
474 * Register|BitsName
475 * ---------------|---------------
476 * ACK_GEN_CALL | ACK_GEN_CALL
477 *
478 * @param I2Cx I2C instance.
479 * @retval None.
480 */
481 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
482 {
483 SET_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
484 }
485
486 /**
487 * @brief Disable General Call(slave mode).
488 * @note When disabled, the Address 0x00 is NACKed.
489 *
490 * Register|BitsName
491 * ---------------|---------------
492 * ACK_GEN_CALL | ACK_GEN_CALL
493 *
494 * @param I2Cx I2C instance.
495 * @retval None.
496 */
497 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
498 {
499 CLEAR_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL);
500 }
501
502 /**
503 * @brief Check if General Call is enabled or disabled(slave mode).
504 *
505 * Register|BitsName
506 * ---------------|---------------
507 * ACK_GEN_CALL | ACK_GEN_CALL
508 *
509 * @param I2Cx I2C instance.
510 * @retval State of bit (1 or 0).
511 */
512 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
513 {
514 return (READ_BITS(I2Cx->ACK_GEN_CALL, I2C_ACK_GEN_CALL_ACK_GEN_CALL) == (I2C_ACK_GEN_CALL_ACK_GEN_CALL));
515 }
516
517 /**
518 * @brief Enable Master Restart.
519 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
520 * This bit determines whether RESTART conditions may be sent when acting as a master.
521 * Some older slaves do not support handling RESTART conditions.
522 * When RESTART is disabled, the master is prohibited from performing the following functions:
523 * - Performing any high-speed mode operation.
524 * - Performing direction changes in combined format mode.
525 * - Performing a read operation with a 10-bit address.
526 *
527 * Register|BitsName
528 * ---------------|---------------
529 * CTRL | RESTART_EN
530 *
531 * @param I2Cx I2C instance.
532 * @retval None.
533 */
534 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
535 {
536 SET_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
537 }
538
539 /**
540 * @brief Disable Master Restart.
541 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
542 *
543 * Register|BitsName
544 * ---------------|---------------
545 * CTRL | RESTART_EN
546 *
547 * @param I2Cx I2C instance.
548 * @retval None.
549 */
550 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
551 {
552 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN);
553 }
554
555 /**
556 * @brief Check if Master Restart is enabled or disabled.
557 *
558 * Register|BitsName
559 * ---------------|---------------
560 * CTRL | RESTART_EN
561 *
562 * @param I2Cx I2C instance.
563 * @retval State of bit (1 or 0).
564 */
565 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
566 {
567 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_RESTART_EN) == (I2C_CTRL_RESTART_EN));
568 }
569
570 /**
571 * @brief Enable Slave issues STOP_DET interrupt only if addressed function.
572 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
573 * During a general call address, the slave does not issue the STOP_DET interrupt if
574 * STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address
575 * by generating ACK. The STOP_DET interrupt is generated only when the transmitted
576 * address matches the slave address (SAR).
577 *
578 * Register|BitsName
579 * ---------------|---------------
580 * CTRL | STOP_DET_INT
581 *
582 * @param I2Cx I2C instance.
583 * @retval None.
584 */
585 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
586 {
587 SET_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
588 }
589
590 /**
591 * @brief Disable Slave issues STOP_DET interrupt only if addressed function.
592 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
593 *
594 * Register|BitsName
595 * ---------------|---------------
596 * CTRL | STOP_DET_INT
597 *
598 * @param I2Cx I2C instance.
599 * @retval None.
600 */
601 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
602 {
603 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT);
604 }
605
606 /**
607 * @brief Hold bus when the RX FIFO if full function.
608 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
609 *
610 * Register|BitsName
611 * ---------------|---------------
612 * CTRL | RXFIFO_FULL_HLD
613 *
614 * @param I2Cx I2C instance.
615 * @retval None.
616 */
617 __STATIC_INLINE void ll_i2c_hold_bus_if_rx_full(i2c_regs_t *I2Cx)
618 {
619 SET_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
620 }
621
622 /**
623 * @brief overflow when the RX FIFO if full function.
624 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
625 *
626 * Register|BitsName
627 * ---------------|---------------
628 * CTRL | RXFIFO_FULL_HLD
629 *
630 * @param I2Cx I2C instance.
631 * @retval None.
632 */
633 __STATIC_INLINE void ll_i2c_overflow_if_rx_full(i2c_regs_t *I2Cx)
634 {
635 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_RXFIFO_FULL_HLD);
636 }
637
638 /**
639 * @brief enable bus clear feature function.
640 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
641 *
642 * Register|BitsName
643 * ---------------|---------------
644 * CTRL | BUS_CLR_FEATURE
645 *
646 * @param I2Cx I2C instance.
647 * @retval None.
648 */
649 __STATIC_INLINE void ll_i2c_enable_bus_clear_feature(i2c_regs_t *I2Cx)
650 {
651 SET_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
652 }
653
654 /**
655 * @brief disable bus clear feature function.
656 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
657 *
658 * Register|BitsName
659 * ---------------|---------------
660 * CTRL | BUS_CLR_FEATURE
661 *
662 * @param I2Cx I2C instance.
663 * @retval None.
664 */
665 __STATIC_INLINE void ll_i2c_disable_bus_clear_feature(i2c_regs_t *I2Cx)
666 {
667 CLEAR_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE);
668 }
669
670 /**
671 * @brief check bus clear feature is enabled function.
672 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
673 *
674 * Register|BitsName
675 * ---------------|---------------
676 * CTRL | BUS_CLR_FEATURE
677 *
678 * @param I2Cx I2C instance.
679 * @retval None.
680 */
681 __STATIC_INLINE uint32_t ll_i2c_is_enabled_bus_clear_feature(i2c_regs_t *I2Cx)
682 {
683 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_BUS_CLR_FEATURE) == (I2C_CTRL_BUS_CLR_FEATURE));
684 }
685
686 /**
687 * @brief Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
688 *
689 * Register|BitsName
690 * ---------------|---------------
691 * CTRL | STOP_DET_INT
692 *
693 * @param I2Cx I2C instance.
694 * @retval State of bit (1 or 0).
695 */
696 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
697 {
698 return (READ_BITS(I2Cx->CTRL, I2C_CTRL_STOP_DET_INT) == (I2C_CTRL_STOP_DET_INT));
699 }
700
701 /**
702 * @brief Configure the Master to transfers in 7-bit or 10-bit addressing mode.
703 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
704 *
705 * Register|BitsName
706 * ---------------|---------------
707 * CTRL | ADDR_BIT_M
708 *
709 * @param I2Cx I2C instance.
710 * @param addressing_mode This parameter can be one of the following values:
711 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
712 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
713 * @retval None.
714 */
715 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
716 {
717 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M, addressing_mode);
718 }
719
720 /**
721 * @brief Get the Master addressing mode.
722 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
723 *
724 * Register|BitsName
725 * ---------------|---------------
726 * CTRL | ADDR_BIT_M
727 *
728 * @param I2Cx I2C instance.
729 * @retval Returned value can be one of the following values:
730 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
731 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
732 */
733 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
734 {
735 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_M));
736 }
737
738 /**
739 * @brief Set the Own Address.
740 * @note The register IC_CON and IC_SAR can only be programmed when the I2C is disabled (IC_ENABLE = 0).
741 *
742 * Register|BitsName
743 * ---------------|---------------
744 * CTRL | ADDR_BIT_S
745 * S_ADDR | SAR
746 *
747 * @param I2Cx I2C instance.
748 * @param own_address This parameter must be a value range between 0 ~ 0x3FF(10-bit mode) or 0 ~ 0x7F(7-bit mode).
749 * Reserved address 0x00 to 0x07, or 0x78 to 0x7f should not be configured.
750 * @param own_addr_size This parameter can be one of the following values:
751 * @arg @ref LL_I2C_OWNADDRESS_7BIT
752 * @arg @ref LL_I2C_OWNADDRESS_10BIT
753 * @retval None.
754 */
755 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
756 {
757 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_ADDR_BIT_S, own_addr_size);
758 WRITE_REG(I2Cx->S_ADDR, own_address);
759 }
760
761 /**
762 * @brief Set the SCL clock high-period count for standard speed.
763 * @note The register IC_SS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
764 *
765 * Register|BitsName
766 * ---------------|---------------
767 * SS_CLK_HCOUNT | SS_SCL_HCNT
768 *
769 * @param I2Cx I2C instance.
770 * @param count This parameter must be a value range between 6 ~ 0xFFF5.
771 * @retval None.
772 */
773 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
774 {
775 WRITE_REG(I2Cx->SS_CLK_HCOUNT, count);
776 }
777
778 /**
779 * @brief Get the SCL clock high-period count for standard speed.
780 *
781 * Register|BitsName
782 * ---------------|---------------
783 * SS_CLK_HCOUNT | COUNT
784 *
785 * @param I2Cx I2C instance.
786 * @retval Value range between 0x6 and 0xFFF5.
787 */
788 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
789 {
790 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_HCOUNT, I2C_SS_CLK_HCOUNT_COUNT));
791 }
792
793 /**
794 * @brief Set the SCL clock low-period count for standard speed.
795 * @note The register IC_SS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
796 *
797 * Register|BitsName
798 * ---------------|---------------
799 * SS_CLK_LCOUNT | COUNT
800 *
801 * @param I2Cx I2C instance.
802 * @param count This parameter must be a value range between 0x8 and 0xFFFF.
803 * @retval None.
804 */
805 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
806 {
807 WRITE_REG(I2Cx->SS_CLK_LCOUNT, count);
808 }
809
810 /**
811 * @brief Get the SCL clock low-period count for standard speed.
812 *
813 * Register|BitsName
814 * ---------------|---------------
815 * SS_CLK_LCOUNT | COUNT
816 *
817 * @param I2Cx I2C instance.
818 * @retval Value range between 0x8 and 0xFFFF.
819 */
820 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
821 {
822 return (uint32_t)(READ_BITS(I2Cx->SS_CLK_LCOUNT, I2C_SS_CLK_LCOUNT_COUNT));
823 }
824
825 /**
826 * @brief Set the SCL clock high-period count for fast speed.
827 * @note The register IC_FS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
828 *
829 * Register|BitsName
830 * ---------------|---------------
831 * FS_CLK_HCOUNT | COUNT
832 *
833 * @param I2Cx I2C instance.
834 * @param count range between 0x6 and 0xFFFF.
835 * @retval None.
836 */
837 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
838 {
839 WRITE_REG(I2Cx->FS_CLK_HCOUNT, count);
840 }
841
842 /**
843 * @brief Get the SCL clock high-period count for fast speed.
844 *
845 * Register|BitsName
846 * ---------------|---------------
847 * FS_CLK_HCOUNT | COUNT
848 *
849 * @param I2Cx I2C instance.
850 * @retval Value range between 0x6 and 0xFFFF.
851 */
852 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
853 {
854 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_HCOUNT, I2C_FS_CLK_HCOUNT_COUNT));
855 }
856
857 /**
858 * @brief Set the SCL clock low-period count for fast speed.
859 * @note The register IC_FS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
860 *
861 * Register|BitsName
862 * ---------------|---------------
863 * FS_CLK_LCOUNT | COUNT
864 *
865 * @param I2Cx I2C instance.
866 * @param count range between 0x8 and 0xFFFF
867 * @retval None.
868 */
869 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
870 {
871 WRITE_REG(I2Cx->FS_CLK_LCOUNT, count);
872 }
873
874 /**
875 * @brief Get the SCL clock low-period count for fast speed.
876 *
877 * Register|BitsName
878 * ---------------|---------------
879 * FS_CLK_LCOUNT | COUNT
880 *
881 * @param I2Cx I2C instance.
882 * @retval Value range between 0x8 and 0xFFFF.
883 */
884 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
885 {
886 return (uint32_t)(READ_BITS(I2Cx->FS_CLK_LCOUNT, I2C_FS_CLK_LCOUNT_COUNT));
887 }
888
889 #ifdef HAL_I2C_VERSION_OLD
890 /**
891 * @brief Get the SCL clock high-period count for high speed.
892 * @note The register IC_HS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
893 *
894 * Register|BitsName
895 * ---------------|---------------
896 * HS_CLK_HCOUNT | COUNT
897 *
898 * @param I2Cx I2C instance.
899 * @param count range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 5.
900 * @retval None.
901 */
902 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
903 {
904 WRITE_REG(I2Cx->HS_CLK_HCOUNT, count);
905 }
906
907 /**
908 * @brief Get the SCL clock high-period count for high speed.
909 *
910 * Register|BitsName
911 * ---------------|---------------
912 * HS_CLK_HCOUNT | COUNT
913 *
914 * @param I2Cx I2C instance.
915 * @retval range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 7.
916 */
917 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
918 {
919 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_HCOUNT, I2C_HS_CLK_HCOUNT_COUNT));
920 }
921
922 /**
923 * @brief Get the SCL clock low-period count for high speed.
924 * @note The register IC_HS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
925 *
926 * Register|BitsName
927 * ---------------|---------------
928 * HS_CLK_LCOUNT | COUNT
929 *
930 * @param I2Cx I2C instance.
931 * @param count range between 0x8 and 0xFFFF
932 * @retval None.
933 */
934 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
935 {
936 WRITE_REG(I2Cx->HS_CLK_LCOUNT, count);
937 }
938
939 /**
940 * @brief Get the SCL clock low-period count for high speed.
941 *
942 * Register|BitsName
943 * ---------------|---------------
944 * HS_CLK_LCOUNT | COUNT
945 *
946 * @param I2Cx I2C instance.
947 * @retval Value range between 0x8 and 0xFFFF
948 */
949 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
950 {
951 return (uint32_t)(READ_BITS(I2Cx->HS_CLK_LCOUNT, I2C_HS_CLK_LCOUNT_COUNT));
952 }
953 #endif
954
955 /**
956 * @brief Set the spike len in fast speed mode.
957 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
958 *
959 * Register|BitsName
960 * ---------------|---------------
961 * FS_SPKLEN | FS_SPKLEN
962 *
963 * @param I2Cx I2C instance.
964 * @param length Spike len.
965 * @retval None.
966 */
967 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
968 {
969 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
970 }
971
972 /**
973 * @brief Get the spike len in fast speed mode.
974 *
975 * Register|BitsName
976 * ---------------|---------------
977 * FS_SPKLEN | FS_SPKLEN
978 *
979 * @param I2Cx I2C instance.
980 * @retval Value range between 0x2 and 0xFF.
981 */
982 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
983 {
984 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
985 }
986
987 #ifdef HAL_I2C_VERSION_OLD
988 /**
989 * @brief Set the spike len in high speed mode.
990 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
991 *
992 * Register|BitsName
993 * ---------------|---------------
994 * HS_SPKLEN | HS_SPKLEN
995 *
996 * @param I2Cx I2C instance.
997 * @param length Spike len.
998 * @retval None.
999 */
1000 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
1001 {
1002 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
1003 }
1004 #endif
1005
1006 /**
1007 * @brief Get the spike len in high speed mode.
1008 *
1009 * Register|BitsName
1010 * ---------------|---------------
1011 * HS_SPKLEN | HS_SPKLEN
1012 *
1013 * @param I2Cx I2C instance.
1014 * @retval Value range between 0x2 and 0xFF.
1015 */
1016 #ifdef HAL_I2C_VERSION_OLD
1017 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
1018 {
1019 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
1020 }
1021 #endif
1022 /**
1023 * @brief Set I2C Speed mode.
1024 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1025 *
1026 * Register|BitsName
1027 * ---------------|---------------
1028 * CTRL | SPEED
1029 *
1030 * @param I2Cx I2C instance.
1031 * @param speed_mode This parameter can be one of the following values:
1032 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1033 * @arg @ref LL_I2C_SPEED_MODE_FAST
1034 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1035 * @retval None.
1036 */
1037 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
1038 {
1039 MODIFY_REG(I2Cx->CTRL, I2C_CTRL_SPEED, speed_mode);
1040 }
1041
1042 /**
1043 * @brief Get I2C Speed mode.
1044 *
1045 * Register|BitsName
1046 * ---------------|---------------
1047 * CTRL | SPEED
1048 *
1049 * @param I2Cx I2C instance.
1050 * @retval Value can be one of the following values:
1051 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
1052 * @arg @ref LL_I2C_SPEED_MODE_FAST
1053 * @arg @ref LL_I2C_SPEED_MODE_HIGH
1054 */
1055 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
1056 {
1057 return (uint32_t)(READ_BITS(I2Cx->CTRL, I2C_CTRL_SPEED));
1058 }
1059
1060 #ifdef HAL_I2C_VERSION_OLD
1061 /**
1062 * @brief Set I2C High Speed Master Code Address.
1063 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
1064 *
1065 * Register|BitsName
1066 * ---------------|---------------
1067 * M_HS_ADDR | HS_MAR
1068 *
1069 * @param I2Cx I2C instance.
1070 * @param code HS mode master code, range between 0x00 and 0x07.
1071 * @retval None.
1072 */
1073 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
1074 {
1075 WRITE_REG(I2Cx->M_HS_ADDR, code);
1076 }
1077
1078 /**
1079 * @brief Get I2C Speed mode.
1080 *
1081 * Register|BitsName
1082 * ---------------|---------------
1083 * M_HS_ADDR | HS_MAR
1084 *
1085 * @param I2Cx I2C instance.
1086 * @retval Returned value range between 0x00 and 0x07.
1087 */
1088 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
1089 {
1090 return (uint32_t)(READ_BITS(I2Cx->M_HS_ADDR, I2C_M_HS_ADDR_HS_ADDR));
1091 }
1092 #endif
1093
1094 /**
1095 * @brief Set the required transmit SDA hold time in units of ic_clk period.
1096 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1097 *
1098 * Register|BitsName
1099 * ---------------|---------------
1100 * SDA_HOLD | TX_HOLD
1101 *
1102 * @param I2Cx I2C instance.
1103 * @param time SDA Tx hold time in units of ic_clk period.
1104 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1105 * @retval None.
1106 */
1107 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1108 {
1109 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_POS);
1110 }
1111
1112 /**
1113 * @brief Get the required transmit SDA hold time in units of ic_clk period.
1114 *
1115 * Register|BitsName
1116 * ---------------|---------------
1117 * SDA_HOLD | TX_HOLD
1118 *
1119 * @param I2Cx I2C instance.
1120 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1121 */
1122 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
1123 {
1124 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_POS);
1125 }
1126
1127 /**
1128 * @brief Set the required receive SDA hold time in units of ic_clk period.
1129 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1130 *
1131 * Register|BitsName
1132 * ---------------|---------------
1133 * SDA_HOLD | RX_HOLD
1134 *
1135 * @param I2Cx I2C instance.
1136 * @param time SDA Tx hold time in units of ic_clk period.
1137 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1138 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1139 */
1140 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1141 {
1142 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_POS);
1143 }
1144
1145 /**
1146 * @brief Get the required receive SDA hold time in units of ic_clk period.
1147 *
1148 * Register|BitsName
1149 * ---------------|---------------
1150 * SDA_HOLD | RX_HOLD
1151 *
1152 * @param I2Cx I2C instance.
1153 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1154 */
1155 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1156 {
1157 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_POS);
1158 }
1159
1160 /**
1161 * @brief Set the SDA setup time when operating as a slave transmitter.
1162 * @note The register IC_SDA_SETUP can only be programmed when the I2C is disabled (ENABLE = 0).
1163 * The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the
1164 * user requires 10 ic_clk periods of setup time, they should program a value of 11.
1165 *
1166 * Register|BitsName
1167 * ---------------|---------------
1168 * SDA_SETUP | SETUP
1169 *
1170 * @param I2Cx I2C instance.
1171 * @param time SDA data setup time in units of ic_clk period, range between 2 ~ 0xFF.
1172 * @retval None.
1173 */
1174 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1175 {
1176 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP, time);
1177 }
1178
1179 /**
1180 * @brief Get the SDA setup time when operating as a slave transmitter.
1181 *
1182 * Register|BitsName
1183 * ---------------|---------------
1184 * SDA_SETUP | SETUP
1185 *
1186 * @param I2Cx I2C instance.
1187 * @retval Value range between 0x02 and 0xFF.
1188 */
1189 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1190 {
1191 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SETUP));
1192 }
1193
1194 /**
1195 * @brief Set threshold of entries (or below) that trigger the TX_EMPTY interrupt
1196 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1197 *
1198 * Register|BitsName
1199 * ---------------|---------------
1200 * TX_FIFO_THD | THD
1201 *
1202 * @param I2Cx I2C instance
1203 * @param threshold This parameter can be one of the following values:
1204 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1205 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1206 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1207 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1208 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1209 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1210 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1211 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1212 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_8
1213 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_9
1214 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_10
1215 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_11
1216 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_12
1217 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_13
1218 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_14
1219 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_15
1220 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_16
1221 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_17
1222 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_18
1223 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_19
1224 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_20
1225 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_21
1226 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_22
1227 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_23
1228 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_24
1229 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_25
1230 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_26
1231 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_27
1232 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_28
1233 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_29
1234 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_30
1235 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_31
1236 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_32
1237 * @retval None.
1238 */
1239 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1240 {
1241 WRITE_REG(I2Cx->TX_FIFO_THD, threshold);
1242 }
1243
1244 /**
1245 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
1246 *
1247 * Register|BitsName
1248 * ---------------|---------------
1249 * TX_FIFO_THD | THD
1250 *
1251 * @param I2Cx I2C instance
1252 * @retval Returned value can be one of the following values:
1253 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1254 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1255 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1256 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1257 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1258 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1259 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1260 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1261 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_8
1262 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_9
1263 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_10
1264 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_11
1265 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_12
1266 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_13
1267 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_14
1268 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_15
1269 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_16
1270 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_17
1271 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_18
1272 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_19
1273 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_20
1274 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_21
1275 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_22
1276 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_23
1277 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_24
1278 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_25
1279 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_26
1280 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_27
1281 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_28
1282 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_29
1283 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_30
1284 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_31
1285 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_32
1286 */
1287 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1288 {
1289 return (uint32_t)(READ_BITS(I2Cx->TX_FIFO_THD, I2C_TX_FIFO_THD_THD));
1290 }
1291
1292 /**
1293 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
1294 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1295 *
1296 * Register|BitsName
1297 * ---------------|---------------
1298 * RX_FIFO_THD | THD
1299 *
1300 * @param I2Cx I2C instance
1301 * @param threshold This parameter can be one of the following values:
1302 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1303 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1304 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1305 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1306 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1307 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1308 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1309 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_8
1310 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_9
1311 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_10
1312 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_11
1313 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_12
1314 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_13
1315 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_14
1316 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_15
1317 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_16
1318 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_17
1319 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_18
1320 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_19
1321 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_20
1322 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_21
1323 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_22
1324 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_23
1325 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_24
1326 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_25
1327 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_26
1328 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_27
1329 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_28
1330 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_29
1331 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_30
1332 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_31
1333 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_32
1334 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1335 * @retval None.
1336 */
1337 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1338 {
1339 WRITE_REG(I2Cx->RX_FIFO_THD, threshold);
1340 }
1341
1342 /**
1343 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
1344 *
1345 * Register|BitsName
1346 * ---------------|---------------
1347 * RX_FIFO_THD | THD
1348 *
1349 * @param I2Cx I2C instance
1350 * @retval Returned value can be one of the following values:
1351 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1352 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1353 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1354 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1355 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1356 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1357 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1358 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_8
1359 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_9
1360 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_10
1361 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_11
1362 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_12
1363 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_13
1364 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_14
1365 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_15
1366 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_16
1367 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_17
1368 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_18
1369 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_19
1370 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_20
1371 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_21
1372 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_22
1373 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_23
1374 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_24
1375 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_25
1376 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_26
1377 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_27
1378 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_28
1379 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_29
1380 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_30
1381 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_31
1382 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_32
1383 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1384 */
1385 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1386 {
1387 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_THD, I2C_RX_FIFO_THD_THD));
1388 }
1389
1390 /**
1391 * @brief Get FIFO Transmission Level
1392 *
1393 * Register|BitsName
1394 * ---------------|---------------
1395 * RX_FIFO_THD | LEVEL
1396 *
1397 * @param I2Cx I2C instance
1398 * @retval Value range between 0x0 and 0x1F.
1399 */
1400 __STATIC_INLINE uint16_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1401 {
1402 return (uint16_t)(READ_BITS(I2Cx->TX_FIFO_LEVEL, I2C_TX_FIFO_LEVEL_LEVEL));
1403 }
1404
1405 /**
1406 * @brief Get FIFO reception Level
1407 *
1408 * Register|BitsName
1409 * ---------------|---------------
1410 * RX_FIFO_THD | LEVEL
1411 *
1412 * @param I2Cx I2C instance
1413 * @retval Value range between 0x0 and 0x1F.
1414 */
1415 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1416 {
1417 return (uint32_t)(READ_BITS(I2Cx->RX_FIFO_LEVEL, I2C_RX_FIFO_LEVEL_LEVEL));
1418 }
1419
1420 /**
1421 * @brief Master initates the SDA stuck at low recovery mechanism.
1422 *
1423 * Register|BitsName
1424 * ---------------|---------------
1425 * EN | SDA_STUCK_RECOVERY
1426 *
1427 * @param I2Cx I2C instance
1428 */
1429 __STATIC_INLINE void ll_i2c_enable_sda_stuck_recovery(i2c_regs_t *I2Cx)
1430 {
1431 SET_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1432 }
1433
1434 /**
1435 * @brief Master disabled the SDA stuck at low recovery mechanism
1436 *
1437 * Register|BitsName
1438 * ---------------|---------------
1439 * EN | SDA_STUCK_RECOVERY
1440 *
1441 * @param I2Cx I2C instance
1442 */
1443 __STATIC_INLINE void ll_i2c_disable_sda_stuck_recovery(i2c_regs_t *I2Cx)
1444 {
1445 CLEAR_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY);
1446 }
1447
1448 /**
1449 * @brief the SDA stuck at low recovery mechanism is enabled or disabled.
1450 *
1451 * Register|BitsName
1452 * ---------------|---------------
1453 * EN | SDA_STUCK_RECOVERY
1454 *
1455 * @param I2Cx I2C instance
1456 * @retval State of bit (1 or 0).
1457 */
1458 __STATIC_INLINE uint32_t ll_i2c_is_enabled_sda_stuck_recovery(i2c_regs_t *I2Cx)
1459 {
1460 return (READ_BITS(I2Cx->EN, I2C_EN_SDA_STUCK_RECOVERY) == (I2C_EN_SDA_STUCK_RECOVERY));
1461 }
1462
1463 /**
1464 * @brief Enable DMA reception requests.
1465 *
1466 * Register|BitsName
1467 * ---------------|---------------
1468 * EN | ABORT
1469 *
1470 * @param I2Cx I2C instance.
1471 * @retval None.
1472 */
1473 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1474 {
1475 SET_BITS(I2Cx->EN, I2C_EN_ABORT);
1476 }
1477
1478 /**
1479 * @brief Check if DMA reception requests are enabled or disabled.
1480 *
1481 * Register|BitsName
1482 * ---------------|---------------
1483 * EN | ABORT
1484 *
1485 * @param I2Cx I2C instance.
1486 * @retval State of bit (1 or 0).
1487 */
1488 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1489 {
1490 return (READ_BITS(I2Cx->EN, I2C_EN_ABORT) == (I2C_EN_ABORT));
1491 }
1492
1493 /**
1494 * @brief Get the transmit abort source.
1495 * @note This can be used to retrieve source of TX_ABRT interrupt.
1496 *
1497 * Register|BitsName
1498 * ---------------|---------------
1499 * TX_ABORT_SRC | ABRT_USER_ABRT
1500 * TX_ABORT_SRC | ABRT_SLVRD_INTX
1501 * TX_ABORT_SRC | ABRT_SLV_ARBLOST
1502 * TX_ABORT_SRC | ABRT_SLVFLUSH_TXFIFO
1503 * TX_ABORT_SRC | ABRT_ARB_LOST
1504 * TX_ABORT_SRC | ABRT_MST_DIS
1505 * TX_ABORT_SRC | ABRT_10B_RD_NORSTRT
1506 * TX_ABORT_SRC | ABRT_SBYTE_NORSTRT
1507 * TX_ABORT_SRC | ABRT_HS_NORSTRT
1508 * TX_ABORT_SRC | ABRT_SBYTE_ACKDET
1509 * TX_ABORT_SRC | ABRT_HS_ACKDET
1510 * TX_ABORT_SRC | ABRT_GCALL_READ
1511 * TX_ABORT_SRC | ABRT_GCALL_NOACK
1512 * TX_ABORT_SRC | ABRT_TXDATA_NOACK
1513 * TX_ABORT_SRC | ABRT_10ADDR2_NOACK
1514 * TX_ABORT_SRC | ABRT_10ADDR1_NOACK
1515 * TX_ABORT_SRC | ABRT_7B_ADDR_NOACK
1516 *
1517 * @param I2Cx I2C instance
1518 * @retval Returned value can be a combination of the following values:
1519 * @arg @ref LL_I2C_ABRT_USER_ABRT
1520 * @arg @ref LL_I2C_ABRT_SLVRD_INTX
1521 * @arg @ref LL_I2C_ABRT_SLV_ARBLOST
1522 * @arg @ref LL_I2C_ABRT_SLVFLUSH_TXFIFO
1523 * @arg @ref LL_I2C_ABRT_ARB_LOST
1524 * @arg @ref LL_I2C_ABRT_MST_DIS
1525 * @arg @ref LL_I2C_ABRT_10B_RD_NORSTRT
1526 * @arg @ref LL_I2C_ABRT_SBYTE_NORSTRT
1527 * @arg @ref LL_I2C_ABRT_HS_NORSTRT
1528 * @arg @ref LL_I2C_ABRT_SBYTE_ACKDET
1529 * @arg @ref LL_I2C_ABRT_HS_ACKDET
1530 * @arg @ref LL_I2C_ABRT_GCALL_READ
1531 * @arg @ref LL_I2C_ABRT_GCALL_NOACK
1532 * @arg @ref LL_I2C_ABRT_TXDATA_NOACK
1533 * @arg @ref LL_I2C_ABRT_10ADDR2_NOACK
1534 * @arg @ref LL_I2C_ABRT_10ADDR1_NOACK
1535 * @arg @ref LL_I2C_ABRT_7B_ADDR_NOACK
1536 *
1537 * @note @arg @ref LL_I2C_ABRT_TX_FLUSH_CNT can be used as a mask to get the
1538 * number of Tx FIFO Data Commands which are flushed due to TX_ABRT
1539 * interrupt.
1540 */
1541 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1542 {
1543 return (uint32_t)(READ_REG(I2Cx->TX_ABORT_SRC) & (~I2C_TX_ABORT_SRC_TX_FLUSH_CNT));
1544 }
1545
1546 /**
1547 * @brief Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
1548 *
1549 * Register|BitsName
1550 * ---------------|---------------
1551 * TX_ABORT_SRC | TX_FLUSH_CNT
1552 *
1553 * @param I2Cx I2C instance
1554 * @retval Tx flush count.
1555 */
1556 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1557 {
1558 return (uint32_t)(READ_BITS(I2Cx->TX_ABORT_SRC, I2C_TX_ABORT_SRC_TX_FLUSH_CNT) >> I2C_TX_ABORT_SRC_TX_FLUSH_CNT_POS);
1559 }
1560
1561 /** @} */
1562
1563 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1564 * @{
1565 */
1566
1567 /**
1568 * @brief Enable specified interrupts.
1569 *
1570 * Register|BitsName
1571 * ---------------|---------------
1572 * INT_MASK | MASK_GEN_CALL
1573 * INT_MASK | MASK_START_DET
1574 * INT_MASK | MASK_STOP_DET
1575 * INT_MASK | MASK_ACTIVITY
1576 * INT_MASK | MASK_RX_DONE
1577 * INT_MASK | MASK_TX_ABRT
1578 * INT_MASK | MASK_RD_REQ
1579 * INT_MASK | MASK_TX_EMPTY
1580 * INT_MASK | MASK_TX_OVER
1581 * INT_MASK | MASK_RX_FULL
1582 * INT_MASK | MASK_RX_OVER
1583 * INT_MASK | MASK_RX_UNDER
1584 *
1585 * @param I2Cx I2C instance.
1586 * @param mask This parameter can be a combination of the following values:
1587 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1588 * @arg @ref LL_I2C_INTR_MASK_START_DET
1589 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1590 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1591 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1592 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1593 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1594 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1595 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1596 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1597 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1598 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1599 * @retval None.
1600 */
1601 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1602 {
1603 SET_BITS(I2Cx->INT_MASK, mask);
1604 }
1605
1606 /**
1607 * @brief Disable specified interrupts.
1608 *
1609 * Register|BitsName
1610 * ---------------|---------------
1611 * INT_MASK | MASK_GEN_CALL
1612 * INT_MASK | MASK_START_DET
1613 * INT_MASK | MASK_STOP_DET
1614 * INT_MASK | MASK_ACTIVITY
1615 * INT_MASK | MASK_RX_DONE
1616 * INT_MASK | MASK_TX_ABRT
1617 * INT_MASK | MASK_RD_REQ
1618 * INT_MASK | MASK_TX_EMPTY
1619 * INT_MASK | MASK_TX_OVER
1620 * INT_MASK | MASK_RX_FULL
1621 * INT_MASK | MASK_RX_OVER
1622 * INT_MASK | MASK_RX_UNDER
1623 *
1624 * @param I2Cx I2C instance.
1625 * @param mask This parameter can be a combination of the following values:
1626 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1627 * @arg @ref LL_I2C_INTR_MASK_START_DET
1628 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1629 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1630 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1631 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1632 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1633 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1634 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1635 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1636 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1637 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1638 * @retval None.
1639 */
1640 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1641 {
1642 CLEAR_BITS(I2Cx->INT_MASK, mask);
1643 }
1644
1645 /**
1646 * @brief Check if the specified interrupts are enabled or disabled.
1647 *
1648 * Register|BitsName
1649 * ---------------|---------------
1650 * INT_MASK | MASK_GEN_CALL
1651 * INT_MASK | MASK_START_DET
1652 * INT_MASK | MASK_STOP_DET
1653 * INT_MASK | MASK_ACTIVITY
1654 * INT_MASK | MASK_RX_DONE
1655 * INT_MASK | MASK_TX_ABRT
1656 * INT_MASK | MASK_RD_REQ
1657 * INT_MASK | MASK_TX_EMPTY
1658 * INT_MASK | MASK_TX_OVER
1659 * INT_MASK | MASK_RX_FULL
1660 * INT_MASK | MASK_RX_OVER
1661 * INT_MASK | MASK_RX_UNDER
1662 *
1663 * @param I2Cx I2C instance.
1664 * @param mask This parameter can be a combination of the following values:
1665 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1666 * @arg @ref LL_I2C_INTR_MASK_START_DET
1667 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1668 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1669 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1670 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1671 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1672 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1673 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1674 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1675 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1676 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1677 * @retval State of bit (1 or 0).
1678 */
1679 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1680 {
1681 return (READ_BITS(I2Cx->INT_MASK, mask) == (mask));
1682 }
1683
1684 /**
1685 * @brief Enable SCL_STUCK_AT_LOW interrupt.
1686 *
1687 * Register|BitsName
1688 * ---------------|---------------
1689 * INT_MASK | SCL_STUCK_AT_LOW
1690 *
1691 * @param I2Cx I2C instance.
1692 * @retval None.
1693 */
1694 __STATIC_INLINE void ll_i2c_enable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1695 {
1696 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1697 }
1698 /**
1699 * @brief Disable SCL_STUCK_AT_LOW interrupt.
1700 *
1701 * Register|BitsName
1702 * ---------------|---------------
1703 * INT_MASK | SCL_STUCK_AT_LOW
1704 *
1705 * @param I2Cx I2C instance.
1706 * @retval None.
1707 */
1708 __STATIC_INLINE void ll_i2c_disable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1709 {
1710 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW);
1711 }
1712 /**
1713 * @brief Check if the SCL_STUCK_AT_LOW Interrupt is enabled or disabled.
1714 *
1715 * Register|BitsName
1716 * ---------------|---------------
1717 * INT_MASK | SCL_STUCK_AT_LOW
1718 *
1719 * @param I2Cx I2C instance.
1720 * @retval State of bit (1 or 0).
1721 */
1722 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
1723 {
1724 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_SCL_STUCKLOW) == (I2C_INT_MASK_MASK_SCL_STUCKLOW));
1725 }
1726
1727 #ifdef HAL_I2C_VERSION_OLD
1728 /**
1729 * @brief Enable MASTER_ON_HOLD interrupt.
1730 *
1731 * Register|BitsName
1732 * ---------------|---------------
1733 * INT_MASK | M_HOLD
1734 *
1735 * @param I2Cx I2C instance.
1736 * @retval None.
1737 */
1738 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1739 {
1740 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1741 }
1742
1743 /**
1744 * @brief Disable MASTER_ON_HOLD interrupt.
1745 *
1746 * Register|BitsName
1747 * ---------------|---------------
1748 * INT_MASK | M_HOLD
1749 *
1750 * @param I2Cx I2C instance.
1751 * @retval None.
1752 */
1753 __STATIC_INLINE void ll_i2c_disable_it_master_on_hold(i2c_regs_t *I2Cx)
1754 {
1755 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD);
1756 }
1757
1758 /**
1759 * @brief Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
1760 *
1761 * Register|BitsName
1762 * ---------------|---------------
1763 * INT_MASK | M_HOLD
1764 *
1765 * @param I2Cx I2C instance.
1766 * @retval State of bit (1 or 0).
1767 */
1768 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1769 {
1770 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_M_HOLD) == (I2C_INT_MASK_MASK_M_HOLD));
1771 }
1772
1773 /**
1774 * @brief Enable RESTART_DET interrupt.
1775 *
1776 * Register|BitsName
1777 * ---------------|---------------
1778 * INT_MASK | RESTART_DET
1779 *
1780 * @param I2Cx I2C instance.
1781 * @retval None.
1782 */
1783 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1784 {
1785 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1786 }
1787
1788 /**
1789 * @brief Disable RESTART_DET interrupt.
1790 *
1791 * Register|BitsName
1792 * ---------------|---------------
1793 * INT_MASK | RESTART_DET
1794 *
1795 * @param I2Cx I2C instance.
1796 * @retval None.
1797 */
1798 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1799 {
1800 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET);
1801 }
1802
1803 /**
1804 * @brief Check if the RESTART_DET Interrupt is enabled or disabled.
1805 *
1806 * Register|BitsName
1807 * ---------------|---------------
1808 * INT_MASK | RESTART_DET
1809 *
1810 * @param I2Cx I2C instance.
1811 * @retval State of bit (1 or 0).
1812 */
1813 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1814 {
1815 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RESTART_DET) == (I2C_INT_MASK_MASK_RESTART_DET));
1816 }
1817 #endif
1818
1819 /**
1820 * @brief Enable GEN_CALL interrupt.
1821 *
1822 * Register|BitsName
1823 * ---------------|---------------
1824 * INT_MASK | GEN_CALL
1825 *
1826 * @param I2Cx I2C instance.
1827 * @retval None.
1828 */
1829 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1830 {
1831 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1832 }
1833
1834 /**
1835 * @brief Disable GEN_CALL interrupt.
1836 *
1837 * Register|BitsName
1838 * ---------------|---------------
1839 * INT_MASK | GEN_CALL
1840 *
1841 * @param I2Cx I2C instance.
1842 * @retval None.
1843 */
1844 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1845 {
1846 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL);
1847 }
1848
1849 /**
1850 * @brief Check if GEN_CALL interrupt is enabled or disabled.
1851 *
1852 * Register|BitsName
1853 * ---------------|---------------
1854 * INT_MASK | GEN_CALL
1855 *
1856 * @param I2Cx I2C instance.
1857 * @retval State of bit (1 or 0).
1858 */
1859 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1860 {
1861 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_GEN_CALL) == (I2C_INT_MASK_MASK_GEN_CALL));
1862 }
1863
1864 /**
1865 * @brief Enable START_DET received interrupt.
1866 *
1867 * Register|BitsName
1868 * ---------------|---------------
1869 * INT_MASK | START_DET
1870 *
1871 * @param I2Cx I2C instance.
1872 * @retval None.
1873 */
1874 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1875 {
1876 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1877 }
1878
1879 /**
1880 * @brief Disable START_DET received interrupt.
1881 *
1882 * Register|BitsName
1883 * ---------------|---------------
1884 * INT_MASK | START_DET
1885 *
1886 * @param I2Cx I2C instance.
1887 * @retval None.
1888 */
1889 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1890 {
1891 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET);
1892 }
1893
1894 /**
1895 * @brief Check if START_DET received interrupt is enabled or disabled.
1896 *
1897 * Register|BitsName
1898 * ---------------|---------------
1899 * INT_MASK | START_DET
1900 *
1901 * @param I2Cx I2C instance.
1902 * @retval State of bit (1 or 0).
1903 */
1904 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1905 {
1906 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_START_DET) == (I2C_INT_MASK_MASK_START_DET));
1907 }
1908
1909 /**
1910 * @brief Enable STOP_DET interrupt.
1911 *
1912 * Register|BitsName
1913 * ---------------|---------------
1914 * INT_MASK | STOP_DET
1915 *
1916 * @param I2Cx I2C instance.
1917 * @retval None.
1918 */
1919 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1920 {
1921 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1922 }
1923
1924 /**
1925 * @brief Disable STOP_DET interrupt.
1926 *
1927 * Register|BitsName
1928 * ---------------|---------------
1929 * INT_MASK | STOP_DET
1930 *
1931 * @param I2Cx I2C instance.
1932 * @retval None.
1933 */
1934 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1935 {
1936 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET);
1937 }
1938
1939 /**
1940 * @brief Check if STOP_DET interrupt is enabled or disabled.
1941 *
1942 * Register|BitsName
1943 * ---------------|---------------
1944 * INT_MASK | STOP_DET
1945 *
1946 * @param I2Cx I2C instance.
1947 * @retval State of bit (1 or 0).
1948 */
1949 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1950 {
1951 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_STOP_DET) == (I2C_INT_MASK_MASK_STOP_DET));
1952 }
1953
1954 /**
1955 * @brief Enable ACTIVITY interrupt.
1956 *
1957 * Register|BitsName
1958 * ---------------|---------------
1959 * INT_MASK | ACTIVITY
1960 *
1961 * @param I2Cx I2C instance.
1962 * @retval None.
1963 */
1964 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1965 {
1966 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1967 }
1968
1969 /**
1970 * @brief Disable ACTIVITY interrupt.
1971 *
1972 * Register|BitsName
1973 * ---------------|---------------
1974 * INT_MASK | ACTIVITY
1975 *
1976 * @param I2Cx I2C instance.
1977 * @retval None.
1978 */
1979 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1980 {
1981 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY);
1982 }
1983
1984 /**
1985 * @brief Check if ACTIVITY interrupt is enabled or disabled.
1986 *
1987 * Register|BitsName
1988 * ---------------|---------------
1989 * INT_MASK | ACTIVITY
1990 *
1991 * @param I2Cx I2C instance.
1992 * @retval State of bit (1 or 0).
1993 */
1994 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1995 {
1996 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_ACTIVITY) == (I2C_INT_MASK_MASK_ACTIVITY));
1997 }
1998
1999 /**
2000 * @brief Enable RX_DONE interrupt.
2001 *
2002 * Register|BitsName
2003 * ---------------|---------------
2004 * INT_MASK | RX_DONE
2005 *
2006 * @param I2Cx I2C instance.
2007 * @retval State of bit (1 or 0).
2008 */
2009 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
2010 {
2011 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2012 }
2013
2014 /**
2015 * @brief Disable RX_DONE interrupt.
2016 *
2017 * Register|BitsName
2018 * ---------------|---------------
2019 * INT_MASK | RX_DONE
2020 *
2021 * @param I2Cx I2C instance.
2022 * @retval None.
2023 */
2024 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
2025 {
2026 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE);
2027 }
2028
2029 /**
2030 * @brief Check if RX_DONE interrupt is enabled or disabled.
2031 *
2032 * Register|BitsName
2033 * ---------------|---------------
2034 * INT_MASK | RX_DONE
2035 *
2036 * @param I2Cx I2C instance.
2037 * @retval State of bit (1 or 0).
2038 */
2039 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
2040 {
2041 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_DONE) == (I2C_INT_MASK_MASK_RX_DONE));
2042 }
2043
2044 /**
2045 * @brief Enable TX_ABRT interrupt.
2046 *
2047 * Register|BitsName
2048 * ---------------|---------------
2049 * INT_MASK | TX_ABORT
2050 *
2051 * @param I2Cx I2C instance.
2052 * @retval None.
2053 */
2054 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
2055 {
2056 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2057 }
2058
2059 /**
2060 * @brief Disable TX_ABRT interrupt.
2061 *
2062 * Register|BitsName
2063 * ---------------|---------------
2064 * INT_MASK | TX_ABORT
2065 *
2066 * @param I2Cx I2C instance.
2067 * @retval None.
2068 */
2069 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
2070 {
2071 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT);
2072 }
2073
2074 /**
2075 * @brief Check if TX_ABRT interrupt is enabled or disabled.
2076 *
2077 * Register|BitsName
2078 * ---------------|---------------
2079 * INT_MASK | TX_ABORT
2080 *
2081 * @param I2Cx I2C instance.
2082 * @retval None.
2083 */
2084 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
2085 {
2086 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_ABORT) == (I2C_INT_MASK_MASK_TX_ABORT));
2087 }
2088
2089 /**
2090 * @brief Enable RD_REQ interrupt.
2091 *
2092 * Register|BitsName
2093 * ---------------|---------------
2094 * INT_MASK | RD_REQ
2095 *
2096 * @param I2Cx I2C instance.
2097 * @retval None.
2098 */
2099 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
2100 {
2101 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2102 }
2103
2104 /**
2105 * @brief Disable RD_REQ interrupt.
2106 *
2107 * Register|BitsName
2108 * ---------------|---------------
2109 * INT_MASK | RD_REQ
2110 *
2111 * @param I2Cx I2C instance.
2112 * @retval None.
2113 */
2114 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
2115 {
2116 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ);
2117 }
2118
2119 /**
2120 * @brief Check if RD_REQ interrupt is enabled or disabled.
2121 *
2122 * Register|BitsName
2123 * ---------------|---------------
2124 * INT_MASK | RD_REQ
2125 *
2126 * @param I2Cx I2C instance.
2127 * @retval State of bit (1 or 0).
2128 */
2129 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
2130 {
2131 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RD_REQ) == (I2C_INT_MASK_MASK_RD_REQ));
2132 }
2133
2134 /**
2135 * @brief Enable TX_EMPTY interrupt.
2136 *
2137 * Register|BitsName
2138 * ---------------|---------------
2139 * INT_MASK | TX_EMPTY
2140 *
2141 * @param I2Cx I2C instance.
2142 * @retval None.
2143 */
2144 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
2145 {
2146 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2147 }
2148
2149 /**
2150 * @brief Disable TX_EMPTY interrupt.
2151 *
2152 * Register|BitsName
2153 * ---------------|---------------
2154 * INT_MASK | TX_EMPTY
2155 *
2156 * @param I2Cx I2C instance.
2157 * @retval None.
2158 */
2159 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
2160 {
2161 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY);
2162 }
2163
2164 /**
2165 * @brief Check if TX_EMPTY interrupt is enabled or disabled.
2166 *
2167 * Register|BitsName
2168 * ---------------|---------------
2169 * INT_MASK | TX_EMPTY
2170 *
2171 * @param I2Cx I2C instance.
2172 * @retval State of bit (1 or 0).
2173 */
2174 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
2175 {
2176 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_EMPTY) == (I2C_INT_MASK_MASK_TX_EMPTY));
2177 }
2178
2179 /**
2180 * @brief Enable TX_OVER interrupt.
2181 *
2182 * Register|BitsName
2183 * ---------------|---------------
2184 * INT_MASK | TX_OVER
2185 *
2186 * @param I2Cx I2C instance.
2187 * @retval None.
2188 */
2189 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
2190 {
2191 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2192 }
2193
2194 /**
2195 * @brief Disable TX_OVER interrupt.
2196 *
2197 * Register|BitsName
2198 * ---------------|---------------
2199 * INT_MASK | TX_OVER
2200 *
2201 * @param I2Cx I2C instance.
2202 * @retval None.
2203 */
2204 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
2205 {
2206 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER);
2207 }
2208
2209 /**
2210 * @brief Check if TX_OVER interrupt is enabled or disabled.
2211 *
2212 * Register|BitsName
2213 * ---------------|---------------
2214 * INT_MASK | TX_OVER
2215 *
2216 * @param I2Cx I2C instance.
2217 * @retval State of bit (1 or 0).
2218 */
2219 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
2220 {
2221 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_TX_OVER) == (I2C_INT_MASK_MASK_TX_OVER));
2222 }
2223
2224 /**
2225 * @brief Enable RX_FULL interrupt.
2226 *
2227 * Register|BitsName
2228 * ---------------|---------------
2229 * INT_MASK | RX_FULL
2230 *
2231 * @param I2Cx I2C instance.
2232 * @retval None.
2233 */
2234 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
2235 {
2236 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2237 }
2238
2239 /**
2240 * @brief Disable RX_FULL interrupt.
2241 *
2242 * Register|BitsName
2243 * ---------------|---------------
2244 * INT_MASK | RX_FULL
2245 *
2246 * @param I2Cx I2C instance.
2247 * @retval None.
2248 */
2249 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
2250 {
2251 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL);
2252 }
2253
2254 /**
2255 * @brief Check if RX_FULL interrupt is enabled or disabled.
2256 *
2257 * Register|BitsName
2258 * ---------------|---------------
2259 * INT_MASK | RX_FULL
2260 *
2261 * @param I2Cx I2C instance.
2262 * @retval None.
2263 */
2264 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
2265 {
2266 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_FULL) == (I2C_INT_MASK_MASK_RX_FULL));
2267 }
2268
2269 /**
2270 * @brief Enable RX_OVER interrupt.
2271 *
2272 * Register|BitsName
2273 * ---------------|---------------
2274 * INT_MASK | RX_OVER
2275 *
2276 * @param I2Cx I2C instance.
2277 * @retval None.
2278 */
2279 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
2280 {
2281 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2282 }
2283
2284 /**
2285 * @brief Disable RX_OVER interrupt.
2286 *
2287 * Register|BitsName
2288 * ---------------|---------------
2289 * INT_MASK | RX_OVER
2290 *
2291 * @param I2Cx I2C instance.
2292 * @retval None.
2293 */
2294 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
2295 {
2296 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER);
2297 }
2298
2299 /**
2300 * @brief Check if RX_OVER interrupt is enabled or disabled.
2301 *
2302 * Register|BitsName
2303 * ---------------|---------------
2304 * INT_MASK | RX_OVER
2305 *
2306 * @param I2Cx I2C instance.
2307 * @retval None.
2308 */
2309 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
2310 {
2311 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_OVER) == (I2C_INT_MASK_MASK_RX_OVER));
2312 }
2313
2314 /**
2315 * @brief Enable RX_UNDER interrupt.
2316 *
2317 * Register|BitsName
2318 * ---------------|---------------
2319 * INT_MASK | RX_UNDER
2320 *
2321 * @param I2Cx I2C instance.
2322 * @retval None.
2323 */
2324 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2325 {
2326 SET_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2327 }
2328
2329 /**
2330 * @brief Disable RX_UNDER interrupt.
2331 *
2332 * Register|BitsName
2333 * ---------------|---------------
2334 * INT_MASK | RX_UNDER
2335 *
2336 * @param I2Cx I2C instance.
2337 * @retval None.
2338 */
2339 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2340 {
2341 CLEAR_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER);
2342 }
2343
2344 /**
2345 * @brief Check if RX_UNDER interrupt is enabled or disabled.
2346 *
2347 * Register|BitsName
2348 * ---------------|---------------
2349 * INT_MASK | RX_UNDER
2350 *
2351 * @param I2Cx I2C instance.
2352 * @retval None.
2353 */
2354 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2355 {
2356 return (READ_BITS(I2Cx->INT_MASK, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2357 }
2358
2359 /** @} */
2360
2361 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
2362 * @{
2363 */
2364
2365 /**
2366 * @brief Get I2C interrupt flags
2367 *
2368 * Register|BitsName
2369 * ---------------|---------------
2370 * INT_STAT | MST_ON_HOLD
2371 * INT_STAT | RESTART_DET
2372 * INT_STAT | GEN_CALL
2373 * INT_STAT | START_DET
2374 * INT_STAT | STOP_DET
2375 * INT_STAT | ACTIVITY
2376 * INT_STAT | RX_DONE
2377 * INT_STAT | TX_ABRT
2378 * INT_STAT | RD_REQ
2379 * INT_STAT | TX_EMPTY
2380 * INT_STAT | TX_OVER
2381 * INT_STAT | RX_FULL
2382 * INT_STAT | RX_OVER
2383 * INT_STAT | RX_UNDER
2384 *
2385 * @param I2Cx I2C instance.
2386 * @retval Returned value can be one or combination of the following values:
2387 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2388 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2389 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2390 * @arg @ref LL_I2C_INTR_STAT_START_DET
2391 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2392 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2393 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2394 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2395 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2396 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2397 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2398 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2399 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2400 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2401 */
2402 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2403 {
2404 return (uint32_t)(READ_REG(I2Cx->INT_STAT));
2405 }
2406
2407 /**
2408 * @brief Get I2C RAW interrupt flags
2409 *
2410 * Register|BitsName
2411 * ---------------|---------------
2412 * RAW_INT_STAT | MST_ON_HOLD
2413 * RAW_INT_STAT | RESTART_DET
2414 * RAW_INT_STAT | GEN_CALL
2415 * RAW_INT_STAT | START_DET
2416 * RAW_INT_STAT | STOP_DET
2417 * RAW_INT_STAT | ACTIVITY
2418 * RAW_INT_STAT | RX_DONE
2419 * RAW_INT_STAT | TX_ABRT
2420 * RAW_INT_STAT | RD_REQ
2421 * RAW_INT_STAT | TX_EMPTY
2422 * RAW_INT_STAT | TX_OVER
2423 * RAW_INT_STAT | RX_FULL
2424 * RAW_INT_STAT | RX_OVER
2425 * RAW_INT_STAT | RX_UNDER
2426 *
2427 * @param I2Cx I2C instance.
2428 * @retval Returned value can be one or combination of the following values:
2429 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2430 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2431 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2432 * @arg @ref LL_I2C_INTR_STAT_START_DET
2433 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2434 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2435 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2436 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2437 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2438 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2439 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2440 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2441 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2442 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2443 */
2444 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2445 {
2446 return (uint32_t)(READ_REG(I2Cx->RAW_INT_STAT));
2447 }
2448
2449 /**
2450 * @brief Indicate the status of SCL_STUCK_AT_LOW flag.
2451 * @note RESET: Clear default value.
2452 * SET : When SCL_STUCK_AT_LOW interrupt is actived.
2453 *
2454 * Register|BitsName
2455 * ---------------|---------------
2456 * INT_STAT | SCL_STUCK_AT_LOW
2457 *
2458 * @param I2Cx I2C instance.
2459 * @retval State of bit (1 or 0).
2460 */
2461 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_scl_stuck_at_low(i2c_regs_t *I2Cx)
2462 {
2463 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_SCL_STUCKLOW) == (I2C_INT_STAT_RAW_SCL_STUCKLOW));
2464 }
2465
2466 /**
2467 * @brief Indicate the status of RAW_SCL_STUCK_AT_LOW flag.
2468 * @note RESET: Clear default value.
2469 * SET : When unmasked RAW_SCL_STUCK_AT_LOW interrupt is actived.
2470 *
2471 * Register|BitsName
2472 * ---------------|---------------
2473 * RAW_INT_STAT | RAW_SCL_STUCK_AT_LOW
2474 *
2475 * @param I2Cx I2C instance.
2476 * @retval State of bit (1 or 0).
2477 */
2478 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_scl_stuck_at_low(i2c_regs_t *I2Cx)
2479 {
2480 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_SCL_STUCKLOW) == (I2C_RAW_INT_STAT_SCL_STUCKLOW));
2481 }
2482
2483 #ifdef HAL_I2C_VERSION_OLD
2484 /**
2485 * @brief Indicate the status of MST_ON_HOLD flag.
2486 * @note RESET: Clear default value.
2487 * SET : When MST_ON_HOLD interrupt is actived.
2488 *
2489 * Register|BitsName
2490 * ---------------|---------------
2491 * INT_STAT | M_HOLD
2492 *
2493 * @param I2Cx I2C instance.
2494 * @retval State of bit (1 or 0).
2495 */
2496 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2497 {
2498 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_M_HOLD) == (I2C_INT_STAT_RAW_M_HOLD));
2499 }
2500
2501 /**
2502 * @brief Indicate the status of RAW_MST_ON_HOLD flag.
2503 * @note RESET: Clear default value.
2504 * SET : When unmasked MST_ON_HOLD interrupt is actived.
2505 *
2506 * Register|BitsName
2507 * ---------------|---------------
2508 * RAW_INT_STAT | M_HOLD
2509 *
2510 * @param I2Cx I2C instance.
2511 * @retval State of bit (1 or 0).
2512 */
2513 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2514 {
2515 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_M_HOLD) == (I2C_RAW_INT_STAT_M_HOLD));
2516 }
2517
2518 /**
2519 * @brief Indicate the status of RESTART_DET flag.
2520 * @note RESET: Clear default value.
2521 * SET : When masked RESTART_DET interrupt is actived.
2522 *
2523 * Register|BitsName
2524 * ---------------|---------------
2525 * INT_STAT | RESTART_DET
2526 *
2527 * @param I2Cx I2C instance.
2528 * @retval State of bit (1 or 0).
2529 */
2530 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2531 {
2532 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RESTART_DET) == (I2C_INT_STAT_RAW_RESTART_DET));
2533 }
2534
2535 /**
2536 * @brief Indicate the status of RAW_RESTART_DET flag.
2537 * @note RESET: Clear default value.
2538 * SET : When unmasked RESTART_DET interrupt is actived.
2539 *
2540 * Register|BitsName
2541 * ---------------|---------------
2542 * RAW_INT_STAT | RESTART_DET
2543 *
2544 * @param I2Cx I2C instance.
2545 * @retval State of bit (1 or 0).
2546 */
2547 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2548 {
2549 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RESTART_DET) == (I2C_RAW_INT_STAT_RESTART_DET));
2550 }
2551 #endif
2552
2553 /**
2554 * @brief Indicate the status of GEN_CALL flag.
2555 * @note RESET: Clear default value.
2556 * SET : When masked GEN_CALL interrupt is actived.
2557 *
2558 * Register|BitsName
2559 * ---------------|---------------
2560 * INT_STAT | GEN_CALL
2561 *
2562 * @param I2Cx I2C instance.
2563 * @retval State of bit (1 or 0).
2564 */
2565 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2566 {
2567 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_GEN_CALL) == (I2C_INT_STAT_RAW_GEN_CALL));
2568 }
2569
2570 /**
2571 * @brief Indicate the status of RAW_GEN_CALL flag.
2572 * @note RESET: Clear default value.
2573 * SET : When unmasked GEN_CALL interrupt is actived.
2574 *
2575 * Register|BitsName
2576 * ---------------|---------------
2577 * RAW_INT_STAT | GEN_CALL
2578 *
2579 * @param I2Cx I2C instance.
2580 * @retval State of bit (1 or 0).
2581 */
2582 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2583 {
2584 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_GEN_CALL) == (I2C_RAW_INT_STAT_GEN_CALL));
2585 }
2586
2587 /**
2588 * @brief Indicate the status of START_DET flag.
2589 * @note RESET: Clear default value.
2590 * SET : When masked START_DET interrupt is actived.
2591 *
2592 * Register|BitsName
2593 * ---------------|---------------
2594 * INT_STAT | START_DET
2595 *
2596 * @param I2Cx I2C instance.
2597 * @retval State of bit (1 or 0).
2598 */
2599 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2600 {
2601 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_START_DET) == (I2C_INT_STAT_RAW_START_DET));
2602 }
2603
2604 /**
2605 * @brief Indicate the status of RAW_START_DET flag.
2606 * @note RESET: Clear default value.
2607 * SET : When unmasked START_DET interrupt is actived.
2608 *
2609 * Register|BitsName
2610 * ---------------|---------------
2611 * RAW_INT_STAT | START_DET
2612 *
2613 * @param I2Cx I2C instance.
2614 * @retval State of bit (1 or 0).
2615 */
2616 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2617 {
2618 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_START_DET) == (I2C_RAW_INT_STAT_START_DET));
2619 }
2620
2621 /**
2622 * @brief Indicate the status of STOP_DET flag.
2623 * @note RESET: Clear default value.
2624 * SET : When masked STOP_DET interrupt is actived.
2625 *
2626 * Register|BitsName
2627 * ---------------|---------------
2628 * INT_STAT | STOP_DET
2629 *
2630 * @param I2Cx I2C instance.
2631 * @retval State of bit (1 or 0).
2632 */
2633 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2634 {
2635 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_STOP_DET) == (I2C_INT_STAT_RAW_STOP_DET));
2636 }
2637
2638 /**
2639 * @brief Indicate the status of RAW_STOP_DET flag.
2640 * @note RESET: Clear default value.
2641 * SET : When unmasked STOP_DET interrupt is actived.
2642 *
2643 * Register|BitsName
2644 * ---------------|---------------
2645 * RAW_INT_STAT | STOP_DET
2646 *
2647 * @param I2Cx I2C instance.
2648 * @retval State of bit (1 or 0).
2649 */
2650 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2651 {
2652 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_STOP_DET) == (I2C_RAW_INT_STAT_STOP_DET));
2653 }
2654
2655 /**
2656 * @brief Indicate the status of ACTIVITY flag.
2657 * @note RESET: Clear default value.
2658 * SET : When masked ACTIVITY interrupt is actived.
2659 *
2660 * Register|BitsName
2661 * ---------------|---------------
2662 * INT_STAT | ACTIVITY
2663 *
2664 * @param I2Cx I2C instance.
2665 * @retval State of bit (1 or 0).
2666 */
2667 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2668 {
2669 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_ACTIVITY) == (I2C_INT_STAT_RAW_ACTIVITY));
2670 }
2671
2672 /**
2673 * @brief Indicate the status of RAW_ACTIVITY flag.
2674 * @note RESET: Clear default value.
2675 * SET : When unmasked ACTIVITY interrupt is actived.
2676 *
2677 * Register|BitsName
2678 * ---------------|---------------
2679 * RAW_INT_STAT | ACTIVITY
2680 *
2681 * @param I2Cx I2C instance.
2682 * @retval State of bit (1 or 0).
2683 */
2684 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2685 {
2686 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_ACTIVITY) == (I2C_RAW_INT_STAT_ACTIVITY));
2687 }
2688
2689 /**
2690 * @brief Indicate the status of RX_DONE flag.
2691 * @note RESET: Clear default value.
2692 * SET : When masked RX_DONE interrupt is actived.
2693 *
2694 * Register|BitsName
2695 * ---------------|---------------
2696 * INT_STAT | RX_DONE
2697 *
2698 * @param I2Cx I2C instance.
2699 * @retval State of bit (1 or 0).
2700 */
2701 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2702 {
2703 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_DONE) == (I2C_INT_STAT_RAW_RX_DONE));
2704 }
2705
2706 /**
2707 * @brief Indicate the status of RAW_RX_DONE flag.
2708 * @note RESET: Clear default value.
2709 * SET : When unmasked RX_DONE interrupt is actived.
2710 *
2711 * Register|BitsName
2712 * ---------------|---------------
2713 * RAW_INT_STAT | RX_DONE
2714 *
2715 * @param I2Cx I2C instance.
2716 * @retval State of bit (1 or 0).
2717 */
2718 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2719 {
2720 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_DONE) == (I2C_RAW_INT_STAT_RX_DONE));
2721 }
2722
2723 /**
2724 * @brief Indicate the status of TX_ABRT flag.
2725 * @note RESET: Clear default value.
2726 * SET : When masked TX_ABRT interrupt is actived.
2727 *
2728 * Register|BitsName
2729 * ---------------|---------------
2730 * INT_STAT | TX_ABORT
2731 *
2732 * @param I2Cx I2C instance.
2733 * @retval State of bit (1 or 0).
2734 */
2735 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2736 {
2737 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_ABORT) == (I2C_INT_STAT_RAW_TX_ABORT));
2738 }
2739
2740 /**
2741 * @brief Indicate the status of RAW_TX_ABRT flag.
2742 * @note RESET: Clear default value.
2743 * SET : When unmasked TX_ABRT interrupt is actived.
2744 *
2745 * Register|BitsName
2746 * ---------------|---------------
2747 * RAW_INT_STAT | TX_ABORT
2748 *
2749 * @param I2Cx I2C instance.
2750 * @retval State of bit (1 or 0).
2751 */
2752 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2753 {
2754 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_ABORT) == (I2C_RAW_INT_STAT_TX_ABORT));
2755 }
2756
2757 /**
2758 * @brief Indicate the status of RD_REQ flag.
2759 * @note RESET: Clear default value.
2760 * SET : When masked RD_REQ interrupt is actived.
2761 *
2762 * Register|BitsName
2763 * ---------------|---------------
2764 * INT_STAT | RD_REQ
2765 *
2766 * @param I2Cx I2C instance.
2767 * @retval State of bit (1 or 0).
2768 */
2769 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2770 {
2771 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RD_REQ) == (I2C_INT_STAT_RAW_RD_REQ));
2772 }
2773
2774 /**
2775 * @brief Indicate the status of RAW_RD_REQ flag.
2776 * @note RESET: Clear default value.
2777 * SET : When unmasked RD_REQ interrupt is actived.
2778 *
2779 * Register|BitsName
2780 * ---------------|---------------
2781 * RAW_INT_STAT | RD_REQ
2782 *
2783 * @param I2Cx I2C instance.
2784 * @retval State of bit (1 or 0).
2785 */
2786 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2787 {
2788 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RD_REQ) == (I2C_RAW_INT_STAT_RD_REQ));
2789 }
2790
2791 /**
2792 * @brief Indicate the status of TX_EMPTY flag.
2793 * @note RESET: Clear default value.
2794 * SET : When masked TX_EMPTY interrupt is actived.
2795 *
2796 * Register|BitsName
2797 * ---------------|---------------
2798 * INT_STAT | TX_EMPTY
2799 *
2800 * @param I2Cx I2C instance.
2801 * @retval State of bit (1 or 0).
2802 */
2803 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2804 {
2805 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_EMPTY) == (I2C_INT_STAT_RAW_TX_EMPTY));
2806 }
2807
2808 /**
2809 * @brief Indicate the status of RAW_TX_EMPTY flag.
2810 * @note RESET: Clear default value.
2811 * SET : When unmasked TX_EMPTY interrupt is actived.
2812 *
2813 * Register|BitsName
2814 * ---------------|---------------
2815 * RAW_INT_STAT | TX_EMPTY
2816 *
2817 * @param I2Cx I2C instance.
2818 * @retval State of bit (1 or 0).
2819 */
2820 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2821 {
2822 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_EMPTY) == (I2C_RAW_INT_STAT_TX_EMPTY));
2823 }
2824
2825 /**
2826 * @brief Indicate the status of TX_OVER flag.
2827 * @note RESET: Clear default value.
2828 * SET : When masked TX_OVER interrupt is actived.
2829 *
2830 * Register|BitsName
2831 * ---------------|---------------
2832 * INT_STAT | TX_OVER
2833 *
2834 * @param I2Cx I2C instance.
2835 * @retval State of bit (1 or 0).
2836 */
2837 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2838 {
2839 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_TX_OVER) == (I2C_INT_STAT_RAW_TX_OVER));
2840 }
2841
2842 /**
2843 * @brief Indicate the status of RAW_TX_OVER flag.
2844 * @note RESET: Clear default value.
2845 * SET : When unmasked TX_OVER interrupt is actived.
2846 *
2847 * Register|BitsName
2848 * ---------------|---------------
2849 * RAW_INT_STAT | TX_OVER
2850 *
2851 * @param I2Cx I2C instance.
2852 * @retval State of bit (1 or 0).
2853 */
2854 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2855 {
2856 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_TX_OVER) == (I2C_RAW_INT_STAT_TX_OVER));
2857 }
2858
2859 /**
2860 * @brief Indicate the status of RX_FULL flag.
2861 * @note RESET: Clear default value.
2862 * SET : When masked RX_FULL interrupt is actived.
2863 *
2864 * Register|BitsName
2865 * ---------------|---------------
2866 * INT_STAT | RX_FULL
2867 *
2868 * @param I2Cx I2C instance.
2869 * @retval State of bit (1 or 0).
2870 */
2871 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
2872 {
2873 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_FULL) == (I2C_INT_STAT_RAW_RX_FULL));
2874 }
2875
2876 /**
2877 * @brief Indicate the status of RAW_RX_FULL flag.
2878 * @note RESET: Clear default value.
2879 * SET : When unmasked RX_FULL interrupt is actived.
2880 *
2881 * Register|BitsName
2882 * ---------------|---------------
2883 * RAW_INT_STAT | RX_FULL
2884 *
2885 * @param I2Cx I2C instance.
2886 * @retval State of bit (1 or 0).
2887 */
2888 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
2889 {
2890 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_FULL) == (I2C_RAW_INT_STAT_RX_FULL));
2891 }
2892
2893 /**
2894 * @brief Indicate the status of RX_OVER flag.
2895 * @note RESET: Clear default value.
2896 * SET : When masked RX_OVER interrupt is actived.
2897 *
2898 * Register|BitsName
2899 * ---------------|---------------
2900 * INT_STAT | RX_OVER
2901 *
2902 * @param I2Cx I2C instance.
2903 * @retval State of bit (1 or 0).
2904 */
2905 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
2906 {
2907 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_STAT_RAW_RX_OVER) == (I2C_INT_STAT_RAW_RX_OVER));
2908 }
2909
2910 /**
2911 * @brief Indicate the status of RAW_RX_OVER flag.
2912 * @note RESET: Clear default value.
2913 * SET : When unmasked RX_OVER interrupt is actived.
2914 *
2915 * Register|BitsName
2916 * ---------------|---------------
2917 * RAW_INT_STAT | RX_OVER
2918 *
2919 * @param I2Cx I2C instance.
2920 * @retval State of bit (1 or 0).
2921 */
2922 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
2923 {
2924 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_OVER) == (I2C_RAW_INT_STAT_RX_OVER));
2925 }
2926
2927 /**
2928 * @brief Indicate the status of RX_UNDER flag.
2929 * @note RESET: Clear default value.
2930 * SET : When masked RX_UNDER interrupt is actived.
2931 *
2932 * Register|BitsName
2933 * ---------------|---------------
2934 * INT_STAT | RX_UNDER
2935 *
2936 * @param I2Cx I2C instance.
2937 * @retval State of bit (1 or 0).
2938 */
2939 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
2940 {
2941 return (READ_BITS(I2Cx->INT_STAT, I2C_INT_MASK_MASK_RX_UNDER) == (I2C_INT_MASK_MASK_RX_UNDER));
2942 }
2943
2944 /**
2945 * @brief Indicate the status of RAW_RX_UNDER flag.
2946 * @note RESET: Clear default value.
2947 * SET : When unmasked RX_UNDER interrupt is actived.
2948 *
2949 * Register|BitsName
2950 * ---------------|---------------
2951 * RAW_INT_STAT | RX_UNDER
2952 *
2953 * @param I2Cx I2C instance.
2954 * @retval State of bit (1 or 0).
2955 */
2956 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
2957 {
2958 return (READ_BITS(I2Cx->RAW_INT_STAT, I2C_RAW_INT_STAT_RX_UNDER) == (I2C_RAW_INT_STAT_RX_UNDER));
2959 }
2960
2961 /**
2962 * @brief Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
2963 *
2964 * Register|BitsName
2965 * ---------------|---------------
2966 * CLR_INT | CLR_INTR
2967 *
2968 * @param I2Cx I2C instance.
2969 * @retval None.
2970 */
2971 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
2972 {
2973 __IO uint32_t tmpreg;
2974 tmpreg = READ_REG(I2Cx->CLR_INT);
2975 (void) tmpreg;
2976 }
2977
2978 /**
2979 * @brief Clear scl stuck interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
2980 *
2981 * Register|BitsName
2982 * ---------------|---------------
2983 * CLR_INT | CLR_INTR
2984 *
2985 * @param I2Cx I2C instance.
2986 * @retval None.
2987 */
2988 __STATIC_INLINE void ll_i2c_clear_flag_scl_stuck_det(i2c_regs_t *I2Cx)
2989 {
2990 __IO uint32_t tmpreg;
2991 tmpreg = READ_REG(I2Cx->CLR_SCL_STUCK_DET);
2992 (void) tmpreg;
2993 }
2994
2995 /**
2996 * @brief Clear GEN_CALL flag.
2997 *
2998 * Register|BitsName
2999 * ---------------|---------------
3000 * CLR_GEN_CALL | CLR_GEN_CALL
3001 *
3002 * @param I2Cx I2C instance.
3003 * @retval None.
3004 */
3005 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
3006 {
3007 __IO uint32_t tmpreg;
3008 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
3009 (void) tmpreg;
3010 }
3011
3012 /**
3013 * @brief Clear START_DET flag.
3014 *
3015 * Register|BitsName
3016 * ---------------|---------------
3017 * CLR_START_DET | CLR_START_DET
3018 *
3019 * @param I2Cx I2C instance.
3020 * @retval None.
3021 */
3022 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
3023 {
3024 __IO uint32_t tmpreg;
3025 tmpreg = READ_REG(I2Cx->CLR_START_DET);
3026 (void) tmpreg;
3027 }
3028
3029 /**
3030 * @brief Clear STOP_DET flag.
3031 *
3032 * Register|BitsName
3033 * ---------------|---------------
3034 * CLR_STOP_DET | CLR_STOP_DET
3035 *
3036 * @param I2Cx I2C instance.
3037 * @retval None.
3038 */
3039 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
3040 {
3041 __IO uint32_t tmpreg;
3042 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
3043 (void) tmpreg;
3044 }
3045
3046 /**
3047 * @brief Clear ACTIVITY flag.
3048 *
3049 * Register|BitsName
3050 * ---------------|---------------
3051 * CLR_ACTIVITY | CLR_ACTIVITY
3052 *
3053 * @param I2Cx I2C instance.
3054 * @retval None.
3055 */
3056 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
3057 {
3058 __IO uint32_t tmpreg;
3059 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
3060 (void) tmpreg;
3061 }
3062
3063 /**
3064 * @brief Clear RX_DONE flag.
3065 *
3066 * Register|BitsName
3067 * ---------------|---------------
3068 * CLR_RX_DONE | CLR_RX_DONE
3069 *
3070 * @param I2Cx I2C instance.
3071 * @retval None.
3072 */
3073 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
3074 {
3075 __IO uint32_t tmpreg;
3076 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
3077 (void) tmpreg;
3078 }
3079
3080 /**
3081 * @brief Clear TX_ABRT flag.
3082 *
3083 * Register|BitsName
3084 * ---------------|---------------
3085 * CLR_TX_ABORT | CLR_TX_ABRT
3086 *
3087 * @param I2Cx I2C instance.
3088 * @retval None.
3089 */
3090 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
3091 {
3092 __IO uint32_t tmpreg;
3093 tmpreg = READ_REG(I2Cx->CLR_TX_ABORT);
3094 (void) tmpreg;
3095 }
3096
3097 /**
3098 * @brief Clear RD_REQ flag.
3099 *
3100 * Register|BitsName
3101 * ---------------|---------------
3102 * CLR_RD_REQ | CLR_RD_REQ
3103 *
3104 * @param I2Cx I2C instance.
3105 * @retval None.
3106 */
3107 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
3108 {
3109 __IO uint32_t tmpreg;
3110 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
3111 (void) tmpreg;
3112 }
3113
3114 /**
3115 * @brief Clear TX_OVER flag.
3116 *
3117 * Register|BitsName
3118 * ---------------|---------------
3119 * CLR_TX_OVER | CLR_TX_OVER
3120 *
3121 * @param I2Cx I2C instance.
3122 * @retval None.
3123 */
3124 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
3125 {
3126 __IO uint32_t tmpreg;
3127 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
3128 (void) tmpreg;
3129 }
3130
3131 /**
3132 * @brief Clear RX_OVER flag.
3133 *
3134 * Register|BitsName
3135 * ---------------|---------------
3136 * CLR_RX_OVER | CLR_RX_OVER
3137 *
3138 * @param I2Cx I2C instance.
3139 * @retval None.
3140 */
3141 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
3142 {
3143 __IO uint32_t tmpreg;
3144 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
3145 (void) tmpreg;
3146 }
3147
3148 /**
3149 * @brief Clear RX_UNDER flag.
3150 *
3151 * Register|BitsName
3152 * ---------------|---------------
3153 * CLR_RX_UNDER | CLR_RX_UNDER
3154 *
3155 * @param I2Cx I2C instance.
3156 * @retval None.
3157 */
3158 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
3159 {
3160 __IO uint32_t tmpreg;
3161 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
3162 (void) tmpreg;
3163 }
3164
3165 /**
3166 * @brief Indicate the status of IC_STATUS SDA stuck at low is not recovered flag.
3167 * @note RESET: stuck at low is recovered.
3168 * SET : stuck at low is not recovered.
3169 *
3170 * Register|BitsName
3171 * ---------------|---------------
3172 * STAT | SDA_STUCK_RCVR
3173 *
3174 * @param I2Cx I2C instance.
3175 * @retval State of bit (1 or 0).
3176 */
3177 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_sda_stuck_not_recovered(i2c_regs_t *I2Cx)
3178 {
3179 return (READ_BITS(I2Cx->STAT, I2C_STAT_SDA_STUCK_RCVR) == (I2C_STAT_SDA_STUCK_RCVR));
3180 }
3181
3182 /**
3183 * @brief Indicate the status of IC_STATUS Slave FSM Activity Status flag.
3184 * @note RESET: Slave FSM is in IDLE state.
3185 * SET : When Slave FSM is not in IDLE state.
3186 *
3187 * Register|BitsName
3188 * ---------------|---------------
3189 * STAT | S_ACTIVITY
3190 *
3191 * @param I2Cx I2C instance.
3192 * @retval State of bit (1 or 0).
3193 */
3194 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
3195 {
3196 return (READ_BITS(I2Cx->STAT, I2C_STAT_S_ACTIVITY) == (I2C_STAT_S_ACTIVITY));
3197 }
3198
3199 /**
3200 * @brief Indicate the status of IC_STATUS Master FSM Activity Status flag.
3201 * @note RESET: Master FSM is in IDLE state.
3202 * SET : When Master FSM is not in IDLE state.
3203 *
3204 * Register|BitsName
3205 * ---------------|---------------
3206 * STAT | M_ACTIVITY
3207 *
3208 * @param I2Cx I2C instance.
3209 * @retval State of bit (1 or 0).
3210 */
3211 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
3212 {
3213 return (READ_BITS(I2Cx->STAT, I2C_STAT_M_ACTIVITY) == (I2C_STAT_M_ACTIVITY));
3214 }
3215
3216 /**
3217 * @brief Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
3218 * @note RESET: Receive FIFO is not full.
3219 * SET : When Receive FIFO is full.
3220 *
3221 * Register|BitsName
3222 * ---------------|---------------
3223 * STAT | RX_FIFO_CF
3224 *
3225 * @param I2Cx I2C instance.
3226 * @retval State of bit (1 or 0).
3227 */
3228 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
3229 {
3230 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_CF) == (I2C_STAT_RX_FIFO_CF));
3231 }
3232
3233 /**
3234 * @brief Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
3235 * @note RESET: Receive FIFO is empty.
3236 * SET : When Receive FIFO is not empty.
3237 *
3238 * Register|BitsName
3239 * ---------------|---------------
3240 * STAT | RX_FIFO_NE
3241 *
3242 * @param I2Cx I2C instance.
3243 * @retval State of bit (1 or 0).
3244 */
3245 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
3246 {
3247 return (READ_BITS(I2Cx->STAT, I2C_STAT_RX_FIFO_NE) == (I2C_STAT_RX_FIFO_NE));
3248 }
3249
3250 /**
3251 * @brief Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
3252 * @note RESET: Transmit FIFO is not empty.
3253 * SET : When Transmit FIFO is empty.
3254 *
3255 * Register|BitsName
3256 * ---------------|---------------
3257 * STAT | TX_FIFO_CE
3258 *
3259 * @param I2Cx I2C instance.
3260 * @retval State of bit (1 or 0).
3261 */
3262 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
3263 {
3264 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_CE) == (I2C_STAT_TX_FIFO_CE));
3265 }
3266
3267 /**
3268 * @brief Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
3269 * @note RESET: Transmit FIFO is full.
3270 * SET : When Transmit FIFO is not full.
3271 *
3272 * Register|BitsName
3273 * ---------------|---------------
3274 * STAT | TX_FIFO_NF
3275 *
3276 * @param I2Cx I2C instance.
3277 * @retval State of bit (1 or 0).
3278 */
3279 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
3280 {
3281 return (READ_BITS(I2Cx->STAT, I2C_STAT_TX_FIFO_NF) == (I2C_STAT_TX_FIFO_NF));
3282 }
3283
3284 /**
3285 * @brief Indicate the status of IC_STATUS ACTIVITY flag.
3286 * @note RESET: I2C is idle.
3287 * SET : When I2C is active.
3288 *
3289 * Register|BitsName
3290 * ---------------|---------------
3291 * STAT | ACTIVITY
3292 *
3293 * @param I2Cx I2C instance.
3294 * @retval State of bit (1 or 0).
3295 */
3296 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
3297 {
3298 return (READ_BITS(I2Cx->STAT, I2C_STAT_ACTIVITY) == (I2C_STAT_ACTIVITY));
3299 }
3300
3301 /**
3302 * @brief Indicate the status of Slave Received Data Lost flag.
3303 * @note RESET: Slave RX Data is not lost.
3304 * SET : Slave RX Data is lost.
3305 *
3306 * Register|BitsName
3307 * ---------------|---------------
3308 * EN_STAT | S_RX_DATA_LOST
3309 *
3310 * @param I2Cx I2C instance.
3311 * @retval State of bit (1 or 0).
3312 */
3313 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
3314 {
3315 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_RX_DATA_LOST) == (I2C_EN_STAT_S_RX_DATA_LOST));
3316 }
3317
3318 /**
3319 * @brief Indicate the status of Slave Disabled While Busy flag.
3320 * @note RESET: Slave is disabled when it is idle.
3321 * SET : Slave is disabled when it is active.
3322 *
3323 * Register|BitsName
3324 * ---------------|---------------
3325 * EN_STAT | S_DIS_BUSY
3326 *
3327 * @param I2Cx I2C instance.
3328 * @retval State of bit (1 or 0).
3329 */
3330 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
3331 {
3332 return (READ_BITS(I2Cx->EN_STAT, I2C_EN_STAT_S_DIS_BUSY) == (I2C_EN_STAT_S_DIS_BUSY));
3333 }
3334 /** @} */
3335
3336 /** @defgroup I2C_LL_EF_DMA_Management DMA_Management
3337 * @{
3338 */
3339
3340 /**
3341 * @brief Enable DMA transmission requests.
3342 *
3343 * Register|BitsName
3344 * ---------------|---------------
3345 * DMA_CTRL | TX_EN
3346 *
3347 * @retval Value range between 0 ~ 0x8.
3348 * @retval None.
3349 */
3350 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
3351 {
3352 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3353 }
3354
3355 /**
3356 * @brief Disable DMA transmission requests.
3357 *
3358 * Register|BitsName
3359 * ---------------|---------------
3360 * DMA_CTRL | TX_EN
3361 *
3362 * @param I2Cx I2C instance.
3363 * @retval None.
3364 */
3365 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
3366 {
3367 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN);
3368 }
3369
3370 /**
3371 * @brief Check if DMA transmission requests are enabled or disabled.
3372 *
3373 * Register|BitsName
3374 * ---------------|---------------
3375 * DMA_CTRL | TX_EN
3376 *
3377 * @param I2Cx I2C instance.
3378 * @retval State of bit (1 or 0).
3379 */
3380 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
3381 {
3382 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_TX_EN) == (I2C_DMA_CTRL_TX_EN));
3383 }
3384
3385 /**
3386 * @brief Enable DMA reception requests.
3387 *
3388 * Register|BitsName
3389 * ---------------|---------------
3390 * DMA_CTRL | RX_EN
3391 *
3392 * @param I2Cx I2C instance.
3393 * @retval None.
3394 */
3395 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3396 {
3397 SET_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3398 }
3399
3400 /**
3401 * @brief Disable DMA reception requests.
3402 *
3403 * Register|BitsName
3404 * ---------------|---------------
3405 * DMA_CTRL | RX_EN
3406 *
3407 * @param I2Cx I2C instance.
3408 * @retval None.
3409 */
3410 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3411 {
3412 CLEAR_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN);
3413 }
3414
3415 /**
3416 * @brief Check if DMA reception requests are enabled or disabled.
3417 *
3418 * Register|BitsName
3419 * ---------------|---------------
3420 * DMA_CTRL | RX_EN
3421 *
3422 * @param I2Cx I2C instance.
3423 * @retval State of bit (1 or 0).
3424 */
3425 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3426 {
3427 return (READ_BITS(I2Cx->DMA_CTRL, I2C_DMA_CTRL_RX_EN) == (I2C_DMA_CTRL_RX_EN));
3428 }
3429
3430 /**
3431 * @brief Set level of TX FIFO that requests a DMA transmit.
3432 * @note TX data level should equal to the watermark level, that is, the dma_tx_req
3433 * signal is generated when the number of valid data entries in the transmit
3434 * FIFO is equal to or below this field value, and TDMAE = 1.
3435 *
3436 * Register|BitsName
3437 * ---------------|---------------
3438 * DMA_TX_LEVEL | LEVEL
3439 *
3440 * @param I2Cx I2C instance
3441 * @param level This parameter should range between 0x0 and 0x8.
3442 * @retval None.
3443 */
3444 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3445 {
3446 WRITE_REG(I2Cx->DMA_TX_LEVEL, level);
3447 }
3448
3449 /**
3450 * @brief Get level of TX FIFO that request a DMA transmit.
3451 *
3452 * Register|BitsName
3453 * ---------------|---------------
3454 * DMA_TX_LEVEL | LEVEL
3455 *
3456 * @param I2Cx I2C instance
3457 * @retval Returned value should range between 0x0 and 0x8.
3458 */
3459 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3460 {
3461 return (uint32_t)(READ_BITS(I2Cx->DMA_TX_LEVEL, I2C_DMA_TX_LEVEL_LEVEL));
3462 }
3463
3464 /**
3465 * @brief Set level of RX FIFO that requests a DMA receive.
3466 * @note The watermark level = DMARDL + 1, that is, dma_rx_req is generated when
3467 * the number of valid data entries in the receive FIFO is equal to or
3468 * more than this field value + 1, and RDMAE = 1. For instance, when DMARDL
3469 * is 0, then dma_rx_req is asserted when 1 or more data entries are present
3470 * in the receive FIFO.
3471 *
3472 * Register|BitsName
3473 * ---------------|---------------
3474 * DMA_RX_LEVEL | LEVEL
3475 *
3476 * @param I2Cx I2C instance
3477 * @param level This parameter should range between 0x0 and 0x8.
3478 * @retval None.
3479 */
3480 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3481 {
3482 WRITE_REG(I2Cx->DMA_RX_LEVEL, level);
3483 }
3484
3485 /**
3486 * @brief Get level of RX FIFO that request a DMA receive.
3487 *
3488 * Register|BitsName
3489 * ---------------|---------------
3490 * DMA_RX_LEVEL | LEVEL
3491 *
3492 * @param I2Cx I2C instance
3493 * @retval Returned value should range between 0x0 and 0x8.
3494 */
3495 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3496 {
3497 return (uint32_t)(READ_BITS(I2Cx->DMA_RX_LEVEL, I2C_DMA_RX_LEVEL_LEVEL));
3498 }
3499
3500 /**
3501 * @brief Get the data register address used for DMA transfer
3502 *
3503 * Register|BitsName
3504 * ---------------|---------------
3505 * DATA_CMD | DAT
3506 *
3507 * @param I2Cx I2C instance
3508 * @retval Address of data register
3509 */
3510 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3511 {
3512 return ((uint32_t) & (I2Cx->DATA_CMD));
3513 }
3514
3515 /**
3516 * @brief Set scl stuck timeout time
3517 *
3518 * Register|BitsName
3519 * --------------------------------| ---------------------
3520 * SCL_STUCK_AT_LOW_TIMEOUT | SCL_STUCK_LOW_TIMEOUT
3521 *
3522 * @param I2Cx I2C instance
3523 * @param timeout timeout time
3524 * @retval Address of data register
3525 */
3526 __STATIC_INLINE void ll_i2c_set_scl_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
3527 {
3528 WRITE_REG(I2Cx->SCL_STUCK_TIMEOUT, timeout);
3529 }
3530
3531 /**
3532 * @brief Set sda stuck timeout time
3533 *
3534 * Register|BitsName
3535 * --------------------------------| ---------------------
3536 * SDA_STUCK_AT_LOW_TIMEOUT | SDA_STUCK_LOW_TIMEOUT
3537 *
3538 * @param I2Cx I2C instance
3539 * @param timeout timeout time
3540 * @retval Address of data register
3541 */
3542 __STATIC_INLINE void ll_i2c_set_sda_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
3543 {
3544 WRITE_REG(I2Cx->SDA_STUCK_TIMEOUT, timeout);
3545 }
3546
3547 /** @} */
3548
3549 /** @defgroup I2C_LL_EF_Data_Management Data_Management
3550 * @{
3551 */
3552
3553 /**
3554 * @brief Configure the slave address for transfer (master mode).
3555 * @note The register IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3556 *
3557 * Register|BitsName
3558 * ---------------|---------------
3559 * TARGET_ADDR | TAR_ADDR
3560 *
3561 * @param I2Cx I2C instance.
3562 * @param slave_addr This parameter must be a value between 0x00 and 0x3F.
3563 * @retval None.
3564 */
3565 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3566 {
3567 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3568 }
3569
3570 /**
3571 * @brief Get the slave address programmed for transfer (master mode).
3572 *
3573 * Register|BitsName
3574 * ---------------|---------------
3575 * TARGET_ADDR | TAR_ADDR
3576 *
3577 * @param I2Cx I2C instance.
3578 * @retval Value between 0x0 and0x3F
3579 */
3580 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3581 {
3582 return (uint32_t)(READ_BITS(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET) >> I2C_TARGET_ADDR_TARGET_POS);
3583 }
3584
3585 /**
3586 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
3587 * @note The register IC_CON and IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3588 *
3589 * Register|BitsName
3590 * ---------------|---------------
3591 * TARGET_ADDR | TAR_ADDR
3592 * CTRL | CON_10BITADDR_MST
3593 *
3594 * @param I2Cx I2C instance.
3595 * @param slave_addr Specifies the slave address to be programmed.
3596 * @param slave_addr_size This parameter can be one of the following values:
3597 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
3598 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
3599 * @note SlaveAddrSize in IC_CON register can only be programmed when the I2C is disabled (IC_ENABLE = 0).
3600 * @retval None.
3601 */
3602 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3603 {
3604 MODIFY_REG(I2Cx->TARGET_ADDR, I2C_TARGET_ADDR_TARGET, slave_addr << I2C_TARGET_ADDR_TARGET_POS);
3605 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3606 }
3607
3608 /**
3609 * @brief Read Receive Data register.
3610 *
3611 * Register|BitsName
3612 * ---------------|---------------
3613 * DATA_CMD | DATA
3614 *
3615 * @param I2Cx I2C instance.
3616 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3617 */
3618 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3619 {
3620 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DATA));
3621 }
3622
3623 /**
3624 * @brief Write in Transmit Data Register .
3625 *
3626 * Register|BitsName
3627 * ---------------|---------------
3628 * DATA_CMD | STOP
3629 * DATA_CMD | CMD
3630 * DATA_CMD | DATA
3631 *
3632 * @param I2Cx I2C instance.
3633 * @param data Value range between 0x00 and 0xFF.
3634 * @param cmd This parameter can be one of the following values:
3635 * @arg @ref LL_I2C_CMD_SLV_NONE
3636 * @arg @ref LL_I2C_CMD_MST_WRITE
3637 * @arg @ref LL_I2C_CMD_MST_READ
3638 * @arg @ref LL_I2C_CMD_MST_GEN_STOP
3639 * @arg @ref LL_I2C_CMD_MST_GEN_RESTART
3640 * @retval None.
3641 */
3642 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3643 {
3644 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3645 }
3646
3647 /** @} */
3648
3649 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
3650 * @{
3651 */
3652
3653 /**
3654 * @brief De-initialize I2C registers (Registers restored to their default values).
3655 * @param I2Cx I2C instance
3656 * @retval None
3657 */
3658 void ll_i2c_deinit(i2c_regs_t *I2Cx);
3659
3660 /**
3661 * @brief Initialize I2C registers according to the specified
3662 * parameters in p_i2c_init.
3663 * @param I2Cx I2C instance
3664 * @param p_i2c_init Pointer to a ll_i2c_init_t structure that contains the configuration
3665 * information for the specified I2C peripheral.
3666 * @retval None
3667
3668 */
3669 void ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3670
3671 /**
3672 * @brief Set each field of a @ref ll_i2c_init_t type structure to default value.
3673 * @param p_i2c_init Pointer to a @ref ll_i2c_init_t structure
3674 * whose fields will be set to default values.
3675 * @retval None
3676 */
3677 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3678
3679 /** @} */
3680
3681 /** @} */
3682
3683 #endif /* I2C0 || I2C1 */
3684
3685 #ifdef __cplusplus
3686 }
3687 #endif
3688
3689 #endif /* ___LL_I2C_H__ */
3690
3691 /** @} */
3692
3693 /** @} */
3694
3695 /** @} */
ll_i2c_is_active_flag_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
Indicate the status of TX_OVER flag.
Definition: ll_i2c.h:2837
ll_i2c_enable
__STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
Enable I2C peripheral (ENABLE = 1).
Definition: ll_i2c.h:384
_ll_i2c_init::own_addr_size
uint32_t own_addr_size
Definition: ll_i2c.h:85
ll_i2c_enable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Enable Slave issues STOP_DET interrupt only if addressed function.
Definition: ll_i2c.h:585
ll_i2c_is_active_flag_status_tfnf
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
Definition: ll_i2c.h:3279
ll_i2c_is_enabled_transfer_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: ll_i2c.h:1488
ll_i2c_is_active_flag_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RX_DONE flag.
Definition: ll_i2c.h:2701
ll_i2c_get_clock_low_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for fast speed.
Definition: ll_i2c.h:884
ll_i2c_enable_sda_stuck_recovery
__STATIC_INLINE void ll_i2c_enable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master initates the SDA stuck at low recovery mechanism.
Definition: ll_i2c.h:1429
ll_i2c_is_enabled_it_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
Check if STOP_DET interrupt is enabled or disabled.
Definition: ll_i2c.h:1949
ll_i2c_is_enabled_it_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
Definition: ll_i2c.h:1768
ll_i2c_set_speed_mode
__STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
Set I2C Speed mode.
Definition: ll_i2c.h:1037
ll_i2c_enable_it_tx_over
__STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
Enable TX_OVER interrupt.
Definition: ll_i2c.h:2189
ll_i2c_disable_it_tx_over
__STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
Disable TX_OVER interrupt.
Definition: ll_i2c.h:2204
ll_i2c_is_active_flag_status_master_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Master FSM Activity Status flag.
Definition: ll_i2c.h:3211
ll_i2c_get_rx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of RX FIFO that triggers an RDA interrupt.
Definition: ll_i2c.h:1385
ll_i2c_get_abort_source
__STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
Get the transmit abort source.
Definition: ll_i2c.h:1541
ll_i2c_is_active_flag_raw_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of RAW_MST_ON_HOLD flag.
Definition: ll_i2c.h:2513
ll_i2c_is_active_flag_status_rfne
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
Definition: ll_i2c.h:3245
ll_i2c_clear_flag_rx_under
__STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
Clear RX_UNDER flag.
Definition: ll_i2c.h:3158
ll_i2c_is_enabled_sda_stuck_recovery
__STATIC_INLINE uint32_t ll_i2c_is_enabled_sda_stuck_recovery(i2c_regs_t *I2Cx)
the SDA stuck at low recovery mechanism is enabled or disabled.
Definition: ll_i2c.h:1458
ll_i2c_dma_get_register_address
__STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
Get the data register address used for DMA transfer.
Definition: ll_i2c.h:3510
ll_i2c_clear_flag_tx_over
__STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
Clear TX_OVER flag.
Definition: ll_i2c.h:3124
ll_i2c_disable_it_tx_empty
__STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
Disable TX_EMPTY interrupt.
Definition: ll_i2c.h:2159
ll_i2c_is_active_flag_raw_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_ABRT flag.
Definition: ll_i2c.h:2752
ll_i2c_enable_dma_req_tx
__STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
Enable DMA transmission requests.
Definition: ll_i2c.h:3350
ll_i2c_is_enabled_it_start_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
Check if START_DET received interrupt is enabled or disabled.
Definition: ll_i2c.h:1904
ll_i2c_is_enabled_stop_det_if_addressed
__STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
Definition: ll_i2c.h:696
ll_i2c_enable_it_start_det
__STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
Enable START_DET received interrupt.
Definition: ll_i2c.h:1874
ll_i2c_get_data_setup_time
__STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
Get the SDA setup time when operating as a slave transmitter.
Definition: ll_i2c.h:1189
ll_i2c_is_active_flag_raw_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
Indicate the status of RAW_RD_REQ flag.
Definition: ll_i2c.h:2786
ll_i2c_is_active_flag_status_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS ACTIVITY flag.
Definition: ll_i2c.h:3296
ll_i2c_enable_transfer_abort
__STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: ll_i2c.h:1473
ll_i2c_is_enabled_bus_clear_feature
__STATIC_INLINE uint32_t ll_i2c_is_enabled_bus_clear_feature(i2c_regs_t *I2Cx)
check bus clear feature is enabled function.
Definition: ll_i2c.h:681
ll_i2c_get_spike_len_fs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
Get the spike len in fast speed mode.
Definition: ll_i2c.h:982
ll_i2c_is_active_flag_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RX_UNDER flag.
Definition: ll_i2c.h:2939
ll_i2c_set_tx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of entries (or below) that trigger the TX_EMPTY interrupt.
Definition: ll_i2c.h:1239
ll_i2c_is_active_flag_raw_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
Indicate the status of RAW_ACTIVITY flag.
Definition: ll_i2c.h:2684
ll_i2c_get_clock_low_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for high speed.
Definition: ll_i2c.h:949
ll_i2c_is_active_flag_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
Indicate the status of STOP_DET flag.
Definition: ll_i2c.h:2633
ll_i2c_is_enabled_master_mode
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
Check if I2C master mode is enabled or disabled.
Definition: ll_i2c.h:465
ll_i2c_disable_dma_req_tx
__STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
Disable DMA transmission requests.
Definition: ll_i2c.h:3365
ll_i2c_disable_it_rx_over
__STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
Disable RX_OVER interrupt.
Definition: ll_i2c.h:2294
_ll_i2c_init::speed
uint32_t speed
Definition: ll_i2c.h:78
ll_i2c_enable_it_read_req
__STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
Enable RD_REQ interrupt.
Definition: ll_i2c.h:2099
ll_i2c_is_active_flag_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RX_OVER flag.
Definition: ll_i2c.h:2905
ll_i2c_is_enabled_it_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
Check if RX_UNDER interrupt is enabled or disabled.
Definition: ll_i2c.h:2354
ll_i2c_enable_it_stop_det
__STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
Enable STOP_DET interrupt.
Definition: ll_i2c.h:1919
ll_i2c_disable_dma_req_rx
__STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
Disable DMA reception requests.
Definition: ll_i2c.h:3410
ll_i2c_set_rx_fifo_threshold
__STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
Set threshold of RX FIFO that triggers an RDA interrupt.
Definition: ll_i2c.h:1337
ll_i2c_is_active_flag_status_tfe
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
Definition: ll_i2c.h:3262
ll_i2c_set_sda_stuck_at_low_timeout
__STATIC_INLINE void ll_i2c_set_sda_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Set sda stuck timeout time.
Definition: ll_i2c.h:3542
ll_i2c_is_active_flag_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RESTART_DET flag.
Definition: ll_i2c.h:2530
ll_i2c_overflow_if_rx_full
__STATIC_INLINE void ll_i2c_overflow_if_rx_full(i2c_regs_t *I2Cx)
overflow when the RX FIFO if full function.
Definition: ll_i2c.h:633
ll_i2c_enable_it_scl_stuck_at_low
__STATIC_INLINE void ll_i2c_enable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Enable SCL_STUCK_AT_LOW interrupt.
Definition: ll_i2c.h:1694
ll_i2c_set_dma_rx_data_level
__STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of RX FIFO that requests a DMA receive.
Definition: ll_i2c.h:3480
ll_i2c_disable_it_restart_det
__STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
Disable RESTART_DET interrupt.
Definition: ll_i2c.h:1798
ll_i2c_is_active_flag_master_on_hold
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
Indicate the status of MST_ON_HOLD flag.
Definition: ll_i2c.h:2496
ll_i2c_disable_it
__STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
Disable specified interrupts.
Definition: ll_i2c.h:1640
ll_i2c_disable_master_restart
__STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
Disable Master Restart.
Definition: ll_i2c.h:550
ll_i2c_get_clock_high_period_hs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for high speed.
Definition: ll_i2c.h:917
ll_i2c_disable_sda_stuck_recovery
__STATIC_INLINE void ll_i2c_disable_sda_stuck_recovery(i2c_regs_t *I2Cx)
Master disabled the SDA stuck at low recovery mechanism.
Definition: ll_i2c.h:1443
ll_i2c_clear_flag_intr
__STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: ll_i2c.h:2971
ll_i2c_is_enabled_it_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
Check if the RESTART_DET Interrupt is enabled or disabled.
Definition: ll_i2c.h:1813
ll_i2c_get_tx_flush_count
__STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
Definition: ll_i2c.h:1556
ll_i2c_get_tx_fifo_threshold
__STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
Get threshold of TX FIFO that triggers an THRE interrupt.
Definition: ll_i2c.h:1287
ll_i2c_disable_it_stop_det
__STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
Disable STOP_DET interrupt.
Definition: ll_i2c.h:1934
ll_i2c_is_enabled_it_activity
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
Check if ACTIVITY interrupt is enabled or disabled.
Definition: ll_i2c.h:1994
ll_i2c_disable_it_scl_stuck_at_low
__STATIC_INLINE void ll_i2c_disable_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Disable SCL_STUCK_AT_LOW interrupt.
Definition: ll_i2c.h:1708
ll_i2c_get_data_rx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
Get the required receive SDA hold time in units of ic_clk period.
Definition: ll_i2c.h:1155
ll_i2c_get_clock_high_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for standard speed.
Definition: ll_i2c.h:788
ll_i2c_disbale_it_rx_full
__STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
Disable RX_FULL interrupt.
Definition: ll_i2c.h:2249
ll_i2c_get_slave_address
__STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
Get the slave address programmed for transfer (master mode).
Definition: ll_i2c.h:3580
ll_i2c_is_active_flag_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RX_FULL flag.
Definition: ll_i2c.h:2871
ll_i2c_clear_flag_scl_stuck_det
__STATIC_INLINE void ll_i2c_clear_flag_scl_stuck_det(i2c_regs_t *I2Cx)
Clear scl stuck interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register.
Definition: ll_i2c.h:2988
ll_i2c_enable_it_master_on_hold
__STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
Enable MASTER_ON_HOLD interrupt.
Definition: ll_i2c.h:1738
ll_i2c_is_enabled_it_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
Check if TX_ABRT interrupt is enabled or disabled.
Definition: ll_i2c.h:2084
ll_i2c_set_own_address
__STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
Set the Own Address.
Definition: ll_i2c.h:755
ll_i2c_init
void ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init)
Initialize I2C registers according to the specified parameters in p_i2c_init.
ll_i2c_clear_flag_start_det
__STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
Clear START_DET flag.
Definition: ll_i2c.h:3022
ll_i2c_set_master_addressing_mode
__STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
Configure the Master to transfers in 7-bit or 10-bit addressing mode.
Definition: ll_i2c.h:715
ll_i2c_disable_it_gen_call
__STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
Disable GEN_CALL interrupt.
Definition: ll_i2c.h:1844
ll_i2c_clear_flag_stop_det
__STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
Clear STOP_DET flag.
Definition: ll_i2c.h:3039
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_i2c_disable_it_start_det
__STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
Disable START_DET received interrupt.
Definition: ll_i2c.h:1889
ll_i2c_is_active_flag_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
Indicate the status of ACTIVITY flag.
Definition: ll_i2c.h:2667
ll_i2c_hold_bus_if_rx_full
__STATIC_INLINE void ll_i2c_hold_bus_if_rx_full(i2c_regs_t *I2Cx)
Hold bus when the RX FIFO if full function.
Definition: ll_i2c.h:617
ll_i2c_disable_master_mode
__STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
Disable I2C master mode and enable slave mode.
Definition: ll_i2c.h:449
ll_i2c_is_active_flag_raw_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
Indicate the status of RAW_GEN_CALL flag.
Definition: ll_i2c.h:2582
ll_i2c_get_master_addressing_mode
__STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
Get the Master addressing mode.
Definition: ll_i2c.h:733
ll_i2c_clear_flag_tx_abort
__STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
Clear TX_ABRT flag.
Definition: ll_i2c.h:3090
ll_i2c_disable_it_activity
__STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
Disable ACTIVITY interrupt.
Definition: ll_i2c.h:1979
ll_i2c_is_active_flag_slave_rx_data_lost
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
Indicate the status of Slave Received Data Lost flag.
Definition: ll_i2c.h:3313
_ll_i2c_init
LL I2C init Structure definition.
Definition: ll_i2c.h:77
ll_i2c_is_active_flag_tx_abort
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
Indicate the status of TX_ABRT flag.
Definition: ll_i2c.h:2735
ll_i2c_disable_it_read_req
__STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
Disable RD_REQ interrupt.
Definition: ll_i2c.h:2114
ll_i2c_is_enabled_general_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
Check if General Call is enabled or disabled(slave mode).
Definition: ll_i2c.h:512
ll_i2c_deinit
void ll_i2c_deinit(i2c_regs_t *I2Cx)
De-initialize I2C registers (Registers restored to their default values).
ll_i2c_get_dma_rx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
Get level of RX FIFO that request a DMA receive.
Definition: ll_i2c.h:3495
ll_i2c_enable_it
__STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
Enable specified interrupts.
Definition: ll_i2c.h:1601
ll_i2c_is_active_flag_slave_dis_whl_busy
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
Indicate the status of Slave Disabled While Busy flag.
Definition: ll_i2c.h:3330
ll_i2c_is_enabled_dma_req_tx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
Check if DMA transmission requests are enabled or disabled.
Definition: ll_i2c.h:3380
ll_i2c_set_scl_stuck_at_low_timeout
__STATIC_INLINE void ll_i2c_set_scl_stuck_at_low_timeout(i2c_regs_t *I2Cx, uint32_t timeout)
Set scl stuck timeout time.
Definition: ll_i2c.h:3526
ll_i2c_clear_flag_rx_done
__STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
Clear RX_DONE flag.
Definition: ll_i2c.h:3073
ll_i2c_set_clock_low_period_ss
__STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for standard speed.
Definition: ll_i2c.h:805
ll_i2c_clear_flag_rx_over
__STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
Clear RX_OVER flag.
Definition: ll_i2c.h:3141
ll_i2c_is_enabled_dma_req_rx
__STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
Check if DMA reception requests are enabled or disabled.
Definition: ll_i2c.h:3425
ll_i2c_is_active_flag_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_scl_stuck_at_low(i2c_regs_t *I2Cx)
Indicate the status of SCL_STUCK_AT_LOW flag.
Definition: ll_i2c.h:2461
ll_i2c_enable_dma_req_rx
__STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
Enable DMA reception requests.
Definition: ll_i2c.h:3395
ll_i2c_is_active_flag_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of TX_EMPTY flag.
Definition: ll_i2c.h:2803
ll_i2c_is_active_flag_raw_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_EMPTY flag.
Definition: ll_i2c.h:2820
ll_i2c_is_enabled_it_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
Check if RX_OVER interrupt is enabled or disabled.
Definition: ll_i2c.h:2309
ll_i2c_receive_data8
__STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
Read Receive Data register.
Definition: ll_i2c.h:3618
ll_i2c_struct_init
void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init)
Set each field of a ll_i2c_init_t type structure to default value.
ll_i2c_disable_general_call
__STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
Disable General Call(slave mode).
Definition: ll_i2c.h:497
ll_i2c_is_enabled_it_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
Check if TX_OVER interrupt is enabled or disabled.
Definition: ll_i2c.h:2219
ll_i2c_set_data_rx_hold_time
__STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required receive SDA hold time in units of ic_clk period.
Definition: ll_i2c.h:1140
ll_i2c_set_spike_len_hs
__STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in high speed mode.
Definition: ll_i2c.h:1000
ll_i2c_is_active_flag_raw_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_scl_stuck_at_low(i2c_regs_t *I2Cx)
Indicate the status of RAW_SCL_STUCK_AT_LOW flag.
Definition: ll_i2c.h:2478
ll_i2c_enable_it_rx_under
__STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
Enable RX_UNDER interrupt.
Definition: ll_i2c.h:2324
ll_i2c_enable_general_call
__STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
Enable General Call(slave mode).
Definition: ll_i2c.h:481
ll_i2c_is_active_flag_status_slave_activity
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Slave FSM Activity Status flag.
Definition: ll_i2c.h:3194
ll_i2c_set_dma_tx_data_level
__STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
Set level of TX FIFO that requests a DMA transmit.
Definition: ll_i2c.h:3444
ll_i2c_is_enabled_it
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
Check if the specified interrupts are enabled or disabled.
Definition: ll_i2c.h:1679
ll_i2c_get_dma_tx_data_level
__STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
Get level of TX FIFO that request a DMA transmit.
Definition: ll_i2c.h:3459
ll_i2c_is_active_flag_raw_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_DONE flag.
Definition: ll_i2c.h:2718
ll_i2c_get_high_speed_master_code
__STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: ll_i2c.h:1088
ll_i2c_set_clock_high_period_fs
__STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for fast speed.
Definition: ll_i2c.h:837
ll_i2c_enable_it_rx_over
__STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
Enable RX_OVER interrupt.
Definition: ll_i2c.h:2279
ll_i2c_enable_it_activity
__STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
Enable ACTIVITY interrupt.
Definition: ll_i2c.h:1964
ll_i2c_is_active_flag_raw_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_START_DET flag.
Definition: ll_i2c.h:2616
ll_i2c_ls_enabled_it_rx_full
__STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
Check if RX_FULL interrupt is enabled or disabled.
Definition: ll_i2c.h:2264
ll_i2c_set_clock_high_period_hs
__STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock high-period count for high speed.
Definition: ll_i2c.h:902
ll_i2c_get_data_tx_hold_time
__STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
Get the required transmit SDA hold time in units of ic_clk period.
Definition: ll_i2c.h:1122
ll_i2c_clear_flag_read_req
__STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
Clear RD_REQ flag.
Definition: ll_i2c.h:3107
ll_i2c_is_active_flag_read_req
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
Indicate the status of RD_REQ flag.
Definition: ll_i2c.h:2769
ll_i2c_get_spike_len_hs
__STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
Get the spike len in high speed mode.
Definition: ll_i2c.h:1017
ll_i2c_enable_it_rx_done
__STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
Enable RX_DONE interrupt.
Definition: ll_i2c.h:2009
ll_i2c_enable_master_restart
__STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
Enable Master Restart.
Definition: ll_i2c.h:534
ll_i2c_init_t
struct _ll_i2c_init ll_i2c_init_t
LL I2C init Structure definition.
ll_i2c_is_enabled_it_tx_empty
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
Check if TX_EMPTY interrupt is enabled or disabled.
Definition: ll_i2c.h:2174
ll_i2c_is_active_flag_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
Indicate the status of GEN_CALL flag.
Definition: ll_i2c.h:2565
ll_i2c_clear_flag_activity
__STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
Clear ACTIVITY flag.
Definition: ll_i2c.h:3056
ll_i2c_is_active_flag_status_rff
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
Definition: ll_i2c.h:3228
ll_i2c_is_active_flag_status_sda_stuck_not_recovered
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_sda_stuck_not_recovered(i2c_regs_t *I2Cx)
Indicate the status of IC_STATUS SDA stuck at low is not recovered flag.
Definition: ll_i2c.h:3177
ll_i2c_set_data_setup_time
__STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
Set the SDA setup time when operating as a slave transmitter.
Definition: ll_i2c.h:1174
ll_i2c_enable_master_mode
__STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
Enable I2C master mode.
Definition: ll_i2c.h:434
ll_i2c_set_clock_low_period_hs
__STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
Get the SCL clock low-period count for high speed.
Definition: ll_i2c.h:934
ll_i2c_disable_bus_clear_feature
__STATIC_INLINE void ll_i2c_disable_bus_clear_feature(i2c_regs_t *I2Cx)
disable bus clear feature function.
Definition: ll_i2c.h:665
ll_i2c_get_rx_fifo_level
__STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO reception Level.
Definition: ll_i2c.h:1415
ll_i2c_get_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
Get I2C interrupt flags.
Definition: ll_i2c.h:2402
ll_i2c_is_active_flag_raw_restart_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_RESTART_DET flag.
Definition: ll_i2c.h:2547
ll_i2c_is_enabled_it_read_req
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
Check if RD_REQ interrupt is enabled or disabled.
Definition: ll_i2c.h:2129
ll_i2c_enable_it_gen_call
__STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
Enable GEN_CALL interrupt.
Definition: ll_i2c.h:1829
ll_i2c_disable_stop_det_if_addressed
__STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
Disable Slave issues STOP_DET interrupt only if addressed function.
Definition: ll_i2c.h:601
ll_i2c_is_enabled_master_restart
__STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
Check if Master Restart is enabled or disabled.
Definition: ll_i2c.h:565
ll_i2c_get_speed_mode
__STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
Get I2C Speed mode.
Definition: ll_i2c.h:1055
ll_i2c_enable_bus_clear_feature
__STATIC_INLINE void ll_i2c_enable_bus_clear_feature(i2c_regs_t *I2Cx)
enable bus clear feature function.
Definition: ll_i2c.h:649
ll_i2c_disable_it_master_on_hold
__STATIC_INLINE void ll_i2c_disable_it_master_on_hold(i2c_regs_t *I2Cx)
Disable MASTER_ON_HOLD interrupt.
Definition: ll_i2c.h:1753
ll_i2c_get_tx_fifo_level
__STATIC_INLINE uint16_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
Get FIFO Transmission Level.
Definition: ll_i2c.h:1400
ll_i2c_set_slave_address
__STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
Configure the slave address for transfer (master mode).
Definition: ll_i2c.h:3565
ll_i2c_set_high_speed_master_code
__STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
Set I2C High Speed Master Code Address.
Definition: ll_i2c.h:1073
ll_i2c_disable_it_rx_done
__STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
Disable RX_DONE interrupt.
Definition: ll_i2c.h:2024
ll_i2c_is_enabled
__STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
Check if the I2C peripheral is enabled or disabled.
Definition: ll_i2c.h:419
ll_i2c_enable_it_restart_det
__STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
Enable RESTART_DET interrupt.
Definition: ll_i2c.h:1783
ll_i2c_is_active_flag_raw_rx_full
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_FULL flag.
Definition: ll_i2c.h:2888
ll_i2c_is_active_flag_raw_rx_under
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_UNDER flag.
Definition: ll_i2c.h:2956
ll_i2c_set_clock_high_period_ss
__STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock high-period count for standard speed.
Definition: ll_i2c.h:773
ll_i2c_is_active_flag_raw_tx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_TX_OVER flag.
Definition: ll_i2c.h:2854
ll_i2c_is_active_flag_raw_stop_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
Indicate the status of RAW_STOP_DET flag.
Definition: ll_i2c.h:2650
ll_i2c_disable_it_rx_under
__STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
Disable RX_UNDER interrupt.
Definition: ll_i2c.h:2339
ll_i2c_set_clock_low_period_fs
__STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
Set the SCL clock low-period count for fast speed.
Definition: ll_i2c.h:869
ll_i2c_is_enable_it_rx_done
__STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
Check if RX_DONE interrupt is enabled or disabled.
Definition: ll_i2c.h:2039
ll_i2c_handle_transfer
__STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
Definition: ll_i2c.h:3602
ll_i2c_clear_flag_gen_call
__STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
Clear GEN_CALL flag.
Definition: ll_i2c.h:3005
ll_i2c_is_enabled_it_scl_stuck_at_low
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_scl_stuck_at_low(i2c_regs_t *I2Cx)
Check if the SCL_STUCK_AT_LOW Interrupt is enabled or disabled.
Definition: ll_i2c.h:1722
ll_i2c_is_active_flag_start_det
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
Indicate the status of START_DET flag.
Definition: ll_i2c.h:2599
ll_i2c_get_clock_high_period_fs
__STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
Get the SCL clock high-period count for fast speed.
Definition: ll_i2c.h:852
ll_i2c_enable_it_rx_abort
__STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
Enable TX_ABRT interrupt.
Definition: ll_i2c.h:2054
ll_i2c_enable_it_tx_empty
__STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
Enable TX_EMPTY interrupt.
Definition: ll_i2c.h:2144
ll_i2c_set_data_tx_hold_time
__STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
Set the required transmit SDA hold time in units of ic_clk period.
Definition: ll_i2c.h:1107
_ll_i2c_init::own_address
uint32_t own_address
Definition: ll_i2c.h:80
ll_i2c_disable
__STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
Disable I2C peripheral (ENABLE = 0).
Definition: ll_i2c.h:404
ll_i2c_set_spike_len_fs
__STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
Set the spike len in fast speed mode.
Definition: ll_i2c.h:967
ll_i2c_is_enabled_it_gen_call
__STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
Check if GEN_CALL interrupt is enabled or disabled.
Definition: ll_i2c.h:1859
ll_i2c_disable_it_tx_abort
__STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
Disable TX_ABRT interrupt.
Definition: ll_i2c.h:2069
ll_i2c_is_active_flag_raw_rx_over
__STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
Indicate the status of RAW_RX_OVER flag.
Definition: ll_i2c.h:2922
ll_i2c_get_raw_it_flag
__STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
Get I2C RAW interrupt flags.
Definition: ll_i2c.h:2444
ll_i2c_get_clock_low_period_ss
__STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
Get the SCL clock low-period count for standard speed.
Definition: ll_i2c.h:820
ll_i2c_transmit_data8
__STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
Write in Transmit Data Register .
Definition: ll_i2c.h:3642
ll_i2c_enable_it_rx_full
__STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
Enable RX_FULL interrupt.
Definition: ll_i2c.h:2234