ll_efuse.h
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1 /**
2 ****************************************************************************************
3 *
4 * @file ll_efuse.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of eFuse LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_EFUSE EFUSE
47 * @brief eFuse LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef ___LL_EFUSE_H__
53 #define ___LL_EFUSE_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr5x.h"
61
62 #if defined (EFUSE)
63
64 /**
65 * @defgroup EFUSE_LL_MACRO Defines
66 * @{
67 */
68
69 #define EFUSE_ZONE_SIZE_BYTE 32U /**< EFUSE size (byte). CAIRO EFUSE SIZE = 32 Bytes */
70 #define EFUSE_ZONE_SIZE_WORD (EFUSE_ZONE_SIZE_BYTE / 4U) /**< EFUSE size (word) */
71
72 /* Exported constants --------------------------------------------------------*/
73 /** @defgroup EFUSE_LL_Exported_Constants EFUSE Exported Constants
74 * @{
75 */
76
77 /** @defgroup EFUSE_LL_EC_OPERATION EFUSE Operation Defines
78 * @brief Operation defines which can be used with LL_EFUSE_WriteReg function
79 * @{
80 */
81 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK /**< Read the whole eFuse value, and check this value with 0 */
82 /** @} */
83
84 /** @defgroup EFUSE_LL_EC_GET_FLAG Get Flags Defines
85 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
86 * @{
87 */
88 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE /**< eFuse initial value check done */
89 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS /**< eFuse initial value check success */
90 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE /**< eFuse one word write done */
91 /** @} */
92
93 /** @defgroup EFUSE_LL_EC_GET_CTL_FLAG Get Power Controller Flags Defines
94 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
95 * @{
96 */
97 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE /**< eFuse power enable done */
98 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE /**< eFuse power disable done */
99 /** @} */
100
101 /** @} */
102
103 /* Exported macro ------------------------------------------------------------*/
104 /** @defgroup EFUSE_LL_Exported_Macros EFUSE Exported Macros
105 * @{
106 */
107
108 /** @defgroup EFUSE_LL_EM_WRITE_READ Common Write and read registers Macros
109 * @{
110 */
111
112 /**
113 * @brief Write a value in eFuse register
114 * @param __instance__ eFuse instance
115 * @param __REG__ Register to be written
116 * @param __VALUE__ Value to be written in the register
117 * @retval None
118 */
119 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
120
121 /**
122 * @brief Read a value in eFuse register
123 * @param __instance__ eFuse instance
124 * @param __REG__ Register to be read
125 * @retval Register value
126 */
127 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
128
129 /** @} */
130
131 /** @} */
132
133 /** @} */
134
135 /* Exported functions --------------------------------------------------------*/
136 /** @defgroup EFUSE_LL_DRIVER_FUNCTIONS Functions
137 * @{
138 */
139
140 /** @defgroup EFUSE_LL_EF_Configuration Configuration functions
141 * @{
142 */
143
144 /**
145 * @brief Set eFuse program time
146 *
147 * Register|BitsName
148 * --------|--------
149 * TPGM | TIME
150 *
151 * @param EFUSEx eFuse instance
152 * @param time This parameter can be one of the following values: 0 ~ 0xFFF
153 * @retval None
154 */
155 __STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
156 {
157 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
158 }
159
160 /**
161 * @brief Get eFuse program time
162 *
163 * Register|BitsName
164 * --------|--------
165 * TPGM | TIME
166 *
167 * @param EFUSEx eFuse instance
168 * @retval Returned value can be one of the following values: 0 ~ 0xFFF
169 */
170 __STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
171 {
172 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
173 }
174
175 /**
176 * @brief Set the interval number of clk cycles between two bit fuse
177 *
178 * Register|BitsName
179 * --------|--------
180 * TPGM | WRITE_INTERVAL
181 *
182 * @param EFUSEx eFuse instance
183 * @param interval This parameter can be one of the following values: 0 ~ 0xFF
184 * @retval None
185 */
186 __STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
187 {
188 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
189 }
190
191 /**
192 * @brief Get the interval number of clk cycles between two bit fuse
193 *
194 * Register|BitsName
195 * --------|--------
196 * TPGM | WRITE_INTERVAL
197 *
198 * @param EFUSEx eFuse instance
199 * @retval Returned value can be one of the following values: 0 ~ 0xFF
200 */
201 __STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
202 {
203 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
204 }
205
206 /**
207 * @brief Enable eFuse PGENB sigal
208 *
209 * Register|BitsName
210 * --------|--------
211 * PGENB | PGENB_SIG
212 *
213 * @param EFUSEx eFuse instance
214 * @retval None
215 */
216 __STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
217 {
218 SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
219 }
220
221 /**
222 * @brief Disable eFuse PGENB sigal
223 *
224 * Register|BitsName
225 * --------|--------
226 * PGENB | PGENB_SIG
227 *
228 * @param EFUSEx eFuse instance
229 * @retval None
230 */
231 __STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
232 {
233 CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
234 }
235
236 /**
237 * @brief Check if eFuse PGENB sigal is enabled
238 *
239 * Register|BitsName
240 * --------|--------
241 * PGENB | PGENB_SIG
242 *
243 * @param EFUSEx eFuse instance
244 * @retval State of bit (1 or 0).
245 */
246 __STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
247 {
248 return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
249 }
250
251 /**
252 * @brief Set eFuse operation mode
253 *
254 * Register|BitsName
255 * --------|--------
256 * OPERATION | INIT_CHECK
257 *
258 * @param EFUSEx eFuse instance
259 * @param mode This parameter can be one of the following values:
260 * @arg @ref LL_EFUSE_INIT_CHECK
261 * @retval None
262 */
263 __STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
264 {
265 WRITE_REG(EFUSEx->OPERATION, mode);
266 }
267
268 /**
269 * @brief Check active flag
270 *
271 * Register|BitsName
272 * --------|--------
273 * STAT | INIT_DONE
274 * STAT | INIT_SUCCESS
275 * STAT | WRITE_DONE
276 *
277 * @param EFUSEx eFuse instance
278 * @param flag This parameter can be one of the following values:
279 * @arg @ref LL_EFUSE_INIT_CHECK_DONE
280 * @arg @ref LL_EFUSE_INIT_CHECK_SUCCESS
281 * @arg @ref LL_EFUSE_WRITE_DONE
282 * @retval State of bit (1 or 0).
283 */
284 __STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
285 {
286 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
287 }
288
289 /**
290 * @brief eFuse v1.1 power on.
291 *
292 * Register|BitsName
293 * --------|--------
294 * TPGM | CRC_CHECK_LEN
295 *
296 * @retval None
297 */
298 __STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
299 {
300 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
301 }
302
303 /**
304 * @brief eFuse v1.1 power off.
305 *
306 * Register|BitsName
307 * --------|--------
308 * TPGM | CRC_CHECK_LEN
309 *
310 * @retval None
311 */
312 __STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
313 {
314 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDD_EN);
315 }
316
317
318 /**
319 * @brief eFuse vddq enable. Vddq must be enble when write efuse, and disable when write done.
320 *
321 * Register|BitsName
322 * --------|--------
323 * RF_REG_2| EFUSE_VDDQ_EN
324 *
325 * @retval None
326 */
327 __STATIC_INLINE void ll_efuse_enable_vddq(void)
328 {
329 SET_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN|AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
330 }
331
332 /**
333 * @brief eFuse vddq disable. Vddq must be enble when write efuse, and disable when write done.
334 *
335 * Register|BitsName
336 * --------|--------
337 * RF_REG_2| EFUSE_VDDQ_EN
338 *
339 * @retval None
340 */
341 __STATIC_INLINE void ll_efuse_disable_vddq(void)
342 {
343 CLEAR_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN|AON_PMU_RF_REG_2_EFUSE_VDDQ_EN_DEL);
344 }
345
346 /**
347 * @brief Get eFuse vddq state. Vddq must be enble when write efuse, and disable when write done.
348 *
349 * Register|BitsName
350 * --------|--------
351 * RF_REG_2| EFUSE_VDDQ_EN
352 *
353 * @retval None
354 */
355 __STATIC_INLINE uint32_t ll_efuse_is_enable_vddq(void)
356 {
357 return (READ_BITS(AON_PMU->RF_REG_2, AON_PMU_RF_REG_2_EFUSE_VDDQ_EN) == AON_PMU_RF_REG_2_EFUSE_VDDQ_EN);
358 }
359
360 /**
361 * @brief Set Efulse power controller timing pararmeter.
362 *
363 * Register |BitsName
364 * ----------|--------
365 * PWR_DELTA| PWR_DELTA_0
366 * PWR_DELTA| PWR_DELTA_1
367 * PWR_DELTA| PWR_DELTA_2
368 *
369 * @retval None
370 */
371 __STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
372 {
373 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_0, vddq_0 + (vddq_1 << 16));
374 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA_1, vddq_2);
375 }
376
377 /**
378 * @brief EFUSE HW Power control enable.
379 *
380 * Register |BitsName
381 * -----------|--------
382 * PWR_CTRL0 | CTRL_ENABLE
383 *
384 * @retval None
385 */
386 __STATIC_INLINE void ll_efuse_enable_controller_power_en(efuse_regs_t *EFUSEx)
387 {
388 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_EN);
389 }
390
391 /**
392 * @brief EFUSE HW Power control enable.
393 *
394 * Register |BitsName
395 * -----------|--------
396 * PWR_CTRL0 | CTRL_ENABLE
397 *
398 * @retval None
399 */
400 __STATIC_INLINE void ll_efuse_disable_controller_power_en(efuse_regs_t *EFUSEx)
401 {
402 CLEAR_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_EN);
403 }
404
405 /**
406 * @brief EFUSE HW Power control begin.
407 *
408 * Register |BitsName
409 * -----------|--------
410 * PWR_CTRL0 | SEQR_BEGIN
411 *
412 * @retval None
413 */
414 __STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
415 {
416 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_BGN);
417 }
418
419 /**
420 * @brief EFUSE HW Power control stop.
421 *
422 * Register |BitsName
423 * -----------|--------
424 * PWR_CTRL0 | CTRL_ENABLE
425 * PWR_CTRL0 | SEQR_STOP
426 *
427 * @retval None
428 */
429 __STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
430 {
431 SET_BITS(MCU_SUB->EFUSE_PWR_CTRL_0, MCU_SUB_EFUSE_PWR_CTL0_STP);
432 }
433
434 /**
435 * @brief EFUSE HW Power control disable.
436 *
437 * Register |BitsName
438 * --------- -|--------
439 * PWR_CTRL0 | CTRL_ENABLE
440 * PWR_CTRL0 | SEQR_BEGIN
441 * PWR_CTRL0 | SEQR_STOP
442 *
443 * @retval None
444 */
445 __STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
446 {
447 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL_0, 0);
448 }
449
450 /**
451 * @brief Check power controller active flag
452 *
453 * Register|BitsName
454 * --------|--------
455 * PWR_CTRL1 | EN_DONE
456 * PWR_CTRL1 | DIS_DONE
457 *
458 * @param EFUSEx eFuse instance
459 * @param flag This parameter can be one of the following values:
460 * @arg @ref LL_EFUSE_PWR_CTL_EN_DONE
461 * @arg @ref LL_EFUSE_PWR_CTL_DIS_DONE
462 * @retval State of bit (1 or 0).
463 */
464 __STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
465 {
466 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL_1, flag) == (flag));
467 }
468
469
470
471 /** @} */
472
473 /** @} */
474
475 #endif /* EFUSE */
476
477 #ifdef __cplusplus
478 }
479 #endif
480
481 #endif /* ___LL_EFUSE_H__ */
482
483 /** @} */
484
485 /** @} */
486
487 /** @} */
ll_efuse_is_enable_vddq
__STATIC_INLINE uint32_t ll_efuse_is_enable_vddq(void)
Get eFuse vddq state. Vddq must be enble when write efuse, and disable when write done.
Definition: ll_efuse.h:355
ll_efuse_disable_controller_power
__STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
EFUSE HW Power control disable.
Definition: ll_efuse.h:445
ll_efuse_enable_vddq
__STATIC_INLINE void ll_efuse_enable_vddq(void)
eFuse vddq enable. Vddq must be enble when write efuse, and disable when write done.
Definition: ll_efuse.h:327
ll_efuse_enable_controller_power_begin
__STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
EFUSE HW Power control begin.
Definition: ll_efuse.h:414
ll_efuse_disable_controller_power_en
__STATIC_INLINE void ll_efuse_disable_controller_power_en(efuse_regs_t *EFUSEx)
EFUSE HW Power control enable.
Definition: ll_efuse.h:400
ll_efuse_disable_pgenb
__STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
Disable eFuse PGENB sigal.
Definition: ll_efuse.h:231
ll_efuse_enable_power
__STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power on.
Definition: ll_efuse.h:298
gr5x.h
CMSIS Cortex-M# Core Peripheral Access Layer Header File for Device GR5405.
ll_efuse_enable_controller_power_stop
__STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
EFUSE HW Power control stop.
Definition: ll_efuse.h:429
ll_efuse_is_enabled_pgenb
__STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
Check if eFuse PGENB sigal is enabled.
Definition: ll_efuse.h:246
ll_efuse_get_interval
__STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
Get the interval number of clk cycles between two bit fuse.
Definition: ll_efuse.h:201
ll_efuse_enable_controller_power_en
__STATIC_INLINE void ll_efuse_enable_controller_power_en(efuse_regs_t *EFUSEx)
EFUSE HW Power control enable.
Definition: ll_efuse.h:386
ll_efuse_set_tpro
__STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
Set eFuse program time.
Definition: ll_efuse.h:155
ll_efuse_disable_vddq
__STATIC_INLINE void ll_efuse_disable_vddq(void)
eFuse vddq disable. Vddq must be enble when write efuse, and disable when write done.
Definition: ll_efuse.h:341
ll_efuse_is_active_flag
__STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check active flag.
Definition: ll_efuse.h:284
ll_efuse_set_operation
__STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
Set eFuse operation mode.
Definition: ll_efuse.h:263
ll_efuse_is_controller_power_flag
__STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
Check power controller active flag.
Definition: ll_efuse.h:464
ll_efuse_disable_power
__STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
eFuse v1.1 power off.
Definition: ll_efuse.h:312
ll_efuse_set_controller_power_timing
__STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0, uint16_t vddq_1, uint16_t vddq_2)
Set Efulse power controller timing pararmeter.
Definition: ll_efuse.h:371
ll_efuse_set_interval
__STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
Set the interval number of clk cycles between two bit fuse.
Definition: ll_efuse.h:186
ll_efuse_enable_pgenb
__STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
Enable eFuse PGENB sigal.
Definition: ll_efuse.h:216
ll_efuse_get_tpro
__STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
Get eFuse program time.
Definition: ll_efuse.h:170