工作职责：
• Analog power stage sub-system and circuits block design, integration and simulation.
• Apply high-voltage and power analog design and layout best practice and guideline towards first silicon success.
• Work closely with system and analog lead to implement sub-system or blocks specifications.
• Work with digital team to ensure block mixed-signal functions are implemented and verified.
• Implement high-voltage power stage and power stage driver circuits in advanced BCD (Bipolar, CMOS, DMOS) processes.
• Provide specification, design review and test requirements documentation to guide support team (system, application, ATE test engineers etc.) to meet design quality, yield and schedule targets.
• Build behavioral modeling of analog and digital circuits with Matlab, Verilog A and System Verilog.
• Perform mixed signal simulations for verification of chip level and system level performance.
• Define layout requirements for layout engineers or complete the circuit layout autonomously.
• Characterize, and de-bug designs in the lab and test platform for mass production as necessary.
• Must be a team player and self-starter.
• 模拟功率级子系统和电路块设计、集成和仿真。
• 应用高压和功率模拟设计和布局最佳实践和指南，以实现芯片首发成功。
• 与系统和模拟主管密切合作，实施子系统或模块规范。
• 与数字团队合作，确保块混合信号功能得到实施和验证。
• 采用先进的BCD（双极、CMOS、DMOS）工艺实现高压功率级和功率级驱动器电路。
• 提供规格、设计审查和测试要求文档，以指导支持团队（系统、应用、ATE 测试工程师等）满足设计质量、良率和进度目标。
• 使用Matlab、Verilog A 和System Verilog 构建模拟和数字电路的行为建模。
• 执行混合信号仿真以验证芯片级和系统级性能。
• 为布局工程师定义布局要求或自主完成电路布局。
• 根据需要在实验室和测试平台中对设计进行表征和调试，以进行批量生产。
• 必须具有团队合作精神并积极主动。
任职资格：
• MS degree in Electrical Engineering with 8+ or PhD degree with 5+ years of IC design experience.
• Silicon proven experience in CMOS or BCD analog mixed-signal design and layout.
• Silicon proven experience designing power related circuits such as switch-mode power supplies, battery chargers, LDOs, class-D amplifier and motor drivers.
• Strong knowledge of BCD silicon process technologies involving high voltage and high power design.
• Strong knowledge of transistor-level analog circuit simulation tools and with extensive experience with Cadence Virtuoso.
• Ability create and execute sub-system and block level AMS based verification test plans.
• Ability to characterize and troubleshoot IC designs in the lab and ATE test floor.
• Outstanding communication and leadership skills.
• Class-D amplifier, PMIC and automotive product design background is a plus.
• 电气工程硕士学位8年以上或博士学位5年以上IC设计经验。
• 在CMOS 或BCD 模拟混合信号设计和布局方面拥有扎实的经验。
• 具有扎实的电源相关电路设计经验，例如开关模式电源、电池充电器、LDO、D 类放大器和电机驱动器。
• 对涉及高压和高功率设计的BCD 硅工艺技术有深入的了解。
• 对晶体管级模拟电路仿真工具有深入的了解，并具有使用Cadence Virtuoso 的丰富经验。
• 能够创建和执行基于子系统和块级AMS 的验证测试计划。
• 能够在实验室和ATE 测试台中对IC 设计进行表征和故障排除。
• 出色的沟通和领导能力。
• D 类放大器、PMIC 和汽车产品设计背景优先。
