Responsibilities

• Be the main contact for all physical design aspects of the SOC design.

• Be responsible for managing and tracking the physical execution of the project towards a global schedule.

• Be responsible for managing the team’s part of global responsibilities on floor planning, power grid planning and clock design.

• Be responsible for all phases of physical design from RTL to the delivery of the final GDS netlist.

• Be responsible for integration flow development for mixed-signal SOCs in state-of-the-art CMOS technology as well as optimization for power, performance, and area to meet product requirements.

• Be responsible for IP tasks including block and pin placements, STA constraints, bus planning, DRC, and physical verification flows, such as LVS, EM, IR, and sign-off flows.

Required Skills and Qualifications

• M.S. or B.S. with 12+ years of relevant industry experience

• Expert in all aspects of Physical Design, Integration, and Physical Verification

• Flow development experience for digital or mixed-signal IPs and SOCs

• Tool experience with Synopsys DC, ICC2, Prime Time or Cadence’s Genus, Innovus, Tempus

• Scripting experience in TCL, Python or Perl

• Familiar with intricate SOC design knowledge for I/O planning, integration of in-house and external IP, custom, mixed-signal and digital block integration and management of multiple power and clock domains, amongst others.

Preferred Skills and Qualifications

• Understanding of analog design flows is a plus

Working at our company

• Work with highly-talented, motivated, and hard-working team members globally

• Receive competitive salary, benefits, and bonus plan

• Relocation package is available

Location: Austin, Texas, USA

CV Receiver: a.acker@goodix.com