Stock Code: 603160

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Design Verification Engineers (Senior to Principal levels)

Join Goodix’s design verification team and work closely with digital/analog designers, participating in all aspects of verification for complete mixed-signal IC developments. Job involves verification of complex systems both at IP and SOC level as well as development of verification methodology for these complex mixed-signal systems.


Responsibilities

• Functional verification planning and test-plan development

• Testbench development using UVM/System Verilog for mixed-signal ASICs

• Triage and debug of design failures, coverage development and closure

• Generating models for functional verification, both digital and mixed signal (AMS)

• Stimulus generation including directed and constraint random test generation

• Regression debug support and infrastructure development


Required Skills and Qualifications

• BS or MS in Electrical Engineering or Computer Engineering with 5+ years (7+ years with BS) of verification experience (Mixed signal products is a plus)

• Strong background with SystemVerilog and methodologies like UVM, OVM, AVM or Vera

• Experience working with industry standard design verification EDA tools like VCS, Xcelium etc.


Preferred Skills and Qualifications

• Experience working with object oriented programming environment

• Scripting languages like Perl or Python 

• Ability to work closely with digital/analog designers to support both pre and post silicon verification efforts

• Knowledge of System Verilog Assertions

• Experience with signal processing

Location: Austin, Texas, USA
CV Receiver: a.acker@goodix.com


Annual Trip

Every year Goodix sponsors a domestic or international trip, which provides employees with an excellent opportunity to explore the world together, build bonds and inspire each other.

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