Join Goodix’s design verification team and participate in all aspects of UVM digital design verification for complete SoC design developments. Job involves verification of complex systems both at IP and SOC level as well as development of verification methodology for these complex systems.
• Working with designers to generate models for functional verification
• Functional verification planning and test-plan development
• Testbench development using UVM/System Verilog
• Triage and debug of design failures, coverage development and closure
• Stimulus generation including directed and constraint random test generation
• Regression debug support and infrastructure development
Required Skills and Qualifications
• BS or MS in Electrical Engineering or Computer Engineering with 3-20 years of digital design verification experience
• Digital verification with real number models in system verilog
• Background with SystemVerilog and methodologies like UVM, OVM, AVM or Vera
• Experience working with industry standard design verification EDA tools like VCS, Xcelium etc.
• Experience with Cadence Virtuoso/Spectre
Preferred Skills and Qualifications
• Experience working with object oriented programming environment
• Scripting languages like Perl or Python
• Ability to work closely with digital/analog designers to support both pre and post silicon verification efforts
• Knowledge of System Verilog Assertions
Location: Austin, Texas, USA
CV Receiver: email@example.com
Every year Goodix sponsors a domestic or international trip, which provides employees with an excellent opportunity to explore the world together, build bonds and inspire each other.
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